Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2013-0079952, filed on Jul. 8, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. 
     BACKGROUND 
     1. Field of the Invention 
     Embodiments of the present disclosure relate to semiconductor memory devices and semiconductor systems including the same. 
     2. Description of the Related Art 
     In general, semiconductor memory devices may include a plurality of memory cells. As the semiconductor memory devices become more highly integrated, the number of the memory cells in each of the semiconductor memory devices has been rapidly increased. Each of the semiconductor memory devices including the memory cells may execute a read operation and/or a write operation in response to control signals provided from a controller to store (or write) input data in the memory cells and/or to output (or read) the data stored in the memory cells. 
     Meanwhile, as the operation speed of semiconductor systems including the semiconductor memory devices and the controllers get faster, it has become more and more important to control or adjust the timing between a command signal, an address signal and data that the controller applies to semiconductor memory devices. That is, the timing between various output signals of the controller has to be accurately controlled for reliable and accurate operations of the semiconductor systems. In particular, as the transmission speed (e.g., input and output speeds) of the data become faster, it may be necessary to accurately find out delay times of the data on channels between the controller and the semiconductor memory device. Finding out information (e.g., the delay times) on the channels through which the data are transmitted is referred to as “channel training”. 
     Referring to  FIG. 1 , a first output data DOUT&lt;1&gt; has stable levels at rising edges “T1” and “T3” and falling edges “T2” and “T4” of a clock signal CLK without any level transitions. Thus, no data errors occur in the first output data DOUT&lt;1&gt;. 
     In contrast, a level of a second output data DOUT&lt;2&gt; changes at the rising edges “T1” and “T3” and the falling edges “T2” and “T4” of the clock signal CLK. Thus, data errors may occur in the second output data DOUT&lt;2&gt;. 
     Similarly, a level of a third output data DOUT&lt;3&gt; changes at the rising edges “T1” and “T3” and the falling edges “T2” and “T4” of the clock signal CLK. Thus, data errors may also occur in the third output data DOUT&lt;3&gt;. 
     According to  FIG. 1 , if the first output data DOUT&lt;1&gt; has a normal delay time, the second output data DOUT&lt;2&gt; may have an abnormal delay time which is greater than the normal delay time and the third output data DOUT&lt;3&gt; may have an abnormal delay time which is less than the normal delay time. 
     If a delay time of data changes due to process/voltage/temperature (PVT) conditions, levels of the data may change at rising edges and falling edges of a clock signal. In such a case, data errors may occur to degrade the reliability of the data. 
     SUMMARY 
     According to an embodiment, a semiconductor system includes a controller and a semiconductor memory device. The controller generates a first command signal. Further, the controller receives a foreground data to generate a foreground control signal for controlling a drivability of the foreground data and to generate a second command signal. The semiconductor memory device receives the first command signal to output a pattern data as the foreground data through a foreground input/output (I/O) line, stores the foreground control signal therein in response to the second command signal, and controls the drivability of the foreground data according to the foreground control signal. 
     According to an embodiment, a semiconductor memory device includes a drive signal generator and an output buffer. The drive signal generator outputs a foreground control signal for controlling a drivability of a foreground data as a foreground drive signal in response to a first command signal, stores the foreground control signal therein in response to a second command signal, and loads a pattern data having a predetermined level combination on a foreground I/O line. The output buffer generates the foreground data in response to a signal loaded on the foreground I/O line and outputs the foreground data through a first pad. A drivability of the foreground data is controlled according to the foreground drive signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention will become more apparent in view of the attached drawings and accompanying detailed description, in which: 
         FIG. 1  is a timing diagram illustrating an abnormal operation of a general semiconductor system according to variation of a data delay time. 
         FIG. 2  is a block diagram illustrating a semiconductor system according to an embodiment of the present invention; 
         FIG. 3  is a block diagram illustrating a controller included in the semiconductor system of  FIG. 2 ; 
         FIG. 4  is a block diagram illustrating a semiconductor memory device included in the semiconductor system of  FIG. 2 ; 
         FIG. 5  is a block diagram illustrating an output buffer included in the semiconductor memory device of  FIG. 4 ; 
         FIG. 6  is a circuit diagram illustrating a first pre-decoder included in the output buffer of  FIG. 5 ; and 
         FIG. 7  is a circuit diagram illustrating a second pre-decoder included in the output buffer of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. 
     Referring to  FIG. 2 , a semiconductor system according to an embodiment of the present invention may include a controller  1  and a semiconductor memory device  2 . 
     The controller  1  may generate a first command signal MRR, first to fourth foreground control signals DC 1 &lt;1:4&gt;, first to fourth background control signals DC 2 &lt;1:4&gt; and a second command signal MRW. The first to fourth foreground control signals DC 1 &lt;1:4&gt;, first to fourth background control signals DC 2 &lt;1:4&gt; and a second command signal MRW may be generated by first to fourth foreground data DQ 1 &lt;1:4&gt; provided from the semiconductor memory device  2 . 
     The semiconductor memory device  2  may be configured to output the first to fourth foreground data DQ 1 &lt;1:4&gt; and the first to fourth background data DQ 2 &lt;1:4&gt; in response to the first command signal MRR. Further, the semiconductor memory device  2  may be configured to store the first to fourth foreground control signals DC 1 &lt;1:4&gt; and the first to fourth background control signals DC 2 &lt;1:4&gt; therein in response to the second command signal MRW. Moreover, the semiconductor memory device  2  may be configured to control drivabilities of the first to fourth foreground data DQ 1 &lt;1:4&gt; and the first to fourth background data DQ 2 &lt;1:4&gt; according to a level combination of the first to fourth foreground control signals DC 1 &lt;1:4&gt; and the first to fourth background control signals DC 2 &lt;1:4&gt;. The first to fourth foreground control signals DC 1 &lt;1:4&gt; may control the drivability of the first to fourth foreground data DQ 1 &lt;1:4&gt; and the first to fourth background control signals DC 2 &lt;1:4&gt; may control the drivability of the first to fourth background data DQ 2 &lt;1:4&gt;. 
     As shown in  FIG. 3 , the controller  1  may include a command generator  11 , a selection signal generator  12 , a comparison signal generator  13  and a control signal generator  14 . 
     The command generator  11  may be configured to generate a pulse of the first command signal MRR in response to a test enable signal TMEN enabled when a test mode starts. Further the command generator  11  may be also configured to generate a pulse of the first command signal MRR even when a level combination of the first to fourth foreground data DQ 1 &lt;1:4&gt; or the first to fourth background data DQ 2 &lt;1:4&gt; is different from a predetermined level combination. Further, the command generator  11  may be configured to generate a pulse of the second command signal MRW when the level combination of the first to fourth foreground data DQ 1 &lt;1:4&gt; or the first to fourth background data DQ 2 &lt;1:4&gt; is identical to the predetermined level combination. 
     The selection signal generator  12  may be configured to generate a selection signal SEL having a first level and a second level which is opposite to the first level. 
     The selection signal may become the first level (e.g., a logic “low” level) if a pulse of a read latency signal RDOUT is inputted after a predetermined time elapses from a time that the pulse of the first command signal MRR is generated. Further, the selection signal SEL may become the second level (e.g., a logic “high” level) if the level combination of the first to fourth foreground data DQ 1 &lt;1:4&gt; or the first to fourth background data DQ 2 &lt;1:4&gt; is identical to the predetermined level combination after the pulse of the read latency signal RDOUT is inputted. The read latency signal RDOUT may correspond to a signal which is enabled after the semiconductor memory device  2  outputs data in response to the first command signal MRR. 
     The comparison signal generator  13  may include a multiplexer  131 , a comparison code generator  132  and a comparator  133 . The multiplexer  131  may be configured to output the first to fourth foreground data DQ 1 &lt;1:4&gt; as first to fourth selection data SD&lt;1:4&gt; when the selection signal SEL has the first level (e.g., a logic “low” level) and output the first to fourth background data DQ 2 &lt;1:4&gt; as the first to fourth selection data SD&lt;1:4&gt; when the selection signal SEL has the second level (e.g., a logic “high” level). The comparison code generator  132  may be configured to generate first and second comparison codes S&lt;1:2&gt; whose level combination is determined according to a level combination of the first to fourth selection data SD&lt;1:4&gt;. The comparator  133  may be configured to generate a pulse of a comparison signal COMP when a level combination of the first and second comparison codes S&lt;1:2&gt; is different from a level combination of first and second test codes T&lt;1:2&gt; having a predetermined level combination. For example, the comparison signal generator  13  may generate a pulse of the comparison signal COMP when the selection signal SEL has the first level (e.g., a logic “low” level) and the first to fourth foreground data DQ 1 &lt;1:4&gt; have a level combination which is different from the predetermined level combination. Further, the comparison signal generator  13  may also generate a pulse of the comparison signal COMP even when the selection signal SEL has the second level (e.g., a logic “high” level) and the first to fourth background data DQ 2 &lt;1:4&gt; has a level combination which is different from the predetermined level combination. A level combination of the first and second comparison codes S&lt;1:2&gt; may vary according to the number of bits having a logic “high” level among the bits of the first to fourth selection data SD&lt;1:4&gt;. In addition, the predetermined level combination of the first and second test codes T&lt;1:2&gt; may be set such that the first test code T&lt;1&gt; has a logic “high” level and the second test code T&lt;2&gt; has a logic “low” level. However, the predetermined level combination of the first and second test codes T&lt;1:2&gt; may be set to be different according to the embodiments. Further, the comparison code generator  132  and the comparator  133  may be received the first command signal MRR, as a control signal. 
     The level combination of the first and second comparison codes S&lt;1:2&gt; according to the number of the bits having a logic “high” level among the bits of the first to fourth selection data SD&lt;1:4&gt; may be summarized as described in the following Table 1. 
     
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 The number of the bits having a logic 
                   
                   
               
               
                 “high” level among the bits of the 
               
               
                 first to fourth selection data SD&lt;1:4&gt; 
                 S&lt;2&gt; 
                 S&lt;1&gt; 
               
               
                   
               
             
             
               
                 0 
                 Low (L) 
                 Low (L) 
               
               
                 1 
                 Low (L) 
                 High (H) 
               
               
                 2 
                 High (H) 
                 Low (L) 
               
               
                 3 
                 High (H) 
                 High (H) 
               
               
                   
               
             
          
         
       
     
     The control signal generator  14  may include a counter  141  and a decoder  142 . The counter  141  may be configured to output first and second count signals CNT&lt;1:2&gt;. The first and second count signals CNT&lt;1:2&gt; may be counted when a pulse of the comparison signal COMP is inputted. When the selection signal SEL has the first level (e.g., a logic “low” level), the decoder  142  may decode the first and second count signals CNT&lt;1:2&gt; to generate first to fourth foreground control signals DC 1 &lt;1:4&gt;. Further, when the selection signal SEL has the second level (e.g., a logic “high” level), the decoder  142  may decode the first and second count signals CNT&lt;1:2&gt; to generate first to fourth background control signals DC 2 &lt;1:4&gt;. That is, the control signal generator  14  may be configured to generate the first to fourth foreground control signals DC 1 &lt;1:4&gt; whose level combination changes when the selection signal SEL has the first level (e.g., a logic “low” level) and a pulse of the comparison signal COMP is inputted. Further, the control signal generator  14  may be configured to generate the first to fourth background control signals DC 2 &lt;1:4&gt; whose level combination changes when the selection signal SEL has the second level (e.g., a logic “high” level) and a pulse of the comparison signal COMP is inputted. 
     For example, a level combination of the first to fourth foreground control signals DC 1 &lt;1:4&gt; according to a level combination of the first and second count signals CNT&lt;1:2&gt; may be summarized as described in the following Table 2. 
     
       
         
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 CNT&lt;2&gt; 
                 CNT&lt;1&gt; 
                 DC1&lt;4&gt; 
                 DC1&lt;3&gt; 
                 DC1&lt;2&gt; 
                 DC1&lt;1&gt; 
               
               
                   
               
             
             
               
                 L 
                 L 
                 L 
                 L 
                 L 
                 H 
               
               
                 L 
                 H 
                 L 
                 L 
                 H 
                 H 
               
               
                 H 
                 L 
                 L 
                 H 
                 H 
                 H 
               
               
                 H 
                 H 
                 H 
                 H 
                 H 
                 H 
               
               
                   
               
             
          
         
       
     
     For example, a level combination of the first to fourth background control signals DC 2 &lt;1:4&gt; according to a level combination of the first and second count signals CNT&lt;1:2&gt; may be summarized as described in the following Table 3. 
     
       
         
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 CNT&lt;2&gt; 
                 CNT&lt;1&gt; 
                 DC2&lt;4&gt; 
                 DC2&lt;3&gt; 
                 DC2&lt;2&gt; 
                 DC2&lt;1&gt; 
               
               
                   
               
             
             
               
                 L 
                 L 
                 L 
                 L 
                 L 
                 H 
               
               
                 L 
                 H 
                 L 
                 L 
                 H 
                 H 
               
               
                 H 
                 L 
                 L 
                 H 
                 H 
                 H 
               
               
                 H 
                 H 
                 H 
                 H 
                 H 
                 H 
               
               
                   
               
             
          
         
       
     
     Referring to  FIG. 4 , the semiconductor memory device  2  may include a drive signal generator  21  and an output buffer  22 . 
     The drive signal generator  21  may include an input buffer  211 , a signal storage unit  212  and a data input/output (I/O) controller  213 . The input buffer  211  may be configured to buffer the first command signal MRR and the second command signal MRW to generate a first internal command signal IRD and a second internal command signal IWT, respectively. The signal storage unit  212  may be configured to output the first to fourth foreground control signals DC 1 &lt;1:4&gt; as first to fourth foreground drive signals DRV 1 &lt;1:4&gt; and may output the first to fourth background control signals DC 2 &lt;1:4&gt; as first to fourth background drive signals DRV 2 &lt;1:4&gt; when the first internal command signal IRD is inputted. Further, the signal storage unit  212  may be configured to store the first to fourth foreground control signals DC 1 &lt;1:4&gt; and the first to fourth background control signals DC 2 &lt;1:4&gt; therein when the second internal command signal IWT is inputted. Moreover, the signal storage unit  212  may be configured to output first to fourth pattern data PD&lt;1:4&gt; having a predetermined level combination in response to the first internal command signal IRD. The data I/O controller  213  may load the first to fourth pattern data PD&lt;1:4&gt; on first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; and on first to fourth background I/O lines GIO 2 &lt;1:4&gt;, respectively, when the test enable signal TMEN is enabled. Further, the data I/O controller  213  may load first to fourth foreground internal data ID 1 &lt;1:4&gt; stored in memory cells on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; and may load first to fourth background internal data ID 2 &lt;1:4&gt; stored in memory cells on the first to fourth background I/O lines GIO 2 &lt;1:4&gt; when the test enable signal TMEN is disabled. For example, the predetermined level combination of the first to fourth pattern data PD&lt;1:4&gt; may be set such that the first and third pattern data PD&lt;1&gt; and PD&lt;3&gt; have a logic “low” level and the second and fourth pattern data PD&lt;2&gt; and PD&lt;4&gt; have a logic “high” level. However, the predetermined level combination of the first to fourth pattern data PD&lt;1:4&gt; may be set to be different according to the embodiment. 
     The output buffer  22  may be configured to control the drivability of the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; according to a level combination of the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; to generate the first to fourth foreground data DQ 1 &lt;1:4&gt;. Further, the output buffer  22  may be control the drivability of the first to fourth background I/O lines GIO 2 &lt;1:4&gt; according to a level combination of the first to fourth background drive signals DRV 2 &lt;1:4&gt; to generate the first to fourth background data DQ 2 &lt;1:4&gt;. 
     Referring to  FIG. 5 , the output buffer  22  may include a first output buffer  23  and a second output buffer  25 . 
     The first output buffer  23  may include a first pre-driver  231  and a first driver  232 . The first pre-driver  231  may be configured to control the drivability of the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; according to a level combination of the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; to generate first to fourth pre-foreground data PRE_DQ 1 &lt;1:4&gt;. The first driver  232  may be configured to buffer the first to fourth pre-foreground data PRE_DQ 1 &lt;1:4&gt; to output the first to fourth foreground data DQ 1 &lt;1:4&gt; through a first pad  24 . 
     The second output buffer  25  may include a second pre-driver  251  and a second driver  252 . The second pre-driver  251  may be configured to control the drivability of the first to fourth background I/O lines GIO 2 &lt;1:4&gt; according to a level combination of the first to fourth background drive signals DRV 2 &lt;1:4&gt; to generate first to fourth pre-background data PRE_DQ 2 &lt;1:4&gt;. The second driver  252  may be configured to buffer the first to fourth pre-background data PRE_DQ 2 &lt;1:4&gt; to output the first to fourth background data DQ 2 &lt;1:4&gt; through a second pad  26 . 
     Referring to  FIG. 6 , the first pre-driver  231  may be configured to include a first buffering unit  2310 , a first inverter IV 20 , a first driving unit  2311 , a second driving unit  2312 , a third driving unit  2313  and a fourth driving unit  2314 . The first buffering unit  2310  may be configured to buffer signals loaded on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; in response to a read enable signal ENDQ enabled to have a logic “high” level when the first command signal MRR is inputted, thereby outputting the buffered signals through a first node ND 21 . For example, the first buffering unit  2310  may include a NAND gate ND 20 . 
     The first inverter IV 20  may inversely buffer a signal on the first node ND 21  to output the inversely buffered signal through a second node ND 22 . The first driving unit  2311  may receive the first foreground drive signal DRV 1 &lt;1&gt; and a first complementary foreground drive signal DRVB 1 &lt;1&gt; to drive the second node ND 22 . The second driving unit  2312  may receive the second foreground drive signal DRV 1 &lt;2&gt; and a second complementary foreground drive signal DRVB 1 &lt;2&gt; to drive the second node ND 22 . The third driving unit  2313  may receive the third foreground drive signal DRV 1 &lt;3&gt; and a third complementary foreground drive signal DRVB 1 &lt;3&gt; to drive the second node ND 22 . The fourth driving unit  2314  may receive the fourth foreground drive signal DRV 1 &lt;4&gt; and a fourth complementary foreground drive signal DRVB 1 &lt;4&gt; to drive the second node ND 22 . That is, the first pre-driver  231  may generate the first to fourth pre-foreground data PRE_DQ 1 &lt;1:4&gt; whose drivabilities are controlled according to a level combination of the first to fourth foreground drive signals DRV 1 &lt;1:4&gt;. The first to fourth complementary foreground drive signals DRVB 1 &lt;1:4&gt; may correspond to inverted signals of the first to fourth foreground drive signals DRV 1 &lt;1:4&gt;, respectively. 
     Referring to  FIG. 7 , the second pre-driver  251  may be configured to include a second buffering unit  2510 , a second inverter IV 21 , a fifth driving unit  2511 , a sixth driving unit  2512 , a seventh driving unit  2513  and a eighth driving unit  2514 . The second buffering unit  2510  may be configured to buffer signals loaded on the first to fourth background I/O lines GIO 2 &lt;1:4&gt; in response to the read enable signal ENDQ enabled to have a logic “high” level when the first command signal MRR is inputted, thereby outputting the buffered signals through a third node ND 23 . For example, the second buffering unit  2510  may include NAND gate ND 21 . The second inverter IV 21  may inversely buffer a signal on the third node ND 23  to output the inversely buffered signal through a fourth node ND 24 . The fifth driving unit  2511  may receive the first background drive signal DRV 2 &lt;1&gt; and a first complementary background drive signal DRVB 2 &lt;1&gt; to drive the fourth node ND 24 . The sixth driving unit  2512  may receive the second background drive signal DRV 2 &lt;2&gt; and a second complementary background drive signal DRVB 2 &lt;2&gt; to drive the second node ND 22 . The seventh driving unit  2513  may receive the third background drive signal DRV 2 &lt;3&gt; and a third complementary background drive signal DRVB 2 &lt;3&gt; to drive the second node ND 22 . The eighth driving unit  2514  may receive the fourth background drive signal DRV 2 &lt;4&gt; and a fourth complementary background drive signal DRVB 2 &lt;4&gt; to drive the second node ND 22 . That is, the second pre-driver  251  may generate the first to fourth pre-background data PRE_DQ 2 &lt;1:4&gt; whose drivabilities are controlled according to a level combination of the first to fourth background drive signals DRV 2 &lt;1:4&gt;. The first to fourth complementary background drive signals DRVB 2 &lt;1:4&gt; may correspond to inverted signals of the first to fourth background drive signals DRV 2 &lt;1:4&gt;, respectively. 
     Operations of the semiconductor system as set forth above will be described hereinafter with reference to  FIGS. 2 to 7  in conjunction with an example that drivabilities of the first to fourth foreground data DQ 1 &lt;1:4&gt; are controlled when delay times of the first to fourth foreground data DQ 1 &lt;1:4&gt; are greater than a normal delay time. The following description will be developed in conjunction with an example that the first to fourth pattern data PD&lt;1:4&gt; are set to have a level combination of ‘L,H,L,H’ and the first to fourth foreground control signals DC 1 &lt;1:4&gt; are set to have a level combination of ‘L,L,L,H’. 
     The command generator  11  of the controller  1  may generate a pulse of a first command signal MRR in response to a test enable signal TMEN enabled when a test mode starts. The selection signal generator  12  may generate a selection signal SEL having a first level (e.g., a logic “low” level) if a pulse of a read latency signal RDOUT is inputted after a predetermined time elapses from a time that the pulse of the first command signal MRR is generated. 
     In the semiconductor memory device  2 , the input buffer  211  of the drive signal generator  21  may buffer the pulse of the first command signal MRR to generate a first internal command signal IRD. The signal storage unit  212  may receive the first internal command signal IRD provided from the input buffer  211  to output first to fourth pattern data PD&lt;1:4&gt; having a level combination of ‘L,H,L,H’. The data I/O controller  213  may receive the first internal command signal IRD provided from the input buffer  211 , to load the first to fourth pattern data PD&lt;1:4&gt; having the level combination of ‘L,H,L,H’ on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt;. The first output buffer  23  may buffer signals loaded on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; to generate first to fourth foreground data DQ 1 &lt;1:4&gt;. In such a case, because the first to fourth foreground control signals DC 1 &lt;1:4&gt; have a level combination of ‘L,L,L,H’, the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; may also have a level combination of ‘L,L,L,H’. That is, only the first foreground drive signal DRV 1 &lt;1&gt; among the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; may have a logic “high” level. Thus, only the first driving unit  2311  among the first to fourth driving units  2311 ,  2312 ,  2313  and  2314  constituting the first pre-driver  231  may operate to drive the second node ND 22 . 
     The multiplexer  131  of the comparison signal generator  13  may receive the selection signal SEL having the first level (e.g., a logic “low” level) to output the first to fourth foreground data DQ 1 &lt;1:4&gt; as first to fourth selection data SD&lt;1:4&gt;. The comparison code generator  132  may generate first and second comparison codes S&lt;1:2&gt; whose level combination is determined according to a level combination of the first to fourth selection data SD&lt;1:4&gt;. For example, if the delay times of the first to fourth foreground data DQ 1 &lt;1:4&gt; are greater than a normal delay time, levels of the first to fourth foreground data DQ 1 &lt;1:4&gt; may change at a rising edge and a falling edge of a clock signal. Thus, the comparison code generator  132  does not generate the first and second comparison codes S&lt;1:2&gt; having a level combination of ‘H,L’. The comparator  133  may compare the first and second comparison codes S&lt;1:2&gt; with first and second test codes T&lt;1:2&gt; having a level combination of ‘H,L’ to generate a pulse of a comparison signal COMP. That is, since the first and second comparison codes S&lt;1:2&gt; does not have the level combination of ‘H,L’, the first and second comparison codes S&lt;1:2&gt; are not identified to the first and second test codes T&lt;1:2&gt; so that the comparator  133  may generate the comparison signal COMP. The level combination ‘H,L’ of the first and second test codes T&lt;1:2&gt; means that the first test code T&lt;1&gt; has a logic “low” level and the second test code T&lt;2&gt; has a logic “high” level. In addition, because the number of bits having a logic “high” level among the bits of the first to fourth pattern data PD&lt;1:4&gt; is two, the first and second test codes T&lt;1:2&gt; may be set to have a level combination of ‘H,L’. 
     The counter  141  of the control signal generator  14  may count first and second count signals CNT&lt;1:2&gt; in response to a pulse of the comparison signal COMP to generate the first and second count signals CNT&lt;1:2&gt; having a level combination of ‘L,H’. The level combination ‘L,H’ of the first and second count signals CNT&lt;1:2&gt; means that the first count signal CNT&lt;1&gt; has a logic “high” level and the second count signal CNT&lt;2&gt; has a logic “low” level. The decoder  142  may decode the first and second count signals CNT&lt;1:2&gt; in response to the selection signal SEL. Since the selection signal SEL has the first level (e.g., a logic “low” level), the decoder  142  may output the first to fourth foreground control signals DC 1 &lt;1:4&gt; having a level combination of ‘L,L,H,H’, as an output signals thereof. 
     The command generator  11  may receive the pulse of a comparison signal COMP provided from the comparator  133  to generate a pulse of the first command signal MRR. The selection signal generator  12  may generate the selection signal SEL having the first level (e.g., a logic “low” level) in response to the read latency signal RDOUT enabled after a predetermined time elapses from a of time that the pulse of the first command signal MRR is generated and the comparison signal COMP. 
     The input buffer  211  of the semiconductor memory device  2  may buffer the pulse of the first command signal MRR provided from the command generator  11  of the controller  1  to generate the first internal command signal IRD. The signal storage unit  212  may receive the first internal command signal IRD to output first to fourth foreground control signals DC 1 &lt;1:4&gt; as the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; and to output the first to fourth pattern data PD&lt;1:4&gt; having a level combination of ‘L,H,L,H’. The data I/O controller  213  may receive the first internal command signal IRD to load the first to fourth pattern data PD&lt;1:4&gt; having the level combination of ‘L,H,L,H’ on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt;. The first output buffer  23  of the output buffer  22  may buffer signals loaded on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt; in response to the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; having a level combination of ‘L,L,H,H’ to generate the first to fourth foreground data DQ 1 &lt;1:4&gt; whose drivabilities are increased. In such a case, because the first to fourth foreground drive signals DRV 1 &lt;1:4&gt; have a level combination of ‘L,L,H,H’, the first and second driving units  2311  and  2312  among the first to fourth driving units  2311 ,  2312 ,  2313  and  2314  constituting the first pre-driver  231  may operate to increase the drivabilities of the first to fourth foreground data DQ 1 &lt;1:4&gt;. 
     The multiplexer  131  of the comparison signal generator  13  may receive the selection signal SEL having the first level (e.g., a logic “low” level) to output the first to fourth foreground data DQ 1 &lt;1:4&gt; as the first to fourth selection data SD&lt;1:4&gt;. The comparison code generator  132  may generate the first and second comparison codes S&lt;1:2&gt; whose level combination varies according to a level combination of the first to fourth selection data SD&lt;1:4&gt;. In such a case, because the drivabilities of the first to fourth foreground data DQ 1 &lt;1:4&gt; have been increased, level transition periods of the first to fourth foreground data DQ 1 &lt;1:4&gt; may become shorter. Thus, the rising edge and the falling edge of the clock signal may occurs after the level transition periods of the first to fourth foreground data DQ 1 &lt;1:4&gt;. As a result, the first and second comparison codes S&lt;1:2&gt; may be generated to have a level combination of ‘H,L’. The comparator  133  may compare the first and second comparison codes S&lt;1:2&gt; with first and second test codes T&lt;1:2&gt; having a level combination of ‘H,L’ not to generate a pulse of the comparison signal COMP. 
     The counter  141  of the control signal generator  14  does not count the first and second count signals CNT&lt;1:2&gt;. The decoder  142  may decode the first and second count signals CNT&lt;1:2&gt; to generate the first to fourth foreground control signals DC 1 &lt;1:4&gt; having a level combination of ‘L,L,H,H’ because the selection signal SEL has the first level (e.g., a logic “low” level). 
     The selection signal generator  12  may generate the selection signal SEL having a second level (e.g., a logic “high” level) because the pulse of the read latency signal RDOUT is inputted but no pulse of the comparison signal COMP is inputted after a predetermined time elapses from a time that the pulse of the first command signal MRR is generated. Thus, the command generator  11  may generate a pulse of a second command signal MRW because the selection signal SEL having the second level is inputted but no pulse of the comparison signal COMP is inputted. 
     The input buffer  211  of the semiconductor memory device  2  may buffer the pulse of the second command signal MRW to generate a second internal command signal IWT. The signal storage unit  212  may receive the second internal command signal IWT to store the first to fourth foreground control signals DC 1 &lt;1:4&gt; therein. 
     After the test mode terminates, the data I/O controller  213  may load first to fourth foreground internal data ID 1 &lt;1:4&gt; stored in memory cells on the first to fourth foreground I/O lines GIO 1 &lt;1:4&gt;. The first output buffer  23  may output the first to fourth foreground data DQ 1 &lt;1:4&gt; whose drivabilities are increased according to a level combination ‘L,L,H,H’ of the first to fourth foreground drive signals DRV 1 &lt;1:4&gt;. 
     The semiconductor system described above may control drivabilities of I/O lines to change level transition periods of data even though delay times of the data vary according to process/voltage/temperature (PVT) conditions. As a result, reliability of the data may be improved. 
     While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor integrated circuit described herein should not be limited based on the described embodiments. Rather, the semiconductor integrated circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Technology Category: 3