Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit and priority of Great Britain Patent Application No. 1313576.9 filed Jul. 30, 2013. The entire disclosure of the above application is incorporated herein by reference. 
     FIELD 
     The present disclosure relates to a method and control system for controlling a power converter by modulating switching signals in a switching device of the power converter. 
     BACKGROUND 
       FIG. 1  shows a well-known three phase power inverter  100  for converting a DC power supply  101  to an AC output  103  which may then be connected to a load (not shown). The inverter comprises three separate phases  200 ,  300 ,  400  (also referred to as phases U, V, W respectively). Each phase includes two switches in series:  200   a ,  200   b  in phase  200 /U;  300   a ,  300   b  in phase  300 /V; and  400   a ,  400   b  in phase  400 /W. Switches  200   a ,  300   a  and  400   a  are connected to the positive rail  105  (and may be referred to as the “upper” switches) and switches  200   b ,  300   b  and  400   b  are connected to the negative rail  107  (and may be referred to as the “lower” switches). In  FIG. 1 , each switch is an IGBT (insulated gate bipolar transistor) and, for each IGBT, an associated anti-parallel diode is also shown. However, any switches with fast switching capability may be used. A control system (such as a processor) (not shown) controls the switching of the switches  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b  to control the AC output of the inverter  100 . 
     A sinusoidal output current can be created at AC output  103  by a combination of switching states of the six switches. However, the inverter  100  must be controlled so that the two switches in the same phase are never switched on at the same time, so that the DC supply  101  is not short circuited. Thus, if  200   a  is on,  200   b  must be off and vice versa; if  300   a  is on,  300   b  must be off and vice versa; and if  400   a  is on,  400   b  must be off and vice versa. This results in eight possible switching vectors for the inverter, as shown in Table 1. In Table 1, the vector values are the states of the three upper switches  200   a ,  300   a ,  400   a , with the three lower switches  200   b ,  300   b ,  400   b  necessarily taking the opposite state to avoid shorting out the DC supply. 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Vector 
                 200a  
                 300a 
                 400a 
                 200b 
                 300b 
                 400b  
                 V UW   
                 V WV   
                 V VU   
                   
               
               
                   
               
             
             
               
                 V 0  = {000} 
                 OFF 
                 OFF 
                 OFF  
                 ON 
                 ON 
                 ON 
                 0 
                 0 
                 0 
                 Zero 
               
               
                 V 1  = {100} 
                 ON 
                 OFF 
                 OFF  
                 OFF 
                 ON 
                 ON 
                 +V dc   
                 0 
                 −V dc   
                 Active 
               
               
                 V 2  = {110} 
                 ON 
                 ON 
                 OFF  
                 OFF 
                 OFF 
                 ON 
                 0 
                 +V dc   
                 −V dc   
                 Active 
               
               
                 V 3  = {010} 
                 OFF 
                 ON 
                 OFF  
                 ON 
                 OFF 
                 ON 
                 −V dc   
                 +V dc   
                 0 
                 Active 
               
               
                 V 4  = {011} 
                 OFF 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
                 −V dc   
                 0 
                 +V dc   
                 Active 
               
               
                 V 5  = {001} 
                 OFF 
                 OFF 
                 ON 
                 ON 
                 ON 
                 OFF 
                 0 
                 −V dc   
                 +V dc   
                 Active 
               
               
                 V 6  ={101} 
                 ON 
                 OFF 
                 ON 
                 OFF 
                 ON 
                 OFF 
                 +V dc   
                 −V dc   
                 0 
                 Active 
               
               
                 V 7  = {111} 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
                 OFF 
                 0 
                 0 
                 0 
                 Zero 
               
               
                   
               
             
          
         
       
     
       FIG. 2  shows the six active vectors and the two zero voltage vectors of Table 1 graphically portrayed in an inverter voltage switching hexagon. Such vectorial representation of three-phase systems is well known to the skilled person and will not be described in detail. However, in general, any three-phase system can be represented uniquely by a rotating vector V S , as shown in  FIG. 2 . The rotating vector V S  comprises components of the six active vectors shown in Table 1 and  FIG. 2 . This is known as Space Vector Modulation (SWM). The voltage at the AC output  103  can be changed by varying the ratio between the zero voltage vectors V 0  and V 7  and the active vector V S  (comprising components of V 1  to V 6 ) (the modulation index) by pulse width modulation (PWM) techniques. 
       FIG. 3  shows an example of pulse width space vector modulation over two switching periods according to the prior art. The switching function for each upper switch  200   a ,  300   a ,  400   a  is a time waveform taking the value 1 when the upper switch is on and 0 when the upper switch is off (as will be appreciated, the switching function for each lower switch  200   b ,  300   b ,  400   b  will be the inverse of the corresponding upper switch) with dead-time included to prevent short circuiting. Thus a low represents the lower switch for the phase (e.g  200   b ,  300   b ,  400   b ) being ON and a high represents the upper switch for the phase (e.g  200   a ,  300   a ,  400   a ) being ON (neglecting dead-time protection). Referring to  FIG. 3 , during the first period t_ 0 , all three upper switches  200   a ,  300   a ,  400   a  are off (value 0) which produces vector V 0  of Table 1. V 0  is a zero voltage vector, so this time period t_ 0  is an inactive period. In the second period t_ 1 , switch  200   a  takes the value 1 and switches  300   a  and  400   a  take the value 0, which produces vector V 1 , which is an active vector. In the third period t_ 2 , switches  200   a  and  300   a  take the value 1 and switch  400   a  takes the value 0, which produces vector V 2 , which is also an active vector. Finally, during the fourth period t_ 3 , all three upper switches  200   a ,  300   a ,  400   a  are on (value 1) which produces zero voltage vector V 7  of Table 1. Thus, the active periods are t_ 1  and t_ 2  and the inactive period t i  is t_ 0  and t_ 3 . The ratio between the total active period (in this case, t_ 1 +t_ 2 ) and total inactive period (in this case, t_ 0 +t_ 3 =t i ) determines the output voltage at the AC output.  FIG. 3  shows a 50% duty cycle (i.e. 50% active) as an example. Other duty cycles may be operative. 
       FIG. 3  shows a typical space vector modulation (SVM) timing pattern for two PWM periods, with symmetric switching (i.e. t_ 0 =t_ 3 ). The ratio of t_ 0  and t_ 3  as shown in  FIG. 3  is one to one. 
       FIG. 4  shows D and Q axis components of the desired output voltage for two output wave cycles versus output voltage angle.  FIG. 5  shows D and Q axis components of the desired output voltage as plotted on the X and Y axis. 
       FIG. 6  shows phase voltages (with respect to the 0V line shown in  FIG. 1 , which is half of the dc bus) with symmetric switching (t_ 0 =t_ 3 ) versus output voltage angle (with a Dc bus of 250V and a 200VII peak demand).  FIG. 7  shows the resulting line to line voltage as seen by the motor load. 
     At low output frequencies (such as output frequencies less than around 1 Hz) the temperature of each individual switch  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b  can become excessive even if the current delivered by the drive is less than the inverter rated output current as each individual switch may be on for a period of time sufficient to cause excessive temperature of the switch. 
     Because of this, and other, problems, the control of switching power converters is an area of increasing interest. 
     It is an object of the described technique to provide an improved method and control system for a power converter. 
     SUMMARY 
     According to a first aspect, there is provided a method for controlling a switching device in a power converter according to a modulation scheme, the switching device for coupling a direct current (DC) source to provide an alternating current (AC) output at a particular switching frequency, the method comprising the: in each switching period, switching the switching device between active configurations providing a finite voltage at the output and inactive configurations providing a zero voltage at the output; wherein the ratio between the total period of time in which the switching device is in an active configuration and the total period of time in which the switching device is in an inactive configuration is the same for each switching period and is determined according to the desired voltage at the AC output; and wherein, in each switching period, there are at least two time periods in which the switching device is in an inactive configuration, and the ratio between those at least two time periods is changed in dependence on the temperature associated with the switching device. 
     The method varies the non-active (zero voltage) portion of the modulation scheme. The ratio between the total non-active portion and the total active portion is kept the same for all the switching periods, according to the desired output voltage. However, the ratio between the at least two inactive time periods changes, for instance in each switching period, whilst keeping the total non-active portion the same, in response to temperature associated with the individual switches of the switching device. The inventors have found that this helps to manage the temperature of the switches at a low switching frequency, without altering the switching period or swapping between switching frequencies. This method does not require a complex pulse width modulator. This method also does not require continual re-scaling of the current measurement or gain. 
     The ratio of t_ 0  and t_ 3  can be used to alter the ratio of upper to lower conduction times while still maintaining the same line to line voltage (as long as the sum of t_ 0  and t_ 3  remains constant). 
     In one embodiment, the ratio in temperature of the upper and lower IGBTs is altered by offsetting the output phase voltages which in turn alters the conduction times and thus the conduction losses. This is achieved by controlling the PWM switching pattern which results in a change in the ON times for the switches. This aims to reduce the probability of the drive tripping on excessive inverter temperature. 
     The method is particularly advantageous for low output frequencies, such as frequencies of 1 Hz or less. This method provides a degree of thermal control which either postpones or removes the need for output current rating reduction at low output frequencies. Thermal control may be provided in a low frequency region (for example below 1 Hz) based on the space vector modulation switching pattern. 
     The ratio between the at least two time periods in which the switching device is in an inactive configuration may be changed in a switching period in dependence upon temperature associated with the individual switches of the switching device. 
     The power converter may comprise a three phase power inverter. The switching device in the three phase inverter comprises three phases, each phase including two switches in series. One switch in each phase is connected to a positive rail, the other switch in each phase is connected to a negative rail and an output is connected between the two switches in each phase. However, the power converter need not comprise a three phase power inverter and the technique is applicable to any multilevel inverter. 
     The method may employ a space vector modulation scheme for controlling the power converter switching device. This is advantageous as it is able to produce a large range of output voltages. 
     In an embodiment at least one of the switches in the three phase inverter is an insulated gate bipolar transistor (IGBT). All the switches may be IGBTs. IGBTs have fast switching capability and are also highly efficient. IGBTs may be included in any inverters, not only three phase inverters. 
     According to a second aspect of the disclosure, there is provided a control system for a power converter switching device, the switching device for coupling a direct current (DC) source to provide an alternating current (AC) output at a particular switching frequency, the control system comprising: a controller for switching the switching device in the power converter according to a modulation scheme, the controller being arranged to switch the switching device, in each switching period, between active configurations providing a finite voltage at the output and inactive configurations providing a zero voltage at the output; wherein the ratio between the total period of time in which the switching device is in an active configuration and the total period of time in which the switching device is in an inactive configuration is the same for each switching period and is determined according to the desired voltage at the AC output; and wherein, in each switching period, there are at least two time periods in which the switching device is in an inactive configuration, and the ratio between those at least two time periods is changed in dependence on the temperature associated with the switching device. 
     The control system of the disclosure varies the non-active (zero voltage) portion of the modulation scheme. The ratio between the total non-active portion and the total active portion is kept the same for all the switching periods, according to the desired output voltage. However, the ratio between the at least two inactive time periods changes (whilst keeping the total non-active portion the same). This produces a way to manage the temperature of the switches at a low switching frequency, without altering the switching period or swapping between switching frequencies. The control system is particularly advantageous for low output frequencies. 
     The ratio between the at least two time periods in which the switching device is in an inactive configuration may be changed for instance every switching period or at a time determined by the control system. 
     According to a third aspect of the disclosure, there is provided a switching power converter comprising: a switching device for coupling a direct current (DC) source to provide an alternating current (AC) output at a particular switching frequency; and a controller for switching the switching device according to a modulation scheme, the controller being arranged to switch the switching device, in each switching period, between active configurations providing a finite voltage at the output and inactive configurations providing a zero voltage at the output; wherein the ratio between the total period of time in which the switching device is in an active configuration and the total period of time in which the switching device is in an inactive configuration is the same for each switching period and is determined according to the desired voltage at the AC output; and wherein, in each switching period, there are at least two time periods in which the switching device is in an inactive configuration, and the ratio between those at least two time periods is changed in response to the operating temperature associated with individual switches in the switching device. 
     The controller in the switching power converter varies the inactive portion of the modulation scheme, whilst keeping the ratio between the total inactive portion and the total active portion the same for all the switching periods, according to the desired output voltage. The ratio between the at least two inactive time periods changes in response to the operating temperature associated with individual switches in the switching device. This is particular useful at low switching frequency, without altering the switching period or swapping between switching frequencies, and is particularly advantageous for low output frequencies. 
     The ratio between the at least two time periods in which the switching device is in an inactive configuration may be changed every switching period in dependence upon the operating temperature of the switching device. 
     Features and advantages described in relation to one aspect of the described technique may also be applicable to another aspect of the described technique. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Prior art arrangements have already been described with reference to accompanying  FIGS. 1 to 7 , in which: 
         FIG. 1  shows a three phase inverter according to the prior art; 
         FIG. 2  shows a voltage switching hexagon for the three phase inverter of  FIG. 1 ; and 
         FIG. 3  shows an example of space vector modulation over two switching periods according to the prior art. 
         FIG. 4  shows an example of D and Q axis components of the desired output voltage for two output wave cycles versus output voltage angle according to the prior art. 
         FIG. 5  shows an example of D and Q axis components of the desired output voltage as plotted on the X and Y axis according to the prior art. 
         FIG. 6  shows an example of phase voltages (with respect to half dc bus) with symmetric switching (t_ 0 =t_ 3 ) versus output voltage angle according to the prior art. 
         FIG. 7  shows an example of the resulting line to line voltage as seen by the motor load according to the prior art. 
       The technique will now be further described, by way of example only, with reference to accompanying  FIGS. 8 to 17 , in which: 
         FIG. 8  shows a three phase inverter according to an embodiment of the disclosure; 
         FIG. 9  shows a flow diagram for controlling the three phase inverter according to an embodiment of the disclosure; 
         FIG. 10  shows an example of space vector modulation over one switching period according to an embodiment of the disclosure with t_ 3  being at its minimum; 
         FIG. 11  shows the phase voltages (with respect to the negative DC bus) versus output voltage angle with asymmetric switching (t_ 0 ≠t_ 3 ) with t_ 3  being at its minimum; 
         FIG. 12  shows an example of space vector modulation over one switching period according to an embodiment of the disclosure with t_ 0  being at its minimum; 
         FIG. 13  shows the phase voltages (with respect to the negative DC bus) versus output voltage angle with asymmetric switching (t_ 0 ≠t_ 3 ) with t_ 0  being at its minimum; 
     
    
    
     DETAILED DESCRIPTION 
     Symmetrical modulation methods, such as that described with reference to  FIG. 3 , split the inactive period t i  in half, placing half the inactive period t_ 0  before the active period and the other half of the inactive period t_ 3  after the active period. Thus, in each switching period, there is a symmetric switching pattern. However, the inventors have found that using a particular non-symmetric switching pattern can ameliorate temperature rises in the switching devices. 
       FIG. 8  shows a three phase inverter according to an embodiment of the disclosure. As with  FIG. 1 ,  FIG. 8  shows a three phase power inverter  100  for converting a DC power supply  101  to an AC output  103  which may then be connected to a motor load. The inverter comprises three separate phases  200 ,  300 ,  400 . Each phase includes two switches in series:  200   a ,  200   b  in phase  200 ;  300   a ,  300   b  in phase  300 ; and  400   a ,  400   b  in phase  400 . Switches  200   a ,  300   a  and  400   a  are connected to the positive rail  105  (and may be referred to as the “upper” switches) and switches  200   b ,  300   b  and  400   b  are connected to the negative rail  107  (and may be referred to as the “lower” switches). In  FIG. 8 , each switch is an IGBT (insulated gate bipolar transistor). However, any switches with fast switching capability may be used. 
       FIG. 8  also shows temperature sensors  500  for sensing the temperature of the associated switch  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b . These temperature sensors may be any sensor suitable to sense the temperature of the individual switch  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b . For instance the temperature sensors  500  may comprise a thermocouple placed close to each switch  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b  on the associated PCB. 
       FIG. 9  is a flow diagram illustrating one embodiment to control the switches  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b  in dependence on the temperature associated with the switches. In operation  902 , a control system (e.g. a processor) receives the temperature readings from temperature sensors  500  associated with the switches  200   a ,  200   b ,  300   a ,  300   b ,  400   a ,  400   b . The control system them determines in operation  904  whether any temperature reading is above a threshold Threshold_ 1 . This threshold is set according to the operating characteristics of the inverter and the individual components used. For instance, for an IGBT, a suitable threshold may be 110 degrees Celsius. When the control system determines in operation  904  that none of the temperature readings is above a threshold (operation  904  answered in the negative), the control system returns to operation  902  and waits to receive the next set of temperature readings. 
     When the control system determines in operation  904  that at least one of the temperature readings is above a threshold (operation  904  answered in the affirmative), the control system turns to operations  906  and  908  and selects the highest temperature reading for an upper switch, T_upper_max and the highest temperature reading for a lower switch, T_lower_max. The control system then determines in operation  910  whether the absolute difference between T_upper_max and T_lower_max is greater than a threshold Threshold_ 2  (for example 5° C.) to provide a margin for hysteresis. If not (operation  910  answered in the negative) then the control system returns to operation  902  and waits to receive the next set of temperature readings (or takes other action that is not discussed further in this disclosure). If the absolute difference between T_upper_max and T_lower_max is greater than a threshold Threshold_ 2  (operation  910  answered in the affirmative) then the control system determines in operation  911  whether T_upper_max is greater than T_lower_max. If so (operation  911  answered in the affirmative) then the control system adjusts the inactive time period to decrease the inactive time period t_ 3  (upper switches  200   a ,  300   a ,  400   a  ON) and increase the inactive time period t_ 0  (lower switches  200   b ,  300   b ,  400   b  ON). This results in the active period within the PWM period switching pattern being slowly moved so that the upper switches are ON for less time than the lower switches. Similarly when the control system determines in operation  911  that T_upper_max is less than T_lower_max (operation  911  answered in the negative) then the control system adjusts the inactive time period to decrease the inactive time period t_ 0  (lower switches  200   b ,  300   b ,  400   b  ON) and increase the inactive time period t_ 3  (upper switches  200   a ,  300   a ,  400   a  ON). This means that the active period within the PWM period switching pattern may be slowly moved so that the lower switches are ON for less time than the upper switches. Thus, if the lower switches ( 200   b ,  300   b ,  400   b ) are warmer than the upper switches ( 200   a ,  300   a ,  400   a ) (given a hysteresis), the active period within the PWM period switching pattern may be slowly moved so that the lower switches are ON for less time than the upper switches. 
     The control system may adjust t_ 0  (and hence t_ 3 ) or t_ 3  (and hence t_ 0 ) in a gradual manner (say between t_ 3 _min and t_ 3 _max) until all temperature readings are below the threshold. This may be subject to a time constant (for example one second) i.e. a one second time constant means that the adjustment of the ratio of t_ 0  to t_ 3  changes from maximum (t_ 0 _max:t_ 3 _min) to minimum (t_ 0 _min:t_ 3 _max) in one second. The value of t_ 0  and t_ 3  may be changed in fixed increments or in a continuous manner. Alternatively the control system may adjust t_ 0  and t_ 3  in an increment dependent upon the magnitude of the highest temperature reading. The change in ratio may be controlled by proportional, integral and derivative (PID) control techniques. Alternatively, the control means may adjust the t− 0 /t_ 3  ratio in any other suitable manner. 
       FIG. 10  shows an example of pulse width space vector modulation over one switching period according to an embodiment of the described technique. Again, the switching function for each phase U, V, W is a time waveform taking the value 1 when the upper switch is on and 0 when the upper switch is off. In  FIG. 10 , the total active period is t_ 1 +t_ 2 , as before, and the total inactive period is t i  as before, the total inactive period t i  including a portion t_ 0  before the active period and a portion t_ 3  after the active period, where t_ 0 +t_ 3 =t i . However, in the modulation scheme illustrated in  FIG. 10 , t_ 0  and t_ 3  are changed in response to temperature of the switching elements of the switching device and t_ 0  and t_ 3  are not necessarily equal. Changing the ratio of t_ 0  to t_ 3  can be used to alter the ratio of upper to lower conduction times while still maintaining the same line to line voltage (as long as the sum of t_ 0  and t_ 3  remains constant). 
     The inventors have found that changing the ratio of t_ 0  to t_ 3  in a switching period (whilst keeping t_ 0 +t_ 3 =t i  to produce the desired output voltage) can help manage the temperature of individual switches  200   a ,  300   a ,  400   a ,  200   b ,  300   b ,  400   b  of the switching device of the power converter. This is particularly advantageous for low output frequencies because at low output frequencies each switch is on for longer than at higher frequencies and the difference in temperature between switches is larger. In simple terms, the magnitude of the line to line voltage vector produced depends on the ratio of the active period to the PWM period and the angle of the line to line voltage vector produced depends on the ratio of t_ 1  and t_ 2  and the order of the edges. The active period is equal to t_ 1  plus t_ 2  and the PWM period is equal to 2*(t_ 0 +Active period+t_ 3 ) or 2*(t_ 0 +t_ 1 +t_ 2 +t_ 3 ). 
     The preferred ratio of t_ 0  to t_ 3  in a given switching period is set in response to the operating temperature associated with individual switches in the switching device. 
     At low output frequencies (&lt;1 Hz) the ratio in temperature of the upper and lower IGBTs can be altered by offsetting the output phase voltages (as referenced to half the DC bus.) This can be achieved by controlling the PWM switching pattern which results in a change in the IGBT ON times. For example, if the upper switches ( 200   a ,  300   a ,  400   a ) are warmer than the lower switches ( 200   b ,  300   b ,  400   b ) (given a hysteresis), the active period within the PWM period switching pattern is slowly moved so that the upper switches are ON for less time than the lower switches subject to a time constant (for example one second). Similarly if the lower switches ( 200   b ,  300   b ,  400   b ) are warmer than the upper switches ( 200   a ,  300   a ,  400   a ) (given a hysteresis), the active period within the PWM period switching pattern is slowly moved so that the lower switches are ON for less time than the upper switches, subject to a time constant (for example one second). 
     The ratio of t_ 0  to t_ 3  can be altered to produce asymmetric switching which produces an offset on the phase voltage waves (as referenced to half the DC bus). The ON times of the upper switches will be at their lowest when t_ 3  equals half the minimum pulse width. The ON times of the lower switches will be at their lowest when t_ 0  equals half the minimum pulse width. The minimum pulse width will depend on the operating characteristics of an individual inverter but in general is the minimum period to allow switching of a switch (e.g. an IGBT) to occur. 
     The resulting line to line voltages will be unchanged as long as the t_ 1  and t_ 2  periods are not changed (the sum of which is the active period) and thus the sum of t_ 0  and t_ 3  remains the same. Also the resulting line to line voltages will be unchanged as long as t_ 0  and t_ 3  are greater or equal to half the minimum pulse width (as any further reduction will result in pulse dropping which will affect the line to line voltages). 
       FIG. 10  shows a phase switching diagram with asymmetric switching (t_ 0 ≠t_ 3 ). The minimum value for t_ 3  is half the minimum pulse width (i.e. the minimum pulse width is 2*t_ 3 _min). As can be seen in  FIG. 10 , the PWM pattern plot shows how the ON times of all three upper IGBTs have been reduced (compared with that shown in  FIG. 3 ) as t_ 3  has been reduced (t_ 3  is an element of all of the upper IGBT ON times). The ON times of the upper IGBTS will be lowest when t_ 3  equals half the minimum pulse width (as shown in  FIG. 10 ).  FIG. 11  shows the phase voltages (with respect to the negative half DC bus) versus output voltage angle with asymmetric switching (t_ 0 ≠t_ 3 ) with t_ 3  being at its minimum ((2*t_ 3 )=minimum pulse width). 
     The D and Q axis components of the desired output voltage for two output wave cycles versus output voltage angle and the D and Q axis components of the desired output voltage as plotted on the X and Y axis remains unchanged as long as the sum of t_ 0  and t_ 3  remains constant. Similarly the resulting line to line voltage as seen by the motor load is unchanged as long as the sum of t_ 0  and t_ 3  remains constant. 
       FIG. 12  shows a phase switching diagram with asymmetric switching (t_ 0 ≠t_ 3 ). The minimum value for t_ 0  is half the minimum pulse width (i.e. the minimum pulse width is 2*t_ 0 _min). As can be seen in  FIG. 12 , the PWM pattern plot shows how the ON times of all three lower IGBTs have been reduced (compared with that shown in  FIG. 3  or  FIG. 10 ) as t_ 0  has been reduced (t_ 0  is an element of all of the lower IGBT ON times). The ON times of the lower IGBTS will be lowest when t_ 0  equals half the minimum pulse width (as shown in  FIG. 12 ).  FIG. 13  shows the phase voltages (with respect to the negative half DC bus) versus output voltage angle with asymmetric switching (t_ 0 ≠t_ 3 ) with t_ 0  being at its minimum ((2*t_ 0 )=minimum pulse width). 
     Thus t_ 0  may be varied between t_ 0 _max (as shown in  FIG. 10 ) and t_ 0 _min (as shown in  FIG. 12 ) with t_ 3  being varied between t_ 3 _min (as shown in  FIG. 10 ) and t_ 3 _max (as shown in  FIG. 12 ) while maintaining the total inactive period ti=t_ 0 +t_ 3  constant, with the resulting phase voltages altering between that shown in  FIG. 11  to that shown in  FIG. 13  respectively. The ON times of the upper IGBTS will be lowest when t_ 3  equals t_ 3 _min (half the minimum pulse width) as shown in  FIG. 10 . The ON times of the lower IGBTS will be lowest when t_ 0  equals t_ 0 _min (half the minimum pulse width) as shown in  FIG. 12 . t_ 0  and t_ 3  are adjusted in response to the operating temperature of the switching device to enable temperature of the switching device to be managed. 
     In the foregoing specification, techniques have been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the scope of the technique. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. 
     It is to be noted that the methods as described have actions being carried out in a particular order. However, it would be clear to a person skilled in the art that the order of any actions performed, where the context permits, can be varied and thus the ordering as described herein is not intended to be limiting. 
     It is also to be noted that where a method has been described it is also intended that protection is also sought for a device arranged to carry out the method and where features have been claimed independently of each other these may be used together with other claimed features. 
     Embodiments have been described herein in relation to IGBT switches. However the method and apparatus described are not intended to be limited to these types of switches but may be applicable to other switches.

Technology Category: 5