Patent Document

CROSS REFERENCE TO RELATED APPLICATION 
     The present application is a divisional application of U.S. patent application Ser. No. 14/750,120, “METHOD OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH ABRUPT JUNCTIONS AND INTEGRATED CIRCUIT CHIPS WITH THE FETS” to Kangguo Cheng et al., filed Jun. 25, 2015, assigned to the assignee of the present invention and incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to manufacturing integrated circuits with metal gate Field Effect Transistors (FETs) with abrupt junctions. 
     Background Description 
     Primary integrated circuit (IC) chip manufacturing goals include increasing chip density and performance at minimized power consumption, i.e., packing more function operating at higher speeds in the same or smaller space. Transistors or devices are formed by stacking layers of shapes on the IC, e.g., printed layer by layer on a wafer using photolithographic techniques. A simple field effect transistor (FET), or device, is defined by the intersection of two shapes, one for channel and one for gate. Generally, device current is governed by the ratio of its width to length. Shrinking/reducing chip feature sizes to increase density and performance provides a corresponding reduction in minimum device dimensions, e.g., minimum channel length. Using shorter devices allows/requires thinner vertical feature dimensions, e.g., a shallower channel layer and junction depth, thinner gate dielectric, and connecting wires and vias. 
     Most state of the art ICs are made on a bulk wafer or in silicon on insulator (SOI) wafer, in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS for minimized power consumption. A typical CMOS circuit includes paired complementary devices, or FETs, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually both gated by the same signal. Since the pair of devices in an ideal inverter have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (modeled as an open switch) and, vice versa. With one switch closed and the other open, ideally, there is no static current flow. 
     No device is ideal, however, and there are unwanted currents flowing even in off devices. Further, as device dimensions shrink, previously negligible device characteristics have become appreciable. For example, gate to channel, gate to source/drain, subthreshold current, and other short channel effects may be problematic in state of the art short channel FETs. Especially for complex chips and arrays with a large number of devices, these short channel effects can be overwhelming. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA). 
     Replacing FET gate oxide with a high-k dielectric has eliminated most of the unwanted gate oxide leakage, e.g., gate to channel and/or gate to source/drain. Since, polysilicon cannot be used with high-k dielectrics, work function metal and aluminum is being used for gates instead of polysilicon. In what is known as Replacement Metal Gate (RMG) FETs, typical polysilicon gate FETs are formed through source/drain extension, source/drain diffusion and interlayer dielectric (ILD) formation on the source/drain diffusions. Then, the polysilicon gates are removed and replaced, e.g., when contacts are formed through the ILD. 
     Unfortunately, forming well-controlled abrupt junctions using state of the art RMG manufacturing processes has been challenging. These processes typically involve various annealing temperatures post extension and source/drain junction formation. These various annealing temperatures affect junction position, e.g., causing unwanted out-diffusion. Diffusing FET junctions may tend to migrate towards each other enhancing short-channel effects. Moreover, high-mobility channel materials, such as germanium (Ge) or III-V semiconductor, have well known material instability issues with very high temperature dopant drive-in, or activation. Source/drain junctions in these materials become very resistive as a result of the low temperature processing required to form a high-k/metal gate (HK/MG) stack, i.e., to replace polysilicon gates with metal gates. 
     Thus, there is a need for reducing short channel effects for RMGFETs; and more particularly, for forming abrupt junctions that are unaffected by subsequent RMGFET formation steps. 
     SUMMARY OF THE INVENTION 
     In an aspect of the invention short channel effects are reduced in Integrated Circuit (IC) field effect transistors (FETs) without impairing performance; 
     In another aspect of the invention abrupt junctions for replacement metal gate FETs (RMGFETs) form unaffected by high temperature annealing in source drain epitaxy growth and diffusion; 
     In yet another aspect of the invention source/drain extensions for RMGFETs, form well controlled, and after forming interlayer dielectric (ILD) on completed RMGFET source/drain regions; 
     In yet another aspect of the invention short channel effects are reduced/minimized in ICs with preferred RMGFETs source/drain extensions that are formed well controlled after forming interlayer dielectric (ILD) on already completed RMGFET source/drain regions; 
     The present invention relates to a method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at each end of FET channels. Source/drain regions adjacent to each channel placeholder extend into and fill the undercut. The channel placeholder is opened to expose channel surface under each channel placeholder. Source/drain extensions are formed under each channel placeholder, adjacent to each source/drain region. After removing the channel placeholders metal gates are formed over each said FET channel. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
         FIG. 1  shows an examples of steps of forming RMGFETs, according to a preferred embodiment of the present invention; 
         FIGS. 2A-B  show an example of defining a chip device on a semiconductor wafer; 
         FIG. 3  shows an example of formed dummy sidewall spacers along the dummy gates on the dummy dielectric; 
         FIG. 4  shows an example of patterned dummy dielectric undercutting the dummy spacers; 
         FIG. 5A-B  shows an example of formed FET source/drains outboard of the dummy spacers and in the undercuts, and ILD formed on the wafer; 
         FIGS. 6A-B  show an example of removing the dummy gates to re-expose the patterned dummy dielectric between the dummy spacers; 
         FIG. 7  shows an example of the structure after removing all of the patterned dummy dielectric to re-expose the wafer surface between and beneath the dummy spacers; 
         FIGS. 8A-C  show an example of forming source/drain extensions under the dummy spacers; 
         FIGS. 9A-D  show an example of forming metal gates above the channel, between the source/drain extensions to complete the RMG FETs; 
         FIG. 10  shows an example of a wafer with multiple IC chips after middle of the line (MOL) dielectric and contact formation and through normal back end of the line (BEOL). 
     
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Turning now to the drawings and, more particularly,  FIG. 1  shows an example of a method  100  of forming semiconductor devices, Replacement Metal Gate (RMG) gate Field Effect Transistors (FETs), and integrated circuit (IC) chips with preferred RMGFETs, according to a preferred embodiment of the present invention. Although described with reference to CMOS, the present invention has application to any suitable replacement metal gate technology. The preferred method  100  has application to forming RMGFETs on bulk or silicon on insulator (SOI) wafers with SOI planar, mesa, fin or nanowire channels. Bulk wafers may be silicon, germanium (Ge), a III-V semiconductor or compound thereof. Fin or nanowire channels may include more than one fin or nanowire. 
     Fabrication begins in step  102  defining dummy devices (FETs). Dummy sidewall spacers are formed step  104  on the dummy dielectric layer. Patterning  106  the dummy dielectric, which partially undercuts the dummy spacers. Next,  108  source/drain regions and interlayer dielectric are formed on the wafer. The dummy gates are removed in step  110  to re-expose the remaining dummy dielectric. The dummy dielectric is removed in  112 . Then, source/drain extensions are formed in  114  under the dummy spacers. In step  116  metal gates are formed to complete the RMGFETs. Thereafter, in step  118  chip processing continues to complete Integrated circuit (IC) chip definition. 
     So, in step  102  dummy devices (FETs) are defined on a typical semiconductor wafer. Preferably, dummy FETs include dummy gates on a dummy dielectric layer. The dummy gates locate FET channels in/on a semiconductor surface of the wafer. Previously, at this point in typical prior art RMGFET formation, the dummy dielectric layer was patterned with the dummy gates (as dummy gate dielectric) and source/drain extension regions were defined adjacent to the dummy gates. 
       FIGS. 2A-B  show an example of defining a chip device on a semiconductor wafer  120  (definition step  102  in  FIG. 1 ). The semiconductor wafer may be an SOI wafer or a bulk doped or undoped wafer of silicon (Si), silicon germanium (SiGe) or any suitable semiconductor. Device channels, formed in/on the semiconductor wafer  120 , may be bulk surface channels or SOI channels, planar, fins or Nanowires. Channels may be defined using an active isolation step such as, for example, shallow trench isolation (STI) or mesa formation. A dummy dielectric layer  122  is, preferably, a 3 to 6 nanometer (3-6 nm) thick oxide formed on the wafer surface  124 , with excellent etch selectivity to subsequently formed dummy gate  126  material. Suitable such oxides include, for example, SiO 2 , GeO 2 , and aluminum oxide (Al 2 O 3 ). 
     Dummy gates  126  are formed by first forming a layer of a suitable material, e.g. polysilicon (poly), on the dummy dielectric layer  122 . A hard mask  128  patterned on the dummy gate material layer defines and protects gates  126 . The hard mask  128  may be any suitable material, including for example, silicon nitride (Si 3 N 4 ) layer, patterned photolithographically using a suitable well know photolithographic mask and etch. After forming the hard mask  128  pattern, exposed dummy gate material is removed, e.g., etched with an etchant selective to poly. As noted hereinabove, source/drain extension regions are not defined adjacent to the dummy gates  126  at this point. 
     Instead, as shown in the example of  FIG. 3 , dummy sidewall spacers  130  are formed (step  104  in  FIG. 1 ) along the dummy gates  126  and on the dummy dielectric  122 . The dummy sidewall spacers  130  may be formed, for example, by forming a conformal layer of sidewall dielectric and removing horizontal portions with a directional etch, e.g., a reactive ion etch (RIE). The dummy sidewall spacer  130  dielectric may be any suitable dielectric, preferably a nitride such as, Si 3 N 4 , SiBCN, SiNH or BN. 
       FIG. 4  shows an example of patterned ( 106  in  FIG. 1 ) dummy dielectric  140  undercutting the dummy spacers  130 . The dummy gates  126  and sidewall spacers  130  serve as a mask for patterning  106  the dummy dielectric layer. Patterning  106  partially undercuts  142  the dummy spacers  130 . The patterned dummy dielectric  140  remains under the dummy gates  126 , and at least partially under dummy sidewalls spacers  130  to undercuts  142 , where source/drain extension regions are subsequently formed. Patterning the dummy dielectric  140  completes placeholder  144  formation for source/drain region and interlayer dielectric formation. 
     So, as shown in the example of  FIGS. 5A-B , FET source/drains  150  (formed  108  in  FIG. 1 ) form outboard of the dummy spacers  130  and extend into the placeholder undercuts  142 , followed by ILD  152  formation. The FET source/drains  150  may be formed, for example, by epitaxially growing doped semiconductor on the semiconductor surface (e.g., on fins) at source/drain regions and/or by a deep source/drain ion-implant. Preferably for finFETs, doped epitaxially grown semiconductor is phosphorous or arsenic-doped silicon (Si) grown on NFET fins, and boron-doped silicon germanium (SiGe) grown on PFET fins. Interlayer dielectric  152  covers the source/drain regions  150  and fills between the placehholders  144 . 
       FIGS. 6A-B  show an example of removing (step  110  in  FIG. 1 ) the dummy gates  126  to re-expose the patterned dummy dielectric  140  between the dummy spacers  130 . An interlayer dialectic (ILD)  160  formed on the wafer fills between the dummy spacers  130 . Preferably, the ILD  160  is an oxide such as SiO 2 , or a lower k oxide. The patterned hard mask  128  is removed, e.g., using an oxide CMP, to re-expose the tops of dummy gates  126 . In this example, the CMP removes upper portions of the dummy spacers  130  and ILD  160 . The exposed dummy gates  126  may be removed, for example, with a suitable etch selective to silicon. 
       FIG. 7  shows an example of the structure after ( 112  in  FIG. 1 ) removing all of the patterned dummy dielectric to re-expose the wafer surface between and beneath the dummy spacers  130 , i.e., at the channel and extensions. The patterned dummy dielectric may be removed using any suitable wet etch, such as a hydrofluoric acid (HF) based solution, or a highly selective dry etch. 
       FIGS. 8A-C  show an example of forming ( 114  in  FIG. 1 ) source/drain extensions under the dummy spacers  130 . Preferably, source/drain extensions are formed by depositing and selectively patterning an atomic layer dopant through the open space between the dummy spacers. A dopant diffusion step, e.g., an extension anneal, forms well controlled source/drain extensions from the patterned atomic layer dopant. 
     In one preferred embodiment, a seven angstrom (7 Å) atomic layer dopant (ALDo) is deposited on the wafer selective to the dummy spacers  130 , forming ALDo  180  where previously existing patterned dummy dielectric was removed. Suitable atomic layer dopants include atomic boron or germanium-boron for PFETs and atomic phosphorous (P) for NFETs. Selectively etching ALDo  180 , e.g., in a timed etch, removes the dopant from the FET channel surface  182 , leaving dopant pockets  184  (&lt;3 nm wide) under the dummy spacers  130 . A junction rapid anneal drives in the dopant in pockets  184 , activating extension  186 . Preferably, the junction rapid anneal is at a temperature that does not alter channel material stability. For example, annealing temperature may range from 450-900° C. depending on the channel material with lower temperatures for III-V semiconductor and Ge, and relatively higher temperatures for Si-based channels. Because, there is no need for subsequent high temperature processing steps or anneals, the source/drain extension  186  junctions remain where they form, essentially unaffected by subsequent fabrication steps. 
       FIGS. 9A-D  show an example of forming ( 116  in  FIG. 1 ) metal gates above the channel, between the source/drain extensions to complete the RMGFETs. First, a suitable selective wet etch strips the dummy spacers  130  away, and exposes the extensions  186 . Final low-k spacers  190  are formed above the extensions  186 , e.g., by forming a conformal layer of sidewall dielectric and removing horizontal portions with a directional etch, e.g., a reactive ion etch (RIE). Suitable low-k dielectric may include, for example, SiBCN, SiNH or BN. A high-k gate dielectric layer  192  is formed, e.g., deposited, on the wafer. Suitable such high-k dielectric may be, for example, hafnium oxide (HfO 2 ), HfSiO, HfSiON, AlO, Al 2 O 3 , Titanium oxide (TiO 2 ), Lanthanum oxide (La 2 O 3 ) or a combination or stack thereof. Metal gates  194  are formed by forming a metal layer on the high-k gate dielectric layer  192  and removing surface portions of the metal layer and high-k dielectric layer  192  to the ILD  160 . The surface metal layer and high-k dielectric layer  192  may be removed using a typical CMP that re-planarizes the wafer surface and leaves metal gates  194  in metal gate dielectric  196 . 
       FIG. 10  shows an example of a wafer  200  with multiple IC chips  202  after ( 118  in  FIG. 1 ) middle of the line (MOL) dielectric and contact formation and through normal back end of the line (BEOL) steps. Circuit definition continues normally as wiring is formed  116  on and above the planarized surface. The wiring connects devices (preferred FETs) together into circuits  202  and circuits  202  together on the chips  204 . BEOL fabrication continues complete the chips  204 , e.g., connecting the circuits to pads and terminal metallurgy. 
     Thus advantageously, short channel effects are reduced/minimized in ICs with preferred RMGFETs. Source/drain extensions are formed well controlled, because they are formed after forming interlayer dielectric (ILD) on already completed source/drain regions and just prior to forming metal gates. 
     While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive.

Technology Category: 5