Patent Document

TECHNICAL FIELD 
     This subject matter is generally related to electronics, and more particularly to digital-to-analog converter (DAC) architectures. 
     BACKGROUND 
     A digital-to-analog converter (DAC) is a device that converts a digital code (e.g., a binary code) into an analog signal. A conventional DAC architecture uses a sequence of numbers to update an analogue voltage at uniform sampling intervals. The sequence of numbers can be written to the DAC with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes from a previous value to a value represented by the currently latched number. The output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant shaped output. The piecewise constant shaped output or rectangular pulses can cause multiple harmonics above the Nyquist frequency, which can be removed with a reconstruction filter. 
     Other conventional DAC architectures, such as DAC methods based on Delta-sigma modulation produce a pulse-density modulated signal that can then be filtered to produce a smoothly varying signal. 
     These conventional DAC architectures typically are implemented as analog circuits and thus can consume a significant amount of current and silicon area, making such conventional DAC architectures unsuitable for some applications where a low cost DAC architecture is desired. 
     SUMMARY 
     A current source is used to pre-charge a capacitor to a known value. The capacitor can then be connected to a buffer to provide a low cost DAC. The DAC can include a self-calibration stage to improve accuracy. The DAC can include two or more parallel circuit branches, each including a current source and a capacitor, where each branch can be calibrated and operated separately to reduce mismatch and to provide a continuous analog voltage output. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a simplified schematic diagram of an exemplary integrating DAC architecture. 
         FIG. 2  is a simplified schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 1  illustrating charge removal and reset during a self-calibration stage. 
         FIG. 3  is a simplified schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 2  illustrating the establishing of a reference during the self-calibration stage. 
         FIG. 4  is a simplified schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 2  illustrating charge removal and reset during a conversion stage. 
         FIG. 5  is a simplified schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 1  illustrating setting a target analog voltage during a conversion stage. 
         FIG. 6  is a simplified schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 2  illustrating setting an output voltage. 
         FIG. 7  is a simplified schematic diagram of an exemplary integrating DAC architecture illustrating multiple branches in different stages of operation to provide continuous output. 
         FIG. 8  is a flow diagram of an exemplary calibration process using an integrating DAC architecture. 
         FIG. 9  is a flow diagram of an exemplary conversion process using an integrating DAC architecture. 
     
    
    
     DETAILED DESCRIPTION 
     Circuit Overview 
       FIG. 1  is a simplified schematic diagram of an exemplary integrating 3-bit DAC architecture  100 . In some implementations, the architecture  100  can include an analog comparator  102 , current sources  104   a - 104   c  (e.g., linear current sources), buffer  106 , state machine  108 , digital counter  110 , switches S 1 -S 12  and capacitors C 1 -C 3 . The architecture  100  can include multiple parallel circuit branches, each branch can include a current source and a capacitor. In the architecture shown, a first branch includes the current source  104   a  and the capacitor C 1 , a second branch includes the current source  104   b  and the capacitor C 2  and a third branch includes the current source  104   c  and capacitor C 3 . 
     The architecture  100  can have two or more parallel branches, where at least two branches can be configured through switches to provide a continuous voltage output. In each branch switches are operable to connect and disconnect the current source to the capacitor and to short the capacitor to ground to remove charge on the capacitor. The current sources  104   a - 104   c  can be selected to be closely matched. In some implementations, an integrator can be used as a source, or capacitors and large resistors as pull-up sources, rather than current sources  104   a - 104   c.    
     The state machine  108  can be implemented using a programmable logic device, a programmable logic controller, logic gates and flip flops or relays. In some implementations, a register can store state variables, a first block of combinational logic can determine the state transition, and a second block of combinational logic can determine the output of the state machine  108 . The state machine  108 , together with the digital counter  110 , can be used to close and open the switches S 1 -S 12  to affect various stages of circuit operation, as described in reference to  FIGS. 2-7 . 
     The digital counter  110  can be implemented using register-type circuits such as a flip-flop (e.g., Up-down counter), or any other known digital counter design. 
     Switches S 1 -S 12  can be semiconductor switches (e.g., MOSFET transistors). The control inputs to the switches S 1 -S 12  can be determined by the state machine  108 . 
     The voltage reference connected to the analog comparator  102  can be any suitable voltage reference (e.g., zener reference, bandgap reference). 
     The buffer  106  can be an operational amplifier configured for unity gain. For example, a unity gain buffer amplifier may be constructed by applying a full series negative feedback to an op-amp by connecting its output to its inverting input, and connecting the signal source to the non-inverting input. Other known buffer designs also can be used. 
     The analog comparator  102  can be a standard op-amp operating in open loop configuration (without negative feedback) or a dedicated analog comparator integrated circuit chip (e.g., Atmel AVR1302 analog comparator). 
     Circuit Operation 
       FIG. 2  is a schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 1  illustrating capacitor charge removal and reset during a self-calibration stage. The portion includes the analog comparator  102 , the first branch of architecture  100  (which includes current source  104   a  and capacitor C 1 ), buffer  106  and switches S 1 , S 4 , S 7 , and S 10 . The analog comparator  102  is connected to a voltage reference. 
     The calibration stage can start by opening switches  51 , S 4  and S 7  and closing switch S 10 . Opening switch S 1  disconnects the analog comparator  102  from the first branch. Opening switch S 4  disconnects the current source  104   a  from the capacitor C 1 . Opening switch S 7  disconnects the buffer  106  from the branch. Closing switch S 10  shorts the capacitor C 1  to ground, thus removing any charge stored over the capacitor C 1 . 
       FIG. 3  is a schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 2  illustrating the establishing of a reference during the self-calibration stage. The calibration stage continues establishes a reference by opening switches S 10  and S 7  and closing switches S 1 , S 4  and S 10 . Opening switch S 10  disconnects the capacitor from ground so that it can be charged by the currents source  104   a . Opening switch S 7  disconnects the buffer  106  from the branch. Closing switch S 1  connects the analog comparator  102  to the capacitor C 1 . Closing switch S 4  connects the current source  104   a  to the capacitor C 1 . 
     In this configuration, the capacitor C 1  is connected to the current source  104   a  and the capacitor C 1  is charged while the digital counter  110  counts cycles until the voltage over the capacitor C 1  is about equal to the reference voltage (or differs by a threshold amount), at which point the analog comparator  102  triggers and the digital count is stored (e.g., stored in a register). 
     A mathematical relationship can be established between the voltage over the capacitor and a digital value expressed as 
                       V   count     =       V   reference       Digital   count         ,           [   1   ]               
where V count  is the voltage change from one cycle, V reference  is the analog reference voltage and Digital count  is the number of cycles counted by the digital counter  110 . V reference  can also be described as the voltage stored over the capacitor plus the offset error in the analog comparator  102 .
 
     The digital count can be normalized to a standard resolution using the following expression 
                       Digital     count   ⁢           ⁢   _   ⁢           ⁢   LSB       =       Digital   count       2   N         ,           [   2   ]               
where Digital count  LSB is the number of cycles per LSB step and N is the desired resolution and is a positive integer. Expression [2] provides the required number of cycles for a voltage charge corresponding to 1 LSB step.
 
       FIG. 4  is a schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 2  illustrating charge removal and reset during a conversion stage. In the start of the conversion stage, switch S 10  is closed and switches S 1 , S 4  and S 7  are opened. Switch S 10  shorts the capacitor C 1  to ground to remove any charge before the current source  104   a  is connected to the capacitor C 1  and starts charging the capacitor C 1 . 
       FIG. 5  is a schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 1  illustrating setting a target analog voltage during a conversion stage. The conversion stage continues by opening switches S 1 , S 10  and S 7  and closing switch S 4  to allow the current source  104   a  to charge the capacitor C 1 . The capacitor C 1  is charged until a count by the digital counter  110  is equal to Digital output     —     count ·Digital count     —     LSB ·V reference  described in expression [1] can also be described as the voltage stored over the capacitor C 1 . With this observation, expression [1] can lead to the following new expression:
 
Digital output     —     count   ·V   count   =V   out ,  [3]
 
where V out  is the output voltage after Digital output     —     count  cycles. Based on expression [3], the required cycles to reach the desired output voltage can be calculated.
 
       FIG. 6  is a schematic diagram of a portion of the exemplary integrating DAC architecture of  FIG. 2  illustrating setting an output voltage. To set the output voltage, switches S 1 , S 4  and S 10  are opened and switch S 7  (connected to the buffer  106 ) is closed. After charging the capacitor C 1  to a target analog voltage, the charged capacitor C 1  is connected to the unity output buffer  106 , resulting in the voltage stored over the capacitor C 1  being transferred to the buffer  106  where it is held at the output of the DAC. 
       FIG. 7  is a schematic diagram of an exemplary integrating DAC architecture illustrating multiple branches in different stages of operation to provide continuous output. More particularly,  FIG. 7  illustrates how two or more branches in architecture  100  can be in different stages of operation at the same time to ensure continuous output from the DAC. Since the branches are calibrated and operated separately, mismatch between the circuit elements in different branches do not affect operation. 
     In the present configuration, switches S 1 , S 4 , S 5  and S 9  are closed and switches S 2 , S 3 , S 6 , S 7 , S 8 , S 10 , S 11  and S 12  are opened. This configuration results in the first branch operating in the calibration stage, the second branch operating in the conversion stage, and the third branch setting the output voltage of the DAC. Table I below illustrates the states of switches S 1 -S 12  for the various stages of operation for the 3 branches of the architecture  100  shown in  FIG. 7 . 
     
       
         
               
             
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE I 
               
             
             
               
                   
               
               
                 Switch States (O = opened, C = closed) 
               
             
          
           
               
                   
                 Branch 1 
                 Branch 2 
                 Branch 3 
               
             
          
           
               
                 Switches 
                 S1 
                 S4 
                 S7 
                 S10 
                 S2 
                 S5 
                 S8 
                 S11 
                 S3 
                 S6 
                 S9 
                 S12 
               
               
                   
               
               
                 Reset 
                 O 
                 O 
                 O 
                 C 
                 O 
                 O 
                 O 
                 C 
                 O 
                 O 
                 O 
                 C 
               
               
                 Establish  
                 C 
                 C 
                 O 
                 O 
                 C 
                 C 
                 O 
                 O 
                 C 
                 C 
                 O 
                 O 
               
               
                 reference 
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 Set analog  
                 O 
                 C 
                 O 
                 O 
                 O 
                 C 
                 O 
                 O 
                 O 
                 C 
                 O 
                 O 
               
               
                 voltage 
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 Set output  
                 O 
                 O 
                 C 
                 O 
                 O 
                 O 
                 C 
                 O 
                 O 
                 O 
                 C 
                 O 
               
               
                 voltage 
               
               
                   
               
             
          
         
       
     
     Exemplary Calibration and Conversion Processes 
       FIG. 8  is a flow diagram of an exemplary calibration process  800  using an integrating DAC architecture. The process  800  can be operated independently in multiple branches of the integrating DAC architecture  100 . 
     In some implementations, the process  800  begins by removing capacitor voltage and resetting a digital counter ( 802 ). For example, the capacitor voltage can be removed by shorting the capacitor to ground, as described in reference to  FIG. 2 . The current source and an analog comparator are connected to the capacitor ( 804 ). The digital counter is started ( 806 ). 
     After starting the digital counter ( 806 ), the current source charges the capacitor ( 808 ) until the voltage over the capacitor is about equal to a reference voltage or differs by a threshold amount. For example, the reference voltage and the capacitor can be input into the analog comparator that is configured to trigger when the capacitor voltage is about equal to the reference voltage. The trigger can be used to stop the digital counter. The count of the digital counter is the number of clock cycles completed when the comparator triggers. 
     When the analog comparator triggers ( 810 ), a mathematical relationship is established between the capacitor voltage at the time of the trigger and a digital value based on the number of cycles counted by the digital counter ( 812 ). 
       FIG. 9  is a flow diagram of an exemplary conversion process  900  using an integrating DAC architecture. In some implementations, the process  900  begins by disconnecting the current source and analog comparator from the capacitor ( 902 ). The voltage over the capacitor is removed ( 904 ). The current source is re-connected to the capacitor ( 906 ). The digital counter is started ( 908 ). The current source charges the capacitor ( 910 ). The charging continues until a target analog voltage is reached ( 912 ). The output voltage of the DAC is set to the capacitor voltage ( 914 ). For example, a unity gain buffer can be connected to the capacitor to hold the analog voltage at the output of the DAC, as described in reference to  FIG. 6 . 
     While this document contains many specific implementation details, these should not be construed as limitations on the scope what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.

Technology Category: 5