Patent Document

BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to power electronics, and more particularly to a method and apparatus of a unified solution for bridgeless power factor controllers and grid connected inverters. 
         [0003]    2. Background Information 
         [0004]    Conventionally, the bridgeless power factor controllers and the grid connected inverters are controlled with different approaches. In both applications, it is essential to regulate the dc voltage to a constant and to control the ac side current to be in phase with the ac side voltage. The difference in the two applications is the direction of power, in the power factor controllers, the power direction is from the ac side to the dc side. In the inverters, the power direction is from the dc side to the ac side. In grid connected inverters, the control often involves DSP or microcontrollers. Complex algorithms have been developed to control the ac current and the dc voltage. It is preferred to have a unified, easy-to-use control solution which works for both power factor controller and grid connected inverter. In this way, the development cycle for both applications can be reduced. It is also desired to have a control solution which leads to better ac current waveform, less power dissipation, and higher reliability. The disclosed invention provides a solution to all those requirements. 
       SUMMARY OF THE INVENTION 
       [0005]    The embodiments of the present invention are directed to the general method and the implementation of the unified controller for both bridgeless power factor controllers and grid connected inverters. The control method involves two steps. The first step is to derive the ac side current reference from the ac side voltage and the dc side voltage. The second step is to regulate the ac side current to the current reference with minimal response time. The first step is based on the mathematical relationships between the ac side voltage, current, and the dc side voltage. It can be implemented with either hardware or software. The hardware implementation example has been provided, mainly based on the sample based controller. The software flow chart has also been provided. The second step may be implemented with all current mode full bridge controllers. In the present invention, a modified hysteretic switching pattern is disclosed. The disclosed switching pattern can minimize the switching event, avoid the usage of deadtime without the risk of shoot-through. 
     
    
     
       BRIEF DESCRIPTION OF FIGURES 
         [0006]      FIG. 1  is the general topology of single phase voltage source converter; 
           [0007]      FIG. 2  shows the waveforms of ac side voltage and current and dc side voltage; 
           [0008]      FIG. 3  is the control diagram of deriving ac current reference Iacref; 
           [0009]      FIG. 4  is the block diagram showing the hardware implementation of ‘Sample Based Controller’ block in  FIG. 3 ; 
           [0010]      FIG. 5  is the software flow chart of ‘Sampled Based Controller’ block in  FIG. 3 ; 
           [0011]      FIG. 6  is the conventional hysteretic switching pattern for single phase converters; 
           [0012]      FIG. 7  shows the disclosed switching pattern for power flow controller during positive half cycle of the ac voltage; 
           [0013]      FIG. 8  shows the disclosed switching pattern for power flow controller during negative half cycle of the ac voltage; 
           [0014]      FIG. 9  shows the disclosed switching pattern for grid connected inverter during positive half cycle of the ac voltage; 
           [0015]      FIG. 10  shows the disclosed switching pattern for grid connected inverter during negative half cycle of the ac voltage; 
           [0016]      FIG. 11  shows an alternate disclosed switching pattern for power flow controller during positive half cycle of the ac voltage; 
           [0017]      FIG. 12  shows an alternate disclosed switching pattern for power flow controller during negative half cycle of the ac voltage; 
           [0018]      FIG. 13  shows an alternate disclosed switching pattern for grid connected inverter during positive half cycle of the ac voltage; 
           [0019]      FIG. 14  shows an alternate disclosed switching pattern for grid connected inverter during negative half cycle of the ac voltage; 
           [0020]      FIG. 15  is the block diagram of the implementation of the disclosed switching pattern; 
           [0021]      FIG. 16  is the complete IC block diagram for general bridgeless PFC circuit and/or grid connected inverter controller 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    Both the bridgeless power factor controller and the grid connected inverter are converters connected to the power grid.  FIG. 1  shows the general topology of the converter. S 1 , S 2 , S 3 , and S 4  are general power semiconductors. Without losing generosity, they are drawn as ideal switches with anti-paralleled diodes. They can be MOSFET, or IGBT, or diode, whichever applicable. The ac source Vac is the voltage source with a stable RMS voltage level and a fixed frequency. Lac  1  and Lac 2  are the interface inductors. C is the dc side bulk capacitor. The dc side voltage Vdc is to be regulated. In either power factor controller or inverter. Vdc must be regulated to a constant value. The ac side current must be a sinusoidal waveform with the same phase angle as the ac voltage. The only difference is that the current sense polarity of a power factor controller is the reverse of an inverter. In the following description, the reversal of the polarity is not explicitly emphasized. It is implied that whenever a power factor controller is mentioned, the current polarity is defined as positive if the current flows from the ac side to the dc side; and whenever an inverter is mentioned, the current polarity is defined as positive if the current flows from the dc side to the ac side. 
         [0023]    The control of the general converter as shown in  FIG. 1  includes two steps. The first step is to find out the ac side current reference, A ‘Sample Based Controller’ is disclosed as an effective and easy-to-implement controller. The second step is to find a way to let the actual ac current follow the current reference as quickly as possible, A new current mode switching pattern is disclosed to improve the waveform and reduce the losses. 
       First Step: Find the ac Side Current Reference—‘Sample Based Controller’ 
       [0024]    Since the ac side current has to be in phase with the ac voltage, it is straightforward to make the ac current reference to be proportional to the ac voltage. The difficult part is how to derive the proportion coefficient, which determines the magnitude of the current. The magnitude of the current determines the amount of power being delivered. So the coefficient is supposed to be derived from the power requirement. In voltage source converter, the variation in the dc side voltage (Vdc in  FIG. 1 ) reflects the relationship between ac side power and dc side power. 
         [0025]    Assume the ac side voltage being 
         [0000]        V   sc ( t )=√{square root over (2)} V   rms  sin(ω t )  (1) 
         [0000]    Where Vac is the ac side voltage as shown in  FIG. 1 ;
 
Vrms is the RMS voltage of Vac;
 
ω=2πf, f is the frequency of the ac side voltage; and
 
t is the time.
 
         [0026]    In steady state operation of the power factor controller, the current direction is from the ac side to the dc side, with the same phase angle of the ac voltage. Assume the RMS value of the current being Irms, so 
         [0000]        I   ac ( t )=√{square root over (2)} I   rms  sin(ω t )  (2) 
         [0000]    Where Iac is the ac side current as shown in  FIG. 1 , with the direction from the ac side to the dc side. 
         [0027]    Assume under steady state, the dc side voltage is Vdc and dc side current is Idc, as shown in  FIG. 1 . Neglect the losses in the semiconductors, the inductor, and the wiring. The following set of power balance equations can be written. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
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         [0000]    Where Pac(t) is the ac side instantaneous power; Pdc is the dc side power, which is a constant; El(t) is the total energy stored in the inductors Lac 1  and Lac 2 ; Ec(t) is the energy stored in the capacitor C; Lac 1 , Lac 2 , and C are the inductors and the dc side capacitor in  FIG. 1 . 
         [0028]    From Equations (1)˜(7), the dc side voltage can be derived as 
         [0000]    
       
         
           
             
               
                 
                   
                     
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         [0000]    Where: Vdc 0  is the initial value of Vdc 
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         [0029]    Equation (8) shows that
       when ΔP=0, Vdc 0  is the rms value of Vdc.   when ΔP=0, Vdc(t) varies periodically at double of the line frequency.   when ΔP&gt;0, Vdc(t) will ramp up   when ΔP&gt;0, Vdc(t) will ramp down   In practical, Q 1 &lt;&lt;Pdc. So when ΔP=0, Vdc(t) reaches Vdc 0  almost at the same time when the ac side voltage reaches zero.       
 
         [0035]      FIG. 2(   a ) shows the waveforms of the ac side voltage and current;  FIG. 2(   b ), ( c ) and ( d ) show the dc side voltage waveform when ΔP=0, ΔP&gt;0 and ΔP&lt;0, respectively. The trend lines are drawn by connecting Vdc(t) only at the moments of ac voltage zero-crossing points. 
         [0036]    The derivation of the ac side current reference is based on the above analysis and the results shown in  FIG. 2 . The control diagram is shown in  FIG. 3 . The current reference Iacref is the product of the ac side voltage and a coefficient k. The coefficient k is derived from ΔVdc, which is the difference between the dc voltage reference and the actual dc voltage. The key point is that k is updated only at the zero crossing points of the ac input voltage. The controller which derives k is called ‘Sample Based Controller’, because it updates k once every half cycle. 
         [0037]    The ‘Sample Based Controller’ block in  FIG. 3  can be implemented either in hardware or in software.  FIG. 4  shows a hardware implementation example. 
         [0038]    In  FIG. 4 , the ‘Zero-crossing of Vac’ signal is from the ‘Zero-crossing Detector’ block in  FIG. 3 . It is a square waveform. Both rising and falling edges indicate a zero-crossing point of the ac voltage. The ‘Signal Conditioning’ block in  FIG. 4  transforms the waveform into a pulsed logic signal. The signal is normally at low level. The rising and/or falling edges of the zero-crossing signal will trigger the logic signal to be high level for a short period of time, which is enough to activate the downstream sample/hold circuit. The pulse duration is in the order of micro-seconds. 
         [0039]    ‘Sample/Hold  1 ’ and ‘Sample/Hold  2 ’ blocks are used to get the new ΔVdc value and to keep the last ΔVdc value. It is important to have the ‘Delay  1 ’ block, so that the last ΔVdc value can be reliably sampled through ‘Sample/Hold  2 ’ block, to become ‘ΔVdc,old’ signal. So the timing of ‘Delay  1 ’ block should be designed to make sure that the starting of the sample period of ‘Sample/Hold  1 ’ is after the completion of the sample period of ‘Sample/Hold  2 ’. 
         [0040]    K P , K D  and K I  are gain blocks. This gives the options of using any one or any combinations of P, I, or D controller. ‘ΔVde,new’ is the present difference between the dc voltage reference and the actual dc voltage. This signal, is fed to gain block K P  directly for proportional controller output. The summing block ‘SUM 1 ’ takes ‘ΔVdc,new’ and ‘ΔVdc.old’ as inputs, with ‘Δdc,new’ being positive, and ‘ΔVdc,old’ being negative. The result is fed to gain block K D  for differential controller output. It is important to have delay block ‘Delay  2 ’ and sample/hold block ‘Sample/Hold  3 ’ for a functional integrator. ‘Sample/Hold  3 ’ is used as a memory of the integration result from the last time. The zero-crossing signal will trigger ‘Sample/Hold  3 ’ block to feed the old integration value to one input of the summing block ‘SUM 2 ’. The other input of ‘SUM 2 ’ block is ‘ΔVdc,new’, so the output of ‘SUM 2 ’ is the new integration result. The ‘Delay  2 ’ block is important to prevent the output, of ‘Sample/Hold  3 ’ block from changing. The timing of the delay block is a little longer than the completion of sample period of ‘Sample/Bold  3 ’ block. In this way, the output of ‘Delay  2 ’ block will remain unchanged for the rest of the half cycle, until the next zero-crossing of the ac voltage. Finally, the output is the coefficient k, which is the sum of P, I and D controllers. Since the output is updated once every half cycle, it is actually a discrete PID controller with sample time being half of the line cycle. 
         [0041]    In  FIGS. 3 and 4 , all functional blocks are simple analog circuits.  FIGS. 3 and 4  form the block diagram of a complete integrated circuit. The circuit can greatly reduce the development cycle of the system, improve the reliability, and lower the system cost. 
         [0042]    The ‘Sample Based Controller’ block in  FIG. 3  can also be implemented in software.  FIG. 5  shows a software flowchart example. 
         [0043]    In the initialization part, the gain values of K P , K D  and K I  are given. All the inputs and outputs are cleared to 0. There should be software limits for the integrator output I and the overall output k. Set both edges of zero-crossing signal to be interruptable. Once a zero-crossing event happens, the interrupt part of the software is executed. In the interrupt software, the outputs of P, I and D controllers are calculated separately and then added up together to get the overall output k. With this method, only a low profile microcontroller is required, due to the low memory requirement, short execution time, and low interrupt frequency. 
       Second Step: A New Current Mode Switching Pattern 
       [0044]    The basis of the new switching pattern is the hysteretic control, in the conventional hysteretic switching pattern, the switches are controlled in pairs.  FIG. 5  shows the current flow of an inverter during positive half cycle of the ac voltage. Refer to  FIG. 1 , S 1  and S 4  are always switched on and off at the same time; S 2  and S 3  are switched on and off at the same time. Whenever S 1  and S 4  are on, S 2  and S 3  must be off and vice versa. The logic is simple. However, there are two main disadvantages in this pattern. Firstly, a deadtime has to be inserted during the commutation between S 1  and S 2 , and also between S 3  and S 4 , to avoid the risk of shoot-through. Secondly, all the switches are commutated once in each switching cycle, which is not necessary and increases the losses. 
         [0045]    The idea of the disclosed switching pattern is to reduce the number of switching events. In each half line cycle, only one switch is in PWM mode for both PFC circuit and the inverter. 
         [0046]    The current flow for positive and negative half cycles of one switching pattern example for bridgeless PFC is shown in  FIG. 7  and  FIG. 8 , respectively. For a bridgeless PFC circuit, there are two diode and two controllable switches. In the positive half cycle, S 2  is in PWM mode and S 4  is kept off. In the negative half cycle, S 2  is kept off and S 4  is in PWM mode. Let a logical variable H represent the sign of the ac side voltage, i.e., 
         [0000]    H=0 when the ac side voltage Vac&lt;0;
 
H=1 when the ac side voltage Vac&gt;=0.
 
         [0047]    Define a hysteretic band ΔI (ΔI&gt;0). Let a logical variable S represent the relationship between the actual current and the current reference as follows: 
         [0000]    S=0 when Iac&gt;Iacref+ΔI
 
S= 1 when Iac&lt;Iacref−ΔI
 
S is not changed when Iac is between (Iacref−ΔI) and (Iacref+ΔI). According to  FIG. 7  and  FIG. 8 , the switching logic equations of the switches can be written as;
 
         [0000]        S   2 = H·S   (9) 
         [0000]        S   4   =  H ·  S     (10) 
         [0000]    Where  H  and  S  are the logic inverse of H and S, respectively. 
         [0048]    The current flow for positive and negative half cycles of one switching pattern example for the inverter is shown in  FIG. 9  and  FIG. 10 , respectively. For an inverter, there has to be four controllable switches. Note  FIGS. 9 and 10  have the same current path as in  FIGS. 7 and 8 , except; the reversal in the direction. In the positive half cycle, S 1  is in PWM mode, S 2  and S 3  are kept off, and S 4  is kept on. In the negative half cycle, S 1  is kept off, S 2  is kept on, S 3  is in PWM mode, and S 4  is kept off. The switching logic equations are: 
         [0000]        S   1 = H·S   (11) 
         [0000]      S 2 =  H   (12) 
         [0000]        S   3 =   H ·  S     (13) 
         [0000]      S 4 =H  (14) 
         [0049]    This method can be recombined to get up to four different switching patterns, due to the symmetric nature of the converter. Another example is shown in  FIG. 11˜14  for another kind of current flow. For the power factor controller, instead of using S 1  and S 3  to be diodes, in this example, S 1  and S 2  are diode. For the inverter, instead of doing PWM on S 1  and S 3 , in this example, S 3  and S 4  are in PWM mode. The resulting switching logic equations for the power factor controller are: 
         [0000]        S   3 = H·S   (15) 
         [0000]        S   4 =   H ·  S     (16) 
         [0050]    The resulting switching logic equations for the inverter are; 
         [0000]      S 1 =H  (17) 
         [0000]      S 2 =  H   (18) 
         [0000]        S   3 =   H ·  S     (19) 
         [0000]        S   4 = H·S   (20) 
         [0051]    Other combinations in power factor controllers include choosing S 3  and S 4  as diodes, or S 2  and S 4  as diodes. 
         [0052]    When S 3  and S 4  are diodes in power factor controllers, the switching logic equations are: 
         [0000]        S   1 =   H ·  S     (21) 
         [0000]        S   2 = H·S   (22) 
         [0053]    The corresponding switching logic equations for the inverter with the same current path are: 
         [0000]        S   1 = H·S   (23) 
         [0000]        S   2 =   H ·  S     (24) 
         [0000]      S 3 =  H   (25) 
         [0000]      S 4 =H  (26) 
         [0054]    When S 2  and S 4  are diodes in power factor controllers, the switching logic equations are: 
         [0000]        S   1 =   H ·  S     (27) 
         [0000]        S   3 = H·S   (28) 
         [0055]    The corresponding switching logic equations for the inverter with the same current path are: 
         [0000]      S 1 =H  (29) 
         [0000]        S   2 =   H ·  S     (30) 
         [0000]      S 3 =  H   (31) 
         [0000]        S   4 = H·S   (32) 
         [0056]    The switching pattern is based on hysteresis comparison and simple logics, so it can be integrated into one integrated circuit. One implementation example is shown in  FIG. 15 . The inputs to the circuit include the ac side voltage Vac, the ac current reference Iacref which is derived from the first step, the measured ac current Iac, and the optional external setting ‘Hysteresis Band Setting’. The outputs are the switching signals. Since there are so many combinations, the outputs are designed to be suitable for ail combinations. For power factor controllers, the output ‘H’ and ‘  H ’ are not used. 
         [0057]    Under this kind of switching pattern, for the bridgeless power factor controller, each controllable switch is in PWM mode for half cycle and in fully on mode for the other half cycle. For the grid connected inverter, one pair of the switches are switched at line frequency only. The other pair of the switches are in PWM mode for half cycle and in off mode for the other half cycle. All unnecessary switching events have been removed. This feature reduces the gate drive loss, which is a considerable reduction in the control power dissipation. There is no risk of shoot-through, so no deadtime is required. This is an important benefit, it not only improves the waveform by removing the distortion caused by the deadtime, but also improves the reliability. 
         [0058]    Finally, the two steps can be combined into one integrated circuit, as shown in  FIG. 16 .  FIG. 16(   a ) shows the top level block, diagram which is a combination of  FIG. 3  and  FIG. 15 .  FIG. 16(   b ) shows the detail implementation of the ‘Sample Based Controller’ block, which is the same as in  FIG. 4 . 
         [0059]    While exemplary embodiments described hereinabove, it should be recognized that these embodiments are provided for illustration and are not intended to be limitative. Any modifications and variations, which do not depart from the spirit and scope of the invention, are intended to be covered herein.

Technology Category: 4