Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a current sensing circuit and, more particularly, to a current sensing circuit for detecting a current flowing through a high-voltage/large-current power switch. 
   2. Description of the Related Art 
   For a synchronous switching DC/DC voltage regulator, an inductor current needs to be detected in magnitude and variation if a current-mode topology is configured as a mechanism of feedback control. Conventionally, a resistor is connected in series to the inductor and then a potential difference is caused across the resistor by the inductor current, which will provide the appropriate information regarding the magnitude and variation of the inductor current. However, the prior art must utilize the series-connected resistor with a result of the I 2 R power consumption. In an application of a large inductor current, the series-connected resistor must occupy a large surface area for satisfying the required current flow capacity under limitations determined by the nature of the semiconductor processing and materials, setting up a barrier to the development of a finer semiconductor chip. Moreover, an operational amplifier is necessary for retrieving the potential difference across the series-connected resistor, making the circuitry more complicated and reducing the operation speed. 
     FIG. 1  is a circuit block diagram showing a synchronous switching DC/DC voltage regulator provided with a conventional current sensing circuit. As shown in the figure, a high-side switch HS and a low-side switch LS are coupled in series between an input voltage source V in  and a ground potential. An inductor L has one terminal coupled to a node A between the high-side switch HS and the low-side switch LS, and the other terminal serving as an output terminal for supplying a regulated output voltage V out . The output terminal may also be provided with an output capacitor C o  for filtering ripples of the output voltage V out . The high-side switch HS and the low-side switch LS are controlled by a high-side drive signal HD and a low-side drive signal LD, respectively, from a current-mode synchronous-switch control circuit  11 . In the synchronous switching DC/DC voltage regulator, the high-side switch HS and the low-side switch LS are operated out of phase. When the high-side switch HS is turned ON and the low-side switch is turned OFF, the input voltage source V in  supplies energy to the inductor L, causing the inductor current I L  to gradually increase. On the other hand, when the high-side switch HS is turned OFF and the low-side switch LS is turned ON, the energy stored in the inductor L is delivered to the output terminal as the output voltage V out , causing the inductor current I L  to gradually decrease. 
   Therefore, in a case that the high-side switch HS is implemented by a PMOS transistor and the low-side switch LS is implemented by an NMOS transistor, the high-side drive signal HD and the low-side drive signal LD are the pulse trains with the same phase. In a case that both of the high-side switch HS and the low-side switch LS are implemented by NMOS transistors, the high-side drive signal HD and the low-side drive signal LD are the pulse trains with 180 degrees out of phase therebetween. In addition, the high-side drive signal HD and the low-side drive signal LD are designed as non-overlapping pulse trains with a turn-on delay for preventing the high-side switch HS and the low-side switch LS from being simultaneously turned ON to erroneously short-circuit the input voltage source V in  and the ground potential. 
   For the current-mode feedback control mechanism, a resistor R s  is coupled in series to the inductor L for detecting the magnitude and variation of the inductor current I L . An operational amplifier  12  retrieves a potential difference across the series-connected resistor R s  caused by the inductor current I L , for generating a detection voltage V s  representative of the inductor current I L . Subsequently, the detection voltage V s  generated by the operational amplifier  12  is fed back to the current-mode synchronous-switch control circuit  11  for performing the current-mode control. 
   The series-connected resistor R s  is necessary in the prior art for detecting the inductor current I L , resulting in the I L   2 R s  power consumption. In an application where the inductor current I L  should be made large, the series-connected resistor R s  must occupy a large surface area for satisfying the required current flow capacity under limitations determined by the nature of the semiconductor processing and materials. Moreover, the operational amplifier  12  for retrieving the potential difference across the series-connected resistor R s  makes the circuitry more complicated and reduces the operation speed. 
   SUMMARY OF THE INVENTION 
   In view of the above-mentioned problems, an object of the present invention is to provide a current sensing circuit capable of reducing the power consumption for detecting a current. 
   Another object of the present invention is to provide a current sensing circuit capable of being constructed by circuit components with a fine size. 
   Still another object of the present invention is to provide a current sensing circuit capable of enhancing the operational speed of the current detection. 
   The present invention provides a current sensing circuit to replace the conventional series-connected resistor and the operational amplifier. The inventors firstly observe that a current flowing through the high-side switch when the high-side switch is turned ON is identical to the inductor current, and the current flowing through the high-side switch produces a potential difference across a high-side switch-channel resistance, i.e. a drain-source conductive resistance R ds(ON) . Therefore, the current sensing circuit according to the present invention directly detects the potential difference across the high-side switch-channel resistance, and then performs inventive voltage/current transformation to obtain a detection current having a linear relationship with the inductor current. The current sensing circuit according to the present invention overcomes the prior art disadvantages regarding the power consumption, size, and operation speed since none of the conventional series-connected resistor and the operational amplifier is needed. Furthermore, the current detection circuit according to the present invention is operated in synchronization with the high-side switch for saving the current-detecting power consumption. 
   According to one aspect of the present invention, a current sensing circuit includes a voltage detection unit, a reference current generation unit, and a transfer unit. The voltage detection unit generates a detection voltage signal representative of a potential difference caused by a current to be detected. The reference current generation unit generates a first reference current and a second reference current. A first linear relationship is established between the first and the second reference currents. The transfer unit is coupled between the voltage detection unit and the reference current generation unit. In response to the detection voltage signal and the first reference current, the transfer unit determines a first operation voltage. In response to the first operation voltage and the second reference current, the transfer unit determines a second operation voltage and a transfer current. The second operation voltage is substantially equal to the first operation voltage. A detection current signal is generated by subtracting at least the second reference current from the transfer current. A second linear relationship is established between the detection current signal and the current to be detected. 
   Preferably, the current sensing circuit further includes a voltage feedback control unit, coupled to the transfer unit, for reflecting a variation of the first operation voltage on the second operation voltage. 
   Preferably, the current sensing circuit further includes a current level shift unit, coupled to the transfer unit or the voltage feedback control unit, for adjusting a direct current level of the detection current signal. 
   According to another aspect of the present invention, a method of sensing a current includes the following steps. A detection voltage signal is generated to be representative of a potential difference caused by a current to be detected. A first reference current is generated. A second reference current is generated such that a first linear relationship is established between the first and the second reference currents. A first operation voltage is determined in response to the detection voltage signal and the first reference current. A second operation voltage and a transfer current are determined in response to the first operation voltage and the second reference current such that the second operation voltage is substantially equal to the first operation voltage. A detection current signal is generated by subtracting at least the second reference current from the transfer current such that a second linear relationship is established between the detection current signal and the current to be detected. 
   Preferably, the method of sensing the current further includes a step of reflecting a variation of the first operation voltage on the second operation voltage through a voltage feedback control. 
   Preferably, the method of sensing the current further includes a step of adjusting a direct current level of the detection current signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein: 
       FIG. 1  is a circuit block diagram showing a synchronous switching DC/DC voltage regulator provided with a conventional current sensing circuit; 
       FIG. 2  is a circuit block diagram showing a synchronous switching DC/DC voltage regulator provided with a current sensing circuit according to the present invention; 
       FIG. 3  is a detailed circuit diagram showing a current sensing circuit of a first embodiment according to the present invention; 
       FIG. 4  is a detailed circuit diagram showing a current sensing circuit of a second embodiment according to the present invention; 
       FIG. 5  is a detailed circuit diagram showing a current sensing circuit of a third embodiment according to the present invention; and 
       FIG. 6  is a detailed circuit diagram showing a current sensing circuit of a fourth embodiment according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The preferred embodiments according to the present invention will be described in detail with reference to the drawings. 
     FIG. 2  is a circuit block diagram showing a synchronous switching DC/DC voltage regulator provided with a current sensing circuit  13  according to the present invention. Referring to  FIG. 2 , a high-side switch HS is connected between an input voltage source Vin and a node A while a low-side switch LS is connected between the node A and a ground potential. An inductor L is connected between the node A and an output terminal. The inventors firstly observe that a channel current IHS flowing through the high-side switch HS when the high-side switch HS is turned ON is identical to an inductor current IL, and the high-side switch-channel current I HS  produces a potential difference across the high-side switch-channel resistance RHS:
   V   in   −V   sen   =I   HS   ·R   HS    
   Therefore, the current sensing circuit  13  according to the present invention directly detects the potential difference (V in −V sen ) across the high-side switch-channel resistance R HS , and then performs inventive voltage/current transformation to obtain a detection current signal I sen  having a linear relationship with the inductor current I L . The current sensing circuit  13  according to the present invention overcomes the prior art disadvantages regarding the power consumption, size, and operation speed since none of the series-connected resistor R s  and the operational amplifier  12  is needed. Furthermore, the current detection circuit  13  according to the present invention activates to detect the current when the high-side switch HS is turned ON and stops detecting when the high-side switch HS is turned OFF, for saving the current-detecting power consumption. 
     FIG. 3  is a detailed circuit diagram showing a current sensing circuit  13 - 1  of a first embodiment according to the present invention. The current sensing circuit  13 - 1  includes a voltage detection unit (P 1 , P 2 ), a reference current generation unit (I bias , N 1 , N 2 , N 3 ), and a transfer unit (P 3 , P 4 , P 5 , P 6 ). 
   More specifically, the voltage detection unit is used for detecting the potential difference across the high-side switch-channel resistance R HS . Assumed that the high-side switch-channel resistance is R HS  and the channel current flowing through the high-side switch HS is I HS , the potential difference V ds  between the drain and source of the high-side switch HS may be expressed as:
 
 V   ds   =V   in   −V   sen   =I   HS   ·R   HS  
 
   In the embodiment shown in  FIG. 3 , the voltage detection unit is implemented by PMOS transistors P 1  and P 2 . The transistor P 1  has a source connected to the input voltage source V in , a gate connected to the ground potential, and a drain connected to a source (i.e. node B) of the transistor P 2 . The transistor P 2  has a gate connected to a gate of the high-side switch HS, and a drain connected to a drain of the high-side switch HS. When a high-side drive signal HD turns ON the high-side switch HS, both of the transistors P 1  and P 2  are operated in the triode region and therefore become equivalent to channel resistances. Assumed that the transistor P 1  has a channel resistance R P1  and the transistor P 2  has a channel resistance R P2 , the voltage V B  at the node B may be expressed as a division of the potential difference since the series-coupled transistors P 1  and P 2  form a resistive voltage divider: 
   
     
       
         
           
             V 
             B 
           
           = 
           
             
               
                 
                   R 
                   P2 
                 
                 · 
                 
                   V 
                   in 
                 
               
               + 
               
                 
                   R 
                   P1 
                 
                 · 
                 
                   V 
                   sen 
                 
               
             
             
               
                 R 
                 P1 
               
               + 
               
                 R 
                 P2 
               
             
           
         
       
     
   
   For preventing the current sensing circuit  13 - 1  according to the present invention from influencing the original characteristics of the circuit to be detected, the voltage detection unit is designed to have a high impedance. Consequently, the channel resistances R P1  and R P2  of the transistors P 1  and P 2  are designed to be extremely larger than the channel resistance R HS  of the high-side switch HS:
 
 R   P1   +R   P2   &gt;&gt;R   HS  
 
   In this case, the current flowing through the transistors P 1  and P 2  can be neglected in comparison with the high-side switch-channel current I HS . As a result, during the ON period of the high-side switch HS, the high-side switch-channel current I HS  appropriately indicates the inductor current I L  even under the detection of the current detection circuit  13 - 1 :
 
I L ≈I HS  
 
   In other words, although the current sensing circuit  13 - 1  according to the present invention detects in practice the high-side switch-channel current I HS , it may be said in circuit application that the inductor current I L  is detected. 
   The reference current generation unit is used for supplying a first reference current I r1  and a second reference current I r2  such that a linear relationship is established between the first reference current I r1  and the second reference current I r2 :
 
 I   r1   =K·I   r2  
 
   where K is a proportional constant larger than or equal to 1. In the embodiment shown in  FIG. 3 , the reference current generation unit includes a bias current source I bias  and three NMOS transistors N 1 , N 2 , and N 3 . The transistor N 1  has a drain connected to the bias current source I bias , a gate connected to its own drain, and a source connected to the ground potential. The transistor N 2  has a gate connected to the gate of the transistor N 1 , a source connected to the ground potential, and a drain for allowing the first reference current I r1  to sink or flow. The transistor N 3  has a gate connected to the gate of the transistor N 1 , a source connected to the ground potential, and a drain for allowing the second reference current I r2  to sink or flow. The transistors N 1 , N 2 , and N 3  together form a multiple-output-stage current mirror having the transistors N 2  and N 3  as independent current output stages. If the transistors N 2  and N 3  are identically manufactured except the width-to-length ratio of the gate is designed under the following condition:
 
( W/L ) N2   =K· ( W/L ) N3  
 
then the first reference current I r1  and the second reference current I r2  can effectively establish the desired linear relationship:
 
   
     
       
         
           
             
               I 
               r1 
             
             
               I 
               r2 
             
           
           = 
           
             
               
                 
                   ( 
                   
                     W 
                     / 
                     L 
                   
                   ) 
                 
                 N2 
               
               
                 
                   ( 
                   
                     W 
                     / 
                     L 
                   
                   ) 
                 
                 N3 
               
             
             = 
             K 
           
         
       
     
   
   The transfer unit is coupled between the voltage detection unit and the reference current generation unit for transferring the detection voltage signal V B  generated from the voltage detection unit into the desired detection current signal I sen  in accordance with the first and second reference currents I r1  and I r2  generated from the reference current generation unit. In the embodiment shown in  FIG. 3 , the transfer unit includes four PMOS transistors P 3 , P 4 , P 5 , and P 6 . The transistor P 3  has a source connected to the node B, a gate connected to the ground potential, and a drain connected to a node C. Consequently, the transistor P 3  is operated in the triode region as an equivalent channel resistance R P3 . The transistor P 4  has a source connected to the input voltage source V in , a gate connected to the ground potential, and a drain connected to a node D. Consequently, the transistor P 4  is operated in the triode region as an equivalent channel resistance R P4 . Moreover, the transistor P 5  has a source connected to the node C while the transistor P 6  has a source connected to the node D. The transistors P 5  and P 6  have their gates connected together and the gate of the transistor P 6  is further connected to its own drain. Therefore, the transistors P 5  and P 6  form a current mirror. The transistor P 5  has a drain connected to the drain of the transistor N 2  for allowing the first reference current I r1  to flow through the transistors P 3  and P 5 . The transistor P 6  has a drain connected to the drain of the transistor N 3  for allowing the second reference current I r2  to flow through the transistor P 6 . 
   Since the linear relationship with the proportional constant K is established between the first and second reference currents I r1  and I r2 , the width-to-length ratios of the transistors P 5  and P 6  must be designed to satisfy the following condition:
 
( W/L ) P5   =K· ( W/L ) P6  
 
   for allowing the first and second reference currents I r1  and I r2  to smoothly flow through the transistors P 5  and P 6 , respectively, given that the transistors P 5  and P 6  are otherwise identically manufactured. 
   Because the first reference current I r1  also flows through the transistor P 3 , a voltage V C  at the node C may be expressed as: 
                   V   C     =       V   B     -       I   r1     ·     R   P3                     =       V   in     -     (       V   in     -     V   B       )     -       I   r1     ·     R   P3                     =       V   in     -         R   P1         R   P1     +     R   P2         ·     (       V   in     -     V   sen       )       -       I   r1     ·     R   P3                     =       V   in     -         R   P1         R   P1     +     R   P2         ·     I   HS     ·     R   HS       -       I   r1     ·     R   P3                     
Now assumed that a transfer current I t  flows though the transistor P 4 , a voltage V D  at the node D may be expressed as:
   V   D   =V   in   −I   t   ·R   P4    
   As described above, because the transistors P 5  and P 6  are coupled as the current mirror and the first and second reference currents I r1  and I r2  correspondingly follow the width-to-length ratios (W/L) P5  and (W/L) P6 , the gate-source voltage V GS(P5)  of the transistor P 5  is operated equal to the gate-source voltage V GS(P6)  of the transistor P 6 . In this case, since the gates of the transistors P 5  and P 6  are coupled together, the voltage at the source of the transistor P 5  (i.e. the voltage V C  at the node C) is equal to the voltage at the source of the transistor P 5  (i.e. the voltage V D  at the node D): 
             V   C     =         V   D     ⇒     
     ⁢       V   in     -         R   P1         R   P1     +     R   P2         ·     I   HS     ·     R   HS       -       I   r1     ·     R   P3           =         V   in     -       I   t     ·     R   P4         ⇒     
     ⁢             I   t     =       ⁢           R   P1         R   P4     ·     (       R   P1     +     R   P2       )         ·     I   HS     ·     R   HS       +         R   P3       R   P4       ·     I   r1                     =       ⁢           R   P1         R   P4     ·     (       R   P1     +     R   P2       )         ·     I   HS     ·     R   HS       +         R   P3       R   P4       ·   K   ·     I   r2                     ≡       ⁢       Ω   ·     I   HS       +     Φ   ·     I   r2                                 Ω   ≡         R   P1     ·     R   HS           R   P4     ·     (       R   P1     +     R   P2       )                     Φ   ≡         R   P3       R   P4       ·   K           
Therefore, the detection current signal I sen  output from the node D may be expressed as:
 
                   I   sen     =       I   t     -     I   r2                   =       Ω   ·     I   HS       +       (     Φ   -   1     )     ·     I   r2                     
Since the proportional constants Ω and Φ and the second reference current I r2  are predetermined parameters and characteristic during the circuit design procedure, the current sensing circuit  13 - 1  according to the present invention effectively outputs the detection current signal I sen  having the listed-above linear relationship with the high-side switch-channel current I HS . Since the high-side switch-channel current I HS  is substantially equal to the inductor current I L , the current sensing circuit  13 - 1  according to the present invention achieves a precise measurement of the inductor current I L .
 
   In one embodiment of the present invention, the channel resistances R P3  and R P4  of the transistors P 3  and P 4  may be designed with the same value, and the transistors P 5  and P 6  are also designed with the same width-to-length ratio such that the proportional constant K becomes equal to 1, thereby making the value of the proportional constant φ equal to 1. In this case, the detection current signal I sen  is further reduced to be directly in proportion to the high-side switch-channel current I HS :
 
 I   sen   =Ω·I   HS  
 
     FIG. 4  is a detailed circuit diagram showing a current sensing circuit  13 - 2  of a second embodiment according to the present invention. As seen by comparing with  FIGS. 3 and 4 , the second embodiment is different from the first embodiment in that the current sensing circuit  13 - 2  of the second embodiment is further provided with a voltage feedback control unit (P 7 ) for rapidly reflecting the variation of the detection voltage signal V B  in order to ensure a stable operation of the current sensing circuit  13 - 2  and a precise detection current signal I sen . 
   In the second embodiment shown in  FIG. 4 , the voltage feedback control unit includes a PMOS transistor P 7  having a gate connected to the drain of the transistor P 5 , a source connected to the source of the transistor P 6 , and a drain for outputting the desired detection current signal I sen . When the high-side switch-channel current I HS  increases (or decreases), the voltage V sen  at the node A decreases (or increases) such that a corresponding fall (or rise) happens to the detection voltage signal V B  at the node B. As a result, the voltage at the source of the transistor P 5  (i.e. the voltage V C  at the node C) and the voltage at the drain of the transistor P 5  simultaneously decrease (or increase) with the same magnitude. Through the feedback control provided by the transistor P 7 , the variation of the voltage at the drain of the transistor P 5  rapidly causes the same magnitude of variation to the voltage at the source of the transistor P 6  (i.e. the voltage V D  at the node D). Consequently, the voltage V D  at the node D rapidly reflects the variation of the voltage V C  at the node C, thereby maintaining the equality therebetween to ensure the stable operation of the current sensing circuit  13 - 2  and the precise detection current signal I sen . 
     FIG. 5  is a detailed circuit diagram showing a current sensing circuit  13 - 3  of a third embodiment according to the present invention. As seen by comparing with  FIGS. 4 and 5 , the third embodiment is different from the second embodiment in that the current sensing circuit  13 - 3  of the third embodiment is further provided with a current level shift unit (N 4 ) for adjusting a direct current level of the detection current signal I sen  so as to produce a predetermined current offset thereon for facilitating the circuit application or design. 
   In the third embodiment shown in  FIG. 5 , the current level shift unit includes an NMOS transistor N 4  having a gate connected to the gate of the transistor N 1 , a source connected to the ground potential and a drain connected to the drain of the transistor P 7  (i.e. node E) for allowing a shift current I a1  to sink or flow. Therefore, the detection current signal I sen  output from the node E has a direct current level adjusted in accordance with the shift current I a1 : 
                   I   sen     =       I   t     -     I   r2     -     I   a1                   =       Ω   ·     I   HS       +       (     Φ   -   1     )     ·     I   r2       -     I   a1                   
If the shift current I a1  is preset equal to (Φ−1)I r2 , the detection current signal I sen  is reduced to be directly in proportion to the high-side switch-channel current I HS :
   sen   =Ω·I   HS    
     FIG. 6  is a detailed circuit diagram showing a current sensing circuit  13 - 4  of a fourth embodiment according to the present invention. As seen by comparing with  FIGS. 4 and 6 , the fourth embodiment is different from the second embodiment in that the current sensing circuit  13 - 4  of the fourth embodiment is further provided with a current level shift unit (N 5 ) for adjusting a direct current level of the detection current signal I sen  so as to produce a predetermined current offset for facilitating the circuit application or design. 
   In the fourth embodiment shown in  FIG. 6 , the current level shift unit includes an NMOS transistor N 5  having a gate connected to the gate of the transistor N 1 , a source connected to the ground potential, and a drain connected to the source of the transistor P 7  (i.e. node D) for allowing a shift current I a2  to sink or flow. Therefore, the detection current signal I sen  output from the drain of the transistor P 7  has a direct current level adjusted in accordance with the shift current I a2 : 
                   I   sen     =       I   t     -     I   r2     -     I   a2                   =       Ω   ·     I   HS       +       (     Φ   -   1     )     ·     I   r2       -     I   a2                   
If the shift current I a2  is preset equal to (Φ−1)I r2 , the detection current signal I sen  is reduced to be directly in proportion to the high-side switch-channel current I HS :
   I   sen   =Ω·I   HS    
   To sum up, the current sensing circuit according to the present invention directly detects the potential difference across the high-side switch-channel resistance, and then performs the inventive voltage/current transformation to obtain the detection current signal having the linear relationship with the inductor current. The current sensing circuit according to the present invention overcomes the prior art disadvantages regarding the power consumption, size, and operation speed since none of the conventional series-connected resistor and the operational amplifier is needed. Furthermore, the current detection circuit according to the present invention is operated in synchronization with the high-side switch for saving the current-detecting power consumption. 
   While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.

Technology Category: 3