Patent Document

FIELD OF THE INVENTION 
     The invention relates to a semiconductor package, particularly relates to a package structure with a molded semiconductor chip and a fabrication method thereof 
     DESCRIPTION OF THE RELATED ART 
       FIG. 1  is a schematic diagram of a conventional semiconductor package. The bottom drain of a MOSFET chip  1  is attached on a bottom base of a cup-shaped lead frame  2  by conductive adhesive  4  with the edges of the MOSFET being spaced from the walls of the cup-shaped lead frame  2 . The lead frame  2  is made of metal alloy or other conductive material. The space between the edges of the MOSFET  1  and the walls in the lead frame  2  is filled with an insulating layer  5 . The lead frame  2  also includes two pins  6  located on two of its opposing edges at its top surface electrically connected to the drain on the bottom of the MOSFET chip  1  for electrical connection to the external device. 
     In addition, as shown in  FIG. 1 , a top surface  3  of the MOSFET  1  as indicated by plane A′ is sub-flush below the plane A of the top surfaces of the pins  6  of the lead frame  2 , thus the temperature cycling failures is reduce and the heat dissipation of the semiconductor package in  FIG. 1  is improved. However, strict alignment in mounting the semiconductor chip onto the lead frame is required to control the top surfaces of each electrode on a same plan thus increase the assembly cost. Further the semiconductor chip must maintain a certain thickness such that the chip will not deform during assembly process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of the prior art semiconductor device packaging structure; 
         FIG. 2  and  FIG. 3  are the schematic diagrams of the front and the back views of the packaging structure respectively of this invention; 
         FIG. 4  to  FIG. 12  are the schematic structural diagrams corresponding to various steps of a first fabrication method of the packaging structure in the invention; 
         FIG. 13  to  FIG. 21  are the schematic structural diagrams corresponding to various steps of a second fabrication method of the packaging structure in the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention. 
       FIG. 2  and  FIG. 3  are perspective top and bottom views respectively of a semiconductor package of the present invention. As shown in  FIG. 3 , a source pad  52 , a gate pad  51  and two drain pads  61 , which are separated from each other, are exposed on a bottom surface of the package, and a top source terminal  12 , a top gate terminal  11  and a bottom drain terminal  13  of the MOSFET  10  ( FIG. 4 ) are electrically connecting to the other external devices (such as another semiconductor chip or integrated circuit board and the like) by these pads respectively. Meanwhile, the bottom surface of a lead frame  40  ( FIG. 9 ) in connection with the bottom drain terminal  13  of the chip  10  is exposed on a top surface of the package ( FIG. 2 ) for improving the heat dissipation of the device. 
     Embodiment 1 
       FIG. 4  to  FIG. 12  illustrate a fabrication method of the semiconductor package according to a first embodiment of the present invention.  FIG. 4  is a perspective view of one of a plurality of semiconductor chips  10  formed on a top surface of a semiconductor wafer (not shown). In the embodiment as shown in  FIG. 4 , each chip  10  is a MOSFET chip including a top gate terminal  11  and top source terminal  12  separated from each other and formed on the top surface of the chip, and a bottom drain terminal  13  formed on the bottom surface of the chip. As shown in  FIG. 5 , conductive contact bodies  21  and  22 , such as metal balls or metal bumps, formed on the top gate terminal  11  and the top source terminal  12  of each chip  10  for electrically connecting with the external devices. Certain common materials in current technologies can be used for forming the contact bodies  21  and  22 , such as copper, tin, lead, and the likes. 
     As shown in  FIG. 6 , a first plastic package body  31  with a big enough thickness H is formed for covering the top surface of each chip  10  and completely encapsulating the contact bodies  21  and  22  on the top surface of the chip  10 . As shown in  FIG. 7 , the first plastic package body  31  is ground from its top surface to a smaller thickness h until the top surface of the contact bodies  21  and  22  is exposed. At this time, the top surfaces of the contact bodies  21  and  22  are flush with the top surface of the first plastic package body  31 . Alternatively, after the contact bodies  21  and  22  are exposed, the top surfaces of the first plastic package body  31  and the contact bodies  21  and  22  can be further ground until reaching a predetermined thickness. As shown in  FIG. 8 , the molded wafer or the chip  10  with an original semiconductor substrate thickness Y is ground from its bottom surface to a smaller thickness y, for example, the thickness y of the ground wafer may be 1 mil or thinner, which can be considered as a substrate-less level without the concern of mechanical deformation in following processes due to the mechanical support of the first plastic package body. At this stage, the molded wafer is singulated into a plurality of individual molded chips  10 , each of which includes a semiconductor chip, as shown in  FIG. 8 . The top surface of the chip is covered with the first plastic body while the sidewalls of the chip are exposed and flush with the sidewalls of the first plastic body. Alternatively, a metal deposition can be carried out on the bottom surface of the ground wafer before singulation. 
       FIG. 9  is a perspective view of a conductive lead frame  40  made of a metal, such as copper and the like or metal alloy material. The lead frame  40  includes a die paddle  41  and two contact parts  42  relatively connected to two opposite edges bent upward at the first side and the third side corresponding to the left side and the right side of the die paddle  41 , where the top surface of the two contact parts  42  is higher than the top surface of the die paddle  41 . In addition, the lead frame  40  also includes notches  43  at the bottom surface of four corners of the lead frame  40  formed by a half-etch process. 
     As shown in  FIG. 10 , the bottom surface of the molded chip  10  is attached on the top surface of the die paddle  41  by a conductive adhesive  70 . As such, the bottom drain terminal  13  of the molded chip  10  is directly electrically connected to the top surface of the die paddle  41  of the lead frame  40 , and therefore electrically connected to the two contact parts  42  through the die paddle  41 . The surface area of the die paddle  41  of the lead frame  40  needs to be larger than that of the molded chip  10 , therefore there is a space between the edge of the molded chip  10  and that of the die paddle  41 . 
     As shown in  FIG. 11 , a second plastic package body  32  is formed on the top surface of the lead frame  40  to cover the side surface of the molded chip  10 . The material of the second plastic package body  32  may be the same as that of the first plastic package body  31  or different. In this figure, the edge line of the molded chip  10  is only displayed for showing the position of the molded chip  10  in the package. Specifically, refer to  FIG. 11 , the space between the edges of the molded chip  10  and the edges of the dies paddle  41  is filled by the second plastic package body  32 . The second plastic package body  32  also covers the bottom surface of the contact parts  42 , the side surfaces of the second side and the fourth side of the lead frame  40  and fills the notches  43  with the contact bodies  21  and  22  at the top source terminal  12  and the top gate terminal  11  of the molded chip  10  being exposed outside of the second plastic package body  32 . The top surface and the side surface of the two contact parts  42  on the first side and the third side of the lead frame  40  are also exposed from the second plastic package body  32  for electrically connecting with the external devices. 
     In this packaging step, the top surface of the molded chip  10  is covered with an adhesive tape before forming the second plastic package body  32  to control the thickness of the second plastic package body  32  during packaging and to protect the top surface of the contact bodies  21  and  22  and the contact part  42  that need to expose after forming the second plastic package body  32 . After forming second plastic package body  32 , the adhesive tape is removed, and second plastic package body  32  at the top surface of the packaging structure is de-flashed or slightly ground to remove the residual packaging material, so that the top surface of the packaging structure is flat and the top surfaces of the contact bodies  21  and  22  and the contact part  42  are exposed from the second plastic package body  32 . At this time, the top surfaces of the contact bodies  21  and  22 , the contact part  42  and the second plastic package body  32  are preferably coplanar but not strictly required. 
     In addition, as shown in  FIG. 2 , the second plastic package body  32  covers the bottom surfaces of the two contact parts  42  of the lead frame  40 . The bottom surface of the die paddle  41  can be completely or partially exposed from the second plastic package body  32  by covering the bottom surface of the die paddle  41  with an adhesive tape before forming the second plastic package body  32  or grinding the bottom surface of the second plastic package body  32  after packaging. As such, the bottom surfaces of the die paddle  41  and the second plastic package body  32  are also coplanar. The exposed bottom surface of the die paddle  41  improves the heat dissipation of the devices or can be used for the electrical connection between the drain terminal  13  at the bottom of the chip  10  to the external devices. 
     Solderable metal pads are plated on the top surface of the packaging structure at the top surfaces of contact bodies  21  and  22  and the contact part  42  to re-pattern the package external connection between the corresponding terminal on the chip  10  and the external device. The location of the plated metal pads on the top surface of the packaging structure depends on the desired application of the device. In the example shown in  FIG. 12 , a metal pad  52  is plated on top of the contact bodies  22  on the two top source terminals  12  of the chip  10  and can be used as a source contact pad  52 . Similarly, a metal pad  51  is plated over the contact body  21  on the gate terminal  11  of the chip  10  and can be used as a gate contact pad  51 , and the metal pads  61  are plated on the contact parts  42  and can be used as a drain contact pads  61 , where the drain contact pads  61  extend to the edges of the first side and the third side of the lead frame. In addition, the gate contact pad  51  covers a portion of the top surface of the first and/or second plastic body and extends to the edge of the second side of the packaging structure but terminates far away from the edges of the first side and the third side of the lead frame, and the source contact pad  52  covers a portion of the top surface of the first and/or second plastic body and extends to the edge of the fourth side of the packaging structure but terminate far away from the edges of the first side and the third side of the lead frame, where the contact pads  51 ,  52  and  61  are electrically separated from each other. The plastic package body  32  surrounds four side surfaces of the molded chip  10  and extends to and covers the side surfaces of the second side and the fourth side of the lead frame  40 , and the gate contact pad  51  and the source contact pad  52  respectively covers parts of top surface of the plastic package body  32  and extends to the edges of the second side and the fourth side of the packaging structure beyond the corresponding edges of the lead frame while the contact pad  61  terminates at a distance away from both the edges of the second side and the fourth side of the packaging structure. 
     Embodiment 2 
       FIG. 13  to  FIG. 21  are perspective schematic diagrams showing a second fabrication method of the packaging structure of the invention. 
       FIG. 13  to  FIG. 15  are similar to  FIG. 4  to  FIG. 6 , in which a plurality of MOSFET chips are formed on a front surface of the wafer and the contact bodies  21  and  22  are formed on the top gate terminal  11  and the top source terminal  12  of each chip  10  respectively, then a first plastic package body  31  is formed with a big enough thickness H to cover the top surface of the chip  10  with contact bodies  21  and  22  being completely encapsulated. 
     In this process, as shown in  FIG. 16 , the top surface of the first plastic package body  31  is not ground to exposed the contact bodies  21  and  22 . The wafer or the chip  10  with an original semiconductor substrate thickness Y is ground from its bottom surface to a smaller thickness y, which can be considered as a substrate-less level. The thickness y of the ground wafer is 1 mil or thinner. And then, the wafer is cut into individual molded chips  10 , each of which includes a semiconductor chip with top surface of the chip covered by the first plastic package body while the sidewalls of the chip are exposed and flush with the sidewalls of the first plastic body, as shown in  FIG. 16 . Back metal deposition to the ground molded wafer bottom surface is optional before cutting the wafer. 
       FIG. 17  shows a lead frame similar as that shown in  FIG. 9 . As shown in  FIG. 18 , the bottom surface of the molded chip  10  is attached on the top surface of the die paddle  41  by a conductive adhesive  70 . As such, the bottom drain terminal  13  of the molded chip  10  is directly electrically connected to the external devices by the die paddle  41  and the contact part  42  of the lead frame  40 . 
     As shown in  FIG. 19 , a second plastic package body  32  is formed to cover the molded chip  10  and the lead frame  40 , including at least the side surface at the second side and fourth side of the lead frame and the bottom surface of the two contact parts  42 , where only the side surfaces of the two contact parts  42  and the bottom surface of the die paddle of the lead frame  40  are exposed. 
     As shown in  FIG. 20 , the top surface of the packaging structure is ground until the contact bodies  21  and  22  at the top gate terminal  11  and the top source terminal  12  on the chip  10  and the top surfaces of the two contact parts  42  on the lead frame  40  are exposed outside of the second plastic package body  32 . The grinding process also forces the top surfaces of the contact bodies  21  and  22  and contact parts  42  into coplanar without the strict alignment requirement in mounting the semiconductor chip of prior arts. 
     As shown in  FIG. 2 , the bottom surface of the die paddle  41  connecting to the drain terminal  13  at the bottom of the chip  10  is exposed for heat dissipation. 
       FIG. 21  is similar to  FIG. 12 , in which solderable metal pads are plated on the top surface of the packaging structure at the top surfaces of contact bodies  21  and  22  and the contact part  42  to re-pattern the package external connection between the corresponding terminal on the chip  10  and the external device. The location of the plated metal pads on the top surface of the packaging structure depends on the desired application of the device. 
     The volume of the packaged device with the wafer level substrate-less MOSFET chip made by the methods of the present invention is effectively reduced. The packaged device include a semiconductor chip  10  with a top source terminal  12  electrically connected to the contact body  22  and the source contact pad  52 , a top gate terminal  11  electrically connected to the contact body  21  and the gate contact pad  51 , a drain  13  terminal at the bottom of the chip  10  electrically connected to a die paddle  41  and the contact part  42  of the lead frame  40  as well as a drain contact pad  61  formed on the contact part  42 . The gate contact pad  51 , the source contact pad  52  and the drain contact pad  61  are insulated and separated by the first plastic package body  31  and the second plastic package body  32 . The top surfaces of the packaging structures with these contact pads are flush and used as the back side ( FIG. 3 ) of a power device facing downward in the actual application for electrically connecting to the external devices. The re-pattern circuit on the surface of the packaging structure can be formed by changing the locations of the contact pads. The bottom surfaces of the packaging structures with the bottom surface of the die paddle  41  of the lead frame  40  being exposed is used as the top side ( FIG. 2 ) of the power device facing upward in the actual application for the electrical connection to the external devices and also for improving the heat dissipation of the device. 
     The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.

Technology Category: 5