Patent Document

PARTIES TO A JOINT RESEARCH AGREEMENT 
     International Business Machines Corporation, a New York corporation, and Macronix International Corporation, Ltd., a Taiwan corporation are parties to a Joint Research Agreement. 
     BACKGROUND 
     1. Field of the Invention 
     This technology relates to an oscillator circuit, and in particular an oscillator circuit with a hysteresis circuit, such as a series of cross-coupled inverters, and separately in particular to the inclusion of multiple current sources to simplify the prediction of the oscillator frequency. 
     2. Description of Related Art 
     Current controlled ring oscillators, with a series of inverters powered by current sources, have a frequency which is difficult to predict, and have a slow transient. The slow transient and the difficulty of predicting the output frequency occur, because despite the inclusion of current sources, the charging and discharging current of an output node in the current controlled oscillator is not determined by a simple relationship to the size of the current sources. Instead, the current controlled ring oscillators has an output frequency which is a complicated and slow function of the sizes of the PMOS and NMOS transistors of the neighboring inverters, mobility, input voltage, etc. 
     SUMMARY 
     One aspect of the technology is an apparatus including an oscillator circuit generating an oscillating signal. 
     The oscillator circuit includes a circuit loop and multiple current sources. The circuit loop includes an output having the oscillating signal. The multiple current sources are turned on independently of a phase of the oscillating signal. The multiple current sources control magnitudes of both charging current and discharging current at nodes of the circuit loop, including the output. Relative magnitudes of different current sources in the multiple current sources determine a frequency of the oscillating signal. 
     In some embodiments, the circuit loop includes multiple series-connected hysteresis circuits. In some embodiment, the nodes connect neighboring hysteresis circuits. In one embodiment, the charging current of the nodes is determined by a current difference between a first current source of a following hysteresis circuit and a second current source of a preceding hysteresis circuit, such that the first current source draws a first current from a high voltage reference and the second current source sinks a second current to a low voltage reference. In another embodiment, the discharging current of the nodes is determined by a current difference between a first current source of a preceding hysteresis circuit and a second current source of a following hysteresis circuit, such that the first current source draws a first current from a high voltage reference and the second current source sinks a second current to a low voltage reference. 
     In some embodiments, the circuit loop includes multiple series-connected cross-coupled inverters. In some embodiments, the nodes connect neighboring cross-coupled inverters of the plurality of series-connected cross-coupled inverters. In one embodiment, the charging current of the nodes is determined by a current difference between a first current source of a following cross-coupled inverter and a second current source of a preceding cross-coupled inverter, such that the first current source draws a first current from a high voltage reference and the second current source sinks a second current to a low voltage reference. In another embodiment, the discharging current of the nodes is determined by a current difference between a first current source of a preceding cross-coupled inverter and a second current source of a following cross-coupled inverter, such that the first current source draws a first current from a high voltage reference and the second current source sinks a second current to a low voltage reference. 
     In some embodiments, the cross-coupled inverters include a first inverter and a second inverter, such that the first inverter has an output connected to an input of the second inverter, the second inverter has an output connected to an input of the first inverter, the input of the first inverter is responsive to a preceding signal from a preceding cross-coupled inverter, and the output of the first inverter sends a following signal to a following cross-coupled inverter. 
     In one embodiment, the relative magnitudes of the different current sources determine the frequency of the oscillating signal, in that the relative magnitudes of the different current sources include a current ratio of a first current source of the first inverter to a second current source of the second inverter, the first current source and the second current source drawing current from a high voltage reference. 
     In another embodiment, the relative magnitudes of the different current sources determine the frequency of the oscillating signal, in that the relative magnitudes of the different current sources include a current ratio of a first current source of the first inverter to a second current source of the second inverter, the first current source and the second current source sinking current to a low voltage reference. 
     In various embodiments, the oscillating signal is a triangle wave. In various embodiments, the oscillating signal is a sinusoidal wave. 
     Another aspect of the technology is a method, comprising the steps:
         generating an oscillating signal from an output of a circuit loop, the frequency of the oscillating signal determined by relative magnitudes of different current sources in a plurality of current sources, the plurality of current sources turned on independently of a phase of the oscillating signal, the plurality of current sources controlling magnitudes of both charging current and discharging current at nodes of the circuit loop.       

    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified diagram of a hysteresis circuit with a pull up portion and a pull down portion. 
         FIG. 2  is a time domain graph of the output voltage of a hysteresis circuit, showing that the present output is determined not just by the present input, but also by the past output. 
         FIG. 3  is a graph of input voltage versus output voltage of a hysteresis circuit, also showing that the present output is determined not just by the present input, but also by the past output. 
         FIG. 4  is a circuit diagram of an inverter circuit which is not a hysteresis circuit. 
         FIG. 5  is a graph of input voltage versus output voltage of the inverter circuit of  FIG. 4 , showing that the present output is determined by the present input without requiring the past output. 
         FIG. 6  is a circuit diagram of a hysteresis circuit, which includes a cross-coupled inverter preceded by an inverter circuit. 
         FIG. 7  is a graph of input voltage versus output voltage of the hysteresis circuit of  FIG. 6 , showing that the present output is determined not just by the present input, but also by the past output. 
         FIGS. 8-10  show example graphs of input voltage versus output voltage of an inverter circuit, showing that the transfer characteristic is predictably varied with the ratio of the strength of the component PMOS and NMOS transistors. 
         FIG. 11  is a graph of input voltage versus output voltage of an inverter circuit, with an example point along the transition region. 
         FIG. 12  is a circuit diagram of an inverter circuit operating at the example point along the transition region as shown in  FIG. 11 . 
         FIG. 13  is a circuit diagram of an inverter circuit with added current sources that attempt to simplify the prediction of the charging current and discharging current of the output node. 
         FIG. 14  is a time domain graph of the output voltage of an inverter circuit, with the added current sources as in  FIG. 13 , illustrating the difference between the expected fast transient discharge speed, and the actual slow transient discharge speed. 
         FIG. 15  is a circuit diagram of an oscillator circuit with a series of hysteresis circuits including cross-coupled inverters. 
         FIG. 16  is a circuit diagram of an oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources to simplify the prediction of the charging current and discharging current of the output node. 
         FIG. 17  is a circuit diagram of a portion of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 , with a charging current path shown, including the two primary current sources that predict the charging current. 
         FIG. 18  is a circuit diagram of a portion of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 , with a discharging current path shown, including the two primary current sources that predict the discharging current. 
         FIGS. 19-25  are time domain graphs of different nodes of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 . 
         FIG. 26  is a circuit diagram of a portion of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 , acting as a key to indicate the graphed nodes of  FIGS. 19-25 . 
         FIG. 27  is a circuit diagram of a voltage controlled oscillator, including the oscillator circuit with a series of hysteresis circuits. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a simplified diagram of a hysteresis circuit with a pull up portion and a pull down portion. 
     Circuit A performs the pull up, and Circuit B performs the pull down. An example of Circuit A is a current source that sources current from a high voltage reference, and an example of Circuit B is a current source that sinks current to a low voltage reference 
       FIG. 2  is a time domain graph of the output voltage of a hysteresis circuit, showing that the present output is determined not just by the present input, but also by the past output. 
     The transient is slow at the beginning, and then fast at the end. 
       FIG. 3  is a graph of input voltage versus output voltage of a hysteresis circuit, also showing that the present output is determined not just by the present input, but also by the past output. 
     It appears to be the overlapped version of the rising and falling time domain curves, adjusted as functions of the input voltage. 
     Hysteresis is created by making the signal hard to transition or slower in one direction than the other direction. 
       FIG. 4  is a circuit diagram of an inverter circuit which is not a hysteresis circuit. 
       FIG. 5  is a graph of input voltage versus output voltage of the inverter circuit of  FIG. 4 , showing that the present output is determined by the present input without requiring the past output. 
     The transition from point A to point E occurs as follows: 
     At A: Vi=0.1, Vo=1 
     At B: Vi=0.3, Vo=1 
     At C: Vi=0.5, Vo=0.5 
     At D: Vi=0.7, Vo=0 
     At E: Vi=0.9, Vo=0 
     The opposite transition from point E to point A is exactly the same as listed above, but in the opposite order. 
       FIG. 6  is a circuit diagram of a hysteresis circuit, which includes a cross-coupled inverter preceded by an inverter circuit. 
     For simplicity, in some embodiments with a series of hysteresis circuits, the hysteresis circuit refers to the cross-coupled inverters, but without the preceding inverter circuit, there is no hysteresis. 
       FIG. 7  is a graph of input voltage versus output voltage of the hysteresis circuit of  FIG. 6 , showing that the present output is determined not just by the present input, but also by the past output. 
     The transition from point A to point E occurs as follows: 
     At A: Vi=0.1, Vo=1 
     At B: Vi=0.3, Vo=1 
     At C: Vi=0.5, Vo=0.9 
     At D: Vi=0.7, Vo=0.7 
     At E: Vi=0.9, Vo=0 
     However, the opposite transition from point E to point A occurs as follows: 
     At E: Vi=0.9, Vo=0 
     At B: Vi=0.7, Vo=0 
     At C: Vi=0.5, Vo=0.1 
     At D: Vi=0.3, Vo=0.3 
     At E: Vi=0.1, Vo=1 
     Because the transition between point A and point E depends on the direction, there is hysteresis. 
     The hysteresis curve of  FIG. 7  is explained in the context of  FIG. 6 . 
     At the beginning, say Vi=0, Vx=1, Vo=0 
     Vi=0.1
         P 1  stays “ON”; the same as P 2  and P 3 .   N 1  stays “OFF”; the same as N 2  and N 3 , as if nothing happened.   Vi=0.1, Vx=1, Vo=0       

     Vi=0.3
         P 1 , P 2  and P 3  are still “ON”.   N 1  is beginning to turn “ON” meaning a tiny amount of current is possibly going through. To simplify, say the current is too small, such that nothing changed.   Vi=0.3, Vx=1, Vo=0       

     Vi=0.5
         P 1  is turning off, but not yet, such that current from the power supply through P 1  to Vx is reduced.   If only the single inverter P 1  and N 1  existed, then current IP 1  would be equal to current IN 1 . But here P 2  is still “ON”, N 2  is still “OFF. Therefore there are two currents IP 1  and IP 2  charging Vx; but only one current IN 1  discharging Vx.   At this moment Vi=0.5, Vx=0.9, Vo=0. Something is happening on Vi and Vx, but nothing is affecting Vo.   Nothing is affecting Vo means Vx=0.9, such that Vo changes nothing.       

     Vi=0.7
         The voltage Vi=0.7 turns off P 1 .   There will be one current IP 2  charging Vx and one current IN 1  discharging Vx. IP 2 &gt;IN 1  due to Vi=0.7. Vo is around 0.   So Vi=0.7, Vx=0.7, Vo=0 approximately.       

     Vi=0.9
         N 1  is really “ON” which makes Vx lower. Vx=0.3 first. Something is going on.   Vx=0.3 makes P 3  turn “ON” which charges up Vo up to about 0.5.   Vo=0.5 makes IP 2  smaller, then Vx will be lower than 0.3.   This feedback loop starts working. The feedback loop keeps increasing Vo up to 1, and decreasing Vx lower to 0.   Finally assume Vi=0.9, Vx=0, Vo=1.       

       FIGS. 8-10  show example graphs of input voltage versus output voltage of an inverter circuit, showing that the transfer characteristic is predictably varied with the ratio of the strength of the component PMOS and NMOS transistors. 
     The ratio of the PMOS and NMOS controls the transient point. 
     In  FIG. 8 , the PMOS:NMOS ratio=1:1 (equal) 
     In  FIG. 9 , the PMOS:NMOS ratio=1:2 (NMOS stronger) 
     In  FIG. 10 , the PMOS:NMOS ratio=2:1 (PMOS stronger) 
     The transient point is controllable by adjusting the P and N wells. 
       FIG. 11  is a graph of input voltage versus output voltage of an inverter circuit, with an example point along the transition region. 
       FIG. 12  is a circuit diagram of an inverter circuit operating at the example point along the transition region as shown in  FIG. 11 . 
     There are three currents I 3 =I 1 -I 2 . The three currents are predictable if they are practically simple to calculate. 
       FIG. 13  is a circuit diagram of an inverter circuit with added current sources that attempt to simplify the prediction of the charging current and discharging current of the output node. 
     The added current sources attempt to control the rising and falling time of the inverter by setting the transient current to I 1  for charging current and I 2  for discharging current. 
       FIG. 14  is a time domain graph of the output voltage of an inverter circuit, with the added current sources as in  FIG. 13 , illustrating the difference between the expected fast transient discharge speed, and the actual slow transient discharge speed. 
     Unfortunately, the transient does not follow the dashed line, as would be the case if the added current sources dominated the transient current. Instead, despite the added current sources, the actual transient follows the slower solid line. The transient is slower than expected. The reason is that although I 1  and I 2  determine the transient speed on the PMOS and NMOS during charging and discharging Vo, the I 3  current through the capacitance is too small. 
     For the purposes of predictability, although the equation is I 3 =I 1 −I 2 , the actual value of I 3  is complicated to calculate, because the current I 3  is related to size, Vi, mobility, etc. 
     Accordingly, there are two problems: slow transient speed, and lack of predictability. Various embodiments add current sources to address both problems. 
       FIG. 15  is a circuit diagram of an oscillator circuit with a series of hysteresis circuits including cross-coupled inverters. 
     The circuit demonstrates current flow during the charging and discharging phases. Assume V 1 =1, Vo=0, V 2 =1 (V 2 =1 will make V 1  go low like and inverter, and oscillation results.) 
     When Vo is at charging phase, ideally, IC is the charging current IC=IP 1 −IN 0 . But this is not the case. 
     When Vo is at discharging phase, ideally, IC is the discharging current=IN 1 −IP 0 . But this is not the case. 
       FIG. 16  is a circuit diagram of an oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources to simplify the prediction of the charging current and discharging current of the output node. 
     The current sources simplify prediction of the charging current and discharging current according to  FIGS. 17 and 18 . 
     The technology adds high controllability to the frequency of a ring oscillator without phase detection. A typical application is medium-high frequency (100 MHz˜1 GHz) operation. 
     I*T=C*V, where I is current, T is period, C is capacitance, and V is peak voltage. There are 4 variables. 
     With a regulated V, C significantly larger than parasitic capacitance, then an accurate I determines 3 variables of the 4 variables, thereby making predictable the remaining 4th variable of T (or Frequency). 
     Accordingly, this technology accurately controls the current. Because C and V are also controlled, the current control also controls the frequency. 
     The following is an example of determining the current to achieve a 250 MHz (4 nS) oscillator signal. 
     I*T=C*V 
     V=2.5 V and regulated. Other voltages are possible. 
     C=250 fF, significant larger than parasitic capacitance. 
     The goal is T=2 ns, which represents a half cycle, corresponding to either the charging half cycle or the discharging half cycle. 
     According to the equation, the controlled current should be I=312.5 uA or about 300 uA. So peak current of IC should be 600 uA or higher, due to parasitic capacitance. This current comes from current reference system. 
     IC=IP 1 −IN 0 =600 uA, or IC=IN 1 −IP 0 =600 uA 
     In the following equations, I 1  is for short for IP 1  or IN 1 ; I 0  is for short for IP 0  or IN 0 . 
     I 1 −I 0 =600 uA 
     I 1 =600 uA, I 0 =0 uA, I 1 :I 0 =infinite; means not physical. 
     I 1 =700 uA, I 0 =100 uA, I 1 :I 0 =7:1; too large a ratio is hard to current match, but saves some power 
     I 1 =800 uA, I 0 =200 uA, I 1 :I 0 =4:1 
     I 1 =1.2 mA, I 0 =400 uA, I 1 :I 0 =3:1; current consumption is getting larger and not so much gain from ratio. 
     In the preceding example calculation, the ratio of the current sources corresponding to IP 1  and IN 0  is 4:1, and the ratio of the current sources corresponding to IN 1  and IP 0  is 4:1. Similarly, the difference between the current sources corresponding to IP 1  and IN 0  is 600 uA, and the difference between the current sources corresponding to IN 1  and IP 0  is 600 uA. 
     In other embodiments, other current ratios are possible. 
     The values of IP 0 , IP 1 , IN 0  and IN 1  are controllable by a trimmed bias or a phase detector. 
     The ideal load capacitance CL varies with whether a phase detector is used. With a phase detector, load capacitance CL could be zero for saving power, and increase the oscillator frequency into the GHz range. Without a phase detector, load capacitance CL should be as large as possible, to avoid process variation, at the cost of more power consumption. 
       FIG. 17  is a circuit diagram of a portion of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 , with a charging current path shown, including the two primary current sources that predict the charging current. 
     During the charging phase, the average charging current IC=K*(IP 1 −IN 0 ) 
     K is a constant. K=½ for triangle current waveform. 
       FIG. 18  is a circuit diagram of a portion of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 , with a discharging current path shown, including the two primary current sources that predict the discharging current. 
     During the discharge phase, the average discharging current IC=K*(IN 1 −IP 0 ) 
     Again, K is a constant. K=½ for triangle current waveform. 
     At a lower frequency range, where the output waveform is triangular, 
     T=2*{[CL*(Vd−Vs)]/[0.5*(x−y)]} 
     (x−y) represents a relative magnitude of the current sources, such as (800 uA−200 uA). 
     (Vd−Vs) represents a difference between the high voltage reference and the low voltage reference. The current sources source current from the high voltage reference Vd and sink current to the low voltage reference Vs. 
     Frequency=1/T (units in Hertz) 
       FIGS. 19-25  are time domain graphs of different nodes of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 . 
       FIGS. 19-25  divide a full clock period into 4 smaller time periods, labeled T 1 , T 2 , T 3 , and T 4 . 
     In both T 1  and T 2 , the output node OUT has a discharging current of IN 1 −IP 0 , and IP 1  and IN 0  are almost off. Because IP 1  and IN 0  are almost off, their contribution can be practically ignored for predicting the oscillator frequency. 
     In both T 3  and T 4 , the output node OUT has a charging current of IP 1 −IN 0 , and IP 0  and IN 1  are almost off. Because IP 0  and IN 1  are almost off, their contribution can be practically ignored for predicting the oscillator frequency. 
       FIG. 19  is IN 1 , the current flowing through the NMOS of an inverter. The NMOS is connected to the output node, and the inverter belongs to a following cross-coupled inverter of neighboring cross-coupled inverters. 
       FIG. 20  is IP 0 , the current flowing through the PMOS of an inverter. The PMOS is connected to the output node, and the inverter belongs to a preceding cross-coupled inverter of neighboring cross-coupled inverters. 
       FIG. 21  is IP 1 , the current flowing through the PMOS of an inverter. The PMOS is connected to the output node, and the inverter belongs to a following cross-coupled inverter of neighboring cross-coupled inverters. 
       FIG. 22  is IN 0 , the current flowing through the NMOS of an inverter. The NMOS is connected to the output node, and the inverter belongs to a preceding cross-coupled inverter of neighboring cross-coupled inverters. 
       FIG. 23  is IC, the current flowing through the capacitance of the output node. The magnitude of the IC current determines the speed of charging or discharging the output node. 
       FIG. 24  is OUT, the output voltage of the output node. Accordingly, the rising part of the output voltage OUT corresponds to positive IC current, and the falling part of the output voltage OUT corresponds to negative IC current. 
       FIG. 25  is CLK, the clock voltage following a buffer of the output node. The buffer helps the oscillator output look more digital. The number of buffers depends on the number of blocks to be driven. Buffers make the transient faster to get a square-like waveform. An inverter not only separates signals, but also provides drivability. 
       FIG. 26  is a circuit diagram of a portion of the oscillator circuit with a series of hysteresis circuits including cross-coupled inverters, and added current sources, as shown in  FIG. 16 , acting as a key to indicate the graphed nodes of  FIGS. 19-25 . 
       FIG. 27  is a circuit diagram of a voltage controlled oscillator, including the oscillator circuit with a series of hysteresis circuits. 
     An improved voltage controllable oscillator includes the improved oscillator technology herein. The voltage controllable oscillator includes a phase detector and a charge pump circuit. The charge pump circuit includes 2 current sources Ip, resistor R, and capacitor C. 
     Other embodiments include CCO (current controllable oscillator) and RCO (resistor controllable oscillator) 
     While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

Technology Category: 5