Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to gate and storage dielectrics of integrated circuit devices. More particularly, this invention relates to scalable gate and storage dielectric systems.  
           [0002]    A dielectric is an insulating material capable of storing electric charge and associated energy by means of a shift in the relative positions of internally bound positive and negative charges known as charge dipoles. This shift is brought about by an external electric field. A dielectric system is a collaborating arrangement of materials including at least one dielectric material.  
           [0003]    Dielectric systems are directly involved in the progress of microelectronic process technology. Successes in the manufacture of quality dielectric systems have done much to advance integrated circuit technology. Improved dielectric systems have traditionally resulted in significant increases in electronic device and system capabilities.  
           [0004]    The quality of a dielectric system can be determined generally by a well-defined criteria. One criterion is the effective dielectric constant K of the system. The effective dielectric constant is dependent on the individual dielectric constants of the materials used in the system. A dielectric constant indicates the relative capacity, as compared to a vacuum where K=1, of the material to store charge. Thus, high dielectric constant materials advantageously produce dielectric systems with high capacity to store charge.  
           [0005]    Another criterion is the scalability of the system. Scalability of a dielectric system refers to its physical size (i.e., its thickness, measured in nanometers, and area). In particular, the ability to minimize the size of the system is important. Note that a system&#39;s thickness and area can each be scaled independently of the other. A dielectric system having a geometrically scalable thickness may allow higher charge storage capacity. A dielectric system having a geometrically scalable area may allow more transistors to be fabricated on a single integrated circuit chip, thus allowing increased functionality of that chip.  
           [0006]    Additional criteria for determining the quality of a dielectric system are dielectric interface compatibility and high temperature structural stability. In order to produce a stable and reliable device, a dielectric must be chemically compatible with the semiconductor substrate or plate material with which the dielectric forms an interface. The substrate or plate material is usually silicon. In addition, the substrate and dielectric interface must remain stable over a range of temperatures.  
           [0007]    Other criteria are a dielectric system&#39;s ability to provide charge control and stoichiometric reproducibility at a substrate/dielectric or plate/dielectric interface. Uncontrollable bonding at an interface may decrease device reliability and cause inconsistent device characteristics from one device to another. Dangling atoms (i.e., atoms that have not formed bonds) from the dielectric material may contribute to an undesirable charge accumulation at the interface. Charge accumulation varying from device to device can lead to an undesirably varying threshold voltage from device to device. The threshold voltage can be defined as the minimum voltage applied to a gate electrode of a device that places the device in active mode of operation.  
           [0008]    In addition, leakage characteristics of a dielectric material are particularly important when the dielectric material is used in scaled down devices. A thin gate dielectric often gives rise to an undesirable tunneling current between a gate and the substrate. Tunneling current results in wasted power and is particularly destructive in memory circuitry, in which capacitors coupled to a gate dielectric system may be undesirably discharged by the tunneling (i.e., leakage) current.  
           [0009]    High temperature chemical passivity is also an important criterion of a dielectric system. A gate dopant may undesirably diffuse through a gate dielectric material during high temperature device fabrication, corrupting the substrate/dielectric or plate/dielectric interface. The dopant may form bonds with the dielectric material and the substrate or plate material causing an undesirable negative charge buildup at the interface. This negative charge may also result in an undesirable increase in the threshold voltage of the device.  
           [0010]    Further, the quality of a dielectric system is also determined by its breakdown characteristics. A uniform dielectric breakdown characteristic across multiple dielectric systems is advantageous because breakdown of a single dielectric system in a device or circuit can cause undesirable and unpredictable device or circuit operation. Loosely defined, a dielectric breakdown occurs when a voltage applied to a dielectric system exceeds a breakdown voltage limit of the dielectric material as it is arranged in the system. Moreover, the breakdown of a storage dielectric can cause stored charge to undesirably dissipate. Thus, a uniform dielectric breakdown characteristic increases system functionality, reliability, and robustness.  
           [0011]    Finally, the quality of a dielectric system is further determined by its ability to permit etch selectivity during fabrication. Etch selectivity refers to an ability to selectively remove material to leave behind a desired pattern. The desired pattern corresponds to the arrangement of materials in a system or device. A material that is not significantly etch selective may pose problems in the fabrication of that system or device, as the material may not permit structural integration with other materials of the device.  
           [0012]    In an ongoing effort to develop improved dielectric systems, diligent research and experimentation have highlighted problematic dielectric system characteristics. Known limitations of traditional dielectric material silicon dioxide (SiO 2 ), namely its low K value, high leakage characteristic resulting from increased scaling, and its high temperature chemical impassivity, show the need for improved dielectric materials and systems. Attempts to find improved dielectric materials and systems, as defined by the criteria described above, have had limited success. Particularly, attempts to develop a dielectric system that concurrently satisfies all of the above concerns and issues and that overcomes the limitations of SiO 2  have been unsuccessful.  
           [0013]    In view of the foregoing, it would be desirable to provide improved dielectric systems.  
           [0014]    It would also be desirable to provide methods of fabricating improved dielectric systems.  
         SUMMARY OF THE INVENTION  
         [0015]    It is an object of the present invention to provide improved dielectric systems.  
           [0016]    It is also an object of the present invention to provide methods of fabricating improved dielectric systems.  
           [0017]    Gate and storage dielectric systems of the present invention provide high effective K values. Improved gate and storage dielectric stacks include a high K dielectric material that produces improved device characteristics such as increased storage capacity and increased drive current. Additionally, the improved dielectric stacks include a passivated overlayer that maintains the high effective K values, in addition to other desirable characteristics. For example, a silicon-rich-nitride passivated overlayer advantageously provides a stoichiometric interface between a dielectric and a substrate or storage plate. In addition, a silicon-rich-nitride passivated overlayer advantageously provides charge control and regulation of threshold voltage in metal-oxide-semiconductor field effect transistors (MOSFETs).  
           [0018]    Methods of fabricating improved gate and storage dielectric systems are also provided by the present invention. A substrate or bottom storage plate is carefully prepared before subsequent deposition of metal or, in other embodiments, dielectric material. Metal or dielectric materials are deposited to minimize thickness and to maximize storage capacity. Increased storage capacity, which is also characteristic of high K materials, increases area scaling capabilities. Increased area scaling can reduce the integrated circuit chip area required to fabricate an integrated circuit device. Thus, either more devices can be fabricated on a single integrated circuit chip, advantageously allowing increased functionality, or more integrated circuit chips can be fabricated on a single wafer, advantageously reducing costs.  
           [0019]    The passivated overlayer is deposited such that the resulting K value of the overlayer does not compromise the high K value of the dielectric used in the dielectric stack. Dielectric stacks may be appropriately annealed to provide greater stack stability. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:  
         [0021]    [0021]FIG. 1 is a cross-sectional diagram of an exemplary embodiment of a gate dielectric stack according to the invention;  
         [0022]    [0022]FIG. 2 is a cross-sectional diagram of a known gate dielectric stack;  
         [0023]    [0023]FIG. 3 is a graph of dielectric constants versus refractive indices of silicon-rich-nitride;  
         [0024]    [0024]FIG. 4 is a cross-sectional diagram of an exemplary embodiment of a storage dielectric stack according to the invention;  
         [0025]    [0025]FIGS. 5 and 6 are cross-sectional diagrams of improved integrated circuit devices using the dielectric stacks of the invention;  
         [0026]    [0026]FIG. 7 is a flowchart of an exemplary embodiment of a method of fabricating a dielectric stack according to the invention;  
         [0027]    [0027]FIG. 8 is a graph of refractive indices of silicon-rich-nitride versus ratios of dichlorosilane-to-ammonia used in the fabrication of silicon-rich-nitride; and  
         [0028]    [0028]FIG. 9 is a flowchart of another exemplary embodiment of a method of fabricating a dielectric stack according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0029]    The present invention provides improved dielectric systems and methods of their fabrication in which many quality concerns and issues of dielectric systems are preferably concurrently satisfied.  
         [0030]    [0030]FIG. 1 shows a gate dielectric stack  100  in accordance with the invention. Stack  100  includes substrate  102 , gate dielectric  104 , passivated overlayer  106 , gate  108 , and gate electrode  110 . Substrate  102  can be one or more semiconductor layers or structures which can include active or operable portions of semiconductor devices. Generally, substrate  102  comprises silicon (Si). Gate  108  can comprise a degenerate heavily doped polysilicon, a metal, or other conductive material.  
         [0031]    Gate dielectric  104 , which can also be referred to as gate insulator  104 , includes a single phase stoichiometrically-uniform-composition material having a high dielectric constant (e.g., K≧10) or a silicon or transition-metal doped derivative thereof. A single phase stoichiometrically uniform material includes a single material having a consistently precise number of atoms and bonds in a molecule of the material. A transition metal dopant of gate dielectric  104  may be zirconium, tungsten, hafnium, titanium, tantalum, or other suitable transition metal. In particular, gate dielectric  104  is preferably stoichiometric alumina (Al 2 O 3 ), which has a K value in the range of about 11 to about 12. Alumina is oxidized aluminum, a metal which can be deposited one atomic layer at a time to form ultra thin metal films (e.g., less than about 3 nm). These metal films are subsequently oxidized in ultra pure oxygen or ozone plasma to produce stoichiometric alumina. Alternatively, gate dielectric  104  can be a composite such as silicon-doped alumina or transition-metal-doped alumina, each typically having a K&gt;15.  
         [0032]    A high K dielectric permits greater scalability of a dielectric stack. Scalability of a dielectric stack refers to the ability to reduce the size of the stack. Smaller dielectric stacks preferably allow, among other things, more transistors to be fabricated on an integrated circuit chip, thus allowing more functionality on that chip. Greater scalability of the area occupied by the stack is possible because a high K gate dielectric has a higher dielectric capacitance per unit area (C d ) for a fixed dielectric thickness (t d ) than a lower K dielectric material, such as traditionally used silicon dioxide (K≈4). This is shown in the relationship C d ∝K/t d . A higher dielectric capacitance per unit area corresponds to a higher capacity to store charge, which can compensate for the storage capacity characteristically lost when the area of a dielectric device or system is scaled.  
         [0033]    Moreover, because drive current is directly proportional to dielectric capacitance in metal-oxide-semiconductor field effect transistors (MOSFETs), the increased dielectric capacitance per unit area provided by a high K dielectric provides increased drive current. Drive current can be generally defined as the current flowing through induced channel  118  from drain electrode  120  to source electrode  122  when, in the presence of sufficient potential between drain electrode  120  and source electrode  122 , a voltage equal to or greater than the threshold voltage of the MOSFET device is applied to the gate. A low K dielectric material in gate dielectric  104  may not provide sufficient drive current, even when the thickness of gate dielectric  104  is scaled. Thus, to provide sufficient drive current, a high K dielectric is often required.  
         [0034]    The scalability of high K gate dielectric  104  is but one consideration when evaluating the quality of a dielectric system. Because gate dielectric  104  forms interface  112  with substrate  102 , the gate dielectric material should also be chemically compatible with the substrate material.  
         [0035]    Alumina, when used as gate dielectric  104 , is chemically compatible with a silicon substrate  102 . However, the combination of the two materials does not inherently provide a stoichiometric interface at interface  112 . During device fabrication, hydroxide ions can cause undesirable and nonstoichiometric formation of alumino-silicate (Al x Si y O z ) at interface  112 . The hydroxide ions may be absorbed into a silicon substrate or plate in the form of Si x O y H z  and may be naturally present due to exposure of the substrate or plate to open air or to ambient hydroxide. Alumino-silicate formed at interface  112  can have an undesirably lower K value than the stoichiometric alumina gate dielectric, producing an undesirably lower effective K value for the dielectric stack. Moreover, known fabrication methods may result in uncontrollable and incomplete alumino-silicate bonding at interface  112 .  
         [0036]    Incomplete bonding at interface  112  can cause an undesirable accumulation of fixed negative charge at interface  112 . This may result in an undesirable increase in the threshold voltage of the device. In particular, dangling atoms from the dielectric material of gate dielectric  104  (i.e., atoms that have not formed bonds) and from substrate  102  may contribute to the undesirable fixed interface charge accumulation at interface  112 .  
         [0037]    Passivated overlayer  106  advantageously prevents dopant used in gate  108  from readily diffusing through high K gate dielectric  104  to form bonds at interface  112 . This dopant diffusion phenomenon may be especially evident at high temperatures common during device fabrication. For example, as shown in FIG. 2, the combination of a phosphorus-doped silicon gate  208  deposited directly upon alumina gate dielectric  204  causes the formation of an alumino-phospho-silicate layer  203  at interface  212 . Interface  212  may have originally been less of an uncorrupted interface between gate dielectric  204  and silicon substrate  202  before high temperature fabrication caused phosphorous dopant diffusion through gate dielectric  204 .  
         [0038]    Alumino-phospho-silicate layer  203  may contribute to negative charge buildup (Q I ) at interface  212 . The known device of FIG. 2 generally has a fixed Q I ≈3e+13 (i.e., that is Q I ≈3×10 13 ) fundamental charge units per cm 2 . One fundamental charge unit is equal to about 1.60218e-19 coulombs. As described above, a fixed charge accumulation in the dielectric material undesirably causes an increase in the threshold voltage. Because dopant diffusion through gate dielectric  204  may be uncontrollable, formation of alumino-phospho-silicate layer  203  may be uncontrollable. Consequently, the negative charge at interface  212 , and the threshold voltage of any device that uses this known stack, may be uncontrollable and may undesirably vary from device to device.  
         [0039]    Alumino-phospho-silicate layer  203  may also have a lower K value than that of gate dielectric  204 . This causes an undesirable lowering of the effective K value of the dielectric stack. Again, this would adversely affect at least one of the advantages of having a high K value, namely scalability.  
         [0040]    Returning to FIG. 1, passivated overlayer  106  forms chemically inert interface  114  with gate  108  and forms chemically inert interface  116  with gate dielectric  104 . A chemically inert interface is an interface at which no substantial bonding occurs between the materials forming the interface.  
         [0041]    Passivated overlayer  106  preferably provides high temperature chemical passivity in dielectric stack  100 . In particular, passivated overlayer  106  prevents diffusion of dopant from gate  108  through gate dielectric  104 , which would subsequently corrupt interface  112  and lower the effective K value of the stack. Passivated overlayer  106  thus prevents additional fixed charge formation. Consequently, the combination of the contaminant protection of passivated overlayer  106  and the stoichiometry of interface  112  provides a reduced interface charge in the device of FIG. 1. Stack  100  advantageously has a fixed Q I  approximately ≦3e+10 fundamental charge units per cm 2 , which is significantly less than the typical fixed interface charge of known devices of Q I ≈3e+13 fundamental charge units per cm 2 .  
         [0042]    In addition, passivated overlayer  106  preferably provides uniformity in the dielectric breakdown voltage limit of the dielectric stack. The contaminant protection provided by passivated overlayer  106  prevents local (i.e., geometrically small) defects in gate dielectric  104  that contribute to a lower dielectric breakdown voltage. Moreover, in the absence of passivated overlayer  106 , uncontrollable dopant diffusion into gate dielectric  104  may likely result in an undesirably uncontrollable and varying threshold voltage.  
         [0043]    Further, passivated overlayer  106  preferably provides uniform injection of either electrons or holes from gate  108  into gate dielectric  104  when a voltage is applied to gate electrode  110 . The injection of electrons or holes corresponds respectively to either an n-type or p-type gate  108 . Passivated overlayer  106  thus improves reliability and uniformity in gate dielectric stack  100 .  
         [0044]    Passivated overlayer  106  is preferably “injector” silicon-rich-nitride (SRN), which is an SRN with a refractive index of about 2.5 or greater, and preferably has a thickness in the range of about 0.5 to about 3.0 nm. Injector SRN can be characterized as a two phase insulator consisting of uniformly distributed silicon nano crystals in a body of stoichiometric nitride. A refractive index of about 2.5 or greater provides passivated overlayer  106  with a dielectric constant comparable to or greater than that of a high K gate dielectric  104 . Particularly, injector SRN has a dielectric constant that is greater than or equal to 12, which is the K value of silicon. Thus, the benefits of a high K gate dielectric  104 , as described above, are not canceled by the addition of passivated overlayer  106 . Alternatively, passivated overlayer  106  can be an SRN with a refractive index of less than about 2.5; however, a maximum K and the benefits associated therewith in a dielectric stack are achieved when the refractive index is greater than about 2.5.  
         [0045]    [0045]FIG. 3 illustrates the relationship between the refractive indices and dielectric constants K of injector SRN. As shown, injector SRN with a refractive index of about 2.5 or greater provides a K value greater than about 12, which is the dielectric constant of silicon.  
         [0046]    [0046]FIG. 4 shows a storage dielectric stack  400  in accordance with the invention. Stack  400  includes bottom plate  402 , storage dielectric  404 , passivated overlayer  406 , and top plate  408 . Bottom plate  402  and top plate  408  can be a degenerate heavily doped silicon, a doped polysilicon material, a metal, or other conductive material.  
         [0047]    Storage dielectric  404  is preferably the same material as that of gate dielectric  104 , namely alumina or a doped derivative of alumina. As previously described, alumina is oxidized aluminum, a metal which can be deposited in ultra thin metal films (e.g., less than about 3 nm) and subsequently oxidized in ultra pure oxygen or ozone plasma to produce stoichiometric is alumina. A high K dielectric value (e.g., K≧10) in storage dielectric  404  provides a higher storage capacity, which is advantageous in memory devices such as DRAMS (dynamic random access memories). High storage capacity in high K dielectrics results from the high capacitance per unit area provided by high K dielectrics, as previously described. Passivated overlayer  406  is preferably the same material as that of passivated overlayer  106 , namely injector SRN or SRN, and preferably serves the same or similar purposes in the stack. In particular, passivated overlayer  406  prevents diffusion of dopant from top plate  408  through storage dielectric  404 .  
         [0048]    Passivated overlayer  406  provides uniform injection of electrons or holes from top plate  408  into storage dielectric  404  during voltage stress and provides uniform dielectric breakdown in storage dielectric  404 . Passivated overlayer  406  preferably has the same range of thickness (i.e., about 0.5 to about 3 nm) and refractive index (i.e., 2 about 2.5) as passivated overlayer  106 . The fixed charge (Q I ) at interface  412  is advantageously about the same as in gate dielectric stack  100 , namely Q I  approximately ≦3e+10 units of fundamental charge per cm 2 .  
         [0049]    [0049]FIG. 5 shows an integrated circuit device  500  using the dielectric stacks of the invention. Device  500  is an embodiment of a deep trench storage capacitor DRAM cell that includes embodiments of the gate and storage dielectric stacks of the invention. Storage (capacitor) dielectric stack  501  includes bottom plate/substrate  502 , storage dielectric  504 , passivated overlayer  506 , and top plate  508 . A logic data bit is written into storage dielectric stack  501  via bit line  510  when sufficient voltage is applied to bit line  510  and the voltage at word line  512  (i.e., at the gate electrode) rises above the threshold voltage of gate dielectric stack  100 . Conversely, a logic data bit is read from storage dielectric stack  501  via bit line  510  when insufficient voltage is applied to bit line  510  and the voltage at word line  512  rises above the threshold voltage of gate dielectric stack  100 . Oxide  514 , oxide  516 , and oxide  518  isolate storage dielectric stack  501 . Improved device characteristics of device  500  are obtained from gate dielectric stack  100  and storage dielectric stack  501 . For example, stoichiometric interface  112  provides a desirable lower threshold voltage for performing both read and write operations. Also, the improved charge storage capacity of storage dielectric stack  501  enhances memory capacity and reliability.  
         [0050]    Similarly, FIG. 6 shows another embodiment of an improved DRAM capacitor device using the dielectric stacks of the invention. Device  600  is a stacked capacitor DRAM cell that includes gate dielectric stack  100  and storage (capacitor) dielectric stack  601  in accordance with the invention. Storage dielectric stack  601  includes bottom plate  602 , storage dielectric  604 , passivated overlayer  606 , and top plate  608 . Operation of device  600  is similar to that of device  500 . A logic data bit is written into storage dielectric stack  601  via bit line  610  when sufficient voltage is applied to bit line  610  and the voltage at word line  612  (i.e., at the gate electrode) rises above the threshold voltage of gate dielectric stack  100 . Conversely, a logic data bit is read from storage dielectric stack  601  via bit line  610  when insufficient voltage is applied at bit line  610  and the voltage at word line  612  rises above the threshold voltage of gate dielectric stack  100 . Current flows through electrical contact  614  as storage dielectric stack  601  charges and discharges. The improved characteristics of device  600  are similar to those of is device  500  and are similarly obtained from the dielectric stacks of the invention.  
         [0051]    The gate and storage dielectric stacks of FIGS. 1 and 4- 6  can be fabricated by the method shown in FIG. 7 in accordance with the invention. Process  700  begins at  702  by first preparing the silicon substrate or silicon bottom plate of a dielectric stack. Native radical hydroxide ions (OH − ) are removed from at least a portion of the surface of, for example, silicon substrate  102  or silicon bottom plate  402 . Hydroxide ions may be present in bonds of silicon and silicon hydroxide (Si x O y H z ) that can form naturally in silicon exposed to open air or to ambient hydroxide. If not removed, these radical hydroxide ions may react with a metal-derived gate dielectric material and substrate material, or a metal-derived storage dielectric material and bottom plate material, to form nonstoichiometric bonding. For example, radical hydroxide ions may react with aluminum and silicon to form a nonstoichiometric Al x Si y O z  material. The removal of OH −  involves controllably introducing a hydrofluoric acid (HF) vapor in an ultra pure nitrogen bleed-in, while maintaining sufficient vacuum. Generally, a vacuum of approximately less than about 10 −6  torr is sufficient and can be maintained in a high vacuum chamber.  
         [0052]    Next, at  704 , a single atomic layer of a metal is deposited on the prepared substrate or bottom plate. The metal is preferably aluminum, subsequently oxidized using a controlled amount of ultra pure oxygen or ozone plasma to form stoichiometric alumina at step  706 . Oxidation may be followed by an appropriate anneal (not shown) to stabilize the dielectric stack. Steps  704  and  706  are preferably repeated until a desired thickness of alumina is obtained. Aluminum may be deposited by atomic layer deposition (“ALD”), molecular bean epitaxy (“MBE”), electron beam evaporation, sputtering, or any other suitable method. This procedure should be performed in a vacuum or in a high partial pressure of dry nitrogen gas (N 2 ) to ensure that no undesirable OH −  ions are in the environment.  
         [0053]    Next, at  708 , a passivated overlayer is deposited on the dielectric material. The passivated overlayer is preferably silicon-rich-nitride (SRN) and is preferably deposited in a layer ranging from about 0.5 to about 3.0 nm in thickness. The SRN preferably has a refractive index of ≧2.5. Passivated overlayer deposition can be accomplished by a low pressure plasma enhanced chemical vapor deposition process with silane (SiH 4 ) or dichlorosilane (SiH 2 Cl 2 ), ammonia (NH 3 ), and nitrogen such that the ratio of SiH 4  to NH 3 , or SiH 2 Cl 2  to NH 3 , is approximately ≧15. This ratio regulates the amount and distribution of each phase of the silicon-rich-nitride, namely the amount and distribution of the silicon nitride insulator (Si 3 N 4 ) and either crystalline or amorphous silicon (Si) particles. The ratio of SiH 2 Cl 2  to NH 3  has been found to be directly proportional to the refractive index of the resulting SRN material, as shown in FIG. 8. Thus, control of the SiH 2 Cl 2 /NH 3  ratio is important. For example, a SiH 2 Cl 2 /NH 3  ratio of 15 produces a SRN material with a refractive index of approximately 2.5, a value that ensures a K&gt;12. As noted previously, a deposited SRN material should preferably have a K value similar to that of the high K dielectric material, such that the advantages of the high K dielectric material are not canceled out by a passivated overlayer with a low K value.  
         [0054]    Returning to FIG. 7, the dielectric stack may then be stabilized by a rapid thermal anneal in nitrogen at  710 . A gate and gate electrode, or top plate, are deposited at  712 , depending on whether a gate dielectric stack or a storage dielectric stack is being fabricated.  
         [0055]    If a storage capacitor is being fabricated, step  708  can be optionally eliminated. That is, a passivated overlayer may not need to be included in a storage dielectric stack fabricated in accordance with the invention. Process  700  without  708  may be sufficient to achieve an improved storage capacitor stack. However, a passivated overlayer in a storage dielectric stack provides a preferably maximum achievable K value and consequently higher storage capacity.  
         [0056]    In another embodiment of a method to fabricate dielectric stacks in accordance with the invention,  704  involves depositing metal to a desired thickness and then subsequently oxidizing the entire thickness in a controlled manner to form the desired stoichiometric dielectric material. For example, aluminum may first be deposited to the desired thickness and then oxidized to form stoichiometric alumina.  
         [0057]    [0057]FIG. 9 shows yet another embodiment of a method to fabricate improved dielectric stacks in accordance with the invention. In process  900 ,  704  and  706  of process  700  are replaced by  902 . At  902 , a dielectric material is deposited directly on a prepared substrate or bottom plate. The dielectric material if preferably alumina and may be deposited by MBE, sputtering, or any other suitable method.  
         [0058]    Thus it is seen that improved gate and storage dielectric systems, and methods of their fabrication, are provided. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.

Technology Category: 5