Patent Document

[0001]    This application claims priority from Japanese Patent Application No. 2011-201707, filed on Sep. 15, 2011, the entire contents of which are herein incorporated by reference. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Embodiment described herein relate to a wiring substrate, a method of manufacturing the wiring substrate, and a semiconductor device. 
         [0004]    2. Related Art 
         [0005]    In the past, there has been a wiring substrate on which a semiconductor chip and the like are mounted. In an example of such a wiring substrate, multilayered build-up wiring is formed on both surfaces of a core substrate including through electrodes. Further, solder bumps of a semiconductor chip are flip-chip connected to connection pads, which are formed on one surface of the wiring substrate, by reflow heating (see e.g., JP-A-2004-47667 and JP-A-2005-86071). 
         [0006]    As described in the section of preliminary content to be described below, the coefficient of thermal expansion of a wiring substrate where build-up wiring layers are formed on both surfaces of a core substrate is considerably larger than that of a semiconductor chip (silicon) to be mounted. Accordingly, the wiring substrate is apt to expand or warp more than the semiconductor chip due to the reflow heating that is performed when the semiconductor chip is mounted. 
         [0007]    For this reason, particularly, if connection bumps of the semiconductor chip narrow, the connection pads of the wiring substrate are disposed to be shifted from the connection bumps of the semiconductor chip when the semiconductor chip is mounted. Accordingly, it is difficult to reliably mount the semiconductor chip. 
       SUMMARY OF THE INVENTION 
       [0008]    An illustrative aspect of the present invention is to provide a wiring substrate on which even a semiconductor chip including narrow connection bumps can be reliably mounted, a method of manufacturing the wiring substrate, and a semiconductor device. 
         [0009]    According to one or more illustrative aspects of the present invention, there is provided a wiring substrate. The wiring substrate comprises: a substrate layer made of glass or silicon and comprising: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface. 
         [0010]    According to one or more illustrative aspects of the present invention, there is provided a wiring substrate. The wiring substrate comprises: a substrate layer made of glass or silicon and comprising: a first surface and a second surface opposite to the first surface, wherein the substrate layer is formed with a through hole whose diameter is gradually decreased from the first surface to the second surface; a connection pad formed on the second surface of the substrate layer; a first wiring layer formed in the through hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. 
         [0011]    According to one or more illustrative aspects of the present invention, there is provided a semiconductor device. The semiconductor device comprises: a wiring substrate comprising: a substrate layer made of glass or silicon and comprising: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer, wherein a diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface; and a semiconductor chip mounted on the wiring substrate so as to be connected to the connection pad. 
         [0012]    According to one or more illustrative aspects of the present invention, there is provided a method of manufacturing a wiring substrate. The method comprises: (a) providing a substrate made of glass or silicon and comprising a first surface and a second surface opposite to the first surface; (b) forming a first hole in a first surface of the substrate so as not to pass through the substrate; (c) forming a first wiring layer on the first surface of the substrate and in the first hole; (d) forming an insulation layer on the first surface of the substrate to cover the first wiring layer; (e) forming a second wiring layer on the insulation layer to electrically connect the first wiring layer; (f) reducing a thickness of the substrate from the second surface of the substrate such that the first wiring layer is still covered by the substrate; (g) forming a second hole in the second surface of the substrate such that the second hole is communicated with the first hole and the first wiring layer is exposed from the second hole; and (h) forming a connection pad in the second hole such that the connection pad is electrically connected to the first wiring layer, wherein the first hole is formed in the first surface of the substrate such that a diameter of the first hole is gradually decreased from the first surface toward the second surface, and the second hole is formed in the second surface of the substrate such that a diameter of the second hole is gradually decreased from the second surface toward the first surface. 
         [0013]    According to one or more illustrative aspects of the present invention, there is provided a method of manufacturing a wiring substrate. The method comprises: (a) providing a substrate made of glass or silicon and comprising a first surface and a second surface opposite to the first surface; (b) forming a hole in a first surface of the substrate so as not to pass through the substrate; (c) forming a first wiring layer on the first surface of the substrate and in the hole; (d) forming an insulation layer on the first surface of the substrate to cover the first wiring layer; (e) forming a second wiring layer on the insulation layer to electrically connect the first wiring layer; (f) reducing a thickness of the substrate from the second surface of the substrate such that the first wiring layer formed in the hole is exposed from the second surface; and (g) forming a connection pad on the second surface of the substrate such that the connection pad is electrically connected to the first wiring layer. 
         [0014]    Other aspects and advantages of the present invention will be apparent from the following description, the drawings and the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a cross-sectional view illustrating preliminary content; 
           [0016]      FIGS. 2A to 2C  are (first) cross-sectional views illustrating a method of manufacturing a wiring substrate according to a first embodiment; 
           [0017]      FIGS. 3A to 3C  are (second) cross-sectional views illustrating the method of manufacturing the wiring substrate according to the first embodiment; 
           [0018]      FIGS. 4A and 4B  are (third) cross-sectional views illustrating the method of manufacturing the wiring substrate according to the first embodiment; 
           [0019]      FIG. 5  is a cross-sectional view of the wiring substrate according to the first embodiment; 
           [0020]      FIG. 6  is a cross-sectional view of a semiconductor device according to the first embodiment; 
           [0021]      FIG. 7  is a cross-sectional view of a wiring substrate according to a modification of the first embodiment; 
           [0022]      FIG. 8  is a cross-sectional view of a semiconductor device according to the modification of the first embodiment; 
           [0023]      FIGS. 9A to 9C  are (first) cross-sectional views illustrating a method of manufacturing a wiring substrate according to a second embodiment; 
           [0024]      FIGS. 10A and 10B  are (second) cross-sectional views illustrating the method of manufacturing the wiring substrate according to the second embodiment; 
           [0025]      FIGS. 11A and 11B  are (third) cross-sectional views illustrating the method of manufacturing the wiring substrate according to the second embodiment; 
           [0026]      FIGS. 12A and 12B  are (fourth) cross-sectional views illustrating the method of manufacturing the wiring substrate according to the second embodiment; 
           [0027]      FIG. 13  is a cross-sectional view of the wiring substrate according to the second embodiment; 
           [0028]      FIG. 14  is a cross-sectional view of a semiconductor device according to the second embodiment; 
           [0029]      FIGS. 15A and 15B  are (first) cross-sectional views illustrating a method of manufacturing a wiring substrate according to a third embodiment; 
           [0030]      FIGS. 16A and 16B  are (second) cross-sectional views illustrating the method of manufacturing the wiring substrate according to the third embodiment; 
           [0031]      FIG. 17  is a cross-sectional view of the wiring substrate according to the third embodiment; 
           [0032]      FIG. 18  is a cross-sectional view of a semiconductor device according to the third embodiment; 
           [0033]      FIG. 19  is a cross-sectional view of a wiring substrate according to a fourth embodiment; and 
           [0034]      FIG. 20  is a cross-sectional view of a semiconductor device according to the fourth embodiment. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0035]    Exemplary embodiments will be described below with reference to the accompanying drawings. 
         [0036]    Preliminary content as a base will be described prior to the description of the embodiments.  FIG. 1  is a cross-sectional view illustrating preliminary content. 
         [0037]    As shown in  FIG. 1 , a core substrate  120  made of a glass epoxy resin or the like is disposed at the middle portion of a wiring substrate  100  according to the preliminary content in a thickness direction of the wiring substrate. Through electrodes TE, which pass through the core substrate  120  in the thickness direction of the core substrate, are formed in the core substrate  120 . 
         [0038]    First wiring layers  200 , which are connected to each other by the through electrodes TE, are formed on both surfaces of the core substrate  120 . Further, interlayer insulation layers  300  in which via holes VH reaching the first wiring layers  200  are formed are formed on both surfaces of the core substrate  120 . 
         [0039]    Second wiring layers  220 , which are connected to the first wiring layers  200  through the via holes VH, are formed on the interlayer insulation layers  300  that are formed on both surfaces of the core substrate  120 . 
         [0040]    In addition, a solder resist  320 , where opening portions  320   a  are formed on connection pads P of the second wiring layer  220 , is formed on the upper interlayer insulation layer  300 . Further, the solder resist  320 , where opening portions  320   a  are formed on connection portions of the second wiring layer  220 , is formed on the lower interlayer insulation layer  300 . External connection terminals  240  are connected to the lower second wiring layer  220 . 
         [0041]    Furthermore, solder bumps  420  of a semiconductor chip  400  are flip-chip connected to the connection pads P, which are formed on the upper surface of the wiring substrate  100 , by reflow heating. The coefficient of thermal expansion of the wiring substrate  100  (interlayer insulation layers (resin)/wiring layers (copper) and the like) is larger than that of the semiconductor chip  400  (silicon). 
         [0042]    For this reason, the wiring substrate  100  expands or warps more than the semiconductor chip  400  due to the heating that is performed for the flip-chip connection between the semiconductor chip  400  and the wiring substrate  100 . As a result, the positions of the connection pads P are shifted. 
         [0043]    In particular, if the pitch of the solder bumps  420  of the semiconductor chip  400  is reduced to 100 μm or less, the connection pads P of the wiring substrate  100  are disposed to be shifted from the solder bumps  420  of the semiconductor chip  400 . Accordingly, it is difficult to reliably mount the semiconductor chip  400 . 
         [0044]    Further, the second wiring layers  220  (connection pads P) are formed on the interlayer insulation layers  300  (resin) by a semi-additive method. In detail, after seed layers (not shown) are formed on the interlayer insulation layers  300  first, plating resists (not shown) including opening portions formed at portions where the second wiring layers  220  are to be disposed are formed. 
         [0045]    After that, metal plating layers are formed by electrolytic plating where the seed layers are used as plating power-supply paths. Furthermore, after the plating resists are removed, the seed layers are etched while the metal plating layers are used as masks. 
         [0046]    Since relatively large irregularities are formed on the surfaces of the interlayer insulation layers  300  (resin), considerable over-etching is needed so that residues are not formed during the etching of the seed layers. For this reason, undercut occurs on the seed layers and the patterns of the metal plating layers are apt to become thin. 
         [0047]    Accordingly, when the “line:space” of the second wiring layers  220  (connection pads P) particularly becomes “10:10 μm” or less, the width of a finished line becomes considerably small and deviates from design specifications. Eventually, the width of the line becomes small, so that the adhesion between the wiring layer and the interlayer insulation layer is reduced and the second wiring layers  220  are partially detached from the surfaces of the interlayer insulation layers  300 . 
         [0048]    As described above, it is difficult to form a wiring layer, of which the “line:space” is “10:10 μm” or less, on a resin layer, which has irregularities, with high yield by a semi-additive method. 
         [0049]    When it is difficult to reduce the pitch of the wiring layer, it is necessary to cope with this by increasing the number of build-up wiring layers to be laminated. For this reason, the thickness of the wiring substrate is increased, so that it is difficult to cope with the demand for the reduction in size and thickness. 
         [0050]    Further, for the suppression of warpage of the whole core layer  120  of the wiring substrate  100 , the thickness of the core layer  120  of the wiring substrate  100  is set to be relatively large, that is, in the range of 400 to 800 μm. Furthermore, the diameter of each of the through electrodes TE passing through the core layer  120  is set to about 200 μm. 
         [0051]    As described above, the through electrodes TE, which are considerably thicker and longer than the first and second wiring layers  200  and  220  or the via holes VH (via conductors), formed in the core layer  120 . For this reason, since signals are apt to be reflected by the through electrodes TE on high-frequency signal transmission lines of the wiring substrate  100 , there is a concern about the degradation of high-frequency characteristics. 
         [0052]    It is possible to solve the above-mentioned problems by using wiring substrates according to embodiments to be described below. 
       First Embodiment 
       [0053]      FIGS. 2 to 4  are cross-sectional views illustrating a method of manufacturing a wiring substrate according to a first embodiment, and  FIG. 5  is a cross-sectional view of the wiring substrate according to the first embodiment. 
         [0054]    In the method of manufacturing the wiring substrate according to the first embodiment, a glass substrate  10   a  having a thickness of 0.3 to 1 mm is prepared first as shown in  FIG. 2A . Aluminoborosilicate glass, such as E-glass or T-glass, is used as an example of the glass substrate  10   a . T-glass is glass of which component ratios of SiO 2  and Al 2 O 3  are higher than those of E-glass. 
         [0055]    After that, first holes H 1  are formed from the upper surface of the glass substrate  10   a  so as not to pass through the glass substrate  10   a  as shown in  FIG. 2B . The first holes H 1  are formed by laser, a drill, a blast method, etching, or the like. 
         [0056]    For example, the diameter of an opening end of the first hole H 1 , which is opened to the surface of the glass substrate  10   a , is about 50 μm and the depth of the first hole H 1  is about 100 μm. Further, the cross-sectional shape of the first hole H 1  is a tapered shape where the diameter of an upper portion is larger than that of a bottom. 
         [0057]    After that, as shown in  FIG. 2C , a first wiring layer  20  is formed on the upper surface of the glass substrate  10   a  including the first holes H 1 . The first wiring layer  20  is formed so as to fill the first holes H 1 . 
         [0058]    The first wiring layer  20  is formed by, for example, a semi-additive method. In detail, first, a seed layer (not shown) made of copper or the like is formed on the upper surface of the glass substrate  10   a  and the inner surfaces of the first holes H 1  by electroless plating or a sputtering method. Then, a plating resist (not shown), which includes opening portions at a portion where the first wiring layer  20  is disposed, is formed. 
         [0059]    In addition, a metal plating layer made of copper or the like is formed at the opening portions of the plating resist by electrolytic plating where the seed layer is used as a plating power-supply path. At this time, the first holes H 1  of the glass substrate  10   a  are filled with the metal plating layer. 
         [0060]    After that, after the plating resist is removed, the seed layer is etched while the metal plating layer is used as a mask. Accordingly, the seed layer and the metal plating layer form the first wiring layer  20 . 
         [0061]    Subsequently, a first interlayer insulation layer  30 , which covers the first wiring layer  20 , is formed on the glass substrate  10   a  as shown in  FIG. 3A . The first interlayer insulation layer  30  is obtained by attaching a resin film, which is made of a thermosetting epoxy resin, a thermosetting polyimide resin or the like, and heating and pressing the resin film with a vacuum press or the like. 
         [0062]    Alternatively, in order to obtain the first interlayer insulation layer  30 , liquid thermosetting resin, such as epoxy or polyimide, may be applied and cured by heating. 
         [0063]    Moreover, first via holes VH 1  reaching the first wiring layer  20  are formed by laser machining that is performed on the first interlayer insulation layer  30 . Alternatively, the first interlayer insulation layer  30  may be made of a photosensitive resin and the first via holes VH 1  may be formed by photolithography. 
         [0064]    After that, as likewise shown in  FIG. 3A , a second wiring layer  22 , which is connected to the first wiring layer  20  through the first via holes VH 1  (via conductors), is formed on the first interlayer insulation layer  30  by the same method as the method of forming the first wiring layer  20 . 
         [0065]    After that, as shown in  FIG. 3B , a second interlayer insulation layer  32  in which second via holes VH 2  reaching the second wiring layer  22  are formed is formed on the first interlayer insulation layer  30  by the same method as the method of forming the first interlayer insulation layer  30 . 
         [0066]    In addition, as likewise shown in  FIG. 3B , a third wiring layer  24 , which is connected to the second wiring layer  22  through the second via holes VH 2  (via conductors), is formed on the second interlayer insulation layer  32  through the repetition of the same machining as described above. 
         [0067]    Subsequently, as shown in  FIG. 3C , a third interlayer insulation layer  34  in which third via holes VH 3  reaching the third wiring layer  24  are formed is formed on the second interlayer insulation layer  32  through the repetition of the same machining as described above. 
         [0068]    In addition, as likewise shown in  FIG. 3C , a fourth wiring layer  26 , which is connected to the third wiring layer  24  through the third via holes VH 3  (via conductors), is formed on the third interlayer insulation layer  34  through the repetition of the same machining as described above. 
         [0069]    Then, a solder resist  36 , where opening portions  36   a  are formed on connection portions of the fourth wiring layer  26 , is formed. After that, a contact layer is formed by sequentially forming a nickel plating layer and a gold plating layer on the connection portions of the fourth wiring layer  26  from below as necessary. 
         [0070]    Since the glass substrate  10   a  has sufficient rigidity, the glass substrate  10   a  functions as a support that prevents warpage in the steps of manufacturing the build-up wiring layers (the second to fourth wiring layers  22 ,  24 , and  26 ). 
         [0071]    Subsequently, as shown in  FIG. 4A , a structure shown in  FIG. 3C  is turned over and the thickness of the entire structure is reduced by machining that is performed in the thickness direction on the surface of the glass substrate  10   a  opposite to the surface of the glass substrate  10   a  on which the first holes H 1  are formed. Accordingly, a glass substrate layer  10  of which the thickness is reduced to the range of 100 to 300 μm is obtained. 
         [0072]    Polishing such as CMP, dry etching, wet etching, blasting, or the like may be used as a method of machining the glass substrate  10   a.    
         [0073]    As described below, in this embodiment, through holes are formed by making the first holes H 1 , which are formed from one surface of the glass substrate layer  10 , communicate with second holes that are formed from the other surface of the glass substrate layer  10 . For this reason, the thickness of the glass substrate  10   a  is reduced so that the glass substrate layer  10  remains on the first wiring layer  20  in the first hole H 1 . 
         [0074]    After that, as shown in  FIG. 4B , second holes H 2  reaching the first wiring layer  20  formed in the first holes H 1  are formed by machining that is performed on portions of the glass substrate layer  10  formed on the first holes H 1 . In an example of  FIG. 4B , the diameter of an opening end of the second hole H 2 , which is opened to the surface of the glass substrate layer  10 , is set to about 50 μm and the depth of the second hole H 2  is set to about 100 μm. 
         [0075]    In the process shown in  FIG. 4B , after forming the second hole H 2 , an exposed surface of the first wiring layer  20  formed in the first hole H 1  is roughened by laser irradiation. 
         [0076]    The cross-sectional shape of the second hole H 2  is a tapered shape where the diameter of an upper portion is larger than that of a bottom. In this way, the first and second holes H 1  and H 2  are disposed symmetrically to a middle portion of the glass substrate layer  10  in the thickness direction of the glass substrate layer as the axis of symmetry. 
         [0077]    Subsequently, as shown in  FIG. 5 , connection pads P, which are connected to the first wiring layer  20  so as to fill the second holes H 2 , are formed on the upper surface of the glass substrate layer  10  from the inside of the second holes H 2 . The connection pads P may be disposed so as to be isolated in the shape of an island, and may be disposed at end portions of lines that are formed so as to be led from the second holes H 2  to the upper surface of the glass substrate layer  10 . 
         [0078]    The connection pads P are made of copper or the like, and a contact layer may be formed on the surfaces of the connection pads by sequentially forming a nickel plating layer and a gold plating layer from below as necessary. 
         [0079]    The connection pads P are formed on the glass substrate layer  10 , of which the surface is smooth, by a semi-additive method that has been described in the step of forming the first wiring layer  20 . For this reason, when the seed layer is etched by a semi-additive method, it is possible to considerably reduce the amount of over-etching as compared to a case where a seed layer is formed on a resin layer having large irregularities. As a result, it is possible to form connection pads P that has a small pitch where the “line:space” is “10:10 μm” or less. 
         [0080]    As described above, a wiring substrate  1  according to the first embodiment is obtained. 
         [0081]    As shown in  FIG. 5 , in the wiring substrate  1  according to the first embodiment, the first holes H 1  are formed from the lower surface of the glass substrate layer  10  to the middle portion of the glass substrate layer  10  in the thickness direction and the second holes H 2  are formed from the upper surface of the glass substrate layer  10  to the middle portion of the glass substrate layer  10  in the thickness direction. The cross-sectional shape of the first hole H 1  is an inverted tapered shape where the diameter of a lower portion (opening end) is larger than that of an upper portion (bottom). Further, the cross-sectional shape of the second hole H 2  is a tapered shape where the diameter of an upper portion (opening end) is larger than that of a lower portion (bottom). 
         [0082]    The first and second holes H 1  and H 2  communicate with each other at the middle portion of the glass substrate layer  10  in the thickness direction. In this way, the first and second holes H 1  and H 2  are disposed symmetrically to each other in the thickness direction of the glass substrate layer  10 , so that through holes TH passing through the glass substrate layer  10  are formed. 
         [0083]    In addition, the first wiring layer  20  is formed on the lower surface of the glass substrate layer  10  from the first holes H 1  so as to fill the first holes H 1 . Further, the connection pads P are formed on the upper surface of the glass substrate layer  10  from the second holes H 2  so as to fill the second holes H 2 . The first wiring layer  20  and the connection pads P form the through electrodes TE that pass through the glass substrate layer  10 . 
         [0084]    As described above, in the first embodiment, the first and second holes H 1  and H 2  are formed from both surfaces of the glass substrate layer  10 , respectively, so that the through holes TH are obtained. 
         [0085]    When through holes having a diameter of 50 μm and a depth of 200 μm are formed from one surface of the glass substrate layer  10  unlike this embodiment, an aspect ratio is large, that is, 4 (depth/diameter). Accordingly, it is not easy to form the through holes, so that there is a concern about the reduction in production yield. 
         [0086]    Moreover, when the aspect ratio of the through hole is large, voids are formed when the through hole is to be filled with the metal plating layer in the above-mentioned semi-additive method. For this reason, yield is apt to deteriorate. 
         [0087]    However, in this embodiment, the first and second holes H 1  and H 2  having a diameter of 50 μm are formed from both surfaces of the glass substrate layer  10  with a depth of 100 μm, and the through holes TH are formed by making the first and second holes H 1  and H 2  communicate with each other. For this reason, since the aspect ratio (depth/diameter) of each of the first and second holes H 1  and H 2  is small, that is, 2 (depth/diameter), it is easy to form the through holes. Accordingly, it is possible to improve production yield. 
         [0088]    In addition, even when the first and second holes H 1  and H 2  are to be filled with the metal plating layer, the formation of voids or the like is avoided since the aspect ratio is small. Accordingly, it is possible to reliably form the wiring layer or the connection pads. 
         [0089]    It is preferable that the first and second holes H 1  and H 2  be connected to each other at the middle position of the glass substrate layer  10  in the thickness direction. In this case, the aspect ratios of the first and second holes H 1  and H 2  are reduced. For this reason, since the formation of voids is prevented when the first and second holes H 1  and H 2  are to be filled with the metal plating layer, it is preferable that the first and second holes H 1  and H 2  be connected to each other at the middle position of the glass substrate layer  10  in the thickness direction. 
         [0090]    However, there is no problem even though the first and second holes H 1  and H 2  are connected to each other while being vertically shifted from the middle position of the glass substrate layer  10  in the thickness direction by a distance corresponding to about ±20% of the thickness of the glass substrate layer  10 . 
         [0091]    Further, when the bottom of one hole of the first and second holes H 1  and H 2  and the bottom of the other hole thereof are connected to each other, there is no problem even though the center of the bottom of the other hole is horizontally shifted from the center of the bottom of one hole by a distance corresponding to about ±20% of the diameter of one hole. 
         [0092]    The same applies to the case where a silicon substrate layer is used instead of the glass substrate layer  10  as in a second embodiment to be described below. 
         [0093]    The first interlayer insulation layer  30  in which the first via holes VH 1  reaching the first wiring layer  20  are formed is formed beneath the first wiring layer  20  that is formed on the lower surface of the glass substrate layer  10 . Further, the second wiring layer  22 , which is connected to the first wiring layer  20  through the first via holes VH 1  (via conductors), is formed beneath the first interlayer insulation layer  30 . 
         [0094]    Likewise, the second interlayer insulation layer  32  in which the second via holes VH 2  reaching the second wiring layer  22  are formed is formed beneath the second wiring layer  22 . Furthermore, the third wiring layer  24 , which is connected to the second wiring layer  22  through the second via holes VH 2  (via conductors), is formed beneath the second interlayer insulation layer  32 . 
         [0095]    Likewise, the third interlayer insulation layer  34  in which the third via holes VH 3  reaching the third wiring layer  24  are formed is formed beneath the third wiring layer  24 . Moreover, the fourth wiring layer  26 , which is connected to the third wiring layer  24  through the third via holes VH 3  (via conductors), is formed beneath the third interlayer insulation layer  34 . In addition, the solder resist  36 , where the opening portions  36   a  are formed on the connection portions of the third wiring layer  24 , is formed beneath the third interlayer insulation layer  34 . 
         [0096]    The connection pads P and the respective wiring layers  20 ,  22 ,  24 , and  26  include portions that fill the holes H 1  and H 2  or the via holes VH 1  to VH 3 , and wiring pattern portions that are formed on the glass substrate layer  10  or the interlayer insulation layers  30 ,  32 , and  34 , respectively. 
         [0097]    In an example of  FIG. 5 , three build-up wiring layers connected to the first wiring layer  20  are laminated beneath the glass substrate layer  10 . However, the number of build-up wiring layers, which are connected to the first wiring layer  20 , may be arbitrarily set to n (n is an integer of 1 or more). 
         [0098]    Next, a method of flip-chip connecting a semiconductor chip to the wiring substrate  1  according to this embodiment will be described. As shown in  FIG. 6 , solder bumps  42  of a semiconductor chip  40  are disposed on the connection pads P of the wiring substrate  1  of  FIG. 5  and are subjected to reflow heating. 
         [0099]    Accordingly, the solder bumps  42  of the semiconductor chip  40  are flip-chip connected to the connection pads P of the wiring substrate  1 . In addition, external connection terminals  28  such as solder balls are formed on the fourth wiring layer  26 . A gap between the semiconductor chip  40  and the wiring substrate  1  may be filled with an underfill resin. 
         [0100]    As a result, a semiconductor device  5  according to the first embodiment is obtained. 
         [0101]    In this case, the mounting surface of the wiring substrate  1  on which the semiconductor chip  40  is to be mounted is formed of the glass substrate layer  10  of which the coefficient of thermal expansion is similar to the coefficient of thermal expansion of the semiconductor chip (silicon), and the connection pads P are formed on the glass substrate layer  10 . 
         [0102]    The coefficient of thermal expansion of each of the glass substrate layer  10  and the semiconductor chip  40  is in the range of 3 to 6 ppm/° C. Further, the coefficient of thermal expansion of the glass substrate layer  10  is in the range of about ±30% of the coefficient of thermal expansion of the semiconductor chip  40 . 
         [0103]    For this reason, a problem that the wiring substrate  1  expands or warps more than the semiconductor chip  40  due to the heating performed for the flip-chip connection of the semiconductor chip  40  is solved. 
         [0104]    Accordingly, even if the pitch of the solder bumps  42  of the semiconductor chip  40  is reduced to 100 μm or less, it is possible to accurately dispose the solder bumps  42  of the semiconductor chip  40  on the connection pads P of the wiring substrate  1 . 
         [0105]    Further, as described above, the through holes TH of the glass substrate layer  10  are obtained by making the first and second holes H 1  and H 2 , which are formed from both surfaces of the glass substrate layer  10 , communicate with each other. The diameter of the through hole TH is set to about 50 μm and the depth of the through hole TH is set in the range of about 100 to 300 μm. 
         [0106]    For this reason, it is possible to make the diameter and length of the through electrode TE be smaller than those of the through electrode TE (diameter: 200 μm, length: 400 to 800 μm) that is formed in the core substrate  120  of the wiring substrate  100  described in the preliminary content. 
         [0107]    Accordingly, since signals are not easily reflected by the through electrodes TE on high-frequency signal transmission lines of the wiring substrate  1  the degradation of high-frequency characteristics is prevented. 
         [0108]    Moreover, since the glass substrate layer  10  having high rigidity is used as a substrate, it is possible to prevent the occurrence of warpage of the wiring substrate  1  even though thermal stress is generated in the wiring substrate  1 . 
         [0109]    Further, since it is possible to reduce the thickness of the glass substrate layer  10 , which functions as a substrate, to the range of 100 to 300 μm, it is possible to make the entire wiring substrate  1  be thinner than the wiring substrate  100  of the preliminary content. 
         [0110]    A wiring substrate  1   a  according to a modification of the first embodiment is shown in  FIG. 7 . As shown in  FIG. 7 , when connection pads are formed in second holes H 2  of a glass substrate layer  10 , concave connection pads PX may be formed on the inner surfaces of the second holes H 2  so that the second holes H 2  are not filled and holes remain in the second holes H 2 . The concave connection pads PX are made of copper (Cu) or gold (Au). 
         [0111]    In a method of forming the concave connection pads PX, first, a thin metal layer made of copper or gold is formed on the upper surface of the glass substrate layer  10  and the inner surfaces of the second holes H 2  by a sputtering method or the like. After that, the metal layer is patterned by photolithography and etching so that the concave connection pads PX remain on the inner surfaces of the second holes H 2 . Accordingly, the concave connection pads PX where the metal layer is formed along the inner surfaces of the second holes H 2  are obtained. 
         [0112]    Alternatively, the concave connection pads PX may be formed by a semi-additive method or electroless plating. 
         [0113]    In the wiring substrate  1   a  according to the modification, a first wiring layer  20  and the concave connection pads PX form through electrodes TE. 
         [0114]    When the wiring substrate  1   a  according to the modification is employed, a semiconductor chip  40  including metal bumps  44  made of copper (Cu) or gold (Au) is used. 
         [0115]    Further, as shown in  FIG. 8 , the metal bumps  44  of the semiconductor chip  40  are fitted and connected to the concave connection pads PX of the wiring substrate  1   a . The metal bumps  44  of the semiconductor chip  40  and the concave connection pads PX of the wiring substrate  1   a  are electrically connected to each other by copper-copper or gold-gold metal bonding. Furthermore, external connection terminals  28  are formed by mounting solder balls on the fourth wiring layer  26 . 
         [0116]    As a result, a semiconductor device  5   a  according to the modification of the first embodiment is obtained. 
       Second Embodiment 
       [0117]      FIGS. 9 to 12  are cross-sectional views illustrating a method of manufacturing a wiring substrate according to a second embodiment, and  FIG. 13  is a cross-sectional view of the wiring substrate according to the second embodiment. 
         [0118]    The second embodiment is characterized in that a silicon substrate is used instead of the glass substrate of the first embodiment. The detailed description of the same steps and elements as those of the first embodiment will be omitted in the second embodiment. 
         [0119]    In the method of manufacturing the wiring substrate according to the second embodiment, a silicon substrate  50   a  having a thickness of 0.3 to 1 mm is prepared first as shown in  FIG. 9A  and first holes H 1  are formed from the upper surface of the silicon substrate  50   a  by the same method as the method, which is used in the first embodiment, so as not to pass through the silicon substrate  50   a.    
         [0120]    Then, an insulation layer  52  formed of a silicon oxide layer is formed on both surfaces of the silicon substrate  50   a  and the inner surfaces of the first holes H 1  as shown in  FIG. 9B  by thermally oxidizing the silicon substrate  50   a . Alternatively, a silicon oxide layer or silicon nitride layer may be formed on the surface of the silicon substrate  50   a , on which the first holes H 1  are formed, by a CVD method and may be used as the insulation layer  52 . 
         [0121]    Next, as shown in  FIG. 9C , a first wiring layer  20  is formed on portions of the insulation layer  52 , which include the first holes H 1  of the silicon substrate  50   a , by the same method as the method used in the first embodiment. The first wiring layer  20  is formed so as to fill the first holes H 1 . 
         [0122]    Subsequently, as shown in  FIG. 10A , three build-up wiring layers (second, third, and fourth wiring layers  22 ,  24 , and  26 ) connected to the first wiring layer  20  are formed by performing the same steps as the steps of  FIGS. 3A to 3C  of the first embodiment. 
         [0123]    Subsequently, as shown in  FIG. 10B , a structure shown in  FIG. 10A  is turned over and the thickness of the entire silicon substrate  50   a  is reduced by machining that is performed on the insulation layer  52  and the silicon substrate  50   a  in the thickness direction. Accordingly, a silicon substrate layer  50  of which the thickness is reduced to the range of about 100 to 300 μm is obtained. At this time, as in the first embodiment, the silicon substrate  50   a  is subjected to machining so that the silicon substrate layer  50  remains on the first wiring layer  20 . 
         [0124]    After that, as shown in  FIG. 11A , second holes H 2  reaching the first wiring layer  20  are formed by machining that is performed on portions of the silicon substrate layer  50  and the insulation layer  52  formed on the first holes H 1 . 
         [0125]    Moreover, as shown in  FIG. 11B , an insulation layer  54  is obtained by forming a silicon oxide layer or a silicon nitride layer on the upper surface of the silicon substrate layer  50  and the inner surfaces of the second holes H 2  by a CVD method. 
         [0126]    Next, as shown in  FIG. 12A , a resist  56  in which opening portions  56   a  are formed at the portions corresponding to the second holes H 2  is patterned by photolithography. For example, a dry film resist is attached to the insulation layer and exposure and development are performed, so that the resist  56  including the opening portions  56   a  is obtained. In addition, the insulation layer  54 , which is formed at the bottoms of the second holes H 2 , is etched and removed by anisotropic dry etching that is performed through the opening portions  56   a  of the resist  56 . After that, the resist  56  is removed. 
         [0127]    As a result, as shown in  FIG. 12B , the insulation layer  54  remains on the upper surface of the silicon substrate layer  50  and the side walls of the second holes H 2  and the first wiring layer  20  is exposed to the bottoms of the second holes H 2 . 
         [0128]    In this way, the through holes TH passing through the silicon substrate layer  50  are obtained from the first and second holes H 1  and H 2 . 
         [0129]    Meanwhile, besides the method of patterning the insulation layer  54  by photolithography and etching, the insulation layer  54  may be formed of a photosensitive insulating resin layer. In this case, a liquid or paste photosensitive insulating resin is applied on the silicon substrate layer  50  of  FIG. 11A . Then, the insulating resin applied on the bottoms of the second holes H 2  is removed by exposure and development, and the photosensitive insulating resin is cured by heating. Accordingly, likewise, it is possible to form the insulation layer  54  so that the first wiring layer  20  is exposed to the bottoms of the second holes H 2 . 
         [0130]    A phenol photosensitive resin, a polyimide photosensitive resin, a polybenzoxazole photosensitive resin, and the like may be used as the photosensitive insulating resin. 
         [0131]    The thickness of the insulation layer  54  depends on the diameter or depth of the second hole H 2 , but is set in the range of, for example, 2 to 50 μm. 
         [0132]    Subsequently, as shown in  FIG. 13 , as in the first embodiment, connection pads P electrically connected to the first wiring layer  20  are formed on portions of the insulation layer  54  that include the second holes H 2  of the silicon substrate layer  50 . The connection pads P are formed so as to fill the second holes H 2 . 
         [0133]    As a result, a wiring substrate  2  according to the second embodiment is obtained. 
         [0134]    As shown in  FIG. 13 , in the wiring substrate  2  according to the second embodiment, the silicon substrate layer  50  is used instead of the glass substrate layer  10  of the wiring substrate  1  according to the first embodiment. 
         [0135]    Further, as in the first embodiment, through holes TH are formed by making the first and second holes H 1  and H 2 , which are formed from both surfaces of the silicon substrate layer  50 , communicate with each other. The insulation layers  52  and  54  are formed on both surfaces of the silicon substrate layer  50  and the inner surfaces of the through holes TH. 
         [0136]    Furthermore, the first wiring layer  20  is formed on the insulation layer  52  of the lower surface of the silicon substrate layer  50  from the first holes H 1  so as to fill the first holes H 1 . Moreover, the connection pads P connected to the first wiring layer  20  are formed on the insulation layer  54  of the upper surface of the silicon substrate layer  50  from the second holes H 2  so as to fill the second holes H 2 . 
         [0137]    The first wiring layer  20  and the connection pads P form the through electrodes TE that pass through the silicon substrate layer  50 . In addition, as in the first embodiment, three build-up wiring layers (second, third, and fourth wiring layers  22 ,  24 , and  26 ) connected to the first wiring layer  20  are formed under the silicon substrate layer  50 . 
         [0138]    The wiring substrate  2  according to the second embodiment has the same advantages as the advantages of the wiring substrate according to the first embodiment. 
         [0139]    Further, as shown in  FIG. 14 , as in the first embodiment, solder bumps  42  of a semiconductor chip  40  are flip-chip connected to the connection pads P of the wiring substrate  2  by reflow heating. Furthermore, external connection terminals  28  are formed by mounting solder balls on the fourth wiring layer  26 . 
         [0140]    As a result, a semiconductor device  6  according to the second embodiment is obtained. 
         [0141]    In this case, the mounting surface of the wiring substrate  2  on which the semiconductor chip  40  is to be mounted is formed of the silicon substrate layer  50  of which the coefficient of thermal expansion is the same as the coefficient of thermal expansion of the semiconductor chip  40  (silicon), and the connection pads P are formed on the silicon substrate layer  50 . 
         [0142]    The coefficient of thermal expansion of each of the silicon substrate layer  50  and the semiconductor chip  40  is in the range of 3 to 6 ppm/° C. Further, the coefficient of thermal expansion of the silicon substrate layer  50  is in the range of about ±30% of the coefficient of thermal expansion of the semiconductor chip  40 . 
         [0143]    For this reason, a problem that the wiring substrate  2  expands or warps more than the semiconductor chip  40  due to the heating performed for the flip-chip connection of the semiconductor chip  40  is solved. 
         [0144]    Accordingly, even if the pitch of the solder bumps  42  of the semiconductor chip  40  is reduced to 100 μM or less, it is possible to accurately dispose the solder bumps  42  of the semiconductor chip  40  on the connection pads P of the wiring substrate  2 . 
         [0145]    Further, as in the case where the glass substrate layer  10  of the first embodiment is used, it is possible to form the connection pads P having a small pitch by a semi-additive method since the surface of the silicon substrate layer  50  is smoother than the surface of the insulation layer made of a resin. 
         [0146]    Furthermore, since it is possible to make the diameter and length of the through electrode TE, which is formed in the silicon substrate layer  50 , be small as in the case where the glass substrate layer  10  of the first embodiment is used, the degradation of high-frequency characteristics is prevented. 
         [0147]    Even in the wiring substrate  2  according to the second embodiment, concave connection pads may be formed on the inner surfaces of the second holes H 2  and the metal bumps of the semiconductor chip may be fitted to the concave connection pads as in the wiring substrate  1   a  according to the modification of the first embodiment. 
       Third Embodiment 
       [0148]      FIGS. 15 and 16  are cross-sectional views illustrating a method of manufacturing a wiring substrate according to a third embodiment, and  FIG. 17  is a cross-sectional view of the wiring substrate according to the third embodiment. 
         [0149]    In the first and second embodiments, the first and second holes are formed from both surfaces of the glass substrate layer and the silicon substrate layer, and the through holes are formed by making the first and second holes communicate with each other. Accordingly, the formation of the holes and filling the holes with the metal plating layer are facilitated by the reduction of the aspect ratio of each of the holes. 
         [0150]    A case where holes are formed from only one surface of a substrate layer to form through holes for the reduction in cost when through holes formed in a glass substrate layer or a silicon substrate layer have a relatively large diameter will be described in the third embodiment. 
         [0151]    The detailed description of the same steps and elements as those of the first embodiment will be omitted in the third embodiment. 
         [0152]    In the method of manufacturing the wiring substrate according to the third embodiment, a glass substrate  10   a  is prepared first as shown in  FIG. 15A  as in the first embodiment, and holes H are formed from the upper surface of the glass substrate  10   a  by machining so as not to pass through the glass substrate  10   a.    
         [0153]    In the third embodiment, the diameter of each of the through holes, which are finally formed in a glass substrate layer, is about 100 μm and is set to be considerably larger than the diameter (50 μm) of each of the through holes of the glass substrate layer and the silicon substrate layer of the first and second embodiments. The diameter of the through holes means the diameter of an end of through hole that is opened to the surface of the glass substrate  10   a.    
         [0154]    Accordingly, if the diameter of the hole H is set to 100 μm and the depth of the hole H is set to 200 μm, the aspect ratio (depth/diameter) of the hole H becomes 2. Accordingly, even though the holes H are formed from only one surface of the glass substrate  10   a , the formation of the holes H is facilitated. 
         [0155]    The cross-sectional shape of the hole H is set to a tapered shape where the diameter of an upper portion is larger than that of a bottom. 
         [0156]    After that, as shown in  FIG. 15B , as in the first embodiment, a first wiring layer  20  is formed on portions of the glass substrate  10   a  including the holes H so as to fill the holes H. 
         [0157]    Subsequently, as shown in  FIG. 16A , three build-up wiring layers (second, third, and fourth wiring layers  22 ,  24 , and  26 ) connected to the first wiring layer  20  are formed by performing the same steps as the steps of  FIGS. 3A to 3C  of the first embodiment. 
         [0158]    After that, as shown in  FIG. 16B , a structure shown in  FIG. 16A  is turned over and the glass substrate  10   a  is made thin by machining that is performed on the exposed surface of the glass substrate  10   a  until the first wiring layer  20  formed at the bottoms of the holes H is exposed to the outside. Accordingly, a thin glass substrate layer  10  is obtained and the first wiring layer  20  is exposed to the upper surface of the glass substrate layer  10 . Further, the holes H are changed into through holes TH passing through the glass substrate layer  10 , and the first wiring layer  20  functions as through electrodes TE that fill the through holes TH. 
         [0159]    After that, as shown in  FIG. 17 , connection pads P electrically connected to the first wiring layer  20  are formed on the upper surface of the glass substrate layer  10  from the upper portions of the holes H (first wiring layer  20 ). 
         [0160]    As a result, a wiring substrate  3  according to the third embodiment is obtained. 
         [0161]    As described above, in the third embodiment, first, the tapered holes H are formed from one surface of the glass substrate  10   a  by laser or the like so as not to pass through the glass substrate  10   a . In addition, after the first wiring layer  20  is formed in the holes H, the glass substrate  10   a  is made thin by machining that is performed on the other surface of the glass substrate  10   a  until the first wiring layer  20  is exposed to the outside. As a result, the through holes TH are obtained. 
         [0162]    For this reason, in the wiring substrate  3  according to the third embodiment, the inverted tapered through holes TH each of which has the diameter of an upper portion smaller than that of a lower portion are formed in the glass substrate layer  10 . The first wiring layer  20  is formed on the lower surface of the glass substrate layer  10  from the inside of the through holes TH so as to fill the through holes TH. Moreover, the connection pads P connected to the first wiring layer  20  are formed on the upper surface of the glass substrate layer  10 . 
         [0163]    Further, as in the first embodiment, three build-up wiring layers (second, third, and fourth wiring layers  22 ,  24 , and  26 ) connected to the first wiring layer  20  are formed under the glass substrate layer  10 . 
         [0164]    Furthermore, as shown in  FIG. 18 , as in the first embodiment, solder bumps  42  of a semiconductor chip  40  are flip-chip connected to the connection pads P of the wiring substrate  3  by reflow heating. In addition, external connection terminals  28  are formed by mounting solder balls on the fourth wiring layer  26 . 
         [0165]    As a result, a semiconductor device  7  according to the third embodiment is obtained. 
         [0166]    The wiring substrate  3  according to the third embodiment has the same advantages as the advantages of the wiring substrate according to the first embodiment. Moreover, the third embodiment is useful when the through holes TH having a relatively large diameter are formed in the glass substrate layer  10 . In this case, since the number of steps is smaller than the number of steps of each of the first and second embodiments, it is possible to reduce cost. 
       Fourth Embodiment 
       [0167]      FIG. 19  is a cross-sectional view of a wiring substrate according to a fourth embodiment. The fourth embodiment is characterized such that a silicon substrate layer is used instead of the glass substrate layer of the third embodiment. The detailed description of the same steps and elements as those of the first embodiment will be omitted in the fourth embodiment. 
         [0168]    As shown in  FIG. 19 , in a wiring substrate  4  according to the fourth embodiment, the glass substrate layer  10  of the wiring substrate  3  according to the third embodiment shown in  FIG. 17  is substituted with a silicon substrate layer  50 . Further, as in the third embodiment, inverted tapered through holes TH, each of which has the diameter of an upper portion smaller than that of a lower portion, are formed in the silicon substrate layer  50 . 
         [0169]    In the fourth embodiment, insulation layers  52  and  54  are formed on both surfaces of the silicon substrate layer  50  and the inner surfaces of the through holes TH. Further, opening portions  54   a  are formed in the insulation layer  54  on the first wiring layer  20  that are formed in the through holes TH. Connection pads P are connected to the first wiring layer  20  through the opening portions  54   a  of the insulation layer  54 . 
         [0170]    When the wiring substrate  4  according to the fourth embodiment is manufactured, a silicon substrate is used in the step of the third embodiment shown in  FIG. 15A  and holes H are formed. Then, the insulation layer  52  is formed on the upper surface of the silicon substrate and the inner surfaces of the holes H by thermal oxidation or a CVD method. 
         [0171]    Moreover, after the step shown in  FIG. 16B , the insulation layer  54  is formed on the upper surface of the silicon substrate layer  50  by a CVD method. The insulation layer  54  may be patterned to form the opening portions  54   a  on the first wiring layer  20 . 
         [0172]    Further, as shown in  FIG. 20 , as in the first embodiment, solder bumps  42  of a semiconductor chip  40  are flip-chip connected to the connection pads P of the wiring substrate  4  by reflow heating. Furthermore, external connection terminals  28  are formed by mounting solder balls on the fourth wiring layer  26 . 
         [0173]    As a result, a semiconductor device  8  according to the fourth embodiment is obtained. 
         [0174]    The wiring substrate  4  according to the fourth embodiment has the same advantages as the advantages of the wiring substrate according to the first embodiment. Moreover, like the third embodiment, the fourth embodiment is useful when the through holes TH having a relatively large diameter are formed in the silicon substrate layer  50 . In this case, since the number of steps is smaller than the number of steps of each of the first and second embodiments, it is possible to reduce cost. 
         [0175]    While the present invention has been shown and described with reference to certain exemplary embodiments thereof, other implementations are within the scope of the claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Category: 5