Patent Document

RELATED APPLICATIONS 
       [0001]    This application claims the benefit of the filing date of U.S. Provisional Application Ser. No. 61/420,538 filed on Dec. 7, 2011 pursuant to 35 U.S.C.§119(e). The entire content of this application is hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    The degree of integration of semiconductor integrated circuits, namely, integrated circuits using metal oxide semiconductor (MOS) transistors, has been increasing. The increasing degree of integration of such integrated circuits results in MOS transistors having small sizes reaching nano-scale dimensions. Inverter circuits are fundamental circuits of digital circuits, and the increasing decrease in the size of MOS transistors included in inverter circuits causes difficulty in suppressing leak currents, leading to problems of reduced reliability due to hot carrier effects and of the reduction in the area of the circuits being prevented because of the requirements of the secure retention of necessary currents. To overcome the above problems, a surrounding gate transistor (SGT) having a structure in which a source, gate, and drain are arranged vertically with respect to a substrate and in which the gate surrounds an island-shaped semiconductor layer has been proposed (for example, Japanese Unexamined Patent Application Publications No. 2-71556, No. 2-188966, and No. 3-145761). 
         [0006]    It is known that in a static memory cell, the current driving force of a driver transistor is made double the current driving force of an access transistor to ensure operational stability (H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, “Demonstration of Highly Scaled FinFET SRA M Cells with High-κ/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond”, IEDM, pp. 237-240, 2008). 
         [0007]    To construct a static memory cell using the above SGT, two driver transistors are used because of the need for a double gate width in order to make it feasible to make the current driving force of a driver transistor double the current driving force of an access transistor to ensure operational stability. This leads to an increase in memory cell area. 
         [0008]    Further, an SGT production method has been proposed of forming a pillar-shaped semiconductor layer, depositing a gate conductive film on the pillar-shaped semiconductor layer, performing planarization, and then etching back the gate conductive film to obtain a desired length (Japanese Unexamined Patent Application Publication No. 2009-182317). This high-degree-of-integration, high-performance, and high-yield SGT production method allows the physical gate length of the SGT to be kept uniform over all the transistors on a wafer. 
         [0009]    Additionally, the increasing decrease in the size of static memory cells reduces the gate capacitance or diffusion layer capacitance of a MOS transistor to be connected to a storage node because of the reduction in dimensions. In this case, if the static memory cell is irradiated with radiation from the outside, electron-hole pairs are generated in a semiconductor substrate along the path of radiation, and at least the electrons or holes of the electron-hole pairs flow into a diffusion layer that forms the drain, causing data inversion. Thus, a soft-error phenomenon occurs in that data cannot be correctly held. The soft-error phenomenon has become a serious problem in recent static memory cells whose sizes have been reduced because as the decrease in the size of memory cells increases, the reduction in the gate capacitance or diffusion layer capacitance of the MOS transistor to be connected to the storage node becomes more noticeable than the electron-hole pairs generated by radiation. Therefore, it has been reported that a capacitor is formed in a storage node of a static memory cell to ensure sufficient electrical charges in the storage node so that the occurrence of soft errors can be avoided to ensure operational stability (Japanese Unexamined Patent Application Publication No. 2008-227344). 
       SUMMARY OF THE INVENTION 
       [0010]    Accordingly, the present invention provides a high-degree-of-integration, operational stability-secured static memory cell using an SGT. 
         [0011]    In an aspect of the present invention, a semiconductor device includes a static memory cell having six MOS transistors arranged on a substrate. The six MOS transistors include first and second NMOS access transistors for accessing a memory, third and fourth NMOS driver transistors for driving a storage node that holds data of the memory cell, and first and second PMOS load transistors that supply charges for holding the data of the memory cell. Each of the first and second NMOS access transistors for accessing the memory has a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer is arranged between the first diffusion layer and the second diffusion layer, and the pillar-shaped semiconductor layer has a side wall on which a gate is formed. Each of the third and fourth NMOS driver transistors for driving the storage node that holds the data of the memory cell has a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer is arranged between the third diffusion layer and the fourth diffusion layer, and the pillar-shaped semiconductor layer has a side wall on which a gate is formed. Each of the first and second PMOS load transistors that supply the charges for holding the data of the memory cell has a fifth diffusion layer, a pillar-shaped semiconductor layer, and a sixth diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer is arranged between the fifth diffusion layer and the sixth diffusion layer, and the pillar-shaped semiconductor layer has a side wall on which a gate is formed. The first diffusion layers, the third diffusion layers, and the fifth diffusion layers are arranged so as to be electrically insulated from the substrate. A length between an upper end of the third diffusion layer and a lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors is shorter than a length between an upper end of the first diffusion layer and a lower end of the second diffusion layer of each of the first and second NMOS access transistors. 
         [0012]    In another aspect of the present invention, a semiconductor device includes a static memory cell having six MOS transistors arranged on a substrate. The six MOS transistor include first and second NMOS access transistors for accessing a memory, third and fourth NMOS driver transistors that drive a storage node for holding data of the memory cell, and first and second PMOS load transistors that supply charges for holding the data of the memory cell. Each of the first and second NMOS access transistors for accessing the memory has a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer is arranged between the first diffusion layer and the second diffusion layer, and the pillar-shaped semiconductor layer has a side wall on which a gate is formed. Each of the third and fourth NMOS driver transistors for driving the storage node that holds the data of the memory cell has a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer is arranged between the third diffusion layer and the fourth diffusion layer, and the pillar-shaped semiconductor layer has a side wall on which a gate is formed. Each of the first and second PMOS load transistors that supply the charges for holding the data of the memory cell has a fifth diffusion layer, a pillar-shaped semiconductor layer, and a sixth diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer is arranged between the fifth diffusion layer and the sixth diffusion layer, and the pillar-shaped semiconductor layer has a side wall on which a gate is formed. The first diffusion layers, the third diffusion layers, and the fifth diffusion layers are arranged so as to be electrically insulated from the substrate. A length between an upper end of the third diffusion layer and a lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors is shorter than a length between an upper end of the fifth diffusion layer and a lower end of the sixth diffusion layer of each of the first and second PMOS load transistors. 
         [0013]    Preferably, the length between the upper end of the first diffusion layer and the lower end of the second diffusion layer of each of the first and second NMOS access transistors is within a range of 1.3 times to three times the length between the upper end of the third diffusion layer and the lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors. 
         [0014]    Preferably, the length between the upper end of the fifth diffusion layer and the lower end of the sixth diffusion layer of each of the first and second PMOS load transistors is within a range of 1.3 times to three times the length between the upper end of the third diffusion layer and the lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors. 
         [0015]    Lengths from lower ends to upper ends of the gates can be the same. 
         [0016]    The upper end of the third diffusion layer of each of the third and fourth NMOS driver transistors can be at a position higher than the upper end of the first diffusion layer of each of the first and second NMOS access transistors. 
         [0017]    The lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors can be at a position lower than the lower end of the second diffusion layer of each of the first and second NMOS access transistors. 
         [0018]    The upper end of the third diffusion layer of each of the third and fourth NMOS driver transistors can be at a position higher than the upper end of the first diffusion layer of each of the first and second NMOS access transistors, and the lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors can be at a position lower than the lower end of the second diffusion layer of each of the first and second NMOS access transistors. 
         [0019]    The first diffusion layer of each of the first and second NMOS access transistors can be formed after the third diffusion layer of each of the third and fourth NMOS driver transistors is formed. 
         [0020]    The fourth diffusion layers of the third and fourth NMOS driver transistors and the second diffusion layers of the first and second NMOS access transistors can be formed by ion implantation. Further, energy of ion implantation for forming the fourth diffusion layer of each of the third and fourth NMOS driver transistors can be higher than energy of ion implantation for forming the second diffusion layer of each of the first and second NMOS access transistors. 
         [0021]    The fourth diffusion layers of the third and fourth NMOS driver transistors can include phosphorus. 
         [0022]    According to the present invention, a high-degree-of-integration, operational stability-secured static memory cell in which the channel length of a driver transistor can be shorter than the channel length of an access transistor, and a method for fabricating the static memory cell can be provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1A  is a plan view of a static memory cell according to first and second embodiments of the present invention; 
           [0024]      FIG. 1B  is a cross-sectional view taken along line X-X′ in  FIG. 1A ; 
           [0025]      FIG. 2A  is a cross-sectional view of a static memory cell according to third and fifth embodiments of the present invention; 
           [0026]      FIG. 2B  is a cross-sectional view of a static memory cell according to fourth and sixth embodiments of the present invention; 
           [0027]      FIG. 3  is a cross-sectional view of a static memory cell according to a seventh embodiment of the present invention; 
           [0028]      FIG. 4  is a cross-sectional view of a static memory cell according to an eighth embodiment of the present invention; 
           [0029]      FIG. 5  is a cross-sectional view of a static memory cell according to a ninth embodiment of the present invention; 
           [0030]      FIG. 6  is a cross-sectional view of a static memory cell according to a tenth embodiment of the present invention; 
           [0031]      FIG. 7  is a cross-sectional view explaining a method for fabricating a static memory cell according to an embodiment of the present invention; 
           [0032]      FIG. 8  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0033]      FIG. 9  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0034]      FIG. 10  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0035]      FIG. 11  is a cross-sectional view explaining the method for fabricating of a static memory cell according to the embodiment of the present invention; 
           [0036]      FIG. 12  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0037]      FIG. 13  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0038]      FIG. 14  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0039]      FIG. 15  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0040]      FIG. 16  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0041]      FIG. 17  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0042]      FIG. 18  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0043]      FIG. 19  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0044]      FIG. 20  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0045]      FIG. 21  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0046]      FIG. 22  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0047]      FIG. 23  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0048]      FIG. 24  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0049]      FIG. 25  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0050]      FIG. 26  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0051]      FIG. 27  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0052]      FIG. 28  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0053]      FIG. 29  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0054]      FIG. 30  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0055]      FIG. 31  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0056]      FIG. 32  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0057]      FIG. 33  is a cross-sectional view explaining a method for fabricating a static memory cell according to another embodiment of the present invention; 
           [0058]      FIG. 34  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0059]      FIG. 35  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0060]      FIG. 36  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0061]      FIG. 37  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0062]      FIG. 38  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0063]      FIG. 39  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0064]      FIG. 40  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0065]      FIG. 41  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0066]      FIG. 42  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0067]      FIG. 43  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0068]      FIG. 44  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0069]      FIG. 45  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0070]      FIG. 46  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0071]      FIG. 47  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0072]      FIG. 48  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0073]      FIG. 49  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0074]      FIG. 50  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0075]      FIG. 51  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0076]      FIG. 52  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0077]      FIG. 53  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0078]      FIG. 54  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0079]      FIG. 55  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0080]      FIG. 56  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; 
           [0081]      FIG. 57  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention; and 
           [0082]      FIG. 58  is a cross-sectional view explaining the method for fabricating a static memory cell according to the embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0083]    Embodiments of the present invention will be described hereinafter with reference to the drawings. It is to be understood that the present invention is not to be limited to the following embodiments. 
         [0084]      FIGS. 1A and 1B  illustrate a plan view and a cross-sectional view of a static memory cell according to a first embodiment of the present invention, respectively. A third NMOS driver transistor  101  has a third diffusion layer  119 , a pillar-shaped semiconductor layer  149 , and a fourth diffusion layer  107 . A gate  125  is formed on side walls of the pillar-shaped semiconductor layer  149 , a portion of the fourth diffusion layer  107 , and a portion of the third diffusion layer  119  of the third NMOS driver transistor  101  via a gate insulating film  113 . 
         [0085]    A first NMOS access transistor  103  has a first diffusion layer  121 , a pillar-shaped semiconductor layer  151 , and a second diffusion layer  109 . A gate  126  is formed on side walls of the pillar-shaped semiconductor layer  151 , a portion of the second diffusion layer  109 , and a portion of the first diffusion layer  121  of the first NMOS access transistor  103  via a gate insulating film  115 . 
         [0086]    The gate height of the gate  125  is low in the vicinity of the third NMOS driver transistor  101 , and the physical gate length of the gate  125  is shorter than that of the gate  126 . The length between the first diffusion layer  121  and the second diffusion layer  109  of the first NMOS access transistor  103  is twice the length between the third diffusion layer  119  and the fourth diffusion layer  107  of the third NMOS driver transistor  101 . Therefore, the current driving force of the driver transistor can be made double the current driving force of the access transistor without increasing the area, and operational stability can be ensured. 
         [0087]    A first PMOS load transistor  102  has a fifth diffusion layer  120 , a pillar-shaped semiconductor layer  150 , and a sixth diffusion layer  108 . The gate  125  is formed on side walls of the pillar-shaped semiconductor layer  150 , a portion of the fifth diffusion layer  120 , and a portion of the sixth diffusion layer  108  of the first PMOS load transistor  102  via a gate insulating film  114 . 
         [0088]    The third NMOS driver transistor  101  and the first PMOS load transistor  102  are connected to each other via the gate  125 . Further, the third diffusion layer  119 , the fifth diffusion layer  120 , and the first diffusion layer  121  are connected to one another via a silicide layer (not illustrated in the drawings). In the drawings, a silicon-on-insulator (SOI) substrate is used to electrically insulate the third diffusion layer  119 , the fifth diffusion layer  120 , and the first diffusion layer  121  from a substrate; however, any other method that can provide electrical insulation may be used. For example, a PN junction may be formed using a Si substrate and electrical insulation may be formed using the reverse bias state of the PN junction. 
         [0089]    A fourth NMOS driver transistor  106  has a third diffusion layer  124 , a pillar-shaped semiconductor layer, and a fourth diffusion layer  112 . A gate  128  is formed on side walls of the pillar-shaped semiconductor layer, a portion of the third diffusion layer  124 , and a portion of the fourth diffusion layer  112  of the fourth NMOS driver transistor  106  via a gate insulating film  118 . 
         [0090]    A second NMOS access transistor  104  has a first diffusion layer  122 , a pillar-shaped semiconductor layer, and a second diffusion layer  110 . A gate  127  is formed on side walls of the pillar-shaped semiconductor layer, a portion of the first diffusion layer  122 , and a portion of the second diffusion layer  110  of the second NMOS access transistor  104  via a gate insulating film  116 . Although not illustrated in the drawings, the length between the first diffusion layer  122  and the second diffusion layer  110  of the second NMOS access transistor  104  is twice the length between the third diffusion layer  124  and the fourth diffusion layer  112  of the fourth NMOS driver transistor  106 . 
         [0091]    A second PMOS load transistor  105  has a fifth diffusion layer  123 , a pillar-shaped semiconductor layer, and a sixth diffusion layer  111 . The gate  128  is formed on side walls of the pillar-shaped semiconductor layer, a portion of the fifth diffusion layer  123 , and a portion of the sixth diffusion layer  111  of the second PMOS load transistor  105  via a gate insulating film  117 . The fourth NMOS driver transistor  106  and the second PMOS load transistor  105  are connected to each other via the gate  128 . Further, the first diffusion layer  122 , the fifth diffusion layer  123 , and the third diffusion layer  124  are connected to one another via a silicide layer (not illustrated in the drawings). 
         [0092]    In the drawings, an SOI substrate is used to electrically insulate the first diffusion layer  122 , the fifth diffusion layer  123 , and the third diffusion layer  124  from the substrate; however, any other method that can provide electrical insulation may be used. For example, a PN junction may be formed using a Si substrate and electrical insulation may be formed using the reverse bias state of the PN junction. 
         [0093]    A contact  130  is formed on the gate  125 , and a contact  137  is formed on the first diffusion layer  122  and the fifth diffusion layer  123 . The contacts  130  and  137  are connected to each other via a metal  142 . Further, a contact  139  is formed on the gate  128 , and a contact  132  is formed on the fifth diffusion layer  120  and the first diffusion layer  121 . The contacts  139  and  132  are connected to each other via a metal  144 . A contact  131  is formed on the sixth diffusion layer  108 , and a contact  138  is formed on the sixth diffusion layer  111 . A metal  143  is connected to the contacts  131  and  138 , and power is supplied. 
         [0094]    A contact  129  is formed on the fourth diffusion layer  107 , a metal  141  is formed, and power is supplied. A contact  140  is formed on the fourth diffusion layer  112 , a metal  148  is formed, and power is supplied. A contact  133  is formed on the second diffusion layer  109 , and a metal  145  is formed, which serves as a bit line. A contact  136  is formed on the second diffusion layer  110 , and a metal  210  is formed, which serves as a bit line. A contact  134  is formed on the gate  126 , and a metal  146  is formed, which serves as a word line. A contact  135  is formed on the gate  127 , and a metal  147  is formed, which serves as a word line. 
         [0095]    The plan view and the cross-sectional view of a static memory cell according to a second embodiment of the present invention are the same as those illustrated in  FIG. 1 . In the second embodiment, the length between the third diffusion layer  119  and the fourth diffusion layer  107  of the third NMOS driver transistor  101  is shorter than the length between the fifth diffusion layer  120  and the sixth diffusion layer  108  of the first PMOS load transistor  102 . In an SRAM, a PMOS load transistor is formed with a minimum size and is formed so that the current driving force of the PMOS load transistor is smaller than the current driving force of an NMOS access transistor. That is, an NMOS access transistor and a PMOS load transistor are formed so as to have the same channel length. Therefore, in the present invention, the channel length of the NMOS driver transistor  101  is shorter than the channel length of the PMOS driver transistor  102 . 
         [0096]      FIGS. 2A and 2B  illustrate cross-sectional views of static memory cells according to third and fourth embodiments of the present invention, respectively. In  FIG. 2A , the length between the upper end of the first diffusion layer  121  of the first NMOS access transistor  103  and the lower end of the second diffusion layer  109  of the first NMOS access transistor  103  is made 1.3 times the length between the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  and the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101 . In  FIG. 2B , the length between the upper end of the first diffusion layer  121  of the first NMOS access transistor  103  and the lower end of the second diffusion layer  109  of the first NMOS access transistor  103  is made three times the length between the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  and the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101 . As the channel length of a driver transistor decreases, operational stability can be ensured, whereas if the channel length is short, the short-channel effects arise, which prevents the transistor from being cut off. Therefore, by way of example, the range from 1.3 times to three times, as described above, can ensure operational stability and can suppress or reduce short-channel effects, where the range may be selected as desired in accordance with the actual demand. 
         [0097]    The cross-sectional views of static memory cells according to fifth and sixth embodiments of the present invention are the same as those in  FIGS. 2A and 2B , respectively. In the fifth embodiment, the length between the upper end of the fifth diffusion layer  120  of the first PMOS load transistor  102  and the lower end of the sixth diffusion layer  108  of the first PMOS load transistor  102 , is made 1.3 times the length between the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  and the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101 . In the sixth embodiment, the length between the upper end of the fifth diffusion layer  120  of the first PMOS load transistor  102  and the lower end of the sixth diffusion layer  108  of the first PMOS load transistor  102  is three times the length between the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  and the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101 . As the channel length of a driver transistor decreases, operational stability can be ensured, whereas if the channel length is short, the short-channel effects arise, which prevents the transistor from being cut off. Therefore, by way of example, the range from 1.3 times to three times, as described above, can ensure operational stability and can suppress or reduce short-channel effects, where the range may be selected as desired in accordance with the actual demand. 
         [0098]      FIG. 3  illustrates a cross-sectional view of a static memory cell according to a seventh embodiment of the present invention. The physical gate lengths of the gates  125  and  126  are made the same. Since the lengths from the lower ends to the upper ends of the gates  125  and  126 , that is, the physical gate lengths, are the same, the SGT production method described above can be used of forming a pillar-shaped semiconductor layer, depositing a gate conductive film on the pillar-shaped semiconductor layer, performing planarization, and then etching back the gate conductive film to obtain a desired length. 
         [0099]    In general, reducing the channel length is equivalent to reducing the physical gate length, as in  FIG. 1 . If the physical gate length is reduced, the gate capacitance is reduced. If the gate capacitance is reduced, a soft error occurs, resulting in operational stability not being ensured. In  FIG. 3 , in contrast, the physical gate lengths are the same while only the channel length of a driver transistor is reduced. Therefore, the gate capacitance is not reduced although the current driving force of the driver transistor is doubled. That is, the current driving force of a driver transistor can be made double the current driving force of an access transistor, resulting in operational stability being ensured. In addition, the occurrence of soft errors can be avoided to ensure operational stability. 
         [0100]      FIG. 4  illustrates a cross-sectional view of a static memory cell according to an eighth embodiment of the present invention. In the embodiment illustrated in  FIG. 4 , the physical gate lengths are the same, and the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  is at a higher portion than the upper end of the first diffusion layer  121  of the first NMOS access transistor  103 . This enables the third NMOS driver transistor  101  to increase the overlap capacitance between the gate  125  and the third diffusion layer  119 . During the cut-off of the third NMOS driver transistor  101 , the overlap capacitance between the gate  125  and the third diffusion layer  119  becomes a parasitic capacitance parasitic to a storage node. Since the overlap capacitance is large, the occurrence of soft errors can further be avoided to ensure operational stability. 
         [0101]      FIG. 5  illustrates a cross-sectional view of a static memory cell according to a ninth embodiment of the present invention. The difference between  FIG. 5  and  FIG. 4  is that the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  is positioned at the same height as the upper end of the first diffusion layer  121  of the first NMOS access transistor  103  and that the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101  is at a position lower than the lower end of the second diffusion layer  109  of the first NMOS access transistor  103 . 
         [0102]    Also in the embodiment illustrated in  FIG. 5 , the physical gate lengths are the same while only the channel length of a driver transistor is reduced. Therefore, the gate capacitance is not reduced although the current driving force of the driver transistor is doubled. Thus, the current driving force of a driver transistor can be made double the current driving force of an access transistor, resulting in operational stability being ensured. In addition, the occurrence of soft errors can be avoided to ensure operational stability. However, further advantages illustrated in  FIG. 4 , that is, the advantages that during the cut-off of the third NMOS driver transistor  101 , the overlap capacitance between the gate  125  and the third diffusion layer  119  becomes a parasitic capacitance parasitic to a storage node and that since the overlap capacitance is large, the occurrence of soft errors can further be avoided to ensure operational stability, are not achievable. However, if a storage node is designed to be located above a transistor, the advantage of further avoiding the occurrence of soft errors can be achieved. As described below with respect to a production method, the creation of the configuration illustrated in  FIG. 4  requires a comparatively long heat treatment to be performed after ion implantation for the third diffusion layer  119 . When the fourth diffusion layer  107  is to be formed by ion implantation, the energy of the implantation is increased or phosphorus with a long diffusion length is used, thus enabling the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101  to be at a position lower than the lower end of the second diffusion layer  109  of the first NMOS access transistor  103 . That is, the duration of heat treatment can be shorter than that in  FIG. 4 . 
         [0103]      FIG. 6  illustrates a cross-sectional view of a static memory cell according to a tenth embodiment of the present invention. The difference between  FIG. 6  and  FIG. 4  is that the upper end of the third diffusion layer  119  of the third NMOS driver transistor  101  is at a position higher than the upper end of the first diffusion layer  121  of the first NMOS access transistor  103  and that the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101  is at a position lower than the lower end of the second diffusion layer  109  of the first NMOS access transistor  103 . 
         [0104]    Also in the embodiment illustrated in  FIG. 6 , the channel length of a driver transistor is made shorter than the channel length of an access transistor, thus enabling operational stability to be ensured. Additionally, an advantage illustrated in  FIG. 4 , that is, the advantage of avoiding the occurrence of soft errors, can also be achieved. Since the diffusion length of the third diffusion layer  119  is short, the duration of heat treatment shorter than that required to create the configuration illustrated in  FIG. 4  is required for formation. When the fourth diffusion layer  107  is to be formed by ion implantation, the energy of the implantation is increased or phosphorus with a diffusion length is used, thus enabling the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101  to be at a position lower than the lower end of the second diffusion layer  109  of the first NMOS access transistor  103 . That is, the duration of heat treatment can be shorter than that required in  FIG. 4 , and the occurrence of soft errors can also be avoided. However, a larger number of steps in the production process than that required to create the configuration illustrated in  FIG. 4  or the configuration illustrated in  FIG. 5  are required. While various embodiments have been illustrated, any of them may be selected as desired in accordance with the actual demand. 
         [0105]    An example of a production process for forming the structure of the static memory cell illustrated in  FIG. 4  according to an embodiment of the present invention will be described with reference to  FIGS. 7 to 32 . 
         [0106]      FIG. 7  illustrates a state where an oxide film  157  is formed on a silicon layer  152 , a planar silicon layer  158  is formed on the oxide film  157 , and pillar-shaped silicon layers  159 ,  160 , and  161  having nitride film hard masks  162 ,  163 , and  164  in upper portions thereof are formed. 
         [0107]    In the state illustrated in  FIG. 7 , an oxide film is deposited and is etched back to form oxide film sidewalls  165 ,  166 , and  167 , as illustrated in  FIG. 8 . After that, a resist  168  for forming a third diffusion layer  119  is formed. 
         [0108]    In this state, as illustrated in  FIG. 9 , arsenic is implanted to form the third diffusion layer  119 . 
         [0109]    After that, as illustrated in  FIG. 10 , the resist  168  is stripped, the oxide film sidewalls  165 ,  166 , and  167  are stripped, and the first heat treatment is carried out. 
         [0110]    Further, as illustrated in  FIG. 11 , oxide film sidewalls  169 ,  170 , and  171  are formed. After that, a resist  172  for forming a first diffusion layer  121  is formed. 
         [0111]    In this state, as illustrated in  FIG. 12 , arsenic is implanted to form the first diffusion layer  121 . 
         [0112]    After that, as illustrated in  FIG. 13 , the resist  172  is stripped, the oxide film sidewalls  169 ,  170 , and  171  are stripped, and the second heat treatment is carried out. Since the third diffusion layer  119  undergoes heat treatment twice, the upper end of the third diffusion layer  119  is made to be at a position higher than the upper end of the first diffusion layer  121 . Therefore, the channel length of a driver transistor is made shorter than the channel length of an access transistor, and operational stability can be ensured. 
         [0113]    Subsequently, as illustrated in  FIG. 14 , oxide film sidewalls  173 ,  174 , and  175  are formed. After that, a resist  176  for forming a fifth diffusion layer  120  is formed. 
         [0114]    In this state, as illustrated in  FIG. 15 , boron is implanted to form the fifth diffusion layer  120 . 
         [0115]    After the above state, as illustrated in  FIG. 16 , the resist  176  is stripped, the oxide film sidewalls  173 ,  174 , and  175  are stripped, and heat treatment is carried out. 
         [0116]    After that, as illustrated in  FIG. 17 , a resist for forming elements separately is formed, silicon etching is performed, and the resist is stripped. 
         [0117]    Subsequently, as illustrated in  FIG. 18 , an oxide film  153  is formed so as to be buried in spaces between the elements. After that, an atmospheric pressure chemical vapor deposition (CVD) oxide film is deposited and is etched back to form an oxide film  177 . In this case, oxide films  178 ,  179 , and  180  remain on the nitride film hard masks  162 ,  163 , and  164 , respectively. 
         [0118]    Further, as illustrated in  FIG. 19 , gate insulating films  113 ,  114 , and  115  are formed, a gate conductive film  181  is deposited, and planarization is performed. After the oxide films  178 ,  179 , and  180  are exposed, the oxide films  178 ,  179 , and  180  are etched, and planarization is further performed using the nitride film hard masks  162 ,  163 , and  164  as stoppers. Each of the gate insulating films  113 ,  114 , and  115  is one of an oxide film, a nitride film, an oxynitride film, and a high-dielectric film. The gate conductive film  181  is one of a polysilicon film, a metal/polysilicon laminated film, and a metal film. 
         [0119]    Subsequently, as illustrated in  FIG. 20 , the gate conductive film  181  is etched back to obtain a desired physical gate length. Consequently, the physical gate length is made uniform over all the transistors. 
         [0120]    Then, an oxide film is deposited, a nitride film is deposited, and etching is performed to make the oxide film and the nitride film remain as sidewalls. As illustrated in  FIG. 21 , an insulating film sidewall composed of an oxide film  184  and a nitride film  185 , an insulating film sidewall composed of an oxide film  186  and a nitride film  187 , and an insulating film sidewall composed of an oxide film  188  and a nitride film  189  are formed. 
         [0121]    Subsequently, as illustrated in  FIG. 22 , resists  182  and  183  for performing gate etching are formed. 
         [0122]    Then, as illustrated in  FIG. 23 , the gate conductive film  181  is etched to from gates  125  and  126 , and the oxide film  177  is etched to form oxide films  154  and  155 . Then, the resists  182  and  183  are stripped. 
         [0123]    Subsequently, as illustrated in  FIG. 24 , the insulating film sidewall composed of the oxide film  184  and the nitride film  185 , the insulating film sidewall composed of the oxide film  186  and the nitride film  187 , and the insulating film sidewall composed of the oxide film  188  and the nitride film  189  are etched. 
         [0124]    Then, a nitride film is deposited, and etching is performed to make the nitride film remain as sidewalls. As illustrated in  FIG. 25 , nitride film sidewalls  190 ,  191 ,  192 ,  193 , and  194  are formed. 
         [0125]    Subsequently, as illustrated in  FIG. 26 , a resist  195  for forming a fourth diffusion layer  107  and a second diffusion layer  109  is formed. 
         [0126]    Then, as illustrated in  FIG. 27 , arsenic is ion-implanted to form the fourth diffusion layer  107  and the second diffusion layer  109 . 
         [0127]    After that, as illustrated in  FIG. 28 , the resist  195  is stripped, and heat treatment is carried out. 
         [0128]    As illustrated in  FIG. 29 , a resist  196  for forming a sixth diffusion layer  108  is formed. 
         [0129]    Subsequently, as illustrated in  FIG. 30 , boron is ion-implanted to form the sixth diffusion layer  108 . 
         [0130]    Then, as illustrated in  FIG. 31 , the resist  196  is stripped, and heat treatment is carried out. 
         [0131]    Subsequently, as illustrated in  FIG. 32 , an interlayer film  156  is deposited, contacts  129 ,  130 ,  131 ,  132 ,  133 , and  134  are formed, and metals  141 ,  142 ,  143 ,  144 ,  145 , and  146  are formed. Before an interlayer film is formed, silicide layers may be formed on the third diffusion layer  119 , the fifth diffusion layer  120 , and the first diffusion layer  121 . Silicide layers may also be formed on the fourth diffusion layer  107 , the sixth diffusion layer  108 , and the second diffusion layer  109 . 
         [0132]    Accordingly, the channel length of a driver transistor is made shorter than the channel length of an access transistor to ensure operational stability. Furthermore, the physical gate length of the driver transistor and the physical gate length of the access transistor are made the same, and therefore the SGT production method described above can be used. That is, the current driving force of the driver transistor can be made double the current driving force of the access transistor to ensure operational stability. Furthermore, only the channel length of the driver transistor is reduced while the physical gate lengths are the same. Therefore, the gate capacitance is not reduced although the current driving force of the driver transistor is doubled. Thus, the occurrence of soft errors can be avoided to ensure operational stability. Additionally, the upper end of the third diffusion layer of the driver transistor is made to be at position higher than the upper end of the first diffusion layer of the access transistor, thus allowing the driver transistor to increase the overlap capacitance between the gate and the third diffusion layer. The occurrence of soft errors can further be avoided to ensure further operational stability. A production method for forming the above structure has been illustrated. 
         [0133]    An example of a production process for forming the structure of the static memory cell illustrated in  FIG. 5  according to an embodiment of the present invention will be described with reference to  FIGS. 33 to 58 . 
         [0134]      FIG. 33  illustrates a structure in which an oxide film  157  is formed on a silicon layer  152 , a planar silicon layer  158  is formed on the oxide film  157 , and pillar-shaped silicon layers  159 ,  160 , and  161  having nitride film hard masks  162 ,  163 , and  164  in upper portions thereof are formed. 
         [0135]    Subsequently, as illustrated in  FIG. 34 , an oxide film is deposited and is etched back to form oxide film sidewalls  169 ,  170 , and  171 . After that, a resist  172  for forming a third diffusion layer  119  and a first diffusion layer  121  is formed. 
         [0136]    Then, as illustrated in  FIG. 35 , arsenic is implanted to form the third diffusion layer  119  and the first diffusion layer  121 . 
         [0137]    Subsequently, as illustrated in  FIG. 36 , the resist  172  is stripped, the oxide film sidewalls  169 ,  170 , and  171  are stripped, and heat treatment is carried out. 
         [0138]    Then, as illustrated in  FIG. 37 , oxide film sidewalls  173 ,  174 , and  175  are formed. After that, a resist  176  for forming a fifth diffusion layer  120  is formed. 
         [0139]    Subsequently, as illustrated in  FIG. 38 , boron is implanted to form the fifth diffusion layer  120 . 
         [0140]    After that, as illustrated in  FIG. 39 , the resist  176  is stripped, the oxide film sidewalls  173 ,  174 , and  175  are stripped, and heat treatment is carried out. 
         [0141]    Subsequently, as illustrated in  FIG. 40 , a resist for forming elements separately is formed, silicon etching is performed, and the resist is stripped. 
         [0142]    Then, as illustrated in  FIG. 41 , an oxide film  153  is formed so as to be buried in spaces between the elements. After that, an atmospheric pressure CVD oxide film is deposited and is etched back to form an oxide film  177 . In this case, oxide films  178 ,  179 , and  180  remain on the nitride film hard masks  162 ,  163 , and  164 , respectively. 
         [0143]    After that, as illustrated in  FIG. 42 , gate insulating films  113 ,  114 , and  115  are formed, a gate conductive film  181  is deposited, and planarization is performed. After the oxide films  178 ,  179 , and  180  are exposed, the oxide films  178 ,  179 , and  180  are etched, and planarization is further performed using the nitride film hard masks  162 ,  163 , and  164  as stoppers. Each of the gate insulating films  113 ,  114 , and  115  is one of an oxide film, a nitride film, an oxynitride film, and a high-dielectric film. The gate conductive film  181  is one of a polysilicon film, a metal/polysilicon laminated film, and a metal film. 
         [0144]    Subsequently, as illustrated in  FIG. 43 , the gate conductive film  181  is etched back to obtain a desired physical gate length. Consequently, the physical gate length is made uniform over all the transistors. 
         [0145]    Then, as illustrated in  FIG. 44 , an oxide film is deposited, a nitride film is deposited, and etching is performed to make the oxide film and the nitride film remain as sidewalls. An insulating film sidewall composed of an oxide film  184  and a nitride film  185 , an insulating film sidewall composed of an oxide film  186  and a nitride film  187 , and an insulating film sidewall composed of an oxide film  188  and a nitride film  189  are formed. 
         [0146]    Further, as illustrated in  FIG. 45 , resists  182  and  183  for performing gate etching are formed. 
         [0147]    Then, as illustrated in  FIG. 46 , the gate conductive film  181  is etched to form gates  125  and  126 , and the oxide film  177  is etched to form oxide films  154  and  155 . Then, the resists  182  and  183  are stripped. 
         [0148]    After that, as illustrated in  FIG. 47 , the insulating film sidewall composed of the oxide film  184  and the nitride film  185 , the insulating film sidewall composed of the oxide film  186  and the nitride film  187 , and the insulating film sidewall composed of the oxide film  188  and the nitride film  189  are etched. 
         [0149]    Subsequently, as illustrated in  FIG. 48 , a nitride film is deposited and etching is performed to make the nitride film remain as sidewalls to form nitride film sidewalls  190 ,  191 ,  192 ,  193 , and  194 . 
         [0150]    Then, as illustrated in  FIG. 49 , a resist  201  for forming a fourth diffusion layer  107  is formed. 
         [0151]    Subsequently, as illustrated in  FIG. 50 , arsenic or phosphorus is ion-implanted to form the fourth diffusion layer  107 . When arsenic is to be used, the energy of the ion implantation may be increased. In addition, phosphorus having a long diffusion length is used, thus enabling the lower end of the fourth diffusion layer  107  of the third NMOS driver transistor  101  to be at a position lower than the lower end of the second diffusion layer  109  of the first NMOS access transistor  103 . Whether to use arsenic or phosphorus may be selected as desired. 
         [0152]    After that, as illustrated in  FIG. 51 , the resist  201  is stripped, and heat treatment is carried out. 
         [0153]    Then, as illustrated in  FIG. 52 , a resist  202  for forming a second diffusion layer  109  is formed. 
         [0154]    Subsequently, as illustrated in  FIG. 53 , arsenic is ion-implanted to from the second diffusion layer  109 . 
         [0155]    Subsequently, as illustrated in  FIG. 54 , the resist  202  is stripped, and heat treatment is carried out. 
         [0156]    Subsequently, as illustrated in  FIG. 55 , a resist  203  for forming a sixth diffusion layer  108  is formed. 
         [0157]    Subsequently, as illustrated in  FIG. 56 , boron is ion-implanted to form the sixth diffusion layer  108 . 
         [0158]    Subsequently, as illustrated in  FIG. 57 , the resist  203  is stripped, and heat treatment is carried out. 
         [0159]    Then, as illustrated in  FIG. 58 , an interlayer film  156  is deposited, contacts  129 ,  130 ,  131 ,  132 ,  133 , and  134  are formed, and metals  141 ,  142 ,  143 ,  144 ,  145 , and  146  are formed. Before an interlayer film is formed, silicide layers may be formed on the third diffusion layer  119 , the fifth diffusion layer  120 , and the first diffusion layer  121 . Silicide layers may also be formed on the fourth diffusion layer  107 , the sixth diffusion layer  108 , and the second diffusion layer  109 . 
         [0160]    Accordingly, the channel length of a driver transistor is made shorter than the channel length of an access transistor to ensure operational stability, and the duration of heat treatment can be shorter than that in  FIG. 4 . 
         [0161]    While production methods for forming the structures illustrated in  FIG. 4  and  FIG. 5  have been described, the structure illustrated in  FIG. 6  can be formed by using a combination of the method of forming the third diffusion layer  119  and the first diffusion layer  121  illustrated in  FIG. 4  and the method of forming the fourth diffusion layer  107  and the second diffusion layer  109  illustrated in  FIG. 5 . 
         [0162]    A variety of embodiments and modifications can be made to the present invention without departing from the broad spirit and scope of the present invention. The foregoing embodiments serve to explain exemplary embodiments of the present invention, and the technical scope of the present invention is not to be limited to the foregoing embodiments.

Technology Category: 5