Patent Document

This application is a division of U.S. Ser. No. 08/190,943 filed Feb. 3, 1994. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a battery charger, and particularly to an end of charge detection technique for use in a battery charger. 
     BACKGROUND TO THE INVENTION 
     Charging characteristics for nickel cadmium (NICD) batteries are shown in curve b of FIG.  5 . The battery voltage increases slowly for 90% of the battery capacity during charging, but then starts to climb steeply after that, from point P 1  onwards. At point P 3  the voltage levels off and starts to decline from point P 3  to point P 4 . It is known to attempt to determine the end of charge point by detecting this voltage drop (−dV) at the end of charging. 
     Due to increasing usage of ultra-fast or fast charging rates (one hour or less than one hour charging time) in present day high end chargers, switch mode power supply technology is employed for the design of chargers due to reasons of size and efficiency. However, these designs have high switching noise. 
     These switching noises can take the form as shown in FIG. 8 a.  They can be spikes or glitches S on an otherwise calm and slowly changing battery voltage level V batt . False detection by a conventional charger monitor using a −dV method can occur in cases like that depicted in FIGS. 8 b  and  8   c . In FIG. 8 b , a noise spike S reaches a voltage level v 1 . If one voltage measurement is made at v 1  and another at v 2 , a −dV detection will be indicated if the measurement at v 2  is lower than that at v 1  by more than the present threshold, e.g. 50 mV. The same false detection will occur if, as in FIG. 8 c,  the measurement at noise spike v 4  is lower than that at v 3  by more than the same threshold value (FIG. 8 c ). 
     Due to the fact that amplitudes of switching noises  5  are generally in the range of hundreds of mV, whereas the detection threshold of −dV detection is only tens of mV, to avoid false detection due to these noise signals, extensive filtering has to be used. Very often, too much filtering causes a slow response and the result is that the battery is overcharged before the −dV point is detected and charging terminated. The avoidance of noise by filtering is also very dependent on the particular design of charger. Optimum filtering for one charger may be insufficient for another. It also increases the cost of implementation. 
     Another known method to avoid false detection in −dV detection techniques is to interrupt charging and to measure the battery voltage before resuming charging. This is done because during the interval when charging is stopped, switching noises are minimal and it is thus an optimum time to take a measurement of battery voltage. The drawback of this approach is that charging times are considerably longer due to the interruptions and also delays are caused due to the waiting times during voltage measurements. The waiting times are necessary for the battery voltage to settle down just after charge interruptions to ensure accurate readings. 
     The aim of the present invention is to enable the −dV point to be detected accurately at the end of charge when charging on an NICD battery in a noisy environment. 
     SUMMARY OF THE INVENTION 
     According to the present invention there is provided a battery charging including: 
     a voltage detection circuit for monitoring the voltage of a battery being charged and for providing sequentially a plurality of voltage values; 
     a comparator connected to compare each voltage value with the preceding voltage value thereby to determine when there is a difference exceeding a threshold value; and 
     a detector arranged to output an end of charge detection signal when said difference has been determined and when the last preceding voltage value has not exceeded the last but one preceding value. 
     Preferably, a further voltage value is generated after the voltage value at which said difference is determined, said further voltage value being compared with the last voltage value. 
     By taking measurements before the moment when a voltage drop is suspected and also taking measurements after that moment, it is possible to eliminate the effect of switching noises and only act on a genuine voltage drop. 
     The voltage detection circuit can be enabled in response to a signal from a pre-measurement circuit which identifies the time when a voltage drop is suspected. This pre-measurement circuit can take the form of a dV/dt circuit (voltage gradient measurement) or a dT/dt circuit (temperature gradient measurement) as described herein. 
     The present invention also provides a method of detecting a voltage drop when charging a battery, the method including monitoring the voltage of a battery being charged and providing sequentially a plurality of voltage values; comparing each voltage value with a preceding voltage value thereby to determine when there is a difference exceeding a theshold value; and producing an end of charge detection signal when said difference has been determined and when the last preceding voltage value has not exceeded the last but one preceding value. 
     For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a battery charging system; 
     FIG. 2 is a circuit diagram of a battery charger controller; 
     FIG. 3 is a flow chart illustrating the sequence of operation of the battery charger controller; 
     FIG. 4 is a block diagram of those components forming the battery charger monitor; 
     FIG. 5 is a graph of voltage against capacity indicating the characteristic of NIMH(a) and NICD(b) cells; 
     FIG. 6 is a graph of temperature against capacity indicating the characteristics of NIMH(d) and NICD(c) cells; 
     FIG. 7 is a block diagram of a negative (−dV) voltage detector; 
     FIGS. 8 a  to  8   c  illustrate the problem that can arise when there is noise on the battery voltage; and 
     FIGS. 9 a  to  9   b  illustrate how the −dV detects and overcomes the problem of noise spikes. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     There follows a description of a low cost, reliable, efficient and accurate battery charger for Ultra-fast or Fast charging (one hour or sub-hour charging time) of NICD or NIMH batteries. The detection concepts include universal end-of-charge detection when charging NICD and/or NIMH batteries without the need to indicate which kind of battery is being used by the user; simple, low cost but accurate way of implementing negative delta-V detection (with which the present invention is principally concerned); and a whole series of charge termination techniques to ensure fast but safe battery charging. 
     FIG. 1 illustrates a battery charger controller Y 3  in use with an ac/dc converter Y 1 , a constant current charger circuit Y 2  and a NICD or NIMH battery pack Y 4  to realise a basic fast (one hour or less) battery charger. 
     The ac/dc converter Y 1  is connected via a switching element in the form of a transistor Y 6  to the primary side of a transformer Y 17 . The primary side of the transformer Y 17  is connected to the output of a bridge rectifier Y 5  across which is connected an ac power supply Y 8  having a range of between 90 to 270 V. The ac/dc converter Y 1  converts AC power from the supply Y 8  to DC power on line Y 7  on the secondary side of the transformer Y 17  through the bridge rectifier Y 5  and the switching element Y 6 . Power line Y 7 , in addition to supplying power to a portable computer through an auxiliary output AO, also supplies power for battery charging through the constant current charger circuit Y 2 . The constant current charger circuit is a power converter which provides a constant current through its output Qc to charge the battery pack Y 4 . A relatively constant current is needed for charging the battery if a voltage drop (−dV) method of end-of-charge detection is to be used, as any variation in the voltage level during charging must then be due to the capacity of the battery. Reference Y 9  denotes a thermistor which can be supplied with the battery pack Y 4  for reasons explained hereinafter. 
     FIG. 2 illustrates the composition of the battery charger controller Y 3  (within the dotted boundary). In FIG. 2, the thick black lines denote on 8 bit bus and the thin line denotes a single bit line. Inputs for the charger controller Y 3  include a voltage on the auxiliary output AO (terminal AUX), a battery voltage (terminal V batt ), a cell temperature signal (terminal Temp) and a power-on signal (terminal Power-on). Outputs from the charger controller Y 3  are supplied by drivers M 20 ,M 21  and M 22  to implement ultra-fast charging, fast charging or trickle charging respectively at the external charger circuit Y 2 . 
     Upon power-up, a power sharing detector M 2  implements ultra-fast charging. This is done by appropriate signals from the {overscore (Q)} outputs  2 , 4  of the power sharing detector M 2 , through gates M 18  and M 19 , which control the drivers M 20  and M 21 . The gate M 18  has one input connected to the {overscore (Q)} output  2  of the power sharing detector M 2  and its other input connected to the {overscore (Q)} output  22  of a flip-flop M 17  which will be described later. The gate M 19  has one input connected to the Q output  4  of the power sharing detector M 2  and its other input connected to the {overscore (Q)} output  22  of the flip-flop M 17 . If the computer is off, charging will be in the ultra-fast mode. Actual implementation of the charging rate is by the external charger circuit Y 2 , controlled by the drivers M 20 ,M 21  and M 22 . A detailed description of the power sharing detector device M 2 , including how measurements and decisions are made, is given in our copending Application No. (Page White &amp; Farrer Ref. 73682), the contents of which are herein incorporated by reference. 
     The cell temperature read from thermistor Y 9  (FIG.  1 ), is supplied to the Temp terminal, and fed through an ADC channel plus filter M 4  into a thermistor detector circuit M 6 . In the case that the thermistor Y 9  is used in the battery pack Y 4  and connected to the charger controller, a dT/dt detector M 7  is enabled by the Q output  6  of the thermistor detector M 6 . If a thermistor is not used, a dV/dt detector M 5  is enabled by the {overscore (Q)} output  8  of the thermistor detector M 6 . 
     If the dT/dt detector M 7  is enabled, the rate of change of the cell temperature is measured. If this rate exceeds a certain limit, a dT/dt flag will be set, indicating a fast rising cell temperature, which is normally the case just before the end-of-charge of the battery. The setting of the dT/dt flag will be indicated by a “high” level at the Q output  10  of the dT/dt detector of the block M 7 . 
     If the dV/dt detector M 5  is enabled, the rate of change of the battery voltage is measured. If it is found to be rising at or above a predetermined rate, a dV/dt flag will be set. This is also an indication that end of charge is approaching as normally, near to the end-of-charge point (90% capacity point), the battery voltage rises steeply before levelling off at its peak and later dips (in the case of an NICD battery) or flattens out (in the case of an NIMH battery). 
     Whether the dV/dt or the dT/dt flag is set, both a −dV detector M 9  and a zero dV/dt detector M 10  will be enabled by the Q outputs  12 , 10  from the dV/dt and dT/dt detectors M 5  and M 7  through a gate M 8 . At the −dV detector M 9  any voltages drop after the setting of the dT/dt or dV/dt flag will be detected and verified. Confirmation of a true voltage drop detection will be indicated by setting a −dV flag putting a “high” level at the Q output  14  of the −dV detector M 9 . Detailed explanation of the −dV detector follows later. 
     Simultaneously, the zero dV/dt detector M 10  measures the slope of the battery voltage until a flat slope is detected within a certain time frame. This flat slope indicates that the peak voltage of the battery has been reached and can be used as an end-of-charge indication, particularly for an NIMH battery which may not exhibit any pronounced voltage dip in its fully charged state. Its Q output  16  is set high in this state. 
     Since the −dV and zero dV/dt detectors M 9 ,M 10  operate simultaneously, either a voltage dip or a flat slope may be detected to indicate end-of-charge, depending on which detection is first detected. Thus both NICD and NIMH batteries can be charged by the same system without the need to tell the system which kind of battery is being used. 
     Setting of the −dV flag or the zero dV/dt flag, indicated by a “high” at the Q output  14  of M 9  or  16  of M 10 , will set the flip-flop M 17  through a gate M 16 . Once M 17  is set by a “high” at its D input  18 , its Q output  20  will go “high” to enable trickle charging and its {overscore (Q)} output  22  will go “low”, disabling ultra-fast or fast charging through the gates M 18 ,M 19  connected to the drivers M 20 ,M 21 . 
     The circuits M 3 ,M 4 ,M 5 ,M 6 ,M 7 ,M 8 ,M 9  and M 10  constitute a battery charger monitor BCM which is described in more detail with reference to FIG.  4 . 
     The flip-flop M 17  can also be set by other circuits besides M 9  and M 10 , as described in the following. 
     A battery presence detector M 15 , connected to sample the battery voltage at terminal V batt  through the ADC channel and filter M 3 , can determine whether a battery is present at the V batt  terminal or not. This is because the Q output  1  of the constant current charger Y 2  in FIG. 1 assumes a preset voltage value when the battery Y 4  is not connected, which is distinctively higher than the maximum voltage that the battery can go in its fully charged state. Thus if the battery presence detector M 15  detects a value nearer to the preset output level of the constant current charger Y 2  it will interpret that the battery is not present and set the flip-flop M 17  through the gate M 16 , by having a “high” level at is Q output  24 . 
     However, if a battery is subsequently reconnected to the battery terminal, the battery presence detector M 15  will detect its presence and reset its Q output  24  to a “low” level. This negative going transition will trigger a reset circuit M 26  to reset all detectors in the battery charger controller Y 3  by a signal RAD at its output for a fresh detection cycle. This enables new packs of batteries to be charged upon replacement without the need for power reset. 
     The flip-flop M 17  is normally reset to enable ultra-fast or fast charging, enabling drivers M 20  and M 21  and disabling drive M 22  upon power-up, provided the ambient temperature in the battery pack Y 4  before the start of charging falls within a temperature window. This temperature window is set by a range defined by a lowest and highest value, for example, 0° C. and 40° C. respectively. The reason is that if the ambient temperature around the battery pack Y 4  is outside this range, it is not advisable to have ultra-fast or fast charging of the battery due to charge efficiency and safety reasons. This ambient temperature comparison is done by an ambient temperature detector M 24  receiving the temperature range Rt at its input  28 . The detector M 24  is enabled on power-up by a signal at its enable input  30 . If the temperature is within range, the detector M 24  will output on its Q output  32  a “high” signal to a set pin  34  of the flip-flop M 17 . After this the Q and {overscore (Q)} outputs  20 , 22  of M 17  will be determined by the states of any one of eight detection circuits M 9 ,M 10 ,M 11 ,M 13 ,M 14 ,M 15 ,M 25  or M 28 , that is a “high” signal from the outputs of any one of these circuits will inhibit ultra-fast or fast charging and enable trickle charging. 
     Detection circuits M 9 ,M 10  and M 15  have been described above. M 11  denotes a maximum temperature detector which samples the digital form of the cell temperature during charging from the Temp input via the ADC channel and filter M 4 . The maximum temperature detector M 11  will set a Temp flat at its Q output  38  if its input exceeds a certain maximum value Tmax set internally. This maximum value Tmax could be in the range of 50 to 60° C. Above this temperature (by 1° C. or more) it is not advisable to charge the battery using a high current due to charge efficiency and safety reasons. The setting of the Temp flag on line  38  will set the flip-flop M 17  thereby switching the charging rate to the trickle mode. 
     During the initial 3 to 5 minutes of the charging cycle, the rate of change of the battery voltage at terminal V batt  is monitored by a full cell detector circuit M 25 . Since for an already charged battery its voltage rises rapidly for the first few minutes of recharging, this occurrence can be detected by the circuit M 25  to indicate a “full” battery. Thus a “high” signal is generated at its Q output  40  which sets the flip-flop M 17  via the gate M 16 . The time frame used to set the initial period for this “full” cell detection is generated by a one-shot timer M 12  which is triggered by the Power-on signal from the Power-on terminal. 
     There is also a maximum voltage detector M 28  which measures the battery voltage during the initial few minutes of the charging cycle and cuts off charging if its value exceed a maximum voltage reference V max , as the battery is most likely a “full” one. This is done by its Q output  44  going high and being supplied to the gate M 16  via a gate M 29 . The time frame used for this detection is also taken from the one-shot timer M 12 , connected to the enable input  42  of the maximum voltage detector M 28 . By detecting fully charged batteries during the initial portion of the charge cycle by detectors M 25  and M 28 , unnecessary charging can be avoided and also the battery is better protected against overcharging. 
     During the same time frame set by the one-shot timer M 12  as mentioned above, a faulty cell detector M 13  also operates. After this preset time frame during which ultra-fast or fast charging is in progress, the detector M 13  will measure the battery voltage and if it is below a certain minimum level V min , its Q output  46  goes “high” and the flip-flip M 17  is set. 
     Finally, there is a count-down timer M 14  which starts counting down after receiving the power-on signal at its input  48  and sets the flip-flop M 17  via its Q output  50  through gate M 16  when its content is decremented to zero. Both this timer M 14  and the maximum temperature detector M 11  are important to terminate charging in cases when the main detection methods (dV/dt M 5 , dT/dt M 7 , −dV M 9  and zero dV/dt M 10 ) fail, so as to ensure the survival of the battery pack at the high charging current. 
     M 27  denotes a clock circuit which generates clock signals for each charging cycle. All readings are taken once every charge cycle. 
     FIG. 3 is the flow chart of the operation inside the described battery charger circuit. 
     After power-on but before charging starts, the cell temperature is measured in the ambient temperature detector circuit M 24 . If it falls outside the temperature window Rt (0° C. to 40° C., as mentioned before) trickle charging M 22  will take place until it falls back to within range. If cell temperature is within range, ultra-fast charging M 20  will be done. 
     During the first few minutes of charging set by the one-shot timer M 12  the battery voltage is measured by circuit M 28 . If it exceeds a certain level per cell, this indicates that the battery is already fully charged so that high current charging is unnecessary. Ultra-fast charging will be terminated and replaced with a trickle charge (in the “burst” mode). In addition the rate of change of battery voltage is also monitored by full cell detector M 25  within the same time frame. If a certain threshold is exceeded, indicating also a “full” cell condition, ultra-fast charging is stopped, and the trickle charge “burst” mode is entered. 
     The battery level is also checked during the same period by M 13  for faulty conditions. If the battery is found to be faulty, ultra-fast charging is stopped, and the trickle charge “burst” mode is entered. After the first few minutes determined by the one-shot timer M 12 , no checking will be done for maximum voltage level, faulty voltage level and “full” cell detection. 
     Next the computer connected to the A 0  line (FIG. 1) is checked for its on/off status by the power sharing detector M 2  to decide whether to continue with ultra-fast charging or switch to fast charging. 
     The battery is then checked for the inclusion of thermistor Y 9  at block M 6 . If a thermistor is used, dT/dt (rate of change of cell temperature) is measured at block M 7 . If a thermistor is not used, dV/dt (rate of change of battery voltage) is measured at block M 5 . At these two blocks the dT/dt or the dV/dt is monitored for the pre-measurement phase and the respective flags set accordingly when detection occurs. 
     The setting of either the dT/dt or dV/dt flag completes the pre-measurement phase and opens the gate for the final end-of-charge detection at M 9  (for detection of setting of −dV flag) and M 10  (for detection of the setting of the zero dV/dt flag) concurrently. Setting of either the −dV flag or zero dV/dt flag will complete the end-of-charge detection, after which charging will be replaced with the “burst” mode (trickle charge). 
     If the battery is not near to the end-of-charge point yet, a scan time follows during which the battery presence detection (by M 15 ), cell temperature detection (by M 11 ) and charging time detection (by M 14 ) are done. If the battery is removed, charging is stopped and the “burst” mode (trickle charging) takes over. In the “burst” mode, the battery contacts are continuously scanned and if a battery is reconnected, the whole charge cycle is repeated. 
     If cell temperature exceeds a maximum value Tmax, high current charging will be stopped and will be replaced with the “burst” mode. Similarly if the internally set timer M 14  counts down to zero before any other detection is made, ultra-fast/fast charging is also stopped. Otherwise the whole charging cycle will repeat itself from point “A” until terminated by the “burst” mode. 
     If the “burst” mode, the trickle charge current is set, M 22 . The battery presence detector M 15  detects if a “full” battery is removed and replaced with another pack. In that event, charging will restart from the beginning without the need for any power down and up again procedure. Otherwise, once in the “burst” mode, the charge cycle will remain in that mode until the power-on reset is applied again. 
     FIG. 4 is a block diagram of a battery charger monitor BCM. The battery charger monitor BCM comprises the ADC channel and filter M 3  connected to the battery voltage input terminal V batt , the ADC channel and filter M 4  connected to the cell temperature input Temp, the dV/dt detector M 5 , the thermistor detector M 6 , the dT/dt detector M 7 , the gate M 8 , a further gate B 4 , the −dV detector M 9  and the zero dV/dt detector M 10 . The gate M 16  is shown in FIG. 4, but only two of its inputs are illustrated. The gate M 16  is shown connected to the flip-flop M 17 . FIG. 4 also shows a timer B 11  which receives a clock signal Clock from the clock M 27  in FIG.  2  and produces outputs Tclk and Vclk. There now follows a more detailed description of the operation of the battery charger monitor BCM. It will be appreciated that FIG. 4 shows the ADC channels and filters M 3  and M 4  each as two components, namely an ADC channel B 1 ,B 7  respectively and a digital filter B 2 ,B 8  respectively. 
     The battery voltage is measured at the V batt  terminal and converted from its analog form to a digital form by one channel of the analog-to-digital converter B 1 . The digital value is then fed into the simple digital filter B 2  for filtering, through an 8-bit bus  60 . 
     Similarly the cell temperature is measured through the Temp terminal and fed into another channel of the analog-to-digital converter B 7  and filtered by the digital filter B 8 . The thermistor detector M 6  samples the 8bit information from the filter B 8  and determines whether a thermistor Y 9  is being used or not. IF yes, the dT/dt detector, M 7 , will be enabled and the dV/dt detector, M 5 , disabled. If otherwise, M 5  will be enabled and M 7  disabled. 
     If the dV/dt detector M 5  is enabled, it will monitor the gradient (dV/dt) of the voltage charging curve which is as illustrated in FIG.  5 . As can be seen in FIG. 5, there is a substantial increase in the gradient between points P 1  and P 2  and this causes a dV/dt flag to be set. If the dT/dt detector M 7  is enabled it will similarly monitor the gradient (dT/dt) of the temperature curve as illustrated in FIG. 6 until it detects a sharp increase in gradient, between points P 6  and P 7  on curve c for a NICD battery or points P 8  and P 9  on curve d for a NIMH battery when it will set a dT/dt flag. The gradient is monitored by making sequential measurements of voltage or temperature at interval durations (e.g. between points P 1  and P 2  in FIG. 5) generated by the timer B 11 . T clk  sets the interval duration for dT/dt measurements and V clk  sets the interval duration for dV/dt measurements. 
     When one of the dV/dt and the dT/dt flags is set, the −dV detector M 9  and the zero dV/dt detector M 10  are simultaneously activated, through the gate M 8 , enabling −dV (voltage drop) and zero dV/dt (voltage level) measurements to be taken concurrently. At this stage battery voltage measurements (through the 8-bit bus from the filter B 2 ) are taken by the −dV detector M 9  at one second intervals to monitor any negative voltage drop. Once this drop is detected (points P 3  and P 4 , FIG. 5 b ) a −dV flag is set. This indicates an end-of-charge condition in an NICD battery. 
     At the same time the battery voltage slope is monitored between points, the interval of which is set by a clock signal Z clk . Z clk  is a clock signal derived from the gate B 4 , the inputs of which come from the dV/dt detector M 5  (V clk ) or the dT/dt detector M 7  (T clk ) depending on which of these circuits is enabled for pre-measurements. Once no change in voltage has been detected between points P 3  and P 5  in FIG. 5, the zero dV/dt flag will be set, due to a flat voltage slope in this region. This indicates an end-of-charge condition in an NIMH battery. 
     Once the −dV flag or the zero dV/dt flag is set, a “high” level will be available at D input  18  of the flip-flop M 17  through the gate M 16 . This “high” level will be transferred to the Q output  20  of M 17  at the next clock pulse to enable trickle charging. The {overscore (Q)} output  22  of the flip-flop M 17  will be held “low” to dissable ultra-fast or fast charging. At this point the battery pack is deemed full and only a low capacity trickle charge is required, for maintenance, to replenish self-discharging of the cells. 
     At start-up, the set pin  34  of the flip-flop M 17  will be held “low” and the clear pin  35  held “high” (always) to disable ultra-fast or fast charging (“low” at the {overscore (Q)} output  22  and “high” at the Q output  20 ) no matter what signal is available at the D input  18 . Once the enable signal (a “high” level) arrives at the set pin  34 , the high current charging (ultra-fast or fast mode) is activated (“high” at the {overscore (Q)} output and “low” at the Q output) until detection is made by the −dV detector M 9  or the zero dV/dt detector M 10 , after which trickle charging will take over. 
     FIG. 7 is a circuit diagram for the negative (−dV) detector M 9 . 
     As described above with reference to FIG. 4, the battery voltage at terminal V batt  is fed into the analog-to-digital converter (ADC) B 1 . In the ADC, the battery voltage is converted from an analog form into a digital form and fed into the digital filter B 2 . After filtering, the 8-bit information is then stored in a V aver  register B 3 . A plurality of registers B 5 ,B 6 ,B 17  are connected to sequentially receive filtered voltage values. The V aver  register B 3  is connected to a V max  register B 5 , which is connected to V aver1  register B 6  which is connected to V aver2  register B 17 . 
     All the registers B 3 ,B 5 ,B 6  and B 17  are clocked by a signal clk from a timer B 18  which takes its input from clock M 27  in FIG.  2 . The signal clk has the same frequency as the measurement cycle (the frequency at which battery voltage measurements are taken). On the first clock pulse, data in the register B 3  is shifted into B 5 , with the latest battery voltage data being stored in B 3 . On the next cycle, the data is clocked through so that the contents of B 5  are shifted into B 6 , the contents of B 3  into B 5 , etc. Thus after four cycles all the registers V aver  (B 3 ), V max  (B 5 ), V aver1  (B 6 ) and V aver2  (B 17 ) should have data in them. 
     B 14  is a peak voltage detector which continuously compares the data from register B 3  at input  50  with that form register B 5  at input  52 . While input  50  is greater than or equal to input  52  an enable signal is fed to register B 5  so that the higher value (content of register B 3 ) will be loaded into register B 5  at the next clock cycle. Otherwise, the enable signal from peak detector B 14  will not be active and the content of register B 5  will not be changed at the next cycle. Thus the V max  register B 5  always contains the highest voltage level on record among all the registers. 
     A −dV detector B 9  compares the contents of register B 3 , which is the newest being read in, with that form register B 5  which holds the highest value. Once the content in register B 3  is lower than that in register B 5  by a predetermined value (e.g. 50 mV) and is detected by −dV detector B 9 , its Q output  56  will go “high”. 
     Registers B 6  and B 17  contain the previous voltage data prior to the detection of the voltage drop. Their data is fed together with that from register B 5  into a level detector B 10 . Only when all three data inputs are equal will the Q output  58  of level detector B 10  go “high”. 
     When both Q outputs from −dV detector B 9  and level detector B 10  are “high”, detected by a gate B 11 , a n-bit shift register B 12  is enabled. A “high” signal will be transferred to its Q 0  pin at the next clock pulse. This “high” signal will be transferred to the Q 1  pin and the signal at the input of shift register B 12  transferred to the Q 0  pin by a further clock pulse. Thus after n clock pulses from the moment both outputs from B 9  and B 10  go “high”, the original “high” level should be transferred to the Q n  pin. Thus it will take n successive verification by detectors B 9  and B 10  to have all the Q pins of shift register B 12  “high”. This system can be used for re-validation of any possible −dV detection, the number of times depending on the number of outputs that the shift register can offer. Only when all Q pins or shift register B 12  are “high” will output circuit B 13  confirm the validity of the detection. It will output a “high” signal at output  62  to disable ultra-fast or fast charging at the external charger circuit Y 2 . 
     In the case of a false detection where the contents of the register B 6  and B 17  are not equal to the contents of the register B 5 , it is most likely that a value corresponding to the amplitude of a voltage “spike” has been stored in the register B 5 . When this situation arises the Q output of the −dV detector B 9  will be “high” and the Q output of the level detector B 10  will be “low”. This will cause the output of an AND gate BB 1  to go “high” because the AND gate BB 1  has as one of its inputs the Q output of the −dV detector B 9 , and as its other input the Q output of the level detector B 10  inverted through an inverter gate BB 3 . Hence through the OR gate BB 2  the register B 5  will be enabled regardless of the state of the peak detector B 14 . Therefore the contents of the register B 3  will be clocked into the register B 5 , the false data in the register B 5  will be clocked into the register B 6 , and the data in the register B 6  will be clocked into the register B 17 . The next clock pulse or cycle will result in another false detection, as the false data is now in register B 6 , and result in the false data data being choked into register B 17 . Thus on the next clock pulse or cycle a further false detection will occur but the false data will be erased from register B 17  and the circuit of FIG. 7 can resume further measurement. It can be seen that in the event of the Q outputs of the −dV comparator B 9  and the level detector B 10  being high the output of the AND gate BB 1  is low and the peak detector B 14  either enables or disables the register B 5  though the OR gate BB 2 . 
     All readings in storage are updated during every battery voltage measurement in an ongoing process no matter whether there is any −dV detection or not. All measurements and re-checking are done without any interruption to charging and within a very short time frame (a few seconds) thus giving very quick response to the monitoring and avoiding overcharging, without any compromise to the accuracy. Also minimum filtering is needed, thus savings cost. 
     The −dV detection circuit described above with reference to FIG. 7 employs a detection method that makes use of the fact that the battery voltage changes very gradually, unlike switching noises which are in the range of hundreds of kHz. By maintaining measurements before the moment when −dV is suspected to occur, and also taking measurements after that moment, it is possible to filter out the switching noises and only act on genuine drops in voltage. 
     Referring to FIG. 9 a,  if the amplitude at V 3  is lower than that at V 2  by more than the threshold (e.g. 50 mV), the reading at V 1  is compared to that at V 2 . If amplitudes at V 1  and V 2  are not the same, then the detection is rejected as noise, as the voltage at V 1  and V 2  are not expected to differ due to the short time duration between measurement (typically one second interval). 
     If a voltage drop of more than 50 mV (−dV detection threshold) is detected from V 4  to V 5 , the voltage at V 6  is taken and compared to that at V 4 . If it is not consistent with the earlier voltage drop (from V 4  to V 5 ), the detection is ignored for the same reason. 
     Only a genuine voltage drop of more than 50 mV like that shown in FIG. 9 b  (from V 8  to V 9 ) will be treated as a true −dV detection, as V 7  and V 8  have the same amplitude and V 10  has a level which is more than 50 mV less than that at V 8 .

Technology Category: 5