Patent Document

BACKGROUND  
         [0001]    This invention relates generally to domino circuits.  
           [0002]    A static CMOS gate is a fully complementary logic gate with P and N-channel (i.e., p-channel and n-channel metal oxide semiconductor) devices configured to implement a desired logic function. A dynamic complementary metal oxide semiconductor (CMOS) gate includes an N-channel device logic structure having a pre-charge or output node precharged to the supply voltage with a single clocked P-channel device. The output node is conditionally discharged (evaluated) by a set of devices forming the logic structure, coupled to external ground.  
           [0003]    The clocked P-channel device has its gate coupled to an input clock signal. When the input clock signal is active, the output node is “precharged” through a P-channel device to the supply voltage. When the clock input is inactive, the output node is conditionally discharged (evaluated) through the set of devices forming the logic structure, to external ground. The logic structure may implement a logic function such as a NAND or a NOR logic function as examples.  
           [0004]    Dynamic or domino logic circuits are dynamic because operation of the circuit is controlled dynamically by an input clock signal. Domino logic units are typically arranged in a plurality of domino stages, each stage having logic cells, such as NAND gates or NOR gates as examples, with each stage separated by an inverting stage. In this arrangement, an input signal applied to the first stage while the clock signal is active, triggers operation of the remaining stages in sequence. This yields a domino-like signal propagation effect within the logic unit.  
           [0005]    During the evaluation phase, the inputs to the set of devices forming the logic structure only change from non-active to an active state. Otherwise, the output node may be corrupted without P-channel devices to pull the output node back up. Inverting stages are provided between each logic stage to facilitate proper precharging or evaluating of the individual domino circuits active during the precharge phase.  
           [0006]    Referring to FIG. 4, a single stage NAND gate domino circuit  10  includes a single P-channel device  12  in combination with a set of N—channel devices  14  forming a logic structure. A keeper  16  may include an inverter and a P-channel transistor. The keeper offsets any charge leakage that might occur at the output node when the N-channel devices  14  of the logic structure are inactive. A domino NAND gate may be referred to as a “clocked” domino gate because the input clock signal is connected to an N-channel device in series with the N-channel devices of the logic structure. The single N-channel device connected to the clock signal selectively blocks a power dissipation path between the external power supply and external ground during the precharge phase.  
           [0007]    In use, dynamic or domino logic circuits operate in phases including a precharge phase and an evaluate phase. During the precharge phase, the transistors of the logic structure of the domino circuit are precharged. During the evaluate phase, input signals may be applied to the gates of each of the transistors of the logic structure and the clock signal is active.  
           [0008]    As feature size and external power supplies are scaled as a result of advances in CMOS process technology, a significant decrease in the charge at the input and output nodes of domino circuits may result. This decrease in node charge may lead to an increase in soft error rates (SER) caused by cosmic radiation and packaging materials.  
           [0009]    During an SER event, domino circuits may generate errors while holding a high or active level at the precharge node. Noise immunity may be improved by adding a P-channel keeper. Although the robustness of a domino gate against soft errors may be enhanced by increasing the size of the keeper, this eventually leads to performance degradation. This may be due in part because contention may arise between the keeper and the N-channel devices of the logic structure. This degradation may be significant, in large fan-in domino topologies for example, as the effective width of the N-channel devices of the structure is small.  
           [0010]    Thus, there is a continuing need for better ways to decrease the soft error rates of domino circuits.  
         SUMMARY  
         [0011]    In accordance with one aspect, a domino circuit includes an output node and an input transistor coupled to the output node. A charge source is coupled to the node and the transistor to selectively charge the node depending on the signal applied to the transistor.  
           [0012]    Other aspects are set forth in the accompanying detailed description and claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 is a schematic depiction of one embodiment of the present invention;  
         [0014]    [0014]FIG. 2 is a schematic depiction of another embodiment of the present invention;  
         [0015]    [0015]FIG. 3 is a schematic depiction of another embodiment of the present invention; and  
         [0016]    [0016]FIG. 4 is a depiction of a corresponding structure in accordance with the prior art. 
     
    
     DETAILED DESCRIPTION  
       [0017]    Referring to FIG. 1, a domino circuit  40  includes a P-channel transistor  42  having its source coupled to an external power supply potential. The drain of the transistor  42  is coupled to the output node  44 . A set of three N-channel input transistors  46 ,  48  and  50  form a logic structure  51 . The devices  46 ,  48  and  50  are illustrated as being coupled to the drain of the P-channel device  42 . In one embodiment of the present invention, the logic structure  51  is a NAND gate formed of N-channel transistors. An additional N-channel transistor  52  has its source coupled to external ground and its gate connected to a clock signal that also drives the gate of the P-channel transistor  42 . The drain of the transistor  52  is coupled to the logic structure  51 , and in the illustrated embodiment, the source of the input transistor  50 .  
         [0018]    While a logic structure  51  that is a NAND gate having three input transistors is illustrated, a variety of other logic structures may be implemented using the principles set forth in the present invention. Another logic structure normally implemented with domino circuits is NOR gate as an example.  
         [0019]    When the clock signal (CLOCK) is active or low, the output node  44  is charged up and is prevented from being discharged because the transistor  52  is not conducting. This condition generally corresponds to the precharge state of the domino circuit  40 .  
         [0020]    Each input transistor  46 ,  48  and  50  has its gate coupled to receive an input signal indicated as I 1 , I 2  or I 3 . Each input signal is also coupled to a P-channel transistor  54 ,  56  or  58 , each arranged to act as a keeper device. Each P-channel transistor  54 ,  56  and  58  has its drain coupled to the output node  44  and its source coupled to the external supply voltage. In one embodiment of the present invention, the drains of adjacent pairs of P-channel transistors, such as the transistors  54  and  56 , may share drain diffusions as indicated in dashed ovals in FIG. 1.  
         [0021]    Also coupled to the output node  44  is an inverter  60  and a P-channel transistor  62  that form a keeper circuit. Like the transistors  54 ,  56  and  58 , the transistor  62  is also coupled between the external supply voltage and the output node  44 .  
         [0022]    As an example, where the input transistors  46 ,  48  and  50  are eight microns in width, and the transistor  52  is also eight microns in width, the effective width of the combined transistors is two microns. In this case, the transistors  54  to  62  may be relatively smaller devices, each have a width of about one micron for example. However, as can been seen in FIG. 2, due to the use of a plurality of transistors  54 ,  56 ,  58  and  62 , the node  44  charge sustaining ability may be increased.  
         [0023]    When all of the input signals I 1 , I 2  and I 3  are high, the transistors  54 ,  56 , and  58  are all shut off and thus the transistors  54 ,  56  and  58  do not deteriorate the delay. However, when one or more of the input signals I 1 , I 2  or I 3  is inactive or low, the domino circuit  40  does not evaluate and one or more of the P-channel transistors  54 ,  56  and  58  is enabled or active. Thus, the transistor  54 ,  56  or  58  coupled to an inactive input signal tends to sustain the potential on the output node  44 . For example, if I 2  is inactive or low, P-channel transistor  56  may be active. By sustaining the potential on the output node  44 , the soft error rate may be improved.  
         [0024]    In some embodiments of the present invention, the effective keeper strength (which is a result of the transistors  54 ,  56 ,  58  and  62 ) may be increased two to four times compared to the design shown in FIG. 2. This domino technology may be used effectively in address decoders and particularly in situations where domino circuits are driven directly from latches.  
         [0025]    Thus, in the circuit  10 , the transistors  54 ,  56  and  58  act as data driven keepers. That is, they selectively sustain the potential on the node  44  depending on the state of the input signals I 1 , I 2  and I 3 . Where the input signal to a given transistor in the logic structure  51  is low, a keeper transistor  54 ,  56  or  58  coupled to that transistor&#39;s gate may actively supply charge to the node  44 .  
         [0026]    While the present invention is illustrated as using n-channel transistors in the logic structure, n-channel transistors may be used in place of p-channel transistors and vice versa.  
         [0027]    The principles described in connection with a NAND gate domino circuit can also be applied to an exclusive OR (XOR) domino circuit as shown in FIG. 2. In this case, a p-channel transistor  66  is coupled to an output node  74 . A transistor  68  is also coupled to the output node  74  and has the signal B coupled to its gate. Anther transistor  70  has an input signal A coupled to its gate. A clock signal is coupled to the gate of the p-channel transistor  66  and an n-channel transistor  72  which is also coupled to ground. A second pair of transistors  88  and  90  have the input signals B and A coupled to their gates. Each of the transistors  68 ,  70 ,  80  and  90  also have their gates coupled to a p-channel transistor  76 ,  78 ,  80  or  82  as illustrated. The drains of the transistors may share diffusions as indicated in dashed lines. A keeper transistor  84  has its gate coupled to an inverter  86  as described previously.  
         [0028]    In this case, the transistors  76 ,  78 ,  80  and  82  act as data driven keepers. That is, they selectively sustain a potential on the node  74  depending on the state of the input signals A, B, {overscore (B)} and {overscore (A)}. Where the input signal to a given transistor in the logic structure is low, a keeper transistor  76 ,  78 ,  80  or  82  coupled to that transistors gate may actively supply charge to the node  74 .  
         [0029]    Referring next to FIG. 3, an embodiment of the present invention in connection with a NOR domino gate receives the input signals I 1 , I 2  and I 3  on the gates of transistors  96 ,  112  and  114 . These gates are also coupled to keeper p-channel transistors  102 ,  104  and  106 . In this case, the p-channel transistors  102 ,  104  and  106  are connected in series between a supply voltage and an output node  100 . Also coupled to an output node  100 , is an inverter  110  and a keeper p-channel transistor  108 . A clock input signal in connected to the gate of a p-channel transistor  94  and an n-channel transistor  98 . Again, the p-channel keeper transistors  102 ,  104  and  106  maintain the potential on the output node  100  when an input signal to a given transistor  96 ,  112  or  114  is low by actively supplying charge to the node  100 .  
         [0030]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Technology Category: 5