Patent Document

CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation-in-part of U.S. patent application Ser. No. 10/219,260, filed Aug. 16, 2002, the entire disclosure of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to a novel architecture for a CMOS-based image sensor, and in particular to an architecture suitable for use at ultra-low voltages (eg below 1V). 
       BACKGROUND OF THE INVENTION 
       [0003]    CMOS-based image sensors have a wide range of potential applications since they may be integrated into a number of electronic products such as personal computers, cellular telephones, personal digital assistants and many others. CMOS active pixel sensors (APS) exploit the mature CMOS industry and can compete with charge coupled devices for low power, high levels of integration and functionality. 
         [0004]    In recent years much effort has been made into reducing the required voltage supply to facilitate the incorporation of APS devices in portable applications such as mobile phones, and personal digital assistants which all need to minimize power consumption in order to maximize battery life. However, if the voltage supply goes below 1V, this has an enormous impact on the signal-to-noise ratio and the dynamic range of the pixels, not only because of the lower allowable signal voltages, but also because of the presence of larger noise voltages due to lower currents. In order to maximize the signal-to-noise ratio and dynamic range of the pixel, the signals have to be as large as possible, preferably from rail-to-rail, and so the pixel has to be equipped with a rail-to-rail input as well as a rail-to-rail output stage. 
       PRIOR ART 
       [0005]      FIG. 1(   a ) shows the structure of a conventional APS design. In this structure the highest available output voltage V out  is limited by the V T  drop of the NMOS reset transistor M 1  and the source follower M 2 , and therefore the maximum available output swing is only V DD −2V T −V Dsat  and this significantly limits the dynamic range of the CMOS APS of  FIG. 1(   a ) as is shown in  FIG. 1(   b ). The APS shown in  FIG. 1(   a ) cannot function at a supply voltage of 1V or below, or at least cannot function without very complex output circuits. 
         [0006]    The voltage output of the active pixel sensor element will have a slope which depends on the illumination intensity with the slope increasing with increasing intensity. The slope, and thus the intensity, may be extracted from the output using known double sampling (DS) or correlated double sampling (CDS) techniques.  FIG. 5  illustrates a conventional CDS technique in which the voltage difference is measured over a fixed time interval. A disadvantage with a conventional CDS technique, however, is that it requires an analog-to-digital converter (ADC) capable of a very fine degree of resolution, which is quite difficult to achieve in an ultra low voltage environment. For example, with an APS capable of operating at low voltages as described further herein, at 1V operation the output swing is only 0.55V and to achieve 8-bits resolution the ADC needs to have a resolution of 2 mV. This implies that the practical dynamic range of an APS is governed not only by the APS architecture itself, but also by the readout method. 
       SUMMARY OF THE INVENTION 
       [0007]    According to the present invention there is provided an optical sensor comprising at least one pixel wherein the pixel generates an output voltage that changes at a rate dependent on the light intensity incident on the pixel, and wherein means are provided for measuring the time for the pixel output voltage to change from a first predefined level to a second predefined level so as to produce an output indicative of the incident light intensity. 
         [0008]    According to still further aspect the present invention also provides a method of generating an output from a pixel of an optical sensor wherein the pixel generates an output voltage that changes at a rate dependent on the light intensity incident on the pixel, the method comprising measuring the time for the pixel output voltage to change from a first predefined level to a second predefined level. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings, in which: 
           [0010]      FIGS. 1(   a ) and ( b ) illustrate (a) a conventional APS architecture and (b) the available output voltage swing, 
           [0011]      FIGS. 2(   a ), ( b ) and ( c ) show (a) the architecture of a CMOS APS, (b) the available output voltage swing and (c) the same structure with the reset transistor changed to NMOSFET and the photodiode connected to the power supply, 
           [0012]      FIGS. 3(   a ) and ( b ) show outputs from a CMOS APS and, in  FIG. 3(   b ) the output from the prior art by way of comparison, 
           [0013]      FIGS. 4(   a ), ( b ), ( c ) and ( d ) show cross-sectional views of four possible structures of the CMOS APS, (a) on bulk silicon with light coming from the top, (b) on SOI with light coming from the top, (c) on SOI with light coming from the bottom, and (d) on bulk silicon with light coming from the bottom after thinning the silicon substrate 
           [0014]      FIG. 5  illustrates a conventional readout methodology, and 
           [0015]      FIG. 6  illustrates a readout methodology according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0016]    Referring firstly to  FIG. 2(   a ) a CMOS APS will now be described. It will be understood that  FIG. 2(   a ) shows just one pixel and in use an array of pixels may be provided. In comparison with the conventional APS architecture shown in  FIG. 1(   a ) it will be noted that the NMOS reset transistor M 1  of the prior art has been replaced by a PMOSFET reset transistor M 1 . This allows the input node to go all the way to V DD  when the chip is reset. After reset, the photodiode will discharge N 1  at a rate that is proportional to the incident light intensity. This signal is amplified by the source follower M 2  and arrives at the node V outn . As in the prior art M 3  is a NMOS transmission gate that is provided to allow the signal to pass upon application of a row select signal. In this signal path there will be an inevitable drop V T  due to the source follower M 2 , and to compensate for this a complementary signal path is provided comprising a PMOS common drain amplifier M 5  and an associated PMOS transmission gate M 4 . This complementary signal path produces an output V outp  and the two outputs (V outn  and V outp ) are combined to give the pixel output V out . 
         [0017]    As mentioned above, a PMOS reset transistor is used to eliminate the threshold voltage drop between V DD  and the node N 1 . In addition, two complementary source followers M 2  and M 5  are used to amplify the signal on node N 1  and the two complementary paths are combined to give the pixel output. 
         [0018]    The input and output swing of the NMOS source follower M 2  is given by: 
         [0000]    
       
      
       V 
       dsat 
       +V 
       TN 
       &lt;V 
       Ninput 
       &lt;V 
       DD  
      
     
         [0000]    
       
      
       V 
       dsat 
       &lt;V 
       Noutput 
       &lt;V 
       DD 
       −V 
       TN  
      
     
         [0000]    Where V Ninput  and V Noutput  are the input and output swings of the node N 1  respectively. V TN  is the threshold voltage of the N-type source follower M 2  and V dsat  is the voltage across the current source. 
         [0019]    The input swing of the PMOS source follower M 5  is given by: 
         [0000]      0 &lt;V   Pinput   &lt;V   DD   −V   dsat   −V   TP    
         [0000]    
       
      
       V 
       TP 
       &lt;V 
       Poutput 
       &lt;V 
       DD 
       −V 
       dsat  
      
     
         [0020]    In order to ensure a full rail-to-rail input, the supply voltage V DD  has to be at least V TN +V TP +2V dsat . At the same time, the available output swing is close to rail-to-rail: 
         [0000]    
       
      
       V 
       dsat 
       &lt;V 
       output 
       &lt;V 
       DD 
       −V 
       dsat  
      
     
         [0021]    This maximum available output swing is shown schematically in  FIG. 2(   b ) and it will be seen from a simple comparison of  FIGS. 1(   b ) and  2 ( b ) that the architecture of the present invention, at least in its preferred forms, provides for a much greater output swing. In particular this allows the minimum supply voltage to be reduced, for example to as low as 1.2V in 0.25 μm CMOS technology where typically V TN =0.4V, V TP =0.6V and V dsat =0.1V. Furthermore if the bias transistors are operated in the triode or weak inversion mode, the supply voltage can be even lower. 
         [0022]      FIG. 2(   c ) shows the complementary structure derived from the pixel architecture given in  FIG. 2(   b ) with the photodiode connected to the power supply voltage and the reset transistor replaced by an NMOSFET connected to ground. 
         [0023]      FIG. 3  illustrates experimental outputs from a CMOS APS using the TSMC [Taiwan Semiconductor Manufacturing Company]0.25 μm CMOS process with 5 metal and 1 polysilicon layer.  FIG. 3(   a ) shows the outputs of the two complementary signal paths at a 1V supply voltage, while the output signal after their combination is shown in  FIG. 3(   b ).  FIG. 3(   b ) also shows a conventional trace from a prior art design (this is the lower trace in  FIG. 3(   b )). It can be seen from  FIG. 3(   b ) that the design of the CMOS APS is capable of working at a 1V supply voltage, whereas the conventional prior art design is incapable of so doing. 
         [0024]    It will also be understood that in the CMOS APA of  FIG. 2(   a ) the reset transistor could be a NMOSFET transistor, in which case source follower M 2  would be PMOS, and complementary source follower M 5  would be NMOS. 
         [0025]    An active pixel sensor could be implemented through bulk silicon technology, but could also be implemented using silicon-on-insulator (SOI) technology.  FIG. 4(   a ) shows an example of a device manufactured using bulk silicon technology and  FIG. 4(   b ) shows and example of a device manufactured using SOI technology. SOI technology uses a thin layer of silicon on an insulator and all active devices are fabricated in the thin layer. Compared to bulk technology SOI technology has a number of advantages including: better isolation between pixels leading to smaller interference between pixels; SOI CMOS technology does not require a separate well for the PMOSFET and can thus provide a higher fill-factor because the transistors in the pixel can be packed closer together; and SOI can further reduce the power consumption due to the smaller loading that has to be driven. 
         [0026]    In  FIG. 4(   a ) and  FIG. 4(   b ) light is incident on the top of the sensor. However, light could also be incident from the bottom as shown in  FIG. 4(   c ) in which the active pixel sensor is implemented on a transparent substrate such as sapphire. Alternatively, the back side of the device could be made transparent by forming it to be very thin by polishing as shown in  FIG. 4(   d ). 
         [0027]    The voltage output of the active pixel sensor element will have a slope which depends on the illumination intensity with the slope increasing with increasing intensity. The slope, and thus the intensity, may be extracted from the output using known double sampling (DS) or correlated double sampling (CDS) techniques.  FIG. 5  illustrates a conventional CDS technique in which the voltage difference is measured over a fixed time interval. A disadvantage with a conventional CDS technique, however, is that it requires an analog-to-digital converter (ADC) capable of a very fine degree of resolution, which is quite difficult to achieve in an ultra low voltage environment. For example, even with an APS according to an embodiment of the invention, at 1V operation the output swing is only 0.55V and to achieve 8-bits resolution the ADC needs to have a resolution of 2 mV. This implies that the practical dynamic range of an APS is governed not only by the APS architecture itself, but also by the readout method. 
         [0028]      FIG. 6  illustrates a novel readout methodology that may preferably be used in place of a conventional CDS technique. In the method of  FIG. 6  two fixed voltages V a  and V b  are defined and the time taken for the pixel output to drop from V a  to V b  is measured. This time is inversely proportional to the illumination intensity. In this method, the dynamic range depends on the conversion speed of the ADC rather than its resolution and this is easier to control with precision, especially in an ultra low voltage environment. This novel methodology is particularly suited for use with CMOS active pixel sensors as described above but could be used with other forms of sensors. The design is particularly suitable for use with sensors capable of use at ultra low voltages (eg below 1V). 
         [0029]    It should also be noted that while in the above examples the output voltage will fall at a rate dependent on the incident light intensity, it is also possible to reconfigure the sensor circuit so that the output voltage increases at a rate dependent on the incident light intensity. For example, looking at  FIG. 2(   a ) rather than having the diode connected to ground and the reset transistor to V dd , this could be reversed with the reset transistor connected to ground and the diode to V dd  as is shown in  FIG. 2(   c ).

Technology Category: 5