Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional application based upon U.S. patent application Ser. No. 14/918,788, filed Oct. 21, 2015 which is a Divisional of U.S. patent application Ser. No. 14/471,278, filed on Aug. 28, 2014, which is a Continuation Application of U.S. application Ser. No. 13/774,453, filed Feb. 22, 2013, which claims the benefit of priority from Japanese Patent Application No. 2012-037968 filed on Feb. 23, 2012, the disclosures of which are incorporated herein in their entirety by reference. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to semiconductor devices, and can be suitably used for the semiconductor devices incorporating an SRAM (Static Random Access Memory), for example. 
         [0003]    As miniaturization of semiconductor devices proceeds, it is becoming more difficult to meet the criteria of a drop of a power supply voltage, power EM (ElectroMigration), and the like. As the countermeasure therefor, adding power supply terminals and/or adding power supply vias are known, but in either case, the interconnectivity might be degraded. 
         [0004]    In connection with the above description, Patent Document 1 (Japanese Patent Laid-Open No. 2001-36049) discloses a description of a semiconductor memory device. This semiconductor memory device includes a plurality of MIS transistors, a main bit line, a sub bit line, a first switching element, a first source line, a second source line, and a word line. Here, the MIS transistors each have a floating gate, a control gate, a source, and a drain. The sub bit line is provided for each set formed for every multiple MIS transistors of a plurality of MIS transistors. The first switching element selectively couples the sub bit line to the main bit line. The first source line is coupled in common to the sources of the multiple MIS transistors in a plurality of sets. The second source line is coupled in common to the sources of the multiple MIS transistors in each of the sets, to which the first source line is not coupled. The word line couples one control gate of multiple MIS transistors in one set to one control gate of multiple MIS transistors in other set. The word line coupled to the control gate of the MIS transistors each having the source, to which the first source line is coupled, includes a first wiring and a second wiring. Here, the first wiring includes a first nonmetallic electric conductor. The second wiring includes metal, and is disposed in a layer different from that of the first wiring and is coupled to the first wiring. The word line coupled to the control gate of multiple MIS transistors each having the source, to which the second source line is coupled, includes a first layer wiring. The first source line and the sub bit line include a second nonmetallic electric conductor. The second source line includes metal. 
         [0005]    Moreover, Patent Document 2 (Japanese Patent Laid-Open No. 2008-227130) discloses a description of a semiconductor integrated circuit. A plurality of standard cells is arranged in this semiconductor integrated circuit. This semiconductor integrated circuit includes a first cell power supply wiring, a second cell power supply wiring, a first upper-layer power supply wiring, and a second upper-layer power supply wiring. Here, the first cell power supply wiring extends in one direction, and supplies current to the standard cells. The second cell power supply wiring is wired in parallel to the first cell power supply wiring, and supplies current to the standard cells. The first upper-layer power supply wiring is wired perpendicularly to the first and second cell power supply wirings, in an upper layer of the first and second cell power supply wirings, and is coupled to the first cell power supply wiring through a via. The second upper-layer power supply wiring is wired perpendicularly to the first and second cell power supply wirings, in an upper layer of the first and second cell power supply wirings, and is coupled to the second cell power supply wiring through a via. In a region overlapping with the first upper-layer power supply wiring and including a portion, in which a via coupling the first cell power supply wiring and the first upper-layer power supply wiring is disposed, the first cell power supply wiring includes a first wide portion with a width wider than the width of a region not overlapping with the first and second upper-layer power supply wirings. 
         [0006]    Furthermore, Patent Document 3 (Japanese Patent Laid-Open No. 2009-49034) discloses a description of a semiconductor device. This semiconductor device includes an interlayer insulating film, a lower wiring layer, an upper wiring layer, and a via hole. Here, the lower wiring layer is disposed on the lower side of the interlayer insulating film. The upper wiring layer is disposed on the upper side of the interlayer insulating film. The via hole extends through the interlayer insulating film, and electrically couples a wiring belonging to the lower wiring layer and a wiring belonging to the upper wiring layer. This semiconductor device has the following features. That is, a plurality of wiring lines and a contact region are provided. Here, the wiring lines extend along a predetermined direction in the lower wiring layer. The contact region is formed by partially coupling at least two wiring lines, and contacts with a via hole. Moreover, in the wiring lines, a void is present in a first interlayer insulating film located between wiring lines adjacent to each other. In a second interlayer insulating film located between a contact portion of the via hole in the contact region and a wiring line adjacent to the contact region, a void is not present. 
         [0007]    Moreover, Patent Document 4 (Japanese Patent Laid-Open No. 2011-14637) discloses a description of a semiconductor device. This semiconductor device includes first and second wirings, third and fourth wirings, a fifth wiring, a first contact conductor, and a second contact conductor. Here, the first and second wirings are provided in a first wiring layer and extend in parallel in a first direction. The third and fourth wirings are provided in a second wiring layer and extend in parallel in a second direction intersecting the first direction. The fifth wiring is provided in a third wiring layer located between the first wiring layer and the second wiring layer. The first contact conductor couples the first wiring and the third wiring. The second contact conductor couples the second wiring and the fourth wiring. Moreover, the first and second contact conductors are arranged in the first direction. 
       SUMMARY 
       [0008]    The present invention has been made in view of the above circumstances and provides semiconductor devices, in which power supply wirings are reinforced without sacrificing the interconnectivity of the semiconductor devices. The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings. 
         [0009]    Hereinafter, a measure for solving the above-described problems is described using reference numerals to be used in “DETAILED DESCRIPTION”. These reference numerals are attached to clarify a correspondence between the description of the claims and “DETAILED DESCRIPTION”. However, these reference numerals shall not be used for interpretation of the technical scope of the inventions described in the claims. 
         [0010]    According to an embodiment, when three wirings (VDD 2 , VSS 2 , ARVSS 2 ) are formed in parallel in the same wiring layer and the center wiring (ARVSS 2 ) among them is shorter than the outer wirings (VDD 2 , VSS 2 ), projecting portions ( 2 D 1 ,  2 D 2 ,  2 S 1 ,  2 S 2 ) integrated into the outer wirings (VDD 2 , VSS 2 ) are formed utilizing a free space (VS 2 ) remaining over the extension line of the center wiring (ARVSS 2 ). 
         [0011]    According to the embodiment, for example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portions. At this time, because the projecting portions are disposed in the free space, the interconnectivity is not sacrificed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1A  is a plan block circuit diagram schematically showing the overall configuration of a typical SRAM; 
           [0013]      FIG. 1B  is a circuit diagram showing the detailed configuration of a memory cell included in a memory cell array shown in  FIG. 1A ; 
           [0014]      FIG. 1C  is a plan view extracting and showing a semiconductor substrate and a first wiring layer of the memory cell shown in  FIG. 1B  and its peripheral region; 
           [0015]      FIG. 1D  is a plan view extracting and showing the first wiring layer and a second wiring layer of the region shown in  FIG. 1C ; 
           [0016]      FIG. 1E  is a plan view extracting and showing the second wiring layer and a third wiring layer of the region shown in  FIG. 1C ; 
           [0017]      FIG. 1F  is a plan view showing a wider range of the second wiring layer and third wiring layer shown in  FIG. 1E ; 
           [0018]      FIG. 1G  is a plan view showing a positional relation between various wirings formed in a third wiring layer and a fourth wiring layer of an SRAM according to a conventional art; 
           [0019]      FIG. 1H  is a block circuit diagram schematically showing the configuration of wirings related to a local ground line of a memory cell array in a typical SRAM; 
           [0020]      FIG. 1I  is a block circuit diagram schematically showing the configuration of wirings related to an external power supply voltage line and an external ground voltage line VSS of the memory cell array in a typical SRAM; 
           [0021]      FIG. 1J  is a block circuit diagram schematically showing the configuration of an impurity region in the typical SRAM and wirings related to power feeding to the impurity region; 
           [0022]      FIG. 2A  is a plan view showing the configuration of a wiring portion  2  according to a first embodiment; 
           [0023]      FIG. 2B  is a plan view showing the configuration of an external power supply voltage line VDD 2  and an external ground voltage line VSS 2  according to the first embodiment; 
           [0024]      FIG. 3A  is a plan view showing the configuration of a wiring portion  3  according to a second embodiment; 
           [0025]      FIG. 3B  is a plan view showing the configuration of an external power supply voltage line VDD 3  and an external ground voltage line VSS 3  according to the second embodiment; 
           [0026]      FIG. 4A  is a plan view showing the configuration of a wiring portion  4  according to a third embodiment; 
           [0027]      FIG. 4B  is a plan view showing the configuration of an external power supply voltage line VDD 4  and an external ground voltage line VSS 4  according to the third embodiment; 
           [0028]      FIG. 5A  is a plan view showing the configuration of a wiring portion  5  according to a fourth embodiment; 
           [0029]      FIG. 5B  is a plan view showing the configuration of an external power supply voltage line VDD 5  and an external ground voltage line VSS 5  according to the fourth embodiment; 
           [0030]      FIG. 6A  is a plan view showing the configuration of a wiring portion  6  according to a fifth embodiment; 
           [0031]      FIG. 6B  is a plan view showing the configuration of external power supply voltage lines VDD 6   a  and VDD 6   b  according to the fifth embodiment; 
           [0032]      FIG. 6C  is a plan view showing the configuration of external ground voltage lines VSS 6   a  and VSS 6   b  according to the fifth embodiment; 
           [0033]      FIG. 7A  is a plan view showing the configuration of a wiring portion  7  according to a sixth embodiment; 
           [0034]      FIG. 7B  is a plan view showing the configuration of external power supply voltage lines VDD 7   a  and VDD 7   b  according to the sixth embodiment; 
           [0035]      FIG. 7C  is a plan view showing the configuration of external ground voltage lines VSS 7   a  and VSS 7   b  according to the sixth embodiment; 
           [0036]      FIG. 8A  is a plan view showing the configuration of a wiring portion  8  according to a seventh embodiment; 
           [0037]      FIG. 8B  is a plan view showing the configuration of external power supply voltage lines VDD 8   a  and VDD 8   b  according to the seventh embodiment; and 
           [0038]      FIG. 8C  is a plan view showing the configuration of external ground voltage lines VSS 8   a  and VSS 8   b  according to the seventh embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0039]    With reference to the accompanying drawings, forms for implementing semiconductor devices according to the present invention are described hereinafter. 
       First Embodiment 
       [0040]      FIG. 1A  is a plan block circuit diagram schematically showing the overall configuration of a typical SRAM. The configuration of the SRAM shown in  FIG. 1A  is described. This SRAM includes a memory mat circuit MM, an output circuit Out, a word driver circuit WdD, a row decoder RD, a control circuit Cnt, a column decoder CD, a word line WL, a first bit line BL and a second bit line /BL constituting a bit line pair, a cell power supply line ARVDD, and a local ground line ARVSS. Here, the bit line pair BL and /BL, the cell power supply line ARVDD, and the local ground line ARVSS are preferably provided in plural numbers, respectively. 
         [0041]    The memory mat circuit MM includes a memory cell array MCA, a first ground line switch circuit ARGSw 1 , and a second ground line switch circuit ARGSw 2 . The memory cell array MCA includes a plurality of memory cells MC arranged in a vertical and horizontal array. 
         [0042]    The output circuit Out includes a column selection switch circuit CSS, a cell power-supply voltage line control circuit ARVC, a sense amplifier circuit SA, and a write driver circuit WtD. 
         [0043]    A connection relation between the components of the SRAM shown in  FIG. 1A  is described. The cell power-supply voltage line control circuit ARVC and the memory cell MC are coupled to each other via the cell power supply line ARVDD. Here, a plurality of memory cells MC horizontally arranged in  FIG. 1A  is preferably coupled to the same cell power supply line ARVDD. Moreover, a plurality of memory cells MC vertically arranged in  FIG. 1A  is preferably grounded via the same local ground line ARVSS. 
         [0044]    The column selection switch circuit CSS and the memory cell MC are coupled to each other via the bit line pair BL and /BL. Here, preferably, the memory cells MC horizontally arranged in  FIG. 1A  are coupled to each other via the same first bit line BL and also coupled to each other via the same second bit line /BL. 
         [0045]    The word driver circuit WdD and the memory cell MC are coupled to each other via the word line WL. Here, the memory cells MC vertically arranged in  FIG. 1A  are preferably coupled to the same word line WL. 
         [0046]    The operation of the SRAM shown in  FIG. 1A  is described. The control circuit Cnt receives a chip enable signal CEN, a write enable signal WEN, and an address signal Add. When the chip enable signal CEN indicates an inactive state, the control circuit Cnt is turned off. When the chip enable signal CEN indicates an active state, the control circuit Cnt is turned on and a read operation and a write operation of the SRAM are carried out. 
         [0047]    When the write enable signal WEN indicates “data write”, the control circuit Cnt activates the write driver circuit WtD. The write driver circuit WtD is activated during the write operation and transfers an input data signal Din to the column selection switch circuit CSS. The write driver circuit WtD becomes inactive except during the write operation. 
         [0048]    When the write enable signal WEN indicates “data read”, the control circuit Cnt activates the sense amplifier circuit SA. The sense amplifier circuit SA is activated during the read operation, and amplifies a weak read-out data signal transferred from the column selection switch circuit CSS to generate an output data signal Dout. The sense amplifier circuit SA becomes inactive except during the read operation. 
         [0049]    The control circuit Cnt generates a row address RAdd and a column address CAdd based on the address signal Add. 
         [0050]    The row decoder RD receives and decodes the row address RAdd, and controls the word driver circuit WdD based on the decoded result. The word driver circuit WdD includes a plurality of word drivers corresponding to each of a plurality of rows. A word driver corresponding to a row which the decoded result of the row address RAdd indicates is activated to drive the corresponding word line WL. 
         [0051]    The column decoder CD receives and decodes the column address CAdd, and controls the column selection switch circuit CSS and the cell power-supply voltage line control circuit ARVC based on the decoded result. 
         [0052]    The column selection switch circuit CSS selects a bit line pair BL and /BL corresponding to the column address CAdd among a plurality of bit line pairs BL and /BL corresponding to a plurality of rows, respectively. The selected bit line pair BL and /BL are coupled to the sense amplifier circuit SA during the read operation, and are coupled to the write driver circuit WtD during the write operation. Note that, the selected bit line pair BL and /BL are charged to a level of the external power supply voltage Vdd by a non-illustrated bit line precharge circuit before the read operation or write operation is executed. 
         [0053]    The cell power-supply voltage line control circuit ARVC controls, for each column, the voltage level of the cell power supply line ARVDD provided for each column. During the write operation, the cell power-supply voltage line control circuit ARVC decreases the voltage of the cell power supply line ARVDD of a selected column from the level of the external power supply voltage Vdd, but maintains the voltage of the cell power supply line ARVDD of the other columns at the level of the external power supply voltage Vdd. Moreover, during the read operation and during standby, the cell power-supply voltage line control circuit ARVC maintains the voltage of all the cell power supply lines ARVDD at the level of the external power supply voltage Vdd. 
         [0054]      FIG. 1B  is a circuit diagram showing the detailed configuration of a memory cell MC [m, n] included in the memory cell array MCA shown in  FIG. 1A . Here, array numbers m and n indicate the column and row in the memory cell array MCA shown in  FIG. 1A , respectively. Note that, all the memory cells MC included in the memory cell array MCA preferably have the same configuration. 
         [0055]    The components of the memory cell MC[m, n] shown in  FIG. 1B  are described. The memory cell MC includes first and second P-channel transistors P 1 , P 2 , first to fourth N-channel transistors N 1  to N 4 , a first storage node SN, and a second storage node /SN. 
         [0056]    The connection relation between the components of the memory cell MC[m, n] shown in  FIG. 1B  is described. The cell power supply line ARVDD is coupled in common to a drain of a first P-channel transistor P 1  and a drain of a second P-channel transistor P 2 . The local ground line ARVSS is coupled in common to a drain of the first N-channel transistor N 1  and a drain of the second N-channel transistor N 2 . The first storage node SN is coupled in common to a source of the first P-channel transistor P 1 , a gate of the second P-channel transistor P 2 , a source of the first N-channel transistor N 1 , a gate of the second N-channel transistor N 2 , and a drain of a third N-channel transistor N 3 . The second storage node /SN is coupled in common to a gate of the first P-channel transistor P 1 , a source of the second P-channel transistor P 2 , a gate of the first N-channel transistor N 1 , a source of the second N-channel transistor N 2 , and a source of a fourth N-channel transistor N 4 . The m-th column word line WL[m] is coupled in common to a gate of the third N-channel transistor N 3  and a gate of the fourth N-channel transistor N 4 . The first bit line BL[n] in the n-th row is coupled to a source of the third N-channel transistor N 3 . The second bit line /BL[n] in the n-th row is coupled to a drain of the fourth N-channel transistor N 4 . 
         [0057]    A typical SRAM is formed by arranging various wirings in a plurality of overlapped wiring layers, and also by arranging vias and contacts that extend through all or some of the wiring layers and couple various wirings. Here, as an example, it is assumed that the wirings related to the memory cell shown in  FIG. 1B  are arranged in a first wiring layer that is the bottom layer. It is assumed that the first bit lines BL and BL[n], the second bit line /BL and /BL[n], and the cell power supply line ARVDD shown in  FIGS. 1A and 1B  are arranged in a second wiring layer formed over the first wiring layer. It is assumed that the word line WL and the local ground line ARVSS shown in  FIGS. 1A and 1B  are arranged in a third wiring layer formed over the second wiring layer. 
         [0058]      FIG. 1C  is a plan view extracting and showing the semiconductor substrate and the first wiring layer of the memory cell MC[m, n] shown in  FIG. 1B  and its peripheral region. 
         [0059]    The components shown in  FIG. 1C  are described. First, over the semiconductor substrate, there are formed four N-channel impurity regions NW 1  to NW 4 , four P-channel impurity regions PW 1 A, PW 1 B, PW 2 A and PW 2 B, and 12gate electrode wirings G 1  to G 12 . Note that, in regions other than the above-described regions over the semiconductor substrate, an element isolation region is formed. Next, 16 first layer wirings M 101  to M 116  are formed in the first wiring layer. Furthermore, between the semiconductor substrate and the first wiring layer, there are formed 18 first layer wiring-impurity region contacts VN 11  to VN 13 , VN 21  to VN 23 , VN 31  to VN 33 , VN 41  to VN 43 , VP 11  to VP 13 , and VP 21  to VP 23  and four first layer wiring-gate electrode wiring contacts VG 1  to VG 4 . 
         [0060]    The positional relation and connection relation between the components shown in  FIG. 1C  are described. Four N-channel impurity regions NW 1  to NW 4  are formed in a shape long in the vertical direction of  FIG. 1C , respectively. Two P-channel impurity regions PW 1 A and PW 1 B are arranged side by side in the vertical direction of  FIG. 1C . Two P-channel impurity regions PW 2 A and PW 2 B are arranged side by side in the vertical direction of  FIG. 1C . Four P-channel impurity regions PW 1 A, PW 1 B, PW 2 A, and PW 2 B are formed between two N-channel impurity regions NW 2  and NW 3 . The N-channel impurity region NW 1 , the N-channel impurity region NW 2 , the P-channel impurity regions PW 1 A and PW 1 B, the P-channel impurity regions PW 2 A and PW 2 B, the N-channel impurity region NW 3 , and the N-channel impurity region NW 4  are arranged in this order from the left to right in  FIG. 1C . The N-channel impurity regions NW 1  to NW 4  and the P-channel impurity regions PW 1 A, PW 1 B, PW 2 A, and PW 2 B are isolated from each other by an element isolation region. 
         [0061]    The gate electrode wirings G 01  to G 12  are formed in the horizontal direction of  FIG. 1C , and are arranged over the N-channel impurity regions NW 1  to NW 4 , the P-channel impurity regions PW 1 A, PW 1 B, PW 2 A and PW 2 B, and the element isolation region. The gate electrode wiring G 01  is formed over the N-channel impurity region NW 1 . The gate electrode wiring G 02  is formed straddling over the N-channel impurity region NW 2  and the P-channel impurity regions PW 1 A and PW 2 A. The gate electrode wiring G 03  is formed straddling over the N-channel impurity regions NW 3  and NW 4 . In the example of  FIG. 1C , the gate electrode wirings G 01  to G 03  are arranged side by side on a straight line. 
         [0062]    The gate electrode wiring G 04  is formed over the N-channel impurity region NW 1 . The gate electrode wiring G 05  is formed straddling over the N-channel impurity region NW 2  and the P-channel impurity regions PW 1 A and PW 2 B. The gate electrode wiring G 06  is formed straddling over the N-channel impurity regions NW 3  and NW 4 . In the example of  FIG. 1C , the gate electrode wirings G 04  to G 06  are arranged side by side on a straight line. 
         [0063]    The gate electrode wiring G 07  is formed straddling over the N-channel impurity regions NW 1  and NW 2 . The gate electrode wiring G 08  is formed straddling over the P-channel impurity regions PW 1 A and PW 2 B and the N-channel impurity region NW 3 . The gate electrode wiring G 09  is formed over the N-channel impurity region NW 4 . In the example of  FIG. 1C , the gate electrode wirings G 07  to G 09  are arranged side by side on a straight line. 
         [0064]    The gate electrode wiring G 10  is formed straddling over the N-channel impurity regions NW 1  and NW 2 . The gate electrode wiring G 11  is formed straddling over the P-channel impurity regions PW 1 B and PW 2 B and the N-channel impurity region NW 3 . The gate electrode wiring G 12  is formed over the N-channel impurity region NW 4 . In the example of  FIG. 1C , the gate electrode wirings G 10  to G 12  are arranged side by side on a straight line. 
         [0065]    The first layer wiring M 101  is arranged straddling over the N-channel impurity regions NW 1  and NW 2 . The first layer wiring M 102  is arranged over the P-channel impurity region PW 1 A. The first layer wiring M 103  is arranged over the N-channel impurity region NW 3 . The first layer wiring M 104  is arranged over the gate electrode wiring G 03 . The first layer wiring M 105  is arranged over the N-channel impurity region NW 4 . 
         [0066]    The first layer wiring M 106  is arranged over the N-channel impurity region NW 1 . The first layer wiring M 107  is arranged over the gate electrode wiring G 07 . The first layer wiring M 108  is arranged straddling over the N-channel impurity region NW 2  and the P-channel impurity region PW 1 A. The first layer wiring M 109  is arranged straddling over the P-channel impurity region PW 2 B and the N-channel impurity region NW 3 . The first layer wiring M 110  is arranged over the gate electrode wiring G 06 . The first layer wiring M 111  is arranged over the N-channel impurity region NW 4 . 
         [0067]    The first layer wiring M 112  is arranged over the N-channel impurity region NW 1 . The first layer wiring M 113  is arranged over the gate electrode wiring G 07 . The first layer wiring M 114  is arranged over the N-channel impurity region NW 2 . The first layer wiring M 115  is arranged over the P-channel impurity region PW 2 B. The first layer wiring M 116  is arranged straddling over the N-channel impurity regions NW 3  and NW 4 . 
         [0068]    The first layer wiring-impurity region contact VN 11  couples the first layer wiring M 101  and the N-channel impurity region NW 1 . The first layer wiring-impurity region contact VN 12  couples the first layer wiring M 106  and the N-channel impurity region NW 1 . The first layer wiring-impurity region contact VN 13  couples the first layer wiring M 112  and the N-channel impurity region NW 1 . The first layer wiring-impurity region contact VN 21  couples the first layer wiring M 101  and the N-channel impurity region NW 2 . The first layer wiring-impurity region contact VN 22  couples the first layer wiring M 108  and the N-channel impurity region NW 2 . The first layer wiring-impurity region contact VN 23  couples the first layer wiring M 114  and the N-channel impurity region NW 2 . The first layer wiring-impurity region contact VN 31  couples the first layer wiring M 103  and the N-channel impurity region NW 3 . The first layer wiring-impurity region contact VN 32  couples the first layer wiring M 109  and the N-channel impurity region NW 3 . The first layer wiring-impurity region contact VN 33  couples the first layer wiring M 116  and the N-channel impurity region NW 3 . The first layer wiring-impurity region contact VN 41  couples the first layer wiring M 105  and the N-channel impurity region NW 4 . The first layer wiring-impurity region contact VN 42  couples the first layer wiring M 111  and the N-channel impurity region NW 4 . The first layer wiring-impurity region contact VN 43  couples the first layer wiring M 116  and the N-channel impurity region NW 4 . 
         [0069]    The first layer wiring-impurity region contact VP 11  couples the first layer wiring M 102  and the P-channel impurity region PW 1 A. The first layer wiring-impurity region contact VP 12  couples the first layer wiring M 108 , the P-channel impurity region PW 1 A, and the gate electrode wiring G 08 . The first layer wiring-impurity region contact VP 13  couples the P-channel impurity region PW 1 B and the gate electrode wiring G 11 . The first layer wiring-impurity region contact VP 21  couples the P-channel impurity region PW 2 A and the gate electrode wiring G 02 . The first layer wiring-impurity region contact VP 22  couples the first layer wiring M 109 , the P-channel impurity region PW 2 B, and the gate electrode wiring G 05 . The first layer wiring-impurity region contact VP 23  couples the first layer wiring M 115  and the P-channel impurity region PW 2 B. 
         [0070]    The first layer wiring-gate electrode wiring contact VG 1  couples the first layer wiring M 104  and the gate electrode wiring G 03 . The first layer wiring-gate electrode wiring contact VG 2  couples the first layer wiring M 110  and the gate electrode wiring G 06 . The first layer wiring-gate electrode wiring contact VG 3  couples the first layer wiring M 107  and the gate electrode wiring G 07 . The first layer wiring-gate electrode wiring contact VG 4  couples the first layer wiring M 113  and the gate electrode wiring G 10 . 
         [0071]    The operation of the components shown in  FIG. 1C  is described. A portion, of the gate electrode wiring G 05 , overlapping with the N-channel impurity region NW 2  behaves as the gate of the N-channel transistor N 1  shown in  FIG. 1B . A portion, of the gate electrode wiring G 05 , overlapping with the P-channel impurity region PW 1 A behaves as the gate of the P-channel transistor P 1  shown in  FIG. 1B . A portion, of the gate electrode wiring G 06 , overlapping with the N-channel impurity region NW 3  behaves as the gate of the N-channel transistor N 4  shown in  FIG. 1B . A portion, of the gate electrode wiring G 07 , overlapping with the N-channel impurity region NW 2  behaves as the gate of the N-channel transistor N 3  shown in  FIG. 1B . A portion, of the gate electrode wiring G 08 , overlapping with the P-channel impurity region PW 2 B behaves as the gate of the P-channel transistor P 2  shown in  FIG. 1B . A portion, of the gate electrode wiring G 07 , overlapping with the N-channel impurity region NW 3  behaves as the gate of the N-channel transistor N 2  shown in  FIG. 1B . The first layer wiring M 108  behaves as the storage node SN shown in  FIG. 1B . The first layer wiring M 109  behaves as the storage node /SN shown in  FIG. 1B . 
         [0072]      FIG. 1D  is a plan view extracting and showing the first wiring layer and the second wiring layer of the region shown in  FIG. 1C . Note that, border lines X 1 , X 2 , Y 1 , and Y 2  shown in  FIG. 1D  indicate the same range as in the case of  FIG. 1C . 
         [0073]    The components shown in  FIG. 1D  are described. In the second wiring layer, there are formed second layer wirings M 201  to M 205 , M 221  to M 223 , and M 231  to M 233 . The second layer wiring M 203  includes a first projecting portion and a second projecting portion. In the first wiring layer, the first layer wirings M 101  to M 116  are formed. Between the first wiring layer and the second wiring layer, first layer wiring-second layer wiring contacts V 101  to V 110  are formed. 
         [0074]    Note that, because the first layer wirings M 101  to M 116  are the same as in the case of  FIG. 1C , further detailed description is omitted. 
         [0075]    The positional relation and connection relation between the components shown in  FIG. 1D  are described. The second layer wirings M 201  to M 205  are formed in a shape long in the vertical direction of  FIG. 1D , respectively. The second layer wirings M 201  to M 205  are arranged in this order from the left to right of  FIG. 1D . The second layer wirings M 221  to M 223  are arranged side by side in the vertical direction of  FIG. 1D  and also arranged between the second layer wirings M 201  and M 202 . The second layer wirings M 231  to M 233  are arranged side by side in the vertical direction of  FIG. 1D  and also arranged between the second layer wirings M 204  and M 205 . 
         [0076]    The second layer wiring M 201  is arranged straddling over the first layer wirings M 101 , M 106 , and M 112 . The second layer wiring M 202  is arranged straddling over the first layer wirings M 101 , M 102 , M 108 , and M 114 . The first projecting portion of the second layer wiring M 203  is arranged over the first layer wiring M 102 . The second projecting portion of the second layer wiring M 203  is arranged over the first layer wiring M 115 . The second layer wiring M 204  is arranged straddling over the first layer wirings M 103 , M 109 , M 115 , and M 116 . The second layer wiring  205  is arranged straddling over the first layer wirings M 105 , M 111 , and M 116 . 
         [0077]    The second layer wiring M 221  is arranged over the first layer wiring M 101 . The second layer wiring M 222  is arranged over the first layer wiring M 107 . The second layer wiring M 223  is arranged over the first layer wiring M 113 . The second layer wiring M 231  is arranged over the first layer wiring M 104 . The second layer wiring M 232  is arranged over the first layer wiring M 110 . The second layer wiring M 233  is arranged over the first layer wiring M 116 . 
         [0078]    The first layer wiring-second layer wiring contact V 101  couples the first layer wiring M 101  and the second layer wiring M 221 . The first layer wiring-second layer wiring contact V 102  couples the first layer wiring M 102  and the first projecting portion of the second layer wiring M 203 . The first layer wiring-second layer wiring contact V 103  couples the first layer wiring M 103  and the second layer wiring M 204 . The first layer wiring-second layer wiring contact V 104  couples the first layer wiring M 105  and the second layer wiring M 205 . The first layer wiring-second layer wiring contact V 105  couples the first layer wiring M 107  and the second layer wiring M 222 . The first layer wiring-second layer wiring contact V 106  couples the first layer wiring M 110  and the second layer wiring M 223 . The first layer wiring-second layer wiring contact V 107  couples the first layer wiring M 112  and the second layer wiring M 201 . The first layer wiring-second layer wiring contact V 108  couples the first layer wiring M 114  and the second layer wiring M 202 . The first layer wiring-second layer wiring contact V 109  couples the first layer wiring M 115  and the second projecting portion of the second layer wiring M 203 . The first layer wiring-second layer wiring contact V 110  couples the first layer wiring M 116  and the second layer wiring M 233 . 
         [0079]    The operation of the components shown in  FIG. 1D  is described. The second layer wirings M 202  and M 204  behave as the bit line pair BL[n] and /BL[n] shown in  FIG. 1B , respectively. The second layer wiring M 203  behaves as the cell power supply line ARVDD shown in  FIG. 1B . 
         [0080]    Note that, because the first layer wirings M 101  to M 116  are the same as in the case of  FIG. 1C , further detailed description is omitted. 
         [0081]      FIG. 1E  is a plan view extracting and showing the second wiring layer and the third wiring layer of the region shown in  FIG. 1C . Note that, the border lines X 1 , X 2 , Y 1 , and Y 2  shown in  FIG. 1E  indicate the same range as in the case of  FIGS. 1C and 1D . 
         [0082]    The components shown in  FIG. 1E  are described. In the third wiring layer, the third layer wirings M 31  to M 33  are formed. In the second wiring layer, there are formed the second layer wirings M 201  to M 205 , M 221  to M 223 , and M 231  to M 233 . Between the second wiring layer and the third wiring layer, second layer wiring-third layer wiring contacts V 21  to V 24  are formed. 
         [0083]    Note that, because the second layer wirings M 201  to M 205 , M 221  to M 223 , and M 231  to M 233  are the same as in the case of  FIG. 1D , further detailed description is omitted. 
         [0084]    The positional relation and connection relation between the components shown in  FIG. 1E  are described. The third layer wirings M 31  to M 33  are formed in a shape long in the horizontal direction of  FIG. 1E , respectively. The third layer wirings M 31  to M 33  are arranged in this order from top to bottom of  FIG. 1E . The third layer wiring M 31  is arranged straddling over the second layer wirings M 201  to M 205 , M 221 , M 231 , and M 232 . The third layer wiring M 32  is arranged straddling over the second layer wirings M 201  to M 205 , M 222 , and M 231 . The third layer wiring M 31  is arranged straddling over the second layer wirings M 201  to M 205 , M 222 , M 223 , and M 233 . 
         [0085]    The second layer wiring-third layer wiring contact V 21  couples the second layer wiring M 221  and the third layer wiring M 31 . The second layer wiring-third layer wiring contact V 22  couples the second layer wiring M 222  and the third layer wiring M 32 . The second layer wiring-third layer wiring contact V 23  couples the second layer wiring M 232  and the third layer wiring M 32 . The second layer wiring-third layer wiring contact V 24  couples the second layer wiring M 233  and the third layer wiring M 33 . 
         [0086]    Note that, because the second layer wirings M 201  to M 205 , M 221  to M 223 , and M 231  to M 233  are the same as in the case of  FIG. 1D , further detailed description is omitted. 
         [0087]    The operation of the components shown in  FIG. 1E  is described. The third layer wirings M 31  and M 33  behave as the local ground line ARVSS shown in  FIG. 1B . The third layer wiring M 32  behaves as the word line WL[m] shown in  FIG. 1B . 
         [0088]    Note that, because the second layer wirings M 201  to M 205 , M 221  to M 223 , and M 231  to M 233  are the same as in the case of  FIG. 1D , further detailed description is omitted. 
         [0089]      FIG. 1F  is a plan view showing a wider range of the second wiring layer and third wiring layer shown in  FIG. 1E . Here, the border lines X 1 , X 2 , Y 1 , and Y 2  indicate the same range as in the case of  FIGS. 1C to 1E . That is,  FIG. 1E  shows the memory cell MC[m, n] shown in  FIG. 1B  and the range corresponding to its periphery, while  FIG. 1F  shows the memory cells MC[m, n] to MC[m+2, n+2] and the range corresponding to its periphery. 
         [0090]    More specifically, a range surrounded on all four sides by the border lines X 2 , X 3 , Y 1 , and Y 2  corresponds to the memory cell MC[m, n+1], a range surrounded on all four sides by the border lines X 1 , X 2 , Y 2 , and Y 3  corresponds to the memory cell MC[m+1, n], and a range surrounded on all four sides by the border lines X 3 , X 4 , Y 3 , and Y 4  corresponds to the memory cell MC[m+2, n+2]. 
         [0091]    The components shown in  FIG. 1F  are described. In the third wiring layer, the third layer wirings M 31  to M 37  are formed. In the second wiring layer, there are formed the second layer wirings M 201  to M 211 , M 221  to M 226 , M 231  to M 236 , M 241  to M 246 , and M 251  to M 256 . 
         [0092]    The positional relation and connection relation between the components shown in  FIG. 1F  are described. The components shown in  FIG. 1F  are periodically arranged in the vertical and horizontal directions, and its cycle corresponds to two memory cells MC. In other words, the components shown in  FIG. 1F  are arranged line-symmetrically to any of the border lines X 1  to X 4  and the border lines Y 1  and Y 2 , within the range of the memory cell array. 
         [0093]    That is, the positional relation and connection relation of the third layer wirings M 34  and M 36  are the same as in the case of the third layer wiring M 32 . The positional relation and connection relation of the third layer wirings M 35  are the same as in the case of the third layer wiring M 31 . The positional relation and connection relation of the third layer wirings M 37  are the same as in the case of the third layer wiring M 33 . 
         [0094]    Moreover, the positional relation and connection relation of the second layer wirings M 206  and M 209  are the same as in the case of the second layer wiring M 203 . The positional relation and connection relation of the second layer wirings M 207  and M 208  are the same as in the case of the second layer wirings M 201  and M 202 , respectively. The positional relation and connection relation of the second layer wirings M 210  and M 211  are the same as in the case of the second layer wirings M 204  and M 205 , respectively. The positional relation and connection relation of the second layer wirings M 224  to M 226 , M 241  to M 243 , and M 244  to M 246  are the same as in the case of the second layer wiring M 221  to M 223 , respectively. The positional relation and connection relation of the second layer wirings M 234  to M 236 , M 241  to M 243 , and M 244  to M 246  are the same as in the case of the second layer wirings M 231  to M 233 , respectively. 
         [0095]    These periodicity and symmetry are also true of the impurity regions over the semiconductor substrate omitted in  FIG. 1F . That is, the P-channel impurity region is formed between the border lines XW 1  and XW 2 , between the border lines XW 3  and XW 4 , between the border lines XW 5  and XW 6 , and between the border lines XW 7  and XW 8 . Moreover, the N-channel impurity region is formed between the border lines XW 2  and XW 3 , between the border lines XW 4  and XW 5 , and between the border lines XW 6  and XW 7 . 
         [0096]    The operation of the components shown in  FIG. 1F  is described. The above-described periodicity and symmetry are also true here. That is, the second layer wiring M 201  behaves as the bit line /BL[n−1]. The second layer wiring M 202  behaves as the bit line BL[n]. The second layer wiring M 203  behaves as the cell power supply line ARVDD. The second layer wiring M 204  behaves as the bit line /BL[n]. The second layer wiring M 205  behaves as the bit line BL[n+1]. The second layer wiring M 206  behaves as the cell power supply line ARVDD. The second layer wiring M 207  behaves as the bit line /BL[n+1]. The second layer wiring M 208  behaves as the bit line BL[n+2]. The second layer wiring M 209  behaves as the cell power supply line ARVDD. The second layer wiring M 210  behaves as the bit line /BL[n+2]. The second layer wiring M 211  behaves as the bit line BL[n+3]. 
         [0097]    Moreover, the third layer wiring M 31  behaves as the local ground line ARVSS. The third layer wiring M 32  behaves as the word line WL[n]. The third layer wiring M 33  behaves as the local ground line ARVSS. The third layer wiring M 34  behaves as the word line WL[n+1]. The third layer wiring M 35  behaves as the local ground line ARVSS. The third layer wiring M 36  behaves as the word line WL[n+2]. The third layer wiring M 37  behaves as the local ground line ARVSS. 
         [0098]      FIG. 1G  is a plan view showing a positional relation between various wirings formed in the third wiring layer and the fourth wiring layer of an SRAM according to a conventional art. These wirings shown in  FIG. 1G  include external power supply voltage lines VDD 41  to VDD 45  and VDD 51  to VDD 54 , external ground voltage lines VSS 41  to VDD 45  and VSS 51  to VSS 54 , local ground lines ARVSS 41  to ARVSS 44 , and the vias V coupling these wirings. Note that, the number of these wirings and the number of these vias V shown in  FIG. 1G  are just one example, or only some of them are shown, and do not limit the semiconductor device of the present invention. 
         [0099]    Among various wirings shown in  FIG. 1G , the external power supply voltage lines VDD 41  to VDD 45 , the external ground voltage lines VSS 41  to VDD 45 , and the local ground lines ARVSS 41  to ARVSS 44  are arranged in parallel to the horizontal direction in  FIG. 1G , in the third wiring layer. Among various wirings shown in  FIG. 1G , the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  are arranged in parallel to the vertical direction in  FIG. 1G , in the fourth wiring layer. Among various wirings shown in  FIG. 1G , the vias V are formed straddling at least between the third wiring layer and the fourth wiring layer, but may further straddle the other wiring layer. 
         [0100]    Note that, the external power supply voltage lines VDD 41  to VDD 44  and the external ground voltage lines VSS 41  to VSS 44  shown in  FIG. 1G  are formed straddling the memory mat circuit MM and the output circuit Out shown in  FIG. 1A . The external power supply voltage line VDD 45  and the external ground voltage line VSS 45  shown in  FIG. 1G  are arranged straddling the word driver circuit WdD and the control circuit Cnt shown in  FIG. 1A . The external power supply voltage lines VDD 51  and VDD 52  and the external ground voltage lines VSS 51  and VSS 52  shown in  FIG. 1G  are arranged straddling the output circuit Out and the control circuit Cnt shown in  FIG. 1A . The external power supply voltage lines VDD 53  and VDD 54  and the external ground voltage lines VSS 53  and VSS 54  shown in  FIG. 1G  are arranged straddling the memory mat circuit MM and the word driver circuit WdD shown in  FIG. 1A . The local ground lines ARVSS 41  to ARVSS 44  shown in  FIG. 1G  are arranged in the memory mat circuit MM, and also arranged between the external power supply voltage lines VDD 41  to VDD 45  and the external ground voltage lines VSS 41  to VSS 45  having the same number. That is, for example, the local ground line ARVSS 42  is arranged between the external power supply voltage line VDD 42  and the external ground voltage line VSS 42 . 
         [0101]    The via V shown in  FIG. 1G  is arranged at an intersection between the external power supply voltage lines VDD 41  to VDD 45  and the external power supply voltage lines VDD 51  to VDD 54  and at an intersection between the external ground voltage lines VSS 41  to VSS 45  and the external ground voltage lines VSS 51  to VSS 54 . In the example shown in  FIG. 1G , all the external power supply voltage lines VDD 41  to VDD 45  and VDD 51  to VDD 54  and the external ground voltage lines VSS 41  to VSS 45  and VSS 51  to VSS 54  have the same width. Accordingly, the shape at the each intersection is square or rectangular near thereto. Here, in the example shown in  FIG. 1G , the shape of the via V is laterally long rectangular, and two rectangular vias V are arranged at the each intersection. 
         [0102]    The connection relation between various wirings of the SRAM shown in  FIG. 1G  is described. The external power supply voltage lines VDD 41  to VDD 45  are coupled to the external power supply voltage lines VDD 51  to VDD 54  via the vias V, respectively. The external ground voltage lines VSS 41  to VSS 45  are coupled to the external ground voltage lines VSS 51  to VSS 54  via the vias V, respectively. 
         [0103]    A wiring portion la enclosed by a dotted line and shown in  FIG. 1G  is focused on. The wiring portion la includes the external power supply voltage line VDD 42 , the local ground line ARVSS 42 , the external ground voltage line VSS 42 , some of the external power supply voltage lines VDD 51  to VDD 54 , some of the external ground voltage lines VSS 51  to VSS 54 , and the vias V coupling these wirings. 
         [0104]    In the wiring portion la shown in  FIG. 1G , of a region between the external power supply voltage line VDD 42  and the external ground voltage line VSS 42 , in a region on the extension of the local ground line ARVSS 42 , i.e., in a region included in the output circuit Out, a free space VS 2  remains in the fourth wiring layer. This free space is present also on the extension in each of the other local ground lines ARVSS 41 , ARVSS 43 , and ARVSS 44 , as with the case of the wiring portion la. Hereinafter, as examples making efficient use of such free space, the wiring portion la will be described, but these examples shall be applicable to all the free spaces. 
         [0105]      FIG. 1H  is a block circuit diagram schematically showing the configuration of wirings related to a local ground line of a memory cell array in a typical SRAM. The components shown in  FIG. 1H  are described. The block circuit diagram shown in  FIG. 1H  includes the memory cell array MCA, the output circuit Out, and the first and second ground line switch circuits ARGSw 1  and ARGSw 2 . Here, each of the first and second ground line switch circuits ARGSw 1  and ARGSw 2  includes a standby signal line STB, the external ground voltage line VSS, the local ground line ARVSS, and a plurality of N-channel transistors NS 1  and NS 2 . The memory cell array MCA includes a plurality of word lines WL formed in the third wiring layer, a plurality of local ground lines ARVSS formed in the third wiring layer, and a plurality of local ground lines ARVSS formed in the fourth wiring layer. 
         [0106]    The positional relation and connection relation between the components shown in  FIG. 1H  are described. The first ground line switch circuit ARGSw 1 , the memory cell array MCA, the second ground line switch circuit ARGSw 2 , and the output circuit Out are arranged in this order from the right to left of  FIG. 1H . In particular, the memory cell array MCA is arranged between the first and second ground line switch circuits ARGSw 1  and ARGSw 2 . 
         [0107]    In each of the N-channel transistors NS 1  included in the first and second ground line switch circuits ARGSw 1  and ARGSw 2 , the gate is coupled to the standby signal line STB. Similarly, one of the source and the drain is coupled to the external ground voltage line VSS, and the other one is coupled to the local ground line ARVSS. 
         [0108]    In each of the N-channel transistors NS 2  included in the first and the second ground line switch circuits ARGSw 1  and ARGSw 2 , one of the source and the drain is coupled to the external ground voltage line VSS, and the other one and the gate are coupled in common to the local ground line ARVSS. 
         [0109]    The local ground lines ARVSS formed in the fourth wiring layer of the memory cell array MCA are arranged in parallel. A spacing between these local ground lines ARVSS of the fourth wiring layer is designated as D. The spacing D corresponds to N memory cells MC. Here, N is an integer of two or more, and is 16 in this example. In other words, one local ground line ARVSS is arranged for every 16 memory cells MC. 
         [0110]    The local ground lines ARVSS formed in the third wiring layer of the memory cell array MCA and the word lines WL also formed in the third wiring layer are arranged in parallel and alternately, and are also perpendicular to the local ground lines ARVSS formed also in the fourth wiring layer. 
         [0111]    For the local ground lines ARVSS formed in the fourth wiring layer of the memory cell array MCA, one endis respectively coupled to the local ground line ARVSS included in the first ground line switch circuit ARGSw 1 , and the other ends are respectively coupled to the local ground line ARVSS included in the second ground line switch circuit ARGSw 2 . Moreover, the local ground lines ARVSS formed in the fourth wiring layer of the memory cell array MCA are respectively coupled to the local ground lines ARVSS, which are also formed in the third wiring layer, via a plurality of the non-illustrated third wiring layer-fourth wiring layer contacts. 
         [0112]    The operation of the components shown in  FIG. 1H  is described. In the first and second ground line switch circuits ARGSw 1  and ARGSw 2 , a common standby signal is supplied to the gates of the N-channel transistors NS 1 . When stand-by instruction is given to the SRAM, the standby signal is set to a high level, and thereby the N-channel transistor NS 1  is turned off. At this time, by means of a diode-connected N-channel transistor NS 2 , the voltage of the local ground line ARVSS is kept higher than the external ground voltage Vss by a threshold voltage Vth. Note that, here the external ground voltage Vss is equal to 0 V. It is assumed that, as a result, a voltage to an extent that the retained data will not be erased is supplied to the memory cell array. 
         [0113]    To the contrary, the N-channel transistor NS 1  is turned on by setting the standby signal to a low level, and the voltage of the local ground line ARVSS becomes approximately the same as the external ground voltage Vss, i.e., 0 V. Note that, it is assumed that a ground voltage is supplied from the outside of the SRAM to the external ground voltage line VSS. Moreover, it is assumed that the standby signal is generated inside the SRAM circuit based on an arbitrary mode signal supplied from the outside of the SRAM. 
         [0114]      FIG. 1I  is a block circuit diagram schematically showing the configuration of wirings related to the external power supply voltage line VDD and the external ground voltage line VSS of the memory cell array in a typical SRAM. The components shown in  FIG. 1I  are described. The block circuit diagram shown in  FIG. 1I  includes the memory cell array MCA, the output circuit Out, the first and second ground line switch circuits ARGSw 1  and ARGSw 2 , a plurality of external power supply voltage lines VDD, a plurality of external ground voltage lines VSS, a plurality of local ground lines ARVSS, and a plurality of signal lines SGN. The memory cell array MCA includes a plurality of memory cell array subgroups MCASG, a plurality of well power-feeding voltage lines VDDW, and a plurality of well grounding voltage lines VSSW. 
         [0115]    The positional relation and connection relation between the components shown in  FIG. 1I  are described. The first ground line switch circuit ARGSw 1 , the memory cell array MCA, the second ground line switch circuit ARGSw 2 , and the output circuit Out are arranged in this order from right to left of  FIG. 1I . 
         [0116]    In the memory cell array MCA, the well power-feeding voltage lines VDDW and the well grounding voltage lines VSSW are formed in the vertical direction of  FIG. 1I , respectively, and each one of the well power-feeding voltage lines VDDW and each one of the well grounding voltage lines VSSW are paired, and are arranged in parallel and side by side in the horizontal direction of  FIG. 1I . Between the pairs, one memory cell array subgroup MCASG is arranged. In other words, one well power-feeding voltage line VDDW, one well grounding voltage line VSSW, and one memory cell array subgroup MCASG are periodically arranged in the horizontal direction of  FIG. 1I . 
         [0117]    Note that, in one memory cell array subgroup MCASG, M memory cells MC are arranged side by side in the horizontal direction of  FIG. 1I . Here, M is an integer of two or more, and is  64  in this example. In this case, in other words, for every  64  memory cells MC, the well power-feeding voltage line VDDW and the well grounding voltage line VSSW are arranged. 
         [0118]    The external power supply voltage lines VDD, the external ground voltage lines VSS, the local ground lines ARVSS, and the signal lines SGN are formed in the horizontal direction of  FIG. 1I , i.e., in the direction perpendicular to the well power-feeding voltage line VDDW and the well grounding voltage line VSSW, and are also arranged in parallel in the vertical direction of  FIG. 1I . 
         [0119]    The local ground line ARVSS extends from the first ground line switch circuit ARGSw 1  to the second ground line switch circuit ARGSw 2 , straddling the memory cell array MCA. The external power supply voltage line VDD and the external ground voltage line VSS extend from the first ground line switch circuit ARGSw 1  to the output circuit Out, straddling the memory cell array MCA and the second ground line switch circuit ARGSw 2 . The signal line SGN extends straddling the first ground line switch circuit ARGSw 1 , the memory cell array MCA, the second ground line switch circuit ARGSw 2 , and the output circuit Out. 
         [0120]    The external power supply voltage lines VDD are respectively coupled to the well power-feeding voltage lines VDDW via a plurality of non-illustrated contacts. Similarly, the external ground voltage lines VSS are respectively coupled to the well grounding voltage lines VSSW via a plurality of non-illustrated contacts. 
         [0121]    The operation of the components shown in  FIG. 1I  is described. The well power-feeding voltage line VDDW is formed in the third wiring layer, and supplies the external power supply voltage Vdd to an N-channel impurity region over the semiconductor substrate via an underlying wiring, a contact, and the like. Similarly, the well grounding voltage line VSSW is formed in the third wiring layer, and supplies the external ground voltage Vss to a P-channel impurity region over the semiconductor substrate via an underlying wiring, a contact, and the like. 
         [0122]      FIG. 1J  is a block circuit diagram schematically showing the configuration of an impurity region in a typical SRAM and wirings related to the power feeding to the impurity region. The components shown in  FIG. 1J  are described. The block circuit diagram shown in  FIG. 1J  includes the first ground line switch circuit ARGSw 1 , a plurality of memory cell array subgroups MCASG, a plurality of well power-feeding voltage lines VDDW, a plurality of well grounding voltage lines VSSW, a plurality of P-channel impurity regions PW, a plurality of N-channel impurity regions NW, the second ground line switch circuit ARGSw 2 , and the output circuit Out. 
         [0123]    The positional relation and connection relation between the components shown in  FIG. 1J  are described. First, because the positional relation between the first ground line switch circuit ARGSw 1 , the memory cell array subgroups MCASG, the well power-feeding voltage lines VDDW, the well grounding voltage lines VSSW, the second ground line switch circuit ARGSw 2 , and the output circuit Out is the same as in the case of  FIG. 1I , further detailed description is omitted. 
         [0124]    Next, the P-channel impurity regions PW and the N-channel impurity regions NW are formed in a region corresponding to the memory cell array MCA over the semiconductor substrate, i.e., the well power-feeding voltage lines VDDW and the well grounding voltage lines VSSW are arranged overlapping with each other over the semiconductor substrate. 
         [0125]    The P-channel impurity regions PW and the N-channel impurity regions NW are formed in a shape long in the horizontal direction of  FIG. 1J , respectively, and are also alternatively arranged in the vertical direction of  FIG. 1J . Accordingly, the respective P-channel impurity regions PW intersect with all the well grounding voltage lines VSSW. Similarly, the respective N-channel impurity regions NW intersect orthogonally with all the well power-feeding voltage lines VDDW. 
         [0126]    The P-channel impurity regions PW and the well grounding voltage lines VSSW are coupled to each other via non-illustrated wirings, contacts, and the like. Similarly, the N-channel impurity regions NW and the well power-feeding voltage lines VDDW are coupled to each other via non-illustrated wiring, contacts, and the like. In  FIG. 1J , the connection relation between these components is schematically shown as a connection point. 
         [0127]      FIG. 2A  is a plan view showing the configuration of a wiring portion  2  according to a first embodiment. The components of the wiring portion  2  shown in  FIG. 2A  are described. The wiring portion  2  shown in  FIG. 2A  includes the external power supply voltage lines VDD 2  and VDD 51  to VDD 54 , the external ground voltage lines VSS 2  and VSS 51  to VSS 54 , the local ground line ARVSS 2 , and the vias V. 
         [0128]    Here, the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 2A  are assumed to be identical to the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 1G , respectively. Moreover, the external power supply voltage line VDD 2 , the external ground voltage line VSS 2 , and the local ground line ARVSS 2  shown in  FIG. 2A  are assumed to correspond to the external power supply voltage line VDD 42 , the external ground voltage line VSS 42 , and the local ground line ARVSS 42  shown in  FIG. 1G , respectively. In this manner, the wiring portion  2  shown in  FIG. 2A  is assumed to be used in substitution for the wiring portion la in the SRAM shown in  FIG. 1G . 
         [0129]      FIG. 2B  is a plan view showing the configuration of the external power supply voltage line VDD 2  and the external ground voltage line VSS 2  according to the first embodiment. The external power supply voltage line VDD 2  shown in  FIGS. 2A and 2B  is equal to the external power supply voltage line VDD 42  shown in  FIG. 1G  having two projecting portions  2 D 1  and  2 D 2  integrally added thereto. 
         [0130]    Here, the first projecting portion  2 D 1  is arranged at an intersecting portion between the external power supply voltage line VDD 2  and the external power supply voltage line VDD 51  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external power supply voltage line VDD 2  and the external power supply voltage line VDD 51 . These vias V may be separately treated as a via group coupled to the first projecting portion  2 D 1  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0131]    Similarly, the second projecting portion  2 D 2  is arranged at an intersecting portion between the external power supply voltage line VDD 2  and the external power supply voltage line VDD 52  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external power supply voltage line VDD 2  and the external power supply voltage line VDD 52 . These vias V may be separately treated as a via group coupled to the second projecting portion  2 D 2  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0132]    Moreover, the external ground voltage line VSS 2  shown in  FIGS. 2A and 2B  is equal to the external ground voltage line VSS 42  shown in  FIG. 1G  having two projecting portions  2 S 1  and  2 S 2  integrally added thereto. 
         [0133]    Here, the first projecting portion  2 S 1  is arranged at an intersecting portion between the external ground voltage line VSS 2  and the external ground voltage line VSS 51  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in FIG.  1 G are formed in accordance with the increased area to couple the external ground voltage line VSS 2  and the external ground voltage line VSS 51 . These vias V may be separately treated as a via group coupled to the first projecting portion  2 S 1  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0134]    Similarly, the second projecting portion  2 S 2  is arranged at an intersecting portion between the external ground voltage line VSS 2  and the external ground voltage line VSS 52  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external ground voltage line VSS 2  and the external ground voltage line VSS 52 . These vias V may be separately treated as a via group coupled to the second projecting portion  2 S 2  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0135]    In the wiring portion  2  according to the first embodiment, from left to right in  FIGS. 2A and 2B , the first projecting portions  2 D 1  and  2 S 1  and the second projecting portions  2 D 2  and  2 S 2  in each of the external power supply voltage line VDD 2  and the external ground voltage line VSS 2  are alternately arranged in this order. This is because in order to form as many vias V as possible in each projecting portion, a shape as long as possible has been selected in the vertical direction of  FIGS. 2A and 2B  in a region between the external power supply voltage line VDD 2  and the external ground voltage line VSS 2 . 
         [0136]    The use of the wiring portion  2  according to the first embodiment shown in  FIGS. 2A and 2B  provides the following effect. That is, the power supply circuit of the semiconductor device is reinforced by increasing a total number of vias V transmitting the external power supply voltage Vdd and the external ground voltage Vss between the wiring layers. The embodiment is effective especially when a drop of a power supply voltage and/or power EM is restrained by a total number of vias V. 
       Second Embodiment 
       [0137]      FIG. 3A  is a plan view showing the configuration of a wiring portion  3  according to a second embodiment. The components of the wiring portion  3  shown in  FIG. 3A  are described. The wiring portion  3  shown in  FIG. 3A  includes the external power supply voltage lines VDD 3  and VDD 51  to VDD 54 , the external ground voltage lines VSS 3  and VSS 51  to VSS 54 , the local ground line ARVSS 3 , and the vias V. 
         [0138]    Here, the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 3A  are assumed to be identical to the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 1G , respectively. Moreover, the external power supply voltage line VDD 3 , the external ground voltage line VSS 3 , and the local ground line ARVSS 3  shown in  FIG. 3A  are assumed to correspond to the external power supply voltage line VDD 42 , the external ground voltage line VSS 42 , and the local ground line ARVSS 42  shown in  FIG. 1G , respectively. In this manner, the wiring portion  3  shown in  FIG. 3A  is assumed to be used in substitution for the wiring portion la in the SRAM shown in  FIG. 1G . 
         [0139]      FIG. 3B  is a plan view showing the configuration of the external power supply voltage line VDD 3  and the external ground voltage line VSS 3  according to the second embodiment. The external power supply voltage line VDD 3  shown in  FIGS. 3A and 3B  is equal to the external power supply voltage line VDD 42  shown in  FIG. 1G  having a projecting portion  3 D integrally added thereto. 
         [0140]    Due to the addition of the projecting portion  3 D, the width of a portion, of the external power supply voltage line VDD 3 , included in the output circuit Out is wider than in the case of the external power supply voltage line VDD 42  shown in  FIG. 1G . In other words, due to the addition of the projecting portion  3 D, the width of a portion, of the external power supply voltage line VDD 3 , intersecting with the external power supply voltage lines VDD 51  and VDD 52  is wider than in the case of the external power supply voltage line VDD 42  shown in  FIG. 1G . As a result, the area of the intersecting portion between the external power supply voltage line VDD 3  and the external power supply voltage lines VDD 51  and VDD 52  increases. In these intersecting portions, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external power supply voltage line VDD 3  to the external power supply voltage lines VDD 51  and VDD 52 , respectively. These vias V may be separately treated as a via group coupled to the projecting portion  3 D and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0141]    Similarly, the external ground voltage line VSS 3  shown in  FIGS. 3A and 3B  is equal to the external ground voltage line VSS 42  shown in  FIG. 1G  having a projecting portion  3 S integrally added thereto. 
         [0142]    Due to the addition of the projecting portion  3 S, a portion, of the external ground voltage line VSS 3 , included in the output circuit Out is wider than in the case of the external ground voltage line VSS 42  shown in  FIG. 1G . In other words, due to the addition of the projecting portion  3 S, the width of a portion, of the external ground voltage line VSS 3 , intersecting with the external ground voltage lines VSS 51  and VSS 52  is wider than in the case of the external ground voltage line VSS 42  shown in  FIG. 1G . As a result, the area of the intersecting portion between the external ground voltage line VSS 3  and the external ground voltage lines VSS 51  and VSS 52  increases. In these intersecting portions, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external ground voltage line VSS 3  to the external ground voltage lines VSS 51  and VSS 52 , respectively. These vias V may be separately treated as a via group coupled to the projecting portion  3 S and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0143]    In the projecting portions  3 D and  3 S shown in  FIGS. 3A and 3B , a collar portion, in which the via V is not formed, is provided also in other than the intersecting portions between the external power supply voltage lines VDD 51  and VDD 52  and between the external ground voltage lines VSS 51  and VSS 52 . By providing this collar portion, the width of the portion included in the output circuit Out becomes uniform in each of the external power supply voltage line VDD 3  and the external ground voltage line VSS 3 . Note that, the external power supply voltage line VDD 3  and the external ground voltage line VSS 3  may be formed so that the wiring widths of the both become the same as shown in  FIGS. 3A  and  3 B, in view of the symmetry as a power supply circuit, but this feature is just an example and does not limit the present embodiment. 
         [0144]    The use of the wiring portion  3  according to the second embodiment shown in  FIGS. 3A and 3B  provides the following effects. That is, the power supply circuit of the semiconductor device is reinforced by increasing a total number of vias V transmitting the external power supply voltage Vdd and the external ground voltage Vss between the wiring layers and increasing the width of the power supply wiring. The embodiment is effective especially when a drop of a power supply voltage and/or power EM is restrained by a total number of vias V and the width of the power supply wiring. 
       Third Embodiment 
       [0145]      FIG. 4A  is a plan view showing the configuration of a wiring portion  4  according to a third embodiment. The components of the wiring portion  4  shown in  FIG. 4A  are described. The wiring portion  4  shown in  FIG. 4A  includes the external power supply voltage lines VDD 4  and VDD 51  to VDD 54 , the external ground voltage lines VSS 4  and VSS 51  to VSS 54 , the local ground line ARVSS 4 , and the vias V. 
         [0146]    Here, the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 4A  are assumed to be identical to the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 1G , respectively. However, in  FIG. 4A , the arrangement is exchanged between the external power supply voltage line VDD 51  and the external ground voltage line VSS 51 . 
         [0147]    Moreover, the external power supply voltage line VDD 4 , the external ground voltage line VSS 4 , and the local ground line ARVSS 4  shown in  FIG. 4A  are assumed to correspond to the external power supply voltage line VDD 42 , the external ground voltage line VSS 42 , and the local ground line ARVSS 42  shown in  FIG. 1G , respectively. In this manner, the wiring portion  4  shown in  FIG. 4A  is assumed to be used in substitution for the wiring portion la in the SRAM shown in  FIG. 1G . 
         [0148]      FIG. 4B  is a plan view showing the configuration of the external power supply voltage line VDD 4  and the external ground voltage line VSS 4  according to the third embodiment. The external power supply voltage line VDD 4  shown in  FIGS. 4A and 4B  is equal to the external power supply voltage line VDD 42  shown in  FIG. 1G  having a projecting portion  4 D integrally added thereto. 
         [0149]    Due to the addition of the projecting portion  4 D, the width of a portion, of the external power supply voltage line VDD 4 , included in the output circuit Out is wider than in the case of the external power supply voltage line VDD 42  shown in  FIG. 1G . In other words, due to the addition of the projecting portion  4 D, the width of a portion, of the external power supply voltage line VDD 4 , intersecting with the external power supply voltage lines VDD 51  and VDD 52  is wider than in the case of the external power supply voltage line VDD 42  shown in  FIG. 1G . As a result, the area of the intersecting portion between the external power supply voltage line VDD 4  and the external power supply voltage lines VDD 51  and VDD 52  increases. In these intersecting portions, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external power supply voltage line VDD 4  to the external power supply voltage lines VDD 51  and VDD 52 , respectively. These vias V may be separately treated as a via group coupled to the projecting portion  4 D and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0150]    Moreover, the external ground voltage line VSS 4  shown in  FIGS. 4A and 4B  is equal to the external ground voltage line VSS 42  shown in  FIG. 1G  having two projecting portions  4 S 1  and  4 S 2  integrally added thereto. 
         [0151]    Here, the first projecting portion  4 S 1  is arranged at an intersecting portion between the external ground voltage line VSS 4  and the external ground voltage line VSS 51  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external ground voltage line VSS 4  and the external ground voltage line VSS 51 . These vias V may be separately treated as a via group coupled to the first projecting portion  4 S 1  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0152]    Similarly, the second projecting portion  4 S 2  is arranged at an intersecting portion between the external ground voltage line VSS 4  and the external ground voltage line VSS 52  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external ground voltage line VSS 4  and the external ground voltage line VSS 52 . These vias V may be separately treated as a via group coupled to the second projecting portion  4 S 2  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0153]    In the wiring portion  4  according to the third embodiment, from left to right in  FIGS. 4A and 4B , the first projecting portion  4 S 1  of the external ground voltage line VSS 4 , the projecting portion  4 D of the external power supply voltage line VDD 4 , and the second projecting portion  4 S 2  of the external ground voltage line VSS 4  are alternately arranged in this order. This is because as with the first embodiment, the shape of each projecting portion is set as long as possible in the vertical direction in  FIGS. 4A and 4B , and also as with the second embodiment, the width of a portion, of the external power supply voltage line VDD 4 , included in the output circuit Out has been increased. Note that, in the wiring portion  4  according to the present embodiment, the shape of the external power supply voltage line VDD 4  and the shape of the external ground voltage line VSS 4  can be easily exchanged. In this case, the positional relation between the external power supply voltage lines VDD 51  and VDD 52  and the external ground voltage lines VSS 51  and VSS 52  are changed as required. 
         [0154]    The use of the wiring portion  4  according to the third embodiment shown in  FIGS. 4A and 4B  provides the following effect. That is, the power supply circuit of the semiconductor device is reinforced by increasing a total number of vias V transmitting the external power supply voltage Vdd and the external ground voltage Vss between the wiring layers and increasing the width of apart of the power supply wiring. The embodiment is effective especially when a drop of a power supply voltage and/or power EM is restrained by a total number of vias V and the width of either one of the external power supply voltage line and the external ground voltage line. 
       Fourth Embodiment 
       [0155]      FIG. 5A  is a plan view showing the configuration of a wiring portion  5  according to a fourth embodiment. The components of the wiring portion  5  shown in  FIG. 5A  are described. The wiring portion  5  shown in  FIG. 5A  includes the external power supply voltage lines VDD 5  and VDD 51  to VDD 54 , the external ground voltage lines VSS 5  and VSS 51  to VSS 54 , the local ground line ARVSS 5 , and the vias V. 
         [0156]    Here, the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 5A  are assumed to be identical to the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 1G , respectively. Moreover, the external power supply voltage line VDD 5 , the external ground voltage line VSS 5 , and the local ground line ARVSS 5  shown in  FIG. 5A  are assumed to correspond to the external power supply voltage line VDD 42 , the external ground voltage line VSS 42 , and the local ground line ARVSS 42  shown in  FIG. 1G , respectively. In this manner, the wiring portion  5  shown in  FIG. 5A  is assumed to be used in substitution for the wiring portion  1   a  in the SRAM shown in  FIG. 1G . 
         [0157]      FIG. 5B  is a plan view showing the configuration of the external power supply voltage line VDD 5  and the external ground voltage line VSS 5  according to the fourth embodiment. The external power supply voltage line VDD 5  shown in  FIGS. 5A and 5B  is equal to the external power supply voltage line VDD 42  shown in  FIG. 1G  having two projecting portions  5 D 1  and  5 D 2  integrally added thereto. 
         [0158]    Here, the first projecting portion  5 D 1  is arranged at an intersecting portion between the external power supply voltage line VDD 5  and the external power supply voltage line VDD 51  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external power supply voltage line VDD 5  and the external power supply voltage line VDD 51 . These vias V may be separately treated as a via group coupled to the first projecting portion  5 D 1  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0159]    Similarly, the second projecting portion  5 D 2  is arranged at an intersecting portion between the external power supply voltage line VDD 5  and the external power supply voltage line VDD 52  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external power supply voltage line VDD 5  and the external power supply voltage line VDD 52 . These vias V may be separately treated as a via group coupled to the second projecting portion  5 D 2  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0160]    Note that, the second projecting portion  5 D 2  also includes a collar portion integrally formed into the external power supply voltage line VDD 5 , in addition to the above-described intersecting portion. This collar portion is formed in a region sandwiched between the external ground voltage line VSS 51  and the external power supply voltage line VDD 52  and also sandwiched between the external power supply voltage line VDD 5  and the external ground voltage line VSS 5 . 
         [0161]    Moreover, the external ground voltage line VSS 5  shown in  FIGS. 5A and 5B  is equal to the external ground voltage line VSS 42  shown in  FIG. 1G  having two projecting portions  5 S 1  and  5 S 2  integrally added thereto. 
         [0162]    Here, the first projecting portion  5 S 1  is arranged at an intersecting portion between the external ground voltage line VSS 5  and the external ground voltage line VSS 51  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external ground voltage line VSS 5  and the external ground voltage line VSS 51 . These vias V may be separately treated as a via group coupled to the first projecting portion  5 S 1  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0163]    Similarly, the second projecting portion  5 S 2  is arranged at an intersecting portion between the external ground voltage line VSS 5  and the external ground voltage line VSS 52  so that the area of this intersecting portion increases. In this intersecting portion, more vias V than those shown in  FIG. 1G  are formed in accordance with the increased area to couple the external ground voltage line VSS 2  and the external ground voltage line VSS 52 . These vias V may be separately treated as a via group coupled to the second projecting portion  5 S 2  and the other via group coupled to the other intersecting portions, for convenience, but the via V straddling both regions may be further formed. 
         [0164]    Note that, the first projecting portion  5 S 1  also includes a collar portion integrally formed into the external ground voltage line VSS 5 , in addition to the above-described intersecting portion. This collar portion is formed in a region sandwiched between the external ground voltage line VSS 51  and the external power supply voltage line VDD 52  and also sandwiched between the external power supply voltage line VDD 5  and the external ground voltage line VSS 5 . 
         [0165]    In the wiring portion  2  according to the first embodiment, from left to right in  FIGS. 2A and 2B , the first projecting portions  2 D 1  and  2 S 1  and the second projecting portions  2 D 2  and  2 S 2  in each of the external power supply voltage line VDD 2  and the external ground voltage line VSS 2  are alternately arranged in this order. This is because in order to form as many vias V as possible in each projecting portion and also secure a wiring width as wide as possible even if partially, a shape as long as possible has been selected in the vertical direction in  FIGS. 2A and 2B  in a region between the external power supply voltage line VDD 2  and the external ground voltage line VSS 2 . 
         [0166]    The use of the wiring portion  2  according to the first embodiment shown in  FIGS. 2A and 2B  provides the following effect. That is, the power supply circuit of the semiconductor device is reinforced by increasing a total number of vias V transmitting the external power supply voltage Vdd and the external ground voltage Vss between the wiring layers and increasing the width of the power supply wiring. The embodiment is effective especially when a drop of a power supply voltage and/or power EM is restrained by a total number of vias V and the width of the power supply wiring and also when an influence by a total number of vias V is larger than an influence by the wiring width. 
       Fifth Embodiment 
       [0167]      FIG. 6A  is a plan view showing the configuration of a wiring portion  6  according to a fifth embodiment. The components of the wiring portion  6  shown in  FIG. 6A  are described. The wiring portion  6  shown in  FIG. 6A  includes the external power supply voltage lines VDD 6   a , VDD 6   b  and VDD 51  to VDD 54 , the external ground voltage lines VSS 6   a , VSS 6   b  and VSS 51  to VSS 54 , the local ground lines ARVSS 6   a  and ARVSS 6   b , and the vias V. 
         [0168]    Here, the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 6A  are assumed to be identical to the external power supply voltage lines VDD 51  to VDD 54  and the external ground voltage lines VSS 51  to VSS 54  shown in  FIG. 1G , respectively. Moreover, the external power supply voltage lines VDD 6   a  and VDD 6   b , the external ground voltage lines VSS 6   a  and VSS 6   b , and the local ground lines ARVSS 6   a  and ARVSS 6   b  shown in  FIG. 6A  are assumed to correspond to the external power supply voltage line VDD 42 , the external ground voltage line VSS 42 , the external power supply voltage line VDD 43 , the external ground voltage line VSS 43 , the local ground line ARVSS 42 , and the local ground line ARVSS 43  shown in  FIG. 1G , respectively. In this manner, the wiring portion  6  shown in  FIG. 6A  is assumed to be used in substitution for the wiring portion  1   b  in the SRAM shown in  FIG. 1G . Here, note that between the external ground voltage line VSS 42  as well as the external power supply voltage line VDD 43  shown in  FIG. 1G  and the external ground voltage line VSS 6   b  as well as the external ground voltage line VSS 6   a  shown in  FIG. 6A , the roles thereof, i.e., the voltages to be applied, are exchanged. 
         [0169]      FIG. 6B  is a plan view showing the configuration of the external power supply voltage lines VDD 6   a  and VDD 6   b  according to the fifth embodiment.  FIG. 6C  is a plan view showing the configuration of the external ground voltage lines VSS 6   a  and VSS 6   b  according to the fifth embodiment. The external power supply voltage lines VDD 6   a  and VDD 6   b  shown in  FIGS. 6A and 6B  are equal to the external power supply voltage line VDD 42  and the external ground voltage line VS 542  shown in  FIG. 1G  having a projecting portion  6 D integrally added thereto. As a result, the external power supply voltage lines VDD 6   a  and VDD 6   b  and the projecting portion  6 D are integrated as a wiring, so hereinafter this is referred to as an external power supply voltage line VDD 6 . 
         [0170]    The projecting portion  6 D is formed in a region, between the external power supply voltage lines VDD 6   a  and VDD 6   b , included in the output circuit Out. Accordingly, the projecting portion  6 D includes a first intersecting portion intersecting with the external power supply voltage lines VDD 51  and VDD 52 , a second intersecting portion intersecting with the external ground voltage lines VSS 51  and VSS 52 , and the other portion. 
         [0171]    In this first intersecting portion, the via V is formed to couple the external power supply voltage line VDD 6  to the external power supply voltage lines VDD 51  and VDD 52 . Here, these vias may be separately treated as a via group provided in an intersecting portion between the external power supply voltage line VDD 6   a  and the external power supply voltage line VDD 51 , a via group provided in an intersecting portion between the external power supply voltage line VDD 6   b  and the external power supply voltage line VDD 51 , and a via group provided in an intersecting portion between the projecting portion  6 D and the external power supply voltage line VDD 51 , but the via V straddling a plurality of intersecting portions may be further formed. Similarly, these vias may be separately treated as a via group provided in an intersecting portion between the external power supply voltage line VDD 6   a  and the external power supply voltage line VDD 52 , a via group provided in an intersecting portion between the external power supply voltage line VDD 6   b  and the external power supply voltage line VDD 52 , and a via group provided in an intersecting portion between the projecting portion  6 D and the external power supply voltage line VDD 52 , but the via V straddling a plurality of intersecting portions may be further formed. 
         [0172]    Similarly, the external ground voltage lines VSS 6   a  and VSS 6   b  shown in  FIGS. 6A and 6C  are equal to the external power supply voltage line VDD 43  and the external ground voltage line VSS 43  shown in  FIG. 1G  having a projecting portion  6 S integrally added thereto. As a result, the external ground voltage lines VSS 6   a  and VSS 6   b  and the projecting portion  6 S are integrated as a wiring, so hereinafter this is referred to as an external ground voltage line VSS 6 . 
         [0173]    The projecting portion  6 S is formed in a region, between the external ground voltage lines VSS 6   a  and VSS 6   b , included in the output circuit Out. Accordingly, the projecting portion  6 S includes a first intersecting portion intersecting with the external power supply voltage lines VDD 51  and VDD 52 , a second intersecting portion intersecting with the external ground voltage lines VSS 51  and VSS 52 , and the other portion. 
         [0174]    In this second intersecting portion, the via V is formed to couple the external ground voltage line VSS 6  to the external ground voltage lines VSS 51  and VSS 52 . Here, these vias may be separately treated as a via group provided in an intersecting portion between the external ground voltage line VSS 6   a  and the external ground voltage line VSS 51 , a via group provided in an intersecting portion between the external ground voltage line VSS 6   b  and the external ground voltage line VSS 51 , and a via group provided in an intersecting portion between the projecting portion  6 S and the external ground voltage line VSS 51 , but the via V straddling a plurality of intersecting portions may be further formed. Similarly, these vias may be separately treated as a via group provided in an intersecting portion between the external ground voltage line VSS 6   a  and the external ground voltage line VSS 52 , a via group provided in an intersecting portion between the external ground voltage line VSS 6   b  and the external ground voltage line VSS 52 , and a via group provided in an intersecting portion between the projecting portion  6 S and the external ground voltage line VSS 52 , but the via V straddling a plurality of intersecting portions may be further formed. 
         [0175]    The use of the wiring portion  6  according to the fifth embodiment shown in  FIGS. 6A to 6C  provides the following effects. That is, the power supply circuit of the semiconductor device is reinforced by providing the external power supply voltage line VDD 6  and the external ground voltage line VSS 6 , the wiring width of each of which has been significantly increased, and increasing a total number of vias V transmitting the external power supply voltage Vdd and the external ground voltage Vss between the wiring layers. The embodiment is effective especially when a drop of a power supply voltage and/or power EM is restrained by a total number of vias V and also there is delamination larger than criteria. 
       Sixth Embodiment 
       [0176]      FIG. 7A  is a plan view showing the configuration of a wiring portion  7  according to a sixth embodiment. The components of the wiring portion  7  shown in  FIG. 7A  are described. The wiring portion  7  shown in  FIG. 7A  includes external power supply voltage lines VDD 7   a , VDD 7   b  and VDD 51  to VDD 54 , external ground voltage lines VSS 7   a , VSS 7   b  and VSS 51  to VSS 54 , local ground lines ARVSS 7   a  and ARVSS 7   b , and the vias V. 
         [0177]      FIG. 7B  is a plan view showing the configuration of the external power supply voltage lines VDD 7   a  and VDD 7   b  according to the sixth embodiment.  FIG. 7C  is a plan view showing the configuration of the external ground voltage lines VSS 7   a  and VSS 7   b  according to the sixth embodiment. The external power supply voltage lines VDD 7   a  and VDD 7   b  shown in  FIGS. 7A and 7B  are equal to the external power supply voltage line VDD 42  and the external ground voltage line VS 542  shown in  FIG. 1G  having a projecting portion  7 D integrally added thereto. As a result, the external power supply voltage lines VDD 7   a  and VDD 7   b  and the projecting portion  7 D are integrated as a wiring, so hereinafter this is referred to as an external power supply voltage line VDD 7 . 
         [0178]    Similarly, the external ground voltage lines VSS 7   a  and VSS 7   b  shown in  FIGS. 7A and 7C  are equal to the external power supply voltage line VDD 43  and the external ground voltage line VSS 43  shown in  FIG. 1G  having a projecting portion  7 S integrally added thereto. As a result, the external ground voltage lines VSS 7   a  and VSS 7   b  and the projecting portion  7 S are integrated as a wiring, so hereinafter this is referred to as an external ground voltage line VSS 7 . 
         [0179]    The wiring portion  7  according to the sixth embodiment shown in  FIGS. 7A to 7C  is equal to the wiring portion  6  according to the fifth embodiment shown in  FIGS. 6A to 6C  added by the following changes. That is, the wiring widths of the external power supply voltage lines VDD 7   a  and VDD 7   b  and the external ground voltage lines VSS 7   a  and VSS 7   b  according to the sixth embodiment are set narrower than those of the external power supply voltage lines VDD 6   a  and VDD 6   b  and the external ground voltage lines VSS 6   a  and VSS 6   b  according to the fifth embodiment. The other configuration of the wiring portion  7  according to the present embodiment is the same as in the case of the fifth embodiment, so further detailed description is omitted. 
         [0180]    In the present embodiment, in addition to an effect similar to the effect obtained by the fifth embodiment, an effect that the interconnectivity improves further than in the case of the fifth embodiment is obtained. 
       Seventh Embodiment 
       [0181]      FIG. 8A  is a plan view showing the configuration of a wiring portion  8  according to a seventh embodiment. The components of the wiring portion  8  shown in  FIG. 8A  are described. The wiring portion  8  shown in  FIG. 8A  includes external power supply voltage lines VDD 8   a , VDD 8   b  and VDD 51  to VDD 54 , external ground voltage lines VSS 8   a , VSS 8   b  and VSS 51  to VSS 54 , and local ground lines ARVSS 8   a  and ARVSS 8   b , and the vias V. 
         [0182]      FIG. 8B  is a plan view showing the configuration of the external power supply voltage lines VDD 8   a  and VDD 8   b  according to the seventh embodiment.  FIG. 8C  is a plan view showing the configuration of the external ground voltage lines VSS 8   a  and VSS 8   b  according to the seventh embodiment. The external power supply voltage lines VDD 8   a  and VDD 8   b  shown in  FIGS. 8A and 8B  are equal to the external power supply voltage line VDD 42  and the external ground voltage line VS 542  shown in  FIG. 1G  having a first projecting portion  8 D 1  and a second projecting portion  8 D 2  added thereto and integrated thereinto. As a result, the external power supply voltage lines VDD 8   a  and VDD 8   b  and the first and second projecting portions  8 D 1  and  8 D 2  are integrated as a wiring, so hereinafter this is referred to as an external power supply voltage line VDD 8 . 
         [0183]    Similarly, the external ground voltage lines VSS 8   a  and VSS 8   b  shown in  FIGS. 8A and 8C  are equal to the external power supply voltage line VDD 43  and the external ground voltage line VSS 43  shown in  FIG. 1G  having a first projecting portion  8 S 1  and a second projecting portion  8 S 2  added thereto and integrated thereinto. As a result, the external ground voltage lines VSS 8   a  and VSS 8   b  and the projecting portion  8 S are integrated as a wiring, so hereinafter this is referred to as an external ground voltage line VSS 8 . 
         [0184]    The wiring portion  8  according to the seventh embodiment shown in  FIGS. 8A to 8C  is equal to the wiring portion  7  according to the sixth embodiment shown in  FIGS. 7A to 7C  added by the following changes. That is, from the projecting portion  7 D of the external power supply voltage line VDD 7  according to the seventh embodiment, portions other than the first or second intersecting portion intersecting with the external power supply voltage line VDD 51  or VDD 52  are removed. Similarly, from the projecting portion  7 S of the external ground voltage line VSS 7  according to the seventh embodiment, portions other than the first or second intersecting portion intersecting with the external ground voltage line VSS 51  or VSS 52  are removed. 
         [0185]    In other words, the first projecting portion  8 D 1  of the external power supply voltage line VDD 8  according to the seventh embodiment shown in  FIG. 8B  intersects with the external power supply voltage line VDD 51 , and is coupled thereto by the via V. Moreover, similarly, the second projecting portion  8 D 2  intersects with the external power supply voltage line VDD 52 , and is coupled thereto by the via V. Similarly, the first projecting portion  8 S 1  of the external ground voltage line VSS 8  according to the seventh embodiment shown in  FIG. 8C  intersects with the external ground voltage line VSS 51 , and is coupled thereto by the via V. Moreover, similarly, the second projecting portion  8 S 2  intersects with the external ground voltage line VSS 52 , and is coupled thereto by the via V. 
         [0186]    The other configuration of the wiring portion  8  according to the present embodiment is the same as in the case of the sixth embodiment, so further detailed description is omitted. 
         [0187]    In the present embodiment, the wiring widths of the external power supply voltage lines VDD 8   a  and VDD 8   b  and the external ground voltage lines VSS 8   a  and VSS 8   b  are suppressed to be small. Accordingly, in the present embodiment, in addition to an effect similar to the effect obtained by the sixth embodiment, an effect that the interconnectivity further improves is obtained. 
         [0188]    In the foregoing, the invention made by the present inventor has been specifically described based on the embodiments, but it is needless to say that the present invention is not limited to the above-described embodiments and various modifications are possible without departing from the scope and spirit of the present invention. Moreover, the respective embodiments described above can be arbitrarily combined without technically contradicting the contents of the embodiments.

Technology Category: 5