Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Chinese Patent Application No. 201510995951.1, filed Dec. 25, 2015. 
       BACKGROUND OF THE RELATED ART 
       [0002]    Technical Field 
         [0003]    The present invention relates to a test-used printed circuit board (PCB), and particularly to a test-used PCB having an in-series circuit involved with a join test action group (JTAG) signal. 
         [0004]    Prior Art 
         [0005]    For currently available test methods for slots, such as a memory slot and a peripheral component interconnect express (PCIE), a test-used printed circuit board (PCB) adopting a boundary scan technology is widely used. 
         [0006]    However, when a test-used PCB is used, it has be correspondingly electrically connected to a joint test action group (JTAG) of a test access port (TAP). When a large of amounts of slots, such as a memory slot and a PCI (peripheral component interconnect) express slot, have to be concurrently tested, the JTAG ports of the TAP controller have to be largely used. However, since the number of the JTAG ports provided by the TAP is limited, the test for the memory slots and the PCI express slots may not be undertaken concurrently. 
         [0007]    Although the number of the JTAG ports to be tested may be promoted by using an extension board of the TAP, the test-used PCB and the JTAG port of the TAP may involve a complexity and a confused corresponding relationship. 
         [0008]    In view of the above, there have long been the issues of complexity and inconvenience for the slots on the PCB to be tested. Therefore, there is a need to set forth an improvement means to settle down this problem. 
       SUMMARY 
       [0009]    In view of the issues of complexity and inconvenience for slots on a printed circuit board (PCB) to be tested encountered in the prior art, the present invention provides a test-used PCB having an in-series circuit involved with a JTAG signal. 
         [0010]    According to the present invention, the test-used PCB having an in-series circuit involved with the JTAG signal comprises a test-used PCB, and the test-used PCB comprises a first JTAG connective interface, a second JTAG connective interface, and at least a JTAG control chip. 
         [0011]    The first JTAG connective interface, the first joint test action group connective interface further comprising a first interface test clock (test clock, TCK) pin, a first interface test mode select (TMS) pin, a first interface test data (TDI) pin and a first interface test data out (TDO) pin. 
         [0012]    The second JTAG connective interface, the second JTAG connective interface further comprises a second TCK pin, a second interface TMS pin, a second interface TDI, and a second interface test TDO. 
         [0013]    The JTAG control chip, the JTAG control chip further comprises a chip TCK pin, a chip TMS pin, a chip TDI, and a chip TDO. 
         [0014]    Wherein, the first and second interface TCK pins and the chip TCK pin are electrically connected, the first and second interface TMS pins and the chip TMS pin are electrically connected, the first interface TDI pin is electrically connected to the chip TDI of one of the JTAG control chips, the chip TDI pin is electrically connected to the chip TDO pin of one of the JTAG control chips, or the chip TDO pin is electrically connected to the second interface TDI pin, and the first interface TDO pin is electrically connected to the second interface TDO pin. 
         [0015]    The system and method of the present invention has the difference as compared to the prior art that the test-used PCB has the first and second JTAG connective interfaces, through which over one test-used PCB may be connected in series, whereby a plurality of test-used PCBs may be connected in-series onto a JTAG port of a test access port (TAP) controller, to reduce the requirement of the TAP controllers and the JTAG port. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The present invention will be better understood from the following detailed descriptions of the preferred embodiments according to the present invention, taken in conjunction with the accompanying drawings, in which: 
           [0017]      FIG. 1  depicts a schematic diagram of a test-used printed circuit board (PCB) having an in-series circuit involved with a join test action group (JTAG) signal according to a first embodiment of the present invention; 
           [0018]      FIG. 2  depicts a schematic diagram of a test-used PCB having the in-series circuit involved with the JTAG signal according to a first embodiment of the present invention; and 
           [0019]      FIG. 3A  and  FIG. 3B  depict a schematic diagram of a pin arrangement of the first and second JTAG connective interfaces of the test-used PCB having the in-series circuit involved with the JTAG signal according to the present invention, respectively. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements. 
         [0021]    In the following, a first embodiment is set forth to explain how a test-used printed circuit board (PCB) having an in-series circuit involved with a join test action group (JTAG) signal according to the present invention is operated, with  FIG. 1  referred to simultaneously, wherein  FIG. 1  depicts a schematic diagram of the PCB having the in-series circuit involved with the JTAG signal according to the first embodiment of the present invention. 
         [0022]    In this embodiment, the test-used PCB having the in-series circuit involved with the JTAG signal according to the present invention comprises the test-used PCB  10 . The test-used PCB  10  further comprises a first JTAG connective interface  11 , a second JTAG connective interface  12 , and a JTAG control chip  13 . A first embodied aspect is only having a single JTAG control chip  13 . 
         [0023]    The first JTAG connective interface  11  further comprises a first test clock (TCK) pin TCK 1 , a first interface test mode select (TMS) pin TMS 1 , a first interface test data in (TDI) pin TDI 1 , and a first interface test data out (TDO) pin TDO 1 . 
         [0024]    The second JTAG connective interface  12  further comprises a second TCK pin TCK 2 , a first interface TMS pin TMS 1 , a first interface TDI pin TDI 1 , and a first interface TDO pin TDO 2 . 
         [0025]    The JTAG control chip  13  further comprises a chip test clock pin TCK 3 , a chip test mode select pin TMS 3 , a chip test data pin TDI 3 , and a chip test data out pin TDO 3 . 
         [0026]    The first interface TCK pin TCK 1 , the second interface clock pin TCK 2  and the chip test clock pin TCK 3  are electrically connected through a buffer chip  14  and a match resistor  15 , to promote a signal in quality. 
         [0027]    The first and second interface TMS pins TMS 1 , TMS 2  are electrically connected through the buffer chip  14  and the match resistor  15 , to promote the signal in quality. 
         [0028]    The first interface TDI pin TDI 1  and the chip TDI pin TDI 3  of the JTAG control chip  13  are electrically connected through pull-up resistor  16 . The chip TDO pin TDO 3  and the second interface TDI pin TDI 2  are electrically connected through the math resistor  15 , to promote the signal in quality. The first interface TDO pin TDO 1  and the second interface TDO pin TDO 2  are electrically connected. 
         [0029]    It is to be noted that a sequence of the first interface TCK pin TCK 1 , the first interface TMS pin TMS 1 , the first interface TDI pin TDI 1  and the first interface TDO pin TDO 1  of the first JTAG connective interface  11  and a sequence of the second interface TCK pin TCK 2 , the second interface TMS pin TMS 2 , the second interface TDI pin TDI 2  and the second interface TDO pin TDO 2  of the second JTAG connective interface  12  are the same. 
         [0030]    In this manner, two test-used PCBs  10  are connected in series through the first JTAG connective interface  11  and second JTAG connective interface  12 , so that a plurality of test-used PCBs  10  may be connected in series to a JATG port of a test access port (TAP) controller, to reduce a requirement of the TAP controller and the JTAG port. 
         [0031]    In the following, a second embodiment is set forth to explain how the test-used PCB having the in-series circuit involved with the JTAG signal according to the present invention is operated, with  FIG. 2  referred to simultaneously, wherein  FIG. 2  depicts a schematic diagram of the PCB having the in-series circuit involved with the JTAG signal according to the second embodiment of the present invention. 
         [0032]    In this embodiment, the PCB having the in-series circuit involved with the JTAG signal according to the present invention comprises the test-used PCB  10 . The test-used PCB  10  further comprises a first JTAG connective interface  11 , a second JTAG connective interface  12 , and a first JTAG control chip  131  and a second JTAG control chip  132 . The second embodied aspect is set forth by having only two JTAG control chips. Further, over two JTAG control chips may be deduced based on this embodied aspect, which is omitted herein for clarity. 
         [0033]    The first JTAG connective interface  11  further comprises a first test clock (TCK) pin TCK 1 , a first interface test mode select (TMS) pin TMS 1 , a first interface test data in (TDI) pin TDI 1 , and a first interface test data out (TDO) pin TDO 1 . 
         [0034]    The second JTAG connective interface  12  further comprises a second TCK pin TCK 2 , a first interface TMS pin TMS 2 , a first interface TDI pin TDI 2 , and a first interface TDO pin TDO 2 . 
         [0035]    The first JTAG control chip  131  further comprises a chip test clock pin TCK 3 , a chip test mode select pin TMS 3 , a chip test data pin TDI 3 , and a chip test data out pin TDO 3 . 
         [0036]    The second JTAG control chip  132  further comprises a chip test clock pin TCK 4 , a chip test mode select pin TMS 4 , a chip test data pin TDI 4 , and a chip test data out pin TDO 4 . 
         [0037]    The first interface TMS pin TMS 1 , the second interface TMS TMS 2  are electrically connected through a buffer chip  14  and a match resistor  15 , to promote a signal in quality. The first and second interface TMS pins TMS 1 , TMS 2  are electrically connected through the match resistor  15 , to promote the signal in quality. The chip TMS pin TMS 3  and the chip TMS pin TMS 4  are directly electrically connected. 
         [0038]    The first interface TDI pin TDI 1  and the chip TDI pin TDI 3  of the JTAG control chip  131  are electrically connected through the pull-up resistor  16 . The chip TDO pin TDO 3  and the chip TDI pin TDI 4  of the second JTAG control chip  132  are directly electrically connected. The chip TDO pin TDO 4  of the second JTAG control chip  132  are electrically connected to through the match resistor  15 , to promote the signal in quality. The first interface TDO pin TDO 1  and the second interface TDO pin TDO 2  are directly electrically connected. 
         [0039]    It is to be noted that a sequence of the first interface TCK pin TCK 1 , the first interface TMS pin TMS 1 , the first interface TDI pin TDI 1  and the first interface TDO pin TDO 1  of the first JTAG connective interface  11  and a sequence of the second interface TCK pin TCK 2 , the second interface TMS pin TMS 2 , the second interface TDI pin TDI 2  and the second interface TDO pin TDO 2  of the second JTAG connective interface  12  are the same. 
         [0040]    In this manner, two test-used PCBs  10  are connected in series through the first JTAG connective interface  11  and second JTAG connective interface  12 , so that a plurality of test-used PCBs  10  may be connected in series to a JATG port of a TAP controller, to reduce a requirement of the TAP controller and the JTAG port. 
         [0041]    In addition, with reference to  FIG. 3A  and  FIG. 3B , wherein  FIG. 3A  and  FIG. 3B  depict a schematic diagram of a pin arrangement of the first and second JTAG connective interfaces of the test-used PCB having the in-series circuit involved with the JTAG signal according to the present invention, respectively. 
         [0042]    The schematic diagram of the first JTAG connective interface  11  and the schematic diagram of the second JTAG connective interface  12  can be used to the first embodiment and the second embodiment. 
         [0043]    The first JTAG connective interface  11  further comprises ground pins GND corresponded and staggered with the first interface TCK pin TCK 1 , the first interface TMS pin TMS 1 , the first interface TDI pin TDI 1  and the first interface TDO pin TDO 1 . The ground pin GND is used to promote an EMI capability of the first interface TCK pin TCK 1 , the first interface TMS pin TMS 1 , the first interface TDI pin TDI 1  and the first interface TDO pin TDO 1 . 
         [0044]    The second JTAG connective interface  12  further comprises ground pins GND corresponded and staggered with the second interface TCK pin TCK 2 , the second interface TMS pin TMS 2 , the second interface TDI pin TDI 2  and the second interface TDO pin TDO 2 . The ground pin GND is used to promote an EMI capability of the second interface TCK pin TCK 2 , the second interface TMS pin TMS 2 , the second interface TDI pin TDI 2  and the second interface TDO pin TDO 2 . 
         [0045]    In addition, a sequence of the first interface TCK pin TCK 1 , the first interface TMS pin TMS 1 , the first interface TDI pin TDI 1  and the first interface TDO pin TDO 1  and the ground pins GND and a sequence of the second interface TCK pin TCK 2 , the second interface TMS pin TMS 2 , the second interface TDI pin TDI 2  and the second interface TDO pin TDO 2  and ground pins GND are the same. 
         [0046]    In this manner, two test-used PCBs  10  are connected in series through the first JTAG connective interface  11  and second JTAG connective interface  12 , so that a plurality of test-used PCBs  10  may be connected in series to a JATG port of a TAP controller, to reduce a requirement of the TAP controller and the JTAG port. 
         [0047]    In summary, the present invention has the technical difference as compared to the prior art that the test-used PCB has the first and second JTAG connective interfaces, through which over one test-used PCB may be connected in series, whereby a plurality of test-used PCBs may be connected in-series onto a JTAG port of a TAP controller, to reduce the requirement of the TAP controller and the JTAG port. 
         [0048]    By using the technical means, the issues encountered in the prior art that the complexity and inconvenience issues on the test-used PCB to be tested may be solved, to further achieve in the technical efficacy where the requirement of the TAP controllers and the JTAG ports may be reduced. 
         [0049]    Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the invention.

Technology Category: 3