Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a Delay-Locked Loop (DLL), or more particularly, a DLL with power-saving function. 
     2. Description of the Prior Art 
     Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating the Dynamic Random Access Memory (DRAM) system  100  of the prior art. The DRAM system  100  comprises the DLL  110  and the DRAM  120 . The DRAM system  100 , according to the DLL  110 , controls the DRAM  120  to access the data. DLL  110  generates a delayed clock signal CLK D  by receiving the reference clock signal CLK, delaying the reference clock signal CLK with a fixed phase, and accordingly generating a delayed clock signal CLK D . In other words, the clock signal CLK and delayed clock signal CLK D  have the same frequency, but the phase of the delayed clock signal CLK D  and the clock signal CLK is statically differentiated by the phase P D . The DRAM  120  comprises input ends I 1  and I 2 . The input end I 1  is utilized to receive the delayed clock signal CLK D  and the input end I 2  is utilized to receive the turn-off signal S CKE . When the DRAM  120  does not receive the turn-off signal S CKE , the DRAM  120  accesses the data according to the delayed clock signal CLK D . When the DRAM  120  receives the turn-off signal S CKE , the DRAM  120  stops receiving the delayed clock signal CLK D  and the data accessing is stopped. 
     When the DRAM  120  receives the turn-off signal S CKE , the DRAM  120  stops receiving the delayed clock signal CLK D  and the data accessing is stopped. In the meanwhile the phase of the delayed clock signal CLK D  of the DLL  110  and the clock signal CLK does not need to be differentiated by the phase P D  precisely. Due to the DLL  110 , after rebooting, needs a long time to generate the delayed clock signal CLK D  with the fixed phase difference P D  compared to the clock signal CLK (indicates the delayed clock signal CLK D  is locked to the clock signal CLK) and this wait time is too long and unacceptable for the DRAM  120 . Hence, the DLL  110  cannot be turned off completely as the DRAM  120  is turned off after receiving the turn-off signal S CKE . The DLL  110  needs to maintain normal operation while the DRAM  120  is turned off from receiving the turn-off signal S CKE , which consequently causing electrical power waste and diminish the convenience of the DRAM system  110  of the prior art. 
     SUMMARY OF THE INVENTION 
     The present invention provides a Delay-Locked Loop (DLL) with power-saving function. The DLL comprises a Voltage-Controlled Delay Loop (VCDL), and a voltage controlling module coupled to the second input end of the VCDL. The VCDL comprises a first input end for receiving a first clock signal, a second input end for receiving a controlling voltage, and an output end for outputting a second clock signal by delaying the first clock signal according to the controlling voltage. The voltage controlling module comprises a capacitor coupled between the second input end of the VCDL and a ground end for sustaining the controlling voltage, a phase detector for generating a first controlling signal and a second controlling signal according to phase difference between the first clock signal and the second clock signal, and a voltage controller. The voltage controller comprises a first controlling end for receiving the first controlling signal, a second controlling end for receiving the second controlling signal, a third controlling end for receiving a turn-off signal, and an output end coupled to the capacitor for sourcing or sinking a current with a predetermined magnitude to adjust the controlling voltage according to the first controlling signal, the second controlling signal and the turn-off signal. 
     The present invention further provides a DLL with power-saving function. The DLL comprises a VCDL and a voltage controlling module coupled to the second input end of the VCDL. The VCDL comprises a first input end for receiving a first clock signal, a second input end for receiving a controlling voltage, and an output end for outputting a second clock signal by delaying the first clock signal according to the controlling voltage. The voltage controlling module comprises a capacitor coupled between the second input end of the VCDL and a ground end for sustaining the controlling voltage, a phase detector for generating a first controlling signal and a second controlling signal according to phase difference between the first clock signal and the second clock signal, and a voltage controller. The voltage controller comprises a current controller and a charge pump. The current controller comprises a first controlling end for receiving the first controlling signal, a second controlling end for receiving the second controlling signal, a third controlling end for receiving a turn-off signal, a first output end for outputting a current controlling signal according to the first controlling signal and the second controlling signal, and a second output end for outputting a boot signal. The charge pump comprises a first controlling end coupled to the first output end of the current controller for receiving the current controlling signal, a second controlling end coupled to the second output end of the current controller for receiving the boot signal, and an output end coupled to the capacitor. Wherein when the charge pump receives the boot signal, the charge pump sources or sinks a current with a predetermined magnitude, according to the current controlling signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating the Dynamic Random Access Memory (DRAM) system of the prior art. 
         FIG. 2  is a diagram illustrating the DRAM system of the present invention 
         FIG. 3  is a diagram illustrating the voltage controller of the present invention. 
         FIG. 4  is a timing diagram illustrating the second embodiment of the current controller of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     For the purpose of saving power and granting the user with more convenience, the present invention provides a system that reduces the power consumption of the DLL  110 , when the DRAM  120  is turned off from receiving the turn-off signal S CKE . 
     Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating the DRAM system  200  of the present invention. As shown in  FIG. 2 , the DRAM system  200  comprises the DLL  210  and the DRAM  220 . 
     The DRAM  220  comprises two input ends I 1  and I 2 . The input end I 1  is utilized to receive the delayed clock signal CLK D  and the input end I 2  is utilized to receive the turn-off signal S CKE . When the DRAM  220  does not receive the turn-off signal S CKE , the DRAM  220  accesses the data according to the delayed clock signal CLK D . When the DRAM  220  receives the turn-off signal S CKE , the DRAM  220  stops receiving the delayed clock signal CLK D  and data accessing is stopped. 
     The DLL  210  comprises the Voltage Controlled Delay Loop (VCDL)  213  and the voltage controlling module  230 . The voltage controlling module  230  comprises the phase detector  211 , the voltage controller  212  and a capacitor C X . The phase detector  211  comprises two input ends I 1  and I 2 , and an output end O. The voltage controller  212  comprises three control ends C 1 , C 2 , and C 3 , and an output end O. The VCDL comprises two input ends I 1  and I 2 , and an output end O. 
     The input end I 1  of the VCDL  213  is utilized to receive the reference clock signal CLK; the input end I 2  is coupled to the capacitor C X ; the output end O is utilized to output the delay clock signal CLK D . The clock signal CLK and the delayed clock signal CLK D  have the same frequency, but the phase of the delayed clock signal CLK D  and the clock signal CLK is statically differentiated by a phase P D . The capacitor C X , with a voltage V X , is coupled between the input end I 2  of the VCDL  213  and the ground end. The VCDL  213  controls the phase difference P D  between the delayed clock signal CLK D  and the clock signal CLK, according to the voltage V X  of the capacitor C X . For instance, the higher the voltage V X , the larger the phase difference P D . Instead, the lower the voltage V X , the smaller the phase difference P D . The voltage controlling module  230  controls the magnitude of the voltage V X  to adjust the phase difference P D . 
     The input end I 1  of the phase detector  211  is utilized to receive the reference clock signal CLK; the input end I 2  is coupled to the output end O of the VCDL  213  to receive the delayed clock signal CLK D ; the output end O is coupled to the control end C of the voltage controller  212 . The phase detector  211 , according to the phase difference between the clock signal CLK and the delayed clock signal CLK D , outputs the control signals S UP  or S DN  to control the voltage controller  212  to further control the magnitude of the voltage V X . For instance, when the phase of the clock signal CLK is behind that of the delayed clock signal CLK D , the phase detector  211  outputs the control signal S DN  to the output end O; when the phase of the clock signal CLK is ahead that of the delayed clock signal CLK D , the phase detector  211  outputs the control signal S UP  to the output end O. 
     The control ends C 1  and C 2  of the voltage controller  212  are coupled to the output ends O 1  and O 2  respectively to receive the control signals S UP  and S DN  outputted from the phase detector  211 ; the output end O of the voltage controller  212  is coupled between the capacitor C X  and the VCDL  213  to source or sink a current I P  of a predetermined value to control the magnitude of the voltage V X ; the control end C 3  of the voltage controller  212  is utilized to receive the turn-off signal S CKE . The operation principle of the voltage controller  212  is explained as below: when the voltage controller  212  receives the control signal S UP , the voltage controller  212  sources the current I P  to the output end O of the voltage controller  212  to increase the voltage V X ; instead, when the voltage controller  212  receives the control signal S DN , the voltage controller  212  sinks the current I P  to the output end O of the voltage controller  212  to decrease the voltage V X . The magnitude of the current I P  is fixed. Also, when the control end C 3  of the voltage controller  212  receives the turn-off signal S CKE , the voltage controller  212  does not source/sink the current I P  to/from the capacitor C X . Hence, the voltage controller  212  of the present invention can be turned off when receiving the turn-off signal S CKE  to save power, without charging the capacitor C X  continuously. In the meanwhile, as the capacitor C X  is discharged to the ground end, the voltage V X  continues to decline, which causing the phase difference between the clock signal CLK and the delayed clock signal CLK D  to shift away from the fixed phase difference P D . Yet when the voltage controller  212  receives the turn-off signal S CKE , the DRAM  220  is also turned off from receiving the turn-off signal S CKE  and the consequent phase error is acceptable. In other words, the DRAM system  200  of the present invention can save power consumption by turning off the voltage controller  212  and the DRAM  220  at the same time. The present invention can also increase the capacitance of the capacitor C X  to decrease the decreasing speed of the voltage V X , limiting the error of the delayed clock signal CLK D  when receiving the turn-off signal S CKE . Also, turning off the voltage controller  212  does not cause the DLL  210  to require a long period of time for the delayed clock signal CLK D  to be locked to the clock signal CLK. In other words, when the voltage controller  212  is rebooted, the delayed clock signal CLK D  generated from the DLL  210  can be locked to the clock signal CLK in a short period of time. 
     Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the voltage controller  212  of the present invention. As shown in  FIG. 3 , the voltage controller  212  comprises the current controller  2121  and the charge pump  2122 . The current controller  2121  comprises three control ends C 4 , C 5 , and C 6 , and two output ends O 1  and O 2 . The charge pump  2122  comprises a control end C, a boot end EN, and an output end O. 
     The current controller  2121  receives the control signal S UP  and S DN , and the turn-off signal S CKE  to output the current controlling signal S I  and the boot signal S EN  accordingly, for controlling the charge pump  2122 . 
     In the first embodiment of the current controller  2121  of the present invention, when the turn-off signal S CKE  is not received, the current controller  2121  continues to transmit the boot signal S EN  to the charge pump  2122 , and transmit the current controlling signal S I  to the charge pump according to the control signals S UP  and S DN . Hence, under the state of continuous on, the charge pump  2122  charges or discharges the capacitor C X  according to the current controlling signal S I . When the turn-off signal S CKE  is received, the current controller  2121  stops transmitting the boot signal S EN  to the charge pump  2122 , causing the charge pump  2122  to be turned off. Hence, the power consumption of the charge pump  2122  is saved. 
     In the second embodiment of the current controller  2121  of the present invention, when the turn-off signal S CKE  is not received, the current controller  2121  continues to transmit the boot signal S EN  to the charge pump  2122 , and transmit the current controlling signal S I  to the charge pump  2122  according to the control signals S UP  and S DN . Hence, under the state of continuous on, the charge pump  2122  charges or discharges the capacitor C X  according to the current controlling signal S I . When the turn-off signal S CKE  is received, the current controller  2121  determines whether to transmit the boot signal S EN  to the charge pump  2122  according to the phase difference between the clock signal CLK and the delayed clock signal CLK D . More particularly, after the turn-off signal S CKE  is received, when the phase difference between the clock signal CLK and the delayed clock signal CLK D  is larger than the first predetermined value D PT , the current controller  2121  still transmits the boot signal S EN  to the charge pump  2122 , causing the charge pump  2122  to charge or discharge the capacitor C X  so the phase difference between the clock signal CLK and the delayed clock signal CLK D  does not continue to increase and cause excessive time for future phase locking. Also, after the turn-off signal S CKE  is received, when the phase difference between the clock signal CLK and the delayed clock signal CLK D  is smaller than the second predetermined value D PB , the current controller  2121  stops transmitting the boot signal S EN  to the charge pump  2122  and the charge pump  2122  is turned off. Hence, the second embodiment of the current controller  2121  of the present invention can still save the power consumption of the charge pump  2122 , and resulting in less time is needed for phasing locking after reboot. In addition, the first predetermined value D PT  can be larger than the second predetermined value D PB . 
     Please refer to  FIG. 4 .  FIG. 4  is a timing diagram illustrating the second embodiment of the current controller  2121  of the present invention. The current controller  2121 , according to the signal period between the controlling signals S UP  and S DN , determines the phase difference between the clock signal CLK and the delayed clock signal CLK D . As shown in  FIG. 4 , in the stage P 1 , the signal period difference of the turn-on state between the control signals S UP  and S DN  is D 1  and the signal period difference D 1  is smaller than the predetermined value D PB , causing the current controller  2121  to stop transmitting the boot signal S EN  and the charge pump  2122  is turned off. In the stage P 2 , the signal period difference of the turn-on state between the control signals S UP  and S DN  is D 2  and the signal period difference D 2  is larger than the predetermined value D PT , causing the current controller  2121  to start transmitting the boot signal S EN  to boot-up the charge pump  2122 . 
     To sum up, the DLL  210  of the present invention can effectively utilize the turn-off signal S CKE  to save the power consumption of the DLL  210 , providing more convenience to the user. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Technology Category: 5