Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a recess transistor (TR) gate in a semiconductor device. More particularly, the present invention relates to a recess transistor gate having increased space between adjacent recess gates and a method of forming the same.  
           [0003]    2. Description of the Related Art  
           [0004]    In order to achieve higher density, conventional dynamic random access memory (DRAM) cells utilize a storage capacitor and an insulated gate field effect transistor (FET). DRAM cells have been successively scaled down in size to the sub-micron range. However, as a result of this reduction in size, there are many challenges in designing a planar gate. As the width of the planar gate narrows accompanied with shorter channels, problems such as junction leakage, source/drain breakdown voltage, and data retention time become issues of concern. Efforts to increase the density and the required gate channel length have led to the development of a recess gate being formed within a silicon substrate. Conventionally, a width of a planar gate on an active region, i.e., an access gate, is larger than a width of a planar gate on a field region, i.e., a pass gate. The narrow space between the gates gives rise to a self-aligned contact (SAC) open margin problem.  
           [0005]    [0005]FIG. 1 illustrates a plan view of a conventional DRAM cell gate layout according to the prior art.  
           [0006]    In FIG. 1, a substrate (not shown) includes an active region  10  and a field region  18 . A gate layer  12  is formed over the substrate to intersect the active region  10 . An access gate  12   a  is formed over each intersection of the gate layer  12  and the active region  10 . Reference character W 1  represents a width of an access gate  12   a . A pass gate  12   b  is formed over each intersection of the gate layer  12  and the field region  18 . Reference character W 2  represents a width of a pass gate  12   b.    
           [0007]    A BC SAC region  14  is formed at a periphery of the active region  10 . Reference character d 1  represents a distance between an access gate and an adjacent pass gate, i.e., a size of the BC SAC region. A DC SAC region  16  is formed at a center of the active region  10 . Reference character d 2  represents a distance between adjacent access gates, i.e., a size of the DC SAC region. In this conventional arrangement, the width W 1  of an access gate  12   a  is designed to be larger than the width W 2  of a pass gate  12   b.    
           [0008]    Thus, as may be seen in this conventional planar gate structure, the width W 1  of the access gate  12   a  is larger than the width W 2  of a pass gate  12   b . Conventionally, it is necessary that the width W 1  of the access gate  12   a  be larger than the width W 2  of the pass gate  12   b  in order to increase the refresh time in the planar type gate. This arrangement, however, leads to the self-aligned contact (SAC) open margin problem as described above.  
         SUMMARY OF THE INVENTION  
         [0009]    In an effort to overcome at least some of the problems described above, the present invention forms a recess type gate having increased space between adjacent recess gates.  
           [0010]    It is a feature of an embodiment of the present invention to provide a memory cell of a semiconductor device including a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.  
           [0011]    In the memory cell, the width of each of the first self-aligned contact regions may be made larger than the width of each of the second self-aligned contact regions by each one of the plurality of access gates having a width smaller than a width of an adjacent pass gate. The width of each of the plurality of access gates may be decreased by a notch formed on at least one side of each of the plurality of access gates.  
           [0012]    In a preferred embodiment of the present invention, the notch formed on at least one side of each of the plurality of access gates is formed adjacent to the first self-aligned contact region so as to face one of the plurality of pass gates.  
           [0013]    In another embodiment of the present invention, the notch formed on at least one side of each of the plurality of access gates is formed adjacent to the second self-aligned contact region so as to face one of the plurality of access gates.  
           [0014]    In still another embodiment of the present invention, each of the plurality of access gates has a pair of notches, each notch formed on opposing sides of each of the plurality of access gates.  
           [0015]    In yet another embodiment of the present invention, sidewall spacers may be formed on sidewalls of each of the plurality of access gates and each of the plurality of pass gates. In addition, a recess hole may be formed having an opening and a bottom for receiving one of the plurality of access gates, wherein a width of the opening of the recess hole is larger than a width of the bottom of the recess hole. Further, the sidewall spacers formed on sidewalls of the plurality of access gates may extend below an upper surface of the substrate.  
           [0016]    It is another feature of an embodiment of the present invention to provide a method of forming a memory cell of a semiconductor memory device including forming an isolation region and an active region on a substrate, performing an ion implantation to form a source/drain region in the substrate, forming a recess gate hole by etching the substrate in the active region, forming a gate oxide layer on the active region of the substrate, forming a gate layer and a gate mask layer sequentially on the entire surface of the substrate, and etching the gate layer and the gate mask layer to form a plurality of access gates on the active region of the substrate and a plurality of pass gates on the field region of the substrate and to form a notch in each of the plurality of access gates so that a width of each of the plurality of access gates is narrower than a width of each of the pass gates, to thereby form a first self-aligned contact region between adjacent pass gates and access gates and a second self-aligned contact region between adjacent access gates, whereby a width of the first self-aligned contact region is larger than a width of the second self-aligned contact region.  
           [0017]    The method may further include forming sidewall spacers on sidewalls of each of the plurality of access gates and each of the plurality of pass gates.  
           [0018]    In the method, forming a recess gate hole by etching the substrate in the active region may include etching the substrate to form a recess gate hole having an opening and a bottom, wherein a width of the opening of the recess hole is larger than a width of the bottom of the recess hole. The method may further include forming sidewall spacers on sidewalls of each of the plurality of access gates and each of the plurality of pass gates, wherein the sidewall spacers formed on sidewalls of the plurality of access gates extend below an upper surface of the substrate.  
           [0019]    The method may further include forming an interlayer dielectric layer over the sidewall spacer formed on the sidewall of one of the plurality of pass gates and the field region of the substrate.  
           [0020]    In the method, forming the notch may include forming the notch on at least one side of each of the plurality of access gates adjacent to the first self-aligned contact region so as to face one of the plurality of pass gates, or may include forming the notch on at least one side of each of the plurality of access gates adjacent to the second self-aligned contact region so as to face one of the plurality of access gates, or may include forming a pair of notches in each of the plurality of access gates, each notch being formed on opposing sides of each of the plurality of access gates. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:  
         [0022]    [0022]FIG. 1 illustrates a plan view of a conventional DRAM cell gate layout according to the prior art;  
         [0023]    [0023]FIG. 2 illustrates a plan view of a DRAM cell gate layout according to a preferred embodiment of the present invention;  
         [0024]    [0024]FIG. 3 illustrates a cross-sectional view taken along line I-I′ of FIG. 2;  
         [0025]    [0025]FIGS. 4A-4G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIGS. 2 and 3;  
         [0026]    [0026]FIG. 5 illustrates an alternate embodiment of the preferred embodiment as shown in FIGS. 2 and 3;  
         [0027]    [0027]FIGS. 6A-6G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIG. 5;  
         [0028]    [0028]FIG. 7 illustrates a plan view of a DRAM cell gate layout according to a second embodiment of the present invention;  
         [0029]    [0029]FIG. 8 illustrates a cross-sectional view taken along line II-II′ of FIG. 7;  
         [0030]    [0030]FIGS. 9A-9G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIGS. 7 and 8;  
         [0031]    [0031]FIG. 10 illustrates an alternate embodiment of the second embodiment as shown in FIGS. 7 and 8;  
         [0032]    [0032]FIGS. 11A-11G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIG. 10;  
         [0033]    [0033]FIG. 12 illustrates a plan view of a DRAM cell gate layout according to a third embodiment of the present invention;  
         [0034]    [0034]FIG. 13 illustrates a cross-sectional view taken along line III-III′ of FIG. 12;  
         [0035]    [0035]FIGS. 14A-14G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIGS. 12 and 13;  
         [0036]    [0036]FIG. 15 illustrates an alternate embodiment of the third embodiment as shown in FIGS. 12 and 13; and  
         [0037]    [0037]FIGS. 16A-16G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIG. 15. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0038]    The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred and alternate embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals and characters refer to like elements throughout.  
         [0039]    Preferred Embodiment  
         [0040]    [0040]FIG. 2 illustrates a plan view of a DRAM cell gate layout according to a preferred embodiment of the present invention. FIG. 3 illustrates a cross-sectional view taken along line I-I′ of FIG. 2. FIGS. 4A-4G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIGS. 2 and 3.  
         [0041]    Referring to FIG. 2, a substrate ( 100  of FIG. 3) includes an active region  100   a  and a field region  100   b . A gate layer  130  is formed over the substrate to intersect the active region  100   a . The gate layer  130  includes an access gate  130   a  and a pass gate  130   b . An access gate  130   a  is formed over each intersection of the gate layer  130  and the active region  100   a . Reference character W A1  represents a width of an access gate  130   a . A pass gate  130   b  is formed over each intersection of the gate layer  130  and the field region  100   b . Reference character W P1  represents a width of a pass gate  130   b.    
         [0042]    A BC SAC region  102  is formed at a periphery of the active region  100   a . Reference character BC 1  represents a distance between an access gate  130   a  and an adjacent pass gate  130   b  in the BC SAC region. A DC SAC region  104  is formed at a center of the active region  100   a . Reference character DC 1  represents a distance between adjacent access gates  130   a  in the DC SAC region.  
         [0043]    The distance BC 1  is made larger than the distance DC 1  by decreasing a width of the access gates by etching notches  106  in the sides of the access gates  130   a  adjacent to the BC SAC region  102 . Preferably, notches  106  are etched only on a side of an access gate facing a pass gate, i.e., in the BC SAC region  102 . The notches  106  preferably have a depth of between about 10-20 nm.  
         [0044]    [0044]FIG. 3 illustrates a cross-sectional view taken along line I-I′ of FIG. 2. In FIG. 3, a pair of access gates  130   a  and a pair of pass gates  130   b  are formed on an active region  100   a  and a field region  100   b  of a substrate  100 , respectively. The substrate  100  includes a source region  108   a  and drain regions  108   b . The active region of the substrate includes a pair of recess holes  110  each formed at a location corresponding to one of the access gates  130   a . Each recess hole  110  is coated with a gate oxide layer  114  and filled with a gate poly layer  120 . Sidewall spacers  150  are formed on sidewalls of the access gates  130   a  and the pass gates  130   b  and a gate mask  140 , which is formed on the access gates  130   a  and the pass gates  130   b.    
         [0045]    An interlayer dielectric (ILD) oxide  160  is deposited over the field region  100   b  of the substrate  100 . A BC SAC  170  is formed in an opening between an access gate  130   a  and a pass gate  130   b  and a DC SAC  180  is formed in an opening between adjacent access gates  130   a.    
         [0046]    Table 1 is a comparison of critical dimensions of the prior art with the present invention. The width of the access gate W A1 , i.e., access gate size, of the present invention is smaller than that in the prior art, however the width of the pass gate W P1 , i.e., the pass gate size, is larger, thereby decreasing the word line resistance. In the present invention, both the size of the BC SAC region BC 1  and the size of the DC SAC region DC 1  are larger than in the prior art. Accordingly, in the present invention, the word line resistance is smaller than in the prior art because a pass gate size W P1  in the present invention is larger than in the prior art. Further, as the sizes of the BC SAC region BC 1  and the DC SAC region DC 1  increase, a SAC open margin improves.  
                               TABLE 1                           W A     W P     BC   DC           Access   Pass gate   BC SAC   DC SAC       Element   gate size   size   size   size                   Prior art   100 nm    60 nm   55 nm   50 nm       Present   70 nm   80 nm   63 nm   57 nm       invention   60 nm   80 nm   74 nm   66 nm                  
 
         [0047]    Preferably, a ratio of BC SAC region/DC SAC region is a range of approximately 1 to 1.2. Most preferably, the ratio is about 1.1, which ratio may be called the golden ratio. A ratio of less than about 1.0 does not satisfy the invention as the BC SAC region is too small. A ratio of greater than about 1.2 is similarly unworkable as the DC SAC region becomes too small to form a contact.  
         [0048]    A method of forming the DRAM cell gate layout according to the preferred embodiment of the present invention will now be described with reference to FIGS. 4A-4G.  
         [0049]    [0049]FIG. 4A illustrates a substrate  100  having an active region  100   a  and a field region  100   b  for forming a shallow trench isolation (STI) region. A first oxide layer  101  is then formed on the active  100   a  and field  100   b  regions of the substrate  100 . An ion implantation (shown by arrows) is then preformed to form source/drain regions in the substrate  100 .  
         [0050]    Referring to FIG. 4B, a second oxide layer  107  is formed on the first oxide layer  101 . An etching process is then performed to form a series of gate trenches  109  to serve as gate contacts.  
         [0051]    Referring to FIG. 4C, after formation of the gate trenches  109 , the second oxide layer  107  and the first oxide layer  101  are removed from the surface of the substrate  100 . Recess gate holes  110  are then formed in the active region  100   a  of the substrate  100  between the source region  108   a  and the drain regions  108   b , respectively, of the substrate  100 .  
         [0052]    Referring to FIG. 4D, a gate oxide layer  114  is formed on the active region  100   a  of the substrate  100 . The gate oxide layer  114  covers an upper surface of the active region  100   a  of the substrate  100  and interior surfaces of the recess gate holes  110 . A gate poly layer  125  and a gate mask layer  135  are then sequentially formed on the gate oxide layer  114  and on the field region  100   b  of the substrate  100 .  
         [0053]    Referring to FIG. 4E, a photoresist layer  138  is formed on the gate poly layer  125  and the gate mask layer  135 . The gate poly layer  125  and the gate mask layer  135  are then etched to form access gates  130   a  and gate masks  140  over the active region  100   a  of the substrate  100  and pass gates  130   b  and gate masks  140  over the field region  100   b  of the substrate  100 . Reference characters W A  and W P  represent widths of an access gate and a pass gate, respectively. Reference character BC represents a distance between an access gate and a pass gate. Reference character DC represents a distance between adjacent access gates.  
         [0054]    Referring to FIG. 4F, an insulation layer (not shown) is formed on the access gates  130   a  and the pass gates  130   b  and the substrate  100  by a chemical vapor deposition (CVD) process. The insulation layer is then etched to form sidewall spacers  150  on sidewalls of the access gates and the pass gates.  
         [0055]    Referring to FIG. 4G, an interlayer dielectric (ILD) oxide  160  is deposited on the access gates  130   a  and the pass gates  130   b  and the substrate  100 . The interlayer dielectric (ILD) oxide  160  is then etched to form an opening  165  over the active region  100   a  of the substrate  100  between adjacent access gates  130   a  and openings  175  over the active region  100   a  of the substrate  100  between the access gate  130   a  and the pass gate  130   b . The opening  175  between an access gate  130   a  and a pass gate  130   b  forms the BC SAC ( 170  of FIG. 3). The opening  165  between adjacent access gates  130   a  forms the DC SAC ( 180  of FIG. 3). The interlayer dielectric (ILD) oxide  160 , the BC SAC  170 , and the DC SAC  180  are then planarized to achieve the resultant structure as shown in FIG. 3.  
         [0056]    Alternate Preferred Embodiment  
         [0057]    [0057]FIG. 5 illustrates an alternate embodiment of the preferred embodiment as shown in FIGS. 2 and 3. FIGS. 6A-6G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIG. 5.  
         [0058]    In FIG. 5, a pair of access gates  130   a ′ and a pair of pass gates  130   b ′ are formed on an active region  100   a ′ and a field region  100   b ′ of a substrate  100 ′, respectively. The substrate  100 ′ includes a source region  108   a ′ and drain regions  108   b ′. The active region of the substrate includes a pair of recess holes  110 ′ each formed at a location corresponding to one of the access gates  130   a ′. Each recess hole  110 ′ is coated with a gate oxide layer  114 ′ and filled with a gate poly layer  120 ′. Sidewall spacers  150 ′ are formed on sidewalls of the access gates  130   a ′ and the pass gates  130   b ′ and a gate mask  140 ′, which is formed on the access gates  130   a ′ and the pass gates  130   b′.    
         [0059]    An interlayer dielectric (ILD) oxide  160 ′ is deposited over the field region  100   b ′ of the substrate  100 ′. A BC SAC  170 ′ is formed in an opening between an access gate  130   a ′ and a pass gate  130   b ′ and a DC SAC  180 ′ is formed in an opening between adjacent access gates  130   a′.    
         [0060]    In this alternate preferred embodiment of the present invention, recess gate holes  110 ′ are formed to have larger top openings as compared to a bottom thereof than in the preferred embodiment of the present invention. Reference character W O1  represents a width of the top opening of the recess gate hole. This larger top opening of the recess gate holes  110 ′ causes an over-etching of the access gates  130   a ′ during the etching to form the access gates  130   a ′ and the pass gates  130   b ′. Subsequently, when sidewall spacers  150 ′ are formed, the sidewall spacers  150 ′ extend below an upper surface of the substrate  100 ′ and into the recess hole  110 ′. Accordingly, a width W′ A1  of the access gate  130   a ′ is made smaller, thereby increasing a distance BC′ 1  and a distance DC′ 1  and improving a contact open margin.  
         [0061]    A method of forming the DRAM cell gate layout according to the alternate preferred embodiment of the present invention will now be described with reference to FIGS. 6A-6G.  
         [0062]    [0062]FIG. 6A illustrates a substrate  100 ′ having an active region  100   a ′ and a field region  100   b ′ for forming a shallow trench isolation (STI) region. A first oxide layer  101 ′ is then formed on the active  100   a ′ and field  100   b ′ regions of the substrate  100 ′. An ion implantation (shown by arrows) is then preformed to form source/drain regions in the substrate  100 ′.  
         [0063]    Referring to FIG. 6B, a second oxide layer  107 ′ is formed on the first oxide layer  101 ′. An etching process is then performed to form a series of gate trenches  109 ′ to serve as gate contacts.  
         [0064]    Referring to FIG. 6C, after formation of the gate trenches  109 ′, the second oxide layer  107 ′ and the first oxide layer  101 ′ are removed from the surface of the substrate  100 ′. Recess gate holes  110 ′ are then formed in the active region  100   a ′ of the substrate  100 ′ between the source region  108   a ′ and the drain regions  108   b ′, respectively, of the substrate  100 ′.  
         [0065]    Referring to FIG. 6D, a gate oxide layer  114 ′ is formed on the active region  100   a ′ of the substrate  100 ′. The gate oxide layer  114 ′ covers an upper surface of the active region  100   a ′ of the substrate  100 ′ and interior surfaces of the recess gate holes  110 ′. A gate poly layer  125 ′ and a gate mask layer  135 ′ are then sequentially formed on the gate oxide layer  114 ′ and on the field region  100   b ′ of the substrate  100 ′.  
         [0066]    As may be seen in FIG. 6D, the recess gate holes  110 ′ are etched to have larger top openings as compared to a bottom thereof than in the preferred embodiment of the present invention. Reference character W O1  represents a width of the top opening of the recess gate hole.  
         [0067]    Referring to FIG. 6E, a photoresist layer  138 ′ is formed on the gate poly layer  125 ′ and the gate mask layer  135 ′. The gate poly layer  125 ′ and the gate mask layer  135 ′ are then etched to form access gates  130   a ′ and gate masks  140 ′ over the active region  100   a ′ of the substrate  100 ′ and pass gates  130   b ′ and gate masks  140 ′ over the field region  100   b ′ of the substrate  100 ′. Reference characters W′ A1  and W′ P1  represent widths of an access gate and a pass gate, respectively. Reference character BC′ 1  represents a distance between an access gate and a pass gate. Reference character DC′ 1  represents a distance between adjacent access gates.  
         [0068]    During the etching to form the access gates  130   a ′ and the pass gates  130   b ′, the larger top opening of the recess gate holes  110 ′ causes an over-etching of the access gates  130   a ′. Subsequently, when sidewall spacers ( 150 ′ of FIG. 6F) are formed, the sidewall spacers  150 ′ extend below an upper surface of the substrate  100 ′ and into the recess hole  110 ′.  
         [0069]    Accordingly, a width W′ A1  of the access gate  130   a ′ is made smaller, thereby increasing a distance BC′ 1  and a distance DC′ 1  and improving a contact open margin.  
         [0070]    Referring to FIG. 6F, an insulation layer (not shown) is formed on the access gates  130   a ′ and the pass gates  130   b ′ and the substrate  100 ′ by a chemical vapor deposition (CVD) process. The insulation layer is then etched to form sidewall spacers  150 ′ on sidewalls of the access gates and the pass gates. As described above, in view of the over-etching of the access gates  130   a ′, the sidewall spacers  150 ′ extend below an upper surface of the substrate  100 ′.  
         [0071]    Referring to FIG. 6G, an interlayer dielectric (ILD) oxide  160 ′ is deposited on the access gates  130   a ′ and the pass gates  130   b ′ and the substrate  100 ′. The interlayer dielectric (ILD) oxide  160 ′ is then etched to form an opening  165 ′ over the active region  100   a ′ of the substrate  100 ′ between adjacent access gates  130   a ′ and openings  175 ′ over the active region  100   a ′ of the substrate  100 ′ between the access gate  130   a ′ and the pass gate  130   b ′. The opening  175 ′ between an access gate  130   a ′ and a pass gate  130   b ′ forms the BC SAC ( 170 ′ of FIG. 5). The opening  165 ′ between adjacent access gates  130   a ′ forms the DC SAC ( 180 ′ of FIG. 5). The interlayer dielectric (ILD) oxide  160 ′, the BC SAC  170 ′, and the DC SAC  180 ′ are then planarized to achieve the resultant structure as shown in FIG. 5.  
         [0072]    In the alternate preferred embodiment, due to over-etching of the access gates  130   a ′, the width W A ′ of the access gate  130   a ′ is made smaller, thereby increasing a distance BC′ and a distance DC′. The increase in the distance BC′ and the distance DC′ results in an improvement to the contact open margin.  
         [0073]    Second Embodiment  
         [0074]    [0074]FIG. 7 illustrates a plan view of a DRAM cell gate layout according to a second embodiment of the present invention. FIG. 8 illustrates a cross-sectional view taken along line II-II′ of FIG. 7. FIGS. 8A-8G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIGS. 7 and 8.  
         [0075]    Referring to FIG. 7, a substrate ( 200  of FIG. 8) includes an active region  200   a  and a field region  200   b . A gate layer  230  is formed over the substrate to intersect the active region  200   a . The gate layer  230  includes an access gate  230   a  and a pass gate  230   b . An access gate  230   a  is formed over each intersection of the gate layer  230  and the active region  200   a . Reference character W A2  represents a width of an access gate  230   a . A pass gate  230   b  is formed over each intersection of the gate layer  230  and the field region  200   b . Reference character W P2  represents a width of a pass gate  230   b.    
         [0076]    A BC SAC region  202  is formed at a periphery of the active region  200   a . Reference character BC 2  represents a distance between an access gate  230   a  and an adjacent pass gate  230   b  in the BC SAC region. A DC SAC region  204  is formed at a center of the active region  200   a . Reference character DC 2  represents a distance between adjacent access gates  230   a  in the DC SAC region.  
         [0077]    In the second embodiment of the present invention, the width of the access gates W A2  is made smaller than the width of the pass gates W P2  by etching notches  206  in sides of the access gates  230   a  adjacent to the DC SAC region  204 . In this embodiment, the notches  206  are etched only on a side of an access gate  230   a  facing an adjacent access gate  230   a , i.e., in the DC SAC region  202 . The notches  106  preferably have a depth of between about 10-20 nm.  
         [0078]    [0078]FIG. 8 illustrates a cross-sectional view taken along line II-II′ of FIG. 7. In FIG. 8, a pair of access gates  230   a  and a pair of pass gates  230   b  are formed on an active region  200   a  and a field region  200   b  of a substrate  200 , respectively. The substrate  200  includes a source region  208   a  and drain regions  208   b . The active region of the substrate includes a pair of recess holes  210  each formed at a location corresponding to one of the access gates  230   a . Each recess hole  210  is coated with a gate oxide layer  214  and filled with a gate poly layer  220 . Sidewall spacers  250  are formed on sidewalls of the access gates  230   a  and the pass gates  230   b  and a gate mask  240 , which is formed on the access gates  230   a  and the pass gates  230   b.    
         [0079]    An interlayer dielectric (ILD) oxide  260  is deposited over the field region  200   b  of the substrate  200 . A BC SAC  270  is formed in an opening between an access gate  230   a  and a pass gate  230   b  and a DC SAC  280  is formed in an opening between adjacent access gates  230   a.    
         [0080]    As in the preferred embodiment, preferably, a ratio of BC SAC region/DC SAC region is a range of approximately 1 to 1.2. Most preferably, the ratio is the golden ration, i.e., about 1.1.  
         [0081]    A method of forming the DRAM cell gate layout according to the second embodiment of the present invention will now be described with reference to FIGS. 9A-9G.  
         [0082]    [0082]FIG. 9A illustrates a substrate  200  having an active region  200   a  and a field region  200   b  for forming a shallow trench isolation (STI) region. A first oxide layer  201  is then formed on the active  200   a  and field  200   b  regions of the substrate  200 . An ion implantation (shown by arrows) is then preformed to form source/drain regions in the substrate  200 .  
         [0083]    Referring to FIG. 9B, a second oxide layer  207  is formed on the first oxide layer  201 . An etching process is then performed to form a series of gate trenches  209  to serve as gate contacts.  
         [0084]    Referring to FIG. 9C, after formation of the gate trenches  209 , the second oxide layer  207  and the first oxide layer  201  are removed from the surface of the substrate  200 . Recess gate holes  210  are then formed in the active region  200   a  of the substrate  200  between the source region  208   a  and the drain regions  208   b , respectively, of the substrate  200 .  
         [0085]    Referring to FIG. 9D, a gate oxide layer  214  is formed on the active region  200   a  of the substrate  200 . The gate oxide layer  214  covers an upper surface of the active region  200   a  of the substrate  200  and interior surfaces of the recess gate holes  210 . A gate poly layer  225  and a gate mask layer  235  are then sequentially formed on the gate oxide layer  214  and on the field region  200   b  of the substrate  200 .  
         [0086]    Referring to FIG. 9E, a photoresist layer  238  is formed on the gate poly layer  225  and the gate mask layer  235 . The gate poly layer  225  and the gate mask layer  235  are then etched to form access gates  230   a  and gate masks  240  over the active region  200   a  of the substrate  200  and pass gates  230   b  and gate masks  240  over the field region  200   b  of the substrate  200 . Reference characters W A2  and W P2  represent widths of an access gate and a pass gate, respectively. Reference character BC 2  represents a distance between an access gate  230   a  and a pass gate  230   b . Reference character DC 2  represents a distance between adjacent access gates  230   a.    
         [0087]    Referring to FIG. 9F, an insulation layer (not shown) is formed on the access gates  230   a  and the pass gates  230   b  and the substrate  200  by a chemical vapor deposition (CVD) process. The insulation layer is then etched to form sidewall spacers  250  on sidewalls of the access gates  230   a  and the pass gates  230   b.    
         [0088]    Referring to FIG. 9G, an interlayer dielectric (ILD) oxide  260  is deposited on the access gates  230   a  and the pass gates  230   b  and the substrate  200 . The interlayer dielectric (ILD) oxide  260  is then etched to form an opening  265  over the active region  200   a  of the substrate  200  between adjacent access gates  230   a  and openings  275  over the active region  200   a  of the substrate  200  between the access gate  230   a  and the pass gate  230   b . The opening  275  between an access gate  230   a  and a pass gate  230   b  forms the BC SAC ( 270  of FIG. 8). The opening  265  between adjacent access gates  230   a  forms the DC SAC ( 280  of FIG. 8). The interlayer dielectric (ILD) oxide  260 , the BC SAC  270 , and the DC SAC  280  are then planarized to achieve the resultant structure as shown in FIG. 8.  
         [0089]    Alternate Second Embodiment  
         [0090]    [0090]FIG. 10 illustrates an alternate embodiment of the second embodiment as shown in FIGS. 7 and 8. FIGS. 11A-11G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIG. 10.  
         [0091]    In FIG. 10, a pair of access gates  230   a ′ and a pair of pass gates  230   b ′ are formed on an active region  200   a ′ and a field region  200   b ′ of a substrate  200 ′, respectively. The substrate  200 ′ includes a source region  208   a ′ and drain regions  208   b ′. The active region of the substrate includes a pair of recess holes  210 ′ each formed at a location corresponding to one of the access gates  230   a ′. Each recess hole  210 ′ is coated with a gate oxide layer  214 ′ and filled with a gate poly layer  220 ′. Sidewall spacers  250 ′ are formed on sidewalls of the access gates  230   a ′ and the pass gates  230   b ′ and a gate mask  240 ′, which is formed on the access gates  230   a ′ and the pass gates  230   b′.    
         [0092]    An interlayer dielectric (ILD) oxide  260 ′ is deposited over the field region  200   b ′ of the substrate  200 ′. A BC SAC  270 ′ is formed in an opening between an access gate  230   a ′ and a pass gate  230   b ′ and a DC SAC  280 ′ is formed in an opening between adjacent access gates  230   a′.    
         [0093]    In this alternate preferred embodiment of the present invention, recess gate holes  210 ′ are formed to have larger top openings as compared to a bottom thereof than in the preferred embodiment of the present invention. Reference character W O2  represents a width of the top opening of the recess gate hole. This larger top opening of the recess gate holes  210 ′ causes an over-etching of the access gates  230   a ′ during the etching to form the access gates  230   a ′ and the pass gates  230   b ′. Subsequently, when sidewall spacers  250 ′ are formed, the sidewall spacers  250 ′ extend below an upper surface of the substrate  200 ′ and into the recess hole  210 ′. Accordingly, a width W′ A2  of the access gate  230   a ′ is made smaller, thereby increasing a distance BC′ 2  and a distance DC′ 2  and improving a contact open margin.  
         [0094]    A method of forming the DRAM cell gate layout according to the alternate second embodiment of the present invention will now be described with reference to FIGS. 11A-11G.  
         [0095]    [0095]FIG. 11A illustrates a substrate  200 ′ having an active region  200   a ′ and a field region  200   b ′ for forming a shallow trench isolation (STI) region. A first oxide layer  201 ′ is then formed on the active  200   a ′ and field  200   b ′ regions of the substrate  200 ′. An ion implantation (shown by arrows) is then preformed to form source/drain regions in the substrate  200 ′.  
         [0096]    Referring to FIG. 11B, a second oxide layer  207 ′ is formed on the first oxide layer  201 ′. An etching process is then performed to form a series of gate trenches  209 ′ to serve as gate contacts.  
         [0097]    Referring to FIG. 11C, after formation of the gate trenches  209 ′, the second oxide layer  207 ′ and the first oxide layer  201 ′ are removed from the surface of the substrate  200 ′. Recess gate holes  210 ′ are then formed in the active region  200   a ′ of the substrate  200 ′ between the source region  208   a ′ and the drain regions  208   b ′, respectively, of the substrate  200 ′.  
         [0098]    Referring to FIG. 11D, a gate oxide layer  214 ′ is formed on the active region  200   a ′ of the substrate  200 ′. The gate oxide layer  214 ′ covers an upper surface of the active region  200   a ′ of the substrate  200 ′ and interior surfaces of the recess gate holes  210 ′. A gate poly layer  225 ′ and a gate mask layer  235 ′ are then sequentially formed on the gate oxide layer  214 ′ and on the field region  200   b ′ of the substrate  200 ′.  
         [0099]    As may be seen in FIG. 11D, the recess gate holes  210 ′ are etched to have larger top openings as compared to a bottom thereof than in the preferred embodiment of the present invention. Reference character W O2  represents a width of the top opening of the recess gate hole.  
         [0100]    Referring to FIG. 11E, a photoresist layer  238 ′ is formed on the gate poly layer  225 ′ and the gate mask layer  235 ′. The gate poly layer  225 ′ and the gate mask layer  235 ′ are then etched to form access gates  230   a ′ and gate masks  240 ′ over the active region  200   a ′ of the substrate  200 ′ and pass gates  230   b ′ and gate masks  240 ′ over the field region  200   b ′ of the substrate  200 ′. Reference characters W′ A2  and W′ P2  represent widths of an access gate  230   a ′ and a pass gate  230   b ′, respectively. Reference character BC′ 2  represents a distance between an access gate  230   a ′ and a pass gate  230   b ′. Reference character DC′ 2  represents a distance between adjacent access gates  230   a′.    
         [0101]    During the etching to form the access gates  230   a ′ and the pass gates  230   b ′, the larger top opening of the recess gate holes  210 ′ causes an over-etching of the access gates  230   a ′. Subsequently, when sidewall spacers ( 250 ′ of FIG. 11F) are formed, the sidewall spacers  250 ′ extend below an upper surface of the substrate  200 ′ and into the recess hole  210 ′. Accordingly, a width W′ A2  of the access gate  230   a ′ is made smaller, thereby increasing a distance BC′ 2  and a distance DC′ 2  and improving a contact open margin.  
         [0102]    Referring to FIG. 11F, an insulation layer (not shown) is formed on the access gates  230   a ′ and the pass gates  230   b ′ and the substrate  200 ′ by a chemical vapor deposition (CVD) process. The insulation layer is then etched to form sidewall spacers  250 ′ on sidewalls of the access gates and the pass gates. As described above, in view of the over-etching of the access gates  230   a ′, the sidewall spacers  250 ′ extend below an upper surface of the substrate  200 ′.  
         [0103]    Referring to FIG. 11G, an interlayer dielectric (ILD) oxide  260 ′ is deposited on the access gates  230   a ′ and the pass gates  230   b ′ and the substrate  200 ′. The interlayer dielectric (ILD) oxide  260 ′ is then etched to form an opening  265 ′ over the active region  200   a ′ of the substrate  200 ′ between adjacent access gates  230   a ′ and openings  275 ′ over the active region  200   a ′ of the substrate  200 ′ between the access gate  230   a ′ and the pass gate  230   b ′. The opening  275 ′ between an access gate  230   a ′ and a pass gate  230   b ′ forms the BC SAC ( 270 ′ of FIG. 10). The opening  265 ′ between adjacent access gates  230   a ′ forms the DC SAC ( 280 ′ of FIG. 10). The interlayer dielectric (ILD) oxide  260 ′, the BC SAC  270 ′, and the DC SAC  280 ′ are then planarized to achieve the resultant structure as shown in FIG. 10.  
         [0104]    In the alternate preferred embodiment, due to over-etching of the access gates  230   a ′, the width W′ A2  of the access gate  230   a ′ is made smaller, thereby increasing a distance BC′ 2  and a distance DC′ 2 . The increase in the distance BC′ 2  and the distance DC′ 2  results in an improvement to the contact open margin.  
         [0105]    Third Embodiment  
         [0106]    [0106]FIG. 12 illustrates a plan view of a DRAM cell gate layout according to a third embodiment of the present invention. FIG. 13 illustrates a cross-sectional view taken along line III-III′ of FIG. 12. FIGS. 14A-14G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIGS. 12 and 13.  
         [0107]    Referring to FIG. 12, a substrate ( 300  of FIG. 13) includes an active region  300   a  and a field region  300   b . A gate layer  330  is formed over the substrate to intersect the active region  300   a . The gate layer  330  includes an access gate  330   a  and a pass gate  330   b . An access gate  330   a  is formed over each intersection of the gate layer  330  and the active region  300   a . Reference character W A3  represents a width of an access gate  330   a . A pass gate  330   b  is formed over each intersection of the gate layer  330  and the field region  300   b . Reference character W P3  represents a width of a pass gate  330   b.    
         [0108]    A BC SAC region  302  is formed at a periphery of the active region  300   a . Reference character BC 3  represents a distance between an access gate  330   a  and an adjacent pass gate  330   b  in the BC SAC region. A DC SAC region  304  is formed at a center of the active region  300   a . Reference character DC 3  represents a distance between adjacent access gates  330   a  in the DC SAC region.  
         [0109]    In the third embodiment of the present invention, the width of the access gates W A3  is made smaller than the width of the pass gates W P3  by etching notches  306  in both sides of the access gates  330   a , i.e., adjacent to the DC SAC region  304  and adjacent to the BC SAC region  302 . The third embodiment is a combination of the preferred and the second embodiment in that the notches  306  are etched on a side of an access gate facing an adjacent access gate, i.e., in the DC SAC region  302 , and a side of an access gate facing a pass gate, i.e., in the BC SAC region  304 . The notches  306  preferably have a depth of between about 10-20 nm.  
         [0110]    [0110]FIG. 13 illustrates a cross-sectional view taken along line III-III′ of FIG. 12. In FIG. 13, a pair of access gates  330   a  and a pair of pass gates  330   b  are formed on an active region  300   a  and a field region  300   b  of a substrate  300 , respectively. The substrate  300  includes a source region  308   a  and drain regions  308   b . The active region of the substrate includes a pair of recess holes  310  each formed at a location corresponding to one of the access gates  330   a . Each recess hole  310  is coated with a gate oxide layer  314  and filled with a gate poly layer  320 . Sidewall spacers  350  are formed on sidewalls of the access gates  330   a  and the pass gates  330   b  and a gate mask  340 , which is formed on the access gates  330   a  and the pass gates  330   b.    
         [0111]    An interlayer dielectric (ILD) oxide  360  is deposited over the field region  300   b  of the substrate  300 . A BC SAC  370  is formed in an opening between an access gate  330   a  and a pass gate  330   b  and a DC SAC  380  is formed in an opening between adjacent access gates  330   a.    
         [0112]    As in the preferred embodiment, preferably, a ratio of BC SAC region/DC SAC region is a range of approximately 1 to 1.2. Most preferably, the ratio is the golden ration, i.e., about 1.1.  
         [0113]    A method of forming the DRAM cell gate layout according to the third embodiment of the present invention will now be described with reference to FIGS. 14A-14G.  
         [0114]    [0114]FIG. 14A illustrates a substrate  300  having an active region  300   a  and a field region  300   b  for forming a shallow trench isolation (STI) region. A first oxide layer  301  is then formed on the active  300   a  and field  300   b  regions of the substrate  300 . An ion implantation (shown by arrows) is then preformed to form source/drain regions in the substrate  300 .  
         [0115]    Referring to FIG. 14B, a second oxide layer  307  is formed on the first oxide layer  301 . An etching process is then performed to form a series of gate trenches  309  to serve as gate contacts.  
         [0116]    Referring to FIG. 14C, after formation of the gate trenches  309 , the second oxide layer  307  and the first oxide layer  301  are removed from the surface of the substrate  300 . Recess gate holes  310  are then formed in the active region  300   a  of the substrate  300  between the source region  308   a  and the drain regions  308   b , respectively, of the substrate  300 .  
         [0117]    Referring to FIG. 14D, a gate oxide layer  314  is formed on the active region  300   a  of the substrate  300 . The gate oxide layer  314  covers an upper surface of the active region  300   a  of the substrate  300  and interior surfaces of the recess gate holes  310 . A gate poly layer  325  and a gate mask layer  335  are then sequentially formed on the gate oxide layer  314  and on the field region  300   b  of the substrate  300 .  
         [0118]    Referring to FIG. 14E, a photoresist layer  338  is formed on the gate poly layer  325  and the gate mask layer  335 . The gate poly layer  325  and the gate mask layer  335  are then etched to form access gates  330   a  and gate masks  340  over the active region  300   a  of the substrate  300  and pass gates  330   b  and gate masks  340  over the field region  300   b  of the substrate  300 . Reference characters W A3  and W P3  represent widths of an access gate and a pass gate, respectively. Reference character BC 3  represents a distance between an access gate  330   a  and a pass gate  330   b . Reference character DC 3  represents a distance between adjacent access gates  330   a.    
         [0119]    Referring to FIG. 14F, an insulation layer (not shown) is formed on the access gates  330   a  and the pass gates  330   b  and the substrate  300  by a chemical vapor deposition (CVD) process. The insulation layer is then etched to form sidewall spacers  350  on sidewalls of the access gates  330   a  and the pass gates  330   b.    
         [0120]    Referring to FIG. 14G, an interlayer dielectric (ILD) oxide  360  is deposited on the access gates  330   a  and the pass gates  330   b  and the substrate  300 . The interlayer dielectric (ILD) oxide  360  is then etched to form an opening  365  over the active region  300   a  of the substrate  300  between adjacent access gates  330   a  and openings  375  over the active region  300   a  of the substrate  300  between the access gate  330   a  and the pass gate  330   b . The opening  375  between an access gate  330   a  and a pass gate  330   b  forms the BC SAC ( 370  of FIG. 13). The opening  365  between adjacent access gates  330   a  forms the DC SAC ( 380  of FIG. 13). The interlayer dielectric (ILD) oxide  360 , the BC SAC  370 , and the DC SAC  380  are then planarized to achieve the resultant structure as shown in FIG. 13.  
         [0121]    Alternate Third Embodiment  
         [0122]    [0122]FIG. 15 illustrates an alternate embodiment of the third embodiment of the present invention. FIGS. 16A-16G illustrate stages in a method of forming the DRAM cell gate layout as shown in FIG. 15.  
         [0123]    In FIG. 15, a pair of access gates  330   a ′ and a pair of pass gates  330   b ′ are formed on an active region  300   a ′ and a field region  300   b ′ of a substrate  300 ′, respectively. The substrate  300 ′ includes a source region  308   a ′ and drain regions  308   b ′. The active region of the substrate includes a pair of recess holes  310 ′ each formed at a location corresponding to one of the access gates  330   a ′. Each recess hole  310 ′ is coated with a gate oxide layer  314 ′ and filled with a gate poly layer  320 ′. Sidewall spacers  350 ′ are formed on sidewalls of the access gates  330   a ′ and the pass gates  330   b ′ and a gate mask  340 ′, which is formed on the access gates  330   a ′ and the pass gates  330   b′.    
         [0124]    An interlayer dielectric (ILD) oxide  360 ′ is deposited over the field region  300   b ′ of the substrate  300 ′. A BC SAC  370 ′ is formed in an opening between an access gate  330   a ′ and a pass gate  330   b ′ and a DC SAC  380 ′ is formed in an opening between adjacent access gates  330   a′.    
         [0125]    In this alternate preferred embodiment of the present invention, recess gate holes  310 ′ are formed to have larger top openings as compared to a bottom thereof than in the preferred embodiment of the present invention. Reference character W O3  represents a width of the top opening of the recess gate hole. This larger top opening of the recess gate holes  310 ′ causes an over-etching of the access gates  330   a ′ during the etching to form the access gates  330   a ′ and the pass gates  330   b ′. Subsequently, when sidewall spacers  350 ′ are formed, the sidewall spacers  350 ′ extend below an upper surface of the substrate  300 ′ and into the recess hole  310 ′. Accordingly, a width W′ A3  of the access gate  330   a ′ is made smaller, thereby increasing a distance BC′ 3  and a distance DC′ 3  and improving a contact open margin.  
         [0126]    A method of forming the DRAM cell gate layout according to the alternate third embodiment of the present invention will now be described with reference to FIGS. 16A-16G.  
         [0127]    [0127]FIG. 16A illustrates a substrate  300 ′ having an active region  300   a ′ and a field region  300   b ′ for forming a shallow trench isolation (STI) region. A first oxide layer  301 ′ is then formed on the active  300   a ′ and field  300   b ′ regions of the substrate  300 ′. An ion implantation (shown by arrows) is then preformed to form source/drain regions in the substrate  300 ′.  
         [0128]    Referring to FIG. 16B, a second oxide layer  307 ′ is formed on the first oxide layer  301 ′. An etching process is then performed to form a series of gate trenches  309 ′ to serve as gate contacts.  
         [0129]    Referring to FIG. 16C, after formation of the gate trenches  309 ′, the second oxide layer  307 ′ and the first oxide layer  301 ′ are removed from the surface of the substrate  300 ′. Recess gate holes  310 ′ are then formed in the active region  300   a ′ of the substrate  300 ′ between the source region  308   a ′ and the drain regions  308   b ′, respectively, of the substrate  300 ′.  
         [0130]    Referring to FIG. 16D, a gate oxide layer  314 ′ is formed on the active region  300   a ′ of the substrate  300 ′. The gate oxide layer  314 ′ covers an upper surface of the active region  300   a ′ of the substrate  300 ′ and interior surfaces of the recess gate holes  310 ′. A gate poly layer  325 ′ and a gate mask layer  335 ′ are then sequentially formed on the gate oxide layer  314 ′ and on the field region  300   b ′ of the substrate  300 ′.  
         [0131]    As may be seen in FIG. 16D, the recess gate holes  310 ′ are etched to have larger top openings as compared to a bottom thereof than in the preferred embodiment of the present invention. Reference character W O3  represents a width of the top opening of the recess gate hole.  
         [0132]    Referring to FIG. 16E, a photoresist layer  338 ′ is formed on the gate poly layer  325 ′ and the gate mask layer  335 ′. The gate poly layer  325 ′ and the gate mask layer  335 ′ are then etched to form access gates  330   a ′ and gate masks  340 ′ over the active region  300   a ′ of the substrate  300 ′ and pass gates  330   b ′ and gate masks  340 ′ over the field region  300   b ′ of the substrate  300 ′. Reference characters W′ A3  and W′ P3  represent widths of an access gate  330   a ′ and a pass gate  330   b ′, respectively. Reference character BC′ 3  represents a distance between an access gate  330   a ′ and a pass gate  330   b ′. Reference character DC′ 3  represents a distance between adjacent access gates  330   a′.    
         [0133]    During the etching to form the access gates  330   a ′ and the pass gates  330   b ′, the larger top opening of the recess gate holes  310 ′ causes an over-etching of the access gates  330   a ′. Subsequently, when sidewall spacers ( 350 ′ of FIG. 16F) are formed, the sidewall spacers  350 ′ extend below an upper surface of the substrate  300 ′ and into the recess hole  310 ′.  
         [0134]    Accordingly, a width W′ A3  of the access gate  330   a ′ is made smaller, thereby increasing a distance BC′ 3  and a distance DC′ 3  and improving a contact open margin.  
         [0135]    Referring to FIG. 16F, an insulation layer (not shown) is formed on the access gates  330   a ′ and the pass gates  330   b ′ and the substrate  300 ′ by a chemical vapor deposition (CVD) process. The insulation layer is then etched to form sidewall spacers  350 ′ on sidewalls of the access gates and the pass gates. As described above, in view of the over-etching of the access gates  330   a ′, the sidewall spacers  350 ′ extend below an upper surface of the substrate  300 ′.  
         [0136]    Referring to FIG. 16G, an interlayer dielectric (ILD) oxide  360 ′ is deposited on the access gates  330   a ′ and the pass gates  330   b ′ and the substrate  300 ′. The interlayer dielectric (ILD) oxide  360 ′ is then etched to form an opening  365 ′ over the active region  300   a ′ of the substrate  300 ′ between adjacent access gates  330   a ′ and openings  375 ′ over the active region  300   a ′ of the substrate  300 ′ between the access gate  330   a ′ and the pass gate  330   b ′. The opening  375 ′ between an access gate  330   a ′ and a pass gate  330   b ′ forms the BC SAC ( 370 ′ of FIG. 15). The opening  365 ′ between adjacent access gates  330   a ′ forms the DC SAC ( 380 ′ of FIG. 15). The interlayer dielectric (ILD) oxide  360 ′, the BC SAC  370 ′, and the DC SAC  380 ′ are then planarized to achieve the resultant structure as shown in FIG. 15.  
         [0137]    In the alternate third embodiment, due to over-etching of the access gates  330   a ′, the width W′ A3  of the access gate  330   a ′ is made smaller, thereby increasing a distance BC′ 3  and a distance DC′ 3 . The increase in the distance BC′ 3  and the distance DC′ 3  results in an improvement to the contact open margin.  
         [0138]    Preferred and alternate embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Technology Category: 5