Patent Document

TECHNICAL FIELD  
       [0001]     The field of the invention is that of fabricating integrated circuits, in particular forming apertures of sub-lithographic dimensions through a dielectric.  
       BACKGROUND OF THE INVENTION  
       [0002]     As dimensions have shrunk, lithographic engineers have resorted to various methods to reduce the size of apertures passing through interlevel dielectrics such as growing a polymer on the vertical surface of a resist hole (Relacs); a reflow of resist; a negative etch bias in transferring the contact hole to the substrate; and deposition of a sidewall spacer on the inside of the contact hole.  
         [0003]     The negative etch bias often introduced a slope in the profile of the aperture, resulting in poor control of the aperture size.  
         [0004]     The spacer approach introduced an additional etch step.  
         [0005]     Various approaches have been shown in patents for depositing layers of oxide from the liquid phase, such as U.S. Pat. No. 6,251,753, U.S. Pat. No. 6,653,245, and U.S. Pat. No. 5,776,829 incorporated by reference.  
       SUMMARY OF THE INVENTION  
       [0006]     The invention relates to a method of reducing the size of a contact aperture being etched into a dielectric.  
         [0007]     A feature of the invention is the etching of an oversized hole using current lithography through a hardmask containing oxide bonds.  
         [0008]     Another feature of the invention is the selective liquid phase deposition (LPD) of oxide on an exposed interior aperture surface containing Si—OH bonds.  
         [0009]     Yet another feature of the invention is etching an aperture through the underlying dielectric using the reduced diameter hole as a mask. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  shows a stack of films for use with the invention.  
         [0011]      FIG. 2  shows the result of etching an oversized hole through a sacrificial oxide.  
         [0012]      FIG. 3  shows the result of selective growing oxide on the exposed oxide surface.  
         [0013]      FIG. 4  shows the result of using the reduced-size hole as an etch mask.  
         [0014]      FIG. 5  shows a partially pictorial, partially schematic view of an integrated circuit using the invention. 
     
    
     DETAILED DESCRIPTION  
       [0015]      FIG. 1  illustrates a portion of an integrated circuit being fabricated showing a substrate  10  that will contain underlying layers, e.g. source/drain areas of planar transistors, other lower interconnect structures, the bulk silicon, etc, not shown in this figure.  
         [0016]     Dielectric  20  is illustratively an interlayer dielectric such as silicon dioxide, a fluorinated silicon dioxide, a silicon oxycarbide material (such as black diamond™ from Applied Materials), an organic material such as SiLK™ or polyimide. The thickness of this material is typically in the range of 500-1000 nm, with preferred values of 600-800 nm. This material will be referred to as the pattern layer, since the result of the process is the formation of a pattern of apertures in this layer.  
         [0017]     A hard mask  30  such as nitride (Si3N4) or polysilicon will be patterned with a hole that is larger than the desired final size and, after processing according to the invention, serve as the mask to etch an aperture through dielectric  20 . Preferably, the initial hole will be formed by conventional lithographic techniques. If the desired final size is so much smaller than the smallest conventional aperture, the initial hole may be formed by a sublithographic technique such as sidewall image transfer.  
         [0018]     A layer  40  containing Si—OH bonds (or having a fraction of oxide, SiO2) has been deposited over the hardmask layer  30 . This layer  40  will serve as a seed layer for the selective deposition of silicon oxide from an aqueous solution. This oxide-containing material can be a conventional layer of CVD oxide such as TEOS, or a spin-on glass material, or a silsesquioxane material.  
         [0019]     Layer  40  could also be a siloxane resist material that is photo sensitive and may be directly imaged with a contact hole pattern.  
         [0020]     Layer  40  could also be an anti-reflective layer ordinarily used for a photoresist layer, e.g. HOSP, available from Honeywell.  
         [0021]     The seed layer  40  can range in thickness from 20-200 nm, with a range of 20-50 nm preferred for an oxide or antireflective layer and 100-200 preferred for a resist layer.  
         [0022]     Typically, resist layer  50  is spun-on over seed layer  40 , exposed and developed to form the structure in  FIG. 1 , having aperture  52  with dimension  55 . Dimension  55  may be sublithographic using a standard technique or it may be formed by a conventional lithographic process.  
         [0023]     A directional oxide etch (illustratively with CHF3/O2 mixtures at 10-100 mtorr, with the wafer biased to create an ion-driven etch process at the wafer surface), stopping on nitride  30 , is used to remove the oxide-containing seed layer  40  at the bottom of the aperture  52  to produce the result shown in  FIG. 2 .  
         [0024]     With the vertical sides of the oxide-containing seed layer  40  exposed (and the top surface covered by the resist) the wafer is immersed in a saturated hydrofluoro-silicic acid H2SiF6 solution, as described in the US patents listed in the background section of the specification, and a film of oxide is grown on the exposed vertical surface through LPD.  
         [0025]     The thickness of the LPD-grown film can range from 5-50 nm or so, for high-density CMOS applications, in which case the width  55  of the contact hole pattern in aperture  52 ′ is reduced by a corresponding 10-100 nm.  
         [0026]     The amount of oxide that is permitted to grow will depend on the desired width reduction and may preferentially be 20-30 nm for many applications.  
         [0027]      FIG. 3  shows the result of the LPD step, in which an oxide film  45  has been formed on the vertical surfaces of seed layer  40 . The diameter of the aperture has been reduced to a value  47 , equivalent to the value  55  minus twice the thickness of film  45 .  
         [0028]     Several options are available to achieve a selective oxide deposition process. If a high quality silicon nitride layer is used as the hardmask  30 , then it will not react with the hydrosilicic acid, in the case of LDP, or with Trimethyl aluminum, in the case of the ALD growth of silicon oxide. Alternatively, if layer  30  is composed of polysilicon, it can be passivated with fluorine by exposing it to HF vapor prior to LDP or ALD oxide growth. In another option, one can use a siloxane resist over nitride layer  30 , or over polysilicon layer  30 , or over an unreactive organic underlayer such as diamond-like carbon annealed in hydrogen, parylene, or bottom antireflective coating. These undercoat films may also be treated with hexamethyidisilazane prior to resist apply, as a means of masking any reactive chemical species on their surface. The siloxane resist is exposed and developed down to the unreactive organic underlayer, followed by growth of the LPD or ALD oxide film directly onto the siloxane resist.  
         [0029]     In an alternative to the growth of the oxide film by LPD, one might also use an atomic layer deposition process, such as that disclosed in US 2004/0043149 (incorporated by reference). In this process, a vapor of trimethylaluminum reacts with active hydroxyl groups on the surface of silicon oxide or siloxane films to create a surface-bound aluminum catalyst species. Then, a vapor of tris(t-butoxy)silanol is introduced to the substrate to grow films of 5-12 nm, depending on reaction time and temperature, at 200-300 C. The catalyst treatment can be repeated, followed by exposure to fresh silanol reagent, to grow films of the desired thickness. This process is highly uniform and conformal, due to its nature as a surface-limited reaction.  
         [0030]      FIG. 4  shows the result of stripping resist  50  and etching through hardmask  30  and then through ILD  20 . The LPD film  45  serves to define the dimension of the aperture formed in hardmask  30 . After the aperture in hardmask  30  is formed, the hardmask defines the width of aperture  100 . It does not matter, therefore, if the etch process used for ILD  20  attacks the film  45 .  
         [0031]      FIG. 5  illustrates in a partially pictorial, partially schematic view of an integrated circuit, in which substrate  10  represents a bulk or SOI substrate, and a transistor  100  having source/drain  102  has been formed by conventional deposition, lithography and implantation techniques. A first level dielectric  20  has apertures formed according to the invention filled with a conductor  104  to form vias, one of which connects to block  400  that represents schematically the remainder of the integrated circuit. The preliminary steps of blanket implants, forming the various transistors will be referred to for purposes of the claims as preparing the substrate and the later steps after the sublithographic vias have been formed; i.e. forming the interconnects and the remainder of the back end processing will be referred to as completing the circuit.  
         [0032]     The etching techniques and etch chemistry will depend on the material being etched and the underlying layer below that material. In an illustrative example, the material of layer  40  is oxide, the material of layer  30  is nitride, and the material of layer  20  is oxide. The etch process to form aperture  52 ′ is a conventional oxide etch that stops on nitride  30 . The etch process to form aperture  100  is also a conventional oxide etch that is resisted by hardmask  30 .  
         [0033]     Advantageously, the thickness of layers  40  and  50  are set such that resist layer  50  and seed layer  40  are both consumed during the etch process that opens aperture  100 , so that a removal step for these layers is not required. If that is not practical in a particular example, then any remainder of layer  40  will be stripped.  
         [0034]     In a particular example in which layer  40  is a siloxane photoresist, layer  50  will not be used and aperture  52 ′ will be formed directly in layer  40 .  
         [0035]     While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.

Technology Category: 5