Patent Document

CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2004-181173, filed on Jun. 18, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an image display system and an image processing device, and more particularly, to an image display system that displays different images on a plurality of display devices (display screens) and to an image processing device used in the image display system.  
         [0004]     2. Description of the Related Art  
         [0005]     In an electronic device (image display system) having a graphics display function such as a car navigation system and a portable game machine, a plurality of virtual sheets called layers to place images thereon are superposed or changed in order to add some element to or to change an image on a display device. Japanese Unexamined Patent Application Publication No. 2003-288071, for example, has disclosed an image processing device which reads a plurality of pieces of image data from a memory and synthesizes the read image data in a predetermined order for output, and an image display system using this image processing device.  
         [0006]     In configuring an image display system that displays different images on, for example, two display devices by use of the conventional image processing device, the image display system need to include two sets of an image processing device including a circuit for reading image data from memories and a circuit for synthesizing the read image data, and memories for storing the image data, in association with the two display devices. This greatly increases the scale of the image display system as well as the manufacturing cost.  
       SUMMARY OF THE INVENTION  
       [0007]     It is an object of the present invention to display different images on a plurality of display devices without any increase in the scale of an image display system.  
         [0008]     According to one of the aspects of the present invention, an image display system includes a plurality N of image display units, an image storing unit, a read unit, a destination specifying unit, a divided-period setting unit, a synthesis unit, and a separating unit. For example, the read unit, the destination specifying unit, the divided-period setting unit, and the synthesis unit constitute an image processing device. The image storing unit stores therein a plurality of pieces of image data. The read unit reads each of the plural pieces of image data from the image storing unit for output. The destination specifying unit specifies the image display unit to be a display destination of each of the plural pieces of image data outputted from the read unit. The divided-period setting unit divides a unit display period of the image display units to N divided periods to correspond to the image display units, respectively. In each of the divided periods set by the divided-period setting unit, the synthesis unit synthesizes, for sequential outputs, the image data from the read unit according to the display destination by the destination specifying unit, in order to multiplex the image data to be displayed on each of the image display units. During the unit display period, the separating unit separates the image data outputted from the synthesis unit in each of the divided periods and outputs the separated image data to the respective image display units corresponding to the divided periods.  
         [0009]     In the image display system as configured above, the image data are multiplexed in each unit display period of the image display units for display on each of the image display units by synthesizing the image data outputted from the read unit in each of the divided periods according to the display destination specified by the destination specifying unit. Therefore, unlike the case where the conventional image processing device is used, the image display system need not include a plurality of sets of a circuit for image data read from an image storing unit, a circuit for synthesizing the read image data (image processing device), and an image storing unit, in association with a plurality of image display units. This enables the display of different images on the plurality of image display units without any increase in the scale of the image display system. As a result, it is able to reduce the manufacturing cost of the image display system.  
         [0010]     In addition, for the image processing device having the read unit, the destination specifying unit, the divided-period setting unit, and the synthesis unit, for example, it is easy to separate image data outputted from the synthesis unit for each of the image display units because Image data is separately outputted in each of the divided periods within the unit display period of the image display units for display thereon. Besides, this image processing device multiplexes the image data to be displayed on the respective image display units, so that it is able to output the image data without any increase in the number of output terminals for the image data. This can contribute to a reduction in the manufacturing cost of the image display system.  
         [0011]     In a preferable example of the aforesaid aspect of the present invention, a plurality of read circuits in the read unit correspond to the plurality of pieces of image data stored in the image storing unit respectively. Each of the read circuits reads a corresponding piece of image data and outputs the read piece together with an image validity signal indicating validity/invalidity of the image data. The destination specifying unit outputs, for each of the plural pieces of the image data outputted from the plural read circuits, a destination signal that indicates an image display unit to be a display destination. The divided-period setting unit outputs a divided-period signal indicating a current divided period. A plurality of mask circuits in the synthesis unit correspond to the plural read circuits, respectively. In accordance with a corresponding destination signal and the divided-period signal, each of the mask circuits masks the image validity signal from its corresponding read circuit during a period which excludes a divided period corresponding to an image display unit to display image data from the corresponding read circuit. A plurality of synthesis circuits in the synthesis unit are connected in series, corresponding to the plural mask circuits respectively. Each of the synthesis circuits selects, for output, image data outputted from its corresponding read circuit when the image validity signal masked by its corresponding mask circuit indicates validity, while selecting, for output, image data outputted from a preceding stage when the image validity signal masked by the corresponding mask circuit indicates invalidity. The read unit and the synthesis unit can be easily formed as described above.  
         [0012]     In a preferable example of the aforesaid aspect of the present invention, the destination specifying unit has, for each of the plural pieces of image data from the plural read circuits, N bits in association with the respective image display units, and outputs each bit value of the N bits as the destination signal. This makes it possible to constitute the destination specifying unit with a simple circuitry.  
         [0013]     In a preferable example of the aforesaid aspect of the present invention, the number N of the image display units is 2. The destination specifying unit has, for each of the plural pieces of the image data from the plural read circuits, a bit in association with one of the two image display units and outputs a bit value and an inverse value of the bit as the destination signal. Compared with a case where the destination specifying unit has, for each of the plural pieces of the image data from the plural read circuits, two bits in association with the two image display units, the number of bits can be halved if the image data outputted from each of the read circuits need not be displayed on both of the image display units. Accordingly, it is possible to reduce the circuit scale of the destination specifying unit.  
         [0014]     In a preferable example of the aforesaid aspect of the present invention, a video image supply unit outputs image data to form a video image in sequence. A write unit writes to the image storing unit the image data sequentially outputted from the video image supply unit. The write unit continuously rewrites the image data in the image storing unit, so as to display the video image on the image display units. With application of the image display system thus configured to, for example, a car navigation system having display screens on a driver&#39;s seat side and a rear seat side of a car, it is possible to display images relating to route guidance on the display screen on the driver&#39;s seat side and to display video images (DVD playback images, images received from television broadcast, or the like) on the display screen on the rear seat side at the same time. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:  
         [0016]      FIG. 1  is a block diagram showing a first embodiment of the present invention;  
         [0017]      FIG. 2  is a block diagram showing a graphics LSI and a separator in  FIG. 1 ;  
         [0018]     FIGS.  3 ( a ) to ( d ) show examples of image data stored in a graphics memory in  FIG. 2 ;  
         [0019]      FIG. 4  shows the register structure of a destination specifying register in  FIG. 2 ;  
         [0020]      FIG. 5  is a block diagram showing a memory read circuit in  FIG. 2 ;  
         [0021]      FIG. 6  is a block diagram showing a phase selector and a synthesis circuit in  FIG. 2 ;  
         [0022]      FIG. 7  is a timing chart showing the operation of the phase selector and the synthesis circuit in  FIG. 2 ;  
         [0023]      FIG. 8  is a timing chart showing the operation of the separator in  FIG. 2 ;  
         [0024]     FIGS.  9 ( a ), ( b ) show examples of image display on an image display system in  FIG. 1 ;  
         [0025]      FIG. 10  shows data flow corresponding to the examples of image display in FIGS.  9 ( a ), ( b );  
         [0026]      FIG. 11  shows data flow corresponding to the examples of image display in FIGS.  9 ( a ), ( b );  
         [0027]     FIGS.  12 ( a ), ( b ) show other examples of image display on the image display system in  FIG. 1 ;  
         [0028]      FIG. 13  shows data flow corresponding to the examples of image display in FIGS.  12 ( a ), ( b );  
         [0029]      FIG. 14  is a block diagram showing an image display system using conventional image processing devices;  
         [0030]      FIG. 15  is a block diagram showing a second embodiment of the present invention;  
         [0031]      FIG. 16  is a block diagram showing a graphics LSI and a separator in  FIG. 15 ;  
         [0032]      FIG. 17  is a block diagram showing a memory write circuit in  FIG. 16 ; and  
         [0033]      FIG. 18  is a diagram showing a modification example of the destination specifying register in  FIG. 4 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0034]     Hereinafter, embodiments of the present invention will be described with reference to the drawings.  FIG. 1  shows a first embodiment of the present invention. An image display system  100  (graphics display system) adopting a raster scan method has a host CPU  102 , a ROM  104 , a RAM  106 , an input device  108 , a graphics LSI  110  (image processing device), a bus  112 , a graphics memory  114  (image storing unit), a separator  116  (separating unit), and display devices  118 ,  120  (image display units). The host CPU  102  controls each unit according to programs stored in the ROM  104  or the RAM  106  and processes various arithmetic operations. The ROM  104  stores the programs to be executed by the host CPU  102  and various kinds of data. The RAM  106  tentatively stores the programs to be executed by the host CPU  102  and various kinds of data. The input device  108  is constituted of, for example, a pointing device, and generates and outputs data according to a user&#39;s operation.  
         [0035]     The graphics LSI  1110  reads image data from the graphics memory  114  and appropriately synthesizes the read image data for output to the separator  116 . The graphics LSI  110  will be described in detail in  FIG. 2 . The bus  112  connects the host CPU  102 , the ROM  104 , the RAM  106 , the input device  108 , and the graphics LSI  110  to one another to enable data exchange thereamong. Image data are written to the graphics memory  114  by the host CPU  102  via the graphics LSI  110 . Further, the graphics memory  114  outputs image data to the graphics LSI  110  in response to a request from the graphics LSI  110 .  
         [0036]     The separator  116  separates the image data outputted from the graphics LSI  110  into image data to be displayed on the display device  118  and image data to be displayed on the display device  120  and outputs the respective image data to the display devices  118 ,  120 .  
         [0037]     The separator  116  will be described in detail together with the graphics LSI  110  in  FIG. 2 .  
         [0038]     The display devices  118 ,  120 , each constituted of, for example, an LCD (Liquid Crystal Display), display the image data outputted from the separator  116 .  
         [0039]      FIG. 2  shows the graphics LSI  110  and the separator  116  in  FIG. 1 . FIGS.  3 ( a ) to ( d ) show examples of image data stored in the graphics memory  114  in  FIG. 2 .  FIG. 4  shows the structure of a destination specifying register  126  in  FIG. 2 .  FIG. 5  shows a memory read circuit  130   a  in  FIG. 2 .  FIG. 6  shows a phase selector  134   a  and a synthesis circuit  138   a  in  FIG. 2 . Image data, for example, shown in FIGS.  3 ( a ) to ( d ) are stored in areas A to D of the graphics memory  114 , respectively. The graphics LSI  110  has a clock generator  122  (divided-period setting unit), a video timing generator  124 , the destination specifying register  126  (destination specifying unit), a host access circuit  128 , memory read circuits  130   a  to  130   d  (read unit), a graphics memory interface  132 , phase selectors  134   a  to  134   d  (mask circuit, synthesis unit), a background color register  136 , and synthesis circuits  138   a  to  138   d  (synthesis unit).  
         [0040]     Using, for example, a PLL circuit and a programmable divider (not shown), the clock generator  122  generates a clock DCLK for determining an image output speed of the graphics LSI  110  to output it to the video timing generator  124 . Specifically, a period of the clock DCLK corresponds to a display period for one pixel on the display devices  118 ,  120  (unit display period). The clock generator  122  outputs to the phase selectors  134   a  to  134   d  a phase signal PHASE (divided-period signal) that varies in synchronization with transition edges of the clock DCLK. A period between rising edges (or falling edges) of the phase signal PHASE corresponds to the display period for one pixel on the display devices  118 ,  120 . Therefore, the display period for one pixel on the display devices  118 ,  120  consists of two periods, namely, one during which the phase signal PHASE indicates “1” and the other one during which the phase signal PHASE indicates “0”. The clock generator  122  also generates a clock DCLKddr whose frequency is the same as that of the clock DCLK and outputs the clock DCLKddr to the separator  116 . In accordance with the clock DCLK from the clock generator  122 , the video timing generator  124  generates a vertical synchronizing signal VSYNC, a horizontal synchronizing signal HSYN, and other additional signals that are generally necessary for image display. The destination specifying register  126  is a register for specifying display destinations (display devices  118 ,  120 ) of the image data stored in the respective areas A to D of the graphics memory  114 , and a register value thereof can be set by the host CPU  102  via the bus  112 .  
         [0041]     For example, as shown in  FIG. 4 , the destination specifying register  126  is an 8-bit register having bits Adisp 1 , Adisp 2  corresponding to the area A of the graphics memory  114 , bits Bdisp 1 , Bdisp 2  corresponding to the area B, bits Cdisp 1 , Cdisp 2  corresponding to the area C, and bits Ddisp 1 , Ddisp 2  corresponding to the area D. It outputs bit values thereof to the phase selectors  134   a  to  134   d  as destination signals Adisp 1  and Adisp 2 , destination signals Bdisp 1  and Bdisp 2 , destination signals Cdisp 1  and Cdisp 2 , and destination signals Ddisp 1  and Ddisp 2 , respectively. For example, when the image data in the area A of the graphics memory  114  is to be displayed only on the display device  118 , the bits Adisp 1 , Adisp 2  are set to “1” and “ 0 ” respectively. When the image data in the area A of the graphics memory  114  is to be displayed only on the display unit  120 , the bits Adisp 1 , Adisp 2  are set to “0” and “1” respectively. When the image data in the area A of the graphics memory  114  is to be displayed both on the display devices  118 ,  120 , the bits Adisp 1 , Adisp 2  are both set to “1”. The same relation applies to between the area B of the graphics memory  114  and the bits Bdisp 1 , Bdisp 2  of the destination specifying register  126 , between the area C and the bits Cdisp 1 , Cdisp 2 , and between the area D and the bits Ddisp 1 , Ddisp 2 .  
         [0042]     In  FIG. 2 , the host access circuit  128  is a circuit via which the host CPU  102  accesses the graphics memory  114  and it is mainly used in writing the image data to be displayed on the display devices  118 ,  120  to the graphics memory  114 . The memory read circuits  130   a  to  130   d  read the image data of respective layers (the areas A to D) from the graphics memory  114  via the graphics memory interface  132 , tentatively store the read image data through high-speed burst transfer, and output the stored image data at a timing appropriate for image display.  
         [0043]     For example, as shown in  FIG. 5 , the memory read circuit  130   a  has a head address register  144 , a stride register  146 , an adder  148 , a selector  150 , a raster address register  152 , a pixel address counter  154 , a control circuit  156 , and a FIFO (First In First Out)  158 . The head address register  144  is a register whose register value is set by the host CPU  102  via the bus  112  shown in  FIG. 1 , and it holds a head address of the area A storing the image data to be displayed. The stride register  146  is a register whose register value is set by the host CPU  102  via the bus  112  and it holds a constant value to be added at the time of address calculation of a subsequent raster.  
         [0044]     The adder  148  adds the register value of the stride register  146  and a register value of the raster address register  152  to output the resultant to the selector  150 . The selector  150  selects an output of the head address register  144  when reading the head of the area A, while in other cases, selecting an output of the adder  148  to output it to the raster address register  152 . The raster address register  152  is a register holding a head address of each raster to be displayed and being loaded with the register value of the head address register  144  in synchronization with the vertical synchronizing signal VSYNC outputted from the video timing generator  124  shown in  FIG. 2 . Further, the register value of the stride register  146  is added to that of the raster address register  152  in synchronization with the horizontal synchronizing signal HSYNC outputted from the video timing generator  124  shown in  FIG. 2 .  
         [0045]     The pixel address counter  154  calculates an address of each pixel forming a raster. The pixel address counter  154  loads the head address of the raster from the raster address register  152  in synchronization with the horizontal synchronizing signal HSYNC. Then, the pixel address counter  154  increments a value thereof by one each time. This counter value of the pixel address counter  154  is an address output to be outputted to the graphics memory  114 . The control circuit  156  outputs an access request signal REQ to the graphics memory interface  132  according to the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, and the state of the FIFO  158 , and receives an access acknowledgement signal ACK as a response therefrom. The control circuit  156  outputs an image validity signal PV according to a window signal WIN outputted from the video timing generator  124  and indicating the display timing for images on the display devices  118 ,  120 . The image validity signal PV is activated to “1” from “0” when the image data outputted from the memory read circuit  130   a  is image data to be displayed on the display device  118  or  120 . Further, the control circuit  156  controls the selector  150 , the raster address register  152 , and the pixel address counter  154 .  
         [0046]     The FIFO  158  stores the image data read from the graphics memory  114  in sequence and reads and outputs the image data in the order of the storage. The data read from the graphics memory  114  are transferred in a high-speed burst transfer mode but this transfer is performed only intermittently. Therefore, displaying the read data as they are would result in discontinuous image display. So, the read data are tentatively stored in the FIFO  158  to be outputted at a timing synchronous with the image display. Note that the memory read circuits  130   b  to  130   d  also have the same configuration as that of the memory read circuit  130   a.    
         [0047]     In  FIG. 2 , the graphics memory interface  132  arbitrates access (read or write) requests from the memory read circuits  130   a  to  130   d  and the host access circuit  128 , permitting the requests one by one to have them access to the graphics memory  114 . The phase selectors  134   a  to  134   d  mask the image validity signals PV outputted from the memory read circuits  130   a  to  130   d . The background color register  136  holds codes of background colors to output the codes to the synthesis circuit  138   d . The synthesis circuits  138   a  to  138   d  are connected in cascade. Each of the synthesis circuits  138   a  to  138   d  appropriately synthesizes the image data outputted from a corresponding one of the memory read circuits  130   a  to  130   d  and the image data outputted from a preceding stage (the synthesis circuits  138   b  to  138   d  and the background color register  136 ) to output the resultant image data.  
         [0048]     For example, as shown in  FIG. 6 , the phase selector  134   a  has a selector  160  and an AND circuit  162 . The selector  160  outputs to the AND circuit  162  the destination signal Adisp 1  outputted from the destination specifying register  126  shown in  FIG. 2  when the phase signal PHASE outputted from the clock generator  122  shown in  FIG. 2  indicates “1”. The selector  160  outputs the destination signal Adisp 2  to the AND circuit  162  when the phase signal PHASE indicates “0”. The AND circuit  162  outputs to the synthesis circuit  138   a  the image validity signal PV, which is outputted from the memory read circuit  130   a , as an image validity signal PVM when the output signal of the selector  160  indicates “1”. The AND circuit  162  fixes the image validity signal PVM to “0” to mask the image validity signal PV outputted from the memory read circuit  130   a  when the output signal of the selector  160  indicates “0”. Note that the phase selectors  134   b  to  134   d  also have the same configuration as that of the phase selector  134   a.    
         [0049]     The synthesis circuit  138   a  is constituted of a selector  164 . The selector  164  selects and outputs the image data from the synthesis circuit  138   b  when the image validity signal PVM outputted from the phase selector  134   a  indicates “0”. The selector  164  selects and outputs the image data outputted from the memory read circuit  130   a  when the image validity signal PVM indicates “1”. Note that the synthesis circuits  138   b  to  138   d  also have the same configuration as that of the synthesis circuit  138   a.    
         [0050]      FIG. 7  shows the operation of the phase selector  134   a  and the synthesis circuit  138   a . When the destination signals Adisp 1 , Adisp 2  indicate “1” and “0” respectively (i.e., when the display device  118  is specified as the display destination of the image data outputted from the memory read circuit  130   a ), the phase selector  134   a  fixes the image validity signal PVM to “0” to mask the image validity signal PV outputted from the memory read circuit  130   a  during a period in which the phase signal PHASE indicates “0”. When, on the other hand, the phase signal PHASE indicates “1”, the image validity signal PV is not masked. Therefore, only when the phase signal PHASE indicates “1”, the image validity signal PVM is at “1” and the synthesis circuit  138   a  outputs the image data outputted from the memory read circuit  130   a  as synthesized image data DATA.  
         [0051]     When the destination signals Adisp 1 , Adisp 2  indicate “0” and “1” respectively (i.e., when the display device  120  is specified as the display destination of the image data outputted from the memory read circuit  130   a ), the phase selector  134   a  fixes the image validity signal PVM to “0” to mask the image validity signal PV outputted from the memory read circuit  130   a  during a period in which the phase signal PHASE indicates “1”. When, on the other hand, the phase signal PHASE indicates “0”, the image validity signal PV is not masked. Therefore, only when the phase signal PHASE indicates “0”, the image validity signal PVM is at “1” and the synthesis circuit  138   a  outputs the image data outputted from the memory read circuit  130   a  as the synthesized image data DATA.  
         [0052]     When the destination signals Adisp 1 , Adisp 2  both indicate “1” (i.e., the display devices  118 ,  120  are both specified as the display destinations of the image data outputted from the memory read circuit  130   a ), the phase selector  134   a  does not mask the image validity signal PV outputted from the memory read circuit  130   a  but outputs it as the image validity signal PVM. Therefore, irrespective of a signal value of the phase signal PHASE, the image validity signal PVM has “1” and the synthesis circuit  138   a  outputs the image data outputted from the memory read circuit  130   a  as the synthesized image data DATA.  
         [0053]     In  FIG. 2 , the separator  116  has output registers  140 ,  142 . The output register  140  accepts the image data outputted from the synthesis circuit  138   a  of the graphics LSI  110 , in synchronization with rising edges of the clock DCLKddr outputted from the clock generator  122  and outputs it to the display device  118 . The output register  142  accepts the image data outputted from the synthesis circuit  138   a , in synchronization with falling edges of the clock DCLKddr outputted from the clock generator  122  and outputs it to the display device  120 .  
         [0054]      FIG. 8  shows the operation of the separator  116 . The output register  140  accepts the image data DATA outputted from the synthesis circuit  138   a , in synchronization with the rising edges of the clock DCLKddr. Therefore, the output register  140  accepts in sequence the image data DATA that is outputted from the synthesis circuit  138   a  when the phase signal PHASE indicates “1”, namely, the image data DATA of data values X 1  to X 3 , and then outputs it to the display device  118 . The output register  142  accepts the image data DATA outputted from the synthesis circuit  138   a , in synchronization with the falling edges of the clock DCLKddr. Therefore, the output register  142  accepts in sequence the synthesized image data DATA that is outputted from the synthesis circuit  138   a  when the phase signal PHASE indicates “0”, namely, the image DATA of data values Y 1  to Y 3 , and outputs it to the display device  120 .  
         [0055]     FIGS.  9 ( a ), ( b ) show examples of image display on the image display system  100  in  FIG. 1 . The examples show images when the destination register  126  sets the bits Adisp 1 , Adisp 2  corresponding to the area A of the graphics memory  114  to “0” and “1” respectively, the bits Bdisp 1 , Bdisp 2  corresponding to the area B to “0” and “1” respectively, the bits Cdisp 1 , Cdisp 2  corresponding to the area C to “1” and “0” respectively, and the bits Ddisp 1 , Ddisp 2  corresponding to the area D to “1” and “0” respectively. In other words, the image data in the areas A, B shown in FIGS.  3 ( a ), ( b ) are displayed only on the display device  120  and the image data in the areas C, D shown in FIGS.  3 ( c ), ( d ) are displayed only on the display device  118 .  
         [0056]     For such image display, the image data in the area A of the graphics memory  114  is supplied to the synthesis circuit  138   a  via the memory read circuit  130   a  and the phase selector  134   a  as indicated by the heavy line arrows in  FIG. 10 . The image data in the area B of the graphics memory  114  is supplied to the synthesis circuit  138   b  via the memory read circuit  130   b  and the phase selector  134   b . Then, when the phase signal PHASE outputted from the clock generator  122  indicates “0”, the image data in the areas A, B of the graphics memory  114  are synthesized by the synthesis circuits  138   a ,  138   b  and accepted by the output register  142  of the separator  116  for output to the display device  120 .  
         [0057]     Further, as indicated by the heavy line arrows in  FIG. 11 , the image data in the area C of the graphics memory  114  is supplied to the synthesis circuit  138   c  via the memory read circuit  130   c  and the phase selector  134   c . The image data in the area D of the graphics memory  114  is supplied to the synthesis circuit  138   d  via the memory read circuit  130   d  and the phase selector  134   d . Then, when the phase signal PHASE indicates “1”, the image data in the areas C, D of the graphics memory  114  are synthesized by the synthesis circuits  138   c ,  138   d  and accepted by the output register  140  of the separator  116  for output to the display device  118 .  
         [0058]     FIGS.  12 ( a ), ( b ) show other examples of image display on the image display system  100  in  FIG. 1 . The examples show images when the destination register  126  sets the bits Adisp 1 , Adisp 2  corresponding to the area A of the graphics memory  114  to “0” and “1” respectively, the bits Bdisp 1 , Bdisp 2  corresponding to the area B to “0” and “1” respectively, the bits Cdisp 1 , Cdisp 2  corresponding to the area C to “1” and “0” respectively, and the bits Ddisp 1 , Ddisp 2  corresponding to the area D to “1” and “1” respectively. In other words, the image data in the areas A, B shown in FIGS.  3 ( a ), ( b ) are displayed only on the display device  120 , the image data in the area C shown in  FIG. 3 ( c ) is displayed only on the display device  118 , and the image data in the area D shown in  FIG. 3 ( d ) is displayed both on the display devices  118 ,  120 .  
         [0059]     For such image display, the image data in the area A of the graphics memory  114  is supplied to the synthesis circuit  138   a  via the memory read circuit  130   a  and the phase selector  134   a  as indicated by the heavy line arrows in  FIG. 13 . The image data in the area B of the graphics memory  114  is supplied to the synthesis circuit  138   b  via the memory read circuit  130   b  and the phase selector  134   b . The image data in the area D of the graphics memory  114  is supplied to the synthesis circuit  138   d  via the memory read circuit  130   d  and the phase selector  134   d . Then, when the phase signal PHASE outputted from the clock generator  122  indicates “0”, the image data in the areas A, B, D of the graphics memory  114  are synthesized by the synthesis circuits  138   a ,  138   b ,  138   d  and accepted by the output register  142  of the separator  116  for output to the display device  120 . Further, similarly to the data flow ( FIG. 11 ) corresponding to the examples of image display in FIGS.  9 ( a ), ( b ), the image data in the area C of the graphics memory  114  is supplied to the synthesis circuit  138   c  via the memory read circuit  130   c  and the phase selector  134   c . Then, when the phase signal PHASE indicates “1”, the image data in the areas C, D of the graphics memory  114  are synthesized by the synthesis circuits  138   c ,  138   d  and accepted by the output register  140  of the separator  116  for output to the display device  118 .  
         [0060]     In the image display system  100  as configured above, the image data to be displayed on the display device  118  and the image data to be displayed on the display device  120  are separately multiplexed in each display period for one pixel on the display devices  118 ,  120  by synthesizing, for each level of the phase signal PHASE, the image data from the memory read circuits  130   a  to  130   d  in accordance with the setting of the destination specifying register  126 . Therefore, the image display system  100  need not include two sets of the circuit for image data read from the graphics memory  114 , the circuit for synthesizing the read image data (graphics LSIs), and the graphics memories  114 , in association with the two display devices  118 ,  120 . As a result, the display devices  118 ,  120  can display thereon different images without any increase in the scale of the image display system  100 . This results in the reduction in manufacturing cost of the image display system  100 .  
         [0061]     Further, the image data to be displayed on each of the display devices  118 ,  120  are separately outputted for each level of the phase signal PHASE within the display period for one pixel on the display devices  118 ,  120 , so that it is easy to separate the image data outputted from the synthesis circuit  138   a  for display on each of the display devices  118 ,  120 . Moreover, it is able to output the image data to be displayed on each of the display devices  18 ,  120  without any increase in the number of output terminals for the image data because the graphics LSI  110  multiplexes the image data. This consequently contributes to the reduction in the manufacturing cost of the image display system  100 .  
         [0062]     On the contrary, in case of displaying different images on the display devices  118 ,  120  in the conventional image processing device (graphics LSI), two sets of graphics LSIs  510 - 1 ,  510 - 2  and graphics memories  114 - 1 ,  114 - 2  are needed for the display devices  118 ,  120 , as shown in  FIG. 14 . This greatly increases the scale of an image display system  500  as well as the manufacturing cost thereof.  
         [0063]     According to the first embodiment as described above, it is able to display different images on the display devices  118 ,  120  without any increase in system scale of the image display system  100 , thereby reducing the manufacturing cost of the image display system  100 . In addition, the image data outputted from the synthesis circuit  138   a  can be easily separated for display on each of the display devices  118 ,  120 . Further, the graphics LSI  110  can output image data to be displayed on each of the display devices  118 ,  120  without any increase in the number of output terminals for image data. This can contribute to the reduction in the manufacturing cost of the image display system  100 .  
         [0064]      FIG. 15  shows a second embodiment of the present invention. In the description of the second embodiment, the same reference numerals and symbols are used to designate the same elements as the elements described in the first embodiment and the detailed description thereof will not be given. An image display system  200  is constituted of the image display system  100  ( FIG. 1 ) of the first embodiment plus a video source  202  (video image supply unit). It has a graphics LSI  210  in place of the graphics LSI  110  of the first embodiment. The video source  202  sequentially outputs to the graphics LSI  210  image data to form a video image such as a DVD playback image.  
         [0065]      FIG. 16  shows the graphics LSI  210  and a separator  116  in  FIG. 15 . The graphics LSI  210  is constituted of the graphics LSI  110  ( FIG. 2 ) of the first embodiment plus a memory write circuit  204  (write unit). The memory write circuit  204  continuously writes to the graphics LSI  114  (for example, an area B) the image data sequentially outputted from the video source  202 .  
         [0066]      FIG. 17  shows the memory write circuit  204  in  FIG. 16 . The memory write circuit  204  is the same as the memory read circuits  130   a  to  130   d  except that it has a control circuit  256  in place of the control circuit  156  ( FIG. 5 ) of the first embodiment. The control circuit  256  outputs an access request signal REQ to a graphics memory interface  132  according to a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC outputted from the video source  202  shown in  FIG. 15 , and to the state of a FIFO  158 . It receives an access acknowledgement signal ACK as a response therefrom. Further, the control circuit  256  controls a selector  150 , a raster address register  152 , and a pixel address counter  154  similarly to the control circuit  156  of the first embodiment. The memory write circuit  204  continuously writes to the graphics memory  114  the image data sequentially outputted from the video source  202 , so that the video images can be displayed on the display devices  118 ,  120 .  
         [0067]     In the second embodiment described above, the same effects as those of the first embodiment are also obtainable. In addition, when it is applied to, for example, a car navigation system having the display device  118  on a driver&#39;s seat side of a car and the display device  120  on a rear seat side, it is possible to display images relating to route guidance on the display device  118  on the driver&#39;s seat side and display video images such as DVD playback images and images received from television broadcast on the display device  120  on the rear seat side.  
         [0068]     The first and second embodiments have described, as a way of example, the destination register  126  constituted of 8 bits (Adisp 1 , Adisp 2 , Bdisp 1 , Bdisp 2 , Cdisp 1 , Cdisp 2 , Ddisp 1 , Ddisp 2 ). However, the present invention is not limited thereto. For example, when image data stored in the graphics memory  114  need not be displayed on both of the display devices  118 ,  120 , a destination specifying register  127  may be provided only with 4 bits (Adisp 1 , Bdisp 1 , Cdisp 1 , Ddisp 1 ) as in shown in  FIG. 18 , outputting their respective bit values as destination signals Adisp 1 , Bdisp 1 , Cdisp 1 , Ddisp 1 , or outputting them as destination signals Adisp 2 , Bdisp 2 , Cdisp 2 , Ddisp 2  via inverters AI, BI, CI, DI respectively. Structuring a register as above makes it possible to halve the number of bits compared with that in the destination specifying register  126 , enabling the reduction in the circuit scale of the destination specifying register.  
         [0069]     The first and second embodiments have described the examples in which the present invention is applied to an image display system having two display devices. However, the present invention is not limited thereto. For example, the present invention may be applied to an image display system having three or more display devices.  
         [0070]     The first and second embodiments have also described the examples in which the graphics LSI and the separator are formed independently. However, the present invention is not limited thereto. For example, a graphics LSI and a separator may be formed as one chip.  
         [0071]     The invention is not limited to the above embodiments and various modifications may be made without departing from the spirit and scope of the invention. Any improvement may be made in part or all of the components.

Technology Category: 3