Patent Document

This application No. is a division of prior application Ser. No. 08/758,852, filed Dec. 2, 1996, now U.S. Pat. No. 6,008,544 filed Dec. 28, 1999 which is a continuation of application Ser. No. 08/524,149, filed Aug. 17, 1995, abandoned, which is a continuation of application Ser. No. 08/162,259, filed Dec. 7, 1993, abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and its manufacturing method, particularly to a semiconductor device comprising an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on a source/drain region (hereinafter refered to as S/D region) adjacent to a gate electrode. 
     2. Description of the Prior Art 
     A higher integration level has been requested for a semiconductor memory in recent years, therefore, it is necessary to further fine a pattern. As one of the means for realizing a higher integration level, an insulated-gate field effect transistor is further fined which serves as a component of the semiconductor memory. 
     FIG. 1A to FIG. 1F are sectional views for explaining a method for manufacturing an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on an S/D region of both sides of a gate electrode. The insulated-gate field effect transistor uses an insulated-gate field effect transistor having a floating gate in an EPROM cell. 
     FIG. 1A shows a state after a floating gate and a control gate are formed and moreover a S/D region is formed in a surface layer of a semiconductor substrate of both sides of the control gate. 
     In FIG. 1A, symbol  1  is a semiconductor substrate,  2  is a gate insulating film on the semiconductor substrate  1 ,  3   a  is a floating gate on the gate insulating film  2 ,  3   c  is a control gate formed above the floating gate  3   a  through an insulating film  3   b ,  4  is an insulating film on the control gate  3   c , and  5   a  and  5   b  are S/D regions formed in the surface layer of the semiconductor substrate  1  of both sides of the control gate  3   c.    
     Under the above state, as shown in FIG. 1B, an insulating film  6  is formed by covering the gate insulating film  2 , floating gate  3   a , insulating film  3   b , and control gate  3   c  in order to form a side wall. 
     Then, as shown in FIG. 1C, an insulating side wall  6   a  is formed on the side surface of the gate electrode  3  by anisotropically etching the insulating film  6 . 
     Then, as shown in FIG. 1D, an inter-layer insulating film  7  is formed on the entire surface. 
     Then, as shown in FIG. 1E, the inter-layer insulating film  7  on the S/D region  5   a  is selectively etched and removed to form a contact hole  7   a  in the inter-layer insulating film  7  on the S/D region  5   a.    
     Then, as shown in FIG. 1F, a conducting film is formed and thereafter patterned to form a source/drain electrode (hereinafter refered to as S/D electrode) or interconnection layer  8  which connects with the S/D region  5   a  through the contact hole  7   a.    
     For the above existing method for fabricating a semiconductor device, however, it is necessary to decrease the size of the S/D regions  5   a  and  5   b  and bring the contact hole  7   a  as closely to the gate electrode  3  as possible in order to integrate elements at a high density. For this reason, in the case that a deviation of an alignment occurs when patterning a contact hole, the contact hole  7   a  may be formed by etching the side wall  6   a  as shown in FIG.  2 . 
     Therefore, when an S/D electrode or interconnection layer is formed in the contact hole  7   a,  the thickness of an insulating film between the gate electrode  3  and the S/D electrode or interconnection layer fluctuates. For this reason, a problem occurs that parasitic capacitance fluctuates or accumulated electric charges fluctuate due to leakage of them. 
     Besides, an existing example is shown in a patent document of the Japanese unexamined publication (KOKAI) 3-96271. In this case, the same problem as described above might occur, too. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an insulated-gate field effect transistor for securing the uniformity of the thickness of an insulating film put between the side surface of a gate electrode and an S/D electrode or interconnection layer while integrating elements at a high density and its manufacturing method. 
     The insulated-gate field effect transistor according to the present invention has a conducting side wall covering an insulating side wall of a gate electrode of the side where a contact hole is formed and contacting an S/D region. 
     Therefore, even if a deviation of an alignment occurs and the contact hole to the S/D region approaches the gate electrode, it is brought onto the conducting side wall. Thus, when an S/D electrode is formed in the contact hole, only the insulating side wall remains as an insulating film actually put between the S/D electrode and gate electrode because the S/D electrode contacts the conducting side wall. Therefore, its thickness becomes constant independently of the position of the contact hole. 
     Moreover, in case that the contact hole goes away from the gate electrode, the conducting side wall is covered with a covering insulating film and the S/D electrode formed in the contact hole does not contact the conducting side wall. Even in this case, as both the conducting side wall and S/D electrode contact the S/D region, the conducting side wall and the S/D electrode have the same potential, so that only the insulating side wall remains as an insulating film actually present between the S/D electrode and gate electrode. Thereby, its thickness becomes constant independently of the position of the contact hole. 
     Furthermore, when forming by introducing impurities a bulk interconnection layer in the semiconductor layer of a side where no contact hole is formed, the second conducting side wall is left at the side where no contact hole is formed and serves as a mask for etching a natural oxide film and introducing impurities while the semiconductor layer is masked at the side where a contact hole is formed. 
     Thus, the allowance for mask alignment increases and the mask is easily formed. Moreover, a sufficient distance between a channel region under the gate electrode and a bulk interconnection layer is secured so that preventing a channel length from becoming short and a gate control voltage from fluctuating. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1A to FIG. 1F are sectional views for explaining a method for manufacturing a semiconductor device according to the prior art; 
     FIG. 2 is a sectional view for explaining a problem of the prior art; 
     FIG. 3A to FIG. 3H are sectional views for explaining a method for manufacturing the insulated-gate field effect transistor of an embodiment of the present invention having a contact hole formed in an inter-layer insulating film on an S/D region of the both sides of a gate electrode; 
     FIG. 4A to FIG. 4D are top views for explaining a method for manufacturing the insulated-gate field effect transistor of the embodiment of the present invention having a contact hole formed in an inter-layer insulating film on an S/D region of both sides of a gate electrode, sectional views taken along the lines A—A in FIG.  4 A and FIG. 4D correspond to FIG.  3 A and FIG. 3E respectively and sectional view taken along the lines B—B in FIG. 4D corresponds to FIG. 4E; 
     FIG. 5 is a circuit block diagram including the insulated-gate field effect transistor of the embodiment of the present invention shown in FIG. 3H; and 
     FIG. 6 is a sectional view for explaining the function and advantage of the insulated-gate field effect transistor of the embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The insulated-gate field effect transistor of the embodiment of the present invention having a contact hole formed in an inter-layer insulating film on an S/D region adjacent to a gate electrode is described below by referring to FIG. 3A to FIG. 3H, FIG. 4A to FIG. 4E, FIG.  5  and FIG.  6 . The insulated-gate field effect transistor uses an insulated-gate field effect transistor having a floating gate in an EPROM cell. 
     FIG. 3A shows a state after an S/D region is formed in the surface layer of a semiconductor substrate of the both sides of a gate electrode having a floating gate and control gate. 
     In FIG. 3A, symbol  11  is a semiconductor substrate made of silicon and  12  is a gate insulating film made of a silicon dioxide film formed on the semiconductor substrate  11 . 
     Symbol  13  is a gate electrode, comprising a floating gate  13   a  and control gate  13   c  formed above a floating  13   a  in the state of putting an insulating film  13   b  between them. The floating gate  13   a  and control gate  13   c  are made of polycrystalline silicon and the insulating film  13   b  is made of a silicon dioxide film. 
     Symbol  14  is an insulating film on the control gate  13   c.    15   a  and  15   b  are S/D regions formed in the surface layer of the semiconductor substrate  11  of both sides of the gate electrode  13 . 
     A plurality of insulated-gate field effect transistors are formed in an EPROM. Therefore, as shown in FIG. 4A, floating gates  13   a ,  13   d,    13   e,    13   g,    13   h,  and  13   j  are formed separately from each other for each insulated-gate field effect transistor. The floating gates  13   a  and  13   d  are covered with a strip-shaped control gate  13   c  common to them, the floating gates  13   e  and  13   g  are covered with a strip-shaped control gate  13   f  common to them and the floating gates  13   h  and  13   j  are covered with a strip-shaped control gate  13   i  common to them. The control gates  13   c ,  13   f , and  13   i  are arranged in parallel at predetermined intervals and connected to a word line. 
     Moreover, S/D regions  15   a  to  15   d  are formed in the surface layer of the semiconductor substrate  11  between the control gates  13   c ,  13   f  and  13   i  and at that of both sides of the floating gates  13   a ,  13   d ,  13   e ,  13   g ,  13   h  and  13   j . However, the S/D region of another side of the floating gates  13   e ,  13   g ,  13   h , and  13   j  is not illustrated. In this case, a region between the control gates  13   c  and  13   f  is called such a side that a contact hole is formed where a contact hole is formed on the S/D regions  15   a  and  15   c , while a region between the control gates  13   c  and  13   i  is called such an other side that a contact hole is not formed where a bulk interconnection layer for electrically connecting the S/D regions  15   b  and  15   d  with each other is formed in the surface layer of the semiconductor substrate  11 . 
     The S/D region  15   a  serves as a source or drain region common to adjacent insulated-gate field effect transistors having the floating gates  3   a  and  13   e.    
     The S/D region  15   b  serves as a drain or source region common to adjacent insulated-gate field effect transistors having the floating gates  3   a  and  13   h.    
     The S/D region  15   c  serves as a source or drain region common to adjacent insulated-gate field effect transistors having the floating gates  13   d  and  13   g.    
     The S/D region  15   d  serves as a drain or source region common to adjacent insulated-gate field effect transistors having the floating gates  13   d  and  13   j.    
     First, to form insulating side walls  16   a  to  16   d  along the side surfaces of the control gates  13   c ,  13   f , and  13   i  shown in FIG. 4A under the above state, an insulating film  16  made of a silicon dioxide film with the thickness of 3,000-4,000 Å on the entire surface of the semiconductor substrate  11 . FIG. 3B shows a sectional view of the film  16  taken along the line A—A in FIG.  4 A. 
     Then, as shown in FIG. 3C, the insulating side wall  16   a  is formed on the side surface of the gate electrode  13  by anisotropically etching the insulating film  16  by means of the reactive ion etching (hereinafter referred to as RIE) using a fluorine-based gas such as HF. In this case, as shown in FIG. 4B, the insulating side walls  16   a  to  16   d  are formed along the side surfaces of the control gates  13   c , . 13   f , and  13   i.    
     Next, as shown in FIG. 3D, a polycrystalline silicon film (conducting film)  17  is formed on the entire surface and thereafter the polycrystalline silicon film  17  is anisotropically etched by RIE using a chlorine-base gas. Thereby, as shown in FIG. 4B, polycrystalline silicon films (conducting side walls)  17   a  to  17   d  respectively covering the side surfaces of the insulating side walls  16   a  to  16   d  and respectively contacting the semiconductor substrate  11  are left. 
     Subsequently, a resist film is formed and thereafter a window  20  of the resist film is patterned so that the conducting side walls  17   a  and  17   c  in a region between the S/D regions  15   a  and  15   c  of the side for forming a contact hole are exposed. Next, as shown in FIG. 4C, the conducting side walls  17   a  and  17   c  are selectively etched through the window  20  and partly removed. Thereby, the conducting side walls  17   a  and  17   c  are electrically separated for each transistor so that the conducting side walls  17   e  and  17   f  contacting the S/D region  15   a  and the side walls  17   g  and  17   h  contacting the S/D region  15   c  are left. 
     Then, after the resist film is removed, as shown in FIG. 4D, the side for forming a contact hole is masked with a not-illustrated new resist film to remove a natural oxide film from the surface of the semiconductor substrate  11  of the other side. Subsequently, conductivity-type impurities same as those in the S/D regions  15   b  and  15   d  are introduced into the region to form a bulk interconnection layer in the surface layer of the semiconductor substrate  11  and electrically connect the S/D regions  15   b  and  15   d  of the other side each other. In this case, the conducting side walls  17   b  and  17   d  serve as masks for removing a natural oxide film and introducing impurities. Moreover, the bulk interconnection layer serves as a source line  21 . FIG. 3E shows a sectional view taken along the line A—A in FIG.  4 D and FIG. 4E shows a sectional view taken along the line B—B in FIG.  4 D. 
     After that, as shown in FIG. 3F, an inter-layer insulating film  18  is formed on the entire surface. 
     Then, as shown in FIG. 3G, the inter-layer insulating film  18  on the S/D region  15   a  is selectively etched and removed by a fluorine-base etching gas to form a contact hole  18   a  in the inter-layer insulating film  18  on the S/D region  15   a . In this case, a contact hole  18   b  is also formed on the S/D region  15   c  shown in FIG. 4D at the same time. 
     Next, as shown in FIG. 3H, an aluminum film is formed and thereafter patterned to form an S/D electrode or interconnection layer  19  connecting with the S/D regions  15   a  and  15   c  through the contact holes  18   a  and  18   b . In this case, an S/D electrode or interconnection layer connecting with the S/D region  15   c  through the contact hole  18   b  shown in FIG. 4C is formed at the same time. 
     Then, an EPROM having the connection shown in FIG. 5 is completed after predetermined steps. In FIG. 5, symbol  21  is a source line where sources of a desired transistor are connected each other and connected to a power-supply line Vs. Symbol  22  is a word line which is connected with the control gate electrode  13   c . Symbol  23  is a bit line which is connected with the drain of each transistor. Symbol  24  is a row decoder for sending an address signal to the control gate  13   c  of a desired transistor through each word line  22  and  25  is a column decoder for sending an address signal to the drain of a desired transistor through each bit line  23 . 
     As described above, the embodiment of the present invention has the conducting side wall  17   e  covering the insulating side wall  16   a  of the side where the contact hole  18   a  is formed and also contacting with the S/D region  15   a.    
     Therefore, when forming the contact hole  18   a  in the inter-layer insulating film  18  covering them, the contact hole  18   a  is formed on the conducting side wall  17   e  even if the contact hole  18   a  approaches the gate electrode  13  due to a deviation of an alignment as shown in FIG.  6 . In this case, the insulating side wall  16   a  between the gate electrode  13  and conducting side wall  17   e  is not exposed to an etchant for forming the contact hole  18   a  in the inter-layer insulating film  18  because the insulating side wall  16   a  is covered with the conducting side wall  17   e . Therefore, the insulating side wall  16   a  keeps the initial thickness. When the S/D electrode or interconnection layer  19  is formed in the contact hole  18   a  under the above state, only the insulating side wall  16   a  remains as an insulating film actually present between the S/D electrode or interconnection layer  19  and the gate electrode  13  because the S/D electrode or interconnection layer  19  contacts the conducting side wall  17   e.    
     Accordingly, its thickness is kept constant independently of the position of the contact hole. 
     In case that the contact hole  18   a  goes away from the gate electrode, the conducting side wall  17   e  is covered with the inter-layer insulating film  18   a  and the S/D electrode or interconnection layer  19  formed in the contact hole  18   b  does not contact the conducting side wall  17   e  as shown in FIG.  3 E. Even in this case, as both the conducting side wall  17   e  and S/D electrode or interconnection layer  19  contact the S/D region, the conducting side wall  17   e  and the S/D electrode or interconnection layer  19  have the same potential, so that only the insulating side wall  16   a  remains as an insulating film actually present between the S/D electrode or interconnection layer  19  and the gate electrode  13 . 
     Accordingly, its thickness is kept constant independently of the position of the contact hole as shown in FIG.  3 H. 
     Therefore, it is possible to prevent parasitic capacitances from fluctuating or accumulated charges from fluctuating due to leakage of them. 
     Moreover, when forming the source line  21  by selectively introducing conductivity-type impurities same as those of the S/D regions  15   b  and  15   d  into the semiconductor substrate  11  of the other side that a contact hole is not formed, as shown in FIG.  4 D and FIG. 4E, the conducting side wall  17   b  on the side surface of the control gate  13   c  is left at the other side and serves as a mask for removing a natural oxide film and introducing impurities while the semiconductor substrate  11  is masked with a not-illustrated new resist film of the side for forming a contact hole. 
     Thus, the allowance for mask alignment increases by the width of the polycrystalline silicon film  17   b  so that a patterning of a mask is easy. Moreover, a sufficient space between a channel region under the gate electrode and a bulk interconnection layer is secured so that preventing a channel length from becoming short and a gate control voltage from fluctuating. 
     For this embodiment, the polycrystalline silicon film  17  is used for the material of the conducting side wall. However, it is also possible to use other type of conducting side wall such as a refractory metal film or refractory metal silicide film. 
     As shown in FIG. 3A, the present invention is applied to an insulated-gate field effect transistor having the gate electrode  13  which comprises the floating gate  3   a  and control gate  13   c  above the floating gate  3   a . However, the present invention can also be applied to an insulated-gate field effect transistor having a gate electrode which comprises only one layer. 
     Moreover, it is possible to replace the step of patterning the polycrystalline silicon film  17   a  shown in FIG. 4C with the step of introducing conductivity-type impurities into the semiconductor substrate  11  shown in FIG.  4 D.

Technology Category: 5