Patent Document

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0001]    N/A 
       CROSS REFERENCE TO RELATED APPLICATION 
       [0002]    N/A 
       BACKGROUND OF THE INVENTION 
       [0003]    The present invention relates to dynamic motor braking systems working to control the speed of an electric motor by dissipating energy generated by the motor, and in particular to a braking system using a hybrid control strategy that offers greater braking capacity and improved operation of motor drives when connected in tandem. 
         [0004]    Motor drives control the frequency and amplitude of the electrical power applied to an electrical motor to improve motor operation, for example, by improving motor starting and stopping, motor speed and torque control, motor synchronization, load management, and energy efficiency. For this purpose, the motor drive will typically receive three-phase line power and rectify it to produce a DC bus voltage. The DC bus voltage is then received by a set of switching semiconductor devices, typically operating in a class D or switching mode, to synthesize multiphase AC electrical power from the DC bus voltage. The frequency and amplitude of the synthesized power is controlled by controlling the switching of the semiconductor devices. 
         [0005]    When a control electrical motor must be slowed, for example against an attached inertial load, the motor may generate (termed “regeneration”) electrical power that appears on the DC bus as an increased DC voltage. This voltage is reduced by a resistor (termed a dynamic braking resistor) shunting the DC bus to dissipate the excess power on the DC bus. Typically this dynamic braking resistor is connected across the DC bus by a solid-state switching device so that it can be removed when braking is not required. 
         [0006]    Two principal techniques may be used for controlling the dynamic braking resistor in order to regulate the DC bus voltage. The first technique, termed the “hysteretic control”, connects the resistor across the DC bus when the voltage on the DC bus rises above a first predetermined limit and disconnects the resistor from the DC bus when the voltage drops below a second predetermined limit. The difference between the first and second predetermined limits provides a degree of hysteresis preventing excessive switching when the DC voltage is near a limit. 
         [0007]    While hysteretic control is simple, it has several drawbacks. First, the regulation of the DC bus voltage is rather coarse producing a voltage “ripple” that can decrease the effectiveness of the motor drive and increase power dissipation and undesired mechanical vibration. Second, often it is desired to connect the DC buses of several motor drives together (termed shared bus or common bus for DC supply configurations) for improved load sharing. When hysteretic control is used, minor differences in the switching limits of the controls will inevitably result in one dynamic braking resistor turning on at a slightly lower level than the other dynamic braking resistor and thus carrying the full burden of regulation. This unequal load sharing eventually reduces the total braking capacity of the connected drives and can result in significant circulating currents between drives. 
         [0008]    One solution to these problems of hysteretic control is the use of “pulse width modulated” or PWM control. Under PWM control, the dynamic braking resistor is connected and disconnected across the DC bus at a high switching rate whose “duty cycle” (the relative proportion of time that the resistor is operating in a shunting capacity) depends on the voltage of the DC bus. As the voltage on the DC bus rises, the duty cycle of the dynamic braking resistor increases drawing more power from the DC bus. 
         [0009]    The high switching rate of the dynamic braking resistor in PWM control substantially reduces the ripple in the regulation of the DC bus voltage. Further, because the duty cycle is proportional to the excess voltage (rather than onloff), small differences in the control of the dynamic braking resistor do not result in one dynamic braking resistor carrying the full burden of the regulation and any circulating currents are reduced. 
         [0010]    Unfortunately, these advantages to PWM control come at an expense. The high switching rate of the solid-state switching device controlling the dynamic braking resistor, necessary to reduce the ripple of the DC bus voltage, increases the power dissipation of the solid-state switching device. This requires that the solid-state switching device be “de-rated”, limiting the maximum amount of braking energy that can be dissipated before the rating of the solid-state switching device is exceeded. 
       SUMMARY OF THE INVENTION 
       [0011]    The present inventors have recognized that the advantages of PWM control can be obtained without the need to de-rate the solid-state switching device by employing a hybrid control strategy that uses PWM control up to a certain DC bus voltage and then switching to hysteretic control. By moving to hysteretic control, the power handling capacity of the solid-state switching device is effectively increased at the point where greatest power handling is required. Further, because the hysteresis takes place only at high DC bus voltages (essentially switching between two high voltage values) the amount of ripple voltage during the hysteretic control is far less than that obtained with a pure hysteretic control system. Switching to hysteretic control via pulse dropping lowers the switching frequency with only a small increase in bus voltage ripple. 
         [0012]    Specifically then, the present invention provides a dynamic braking controller for a motor drive, the motor drive using a voltage on a DC bus and the DC bus communicating with an inverter providing controlled power to an electric motor. The invention includes a series connected resistor and solid-state switching device, the two shunting the DC bus. A control circuit controls the solid-state switching device so that for larger energy dissipation, the solid-state switching device is controlled in a hysteretic mode in which the solid-state switching element is turned fully on for DC bus voltages only above a predetermined threshold. For smaller energy dissipation, the control circuit controls the solid-state switching element in a pulse width modulation mode wherein the solid-state switching element is repeatedly switched on and off with an on-time being a function of DC bus voltage. 
         [0013]    It is thus one object of the invention to tailor the control of the dynamic braking according to the amount of energy that must be dissipated. For high energies that may tax the solid-state switching element, a more efficient hysteresis mode is used, while for lower energies better regulation and improved tandem operation are obtained using pulse width modulation. 
         [0014]    The pulse width modulation mode may provide a substantially continuous control of pulse width as a function of DC bus voltage and the hysteresis mode may provide a discontinuous function of pulse width as a function of DC bus voltage. In the pulse width modulation mode, the pulse width modulation need not be controlled by a proportional controller (accepting an input of bus voltage) but any control strategy may be used, for example, a proportional, integral, derivative control strategy. 
         [0015]    It is thus another object of the invention to provide improved voltage regulation with PWM control within the power dissipation limits of the solid-state switching device, while still providing a large range of control available with hysteretic control. 
         [0016]    The control circuit may control the solid-state switching device in a first mode below a threshold DC bus voltage by switching the solid-state switching device at a first average rate to control the average on-time of the solid-state switching device, and in a second mode above the threshold DC bus voltage by switching the solid-state switching device at a second average rate less than the first average rate to control the average on-time of the solid-state switching device to be greater than the average on-time in the first mode. 
         [0017]    It is thus another object of the invention to reduce switching losses in the solid-state switching devices, as greater power dissipation must be achieved. By reducing switching losses, a larger switching device current may be achieved with the same junction temperature, leading to a larger current applied to the dynamic braking resistor. Thus, although the power dissipated in the solid-state switches is reduced, the total power dissipated in the braking resistor is increased by a much greater amount. 
         [0018]    In the first mode, the control circuit may provide pulse width modulation of the solid-state switching device as a continuous function of DC bus voltage up to a maximum duty cycle and in the second mode may alternate between holding the solid-state switching device in an on-state and switching the solid-state switching device at the maximum duty cycle, in effect, pulse dropping as the maximum duty cycle is exceeded. 
         [0019]    It is thus an object of the invention to reduce the ripple voltage that occurs in a hysteresis mode by switching not between on and off but between on and a switched on/off state. 
         [0020]    The first average rate may be greater than 1 kHz and the second average rate may be less than 1 kHz. For example, the first average rate may be substantially 2 kHz and the second average rate may be substantially in a range of 50 to 200 Hz. The importance is the substantial difference between the two frequencies. 
         [0021]    Thus it is an object of the invention to provide for significant differences in switching frequency and thus in switching loss in the two control modes. 
         [0022]    The control circuit may switch the solid-state switching device off in a third mode at a second DC bus voltage less than the threshold DC bus voltage. 
         [0023]    Thus it is an object of the invention to provide a mode having no switching losses when dynamic braking does not occur. 
         [0024]    The maximum duty cycle of the pulse width modulation mode may be substantially 0.8-0.9. 
         [0025]    It is thus an object of the invention to switch away from PWM mode when switching losses will be significant because of high current draw. 
         [0026]    The invention may further include a second (or more) motor drive(s) having a second DC bus communicating with a second inverter providing control power to a second electric motor where the first and second DC buses are electrically interconnected for power-sharing. The second motor drive may further include a second dynamic braking controller having a second series connected resistor and second solid-state switching device shunting the second DC bus. Both of the solid-state switching devices may be operated to: 
         [0027]    (a) control the solid-state switching devices in a hysteresis mode wherein the solid-state switching elements are turned on for DC bus voltages above the predetermined threshold; and 
         [0028]    (b) control the solid-state switching devices in a pulse width modulation mode wherein the solid-state switching elements are repeatedly switched on and off with an on-time being a function of DC bus voltage for DC bus voltages below the predetermined threshold. 
         [0029]    It is thus another object of the invention to provide a dynamic braking system that works well with tandem connected motor drives or drive systems where a common converter supplies a DC bus to a system of two or more drives. 
         [0030]    These particular features and advantages may apply to only some embodiments falling within the claims and thus do not define the scope of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIG. 1  is a block diagram of two motor controllers having joined DC buses as may be used with the present invention; 
           [0032]      FIG. 2  is a detailed schematic diagram of the motor controllers of  FIG. 2  showing a dynamic braking resistor and associated solid-state switching element; 
           [0033]      FIG. 3  is a graph of DC bus voltage versus time aligned with a similar graph of control voltage for the solid-state switching element of the present invention showing the different control modes; and 
           [0034]      FIG. 4  is a set of plots of the control voltage for different control modes showing effective different average switching frequencies. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0035]    Referring now to  FIG. 1 , a motor control system  10  may include a first motor drive  12   a  and a second motor drive  12   b  each providing controlled three-phase power  14   a  and  14   b  to respective motors  16   a  and  16   b . The motors  16   a  and  16   b  may, for example, be 50 hp or 15 hp motors drawing as much as 65 or 22 amps at approximately 460 VAC RMS or approximately 650 VDC. Referring to  FIGS. 1 and 2 , motor drives  12   a  and  12   b  may receive three-phase power  18  at respective rectifiers  20   a  and  20   b  to produce DC power on DC links  22   a  and  22   b . Sometimes, the drives may also be used as a common DC bus configuration where its power is drawn from a common DC bus without rectifier circuit enabled. As shown in  FIG. 2 , the rectifier  20  may, for example, be a bridge of diodes  36  rectifying the three-phase power  18  into a high voltage (approximately 650 VDC) on the DC link  22 . The DC links  22   a  and  22   b  may be shunted by link capacitors  30   a  and  30   b  respectively which provide for energy storage. 
         [0036]    Power from the DC links  22   a  and  22   b  is received by inverters  34   a  and  34   b  which produce the control power  14   a ,  14   b . The inverters  34  generally provide a series of solid-state switches  38  (shown here with flyback diodes) that may be controlled by a switch controller  41  of a type well known in the art, for example, a PWM or direct torque controller, to provide for the power  14  to the motor  16 . 
         [0037]    The DC links  22   a  and  22   b  of motor drives  12   a  and  12   b  may be joined in parallel by conductors  24  to allow load sharing so that one rectifier  20   a , for example, may provide power to motor  16   b  under high demand situations and vice versa or so that power may be shared when one drive is motoring and the other drive is regenerating power to conserve power or when overhauling loads occur. For example, the dynamic braking of the present invention could be used in situations where both motors would regenerate at the same time in an emergency stop situation. It will be understood that additional motor drives  12  beyond two may be connected in this manner and that the present invention is applicable to other than emergency stopping situations or situation where both motors are regenerating. 
         [0038]    Each DC link  22   a  and  22   b  may also include a dynamic braking circuit  32   a  and  32   b  connected to the three-phase power  18  to limit the voltage on the bus when the drives are regenerating. As shown best in  FIG. 2 , each dynamic braking circuit  32  may include a dynamic braking resistor  40  in series with a solid-state switching device  42  (such as an insulated gate bipolar transistor (IGBT)) and in parallel with a flyback diode  44  of a type well known in the art. 
         [0039]    The resistor  40  and solid-state switching device  42  are connected in series to shunt the DC link  22  when the solid-state switching device  42  is closed and thereby to dissipate power in the capacitors  30  and generally lower the voltage of the DC link  22 . By shunting the DC link  22  with the resistor  40 , energy from the motor  16  during braking that is accumulated in the capacitor  30  may be extracted and dissipated. 
         [0040]    The solid-state switching device  42  is controlled by a signal from a dynamic braking controller  46  which may, for example, be a separate circuit or incorporated into controller  41  and which may be discrete circuitry or a programmed microcontroller of a type well known in the art. The dynamic braking controller  46  also receives electrical signals from the DC link  22  providing for a measurement of the voltage of the DC link  22 . 
         [0041]    Referring now to  FIG. 3 , the dynamic braking controller  46  of the present invention executes a hybrid control strategy for controlling the solid-state switching device  42  and thus the power dissipation applied to the DC link  22 . The hybrid control strategy provides for three generally controlled regimes that may be triggered by the voltage of the DC link  22 . In a first control range  50 , for DC bus voltages  52  (V bus ) less then V dc     —     off , no signal is provided by the dynamic braking controller  46  to the solid-state switching device  42  so that the solid-state switching device  42  remains in an off or open state. In this condition the resistor  40  is disconnected from the DC link  22  and no power is dissipated by the dynamic braking circuit  32 . In this case the duty cycle d of a control signal to solid-state switching device  42  is effectively zero per the following equation (1): 
         [0000]        d= 0 for V bus &lt;V dc     —     off   (1) 
         [0042]    In a second control range  54  for DC bus voltages  52  above V dc     —     off  and less than V dc     —     transition , the dynamic braking controller  46  provides a control signal to solid-state switching device  42  producing a pulse width modulation  56  switching the solid-state switching device  42  between a low state holding the solid-state switching device  42  off and a high state turning the solid-state switching device  42  on. The switching occurs at a regular switching frequency  58  typically being approximately 2 kHz. The on-times  60  of the pulse width modulation  56  provide a duty cycle that is a continuous function of the DC bus voltages  52  in the range between V dc     —     off  and V dc     —     transition  per the following equation (2): 
         [0000]    
       
         
           
             
               
                 
                   d 
                   = 
                   
                     
                       
                         d 
                         max 
                       
                        
                       
                         
                           
                             V 
                             bus 
                           
                           - 
                           
                             V 
                             dc_off 
                           
                         
                         
                           
                             V 
                             dc_transition 
                           
                           - 
                           
                             V 
                             dc_off 
                           
                         
                       
                        
                       
                           
                       
                        
                       for 
                        
                       
                           
                       
                        
                       
                         V 
                         dc_off 
                       
                     
                     &lt; 
                     
                       V 
                       bus 
                     
                     &lt; 
                     
                       V 
                       dc_transition 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   where 
                    
                   
                       
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     d 
                     max 
                   
                   = 
                   
                     
                       
                         
                           V 
                           transition 
                         
                         - 
                         
                           V 
                           dc_off 
                         
                       
                       
                         
                           V 
                           dc_on 
                         
                         - 
                         
                           V 
                           dc_off 
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0043]    The maximum duty cycle d max  will typically be about 0.8-0.9 as determined generally from the switching device thermal limit and the difference between the switching and conductions losses. V transition  may be for example around 750 V. More generally, the maximum duty cycle will be the difference between switching losses in the PWM operation and conduction losses in the switching device. The continuous control function exercised in the second control range  54  minimizes ripple in the DC bus voltage  52 ′. 
         [0044]    In a third control range  62 , the dynamic braking controller  46  provide a control signal to solid-state switching device  42  producing a hysteretic control signal  64  varying between a first state  66  and second state  68 . In the first state  66  the control signal provides a constant on-time  60 ′ providing a duty cycle equal to d max . In the second state  68  the control signal provides a continuously on signal having a duty cycle of one so that the solid-state switching device  42  is held on without switching effectively dropping pulses resulting in the elimination of switching losses for a given period and thus a lowering of the switching frequency. 
         [0045]    The dynamic braking controller  46  determines the state  66  or  68  according to the last threshold of V transition  and V dc     —     on  that the DC bus voltage  52  reached. Thus, for example, as the DC bus voltage  52  rises through V dc     —     transition  it switches to state  66  and remains there until the DC bus voltage  52  reaches V dc     —     on  at which point it switches to state  68  until the DC bus voltage  52  again drops to V dc     —     transition . At that point, the control circuit switches to state  68  and remains there until V bus  drops to less than V dc     —     transition  upon which the control circuit again switches to state  66 . This system provides for switching hysteresis. Because the hysteretic control signal  64  varies between fully on and a pulsed operation, the ripple in the DC bus voltage  52 ″ in this third control range  62  is much reduced with respect to normal hysteretic control. In third control range  62  the duty cycle is thus controlled per the following equation (4): 
         [0000]    
       
         
           
             
               
                 
                   d 
                   = 
                   
                     { 
                     
                       
                         
                           
                             d 
                             max 
                           
                         
                       
                       
                         
                           1 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0046]    Referring now to  FIG. 4 , it will be seen that in the second control range  54 , the average switching frequency  58  is constant and only the duty cycle (on-time  60 ) changes. In contrast, in third control range  62 , the average switching frequency varies being an average of switching frequency  58  (of state  66 ) and switching frequency  58  of zero in state  68 . Because average switching frequency in the third control range  62  is typically 50 to 200 Hz and much less than the switching frequency  58  (2 kHz) of second control range  54 , switching losses (e.g., power lost when the solid-state switching device  42  is neither at near-infinite nor near-zero resistance) are much reduced allowing continued operation of the solid-state switching device  42  at higher voltages and higher on-time (duty cycle) producing greater power dissipation and thus greater braking effect as the DC link voltage increases. As will be understood to those of skill in the art, this power dissipation is power taken from the load (motor  16 ) and dissipated as heat in the braking resistor  40   
         [0047]    The functionally continuous control of the solid-state switching device  42  through most of second control range  54 , where small areas in measurement result in only small differences in duty cycle, allows good sharing of braking responsibilities between the solid-state switching device  42  of the two motor drives  12   a  and  12   b.    
         [0048]    It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims.

Technology Category: 5