Patent Document

TECHNICAL FIELD 
     The present disclosure is generally related to data transmission and, more particularly, is related to a dual mode transmitter and method for transmitting data according to DisplayPort (DP) standard or High Definition Multimedia Interface (HDMI) standard. 
     BACKGROUND 
     An audio/visual signal can be communicated from a computing device to a display via a cable. For example,  FIG. 1  is a front view of a personal computer  100  including a cable  130  connecting a computing device  110  and a display  120 , such as a liquid crystal display (LCD) or plasma screen. Different standards, such as the DP standard or the HDMI standard, may be used for communicating the audio/visual signal from the computing device to the display. Under the DP standard, the transmission protocol is based on micro packets and is extensible for future feature additions, whereas the HDMI transmission protocol is a serial data stream at a 10× pixel clock rate. Also, for the DP standard, the transmission is an alternating current (AC) transmission in a voltage range of 400 mV-1200 mV. For the HDMI standard, the transmission is a direct current (DC) transmission in a voltage range of 1000 mV-1200 mV. 
     Each standard has advantages and disadvantages. DP supports both external (e.g., desktop) and internal (e.g., laptop) display connections whereas HDMI does not. Unlike DP, however, HDMI supports xvYCC color space, Dolby True High Definition (DolbyTrueHD), Digital Theater Systems-High Definition (DTS-HD) Master Audio bitstream, Consumer Electronics (CE) control signals, and compatibility with Digital Visual Interface (DVI). Given the different capabilities of the DP and HDMI standards, it may be useful to change data from one standard to another standard for a particular application. 
       FIG. 2  is a block diagram of the personal computer  100  illustrated in  FIG. 1  including a conventional configuration for changing a DP transmission to an HDMI transmission using a level shifter  114 . The computing device  110  includes a DP transmitter  112 , whereas the display  120  includes an HDMI interface. Therefore, the DP data signal outputted by the DP transmitter  112  is changed, using a level shifter  114 , into an HDMI data signal compatible with the HDMI interface on the display  120 . 
     Specifically, referring to  FIG. 2 , the computing device  110  includes a system board  115 . The system board  115  includes a graphics processing chip  111 , a DP component  113 , and a level shifter  114 . The graphics processing chip  111  includes the DP transmitter  112 , and the DP component  113  is coupled to the DP transmitter  112 . The level shifter  114  receives the output of the DP component  113 , changes the voltage level and current, and outputs an HDMI data signal. The HDMI data signal is communicated from the computing device  110  to the display  120 . 
     In the conventional configuration illustrated in  FIG. 2 , the level shifter  114  is not located in the graphics processing chip  111  and is a separate chip located on the system board  115 . Because the level shifter  114  is external to the graphics processing chip  111 , the level shifter  114  takes up valuable hardware space in the computing device  110  and adds additional cost. Similarly, in the case of changing an HDMI data signal to a DP data signal according to a conventional configuration, an HDMI component and a level shifter external to the graphics processing chip are necessary. These external items occupy space on the system board  115 , and the conventional configuration is an expensive, bulky solution for changing between HDMI transmission and DP transmission. 
       FIG. 3  is a circuit diagram of the conventional configuration illustrated in  FIG. 2 . The circuit diagram illustrates a conventional configuration for changing from DP transmission to HDMI transmission using a level shifter  114 . The switching elements SN 2 , SN 3  are controlled by a data signal D 1  whereas switching elements SN 1 , SN 4  are controlled by a complementary data signal D 1  bar. Switching elements SN 1  and SN 2  are coupled to a current source, which is tied to ground. Switching elements SN 3  and SN 4  are coupled to a current source, which is biased at 2V. Switching elements SN 1  and SN 3  are coupled together, and switching elements SN 2  and SN 4  are also coupled together. Also shown in  FIG. 3  is a DP component  113  including two resistors R 31 , R 32  biased at 0.7V, and each resistor R 31 , R 32  is coupled to a junction between the coupled switching elements (e.g., SN 1  and SN 3 ; SN 2  and SN 4 ) as illustrated in  FIG. 3 . Also coupled to each junction between the coupled switching elements (e.g., SN 1  and SN 3 ; SN 2  and SN 4 ) is a capacitor C 31 , C 32 . Further, in  FIG. 3 , a level shifter  114  is coupled to the capacitors C 31 , C 32  as illustrated, and the output of the level shifter  114  is delivered to the receiver  121 , included in the display  120  illustrated in  FIG. 1 . As discussed above with respect to  FIG. 2 , the level shifter  114  is externally used on system board for changing DP transmission to HDMI transmission. In addition, the level shifter  114  consumes valuable hardware space and the configuration is an expensive solution. 
     SUMMARY 
     Embodiments of the present disclosure provide a system and method for dual mode DP and HDMI transmission. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlled by a data signal. The dual mode DP and HDMI transmitter also comprises a control circuit coupled to the driver circuit. The control circuit is configurable to transmit the data signal in a DP mode or an HDMI mode according to a mode signal. 
     The present disclosure can also be viewed as providing methods for dual mode DP and HDMI mode transmission. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: receiving a mode signal; determining whether to configure the dual mode DP and HDMI transmitter for transmitting in a DP mode or an HDMI mode based on the received mode signal; and configuring the dual mode DP and HDMI transmitter in accordance with the determination. 
     Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
         FIG. 1  is a front view of a personal computer. 
         FIG. 2  is a block diagram of the personal computer illustrated in  FIG. 1  and illustrates a conventional configuration for changing a DP transmission to a HDMI transmission using a level shifter. 
         FIG. 3  is a circuit diagram illustrating the conventional configuration depicted in  FIG. 2 . 
         FIG. 4  is a circuit diagram of an embodiment of a dual mode DP and HDMI transmitter. 
         FIG. 5  is a flow chart illustrating an embodiment of a method for configuring a dual mode DP and HDMI transmitter. 
         FIG. 6  is a block diagram illustrating a first embodiment of a personal computer. 
         FIG. 7  is a circuit diagram illustrating the first embodiment of the personal computer depicted in  FIG. 6 . 
         FIG. 8  is a block diagram illustrating a second embodiment of a personal computer. 
         FIG. 9  is a circuit diagram illustrating the second embodiment of the personal computer depicted in  FIG. 8 . 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure describes systems and/or methods for dual mode DisplayPort (DP) and High Definition Multimedia Interface (HDMI) transmission. A dual mode DP and HDMI transmitter can be included as an integrated circuit on a graphics processing chip. The dual mode DP and HDMI transmitter can be configured to transmit in a DP mode or an HDMI mode depending on the type of interface in a display of a personal computer. The dual mode DP and HDMI transmitter is configured by applying a mode signal to the transmitter, and the mode signal is saved on a register in a chipset. Once the dual mode DP and HDMI transmitter is configured to transmit in the DP mode or the HDMI mode, a DP component or HDMI component can be coupled to the transmitter depending on the configuration. The configured dual mode DP and HDMI transmitter and the appropriate coupled component are included in a computing device, which transmits an audio/visual signal according to the selected mode to a display. The dual mode DP and HDMI transmitter eliminates the need for the external level shifter discussed above, and thus, the required hardware space in a computing device may be reduced. Additionally, because an external level shifter is not needed, expenses associated with the level shifter can be saved. 
       FIG. 4  is a circuit diagram of an embodiment of a dual mode DP and HDMI transmitter  417 . The dual mode DP and HDMI transmitter  417  in the embodiment illustrated in  FIG. 4  includes a driver circuit  419  and a control circuit  418 . The driver circuit  419  includes switching elements SN 41 , SN 42 , which are controlled by a data signal D 1  and a complementary data signal D 1  bar, respectively. The data signal D 1  and the complementary data signal D 1  bar are in a differential form and are audio/visual signals. 
     The control circuit  418  includes resistors R 1 , R 2  coupled to switching elements SP 41 , SP 42 , respectively, which are coupled to a 2V bias. In the embodiment, the substrate of switching elements SP 41 , SP 42  is coupled to switching elements SN 43 , SN 44 , and switching elements SN 43 , SN 44  each receive the mode signal M as input. Switching elements SN 43 , SN 44  are coupled to the 2V bias. Switching elements SP 41  and SP 42  are each controlled by the output of a NAND gate N 1 , which has the mode signal M and a resistance calibration signal A for inputs. In the embodiment, the dual mode DP and HDMI transmitter  417  illustrated in  FIG. 4  is an integrated circuit included on a graphics processing chip. 
     As mentioned above, the dual mode DP and HDMI transmitter  417  is configurable by the application of a mode signal M. When the mode signal M has a logical value of “1,” which in this nonlimiting example indicates the mode for transmission is the DP mode, the resistors R 1 , R 2  are coupled to 2V because current flows through the switching elements SN 43 , SN 44 , SP 41 , SP 42 . Therefore, in DP mode, I S0 =I 10 +I 20  and Vswing=IR/2. As a result, the dual mode DP and HDMI transmitter  417  is configured to transmit in the DP mode. When the mode signal M has a logical value of “0,” which in this nonlimiting example indicates the mode for transmission is the HDMI mode, the resistors R 1 , R 2  are decoupled from 2V because current cannot flow through the switching elements SN 43 , SN 44 , SP 41 , SP 42 . Therefore, in HDMI mode, I S0 =I 10 =˜10 mA; I 20 =0 mA; and Vswing=IR. As a result, the dual mode DP and HDMI transmitter  417  is configured to transmit in the HDMI mode. 
     In some embodiments, the resistors R 1 , R 2  in the control circuit  418  are poly resistors. In addition, the switching elements SP 41 , SP 42  are metal-oxide-semiconductor field-effect-transistor (MOSFET) resistors, and in particular, PMOS resistors. In some embodiments, there may be a plurality of PMOS resistors in series. Further, in some embodiments, there may be a plurality of poly resistors in series. The current flow through switching elements SP 41 , SP 42  is calibrated by the output of the NAND gate N 1 , which receives the resistance calibration signal A as an input. In this way, the effective resistance of a circuit path including a MOSFET resistor and a poly resistor is calibrated to 50 ohms. At the connection for the component, the PMOS parasitic capacitance is mitigated, and therefore, the overall RC time constant is reduced. In other words, the combination of the MOSFET resistors and poly resistors reduce parasitic capacitances and, thus, enable high frequencies of operation. 
       FIG. 5  is a flow chart illustrating an embodiment of a method  500  for configuring a dual mode DP and HDMI transmitter  417 . The method  500  includes blocks  520 ,  530 ,  532 ,  534 , and  536 . Referring to  FIGS. 4 and 5 , in block  520 , a mode signal M is received at a dual mode DP and HDMI transmitter  417 . In the embodiment, the mode signal M is stored in a register in a chipset. The chipset includes a graphic processing chip, and the graphics processing chip includes the dual mode DP and HDMI transmitter  417 . 
     In block  530 , a determination whether to configure the dual mode DP and HDMI transmitter  417  for transmitting in a DP mode or an HDMI mode is made. The determination is made using the control circuit  418  based on the received mode signal M. Specifically, the output of the NAND gate N 1 , which receives the mode signal M, controls switching elements SP 41 , SP 42 , and the switching elements SN 43 , SN 44  are controlled by the mode signal M. 
     In block  532 , the dual mode DP and HDMI transmitter is configured in accordance with the determination. For example, responsive to the determination being to configure the dual mode DP and HDMI transmitter  417  to transmit in a DP mode, an active load is coupled to a source. In the embodiment, the active load is 50 ohms. Referring to  FIG. 4 , the resistors R 1 , R 2  are coupled to the 2V bias because the switching elements SP 41 , SP 42 , SN 43 , SN 44  are conducting current based on the determination discussed with respect to block  530 . The dual mode DP and HDMI transmitter  417  that results from block  532  is configured to transmit in the DP mode. 
     In block  534 , the active load is calibrated according to a calibration signal A. The current flow through switching elements SP 41 , SP 42  is calibrated by the output of NAND gate N 1 , which receives the resistance calibration signal A as an input. In this way, the effective resistance of each circuit path including a MOSFET resistor and a poly resistor can be calibrated to 50 ohms. At the connection for the component, the PMOS parasitic capacitance is mitigated, and therefore, the overall RC time constant is reduced. In other words, the combination of the MOSFET resistors and poly resistors reduce parasitic capacitances and, thus, enable high frequencies of operation. Block  532  and block  534  may be performed at the same time when the mode signal is set to DP mode. 
     In block  536 , the dual mode DP and HDMI transmitter is configured in accordance with the determination. For example, responsive to the determination being to configure the dual mode DP and HDMI transmitter  417  to transmit in a HDMI mode, an active load is decoupled from a source. Referring to  FIG. 4 , the resistors R 1 , R 2  and switching elements SP 41 , SP 42 , SN 43 , SN 44  are decoupled from the 2V bias because the switching elements SP 41 , SP 42 , SN 43 , SN 44  are not conducting current based on the determination discussed with respect to block  530 . The dual mode DP and HDMI transmitter  417  that results from block  536  is configured to transmit in the HDMI mode. 
       FIG. 6  is a block diagram illustrating a first embodiment of a personal computer  600 . The personal computer  600  includes a computing device  610 , a display  620 , and a cable  632  coupling the computing device  610  to a receiver  621  included in the display  620 . The display  620  has a DP interface. The computing device  610  includes a graphics processing chip  611 , which is an integrated circuit including the dual mode DP and HDMI transmitter  417 A. In the embodiment, the graphics processing chip  611  is included in a chipset. The dual mode DP and HDMI transmitter  417  described in  FIG. 4  is configured to be a dual mode DP and HDMI transmitter  417 A configured to transmit in DP mode according to a mode signal M. The chipset includes the mode signal M stored in a register. The dual mode DP and HDMI transmitter  417 A is coupled to a DP component  618 , which is also included in the computing device  610 . Both the graphics processing chip  611  and the DP component  618  may be coupled to a system board in the computing device  610 . A DP data signal may be transmitted from the computing device  610  to the display  620  via the cable  632  when the personal computer is in operation. 
       FIG. 7  is a circuit diagram illustrating the first embodiment of the personal computer  600  depicted in  FIG. 6 . The dual mode DP and HDMI transmitter  417 A is configured to transmit in DP mode (M=1), and as discussed above with respect to  FIG. 4 , the dual mode DP and HDMI transmitter  417 A includes a driver circuit  419  controlled by a data signal D 1  and a complementary data signal D 1  bar in differential form. Further, the dual mode DP and HDMI transmitter  417 A also includes a control circuit  418  coupled to the driver circuit  419 . Because the dual mode DP and HDMI transmitter  417 A is configured to transmit in a DP mode, the active load has been coupled to the source. Specifically, the resistors R 1 , R 2  are coupled to the 2V bias because the switching elements SP 41 , SP 42 , SN 43 , SN 44  are conducting current. Therefore, in DP mode, I S0 =I 10 +I 20  and Vswing=IR/2. 
     Also included in the computing device  610  is a DP component  618  coupled to the dual mode DP and HDMI transmitter  417 A configured to transmit in DP mode. The DP component  618  includes two capacitors in parallel and two resistors in series as shown in  FIG. 7 . The biased voltage between the two resistors is 0.7V, and the two resistors are each 50 ohm resistors. The capacitors of the DP component  618  are coupled to the connections between the driver circuit  419  and the control circuit  418  as illustrated. The output of the DP component  618  is communicated over cable  632  to the receiver  621 . The DP component  618  may be added by the customer. The output of the DP component  618  is coupled via a cable  632  to the receiver  621  of the display  620 , which includes DP interface. 
     According to the first embodiment of a personal computer illustrated in  FIGS. 6 and 7 , the dual mode DP and HDMI transmitter  417 A configured to transmit in a DP mode includes a driver circuit  419  controlled by a data signal D 1  and a complementary data signal D 1  bar in differential form. The dual mode DP and HDMI transmitter  417 A configured to transmit in a DP mode provides the appropriate biasing and resistance for DP mode by the control circuit  418  in combination with the DP component  618 . Specifically, the control circuit  418  provides biasing of 2V and an effective resistance of 50 ohms. As would be understood by a person having ordinary skill in the art, a DP data signal is then communicated as an output of the DP component  618  to the display  620 . 
       FIG. 8  is a block diagram illustrating a second embodiment of a personal computer  800 . The personal computer  800  includes a computing device  810 , a display  820 , and a cable  834  coupling the computing device  810  to a receiver  821 , which is included in the display  820 . The display  820  has an HDMI interface. The computing device  810  includes a graphics processing chip  811 , which is an integrated circuit including the dual mode DP and HDMI transmitter  417 B. In the embodiment, the graphics processing chip  811  is included in a chipset. The dual mode DP and HDMI transmitter  417  described in  FIG. 4  is configured to be a dual mode DP and HDMI transmitter  417 B configured to transmit in HDMI mode according to a mode signal M. The chipset includes the mode signal M stored in a register. The dual mode DP and HDMI transmitter  417 B is coupled to an HDMI component  818 , which is also included in the computing device  810 . Both the graphics processing chip  811  and the HDMI component  818  may be coupled to a system board in the computing device  810 . An HDMI data signal may be transmitted from the computing device  810  to the display  820  via the cable  834  when the personal computer is in operation. 
       FIG. 9  is a circuit diagram illustrating the second embodiment of the personal computer  800  depicted in  FIG. 8 . The dual mode DP and HDMI transmitter  417 B is configured to transmit in HDMI mode (M=0). The dual mode DP and HDMI transmitter  417 B includes a driver circuit  419  controlled by a data signal D 1  and a complementary data signal D 1  bar in a differential form. Further, the dual mode DP and HDMI transmitter  417 B also includes a control circuit  418  coupled to the driver circuit  419 . Because the dual mode DP and HDMI transmitter  417 B is configured to transmit in a HDMI mode, the active load has been decoupled from the source. Specifically, the resistors R 1 , R 2  are decoupled from the 2V bias because the switching elements SP 41 , SP 42 , SN 43 , SN 44  are not conducting current. Therefore, in HDMI mode, there is an open circuit between the 2V bias and each of the resistors R 1 , R 2 . Hence in HDMI mode, I S0 =I 10 =˜10 mA; I 20 =0 mA; and Vswing=IR. 
     Also included in the computing device  810  is a HDMI component  818  coupled to the dual mode DP and HDMI transmitter  417 B configured to transmit in HDMI mode. The HDMI component  818  includes two resistors biased at 3.3V as shown in  FIG. 9 , and the two resistors are each 50 ohm resistors. The output of the HDMI component  818  is communicated over cable  834  to the receiver  821  in the display  820 , which includes an HDMI interface. 
     According to the second embodiment illustrated in  FIGS. 8 and 9 , dual mode DP and HDMI transmitter  417 B configured to transmit in a HDMI mode receives a data signal D 1  and a complementary data signal D 1  bar in differential form at the driver circuit  419 . The dual mode DP and HDMI transmitter  417 B configured to transmit in a HDMI mode then provides the appropriate biasing and resistance for HDMI mode in combination with the HDMI component  818 . Specifically, there is an open circuit between the 2V bias and each of the resistors R 1 , R 2 . As would be understood by a person having ordinary skill in the art, an HDMI data signal is then communicated as an output of the HDMI component  818  to the display  820 . 
     In some embodiments, each of the switching elements comprise a solid state switch such as a transistor, etc. Specifically, MOSFET transistors or other types of transistors are employed. Alternatively, other types of switching elements may be employed such as switches or other elements may be used. The switching elements are operatively coupled to and are manipulated by one or more control inputs. 
     It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present disclosure and protected by the following claims.

Technology Category: 3