Patent Document

This application claims priority from U.S. Provisional Application Ser. No. 60/541,828 filed Feb. 5, 2004. The entirety of that provisional application is incorporated herein by reference. 

   BACKGROUND 
   1. Field of the Invention 
   The present application relates to charge pumps and more particularly to charge pumps suitable for use in integrated circuits. 
   2. Background of the Technology 
   A charge pump is a circuit topology that is designed to produce a voltage at a higher potential than that provided by a source. Charge pumps may be used in a wide variety of applications, including, but not limited to, serving as power supplies for passive RFID (radio frequency identification) circuits. 
   If the source/input to the charge pump is of single polarity, a charge pump generically must be of the form disclosed by IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, (June 1976), using different clock phases. Most MOS charge pumps are of this form, as reflected by U.S. Pat. Nos. 6,137,344, 6,198,342, and 6,501,325. This form of charge pump relies on alternate phases of a clock to spill the charges through the MOS device while it is in a conduction mode, and block the reverse flow of charge back through the device by a clock phase that turns the device off during the back cycle. This form of charge pump is an active-mode charge pump, requiring external clocks and power rails. 
   If the source is of alternating polarity voltage, whether sinusoidal power source or radio-frequency signal, then the charge pump is of the form of an AC-DC converter, and the sequence of charge pump stages provides a single polarity output with voltage multiplication. The source must be of alternating polarity for the charge to be lifted to higher voltage levels at the output, with the MOS device as a diode construct. This form of charge pump is a passive-mode charge pump, requiring no external clock phases or power rails. The passive mode type of charge pump is fairly rare. The only known examples are U.S. Pat. Nos. 6,549,064 and 6,819,162. The charge pumps disclosed by these two patents use a mix of capacitors and MOSFETs. For U.S. Pat. No. 6,549,064 each stage consists of 3 MOSFETs and 2 capacitors, with two of the MOSFETs configured to act as diodes and the remaining transistor configured as a regular MOSFET device. U.S. Pat. No. 6,819,162 a negative voltage is induced by a plurality of pump stages, with each stage consisting of 4 MOSFETS, 4 diodes, and 2 capacitors. 
   All charge pumps require a diode-capacitance action in order to accomplish the capture and accumulation of charge, relying on either clock phasing or alternating polarity to invoke the on-off diode action necessary for functionality. Even though the MOSFET is a capacitance construct is unusual to use the MOSFET as a capacitor. The only known instance in which MOSFETs are used in this manner is U.S. Pat. No. 6,166,585. For this patent, the MOS capacitances are devised as simple capacitors, driven by phased clocks and supplied by power rails as an active mode form of charge pump. 
   The charge pumps disclosed in the aforementioned prior art suffer from various drawbacks, including either a need for external clock circuitry or overly complex designs using a mix of capacitors, diodes and MOSFETs. 
   SUMMARY 
   The aforementioned issues are addressed to a great extent by a new charge pump that includes a plurality of stages or a single stage, each of which includes two MOS transistors with no need of collateral capacitances or diodes. Each transistor is configured to operate as a transcapacitance in the accumulation mode. Preferred embodiments of the charge pump make no use of any capacitor except that of the MOS capacitance and no use of any diodes except that of the embedded diode features of the MOS transistor. This charge pump may be realized in any MOS technology. In some embodiments, the nMOS technology is employed. Other embodiments make use of a pMOS or a CMOS technology. The topology described herein is unique because it uses the MOSFET devices as transcapacitances rather than as transistors, thereby eliminating the need to have separate and distinct capacitances and/or diodes, as is conventional for most charge pump constructs. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
     The aforementioned advantages and features will be more readily understood with reference to the following detailed description and the accompanying drawings in which: 
       FIG. 1  is a schematic diagram of a single stage of an NMOS charge pump, consisting of two transistors configured in the transcapacitance (transfer capacitance) orientation. 
       FIG. 2  is a schematic diagram of a four-stage NMOS charge pump utilizing the stage of  FIG. 1 . 
       FIG. 3  is a plot of a simulation of the 4-stage charge pump of  FIG. 2  with input source amplitude Vp=3.0V at 915 MHz. 
       FIG. 4  is a schematic diagram of a single stage nMOS charge pump of the form shown in  FIG. 1  to which collateral capacitances have been added to enhance the performance of the charge pump. 
       FIG. 5  is a plot of a simulation of a 4-stage charge pump of the form of  FIG. 2  which has been enhanced through the addition of collateral capacitances in the manner shown in  FIG. 4 , with input source amplitude Vp=3.0V at 915 MHz. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, a plurality of specific details, such as numbers of charge pump stages and input and output voltages, are set forth in order to provide a thorough understanding of the embodiments described herein. The details discussed in connection with the preferred embodiments should not be understood to limit the present invention. Furthermore, for ease of understanding, certain method steps are delineated as separate steps; however, these steps should not be construed as necessarily distinct nor order dependent in their performance. 
   A single stage  100  of a charge pump according to one embodiment is illustrated in  FIG. 1 . The stage  100  includes two MOSFETs, M 1  and M 2 . Each of the transistors M 1 , M 2  have four terminals, commonly identified as gate  110 , source  120 , drain  140 , and body  130 . The body of the transistors M 1 , M 2  is of opposite type to both that of the source  120  and drain  140  materials, which are usually implanted, as well as opposite in type to that of the field-induced channel. The gate  110  of each transistor M 1 , M 2  is isolated from the induced surface charge layer and the body  130  by a thin-layer insulator, typically an oxide, that forms a ‘MOS’ (metal-oxide-semiconductor) capacitative junction on the order of 1-2 fF per μm 2 . Charge may be accumulated on the opposite sides of the insulating oxide layer of the MOS sandwich. 
   The input signal is connected across two terminals, also called input nodes, as represented by  FIG. 1 . One of these nodes is designated as ground and the other is designated as the source signal node Vs. The source is an alternating polarity signal, so the source node Vs will alternate between two levels that are nominally equal and opposite in polarity about the ground (or neutral) node at a frequency peculiar to the origin of the source. 
   The body  130   a  of the first nMOS transistor, M 1 , is connected to ground. Its drain  140   a  and source  120   a  are connected together. Its gate  130   a  is connected to the input signal node Vs. The transistor M 1 , by virtue of the intrinsic diode-capacitance junction, captures charge on the accumulation surface layer at the semiconductor-oxide interface. The charge accumulates as result of applied potential and the intrinsic MOS gate-to-body capacitance. The potential across the MOS capacitance will be switched in polarity by the alternating potential of the signal from the source Vs and force the charge to flow from the accumulation layer and onto the drain and source nodes  140   a ,  120   a . This MOS capacitance is therefore called the “pumping” transfer capacitance, which may be more correctly defined as a “pumping transcapacitance” since it is a MOS transistor used in a capacitive charge-transfer mode rather than a trans-resistance (transistor) mode. 
   The body terminal  130   b  of the second nMOS transistor, M 2 , is connected to the joined drain and source nodes  140   a ,  120   a  of the first nMOS transistor M 1 . The drain and source terminals  140   b ,  120   b  of transistor M 2  are connected together. The gate terminal  110   b  is connected to ground. The body of transistor M 2 , as well as all others, must be isolated from other transistors by means of an implanted or diffused well or by other means. 
   The topology of the transistor M 2  reacts to the “pumping action” of the first nMOS transistor M 1 . As result of the intrinsic diode-capacitance junction of the nMOS device, the diode action of both transistors M 1 , M 2  prevents the charge from flowing backwards, and the MOS capacitance of the transistor M 2  therefore accumulates the charge that is pumped by transistor M 1 . The nMOS device and intrinsic gate-body capacitance of transistor M 2  is therefore called the “accumulation transcapacitance.” 
   As discussed above,  FIG. 1  illustrates a single stage  100  of a charge pump. A four stage charge pump is illustrated in  FIG. 2 . The two transistors M 1  and M 2  of  FIG. 1  comprise what will be defined as the first stage  100  of the charge pump, with output node being that of the joined drain and source nodes  140   b ,  120   b  of transistor M 2 . The body terminal  130   c  of the next transistor in the sequence, M 3  (the first transistor of the second stage  200 ), is connected to the output drain and source terminals  140   b ,  120   b  of transistor M 2  of the first stage  100 . The gate terminal  110   c  of transistor M 3  is connected to the input signal node Vs. The drain and source terminals  140   c ,  120   c  of transistor M 3  are connected together, and form a next-stage “pumping transcapacitance” in the same manner as that of the capacitor M 1  of the first stage  100 . 
   The body terminal  130   d  of the next transistor (M 4 ) in the second stage is connected to the joined drain and source terminals  140   c ,  120   c  of transistor M 3 . The drain and source terminals  140   d ,  120   d  of M 4  are connected together. The gate terminal  110   d  of transistor M 4  is connected to ground. The intrinsic diode-capacitance action of the NMOS device M 4  forms the second-stage “accumulation transcapacitance.” The two transistors M 3  and M 4  thereby comprise what can be defined as the second stage of the charge pump, with output at the joined drain and source nodes  140   d ,  120   d  of transistor M 4 . 
   Connection of the transistors in successive stages  300 ,  400  (and as many additional stages as desired) is continued in the same manner, with joined drain and source nodes of each transistor in the sequence connected to the body of the next transistor, and gates alternately connected to ground and input signal, as shown in  FIG. 2 . This results in the formation of a sequence, or plurality, of stages, connected as described above, with exception only of the first transistor, as represented by M 1  and the last transistor, as represented by M 8 . The first transistor is connected as described above. The joined drain and source nodes of the last transistor M 8  are directed to a load capacitance CL. Because the stages are successive and sequential, the potential from one stage adds to the next stage. 
     FIG. 2  is a construct that represents four stages, made up of transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , and M 8 , respectively. Transistors M 1 , M 3 , M 5  and M 7  are the “pumping transcapacitances,” and transistors M 2 , M 4 , M 6 , and M 8  are the “accumulation transcapacitances.” Ideally, each stage adds a potential of twice the amplitude of the signal. For  FIG. 2 , the difference between the output nodes is then ideally eight times the voltage amplitude of the input AC signal. The charge pump topology can have as many stages as desired, to produce an ideal output voltage that is 2*N higher than the input source amplitude, where N is the number of stages. 
   If the intrinsic diode-capacitance MOS transistor junction is not ideal (which will be the case in a practical circuit), then the 2*N amplitude multiplication factor is reduced. Gate thresholds must also be exceeded, which also reduces the multiplication factor. But as long as the multiplication factor is greater than unity, the charge is accumulating and usable energy is stored on the capacitance across the output. The output of the charge pump is directed to a storage capacitance placed across the output nodes, such as indicated by capacitance CL in  FIG. 2 . This storage capacitance can then serve as a transient power source for an integrated circuit load, which in  FIG. 2  is represented by the resistor R 1  in parallel with the capacitance CL. 
   The substrate-to-well capacitance can also be used as a storage capacitance, for which the circuit will then be of the form of a three-dimensional charge accumulation construct. 
   For an nMOS charge pump such as that shown in  FIG. 2 , the polarity at the output will be positive relative to ground. If the construct were designed in terms of pMOS transistors, the output would be negative relative to ground. If both constructs are used, as in a CMOS (complementary MOS) version, the output nodes would then be of opposite polarities and would be taken in push-pull between the outputs. For the CMOS version the technology would have to be of triple-well form, otherwise one of the polarities would be shorted out by the substrate. 
   The functionality of the topology has been verified by simulation using state-of-the-art MOS models (level-49) for both NMOS and CMOS versions, at input signal frequencies as high as 1.0 GHz. The performance of the topology is represented by the plot  300  of  FIG. 3 , which is a plot of voltage vs. time for a plurality of charge pumps with varying MOS transcapacitance areas.  FIG. 3  indicates that, for the 4-stage example shown in  FIG. 2 , the output voltage level is at a single polarity and is several times the amplitude of the input source. For the curve  310  representing the largest MOS transcapacitance area, the output voltage is approximately 8.5 volts for an input voltage of 3.0 volts. This is a multiplication factor of 8.5/2.3≈2.8 (as compared to an ideal multiplication factor of 2*N=8 for a four stage charge pump). 
   Although one aspect of inventive charge pump described herein is that collateral capacitances and diodes are not required, the invention should not be understood to preclude the use of other components to enhance or modify the charge pump output. For example, as shown in  FIG. 4 , collateral capacitances may be included in the charge pump stages. In the example of  FIG. 4 , a capacitance of a size equal to that of the MOS capacitance is deployed across each of the MOS transcapacitances (i.e., across the body and gate terminals of each transistor). When this construct is extended to a multiple stage topology, such as a four stage charge pump of the form illustrated in  FIG. 3 , it results in an enhancement of the voltage output as reflected by  FIG. 5 . 
   Obviously, numerous other modifications and variations of the present invention are possible in light of the above descriptions. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Technology Category: 5