Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority to Korean patent application number 10-2013-0090201, filed on Jul. 30, 2013, the entire disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field of Invention 
         [0003]    Various embodiments of the present invention relate to an integrated circuit design technology, and more particularly, to a current generation circuit and a semiconductor device having the same. 
         [0004]    2. Description of Related Art 
         [0005]    A semiconductor device may include a memory cell array and a plurality of circuits. The memory cell array may store data. The circuits may program the memory cell array with data, or read or erase the stored data. In addition, the circuits may include a page buffer unit, a voltage generation circuit, a row decoder, a page buffer unit, a column decoder and an input/output circuit. Among them, the page buffer unit may include a plurality of page buffers. These page buffers may exchange data through bit lines coupled to the memory cell array; sense data transferred through the bit lines, during read and verification operations; and output a sensing result. For example, the page buffers may compare a current of the data transferred through the bit lines with a reference current, and output data based on a comparison result. 
         [0006]    However, since the page buffers operate simultaneously during the read and verification operations, a voltage (e.g., power voltage) being applied to the circuits may be temporarily reduced. The temporary reduction in the voltage may cause the reference current to be temporarily changed, and the reliability of a sensing operation of the page buffers may be reduced due to the temporary change in the reference current. 
       BRIEF SUMMARY 
       [0007]    Exemplary embodiments of the present invention are directed to a current generation circuit that may generate a current having a constant level despite presence of variations in a power voltage and a semiconductor device having the same. 
         [0008]    A current generation circuit according to an exemplary embodiment of the present invention may include a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage, and a current driving circuit suitable for generating a current based on a voltage output from the comparison circuit. 
         [0009]    A semiconductor device according to an exemplary embodiment of the present invention may include a memory cell array including a plurality of memory blocks storing data, a page buffer unit suitable for exchanging data with the memory cell array through bit lines and performing a sensing operation using a reference current, and a current generation circuit suitable for generating the reference current, which is constant regardless of variations in a voltage level of a power voltage, and supplying the reference current to the page buffer unit. 
         [0010]    A memory system according to an exemplary embodiment of the present invention may include a memory control unit suitable for outputting control signals through plurality of pins in response to an external command input through a system bus, a memory interface unit suitable for outputting interface signals including a command signal and an address in response to the control signals, and a memory storage unit including a semiconductor device storing data, wherein the semiconductor device includes a current generation circuit suitable for generating a reference current, which is constant regardless of variations in a voltage level of a power voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram illustrating a current generation circuit according to an embodiment of the present invention; 
           [0012]      FIGS. 2A and 2B  are circuit diagram illustrating a switching operation of the current generation circuit shown in  FIG. 1 ; 
           [0013]      FIG. 3  is a tinning diagram illustrating an operation of the current generation circuit shown in  FIGS. 1 ,  2 A and  2 B; 
           [0014]      FIG. 4  is a block diagram of a semiconductor device including the current generation circuit shown in  FIG. 1 ; and 
           [0015]      FIG. 5  is a block diagram of a memory system including the semiconductor device shown in  FIG. 4 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0016]    Hereinafter various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The figures are provided to enable those of ordinary skill in the art to make and use the present invention according to the exemplary embodiments of the present invention. Throughout the disclosure, reference numerals correspond directly to the like numbered parts in the various figures and embodiments of the present invention. 
         [0017]    Furthermore, ‘connected/coupled’ represents that one component is directly coupled to another component or indirectly coupled through another component. In this specification, a singular form may include a plural form as long as it is not specifically mentioned in a sentence. Furthermore, ‘include/comprise’ or ‘including/comprising’ used in the specification represents that one or more components, steps, operations, and elements exists or are added. 
         [0018]      FIG. 1  is a circuit diagram illustrating a current generation circuit according to an embodiment of the present invention. 
         [0019]    Referring to  FIG. 1 , the current generation circuit  100  may receive a first voltage V1, which is generated by a voltage generation circuit  200 , and generate a predetermined current (e.g., a reference current) and transfer the constant current to the internal circuit  300 . 
         [0020]    The current generation circuit  100  may include a mirroring circuit  110 , a comparison circuit  120  and a current driving circuit  130 . 
         [0021]    The mirroring circuit  110  may be charged by using the first voltage V1, which is generated from the voltage generation circuit  200 , and a power voltage VCC when the current generation circuit  100  operates in a sample mode. For example, the voltage generation circuit  200  may generate the first voltage V1 having a higher voltage level than that of the power voltage VCC. The mirroring circuit  110  may include a first switch  111  and a capacitor  112 . The first switch  111  may transfer the first voltage V1 to the first node N1 or block the first voltage V1. The capacitor  112  may be coupled between the first node N1 and a power voltage VCC terminal and be charged by using the first voltage V1. The first switch  111  may be turned on when the current generation circuit  100  operates in the sample mode and turned off when the current generation circuit  100  operates in a hold mode. The first switch  111  may be controlled by a control circuit (denoted by  1200  of  FIG. 4 ). 
         [0022]    The comparison circuit  120  may include an operational amplifier  121 . The operational amplifier  121  may compare voltages applied to a first input terminal and a second input terminal  12 , and output a result of comparison to a second node N2. For example, the voltage charged in the capacitor  112  may be applied to the first input terminal  11  of the comparison circuit  120 , and a feedback voltage may be applied to the second input terminal  12 . The feedback voltage may be substantially the same as a voltage output from the comparison circuit  120 . In this case, the operational amplifier  121  operates as a unity gain buffer, which generates an output voltage following an input voltage. 
         [0023]    The current driving circuit  130  may generate a current by forming a current path between the power voltage VCC terminal and the internal circuit  300  based on the voltage, which is applied to the second node N2, when the current generation circuit  100  operates in the hold mode. For example, the current driving circuit  130  may include a second switch  131  and a driver  132 . The second switch  131  may be coupled to the second node N2. In addition, the second switch  131  may be turned on when the current generation circuit  100  operates in the hold mode and turned off when the current generation circuit  100  operates in the sample mode. The driver  132  may couple the power voltage VCC terminal and the internal circuit  300  based on the voltage transferred through the second switch  131 . In other words, the driver  132  may be implemented with an NMS transistor having a drain coupled to the power voltage VCC terminal and a source coupled to the internal circuit  300 , and a gate coupled to the second switch  131 . The second switch  131  may be controlled by the control circuit  1200  shown in  FIG. 4 . 
         [0024]    The internal circuit  300  may include circuits that operate when the power voltage VCC is applied thereto. The mirroring circuit  110 , the comparison circuit  120 , the current driving circuit  130 , and the internal circuit  300  may receive the power voltage VCC being supplied from the same voltage source. For example, the internal circuit  300  may include a page buffer unit. 
         [0025]    A method of operating the current generation circuit  100  is described below in detail. 
         [0026]      FIGS. 2A and 2B  are circuit views illustrating a switching operation of the current generation circuit  100  shown in  FIG. 1 . 
         [0027]    Referring to  FIG. 2A , when the current generation circuit  100  operates in a sample mode, the first switch  111  may be turned on, and the second switch  131  may be turned off. When the first switch  111  is turned on, the capacitor  112  may be charged by using the first voltage V1 generated from the voltage generation circuit  200 . In order to differentiate the first voltage V1, which is generated by the voltage generation circuit  200 , from the voltage charged in the capacitor  112 , the voltage charged in the capacitor  112  may be defined as a second voltage V2. When the capacitor  112  is charged with the second voltage V2, the second voltage V2 may also be input to the first input terminal  11  of the operational amplifier  121 . During an initial operation, since the second input terminal  12  of the operational amplifier  121  is in a floating state, when the second voltage V2, which is a positive voltage, is applied to the first input terminal the operational amplifier  121  may output a high-level voltage. However, since the second switch  131  is turned off, a gate of the driver  132  may be in a floating state. Therefore, when the current generation circuit  100  operates in the sample mode, a current path may not be established between the power voltage VCC terminal of the current driving circuit  130  and the internal circuit  300 . 
         [0028]    Referring to  FIG. 2B , when the current generation circuit  100  operates in the hold mode, the first switch  111  may be turned off, and the second switch  131  may be turned on. When the first switch  11  is turned off, the first voltage V1, which is generated by the voltage generation circuit  200 , may not be transferred to the operational amplifier  121 . Therefore, the operational amplifier  121  may be affected by the second voltage V2 charged in the capacitor  112 , but not by the voltage generation circuit  200 . The second voltage V2 may be applied to the first input terminal I1 of the operational amplifier  121 , and a voltage, which is output to an output terminal of the operational amplifier  121 , may be fed back to the second input terminal  12  thereof. Since the voltage, which is output from the operational amplifier  121 , has a high voltage level substantially the same as the level of the second voltage V2, the operational amplifier  121  may keep outputting a high-level voltage. Since the second switch  131  is turned on, the voltage, which is output from the operational amplifier  121 , may be applied to the gate of the driver  132 . The voltage, which is output from the operational amplifier  121 , may be defined as a third voltage V3 for convenience of illustration. Since the third voltage V3 has a high voltage level (i.e., a positive voltage), the driver  132  may be turned on. When the driver  132  is turned on, the driver  132  may form a current path CP. 
         [0029]    When the current path CP is formed, the internal circuit  300  may receive the output current of the current driving circuit  130  and the power voltage VCC, and perform various operations. A description is made in reference to an example in which the internal circuit  300  is a page buffer unit. 
         [0030]    The page buffer unit may include a plurality of page buffers. Therefore, when the page buffers operate at the same time, a voltage level of the power voltage VCC may be temporarily reduced. The temporary reduction in power voltage level may be referred to as a voltage drop. Since the mirroring circuit  110  and the current driving circuit  130  of the current generation circuit  100  receive the same power voltage VCC applied to the internal circuit  300 , when the voltage level of the power voltage VCC being applied to the internal circuit  300  is temporarily reduced, the voltage level of the power voltage VCC being applied to the mirroring circuit  110  and the current driving circuit  130  may also be temporarily reduced. 
         [0031]    When the voltage level of the power voltage VCC applied to the voltage mirroring circuit  110  is temporarily reduced, the voltage level of the second voltage V2 being applied to the first node N1 may also be temporarily reduced by coupling effect of the capacitor. When the level of the voltage, which is applied to the first input terminal I1, is temporarily reduced to be lower than that of the voltage, which is applied to the second input terminal  12  of the operational amplifier  121 , due to the temporary reduction in the voltage level of the second voltage V2, the third voltage V3 may also be temporarily reduced. 
         [0032]    The voltages applied to the gate and the drain of the driver  132 , which is included in the current driving circuit  130 , may be temporarily reduced at the same time since the current driving circuit  130  also receives the same power voltage VCC applied to the mirroring circuit  110  and the internal circuit  300 . In other words, when the voltage level of the power voltage VCC is temporarily reduced by operations of the internal circuit  300 , since the voltage applied to the gate of the driver  132  as well as the drain thereof is also temporarily reduced, a level difference may not occur between the gate and the drain of the driver  132 . As a result, variations in the amount of current flowing through the current path CP may be prevented. For example, when the current, which is generated by the current generation circuit  100 , is used as a reference current in the internal circuit  300 , a reference current having a constant voltage level may be generated regardless of variations in the power voltage VCC. Accordingly, reliability of the current generation circuit  100  may be improved. 
         [0033]      FIG. 3  is a timing diagram illustrating an operation of the current generation circuit  100  shown in  FIGS. 1 ,  2 A and  2 B. 
         [0034]    Referring to  FIG. 3 , it is assumed that the current generation circuit  100  operates in the hold mode. 
         [0035]    When the current generation circuit  100  operates the hold mode, the first switch  111  of the mirroring circuit  110  may be turned off, and the second switch  131  of the current driving circuit  130  may be turned on, so that the current driving circuit  130  may form the current path CP by the second voltage V2 charged in the capacitor  112 . 
         [0036]    Meanwhile, when the internal circuit  300  operates, the voltage level of the power voltage VCC, which is output from the same voltage source, may be temporarily reduced. For example, the voltage levels of the power voltage VCC being supplied to the internal circuit  300 , the power voltage VCC being supplied to the current driving circuit  130 , and the power voltage VCC being supplied to the mirroring circuit  110  may be temporarily reduced. In the mirroring circuit  110 , when the voltage level of the power voltage VCC is reduced by mirroring (MR), the voltage level of the second voltage V2 may be reduced by coupling effect of the capacitor. In the comparison circuit  120 , the voltage level of the third voltage V3 may be reduced. The current driving circuit  130  may operate based on the power voltage VCC and the third voltage V3. Since the voltage levels of the power voltage VCC and the third voltage V3 are temporarily reduced at the same time, a constant current may be generated by maintaining the constant current path CP formed by the driver  132 . 
         [0037]    As described above, even when the voltage level of the power voltage VCC is temporarily reduced while the internal circuit  300  is operating, the current generation circuit  100  may generate a constant current and apply the constant current to the internal circuit  300 . As a result, the reliability of various operations of the internal circuit  300  may be improved. 
         [0038]      FIG. 4  is a block diagram of a semiconductor device including the current generation circuit  100  shown in  FIG. 1 . 
         [0039]    Referring to  FIG. 4 , the semiconductor device  1000  may include a memory cell array  1100 , peripheral circuits  100 ,  200 ,  1300 ,  1400 ,  1500  and  1600  and a control circuit  1200 . The memory cell array  1100  may store data. The peripheral circuits  100 ,  200 ,  1300 ,  1400 ,  1500  and  1600  may program the memory cell array  1100  with data, or read or erase the stored data. The control circuit  1200  may control the peripheral circuits  100 ,  200 ,  1300 ,  1400 ,  1500  and  1600 . 
         [0040]    The memory cell array  1100  may include a plurality of memory blocks in which data is stored. The memory blocks may have similar configurations and include two-dimensional or three-dimensional structured cell strings. 
         [0041]    The control circuit  1200  may output operating signals PGM, READ and ERASE, a row address RADD, a column address CADD and page buffer control signals PBSIG in response to a command signal CMD and an address ADD. 
         [0042]    The current generation circuit  100  may include a mirroring circuit and form the current path CP based on the power voltage VCC and the first voltage V1. The constant current path CP may be formed even when the voltage level of the power voltage VCC is temporarily reduced, thereby generating a current having a constant level. 
         [0043]    The voltage generation circuit  200  may generate operating voltages Vpgm, Vread and V1 in response to the operating signals PGM, READ and ERASE. For example, when a program signal PGM applied to the voltage generation circuit  200 , the voltage generation circuit  200  may generate voltages (Vpgm) for a program operation in response to the program signal PGM. 
         [0044]    The row decoder  1300  may select one of the memory blocks, which is included in the memory cell array  110 , and may transfer operating voltages to word lines WL of a selected memory block in response to the row address RADD. 
         [0045]    The page buffer unit  1400  may be coupled to the memory cell array  1100  through bit lines BL and transfer data to the memory cell array  1100  or receive the data, which are stored in the memory cell array  1100 , in response to the page buffer control signals PBSIG. In addition, the page buffer unit  1400  may receive a constant current (e.g., reference current), which is generated by the current generation circuit  100 , during a read or verification operation and perform a sensing operation using the constant current. 
         [0046]    The column decoder  1500  may be coupled to the page buffer unit  1400  through column lines CL and transfer data to each of the page buffers in response to a column address CADD. 
         [0047]    The input/output circuit  1600  may be coupled to the column decoder  1500  through input/output lines IL and exchange input/output data IQ with the column decoder  1500 . 
         [0048]    As described above, the current generation circuit  100  of the semiconductor device  1000  may generate a constant current and may transfer the constant current to the page buffer unit  1400 . However, the current generation circuit  100  may be coupled to other circuits requiring the constant current, in addition to the page buffer unit  1400 . 
         [0049]      FIG. 5  is a block diagram illustrating a memory system including the semiconductor device shown in  FIG. 4 . 
         [0050]    Referring to  FIG. 5 , the memory system  2000  may include a memory control unit  2100 , a memory interface  2200 , and a memory storage unit  2300 . 
         [0051]    The memory control unit  2100  may apply control signals CONSIG to the memory interface  2200  through a plurality of pins in response to an external command that is input through a system bus. For example, the memory control unit  2100  may apply the control signals CONSIG to the memory interface  2200  through address pins, a chip enable signal pin, a selection signal pin, an output enable signal pin, a reset signal pin, a write enable signal pin a write inhibit signal pin a clock signal pin, and an address effective input signal pin. In addition, the memory control unit  2100  may exchange data DQ with the memory interface  2200  through data pins. 
         [0052]    The memory interface  2200  may exchange the data DQ with the memory storage unit  2300  by applying interface signals IFSIG including the command signal and the address to the memory storage unit  2300  in response to the control signals CONSIG. 
         [0053]    The memory storage unit  2300  may include the semiconductor device  1000  in which data is stored. The semiconductor device  1000  may perform program, read, and erase operations in response to the interface signals IFSIG. The semiconductor device  1000  may include a current generation circuit configured to generate a constant current despite temporary changes in the power voltage VCC. Since the semiconductor device  1000  uses a constant current, which is generated by the current generation circuit, during a read operation or a verification operation, the reliability of the semiconductor device  1000  may be improved. Therefore, the reliability of the memory storage unit  2300  having the semiconductor device  1000  with the improved reliability may also be improved, and the memory system including the memory storage unit  2300  may also be improved correspondingly. 
         [0054]    According to the embodiments of the present invention, since a current (e.g., reference current) having a constant level may be generated regardless of temporary changes in power voltage, reliabilities of a semiconductor device and a memory system performing read and verification operations may be improved. 
         [0055]    In the drawings and specification, typical exemplary embodiments of the invention have been disclosed. Although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. As for the scope of the invention, it is to be set forth in the following claims. Therefore, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Technology Category: 3