Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 12/002,829, filed Dec. 18, 2007, U.S. Pat. No. 7,859,916. This application is incorporated by reference herein in its entirety and for all purposes. 
    
    
     TECHNICAL FIELD 
     Embodiments of the present invention relate generally to integrated memory devices, and more specifically, in one or more embodiments, to an input buffer that can operate in a symmetrical manner despite receiving a single-ended input signal rather than complementary input signals. 
     BACKGROUND 
     Input buffers are used for a wide variety of functions in integrated circuits. Buffers generally have a high input impedance to avoid excessively loading circuits to which they are connected, and, conversely, have a low output impedance to drive electrical circuits without excessive loading. Buffers are typically used in digital circuits to condition electrical signals applied to internal circuitry so that internal signals are generated with well-defined logic levels and transition characteristics. For example, buffers may be utilized for coupling command, address and write data signals from respective buses in a memory device, such as a dynamic random access memory (“DRAM”) and a synchronous dynamic random access memory (“SDRAM”), so that clean, unambiguous signals are properly received by various components of the memory device. 
     Input buffer circuits may be used to convert high speed, small swing input signals to digital signals, such as signals required by internal circuitry in memory devices. Differential input buffers conventionally include differential amplifiers, which are symmetrically structured and typically have a differential pair of input terminals and/or output terminals. The symmetrical topography of these differential amplifiers causes them to operate in a symmetrical manner when they receive complementary signals. Differential input buffers are particularly useful in digital circuits for determining whether a single input signal is above a fixed reference voltage, signifying a logic “1” or below the fixed reference voltage, signifying a logic “0”. However, in such cases, the input buffers receive a single input signal rather than two complementary input signals. This lack of symmetry in applying signals to the input buffers can cause them to operate in a non-symmetrical manner. As a result, they may not respond to an input signal transitioning from a first level to a second level in the same manner that they respond to an input signal transitioning from the second level to the first level. Moreover, input buffers respond faster to a differential input and hence, can be used at higher frequencies for differential inputs. 
     There is, therefore, a need for an input buffer that operates more symmetrically when receiving a single-ended input signal so that it responds to transitions of the input signal in one direction in the same manner that it responds to transitions of the input signal in the opposite direction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic of a differential input buffer circuit according to an embodiment of the invention. 
         FIG. 2  is signal diagram showing input and output signals of the differential input buffer circuit of  FIG. 1 . 
         FIG. 3  is a functional block diagram illustrating a memory device that includes at least one differential input buffer circuit according to an embodiment of the invention. 
         FIG. 4  is a functional block diagram illustrating a computer system including the memory device of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
     One embodiment of a differential input buffer  100  is shown in  FIG. 1  that includes a pair of differential amplifiers  101 ,  102 . The amplifiers  101 ,  102  are connected in parallel between a PMOS transistor  105  coupled to a supply voltage V CC  and an NMOS transistor  108  coupled to ground GND. The PMOS transistor  105  is turned ON by an active low ENABLE control signal that also turns ON the NMOS transistor  108  by coupling the ENABLE signal to the gate of the NMOS transistor  108  through an inverter  107 . When turned ON, the transistor  105  functions as a current source providing a constant current to the amplifiers  101 ,  102  at a node  106 , and the transistor  108  functions as a current sink to discharge a constant current from the amplifiers  101 ,  102  at a node  109 . 
     The amplifiers  101 ,  102  have essentially the same components, but are configured complementary with respect to each other. The amplifier  101  includes a pair of PMOS transistors  116 ,  118  whose gates are coupled to each other in a manner such that their gate-to-source voltages are the same. Therefore, the transistors  116 ,  118  have the same ON-resistance (source-to-drain/drain-to-source resistance). The drains of the transistors  116 ,  118  are respectively coupled to the drains of NMOS transistors  120 ,  122 , whose gates are configured to receive input terminals to the buffer  100 . The gate of the transistor  120  receives an input signal V IN , and the gate of the transistor  122  receives a reference signal V REF  that is applied to a node  103 . The drain of the transistor  116  is additionally coupled to an output node  110 . The sources of the transistors  120 ,  122  are coupled to each other and to the drains of NMOS transistors  124 ,  126  such that when the ON-resistance of the transistors  124 ,  126  change, subsequently changing the voltage at the sources of the transistors  120 ,  122 . Since the amplifier  102  has a topology that is complementary to the topology of the amplifier  101 , the amplifier  102  includes a pair of NMOS transistors  144 ,  146  whose gates are coupled to each other and to the drain of the transistor  146 . The sources of the transistors  144 ,  146  are coupled to the node  109  to be coupled to GND when the transistor  108  is turned ON. The drains of the transistors  144 ,  146  are respectively coupled to the drains of PMOS transistors  140 ,  142 . The output node  110  is similarly coupled between the drain of the transistor  144  and the drain of the transistor  140 . Like the transistors  120 ,  122 , the input signals to the buffer  100  are received by the gates of the PMOS transistors  140 ,  142 . The sources of the transistors  140 ,  142  are coupled to the drains of PMOS transistors  132 ,  134 . Similarly, the gate of the transistor  132  is coupled to the gates of the transistors  144 ,  146 . 
     The amplifiers  101 ,  102  as explained so far are conventional, and they are coupled to each other in a conventional manner. However, in contrast to the prior art, the amplifier  101  includes capacitively coupling the gate of the transistor  120  to the gates of the transistors  116 ,  118 ,  124  at node  111 , such as by a coupling capacitor  152 . Similarly, the gate of the transistor  140  may be capacitively coupled to the gates of the transistors  132 ,  144 ,  146  at node  113 . In a similar manner, a coupling capacitor  153  may be used to represent capacitively coupling the node  113  to the gate of the transistor  140 . These capacitors  152 ,  153  couple transitions of the input signal V IN  to the nodes  111  and  113 , respectively. As explained in greater detail below, this capacitive coupling makes the amplifiers  101 ,  102  operate in a substantially symmetrical manner because they mimic the operation of the amplifiers  101 ,  102  as if complementary signals were applied to the amplifiers  101 ,  102 . 
     The V DIFF  signal may be further refined by propagating the output signal through an output unit  155  coupled to the output node  110 . The output unit  155  may include a series of inverters,  157 A-C, that incrementally condition the voltage V DIFF  at each stage to generate a desired output signal V OUT . 
     As previously described, the V IN  signal swings between high and low voltage levels within a particular range for which the input buffer  100  is designed. In operation, when the magnitude of V IN  transitions to a voltage level that is lower than the voltage level of the reference voltage V REF , the transistor  120  is turned OFF, and the transistor  140  is turned ON. Turning ON the transistor  140  decreases its ON-resistance to pull the magnitude of a V DIFF  signal at the output node  110  towards V CC . Since the source terminals of the transistors  140 ,  142  are connected, the gate-to-source voltage of the transistor  142  decreases due to voltage at the source terminal decreasing and the V REF  remaining constant, thus the ON-resistance of the transistor  142  increases. Consequently, the voltage at the node  113  decreases. However, due to coupling the V IN  signal to the node  113  through the coupling capacitor  153 , the voltage at the node  113  is further decreased responsive to the V IN  signal transitioning low, thereby decreasing the ON-resistance of the transistor  132  and increasing the ON-resistance of the transistors  144 ,  146  at a faster rate to further pull the output node  110  towards V CC  at the faster rate. By coupling a portion of the V IN  signal through the capacitor  153 , the voltage node  113 , which responds to the gate-to-source voltage change of the transistor  142 , changes as if the V REF  input is transitioning in the opposite direction relative to the transition of the V IN  signal. Therefore, the amplifier  102  operates as if it receives complementary input signals despite the V REF  input at node  103  remaining constant. 
     Due to the high ON-resistance of the transistor  120  in the amplifier  101 , the transistor  120  is essentially turned off. Therefore, the source terminal voltages of the transistors  120 ,  122  are low since the source terminal of the transistor  122  is coupled to GND through the transistor  126 . Thus the gate-to-source voltage of the transistor  122  is increased to decrease the ON-resistance of the transistor  122 , which is opposite to the increased ON-resistance of the transistor  120  due to V IN  transitioning low. Consequently, the magnitude of the voltage at the node  111  decreases and further enables the transistors  116 ,  118  while disabling the transistor  124 . As the V IN  signal transitions lower, the feedback from the coupling capacitor  152  further drains the node  111 , which decreases the ON-resistance of transistors  116 ,  118  at a faster rate. Consequently, the magnitude of the V DIFF  signal at the output node  110  is further pulled towards V CC  by the amplifier  101 . 
     The operation of the amplifiers  101 ,  102  is opposite to that described operation above when the V IN  signal transitions high. As the voltage of V IN  increases, the ON-resistance of the transistor  120  in the amplifier  101  decreases and the transistor  140  in the amplifier  102  increases. As the ON-resistance of the transistor  120  decreases, the output node  110  is pulled towards GND, thereby decreasing the magnitude of V DIFF . Consequently, the gate-to-source voltages of the transistors  122 ,  142  adjust such that the ON-resistance of the transistor  122  increases and the ON-resistance of the transistor  142  decreases due to the effects of the magnitude of V IN  increasing and the V REF  remaining constant. In response, the voltage at node  111  increases due to the higher ON-resistance of the transistor  122 . As a result, the node  111  provides a higher gate voltage to the transistors  116 ,  118 ,  124 . The higher voltage on the gate of transistor  124  decreases its ON-resistance, which further pulls the output node  110  towards GND. However, the higher voltage on the transistors  116 ,  118  increase their ON-resistances, which gradually turns them off. Additionally, a portion of the input signal V IN  is applied to the node  111  through the capacitor  152  in a manner that mimics a transition of the V REF  signal in the opposite direction of the V IN  signal, as previously described. Therefore, the amplifier  101  behaves in a symmetrical manner like a conventional differential amplifier. As a result, as the V IN  signal transitions high, the voltage at node  111  responds as if the V REF  transitions low as V IN  transitions high. Therefore, the gate voltages are provided to the transistors  116 ,  118 ,  124  at a faster rate, which causes the output signal V DIFF  to respond faster to the transition of V IN . 
     Similar to the previous operation, the voltage at node  113  increases due to the lower ON-resistance of the transistor  142  coupling the node  113  (at the drain of the transistor  146 ) to V CC  through the transistor  134 . The voltage of node  113  is increased at a faster rate due to the V IN  signal been partially fed through the coupling capacitor  153 . Thus the node  113  is driven to a higher voltage at a faster rate, which is applied to the transistors  144 ,  146  and  132 . Therefore, the ON-resistance of the transistors  144 ,  146  decrease at a faster rate and the ON-resistance of the transistor  132  increases at a faster rate, thereby further driving the output node  110  towards GND. As the input signal V IN  transitions high, the amplifiers  101 ,  102  operate to drive the V DIFF  signal towards GND. 
       FIG. 2  is a signal diagram comparing an output signal  215  of the prior art buffer without the capacitors  152 ,  153  to an output signal  225  of the buffer  100  using the capacitors  152 ,  153 . Also shown in  FIG. 2  are the input signal V IN  and the reference voltage V REF , which are the same for both the prior art buffer and the buffer  100 . In response to the input signal V IN  transitioning high at time T 1 , the output signal  225  of the buffer  100  transitions high at a time T 2  after a delay. However, the prior art buffer takes longer to generate its output signal  215 , which transitions high at a time T 3 . The buffer  100 , therefore, has a faster response time  235  than the prior art buffer by a time difference  245  (T 3 −T 2 ) due to the buffer  100  coupling a portion of the input signal V IN  to the source/drain of the V REF  input transistors  122 ,  142 . 
     The buffer  100  is illustrated in a memory device, such as a synchronous dynamic random access memory (“SDRAM”) device  300  according to embodiments of the invention. The SDRAM device  300  includes an address register  312  that receives either a row address or a column address on an address bus  314 , preferably by coupling address signals corresponding to the addresses though one embodiment of input buffers  316 . The address bus  314  is generally coupled to a memory controller (not shown). Typically, a row address is initially received by the address register  312  and applied to a row address multiplexer  318 . The row address multiplexer  318  couples the row address to a number of components associated with either of two memory banks  320 ,  322  depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks  320 ,  322  is a respective row address latch  326 , which stores the row address, and a row decoder  328 , which applies various signals to its respective array  320  or  322  as a function of the stored row address. The row address multiplexer  318  also couples row addresses to the row address latches  326  for the purpose of refreshing the memory cells in the arrays  320 ,  322 . The row addresses are generated for refresh purposes by a refresh counter  330 , which is controlled by a refresh controller  332 . 
     After the row address has been applied to the address register  312  and stored in one of the row address latches  326 , a column address is applied to the address register  312  and coupled through the input buffers  316 . The address register  312  couples the column address to a column address latch  340 . Depending on the operating mode of the SDRAM  300 , the column address is either coupled through a burst counter  342  to a column address buffer  344 , or to the burst counter  342  which applies a sequence of column addresses to the column address buffer  344  starting at the column address output by the address register  312 . In either case, the column address buffer  344  applies a column address to a column decoder  348  which applies various signals to respective sense amplifiers and associated column circuitry  350 ,  352  for the respective arrays  320 ,  322 . 
     Data to be read from one of the arrays  320 ,  322  is coupled to the column circuitry  350 ,  352  for one of the arrays  320 ,  322 , respectively. The data is then coupled through a read data path  354  to a data output register  356 . Data from the data output register  356  is coupled to a data bus  358  through data output buffers  359 . Data to be written to one of the arrays  320 ,  322  is coupled from the data bus  358  to a data input register  360  through data input buffers  361  according to an embodiment of the invention. The data input register  360  then couples the write data to the column circuitry  350 ,  352  where they are transferred to one of the arrays  320 ,  322 , respectively. A mask register  364  may be used to selectively alter the flow of data into and out of the column circuitry  350 ,  352 , such as by selectively masking data to be read from the arrays  320 ,  322 . 
     The above-described operation of the SDRAM  300  is controlled by a command decoder  368  responsive to command signals received on a control bus  370  though command input buffers  372  according to an embodiment of the invention. These high level command signals, which are typically generated by a memory controller (not shown), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. Various combinations of these signals are registered as respective commands, such as a read command or a write command. The command decoder  368  generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by each of the command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. 
     Although, the memory device illustrated in  FIG. 3  is a synchronous dynamic random access memory (“SDRAM”)  300  that includes the buffer  100  or a buffer according to another embodiment of the invention, the buffer  100  or other embodiments of a buffer can be used in other types of memory devices, as well as other types of digital devices. 
       FIG. 4  shows a computer system  400  containing the SDRAM  400  of  FIG. 3 . The computer system  400  includes a processor  402  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  402  includes a processor bus  404  that normally includes an address bus, a control bus, and a data bus. In addition, the computer system  400  includes one or more input devices  414 , such as a keyboard or a mouse, coupled to the processor  402  to allow an operator to interface with the computer system  400 . Typically, the computer system  400  also includes one or more output devices  416  coupled to the processor  402 , such output devices typically being a printer or a video terminal. One or more data storage devices  418  are also typically coupled to the processor  402  to allow the processor  402  to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices  418  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  402  is also typically coupled to cache memory  426 , which is usually static random access memory (“SRAM”), and to the SDRAM  100  through a memory controller  430 . The memory controller  430  is coupled to the SDRAM  300  through the normally control bus  370  and the address bus  314 . The data bus  358  is coupled from the SDRAM  300  to the processor bus  404  either directly (as shown), through the memory controller  430 , or by some other means. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, embodiments of the invention are not limited except as by the appended claims.

Technology Category: 5