Patent Document

FIELD OF THE INVENTION 
     The present invention relates to a method and circuit arrangement for monitoring devices which are activated by electrical pulses. 
     BACKGROUND INFORMATION 
     In motor vehicle engineering, many devices, in particular valves such as brake control valves, anti-lock brake valves, trailer brake valves and the like, are activated by electrical pulses and, in particular, pulse-width-modulated signals (referred to below as PWM signals). The control devices which are used for this purpose usually contain a program-controlled microprocessor which activates the corresponding valves via an output stage (driver circuit). 
     In safety-critical applications, such as in brake valves of motor vehicles, it is necessary to detect as quickly as possible faults which occur, such as failure of the driver circuit, line breaks, short circuits, grounding faults and similar. For this purpose, costly checking circuits are known which monitor and signal possible faults. 
     For example DE 42 15 075 C2 discusses a method for activating an electrical component with at least one microcomputer with two control inputs. Signals are transmitted unidirectionally on a first control line and bidirectionally on the second control line. The second control line is also used here as fault feedback line, and the bidirectional connection is capable of differentiating two different LOW levels, with corresponding levels being compared using a comparator and conclusions about a fault state being drawn therefrom. 
     Further monitoring circuits are discussed in German patent documents DE 197 58 101 C2, DE 42 02 601 A1, and DE 29 38 344 A1. 
     SUMMARY OF THE INVENTION 
     An object of the exemplary embodiments and/or exemplary methods of the present invention is to improve a method and a device of the type mentioned at the beginning to the effect that the most reliable possible monitoring of the activation of a device which is activated by electrical pulses is possible with low expenditure in terms of circuitry. 
     This object is achieved for the method described herein, and for the circuit arrangement described herein. 
     Advantageous refinements and developments of the exemplary embodiments and/or exemplary methods of the present invention also described herein. 
     One aspect of the exemplary embodiments and/or exemplary methods of the present invention is to evaluate the feedback of an output stage using a counter. The control device therefore transmits first electrical pulses to the output stage which activates a corresponding device, such as for example a solenoid valve, with these pulses. Pulse-width-modulated pulses are usually used here. The output of the output stage is tapped and the pulses which are tapped in this way are fed back and also counted. By comparison of the number of the first pulses and the number of the second pulses, a fast and reliable indication is obtained as to whether all the activation pulses which are transmitted to the output stage were also passed on to the device which is to be activated. 
     In a particular way, an upward/downward counter may be used, to whose upward counting input some of the pulses are applied and to whose downward counting input the other pulses are applied. In the fault-free state, the counter reading of this upward/downward counter is equal to zero, wherein it is possible to predetermine a tolerance band above which counter reading a fault is to be signaled. 
     There may be provision that the counter is reset to the counter reading zero at periodic intervals. 
     The corresponding circuit arrangement with a control device and a driver circuit has a feedback circuit which is connected to the output of the driver circuit and is connected to a counting input of a counter. The feedback circuit is constructed in a particularly simple way in the form of a voltage divider. 
     In the control device, the counter reading of the counter may be interrogated and checked by a microprocessor at regular intervals to determine whether the counter reading has a value which is to be expected. This value is dependent on how high the activation frequency is and what type of counter is used. 
     In the text which follows, the exemplary embodiments and/or exemplary methods of the present invention will be explained in more detail on the basis of two exemplary embodiments and with reference to the drawing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a basic circuit diagram of a first exemplary embodiment according to the present invention. 
         FIG. 2  shows a basic circuit diagram of a second exemplary embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The circuit arrangement according to the present invention has as device a load  1  which is to be activated and which is, for example, a solenoid valve of a brake system. This load  1  is activated by PWM signals. For this purpose, a control device  2  is provided with a microprocessor which supplies corresponding PWM signals to the load  1  via an output stage  3 . The output stage  3  has an RC element with a resistor R 1  and a capacitor C 2  as well as a transistor T 1  to whose output the load  1  is connected. A feedback circuit  4 , which contains a voltage divider with resistors R 2  and R 3  as well as a capacitor C 1 , is connected to this output, wherein one output of the feedback circuit  4  is connected to a counting input  5 . 1  of a counter  5 . 
     In addition, the counter  5  has here a second counting input  5 . 2  which receives internally in the control device  2  the PWM signals which are fed to the output stage  3 . One of the counting inputs  5 . 1  or  5 . 2  causes the counter to count upward, while the other counting input  5 . 2  or  5 . 1  brings about downward counting. As a result, for example the pulses which arrive at the counting input  5 . 2  and are therefore transmitted simultaneously to the output stage  3  are counted upward, and the pulses which arrive from the feedback circuit are counted downward at the counting input  5 . 1 . If all the pulses which are transmitted to the output stage  3  also pass back to the counting input  5 . 1  via the feedback circuit  4 , the counter reading of the counter  5  is equal to zero and is output at the counter output  5 . 3 . An interrogation circuit  6  is connected to this output  5 . 3  and signals when the interrogated counter reading has exceeded a specific predefined value. 
     The exemplary embodiment in  FIG. 2  differs from that in  FIG. 1  only in the type of counters. Two counters  5  and  7  are provided here. The first counter  5  is connected by its counting input  5 . 2  to the feedback circuit  4 , while the PWM pulses which are transmitted to the output stage  3  are applied to the second counter  7  internally in the control device  2 . Both counters  5  and  7  are compared with a comparator  8  which compares the counting contents of the two counters  5  and  7  at regular intervals. If the deviation between the counter readings of counters  5  and  7  is above a predefined limiting value, the comparator  8  also signals a fault. 
     In both exemplary embodiments it is advantageous to reset the counter reading of the counters  5  or  5  and  7  to zero at predefined time intervals. 
     In the case of the faults which are customary in motor vehicles, for example a line break, a short circuit, soldering through of the power transistor T 1  in the output stage  3  or the like, the PWM pulses which are transmitted to the output stage  3  will no longer appear at the output of the output stage  3  or will appear in a highly falsified form, with the result that faults can be quickly and easily detected. In this context it is, of course, expedient to set, at the counting input  5 . 1 , corresponding high and low levels at which a counting process is triggered. In order to avoid transit time errors of the counters and in order to avoid unnecessarily frequent fault messages owing to individual extraneous interference pulses, there is provision in both exemplary embodiments that a fault message is not output until the counter reading or the counter readings is/are outside a predetermined tolerance band.

Technology Category: 7