Patent Document

RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 61/362,895, filed Jul. 9, 2010. This application is herein incorporated by reference in its entirety for all purposes. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to a comparator-based buffer with a dual overshoot correction to improve the performance of high-gain amplifiers which drive a switched-capacitor load. 
     BACKGROUND OF THE INVENTION 
     Universally, there are product demands for electronics miniaturization, reduced power consumption, and higher performance. These demands increase the need for smaller, more efficient circuits for digital to analog and analog to digital converters. Particularly, this includes high performance, high gain amplifiers. Biomedical applications are one, nonlimiting, example. 
     High-gain amplifiers have difficulties driving large capacitor loads. They need increased bandwidth, higher slew rate, and hence larger power consumption. While there are established ways of dealing with this problem, they present disadvantages. Multiple gain stages may be used to relax the bandwidth requirement. Alternatively, buffer amplifiers can be inserted to decrease the capacitive loading of the main amplifier. 
     However, both methods increase the power consumption of the system.  FIG. 1  displays a conventional comparator-based switched-capacitor (CBSC) circuit  100  to replace amplifiers requiring large static currents with comparators employing small static currents. It includes comparator  105 , current sources  110  and  115 , switches  120  and  125 , and capacitor  130 . However, this architecture suffers from overshoot error, caused by comparator delay. To correct this error, an additional “fine” phase is required. During this phase, a low current source is used to correct the error caused by the delay. This requires additional circuitry. 
     What is needed are techniques for driving large capacitor loads with high gain amplifiers that have low power consumption and simplified circuitry. 
     SUMMARY OF THE INVENTION 
     The present invention provides an alternative approach for connecting high-gain amplifiers to sampling capacitors. Embodiments use simplified error correction techniques including a comparator-based buffer and resistor-based overshoot correction. 
     Embodiments include a buffer comprising an input terminal; an output terminal; a comparator comprising a first positive terminal, wherein the first positive terminal is connected to the input terminal; a resistor in a charging path which is between a second negative terminal of the comparator and the output terminal; a current source which supplies a current to the resister; a first switch which is connectable between the second negative terminal and the output terminal through the resister, wherein the first switch is controlled by the comparator; a second switch which is connectable between the input terminal and the output terminal, wherein the second switch in a reversed phase of the first switch is controlled by the comparator; and a third switch which resets a voltage of the first negative terminal. In another embodiment, the third switch is connectable between the second negative terminal and a desired voltage. For a further embodiment, the current source is forced to supply the current from a power supply to the resister; wherein the desired voltage is one of a ground voltage or a lower voltage than minimum value of the input terminal. In yet another embodiment, the current source is sinked to supply the current from the resister to ground; and wherein the desired voltage is a power supply voltage, or an upper voltage greater than maximum value of the input terminal. A yet further embodiment comprises at least a first phase, a second phase, and a third phase; wherein the third switch (SW 3 ) is turned on to reset a voltage of the first negative terminal in the first phase (φS=H, φ 1 =H, φ 2 =L, beginning of coarse phase), and the comparator turns on the first switch and turns off the second switch; wherein the third switch (SW 3 ) is turned off in the second phase (φS=L, φ 1 =H, φ 2 =L, post beginning of coarse phase); wherein the comparator turns off the first switch and turns on the second switch in the third phase (φS=L, φ 1 =H, φ 2 =L, fine phase). A subsequent embodiment further comprises a high gain amplifier connected to the buffer whereby a high gain buffer is formed. Other embodiments further comprise an analog to digital converter (ADC) connected to the high gain buffer; wherein the analog to digital converter comprises a switched capacitor circuit in a first stage. 
     Another embodiment includes a comparator-based buffer comprising at least a comparator; a current source; a switch (SW 1 , SW 2 ) for cancelling overshoot value of time delay of the comparator; and a resistor in a charging path, wherein the resistor generates a constant difference (VCR=RC*IS) between a negative terminal of the comparator and an output terminal of the comparator, for compensating the overshoot. An additional embodiment comprises a reset phase (φS=H, φ 1 =H, φ 2 =L, beginning of coarse phase); a coarse settling phase (φS=L, φ 1 =H, φ 2 =L, post beginning of coarse phase); and a fine settling phase (φS=L, φ 1 =L, φ 2 =H, fine phase). 
     Yet another embodiment includes a system for high gain amplifiers to drive a switched capacitor load comprising a buffer section comprising a high gain amplifier input; a current source; a comparator; at least a first switch, a second switch, and a resistor in a charging path; and an analog to digital converter (ADC) section comprising a sampling capacitor; wherein when a second phase (φ 2 ) rises, the sampling capacitor is discharged and reset to ground when a first phase rises and a third phase rises, voltage V A  resets, and output of the comparator turns on the first switch connected to the current source, when the third phase falls, the sampling capacitor charges to input voltage V in , when the voltage V A  exceeds the input voltage V in , the first switch opens and output of the high gain amplifier is connected directly to input of the sampling capacitor of the ADC through the second switch, reducing overshoot error, and when the second phase rises, charge on the sampling capacitor is delivered to the ground and an amplifier of the ADC. 
     A further embodiment includes a method for high gain amplifiers to drive a switched capacitor load, the method comprising the steps of discharging at least one sampling capacitor when a second phase Φ 2  rises; resetting voltage V A , and turning on at least a first switch by a comparator output when a first phase Φ 1  and a third phase ΦS rise; charging the sampling capacitor to V in  when the third phase ΦS falls; opening the first switch when the voltage V A  exceeds the V in ; and delivering charge of the at least one sampling capacitor to virtual ground and an amplifier of an analog to digital converter (ADC) section when the second phase Φ 2  rises. In another embodiment, the voltage V in  is input voltage to the high gain amplifier. For a further embodiment, the voltage V A  is a voltage at a negative input to the comparator. In yet another embodiment, the first phase Φ 1  is an input sampling clock phase for the at least one sampling capacitor. For other embodiments, the second phase Φ 2  is a holding clock phase for the at least one sampling capacitor. In a subsequent embodiment, the third phase ΦS is a short pulse. In an additional embodiment, the short pulse third phase ΦS is synchronized with the first phase Φ 1 . For further embodiments, the step of charging comprises opening at least a third switch between a node of the voltage V A  and a ground. Other embodiments provide that the step of opening the first switch comprises connecting output of amplifier directly to the sampling capacitor through a second switch whereby overshoot error is reduced. A yet further embodiment provides that the at least a first switch is connected between a current source and resistor and a voltage V B  node. 
     The features and advantages described herein are not all-inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and not to limit the scope of the inventive subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a conventional comparator-based switched-capacitor circuit. 
         FIG. 2  is a comparator-based buffer configured in accordance with one embodiment of the present invention. 
         FIG. 3  is a graph depicting coarse and fine charge transfer phases of the output correction system configured in accordance with one embodiment of the present invention. 
         FIG. 4  is a comparator schematic configured in accordance with one embodiment of the present invention. 
         FIG. 5  is a graph depicting transient simulation results configured in accordance with one embodiment of the present invention. 
         FIG. 6  is a flow chart of a method for high gain amplifiers to drive a switched capacitor load configured in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description provides example embodiments of the presently claimed invention with references to the accompanying drawings. The description is intended to be illustrative and not limiting the scope of the present invention. Embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention. Other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. Drawings are not necessarily to scale; the emphasis is to illustrate the principles of the invention. 
     A comparator-based buffer with a dual overshoot correction improves the performance of high-gain amplifiers which drive a switched-capacitor load. Effectiveness of the invention is demonstrated by simulations. 
       FIG. 2  depicts an embodiment of a comparator-based buffer  200 . Its clock uses three phases, Φ 1   205 , Φ 2   210 , and ΦS  215 . When Φ 1  equals 1  230 , this is a sampling phase of input sampling capacitor C S    225  of ADC  270 , and sampling capacitor C S    225  is connected to the node of the voltage V B  AT  285 . When Φ 2  equals 1  220 , this is a holding phase of input sampling capacitor C S    225  of ADC  270 , and sampling capacitor C S    225  is connected to amplifier  280  of ADC  270 . ΦS  215 , which comprises a short pulse  235 , synchronizes with Φ 1   205 . 
     When Φ 2  equals 1  220 , sampling capacitor C S    225  is discharged, and reset to ground. 
     When Φ 1  rises  230  and OS rises  235 , switch SW 3    295  connects to ground, voltage V A    260  resets in a short time, and comparator  240  output turns on switch SW 1    245  connected to current source  250 . At this time, resistor R C    290  connects between the node of the voltage V A    260  and the node of the voltage V B    285 . 
     When ΦS falls, switch SW 3    295  opens and sampling capacitor C S    225  starts to charge up to input voltage V in    255 . 
     This operation ends when voltage V A    260  exceeds V in    255 , and SW 1    245  opens. At this time, output of amplifier  265  (V in    255 ) is connected directly to input sampling capacitor C S    225  of ADC  270  through switch SW 2    275 , to reduce the overshoot error. 
     Finally, when Φ 2   210  rises  220 , the charge on C S    225  is delivered into the virtual ground and connected to amplifier  280  of ADC  270 . 
     Current source  250  connects between resistor R C    290  and a power supply which is forced to supply a current to the resister Rc  290 . Switch SW 3    295  connects to ground or a lower voltage than the minimum value of V in . 
     In another embodiment of a comparator-based buffer  200 , current source  250  connects between resistor R C    290  and ground, which is sinked to supply a current from resister R C    290 . Switch SW 3    295  connects to the power supply voltage or an upper voltage greater than the maximum value of V in . 
     Embodiments require only a short time for the fine charge transfer, and hence comparator  240  can be optimized by proper trade-off between time delay and power consumption. In addition, the correction will be accurate, because of the direct connection between amplifier  280  and sampling capacitor  225 . 
     Embodiments comprise a resistor-based overshoot correction solution. To reduce the overshoot of V B    285 , a simplified correction approach is used. As mentioned, for other known approaches an additional reference voltage or switched-capacitor circuitry are used. In these other schemes, the error voltage is modeled by an input offset voltage of the comparator, and partially cancelled by a negative input voltage to decrease the swing requirements in the fine correction phase. In embodiments of the invention, a resistor R C    290  is placed in the charging path ( FIG. 2 ). 
       FIG. 3  is a graph  300  depicting the resulting voltages for coarse  305  and fine  310  charge transfer phases of the output correction system. It presents values for V A    315 , V B    320 , and Comp.  325 . Due to R C  ( FIG. 2 ,  290 ), there is a constant difference V CR    330  between V A    315  and V B    320  during the coarse phase. V CR =R C ·I S  and compensates for the overshoot caused by the comparator delay. 
     By choosing R C =t d /C S , where t d  is the time delay of comparator ( FIG. 2 ,  240 ), the overshoot of V B    320  can be cancelled. Since t d  can only be estimated from simulations and is signal-dependent, for embodiments the fine correction phase will still be needed, but it can be much shorter than without inserting R C . 
       FIG. 4  provides an embodiment  400  of the comparator circuit used in simulations using the SPICE-class circuit simulator Spectre®. Spectre® is a registered trademark of Cadence Design Systems, Inc. Corporation, Delaware. 
       FIG. 5  is a graph  500  depicting transient simulation results for an embodiment. The circuit of  FIG. 2  was simulated using Spectre®. Selected values comprise C S =3 pF, a settling time of 330 ns, and I S =9 pA. The comparator shown in  FIG. 4  was used. Simulations indicated an average delay t d =2.17 ns for this stage. Since the on-resistance of switch SW 1  ( FIG. 2 ,  245 ) is 1.4 kΩ, R C =5.5 kΩ was chosen. The output impedance of the high-gain amplifier was assumed to be 40 kΩ. VDD was 1.2 V. The graph shows the simulated transient of V B  without correction  505  and with the correction  510  provided by R C . After the coarse phase, the corrected output is very close to V in    515 , and the amplifier only needs to provide a small voltage change during the fine correction phase. However, for the uncorrected scheme, the fine phase is not long enough to correct for the overshoot voltage. 
       FIG. 6  is a flow chart  600  of an embodiment of the method for high gain amplifiers to drive a switched capacitor load. Steps comprise discharging sampling capacitor C S  when Φ 2 =1  605 ; turning on switch SW 1  by comparator output when Φ 1  and ΦS rise  610 ; charging sampling capacitor C S  to V IN    615 ; opening switch SW 1  when V A  exceeds V IN    620 ; and delivering sampling capacitor charge to virtual ground when Φ 2  rises  625 . 
     Table 1 summarizes simulation results with various input voltages for the corrected and the uncorrected outputs. They are found at the end of the fine phase. The error of the corrected circuit is much smaller than that of the uncorrected one. 
     
       
         
               
               
               
             
               
               
               
             
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 Error voltage [mV] 
                   
               
             
          
           
               
                 V in  [V] 
                 corrected 
                 uncorrected 
               
               
                   
               
             
          
           
               
                 0.4 
                 15.7 
                 39.7 
               
               
                 0.5 
                 12.3 
                 33.4 
               
               
                 0.6 
                 8.4 
                 28.5 
               
               
                 0.7 
                 5.2 
                 24.1 
               
               
                 0.8 
                 2.4 
                 20.3 
               
               
                   
               
             
          
         
       
     
     The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Technology Category: 5