Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Taiwan Application Series Number 104129275 filed on Sep. 4, 2015, which is incorporated by reference in its entirety. 
     BACKGROUND 
     The present disclosure relates generally to ripple suppressors providing driving current, and more particularly to methods and ripple suppressors that could prevent a power transistor providing driving current from operating in a linear region. 
     In view of its high efficiency and low power consumption, light emitting diode (LED) has been widely adapted as a lighting source in daily life. In consideration of fabrication cost, the circuit for driving LED usually employs only one single stage of a power-factor-correction (PFC) power convertor. Standing alone, a PFC power converter is well known to have a considerably high output current ripple. One common solution to reduce this output current ripple is shunt at the output of a PFC power converter a capacitor of very large capacitance, which normally is an electrolyte capacitor. As known in the art, electrolyte capacitors are bulky in size and short in life span, and not welcome by modern LED products, which are usually requested to be compact and durable. 
     In order to avoid using an electrolyte capacitor, ripple suppressors are proposed to stabilize the current through LEDs.  FIG. 1  demonstrates a LED system  10  including a bridge rectifier  12 , a buck converter  14 , a LED chain  16 , and a ripple suppressor  18 , configuration of which is shown therein. Buck converter  14  could provide PFC and constant average output current control as well.  FIGS. 2A and 2B  illustrate two ripple suppressors  18   a  and  18   b  in the art, each having a power NMOS transistor (Mna or Mnb). The gate voltage of the power NMOS transistor in each of  FIGS. 2A and 2B  results from low-passing the drain voltage of the power NMOS transistor. As the gate voltage should be stable, the drain-to-source current I DS  of the power NMOS transistor, which flows through the path under the gate of the power NMOS transistor and is substantially equal to the current through the LED chain  16 , is proximately constant, suppressing ripples of the drain-to-source current I DS . 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted. 
       The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  demonstrates a LED system; 
         FIGS. 2A and 2B  illustrate two ripple suppressors in the art; 
         FIG. 3  demonstrates another ripple suppressor; 
         FIG. 4  demonstrates waveforms of the output voltage V OUT , the drain voltage V D  and the gate voltage V G  of the ripple suppressor in  FIG. 1 ; 
         FIG. 5  shows a ripple suppressor according to embodiments of the invention; 
         FIG. 6  demonstrates how peaks and valleys are affected by variation of divisor N; 
         FIG. 7  demonstrates another ripple suppressor according to embodiments of the invention; 
         FIGS. 8A and 8B  demonstrates two ripple suppressors according to embodiments of the invention; and 
         FIGS. 9A to 9C  demonstrate three ripple suppressors according to embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The ripple suppressors  18   a  and  18   b  in  FIGS. 2A and 2B  are supposed to have the power NMOS transistors Mna and Mnb operate ideally in a saturate region. An idea NMOS transistor, if operating in a saturate region, has a drain-to-source current I DS  independent to drain-to-source voltage V DS . The power NMOS transistors Mna and Mnb are expected to be as ideal as possible. Nevertheless, cost increases for the process of making a power NMOS transistor more ideal. 
       FIG. 3  demonstrates another ripple suppressor  18   d , including a resistor Rf, a low-pass filter  22 , a divider  24 , and a voltage-controlled current source  26 , wherein resistor Rf is optional and could be omitted in  FIG. 3  and some of the embodiments in the following drawings. It doesn&#39;t matter to the performance of suppressing current ripple how ideal the power NMOS transistor Mnd in the ripple suppressor  18   d  is. The low-pass filter  22  has a transconductance comparator  28  and a capacitor CF, low passing the drain voltage V D  to generate an average voltage V AVG  as an output. The divider  24  divides the average voltage V AVG  by a divisor N to generate a current-setting signal V SET . The low-pass filter  22  and the divider  24  are deemed together to be a stabilizer for generating and stabilizing the current-setting signal V SET . The voltage-controlled current source  26  has a power NMOS transistor Mnd, an operational amplifier OP 1  and a current-sense resistor Rs. The operational amplifier OP 1  outputs a gate voltage V G  to the gate of the power NMOS transistor Mnd, and has two inputs coupled to receive the current-setting signal V SET  and the current-sense signal V S , respectively. The voltage-controlled current source  26  provides a negative feedback, intending to make the current-sense signal V S  equal to the current-setting signal V SET . When the power NMOS transistor Mnd is operating in a saturate region, the drain-to-source I DS  is substantially constant, having a value equal to the voltage of current-setting signal V SET  divided by the resistance of current-sense resistor Rs, and variation of the drain-to-source voltage V DS  could have no impact to the drain-to-source I DS . 
       FIG. 4  demonstrates waveforms of the output voltage V OUT , the drain voltage V D  and the gate voltage V G  of the ripple suppressor  18  in  FIG. 1 . In case that the output capacitor COUT in  FIG. 1  has its capacitance reduced, the waveforms of the output voltage V OUT , the drain voltage V D  and the gate voltage V G  could change from the left half of the  FIG. 4  to the right half. As the capacitor COUT decreases, amplitude of the vibration of the output voltage V OUT  enlarges.  FIG. 4  demonstrates at the right half some shadowed areas  29 , where the drain voltage V D  is too low and causes the power NMOS transistor Mnd in the voltage-controlled current source  26  to operate in a linear region instead of in a saturate region. As a result, the drain-to-source I DS  starts decreasing in these shadowed areas  29 , no more being held as a constant, and the luminance of the LED chain  16  darkens accordingly. In other words, it implies that the right half of  FIG. 4  has issues of flickering. 
       FIG. 5  shows a ripple suppressor  18   e  according to embodiments of the invention. Different from the ripple suppressor  18   d  in  FIG. 3 , the ripple suppressor  18   e  in  FIG. 5  has additionally an auto-calibration circuit  30 , which monitors the gate voltage V G  to control the divisor N used by the divider  24 , so as to make the gate voltage V G  in compliance with a predetermined condition. In  FIG. 5 , this predetermined condition is substantially confine peaks V G-PEAK  of the gate voltage V G  to the range between predetermined values V TH-HH  and V TH-HL , and restrict valleys V G-VLY  of the gate voltage V G  not to be less than a predetermined value V TH-L  as shown in  FIG. 6 . In one embodiment of the invention, predetermined values V TH-HH , V TH-HL  and V TH-L  are 10V, 8V and 3V, respectively. The predetermined values V TH-HH  and V TH-HL  are the top and bottom limits of the range, respectively. 
     The auto-calibration circuit  30  has a peak detector  40  and a valley detector  42 , monitoring the gate voltage V G  to sequentially generate peaks V G-PEAK  and valleys V G-VLY  When a present peak V G-PEAK  exceeds the predetermined value V TH-HH  the output of the comparator  36  makes the divisor controller  32  increase the divisor N of the divider  24 , so the current-setting signal V SET  decreases, causing the decrement of a next peak V G-PEAK . Similarly, if a present peak V G-PEAK  is below the predetermined value V TH-HL  the output of the comparator  35  makes the divisor controller  32  decrease the divisor N of the divider  24 , so the current-setting signal V SET  increases, causing the increment of a next peak V G-PEAK . If a present valley V G-VLY  is below the predetermined value V TH-L  the output of the comparator  34  could make the divisor controller  32  decrease the divisor N of the divider  24 , so a next valley V G-VLY  increases as a result. In one embodiment, the divisor controller  32  might increase or decrease the divisor N once every 50 ms. 
     As the time goes by, the auto-calibration circuit  30  can confine peaks V G-PEAK  of the gate voltage V G  to the range between the predetermined values V TH-HH  and V TH-HL , and restrict valleys V G-VLY  of the gate voltage V G  not to be less than the predetermined value V TH-L . 
     Keeping peaks V G-PEAK  under the predetermined value V TH-HH  is beneficial since the power NMOS transistor might operate in an unfavorable linear region if the gate voltage is high above the predetermined value V TH-HH . In other words, keeping peaks V G-PEAK  under the predetermined value V TH-HH  prevents the power NMOS transistor from operating in a region other than a saturate region. Keeping peaks V G-PEAK  above the predetermined value V TH-HL  intentionally raises the gate voltage V G  to enjoy a lower ON resistance R DS-ON  of the power NMOS transistor Mne, thereby reducing the power consumption caused by ripple suppressor  18   e . Likely, keeping valleys V G-VLY  above the predetermined value V TH-L  prevents a very low gate voltage V G  that could result in a higher ON resistance R DS-ON  of the power NMOS transistor Mne and cause the ripple suppressor  18   e  to consume much power. 
     The current-setting signal V SET  in  FIG. 5  is generated by processing the drain voltage V D  first through the low-pass filter  22  and second through the divider  24 . The low-pass filter  22  low passes the drain voltage V D  first to generate a filtered signal, which then is divided by the divisor N of the divider  24  to output the current-setting signal V SET . The low-pass filter  22  and the divider  24  are connected in cascade. This invention is not limited to  FIG. 5 , nevertheless.  FIG. 7  demonstrates another ripple suppressor  18   f  according to embodiments of the invention, where the low-pass filter  22  follows the divider  24  while the divisor controller  32  controls the divisor N used by the divider  24 . In other words, in  FIG. 7 , the divider  24  first divides the drain voltage V D  to generate an intermediate signal, which is then low passed to generate the current-setting signal V SET . The ripple suppressor  18   f  of  FIG. 7  could enjoy the same advantage with the ripple suppressor  18   e  of  FIG. 5 . 
       FIG. 8A  demonstrates another ripple suppressor  18   g  according to embodiments of the invention. The ripple suppressor  18   g  also has an auto-calibration circuit  43 , which monitors the gate voltage V G  to control the divisor N used by the divider  24 , so as to make the gate voltage V G  in compliance with a predetermined condition. In this embodiment, this predetermined condition is that an average of the gate voltage V G  is about a predetermined value V TAR , which is 6V for example. The auto-calibration circuit  40  is basically an averaging circuit with a transconductance comparator  45  and a capacitor  44 . In response to difference between the gate voltage V G  and the predetermined value V TAR , the transconductance comparator  45  charges or discharges the capacitor  44 , whose voltage, as an output, controls the divisor N of the divider  24 . 
     For example, if an average of the gate voltage V G  exceeds the predetermined value V TAR , the voltage of the capacitor  44  raises, causing the divisor N to increase, preferably once every 50 ms, so as to lower the current-setting signal V SET , and the average of the gate voltage V G  as well. In the opposite, if an average of the gate voltage V G  is below the predetermined value V TAR , the auto-calibration circuit  43  will reduce the voltage of the capacitor  44 , and both the current-setting signal V SET  and the average of the gate voltage V G  increase accordingly. The auto-calibration circuit  43  therefore makes an average of the gate voltage V G  substantially equal to the predetermined value V TAR . This achievement could prevent the power NMOS transistor Mng from wrongly operating in a linear region due to an overhigh gate voltage V G , or from inefficiently consuming too much power because of a much low gate voltage V G . 
     In  FIG. 8A , the divider  24  follows the low-pass filter  22  to generate the current-setting signal V SET , but this invention is not limited to.  FIG. 8B  demonstrates a ripple suppressor  18   h  according to embodiments of the invention, where the low-pass filter  22  follows the divider  24  to generate the current-setting signal V SET  while the auto-calibration circuit  43  controls the divisor N used by the divider  24 . 
     Each auto-calibration circuit in  FIGS. 5, 7, 8A and 8B  controls a divisor used by a divider, but the invention is not limited to.  FIGS. 9A to 9C  demonstrate three ripple suppressors  18   k ,  18   m  and  18   n , where each auto-calibration circuit  43  controls an offset voltage V OS  provided by an offset circuit  62 . Taking the ripple suppressor  18   k  for example, the low-pass filter  22 , the divider  24 , and the offset circuit  62  are connected in cascade. The offset circuit  62  is connected between the divider  24  and the voltage-controlled current source  26 , providing an offset voltage V OS  to add to the output of divider  24 . If an average of the gate voltage V G  exceeds the predetermined value V TAR , for example, the offset voltage V OS  ramps down slowly, possibly once every 100 ms, the current-setting signal V SET  reduces, so as to lower the average of the gate voltage V G , and vice versa. The ripple suppressor  18   k  therefore makes an average of the gate voltage V G  substantially equal to the predetermined value V TAR . 
     The offset circuit  62  in  FIG. 9B  is connected between the low-pass filter  22  and the divider  24 . The offset circuit  62  in  FIG. 9C  is connected between the drain of the power NMOS transistor Mnn and the low-pass filter  22 . Based on the aforementioned teaching, each of the ripple suppressors  18   m  and  18   n  in  FIGS. 9B and 9C  could also make an average of the gate voltage V G  substantially equal to the predetermined value V TAR . 
     Similarly, in some embodiments of the invention, the auto-calibration circuit  43  in each of  FIGS. 9A, 9B and 9C  could be replaced with the auto-calibration circuit  30  of  FIG. 5 . An auto-calibration circuit according to embodiments of the invention could monitor the gate voltage of a power NMOS transistor to control a divisor of a divider or an offset voltage of an offset circuit. An auto-calibration circuit could confine peaks of the gate voltage within a predetermined range, or make an average of the gate voltage equal to a predetermined value. 
     Based on the aforementioned embodiments, an auto-calibration circuit monitors the gate voltage V G  to adjust the current-setting signal V SET , so as to make the gate voltage V G  in compliance with a predetermined condition. This predetermined condition could keep a power NMOS transistor away from operating in a linear region or make the power NMOS transistor operate more efficiently. 
     While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Category: 3