Patent Document

FIELD OF THE INVENTION  
         [0001]    The present invention relates to a logic circuit which is capable of adjusting a switching threshold in accordance with the voltage level of applied input logic signals.  
         BACKGROUND OF THE INVENTION  
         [0002]    Digital logic circuits are sometimes arranged such that a first logic circuit operates with one supply voltage, e.g., 3.3 volts, while another circuit supplying input logic signals to the first logic circuit operates with a different supply voltage, e.g., 1.8 volts. In such a case, the logic signals supplied to the first logic circuit are incompatible with the switching threshold of the first logic circuit, which is set for applied input signals of 3.3 volts, causing erroneous and undesired switching operations.  
           [0003]    A simple way of adjusting a switching threshold of a logic circuit to handle input logic signals of different voltage levels is needed.  
         BRIEF SUMMARY OF THE INVENTION  
         [0004]    The present invention provides a simple way of adjusting the switching threshold of a logic circuit in accordance with the signal level of input logic signals which are applied to it.  
           [0005]    The invention provides a logic circuit with a voltage level detector stage which detects the supply voltage of a circuit supplying applied input signals, and an adaptive threshold stage which, in response to the output of the detector stage, selects a switching threshold level for switching operations in response to the applied logic input signals.  
           [0006]    The adaptive threshold stage may be formed as a CMOS inverter circuit in which certain transistors are turned on or off in response to the output of the detector stage to thereby alter the inverter switching threshold.  
           [0007]    These and other features and advantages of the invention will be more clearly seen from the following description of the invention which is provided in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1 depicts a conventional CMOS inverter circuit;  
         [0009]    [0009]FIG. 2 and FIG. 3 are timing diagrams illustrating operation of the FIG. 1 circuit;  
         [0010]    [0010]FIG. 4 depicts an adaptive threshold logic circuit in accordance with an exemplary embodiment of the invention;  
         [0011]    [0011]FIG. 5 is a timing diagram illustrating operation of the FIG. 4 circuit; and  
         [0012]    [0012]FIG. 6 depicts a processor system containing various components which may employ an adaptive threshold logic circuit of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    [0013]FIG. 1 is an electrical schematic drawing of a typical CMOS inverter  6  which switches states in response to switching states of logic signals applied to input line  33 . The inverter  6  includes a p-channel MOS transistor  12  serially connected to an n-channel MOS transistor  14 , with the serial connection of the two transistors being connected between V DD    25  and ground  27 . The CMOS inverter  6  provides inverted output logic signals on line  29  in response to the states of logic signals applied to input line  33 .  
         [0014]    The transistors  12  and  14  are configured such that when V DD  is at one voltage level, e.g., 3.3 volts, and the input logic signals on line  33  transition between voltage levels of zero and 3.3 volts, the inverted output signals on line  29  are likewise transitioning between 3.3 volts and zero volts with relatively low signal skew or waveform distortion because the switching threshold of transistors  12  and  14  is well matched to the expected zero to 3.3 volt transitions of the signals on line  33 .  
         [0015]    This is illustrated in FIG. 2 which shows that the output of inverter  6  begins to transition state in response to an input logic signal reaching a value of approximately V DD /2 on rising and falling edges of the input logic signal. In actuality, there may be a slight respective offset from V DD /2 for the switching threshold on the rising and falling edges of the input signal. In other words, the switching threshold is approximately centered between zero volts and V DD . The cycle of the output signal waveform is essentially the same as that of the input signal waveform, that is t 1 =t 2 .  
         [0016]    When, however, an input logic signal transitions between zero volts and a voltage level lower than V DD , e.g., 1.8 volts, as shown in FIG. 3, the output signal waveform is distorted because the switching threshold of inverter  6  remains at essentially V DD /2 which is not centered between zero and 1.8 volts. As a result, the duty cycle of the output signal waveform is different from the duty cycle of the applied input signal, and the output signal on line  29  is no longer a true representation of the inverted input signal on line  33 , i.e., t 1 ≠t 2 .  
         [0017]    The present invention avoids this problem and provides an adaptive logic circuit which can change the switching threshold in response to the voltage level of the applied input signal so that the output signal faithfully transitions with minimal switching threshold signal distortions in response to signal transitions of an applied input signal.  
         [0018]    For purposes of simplifying discussion, the adaptive logic circuit of the invention will be illustrated as an adaptive CMOS inverter circuit, but the invention can be applied to any logic circuit having switching thresholds.  
         [0019]    Referring now to FIG. 4, an exemplary embodiment of the invention is illustrated. A CMOS inverter  9  is illustrated as including a detector stage  11  which is formed as a threshold circuit, and a threshold adapter stage  13  which is defined to accept data from a downstream logic circuit on input line  33 , and provide an output signal on output line  29 .  
         [0020]    To accommodate different levels of possible input signal potential at input line  33 , the invention employs detector stage  11 , which may be formed as a Schmitt trigger. This is an inverter stage which has a predefined threshold which may be preset. An input to detector stage  11  is from an input line V X  which receives a voltage signal which is the supply voltage of a downstream logic circuit which provides logic signals at input line  33 . If V X  is at a level of V DD , e.g., 3.3 volts, indicating that the downstream circuit potential is at the same level as the V DD  of the threshold adaptor stage  13 , the detector stage produces a first output signal at its output. If, on the other hand, a signal at the input terminal V X  is below V DD , by a specified percentage as set as a threshold of the detector stage  11 , the detector stage produces a second output signal.  
         [0021]    The switching threshold of the detector stage  11  can be set so that the detector stage will switch when the voltage applied to the input V X  is below by a certain percentage the supply voltage V DD  of the threshold adaptor stage  13 , e.g., a voltage of 70% of V DD .  
         [0022]    The threshold adaptor stage  13  as shown in FIG. 4 includes p-channel MOS transistors  15 ,  17 ,  19 , and n-channel MOS transistors  21 ,  22 , and  23 . Transistors  15 ,  19  and  22  are connected between the voltage potential V DD    25  and ground  27 . The gates of p-channel transistors  15  and  19  are coupled together and are further coupled to the input line  33 . The gate of n-channel transistor  22  is also coupled to the input line  33 .  
         [0023]    P-channel transistor  17  is connected in parallel with the p-channel transistor  15 , and the gate of transistor  17  is connected to the output of the detector stage  11 . The connection between the serially connected transistors  19  and  22  forms a node A which is in turn connected to the output line  29 . Connected between the output line  29  and ground  27  is a pair of serially connected n-channel transistors  21  and  23 . N-channel transistor  22  is connected between node A and ground, and is also connected in parallel with the series connection of transistors  21  and  23 .  
         [0024]    The gate of transistor  23  is also connected to the output of detector stage  11 , and the gate of transistor  21  is connected to the line input  33 . Thus, adaptor stage  13  is a CMOS inverter formed by p-channel transistors  15 ,  17  and  19  and n-channel transistors  21 ,  22  and  23 . However, the switching threshold of threshold adaptor stage  13  can change depending on the on or off condition of transistors  17  and  23  which are controlled by the output of the detector stage  11 .  
         [0025]    The detector stage  11  output is either a low logic level if the signal applied to the V X  input terminal  31  exceeds the threshold of detector stage  11 , that is, is close to a voltage V DD  of the threshold adaptor stage  13 , or is at a logic high level if the signal applied to the V X  input terminal  31  is below the detector stage  11  threshold.  
         [0026]    When the output of the detector stage  11  is in a low state, transistor  23  is turned off and transistor  17  is turned on. Since transistor  23  is turned off, transistor  21  is rendered nonconductive. Transistor  15  is, in turn, bypassed by virtue of transistor  17  being on. As a result, the switching threshold for input signals on line  33  is set by the switching characteristics of transistors  19  and  22 .  
         [0027]    On the other hand, if the output of the detector stage  11  is high, meaning that the voltage at V X  is below the preset threshold then transistor  23  is turned on and transistor  17  is turned off. In this state, the switching level of adaptor stage  13  is set by the switching state established by the series connection of transistors  15  and  19  which is in series with the parallel circuit formed by transistor  22  in parallel with the series connection of transistors  21  and  23 .  
         [0028]    Transistors  17  and  21  are much larger transistors than the other transistors so that they are effectively on or off switches, so threshold adjustments in each of the two different switching threshold states can be made by selecting the switching characteristics of the remaining transistors  15 ,  19 ,  22  and  23 .  
         [0029]    Thus, depending on the voltage detected by detector stage  11 , the threshold of the threshold adaptor stage  13  can be adjusted by switching one of transistors  17  and  23  on and the other off in accordance with the output of detector stage  11  to thereby change the CMOS inverter  9  from a first threshold switching characteristic to a second threshold switching characteristic. Since the voltage on input line  31  represents the level of the logic signals applied to input line  33 , an appropriate switching threshold can be set by the threshold adaptor stage  13  so that the output signal at output terminal  29  is appropriate for the logic input signals applied at input line  33 .  
         [0030]    [0030]FIG. 5 illustrates how the threshold voltage of CMOS inverter  6  changes between a first threshold value of V DD /2 associated with input logic signals which transition between zero volts and V DD , and a second threshold value of V in /2 associated with input logic signals which transition between zero volts and V in . Transistors  15 ,  19 ,  22  and  23  are fabricated to provide these two switching thresholds depending on the on/off states of transistor  17  and  21 .  
         [0031]    [0031]FIG. 4 also shows that one detector stage  11  can control the switching threshold of a plurality of threshold adaptor stages  13 .  
         [0032]    The invention may be used in any digital logic circuit, including but not limited to gate circuits, inverters, timing circuits and in larger devices such as a DSP, programmable logic devices, processors, memory devices which include memory cell arrays and peripheral logic coupled to the array, and the like. For example, as shown in FIG. 6, a processor based system, such as a computer system, for example, generally comprises a central processing unit (CPU)  210 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices  240 ,  250  over a bus  270 . The computer system  200  also includes random access memory (RAM)  260 , a read only memory (ROM)  280  and, in the case of a computer system may include peripheral devices such as a floppy disk drive  220  and a compact disk (CD) ROM drive  230  which also communicate with CPU  210  over the bus  270 . At least one of CPU  210  and one or more integrated circuits connected thereto, such as employed for RAM  260  and ROM  280 , are preferably constructed as integrated circuits which include an adaptive threshold logic circuit as described above with respect to FIGS. 4 and 5. It may also be desirable to integrate the processor  210  and memory  260  on a single IC chip and have one or both of processor  210  and memory  260  employ the adaptive threshold logic circuit described above with reference to FIGS. 4 and 5.  
         [0033]    While an exemplary embodiment of the invention has been described and illustrated above, it should be apparent that many modification substitutions and other variations can be made without departing from the spirit or scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description and accompany drawings, and is only limited by the scope of the appended claims.

Technology Category: 5