Patent Document

CLAIM OF PRIORITY  
       [0001]     This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C.§119 from an application for PLASMA DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME earlier filed in the Korean Intellectual Property Office on 19 Oct. 2004 and there duly assigned Serial No. 10-2004-0083499.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a Plasma Display Panel (PDP), and more particularly, to a PDP that can be driven with a low voltage by differentiating thicknesses of dielectric layers that bury discharge electrodes, and its method of manufacture.  
         [0004]     2. Description of the Related Art  
         [0005]     Typically, Plasma Display Panels (PDPs) are flat display panels that display desired numbers, characters, or graphics by discharging a gas injected between two substrates each having discharge electrodes and exciting a phosphor layer using ultraviolet rays generated from the discharged gas.  
         [0006]     Such PDPs can be classified into Direct Current (DC) PDPs and Alternating Current (AC) PDPs according to patterns of waveforms of driving voltages supplied to discharge cells, for example, according to the form of discharge. Such PDPs can also be classified into opposed discharge PDPs and surface discharge PDPs according to the arrangement of electrodes.  
         [0007]     A three-electrode surface discharge PDP includes a front substrate and a rear substrate, which are arranged to face each other.  
         [0008]     X and Y electrodes are arranged on an inner surface of the front substrate in such a way that an X electrode and a Y electrode are both located within each discharge cell. The X electrode includes a first electrode line, which is transparent, and a first bus electrode, which is overlapped by the first electrode line. The Y electrode includes a second electrode line, which is transparent, and a second bus electrode, which is overlapped by the second electrode line. The X and Y electrodes are buried in a front dielectric layer. The front dielectric layer is coated with a protective layer.  
         [0009]     Address electrodes are arranged on an inner surface of the rear substrate to cross the X and Y electrodes. The address electrodes are buried in a rear dielectric layer.  
         [0010]     Barrier ribs are formed within a space between the front and rear substrates to define discharge cells. The discharge cells defined by the barrier ribs are coated with a Red phosphor layer R, a Green phosphor layer G, and a Blue phosphor layer B.  
         [0011]     Briefly looking at a process of manufacturing the PDP having the above-described structure, the X and Y electrodes are first arranged in parallel on the inner surface of the front substrate. Then, a raw material for the front dielectric layer is printed on the entire inner surface of the resultant front substrate so that the X and Y electrodes can be buried in the material. Thereafter, the front dielectric layer is formed through drying and other predetermined processes, and the protective layer is deposited on the front dielectric layer.  
         [0012]     After the address electrodes are arranged in parallel on the inner surface of the rear substrate, a raw material for the rear dielectric layer is printed on the entire inner surface of the resultant rear substrate so that the Y electrodes can be buried in the material. Thereafter, the rear dielectric layer is formed through drying and other predetermined processes.  
         [0013]     Thereafter, the barrier ribs are formed on the rear substrate, and a Red phosphor layer R, a Green phosphor layer G, and a Blue phosphor layer B are repeatedly formed on the discharge cells defined by adjacent barrier ribs.  
         [0014]     Through this process, the front and rear substrates are completed.  
         [0015]     As to the discharge characteristics of the PDP described above, because the red, green, and blue phosphor layers R, G, and B have different discharge characteristics, voltage margins Va, which are minimal address voltages required upon addressing, are different for the R. G, and B phosphor layers.  
         [0016]     For example, when the voltage V set  is 170V, an address voltage V a  of a discharge cell coated with the blue phosphor layer B is about 55V, while an address voltage V a  of a discharge cell coated with the red phosphor layer R is about 63V.  
         [0017]     In practice, at least an address voltage V a  for a discharge cell coated with a Red phosphor layer, which has the smallest voltage margin V a , must be used to drive the PDP. Thus, a driving circuit for the PDP is overloaded.  
       SUMMARY OF THE INVENTION  
       [0018]     The present invention provides a PDP which reduces a variation among voltage margins of Red, Green, and Blue phosphor layers by differentiating thicknesses of dielectric layers that bury discharge electrodes corresponding to discharge cells coated with the R, G, and B phosphor layers, thereby increasing the overall voltage margin, and a method of manufacturing the PDP.  
         [0019]     According to one aspect of the present invention, a Plasma Display Panel (PDP) is provided comprising: a first substrate; a plurality of first discharge electrodes arranged on the first substrate; a second substrate arranged opposite to the first substrate and in parallel therewith; a plurality of second discharge electrodes arranged on the second substrate to cross the first discharge electrodes, the second discharge electrodes being adapted to be addressed with the first discharge electrodes and located on different levels; barrier ribs disposed between the first and second substrates to define discharge cells; and Red (R), Green (G), and Blue (B) phosphor layers coated on lateral sides of the barrier ribs.  
         [0020]     Second discharge electrodes corresponding to discharge cells coated with R, G, and B phosphor layers are preferably different distances away from the first discharge electrodes.  
         [0021]     Second discharge electrodes corresponding to discharge cells having higher voltage margins are preferably farther from the first discharge electrodes than second discharge electrodes corresponding to discharge cells having lower voltage margins.  
         [0022]     Second discharge electrodes corresponding to discharge cells coated with R, G, and B phosphor layers are preferably buried in parts of a dielectric layer of different thicknesses.  
         [0023]     Parts of the dielectric layer that bury the second discharge electrodes corresponding to discharge cells coated with R, G, and B phosphor layers preferably have different thicknesses to differentiate intervals from the second discharge electrodes to each of the first discharge electrodes.  
         [0024]     Parts of the dielectric layer that bury the second discharge electrodes corresponding to the discharge cells having higher voltage margins are preferably thicker than parts of the dielectric layer that bury the second discharge electrodes corresponding to the discharge cells having lower voltage margins.  
         [0025]     The dielectric layer preferably becomes thinner in a direction from a part that buries the second discharge electrode corresponding to the discharge cell having the greatest voltage margin to a part that buries the second discharge electrode corresponding to the discharge cell having the lowest voltage margin.  
         [0026]     The first discharge electrodes preferably include X and Y electrodes that are alternately arranged so that a pair of X and Y electrodes are arranged within each discharge cell, and the second discharge electrodes are address electrodes preferably arranged to cross the X and Y electrodes.  
         [0027]     The address electrodes preferably include first address electrodes arranged under the discharge cells coated with a first one of the R, G, and B phosphor layers, second address electrodes arranged under the discharge cells coated with a second one of the R, G, and B phosphor layers, and third address electrodes arranged under the discharge cells coated with a third one of the R, G, and B phosphor layers; and the first, second, and third address electrodes are preferably arranged to be different distances away from the X and Y electrodes.  
         [0028]     The first address electrodes, which are arranged under the discharge cells having higher voltage margins, are preferably farther from the X and Y electrodes than the third address electrodes, which are arranged under the discharge cells having lower voltage margins.  
         [0029]     Parts of the dielectric layer that bury the first, second, and third discharge electrodes preferably have different thicknesses to differentiate intervals from the first, second, and third discharge electrodes to each of the X and Y electrodes.  
         [0030]     According to another aspect of the present invention, a method of manufacturing a Plasma Display Panel (PDP) is provided, the method comprising: arranging first discharge electrodes on a first substrate: arranging a second substrate to be opposite to the first substrate; and arranging a plurality of second discharge electrodes on the second substrate at different levels, the plurality of second discharge electrodes being adapted to be addressed by the first discharge electrodes; and forming a dielectric layer to bury the second discharge electrodes.  
         [0031]     The second discharge electrodes are preferably arranged under discharge cells coated with Red (R), Green (G), and Blue (B) phosphor layers to be different distances away from the first discharge electrodes.  
         [0032]     Second discharge electrodes corresponding to discharge cells having higher voltage margins are preferably arranged farther from the first discharge electrodes than second discharge electrodes corresponding to discharge cells having lower voltage margins.  
         [0033]     Parts of the dielectric layer that bury the second discharge electrodes arranged under the discharge cells coated with R, G, and B phosphor layers are preferably formed to have different thicknesses.  
         [0034]     Forming the second discharge electrodes and the dielectric layer preferably comprises: forming first electrodes for use as the second discharge electrodes on parts of the second substrate that are under discharge cells coated with a first one of Red (R), Green (G), and Blue (B) phosphor layers; forming a first dielectric layer to bury the first electrodes; forming second electrodes for use as the second discharge electrodes on parts of the first dielectric layer that are under the discharge cells coated with a second one of the R, G, and B phosphor layers; forming a second dielectric layer to bury the second electrodes; forming third electrodes for use as the second discharge electrodes on parts of the second dielectric layer that are under the discharge cells coated with the phosphor layers of a third one of the R, G, and B phosphor layers; and forming a third dielectric layer to bury the third electrodes.  
         [0035]     According to still another aspect of the present invention, a Plasma Display Panel (PDP) manufactured by a method is provided, the method comprising: arranging first discharge electrodes on a first substrate: arranging a second substrate to be opposite to the first substrate; and arranging a plurality of second discharge electrodes on the second substrate at different levels, the plurality of second discharge electrodes being adapted to be addressed by the first discharge electrodes; and forming a dielectric layer to bury the second discharge electrodes.  
         [0036]     The second discharge electrodes are preferably arranged under discharge cells coated with Red (R), Green (G), and Blue (B) phosphor layers to be different distances away from the first discharge electrodes.  
         [0037]     Second discharge electrodes corresponding to discharge cells having higher voltage margins are preferably arranged farther from the first discharge electrodes than second discharge electrodes corresponding to discharge cells having lower voltage margins.  
         [0038]     Parts of the dielectric layer that bury the second discharge electrodes arranged under the discharge cells coated with R, G, and B phosphor layers are preferably formed to have different thicknesses.  
         [0039]     Forming the second discharge electrodes and the dielectric layer preferably comprises: forming first electrodes for use as the second discharge electrodes on parts of the second substrate that are under discharge cells coated with a first one of Red (R), Green (G), and Blue (B) phosphor layers; forming a first dielectric layer to bury the first electrodes; forming second electrodes for use as the second discharge electrodes on parts of the first dielectric layer that are under the discharge cells coated with a second one of the R, G, and B phosphor layers; forming a second dielectric layer to bury the second electrodes; forming third electrodes for use as the second discharge electrodes on parts of the second dielectric layer that are under the discharge cells coated with the phosphor layers of a third one of the R, G, and B phosphor layers; and forming a third dielectric layer to bury the third electrodes. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0040]     A more complete appreciation of the present invention and many of the attendant advantages thereof, will be readily apparent as the present invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:  
         [0041]      FIG. 1  is an exploded perspective view of a PDP;  
         [0042]      FIG. 2  is a graph of differences among voltage margins for red, green, and blue phosphors versus V set  for the PDP of  FIG. 1 ;  
         [0043]      FIG. 3  is an exploded perspective view of a PDP according to an embodiment of the present invention;  
         [0044]      FIG. 4  is a cross-section taken along line I-I of  FIG. 3 ;  
         [0045]      FIG. 5  is a flowchart of a method of manufacturing the PDP of  FIG. 3 ;  
         [0046]      FIG. 6  is a graph of the tendencies of voltage margins in a PDP; and  
         [0047]      FIG. 7  is a graph of the tendencies of voltage margins in a PDP according to the embodiment of  FIG. 3 , as compared to that of the PDP of  FIG. 6 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0048]      FIG. 1  is an exploded perspective view of a three-electrode surface discharge PDP  100 . Referring to  FIG. 1 , the PDP  100  includes a front substrate  110  and a rear substrate  120 , which are arranged to face each other.  
         [0049]     X and Y electrodes  130  and  140  are arranged on an inner surface of the front substrate  110  in such a way that an X electrode  130  and a Y electrode  140  are both located within each discharge cell. The X electrode  130  includes a first electrode line  131 , which is transparent, and a first bus electrode  132 , which is overlapped by the first electrode line  131 . The Y electrode  140  includes a second electrode line  141 , which is transparent, and a second bus electrode  142 , which is overlapped by the second electrode line  141 . The X and Y electrodes  130  and  140  are buried in a front dielectric layer  150 . The front dielectric layer  150  is coated with a protective layer  160 .  
         [0050]     Address electrodes  170  are arranged on an inner surface of the rear substrate  120  to cross the X and Y electrodes  130  and  140 . The address electrodes  170  are buried in a rear dielectric layer  180 .  
         [0051]     Barrier ribs  190  are formed within a space between the front and rear substrates  110  and  120  to define discharge cells. The discharge cells defined by the barrier ribs  190  are coated with a red phosphor layer R, a green phosphor layer G, and a blue phosphor layer B.  
         [0052]     Briefly looking at a process of manufacturing the PDP  100  having the above-described structure, the X and Y electrodes  130  and  140  are first arranged in parallel on the inner surface of the front substrate  110 . Then, a raw material for the front dielectric layer  150  is printed on the entire inner surface of the resultant front substrate  110  so that the X and Y electrodes  130  and  140  can be buried in the material. Thereafter, the front dielectric layer  150  is formed through drying and other predetermined processes, and the protective layer  160  is deposited on the front dielectric layer  150 .  
         [0053]     After the address electrodes  170  are arranged in parallel on the inner surface of the rear substrate  110 , a raw material for the rear dielectric layer  180  is printed on the entire inner surface of the resultant rear substrate  120  so that the Y electrodes  170  can be buried in the material. Thereafter, the rear dielectric layer  180  is formed through drying and other predetermined processes.  
         [0054]     Thereafter, the barrier ribs  190  are formed on the rear substrate  10 , and a Red phosphor layer R, a Green phosphor layer G, and a Blue phosphor layer B are repeatedly formed on the discharge cells defined by adjacent barrier ribs  190 .  
         [0055]     Through this process, the front and rear substrates  110  and  120  are completed.  
         [0056]     Discharge characteristics of the PDP  100  are shown in  FIG. 2 . In  FIG. 2 , the X axis indicates a voltage V set  used to accumulate wall charges in a reset stage, and the Y axis indicates an address voltage V a .  
         [0057]     As shown in  FIG. 2 , because the red, green, and blue phosphor layers R, G, and B have different discharge characteristics, voltage margins Va, which are minimal address voltages required upon addressing, are different for the red, green, and blue phosphor layers R, G, and B.  
         [0058]     For example, when the voltage V set  is 170V, an address voltage V a  of a discharge cell coated with the blue phosphor layer B is about 55V as shown in curved line B, while an address voltage V a  of a discharge cell coated with the red phosphor layer R is about 63V as shown in curved line R.  
         [0059]     In practice, at least an address voltage V a  for a discharge cell coated with a red phosphor layer, which has the smallest voltage margin V a , must be used to drive the PDP  100 . Thus, a driving circuit for the PDP  100  is overloaded.  
         [0060]     A PDP according to an embodiment of the present invention is described below with reference to the accompanying drawings.  
         [0061]      FIG. 3  is an exploded perspective view of a PDP  300  according to an embodiment of the present invention.  FIG. 4  is a cross-section of the PDP  300  taken along line I-I of  FIG. 3 .  
         [0062]     Referring to  FIGS. 3 and 4 , the PDP  300  includes a front substrate  310  and a rear substrate  320  which are arranged to face each other in parallel. The front and rear substrates  310  and  320  are attached together by frit glass coated on the edges of the facing inner surfaces thereof and then sealed.  
         [0063]     The front substrate  310  is formed of a transparent material, for example, soda lime glass. X and Y electrodes  330  and  340 , which are discharge sustain electrodes, are arranged at regular intervals in direction Y on the inner surface (i.e., the bottom surface) of the front substrate  310 . The X and Y electrodes  330  and  340  alternate.  
         [0064]     An X electrode  330  includes a first electrode line  331 , which is transparent and formed on the inner surface of the front substrate  310 , and a first bus electrode  332 , which is formed on some area of the first electrode line  331 . The Y electrode  340  includes a second electrode line  341 , which is transparent and formed on the inner surface of the front substrate  310 , and a second bus electrode  342 , which is formed on some area of the second electrode line  341 .  
         [0065]     The first and second electrode lines  331  and  341  are disposed in pairs within each discharge cell and are formed of a transparent material, for example, Indium Tin Oxide (ITO), to improve the aperture ratio of the front substrate  310 . The first and second bus lines  332  and  342  are formed of highly conductive metal, for example, silver (Ag) paste or a chrome-copper-chrome alloy, to reduce resistances of the first and second electrode lines  331  and  341  and to improve electrical conductivity.  
         [0066]     A space between a pair of X and Y electrodes  330  and  340  and an adjacent pair of X and Y electrodes  330  and  340  is a non-discharge area. The non-discharge area can include a black stripe layer to improve the contrast of the PDP  300 .  
         [0067]     The X and Y electrodes  330  and  340  are buried in the front dielectric layer  350 . The front dielectric layer  350  is formed by adding a variety of fillers to a glass paste. The front dielectric layer  350  can be printed on only parts of the bottom surface of the front substrate  310  on which the X and Y electrodes  330  and  340  are formed. Alternatively, the front dielectric layer  350  can be printed on the entire bottom surface of the front substrate  310 . A protective layer  360 , which is formed of Magnesium Oxide (MO), for example, is deposited on the front dielectric layer  350  to protect the front dielectric layer  350  and increase the amount of secondary electrons emitted.  
         [0068]     Address electrodes  370  are arranged on the inner surface of the rear substrate  320  to cross the X and Y electrodes  330  and  340 . The address electrodes  370  are buried in a rear dielectric layer  380 .  
         [0069]     Barrier ribs  390  are formed within a space between the front and rear substrates  310  and  320  to define discharge cells. The barrier ribs  390  include first barrier ribs  391 , which are disposed in an X direction of the panel  300 , and second barrier ribs  392 , which are disposed in a Y direction of the panel  300 . The first barrier rib  391  extends from sidewalls of a pair of adjacent second barrier ribs  392  in a direction where the sidewalls face each other. The first and second barrier ribs  391  and  392  are combined in a matrix shape.  
         [0070]     Alternatively, the barrier ribs  390  can be other various shapes, such as, a meander shape, a delta shape, or a honeycomb shape. Accordingly, a defined discharge cell is not limited to a particular shape, such as, a polygon other than a rectangle or a circle.  
         [0071]     A discharge gas, such as, neon-xenon or helium-xenon, is injected into the discharge cells defined by the front and rear substrates  310  and  320  and the barrier ribs  390 .  
         [0072]     The discharge cells are coated with Red (R), Green (G), and Blue (B) phosphor layers  410 , which are excited by ultraviolet rays generated by the discharge gas to emit visible light. Although the R, G, and B phosphor layers  410  can be coated on any areas of the discharge cells, they are coated on the inner areas of the barrier ribs  390  in the present embodiment.  
         [0073]     A discharge cell is coated with a phosphor layer  410 . Preferably, but not necessarily, an R phosphor layer  410  is formed of (Y,Gd)BO 3 ·Eu +3 , a G phosphor layer  410  is formed of Zn 2 SiO 4 :Mn 2+ , and a B phosphor layer  410  is formed of BaMgAl 10 O 17 :Eu 2+ .  
         [0074]     The rear dielectric layer  380 , in which the address electrode  370  is buried, is formed so that parts of the rear electric layer  380  corresponding to discharge cells coated with R, G, and B phosphor layers  410  can have different thicknesses.  
         [0075]     More specifically, the address electrodes  370  are arranged on the rear substrate  320  at regular intervals in direction X of the panel  300 . The address electrodes  370  in strips are arranged in parallel and extend across centers of the discharge cells in direction Y of the panel  300 .  
         [0076]     Address electrodes  370  for R, G, and B phosphor layers  410  are not on an identical level. In other words, an interval between the upper surface of the rear dielectric layer  380  and the address electrodes  370  gradually decreases in a direction from a discharge cell coated with the B phosphor layer  410 , having the highest voltage margin, to a discharge cell coated with the R phosphor layer  410 , having the lowest voltage margin.  
         [0077]     To achieve this, a first address electrode  371  is disposed on a part of the upper surface of the rear substrate  320  that is directly under a discharge cell coated with the B phosphor layer  410 . The first address electrode  371  extends across the discharge cell coated with the B phosphor layer  410 . The first address electrode  371  is buried in the first barrier dielectric layer  381 . The first barrier dielectric layer  381  is printed on the entire surface of the rear substrate  320 .  
         [0078]     A second address electrode  372  is disposed on a part of the upper surface of the rear substrate  320  that is directly under a discharge cell coated with the G phosphor layer  410 . The second address electrode  372  extends across the discharge cell coated with the G phosphor layer  410 . The second address electrode  372  is buried in a second barrier dielectric layer  382 . The second barrier dielectric layer  382  is also printed on the entire surface of the rear substrate  320 .  
         [0079]     A third address electrode  373  is disposed on a part of the upper surface of the rear substrate  320  that is directly under a discharge cell coated with the R phosphor layer  410 . The third address electrode  373  extends across the discharge cell coated with the R phosphor layer  410 . The third address electrode  373  is buried in the third barrier dielectric layer  383 . The third barrier dielectric layer  383  is printed on the entire surface of the rear substrate  320 .  
         [0080]     The first, second, and third rear dielectric layers  381 ,  382 , and  383  are formed of substantially the same material and are formed by repeatedly printing the material on the rear substrate  320  in the direction perpendicular to the plane of the rear substrate  320 , that is, in the Z direction.  
         [0081]     When a distance between the first address electrode  371  directly under the discharge cell coated with the B phosphor layer  410  and the second bus line  342  is H 1 , a distance between the second address electrode  372  directly under the discharge cell coated with the G phosphor layer  410  and the second bus line  342  is H 2 , and a distance between the third address electrode  373  directly under the discharge cell coated with the R phosphor layer  410  and the second bus line  342  is H 3 , the distances decreased in the sequence of H→H2→H3.  
         [0082]     When a thickness of the first rear dielectric layer  381 , in which the first address electrode  371  corresponding to the discharge cell coated with the B phosphor layer  410 , is t 1 , a thickness of the second rear dielectric layer  382 , in which the second address electrode  372  corresponding to the discharge cell coated with the G phosphor layer  410 , is t 2 , and a thickness of the third rear dielectric layer  383 , in which the third address electrode  373  corresponding to the discharge cell coated with the R phosphor layer  410 , is t 3 , an interval from a bottom surface of the first rear dielectric layer  381 , in which the first address electrode  371  is buried, to the upper surface of the rear dielectric layer  380  is t 1 +t 2 +t 3 . An interval from a bottom surface of the second rear dielectric layer  382 , in which the second address electrode  372  is buried, to the upper surface of the rear dielectric layer  380  is t 2 +t 3 . An interval from a bottom surface of the third rear dielectric layer  383 , in which the third address electrode  373  is buried, to the upper surface of the rear dielectric layer  380  is t 3 .  
         [0083]     Accordingly, a thickness t 1 +t 2 +t 3  of a part of the rear dielectric layer  380  that buries the first address electrode  371  is the greatest. A thickness t 3  of a part of the rear dielectric layer  380  that buries the third address electrode  373  is the smallest. A thickness t 2 +t 3  of a part of the rear dielectric layer  380  that buries the second address electrode  372  is in between the above thicknesses.  
         [0084]     Intervals between the first, second, and third address electrodes  371 ,  372 , and  373  and each of the Y electrodes  340  are different. More specifically, the first address electrode  371  corresponding to the discharge cell coated wit the B phosphor layer  410 , which has the highest voltage margin, is the farthest from the Y electrodes  340 , and the third address electrode  373  corresponding to the discharge cell coated with the R phosphor layer  410 , which has the lowest voltage margin, is the closest to the Y electrodes  340 . Accordingly, a deviation among voltage margins of discharge cells coated with Red, Green, and Blue phosphor layers can be reduced.  
         [0085]     In contrast with this embodiment, depending on the types of Red, Green, and Blue phosphor layers or the structure of barrier ribs, a discharge cell coated with a Red phosphor layer may have the highest voltage margin, or a discharge cell coated with a Green phosphor layer may have the lowest voltage margin.  
         [0086]     Formations of the address electrodes  370  and the rear dielectric layer  380  during the manufacture of the PDP  300  are described with reference to  FIGS. 4 and 5 .  
         [0087]     First, in step S 10 , the rear substrate  320  is prepared. Next, in step S 20 , first address electrodes  371  are arranged in parallel on the surface of the rear substrate  320 . The first address electrodes  371  are discharge electrodes extending across discharge cells to be defined later and coated with B phosphor layers  410  having the highest voltage margins.  
         [0088]     Then, in step S 30 , the first rear dielectric layer  381  is printed on the entire surface of the rear substrate  320  to bury the first address electrodes  371 .  
         [0089]     Thereafter, in step S 40 , second address electrodes  372  are arranged in parallel on the surface of the first rear dielectric layer  381 . The second address electrodes  372  are discharge electrodes extending across discharge cells to be defined later and coated with G phosphor layers  410  having the second highest voltage margins.  
         [0090]     Then, in step S 50 , the second rear dielectric layer  382  is printed on the entire surface of the rear substrate  320  to bury the second address electrodes  372 .  
         [0091]     Next, in step S 60 , third address electrodes  373  are arranged in parallel on the surface of the second rear dielectric layer  382 . The third address electrodes  373  are discharge electrodes extending across discharge cells that are to be defined later and coated with R phosphor layers  410  having the smallest voltage margins.  
         [0092]     Then, in step S 70 , the third rear dielectric layer  383  is printed on the entire surface of the rear substrate  320  to bury the third address electrodes  373 .  
         [0093]     By alternating the first, second, and third address electrodes  371 ,  372 , and  373  with the first, second, and third rear dielectric layers  381 ,  382 , and  383  as described above, distances between the first, second, and third address electrodes  371 ,  372 , and  373  for the discharge cells coated with the Red, Green, and Blue phosphor layers, respectively, and the Y electrodes  340  are made different. Consequently, the first, second, and third address electrodes  371 ,  372 , and  373  are covered with different thicknesses of parts of the rear dielectric layer  380 .  
         [0094]     Then, in step S 80 , barrier ribs  390  are formed on the rear substrate  320  to define the discharge cells, and the discharge cells are coated with the R, G, and B phosphor layers  410 .  
         [0095]      FIG. 6  is a graph of the tendencies of voltage margins in a PDP such as the PDP of  FIG. 1 . In this PDP, address electrodes for discharge cells coated with Red, Green, and Blue phosphors are located on an identical level.  
         [0096]      FIG. 7  is a graph of the tendencies of voltage margins in the PDP according to the embodiment of the present invention of  FIG. 3 . In this PDP, an address electrode  373 , corresponding to a discharge cell coated with the R phosphor layer  410  and having the smallest voltage margin, is disposed to be closest to a Y electrode  340 , and an address electrode  371 , corresponding to a discharge cell coated with the B phosphor layer  410  and having the highest voltage margin, is disposed to be farthest from the Y electrode  340 .  
         [0097]     In  FIGS. 6 and 7 , the X axis indicates a voltage V set  used to accumulate wall charges in a reset stage, and the Y axis indicates an address voltage V a .  
         [0098]     Referring to  FIG. 6 , when the voltage V set  is 170V, an address voltage V a  of a discharge cell coated with the R phosphor layer is about 68V, and an address voltage V a  of a discharge cell coated with the B phosphor layer is about 55V. Hence, a difference between voltage margins of the discharge cells coated with the R and B phosphor layers is about 13V. An overload of at least 68V is required to drive the panel.  
         [0099]     Referring to  FIG. 7 , when the voltage V set  is 170V, an address voltage V a  of a discharge cell coated with the R phosphor layer  410  is about 62V, and an address voltage V a  of a discharge cell coated with the B phosphor layer  410  is about 57V. Hence, a difference between the voltage margins of the discharge cells coated with the R and B phosphor layers  410  is about 5V. In other words, a difference between voltage margins in this PDP decreases by about 8V as compared with the PDP in  FIG. 6 .  
         [0100]     Due to this reduction of the difference among the address voltages of the discharge cells coated with the R and B phosphor layers  410 , the uniformity of voltages for the PDP improves. In addition, a maximum voltage margin required to drive the panel is 62V, and the voltage margin is improved by about 9% as compared with the PDP in  FIG. 6 . This reduction of the voltage to drive the panel contributes to stable driving of the panel.  
         [0101]     The above-described PDP and the method of manufacturing the same according to the present invention have the following effects. First, address electrodes for discharge cells coated with R, G, and B phosphor layers are positioned on different levels, so that address voltages become more uniform regardless of the color of a phosphor layer.  
         [0102]     Second, a thickness of a dielectric layer is optimized according to the discharge characteristics of the discharge cells coated with the R, G, and B phosphor layers, so that a load upon a driving circuit is reduced.  
         [0103]     Third, optimization of different discharge voltages depending on the R, G, and B phosphor layers contributes to a reduction in the power consumption and an improvement in the discharge efficiency.  
         [0104]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various modifications in form and detail can be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Technology Category: 5