Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. patent application Ser. No. 11/729,033, filed on Mar. 28, 2007. 
     
    
     BACKGROUND 
       [0002]    Transistors are foundational devices of the semiconductor industry. One type of transistor, the field effect transistor (FET), has among its components gate, source, and drain terminals. A voltage applied between the gate and the source terminals generates an electric field that creates an “inversion channel” through which current can flow. Such current flow may be controlled by varying the magnitude of the applied voltage. 
         [0003]    Many configurations and fabrication methods have been devised for transistor gate terminals (as well as for other transistor components). One such configuration is what is called a double gate transistor, in which a transistor has two gates instead of a single gate. Forming such a transistor can raise certain difficulties such as tip implants into a non-gated or channel region of the transistor, which can cause undesired off-state leakage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a plan view of a double gate transistor in accordance with an embodiment of the present invention. 
           [0005]      FIGS. 2A and 2B  are cross-section and top views of the embodiment of  FIG. 1 . 
           [0006]      FIG. 3  is a flow diagram of a method for forming self-aligned tip spacers in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0007]    In various embodiments, self-aligned tip spacers may be provided in a multi-gate transistor structure to mask a portion of a silicon-on-insulator (SOI) structure. By masking off a part of the SOI structure, these spacers may act as masks to prevent implantation into the area under them, while the side surfaces of the SOI structure are implanted as needed. This is so, as diffusions that are performed to implant tip material can occur at an angle such as a 45° angle. 
         [0008]    Referring now to  FIG. 1 , shown is a plan view of a double gate transistor  10  in accordance with an embodiment of the present invention. As shown in  FIG. 1 , transistor  10  includes a buried oxide layer (BOX)  20 . While not shown in  FIG. 1 , it is to be understood that BOX  20  may be formed on a suitable substrate such as a silicon substrate. A silicon structure  30 , which may be a SOI layer that is patterned into a fin-type structure formed on BOX  20 . In turn, a front gate  40   a  and a back gate  40   b , which may be formed of polysilicon may be deposited and patterned to form the front and back gates respectively. Front and back gates  40   a  and  40   b  may be separated by an insulator  50  which may be a nitride layer, for example. A high dielectric constant (high-K) material may be present at the interfaces between the sidewalls of SOI  30  and gates  40   a  and  40   b , as the high-K insulator may be formed prior to gate polysilicon deposition. To mask off a portion of the top surface of SOI  30 , a localized spacer  55  may be formed, also of nitride, for example. While only shown on one side of transistor  10 , it is to be understood that a corresponding spacer may be formed on the other side of transistor  10 . 
         [0009]      FIG. 2A  shows a cross-section view along the line B-B′ of  FIG. 1  and a top down view of the transistor structure, respectively. Specifically, as shown in  FIG. 2A  by presence of tip spacers  55   a  and  55   b , after diffusion of implants zero or reduced diffusions are present in locations  35  immediately underneath spacers  55   a  and  55   b . Instead, the implants are primarily provided in portions  30   a  and  30   b , while pure silicon remains in SOI portion  30 . Similarly, from a top down view as shown in  FIG. 2B  spacers  55   a  and  55   b  abut insulator  50  to provide a mask over the underlying portions  35  of SOI  30 . 
         [0010]    Referring now to  FIG. 3 , shown is a flow diagram of a method in accordance with one embodiment of the present invention. As shown in  FIG. 3 , method  100  may be used to form a double gate transistor in accordance with one embodiment. Method  100  may begin by patterning a stack structure that is formed of multiple layers including a SOI layer, an oxide layer, and a nitride layer (block  110 ). Specifically, trenches may be formed on either side of a stack by performing nitride and SOI dry etching. Thus a silicon fin may be formed over an underlying oxide layer, e.g., a BOX layer that is exposed on either side of the fin, with dielectric and insulation layers formed over the fin. 
         [0011]    Referring still to  FIG. 3 , then at block  120  a polysilicon layer may be deposited and then polished down to the level of the nitride layer. Note that polysilicon does not exist along the stack profile after the polishing step. The polysilicon may be used to form the double gates, i.e., on either side of the stack. Then at block  130  a hard mask layer may be deposited, which may be a nitride-based hard mask, in some embodiments. 
         [0012]    Referring still to  FIG. 4  at block  140 , the hard mask and underlying nitride layer may be selectively removed, e.g., via an etch process that will lead to localized tip spacers that extend from both sides of the insulation layers longitudinally. After the hard mask etch, the hard mask is completely etched away with most of the nitride layer underneath. At the same time, polysilicon, when exposed, is also eroded. Laterally, however, the hard mask etch can be designed to give a slight flare, and at the bottom of the hard mask flare the nitride layer is also tapered during the same etch process. Consequently, this flare is transferred to the underlying nitride layer. Note that the dual stack hard mask/nitride may be patterned with photoresist. Therefore, spacers will be formed at the nitride sidewalls due to this tapering. This taper is the main reason for the spacer to be created on top of the SOI during the subsequent processing steps. 
         [0013]    The amount of nitride recessed laterally may be controlled during the final part of the etch sequence so as to not eliminate this spacer. In various embodiments, a predetermined control of radio frequency (RF) power and etch chemistry may be implemented. For example, in some embodiments a derivative of a conventional plasma etch may be used. Further, RF power may be modified. Specifically a power in the 500-1500 watts (W) range may change the extent of the spacer footing. Still further, pressures may be changed from approximately 100 to 200 milliTorrs (mT) to enable this flared shape rather than a vertical etch. Typical etch chemistries include methyl fluoride, carbon monoxide and oxygen (CH 3 F, CO and O 2 ). This subsequent nitride etch can also be carried out immediately post polysilicon etch, without inserting a break in the etch step (between poly and nitride etch). Various tool configurations such as electron cyclotron resonance (ECR) or inductively coupled plasma (ICP) sources can also be employed to etch the nitride on the SOI to create the final desired structure. 
         [0014]    Referring still to  FIG. 4 , another patterning process may be performed to remove polysilicon from the non-gate, i.e., the implantation regions, to thus expose the SOI fin (block  150 ). Specifically, a polysilicon etch may be followed by a slight nitride-clean dry etch step, such that the SOI is exposed, with no spacer along its sidewalls, while the self-aligned nitride spacer remains along the insulation layers&#39; sidewalls. This patterning thus preserves the localized tip spacers. The top hard mask can then be stripped off to give the final structure. 
         [0015]    This etching will enable diffusion of source and drain materials into the SOI fin. Furthermore, due to the self-aligned tip spacers, these tip implantations will not impinge into the channel region present under the stack. These self-aligned tip spacers may thus act as a mask on the top surface of the SOI fin extending from the insulation layer to protect a channel region present under the remaining insulation layer. Thus, diffusions may be performed to implant tips into the SOI fin (block  160 ). Further processing may be performed to form the source and drains, metallization contacts and so forth. 
         [0016]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Technology Category: 5