Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates generally to semiconductor memories and, more particularly, to an improved static random access memory interconnect structure. 
         [0003]    2. Description of Related Art 
         [0004]    High-density SRAM devices are desirable for high-speed cache applications. As the technology of process and device integration is advanced, more and more systems are being incorporated in a single chip. For example, a SRAM cell is formed by a number of transistors, i.e. pMOS and nMOS. In addition, in order for the SRAM to be economically employed in electronic systems for high-performance, continuous efforts are being made to reduce its cost and chip size. 
         [0005]    A FinFET is a non-planar, double-gate transistor built on an SOI substrate. In a typical FinFET, the conducting channel is wrapped around a thin silicon fin, which forms the body of the device. Typically, the dimensions of the fin determine the effective channel length of the device. In recent years, the effective channel length of a FinFET is becoming shorter and shorter. In fact, the shorter channel effect is expected to replace planar devices in the future generation high performance CMOS microprocessors. In addition, FinFET devices are also expected to improve SRAM stability due to reduced channel doping and hence lower dopant random fluctuation.  FIG. 1  illustrates an example of such SRAM cell  10  illustrating a conventional SRAM contact  12  and MI interconnect  14  in which a piece of metal layer is used to connect a part of pull-down device to a part of pull-up device through two contacts. 
         [0006]    To realize the improved short channel effect benefit, the FinFET channel region must be of sub-lithographic width (about 20 nm), which can be created using spacer image transfer technique, among other know techniques. However, an additional mask is normally required to cut the spacer image to achieve the desired circuit layout. But additional masks introduce a number of concerns that have made earlier introduction unattractive. For example, an additional mask typically translates to an increase in manufacturing cost due to higher consumption of materials and tool time, as well as new processes required for multiple patterning. Moreover, it results in an overlay error between these two masks. 
         [0007]    Accordingly, a need exists for forming an SRAM design for achieving sub-lithographic fin thickness using alternative methods circumventing the limitations of using an additional cut mask. The present disclosure provides a structure and method of forming an SRAM having an improved contact and metal wiring. 
       SUMMARY OF THE INVENTION 
       [0008]    The present disclosure is directed to a structure and method of forming an improved static random access memory (SRAM) interconnect structure formed on a semiconductor substrate. In one embodiment, a method of forming an improved SRAM interconnect structure is described. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of the semiconductor substrate; removing the patterned poly-silicon layer, wherein the removing of the patterned poly-silicon layer reveals a portion of a cap layer formed over the silicon layer; etching the portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer for forming a gate oxide; and forming a gate conductor over the gate oxide. The forming of the sidewall spacer includes depositing a cap layer on the silicon layer; depositing a poly-silicon layer on the cap layer; patterning the poly-silicon layer to reveal a portion of the cap layer for producing a sidewall of the poly-silicon layer; and forming a spacer on the sidewall of the poly-silicon layer. In one embodiment, the sidewall spacer includes a spacer material. In particular, the spacer material is selected from a group consisting of nitride, oxide, oxynitride, and any combinations thereof. The cap layer includes a cap nitride layer. 
         [0009]    In another embodiment, a method of forming a static random access memory (SRAM) interconnect structure is described. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; etching a potion of the silicon layer, in which a portion of the silicon layer connects at least a portion of pull-down device of the SRAM to at least a portion of pull-up device of the SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. The step of forming a sidewall spacer includes depositing a cap layer on the silicon layer; depositing a poly-silicon layer on the cap layer; patterning the poly-silicon layer to reveal a portion of the cap layer for producing a sidewall of the poly-silicon layer; and forming a spacer on the sidewall of the poly-silicon layer. In one particular embodiment, the sidewall spacer comprises a spacer material. In another embodiment, the spacer material is selected from a group consisting of nitride, oxide, oxynitride, and any combinations thereof and the cap layer includes a cap nitride layer. 
         [0010]    Other features of the presently disclosed structure and method of forming an SRAM interconnect structure will become apparent from the following detailed description taken in conjunction with the accompanying drawing, which illustrate, by way of example, the presently disclosed structure and method. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The features of the presently disclosed structure and method for improved SRAM interconnect will be described hereinbelow with references to the figures, wherein: 
           [0012]      FIG. 1  illustrates a simplified overhead view of a conventional crosspoint SRAM contact and M 1  interconnect; 
           [0013]      FIG. 2A  illustrates a simplified overhead view of a crosspoint SRAM contact and M 1  interconnect, in accordance with one embodiment of the present disclosure; 
           [0014]      FIG. 2B  illustrates a simplified overhead view of an SRAM memory array including a plurality of SRAM contact and M 1  interconnects of  FIG. 2A ; 
           [0015]      FIGS. 3-13  illustrate simplified cross-sectional views of a method of forming an SRAM interconnect structure in accordance with one embodiment of the present disclosure; 
           [0016]      FIG. 14  illustrates a simplified cross-sectional view of taken along section  14 - 14  of  FIGS. 15A and 15B ; and 
           [0017]      FIGS. 15A and 15B  illustrate simplified overhead views of the structure of  FIGS. 3-14 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Referring now to the drawing figures, wherein like references numerals identify identical or corresponding elements, an embodiment of the presently disclosed structure and method for improved SRAM interconnect, will be disclosed in detail. In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one skilled in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the invention. 
         [0019]      FIGS. 2A and 2B  illustrate a structure made in accordance with one embodiment of the present disclosure. In particular,  FIG. 2B  is a schematic representation of a cell arrangement including a plurality of SRAM cells formed by a plurality of FET on the exterior surface of a back oxide layer. The structure includes an SRAM cell including ring-shaped based FinFET SRAM having reduced contact and M 1  interconnect. A silicon layer is formed between a pull-down device and a pull-up device, which eliminates the need of four contacts and two pieces of metal wires in the later stage of the process. The lithographic process window is improved as a result of the pattern reduction at contact and metal levels. 
         [0020]      FIGS. 3-14  illustrate exemplary process steps of forming an improved SRAM interconnect, in accordance with one embodiment of the present disclosure. In particular, a structure and method of forming an SRAM having an improved contact and metal wiring is described. More in particular, a pad oxide layer is first formed over the device structure prior to patterning, followed by a cap nitride layer. Using standard deposition methods, a polysilicon hardmask layer is deposited followed by a patterned photoresist for forming one or more shallow trench areas. An oxide deposition layer is then formed for forming one or more oxide spacers. The polysilicon hardmask is the removed. A nitride etch is then formed followed by a silicon etch the etch mask is then removed. Finally, a gate oxide form is according to conventional methods. Finally, a conventional litho is deposited to form gate conductor. 
         [0021]    With initial reference to  FIG. 3 , an early stage in the manufacture of an exemplary standard process for forming a FinFET SRAM with improved contact and metal wiring on a semiconductor structure, in accordance with the present disclosure, is illustrated and is designated generally as structure  100 . Structure  100  includes generally a base semiconductor substrate  102 ; a buried oxide (BOX) layer  104  formed on base semiconductor substrate  102 ; and a Silicon on Insulator (SOI) layer  106  formed on BOX layer  104 , where BOX layer  104  isolates SOI layer  106  from base semiconductor substrate  102 . A pad layer  108  covered with a cap layer  110  is formed on a top surface of SOI layer  106 . 
         [0022]    Base semiconductor substrate  102  may include any of several semiconductor materials well known in the art, such as, for example, a bulk silicon substrate, silicon-on-insulator (SOI) and silicon-on-sapphire (SOS). Other non-limiting examples include silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy and compound (i.e. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide semiconductor material. Typically, base semiconductor substrate  102  may be about, but is not limited to, several hundred microns thick. For example, base semiconductor substrate  102  may include a thickness ranging from about  0 . 5 mm to about  1 . 5 mm. 
         [0023]    BOX layer  104  may be formed from any of several dielectric materials. Non-limiting examples include, for example, oxides, nitrides and oxynitrides of silicon. Oxides, nitrides and oxynitrides of other elements are also envisioned. In addition, BOX layer  104  may include crystalline or non-crystalline dielectric material. Moreover, BOX layer  104  may be formed using any of several methods. Non-limiting examples include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. Typically, BOX layer  104  includes an oxide of the semiconductor from which base semiconductor substrate  102  is comprised. In one embodiment, BOX layer  104  includes a thickness of about 150 nm. Alternatively, BOX layer  104  may include a thickness ranging from about 10 nm to about 500 nm. 
         [0024]    SOI layer  106  may include any of the several semiconductor materials included in base semiconductor substrate  102 . In general, base semiconductor substrate  102  and SOI layer  106  may include either identical or different semiconductor materials with respect to chemical composition, dopant concentration and crystallographic orientation. In one particular embodiment of the present disclosure, base semiconductor substrate  102  and SOI layer  106  include semiconductor materials that include at least different crystallographic orientations. Typically one of base semiconductor substrate  102  and SOI layer  106  includes a {110} crystallographic orientation and the other of base semiconductor substrate  102  and SOI layer  106  includes a {100} crystallographic orientation. Typically, SOI layer  106  includes a thickness ranging from about 5 nm to about 100 nm. Methods for making SOI substrate are well known in the art. Non-limiting examples include SIMOX (Separation by Implantation of OXygen), wafer bonding, and ELTRAN® (Epitaxial Layer TRANsfer). 
         [0025]    Pad layer  108  includes an insulating material such as, for example, silicon nitride. Pad layer  108  may be formed using conventional deposition methods, for example, low-pressure chemical vapor deposition (LPCVD) and depositing SiN of a thickness ranging from about 10 nm to about 500 nm. In one particular embodiment, pad nitride layer  108  includes a thickness of about 100 nm. Optionally, a thin (2 nm to 10 nm, preferably 5 nm) thermal oxide layer (not shown) may be formed on SOI layer  106  prior to forming pad nitride layer  108 . 
         [0026]    Cap layer  110  includes any material capable of functioning as an etch stop layer, such as, for example, silicon nitride (Si3N4) and silicon oxinitride (SiOxNy). 
         [0027]    With reference to  FIG. 4 , a cell location is identified and a mask layer  112  of a suitable masking material is deposited on cap layer  110  and patterned using a conventional photolithography technique. Mask layer  112  includes suitable masking materials such as, for example, a photoresist or a hardmask (e.g. silicon dioxide). In one particular embodiment, mask layer  112  includes a polysilicon hardmask layer and it may be formed using conventional deposition processes, such as, for example, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc. In one embodiment, mask layer  112  includes a thickness ranging from about 5 nm to about 70 nm. 
         [0028]    With reference to  FIG. 5  in conjunction with  FIG. 4 , a patterned photoresist layer  114  is formed over mask layer  112  to facilitate etching through a portion of mask layer  112  and forming one or more shallow trenches  116   a  ,  116   b  , in accordance with conventional photolithographic techniques. 
         [0029]    With reference to  FIG. 6 , the structure is stripped of any etch residue using suitable stripping and cleaning processes. Examples of stripping methods include wet chemical, dry plasma and aggregate stripping methods thereof. 
         [0030]    With reference to  FIG. 7 , blanket deposition of a thin layer of a sacrificial silicon oxide layer  118  is formed over the structure using conventional deposition methods. In one embodiment, silicon oxide layer  118  includes a thickness of about 10 nm to 50 nm. 
         [0031]    With reference to  FIG. 8 , a conventional spacer oxide layer  120  are formed on the sidewalls of mask  112  by selectively etching silicon oxide layer  118  with an anisotropic etch step. 
         [0032]    With reference to  FIG. 9 , mask layer  112  is then removed using conventional wet etching methods. 
         [0033]    With reference to  FIG. 10  cap layer  110  is etched by patterning cap layer  110  using spacer oxide layer  120  as a mask. 
         [0034]    With reference to  FIG. 11 , pad layer  108  is patterned to convert pad layer  108  into an intermediate masking layer. SOI  106  is etched by a RIE using spacer oxide layer  120  and cap layer  110  as a hard mask. The RIE etching process continues through SOI  106  until the exterior (i.e. top) surface of BOX  104  is reached, where the etching process stops. 
         [0035]    With reference to  FIG. 12 , etch mask (i.e. silicon oxide layer  120 ) is mostly consumed during the multiple RIE processes. 
         [0036]    With reference to  FIG. 13 , a layer of silicon oxide  122  is formed using oxidation process or a layer of high-K dielectric layer is deposited using CVD or ALD process. 
         [0037]      FIG. 14  illustrates the structure of  FIG. 13  after deposition and planarization of a blanket deposition of gate polysilicon layer  124 . As illustrated by this figure, gate polysilicon layer  124  has been planarized well past the top of the structure. Gate polysilicon layer  124  may be doped or undoped. 
         [0038]      FIGS. 15A and 15B  illustrate simplified overhead views of the structure illustrated by  FIG. 14 . The ring formed by the NFET drain silicon on the left and the PFET drain silicon on the right provides the interconnect which is normally done with metal wiring and extra metal contact to the NFET drain silicon on the left. Thus metal congestion in the SRAM cell is much released. 
         [0039]    It will be understood that numerous modifications and changes in form and detail may be made to the embodiments of the presently disclosed structure and method of forming an improved SRAM interconnect structure. It is contemplated that numerous other configuration of the SRAM may be used, and the material of the structure and method may be selected from numerous materials other than those specifically disclosed. Therefore, the above description should not be construed as limiting the disclosed structure and method, but merely as exemplification of the various embodiments thereof. Those skilled in the art will envisioned numerous modifications within the scope of the present disclosure as defined by the claims appended hereto. Having thus complied with the details and particularity required by the patent laws, what is claimed and desired protected is set forth in the appended claims.

Technology Category: 5