Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates generally to storage device controllers, and more particularly, to efficiently managing data flow using a WWN module. 
   2. Background 
   Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives/disks) (referred to herein as “storage device”). 
   In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system. 
   The storage device is coupled to the host system via a controller that handles complex details of interfacing the storage device to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces. 
   Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into a buffer memory. Data is read from the device and stored in the buffer memory. 
   Various standard interfaces are used to move data from host systems to storage devices. Fibre channel is one such standard. Fibre channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users. 
   Host systems often communicate with storage systems using the standard “PCI” bus interface. PCI stands for Peripheral Component Interconnect, a local bus standard that was developed by Intel Corporation®. The PCI standard is incorporated herein by reference in its entirety. Most modern computing systems include a PCI bus in addition to a more general expansion bus (e.g. the ISA bus). PCI is a 64-bit bus and can run at clock speeds of 33 or 66 MHz. 
   PCI-X is a standard bus that is compatible with existing PCI cards using the PCI bus. PCI-X improves the data transfer rate of PCI from 132 MBps to as much as 1 GBps. The PCI-X standard (incorporated herein by reference in its entirety) was developed by IBM®, Hewlett Packard Corporation® and Compaq Corporation® to increase performance of high bandwidth devices, such as Gigabit Ethernet standard and Fibre Channel Standard, and processors that are part of a cluster. 
   The iSCSI standard (incorporated herein by reference in its entirety) is based on Small Computer Systems Interface (“SCSI”), which enables host computer systems to perform block data input/output (“I/O”) operations with a variety of peripheral devices including disk and tape devices, optical storage devices, as well as printers and scanners. 
   A traditional SCSI connection between a host system and peripheral device is through parallel cabling and is limited by distance and device support constraints. For storage applications, iSCSI was developed to take advantage of network architectures based on Fibre Channel and Gigabit Ethernet standards. iSCSI leverages the SCSI protocol over established networked infrastructures and defines the means for enabling block storage applications over TCP/IP networks. iSCSI defines mapping of the SCSI protocol with TCP/IP. The iSCSI architecture is based on a client/server model. Typically, the client is a host system such as a file server that issues a read or write command. The server may be a disk array that responds to the client request. 
   Serial ATA (“SATA”) is another standard, incorporated herein by reference in its entirety that has evolved from the parallel ATA interface for storage systems. SATA provides a serial link with a point-to-point connection between devices and data transfer can occur at 150 megabytes per second. 
   Another standard that has been developed is Serial Attached Small Computer Interface (“SAS”), incorporated herein by reference in its entirety. The SAS standard allows data transfer between a host system and a storage device. SAS provides a disk interface technology that leverages SCSI, SATA, and fibre channel interfaces for data transfer. SAS uses a serial, point-to-point topology to overcome the performance barriers associated with storage systems based on parallel bus or arbitrated loop architectures. 
   The SAS specification addresses all devices in its domain by using a World Wide Name (WWN) address. The WWN is a unique 64-bit field that is allocated by IEEE to storage devices manufacturers. 
   In a SAS domain there could be up to 256 active devices. The devices could be of Initiator type or Target type. Initiator device initiates an Input/Output process (I/O) by sending a Command frame. The Target device completes an I/O by sending a Response frame. Any Initiator device may have up to 256 active I/O commands at a given time. Before any frame is sent, a connection is established between two SAS devices. A connection consists of an “Open Address” frame with a WWN field in it. On every Open Address, the receiving device compares the Open Address WWN to open I/O commands. Also, every I/O command may have multiple connections. 
   Typically, storage controllers use a Micro Controller that is 8-bit wide. The foregoing process of tracking connections using the 64-bit WWN addresses is time consuming. Therefore, there is a need for a system and method for efficiently manage connections and effectively use the WWN addresses. 
   SUMMARY OF THE INVENTION 
   In one aspect of the present invention, a method for managing frames entering or leaving a storage controller is provided. The method includes, comparing frame elements of incoming frames, including a unique World Wide Name (WWN) address with a WWN module entry; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. A WWN index value is provided to a processor of the storage controller. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device. 
   In yet another aspect of the present invention, a storage controller for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device is provided. The storage controller includes: a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, and an input/output counter value that tracks plural commands for a connection. The WWN module uses the WWN index value that represents an address of a row having plural entries. 
   The WWN module is a part of a link module that interfaces between a transport module and a physical module for transferring information. The WWN index value is smaller than the WWN address and can be read by a micro-controller or processor of the storage controller. 
   In yet another aspect of the present invention, a WWN module in a storage controller is provided. The WWN module includes, a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, and an input/output counter value that tracks plural commands for a connection. 
   This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
       FIG. 1A  shows an example of a storage drive system used with the adaptive aspects of the present invention; 
       FIG. 1B  shows a block diagram of a SAS module used in a controller, according to one aspect of the present invention; 
       FIG. 1C  shows a detailed block diagram of a SAS module, according to one aspect of the present invention; 
       FIG. 1D  shows a SAS frame that is received/transmitted using the SAS module according to one aspect of the present invention; 
       FIG. 2A  shows a block diagram of a WWN Index module, according to one aspect of the present invention; 
       FIG. 2B  shows yet another block diagram of a WWN Index module with plural commands, according to one aspect of the present invention; 
       FIGS. 3A-3G  illustrate the various process steps for implementing the WWN index module, according to one aspect of the present invention; and 
       FIG. 4  is a process flow diagram for using the WWN index module, according to one aspect of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Controller Overview 
   To facilitate an understanding of the preferred embodiment, the general architecture and operation of a controller will initially be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture. 
     FIG. 1A  shows an example of a storage drive system (with an optical disk or tape drive), included in (or coupled to) a computer system. The host computer (not shown) and the storage device  110  (also referred to as disk  110 ) communicate via a port using a disk formatter “DF”  104 . In an alternate embodiment (not shown), the storage device  110  is an external storage device, which is connected to the host computer via a data bus. The data bus, for example, is a bus in accordance with a Small Computer System Interface (SCSI) specification. Those skilled in the art will appreciate that other communication buses known in the art can be used to transfer data between the drive and the host system. 
   As shown in  FIG. 1A , the system includes controller  101 , which is coupled to buffer memory  111  and microprocessor  100 . Interface  109  serves to couple microprocessor bus  107  to microprocessor  100  and a micro-controller  102  and facilitates transfer of data, address, timing and control information. A read only memory (“ROM”) omitted from the drawing is used to store firmware code executed by microprocessor  100 . 
   Controller  101  can be an integrated circuit (IC) that comprises of various functional modules, which provide for the writing and reading of data stored on storage device  110 . Buffer memory  111  is coupled to controller  101  via ports to facilitate transfer of data, timing and address information. Buffer memory  111  may be a double data rate synchronous dynamic random access memory (“DDR-SDRAM”) or synchronous dynamic random access memory (“SDRAM”), or any other type of memory. 
   Disk formatter  104  is connected to microprocessor bus  107  and to buffer controller  108 . A direct memory access (“DMA”) DMA interface (not shown) is connected to microprocessor bus  107  and to data and control port (not shown). 
   Buffer controller (also referred to as “BC”)  108  connects buffer memory  111 , channel one (CH 1 ) logic  105 , error correction code (“ECC”) module  106  to bus  107 . Buffer controller  108  regulates data movement into and out of buffer memory  111 . 
   CH 1  logic  105  is functionally coupled to SAS module  103  that is described below in detail. CH 1  Logic  105  interfaces between buffer memory  111  and SAS module  103 . SAS module  103  interfaces with host interface  104 A to transfer data to and from disk  110 . 
   Data flow between a host and disk passes through buffer memory  111  via channel  0  (CH 0 ) logic  106 A. ECC module  106  generates ECC that is saved on disk  110  during a write operation and provides correction mask to BC  108  for disk  110  read operation. 
   The Channels, CH 0   106 A, CH 1   105  and Channel  2  (not shown) are granted arbitration turns when they are allowed access to buffer memory  111  in high speed burst write or read operations for a certain number of clocks. The channels use first-in-first out (“FIFO”) type memories to store data that is in transit. Firmware running on processor  100  can access the channels based on bandwidth and other requirements. 
   To read data from device  110 , a host system sends a read command to controller  101 , which stores the read commands in buffer memory  111 . Microprocessor  100  then reads the command out of buffer memory  111  and initializes the various functional blocks of controller  101 . Data is read from device  110  and is passed to buffer controller  108 . 
   To write data, a host system sends a write command to disk controller  101 , which is stored in buffer  111 . Microprocessor  100  reads the command out of buffer  111  and sets up the appropriate registers. Data is transferred from the host and is first stored in buffer  111 , before being written to disk  110 . Cyclic redundancy code (“CRC”) values are calculated based on a logical block address (“LBA”) for the sector being written. Data is read out of buffer  111 , appended with ECC code and written to disk  110 . 
   Frame Structure: 
     FIG. 1D  shows a SAS frame  129  that is received/transmitted using SAS module  103 . Frame  129  includes a WWW address  129 A, a start of frame (“SOF”) value  129 G, a frame header  129 B that includes a frame type field  129 E, payload/data  129 C, CRC value  129 D and end of frame (“EOF”)  129 F. WWN address  129 A is used for each open connection at a given time. 
   Also, a frame may be an interlock or non-interlocked, specified by field  129 E. For an interlock frame, acknowledgement from a host is required for further processing, after the frame is sent to the host. Non-interlock frames are passed through to a host without host acknowledgement (up to 256 frames per the SAS standard). 
   SAS Module  103 : 
     FIG. 1B  shows a top level block diagram for SAS module  103  used in controller  101 . SAS module  103  includes a physical (“PHY”) module  112 , a link module  113  and a transport module (“TRN”)  114  described below in detail. A micro-controller  115  is used to co-ordinate operations between the various modules. A SAS interface  116  is also provided to the PHY module  112  for interfacing with a host and interface  117  is used to initialize the PHY module  112 . 
     FIG. 1C  shows a detailed block diagram of SAS module  103  with various sub-modules. Incoming data  112 C is received from a host system, while outgoing data  112 D is sent to a host system or another device/component. 
   PHY Module  112 : 
   PHY module  112  includes a serial/deserializer (“SERDES”)  112 A that serializes encoded data for transmission ( 112 D), and de-serializes received data ( 112 C). SERDES  112 A also recovers a clock signal from incoming data stream  112 C and performs word alignment. 
   PHY control module  112 B controls SERDES  112 A and provides the functions required by the SATA standard. 
   Link Module  113 : 
   Link module  113  opens and closes connections, exchanges identity frames, maintains ACK/NAK (i.e. acknowledged/not acknowledged) balance and provides credit control. As shown in  FIG. 1C , link module  113  has a receive path  118  that receives incoming frames  112 C and a transmit path  120  that assists in transmitting information  112 D. Addresses  121  and  122  are used for received and transmitted data, respectively. WWN index module  119 A is used for maintaining plural connections states, described below in detail. 
   Receive path  118  includes a converter  118 C for converting 10-bit data to 8-bit data, an elasticity buffer/primitive detect segment  118 B that transfers data from a receive clock domain to a transmit block domain and decodes primitives. Descrambler module  118 A unscrambles data and checks for cyclic redundancy check code (“CRC”). 
   Transmit path  120  includes a scrambler  120 A that generates CRC and scrambles (encodes) outgoing data; and primitive mixer module  120 B that generates primitives required by SAS protocol/standard and multiplexes the primitives with the outgoing data. Converter  120 C converts 8-bit data to 10-bit format. 
   Link module  113  uses plural state machines  119  to achieve the various functions of its sub-components. State machines  119  includes a receive state machine for processing receive frames, a transmit state machine for processing transmit frames, a connection state machine for performing various connection related functions and an initialization state machine that becomes active after an initialization request or reset. 
   Transport Module  114 : 
   Transport module  114  interfaces with CH 1   105  and link module  113 . In transmit mode, TRN module  114  receives data from CH  1   105 , loads the data (with fibre channel header (FCP)  127 ) in FIFO  125  and sends data to Link module  113  encapsulated with a header ( 129 B) and a CRC value ( 129 D). In receive mode, TRN MODULE  114  receives data from link module  113  (in FIFO  124 ), and re-packages data (extracts header  126  and  128 ) before being sent to CH  1105 . CH 1   105  then writes the data to buffer  111 . State machine  123  is used to co-ordinate data transfer in the receive and transmit paths. 
   WWN Index Module  119 A 
   WWN Index module  119 A, as shown in  FIG. 2A , includes a table with “n” (where n is greater than  1 ) elements. WWN Index module  119 A stores information about each open connection between storage controller  101  and a device/host. WWN Index module  119 A has plural rows/layers. Each row (for example, row  206  in  FIG. 2A ) is referred to by its WWN index value (address value)  205 . For example, row  206  includes a SAS address field (64 bit WWN address)  200 , an Initiator Connection tag (16 bits)  201 , an I/O counter (10 bits)  202 , a single bit (“V”)  203  to indicate the validity of an entry and a fresh (F) field  204  that indicates the latest row that is being serviced. 
   When an Open Address frame is received, the WWN address  129 A (WWN address field) of the received frame is compared with the WWN address field ( 200 ) in module  119 A. A successful comparison returns a WWN index value  205 . This WWN index value  205  is provided to MC  115 . Since the WWN index value  205  is an 8-bit field, MC  115  can handle it very efficiently. 
   It is noteworthy that the present invention is not limited to any particular size of module  119 A or any of its entries. For example, WWN index value  205  is not limited to an 8-bit value or any other size. 
   If a WWN address of an Open Address frame is not recognized by module  119 A entries and the first frame is of Command type, then a new entry (or row  206 ) is created and its I/O count  202  is set to one. The new row  206  is allocated a WWN index value  205 , so that when a frame from the same source/connection arrives again, then module  119 A can return the proper WWN index value ( 205 ) after the comparison. 
   For each frame crossing link module  113 , the frame type is checked. If the frame is of Command type, the I/O counter of the active entry is incremented (increased) ( 202 ). If the frame is of Response type, the I/O count of the active entry is decremented (decreased). When the I/O count reaches zero, the valid bit  203  is reset and the entry becomes vacant. 
     FIG. 2B  shows a detailed diagram of WWN module  119 A with row  206 . The various entries are loaded in rows based on receive access (path)  207  and transmit access (path)  208 . Reset command  209  is used to reset module  119 A. MC  102 , MC  115  or MP  100  may issue the reset command. 
   “Get Index by WWN”  213  (or signal  213 ) allows searching of module  119 A by WWN address  200  and/or Initiator Tag value  201 . MC  115 , MC  102  or MP  100  may use this function. If the “Get Index by WWN” function  213  finds an entry that matches a search term (for example, for an incoming frame), then the WWN index value  205  is returned with a “success” flag. If no match is found then a new entry is allocated and the new value is returned. If the table is full based on signal  213 , then a “fail” flag is returned. A successful allocation causes the valid bit  203  to be set. The valid bit  203  is cleared fro an entry when the I/O counter value  202  reaches a certain value, for example, 0. 
   Signal/command “INC by Index”  212  is used to increment the index value  205 . Also, MP  100  (or MC  102  or  115 ) may load a row (for example,  206 ) by using an index value  205  (by using “Load by Index” command  211 ). Using “Clear by Index” signal/command  210  clears entries in a row ( 206 ). 
     FIG. 4  shows a flow diagram for using module  119 A, according to one aspect of the present invention. Turning in detail to  FIG. 4 , in step S 400 , a request to open connection is made between a device (SAS peer device)  300 A ( FIG. 3A ) and controller  101 . If the request is accepted, then a connection is established in step S 401 , otherwise the process loops back to step S 400  and waits. The connection is shown as  301 A in  FIG. 3A . At this stage the I/O counter value is zero (shown as  202 A). 
   In step S 402 , the process determines if a WWN address entry exists. If yes, the process moves to step S 404 . If an entry does not exist in step S 402 , then an entry is created in step S 403 . 
   In step S 404 , a WWN index value is established for the entry (WWN index value  205 ). 
   In step S 405 , a frame is received/transmitted by controller  101 . 
   In step S 406 , the process determines if a frame is of command type. If yes, then I/O counter value  202  is incremented ( 202 B,  FIG. 3B ). If the frame is not of command type, then in step S 408 , the process determines if the frame is of response type. If the frame is of a response type, then the I/O counter value  202  is decremented ( 202 B,  FIG. 3F ). 
   If the frame is not of a response type (in step S 410 ), then the connection is closed in step S 410  and in step S 411 , all the entries are de-allocated with the I/O counter value  202  cleared to zero ( 202 A,  FIG. 3A ). 
     FIGS. 3A-3G  illustrate the use of WWN module  119 A, according to one aspect of the present invention.  FIG. 3A  shows that a connection  301 A is established between controller  101  and device  300 A. I/O counter value is zero, shown as  202 A.  FIG. 3B  shows that a command  300  is received and thereafter, the I/O counter value is increased to 1 (shown as  202 B). 
     FIG. 3C  shows that data  301  is received from device  300 A and I/O counter value remains the same (i.e. 1).  FIG. 3D  shows that controller  101  receives another command  302  and that device  300 A is ready for a transfer (shown as  300 B). The I/O counter value is increased to 2, shown as  202 C. 
     FIG. 3E  shows that data  304  is received by device  300 A via controller  101  and data  303  is received from device  300 A. I/O counter value remains 2 (shown as  202 C). 
     FIG. 3F  shows that command  300  is complete and a response  305  is received by device  300 A. I/O counter value is decreased to 1 and is shown as  202 B. 
     FIG. 3G  shows that data  306  is received by device  300 A via controller  101 . After command  302  is complete, response  307  is sent to device  300 A. Thereafter, the I/O counter value is decreased to zero, shown as  202 A. 
   In one aspect of the present invention, a dynamic WWN module is provided that dynamically updates connection information. Also, the WWN module provides an easy to use index value that can be used by MC  115 , MC  102  and MP  100 . 
   Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure.

Technology Category: 5