Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority of U.S. Provisional Patent Application Ser. No. 60/653,945, filed on Feb. 18, 2005. The subject matter of this earlier filed application is hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a network device for processing data in a network and more particularly to parsing of data received by a network device that allows for enhanced processing speeds and data handling.  
         [0004]     2. Description of the Related Art  
         [0005]     A network may include one or more network devices, such as Ethernet switches, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device may include port interface modules, designed to send and receive data over a network, a Memory Management Unit (MMU), to store that data until it is forwarded or further processed and resolution modules, that allow the data to be reviewed and processed according to instructions. The resolution modules include switching functionalities for determining to which destination port data should be directed. One of the ports on the network device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.  
         [0006]     Many network devices operate as Ethernet switches, where packets enter the device from multiple ports, where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU. The MMU enables sharing of packet buffer among different ports while providing resource guarantees for every ingress port, egress port and class of service queue.  
         [0007]     However, many of these prior art network devices cannot provide fast handling of network data that also allows for flexibility in what portions of the received data are evaluated in order to determine how the data should be forwarded. Thus, when, for example, packets are received that have tunnel encapsulation, extra processing must be performed so that the proper attributes of the packets can be determined.  
       SUMMARY OF THE INVENTION  
       [0008]     According to one embodiment of the invention, a network device for processing data on a data network, the network device includes a port interface, in communication with a plurality of ports, configured to receive data packets from a data network and to send processed data packets to the data network, a memory management unit, in communication with and controlling memory external to the network device, configured store data on and retrieve data from the memory, a parser, in communication with the port interface and the memory management unit, configured to parse the received data packets to determine attributes of the data packets and a search engine, in communication with the parser, configured to perform table lookup searches in response to requests from the parser. The parser comprises at least two stages, where the at least two stages are each configured to parser particular portions of the received data packets.  
         [0009]     Additionally, the network device may include a computer management interface, in communication with the parser, configured to translate and supply control information for the network device. Also, the parser may include a tunnel parser, configured to determine a type of tunnel encapsulation of a particular received packet. The plurality of ports may include at least one higher speed port and a higher speed port parser, where the higher speed port parser is configured to parse data packets received by the at least one higher speed port.  
         [0010]     Additionally, the parser may include a deep parser, configured to determine specific attributes of a particular received packet that are used to determine a destination for the particular received packet. The parser may also include a field parser that is configured to determine specific fields within the particular received packet. The deep parser may include a protocol checker that is configured to check internet protocol attributes of the particular received packet.  
         [0011]     According to another aspect of the invention, a method for processing data in a network device includes the steps of receiving data packets at a plurality of ports by a port interface, forwarding data packets to a parser, performing a first stage of parsing of the data packets, to determine a first set of attributes for the data packets, performing a second stage of parsing of the data packets, to determine a second set of attributes for the data packets, forwarding the data to a memory management unit, storing the data by the memory management unit in a memory external to the network device, retrieving the received data from the memory and modifying the received data, if needed, based on the determined sets of attributes to produce processed data and forwarding processed data to an egress port of the plurality of ports.  
         [0012]     According to another aspect of the invention, a network device for processing data includes port means for receiving data packets and sending processed data packets, first parsing means for parsing the data packets to determine a first set of attributes for the data packets, second parsing means for parsing the data packets to determine a second set of attributes for the data packets, memory means for storing the data received from the first parsing means and the second parsing means by a memory management unit in a memory external to the network device and retrieving the stored data and modifying means for modifying retrieved, stored data, based on the determined sets of attributes to produce processed data. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention that together with the description serve to explain the principles of the invention, wherein:  
         [0014]      FIG. 1  illustrates a network device in which an embodiment of the present invention may be implemented;  
         [0015]      FIG. 2  illustrates a block diagram illustrating the communication using ports of the network device, according to an embodiment of the instant invention;  
         [0016]      FIG. 3  illustrates memory structures to be used with the network device, with  FIG. 3   a  illustrating the shared memory that is external to the network device and  FIG. 3   b  illustrating the Cell Buffer Pool of the shared memory architecture;  
         [0017]      FIG. 4  illustrates buffer management mechanisms that are used by the memory management unit to impose resource allocation limitations and thereby ensure fair access to resource;  
         [0018]      FIG. 5  illustrates a two stage parser, according to certain embodiments of the present invention;  
         [0019]      FIG. 6  illustrates another parser for use with interconnected port, according to certain embodiments of the present invention;  
         [0020]      FIG. 7  illustrates a result matcher, according to certain embodiments of the present invention; and  
         [0021]      FIG. 8  illustrates a configuration of an egress port arbitration implemented in the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0022]     Reference will now be made to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0023]      FIG. 1  illustrates a network device, such as a switching chip, in which an embodiment the present invention may be implemented. Device  100  includes port interface modules  112  and  113 , a MMU  115 , an ingress and egress module  130  and a search engine  120 . The ingress and egress module  130  parses the data received and performs look ups based on the parsed data using the search engine  120 . The primary function of MMU  115  is to efficiently manage cell buffering and packet pointer resources in a predictable manner, even under severe congestion scenarios. Through these modules, packet modification can occur and the packet can be transmitted to an appropriate destination port.  
         [0024]     According to several embodiments, the device  100  may also include one internal fabric high speed port, for example a HiGig™ port,  108 , one or more external Ethernet ports  109   a - 109   x , and a CPU port  110 . High speed port  108  is used to interconnect various network devices in a system and thus form an internal switching fabric for transporting packets between external source ports and one or more external destination ports. As such, high speed port  108  may not externally visible outside of a system that includes the multiple interconnected network devices. CPU port  110  is used to send and receive information to and from external switching/routing control entities or CPUs. According to an embodiment of the invention, CPU port  110  may be considered as one of external Ethernet ports  109   a - 109   x . Device  100  interfaces with external/off-chip CPUs through a CPU processing module  111 , such as a CMIC, which interfaces with a PCI bus that connects device  100  to an external CPU.  
         [0025]     In addition, the search engine module  120  may be composed of additional search engine modules,  122 ,  124  and  126 , that are used to perform particular look ups that are used in the characterization and modification of data being processed by the network device  100 . Likewise, the ingress and egress module  130  also includes additional modules that are directed to parsing data received from the internal fabric high speed port  134  and the other ports  138 , with other modules  132  and  136  for forwarding data back to the ports of the network device. The two parsers are discussed in greater detail below.  
         [0026]     Network traffic enters and exits device  100  through external Ethernet ports  109   a - 109   x . Specifically, traffic in device  100  is routed from an external Ethernet source port to one or more unique destination Ethernet ports. In one embodiment of the invention, device  100  supports twelve physical Ethernet ports  109 , each of which can operate in 10/100/1000 Mbps speed and one high speed port  108  which operates in either 10 Gbps or 12 Gbps speed.  
         [0027]     The structure of the physical ports  112  are further illustrated in  FIG. 2 . A series of serializing/deserializing modules  103  send and receive data, where data received as each port is managed by a port manager  102 A-L. The series of port managers have a timing generator  104  and a bus agent  105  that facilitate their operation. The data received and transmitted to a port information base so that the flow can be monitored. It is noted that high speed port  108  has similar functionalities but does not require as many elements since only one port is being managed but at a higher speed.  
         [0028]     In an embodiment of the invention, device  100  is built around a shared memory architecture, as shown in  FIGS. 3   a - 3   b  wherein MMU  115  enables sharing of a packet buffer among different ports while providing for resource guarantees for every ingress port, egress port and class of service queue associated with each egress port.  FIG. 3   a  illustrates the shared memory architecture of the present invention. Specifically, the memory resources of device  100  include a Cell Buffer Pool (CBP) memory  302  and a Transaction Queue (XQ) memory  304 . CBP memory  202  is an off-chip resource that is made of, according to some embodiments, 4 DRAM chips  306   a - 306   d . According to an embodiment of the invention, each DRAM chip has a capacity of 288 Mbits, wherein the total capacity of CBP memory  302  is 122 Mbytes of raw storage. As shown in  FIG. 3   b , CBP memory  302  is divided into 256K 576-byte cells  308   a - 308   x , each of which includes a 32 byte header buffer  310 , up to 512 bytes for packet data 312 and 32 bytes of reserved space  314 . As such, each incoming packet consumes at least one full 576 byte cell  308 . Therefore in an example where an incoming includes a 64 byte frame, the incoming packet will have 576 bytes reserved for it even though only 64 bytes of the 576 bytes is used by the frame.  
         [0029]     Returning to  FIG. 3   a , XQ memory  304  includes a list of packet pointers  316   a - 316   x  into CBP memory  302 , wherein different XQ pointers  316  may be associated with each port. A cell count of CBP memory  302  and a packet count of XQ memory  304  is tracked on an ingress port, egress port and class of service basis. As such, device  100  can provide resource guarantees on a cell and/or packet basis.  
         [0030]     Once a packet enters device  100  on a source port  109 , the packet is transmitted to parser  130  for processing. During processing, packets on each of the ingress and egress ports share system resources  302  and  304 . In specific embodiments, two separate 64 byte bursts of packets are forwarded to the MMU from the local ports and the HiGig port.  FIG. 4  illustrates buffer management mechanisms that are used by MMU  115  to impose resource allocation limitations and thereby ensure fair access to resources. MMU  115  includes an ingress backpressure mechanism  404 , a head of line mechanism  406  and a weighted random early detection mechanism  408 . The Ingress backpressure mechanism  404  supports lossless behaviour and manages buffer resources fairly across ingress ports. Head of line mechanism  406  supports access to buffering resources while optimizing throughput in the system. Weighted random early detection mechanism  408  improves overall network throughput.  
         [0031]     The ingress backpressure mechanism  404  uses packet or cell counters to track the number of packets or cells used on an ingress port basis. The ingress backpressure mechanism  404  includes registers for a set of 8 individually configurable thresholds and registers used to specify which of the 8 thresholds are to be used for every ingress port in the system. The set of thresholds include a limit threshold  412 , a discard limit threshold  414  and a reset limit threshold  416 . If a counter associated with the ingress port packet/cell usage rises above discard limit threshold  414 , packets at the ingress port will be dropped. Based on the counters for tracking the number of cells/packets, a pause flow control is used to stop traffic from arriving on an ingress port that have used more than its fair share of buffering resources, thereby stopping traffic from an offending ingress port and relieving congestion caused by the offending ingress port.  
         [0032]     Specifically, each ingress port keeps track of whether or not it is in an ingress backpressure state based on ingress backpressure counters relative to the set of thresholds. When the ingress port is in ingress backpressure state, pause flow control frames with a timer value of (0xFFFF) are periodically sent out of that ingress port. When the ingress port is no longer in the ingress backpressure state, the pause flow control frame with a timer value of 0x00 is sent out of the ingress port and traffic is allowed to flow again. If an ingress port is not currently in an ingress backpressure state and the packet counter rises above limit threshold  412 , the status for the ingress port transitions into the ingress backpressure state. If the ingress port is in the ingress backpressure state and the packet counter falls below reset limit threshold  416 , the status for the port will transition out of the backpressure state.  
         [0033]     The head of line mechanism  406  is provided to support fair access to buffering resources while optimizing throughput in the system. The head of line mechanism  406  relies on packet dropping to manage buffering resources and improve the overall system throughput. According to an embodiment of the invention, the head of line mechanism  406  uses egress counters and predefined thresholds to track buffer usage on a egress port and class of service basis and thereafter makes decisions to drop any newly arriving packets on the ingress ports destined to a particular oversubscribed egress port/class of service queue. Head of line mechanism  406  supports different thresholds depending on the color of the newly arriving packet. Packets may be colored based on metering and marking operations that take place in the ingress module and the MMU acts on these packets differently depending on the color of the packet.  
         [0034]     According to an embodiment of the invention, head of line mechanism  406  is configurable and operates independently on every class of service queue and across all ports, including the CPU port. Head of line mechanism  406  uses counters that track XQ memory  304  and CBP memory  302  usage and thresholds that are designed to support a static allocation of CBP memory buffers  302  and dynamic allocation of the available XQ memory buffers  304 . A discard threshold  422  is defined for all cells in CBP memory  302 , regardless of color marking. When the cell counter associated with a port reaches discard threshold  422 , the port is transition to a head of line status. Thereafter, the port may transition out of the head of line status if its cell counter falls below a reset limit threshold  424 .  
         [0035]     For the XQ memory  304 , a guaranteed fixed allocation of XQ buffers for each class of service queue is defined by a XQ entry value  430   a - 430   h . Each of XQ entry value  430   a - 430   h  defines how many buffer entries should be reserved for an associated queue. For example, if 100 bytes of XQ memory are assigned to a port, the first four class of service queues associated with XQ entries  430   a - 430   d  respectively may be assigned the value of 10 bytes and the last four queues associated with XQ entries  430   d - 430   h  respectively may be assigned the value of 5 bytes.  
         [0036]     According to an embodiment of the invention, even if a queue does not use up all of the buffer entries reserved for it according to the associated XQ entry value, the head of line mechanism  406  may not assign the unused buffer to another queue. Nevertheless, the remaining unassigned 40 bytes of XQ buffers for the port may be shared among all of the class of service queues associated with the port. Limits on how much of the shared pool of the XQ buffer may be consumed by a particular class of service queue is set with a XQ set limit threshold  432 . As such, set limit threshold  432  may be used to define the maximum number of buffers that can be used by one queue and to prevent one queue from using all of the available XQ buffers. To ensure that the sum of XQ entry values  430   a - 430   h  do not add up to more than the total number of available XQ buffers for the port and to ensure that each class of service queue has access to its quota of XQ buffers as assigned by its entry value  430 , the available pool of XQ buffer for each port is tracked using a port dynamic count register  434 , wherein the dynamic count register  434  keeps track of the number of available shared XQ buffers for the port. The initial value of dynamic count register  434  is the total number of XQ buffers associated with the port minus a sum of the number of XQ entry values  430   a - 430   h . Dynamic count register  434  is decremented when a class of service queue uses an available XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value  430 . Conversely, dynamic count register  434  is incremented when a class of service queue releases a XQ buffer after the class of service queue has exceeded its quota as assigned by its XQ entry value  430 .  
         [0037]     When a queue requests XQ buffer  304 , head of line mechanism  406  determines if all entries used by the queue is less than the XQ entry value  430  for the queue and grants the buffer request if the used entries are less then the XQ entry value  430 . If however, the used entries are greater than the XQ entry value  430  for the queue, head of line mechanism  406  determines if the amount requested is less than the total available buffer or less then the maximum amount set for the queue by the associated set limit threshold  432 . Set limit threshold  432  is in essence a discard threshold that is associated with the queue, regardless of the color marking of the packet. As such, when the packet count associated with the packet reaches set limit threshold  432 , the queue/port enters into a head of line status. When head of line mechanism  406  detects a head of line condition, it sends an update status so that packets can be dropped on the congested port.  
         [0038]     However, due to latency, there may be packets in transition between the MMU  115  and the ports and when the status update is sent by head of line mechanism  306 . In this case, the packet drops may occur at MMU  115  due to the head of line status. In an embodiment of the invention, due to the pipelining of packets, the dynamic pool of XQ pointers is reduced by a predefined amount. As such, when the number of available XQ pointers is equal to or less than the predefined amount, the port is transition to the head of line status and an update status is sent to by MMU  115  to the ports, thereby reducing the number of packets that may be dropped by MMU  115 . To transition out of the head of line status, the XQ packet count for the queue must fall below a reset limit threshold  436 .  
         [0039]     It is possible for the XQ counter for a particular class of service queue to not reach set limit threshold  432  and still have its packet dropped if the XQ resources for the port are oversubscribed by the other class of service queues. In an embodiment of the invention, intermediate discard thresholds  438  and  439  may also be defined for packets containing specific color markings, wherein each intermediate discard threshold defines when packets of a particular color should be dropped. For example, intermediate discard threshold  438  may be used to define when packets that are colored yellow should be dropped and intermediate discard threshold  439  may be used to define when packets that are colored red should be dropped. According to an embodiment of the invention, packets may be colored one of green, yellow or red depending on the priority level assigned to the packet. To ensure that packets associated with each color are processed in proportion to the color assignment in each queue, one embodiment of the present invention includes a virtual maximum threshold  440 . Virtual maximum threshold  440  is equal to the number of unassigned and available buffers divided by the sum of the number of queues and the number of currently used buffers. Virtual maximum threshold  440  ensures that the packets associated with each color are processed in a relative proportion. Therefore, if the number of available unassigned buffers is less than the set limit threshold  432  for a particular queue and the queue requests access to all of the available unassigned buffers, head of line mechanism  406  calculates the virtual maximum threshold  440  for the queue and processes a proportional amount of packets associated with each color relative to the defined ratios for each color.  
         [0040]     To conserve register space, the XQ thresholds may be expressed in a compressed form, wherein each unit represents a group of XQ entries. The group size is dependent upon the number of XQ buffers that are associated with a particular egress port/class of service queue.  
         [0041]     Weighted random early detection mechanism  408  is a queue management mechanism that pre-emptively drops packets based on a probabilistic algorithm before XQ buffers  304  are exhausted. Weighted random early detection mechanism  408  is therefore used to optimize the overall network throughput. Weighted random early detection mechanism  408  includes an averaging statistic that is used to track each queue length and drop packets based on a drop profile defined for the queue. The drop profile defines a drop probability given a specific average queue size. According to an embodiment of the invention, weighted random early detection mechanism  408  may defined separate profiles on based on a class of service queue and packet.  
         [0042]     As illustrated in  FIG. 1 , the MMU  115  receives packet data for storage from the parser  130 . As discussed above, the ingress and egress module  130  includes a two stage parser, where that portion is illustrated schematically in  FIG. 5 . The data are received at ports  501  of the network device, as discussed above. Data may also be received through the CMIC  502 , where that data is passed to an ingress CMIC interface  503 . The interface acts to convert the CMIC data from a CMIC-bus format to an ingress data format. In one embodiment, the data is converted from 45-bit to 172-bit format, such that the latter format includes 128-bit data, 20-bit control and possibly a 24-bit HiGig header. The data are thereafter sent in 64-byte bursts to the ingress arbiter  504 .  
         [0043]     The ingress arbiter  504  receives data from the ports  501  and the ingress CMIC interface  503 , and multiplexes those inputs based on time division multiplexing arbitration. Thereafter, the data are sent to the MMU  510 , where any HiGig header is removed and the format is set to a MMU interface format. Packet attributes are checked, such as end-to-end, Ingress Back Pressure (IBP) or Head of Line (HOL) packets. In addition, the first 128 bytes of data are snooped and the HiGig header is passed to the parser ASM  525 . If the burst of data received contains an end marker, the CRC result and packet length are sent to the result matcher  515 . Also, the packet length is estimated from the burst length and a 16-bit packet ID is generated for debugging purposes.  
         [0044]     The parser ASM  525  converts the 64 byte data burst, at 4 cycles per burst, into 128-byte burst, at 8 cycles per burst. The 128-byte burst data is forwarded to both the tunnel parser  530  and the parser FIFO  528  at the same time to maintain the same packet order. The tunnel parser  530  determines whether any type of tunnel encapsulation, including MPLS and IP tunnelling, is being employed. In addition, the tunnel parser also checks for outer and inner tags. Through the parsing process, the session initiated protocol (SIP) is provided for subnet based VLAN, where the SIP parsing occurs if the packet is an address resolution protocol (ARP), reverse ARP (RARP) or IP packet. A trunk port grid ID is also constructed based on the source trunk map table, unless there is no trunking or if the trunk ID is obtained from the HiGig header.  
         [0045]     The tunnel parser  530  works with the tunnel checker  531 . The tunnel checker checks the checksum of the IP header, and characteristics of UDP tunnelling and IPv6 over IPv4 packets. The tunnel parser  530  utilizes the search engine  520  to determine the tunnel type through preconfigured tables.  
         [0046]     The parser FIFO  528  stores 128 bytes of packet headers and 12 bytes of HiGig headers, that is parsed again by the deep parser  540 . The header bytes are stored while the search engine completes a search and is ready for the deeper search. Other attributes are also maintained by the FIFO, such as valid header length, HiGig header status and the packet ID. The deep parser  540  provides three different types of data, including search results from the search engine  520  that are “flow through,” inner parser results and HiGig module header. Special packet types are determined and passed along to the search engine. The deep parser  540  reads the data from the parser FIFO, where pre-defined fields are parsed. The search engine provides lookup results based on the values passed to the search engine, where the packet ID is checked to maintain packet order.  
         [0047]     The deep parser  540  also uses the protocol checker  541  to check the inner IP header checksum, check for denial of service attack attributes, errors in the HiGig module header and perform a martian check. The deep parser also works with the field processor parser  542 , to parse predefined fields and user defined fields. The predefined fields are received from the deep parser. These fields include MAC destination address, MAC source address, inner and outer tags, Ether type, IP destination and source addresses, Type of Service, IPP, IP flags, TDS, TSS, TTL, TCP flags and flow labels. User defined fields are also parsible, up to 128-bytes of packet header.  
         [0048]     As discussed above, the data that is received on the HiGig port is treated separately from other data received on the local ports. As illustrated in  FIG. 1 , HiGig port  108  has its own buffers and data flows from the port to its own parser  134 . The HiGig parser is illustrated in greater detail than  FIG. 6 . The structure is similar to the two stage parser, illustrated in  FIG. 5 , with several differences. Data received at the HiGig port  601  is forwarded to the HiGig port assembler  604 . The assembler receives the data and HiGig header in 64 byte bursts, with a similar format as used for the local ports. The data are sent to the MMU  610  without the HiGig header and in a MMU interface format.  
         [0049]     The first 128 bytes of the data is snooped and sent, along with the HiGig header, to the deep parser  640 . With similarity to the two stage parser, end-to-end message are checked, with the parsed results being sent in a side band. Also similarly, the CRC and packet lengths are checked and the results are forwarded to the result matcher  615 . In addition, a 16 bit packet ID is generated for use in debugging and tracking the flow of the packet.  
         [0050]     The HiGig version of the deep parser  640  is a subset of the two stage deep parser  540 , and performs similar functions. There is, however, no pass through of information from the search engine  620 , it cannot skip the MPLS header and parse the payload only and does not send deep data to the search engine. In function, the HiGig version of the FP parser  642  is the same as the FP parser  542  discussed above.  
         [0051]     The result matcher is illustrated in greater detail in  FIG. 7 . It is noted that the result matcher may be used commonly between the parsers or each parser may utilize its own result matcher. In the embodiment illustrated, both types of ports  710  &amp;  720  receive data and forward quantities to the result checker through the actions of the ingress assembler  715  and the ingress arbiter  725 . The quantities include port number, presence of EOF, the CRC and the packet length. The result matcher acts as a series of FIFOs to match search results through the use of the search engine  705 . The tag and the MIB event are matched with the packet length and the CRC status on a per port basis. The search results are provided every eight cycles for network ports and eight cycles for the high speed port. The structure allows for results to be stored in the result matcher per port if there is a delay that is longer than the incoming packet time and awaiting the end of packet results when the search delay is shorter than the incoming packet time.  
         [0052]     After the process of parsing and evaluating of data received, a forwarding decision is made with regard to the received information. The forwarding decision is generally made as to what destination port the packet data should be sent to, although the decision can be made to drop a packet or forward a packet to a CPU or other controller through the CMIC  111 . On egress, the packet is modified based on the parsing and evaluation of the network device. Such modification can include tagging, modification of header information or addition of a module header, if the egress port is the HiGig port. The modification is performed on a cell basis to avoid delays in the forwarding of the packet data.  
         [0053]      FIG. 8  illustrates a configuration of an egress port arbitration implemented in the present invention. According to  FIG. 8 , MMU  115  also includes a scheduler  802  that provides arbitration across the eight class of service queues  804   a - 804   h  associated with each egress port to provide minimum and maximum bandwidth guarantees. It is noted that while eight classes of service are discussed, other formulations of classes of service are also supported. Scheduler  802  is integrated with a set of minimum and maximum metering mechanisms  806   a - 806   h  that each monitors traffic flows on a class of service basis and an overall egress port basis. Metering mechanisms  806   a - 806   h  support traffic shaping functions and guarantee minimum bandwidth specifications on a class of service queue and/or egress port basis, wherein scheduling decisions by schedule  802  are configured largely via traffic shaping mechanisms  806   a - 406   h  along with a set of control masks that modify how scheduler  802  uses traffic shaping mechanisms  806   a - 806   h.    
         [0054]     As shown in  FIG. 8 , minimum and maximum metering mechanisms  806   a - 806   h  monitor traffic flows on a class of service queue basis and an overall egress port basis. Maximum and minimum bandwidth meters  806   a - 806   h  are used to feed state information to scheduler  802  which responds by modifying its service order across class of service queues  804 . The network device  100  therefore enables system vendors to implement a quality of service model by configuring class of service queues  804  to support an explicit minimum and maximum bandwidth guarantee. In an embodiment of the invention, metering mechanisms  806   a - 806   h  monitor traffic flow on a class of service queue basis, provides state information regarding whether or nor a class of service flow is above or below a specified minimum and maximum bandwidth specification, and transmits the information into scheduler  802  which uses the metering information to modify its scheduling decisions. As such, metering mechanisms  806   a - 806   h  aid in partitioning class of service queues  804  into a set of queues that have not met the minimum bandwidth specification, a set that have met its minimum bandwidth but not its maximum bandwidth specification and a set that have exceeded its maximum bandwidth specification. If a queue is in the set that have not met its minimum bandwidth specification and there are packets in the queue, scheduler  802  services the queue according to the configured scheduling discipline. If a queue is in the set that have met its minimum bandwidth specification but has not exceeded it maximum bandwidth specification and there are packets in the queue, scheduler  802  services the queue according to the configured scheduling discipline. If a queue is in the set that have exceeded its maximum bandwidth specification or if the queue is empty, scheduler  802  does not service the queue.  
         [0055]     The minimum and maximum bandwidth metering mechanisms  806   a - 806   h  may be implemented using a simple leaky bucket mechanism which tracks whether or not a class of service queue  804  has consumed its minimum or maximum bandwidth. The range of the minimum and maximum bandwidth setting for each class of service  804  is between 64 kbps to 16 Gbps, in 64 kbps increments. The leaky bucket mechanism has a configurable number of tokens “leaking” out of buckets, each of which is associated with one of queues  804   a - 804   h , at a configurable rate. In metering the minimum bandwidth for a class of service queue  804 , as packets enter the class of service queue  804 , a number of tokens in proportion to the size of the packet is added to a respective bucket, having a ceiling of bucket high threshold. The leaky bucket mechanism includes a refresh update interface and a minimum bandwidth which defines how many tokens are to be removed every refresh time unit. A minimum threshold is set to indicate whether a flow has satisfied at least its minimum rate and a fill threshold is set to indicate how many tokens are in leaky bucket. When the fill threshold rises above minimum threshold, a flag which indicates that the flow has satisfied its minimum bandwidth specification is set to true. When fill threshold falls below minimum threshold, the flag is set to false.  
         [0056]     After metering mechanisms  806   a - 806   h  indicate that the maximum bandwidth specified has been exceeded high threshold, the scheduler  802  ceases to service the queue and the queue is classified as being in the set of queues that have exceeded it maximum bandwidth specification. A flag is then set to indicate that the queue has exceeded its maximum bandwidth. Thereafter, the queue will only receive service from scheduler  802  when its fill threshold falls below high threshold and the flag indicating that it has exceeded its maximum bandwidth is reset.  
         [0057]     Maximum rate metering mechanism  808  is used to indicate that the maximum bandwidth specified for a port has been exceeded and operates in the same manner as meter mechanisms  806   a - 806   h  when the maximum total bandwidth has been exceeded. According to an embodiment of the invention, the maximum metering mechanism on a queue and port basis generally affects whether or not queue  804  or a port is to be included in scheduling arbitration. As such, the maximum metering mechanism only has a traffic limiting effect on scheduler  802 .  
         [0058]     On the other hand, minimum metering on a class of service queue  804  basis has a more complex interaction with scheduler  802 . In one embodiment of the invention, scheduler  802  is configured to support a variety of scheduling disciplines that mimic the bandwidth sharing capabilities of a weighted fair queuing scheme. The weighted fair queue scheme is a weighted version of packet based fair queuing scheme, which is defined as a method for providing “bit-based round robin” scheduling of packets. As such, packets are scheduled for access to an egress port based on their delivery time, which is computed as if the scheduler is capable of providing bit-based round robin service. A relative weight field influences the specifics of how the scheduler makes use of the minimum metering mechanism, wherein the scheduler attempts to provide a minimum bandwidth guarantee.  
         [0059]     In one embodiment of the invention, the minimum bandwidth guarantee is a relative bandwidth guarantee wherein a relative field determines whether or not scheduler  802  will treat the minimum bandwidth metering settings as a specification for a relative or an absolute bandwidth guarantee. If the relative field is set, the scheduler treats minimum bandwidth  806  setting as a relative bandwidth specification. Scheduler  802  then attempts to provide relative bandwidth sharing across backlogged queues  804 .  
         [0060]     The foregoing description has been directed to specific embodiments of this invention. It will be apparent, however, that other variations and modifications may be made to the described embodiments, with the attainment of some or all of their advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Technology Category: 5