Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/058,603, filed Oct. 1, 2014, which is hereby incorporated by reference herein in its entirety. 
     
    
     STATEMENT REGARDING GOVERNMENT FUNDED RESEARCH 
       [0002]    This invention was made with government support under contract FA8650-10-1-7042 awarded by Defense Advanced Research Projects Agency. The government has certain rights in the invention. 
     
    
     BACKGROUND 
       [0003]    As the number of electronic devices wirelessly communicating with devices connected to the Internet and each other continues to increase, the need to improve mechanisms for long-range, high-data-rate wireless communication similarly increases. Areas for improvement of existing technologies include, for example, the cost of transmitters and receivers, the power used, the range of communications, the size of the transmitters and receivers, the ability to reduce interference between transmitters and receivers, etc. 
         [0004]    Accordingly, new circuits and methods for wireless transmitters are provided. 
       SUMMARY 
       [0005]    Circuits and methods for wireless transmitters are provided. In some embodiments, circuits for a transmitter are provided, the circuits comprising: a digital-to-amplitude converter (DAC) having an input and an output, comprising: a plurality of binary weighted switching transistors, each having a gate coupled to one of a plurality of amplitude control bits, a drain, and a source, and wherein the drain of each of the plurality of binary weighted switching transistors are connected together and wherein the source of each of the plurality of binary weighted switching transistors are connected together; a first transistor having a gate coupled to an input signal and a first bias voltage, a source coupled to the drains of the plurality of binary weighted switching transistors, and a drain; a second transistor having a gate coupled to a second bias voltage, a source coupled to the drain of the first transistor, and a drain; a third transistor having a gate coupled to a third bias voltage, a source coupled to the drain of the second transistor, and a drain; a fourth transistor having a gate coupled to a fourth bias voltage, a source coupled to the drain of the third transistor, and a drain; and an inverter having an input coupled to another amplitude control bit and having an output coupled to the output of the DAC and the drain of the fourth transistor; and an antenna coupled to the output of the DAC. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a schematic of an example of a transmitter in accordance with some embodiments. 
           [0007]      FIG. 2  is a schematic of an example of a frequency multiplier in accordance with some embodiments. 
           [0008]      FIG. 3  is a schematic of an example of phase modulator/shifter in accordance with some embodiments. 
           [0009]      FIG. 4  is a schematic of an example of a mixer in accordance with some embodiments. 
           [0010]      FIG. 5  is a schematic of an example of an array driver in accordance with some embodiments. 
           [0011]      FIG. 6  is a schematic of an example of a limiting amplifier in accordance with some embodiments. 
           [0012]      FIG. 7  is a schematic of an example of a hybrid power digital-to-amplitude converter in accordance with some embodiments. 
           [0013]      FIG. 8  is a schematic of an example of a two-stack driver in accordance with some embodiments. 
           [0014]      FIG. 9  is a schematic of an example of an adaptive bias circuit in accordance with some embodiments. 
           [0015]      FIG. 10  is a schematic of an example of a four-stack amplifier in accordance with some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    In accordance with some embodiments, circuits and methods for wireless transmitters are provided. 
         [0017]    Turning to  FIG. 1 , an example  100  of a digital polar phased array transmitter in accordance with some embodiments is shown. In some embodiments, any suitable number of transmitters  100  can be used in a transmitter application. For example, in some embodiments, one transmitter (having four (for example) elements (described below)) can be used. In another embodiment, four transmitters (each having four (for example) elements (described below)) can be used, for example. 
         [0018]    In some embodiments, any suitable modulation technique can be used with transmitter(s)  100 . For example, in some embodiments, QAM64 modulation can be used. 
         [0019]    As illustrated, transmitter  100  includes a local oscillator reference input  102 , a frequency multiplier  104 , a quadrature hybrid  106 , a resistor  108 , a phase modulator  110 , a digital interface  112 , an array driver  114 , digital polar transmitter elements  116 ,  118 ,  120 , and  122 , transmitter outputs  124 ,  126 ,  128 , and  130 , serial digital inputs  132 , a global biasing circuit  170 , and an ESD circuit  172 . 
         [0020]    A local oscillator reference signal is received by transmitter  100  at input  102 . Any suitable local oscillator reference signal having any suitable frequency can be used. For example, in some embodiments, local oscillator reference signal can have a frequency of 30 GHz. 
         [0021]    The local oscillator reference signal is received by frequency multiplier  104  and multiplied to a higher frequency. Any suitable frequency multiplier can be used (e.g., a frequency multiplier as described below in connection with  FIG. 2  can be used), and the local oscillator reference signal can be multiplied by any suitable amount. For example, in some embodiments, the frequency multiplier can multiply the local oscillator reference signal by two. 
         [0022]    The output of frequency multiplier  104  can be received by quadrature hybrid  106 . The quadrature hybrid can be any suitable quadrature hybrid in accordance with some embodiments. As illustrated, resistor  108  can be connected from one of the inputs of the quadrature hybrid to ground to provide a reference impedance. Any suitable resistor can be used in some embodiments. For example, a 50 ohm resistor can be used. 
         [0023]    In-phase and quadrature components of the multiplied local oscillator reference signal can be output by hybrid  106  to phase modulator  110 . The phase modulator can be any suitable phase modulator, such as the phase modulator/shifter described below in connection with  FIGS. 3 and 4 . The phase modulator can be controlled by phase control outputs [P 0,I -P 7,I ] and [P 0,Q -P 7,Q ] of digital interface  112 . 
         [0024]    Array driver  114  can receive the output of phase modulator  110  and provide a drive signal to digital polar transmitter elements  116 ,  118 ,  120 , and  122  that is split evenly among the digital polar transmitter elements. Any suitable array driver can be used in some embodiments. For example, in some embodiments, the array driver described below in connection with  FIG. 5  can be used. 
         [0025]    Digital polar transmitter elements  116 ,  118 ,  120 , and  122  can drive transmitter outputs  124 ,  126 ,  128 , and  130  in response to the drive signal from array driver  114  and amplitude control outputs [A 0 -A 7 ] of digital interface  112 . Each of transmitter outputs  124 ,  126 ,  128 , and  130  can be connected to a suitable antenna. For example, in some embodiments, the antenna(s) can be phased array antennas, on-printed-circuit-board antennas, and/or any other suitable type of antenna. Any suitable number of digital polar transmitter elements can be used in some embodiments. For example, in some embodiments, four digital polar transmitter elements can be used to drive a 2×2 array of four antennas. 
         [0026]    As further shown in  FIG. 1 , digital polar transmitter elements  116 ,  118 ,  120 , and  122  can each include a resistor  140 , a quadrature hybrid  142 , a phase shifter  144 , a limiting amplifier  146 , and a hybrid power digital amplitude converter (DAC)  148 . 
         [0027]    The drive signal from array driver  114  can be provided to quadrature hybrid  142 . The quadrature hybrid can be any suitable quadrature hybrid in accordance with some embodiments. As illustrated, resistor  140  can be connected from one of the inputs of the quadrature hybrid to ground to provide a reference impedance. Any suitable resistor can be used in some embodiments. For example, a 50 ohm resistor can be used. 
         [0028]    In-phase and quadrature components of the drive signal from array driver  114  can be output by hybrid  142  to phase shifter  144 . The phase shifter can be any suitable phase shifter, such as the phase modulator/shifter described below in connection with  FIGS. 3 and 4 . The phase shifter can be controlled by control signals φ 1 , φ 2 , φ 3 , and φ 4  from a controller  174 . These control signals can be used to control the phase of the signal to be transmitted by the digital polar transmitter element for any suitable purpose, such as for beamforming. 
         [0029]    Controller can include any suitable hardware processor (e.g., a microprocessor, microcontroller, dedicated control logic, a digital signal processor, etc.), a scan chain, registers, memory, interfaces, inputs, outputs, etc. and can perform any suitable functions, such as controlling phase shifters  144 , controlling bias functions, performing specialized processing for phased arrays, compensating for various implementation non-idealities that result in beam pointing error, etc. 
         [0030]    The outputs of phase shifter  144  can be provided to limiting amplifier  146 . The limiting amplifier can be any suitable limiting amplifier, such as the limiting amplifier described below in connection with  FIG. 6 . 
         [0031]    The output of limiting amplifier  146  can be provided to hybrid power DAC  148 . Hybrid power DAC  148  can be any suitable hybrid power DAC in some embodiments. For example, hybrid power DAC  148  can be implemented using the hybrid power DAC described below in connection with  FIG. 7 . 
         [0032]    As shown in  FIG. 1 , digital interface  112  can include variable gain amplifiers (VGAs)  158 , continuous time linear equalizers (CTLEs)  160 , and demultiplexers  162 ,  164 , and  166 . Digital interface can receive digital serial inputs  132 . More particularly, inputs  132  can include I phase control inputs, Q phase control inputs, amplitude control inputs, and a clock at inputs  150 ,  154 ,  152 , and  156 , respectively. Based on the inputs received at  132 , the digital interface can generate phase control outputs [P 0,I -P 7,I ] and [P 0,Q -P 7,Q ] and amplitude control outputs [A 0 -A 7 ] from demultiplexers  162 ,  166 , and  164 , respectively. 
         [0033]    Global biasing circuitry  170  can be provided, as known in the art, to generate biasing voltages in circuit  100  in accordance with some embodiments. 
         [0034]    ESD circuitry  172  can be provided, as known in the art, to protect circuit  100  from electrostatic discharge and over-voltage conditions in accordance with some embodiments. 
         [0035]      FIG. 2  shows an example  200  of a frequency multiplier that can be used to implement frequency multiplier  104  of  FIG. 1  in some embodiments. As shown, a local oscillator reference signal can be received at node  202 , the signal multiplied by two, and then the resulting signal output at node  204 . In some embodiments, match blocks  206  and  208  can include any suitable components for matching the impedance of the points on the left and right of each match block. For example, in some embodiments, match blocks  206  and  208  can include inductors, spirals, transmission lines, and/or capacitors. 
         [0036]    Turning to  FIG. 3 , an example  300  of a phase modulator/shifter that can be used as phase modulator  110  and/or phase shifter  144  of  FIG. 1  in some embodiments. As shown, phase modulator/shifter  300  includes mixers  302  and  304 . Any suitable mixers can be used as mixers  302  and  304 . For example, in some embodiments, example mixer  400  described below in connection with  FIG. 4  can be used as mixers  302  and/or  304 . 
         [0037]    As shown in  FIG. 4 , mixer  400  includes eight switching transistors represented in this figure by transistors  402 ,  404 ,  406 , and  408 . The transistors other than transistor  408  (the most significant bit (MSB) transistor) are binary weighted with weights of W, 2W, . . . , 2 6 W, where W represents a given combination of finger width and number of fingers in a transistor. Any suitable combination of finger width and number of fingers can be used in the transistors for W, such as a finger width of 0.152 micron and one finger, in some embodiments. 
         [0038]    The gates of these transistors are connected to inputs b 0 , b 1 , b 2 , . . . , b 7 . These bits can be provided by phase control bits [P 0,I -P 7,I ], [P 0,Q -P 7,Q ], φ 1 , φ 2 , φ 3 , or φ 4  shown in  FIG. 1  in some embodiments. The binary value that is provided to the inputs, determines the amount of modulation or shift of the input signal such that a higher value turns on a higher total weighting of switches, resulting in a higher current flow through the switches. Although eight transistors and inputs are shown, any suitable number of inputs and transistors can be used in some embodiments. A bias voltage, V b , can also be provided to calibrate the shifter to account for variations in process, voltage, and temperature. 
         [0039]    Turning to  FIG. 5 , an example  500  of an array driver that can be used to implement array driver  114  of  FIG. 1  is shown in accordance with some embodiments. As shown, an input signal can be presented at inputs  502  of driver  500 , the signal will be amplified, and the resulting signal will be provided at node  504 . 
         [0040]    Turning to  FIG. 6 , an example  600  of a limiting amplifier that can be used to implement limiting amplifier  146  of  FIG. 1  is shown in accordance with some embodiments. As shown, an input signal can be presented at node  602  of limiting amplifier  600 , the signal will be amplified, and the resulting signal will be provided at node  504 . 
         [0041]      FIG. 7  shows an example  700  of a hybrid power DAC that can be used to implement hybrid power DAC  148  of  FIG. 1  in accordance with some embodiments. As shown, in some embodiments, hybrid power DAC  700  can be implemented as a differential Class-E power amplifier with four stacked transistors that is augmented with trail transistors (at the common source node) and a supply inverter (connected to the differential DC-feed spiral of the four-stack Class E power amplifier) to incorporate amplitude modulation capability. 
         [0042]    In some embodiments, hybrid power DAC  700  includes inputs  702  and  704 , outputs  706  and  708 , inverters  710 , switching transistors  712 ,  714 , and  716 , stacked transistors  717 ,  718 ,  720 , and  722 , DC feed inductors (implemented as transmission lines)  724 , gate bias inputs  726 ,  728 ,  730 , and  732 , two-stack drivers  734 , and match blocks  736 . 
         [0043]    As shown in  FIG. 7 , hybrid power DAC  700  includes two inverters  710  and N−1 switching transistors, represented in this figure by transistors  712 ,  714 , and  716 . The N−1 switching transistors (represented by transistors  712 ,  714 , and  716 ) are binary weighted with weights of W 1 , 2W 1 , . . . , 2 N-1 W 1 , where W 1  represents a given combination of finger width and number of fingers in a transistor. Any suitable combination of finger width and number of fingers can be used in the transistors for W 1 , such as a finger width of 2.793 micron and two fingers, in some embodiments. The gates of the transistors are connected to inputs b 0 , b 1 , b 2 , . . . , b N-1  and the input to the inverter is connected to input b N  (the most significant bit (MSB)). 
         [0044]    As suggested by the use of N in  FIG. 7 , any suitable number of switching transistors, and hence inputs b 0  . . . b N-1  can be used in some embodiments. 
         [0045]    The binary value that is provided to inputs b 0 , b 1 , b 2 , . . . , b N  determines the amount of amplification provided by the hybrid power DAC. These bits can be provided by amplitude control bits [A 0 -A 7 ] shown in  FIG. 1  in some embodiments. More particularly, a higher value at inputs b 0 , b 1 , b 2 , . . . , b N-1  turns on a higher total weighting of the switching transistors, resulting in a higher current flow through the switching transistors, and the value of input b N  at the input to inverter  710  determines the supply voltage V DD,PA  supplied to the stack of transistors including stacked transistors  717 ,  718 ,  720 , and  722  and the switching transistors. 
         [0046]    The manner in which this amplification is achieved is further illustrated in connection with  FIG. 10 . As shown, for a given input at the gate of transistor M 1   1002 , a voltage between ground and 2V DD  (represented by voltage  1010 ) (where, V DD  here represents the nominal voltage supply in the technology used, for example, 1.2V nominally in 45 nm SOI CMOS) is produced at the source of transistor M 2   1004 . This results in a voltage between V ON  and 2V DD  being present at the gate of transistor M 2   1004  through capacitance Cgs between the source and the gate of transistor M 2   1004  (which capacitance is inherently present in transistor M 2   1004 ), resulting in a voltage between ground and 4V DD  (represented by voltage  1012 ) being produced at the source of transistor M 3   1006 . This results in a voltage between V ON  and 4V DD  being present at the gate of transistor M 3   1006  through capacitance Cgs between the source and the gate of transistor M 3   1006 , resulting in a voltage between ground and 6V DD  (represented by voltage  1014 ) being produced at the source of the transistor above transistor M 3   1006 . This process is repeated for the transistors going upward along the stack represented by transistors  1002 ,  1004 ,  1006 , and  1008  until a voltage of between V ON  and 2(n−1)V DD  (represented by voltage  1016 ) is produced at the gate of transistor M n    1008 , which results in a voltage between ground and 2nV DD  being produced at the drain of transistor M n    1008  and the output of the stack. 
         [0047]    As stated above, whether the output of the stack is at ground or 2nV DD  depends on the input at the gate of transistor M 1   1002 . Referring back to  FIG. 7 , the corresponding inputs in the hybrid power DAC are at the gates of transistors M 1   717 . As shown, these input are controlled by the outputs of two-stack drivers  734 , which are driven by inputs  702  and  704 . 
         [0048]    An example  800  of a two-stack driver that can be used for two-stack driver  734  in accordance with some embodiments is shown in  FIG. 8 . As shown, the input to the two-stack driver is provided at node  802  and the output is produced at node  804 . 
         [0049]    As shown in  FIG. 7 , the outputs of two-stack drivers  734  are connected to the gates of transistors M 1   717  by match blocks  736 . In some embodiments, match blocks  736  can include any suitable components for matching the impedance of the points on the left and right of each match block. For example, in some embodiments, match blocks  736  can include inductors, spirals, transmission lines, and/or capacitors. 
         [0050]    As also shown in  FIG. 7 , the gates of transistors M 1   717 , M 2   718 , M 3   720 , and M 4   722  are biased by bias voltages V g1 , V g2 , V g3 , and V g4 . These bias voltages can be produced in any suitable manner. For example, in some embodiments, for each hybrid power DAC  700 , an adaptive bias circuit, such as adaptive bias circuit  900  shown in  FIG. 9 , can be provided. 
         [0051]    As illustrated in  FIG. 9 , circuit  900  includes a voltage divider  902  formed from four resistors R 1 . These resistors can have any suitable value. The voltage divider is powered by V DD,PA , which as described in  FIG. 7  is variable and controlled by the output of inverters  710 . Voltages V 1 , V 2 , and V 3  shown in  FIG. 9  are provided to transistors  904 ,  906 , and  908 , respectively. The bias voltages are then produced at the nodes labelled V g1 , V g2 , V g3 , and V g4 . 
         [0052]    Resistors R big  can have any suitable values sufficiently large compared to the gate impedance (of the gates connected to the corresponding bias voltage) to have suitable performance but not too large so as to affect modulation speed. In some embodiments, R big  can be a 1 kΩ resistor. 
         [0053]    In some embodiments, transistor  910  can be implemented as a bank of parallel binary weighted transistors (e.g., like the binary weighted transistors described above in connection with  FIGS. 4 and 7 ) so that the bias voltages produced by circuit  900  can be controlled by controller  174  of  FIG. 1 . In some of these embodiments, any suitable number of parallel binary weighted transistors can be provided, and each of the transistors can have any suitable weighting(s). When such control is not needed, transistor  910  can be a single transistor. 
         [0054]    Although specific components having specific properties (e.g., resistances, capacitance, sizes, relative sizes, voltages, etc.) are shown in  FIGS. 1-10 , one or more of the components in any one or more of these figures can be omitted or substituted with one or more alternate components having one or more different properties, in some embodiments. 
         [0055]    The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the claimed subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects. 
         [0056]    Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and the numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is only limited by the claims which follow. Features of the disclosed embodiments can be combined and rearranged in various ways.

Technology Category: 5