Patent Document

FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor devices, and, more particularly, to such semiconductor devices having compressively strained Silicon channels. 
       BACKGROUND OF THE INVENTION 
       [0002]    Conventional Metal Oxide Semiconductor (MOS) technology integration schemes are increasingly pushed to reduce device dimensions. The downscaling of the physical dimensions of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has led to performance improvements of integrated circuits and an increase in the number of transistors per chip. For example, current integration schemes are attempting to reduce technology node dimensions to  22  nanometers (nm) or less. As the device dimensions are reduced to these small values, a number of problems have been identified related to geometry effects. For example, the addition of some technology boosters, such as an application of strain to the channel and high dielectric constant (“high k”) gate material appears to be crucial for maintaining the scaling trend of MOSFETs. Various strain engineering techniques are employed to modulate strain in the transistor channel, in order to enhance the carrier (electron or hole) transport. Strained silicon is generally understood as a layer of silicon wherein the silicon atoms have been stretched out or contracted beyond their normal interatomic distance. 
         [0003]    Some examples of these techniques include embedded silicon germanium (e-SiGe) in source/drain regions, stress liners, epitaxial growth of strained Silicon (Si) channel on relaxed SiGe, and epitaxial growth of strained SiGe channel on Silicon. The aggressive scaling of the MOSFET pitch, however, has increasingly diminished the effectiveness of some process-induced strain technologies, such as the stress liners and the embedded SiGe. A need therefore exists for improved strain engineering techniques. 
         [0004]    Epitaxial growth of strained channels has been suggested as a viable option for inducing additional strain. It is known that electron and hole transport properties can be enhanced by tensile and compressive strains, respectively. The latter is conventionally achieved by the growth of SiGe directly on Si, wherein the amount of strain increases with the Ge content. The increase of the transistor off current due to the reduction of the SiGe bandgap as a result of the increase in the Ge content can, however, counteract the performance enhancement achieved by the higher strain level in SiGe. 
         [0005]    U.S. patent application Ser. No. 13/037,944, filed Mar. 1, 2011, entitled “Growing Compressively Strained Silicon Directly on Silicon at Low Temperatures,” incorporated by reference herein, discloses techniques for growing compressively strained Silicon on Silicon at low temperatures. A need remains for MOSFET structures having compressively strained Silicon channels. 
       SUMMARY OF THE INVENTION 
       [0006]    Generally, MOSFET structures are provided having a compressively strained silicon channel. According to one aspect of the invention, a semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. 
         [0007]    The compressively strained silicon layer can be formed, for example, on the portion of the silicon substrate at low temperatures. The compressively strained silicon layer can comprise, for example, (i) a highly doped epitaxial embedded silicon layer formed on the portion of the silicon substrate in one or more recessed source/drain pockets below spacers; (ii) an undoped epitaxial embedded silicon layer formed on the portion of the silicon substrate in the channel and further comprising a layer of embedded silicon germanium in one or more recessed source/drain pockets below spacers; or (iii) an undoped epitaxial embedded silicon layer fowled on the portion of the silicon substrate in the channel and a compressively strained, highly doped epitaxial embedded silicon layer formed in one or more recessed source/drain pockets below spacers. 
         [0008]    A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a sectional view of an exemplary wafer manufactured pursuant to the techniques described in. U.S. patent application Ser. No. 13/037,944; 
           [0010]      FIGS. 2 and 3  illustrate cross-sectional views of an exemplary p-channel MOSFET (pFET) structure after being processed in a known manner to provide recessed source/drain pockets below spacers adjacent to a gate stack; 
           [0011]      FIG. 4  illustrates an exemplary wafer comprising a compressively strained, highly doped epitaxial embedded silicon layer grown on a crystalline silicon substrate; 
           [0012]      FIGS. 5 and 6  illustrate cross-sectional views of exemplary pFET structures incorporating aspects of the present invention; 
           [0013]      FIG. 7  illustrates an exemplary wafer comprising a compressively strained, undoped epitaxial embedded silicon layer grown on a crystalline silicon substrate; and 
           [0014]      FIGS. 8 through 11  illustrate cross-sectional views of exemplary pFET structures according to alternate embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0015]    The present invention provides a number of improved MOSFET structures having compressively strained Silicon channels.  FIG. 1  is a sectional view of an exemplary wafer  10  manufactured pursuant to the techniques described in U.S. patent application Ser. No. 13/037,944, filed Mar. 1, 2011, entitled “Growing Compressively Strained Silicon Directly on Silicon at Low Temperatures,” incorporated by reference herein. The wafer  10  includes a crystalline silicon substrate  12  and a compressively strained, epitaxial silicon layer  14  deposited directly thereon. The layer  14  can optionally include elements in addition to silicon, but does not necessarily require such elements other than hydrogen in an amount sufficient to impart the desired strain. In addition, the substrate  12  does not need to be comprised entirely of crystalline silicon. It is only necessary that the surface upon which the silicon layer is formed be comprised of crystalline silicon. In the exemplary embodiment of  FIG. 1 . the strain in the layer  14  is substantially uniform throughout and at least partially attributable to hydrogen atoms incorporated in the layer. 
         [0016]      FIG. 2  illustrates a cross-sectional view of an exemplary p-channel MOSFET (pFET) structure  200  after being processed in a known manner to provide recessed source/drain pockets  210  below spacers  260 . As shown in  FIG. 2 , the exemplary pFET structure  200  is formed on a Silicon-On-Insulator (SOI) wafer comprising one or more silicon substrate layers  230  and a buried oxide (BOX) layer  240 . A gate stack  250  is formed above the top silicon layer  230 . The gate stack  250  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  250  may be altered to optimize transistor performance. The spacers  260  are provided on the sidewalls of the gate stacks  250 . The spacers  260  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  260  may serve to protect the sidewalls of the gate stack  250  during subsequent processing, in a known manner. 
         [0017]    As discussed hereinafter, a compressively strained Silicon layer is formed on the top Silicon substrate layer  230  in the recessed source/drain pockets  210  below spacers  260 , in accordance with aspects of the present invention. 
         [0018]    The recessed source/drain pockets  210  below spacers  260  may be obtained by exposing the top silicon substrate layer  230  to a reactive ion etching (RIE) or another suitable process to form the recesses  210  in the region below the spacers  260 . A reactive ion etching (RIE) process or another suitable process will remove portions of the top silicon layer  230 . The etchant selectively removes the silicon layer  230  under the spacer regions  260  and may be, for example, HCl, Chlorine, Fluorine, SF6 and other etchant gases and mixtures of thereof. 
         [0019]      FIG. 3  illustrates a cross-sectional view of an alternate exemplary p-channel MOSFET (pFET) structure  300  after being processed in a known manner to provide recessed source/drain pockets  310  below spacers  360 . As shown in  FIG. 3 , the exemplary pFET structure  300  is formed on a bulk substrate comprising at least one more silicon substrate layer  330 . A gate stack  350  is formed above the top silicon layer  330 . The gate stack  350  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  350  may be altered to optimize transistor performance. The spacers  360  are provided on the sidewalls of the gate stacks  350 . The spacers  360  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  360  may serve to protect the sidewalls of the gate stack  350  during subsequent processing, in a known manner. 
         [0020]    As indicated above, a compressively strained Silicon layer formed on a Silicon substrate is formed in the recessed source/drain pockets  310  below spacers  360  in accordance with aspects of the present invention. 
         [0021]    The recessed source/drain pockets  310  below spacers  360  may be obtained in a similar manner to  FIG. 2 . 
         [0022]      FIG. 4  illustrates an exemplary wafer  400  manufactured pursuant to the techniques described in U.S. patent application Ser. No. 13/037,944, filed Mar. 1, 2011, entitled “Growing Compressively Strained Silicon Directly on Silicon at Low Temperatures,” incorporated by reference herein. The exemplary structure  400  of  FIG. 4  is employed by the embodiments of  FIGS. 5 and 6  to fill the recessed source/drain pockets  210 ,  310  in order to exert a uniaxial compressive strain to the channel. 
         [0023]    As shown in  FIG. 4 , the wafer  400  comprises a crystalline silicon substrate  412  and a compressively strained, highly doped epitaxial embedded silicon layer  414  grown directly thereon. The dopant materials may comprise, for example, an acceptor dopant, such as Boron, that can be incorporated in-situ with the epitaxial growth process. It can be shown that the wafer  400  of  FIG. 4  exhibits a compressive strain of approximately 0.23%. 
         [0024]      FIG. 5  illustrates a cross-sectional view of an exemplary pFET structure  500  incorporating aspects of the present invention. As shown in  FIG. 5 , the exemplary pFET structure  500  employs the structure  400  of  FIG. 4  to fill the recessed source/drain pockets  210 , in order to exert a uniaxial compressive strain  540  to the channel  535 . The exemplary pFET structure  500  is formed on a Silicon-On-Insulator (SOI) wafer comprising one or more silicon substrate layers  230  and a buried oxide (BOX) layer  240 , in a similar manner to  FIG. 2 . A gate stack  250  is formed above the top silicon layer  230 . The gate stack  250  can he comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  250  may be altered to optimize transistor performance. The spacers  260  are provided on the sidewalls of the gate stacks  250 . The spacers  260  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  260  may serve to protect the sidewalls of the gate stack  250  during subsequent processing, in a known manner. 
         [0025]    As shown in  FIG. 5 , a compressively strained, highly doped epitaxial embedded silicon layer  510  is formed on the top Silicon substrate layer  230  in the recessed source/drain pockets  210  below spacers  260 , using the techniques of  FIG. 4  and in accordance with aspects of the present invention. The recessed source/drain pockets  210  below spacers  260  may be obtained in a similar manner to  FIG. 2 . 
         [0026]      FIG. 6  illustrates a cross-sectional view of an alternate exemplary pFET structure  600  incorporating aspects of the present invention. As shown in  FIG. 6 , the exemplary pFET structure  600  employs the structure  400  of  FIG. 4  to fill the recessed source/drain pockets  310 , in order to exert a uniaxial compressive strain  640  to the channel  635 . As shown in  FIG. 6 , the exemplary pFET structure  600  is formed on a bulk substrate comprising at least one more silicon substrate layer  330 . A gate stack  350  is formed above the top silicon layer  330 . The gate stack  350  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  350  may be altered to optimize transistor performance. The spacers  360  are provided on the sidewalls of the gate stacks  350 . The spacers  360  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  360  may serve to protect the sidewalls of the gate stack  350  during subsequent processing, in a known manner. 
         [0027]    As shown in  FIG. 6 , a compressively strained, highly doped epitaxial embedded silicon layer  610  is formed on the top Silicon substrate layer  330  in the recessed source/drain pockets  310  below spacers  360 , using the techniques of  FIG. 4  and in accordance with aspects of the present invention. The recessed source/drain pockets  310  below spacers  360  may be obtained in a similar manner to  FIG. 2 .  FIG. 7  illustrates an exemplary wafer  700  manufactured pursuant to the techniques described in U.S. patent application Ser. No. 13/037,944, filed Mar. 1, 2011, entitled “Growing Compressively Strained Silicon Directly on Silicon at Low Temperatures,” incorporated by reference herein. The exemplary structure  700  of  FIG. 7  is employed by the embodiments of  FIGS. 8 and 9  to fill the channel region in order to exert a compressive strain to the channel. The strain can be either uniaxial or biaxial depending on the dimensions and the geometry of the channel. Long and narrow channel geometry is preferred to exert a uniaxial strain. 
         [0028]    As shown in  FIG. 7 , the wafer  700  comprises a crystalline silicon substrate  712  and a compressively strained, undoped epitaxial embedded silicon layer  714  grown directly thereon. It can be shown that the wafer  700  of  FIG. 7  exhibits a compressive strain of approximately 0.8%. 
         [0029]      FIG. 8  illustrates a cross-sectional view of an exemplary pFET structure  800  incorporating aspects of the present invention. As shown in  FIG. 8 , the exemplary pFET structure  800  employs the structure  700  of  FIG. 7  to fill the channel region  835  and thereby exert a uniaxial compressive strain  840  to the channel  835 . In addition, a layer  810  of embedded silicon germanium (e-SiGe) is formed in the recessed source/drain pockets  210  of  FIG. 2 . 
         [0030]    The exemplary pFET structure  800  is formed on a Silicon-On-Insulator (SOI) wafer comprising one or more silicon substrate layers  230  and a buried oxide (BOX) layer  240 , in a similar manner to  FIG. 2 . A gate stack  250  is formed above the top silicon layer  230 . The gate stack  250  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  250  may be altered to optimize transistor performance. The spacers  260  are provided on the sidewalls of the gate stacks  250 . The spacers  260  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  260  may serve to protect the sidewalls of the gate stack  250  during subsequent processing, in a known manner. 
         [0031]    As shown in  FIG. 8 , a compressively strained, undoped epitaxial embedded silicon layer  820  is formed on the top Silicon substrate layer  230  in the channel region  835 , using the techniques of  FIG. 7 , and a layer  810  of e-SiGe is formed in the recessed source/drain pockets  210  below spacers  260 , in accordance with aspects of the present invention. The recessed source/drain pockets  210  below spacers  260  may be obtained in a similar manner to  FIG. 2 . 
         [0032]      FIG. 9  illustrates a cross-sectional view of an alternate exemplary pFET structure  900  incorporating aspects of the present invention. As shown in  FIG. 9 , the exemplary pFET structure  900  employs the structure  700  of  FIG. 7  to fill the channel region  935  and thereby exert a uniaxial compressive strain  940  to the channel  935 . In addition, a layer  910  of embedded silicon germanium (e-SiGe) is formed in the recessed source/drain pockets  310  of  FIG. 3 . 
         [0033]    As shown in  FIG. 9 , the exemplary pFET structure  900  is formed on a bulk substrate comprising at least one more silicon substrate layer  330 . A gate stack  350  is formed above the top silicon layer  330 . The gate stack  350  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  350  may be altered to optimize transistor performance. The spacers  360  are provided on the sidewalls of the gate stacks  350 . The spacers  360  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  360  may serve to protect the sidewalls of the gate stack  350  during subsequent processing, in a known manner. 
         [0034]    As shown in  FIG. 9 , compressively strained, undoped epitaxial embedded silicon layer  920  is formed on the top Silicon substrate layer  330  in the channel region  935 , using the techniques of  FIG. 7 , and a layer  910  of e-SiGe is formed in the recessed source/drain pockets  310  below spacers  360 , in accordance with aspects of the present invention. The recessed source/drain pockets  310  below spacers  360  may be obtained in a similar manner to  FIG. 2 . 
         [0035]      FIG. 10  illustrates a cross-sectional view of an exemplary pFET structure  1000  incorporating aspects of the present invention. As shown in  FIG. 10 , the exemplary pFET structure  1000  employs aspects of the structures  400  and  800  of  FIGS. 4 and 8 , respectively. As shown in  FIG. 10 , the exemplary pFET structure  1000  employs a compressively strained, undoped epitaxial embedded silicon layer  1020  in the channel region  1035 , using the techniques of  FIG. 7 , to exert a uniaxial compressive strain  1040  to the channel  1035 . In addition, a compressively strained, highly doped epitaxial embedded silicon layer  1010  is formed in the recessed source/drain pockets  210 . 
         [0036]    The exemplary pFET structure  1000  is formed on a Silicon-On-Insulator (SOI) wafer comprising one or more silicon substrate layers  230  and a buried oxide (BOX) layer  240 , in a similar manner to  FIG. 2 . A gate stack  250  is formed above the top silicon layer  230 . The gate stack  250  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  250  may be altered to optimize transistor performance. The spacers  260  are provided on the sidewalls of the gate stacks  250 . The spacers  260  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  260  may serve to protect the sidewalls of the gate stack  250  during subsequent processing, in a known manner. 
         [0037]    As shown in  FIG. 10 , a compressively strained, undoped epitaxial embedded silicon layer  1020  is formed on the top Silicon substrate layer  230  in the channel region  1035 , using the techniques of  FIG. 7 , and a layer  1010  of a compressively strained, highly doped epitaxial embedded silicon is formed in the recessed source/drain pockets  210  below spacers  260 , in accordance with aspects of the present invention. The recessed source/drain pockets  210  below spacers  260  may be obtained in a similar manner to  FIG. 2 . 
         [0038]      FIG. 11  illustrates a cross-sectional view of an alternate exemplary pFET structure  1100  incorporating aspects of the present invention. As shown in  FIG. 11 , the exemplary pFET structure  1100  employs a compressively strained, undoped epitaxial embedded silicon layer  1120  in the channel region  1135 , using the techniques of  FIG. 7 , to exert a uniaxial compressive strain  1140  to the channel  1135 . In addition, a compressively strained, highly doped epitaxial embedded silicon layer  1110  is formed in the recessed source/drain pockets  310 . 
         [0039]    As shown in  FIG. 11 , the exemplary pFET structure  1100  is formed on a bulk substrate comprising at least one more silicon substrate layer  330 . A gate stack  350  is formed above the top silicon layer  330 . The gate stack  350  can be comprised of, for example, a gate dielectric layer and a gate conductor layer (not shown). As is known in the art, the exact composition of the gate stack  350  may be altered to optimize transistor performance. The spacers  360  are provided on the sidewalls of the gate stacks  350 . The spacers  360  are typically comprised of an oxide, nitride or oxynitride material, including combinations and multilayers thereof. The spacers  360  may serve to protect the sidewalls of the gate stack  350  during subsequent processing, in a known manner. 
         [0040]    As shown in  FIG. 11 , a compressively strained, undoped epitaxial embedded silicon layer  1120  is formed on the top Silicon substrate layer  330  in the channel region  1135 , using the techniques of  FIG. 7 , and a layer  1110  of compressively strained, highly doped epitaxial embedded silicon is formed in the recessed source/drain pockets  310  below spacers  360 , in accordance with aspects of the present invention. The recessed source/drain pockets  310  below spacers  360  may be obtained in a similar manner to  FIG. 2 . As shown in  FIG. 11 , the alternate exemplary pl-ET structure  1100  optionally further comprises raised source/drain regions  1130  grown on the embedded S/D regions. The optional raised source/drain regions  1130  further reduce the series resistance, in a known manner. The raised source/drain regions  1130  can be comprised of, for example, Si x Ge 1-x  with 0.5&lt;x&lt;1. The raised source/drain regions  1130  shown in  FIG. 11  can optionally be added to all of the pFET structures described herein, as would be apparent to a person of ordinary skill in the art. 
         [0041]    The disclosed techniques can be employed in combination with other methods to further enhance the strain in the channel, such as stress liners and strained channels. The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed structures and method which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. Accordingly, while the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention, as defined by the following claims. 
         [0042]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0043]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Technology Category: 5