Patent Document

[0001]     This application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. JP2005-273752 filed Sep. 21, 2005, the entire content of which is hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a circuit for outputting only a normal signal pulse by removing a noise signal.  
         [0004]     2. Description of the Related Arts  
         [0005]     As illustrated in  FIG. 2 , in a conventional noise removing circuit for removing noise from a digital signal, an input signal is branched into two signals: a signal to be inputted to a gate circuit (corresponding to an AND gate circuit  16  of  FIG. 2 ) and a signal to be inputted to a delay circuit  15 . The delay circuit  15  delays the input signal to output the delayed signal, and the delayed signal is inputted to the gate circuit. The gate circuit performs calculation to obtain a logical multiplication or a logical addition (a logical multiplication is obtained in  FIG. 2 ) of the two inputs, and outputs the result.  
         [0006]     The delay circuit  15  delays the input signal by an amount larger than the width of a noise pulse, and the delayed signal is inputted to the AND gate circuit  16 . The AND gate circuit  16  obtains a logical multiplication of the input signal and the input signal delayed by the delay circuit to thereby remove a noise pulse. The AND gate circuit  16  then makes the trailing edges of signal components of the input signals to be in phase with each other to generate a final output signal (see, for example, JP 06-132791 A).  
         [0007]     However, in application of such the conventional noise removing circuit there is a problem in that, when a noise pulse inputted has a width that is equal to or larger than a delay time of the delay circuit, a noise pulse having such a width can not be removed and allowed to be passed along with a normal signal pulse.  
         [0008]     Further, the pulse width of an output signal outputted from such the conventional noise removing circuit has a pulse width corresponding to a pulse width obtained by eliminating the delay time from an output signal, which leads to another problem in that it is difficult to make the signal in phase with a clock signal in a subsequent stage.  
       SUMMARY OF THE INVENTION  
       [0009]     In order to solve the above-described problems, the present invention provides a noise filter circuit with a flip-flop additionally provided to a stage subsequent to a noise removing circuit which uses a delay circuit, in which the delay time of a clock signal to be inputted to the flip-flop is made different from the delay time of the noise removing circuit, to thereby make a normal signal pulse to be synchronized with the clock signal.  
         [0010]     According to the noise filter circuit of the present invention, even if a noise pulse having a width larger than a delay time is inputted, the noise pulse is prevented from being passed on to a subsequent stage unless the noise pulse is in synchronization with a leading edge or a trailing edge of a clock signal in the flip-flop in the subsequent stage. Accordingly, only a normal signal pulse can be outputted in synchronization with a clock signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     In the accompanying drawings:  
         [0012]      FIG. 1  is a circuit diagram of a noise filter circuit according to the present invention;  
         [0013]      FIG. 2  is a circuit diagram of a conventional noise removing circuit;  
         [0014]      FIG. 3  is a timing chart of the noise filter circuit according to the present invention;  
         [0015]      FIG. 4  is a circuit diagram of a delay circuit used in the noise filter circuit according to an embodiment of the present invention; and  
         [0016]      FIG. 5  is a circuit diagram of a low-pass filter used in the noise filter circuit according to the embodiment of the present invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]     An embodiment of the present invention is now described in detail in the following with reference to the accompanying drawings.  FIG. 1  is a circuit diagram of a noise filter circuit according to the present invention. The noise filter circuit includes: a first signal input terminal  1 ; a noise removing circuit  7  for receiving a signal inputted from the first signal input terminal  1  through an ESD/CDM protection circuit  2  and a low-pass filter  3 ; a clock input terminal  11 ; a second delay circuit  12  for delaying a signal inputted from the clock input terminal  11 ; a second signal input terminal  8 ; a third delay circuit  9  for delaying a signal inputted from the second signal input terminal  8 ; an OR gate circuit  10  for receiving a signal inputted from the noise removing circuit  7  and a signal from the third delay circuit  9 ; and a flip-flop  13  for receiving a signal inputted from the OR gate circuit  10  and a clock from the second delay circuit  12 . The noise removing circuit  7  includes, for example: an inverter circuit  4  for inverting a signal inputted from the low-pass filter  3 ; a first delay circuit  5  for delaying a signal inputted from the inverter circuit  4 ; and a NOR gate circuit  6  for receiving a signal inputted from the inverter circuit  4  and a signal inputted from the first delay circuit  5 . Alternatively, as illustrated in  FIG. 2 , the noise removing circuit  7  may include: the first delay circuit  5  for delaying a signal inputted from the low-pass filter  3 ; and an AND gate circuit  16  for receiving a signal inputted from the low-pass filter  3  and a signal inputted from the first delay circuit  5 . The low-pass filter  3  is, for example, formed of a circuit illustrated in  FIG. 5 .  
         [0018]     The low-pass filter  3  removes a high frequency noise component from the signal inputted from the first signal input terminal  1 . The noise removing circuit  7  removes a noise pulse having a width that is smaller than a delay time of the delay circuit  5 . The flip-flop  13  in a subsequent stage outputs the signal in synchronization with a clock delayed by the second delay circuit  12 .  
         [0019]     The noise filter circuit according to the present invention is described in the following with reference to a timing chart of  FIG. 3 .  
         [0020]     First, considered is a case where a noise and a normal pulse signal illustrated as input data  1  are inputted to the first signal input terminal  1 . The signal of the input data  1  passes through the inverter circuit  4  to be branched into two signals, one of the two signals is directly inputted to the NOR gate circuit  6 ; and the other of the two signals is inputted to the NOR gate circuit  6  through the delay circuit  5 . The signal outputted from the NOR gate circuit  6  is a signal from which a noise pulse having a width that is smaller than the delay time of the delay circuit  5  is removed (output of the OR gate  10 ). To be more specific, the output signal of the OR gate  10  is a signal having a width that is smaller than that of the signal waveform of the input data  1  by the delay time of the delay circuit  5 , and having the same phase as that of the signal waveform of the input data  1 . As for a noise pulse having a width that is equal to or larger than the delay time of the delay circuit  5 , a noise pulse having a width that is smaller by the delay time is outputted to the subsequent stage.  
         [0021]     A signal from the OR gate circuit  10  is inputted to the flip-flop  13 . The flip-flop  13  is a circuit structured to maintain the input data when a clock rises, until the next leading edge. When a pulse signal having a width of one clock is inputted through the flip-flop, a leading edge of a clock signal is usually set to the center of the input signal pulse so as to output a pulse with stability. A portion of the width of a normal signal pulse which has passed through the noise removing circuit  7  is eliminated from a leading edge side by the amount of the delay time. Therefore, a clock signal to be inputted to the flip-flop  13  is required to be delayed by using the second delay circuit  12 , with consideration given to the eliminated pulse width. In this case, the delay time of the clock signal may be set according to the following equation: 
 
(the delay time of the clock signal)=(the delay time of the noise removing circuit)/ 2    (1) 
 
         [0022]     When delays other than the delay time of the noise removing circuit (delays due to the low-pass filter, wiring resistance, and parasitic capacitance) are taken into consideration, the delay time of the clock signal may be set according to the following equation: 
 
(the delay time of the clock signal)=(the delay time of the noise removing circuit)/ 2 +(the total of the other delay times)   2) 
 
         [0023]     In this way, a noise which could not be removed by the noise removing circuit  7  is removed, and a normal signal pulse is outputted with stability in synchronization with the delayed clock signal.  
         [0024]     Next, considered is a case where a normal signal pulse (a pulse signal illustrated by the dotted line) illustrated as input data  2  is inputted from the second signal input terminal  8 .  
         [0025]     The normal signal pulse is inputted directly to the flip-flop without being passed through the noise removing circuit  7 . Accordingly, by delaying the signal pulse by the same time period as that of a clock signal, by using the third delay circuit  9  (to obtain a pulse signal illustrated by a dotted line in the output of the OR gate  10 ), a synchronized signal can be outputted from the flip-flop with stability.  
         [0026]     Further, due to a structure where a clock signal to be inputted from the clock input terminal  11  as a clock to be used in logics other than the flip-flop  13  is directly inputted without being passed through a delay circuit, internal logics other than the flip-flop operate in synchronization with a clock signal inputted from the clock input terminal  11 . That is, the internal logics other than the flip-flop  13  operate in synchronization with a clock signal inputted from the outside, which makes it possible to prevent unnecessary noises from being generated due to out-of-phase clock signals as compared with a case of using a clock that is purposely delayed inside.  
         [0027]      FIG. 4  illustrates an exemplary circuit diagram of a delay circuit used in the noise filter circuit according to this embodiment. Due to a structure where the capacitance of each capacitor  21  or the channel resistance of a transistor in each inverter  22  in the stages preceding to the capacitors (based on the gate length and the gate width) can be made variable by trimming or optional switching of polysilicon/aluminum, the delay time can be adjusted as desired.  
         [0028]     Further, the noise filter circuit according to this embodiment includes the ESD/CDM protection circuit provided at the first signal input terminal  1  or the second signal input terminal  8 , which prevents problems from being caused when sudden surge is inputted from the terminals or when electric charge accumulates in a node of the input terminals that are in a floating state.  
         [0029]     Further, the noise filter circuit according to this embodiment has a configuration where the low-pass filter  3  is replaced with a Schmitt trigger circuit or a Schmitt trigger circuit is additionally provided in a stage subsequent to the low-pass filter  3  to thereby prevent chattering when a signal pulse of the first signal input terminal  1  rises or falls.

Technology Category: 5