Patent Document

RELATED APPLICATION 
     This application is related to four other applications and all four applications are listed below. The contents of the two other applications, each filed concurrently herewith, are incorporated herein by reference as if set forth in full. (1) “Switched Capacitor Filter for Reference Voltages in Analog to Digital Converter” filed on Aug. 28, 2000 and assigned Ser. No. 09/648770; (2) “Power Supply for Charge Pump in Analog to Digital Converter” filed on Aug. 28, 2000 and assigned Ser. No. 09/648462; (3) “Analog-To-Digital Converter With Enhanced Differential Non-Linearity” filed on Aug. 22, 2000 and assigned Ser. No. 09/643819; and (4)“Frequency Compensation For a Linear Regulator” filed on Sep. 1, 2000 and assigned Ser. No. 09/654392. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to switched capacitor analog to digital converters (ADCs) and particularly relates to a charge pump that provides an elevated voltage for use in establishing reference voltages for such ADCs. 
     2. Background of the Invention 
     Switched capacitor ADCs provide efficient high speed conversion of analog signals to digital signals. A representative switched capacitor ADC is shown at  10  in FIG. 1, in the form of a multi-stage pipelined ADC. As seen there, ADC  10  includes multiple stages, such as stages  11  and  12 , each providing one or more bits of digital data to a digital correction circuit  15 , which resolves the digital output from each stage into an overall digital output  16  that corresponds to an analog input  17 , Each stage is a switched capacitor circuit operating in response to clock signals such as φ 1  and φ 2  and comparing an analog voltage input to thresholds based on reference signals Vrefp and Vrefn so as to produce the digital outputs as well as a residual analog signal. The residual analog signal is provided as input to the subsequent stage. 
     For proper operation of ADC  10 , generators are needed for phase and timing signals as well as for reference voltages. These are shown respectively at  20  and  30  of FIG.  1 . Thus, generator  20  for phase and timing signals generates clock signal φ 1  for use during the sample phase of multiple stages  11  and  22 , as well as clock signal φ 2  for use during the amplification phase of multiple stages  11  and  12 . Likewise, generator  30  generates reference voltages Vrefp and Vrefn for use by multiple stages  11  and  12 . The focus of the present application is on the generator  30  for the reference voltages. 
     FIG. 2 shows a conventional generator  30  for generating reference voltage Vrefp; a similar circuit shown schematically at  31  is used to generate reference voltage Vrefn. As shown in FIG. 2, generator  30  includes a follower  32  connected between voltage source V+ and a current source  35  which, in turn, is connected to ground. Follower  32  is driven at its gate side by amplifier  34 , which is connected in negative feedback relationship using a reference voltage Vref as a reference and the output Vrefp as negative feedback. With this arrangement, follower  32  is driven by amplifier  34  so as to provide an output Vrefp with good current capabilities stabilized through negative feedback at a voltage level corresponding to Vref. 
     Problems arise, however, in use of generators in the form shown at  30 . For example, due to higher frequency switching of generator  30 , and due to noise/glitches generated from MDACs and capacitors which are connected to the reference generator  30 , the amplifier  34  (FIG. 2) needs to be very fast, such that it can react quickly to the noise and reset Vrefp to an ideal value (e.g., preferably within a fraction of a clock period). However, this would be difficult to achieve for high speed ADCs. Also, amplifier thermal noise would be high in such cases, which would make the Vrefp signal noisy. 
     An alternative is to design a low bandwidth amplifier to slowly servo Vrefp, and to use an external capacitor (e.g., with a sufficiently large capacitance) to lower the impedance seen by the reference at high frequencies. This alternative may minimize switching glitches and noise, but it also requires extra circuitry, and for example, an extra pin. 
     Another problem involves the value of Vrefp relative to the source voltage V+. Specifically, because a voltage drop Vgs exists between the gate and source of follower  32 , and because it is not possible for amplifier  34  to output a voltage greater than the supply voltage V+, the value of Vrefp must be lower than V+ by at least an amount equal to Vgs. Typically, Vgs is around 1 v, and for adequate design margins, vrefp is typically set to a value 1.5 v less than source voltage V+. This amount of voltage drop, however, is wasteful and unnecessarily limits the dynamic conversion range of multiple stages  11  through  12 . 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to address the foregoing through the provision of an improved generator for reference voltage signals used in a switched capacitor ADC. 
     In its most preferred form, a generator for reference voltage signals according to the invention is shown at  100  in FIG.  3 . As seen there, the generator includes a follower  132  connected between a voltage source V+ and a current source  135  connected in turn to ground, as well as an amplifier  134  connected in negative feedback relationship with a reference voltage. Negative feedback to amplifier  134  is provided from the output of follower  132  (which forms the reference voltage signals Vrefp or Vrefn that are supplied to the ADC) through a switched capacitor filter  200 . 
     The output of amplifier  134  is provided to a current sink  300  which drives the gate of follower  132 . Current sink  300  has an effective resistance whose value is low relative to that of other components in generator  100 , thereby providing a path to sink current through follower  132  and thereby providing increased rejection of noise. 
     Source voltage for current sink  300  is provided through charge pump  400 . Charge pump  400  operates to increase the effective voltage level of supply voltage V+ for use by current sink  300 , thereby allowing a design in which reference voltages for ADC  10  (such as Vrefp and Vrefn) are set very nearly equal to supply voltage V+ in spite of the voltage drop Vgs of follower  132 . 
     Although in its preferred form all three components (i.e., charge pump  400 , current sink  300  and switched capacitor filter  200 ) are used in the construction of a generator for reference voltages, it is possible to use fewer than all three components, such as only one or two components. 
     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiment thereof in connection with the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a view of a conventional switched capacitor ADC together with generators for phase and timing signals and reference voltages. 
     FIG. 2 is a view of a conventional generator for reference voltage signals. 
     FIG. 3 is a view showing a generator for reference voltages according to the present invention, connected to a switched capacitor ADC. 
     FIGS. 4A and 4B are views for explaining a switched capacitor filter for filtering the feedback leg of the feedback loop from noise generated by the switched capacitor ADC. 
     FIGS. 4C through 4F are views for explaining the general operation of a switched capacitor filter. 
     FIG. 5 is a view for explaining timing of the filter of FIGS. 4A through 4E. 
     FIG. 6 is a view for explaining the operational principle of a charge pump according to the invention. 
     FIG. 7 is a view for explaining timing signals for the charge pump of FIG.  6 . 
     FIG. 8 is a detailed schematic view of a charge pump according to FIG.  6 . 
     FIG. 9 is a view for explaining a current sink according to the invention. 
     FIG. 10 is a view for modeling a charge pump according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Reverting again to FIG. 3, a switched capacitor ADC is shown in the form of a multi-stage pipelined ADC which includes multiple stages  11  through  12  each providing one or more bits of digital data to a digital correction circuit  15  which resolves the digital output from each stage into an overall digital output  16  that corresponds to an analog input  17 . Each stage is a switched capacitor circuit operating in response to clock signal φ 1  for a sample phase and clock signal φ 2  for an amplifying phase, and comparing an analog voltage input to thresholds based on reference signals Vrefp and Vrefn so as to produce the digital outputs as well as a residual analog signal. The residual analog signal is provided as input to a subsequent stage. 
     Generator  20  provides phase and timing signals including clock signals φ 1  and φ 2 . 
     Generator  100  generates reference voltages Vrefp and Vrefn for use by each of multiple stages  11  through  12 . As shown in FIG. 3, generator  100  generates reference voltage Vrefp which is output from the source terminal of follower  132  which is connected between voltage supply V+ and a current source  135  which in turn is connected to ground. Follower  132  is driven in negative feedback relationship to Vrefp through amplifier  134  whose reference is reference signal Vref. The negative feedback leg for amplifier  134  is provided through filter  200  which is a switched capacitor filter operating in synchronism with phase and timing signals φ 1  and φ 2  so as to sample and filter reference voltage Vrefp during known quiescent periods of the φ 1  sample phase and the φ 2  amplification phase. 
     The gate of follower  132  is driven by current sink  300 , which accepts as its input the output from amplifier  134 . Current sink  300  has an effective resistance which is low relative to other effective resistances in the circuit, thereby providing a low resistance path to sink current through follower  132  and thereby providing further immunization from the effects of high frequency noise. 
     A voltage source for current sink  300  is provided by charge pump  400  which provides an effectively higher voltage to current sink  300  than is otherwise available through supply voltage V+. Because of the higher effective voltage provided by charge pump  400 , it is possible to supply a reference voltage Vrefp which is very close to supply voltage V+, in spite of the existence of voltage drop Vgs across follower  132 . 
     A complementary reference voltage generator  101  is provided for Vrefn. Circuit  101  involves components similar to switched capacitor filter  200 , current sink  300  and charge pump  400 , but operates those components in complementary relationship to those of generator  100  in correspondence to the reversed roles of φ 1  and φ 2  in the generator. 
     Each of the components of switched capacitor filter  200 , current sink  300  and charge pump  400 , are described in more detail below. 
     [Switched Capacitor Filter  200 ] 
     FIGS. 4A and 4B are views for explaining switched capacitor filter  200 , which provides a final and settled value of the reference Vrefp signal for the feedback leg of amplifier  134 . One difference between FIGS. 4A and 4B involves the presence in FIG. 4A of current sink  300  and charge pump  400 , whereas those components are absent in the view of FIG.  4 B. These views are therefore intended to reinforce the notion that less than all three components (i.e., switched capacitor filter  200 , current sink  300  and charge pump  400 ) may be used in a generator for reference voltages, still with advantageous results. 
     General operating features of a switched capacitor filter  200  will be described with reference to FIGS. 4C through 4E. A source signal waveform is illustrated in each of these figures. As shown in FIGS. 4C and 4D, a combination of switches φ 1  and φ 2  (e.g., switches driven by clocks φ 1  and φ 2 , respectively) and capacitor Cp 1  is modeled as a resistor R=1/(f·Cp 1 ), where f is the frequency of the φ 1  and φ 2  clocks. When φ 1  and φ 2  are non-overlapping clocks (e.g., as shown in FIG.  5 ), RCp 2  low pass feedback is provided by the configuration shown in FIG. 4E, with R=T/Cp 1 =1/(fCp 1 ). FIG. 4E illustrates the settling of the source signal. 
     In a situation where the source or excitation to such a switched capacitor filter is a glitch type signal for example V 1 , V 2  and V 3 , e.g., every T/2 seconds, as shown in FIG. 4F, the height of the initial glitch is signal dependent. Hence, the average of this signal over one T period (e.g., low pass filtering the signal) can vary depending on signal value. To minimize this dependence, φ 1  is preferably skewed such that the network RCp 2  does not see a glitch. Instead the network preferably sees a partially settled signal. As a result, the signal dependency is reduced to the feedback amplifier. 
     Referring to FIGS. 4A and 4B, filter  200  includes switched capacitors Cp 1  and Cp 2  switched in accordance with clock signals φa and φb. Clock signals sa and φb are, in turn, timed relative to clock signal φ 1  (sample) and clock signal φ 2  (amplify) for ADC  10 . Preferably, the value of Cp 2  is much greater than Cp 1 . For example, Cp 2  is advantageously ten times the size of Cp 1 , such as Cp 2 =1 picofarad and Cp 1 =100 femtofarads. The purpose of this relationship is explained in more detail below. 
     In general, ha is driven in synchronism with φ 2  (amplification), but only after a time T 1  from when amplification commences. The purpose for this delay T 1  is to ensure that Vrefp has recovered to a relatively stable value after any initial noise spikes generated during initial stages of amplification by multiple stages  11  through  12 . When φa closes, Cp 1  samples the value of Vrefp, and holds that value after φa opens, during which time φb remains open. 
     φb, on the other hand, is driven in synchronism with φ 1  (sample), or more precisely is driven out of synchronism with φa. φb closes while φa is open, thereby allowing any charge accumulated on capacitor Cp 2  to mix with the charge newly acquired by capacitor Cp 1 , which reflects the current voltage level of Vrefp. It is the voltage accumulated on Cp 2  that is provided to the negative feedback leg of amplifier  134 , and that value is maintained even after φb opens. 
     FIG. 5 is a timing diagram showing operation of switched capacitor filter  200 . As previously described, φ 1  and φ 2  are sample and amplification signals, respectively, φa is driven in synchronism with amplification phase φ 2  but commencing a short time T 1  after amplification begins, and φb is driven out of synchronism with φa and preferably in synchronism with φ 1 . Immediately after amplification phase φ 2  commences, Vrefp is subjected to a voltage spike which is quickly accommodated by follower  132  so as to return to a nominal value. T 1  is selected at design time so that it is timed for this nominal value. After time T 1 , φa closes thereby allowing the voltage on capacitor Cp 1  (designated as Vcp 1 ) to follow any change in voltage level that might have occurred since the last closure of φa. φa then opens, followed by closure of φb, at which time the charge on capacitor Cp 1  is mixed with the charge currently stored on capacitor Cp 2 , thereby resulting in a change in voltage impressed across capacitor Cp 2  (designated as Vcp 2 ). As further shown in FIG. 5, the output value of Vrefp follows the change in voltage across capacitor Cp 2  by virtue of the negative feedback relationship caused by amplifier  134 . 
     The value for capacitor Cp 2  is much greater than that for Cp 1  because the purpose of capacitor Cp 1  is to sample the voltage of Vrefp quickly, whereas the purpose of capacitor Cp 2  is to accumulate charge over a longer period of time and to provide a reasonable damping effect with good response time. This relationship is obtained with the previously-described 10:1 ratio between capacitances for Cp 2  and Cp 1 . In a preferred embodiment, the pole (p) of the cp 2  capacitor is p (Cp 1 /Cp 2 )·f, where f equals 125 MHz, Cp 1 /Cp 2  equals 0.1, yielding a pole (p) of 12.5 MHz. 
     Because capacitor Cp 2  is filtered from high frequency noise injected by ADC  10  onto Vrefp, noise rejection from amplifier  134  (and onto follower  132 ) is greatly enhanced with respect to conventional feedback relationships. That noise rejection is reflected by the absence of any external capacitor such as Cext found in conventional voltage generators, because such an external capacitor is ordinarily not required. 
     [Charge Pump  400 ] 
     Charge pump  400  is provided so as to produce an artificially elevated voltage level for follower  134 , so that it is possible to run the reference voltages Vrefp and Vrefn very close to supply voltage V+, in spite of the presence of the voltage drop Vgs from gate to source of follower  132 . FIG. 6 shows the operational principles of charge pump  400 . 
     As shown in FIG. 6, the reference voltage Vrefp for ADC  10  is generated from the source terminal of follower  132  which is connected between supply voltage V+ and a current source, which, in turn, is connected to ground. Vrefp is monitored through a negative feedback relationship to amplifier  134  whose reference is provided by a reference voltage Vret and whose feedback leg is connected to switched capacitor filter  200 . Alternatively, switched capacitor filter  200  need not be supplied. The output of amplifier  134  is provided to the gate of sink  135 , whose source is connected to the gate of follower  132 . Sink  135  is provided to allow a sink of current from drain to gate of follower  132 , thereby providing an effectively low impedance looking inwardly toward sink  135  and amplifier  134 . 
     The source terminal of sink  135  is supplied by charge pump  400 . In principle, charge pump  400  operates to artificially elevate source voltage V+ through capacitive switching and capacitive biasing, as explained more fully below. 
     Specifically, charge pump  400  takes voltage source V+ through a current source and a biasing resistor R 3  and connects to two pairs of diagonally complementary switches S 1  and S 2 . These switches operate in connection with capacitors C 1  and C 1   a  which are biased in synchronism with operation of switches S 1  and S 2  through biasing pulse Vpulse. 
     In more detail, and focusing on the left leg of charge pump  400 , when switch S 1  is closed and in the absence of a biasing pulse on vpulse, capacitor C 1  charges to the level of supply voltage V+. Thereafter, switch S 1  closes and vpulse issues, thereby biasing the voltage at V 4  upwardly from V+ by the value of Vpulse. Preferably, Vpulse is the same value as supply voltage V+, thereby effectively doubling the voltage at V 4 . In synchronism with the issuance of Vpulse, switch S 2  closes, thereby providing a voltage at V 5  which is elevated relative to supply voltage V+. 
     Diagonally complementary operations of switches S 1  and S 2  occur in the right leg of charge pump  400 . Thus, while switch S 2  in the left leg is open, switch Si in the right leg is closed, thereby providing a biased voltage previously-impressed on capacitor C 1   a  to voltage V 5 . This diagonally-complementary operation of switches ensures that the voltage at V 5  is artificially elevated relative to supply voltage V+. 
     In practice, of course, the biased voltages across capacitors C 1  and C 1   a  are depleted by operation of current sink  135 . This is shown in the waveforms of FIG.  7 . 
     As shown in FIG. 7, and as previously described, switches S 1  and S 2  operate complementarily, and Vpulse operates in synchronism with closure of switch S 2 . During the time when switch S 1  is closed, the voltage from capacitor C 1  at V 4  charges to the value of supply voltage V+. Thereafter, when switch S 1  opens and switch S 2  closes, and the voltage of capacitor C 1  is biased by issuance of vpulse, the voltage at V 4  increases to an elevated level relative to supply voltage V+ as signified by V++. Operation of current sink  135 , however, discharges capacitor C 1 , thereby resulting in a charge/discharge cycle signified at V 5  in FIG.  7 . Notably, although the voltage V 5  does not maintain its highest level at V++, it nevertheless maintains an average level which is elevated with respect to V+. 
     Because the voltage at V 5  is elevated relative to supply voltage V+, it is possible to operate Vrefp at a value very close to supply voltage V+, in spite of the gate-to-source voltage drop Vgs across follower  132 . 
     In practice, however, it turns out to be difficult to build switches S 1  and S 2  because those switches must be turned on and off with voltages on the order of the supply voltage V+, yet must control voltages of values elevated with respect to V+. 
     FIG. 8 is a detailed schematic diagram for a practical implementation of charge pump  400 . 
     As shown in FIG. 8, and focusing on the left leg of charge pump  400 , switch S 1  is formed by FET  401 , and switch S 2  is formed by a back-to-back connection of FET  402  and PMOSFET  404 . Switch S 1  is driven inversely from Vpulse through inverter  405 , and capacitor C 1  is biased in coordination with Vpulse through dual inverters  406 . In addition, a helper capacitor C 3  is switched and biased in coordination with capacitor C 1  through FET  407  which operates as a switch. 
     In operation of the circuitry shown in FIG. 8, when switch S 1  closes, capacitor C 1  is charged to a voltage level corresponding to voltage supply V+. Correspondingly, capacitor C 3  is charged through FET  407 . Then, upon issuance of vpulse, switch S 1  opens and capacitor C 1  is biased by the value of Vpulse. Corresponding, FET  407  opens and capacitor C 3  is also biased by vpulse. 
     Closure of switch S 2  is a two-part operation. In the first part, since the value of V 4  is approximately twice the value of reference voltage V+, it is not possible for FET  402  to turn on and allow capacitor C 1  to discharge to current sink  135 . However, by virtue of the diagonally complementary operation of the switches in the right and left legs of charge pump  400 , FET  409  is currently on and voltage at V 4  is currently the same as supply voltage V+. The supply voltage drives the gate of PMOSFET  404  which therefore turns on and allows discharge of capacitor C 1  to current sink  135 . As capacitor C 1  discharges, voltage at V 4  decreases and will eventually decrease to a point where PMOS  404  can no longer remain on. However, by that time, the biased voltage from capacitor C 3  allows FET  402  to turn on, thereby maintaining an “ON” state for switch S 2  and continuously allowing capacitor C 1  to discharge to sink  135 . As will be appreciated by one of ordinary skill in the art, capacitor C 2  and buffer  405  are configured as a level shifter. 
     Charge pump  400  can be modeled as a resistor Rcp and a voltage supply that preferably supplies a voltage of approximately two times (e.g., 2V+) a voltage source (e.g., V+), as shown in FIG. 10. A voltage V 5  (i.e., V 5 =Vrefp+Vgs) is established such that the current (i) through the charge pump (e.g., Rcp) can be approximated by i=(2V+−(Vrefp +Vgs))/Rcp. 
     [Current Sink  300 ] 
     FIG. 9 is a detailed schematic view showing current sink  300 . Referring to the model shown in FIG. 10, the voltage V 5  varies continuously according to the charge/discharge cycle shown at VS in FIG.  7 . Accordingly, if charge pump  400  is used, it is advantageous also to utilize a current sink  300  so as to reject noise generated by charge pump  400  in accordance with action of its switches S 1  and S 2 . 
     As shown in FIG. 9, current sink  300  includes a low pass filter  301  which may include a simple RC circuit, which provides an input impedance (as viewed from the charge pump) that is low for high frequencies and higher for lower frequencies. The output of low pass filter  301  is provided to follower  132 . The input to low pass filter  301  is provided by a buffer composed of the combination of PETs  302 ,  303  and  304  and capacitors C 1  and C 2 . Operation of this buffer is described in more detail below. Generally speaking, however, the buffer provides a buffered output based on the output of amplifier  134  and further provides an input impedance (as viewed from the charge pump) which is low for low frequencies and higher for high frequencies, thereby acting as a current sink for the output of charge pump  400 . 
     The buffer is referred to generally at reference numeral  310 . 
     At low frequency operation of buffer  310 , the impedance thereof is influenced primarily by the transconductance of FET  302  since capacitor C 1  is essentially open. Specifically, at low frequencies the impedance of buffer  310  is the inverse of the transconductance of FET  302 , divided by the gain provided by FETs  303  and  304 . As a consequence, low frequency impedance of buffer  310  is lower than that of current sink  135  (FIG. 6) because of the amplifying effect of FETs  303  and  304 . 
     At mid to high frequencies, capacitor C 1  shorts. Consequently, in the absence of low pass is filter  301 , the input impendence of buffer  310  would increase to approximately the inverse of the transconductance of FET  302  (i.e., not divided by the gain of FETS  303  and  304 ). However, the presence of low pass filter  301  effectively ensures that at higher frequencies, the overall input impedance of current sink  300  remains low. 
     By virtue of the coordination in input impedances of low pass filter  301  and buffer  310 , it is possible to ensure that the overall input impedance of current sink  300  remains low throughout the frequency range of interest. As a consequence, because the input impedance is low, noise from charge pump  400  is rejected efficiently. 
     The invention has been described with respect to particular illustrative embodiments. It is to be understood that the invention is not limited to the above-described embodiments and that various changes and modifications may be made by those of ordinary skill in the art without departing from the spirit and scope of the invention.

Technology Category: 5