Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a non-volatile semiconductor storage device which stores data by accumulating charges in a floating gate of each memory cell. More particularly, the present invention relates to an improved technique for driving word lines of such a non-volatile semiconductor storage device using a hierarchical word line drive circuit. 
     2. Description of Related Art 
     Control gates are generally used as word lines in non-volatile semiconductor storage devices such as flash memories and EEPROMs (electrically erasable programmable read-only memories) which are configured to store data by accumulating charges in a floating gate of each memory cell. By applying an appropriate voltage to a word line (i.e., control gate), it is possible to program, erase, or read desired data to/from each memory cell. 
     Recent non-volatile semiconductor storage devices are configured such that both positive and negative potentials can be applied to word lines as disclosed in Japanese Patent Laid-Open No. 2005-317138. Such a configuration makes it possible to downsize gates of transistors which compose memory cells and word line drive circuits, and thereby downsize the non-volatile semiconductor storage devices. 
     Another trend in recent non-volatile semiconductor storage devices is hierarchical design of word line drive circuits. The recent non-volatile semiconductor storage devices use hierarchical word line drive circuits to make it possible to drive a large number of word lines. For example, Japanese Patent Laid-Open No. 10-3794 discloses a hierarchical word line drive circuit consisting of block decoders, gate decoders, and sub-decoders. 
     One of requirements for a hierarchical word line drive circuit is that the drivers in the final word line drive stage have a simple configuration. There are as many drivers in the final stage as there are word lines, and thus simplification of driver configuration in the final stage is very useful in downsizing the word line drive circuit. 
     Japanese Patent Laid-Open No. 2001-43693 discloses a hierarchical word line drive circuit in which drivers in the final word line drive stage consists of two MOS transistors.  FIG. 1  is a circuit diagram showing a configuration of the word line drive circuit disclosed in the patent document. The word line drive circuit shown in  FIG. 1  has an even-numbered global decoder  100 , odd-numbered global decoder  120 , row local decoder  140 , row partial decoder  160 , and block decoder  180 . 
     The even-numbered global decoder  100  has a NAND gate  102 , NOR gate  104 , and level shifter  106  and drives an even-numbered global word line EGWLi. The odd-numbered global decoder  120  has a NAND gate  122 , NOR gate  124 , and level shifter  126  and drives an odd-numbered global word line OGWLi. 
     The row local decoder  140  is a circuit which drives local word lines WLi connected to memory cells (not shown). The row local decoder  140  consists of PMOS transistors P 10  to P 24  and NMOS transistors N 10  to N 24 . The row partial decoder  160  has a NAND gate  162  and level shifter  164  and generates word line selection signals PWL 0  to PWL 7 . The block decoder  180  has a NAND gate  182 , AND gate  184 , and level shifter  186  and supplies the row local decoder  140  with a negative voltage used for erasing operations. 
     With the word line drive circuit in  FIG. 1 , each local word line is driven by a driver consisting of two MOS transistors (one PMOS transistor and one NMOS transistor). For example, the local word line WL 0  is driven by a driver consisting of the PMOS transistor P 10  and NMOS transistor N 10  while the local word line WL 1  is driven by a driver consisting of the PMOS transistor P 11  and NMOS transistor N 11 . 
     The word line drive circuit in  FIG. 1  operates as follows in write operations. An operation performed when the local word line WL 2  is selected will be described below. When the write operations are performed, the even-numbered global decoder  100  drives the even-numbered global word line EGWLi at 0 V. Consequently, the PMOS transistors P 10  to P 16  turn on and the NMOS transistors N 10  to N 16  turn off. On the other hand, the odd-numbered global decoder  120  drives the odd-numbered global word line OGWLi at 10 V. Consequently, the PMOS transistors P 10  to P 16  turn off and the NMOS transistors N 10  to N 16  turn on. The row partial decoder  160  sets the word line selection signal PWL 2  at 10 V and sets the remaining word line selection signals PWL 0 , PWL 1 , and PWL 3  to PWL 7  at ground potential. The block decoder  180  generates a 0 V potential. 
     Consequently, the local word line WL 2  is electrically connected to the word line selection signal PWL 2  with a potential of 10 V via the PMOS transistor P 12 , and is driven at 10 V. 
     In read operations, the word line drive circuit in  FIG. 1  operates in the same manner as in write operations except that a voltage of 5 V is used instead of 10 V. 
     A feature of the word line drive circuit in  FIG. 1  is that each local word line is driven by only two MOS transistors. This simple configuration is effective in reducing overall size of the word line drive circuit. 
     [Patent Document 1] Japanese Patent Laid-Open No. 2005-317138 
     [Patent Document 2] Japanese Patent Laid-Open No. 10-3794 
     [Patent Document 3] Japanese Patent Laid-Open No. 2001-43693 
     However, the word line drive circuit in  FIG. 1  has a problem in that part of unselected local word lines is brought into a floating state. The local word lines WL 1 , WL 3 , WL 5 , and WL 7 , which are electrically connected to outputs of the block decoder  180  via the NMOS transistors N 18 , N 20 , N 22 , and N 24 , respectively, are driven at 0 V to be sure, but the local word lines WL 0 , WL 4 , and WL 6  are brought into a floating state. Gate and source potentials of the PMOS transistors P 10 , P 14 , and P 16  are all 0 V. Thus, the PMOS transistors P 10 , P 14 , and P 16  do not turn on. Neither do the NMOS transistors N 10 , N 14 , and N 16 , as described above. Consequently, the local word lines WL 0 , WL 4 , and WL 6  are cut off from outputs of both row partial decoder  160  and block decoder  180  and brought into a floating state. 
     In this regard, Japanese Patent Laid-Open No. 2001-43693 states that since the local word lines WL 1 , WL 3 , WL 5 , and WL 7 , which are electrically connected to outputs of the block decoder  180  via the NMOS transistors N 18 , N 20 , N 22 , and N 24 , respectively, are driven at 0 V, the local word lines WL 0 , WL 4 , and WL 6  are electrically shielded, which prevents coupling among word lines. 
     However, it is not desirable from the viewpoint of stability of operation that local word lines, which are long and thick, enter a floating state. When local word lines enter a floating state, data may be read or written erroneously due to noise. Desirably, unselected local word lines are kept at a fixed potential (typically at ground potential). 
     SUMMARY OF THE INVENTION 
     To solve the above problems, the present invention takes the following measures. Incidentally, when describing technical matters composing these measures, the same reference numerals/characters as those used in DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS are attached to clarify correspondence between description provided in the appended claims and description provided in DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS. However, it should be understood that the attached reference numerals/characters are not intended to limit the scope of the present invention defined in the appended claims. 
     The present invention provides a non-volatile semiconductor storage device comprising: a memory array ( 1 ) containing memory cells which store data by accumulating charges in floating gates; word lines (WL_i_j) installed in the memory array ( 1 ) and used as control gates of the memory cells; a pre-decoder ( 3 ) which generates pre-decode signals (PX_i); a main decoder ( 4 ) which generates main decode signals (MX_j); and a sub-decoder ( 2 ). The sub-decoder ( 2 ) is equipped with pull-up power lines ( 23   j ) whose potentials are controlled by the main decode signals (MX_j), a pull-down power line ( 24 ), and drivers ( 22 ) which drive word lines (WL_i_j) according to the pre-decode signals (PX_i). Each of the drivers ( 22 ) comprises a PMOS transistor (P 3 ) whose source is connected with one of the pull-up power lines ( 23   j ), whose drain is connected with one of the word lines (WL_i_j), and whose gate is supplied with an appropriate pre-decode signal (PX_i) as well as an NMOS transistor (N 3 ) whose drain is connected with the drain of the PMOS transistor (P 3 ), whose gate is supplied with the appropriate pre-decode signal (PX_i), and whose source is connected with the pull-down power line ( 24 ). The pre-decoder ( 3 ) can pull down the pre-decode signals (PX_i) to a negative potential lower than a ground potential. 
     The non-volatile semiconductor storage device configured as described above can reduce the size of the word line drive circuit because each driver consists of only two MOS transistors. Besides, when the pull-up power lines ( 23   j ) are driven at the ground potential in response to the main decode signals (MX_j), the non-volatile semiconductor storage device can fix the word lines (WL_i_j) at the ground potential by pulling down the pre-decode signals (PX_i) to a negative potential lower than the ground potential. Thus, the non-volatile semiconductor storage device according to the present invention can prevent the word lines (WL_i_j) from entering a floating state. 
     The present invention provides a small-size word line drive circuit which can operate without bringing word lines into a floating state. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram showing a configuration of a conventional word line drive circuit of a non-volatile semiconductor storage device; 
         FIG. 2  is a block diagram showing a configuration of a non-volatile semiconductor storage device according to an embodiment of the present invention; 
         FIG. 3  is a circuit diagram showing a configuration of a sub-decoder according to the embodiment; 
         FIG. 4  is a block diagram showing a configuration of a pre-decoder according to the embodiment; 
         FIG. 5  is a circuit diagram showing a configuration of an output stage of the pre-decoder in  FIG. 4 ; 
         FIG. 6  is a block diagram showing a configuration of a main decoder according to the embodiment; 
         FIG. 7  is a circuit diagram showing a configuration of an output stage of the main decoder in  FIG. 5 ; 
         FIG. 8  is a timing chart showing operation of the non-volatile semiconductor storage device according to the embodiment; and 
         FIG. 9  is a circuit diagram showing a configuration of a sub-decoder according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Overall Configuration 
       FIG. 2  is a block diagram showing a configuration of a non-volatile semiconductor storage device  10  according to an embodiment of the present invention. The non-volatile semiconductor storage device  10  has memory arrays  1   1  to  1   4 , sub-decoders  2   1  to  2   4 , pre-decoders  3   1  and  3   2 , and main decoders  4   1  and  4   2 . It should be noted that subscripts to reference characters/numerals may be omitted when there is no need to distinguish among a plurality of the same components. For example, memory arrays  1   1  to  1   4  may be referred to collectively as the memory array(s)  1 . 
     The memory array  1  consists of memory cells arranged in a matrix and used to store data by accumulating charges in floating gates. It should be noted that the term “floating gate” is not limited to a conductive one such as polysilicon and includes insulators capable of holding charges, such as adopted in MONOS (metal oxide nitride oxide silicon) technology. Each memory array  1  has a plurality of word lines WL_ 0 _ 0  to WL_n_m and bit lines (not shown). Hereinafter, the word lines WL_ 0 _ 0  to WL_n_m will be referred to collectively as the word line(s) WL when they are not distinguished from each other. On the other hand, a numeral enclosed in parentheses will be used to clearly indicate a word line (or word lines) WL installed in a specific memory array  1 . For example, word line WL_ 0 _ 0  ( 1 ) denotes a word line installed in the memory array Each memory cell is installed at an intersection of a word line WL and bit line. The word line WL functions as a control gate of each memory cell. 
     The sub-decoder  2  drives a word line selected from among the word lines WL_ 0 _ 0  to WL_n_m according to the pre-decode signals PX_ 0  to PX_n supplied from the pre-decoder  3  and the main decode signals MX_ 0  to MX_m supplied from the main decoder  4 . Specifically, if the pre-decode signal PX_i and main decode signal MX_j are selected during a write operation or read operation, the sub-decoder  2  selects and pulls up the word line WL_i_j. As described later, in write operations, the selected word line is pulled up to a high potential VPOS (typically 10 V) and in read operations, the selected word line is pulled up to a power supply potential VCC (typically 5 V). On the other hand, in erase operations, the sub-decoder  2  pulls down all the word lines WL_ 0 _ 0  to WL_n_m to a negative potential VNEG (typically −10 V). 
     The pre-decoder  3  selects the pre-decode signals PX_ 0  to PX_n for upper addresses A 0  to A 2  while the main decoder  4  selects the main decode signals MX_ 0  to MX_m for lower addresses A 3  to A 8 . It should be noted that in  FIG. 2 , a set of main decode signals MX_ 0  to MX_m are supplied to multiple sub-decoders  2 . According to this embodiment, main decode signals MX_ 0  ( 1 ) to MX_m ( 1 ) generated by the main decoder  4   1  are supplied to two sub-decoders  2   1  and  2   2  while main decode signals MX_ 0  ( 2 ) to MX_m ( 2 ) generated by the main decoder  4   2  are supplied to two sub-decoders  2   3  and  2   4 . 
     Configurations of the sub-decoder  2 , pre-decoder  3 , and main decoder  4  will be described in detail below. 
     Configuration of Sub-Decoder  2   
       FIG. 3  is a circuit diagram showing a configuration of the sub-decoder  2 . The sub-decoder  2  has m+1 level shifters  21   0  to  21   m , (n+1)×(m+1) drivers  22 - 0 - 0  to  22 - n - m , pull-up power lines  23   0  to  23   m , a pull-down power line  24 , and a power switch  25 . The level shifters  21   0  to  21   m  will be referred to collectively as the level shifter(s)  21  when they are not distinguished from each other. In the same fashion, the drivers  22 - 0 - 0  to  22 - n - m  will be referred to collectively as the driver(s)  22 . 
     The level shifters  21   0  to  21   m  drive the pull-up power lines  23   0  to  23   m , respectively, in response to the main decode signals MX_ 0  to MX_m. The pull-up power lines  23   0  to  23   m  are wires used to distribute desired positive potentials (power supply potential VCC or high potential VPOS) to the drivers  22 . The pull-up power line  23   0  is connected to the drivers  22 - 0 - 0  to  22 - n - 0 . Similarly, the pull-up power line  23   j  is connected to the drivers  22 - 0 - j  to  22 - n - j . The potentials of the pull-up power lines  23   0  to  23   m  are controlled by the main decoder  4  using the main decode signals MX_ 0  to MX_m. 
     According to this embodiment, each level shifter  21  consists of PMOS transistors P 1  and P 2  and NMOS transistors N 1  and N 2 . The drains of the PMOS transistors P 1  and P 2  are connected to the gates of the other PMOS transistors. The PMOS transistors P 1  and P 2  have their sources commonly connected to a power line VXPG 1  and have their substrate terminals commonly connected to a power line VXPG 2 . The power lines VXPG 1  and VXPG 2  are driven at a high potential VPOS higher than the power supply potential VCC in write operations, and at the power supply potential VCC in read operations. The drain of the PMOS transistor P 1  is connected to the drain of the NMOS transistor N 1  while the drain of the PMOS transistor P 2  is connected to the drain of the NMOS transistor N 2 . The gate of the NMOS transistor N 1  is supplied with a predetermined control voltage MXCNT. The gate and source of the NMOS transistor N 2  are supplied with a main decode signal from the main decoder  4 . More specifically, the gate and source of the NMOS transistor N 2  of the level shifter  21   j  is supplied with the main decode signal MX_j. The source of the NMOS transistor N 2  is connected to a ground terminal which has a ground potential VSS. The pull-up power lines  230  to  23   m  are connected to the drains of the PMOS transistor P 2  of the level shifters  21   0  to  21   m , respectively. 
     The drivers  22  constitute output stages which finally drive word lines in response to the pre-decode signals PX_ 0  to PX_n. Each driver  22  consists of two transistors: a PMOS transistor P 3  and NMOS transistor N 3 . In the driver  22 - i - j , the source of the PMOS transistor P 3  is connected with the pull-up power line  23   j  and the source of the NMOS transistor N 3  is commonly connected with the pull-down power line  24 . The gates of the PMOS transistor P 3  and NMOS transistor N 3  of the driver  22 - i - j  are supplied with the pre-decode signal PX_i. The word line WL_i_j is connected to the drain of the PMOS transistor P 3  and NMOS transistor N 3  of the driver  22 - i - j.    
     It should be noted that each driver  22  consists of only two MOS transistors. This con figuration is effective in reducing the size of the circuit used to drive the word lines. 
     The power switch  25  sets the pull-down power line  24  to the ground potential VSS or negative potential VNEG. More specifically, the power switch  25  sets the pull-down power line  24  (i.e., the source of the NMOS transistor N 3 ) to the ground potential VSS in write and read operations, and sets the pull-down power line  24  to the negative potential VNEG in erase operations. 
     Configuration of Pre-Decoder  3   
       FIG. 4  is a block diagram showing a configuration of the pre-decoder  3 . The pre-decoder  3  has a selector  31  and output stages  32   0  to  32   n . The selector  31  selects, the pre-decode signals PX_ 0  to PX_n for the upper addresses A 0  to A 2 . Specifically, when selecting the pre-decode signal PX_i, the selector  31  activates complementary selection signals PSEL_i and /PSEL_i (i.e., it pulls up the selection signal PSEL_i to a “High” level and pulls down the selection signal /PSEL_i to a “Low” level). The output stage  32   i  generates a pre-decode signal PX_i in response to the selection signals PSEL_i and /PSEL_i. 
       FIG. 5  is a circuit diagram showing a configuration of the output stage  32   i  of the pre-decoder  3 . The output stage  32   i  has a positive voltage level shifter  33 , negative voltage level shifter  34 , and buffer  35 . 
     The positive voltage level shifter  33  outputs the high potential VPOS or ground potential VSS in response to the selection signal PSEL_i or /PSEL_i. According to this embodiment, the positive voltage level shifter  33  consists of PMOS transistors P 11  and P 12  and NMOS transistors N 11  and N 12 . The gates of the PMOS transistors P 11  and P 12  are connected to the drains of the other PMOS transistors. The sources of the PMOS transistors P 11  and P 12  are commonly connected to a high voltage terminal which has the high potential VPOS. The drains of the PMOS transistors P 11  and P 12  are connected to the drains of the NMOS transistors N 11  and N 12 , respectively. The gates of the NMOS transistors P 11  and P 12  are supplied with the selection signals PSEL_i and /PSEL_i, respectively. The sources of the NMOS transistors N 11  and N 12  are connected to a ground terminal which has the ground potential VSS. 
     On the other hand, the negative voltage level shifter  34  outputs the power supply potential VCC or negative potential VNEG in response to the selection signal PSEL_i or /PSEL_i. According to this embodiment, the negative voltage level shifter  34  consists of PMOS transistors P 13  and P 14  and NMOS transistors N 13  and N 14 . The gates of the PMOS transistors P 13  and P 14  are connected to the drains of the other PMOS transistors. The gates of the PMOS transistors P 13  and P 14  are supplied with the selection signals /PSEL_i and PSEL_i, respectively. The sources of the PMOS transistors P 13  and P 14  are commonly connected to a power supply terminal which has power supply potential VCC. The drains of the PMOS transistors P 13  and P 14  are connected to the drains of the NMOS transistors N 13  and N 14 , respectively. The sources of the NMOS transistors N 13  and N 14  are connected to a negative voltage terminal which has the negative potential VNEG. 
     The buffer  35  generates a pre-decode signal PX_i in response to outputs from the positive voltage level shifter  33  and negative voltage level shifter  34 . According to this embodiment, the buffer  35  consists of a PMOS transistor P 15  and NMOS transistor N 15 . The PMOS transistor P 15  has its source connected to the high voltage terminal which has the high potential VPOS, and its gate connected to the output of the positive voltage level shifter  33 . The PMOS transistor P 15  has its drain connected to the drain of the NMOS transistor N 15 . The NMOS transistor N 15  has its source connected to the negative voltage terminal which has the negative potential VNEG, and its gate connected to the output of the negative voltage level shifter  34 . 
     When the pre-decode signal PX_i is selected for the addresses A 0  to A 2  (i.e., when the selection signals PSEL_i and /PSEL_i are activated), the pre-decoder  3  configured as described above pulls down the pre-decode signal PX_i to the negative potential VNEG. When the pre-decode signal PX_i is unselected, the pre-decoder  3  pulls up the pre-decode signal PX_i to the high potential VPOS. It should be noted that according to this embodiment, the pre-decode signal PX_i is an active low signal. 
     Configuration of Main Decoder  4   
       FIG. 6  is a block diagram showing a configuration of the main decoder  4 . The main decoder  4  has a selector  41  and output stages  42   0  to  42   m . The selector  41  selects the main decode signals MX_ 0  to MX_m for the upper addresses A 3  to A 8 . Specifically, when selecting the main decode signal MX_j, the selector  41  activates complementary selection signals MSEL_j and /MSEL_j (i.e., it pulls up the selection signal MSEL_j to a “High” level and pulls down the selection signal /MSEL_j to a “Low” level). The output stage  42   j  generates a main decode signal MX_j in response to the selection signals MSEL_j and /MSEL_j. 
       FIG. 7  is a circuit diagram showing a configuration of the output stage  42   j  of the main decoder  4 . A level shifter consisting of four MOS transistors: PMOS transistors P 16  and P 17  and NMOS transistors N 16  and N 17  is used in the output stage  42   j . The gates of the PMOS transistors P 16  and P 17  are connected to the drains of the other PMOS transistors. The sources of both PMOS transistors P 16  and P 17  are connected to a power supply terminal which has the power supply potential VCC. The drains of the PMOS transistors P 16  and P 17  are connected to the drains of the NMOS transistors N 16  and N 17 , respectively. The gates of the NMOS transistors N 16  and N 17  are supplied with the selection signals /MSEL_j and MSEL_j, respectively. The sources of the NMOS transistors N 16  and N 17  are connected to a ground terminal which has the ground potential VSS. The main decode signal MX_j is outputted from the drains of the PMOS transistor P 17  and NMOS transistor N 17 . 
     When the main decode signal MX_j is selected for the addresses A 3  to A 8  (i.e., when the selection signals MSEL_j and /MSEL_j are activated), the main decoder  4  configured as described above pulls down the main decode signal MX_j to the ground potential VSS. When the main decode signal MX_j is unselected, the main decoder  4  pulls up the main decode signal MX_j to the power supply potential VCC. It should be noted that the main decode signal MX_j is an active low signal. 
     Operation of Non-Volatile Semiconductor Storage Device 
     A feature of the non-volatile semiconductor storage device  10  according to this embodiment is that while each word line is driven by only two MOS transistors, no word line is brought into a floating state during its operation. This feature can be implemented as follows. 
     When the non-volatile semiconductor storage device  10  performs a write operation, the power lines VXPG 1  and VXPG 2  of the sub-decoder  2  are supplied with the high potential VPOS higher than the power supply potential VCC and the pull-down power line  24  (i.e., the source of the NMOS transistor N 3  of the driver  22 ) is set to the ground potential VSS by the power switch  25 . 
     Furthermore, desired pre-decode signals and main decode signals are selected for the addresses A 0  to A 8 . A write operation of the non-volatile semiconductor storage device  10  will be described below, citing a case where the main decode signal MX_m and pre-decode signal PX_ 0  are selected, activating the word line WL_ 0   —   m  (i.e., pulling it up to the high potential VPOS). 
     When the main decode signal MX_m and pre-decode signal PX_ 0  are selected, the main decode signal MX_m is driven at the ground potential VSS and the pre-decode signal PX_ 0  is driven at the negative potential VNEG as shown at top of  FIG. 8 . Consequently, the pull-up power line  23   m  is driven at the high potential VPOS and another pull-up power line  23   k  (k≠m) is driven at the ground potential VSS. Furthermore, since the pre-decode signal PX_ 0  is pulled down to the negative potential VNEG, the PMOS transistor P 3  of the driver  22 - 0 - m  turns on and the word line WL_ 0   —   m  is connected to the pull-up power line  23   m . Consequently, the word line WL_ 0   —   m  is pulled up to the high potential VPOS. 
     At this time, the word lines other than the word line WL_ 0   —   m  are kept at the ground potential VSS as described in detail below. First, description will be given of a word line WL_i_m (i≠0) for which the corresponding main decode signal is selected and pre-decode signal is unselected. Since the pre-decode signal PX_i is kept at the high potential VPOS, the NMOS transistor N 3  of the driver  22 - i - m  is turned on. Consequently, the word line WL_i_m is connected to the pull-down power line  24  via the NMOS transistor N 3 . Since the pull-down power line  24  is set at the ground potential VSS in write operations, the word line WL_i_m is kept at the ground potential VSS. 
     Regarding a word line WL_ 0   —   k  (k≠m) for which the corresponding main decode signal is unselected and pre-decode signal is selected, since the main decode signal MX_k is unselected, the pull-up power line  23   k  is pulled down to the ground potential VSS. On the other hand, the pre-decode signal PX_ 0  has been pulled down to the negative potential VNEG. Thus, the PMOS transistor P 3  of the driver  22 - 0 - k  turns on with its source supplied with the ground potential VSS, and its gate is supplied with the negative potential VNEG lower than the ground potential VSS. Consequently, the word line WL_ 0   —   k  is connected to the pull-up power line  23   k  via the PMOS transistor P 3  and kept at the ground potential VSS. 
     Finally, regarding a word line WL_i_k (i≠m, k≠m) for which the corresponding main decode signal and pre-decode signal are both unselected, since the pre-decode signal PX_i is kept at the high potential VPOS, the NMOS transistor N 3  of the driver  22 - i - k  is turned on. Consequently, the word line WL_i_k is connected to the pull-down power line  24  via the NMOS transistor N 3 . Since the pull-down power line  24  is set at the ground potential VSS in write operations, the word line WL-i-k is kept at the ground potential VSS. 
     In this way, in write operations, selected word lines are pulled up to the high potential VPOS while unselected word lines are kept at the ground potential VSS. 
     Read operations are performed in the same manner as write operations except that the power lines VXPG 1  and VXPG 2  of the sub-decoder  2  are supplied with the power supply potential VCC rather than the high potential VPOS. It will be self-apparent to those skilled in the art that selected word lines are pulled up to the power supply potential VCC while unselected word lines are kept at the ground potential VSS. 
     In erase operations, the pull-down power line  24  is pulled down to the negative potential VNEG by the power switch  25  while all the pre-decode signals and main decode signals remain unselected. Consequently, the sources of the NMOS transistors N 3  of all the drivers  22  are pulled down to the negative potential VNEG. On the other hand, since the unselected pre-decode signals PX_ 0  to PX_n are pulled up to the high potential VPOS, the high potential VPOS is supplied to the gates of the NMOS transistors N 3 , turning on the NMOS transistors N 3 . Consequently, all the word lines WL_ 0 _ 0  to WL_n_m are connected to the pull-down power line  24  and pulled down to the negative potential VNEG. Again, no word line is brought into a floating state. 
     In this way, with the non-volatile semiconductor storage device  10  according to this embodiment, each word line is driven by only two MOS transistors, but no word line is brought into a floating state during its operation. This is suitable for reducing the size of the non-volatile semiconductor storage device  10  and stabilizing its operation effectively. 
     A preferred embodiment of the present invention has been described in detail, but the present invention is not limited to the above embodiment. For example, as shown in  FIG. 9 , the main decode signals MX_ 0  to MX_m may be supplied directly to the pull-up power lines  23   0  to  23   m  (i.e., the sources of the PMOS transistors P 3  of the drivers  22 ). In that case, the level shifters  21   0  to  21   m  are eliminated from the sub-decoder  2  and the main decode signals MX_ 0  to MX_m are set to be active high. Specifically, when the sub-decoder  2  is configured as shown in  FIG. 9 , selected main decode signals MX_j are driven at the high potential VPOS in write operations, and at the power supply potential VCC in read operations. Unselected main decode signals MX_j are driven at the ground potential VSS. Also, the output stages  42   j  of the main decoder  4  are configured such that the main decode signals MX_ 0  to MX_m will be active high. 
     However, it is more preferable that the main decode signals MX_ 0  to MX_m are supplied to the level shifters  21   0  to  21   m  of each sub-decoder  2  and the pull-up power lines  23   0  to  23   m  are driven by the level shifters  21   0  to  21   m , as is the case with this embodiment. This is because such configurations reduce loads on both output stages  42   j  (i.e., circuits which generate the main decode signals MX_ 0  to MX_m) and level shifters  21   0  to  21   m , making it possible to drive word lines in a short time. With a configuration in which the main decode signals MX_ 0  to MX_m are supplied directly to the pull-up power lines  23   0  to  23   m , the output stages  42   j  of the main decoder  4  must drive the PMOS transistors P 3  of many drivers  22 . This will increase the load on the output stages  42   j  and unwantedly increase the time required to drive the word lines.

Technology Category: 3