Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to digital communication techniques. More specifically, the invention relates to a system and method for balancing the amplitude and phase of a received, quadrature-phase modulated signal. 
     2. Description of the Prior Art 
     One of the common methods for modulating digital signals is the use of multilevel systems or M-ary techniques. M-ary modulation techniques are natural extensions of binary modulation techniques and apply to L-level amplitude or phase shift keying. A commonly used quadriphase scheme is called quadrature phage shift keying or QPSK. Like all of the M-ary amplitude or phase schemes, its principle advantage is bandwidth reduction. 
     Since pulse rate f p  is: 
     
       
         f p =f s  log L  M,  Equation 1 
       
     
     where f s  is the symbol rate and M is the number of messages; with L representing the number of modulation levels, the larger L is, the smaller the pulse rate and hence, the smaller the bandwidth. 
     In telecommunication applications, QPSK modulates two different signals into the same bandwidth creating a two-dimensional signal space. This is accomplished by creating a composite phase modulated signal using two carriers of the same frequency but having a phase difference of 90 degrees as shown in FIG.  1 A. By convention, the cosine carrier is called the in-phase component I and the sine carrier is the quadrature component Q. The I component is the real component of the signal and the Q component is the imaginary component of the signal. Each of the I and Q components are bi-phase modulated. A QPSK symbol consists of at least one sample from both the in-phase I and quadrature Q signals. The symbols may represent a quantized version of an analog sample or digital data. 
     All phase modulated schemes must overcome the inevitable problem of phase synchronization. For proper operation of QPSK signaling, the I and Q channels should have the same gain throughout processing both received channels, keeping the I and Q channels uncorrelated. Mismatched signal gains or magnitudes between the uncorrelated I and Q channels create errors when processing. Phase differences other than 90 degrees between the signals cause spillover between the channels and similarly result in degraded performance. 
     Typical receivers exhibit different overall gains for the separate I and Q channels due to mismatched gains in the mixers, filters, and A/D converters caused by variations in component values due in part to temperature, manufacturing tolerances and other factors. Amplitude and phase imbalance between the I and Q channels result in the distortions shown in FIGS. 1B and 1C, decreasing overall signal-to-noise ratio (SNR). 
     Prior art approaches taken to avoid amplitude and phase imbalance rely upon very precise circuitry controlling each gain stage with active temperature compensation. These expensive designs require components that are manufactured with extremely low temperature coefficients and with the mixers for the I and Q channels custom matched during manufacture. 
     Accordingly, there exists a need for a system that balances the amplitude and phase of a QPSK signal upon reception increasing signal integrity and thereby reducing bit error rate (BER). 
     SUMMARY OF THE INVENTION 
     The present invention balances the amplitude and phase of a received QPSK signal that may have been corrupted during transmission. The output from the system is a signal corrected in both amplitude and phase. The system determines the amplitude of the I and Q channels of a received signal, compares them, and applies a correction to one or both channels correcting amplitude imbalance. For phase imbalance, the system calculates the cross-correlation of the I and Q channels which should average to zero. A correction factor is derived from the cross-correlation product and is applied to both channels, returning the phase cross-correlation to zero. 
     Accordingly, it is an object of the invention to provide a system which balances the amplitude of a received QPSK signal. 
     It is a further object of the invention to provide a system which balances the phase of a received QPSK signal. 
     Other objects and advantages of the system and method will become apparent to those skilled in the art after reading the detailed description of the preferred embodiment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a plot of a QPSK symbol, balanced in both amplitude and phase. 
     FIG. 1B is a plot of a QPSK symbol, amplitude imbalanced. 
     FIG. 1C is a plot of a QPSK symbol, phase imbalanced. 
     FIG. 2 is a block diagram of an amplitude balancing system in accordance with the present invention. 
     FIG. 3 is a block diagram of a phase balancing system in accordance with the present invention. 
     FIG. 4 is a vector representation showing phase correction. 
     FIG. 5 is a block diagram of a combined amplitude and phase balancing system in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiment will be described with reference to the drawing figures where like numerals represent like elements throughout. 
     An embodiment showing the amplitude balancing system  17  of the present invention is shown in FIG. 2 where two bi-phase modulated signals  19  are input  21 I,  21 Q. Quantizing is the process of measuring the intensity of a signal in each sample and assigning a digital number to that measured value. Each time the sampling circuit samples the signal, it measures the intensity of the varying analog signal at that discrete moment in time. The input  23 I,  23 Q data streams represent the discrete samples of data assembled into finite words each having a plurality of bits. The number of bits that define each word determine the total quantization of each sample or symbol. For example, six-bit quantization: 
     
       
         quantization levels=2 n −1  Equation 2 
       
     
     with n equal to 6 would yield a resolution of 63 levels. Desired signal resolution determines n. 
     Each signal  23 I,  23 Q component, I and Q, is coupled to an input of an amplifier  25 I,  25 Q which has an adjustable gain. The output  27 I,  27 Q of the amplifiers  25 I,  25 Q are coupled to an absolute value processor  29 I,  29 Q to obtain the relative magnitudes of each incoming symbol  23 I,  23 Q. The output  31 I,  31 Q of the absolute value processors  29 I,  29 Q are coupled to inputs of respective low pass filters  33 I,  33 Q. 
     The low pass filters  33 I,  33 Q time-average the received component symbols  23 I,  23 Q, giving additional weight to recent samples and decreasing weight to previous samples. In the present embodiment  17 , IIR (infinite impulse response) filters  33 I,  33 Q with one pole are used, however, other types of filters or different order IIR filters can also be used without deviating from the principle of the invention. The low pass filter outputs  35 I,  35 Q present averaged estimates of the sample amplitudes output from the absolute value processors  29 I,  29 Q. 
     A summer  37  obtains the difference from the outputs  35 I,  35 Q of the low pass filters  33 I,  33 Q producing an error reference signal  39 . If the I and Q components of an input signal  23 I,  23 Q are orthogonal to each other, the error reference signal  39  will have zero magnitude, indicating a balanced symbol. If the error reference signal  39  produces a value other than zero, the symbols are not amplitude balanced. 
     A non-zero-value error reference signal  39  becomes an error correction value. The reference signal  39  is coupled to an input of a hard limiter processor  41 . The hard limiter  41  outputs a signal  43  smaller in magnitude, either positive or negative, in dependence upon the error reference signal  39 . The hard limiter processor  41  clips the error reference signal  39  magnitude thereby making the sign of the error reference signal  39  a correction factor. This is done for simplifying the implementation, the hard limiter is not essential to the invention. 
     The output  43  of the hard limiter processor  41  is coupled to a leaky integrator which is an accumulator  45 . The accumulator  45  adds the present value input with an accumulated value from previous input values and outputs  47  a sum. Since the accumulator  45  has a finite bit width, over time, the accumulated value will self-limit in magnitude and plateau if errors persist and are great. The accumulated plurality of error reference signals  39  in the internal accumulator of the accumulator  45  will average to zero when the system reaches stasis. 
     The output  47  from the accumulator  45  is coupled to a gain input  49 I,  49 Q on each adjustable gain amplifier  25 I,  25 Q. The amplifiers  251 ,  25 Q balance the amplitudes of the received I and Q symbols  23 I,  23 Q, increasing or attenuating their gains in dependence with the accumulator  45  output signal  47 . As can be seen, the reference signal  39  is negative feedback to the upstream amplification stages  25 I,  25 Q. A positive control voltage at the gain input  49 I,  49 Q indicates a gain increase for that amplifier; a negative control voltage indicates attenuation. 
     If the amplitudes of the input signals  23 I,  23 Q are not balanced, the system will adjust the variable amplifiers  25 I,  25 Q (attenuating one component while boosting the other) according to the accumulator  45  output signal  47  until the I and Q symbol amplitudes are within a predetermined tolerance. If the symbol gains are equal, but vary between received symbols, the system  17  will not effect correction. A downstream automatic gain control (AGC)(not shown) equalizes the system output  51 I,  51 Q for further signal processing (not shown). 
     An embodiment showing the phase correction system  61  of the present invention is shown in FIG.  3 . Two bi-phase modulated signals  19  are input  63 I,  63 Q into the system  61 . The input  63 I,  63 Q data streams  65 I,  65 Q for the I and Q symbols are coupled to a first input  67 I,  67 Q of parallel summers  69 I,  69 Q. The output  71 I,  71 Q of each summer  69 I,  69 Q are the system output  73 I,  73 Q and feedback for the phase correction system  61 . Both feedback lines  71 I,  71 Q are coupled to a mixer  75  for correlation. The mixer  75  cross-correlated output signal  77  is coupled to an integrator  79 . The integrator  79  time-averages the cross-correlation product  77 . The integrator output is coupled to a hard limiter processor  83 . The hard decision processor  83  limits the magnitude of the integrated cross-correlation product. The hard decision processor  83  output  85  retains sign. The hard limiter processor  83  output  85  is coupled to an accumulator input  87 . The hard decision processor  83  reduces implementation complexity, one skilled in this art would recognize that it is not essential. 
     As previously discussed, the function of an accumulator is to accumulate, over-time, the present input value with previous inputs. The sum is output as a correction signal. 
     The correction signal  89  is coupled to a first input  91 I of a variable gain amplifier  93 I coupling the Q input  65 Q with the I input  63 I. The correction signal  89  also is coupled to a first input  91 Q of a variable gain amplifier  93 Q coupling the I symbol input  65 I with the Q input  63 Q. 
     The correction signal  89  adjusts both amplifiers  93 I,  93 Q increasing or decreasing their gain. The amplifier outputs  95 I,  95 Q are coupled to a second input  97 I,  97 Q of the input adders  69 I,  69 Q. 
     The phase correction is shown as a vector representation in FIG.  4 . The adders  69 I,  69 Q subtract the portion of Q component  63 Q from the I component  65 I; 
     
       
         I=x−ry,  Equation 3 
       
     
     
       
         −I=−x−ry,  Equation 4 
       
     
     where r  Δ  cross correlation, 
     and the portion of I component  63 I from the Q component  65 Q; 
      Q=y−xr,  Equation 5 
     
       
         Q=−y−xr,  Equation 6 
       
     
     where r  Δ  cross correlation, 
     in order to remove the cross correlation contribution from each. Once the parts of the signals that result in the cross correlation are removed, the outputs  71 I and  71 Q of the adders  69 I,  69 Q become uncorrelated I, Q and orthogonal in signal space. 
     An alternative embodiment combining both systems correcting amplitude  17  and phase  61  imbalance is shown in FIG.  5 . The system  101  is a simple series connection outputting  103 I,  103 Q a symbol corrected in both amplitude and phase. Another combined embodiment where the amplitude balancer  17  follows the phase balancer  61  is also possible. 
     While specific embodiments of the present invention have been shown and described, many modifications and variations could be made by one skilled in the art without departing from the spirit and scope of the invention. The above description serves to illustrate and not limit the particular form in any way.

Technology Category: 5