Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 11/554,659, filed Oct. 31, 2006, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2005-367544, filed on Dec. 21, 2005 and No. 2006-98740, filed on Mar. 31, 2006. The contents of all of those documents are incorporated herein by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device, and more particularly, to a high-voltage power semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 49  is a top view of a conventional horizontal n-channel IGBT (Insulated Gate Bipolar Transistor) generally denoted at  700 .  FIG. 50  is a cross sectional view of FIG.  49  taken along the direction X-X. 
         [0006]    As shown in  FIG. 50 , the IGBT  700  includes a p-type substrate  1 . The p-type substrate  1  seats an n −  layer  2  in which an n-type buffer layer  3  is formed. There is a p-type collector layer  4  in the n-type buffer layer  3 . 
         [0007]    A p-type base layer  5  is formed in the n −  layer  2 , over a predetermined distance from the p-type collector layer  4 . In the p-type base layer  5 , an n-type emitter layer (n + )  6  is formed so that it is on the inner side relative to a peripheral portion of the p-type base layer  5  and shallower than the p-type base layer  5 . A p-type emitter layer (p + )  7  as well is formed in the p-type base layer  5 . 
         [0008]    A field oxide film  8  is formed on the surface of the n −  layer  2  which is located between the n-type buffer layer and the p-type base layer  5 . On a channel region  15  formed in the p-type base layer  5  and located between the emitter layer  6  and the n −  layer  2 , a gate wire  10  is disposed via a gate oxide film  9 . Further, there is a protection film  11  which is disposed covering the field oxide film  8  and the like. 
         [0009]    A gate electrode  12  is disposed such that it is electrically connected with the gate wire  10 . An emitter electrode  13  is further disposed such that it is electrically connected with both the n-type emitter layer  6  and the p-type emitter layer  7 . In addition, a collector electrode  14  is disposed such that it is electrically connected with the p-type collector layer  4 . The emitter electrode  13 , the collector electrode  14  and the gate electrode  12  are electrically isolated from each other. 
         [0010]    As shown in  FIG. 49 , the p-type collector layer  4  is located at the center of the IGBT  700  in which structure the n-type buffer layer  3 , the n −  layer  2 , the p-type base layer  5 , the n-type emitter layer  6  and the p-type emitter layer  7  surround the p-type collector layer  4  in this order, and this structure has an endless shape which is defined by connecting two semi-circular sections by straight sections. For easy understanding,  FIG. 49  omits the field oxide film  8 , the gate oxide film  9 , the gate wire  10 , the gate electrode  12 , the protection film  11 , the emitter electrode  13  and the collector electrode  14  (JPB 3647802). 
       SUMMARY OF THE INVENTION 
       [0011]      FIG. 51  shows a collector-emitter current (I CE ) characteristic which the IGBT  1000  exhibits upon application of a collector-emitter voltage (V CE ) in a condition that a constant gate-emitter voltage (V GE ) is applied upon the IGBT  700 . The collector-emitter voltage (V CE ) is measured along the horizontal axis, whereas the vertical axis denotes the collector-emitter current (I CE ). A room temperature is a temperature for measurement. 
         [0012]    From  FIG. 51 , one can see that as V CE  gradually rises, ICE becomes approximately 0.2 A when V CE  reaches 6V or becomes close to 6V and beyond this, I CE  tends to get saturated. This causes a problem that however high V CE  becomes, I CE  will not become sufficiently large. There is another problem that as the gradient expressing I CE  remains moderate while V CE  grows from 0V to 6V and the ON-resistance (V CE /I CE ) is therefore high. 
         [0013]      FIG. 52  shows the turn-off waveform of the IGBT  700 . The turn-off time is measured along the horizontal axis and the collector-emitter voltage (V CE ) or the collector-emitter current (I CE ) is measured along the vertical axis. In  FIG. 52 , the symbol (A V ) denotes changes of the V CE  value and the symbol (A I ) denotes changes of the I CE  value. 
         [0014]    As one can tell from  FIG. 52 , the fall time (i.e., the time needed for I CE  to come down to 10% from 90% which is the maximum value) has a large value exceeding 1 μs. The junction-isolated (JI) horizontal IGBT  700  in which the IGBT is formed in the n −  layer  2  on the p-type substrate  1  thus has problem that its switching speed is slow and it has a large switching loss. 
         [0015]    The horizontal IGBT  700  has a further problem that a short-circuit in an inverter circuit or the like latches up a parasitic thyristor which is formed by the p-type collector layer  4 /the n-type buffer layer  3 /the n −  layer  2 /the p-type base layer  5 /the n-type emitter layer  6  and increases the current density of the IGBT  700  so that the IGBT may get destroyed easily. 
         [0016]    The present invention has been made to solve these problems, and accordingly, an object of the present invention is to provide a semiconductor device which exhibits an improved collector-emitter current characteristic, shortens the fall time and increases the latch-up tolerance of a parasitic thyristor. 
         [0017]    The present invention is directed to a horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including:
       a semiconductor substrate of a first conductivity type;   a semiconductor region of a second conductivity type formed on the semiconductor substrate;   a collector layer of the first conductivity type formed within the semiconductor region;   a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and   a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, wherein   the unit semiconductor elements are disposed adjacent to each other.       
 
         [0024]    According to the present invention, it is possible to obtain a semiconductor device which exhibits an excellent collector-emitter current characteristic and has a short fall time and in which the latch-up tolerance of a parasitic thyristor is high. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1  is a top view of an IGBT according to an embodiment 1 of the present invention; 
           [0026]      FIG. 2  is a cross sectional view of the IGBT according to the embodiment 1 of the present invention; 
           [0027]      FIG. 3  is a top view of another IGBT according to the embodiment 1 of the present invention; 
           [0028]      FIG. 4  shows a relationship between the number of unit IGBTs included in the IGBT according to the embodiment 1 of the present invention and the total channel width; 
           [0029]      FIG. 5  shows a channel region of a conventional IGBT over the IGBT according to the embodiment of the present invention; 
           [0030]      FIG. 6  is a graph which compares the surface area size of the IGBT according to the embodiment 1 of the present invention with that of a conventional IGBT; 
           [0031]      FIG. 7  is a graph which compares the surface area size of the IGBT according to the embodiment 1 of the present invention with that of a conventional IGBT; 
           [0032]      FIG. 8  shows a relationship between a collector-emitter voltage (V CE ) and a collector-emitter current (I CE ) in the IGBT according to the embodiment of the present invention; 
           [0033]      FIG. 9  is a top view of an IGBT according to an embodiment 2 of the present invention; 
           [0034]      FIG. 10  is a cross sectional view of the IGBT according to the embodiment 2 of the present invention; 
           [0035]      FIG. 11  is a top view of another IGBT according to the embodiment 2 of the present invention; 
           [0036]      FIG. 12  shows the turn-off waveform of the IGBT according to the embodiment 2 of the present invention; 
           [0037]      FIG. 13  shows an electric potential distribution, a current distribution, and the boundary line of a depletion region as they are at the time of switching turn-off of a resistance load within the IGBT according to the embodiment 1 of the present invention; 
           [0038]      FIG. 14  shows a hole distribution as it is at the time of switching turn-off of a resistance load within the IGBT according to the embodiment 1 of the present invention; 
           [0039]      FIG. 15  shows a hole distribution and an electron distribution as they are at the time of switching turn-off of a resistance load, and a concentration as it is in equilibrium within the IGBT according to the embodiment 1 of the present invention; 
           [0040]      FIG. 16  shows an electric potential distribution, a current distribution, and the boundary line of a depletion region within the IGBT as they are at the time of switching turn-off of a resistance load according to the embodiment 2 of the present invention; 
           [0041]      FIG. 17  shows a hole distribution as it is at the time of switching turn-off of a resistance load within the IGBT according to the embodiment 2 of the present invention; 
           [0042]      FIG. 18  shows a hole distribution and an electron distribution as they are at the time of switching turn-off of a resistance load, and a concentration as it is in equilibrium within the IGBT according to the embodiment 2 of the present invention; 
           [0043]      FIG. 19  is a cross sectional view of an IGBT according to a embodiment 3 of the present invention; 
           [0044]      FIG. 20  is a cross sectional view of other IGBT according to the embodiment 3 of the present invention; 
           [0045]      FIG. 21  shows an electric field distribution, a current distribution, and the boundary line of a depletion region within the IGBT as they are at the time of switching turn-off of a resistance load according to the embodiment 2 of the present invention; 
           [0046]      FIG. 22  shows an electric field distribution, a current distribution, and the boundary line of a depletion region within the IGBT as they are at the time of switching turn-off of a resistance load according to the embodiment 3 of the present invention; 
           [0047]      FIG. 23  is a top view of a part of an IGBT according to an embodiment 4 of the present invention; 
           [0048]      FIG. 24  is a cross sectional view of the IGBT according to the embodiment 4 of the present invention; 
           [0049]      FIG. 25  is a cross sectional view of the IGBT according to the embodiment 4 of the present invention; 
           [0050]      FIG. 26  is a top view of a part of the IGBT according to the embodiment 4 of the present invention; 
           [0051]      FIG. 27  is a top view which shows the arrangement of a p-type emitter layer in the IGBT according to the embodiment 4 of the present invention; 
           [0052]      FIG. 28  is a top view of a part of an IGBT according to an embodiment 5 of the present invention; 
           [0053]      FIG. 29  is a cross sectional view of the IGBT according to the embodiment 5 of the present invention; 
           [0054]      FIG. 30  is a top view of an IGBT according to an embodiment 6 of the present invention; 
           [0055]      FIG. 31  is a top view of another IGBT according to the embodiment 6 of the present invention; 
           [0056]      FIG. 32  is a cross sectional view of the IGBT according to the embodiment 6 of the present invention; 
           [0057]      FIG. 33  is a cross sectional view of an IGBT according to a embodiment 7 of the present invention; 
           [0058]      FIG. 34  is a cross sectional view of another IGBT according to the embodiment 7 of the present invention; 
           [0059]      FIG. 35  is a top view of a part of an IGBT according to an embodiment 8 of the present invention; 
           [0060]      FIG. 36  is a cross sectional view of the IGBT according to the embodiment 8 of the present invention; 
           [0061]      FIG. 37  is a cross sectional view of the IGBT according to the embodiment 8 of the present invention; 
           [0062]      FIG. 38  is a top view which shows the arrangement of a p-type emitter layer in an IGBT according to an embodiment 9 of the present invention; 
           [0063]      FIG. 39  is a cross sectional view of the IGBT according to the embodiment 9 of the present invention; 
           [0064]      FIG. 40  is a top view of an IGBT according to an embodiment 10 of the present invention; 
           [0065]      FIG. 41  is an enlarged view of the IGBT according to the embodiment 10 of the present invention; 
           [0066]      FIG. 42  is an enlarged view of the IGBT according to the embodiment 10 of the present invention; 
           [0067]      FIG. 43  is an enlarged view of the IGBT according to the embodiment 10 of the present invention; 
           [0068]      FIG. 44  is a top view of other IGBT according to the embodiment 10 of the present invention; 
           [0069]      FIG. 45  is an enlarged view of another IGBT according to the embodiment 10 of the present invention; 
           [0070]      FIG. 46  is an enlarged view of another IGBT according to the embodiment 10 of the present invention; 
           [0071]      FIG. 47  is an enlarged view of another IGBT according to the embodiment 10 of the present invention; 
           [0072]      FIG. 48  is a cross sectional view of the IGBT according to the embodiment 10 of the present invention; 
           [0073]      FIG. 49  is a top view of a conventional IGBT; 
           [0074]      FIG. 50  is a cross sectional view of the conventional IGBT; 
           [0075]      FIG. 51  shows a relationship between a collector-emitter voltage (V CE ) and a collector-emitter current (I CE ) in the conventional IGBT; and 
           [0076]      FIG. 52  shows the turn-off waveform of the conventional IGBT. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1 
       [0077]      FIG. 1  is a top view of a horizontal n-channel IGBT (Insulated Gate Bipolar Transistor) according to the embodiment 1 of the present invention generally denoted at  100 .  FIG. 2  is a cross sectional view of  FIG. 1  taken along the direction A-A. 
         [0078]    As shown in  FIG. 2 , the IGBT  100  includes a p-type substrate  1  of silicon or the like. The p-type substrate  1  seats an n −  layer  2  in which an n-type buffer layer  3  is selectively formed. There is a p-type collector layer  4  selectively formed in the n-type buffer layer  3 . 
         [0079]    The buffer layer  3  may be omitted (This similarly applies also to the embodiments described below.). 
         [0080]    In the n −  layer  2 , the p-type base layer  5  is selectively formed in over a predetermined distance from the p-type collector layer  4 . In the p-type base layer  5 , the n-type emitter layers (n + )  6  are selectively formed so that they are located on the inner side relative to a peripheral portion of the p-type base layer  5  and shallower than the p-type base layer  5 . A p-type emitter layer (p + )  7  as well is formed in the p-type base layer  5 . 
         [0081]    A field oxide film  8  which may be a silicon oxide film for instance is formed on the surface of the n −  layer  2  which is located between the n-type buffer layer  3  and the p-type base layer  5 . On a channel region  15  formed in the p-type base layer  5  and located between the emitter layer  6  and the n −  layer  2 , a gate wire  10  is disposed via a gate oxide film  9  which may be a silicon oxide film for example. The gate wire  10  is made of aluminum for example. Further, a protection film  11  which may be a silicon nitride film for instance is disposed covering the field oxide film  8 , etc. 
         [0082]    A gate electrode  12  is disposed such that it is electrically connected with the gate wire  10 . The gate electrode  12  is made of aluminum for example. 
         [0083]    An emitter electrode  13  is further disposed such that it is electrically connected with both the n-type emitter layers  6  and the p-type emitter layer  7 . In addition, a collector electrode  14  is disposed such that it is electrically connected with the p-type collector layer  4 . The emitter electrode  13  and the collector electrode  14  are made of aluminum for instance. The emitter electrode  13 , the collector electrode  14  and the gate electrode  12  are electrically isolated from each other. 
         [0084]    Further, as shown in  FIG. 1 , the IGBT  100  according to the embodiment 1 has a structure that ring-like multiple unit IGBTs, in each one of which the p-type collector layer  4  is located at the center and surrounded by the n-type buffer layer  3 , the n −  layer  2 , the p-type base layer  5 , the n-type emitter layer  6  and the p-type emitter layer  7  in this order, are arranged adjacent to each other and disposed side by side. Although the foregoing has described that the unit IGBTs have circular shapes, the unit IGBTs may have oval shapes which are close to circles or polygonal shapes which are close to circles. 
         [0085]      FIG. 3  is a top view of another IGBT according to the embodiment 1 of the present invention generally denoted at  150 . This is the same structure as that of the IGBT  100  except for that the p-type emitter layers  7  of circle-like adjacent unit IGBTs partially overlap each other. 
         [0086]      FIG. 4  shows a relationship between the number of unit IGBTs and the total channel width, each in an instance that an IGBT is formed by a single conventional IGBT  700  which is long and thin and has an endless shape and an instance that an IGBT is like the IGBT  150  according to the embodiment 1 which is formed by plural circular unit IGBTs. In  FIG. 4 , the horizontal axis denotes the number of unit IGBTs and the vertical axis denotes the total channel width. 
         [0087]    Where multiple circular unit IGBTs are disposed side by side, the total channel width is longer as compared with where only one thing and long IGBT is used: The total channel width in an instance that ten unit IGBTs are disposed side by side is approximately double the channel width of one IGBT. 
         [0088]      FIG. 5  shows a channel region of the conventional IGBT  700  over the IGBT  150  which is formed by three unit IGBTs. It is seen that use of the IGBT  150  according to the embodiment 1 increases the channel width. 
         [0089]      FIG. 6  is a graph which compares the surface area sizes (occupation area sizes) of the IGBT  150  according to the embodiment 1 and the conventional IGBT which are compared against each other in  FIG. 5 . The horizontal axis denotes the number of unit IGBTs, while the vertical axis denotes the surface area size of the IGBT. It is seen that more unit IGBTs in the structure, the smaller the surface area size is, as compared with the IGBT  700  which has the conventional structure. 
         [0090]    As shown in  FIG. 7 , for instance, in the event that the IGBT  150  is formed by three unit IGBTs, the surface area size indicated by the shaded area can be reduced as compared with the IGBT  700  which has the conventional structure. 
         [0091]    In the event that a horizontal IGBT is to be formed in an area of a limited space, use of the IGBT  100  or  150  according to the embodiment 1 reduces the surface area size (occupation area size) and extends the total channel width as compared with the IGBT  700  which has the conventional structure. 
         [0092]      FIG. 8  shows a collector-emitter current (I CE ) characteristic which the IGBT  1500  according to the embodiment 1 exhibits upon application of a collector-emitter voltage (V CE ) in a condition that a constant gate-emitter voltage (V GE ) is applied upon the IGBT  150 . The collector-emitter voltage (V CE ) is measured along the horizontal axis, whereas the vertical axis denotes the collector-emitter current (I CE ). A room temperature is a temperature for measurement. 
         [0093]    From  FIG. 8 , one can see that as V CE  gradually rises, I CE  becomes approximately 0.4 A when V CE  reaches 6V or becomes close to 6V and around beyond this, I CE  tends to get saturated, and I CE  on that occasion has a large value which is about double that of the conventional IGBT (see  FIG. 51 ). It is also seen that the gradient is greater than in the conventional IGBT while V CE  grows from 0V to 6V and that the ON-resistance (V CE /I CE ) is low. 
         [0094]    The improved I CE  characteristic is attributable to the longer total channel width than that of the IGBT  700  which has the conventional structure. 
         [0095]    While  FIGS. 4 through 8  refer to the IGBT  150 , an approximately similar result is obtained on the IGBT  100  as well. 
       Embodiment 2 
       [0096]      FIG. 9  is a top view of a horizontal n-channel IGBT according to the embodiment 2 of the present invention generally denoted at  200 .  FIG. 10  is a cross sectional view of  FIG. 9  taken along the direction B-B. In  FIGS. 9 and 10 , the same reference symbols as those appearing in  FIGS. 1 and 2  denote the same or corresponding portions. 
         [0097]    As shown in  FIG. 10 , the IGBT  200  has an SOI structure in which a buried oxide film  20  which may be a silicon oxide film for example is formed between the p-type substrate  1  and the n −  layer  2 . The structure is otherwise the same as that of the IGBT  100 . The structure of the IGBT  200  shown in the top view in  FIG. 9  is the same as the structure of the IGBT  100  shown in  FIG. 2 . In this structure, the conductivity type of the substrate  1  can be chosen irrespectively of the conductivity type of the n −  layer  2 . 
         [0098]      FIG. 11  is a top view of another IGBT according to the embodiment 2 of the present invention generally denoted at  250 . This is the same structure as that of the IGBT  200  except for that the p-type emitter layers  7  of circle-like adjacent unit IGBTs partially overlap each other. 
         [0099]    The IGBTs  100  and  150  according to the embodiment 1 may be called “the junction-isolated type” while the IGBTs  200  and  250  according to the embodiment 2 may be called “dielectric-isolated type”. 
         [0100]      FIG. 12  shows the turn-off waveform of the IGBT  200 . The turn-off time is measured along the horizontal axis and the collector-emitter voltage (V CE ) or the collector-emitter current (I CE ) is measured along the vertical axis. In  FIG. 12 , the symbols ( 1   V ) and ( 1   C ) denote changes of the V CE  value and the I CE  value in the IGBT  100  according to the embodiment 1, and the symbols ( 2   V ) and ( 2   C ) denote changes of the V CE  value and the I CE  value in the IGBT  200  according to the embodiment 2. 
         [0101]    Although the fall time (tf: the time needed for I CE  to come down to 10% from 90% which is the maximum value) has a large value exceeding 1 μs in the IGBT  700  which has the conventional structure shown in  FIG. 50 , the fall time is approximately 0.5 μs in the IGBT (See ( 2 C).) according to the embodiment 2. The IGBT according to the embodiment 2 thus has a faster switching speed and a smaller switching loss than the conventional IGBT ( FIG. 52 ). In the turn-off waveform as it is upon switching of a resistance load, as V CE  rises, I CE  decreases at about the same absolute value of falling rate as that of the rising rate of V CE . 
         [0102]      FIG. 13  shows a current distribution (solid lines) and a voltage distribution (dashed lines) and the boundary line of a depletion region (dotted-and-dashed line) as they are at the time of switching turn-off of a resistance load (10.6 μs) within the junction-isolated horizontal IGBT  100  according to the embodiment 1 described above, which drawing corresponds to the cross sectional view in  FIG. 1 . 
         [0103]    In the case of the junction-isolated horizontal IGBT  100 , a depletion layer expanding from the emitter side spreads not only to the collector side but even to the p-type substrate, and therefore, the electric potential distribution and the current distribution as well spread to the p-type substrate. This suppresses depletion toward the collector side and makes the V CE  increase relatively moderate. As a result, the corresponding I CE  decrease as well is relatively moderate. 
         [0104]      FIG. 14  shows a hole distribution (solid lines) as it is at the time of switching turn-off of a resistance load (10.6 μs) within the junction-isolated horizontal IGBT  100  according to the embodiment 1 described above, which drawing corresponds to the cross sectional view in  FIG. 1 . 
         [0105]    In the junction-isolated horizontal IGBT  100 , as shown in  FIG. 13 , depletion toward the collector side from the emitter side is suppressed, there are numerous holes distributed inside n −  layer and the p-type substrate. When there are numerous holes distributed inside n −  layer, the p-type substrate and the like, it takes time until the holes disappear and the fall time (tf) becomes relatively long. 
         [0106]      FIG. 15  shows (a) a hole distribution and (b) an electron distribution at the time of switching turn-off of a resistance load (10.6 μs) and (c) a concentration as it is in equilibrium within the junction-isolated horizontal IGBT  100  according to the embodiment 1 described above, which drawing shows the distributions from the collector side to the emitter side at a constant depth inside n −  layer. 
         [0107]    As shown in  FIG. 13 , since depletion toward the collector side from the emitter side is suppressed in the junction-isolated horizontal IGBT  100 , the n −  layer excessively contains holes and electrons beyond their concentrations in equilibrium. Since there are numerous and excessive holes and electrons within the n −  layer, it takes a long time before the excessive holes and electrons disappear from the n layer. Due to this, the fall time (tf) is only slightly faster than in the IGBT  700  which has the conventional structure. 
         [0108]    Meanwhile,  FIG. 16  shows an electric potential distribution (solid lines), (b) a current distribution (dashed lines) and the boundary line of a depletion region (dotted-and-dashed line) at the time of switching turn-off of a resistance load (10.6 μs) within the dielectric-isolated horizontal IGBT  200  according to the embodiment 2, which drawing corresponds to the cross sectional view in  FIG. 10 . 
         [0109]    In the dielectric-isolated horizontal IGBT  200 , due to the buried oxide film present between the n −  layer and the p-type substrate, a depletion layer spreading from the emitter side will not expand to the p-type substrate but instead grows toward the collector side within the n −  layer. The p-type substrate therefore does not have a current distribution or an electric potential distribution. This encourages depletion toward the collector side, which increases V CE . In consequence, the corresponding I CE  as well increases, which quickens the fall time (tf). 
         [0110]      FIG. 17  shows a hole distribution (denoted at the solid lines) as it is at the time of switching turn-off of a resistance load (10.6 μs) within the dielectric-isolated horizontal IGBT  200  according to the embodiment 2, which drawing corresponds to the cross sectional view in  FIG. 10 . 
         [0111]    In the dielectric-isolated horizontal IGBT  200 , as shown in  FIG. 16 , depletion toward the collector side from the emitter side is facilitated, and hence, there are a few holes distributed within the n −  layer. Due to this, it takes only a short time before the holes distributed within the n −  layer disappear and the fall time (tf) becomes short. 
         [0112]      FIG. 18  shows (a) a hole distribution and (b) an electron distribution at the time of switching turn-off of a resistance load (10.6 μs) and (c) a concentration as it is in equilibrium within the dielectric-isolated horizontal IGBT  200 , which drawing shows the distributions from the collector side to the emitter side at a constant depth inside n −  layer. 
         [0113]    In the dielectric-isolated horizontal IGBT  200 , as described above, since depletion toward the collector side from the emitter side is facilitated, an area free from the spreading depletion layer is narrow in the n −  layer. Hence, with in the n −  layer, there are only a few holes and electrons beyond their concentrations in equilibrium (excessive holes and excessive electrons). When there are only a few excessive holes and electrons in the n −  layer, it takes only a short time before the excessive holes and electrons disappear, which quickens the fall time (tf). 
         [0114]    The IGBT  200  according to the embodiment 2 thus shortens the fall time (tf), in addition to the improved emitter current (I CE ) characteristic which is realized by the IGBT  100  according to the embodiment 1. 
         [0115]    While  FIGS. 16 through 18  refer to the IGBT  200 , an approximately similar effect is attained by the IGBT  250  as well. 
         [0116]    The structure of disposing the insulation film  20  between the p-type substrate  1  and the n −  layer is applicable also to conventional IGBTs. 
       Embodiment 3 
       [0117]      FIG. 19  is a cross sectional view of a horizontal n-channel IGBT according to the embodiment 3 of the present invention generally denoted at  300 , which is illustration viewed from the same direction as the A-A direction in  FIG. 1 . In  FIG. 19 , the same reference symbols as those appearing in  FIG. 2  denote the same or corresponding portions. 
         [0118]    The IGBT  300  shown in  FIG. 19  includes, on the emitter side, a p −  layer  30  which is formed narrower and deeper than the p-type base layer  5  but not deep enough to reach the p-type substrate  1  in such a manner that it contacts the bottom surface of the p-type base layer  5 . The structure is otherwise the same as that of the IGBT  100  which is shown in  FIG. 2 . 
         [0119]      FIG. 20  is a cross sectional view of other horizontal n-channel IGBT according to the embodiment 3 of the present invention generally denoted at  350 , which is illustration viewed from the same direction as the B-B direction in  FIG. 9 . In  FIG. 20 , the same reference symbols as those appearing in  FIG. 10  denote the same or corresponding portions. 
         [0120]    The IGBT  350  shown in  FIG. 20  includes, on the emitter side, a p −  layer  30  whose width (the length along the right-to-left direction in  FIG. 20 ) is narrower and which is deeper than the p-type base layer  5  but not deep enough to reach the buried insulation film  20  in such a manner that it contacts the bottom surface of the p-type base layer  5 . The structure is otherwise the same as that of the IGBT  200  which is shown in  FIG. 10 . 
         [0121]      FIG. 21  shows a current distribution (solid lines), an electric field distribution (dashed lines) and the boundary line of a depletion region (dotted-and-dashed line) as they are at the time of switching turn-off of a resistance load (10.6 μs) within the dielectric-isolated horizontal IGBT  200  according to the embodiment 2, which drawing corresponds to the cross sectional view in  FIG. 10 . 
         [0122]    Meanwhile,  FIG. 22  shows a current distribution (solid lines) and an electric field distribution (dashed lines) as they are at the time of switching turn-off of a resistance load (10.6 μs) and the boundary line of a depletion region (dotted-and-dashed line) within the dielectric-isolated horizontal IGBT  350  according to the embodiment 3, which drawing corresponds to the cross sectional view in  FIG. 20 . 
         [0123]    One can tell from  FIG. 21  that in the dielectric-isolated structure including the buried insulation film, the current flows through the n −  layer which is right above the buried oxide film. 
         [0124]    Noting this, the p −  layer may be disposed in a lower section of the p-type base layer, to thereby permit the hole current arriving at the n −  layer on the emitter side easily flow into a section developing a high electric field at the bottom of the p −  layer. 
         [0125]      FIG. 22  of the IGBT  350  shows that the hole current flowing immediately below the n-type emitter layer is less than in the IGBT  250  ( FIG. 21 ). In consequence, a parasitic thyristor will not easily operate in the IGBT  350  unlike in the IGBT  250 , which improves the latch-up tolerance. 
         [0126]    Further, the width of the p −  layer is narrower than the p-type base layer in the IGBT  350 . Due to this, the hole current arriving at the n −  layer on the emitter side flows approximately upward within the p −  layer to the emitter electrode, which shortens the fall time (tf) than in the IGBT  250  which does not include the p −  layer. 
         [0127]    As described above, in the IGBTs  300  and  350  according to this embodiment, the p −  layer formed in the lower section of the p-type base layer prevents latching-up of a parasitic thyristor and shortens the fall time (tf). This effect is remarkable particularly in the case of the IGBT  350  including the buried insulation film in particular. 
         [0128]    The structure that the p −  layer is formed in the lower section of the p-type base layer may be applied to a conventional IGBT to achieve a similar effect. 
       Embodiment 4 
       [0129]      FIG. 23  is a top view of a part of a horizontal n-channel IGBT according to the embodiment 4 of the present invention generally denoted at  400 , showing the n-type emitter (n + ) layer  6  formed within the p-type base layer  5  (a connection region with an emitter electrode (emitter contact region)). 
         [0130]    As shown in  FIG. 23 , the n-type emitter layer  6  includes multiple outwardly protruding projections (convex areas)  16  in the IGBT  400 . As shown in  FIG. 23 , the relationship W 1 &gt;W 2  holds between the width of the projections  16  (W 2 ) and the gap between the neighboring projections  16  (W 1 ). The structure is otherwise the same as that of the IGBT  100  described earlier. 
         [0131]      FIG. 24  is a cross sectional view of  FIG. 23  taken along the direction C-C, and  FIG. 25  is a cross sectional view of  FIG. 23  taken along the direction D-D.  FIGS. 24 and 25  also show the flows of holes as they are upon turning off of the IGBT and during the steady ON-state. 
         [0132]    The width of the n-type emitter layer in the cross sectional view in  FIG. 24  is approximately equal to the width of the n-type emitter layer of the IGBT  100  shown in  FIG. 1 . Meanwhile, the width of the n-type emitter layer in the cross sectional view in  FIG. 25  is narrower than the width of the n-type emitter layer  6  of the IGBT  100  shown in  FIG. 1 . 
         [0133]    In  FIG. 25 , since the width of the n-type emitter (n + ) is narrow, the width of the p-type base layer right under the n-type emitter layer of a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer is narrow, and the base resistance of the p-type base region is low. This suppresses an operation of the parasitic npn bipolar transistor and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. 
         [0134]    Thus, at the time of turning off or during the steady ON-state of the IGBT  400  according to the embodiment 4, the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
         [0135]    Further, in the IGBT  400 , the projections  16  are portions of the n-type emitter layer  6  and the both are connected electrically with each other, and hence, use of this structure will not reduce the channel width than in the IGBT  100 . For this reason, the collector-emitter current (I CE ) characteristic upon application of the collector-emitter voltage (V CE ) in a condition that the constant gate-emitter voltage (V GE ) is applied is excellent as in the IGBT  100 . 
         [0136]    In addition, the n-type emitter layer has the projections and their sizes satisfy the relationship W 1 &gt;W 2  ( FIG. 23 ) in the IGBT  400 . In short, with a gate electrode leading wire disposed between two projections as shown in  FIG. 26  makes it unnecessary to sever the n-type emitter layer which intersects gate electrode leading wires as in the conventional structure. This permits disposing gate electrode leading wires without reducing the channel width. 
         [0137]    Hence, the collector-emitter current (I CE ) characteristic upon application of the collector-emitter voltage (V CE ) in a condition that the constant gate-emitter voltage (V GE ) is applied is excellent 
         [0138]    The n-type emitter layer having such a structure is applicable also to a conventional IGBT. 
         [0139]      FIG. 27  is a top view which shows the arrangement of the p-type emitter layer (denoted at the symbol “p + ” in  FIGS. 24 and 25 ) vis-à-vis the n-type emitter layer in the horizontal n-channel IGBT shown in  FIG. 23 . 
         [0140]    As shown in  FIG. 27A , the p-type emitter layer may be shaped like a stripe which surrounds the n-type emitter layer. 
         [0141]    Alternatively, as shown in  FIGS. 27A and 27B , the p-type emitter layer may be shaped like a ring which is along the n-type emitter layer. Shown in  FIG. 27  is the shape in which there is a predetermined gap between the p-type emitter layer and the n-type emitter layer, while shown in  FIG. 27C  is the shape in which the p-type emitter layer and the n-type emitter layer contact each other. 
         [0142]    Further, alternatively, as shown in  FIG. 27D , the p-type emitter layer may be discontinuous along the n-type emitter layer. 
         [0143]    Such a configuration of the p-type emitter layer is applicable also to the p-type emitter layers of the other embodiments. 
       Embodiment 5 
       [0144]      FIG. 28  is a top view of a part of a horizontal n-channel IGBT according to the embodiment 5 of the present invention generally denoted at  500 , showing a connection region (emitter contact region) between the n-type emitter layer and the emitter electrode.  FIG. 29  is a cross sectional view of the IGBT  500  shown in  FIG. 28  taken along the direction E-E. 
         [0145]    As shown in  FIG. 28 , in the IGBT  500  according to the embodiment 5, the projections of the n-type emitter layer have T-shaped tips in addition to what the IGBT  400  ( FIG. 25 ) includes, which increases the size of the area where the n-type emitter layer and emitter electrode wires contact each other. The structure is otherwise the same as the IGBT  400 . 
         [0146]    The n-type emitter layer newly disposed in the IGBT  500  is formed to have a narrow width (the length along the horizontal direction in  FIG. 29 ) as shown in  FIG. 29 . This lowers the base resistance in the p-type base region right under the n-type emitter layer in a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer. This suppresses an operation of the parasitic npn bipolar transistor and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT  500 , the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
         [0147]    Further, in the IGBT  500 , since the area where the n-type emitter layer and emitter electrode wires contact each other expands, the contact resistance between the n-type emitter layer and the emitter electrode wires is small. 
         [0148]    As described above, in the horizontal n-channel IGBT  500  according to the embodiment 5, the projections of the n-type emitter layer are T-shaped unlike in the IGBT according to the embodiment 4, which increases the size of the area where the n-type emitter layer and the emitter electrode wires contact each other and reduces the contact resistance between the n-type emitter layer and the emitter electrode wires. The result of this is an improved collector-emitter current (I CE ) characteristic upon application of the collector-emitter voltage (V CE ) in a condition that the constant gate-emitter voltage (V GE ) is applied. 
         [0149]    The n-type emitter layer having this structure is applicable also to a conventional IGBT. 
       Embodiment 6 
       [0150]      FIG. 30  is a top view is an IGBT generally denoted at  600  which is a combination of two IGBTs  150  according to the embodiment 1.  FIG. 31  is a top view is an IGBT generally denoted at  650  which is a combination of two IGBTs  700 .  FIG. 32  is a cross sectional view of the IGBT  600  of  FIG. 30  taken along the direction F-F. In  FIGS. 30 and 31 , the same reference symbols as those used in  FIGS. 2 and 3  denote the same or corresponding portions. 
         [0151]    As denoted at the shade lines in  FIGS. 30 and 31 , in the IGBTs  600  and  650  according to the embodiment 6, there are p-type emitter layers  17  disposed in areas between a common contact line to adjacent two unit IGBTs and two IGBTs and areas enclosed by three adjacent unit IGBTs, which expands the area sizes of the contact between the p-type emitter layers and the emitter electrode wires. 
         [0152]    In this structure, the p-type emitter layers  7  and  17  are relatively wider than the n-type emitter layer  6 . This reduces the contact resistance between the p-type emitter layers  7  and  17  and emitter wires, and ensures a smooth flow of holes to the contact region, where the p-type emitter (p + ) layers and the emitter wires (emitter electrode) contact, without becoming stagnant immediately below the n-type emitter layer as shown in  FIG. 32 . An indirect reason behind this is the reduced base resistance at the p-type base region right under the n-type emitter layer. 
         [0153]    This suppresses an operation of a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT  600 , the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
       Embodiment 7 
       [0154]      FIG. 33  is a cross sectional view of a horizontal n-channel IGBT according to the embodiment 7 of the present invention generally denoted at  1100 , which is illustration viewed from the same direction as the A-A direction in  FIG. 1 . In  FIG. 33 , the same reference symbols as those appearing in  FIG. 19  denote the same or corresponding portions. 
         [0155]    As compared to the IGBT  300  according to the embodiment 3 ( FIG. 19 ), the IGBT  1100  according to the embodiment 7 ( FIG. 33 ) has a structure which does not include the p-type emitter layers  7 , except for which the structure is the same as that of the IGBT  300 . In the IGBT  1100 , there is no p-type emitter, but instead the p-type base layer  5  has a structure which serves also as a p-type emitter. 
         [0156]      FIG. 34  is a cross sectional view of other horizontal n-channel IGBT according to the embodiment 7 of the present invention generally denoted at  1150 , which is illustration viewed from the same direction as the A-A direction in  FIG. 1 . In  FIG. 34 , the same reference symbols as those appearing in  FIG. 20  denote the same or corresponding portions. The structure of the IGBT  1150  is the same that of the IGBT  1100  as it is modified to additionally include the buried insulation film  20 . 
         [0157]    As compared to the IGBT  350  according to the embodiment 3 ( FIG. 20 ), the IGBT  1150  according to the embodiment 7 ( FIG. 34 ) has the same structure as that of the IGBT  350  except for omission of the p-type emitter layers  7 . In the IGBT  1150  as well, there is no p-type emitter, but instead the p-type base layer  5  serves also as a p-type emitter. 
         [0158]    In the IGBTs  1100  and  1150  according to the embodiment 7, the p −  layer disposed in a lower section of the p-type base layer prevents latching-up of a parasitic thyristor and shortens the fall time (tf). This effect is remarkable particularly in the case of the IGBT  1150  including the buried insulation film in particular. 
         [0159]    The structure is simple as the p-type base layer  5  serves also as a p-type emitter, which in turn simplifies the manufacturing process. 
       Embodiment 8 
       [0160]      FIG. 35  is a top view of a part of a horizontal n-channel IGBT according to the embodiment 8 of the present invention generally denoted at  1200 , showing the n-type emitter (n + ) layer  6  formed within the p-type base layer  5  (a connection region with an emitter electrode (emitter contact region)). 
         [0161]    As in the IGBT  400  shown in  FIG. 23 , the n-type emitter layer  6  includes multiple outwardly protruding projections (convex areas)  16  in the IGBT  1200 , and the relationship W 1 &gt;W 2  holds between the width of the projections  16  (W 2 ) and the gap between the neighboring projections  16  (W 1 ). 
         [0162]      FIG. 36  is a cross sectional view of  FIG. 35  taken along the direction C-C, and  FIG. 37  is a cross sectional view of  FIG. 35  taken along the direction D-D. 
         [0163]    As compared to the IGBT  400  according to the embodiment 4 described above, the IGBT  1200  according to the embodiment 8 ( FIGS. 36 and 37 ) has a structure which does not include the p-type emitter layers, except for which the structure is the same as that of the IGBT  400 . In the IGBT  1200 , there is no p-type emitter, but instead the p-type base layer  5  has a structure which serves also as a p-type emitter. 
         [0164]    Having such a structure, the IGBT  1200  according to the embodiment 8 achieves an approximately similar effect to that according to the IGBT  400  described above. In addition, the structure is simple as the p-type base layer  5  serves also as a p-type emitter, which in turn simplifies the manufacturing process. 
         [0165]    In other words, since the width of the n-type emitter (n+) is narrow in  FIG. 37 , the width of the p-type base layer right under the n-type emitter layer of a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer is narrow, and the base resistance of the p-type base region is low. This suppresses an operation of the parasitic npn bipolar transistor and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. 
         [0166]    Thus, at the time of turning off or during the steady ON-state of the IGBT  1200  according to the embodiment 8, the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
       Embodiment 9 
       [0167]      FIG. 38  is a top view of a part of a horizontal n-channel IGBT according to the embodiment 9 of the present invention generally denoted at  1300 , showing a connection region (emitter contact region) between the n-type emitter layer and the emitter electrode.  FIG. 39  is a cross sectional view of the IGBT  1300  shown in  FIG. 38  taken along the direction E-E. 
         [0168]    As compared to the IGBT  500  according to the embodiment 5 ( FIGS. 28 and 29 ), the IGBT  1300  according to the embodiment 9 ( FIGS. 38 and 39 ) has a structure which does not include the p-type emitter layers, except for which the structure is the same as that of the IGBT  500 . In the IGBT  1300 , there is no p-type emitter, but instead the p-type base layer  5  has a structure which serves also as a p-type emitter. 
         [0169]    Having such a structure, the IGBT  1300  according to the embodiment 9 achieves an approximately similar effect to that according to the IGBT  500  described above. In addition, the structure is simple as the p-type base layer  5  serves also as a p-type emitter, which in turn simplifies the manufacturing process. 
         [0170]    In other words, in the IGBT  1300 , since the projections of the n-type emitter layer have T-shaped tips in addition to what the IGBT  400  according to the embodiment 4 includes, which increases the size of the area where the n-type emitter layer and emitter electrode wires contact each other and reduces the contact resistance between the n-type emitter layer and the emitter electrode wires. The result of this is an improved collector-emitter current (I CE ) characteristic upon application of the collector-emitter voltage (V CE ) in a condition that the constant gate-emitter voltage (V GE ) is applied. 
       Embodiment 10 
       [0171]      FIG. 40  is a top view of a part of a horizontal n-channel IGBT according to the embodiment 10 of the present invention generally denoted at  1400 , in which the same reference symbols as those appearing in  FIG. 30  denote the same or corresponding portions.  FIGS. 41 through 43  are enlarged views of the portion denoted at A in  FIG. 40 . 
         [0172]    In the IGBT  1400  according to the embodiment 10, there are the p-type emitter layers  17  disposed in areas between a common contact line to adjacent two unit IGBTs and two IGBTs, which expands the area of the contact between the p-type emitter layers and the emitter electrode wires (emitter contact region) ( FIGS. 41 through 43  show the emitter contact region.). This brings about a similar effect to that promised by the IGBT  650  according to the embodiment 6 described earlier ( FIG. 31 ). 
         [0173]    In short, it is possible to suppress an operation of a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer and to prevent latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT  1400 , the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
         [0174]    As shown in  FIGS. 40 and 41 , the n-type emitter layer may be disposed discontinuously along the p-type base layer  5  in the IGBT  1400 . Alternatively, the n-type emitter layer  6  may be disposed in an endless shape although not shown. 
         [0175]    Further alternatively, the n-type emitter layer  6  may have an endless-shape structure in which multiple outwardly-protruding projections (convex areas) are formed in the IGBT  1400 , as shown in  FIG. 42 . 
         [0176]    Yet another alternative is to use a structure without any p-type emitter layer  7  in the structure which is shown in  FIG. 42 , as shown in  FIG. 43 . 
         [0177]    The p-type emitter layers  17  of the IGBT  1400  according to this embodiment can be formed regardless of the shape of the n-type emitter layer  6  or whether there is the p-type emitter layers  7 , thereby improving the latch-up tolerance of a parasitic thyristor at the time of turning off or during the steady ON-state of the IGBT  1400 , 
         [0178]      FIG. 44  is a top view of other horizontal n-channel IGBT according to the embodiment 10 of the present invention generally denoted at  1500 , in which the same reference symbols as those appearing in  FIG. 30  denote the same or corresponding portions.  FIGS. 45 through 47  are enlarged views of the portion denoted at B in  FIG. 44 . 
         [0179]    In the IGBT  1500 , there are the p-type emitter layers disposed in areas between a common contact line to adjacent two unit IGBTs and two IGBTs and areas enclosed by adjacent three unit IGBTs, which expands the area of the contact between the p-type emitter layers and the emitter electrode wires (emitter contact region) ( FIGS. 44 through 47  show the emitter contact region.). This brings about a similar effect to that promised by the IGBT  600  according to the embodiment 6 described earlier ( FIG. 30 ). 
         [0180]    In short, it is possible to suppress an operation of a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer and to prevent latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT  1500 , the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
         [0181]    As shown in  FIGS. 44 and 45 , the n-type emitter layer may be disposed discontinuously along the p-type base layer  5  in the IGBT  1500 . Alternatively, the n-type emitter layer  6  may be disposed in an endless shape although not shown. 
         [0182]    Further alternatively, the n-type emitter layer  6  may have an endless-shape structure in which multiple outwardly-protruding projections (convex areas) are formed in the IGBT  1400 , as shown in  FIG. 46 . 
         [0183]    Yet another alternative is to use a structure without any p-type emitter layer  7  in the structure which is shown in  FIG. 46 , as shown in  FIG. 47 . 
         [0184]    In this structure, the p-type emitter layers  7  and  17  are relatively wider than the n-type emitter layer  6 . This reduces the contact resistance between the p-type emitter layers  7  and  17  and emitter wires, and ensures a smooth flow of holes to the contact region, where the p-type emitter (p + ) layers and the emitter wires (emitter electrode) contact, without becoming stagnant immediately below the n-type emitter layer as shown in  FIG. 48  (the cross sectional view of  FIG. 46  taken along the direction H-H). An indirect reason behind this is the reduced base resistance at the p-type base region right under the n-type emitter layer. 
         [0185]    This suppresses an operation of a parasitic npn bipolar transistor formed by the n −  layer/the p-type base layer/the n-type emitter layer and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n −  layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT  1500 , the latch-up tolerance of a parasitic thyristor improves in the IGBT. 
         [0186]    Although the embodiments 1 through 10 are directed to horizontal n-channel IGBTs, the present invention is applicable also to a horizontal p-channel IGBT in which case the p-type and the n-type appearing in the description above should be replaced with each other. 
         [0187]    The present invention is further applicable to a horizontal MOSFET, a horizontal device using other MOS gate structure or the like.

Technology Category: 5