Patent Document

FIELD 
       [0001]    Embodiments of the present disclosure relate generally to the field of circuits, and more particularly to a voltage regulator circuit. 
       BACKGROUND 
       [0002]    A radio frequency (RF) power amplifier (PA) is a component of an RF front-end module (FEM) that provides up-converted signal transmission in wireless telecommunications by amplifying a radio signal into an antenna. Transistors within an RF PA are typically biased by supplying an unregulated battery voltage to the FEM. In some instances, a supplemental regulated voltage source can be made available external to the FEM. However, this increases the overall system cost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
           [0004]      FIG. 1  illustrates a front-end module in accordance with some embodiments. 
           [0005]      FIG. 2  illustrates an enabler of a voltage regulator in accordance with some embodiments. 
           [0006]      FIG. 3  illustrates a generator of a voltage regulator in accordance with some embodiments. 
           [0007]      FIG. 4  illustrates a conveyor of a voltage regulator in accordance with some embodiments. 
           [0008]      FIG. 5  illustrates a graph plotting regulated voltage versus ambient temperature for a number of different supply voltages in accordance with various embodiments. 
           [0009]      FIG. 6  illustrates a graph plotting regulated voltage versus supply voltage for a number of different ambient temperatures in accordance with various embodiments. 
           [0010]      FIG. 7  illustrates a wireless device in accordance with some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific devices and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments. 
         [0012]    Further, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. 
         [0013]    The phrase “in one embodiment” is used repeatedly. The phrase generally does not refer to the same embodiment; however, it may. The terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise. 
         [0014]    In providing some clarifying context to language that may be used in connection with various embodiments, the phrases “A/B” and “A and/or B” mean (A), (B), or (A and B); and the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). 
         [0015]    The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other. 
         [0016]    Certain components, e.g., transistors, may be shown or described in conventions typically associated with particular materials, structures, polarities, etc. However, unless noted otherwise, other materials, structures, polarities, etc. may be used in other embodiments of the present disclosure with appropriate modifications being made to the implementing device/system. With particular reference to transistors, unless otherwise noted, a transistor may be made with any type of material, e.g., germanium, silicon, gallium arsenide, aluminum gallium arsenide, silicon carbide, etc.; any type of structure, e.g., bipolar junction transistor (BJT), junction gate field effect transistor (JFET), metal-oxide semiconductor FET (MOSFET), heterojunction bipolar transistor (HBT), insulated-gate bipolar transistor (IGBT), etc.; and/or any type of polarity, e.g., N-channel, P-channel, NPN, PNP, etc. Furthermore, in some embodiments, suitable transistor-like technologies may used in place of transistors. 
         [0017]      FIG. 1  illustrates a front-end module  100  (FEM) having a voltage regulator  102  integrated with a radio frequency (RF) power amplifier (PA)  104  (hereinafter simply “PA  104 ”) in a substrate  108  in accordance with some embodiments. The voltage regulator  102  may be coupled with a bias circuit  112 , to provide the bias circuit  112  with a regulated voltage (V REG ) sufficient to support proper biasing of the PA  104 . V REG  may be a stable voltage that is largely insensitive to ambient temperature and supply voltage variations. Integrating the voltage regulator  102 , the bias circuit  112 , and the PA  104  in the substrate  108  may facilitate the provision of a stable bias control while reducing costs and size constraints commonly associated with external bias controls. 
         [0018]    While the embodiments described herein discuss the voltage regulator  102  providing V REG  to the bias circuit  112  associated with the PA  104 , in other embodiments the voltage regulator  102  may provide V REG  to additional/alternative circuits integrated in the substrate  108 . Furthermore, in other embodiments, the bias circuit  112  may bias additional/alternative circuits integrated in the substrate  108 . These other circuits could include, but are not limited to, a power detector and/or a temperature sensor. 
         [0019]    The voltage regulator  102  may have an enabler  116 , a generator  120 , and a conveyor  124  coupled with each other at least as shown. The enabler  116  may be configured to alternatively provide and withhold a switched supply voltage (swV cc ) to respectively enable and disable the voltage regulator  102 . When enabled, the enabler  116  may provide swV cc  to the generator  120  and/or conveyor  124 . 
         [0020]    The generator  120 , being provided with swV cc , may generate a reference voltage (V REF ) having a set of desired characteristics. For example, V REF  may be sufficiently stable and relatively insensitive to variations in ambient temperature and/or supply voltage. The generator  120  may provide V REF  to the conveyor  124 . 
         [0021]    The conveyor  124  may be configured to scale V REF  to V REG . While V REG  may be at a level that is higher (or lower) than V REF , it may share V REF &#39;s set of desired characteristics.  FIGS. 2-4  will describe the function and components of the various blocks of the voltage regulator  102  in additional detail in accordance with some embodiments. 
         [0022]      FIG. 2  illustrates the enabler  116  in accordance with some embodiments. The enabler  116  may include a number of components, including enhancement/depletion (e/d) pseuodomorphic heterostructure field effect transistors (pHEMTs), arranged in a manner to alternately enable and disable the voltage regulator  102 . The enabler  116  may allow provision of V REG  to the bias circuit  112  when the voltage regulator  102  is enabled, and may reduce direct current (DC) leakage current when the voltage regulator  102  is disabled. 
         [0023]    The enabler  116  may include a supply port  204  configured to admit a supply voltage (V cc ). The admitted V cc  may be provided to power terminals of inverters  208 ,  212 , and  216  and also to a drain terminal of a transistor  220 . The enabler  116  may also include an enable port  224  configured to admit an enable signal (EN) from an external component/device such as, but not limited to, a controller. As used herein, an “external device/component” is a device/component that is not integrated in the substrate  108 . 
         [0024]    The admitted EN may be buffered at buffer  228  and then provided to the inverters  208 ,  212 , and  216 . When the EN is at a high logic state, in one example, the inverter  216  may control a gate of transistor  220  to admit a switched supply voltage (swV cc ) to a high-rail output port  232 ; and the inverter  212  may control a gate of transistor  236  to admit a switched system ground (swGND) to a low-rail output port  240 . When the EN is at a low logic state, in this example, both the high-rail output port  232  and the low-rail output port  240  may float.  FIG. 3  illustrates the generator  120  in accordance with various embodiments. The generator  120  may have a FET portion, e.g., a PHEMT portion  304 , and a heterojunction bipolar transistor (HBT) portion  308  that are configured to cooperatively generate a temperature and/or supply voltage compensated V REF  as will be described. Generally, the PHEMT portion  304  may provide a stable bias current to the HBT portion  308 , which may serve as a band-gap reference-voltage generator. 
         [0025]    The generator  120 , having both the PHEMT portion  304  and the HBT portion  308  in the substrate  108 , may be referred to as a BiHEMT component. The substrate  108  may include gallium arsenide (GaAs) to accommodate BiHEMT components, such as the generator  120 . 
         [0026]    The PHEMT portion  304  may include a high-rail input port  312  to admit swV cc  to the generator  120 . Drain terminals of a transistor  316  and a gap current source (GCS) transistor  320  may be coupled with the high-rail input port  312 . 
         [0027]    A source terminal of the GCS transistor  320  may be coupled with a collector of a bipolar junction transistor (BJT)  328  of the HBT portion  308 . The GCS transistor  320  may source a current (I 3 ) to the BJT  328 . I 3  may be proportional to a size of a physical gap within a gate of the GCS transistor  320 . Such GCS transistors may be capable of functioning as stable and precise low-current sources. 
         [0028]    The source terminal of the GCS transistor  320  may also be coupled with the transistor  316  in a manner to set an appropriate potential at a gate terminal of the transistor  316 , which may source a current (I 1 ) to a proportional-to-absolute temperature (PTAT) block  324  of the HBT portion  308 . 
         [0029]    The PTAT block  324  may include resistors  332 ,  336 , and  340  and BJTs  344  and  348 . The PTAT block  324  may be used to generate V REF  at an output port  352  by scaling a base-emitter voltage of BJT  328 , V BE3 . 
         [0030]    The PTAT block  324  may act as a current mirror to set current  12  approximately equal to U 1 . Thus, a product of I 1  and R 1  is approximately equal to a product of I 2  and R 2 . The base emitter voltage of BJT  344 , V BE1 , may then be given by: 
         [0000]        V   BE1   =V   BE2   +I   2   *R   3 ,   Equation 1 
         [0031]    where V BE2  is the base-emitter voltage of BJT  348  and R 3  is the resistance of the resistor  340 . The delta base-emitter voltage, ΔV BE , may be given by: 
         [0000]      Δ V   BE   =V   BE1   −V   BE2   =I   2   *R   3 ,   Equation 2 
         [0032]    and 
         [0000]    
       
         
           
             
               
                 
                   
                     Δ 
                      
                     
                         
                     
                      
                     
                       V 
                       BE 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           T 
                         
                         * 
                         
                           ln 
                            
                           
                             ( 
                             
                               
                                 I 
                                 1 
                               
                               
                                 I 
                                 
                                   S 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                             
                             ) 
                           
                         
                       
                       - 
                       
                         
                           V 
                           T 
                         
                         * 
                         
                           ln 
                            
                           
                             ( 
                             
                               
                                 I 
                                 2 
                               
                               
                                 I 
                                 
                                   S 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                     = 
                     
                       
                         V 
                         T 
                       
                       * 
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               
                                 I 
                                 1 
                               
                               * 
                               
                                 I 
                                 
                                   S 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             
                               
                                 I 
                                 2 
                               
                               * 
                               
                                 I 
                                 
                                   S 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   3 
                 
               
             
           
         
       
     
         [0033]    where V T  is a thermal potential that is the product of Boltmann&#39;s constant and the absolute temperature divided by the electronic charge; I S1  is a saturation current of the BJT  344 , and I S2  is a saturation current of the BJT  348 . 
         [0034]    Given the assumption that V BE1≈V   BE3 , which may be valid due to both emitter terminals being coupled with swGND and similar potentials existing at both collector terminals, results in: 
         [0000]      I 1 *R 1 =I 2 *R 2 .   Equation 4 
         [0035]    Hence, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       2 
                     
                     = 
                     
                       
                         
                           Δ 
                            
                           
                               
                           
                            
                           
                             V 
                             BE 
                           
                         
                         
                           R 
                           3 
                         
                       
                       = 
                       
                         
                           
                             
                               V 
                               T 
                             
                             
                               R 
                               3 
                             
                           
                           * 
                           
                             ln 
                              
                             
                               ( 
                               
                                 
                                   
                                     I 
                                     1 
                                   
                                   * 
                                   
                                     I 
                                     
                                       S 
                                        
                                       
                                           
                                       
                                        
                                       2 
                                     
                                   
                                 
                                 
                                   
                                     I 
                                     2 
                                   
                                   * 
                                   
                                     I 
                                     
                                       S 
                                        
                                       
                                           
                                       
                                        
                                       1 
                                     
                                   
                                 
                               
                               ) 
                             
                           
                         
                         = 
                         
                           
                             
                               V 
                               T 
                             
                             
                               R 
                               3 
                             
                           
                           * 
                           
                             ln 
                              
                             
                               ( 
                               
                                 
                                   
                                     R 
                                     2 
                                   
                                   * 
                                   
                                     I 
                                     
                                       S 
                                        
                                       
                                           
                                       
                                        
                                       2 
                                     
                                   
                                 
                                 
                                   
                                     R 
                                     1 
                                   
                                   * 
                                   
                                     I 
                                     
                                       S 
                                        
                                       
                                           
                                       
                                        
                                       1 
                                     
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   ; 
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   5 
                 
               
             
           
         
       
     
         [0036]    and V REF  may be given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     REF 
                   
                   = 
                   
                     
                       
                         
                           I 
                           2 
                         
                         * 
                         
                           R 
                           2 
                         
                       
                       + 
                       
                         V 
                         
                           BE 
                            
                           
                               
                           
                            
                           3 
                         
                       
                     
                     = 
                     
                       
                         
                           
                             R 
                             2 
                           
                           
                             R 
                             3 
                           
                         
                          
                         
                           V 
                           T 
                         
                         * 
                         
                           ln 
                            
                           
                             ( 
                             
                               
                                 
                                   R 
                                   2 
                                 
                                 * 
                                 
                                   I 
                                   
                                     S 
                                      
                                     
                                         
                                     
                                      
                                     2 
                                   
                                 
                               
                               
                                 
                                   R 
                                   1 
                                 
                                 * 
                                 
                                   I 
                                   
                                     S 
                                      
                                     
                                         
                                     
                                      
                                     1 
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                       + 
                       
                         
                           V 
                           
                             BE 
                              
                             
                                 
                             
                              
                             3 
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   6 
                 
               
             
           
         
       
     
         [0037]    Equation 6 reduces to: 
         [0000]        V   REF   =kV   T   +V   BE3   Equation 7 
         [0038]    where 
         [0000]    
       
         
           
             
               
                 
                   k 
                   = 
                   
                     
                       
                         R 
                         2 
                       
                       
                         R 
                         3 
                       
                     
                     * 
                     
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               
                                 R 
                                 2 
                               
                               * 
                               
                                 I 
                                 
                                   S 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             
                               
                                 R 
                                 1 
                               
                               * 
                               
                                 I 
                                 
                                   S 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                             
                           
                           ) 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   8 
                 
               
             
           
         
       
     
         [0039]    The k factor, as can be seen by Equation 8, is defined as a product of a resistance ratio and a logarithmic ratio. The different ratios are comprised of various resistances and saturation currents of the PTAT block  324 . Utilizing the ratios of the resistance/saturation currents, reduces the dependence on the size of the components, which may vary slightly over process. This may, in turn, reduce sensitivity of V REF  to variations in swV cc . 
         [0040]    It may be noted that a very high repeatability rate may be achieved given the behavior of V REF  being based, at least in part, on ratios of resistances/saturation currents. This may be due, at least in part, to tight process controls that relate to the manufacture of the corresponding resistors and transistors. However, a more prominent variation in V REF  may occur from process variations of current sources based on PHEMT devices. The variations in current sources may be translated into the V REF  through the log function of Equation 3. Accordingly, GCS transistors, e.g., GCS transistor  320 , with their associated precision at low current levels, are especially suited for use as current sources in various embodiments. Other embodiments may utilize other PHEMT current sources that are enabled through the use of BiHEMT processes. 
         [0041]    The voltage component of V REF  that is provided by the PTAT block  324 , i.e., V T , may have a positive temperature coefficient, while the voltage component of V REF  provided by the BJT  328 , i.e., V BE3 , may have a negative temperature coefficient. This complementary temperature relationship may provide a temperature-compensated V REF  that is less sensitive to variations in ambient temperature. 
         [0042]      FIG. 4  illustrates the conveyor  124  in accordance with various embodiments. The conveyor  124  may be a voltage-to-voltage conveyor that scales V REF , with its desired insensitivity characteristics, to a magnitude that provides the bias circuit  112  with sufficient current driving capacity. The conveyor  124  shown in  FIG. 4  may be structured with e/d PHEMT devices configured to receive V REF  at an input port  404 , and to output V REG  at an output port  408 . The conveyor  124  may include transistors  412  and  416  arranged as a differential pair. The differential pair may have a very high gain, at low frequencies, and operate to set point B equal, in magnitude, to point A. Point A may be considered a positive input to the differential pair, and point B may be considered a negative input to the differential pair. 
         [0043]    The conveyor  124  may have a supply port  418  coupled to a drain terminal of the transistor  412  and coupled to a GCS transistor  420 . The GCS transistor  420  may source a current into a drain terminal of the transistor  416  in order to set an operating point of the differential pair. The conveyor  124  may also have GCS transistors  424  and  428  that are configured to bias the differential pair by pulling equal amounts of current from transistors  412  and  416 . The GCS transistors  420 ,  424 , and  428 , similar to GCS transistor  320 , may be stable low-current sources. 
         [0044]    The conveyor  124  may include a transistor  432  with its drain terminal coupled to supply port  436 . The transistor  432  may source a relatively small amount of current into resistors  440  and  444 , which provide for voltage division at the negative input to the differential pair, i.e., point B. The relationship between V REG  and V REF  may be defined by the following equation. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         REG 
                       
                       
                         
                           R 
                           1 
                         
                         + 
                         
                           R 
                           2 
                         
                       
                     
                     = 
                     
                       
                         V 
                         REF 
                       
                       
                         R 
                         2 
                       
                     
                   
                   , 
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   9 
                 
               
             
           
         
       
     
         [0045]    where R 1  is the resistance of resistor  440  and R 2  is the resistance of resistor  444 . Equation 9 reduces to: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     REG 
                   
                   = 
                   
                     
                       V 
                       REF 
                     
                     * 
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               R 
                               1 
                             
                             
                               R 
                               2 
                             
                           
                         
                         ) 
                       
                       . 
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   10 
                 
               
             
           
         
       
     
         [0046]    Thus, V REG  may be proportional to a ratio of resistors  440  and  444 . 
         [0047]    The transistor  432  may be controlled by having its gate terminal coupled with a drain terminal of transistor  416  through a resistor  448 . A non-inverting output (OUT+) may provide feedback to point B that is equal to V REF . 
         [0048]      FIGS. 5 and 6  provide various results from a voltage regulator designed in accordance with various embodiments. In particular,  FIG. 5  illustrates a graph  500  plotting V REG  versus ambient temperature for a number of different supply voltages; and  FIG. 6  illustrates a graph  600  plotting V REG  versus supply voltage for a number of different ambient temperatures. A design goal of these embodiments may be to achieve the largest possible V REG . Due to a small voltage overhead used for operation of the voltage regulator, ˜0.1 V, some variation of the V REG  may be observed with respect to the supply voltage 3.0 V&lt;V cc &lt;5.0 V. If a lower V REG  were desired, e.g., 2.8 V at a V cc  of 3.0 V or greater, a tighter control of the V REG  may be achieved. As can be seen in  FIGS. 5 and 6 , a very low temperature variation is observed in V REG , which may indicate a desired operation of the voltage regulator. 
         [0049]      FIG. 7  illustrates a wireless transmission device  700  in accordance with various embodiments. The wireless transmission device  700  may have an antenna structure  704 , a duplexer  708 , a transmitter  712 , a receiver  716 , transmit/receive (TX/RX) circuitry  720 , a main processor  724 , and a memory  728  coupled with each other at least as shown. The wireless transmission device  700  may also include a power supply  730 , e.g., a battery, coupled with the various components to provide DC power. The transmitter  712 , receiver  716  and duplexer  708  may be collectively referred to as the FEM  732 . 
         [0050]    In various embodiments, the wireless transmission device  700  may be, but is not limited to, a mobile telephone, a paging device, a personal digital assistant, a text-messaging device, a portable computer, a base station, a radar, a satellite communication device, or any other device capable of wirelessly transmitting RF signals. 
         [0051]    The main processor  724  may execute a basic operating system program, stored in the memory  728 , in order to control the overall operation of the wireless transmission device  700 . For example, the main processor  724  may control the reception of signals and the transmission of signals by TX/RX circuitry  720 , receiver  716 , and transmitter  712 . The main processor  724  may be capable of executing other processes and programs resident in the memory  728  and may move data into or out of memory  728 , as desired by an executing process. 
         [0052]    The TX/RX circuitry  720  may receive outgoing data (e.g., voice data, web data, e-mail, signaling data, etc.) from the main processor  724 . The TX/RX circuitry  720  may transmit an RF signal that represents the outgoing data to the transmitter  712 . The transmitter  712  may include a PA  736  to amplify the RF signal for transmission. The amplified RF signal may be forwarded to the duplexer  708  and then to the antenna structure  704  for an over-the-air (OTA) transmission. 
         [0053]    The wireless transmission device  700  may operate under one or more of a number of communication standards and may operate in variety of diverse operational environments. Accordingly, it may be desirable for the FEM  732  to be adaptable to the variety of standards and/or environments. To allow for this adaptable operation, the FEM  732  may include a BiHEMT-based voltage regulator, e.g., VR  740 , that is integrated with a bias circuit (BC)  744 , and the PA  736  as shown. The PA  736 , VR  740 , and BC  744  may be similar to, and substantially interchangeable with, similar named components discussed elsewhere in this disclosure. So equipped, the FEM  732  may provide a regulated voltage source that is sufficient for the BC  744  to source a stable biased current to RF transistors of the PA  736  under dynamic signal operation. Furthermore, the linearity desired from the PA  736  to support a variety of communication standards may benefit from precisely set quiescent current that will facilitate low dynamic gain and phase variation under RF excitation. 
         [0054]    In a manner complementary to the transmission operation, the TX/RX circuitry  720  may receive an incoming OTA signal from the antenna structure  704  through the duplexer  708  and receiver  716 . The TX/RX circuitry  720  may process and send the incoming signal to the main processor  724  for further processing. While the wireless transmission device  700  is shown with transmitting and receiving capabilities, other embodiments may include wireless transmission devices without receiving capabilities. 
         [0055]    In various embodiments, the antenna structure  704  may include one or more directional and/or omnidirectional antennas, including, e.g., a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a microstrip antenna or any other type of antenna suitable for OTA transmission/reception of RF signals. 
         [0056]    Although the present disclosure has been described in terms of the above-illustrated embodiments, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. Those with skill in the art will readily appreciate that the teachings of the present disclosure may be implemented in a wide variety of embodiments. This description is intended to be regarded as illustrative instead of restrictive.

Technology Category: 5