Patent Document

RELATED APPLICATION  
       [0001]     The present application is a continuation of International Application No. PCT/FR02/04116 filed on Nov. 29, 2002, the entire disclosure of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to a decoding and error correcting method applicable to a secured code word. The present invention also relates to a decoding and error correcting circuit for transforming a secured code word into a corrected decoded word.  
       BACKGROUND OF THE INVENTION  
       [0003]     Data security/correction devices are widely used to write data in memories, particularly electrically erasable and programmable memories of the EEPROM or FLASH EEPROM type. Data is secured when saved in the memory by adding security bits, and the data is corrected as a result of the security bits when read.  
         [0004]     Moreover, data is traditionally coded before being saved in a memory when a certain level of confidentiality is required, and the data is decoded when the memory is read. Coding is defined to mean coding a binary word by a scrambling function to obtain a coded word. Therefore, sometimes combining a coding function and a security function in a single device is required to obtain from initial data a secured coded data entry, i.e., a binary word having undergone a double coding and security process.  
         [0005]      FIG. 1  represents in block form a prior art data security/correction device ECC 1 . The device ECC 1  comprises a data security circuit WR 1  and a data correction circuit RD 1 . The circuit WR 1  has one input IN 1  to receive a binary word X 1 , and one output OUT 1  to deliver a secured word X 2 . The circuit RD 1  has one input IN 2  to receive the secured word X 3  having an error E, and one output OUT 2  to deliver a corrected word X 4 .  
         [0006]     The circuit WR 1  comprises a block B 1  that applies a function G to the word X 1 , and delivers the secured word X 2 . The function G is a security bit generation function that can be represented in the form of a matrix of (2 K ) lines and (2 K +J) columns. By representing the binary word X 1  in the form of a vector of 2 K  bits, the secured word X 2  obtained complies with the following relation: 
 
 X   2 = X   1 * G =DATA( X   2 )//CODE( X   2 ). 
 
         [0007]     The symbol * represents a matrix product, // is a symbol for concatenation (i.e., linking together in series or in a chain), DATA(X 2 ) is a first part of the word X 2  comprising 2 K  data bits, and CODE(X 2 ) is a second part of the word X 2  comprising J security bits.  
         [0008]     The function G does not change the data bits of the initial word X 1 , such that the word DATA(X 2 ) comprises data bits equal to those of the initial word X 1 . Therefore, the following can be written: 
 
X 2 =X 1 //CODE(X 2 ). 
 
         [0009]     As an example, it will be assumed that only one bit is to be detected and corrected in a word of eight bits by the Hamming algorithm. According to this algorithm, the number J of security bits must be equal to K+1 to detect and correct only one error bit in a word of 2 K  bits. Therefore, in this example, K=3 and J=K+1=4 and the words X 1 , X 2  are written as described in part 1 of the supplemental information, which follows the detailed description. The function G is a matrix of 2 K  lines and (2 K +K+1) columns, i.e., 8 lines and 12 columns, as described in part  2  of the supplemental information. The matrix G generates 4 security or parity bits p 0 , p 1 , p 2 , p 3  as described in part  3  of the supplemental information.  
         [0010]     It is now assumed that the secured word X 2  is saved in a memory MEM, and that it is then read in that memory. Between the writing of the word and the moment it is read, the word is likely to be altered, which results in the word having an error. Such an error, statistically speaking, is quite frequent with electrically erasable and programmable memories of the EEPROM or FLASH EEPROM type. This is generally due to a defect affecting a floating-gate transistor of a memory cell (for example, a drift of its threshold voltage), or to a connection defect of a bit line or of a word line, etc.  
         [0011]     To distinguish the word read from the initial secured word X 2  that is presumed to be free from any error, the word read in the memory is called X 3  and is considered equal to the sum of the word X 2  and an error E: 
 
 X   3 = X   2 + E  
 
         [0012]     The symbol + is the bit to bit addition without carrying the sum forward, and E is a word of 2 K +J bits representing the error affecting the word X 2 . This error may possibly be zero.  
         [0013]     The word X 3  and the error E can also be written as: 
 
X 3 =DATA(X 3 )//CODE(X 3 ) 
 
E=ERR 1 //ERR 2 . 
 
         [0014]     DATA(X 3 ) is a word comprising 2 K  data bits, CODE(X 3 ) is a word comprising J security bits, ERR 1  is a word representing the error on the data bits formed by the 2 K  first bits of the error E, and ERR 2  is a word representing the error on the security bits formed by the J following bits of the error E. The result is: 
 
DATA( X   3 )=DATA( X   2 )+ERR 1 = X   1 +ERR 1  
 
CODE( X   3 )=CODE( X   2 )+ERR 2 . 
 
         [0015]     The symbol + is the bit to bit addition without carrying the sum forward. For a better understanding, and using the example mentioned above (2 K =8 and J=4), the words E, ERR 1 , ERR 2 , DATA(X 3 ), CODE(X 3 ) are written as mentioned in part  4  of the supplemental information.  
         [0016]     The correction of the word X 3  incorporating the error E (that can be zero) is carried out by the circuit RD 1 . This circuit comprises an error correcting block B 2 , a syndrome or pattern generator block B 3 , and an error vector generator block B 4 .  
         [0017]     The block B 2  has two inputs E 1 , E 2  for receiving 2 K  bits each, and one output for providing 2 K  bits. The input E 1  receives the data bits of the word X 3 , i.e., the word DATA(X 3 ). The input E 2  receives an error vector EV delivered by the block B 4 . The block B 2  delivers a corrected word X 4  that is equal to the initial word X 1  provided that the effective error concerns a number of bits lower than or equal to the maximum number of bits that can be detected and corrected.  
         [0018]     The word X 4  is obtained by the logic combination of the word DATA(X 3 ) and of the vector EV. This logic combination is generally done by the EXCLUSIVE OR function (xor function, symbol ⊕).  
         [0019]     The block B 3  receives the word X 3  at an input, applies a function H to the word X 3 , and delivers a pattern SYN such that: 
 
SYN  32   X   3 * H  
 
SYN=( X   2 + E )* H  
 
SYN=( X   1 * G+E )* H  
 
SYN= X   1 * G*H+E*H  
 
SYN= E*H  
 
 The functions H and G are orthogonal functions and their product G*H is equal to 0. 
 
         [0021]     With the Hamming algorithm, the function H is a matrix of (2 K +K+1) lines and (K+1) columns, orthogonal at G. For a better understanding, such a matrix H is described in part  5  of the supplemental information, in which K=3 and J=4. This matrix H generates a pattern SYN of four bits S 0 , S 1 , S 2 , S 3  allowing one error per word to be detected and corrected. The logic value of the bits S 0  to S 4  is described in part  6  of the supplemental information.  
         [0022]     The pattern SYN is applied to the block B 4  that performs a pattern/vector conversion function EV=f(SYN), and delivers an appropriate vector EV. This pattern/vector conversion function conforms to a predetermined table of correspondence. For a better understanding, a pattern/vector table of correspondence is described in part  7  of the supplemental information, in which K=3 and J=4.  
         [0023]     In theory each error vector EV comprises one part EV 1  and one part EV 2 , and can be written: 
 
EV=EV 1 //EV 2  
 
 EV 1  is an error vector of 2 K  bits representing an error on the data, and EV 2  is an error vector of J bits representing an error on the security bits. In practice, error correcting on the security bits is pointless, and only the error vector EV 1  is delivered by the block B 4  and is applied to the input E 2  of the block B 2 . 
 
         [0025]     The error vector EV is equal to the error E itself when the block B 2  performs the EXCLUSIVE OR function. In fact: 
 
DATA( X   3 )⊕(EV 1 = X   1  
 
 However: 
 
DATA( X   3 )⊕EV 1 = X   1 +ERR 1 ⊕EV 1  
 
 which gives: 
 
ERR 1 ⊕EV 1 =0 
 
 which implies that: 
 
ERR 1 =EV 1  
 
 The symbol + is the bit to bit addition without carrying the sum forward, and ⊕ is the EXCLUSIVE OR function. 
 
         [0030]      FIG. 2  represents a device ECC 2  that differs from the device ECC 1  by the fact that it comprises, in addition, coding and decoding means, which forms a data coding/decoding and security/correction device.  
         [0031]     The device ECC 2  comprises a data coding and security circuit WR 2 , and a data decoding and correction circuit RD 2 . The circuit WR 2  has one input IN 1  to receive a binary word X 0 , and one output OUT 1  to deliver a secured code word X 2 . The circuit RD 2  has one input IN 2  to receive a secured code word X 3  having an error E (that can be zero), and one output OUT 2  to deliver a corrected decoded word X 5 .  
         [0032]     The circuit WR 2  comprises in series one block B 0  and the block B 1  described above. The input of the block B 0  receives at one input the word X 0 , applies a coding function A to the word X 0  and delivers a code word X 1  to one input of the block B 1 . The block B 1  applies to the word X 1  the function G already described, and delivers the word X 2  to the output OUT 1  of the circuit WR 2 . An example of the coding function A is described in part  8  of the supplemental information, in the form of a matrix of 2 K  lines and 2 K  columns, in which K=3.  
         [0033]     It will now be considered as above that the word X 2  is stored in a memory MEM, and the word read subsequently in the memory shall be designated X 3 , with X 3  being equal to the word X 2  to which the error E is added. The correction of the error E and the decoding of the word X 3  are carried out by the circuit RD 2 . The latter differs from the circuit RD 1  of the device ECC 1  by the fact that a decoding block B 5  is arranged between the output of the block B 2  and the output OUT 2 . The block B 5  applies a decoding function A −1  that is the reciprocal of the function A to the data received at its input. An example of the decoding function A −1  is described in part  9  of the supplemental information. The function A −1  is an inverse matrix of the matrix A described in part  8  of the supplemental information.  
         [0034]     The operation of the device ECC 2  is therefore as follows. The block B 0  generates a code word X 1  from the initial word X 0 . The block B 1  generates a secured code word X 2  from the code word X 1 . The block B 2  carries out an error correction on a secured code word X 3 , and delivers a corrected code word X 4 . The block B 5  carries out the decoding of the corrected code word X 4  and delivers a corrected decoded word X 5 . The blocks B 1 , B 3  and B 4  are identical to those of the device ECC 1 , since the word X 1  is a code word that has no impact on the security and the correction of this word.  
         [0035]     The circuits ECC 1  and ECC 2  that have just been described are traditionally formed from hard-wired logic blocks. The conversion time of the word X 1  into the word X 2  (security) and the conversion time of the word X 3  into the word X 4  (correction) therefore directly varies according to the data propagation time in the logic gates present along the data path between the input IN 1  and the output OUT 1  and between the input IN 2  and the output OUT 2 .  
         [0036]     The drawback of the device ECC 2  is that the data transfer process is slowed down by the addition of the blocks B 0  and B 5  along the data path. The blocks B 0  and B 5  are in fact, like the blocks B 1  to B 4 , and are produced using logic gates and have a determined data transfer time. The addition of the blocks B 0  and B 5  can increase by 30 to 50% the data transfer time between the inputs and the outputs of the device ECC 2 , as compared to the device ECC 1 .  
       SUMMARY OF THE INVENTION  
       [0037]     In view of the foregoing background, an object of the present invention is to provide a decoding and error correcting method that allows the data processing time to be accelerated.  
         [0038]     Another object of the present invention is to provide a decoding and error correcting circuit that has a shorter data transfer time than the prior art circuit described above.  
         [0039]     Yet another object of the-present invention is to provide a coding and security circuit that has a shorter data transfer time than the prior art circuit described above.  
         [0040]     These and other objects, advantages and features in accordance with the present invention are provided by a decoding and error correcting method applicable to a secured code word likely to have an error relative to an initial secured code word. The method preferably comprises one error correcting step, and one decoding step using a decoding function. The decoding step is carried out before the error correcting step, and preferably comprises application of the decoding function to the secured code word to obtain a secured decoded word containing a coded error.  
         [0041]     The error correcting step preferably comprises the application of a coded error vector to the secured decoded word. The method may also comprise one step of determining the coded error vector that is carried out at the same time as the decoding step.  
         [0042]     The step of determining the coded error vector may comprise the transformation by the decoding function of a non-coded error vector that would be applicable to the secured code word if the latter were corrected before being decoded.  
         [0043]     The step of determining the error vector may comprise one step of determining a pattern by applying a pattern calculation function to the secured code word, and one step of producing the coded error vector directly from the pattern by a table of direct correspondence between the pattern and coded error vector.  
         [0044]     The initial secured code word is preferably obtained by transforming, by a coding function, an initial word into a code word, and by transforming the code word using a security function. The initial secured code word is preferably obtained by applying to an initial word a coding and security function that is the result of the combination of a coding function and of a security function. The method is preferably implemented using hard-wired logic circuits.  
         [0045]     The present invention also relates to a decoding and error correcting circuit comprising a data path having one input to receive a secured code word and one output to deliver a corrected decoded word. A decoding block is arranged along the data path for applying a decoding function to a word present at one input of the decoding block. An error correcting block is arranged along the data path and has a first input to receive a word to be corrected, and a second input to receive an error vector. The decoding block is arranged on the data path upstream from the error correcting block, and delivers to the first input of the error correcting block a secured decoded word containing a coded error.  
         [0046]     The circuit preferably comprises a pattern determination block having one input linked to the input of the data path. The circuit also preferably comprises means for determining a coded error vector, and has one input linked to one output of the pattern determination block and one output linked to the second input of the error correcting block.  
         [0047]     The means for determining a coded error vector is arranged to deliver, from a pattern, a coded error vector equal to the transform by the decoding function of a non-coded error vector corresponding to the pattern. The means for determining a coded error vector may comprise a single block performing a conversion conforming to a table of direct correspondence between the pattern and the coded error vector.  
         [0048]     The decoding block, the error correcting block, the pattern determination block and the means for determining a coded error vector may be hard-wired logic circuits.  
         [0049]     The present invention also relates to a data coding/decoding and security/correction device comprising a decoding and error correcting circuit as defined above for transforming a secured code word into a corrected decoded word, and a coding and security circuit to transform an initial word into the secured code word.  
         [0050]     The coding and security circuit preferably comprises means for applying a coding function to an initial word, and for applying a security function to the code word. The coding and security circuit preferably comprises a single coding and security block for applying to an initial word the combination of the coding function and of the security function. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0051]     These and other objects, advantages and features of the present invention shall be explained in greater detail in the following description of the method of the present invention, and an example of an embodiment of a device according to the present invention, given in relation with, but not limited to, the following figures, in which:  
         [0052]      FIG. 1  is a block diagram of a data security and correction device in accordance with the prior art;  
         [0053]      FIG. 2  is a block diagram of a data coding/decoding and security/correction device comprising a coding and security circuit and a decoding and correction circuit in accordance with the prior art; and  
         [0054]      FIG. 3  is a block diagram of a data coding/decoding and security/correction device comprising a coding and security circuit and a decoding and correction circuit in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0055]      FIG. 3  represents a data coding/decoding and security/correction device ECC 3  according to the present invention. The device ECC 3  comprises a data coding and security circuit WR 3  and a data decoding and correction circuit RD 3 . The circuit WR 3  has one input IN 1  to receive a binary word X 0 , and one output OUT 1  to deliver a secured code word X 2 . The circuit RD 3  has one input IN 2  to receive a secured code word X 3  having an error E (that can be zero), and one output OUT 2  to deliver a corrected decoded word X 5 .  
         [0056]     According to the present invention, the circuit WR 3  comprises a block B 1 ′ that applies a coding and security function A*G to the word X 0 , and delivers the secured code word X 2  to the output OUT 1 . The function A*G is the product of a coding function A and of a security function G as readily known by one skilled in the art.  
         [0057]     As an example, it will be assumed that only one bit is to be detected and corrected in a word of eight bits by means of the Hamming algorithm. The parameters K and J already described above are, in this case, equal to 3 and to 4. The function G, in this case, is the matrix of 8 lines and 12 columns described in part  2  of the supplemental information. The function A is, for example, the matrix of 8 lines and 8 columns described in part  8  of the supplemental information. The corresponding function A*G according to the present invention, in this case, is equal to the matrix product of A and G and is described in part  10  of the supplemental information.  
         [0058]     Generally speaking, the transit time of the data in the block B 1 ′ is roughly equal to the transit time of data in one of the prior art blocks B 0  or B 1  described above. The conversion time of the word X 0  into the secured code word X 2  is, therefore, noticeably reduced by half in accordance with the present invention.  
         [0059]     It will now be considered, as above, that the word X 2  is stored in a memory MEM, and the word read subsequently in the memory shall be designated X 3 . X 3  is equal to the sum of the word X 2  and an error E. The correction of the error E and the decoding of the word X 3  are carried out by the circuit RD 3 .  
         [0060]     The circuit RD 3  comprises an error correcting block B 2 , a pattern generator block B 3 , an error vector EV′ generator block B 4 ′, and a decoding block B 5 . The blocks B 2 , B 3 , B 5  are identical to the blocks in the prior art circuit ECC 2  described above. The block B 4 ′ delivers error vectors EV 1 ′ having 2 K  bits corresponding to an error on the data and forming the useful part of an error vector EV′ of the type: 
 
EV′=EV 1 ′//EV 2 ′
 
 in which EV 2 ′ is an error vector of J bits corresponding to an error on security codes. EV 2 ′ is not used in practice. 
 
         [0062]     According to the present invention, the decoding block B 5  that applies the decoding function A −1  to the data it receives at input, is arranged on the data path between the input IN 2  of the circuit RD 3  and the input E 1  of the correction block B 2 . In other terms, the block B 2  receives at its input El non-corrected decoded data. As illustrated above, the word X 3  applied to the input IN 2  of the circuit RD 3  can be written: 
 
 X   3 = X   2 + E  
 
 X   3 = X   0 * A*G+E  
 
 The symbol + is the bit to bit addition without carrying the sum forward, and E is a word of 2 K +J bits representing the error affecting the word X 2 . 
 
         [0064]     The word X 3  and the error E can be written in the following form: 
 
X 3 =DATA(X 3 )//CODE(X 3 ) 
 
E=ERR 1 //ERR 2 . 
 
         [0065]     DATA(X 3 ) is a word comprising the 2 K  data bits of the word X 3 , CODE(X 3 ) is a word formed by the J security bits of the word X 3 , ERR 1  is a word comprising the 2 K  first bits of the error E, and ERR 2  is a word comprising the J following bits of the error. The result is: 
 
DATA( X   3 )=DATA( X   2 )+ERR 1 =(DATA( X   0 )* A*G )+ERR 1  
 
CODE( X   3 )=CODE( X   2 )+ERR 2 . 
 
         [0066]     The word DATA(X 3 ) is applied to the input of the block B 5  without the security bits CODE(X 3 ). Therefore, the word X 4 ′ delivered by the block B 5  is equal to: 
 
 X   4 ′=DATA( X   3 )* −1 =( X   0 * A*G*A   −1 )+ERR 1 * A   −1  
 
 As A and A −1  are reciprocal functions, the result is: 
 
 X   4 ′=( X   0 * G )+ERR 1 * A   −1  
 
 Since the security function G does not change the data bits, the result is: 
 
 X   4 ′= X   0 +ERR 1 * A   −1 . 
 
         [0069]     Therefore, the word applied X 4 ′ to the input of the correction circuit B 2  is not a secured code word as in previous practices, but a decoded word comprising a coded error. The decoded word is the word X 0  and the coded error is the term ERR 1 *A −1 i.e., the transform of the error ERR 1  by the decoding function A −1 . The decoding function A −1  is comparable to a coding function when it is applied to an element that has not previously been coded by the reciprocal function A.  
         [0070]     The error vector EV 1   ′  that must be applied to the input E 2  of the block B 2  to correct the coded error ERR 1 *A −1  should now be determined. As the word X 3  is applied entirely to the pattern generator block H, the result is: 
 
SYN= X 3 *H  
 
SYN=( X   2 + E )* H  
 
SYN=( X   1 * A*G+E )* H  
 
SYN= X   1 * A*G*H+E*H.  
 
         [0071]     Since the product of the functions H and G is zero, the pattern SYN is therefore equal to: 
 
SYN= E*H  
 
 Consequently, the pattern generated by the block B 3  is identical to the pattern generated by the block B 3 l of the devices ECC 1  and ECC 2  described above. 
 
         [0073]     Moreover, the error vector EV 1  is equal to the non-coded error ERR 1 , such that the error vector EV 1 ′ can be expressed from the error vector EV 1 : 
 
EV 1 ′=ERR 1 * A   −1 =EV 1 * A   −1 . 
 
         [0074]     The error vector EV 1 ′ according to the present invention is therefore a coded error vector, equal to the transform by the function A −1  of the classical error vector EV 1 .  
         [0075]     The block B 4 ′ can be produced by combining in series the block B 4  and a block performing the function A −1 . Advantageously, a table of direct correspondence is determined giving the vector EV 1 ′ for each pattern value according to the present invention. Each vector EV 1 ′ of the table of direct correspondence is calculated by applying the function A −1  to the vectors EV 1  given by a classical table of correspondence. A hard-wired logic block B 4 ′ is then produced performing the conversion function given by the table of direct correspondence.  
         [0076]     For a better understanding, a table of correspondence according to the present invention is described in part  11  of the supplemental information. This table of correspondence (Table 2) is obtained by applying the function A −1  to the vectors EV of the table of correspondence (Table 1) described in part  7  of the supplemental information.  
         [0077]     The operation of the device ECC 3  can therefore be summarized as follows. The block B 1 ′ generates a secured code word X2 from the initial word X 0 . The block B5 carries out the decoding of the secured code word X 3  and delivers a non-corrected decoded word X 4 ′ comprising a coded error ERR 1 *A −1 . The block B 2  carries out the correction of the coded error by a coded error vector EV 1 ′ in the same way as the coded error, i.e., by applying the function A −1  to a classical error vector EV 1 . Preferably, the block B 4 ′ delivers directly from the pattern SYN the error vector EV 1 ′.  
         [0078]     The decoding and correction circuit RD 3  according to the present invention offers the advantage of having a parallel architecture, in which the decoding of the word X 3  by the block B 5  is carried out at the same time as the determination of the pattern and of the error vector EV 1 ′ by the blocks B 3  and B 4 ′. Therefore, the decoding operation does not involve any slowing down of the data transfer time as in the prior art circuit ECC 2 , in which the decoding block B 5  is arranged downstream from the correction block.  
         [0079]     For a better understanding a description will now be given of an example of implementation of the decoding and correction method according to the present invention, using the functions A, G and H described in the supplemental information. It will be assumed that the word X 1  indicated below is to be written then read in the memory MEM: 
 
X 1 =1 1 0 0 1 0 1 1. 
 
         [0080]     After coding and securing the word X 0  using the function A*G (block B 1 ′) the following is obtained: 
 
X 2 = 0   1   0   0   0   0   1   1   0   1   0   1 . 
 
         [0081]     X 3  is written in the memory MEM, and then a word is reread: 
 
 X   3 = X   2 + E.  
 
         [0082]     Assuming that the error E is as follows: 
 
E=0 0 0 1 0 0 0 0 0 0 0 0. 
 
         [0083]     The read word X 3  is therefore equal to:  
             X2   =       ⁢     0   ⁢           ⁢   1   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   1   ⁢           ⁢   1   ⁢           ⁢   0   ⁢           ⁢   1   ⁢           ⁢   0   ⁢           ⁢   1                   +   E     =       ⁢     0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢     1   _     ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   0                 =     X3   =       ⁢     0   ⁢           ⁢   1   ⁢           ⁢   0   ⁢           ⁢     1   _     ⁢           ⁢   0   ⁢           ⁢   0   ⁢           ⁢   1   ⁢           ⁢   1   ⁢           ⁢   0   ⁢           ⁢   1   ⁢           ⁢   0   ⁢           ⁢   1.                 
 
         [0084]     Using the function H (block B 3 ) the corresponding pattern SYN is calculated: 
 
 X   3 * H= 0 1 1 0. 
 
         [0085]     Using the Table 2 in part  11  of the supplemental information (block B 4 ′) the coded error vector EV 1 ′ is determined: 
 
EV 1 ′=1 0 0 1 1 1 0 1. 
 
         [0086]     At the same time as the determination of the pattern and of the error vector, the non-corrected decoded word X 4 ′ is determined by the function A −1  (block  5 ): 
 
 X ′=(DATA( X   2 )+ERR 1 )* A   −1 =0 1 0 1 0 1 1 0. 
 
         [0087]     Then the word is corrected: 
 
X 5 =X 4 ′ xor EV 1 ′
 
X 5 =0 1 0 1 0 1 1 0 xor 1 0 0 1 1 1 0 1 
 
X 5 =1 1 10 0 1 0 1 1 
 
X 5 =X 1 . 
 
         [0088]     It will be clear to those skilled in the art that the data coding/decoding and security/correction device according to the present invention is susceptible to different embodiments and applications. In particular, the applications concern integrated circuits fitted with a memory. The device according to the present invention is interposed between the inputs and outputs of the memory. In particular, these are integrated circuits for smart cards, microcontrollers, integrated memories such as EPROM, EEPROM, FLASH EEPROM type memories, etc.  
         [0089]     As another example of application, the coding and security circuit WR 3  can be arranged at one end of a data transmission line and the decoding and correction circuit RD 3  can be arranged at the other end of the line. This is done to decode and correct the data received, as errors can be due to transmission problems or to disturbances along the line.  
       SUPPLEMENTAL INFORMATION  
       [0090]     Part 1—Words X 1  and X 2 : 
 
X 1 =x 0  x 1  x 2  x 3  x 4  x 5  x 6  x 7  
 
X 2 =DATA(X 2 )//CODE(X 2 ) 
 
X 2 =x 0  x 1  x 2  x 3  x 4  x 5  x 6  x 7  p 0  p 1  p 2  p 3  
 
 with 
 
DATA(X 2 )=X 1 =x 0  x 1  x 2  x 3  x 4  x 5  x 6  x 7  
 
CODE(X 2 )=p 0  p 1  p 2  p 3  
 
 p 0 , p 1 , p 3 , P 4  are security bits. 
 
         [0093]     Part 2—Matrix generating security bits according to the Hamming algorithm when K=3 and J=4 (correction of only one error bit):  
       G   =     (         1       0       0       0       0       0       0       0       1       0       0       1           0       1       0       0       0       0       0       0       1       1       1       0           0       0       1       0       0       0       0       0       1       1       0       1           0       0       0       1       0       0       0       0       0       1       1       1           0       0       0       0       1       0       0       0       0       1       1       0           0       0       0       0       0       1       0       0       1       0       1       0           0       0       0       0       0       0       1       0       0       0       1       1           0       0       0       0       0       0       0       1       0       1       0       1         )         
 
         [0094]     Part 3—Security bits generated by the matrix G: 
 
p 0 =x 0  xor x 1  xor x 2  xor x 5  
 
p 1 =x 2  xor x 3  xor x 4  xor x 7  xor x 1  
 
p 2 =x 4  xor x 5  xor x 6  xor x 1  xor x 3  
 
p 3 =x 6  xor x 7  xor x 0  xor x 2  xor x 3  
 
 xor is the EXCLUSIVE OR function. 
 
         [0096]     Part 4—Words E, ERR 1 , ERR 2 , X 3 , DATA(X 3 ), CODE(X 3 ): 
 
E=ER 1 //ER 2 =e 0  e 1  e 2  e 3  e 4  e 5  e 6  e 7  e 8  e 9  e 10  e 11  
 
ERR 1 =e 0  e 1  e 2  e 3  e 4  e 5  e 6  e 7  
 
ERR 2 =e 8  e 9  e 10  e 11  
 
 X   3 = X   2 + E =( x   0 + e   0 ) ( x   1 + e   1 ) ( x   2 + e   2 ) ( x   3 + e   3 ) 
 
( x   4 + e   4 ) ( x   5 + e   5 ) ( x   6 + e   6 ) ( x   7 + e   7 ) ( p   0 + e   8 ) 
 
( p   1 + e   9 ) ( p   2 + e   10 ) ( p   3 + e   11 ) 
 
DATA( X   3 )=( x   0 + e   0 ) ( x   1 + e   1 ) ( x   2 + e   2 ) ( x   3 + e   3 ) 
 
(x 4 +e 4 ) (x 5 +e 5 ) (x 6 +e 6 ) (x 7 +e 7 ) 
 
CODE( X   3 )=( p   0 + e   8 ) ( p   1 + e   9 ) ( p   2 + e   10 ) ( p   3 + e   11 ) 
 
         [0097]     Part 5—Hamming matrix H when K=3 and J=4:  
       H   =     (         1       0       0       1           1       1       1       0           1       1       0       1           0       1       1       1           0       1       1       0           1       0       1       0           0       0       1       1           0       1       0       1           1       0       0       0           0       1       0       0           0       0       1       0           0       0       0       1         )         
 
         [0098]     Part 6—Value of the pattern SYN generated by the matrix H when K=3 and J=4: 
 
SYN=S 0  S 1  S 2  S 3  
 
S 0 =x 0  xor x 1  xor x 2  xor x 5  xor p 0  
 
S 1 =x 2  xor x 3  xor x 4  xor x 7  xor x 1  xor p 1  
 
S 2 =x 4  xor x 5  xor x 6  xor x 3  xor x 1  xor p 2  
 
S 3 =x 6  xor x 7  xor x 3  xor x 2  xor x 0  xor p 3  
 
Part 7—Example of a classical table of correspondence when K=3 and J=4: 
 
                                         TABLE 1                                       Vector EV                PATTERN   EV1   EV2               0 1 0 1   1 0 0 0 0 0 0 0   0 0 0 0       0 0 1 1   0 1 0 0 0 0 0 0   0 0 0 0       1 0 1 0   0 0 1 0 0 0 0 0   0 0 0 0       0 1 1 0   0 0 0 1 0 0 0 0   0 0 0 0       0 1 1 1   0 0 0 0 1 0 0 0   0 0 0 0       1 1 0 1   0 0 0 0 0 1 0 0   0 0 0 0       1 1 1 0   0 0 0 0 0 0 1 0   0 0 0 0       1 0 0 1   0 0 0 0 0 0 0 1   0 0 0 0       0 0 0 0   0 0 0 0 0 0 0 0   0 0 0 1       0 0 0 1   0 0 0 0 0 0 0 0   0 0 1 0       0 0 1 0   0 0 0 0 0 0 0 0   0 1 0 0       0 1 0 0   0 0 0 0 0 0 0 0   1 0 0 0       1 0 0 0   0 0 0 0 0 0 0 0   0 0 0 0       1 0 1 1   0 0 0 0 0 0 0 0   0 0 0 0       1 1 0 0   0 0 0 0 0 0 0 0   0 0 0 0       1 1 1 1   0 0 0 0 0 0 0 0   0 0 0 0                  
 
         [0099]     Part 8—Example of coding function A when K=3:  
       A   =     (         1       1       0       0       0       1       0       1           0       1       0       0       0       0       0       0           0       1       1       0       1       0       0       0           1       0       0       1       0       0       0       1           0       0       0       0       1       0       0       0           0       1       0       0       0       1       0       1           1       1       0       0       0       1       1       1           0       0       0       0       1       0       0       1         )         
 
         [0100]     Part 9—Example of decoding function A −1  when K=3:  
         A     -   1       =     (         1       0       0       0       0       1       0       0           0       1       0       0       0       0       0       0           0       1       1       0       1       0       0       1           1       0       0       1       1       1       0       1           0       0       0       0       1       0       0       0           0       1       0       0       1       1       0       1           1       0       0       0       0       0       1       0           0       0       0       0       1       0       0       1         )         
 
         [0101]     Part 10—Example of coding and security function A*G when K=3:  
         A   *   G     =     (         1       1       0       0       0       1       0       1       0       1       0       1           0       1       0       0       0       0       0       0       1       1       1       0           0       1       1       0       1       0       0       0       0       1       0       1           1       0       0       1       0       0       0       1       1       0       1       1           0       0       0       0       1       0       0       0       0       1       1       0           0       1       0       0       0       1       0       1       0       0       0       1           1       1       0       0       0       1       1       1       1       0       1       1           0       0       0       0       1       0       0       1       0       0       1       1         )         
 
         [0102]     Part 11—Example of a table of correspondence according to the present invention when K=3 and J=4:  
                                         TABLE 2                                       Vector EV′ = EV * A −1                  PATTERN   EV1′ = EV1 * A −1     EV2′ = EV2 * A −1                 0 1 0 1   1 0 0 0 0 1 0 0   (not used)       0 0 1 1   0 1 0 0 0 0 0 0   (not used)       1 0 1 0   0 1 1 0 1 0 0 1   (not used)       0 1 1 0   1 0 0 1 1 1 0 1   (not used)       0 1 1 1   0 0 0 0 1 0 0 0   (not used)       1 1 0 1   0 1 0 0 1 1 0 1   (not used)       1 1 1 0   1 0 0 0 0 0 1 0   (not used)       1 0 0 1   0 0 0 0 1 0 0 1   (not used)       0 0 0 0   0 0 0 0 0 0 0 0   (not used)       0 0 0 1   0 0 0 0 0 0 0 0   (not used)       0 0 1 0   0 0 0 0 0 0 0 0   (not used)       0 1 0 0   0 0 0 0 0 0 0 0   (not used)       1 0 0 0   0 0 0 0 0 0 0 0   (not used)       1 0 1 1   0 0 0 0 0 0 0 0   (not used)       1 1 0 0   0 0 0 0 0 0 0 0   (not used)       1 1 1 1   0 0 0 0 0 0 0 0   (not used)

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