Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a type of switched-mode power supply (SMPS), and more particularly to an SMPS capable of providing over current protection (OCP) or over load protection (OLP). 
         [0003]    2. Description of the Prior Art 
         [0004]    Power supplies act as a type of power management device utilized for converting power to provide power to electronic devices or components. Sometimes, power management devices adopt a switched-mode power supply architecture, because energy conversion efficiency of the SMPS architecture is good, and number of required inductive devices is relatively low. The SMPS architecture is applicable to many current-generation electronic devices or components. An SMPS requires multiple protection mechanisms for preventing damage caused by internal or external events that may arise from inaccurate or inappropriate conditions. Over voltage protection (OVP), over temperature protection (OTP), over current protection (OCP), and over load protection (OLP) are some of a few types of protection mechanisms employed in power supplies. OCP is typically concerned with limiting maximum output current; OLP is typically concerned with limiting maximum output power. 
         [0005]      FIG. 1  illustrates a type of booster having OCP/OLP. Booster  10  is only utilized as one example of OCP/OLP. OCP/OLP may also be utilized in other SMPS architectures. 
         [0006]    Switch  14  of booster  10  controls current flowing through inductor  12 . When gate signal GATE turns on switch  14 , energy stored on inductor  12  increases. When gate signal GATE turns off switch  14 , energy stored on inductor  12  is released into a load through diode  16  to charge load capacitor  20 . Sense resistor  22  detects inductor current flowing through inductor  12  while switch  14  conducts (is on). Voltage level of current sensing signal V CS  at terminal CS reflects inductor current magnitude, based on which controller  18  generates gate signal GATE. 
         [0007]      FIG. 2  illustrates a type of controller  18   a  suitable for use with booster  10  of  FIG. 1 . When controller  18   a  turns on switch  14  of  FIG. 1 , voltage level of current sensing signal V CS  increases with turn on time. Comparator  36  controls peak value of current sensing signal V CS  to be approximately less than limiting signal V CS-LIMIT . Comparator  36  causes gate controller  34  to turnoff switch  14  whenever current sensing signal V CS  exceeds limiting signal V CS-LIMIT , thereby achieving OCP/OLP. However, signal propagation delay causes peak value of the current sensing signal V CS  to be slightly higher than the limiting signal V CS-LIMIT , and this difference increases with increased voltage level of input voltage supply V IN . If limiting signal V CS-LIMIT  is a fixed value, maximum output current or maximum output power limited by the OCP/OLP provided in  FIG. 2  changes with voltage level of input voltage supply V IN . This type of result makes it hard for the OCP/OLP to meet system specifications. 
         [0008]    Even if peak value of the current sensing signal V CS  is held to a fixed value, maximum output current/power defined by OCP/OLP will be different if inductor  12  is operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). 
         [0009]    Thus, OCP/OLP circuit requires special design, so that maximum output current/power approximates a fixed value when triggered, and does not change with conduction mode or input voltage supply voltage. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  illustrates a type of booster having OCP/OLP. 
           [0012]      FIG. 2  illustrates a type of controller suitable for use with booster of  FIG. 1 . 
           [0013]      FIG. 3  is a graph illustrating relationship between V CS-PEAK  and V CS-AVG  of equation (3). 
           [0014]      FIG. 4  is a diagram illustrating controller that may be utilized with booster of  FIG. 1  according to an embodiment 
           [0015]      FIG. 5A  and  FIG. 5B  illustrate two types of signal delay compensator that may be utilized with  FIG. 4 . 
           [0016]      FIG. 6  illustrates average current comparator, modifier, and clamp, which may be utilized with  FIG. 4 . 
           [0017]      FIG. 7  illustrates relationship of limiting signal VCS-LIMIT and expected average inductor current signal VCS-AVG-EXP, and simplification result thereof. 
           [0018]      FIG. 8  illustrates a converter for use in controller of  FIG. 4 . 
           [0019]      FIG. 9  illustrates a controller according to an embodiment 
           [0020]      FIG. 10  illustrates one example of a peak value detector. 
           [0021]      FIG. 11  illustrates simplified relationship of VCS-PEAK and VCS-AVG. 
           [0022]      FIG. 12  illustrates a converter for realizing relationship in  FIG. 11 , and usable in  FIG. 9 . 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    In the following description, similar reference numerals refer to same or similar devices/components. A person of ordinary skill in the art may make embodiments utilizing same or similar methods/architectures according to disclosure/teaching of the present invention, so repeated description is not provided. 
         [0024]    An embodiment provides an SMPS, of which when OCP/OLP is triggered, maximum output current/power is independent of input voltage and conduction modes. 
         [0025]    Please refer to booster  10  of  FIG. 1 . Power P transferred to load capacitor  20  by inductor  12  may be expressed as follows: 
         [0000]        P= ½ *L* ( I   2   CS-PEAK   −I   2   CS-INI )* f   SW   (1)
 
         [0000]    where L represents inductance of inductor  12 , I CS-PEAK  represents peak value of inductor current flowing through inductor  12  (which is also peak value of current flowing through switch  14 ), I CS-INI  represents initial inductor current flowing through inductor  12  (which is also initial current flowing through switch  14 ) each time switch  14  turns on, and f SW  represents switching frequency of switch  14 . In DCM operation, I CS-INI  is 0 Amps; in CCM operation, I CS-INI  is greater than 0 Amps. 
         [0026]    The right half of equation (1) should be a fixed value because maximum output power P OLP  is a fixed value when OLP is triggered. The right half of equation (1) should be a fixed value for OCP as well, because maximum output current C OCP  is a fixed value when OCP is triggered, assuming output voltage V OUT  is kept at a fixed voltage level. 
         [0027]    Assuming switching frequency f SW  of booster  10  does not change, a part in equation (1), when OLP/OCP is triggered, can be rewritten as: 
         [0000]        I   2   CS-PEAK   −I   2   CS-INI =4 *I   CS-AVG *( I   CS-PEAK   −I   CS-AVG )= K   1   (2)
 
         [0000]    where I CS-AVG  represents ½*(I CS-PEAK +I CS-INI ), which may also represent average inductor current flowing through switch  14  when switch  14  is turned on; K 1  is a constant, too. 
         [0028]    Equation (2) may be rewritten as follows: 
         [0000]        V   CS-PEAK   =V   CS-AVG   +K/V   CS-AVG   (3)
 
         [0000]    where K is a constant, V CS-PEAK  and V CS-AVG  represent voltage levels of current sensing signal V CS  corresponding to inductor currents I CS-PEAK  and I CS-AVG , respectively. When OCP/OLP occurs, as long as V CS-PEAK  and V CS-AVG  meet the requirement of equation (3), maximum output current/power defined by OCP/OLP approximates a fixed value. 
         [0029]      FIG. 3  is a graph illustrating relationship between V CS-PEAK  and V CS-AVG  of equation (3). Two dashed lines represent V CS-PEAK =V CS-AVG  and V CS-PEAK =K/V CS-AVG , respectively. For example, if booster  10  is designed to operate in DCM, V CS-PEAK  of 0.9 Volts should trigger OCP/OLP, meaning V CS-AVG  is 0.45 Volts, and K should be 0.45*0.45 Volts 2 . Solid curve of  FIG. 3  represents relationship between V CS-PEAK  and V CS-AVG  when OCP/OLP is triggered. 
         [0030]    Thus, as long as V CS-PEAK  and V CS-AVG  of any switching cycle are known, and are substituted into equation (3) for calculation, it may be determined whether output current/power is greater or less than maximum output current/power defined by OCP/OLP, thereby updating limiting signal V CS-LIMIT . After a few switching cycles, output current/power of every switching cycle will be approximately a fixed value, which is maximum output current/power defined by OCP/OLP. 
         [0031]      FIG. 4  is a diagram illustrating controller  18   b  that may be utilized with booster  10  of  FIG. 1  according to an embodiment, and may be utilized with other types of SMPS. Gate controller  34  receives signals from other signal processor  32  and signal delay compensator  51  for driving switch  14 . Signal delay compensator  51  may approximately compensate signal delay effect, making peak value V CS-PEAK  of current sensing signal V CS  almost equal to limiting signal V CS-LIMIT . Thus, limiting signal V CS-LIMIT  may be seen as peak value V CS-PEAK  of current sensing signal in any switching cycle. Converter  56  approximately takes limiting signal V CS-LIMIT  as an input, and outputs expected average inductor current signal V CS-AVG-EXP  according to relationship between V CS-PEAK  and V CS-AVG  (which may be obtained through simplification of solid line in  FIG. 3 ). Average current comparator  52  compares average current V CS-AVG-REAL  (which is the average of V CS  when switch  14  is turned on) and expected average inductor current signal V CS-AVG-EXP . Output of average current comparator  52  causes modifier  54  to modify limiting signal V CS-LIMIT . Clamp  59  is utilized for limiting maximum and minimum of limiting signal V CS-LIMIT . 
         [0032]    It can be seen from  FIG. 4  that converter  56 , average current comparator  52 , and modifier  54  substantially form a closed loop. After multiple switching cycles, relationship between V CS-PEAK  and V CS-AVG  approaches solid line of  FIG. 3  or a corresponding segment thereof, such that operation of the loop causes maximum output current/power defined by OCP/OLP to become a fixed value. 
         [0033]    Signal delay compensator  51 , converter  56 , and average current comparator  52 , and modifier  54  may be seen as a regulator that modifies limiting signal V CS-LIMIT  to cause peak value V CS-PEAK  and average current V CS-AVG-REAL  corresponding to current sensing signal V CS-LIMIT  to approach predetermined relationship in  FIG. 3  with progression of switching cycles. 
         [0034]    For example, when expected average inductor current signal V CS-AVG-EXP  is lower than average current V CS-AVG-REAL , limiting signal V CS-LIMIT  increases in the next switching cycle. Thus, expected average inductor current signal V CS-AVG-EXP  approaches average current V CS-AVG-REAL  in the next switching cycle. 
         [0035]      FIG. 5A  and  FIG. 5B  illustrate two types of signal delay compensator  51 A and  51   b  that may be utilized with  FIG. 4 . In  FIG. 5A , signal delay compensator  51   a  primarily comprises comparators  502 ,  504 , capacitor  508 , current sources I R , I L , and resistors R B , R BIAS1 . If peak value V CS-PEAK  of current sensing signal V CS  is greater than limiting signal V CS-LIMIT  comparator  504  causes current source I R  to charge capacitor  508  and pull up capacitor voltage V bias . If peak value V CS-PEAK  of current sensing signal V CS  is less than limiting signal V CS-LIMIT  current source I L  slowly discharges capacitor  508  and pull down capacitor voltage V bias . Current source I L  must be much smaller than current source I R . Voltage V BIAS1  is generated across resistor R BIAS1  as capacitor voltage V bias  is converted into current I bias  through resistor R B  and current mirrors  506 ,  507 , thereby providing a lower limiting signal V CS-LIMIT-LOWER  lower than limiting signal V CS-LIMIT . Output signal of comparator  502  turns off switch  14  when current sensing signal V CS  is greater than lower limiting signal V CS-LIMIT-LOWER . After multiple switching cycles, capacitor voltage V bias  is held at approximately a fixed value, making comparator  502  early send signal when current sensing signal V CS  equals lower limiting signal V CS-LIMIT-LOWER  finally causing peak value V CS-PEAK  of current sensing signal V CS  to equal limiting signal V CS-LIMIT . Current source I L  may be optional if self-leakage of capacitor  508 , or junction leakage, is utilized to pull down capacitor voltage V bias  slowly. 
         [0036]    Signal delay compensator  51   b  of  FIG. 5B  may also cause peak value V CS-PEAK  of current sensing signal V CS  to equal limiting signal V CS-LIMIT . Different from generation of lower limiting signal V CS-LIMIT-LOWER  in  FIG. 5A ,  FIG. 5B  shows generating higher current sensing signal V CS-HIGHER . Other circuit architecture and operating principles of  FIG. 5B  are same or similar to  FIG. 5A , and can be derived from  FIG. 5A  by persons skilled in the art. 
         [0037]      FIG. 6  illustrates average current comparator  52   a , modifier  54   a , and clamp  59   a , which may be utilized with  FIG. 4 . 
         [0038]    It can be seen from variation in output voltage V M  of average current comparator  52   a  whether average current V CS-AVG-REAL  (average of current sensing signal V CS ) is greater than or less than expected average inductor current signal V CS-AVG-EXP . Current source  362  provides fixed current I con  to charge capacitor  366  when current sensing signal V CS  is greater than expected average inductor current signal V CS-AVG-EXP . Current source  364  provides fixed current I con  to discharge capacitor  366  when current sensing signal V CS  is less than expected average inductor current signal V CS-AVG-EXP . Current sensing signal V CS  increases linearly, so output voltage V M  increases if average current V CS-AVG-REAL  is greater than expected average inductor current signal V CS-AVG-EXP  when gate signal GATE causes switch  14  to turn on. Output voltage V M  decreases if average current V CS-AVG-REAL  is relatively small. 
         [0039]    Modifier  54   a  updates limiting signal V CS-LIMIT  according to output voltage V M  when gate-bar signal  GATE  causes switch  14  to turn off. To prevent over voltage or under voltage, clamp  59   a  utilizes two diodes to force voltage level of limiting signal V CS-LIMIT  between top limit V CS-LIMIT-TOP  and bottom limit V CS-LIMIT-BOTTOM . 
         [0040]      FIG. 7  illustrates, in the left side, the relationship of limiting signal V CS-LIMIT  and expected average inductor current signal V CS-AVG-EXP , namely the relationship of V CS-PEAK  and V CS-AVG  of  FIG. 3 ; and, in the right side, a simplification result thereof. The relationship of V CS-PEAK  and V CS-AVG  in  FIG. 3  is a curve, circuit implementation of which may be relatively complicated. Thus, the curve in  FIG. 3  may be represented as a single line segment or a piecewise linear curve. A signal straight line is a simplest method for representing upper half of the curve, as shown by line L in the right side of  FIG. 7 . Lower half of the curve may be omitted, as such conditions do not arise in practical operation. Line L in  FIG. 7  (right) may be realized by multiple different types of circuits. For example, as shown in  FIG. 8 , a simple operational amplifier together with resistors R 1  and R 2  may realize line L, acting as a converter  56   a  for use in controller  18   b  of  FIG. 4 . 
         [0041]      FIG. 9  illustrates a controller  18   c  according to an embodiment, which may be utilized with booster  10  of  FIG. 1 , and is suitable for use with other types of SMPS. 
         [0042]      FIG. 9  does not include signal delay compensator  51  of  FIG. 4 , utilizing only comparator  36  to replace signal delay compensator  51  so as to expect peak value V CS-PEAK  of current sensing signal VCS not to be greater than limiting signal V CS-LIMIT . As described above, due to signal delay, such an architecture causes peak value V CS-PEAK  to approach but exceed limiting signal V CS-LIMIT . In  FIG. 9 , peak value detector  61  is utilized for detecting peak value V CS-PEAK . Converter  57  takes peak value V CS-PEAK  as input, and outputs expected average inductor current signal V CS-AVG-EXP  roughly based on relationship between V CS-PEAK  and V CS-AVG  (which could be obtained from the simplification of solid curve in  FIG. 3 ). 
         [0043]      FIG. 9  also includes a closed loop, substantially formed by peak value detector  61 , converter  57 , average current comparator  52 , modifier  54 , comparator  36 , gate controller  34 , switch  14 , and sense resistor  22 . After multiple switching cycles, relationship between V CS-PEAK  and V CS-AVG  approaches solid line or a corresponding segment thereof in  FIG. 3 , such that operation of the loop causes maximum output current/power defined by OCP/OLP to become a fixed value. 
         [0044]    Peak value detector  61 , converter  57 , and average current comparator  52 , and modifier  54  can be seen as another adjusting module for adjusting limiting signal V CS-LIMIT  to cause peak value V CS-PEAK  and average current V CS-AVG-REAL  corresponding to current sensing signal V CS  to approach predetermined relationship in  FIG. 3  along with progression of switching cycles. 
         [0045]      FIG. 10  illustrates one example of a peak value detector  61   a . A capacitor thereof may store peak value V CS-PEAK .  FIG. 11  illustrates simplified relationship of V CS-PEAK  and V CS-AVG  for causing maximum output current/power defined by OCP/OLP to become a fixed value.  FIG. 12  illustrates a converter  57   a  for realizing relationship in  FIG. 11 , and usable in  FIG. 9 . 
         [0046]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Technology Category: 5