Patent Document

TECHNICAL FIELD  
         [1]    1. This invention relates to integrated circuitry capacitors and methods of forming the same.  
         BACKGROUND OF THE INVENTION  
         [2]    2. One common goal in capacitor fabrication is to maximize the capacitance for a given size capacitor. It is desirable that stored charge be at a maximum immediately at the physical interface between the respective electrodes or capacitor plates and the capacitor dielectric material between the plates. Typical integrated circuitry capacitors have electrodes or plates which are formed from doped semiconductive material such as polysilicon. The polysilicon is usually heavily doped to impart a desired degree of conductivity for satisfactory capacitor plate operation.  
           [3]    3. One drawback of heavily doping polysilicon is that during operation a charge depletion region develops at the interface where charge maximization is desired. Hence, a desired level of charge storage is achieved at a location which is displaced from the interface between the capacitor plate and the dielectric material.  
           [4]    4. Another drawback of heavily doping the polysilicon capacitor plates is that during processing, some of the dopant can migrate away from the polysilicon and into other substrate structures. Dopant migration can adversely affect the performance of such structures. For example, one type of integrated circuitry which utilizes capacitors are memory cells, and more particularly dynamic random access memory (DRAM) devices. Migratory dopants from doped polysilicon capacitor plates can adversely impact adjacent access transistors as by undesirably adjusting the threshold voltages.  
           [5]    5. As the memory cell density of DRAMs increases there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. The principal way of increasing cell capacitance heretofore has been through cell structure techniques. Such techniques include three dimensional cell capacitors such as trench or stacked capacitors.  
           [6]    6. This invention arose out of concerns associated with improving integrated circuitry capacitors. This invention also grew out of concerns associated with maintaining and improving the capacitance and charge storage capabilities of capacitors utilized in memory cells comprising DRAM devices.  
         SUMMARY OF THE INVENTION  
         [7]    7. Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. Other materials can be used such as chemical vapor deposited platinum, TiN, and the like. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [8]    8. Preferred embodiments of the invention are described below with reference to the following accompanying drawings.  
         [9]    9.FIG. 1 is a view of a semiconductor wafer fragment undergoing processing in accordance with the invention.  
         [10]    10.FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 1.  
         [11]    11.FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 2.  
         [12]    12.FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 3.  
         [13]    13.FIG. 5 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 4.  
         [14]    14.FIG. 6 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 5.  
         [15]    15.FIG. 7 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 6.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [16]    16. This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).  
         [17]    17. Referring to FIG. 1, a semiconductor wafer fragment in process is indicated generally at  10  and includes a semiconductor substrate  12 . In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductor material, including, but not limited to, bulk semiconductor materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductor material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.  
         [18]    18. Isolation oxide regions  14  are formed relative to substrate  12  and define therebetween a substrate active area over which a plurality of capacitors are to be formed. Conductive lines  16 ,  18 ,  20 , and  22  are provided over substrate  12 . Such lines typically include, as shown for line  16 , a thin oxide layer  24 , a conductive polysilicon layer  26 , a silicide layer  28 , a protective insulative cap  30 , and sidewall spacers  32 . A plurality of diffusion regions  17 ,  19 , and  21  are received within substrate  12  and constitute source/drain regions for transistors which serve as access transistors for the capacitors to be formed. Diffusion regions  17 ,  19  and  21  define substrate node locations with which electrical communication is desired. An insulative layer  34  is formed over substrate  12  and typically comprises an oxides such as borophosphosilicate glass. Of course, other materials such as phosphosilicate glass, borosilicate glass, and the like can be used. Subsequently, insulative layer  34  is patterned and etched to define openings  36 ,  38  over diffusion regions  17 ,  21  respectively, and relative to which capacitors are to be formed. Insulative layer  34  defines a substrate outer surface  35 .  
         [19]    19. A first layer  40  is formed over substrate outer surface  35 . An exemplary and preferred material for layer  40  comprises a conductive or semiconductive material such as conductively doped polysilicon. Layer  40  defines at least a portion of a first or inner capacitor plate. Layer  40  also has a first conductivity and defines a capacitor plate which is operably adjacent and in electrical communication with the node locations defined by diffusion regions  17  and  21 . Accordingly, layer  40  is electrically connected with the node locations defined by diffusion regions  17 ,  21 .  
         [20]    20. Referring to FIG. 2, a second layer  42  is formed over first layer  40 . In a preferred implementation, second layer  42  comprises a conductive material which constitutes roughened or rugged polysilicon. An exemplary and preferred roughened or rugged polysilicon is hemispherical grain polysilicon. Such is, in one aspect, substantially undoped as formed over first layer  40 . Subsequently, and through suitable processing, outdiffusion of dopant from conductively doped polysilicon layer  40  into layer  42  renders second layer  42  conductive. Together, layers  40  and  42  constitute a doped semiconductive material having a first average conductivity. Accordingly, layers  40  and  42  constitute a first or inner capacitor plate having an outermost surface  44  of hemispherical grain polysilicon. Accordingly, outermost surface  44  defines a generally roughened surface area.  
         [21]    21. Referring to FIG. 3, a layer  46  is formed over substrate  12  and outer surface  44  of layer  42 . According to one aspect, layer  46  constitutes a conductive material having a second average conductivity which is greater than the first average conductivity of layers  40 ,  42 . A preferred manner of forming layer  46  is through suitable chemical vapor deposition thereof over layer  42 . Accordingly, such forms a generally conformal layer over the roughened surface area of the preferred hemispherical grain polysilicon layer  42 . Hence, layer  46  is disposed over and operably adjacent layers  40 ,  42 .  
         [22]    22. Suitable materials for layer  46  include conductive metal compounds, metal alloys, and elemental metals. Other suitable materials include those which are preferably not conductively doped semiconductive material such as polysilicon. Accordingly, layer  46  constitutes a material other than doped semiconductive material. An exemplary and preferred material for layer  46  is elemental titanium which is chemical vapor deposited over layer  42 . Other materials can be used such as chemical vapor deposited platinum, TiN, and the like. Layer  46  is preferably chemical vapor deposited directly onto the hemispherical grain polysilicon material of layer  42 .  
         [23]    23. Referring to FIG. 4, layers  40 ,  42 , and  46  are planarized to electrically isolate the layers within respective opening  36 ,  38 . Exemplary planarization techniques include mechanical abrasion of the substrate as by chemical mechanical polishing. Other techniques are possible.  
         [24]    24. Referring to FIG. 5, a capacitor dielectric layer  48  is formed operably proximate the first capacitor plate, over layer  46  and within openings  36 ,  38 . Accordingly, layer  48  is spaced from the material of layers  40 ,  42  a distance which is defined by layer  46 . Exemplary materials for layer  48  are Si 3 N 4  and SiO 2  alone, or in combination. Other materials such as tantalum pentoxide (Ta 2 O 5 ), barium strontium titanate (BST), and other dielectric materials can be used.  
         [25]    25. Alternately considered, the preferred metal layer  46  is formed intermediate conductive capacitor plate  40 ,  42  and capacitor dielectric layer  48  preferably by chemical vapor deposition prior to providing capacitor dielectric layer  48 . As formed, metal layer  46  is at least in partial physical contacting relationship with capacitor dielectric layer  48 . Accordingly, layer  46  is interposed between capacitor plate  40 ,  42  and dielectric layer  48 . In a most preferred aspect, conductive layer  46  consists essentially of non-semiconductive material such as titanium, or titanium silicide.  
         [26]    26. Referring to FIG. 6, a second capacitor plate layer  50  is formed over dielectric layer  48  and operatively proximate layer  46 . In a preferred implementation, layer  50  defines an outer capacitor plate which defines a cell plate layer of a DRAM storage capacitor. An exemplary material for capacitor plate layer  50  is polysilicon.  
         [27]    27. Referring to FIG. 7, individual storage capacitors are patterned and etched to form capacitors  52 ,  54 . An insulative layer  56  is formed thereover and is subsequently patterned and etched to form an opening which outwardly exposes diffusion region  19 . Subsequently formed conductive material  58  provides a conductive bit line contact plug, and a subsequently formed conductive layer  60  provides a bit line in operative electrical contact therewith. Accordingly, such defines, in the illustrated and preferred embodiment, DRAM storage cells comprising storage capacitors  52 ,  54 . The FIG. 7 construction illustrates but one example of DRAM storage cell constructions. Of course, other constructions which utilize the inventive methodology are possible  
         [28]    28. The above-described methodology and capacitor constructions provide a desirable solution to concerns associated with charge depletion effects at the interface between a capacitor plate and a dielectric layer. The interpositioning of a layer of conductive material relative to the capacitor plate and the dielectric layer, which is more conductive than capacitor plate, effectively relocates the location of the capacitor&#39;s stored charge to a more desirable location. In addition, in implementations where doped semiconductive material is utilized for an inner capacitor plate and the “more conductive” interposed layer is formed thereover, a lesser degree of doping can be utilized such that dopant migration into other substrate structures is reduced. This is particularly useful when the capacitor plate includes an additional layer which is generally undoped as formed and subsequently rendered suitably conductive by outdiffusion of dopant from an adjacent layer.  
         [29]    29. In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Technology Category: 5