Patent Document

This application claims the benefit of U.S. provisional application No. 60/178,733, filed Jan. 28, 2000. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a line driver and an amplifying method in said line driver. 
     DESCRIPTION OF RELATED ART 
     Multi-carrier modulation is a known method for transmitting broadband information (for example, video, Internet or telephony) over radio connections or copper wire. The latter may be e.g. xDSL systems, such as Asymmetric Digital Subscriber Line (ADSL), High-rate Digital Subscriber Line (HDSL) or Very high speed asymmetric Digital Subscriber Line (VDSL). Two similar methods in multi-carrier modulation are Orthogonal Frequency Division Multiplex (OFDM), used in radio applications, and Discrete Multitone (DMT), which is used in copper wires. 
     Very briefly explained, the bits that are to be transmitted, (of for example a digitally encoded video signal) are encoded as complex numbers in a transmitter. In the transmitter an Inverse Fast Fourier Transform (IFFT) and a digital-to-analogue conversion are carried out whereupon the result is sent out on a line to a receiver. 
     The IFFT-modulation gives a sum of orthogonal carriers or tones, the amplitudes and phase displacement of which are determined by the values and phases of the complex numbers. These carriers are then transmitted in time slots at constant time intervals and are called symbols. In the receiver an analogue-to-digital conversion and a Fast Fourier Transform (FFT) are carried out instead. In this way, the original bits are retrieved. Attenuation and phase displacement may be easily compensated for, by multiplication by a complex number for each carrier. 
     In an xDSL system there is a line driver after the digital-to-analogue conversion in the transmitter. Said line driver is an amplifier that feeds the line. Since the output from the IFFT-modulation approximately is Gaussian distributed, the peak-to-average ratio is very high. This means that the line driver must have a high supply voltage in order to adequately transmit the occasional high signal peaks that may occur. 
     Unfortunately, such a high supply voltage results in substantial power dissipation in the line driver. In fact, e.g. in a typical commercial ADSL-system, about 67% of the total power is consumed in the line driver. Thus, there is a need to reduce the power dissipation in such a line driver. Power dissipated in digital logic will be possible to reduce in the future by improved semiconductor technology, but physical laws limits the possibilities to reduce the power in the line driver. 
     In WO99/18662 reduced power dissipation is achieved by using several power supplies to the line driver. In the first embodiment two different positive power supplies are used, which provide power at first and second levels, respectively, where the second level is greater than the first level. A controller causes power to be supplied from the first power supply to the line driver when the magnitude of the input voltage is less than or equal to a predetermined threshold. When the magnitude of the input voltage is greater than the threshold, the controller causes power to be supplied from the second power supply to the line driver. 
     The problem with this embodiment is that when the amplifier is in an idle mode, it will take an idle voltage in the middle of the voltage range. Idle voltage is in the present description defined as the voltage that is received on the output of the line driver when there is no input signal to it. This is mainly applicable in circuits that are connected differential or in circuits that are AC-connected. 
     Thus, if the power supply voltage presently used is 5V, then the idle voltage will be 2,5V and if the power supply voltage presently used is 12V, then the idle voltage will be 6V. Hence, the idle voltage differs depending on which power supply voltage it is that is presently used. This is bad, because then the output voltage will change when the power supply voltage is changed, even though it is supposed to be an idle mode. Another problem is that it is necessary to use two different power supplies, which is expensive, inefficient and place consuming. 
     The second embodiment in WO99/18662 uses four power supplies, two positive and two negative of corresponding values. This makes the idle voltage at zero at all times. The problem with this embodiment is that as many as four different power supplies are needed. 
     SUMMARY 
     The purpose with the present invention is to provide a line driver, such as a line driver in a multi carrier system, with a low power dissipation and a stable idle voltage without having. to use a lot of different power supplies. 
     The problems mentioned above with the different embodiments WO99/18662 are solved by defining a voltage range, within which it is the greatest probability that the input voltage to the line driver will fall. A power supply to the line driver is chosen accordingly and whole or part of the power supply voltage is used for generating the output voltage as long as the input voltage is within said range. 
     Further, a capacitor is included in the line driver and is loaded to a capacitor voltage. Whole or part of said capacitor voltage may then be used in addition to whole or part of the power supply voltage to generate the output voltage when the input voltage is outside said range. 
     The advantages are that a low power dissipation and a stable idle voltage is achieved in a simple circuit without the need for many power supplies. The larger the differences of probability are within the range compared to outside the range the larger is the gain of lowered power dissipation. This is particularly evident in e.g. systems with Gaussian distributed input voltage probabilities, such as is the case for a line driver in a multicarrier system. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention outlined above are described more fully below in the detailed description in conjunction with the drawings where like reference numerals refer to like elements throughout. 
     FIG. 1 is a function block diagram showing an example multi-carrier modulation system in which the present invention may be employed. 
     FIGS. 2 a  and  2   b  are simplified illustrations of a line driver in a digital subscriber line environment. 
     FIG. 3 is a graph showing a Gaussian distribution of multi-carrier modulator output voltages. 
     FIGS. 4 a-c  is a circuit diagram showing a voltage-generating block according to the present invention. 
     FIG. 5 is a circuit diagram showing a first embodiment of a line driver according to the present invention. 
     FIG. 6 is a circuit diagram showing a second embodiment of a line driver according to the present invention. 
     FIG. 7 is a simplified illustration of a first embodiment of a control circuit for the circuits in FIG. 5 or 6. 
     FIG. 8 is a simplified illustration of a second embodiment of a control circuit for the circuits in FIG. 5 or 6. 
     FIG. 9 is a circuit diagram showing a third embodiment of a line driver according to the present invention. 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     FIG. 1 shows, schematically, how the main parts of a prior art system for multi-carrier modulation may look. In a transmitter  1  modulation of data bits, for example from a digitally encoded video signal, is performed. 
     The bits to be transmitted are encoded in the transmitter  1  as N complex numbers before a hermit symmetry operation is carried out in a calculation block  4 . 2N complex numbers are obtained having a symmetric real part and an asymmetric imaginary part. 
     An Inverse Fast Fourier Transform (IFFT) is then performed in an IFFT calculation unit  5 , as a modulation. Since the imaginary part becomes zero it may be eliminated and a real signal remains, which passes a parallel to serial converter  6 , a digital-to-analogue converter  7  and a line driver  12 . 
     This gives a sum of orthogonal carriers or tones, the amplitudes and phases of which are determined by the values and phases of the original complex numbers. These carriers are then transmitted in a line  2  at constant time intervals/time slots and are called symbols. 
     In a receiver  3  the data, in the opposite way, passes an analogue-to-digital converter  8 , a serial-to-parallel converter  9  and an FFT calculation unit  10 , in which an FFT is carried out, as a demodulation. This gives 2N complex numbers. For symmetry reasons, for example the upper half of the 2N complex numbers may be discarded, leaving a number N of complex numbers. 
     Finally, an equalizer  11  is used, which compensates for attenuation and phase displacement by multiplying the different numbers with complex numbers so that finally the same data bits are obtained that were transmitted to begin with. 
     In FIG. 2 a  a line driver  12  is shown. A modulated input voltage U in  from the digital-to-analogue converter  7  is fed into the line driver  12 , which is an amplifier supplied with a power supply voltage V cc.  The line driver  12  produces an output voltage U out  to a transformer  13 , which feeds the line  2 . From the point of view of the line driver  12  it may be seen as there is a resistive load R L  on the output of the line driver  12 , which is schematically shown in FIG. 2 b.    
     Power dissipation P d  is the power that results in heating the line driver  12  and may be characterised in accordance with the following equation: 
     
       
           P   d =( V   cc   −U   out )· U   out   /R   L   +P   f   (1) 
       
     
     The parameter P f  is a technology dependent power that may be possible to reduce in the future if new semiconductor technology is invented. It is however also partly dependent on the power supply voltage V cc.  The rest of the power dissipation P d  can only be reduced with a lower power supply voltage V cc . However, the lower power supply voltage V cc  you use, the lower the clipping limit will be and the more disturbances will be in the transmitted signal. 
     The output voltage U out  from a transmitter in a DMT, OFDM or similar system is approximately Gaussian distributed, see FIG. 3, i.e. it follows approximately the density function:                P                   (     U   out     )       =       1     σ                     2                 π                e         -       (       U   out     -   m     )     2       /   2                     σ   2                   (   2   )                                
     where the parameter m is a measure on where the peak of the curve is and the parameter σ is a measure on the shape of the peak. Both parameters m, σ are dependent on the application. 
     If, as an example, a low probability of clipping of 10 −8  is accepted, then the clip level will be at approximately 5,6σ a and thus the supply voltage V cc  must be at least 5,6σ. 
     However, one may note that most of the time the output signal U out  will be in the mid-range. It would thus be desirable to have a solution where a lower supply voltage is used most of the time and a high supply voltage is used only when it is strictly necessary. That would reduce the overall power dissipation in the line driver. 
     In FIGS. 4 a-c  is shown a part of the invention in the form of a voltage generating block  30 , which makes it possible to generate different magnitudes of output voltage, without having to use many power supplies. A first  21  and a second  22  switch are connected in series between a power supply V cc  and ground G. In parallel with the first  21  and second  22  switches a third  23  and fourth  24  switch are connected in the same way. A capacitor  25  is connected on one side to a first connection point  26  between the first  21  and the second  22  switch. On the other side the capacitor  25  is connected to a second connection point  27  between the third  23  and the fourth  24  switch. A capacitor voltage U c  is indicated over the capacitor  25  between the first  26  and second  27  connection point. The switches  21 ,  22 ,  23 ,  24  may preferably be switch-transistors. 
     To load the capacitor  25  the switches  21 ,  22 ,  23 ,  24  are switched as in FIG. 4 a.  The first  21  and the fourth  24  switch are closed, while the second  22  and the third  23  switch are open. This loads the capacitor  25  and the capacitor voltage U c  becomes approximately equal to the supply voltage V cc  minus losses in the switches  21 ,  24  and other losses. 
     When a positive voltage higher than the supply voltage V cc  is going to be used, the first  21  and the fourth  24  switch are opened, while the third switch  23  is closed, as in FIG. 4 b.  Then it is possible to take out a first voltage V max  between the first connection point  26  and ground G. The output voltage V max  is approximately equal to 2·V cc , due to the fact that the capacitor voltage U c ≈V cc  is added to the supply voltage V cc . 
     Of course the capacitor  25  will discharge, but if the double voltage only is used under a short time and the capacitor  25  then is recharged, the capacitor voltage U c  will not drop very much. This condition is fulfilled if voltage peaks are not coming very often, as is the case in e.g. multi-carrier systems. 
     If instead a negative voltage is needed after loading, then the first  21  and the fourth  24  switch are opened, while the second switch  22  is closed, as in FIG. 4 c.  Then it is possible to take out a second voltage V min  between the second connection point  27  and ground G. The second voltage V min  is approximately equal to −V cc , due to the fact that the capacitor voltage U c ≈V cc . 
     Thus, a voltage interval of V min  to V max , i.e. −V cc  to 2V cc , is obtained. This makes the idle voltage at V cc /2, independently of the magnitude of the output voltage. 
     An alternative to the embodiment in FIGS. 4 a-c  is to use two capacitors, i.e. a first capacitor for positive output voltages larger than the idle voltage and a second capacitor for positive voltages smaller than the idle voltages and for negative voltages. 
     One example on how the embodiment with one capacitor may be implemented in practice in a line driver is shown in FIG.  5 . The input signal U in , goes into a drive stage  31 . A first transistor  32  and a second transistor  33  are connected with their respective bases to the output side of the drive stage  31 . The voltage-generating block  30  from FIG. 4 a-c  has its first connection point  26  connected to the collector of the first transistor  32  and its second connection point  27  connected to the collector of the second transistor  33 . Further, the emitters of the two transistors  32 ,  33  are connected in a third connection point  34 . The output voltage U out  is taken out from said third connection point  34 . 
     When a positive output voltage higher than the idle voltage is needed then the first transistor  32  leads, but the second transistor  33  does not lead. When a positive output voltage lower than the idle voltage or a negative output voltage is needed then the second transistor  33  leads, but the first transistor  32  does not lead. In both cases the magnitude of the output voltage U out  is controlled from the drive stage  31  via the base current to the transistor  32 ,  33  in use. 
     When a positive output voltage higher than the supply voltage is needed, then the switches are switched as described in FIG. 4 b  and the first voltage V max  may be taken out from the first connection point  26 . Thus, the output signal U out  may become a value up to approximately the first voltage V max . 
     When a positive output voltage lower than the supply voltage or a negative output voltage is needed, then the switches are switched as described in FIG. 4 c  and the second voltage V min  may be taken out from the second connection point  27 . Thus, the output signal U out  may become a value to approximately the second voltage V min . 
     In the figure the first transistor is an NPN-transistor and the second transistor is a PNP-transistor. This is only an example. The man skilled in the art can easily use other transistors or equivalent means, to get the same function. 
     One or more control signals may be employed in order to control when and how the switches are going to switch and to control how the drive stage is to control the base currents when the voltage-generating block  30  is used and not, respectively. 
     Further, the output signal U out  may be fed back to the input side of the drive stage  31  and be used to ensure that the output signal U out  is a linear function of the input signal U in . 
     One advantage with the embodiment in FIG. 5 is that it is simple and that only two transistors need to be used. One disadvantage is that the current always has to pass switches also when no peak voltages are needed, with following losses in the switches. 
     A way of avoiding passing switches when no peak voltage is needed is shown in FIG.  6 . FIG. 6 is the same figure as FIG. 5, but with a third transistor  41  and a fourth transistor  42  added in parallel with the first transistors  32 ,  33 . Also for these transistors, the man skilled in the art can use other transistors or equivalent means, to get the same function. 
     The third transistor  41  is connected with its base to the output of the drive stage  31 , with its collector connected to the power supply V cc  and with its emitter connected to the third connection point  34 . The fourth transistor  42  is connected with its base to the output of the drive stage  31 , with its collector connected to ground and with its emitter connected to the third connection point  34 . 
     In this way the third and fourth transistor  41 ,  42  will be used in the mid voltage range, while the first and second transistor  32 ,  33  and the voltage-generating block  30  will be used when voltage peaks are needed. Since the switches are only passed when they are necessary, losses are further reduced. 
     In the figure the third transistor is an NPN-transistor and the fourth transistor is a PNP-transistor. This is only an example. The man skilled in the art can easily use other transistors or equivalent means, to get the same function. 
     In order to control the switches and the drive stage, a digital input signal U D  to the digital-to-analogue converter  7  may be used as in FIG.  7 . In a digital comparator  51  the digital input signal U D is compared to a first threshold V th1  and a second threshold V th2 . If the digital input signal U D is larger than the first threshold V th1 , then the switches are controlled so as to connect the capacitor to generate a first voltage V max , compare FIG. 4 b , and the output from the drive stage  31  is adjusted accordingly. 
     If the digital input signal U D is lower than the second threshold V th2 , then the switches are controlled so as to connect the capacitor  25  to generate a second voltage V min , compare FIG. 4 c , and the output from the drive stage  31  is adjusted accordingly. In the range between the first V th1  and the second V th2  threshold the capacitor  25  is recharged. 
     The comparator  51  may be implemented in hardware or software. To ensure that the switches are switched at right time a delay  52  may be introduced before the digital-to analogue converter  7 . 
     For the control it is also possible to use the analogue output from the digital-to-analogue converter, see FIG.  8 . The compare is in this case made in an analogue comparator  55 , but works otherwise as in FIG.  7 . This however requires a faster comparison than in FIG.  7 . 
     In practices the thresholds in the different embodiments will not be implemented to correspond to output voltages exactly to 0 V and to the supply voltage, but rather a little higher than 0 V and a little lower than the supply voltage, respectively. This applies particularly in the case with the analogue comparison, where it is an alternative or a complement to having a fast comparison. 
     To be able to output a large output voltage range, the line driver may be balanced, which is shown in FIG.  9 . Between the digital-to-analogue converter 7 and the output transformer  13  two line drivers are connected with 180° phase difference, which is schematically shown in FIG. 9 as a phase difference block  61 . The phase difference may be accomplished before or after one of the line drivers. The total output voltage difference then becomes two times that from a single line driver. In FIG. 9 is shown the embodiment from FIG. 5, but of course the embodiment from FIG. 6 or anything equivalent will do as well.

Technology Category: 4