Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a semiconductor device to reduce a self-aligned contact failure of a landing plug contact.  
       DESCRIPTION OF RELATED ARTS  
       [0002]     In a landing plug contact (LPC) module process of dynamic random access memory (DRAM) devices with a size of approximately 80 nm or lower, although the size of the devices has been reduced, a thickness of a gate spacer has not been decreased. Accordingly, it may be difficult to perform a LPC opening process and a gap-filling process.  
         [0003]     Particularly, in case of the DRAM devices, there may be a height difference between an active region and a field region when a recess gate is used to improve a refresh property. As a result, a difference in a stress of a silicide layer which forms a gate pattern may be generated. The difference in the stress of the silicide layer causes an excessive oxidation on sidewalls of the silicide layer and thus, a self-aligned contact (SAC) fail may often be induced.  
         [0004]      FIGS. 1A and 1B  are cross-sectional views illustrating a typical method for fabricating a semiconductor device.  
         [0005]     As shown in  FIG. 1A , a device isolation structure  11  is formed in a certain portion of a substrate  10  by performing a shallow trench isolation (STI) process. Then, a plurality of recesses  12  are formed in predetermined portions of the substrate  10 .  
         [0006]     A gate insulation layer  13  is formed over the above resulting structure. Afterwards, a plurality of recess gate lines G are formed over the gate insulation layer  13  being partially filled into the recesses  12 . Each of the recess gate lines G is formed by sequentially stacking the gate insulation layer  13 , a polysilicon layer  14 , a tungsten silicide layer  15 , a gate hard mask  16 , and an anti-reflective coating layer  17 .  
         [0007]     When a photoresist layer (not shown) is formed over the gate hard mask  16 , a photolithograph process is performed on thereafter. The photolithograph process can be easily performed due to the anti-reflective coating layer  17 . The anti-reflective coating layer  17  is formed of silicon oxynitride (SiON).  
         [0008]     After forming the recess gate lines G, a light oxidation process is performed at a temperature ranging from approximately 700° C. to approximately 900° C. As a result, an oxide layer  18  is formed on sidewalls of the polysilicon layer  14  and the tungsten silicide layer  15  exposed by the light oxidation process.  
         [0009]     The oxide layer  18  is excessively grown on both sidewalls of the recess gate lines G due to an abnormal oxidation of the tungsten silicide layer  15  during the light oxidation process.  
         [0010]     As described above, after performing a light oxidation process, an abnormal oxidation may occur in the tungsten silicide layer because the tungsten silicide layer has different levels of stress caused by a height difference between the recess gate and the device isolation structure. Afterwards, sidewalls of the tungsten silicide layer are more likely to be damaged during the landing plug contact (LPC) process. Accordingly, a SAC fail may be induced.  
         [0011]     A region where the oxide layer  18  is excessively grown over the sidewalls of the recess gate lines G is denoted with reference letter A.  
         [0012]     As shown in  FIG. 1B , an ion-implantation process is performed on the above resulting structure in which the oxide layer  18  is excessively formed due to the abnormal oxidation of the tungsten silicide layer  15 . Then, a buffer oxide layer  19  and a spacer nitride layer  20  are sequentially formed to reduce a stress of a nitride layer.  
         [0013]     The buffer oxide layer  19  and the spacer nitride layer  20  are formed over a projected profile shown as the region A in  FIG. 1A . Hence, the buffer oxide layer  19  and the spacer nitride layer  20  have the same projected profile as the region A. Reference letter B denotes a region where the buffer oxide layer  19  and the spacer nitride layer  20  are projected due to the excessive growth of the oxide layer  18 .  
         [0014]     During a landing plug contact (LPC) process, the region B is exposed too much. Thus, the spacer nitride layer  20  formed around the region B is etched and the buffer oxide layer  19  becomes exposed and etched. When the buffer oxide layer  19  is etched, an electric short-circuit may be generated between a landing plug and a gate.  
         [0015]     More specifically, after forming the spacer nitride layer  20 , an oxide-based inter-layer insulation layer (not shown) is formed. Afterwards, an etching process is performed to form a landing plug contact (LPC). During the etching process, the spacer nitride layer  20  formed around the projected region B is etched and as a result, the buffer oxide layer  19  also formed around the projected region B is exposed and etched. If a polysilicon layer for a landing plug is formed over the above resulting structure, a landing plug and a gate may be electrically short-circuited through the buffer oxide layer  19 . Accordingly, a self-aligned contact (SAC) fail may be induced. Also, the abnormal oxidation may take place by a reaction between silicon atoms of the tungsten silicide layer and oxygen gas used for the light oxidation process.  
       SUMMARY OF THE INVENTION  
       [0016]     It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device, wherein the method reduces a self-aligned contact fail of a landing plug contact.  
         [0017]     In accordance with one aspect of the present invention, there is provided a method for fabricating a semiconductor device, including: providing a substrate structure in which a plurality of gate lines are already formed; forming a capping layer over the substrate structure; oxidizing the capping layer; and forming an insulation layer over the oxidized capping layer.  
         [0018]     In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including: providing a substrate structure in which a plurality of recess gate lines are already formed; forming a nitride-based layer over the substrate structure; oxidizing the nitride-based layer; and forming an insulation layer over the oxidized nitride-based layer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0020]      FIGS. 1A and 1B  are cross-sectional views illustrating a typical method for fabricating a semiconductor device; and  
         [0021]      FIGS. 2A  to  2 C are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]     Hereinafter, detailed descriptions on certain embodiments of the present invention will be provided with reference to the accompanying drawings.  
         [0023]      FIGS. 2A  to  2 C are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.  
         [0024]     As shown in  FIG. 2A , a plurality of device isolation layers  22  are formed in certain portions of a substrate  21  through a shallow trench isolation (STI) process. Then, a plurality of recesses  23  are formed in predetermined portions of the substrate  21 .  
         [0025]     A gate insulation layer  24  is formed over the above resulting structure and afterwards, a plurality of recess gate lines G are formed over the gate insulation layer  24  being partially filled into the recesses  23 . Each of the recess gate lines G is formed by sequentially stacking the gate insulation layer  24 , a polysilicon layer  25 , a tungsten silicide layer  26 , a gate hard mask  27 , and an anti-reflective coating layer  28 .  
         [0026]     When a photoresist layer (not shown) is formed over the hard mask  27 , and a photolithograph process is performed on the hard mask  27  thereafter. The photolithography process can be easily performed due to the anti-reflective coating layer  27 . The anti-reflective coating layer  27  is formed of silicon oxynitride (SiON).  
         [0027]     A capping layer  29  is formed over a profile of the substrate  21  and the recess gate lines G. The capping layer  29  is formed to a thickness ranging from approximately 30 Åto approximately 80 Å. The capping layer  29  has the same thickness as an oxide layer formed through a light oxidation process of the typical method.  
         [0028]     The capping layer  29  includes a nitride-based material such as Si x N y , wherein x and y are natural numbers greater than approximately 1. For instance, the capping layer  29  is formed by using a mixture gas including silane (SiH 4 ), ammonia (NH 3 ), and nitrogen (N 2 ) at a temperature ranging from approximately 400° C. to approximately 600° C. Compared to the typical method, according to this embodiment of the present invention, the capping layer  29  is formed through a nitride layer deposition process and thus, silicon of the tungsten silicide layer  26  does not react with oxygen (O 2 ) As a result, the capping layer  29  can be stably formed over sidewalls of the tungsten silicide layer  26 .  
         [0029]     As shown in  FIG. 2B , a radical oxidation process is performed on the above resulting substrate structure  21  to oxidize the capping layer  29 . As a result, an oxide layer  29 A is formed. The nitride-based layer (i.e., the capping layer  29 ) is transformed to the oxide layer  29 A using O 2  ions and hydrogen (H 2 ) ions at a low pressure. In more detail, H 2  or H 2 O is mixed with O 2  (i.e., O 2 /H 2  or O 2 /H 2 O) at a pressure ranging from approximately 0.3 Torr to approximately 1.5 Torr and a temperature ranging from approximately 400° C. to approximately 700° C. Thus, the O 2  ions react with silicon included in a nitride layer to form a silicon oxide (SiO 2 ) layer. As a result, only the capping layer  29  is transformed to the oxide layer  29 A.  
         [0030]     The tungsten silicide layer  26  is capped by the nitride-based capping layer  29  during the radical oxidation process. Thus, the tungsten silicide layer  26  is not exposed to an oxidation reaction. Accordingly, an abnormal oxidation of a tungsten silicon layer often occurring in the typical method can be reduced. Specifically, the abnormal oxidation of a silicide layer can be reduced by performing an oxidation process at a low temperature not at a high temperature of approximately 700° C. or higher.  
         [0031]     As shown in  FIG. 2C , a spacer layer  30  is formed over a surface of the oxide layer  29 A. The spacer layer  30  includes a nitride-based material. Although not shown, an inter-layer oxide layer is formed over the substrate  21  and the recess gate lines G and then, a landing plug contact (LPC) process is performed to form a landing plug contact (LPC).  
         [0032]     As described above, after forming the recess gate lines G, a capping layer is formed and then, a radical oxidation process is performed at a low temperature ranging from approximately 400° C. to approximately 700° C. to oxidize the capping layer. As a result, an abnormal oxidation of a tungsten silicide layer can be reduced, and an oxide layer reducing stress on a substrate during a LPC process and damage caused during an ion-implantation process can be stably formed. Accordingly, a property of devices can be improved and a SAC fail of the LPC can be reduced.  
         [0033]     According to this embodiment of the present invention, a capping layer is formed over recess gate lines before performing a radical oxidation process. Then, an oxide layer is formed by using a radical oxidation process at a temperature ranging from approximately 400° C. to approximately 700° C. As a result, silicon atoms existing in a silicide layer of the typical method do not react with O 2  to reduce an oxidation. An abnormal oxidation of a tungsten silicide layer and a stress generated between a device isolation layer and a tungsten silicide layer can be reduced.  
         [0034]     The present application contains subject matter related to the Korean patent application No. KR  2005-0121689,  filed in the Korean Patent Office on Dec. 12, 2005, the entire contents of which being incorporated herein by reference.  
         [0035]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Technology Category: 5