Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional application of and claims priority to U.S. application Ser. No. 09/538,043, filed March 29, 2000. 
    
    
     GOVERNMENT SPONSORED RESEARCH 
     This invention was made with Government support under contract DAAHO 1-98 -C-R184 awarded by the U.S. Army aviation and Missile Command. The Government has certain rights in the invention. 
    
    
     BACKGROUND 
     The present disclosure generally relates to analog-to-digital converters, and specifically to establishing internal reference voltage and offset in such converters. 
     In typical analog-to-digital (A-to-D) conversion, reference voltage levels are used to generate a digital representation of an analog input signal. Dynamic range/signal resolution is often maximized when the expected range of the analog input signal matches the reference voltage level. 
     FIG. 1 shows one type of A-to-D converter  100  that uses a technique known as successive approximation. The operation of this A-to-D converter  100  is analogous to weighing an unknown object on a laboratory balance scale as  1, ½, ¼, ⅛, . . . {fraction (1 /n)} standard weight units. The largest weight is placed on the balance pan first; if it does not tip, the weight is left on and the next largest weight is added. If the balance does tip, the weight is removed and the next one added. The same procedure is used for the next largest weight and so on down to the smallest. After the n-th standard weight has been tried and a decision made, the weighing is finished. The total of the standard weights remaining on the balance is the closest possible approximation to the unknown weight. This weighing logic is implemented as a D-to-A converter  102  in FIG.  1 . 
     One embodiment of the successive approximation A-to-D converter  200  is illustrated in FIG. 2. A bank of capacitors  202  and switches  204  implement the weighing logic  201  with successively smaller size capacitors. A capacitor of size 2 n−1 *C represents the most-significant bit (MSB) while a capacitor of size C represents the least-significant bit (LSB) The value n is the number of binary bits in an A-to-D converter  200 . Maximum capacitance provided at the input signal node  214  is 2 n −1) * C=C+ . . . +2 n−2 *C+2 n−1  * C. This is equivalent to a digital value of all ones. Therefore, the LSB voltage is          V   LSB     =         V   MAX       C   MAX       =         V   REF         (       2   n     -   1     )     *   C       .                              
     An input signal (V IN )  206  is sampled onto the bank of capacitors  202  and a comparator  208 . Initially, the bottom plates of the capacitors  202  are grounded. During the conversion process, the bottom plates of the capacitors  202  are successively connected to the reference voltage (V REF )  210 . Corresponding bits are derived and stored in latches  212 . 
     A reference voltage level is generally adjusted and programmed to the input signal level. Since this reference voltage level is often adjusted to the full voltage swing of the input signal, the reference voltage must either be supplied to the A-to-D converter  200  from off-chip or generated on-chip using reference circuits. 
     SUMMARY 
     The present application defines an A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply. 
     The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor. 
     The logic circuit is coupled to the comparator, and has successively smaller size capacitors. Each capacitor is connected to at least one switch. The switch is configured to successively connect each capacitor to different levels of the supply signal. The adjustable capacitor is also coupled to the comparator, and is configured to provide additional capacitance. The additional capacitance reduces full swing of the adjustable reference level to enable the logic circuit to operate with the supply signal. 
     The present application also defines a method of converting analog signal to digital signal. The method includes adjusting a reference capacitor at an input signal node to appropriately reduce full swing of a reference level. Conversion capacitors are selectively connected to a supply signal to program the reference level. The method also includes comparing an input signal to the programmed reference level, and reading a digital output value into latches if the comparison results in a match. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Different aspects of the disclosure will be described in reference to the accompanying drawings wherein: 
     FIG. 1 is a block diagram of a successive approximation A-to-D converter; 
     FIG. 2 is a detailed block diagram of a successive approximation A-to-D converter; 
     FIG. 3 is a schematic diagram of an A-to-D converter system according to one aspect; 
     FIG. 4 is a flowchart of an A-to-D conversion process according to another aspect; 
     FIG. 5 shows an example of a CMOS image sensor integrated circuit having the A-to-D converter of the present invention; 
     FIG. 6 is a block diagram of a pixel array and associated readout circuit and an A-to-D converter; and 
     FIG. 7 is a schematic diagram of an A-to-D converter system according to a further aspect of the present invention. 
    
    
     DETAILED DESCRIPTION 
     The present application defines an A-to-D converter system that provides an efficient solution to the problem of supplying the reference voltage. In one aspect, the solution considers implementation of the A-to-D converter in compact micro-power level circuits. 
     For example, an array of A-to-D converters is used in CMOS image sensors. These sensors can include active pixel sensors (APS) and charge-coupled devices (CCD). The image sensor is arranged into an array of column pixels and row pixels. Each pixel collects electrical charge when exposed to light. Control signals provided to the pixels periodically enable the controllers to transfer the collected charge to the array of A-to-D converters. The collected charge is converted to digital data and stored in the column-parallel latches. 
     Since the available chip area and power is limited in column parallel circuits, it is advantageous to provide a substantially compact design where the reference voltage uses the existing supply voltage. Further, by adjusting the total capacitance of the binary-weighted conversion capacitors, the effective reference voltage can be changed. 
     A schematic diagram of an embodiment of the A-to-D converter system  300  is shown in FIG.  3 . The converter system  300  eliminates the need for the internally-generated or externally-supplied reference voltage  210  by using the rail supply voltage (V DD )  304 . The converter system  300  allows the capacitors  302  to use the existing supply voltage  304  by providing an adjustable reference capacitor (C REF )  308  at the positive input signal node  306 . Initially, the bottom plates of the capacitors  302  are grounded. During the conversion process, the bottom plates of the capacitors  302  are successively connected to the supply voltage  304 . 
     The adjustable reference capacitor  308  provides additional capacitance at the positive input signal node  306 . Thus, the maximum capacitance at the positive input signal node  306  increases to 
     
       
         2 n −1)* C+C   REF .  (2) 
       
     
     The least-significant bit (LSB) voltage is equal to                V   LSB     =         V   MAX       C   MAX       =         V   DD           (       2   n     -   1     )     *   C     +     C   REF         .               (   3   )                                
     In one example, if the value of C REF    308  is adjusted to equal the total capacitance ( 2   n −1)*C) of the conversion capacitors  302 , the maximum capacitance at the positive input signal node  306  becomes 2*(2 n −1)*C. Therefore, the effective reference level of the A-to-D converter  300  that is required to match the input signal swing  310  is reduced to one-half that of the conventional A-to-D converter  200 . Further, the actual capacitance value of C REF    308  can be adjusted to reduce the effective reference voltage level by any amount within some tolerance value. 
     In some embodiments, the metal-oxide silicon field-effect transistor (MOSFET) switches  312  are appropriately modified for a low-voltage application when the supply voltage  304  is used in place of the internally-generated or externally-supplied reference voltage  210 . For example, when the supply voltage  304  is about 1.2 volts and the threshold voltages of the switches  312  are more than 0.6 volts, the n-channel switches cannot effectively pass voltages close to one-half of the supply voltage  304 . Therefore, the p-channel MOSFET switches  312  are used to connect the bottom plates of the conversion capacitors  302  to the supply voltage  304 . 
     FIG. 4 shows a flowchart of an A-to-D conversion process. According to an illustrated embodiment, the conversion process uses the supply voltage instead of the externally-supplied or internally-generated reference voltage. 
     At step  400 , a reference capacitor at the positive input signal node is adjusted to appropriately reduce an effective reference signal level. Once the reference capacitance is adjusted to some optimum value, the conversion capacitors are selectively connected to the supply voltage at step  402 . The selective connection programs the reference signal level. At step  404 , the input signal is compared to the programmed reference signal level. If the comparison match is found (step  406 ), a digital output value is read out from the latches at step  408 . 
     Although the above-described solution slightly increases the dynamic power consumption in an A-to-D converter, the solution reduces the overall system power consumption. This solution is especially beneficial to low-voltage, low-power CMOS imagers because the supply voltage (approximately 1.2 to 1.5 volts) is close to the required reference voltage (approximately 1.0 volt). Other advantages include overall circuit simplification and no decoupling capacitors that are required to stabilize the reference voltage. 
     FIG. 5 shows an example of a CMOS image sensor integrated circuit chip  500 . The chip  500  includes an array of active pixel sensors  502  and a controller  504 . The controller  504  provides timing and control signals to enable read out of signals stored in the pixels. For some embodiments, arrays can have dimensions of 128×128 or some larger number of pixels. However, in general, the size of the array  502  will depend on the particular implementation. The image array  502  is read out a row at a time using a column-parallel readout architecture. The controller  504  selects a particular row of pixels in the array  502  by controlling the operation of the vertical addressing circuit  506  and row drivers  508 . Charge signals stored in the selected row of pixels are provided to a readout circuit  510 . The pixels read from each of the columns can be read out sequentially using a horizontal addressing circuit  514 . Differential pixel signals (V in   + , V in   − ) are provided at the output of the readout circuit  510 . The differential pixel signals are converted to digital values by an A-to-D converter  512  having a reference capacitor. This capacitor can be used to reduce the effective capacitance at the positive input signal node. 
     As shown in FIG. 6, the array  502  includes multiple columns  600  of CMOS active pixel sensors  602 . Each column includes multiple rows of sensors  602 . Signals from the active pixel sensors  602  in a particular column can be read out to a readout circuit  604  associated with that column. Signals stored in the readout circuits  604  can be read to an output stage  606 . This output stage  606  is common to the entire array of pixels  502 . The analog output signals are sent to a differential A-to-D converter  608 . 
     A further aspect of the A-to-D converter  700  is shown in FIG.  7 . An offset signal is provided at the negative input signal node. In one embodiment, the offset signal is generated by an offset adjustment circuit  702  to remove dark signals appearing on the pixel array  502 . In other embodiments, the offset signal electronically increases the brightness of the image or compensates for some artificial offset added in the signal processing chain in the readout circuit  510 . The offset adjustment circuit  702  includes two capacitors  704 ,  706 . A larger-valued capacitor  704  is connected between the negative input signal node  708  and ground. A smaller-valued capacitor is, in general, a variable capacitor  706 . The top plate of the variable capacitor  706  is connected to the negative input signal node  708 . The bottom plate of the variable capacitor  706  is connected either to a reference voltage or to ground. 
     When a positive offset is desired during sampling, an Offset Enable signal  710  is asserted. Otherwise, if a negative offset is desired during sampling, an Offset Clamp signal  712  is asserted. This signal is then de-asserted to turn the clamp switch  716  off and turn the enable switch  718  on. During conversion, if a positive offset is desired, an Offset Clamp signal  712  is asserted. 
     Other embodiments and variations are possible. For example, a variable offset can be achieved by either using the variable capacitor  706  or a variable reference voltage  714 . Further, the reset capacitor  704  can be omitted if the offset signal is relatively large compared to the full input voltage swing. Moreover, all references to voltages are for illustrative purposes only. The term “voltage” can be replaced with “current”, “power”, or “signal” where appropriate. 
     All these are intended to be encompassed by the following claims.

Technology Category: 5