Patent Document

BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a phase offset tracking module and method for tracking the phase offset caused by residual frequency offset in OFDM based transmission systems, and in particular, to a phase offset tracking module and method for tracking a phase offset in a receiver.  
         [0003]     2. Description of the Related Art  
         [0004]     In a related receiver, the phase offset tracking module (e.g. digital phase lock loop (DPLL)) is utilized to track a phase offset in each received symbol, especially in an Orthogonal Frequency Division Multiplexing (OFDM) receiver. The phase offset tracking module, however, may take a long convergence time and degrade performance for initial symbols during acquisition stage. Additionally, the related DPLL can not be applied directly in some receivers (e.g. Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) receiver).  
       BRIEF SUMMARY OF INVENTION  
       [0005]     A detailed description is given in the following embodiments with reference to the accompanying drawings.  
         [0006]     An object of the invention is to provide a phase offset tracking method for tracking a phase offset in an Orthogonal Frequency Division Multiplexing receiver. The OFDM receiver receives various kinds of input symbols and compensates a phase offset in each symbol. Each input symbol comprises an input phase offset. The phase offset tracking method comprises: utilizing a first(loop) and a second(accumulate) registers to respectively store a first and a second register values; estimating an error phase according to a phase compensated OFDM symbol and its associated pilots; setting the first and second register values initially according to the value of estimated error phase of a first symbol; after these initial settings, the following operations are the same as traditional DPLL, filtering the estimated error phase to generate a filtered signal according to the first register value; accumulating the filtered signal continuously according to the second register value to generate the output phase; and compensating the phase offset in each input symbol according to the output phase.  
         [0007]     Another object of the invention is to provide a phase offset tracking method for tracking a phase offset in a Multi-band Orthogonal Frequency Division Multiplexing receiver. The phase offset tracking method comprises: utilizing different loop and accumulate registers to respectively store different first and second register values in different bands; estimating an error phase according to an OFDM symbol and its associated pilots; setting different first and second register values initially according to the estimated error phases of a first symbol in different bands; filtering the estimated error phase to generate a filtered signal according to the first register value of a current band; accumulating the filtered signal continuously according to the second register value of the current band to generate the output phase; and compensating the phase offset in each input symbol of the current band according to the output phase. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0008]     The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0009]      FIG. 1  shows a block diagram of an OFDM receiver according to a first embodiment of the invention;  
         [0010]      FIG. 2  shows a timing diagram of register values R A  (accumulate register) and R L  (loop register) in the phase offset tracking module, and the phase offset input phase θ i , of each symbol according to a first embodiment;  
         [0011]      FIG. 3  shows another timing diagram of register values R A  and R L  in the phase offset tracking module, and the residual error phase θ e  of each symbol according to a second embodiment;  
         [0012]      FIG. 4A  shows different TFC numbers representing different frequency hopping sequences;  
         [0013]      FIG. 4B  shows a timing diagram of a received packet;  
         [0014]      FIG. 5  shows a block diagram of the phase offset tracking module for MB-OFDM system in  FIG. 1 ;  
         [0015]      FIG. 6  shows a timing diagram of the natural frequency variation according to a third embodiment;  
         [0016]      FIG. 7A  show timing diagrams of updating the register values R A  and R L  with different TFC numbers according to a fourth embodiment;  
         [0017]      FIG. 7B  show timing diagrams of updating the register values R A  and R L  with different TFC numbers according to a fifth embodiment. 
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0018]     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.  
         [0019]     Please refer to  FIG. 1 .  FIG. 1  shows a block diagram of an OFDM receiver  100  according to a first embodiment of the invention. The OFDM receiver  100  comprises an analog-to-digital converter (ADC)  110 , a look up table (LUT)  120  to transform the compensated output phase θ o,N  to its corresponding sine and cosine values, a complex multiplier  130 , a Fast Fourier Transform (FFT) module  140 , a frequency-domain equalizer (FEQ)  150 , a directed phase offset symbol compensator  160 , a demodulator  170 , and a phase offset tracking module  180 . The ADC  110  converts analog packets to digital packets. The multiplier  130  multiples a digital packet (comprising a plurality of input symbols, r N  is the Nth input symbol and θ i,N  is the input phase offset corresponding to r N  and naturally, θ i,N  is equal to θ i,N  plus Δ, where Δ is the unit phase offset) by a compensating signal (wherein, the phase of the compensating signal is called the output phase θ o,N  corresponding to the Nth symbol r N ) from the LUT  120  to obtain a phase offset compensated signal (r′ N  is the Nth compensated symbol and θ e,N  is equal to θ i,N  minus θ o,N  is the residual error phase corresponding to r′ N ). The FFT module  140  and the FEQ  150  transfers and equalizes the phase offset compensated signal to generate the frequency-domain signal (R N  is the Nth frequency-domain symbol and θ e,N  is the residual error phase of R N ). A detailed description of elements  140 ,  150 ,  170  (familiar to those skilled in the art) is omitted and the element  160  will be described later (with  FIG. 3 ). The phase offset tracking module  180  outputs a phase offset output signal (utilized to generate the compensated signal, θ o ,N is the output phase of the Nth symbol) according to a plurality of error phases (θ c′,N  is the Nth estimated error phase extracted from the element  182 ). A detailed description of the phase offset tracking module  180  is provided in the following.  
         [0020]      FIG. 2  shows a timing diagram of register values R A  and R L  in the phase offset tracking module  180 , and the phase offset input phase θ i  of each symbol according to a first embodiment. The phase offset tracking module  180  is a modified digital phase lock loop (DPLL) utilized to track the phase offset of each OFDM symbol comprising a phase offset estimator  182 , a loop filter  184 , and an accumulator  186 . The phase offset estimator  182  estimates the error phase θ e  corresponding to each symbol. The accumulator  186  accumulates input data continuously to generate the output phase θ o  corresponding to each symbol to compensate the phase offset of each input symbol in the digital packet ( FIG. 1 ). Please refer to  FIG. 2 . Where Csym represents channel estimation symbols and Hsym represents Header symbols. At time T 1 , in ideal case, after Hsym 1  has been processed, we can get the estimated phase error θ e′,T1  at the value of the unit phase-error Δ(θ e′,T1 =θ e,T1 =θ i1 −0=Δ), then the register value R L  utilized in the loop filter  184  is set to the unit phase error Δ and the register value R A  utilized in the accumulator  186  is set to 2Δ by force after the first coming header symbol Hsym_ 1  has been processed. At time T 2 , after Hsym 2  has been processed, we can estimate the phase error θ e,T2  at the value of zero (θ e′,T2 =θ e,T2 =θ i,T2 −R A,T1 =2Δ−2Δ=0), so the register value R A  is equal to 3Δ(R A,T2 =R A,T1 +R L,T1 +θ e′,T2 ×(c1+c2)=2Δ+Δ+0×(c1+c2)=3Δ) after the second coming header symbol Hsym_ 2  has been processed. At time T 3 , the register value R A  is equal to 4Δ after the second coming header symbol Hsym_ 3  has been processed. Compared with the related art, the convergence time of the phase offset tracking module  180  is shorter to only one symbol duration due to the forced setting of the register value R L  and R A  at time T 1  (in stable condition, R L,N =Δ, θ e′,N=0 , R A,N =R A,N−1 +Δ). In a traditional DPLL, the register values R L  equals to the value C 1 ×Δ and R A  equals to the value C 2 ×Δ at time T 1  and hence require longer convergence time.  
         [0021]     Please refer to  FIG. 3 .  FIG. 3  shows another timing diagram of register values R A  and R L  in the phase offset tracking module  180 , and the phase offset input phase θ i  of each symbol according to a second embodiment. In the duration T 0 ˜T 1 , the inaccuracy of residual phase offset (θ e,T1 =θ i1 −0=Δ) may degrade the performance since the operation of the DPLL is not in stable condition and the first coming header symbol (Hsym_ 1 ) must be further compensated. The phase offset estimator  182  gets an estimated error phase θ e′,T1  of the first incoming header symbol (Hsym_ 1 ) and the multiplier  162  multiples the first coming header symbol by the estimated error phase θ e′,1  from the transformer  164  to further compensate the first coming header symbol, and for performance purpose, we can extend the direct phase compensation time to further more symbols to prevent the performance degrade due to the residual phase error in non-convergence symbols. Compared with the phase offset tracking module  180  in the first embodiment, the key difference is that the phase offset tracking module  180  in this embodiment further compensates the initial coming header symbols. The above-mentioned phase offset tracking modules (in the first and second embodiments) are utilized in the OFDM receiver. Some phase offset tracking modules utilized in another MB-OFDM receiver are provided in the following.  
         [0022]     The Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) technology is a next generation OFDM technology (e.g. IEEE 802.15 for MB-OFDM or IEEE 802.11n for next generation WLAN), in which the carrier frequency always varies (hops) with time. The band hopping sequence is determined according to a current time-frequency code (TFC) number in a packet. Please refer to  FIGS. 4A and 4B  at the same time.  FIG. 4A  shows different TFC numbers representing different frequency hopping sequences. For example, if the TFC number is 1, the band hopping sequence is BAND_ID_ 1 , BAND_ID_ 2 , and BAND_ID_ 3 ; if the TFC number is 2, the band hopping sequence is BAND_ID_ 1 , BAND_ID_ 3 , and BAND_ID_ 2 . Please refer to  FIG. 4B .  FIG. 4B  shows a timing diagram of a received packet, in which the TFC number is equal to 1. The packet comprises a plurality of synchronization symbols S sym , a plurality of channel estimation symbols C sym , a plurality of header symbols H sym , and a plurality of payload symbols P sym . At time T 1 , the carrier frequency of the symbol falls in the band BAND_ID_ 1 ; at time T 2 , the carrier frequency of the symbol hops to another band BAND_ID_ 2 ; at time T 3 , the carrier frequency of the symbol hops to another BAND_ID_ 3 . The hopping process will be repeated again and again according to the specific hopping sequence. MB-OFDM is an efficient multi-channel modulation technology; however, the phase offset of each symbol may accumulate and decrease performance. Hence a method for compensating phase offset is desirable.  
         [0023]     Please refer to  FIG. 5 .  FIG. 5  shows a block diagram of the phase offset tracking module  180  in  FIG. 1 . The key difference with the previous embodiments is that there are multiple loop and accumulator registers which are responsible for different bands. The phase offset estimator  510  estimates the error phase θ e  corresponding to each symbol. The loop filter  520  and the accumulator  530  further comprise multiplexers (MUX)  521  and  522 , and multiplexers  531  and  532 . These multiplexers always select proper register values R L  and R A  corresponding to the current band (e.g. BAND_ID_ 1 , BAND_ID_ 2 , or BAND_ID_ 3 ) when switching bands. For example, if the current band is BAND_ID_ 1 , these multiplexers select R L1  and R A1  as register values R L  and R A  to solve the phase jumping phenomenon that occurs in band switching.  
         [0024]     Please refer to  FIG. 6 .  FIG. 6  shows a timing diagram of the natural frequency (change according to the values of coefficients C 1  and C 2 ) variation according to a third embodiment. When the current received symbol is header symbol H sym , the natural frequency f nature  is set to high and used in acquisition stage. When the current received symbol is payload symbol P sym , the natural frequency f nature  is set to low and used in tracking stage. Compared with the related art, the two-level natural frequency of the DPLL meets the requirement of residual phase offset in specific transmission modes to improve the performance.  
         [0025]     Please refer to  FIG. 7A  and  FIG. 7B  at the same time.  FIG. 7A  and  FIG. 7B  show timing diagrams of updating the register values R A  and R L  with different TFC numbers according to a fourth and a fifth embodiments, respectively. Because all BAND_ID s are the same, take band BAND_ID_ 1  symbols as an example, the updated register values R A1  and R L1  are shown in  FIG. 7A  (TFC number=1, TFC number=3 is the same case). The error phase θ e1  of the band BAND_ID_ 1  satisfies the following formula:  
         θ     e   ⁢           ⁢   1       =     {             θ     i   ⁢           ⁢   1       -     R         A   ⁢           ⁢   1     ,   1     ⁢                         when   ⁢           ⁢   C_sym   ⁢           ⁢   %   ⁢           ⁢   6     =   0                 θ     i   ⁢           ⁢   1       -     R         A   ⁢           ⁢   1     ,   2     ⁢                         when   ⁢           ⁢   C_sym   ⁢           ⁢   %   ⁢           ⁢   6     =   3                 
 
         [0026]     Wherein θ i1  is the input phase of the band BAND_ID_ 1  symbols and R A1  is the register value of the band BAND_ID_ 1 . At time T 1 , the register value R L1  utilized in the loop filter  520  is set to 6Δ by force and the register values R A1,1  and R A1,2  utilized in the accumulator  530  are respectively set to 10.5Δ and 13.5Δ by force after the first and second coming header symbols (H 0  and H 3 ) are processed (at time T 01  and T 02 ). At time T 1 , the averaged estimated error phase θ e1 , of the band BAND_ID_ 1  is estimated according to the equation: θ e1′,T1 =(θ e1′,T01 +θ e1′,T02 )/2={(θ i1,T01 −R A1,1 )+(θ i1,T02 −R A1,2 )}/2={(4.5Δ−0)+(7.5Δ−0)}/2=6Δ. At time T 2 , likes the operations of the related art, the register values R A1,1  and R A1,2  are accumulated naturally (equal to 16.5Δ=10.5Δ+6Δ and 19.5Δ=13.5Δ+6Δ) and do not need to be set by force anymore (only set by force in the first time at time T 1  in order to reduce the convergence time). At time T 2 , the averaged estimated error phase θ e1′  of the band BAND_ID_ 1  is estimated according to the equation: θ e1′,T2 =(θ e1′,T03 +θ e1′,T04 )/2={(θ i1,T03 −R A1,1 )+(θ i1,T04 −R A1,2 )}/2={(10.5Δ−10.5Δ)+(13.5Δ−13.5Δ)}/2=0. A detailed description of setting the register values by force in the first time (at time T 1 ) is provided in the following.  
         [0027]     The value 6Δ utilized to set the register value R L1  is calculated according to the first and second coming header symbols (H 0  and H 3 ). As shown in the figure, since the distance between T o,0 , and T o,1  is 4.5 symbols, the input phase offset θ i1  of the first coming header symbol Hsym_ 1  is 4.5Δ (at time T 01 ) and the input phase offset θ i1  of the second coming header symbol Hsym_ 1  is 7.5Δ (at T 02 ). The value 6Δ is obtained by taking average value of the first and second coming header symbols Hsym_ 1  ((7.5+4.5)/2=6). After the value 6Δ is obtained, the corresponding values 10.5Δ(2*R L1 −R L1 /4=2*6Δ−6Δ/4) and 13.5Δ(2*R L1 +R L1 /4=2*6Δ+6Δ/4) utilized to set the register values R A1,1  and R A1,2  are then obtained.  
         [0028]     Please refer to  7 B. Still taking band BAND_ID_ 1  symbols as an example, the updated register values R A1  and R L1  are shown in  FIG. 7B  (TFC number=1). The phase offset error signal θ e1  of the band BAND_ID_ 1  satisfies the following formula: 
 
θ e1 =θ i1   −R   A1  
 
         [0029]     Wherein θi 1  is the phase offset input signal of the band BAND_ID_ 1  symbols and R A1  is the register value of the band BAND_ID_ 1 . At time T 1 , the register value R L , utilized in the loop filter  520  is set to 6Δ by force and the register values R A1  utilized in the accumulator  530  is set to 12Δ by force after the first and second coming header symbols (H 0  and H 1 ) are processed (at time T 01  and T 02 ). At time T 1 , the averaged estimated error phase θ e1′  of the band BAND_ID_ 1  is estimated according to the equation: θ e1′,T1 =(θ e1′,T01 +θ e1′,T02 )/2={(θ i1,T01 −R A1,1 )+(θ i1,T02 −R A1,2 )}/2={(5.5Δ−0)+(6.5Δ−0)}/2=6Δ. At time T 2 , the register value R A1  is accumulated naturally (equal to 18Δ=12Δ+6Δ) and do not need to be set by force anymore (only set by force in the first time at time T 1  in order to reduce the convergence time). At time T 2 , the averaged estimated error phase θ e1′  of the band BAND_ID_ 1  is estimated according to the equation: θ e1′,T2 =(θ e1′,T03 +θ e1,T04 )/2={(θ i1,T03 −R A1,1 )+(θ i1,T04 −R A1,2 )}/2={(11.5Δ−12Δ)+(12.5Δ−12Δ)}/2=0. A detailed description of setting the register values by force in the first time (at time T 1 ) is provided in the following.  
         [0030]     The value 6Δ utilized to set the register value R L1  is calculated according to the first and second coming header symbols (H 0  and H 1 ). As shown in the figure, the input phase offset θ i1  of the first coming header symbol Hsym_ 1  is 5.5Δ (at time T 01 ) and the input phase offset θ i1  of the second coming header symbol Hsym_ 1  is 6.5Δ (at T 02 ). The value 6Δ is obtained by taking average value of the first and second coming header symbols Hsym_ 1  ((5.5+6.5)/2=6). After the value 6Δ is obtained, the corresponding value 12Δ (2*R L1 ) utilized to set the register values R A1  is then obtained. Because the BAND_IDs are identical for TFC Number 5-7, we can use only one loop and accumulate registers and do phase tracking symbol by symbol or just use one of the two phase tracking methods described above.  
         [0031]     Compared with the related art, the convergence time of the phase offset tracking module in the invention is much shorter due to the force setting of registers inside. Hence performance can be increased. Additionally, the phase offset tracking modules can be utilized in the OFDM receiver or the MB-OFDM receiver in different embodiments.  
         [0032]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Category: 5