Patent Document

TECHNICAL FIELD 
       [0001]    This disclosure relates to the field of time of flight ranging systems, and, more particularly, to electronic device packages containing time of flight ranging systems and associated methods of making those electronic device packages. 
       BACKGROUND 
       [0002]    Time of flight ranging systems are now used in a variety of commercial and consumer products. A typical time of flight ranging system includes a ranging light emitter, such as a laser, that emits pulses of light. This light travels toward a target, and some of the light reflects off the target surface and returns to the time of flight ranging system where it is detected by a reflected light detector. Since the speed of light is known, by precisely measuring the elapsed time between emission of the light and detection of the reflected light, the distance between the time of flight ranging system and the target can be determined. 
         [0003]    Particularly in the realm of consumer products, there is an ever present desire for miniaturization of components. Therefore, new developments in packaging arrangements and methods for building those packaging arrangements are desired for time of flight ranging systems. 
       SUMMARY 
       [0004]    This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter. 
         [0005]    Disclosed herein is an electronic device having a substrate, and an integrated circuit disposed within the substrate and having a top surface. The integrated circuit may be a laser emitting integrated circuit or a reflected light detector. A first interconnect layer is formed on the top surface of the substrate. A first optically transparent layer is formed on the top surface of the substrate and covering the top surface of the integrated circuit. A second interconnect layer is formed on a top surface of the first optically transparent layer. The second interconnect layer is patterned so as to not obstruct light traveling to or from the top surface of the integrated circuit through the first optically transparent layer. 
         [0006]    Also disclosed herein is an electronic device having a substrate, with a laser emitting integrated circuit disposed within the substrate and having a top surface. A first interconnect layer is formed on a top surface of the substrate, and a first optically transparent layer formed on the top surface of the substrate and covering the top surface of the laser emitting integrated circuit. A second interconnect layer is formed on a top surface of the first optically transparent layer. The second interconnect layer is patterned so as to permit light emitted from the top surface of the laser emitting integrated circuit to pass through the first optically transparent layer and exit the electronic device. Another electronic device disclosed herein includes a substrate, with a reflected light detector disposed within the substrate and having a top surface. A first interconnect layer is formed on the top surface of the substrate, and a first optically transparent layer is formed on a top surface of the substrate and covering the top surface of the reflected light detector. A second interconnect layer is formed on a top surface of the first optically transparent layer. The second interconnect layer is patterned so as to permit light to pass through the first optically transparent layer and reach the reflected light detector. 
         [0007]    Also disclosed herein is a method of making the electronic device. The method includes forming a first interconnect layer on a substrate, and forming a cavity in the substrate. A bottom side of the substrate is laminated so as to cover a bottom side of the cavity, and an integrated circuit is placed within the cavity of the substrate. A first optically transparent layer is disposed on the top surface of the substrate and covering a top surface of the integrated circuit. A second interconnect layer is disposed on a top surface of the first optically transparent layer in a pattern that does not obstruct light traveling to or from the top surface of the integrated circuit. The integrated circuit is a laser emitting integrated circuit or a reflected light detector. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure where either a VCSEL or time of flight sensor has terminals on a top side thereof and is packaged within a substrate. 
           [0009]      FIG. 2  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure where both a VCSEL and a time of flight sensor is packaged within a substrate. 
           [0010]      FIG. 3  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure where either a VCSEL or time of flight sensor has terminals on top and bottom sides thereof and is packaged within a substrate. 
           [0011]      FIG. 4  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure with either a VCSEL or time of flight sensor similar to that of  FIG. 1  but where the first optically transparent layer has been thinned adjacent a top surface of the VCSEL or time of flight sensor. 
           [0012]      FIG. 5  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure with either a VCSEL or time of flight sensor similar to that of  FIG. 1  but where the first optically transparent layer has been removed adjacent a top surface of the VCSEL or time of flight sensor. 
           [0013]      FIG. 6  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure with either a VCSEL or time of flight sensor similar to that of  FIG. 1  but where a lens covers a portion of the top surface of the chip. 
           [0014]      FIGS. 7-17  are a series of schematic cross sectional diagrams showing formation of the electronic device of  FIG. 1 . 
           [0015]      FIG. 18  is a schematic cross sectional diagram of an electronic device in accordance with this disclosure similar to that of  FIG. 1  but where a lens covers a portion of the top surface of the chip and is in turn covered by the first optically transparent layer. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    The present description is made with reference to the accompanying drawings, in which example embodiments are shown. However, many different embodiments may be used, and thus the description should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and elements separated in number by century are similar. 
         [0017]    With initial reference to  FIG. 1 , an electronic device  100  is now described. The electronic device  100  includes a chip  110 , such as one incorporating a vertical cavity surface emitting laser (VCSEL) diode or a time of flight sensor (such as a single photon avalanche diode), embedded within a substrate  102 . In the case where the chip  110  includes a VCSEL diode, it emits laser light from its top surface, and in the case where the chip  110  includes a time of flight sensor, it senses light impinging upon its top surface. The chip  110  has terminals  112   a ,  112   b  extending from an upper surface thereof. The size of the chip may range from 0.8 mm×0.8 mm to 0.15 mm×0.15 mm, with a thickness ranging between 0.1 mm to 0.3 mm. 
         [0018]    The substrate  102  may be comprised of any suitable substrate material, such as one meeting the known FR4 standards, and may have a size ranging from 5.0 mm×4.0 mm to 2.0 mm to 3.0 mm, with a thickness ranging between 400 μm to 300 μm. 
         [0019]    Interconnect layer  104  is formed on the top surface of the substrate  102 , while interconnect layer  106  is formed on the bottom surface of the substrate  102 . The interconnect layers  104  and  106  may be constructed from copper or other suitable materials, with thicknesses on the order of 35 μm. 
         [0020]    An optically transparent layer  114  is formed on the top surface of the substrate  102 , covering the top surface of the chip  110  as well as the interconnect layer  104 . The top surface of the optically transparent layer  114  is shown as even with the top surface of the terminals  112   a ,  112   b  of the chip  110 , although in some instances may be uneven such that access to the terminals  112   a  and  112   b  is easily provided. Similarly, an optically transparent layer  118  is formed on the bottom surface of the substrate  102 , covering the bottom surface of the chip  110  as well as the interconnect layer  106 . 
         [0021]    The optically transparent layers  114 ,  118  are to be transparent or permissive to the passing of light of the same optical wavelength of that emitted by, or detected by, the chip  110 . One suitable material from which the optically transparent layers  114 ,  118  may be constructed from build-up film, such as ABF, although any suitable material may be used. The optically transparent layers  114 ,  118  may have a thickness on the order of 25 μm. 
         [0022]    An interconnect layer  116  is formed on the top surface of the optically transparent layer  114 , and an interconnect layer  120  is formed on the bottom surface of the optically transparent layer  118 . The interconnect layers  116 ,  120  may be constructed from copper or other suitable materials, with thicknesses on the order of 40 μm. 
         [0023]    Vias  197  may extend through the optically transparent layers  114  and  118  so as to respectively connect the interconnect layers  104  and  116 , and  106  and  110 . 
         [0024]    Metallic coating layers  128  and  126  are respectively formed on the outer surfaces of the interconnect layers  116  and  120 . The metallic coating layers  128 ,  126  may be constructed from NiAu and function to protect the exposed surfaces of the interconnect layer  116  and  128 . 
         [0025]    The use of the optically transparent layer  114 , together with the patterning of the interconnect layers  104  and  116 , permit the entry and exit of light into the chip  110 , making the electronic device  100  usable and useful for performing time of flight ranging. 
         [0026]    Other advantages of this design include a higher thermal stability due to the embedding of the chip  110 , as well as electromagnetic shielding provided by the interconnect layers  104 ,  116  and  106 ,  120 . In some applications, additional layers including different shielding structures may be included. Also, the use of interconnect layers instead of wire bonds may help to reduce generated or detected electromagnetic interference, to reduce impedances, and to permit direct connection to driver circuitry. 
         [0027]    A variety of similar permutations of the design described above are within the scope of this disclosure. For example, as shown in  FIG. 2 , both a VCSEL  210  and time of flight sensor  211  may be embedded within the substrate  102 . This permits the creation of a single package for use in a time of flight system. Moreover, it allows for producing of a device having connections to both the VCSEL  210  and time of flight sensor  211  that are at a same height even if the terminals of those components have different heights. 
         [0028]    As shown in  FIG. 3 , the chip  310  need not have both of its terminals extending from its top surface, and may instead have one terminal  312   b  extending from its top surface, while its other terminal  312   a  extends from its bottom surface. In other applications, both terminals might extend from the bottom surface, or there may be any number of terminals, with each extending from either the top or bottom surface. 
         [0029]    In some applications, perhaps due to the specific material used to construct the optically transparent layer  414  or due to the wavelength of the light to enter or exit the chip  110 , the optically transparent layer  414  may have a reduced thickness adjacent a portion of the top surface of the chip  110 . Such a situation is shown in  FIG. 4 . In yet another application, the optically transparent layer  514  may be completely removed adjacent a top portion of the top surface of the chip  110 , such as shown in  FIG. 5 . 
         [0030]    The electronic device  100  may be incorporated into a variety of structures and devices, and may have external components attached. For example, as shown in  FIG. 6 , a lens  675  may be attached to the top surface of the optically transparent layer  114  adjacent the top surface of the chip  110  so as to focus light entering or exiting the chip  110 . Similarly, as shown in  FIG. 18 , a lens or transparent cap  676  may be attached to the top surface of the chip  110  but covered by the optically transparent layer  114 . 
         [0031]    Formation of the electronic device  100  will now be described with reference to the series shown in  FIGS. 7-17 . Initially, the substrate  102  is clad with copper layers  104   a  and  106   a  that will ultimately become interconnect layers ( FIG. 7 ). Then, the copper layers  104   a  and  106   a  are patterned into suitable shapes so as to become interconnect layers  104  and  106  ( FIG. 8 ). This patterning is performed via suitable processes, such as etching. In some applications, the copper layers  104   a  and  106   a  may instead be part of a film layer that is applied to the substrate  102 . 
         [0032]    Next, a cavity  101  is formed into the substrate  102  via suitable processes ( FIG. 9 ). Thereafter, an adhesive layer  108  is laminated to the bottom surface of the substrate  102  so as to close off the bottom side of the cavity  101  formed in the substrate  102  ( FIG. 10 ). Then, the chip  110  is placed into the cavity  101  ( FIG. 11 ). 
         [0033]    Then, a sheet of optically transparent material  114 , with pre-formed copper cladding  116  thereon is laid on top of the chip  110 , interconnect layer  104 , and substrate  102  and pressed into place ( FIG. 12 ). Laser drilling and copper plating is then used to connect the terminals  112   b ,  112   b  to the copper cladding  116  ( FIG. 13 ). 
         [0034]    At least a portion of the adhesive layer  108  is then removed, and another sheet of optically transparent material  118  is placed adjacent the bottom surface of the chip  110 , interconnect layer  106 , and substrate  102 , and pressed into place ( FIG. 13 ,  FIG. 14 ). The sheet of optically transparent material  118  has pre-formed copper cladding  120  therein. 
         [0035]    Thereafter, the copper layers  116  and  120  are etched ( FIG. 15 ), and etching is performed so as to pattern them into the desired interconnect layers ( FIG. 16 ). At this point, if desired, portions of the optically transparent material  114  adjacent the top surface of the chip  110  may be removed. 
         [0036]    Then, photo resist layers  103  and  105  are respectively patterned over the outer surfaces of the optically transparent layers  114  and  118  ( FIG. 17 ), and then the protective layers  128  and  126  are formed via plating (shown in  FIG. 1 ). 
         [0037]    The formation of the electronic device  100  using the techniques described above provide for a high yield and low cost of manufacture. These techniques allow for the formation of an electronic device  100  in which the die size is up to 40% the size of the substrate. 
         [0038]    Many modifications and other embodiments will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that various modifications and embodiments are intended to be included within the scope of the appended claims.

Technology Category: 5