Patent Document

TECHNICAL FIELD OF THE INVENTION 
       [0001]    The invention relates generally to semiconductor integrated circuit manufacturing and, more particularly, to the accommodation of circuit design changes during the manufacturing process. 
       BACKGROUND OF THE INVENTION 
       [0002]    During conventional semiconductor integrated circuit manufacturing (e.g., during VLSI manufacturing), it is occasionally necessary to modify a logic circuit design within the integrated circuit. It is therefore a common conventional practice to provide some spare logic gates, such as inverters, AND gates, NOR gates, etc., which can hopefully be used to make the desired modifications in the logic circuit design. Unfortunately, there is no way to insure that these spare gates will provide the particular logic functionality that is required to implement the desired change in the logic circuit design. For example, the spare gate may be a NAND gate, when the desired change in the logic circuit design calls for the insertion of a NOR gate. 
         [0003]    Even if a spare logic gate is available to provide the logic functionality required by the desired change in the logic circuit design, the process of inserting the spare logic gate into the logic circuit design typically requires changing the photolithographic masks associated with at least one metal layer and one via layer of the integrated circuit. Modification of a photolithographic mask can be a relatively expensive operation in the integrated circuit manufacturing process. 
       SUMMARY OF THE INVENTION 
       [0004]    To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide for a spare logic gate design that supports a wide range of logic functions and can be inserted into a target logic circuit design with minimal changes in the photolithographic mask set. 
         [0005]    Exemplary embodiments of the invention provide a spare logic circuit for implementing any one of a plurality of logic gates. The select inputs of a multiplexer circuit are utilized as logic gate inputs, and the output of the multiplexer circuit is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. 
         [0006]    By modifying a single photolithographic mask, exemplary embodiments of the invention can (1) configure a spare logic gate to perform a desired logic function, (2) connect a spare logic gate into a target logic circuit, or (3) both configure and connect a spare logic gate. 
         [0007]    The foregoing has broadly outlined the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the invention will be described below that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
         [0008]    Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it is advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, cooperate with, be proximate to, be bound to or with, have a property of, or the like. The term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as future uses of such defined words and phrases. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
           [0010]      FIG. 1  is a truth table that illustrates sixteen (16) logic functions that can be performed by a two-input logic gate; 
           [0011]      FIGS. 2 through 5  diagrammatically illustrate examples of two-input logic gates which can be implemented by various embodiments of the invention; 
           [0012]      FIG. 6  diagrammatically illustrates a spare logic gate construction according to exemplary embodiments of the invention; 
           [0013]      FIG. 7  diagrammatically illustrates the construction of a spare logic gate node and a power rail according to exemplary embodiments of the invention; 
           [0014]      FIGS. 8 through 10  diagrammatically illustrate how exemplary embodiments of the invention can produce the logic gate of  FIG. 4  from the spare logic gate of  FIG. 6  by modification of a single photolithographic mask; 
           [0015]      FIG. 11  illustrates a physical example of the structures represented in  FIG. 7 ; and 
           [0016]      FIG. 12  illustrates a physical example of the structures represented in  FIGS. 8 through 10 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]    Exemplary embodiments of the present invention provide a “universal” two-input spare logic gate which can be selectively configured to implement any desired one of all possible two-input logic functions. The spare logic gate can be laid out such that only a single metal mask layer change is needed for configuring and connecting the spare logic gate as desired. 
         [0018]    Considering an arbitrary two-input logic gate, if A and B are the inputs, then there are sixteen (16) possible output combinations, Y 0  through Y 15 . The input and output combinations are illustrated in the truth table of  FIG. 1 . For example, Y 1  represents the logic function of an AND gate, Y 8  represents the logic function of a NOR gate, and Y 6  represents the logic function of an XOR gate. The truth table of  FIG. 1  also provides the functionality of an inverter, for example A and Y 12  can be the input and output, respectively, of an inverter. 
         [0019]    According to exemplary embodiments of the invention, the truth table of  FIG. 1  can be implemented with a conventional 4-to-1 multiplexer circuit, with the multiplexer select inputs corresponding to the logic inputs A and B of  FIG. 1 , and with the multiplexer output corresponding to the logic outputs Y 0  through Y 15  of  FIG. 1 . The desired logic function is programmed by tying the data inputs of the multiplexer circuit to one of two possible logic levels, for example the positive supply voltage (Vdd) or the negative supply voltage (Vss).  FIGS. 2 ,  3 ,  4  and  5  respectively illustrate XOR  21 , inverter  31 , AND  41 , and NOR  51  functions produced by appropriately programming a 4-to-1 multiplexer circuit. In  FIGS. 2 through 5 , the multiplexer data inputs are designated D 0 , D 1 , D 2  and D 3 , and the multiplexer select inputs are designated S 0  and S 1 . Also in  FIGS. 2 through 5 , A and B represent the logic inputs of  FIG. 1 , and thus also designate the nodes of a target circuit that are to be connected to drive the inputs S 0  and S 1  of the spare logic gate. In the examples shown in  FIGS. 2 through 5 , the data inputs D 0  through D 3  are tied either to ground (Vss) or to the positive supply voltage (Vdd) in order to appropriately program the desired logic function. The D 0  through D 3  programming necessary to produce any of the logic functions illustrated in  FIG. 1  can be readily determined by inspection of  FIG. 1 . 
         [0020]    With a layout according to exemplary embodiments of the invention, it is possible to provide a 4-to-1 multiplexer circuit as a universal two-input spare logic gate that is configurable and connectable by modifying only a single photolithographic mask from among all of the metal and via layer masks in the photolithographic mask set that is utilized to produce the integrated circuit. To avoid standby current, all inputs of the spare 4-to-I multiplexer circuit, namely D 0  through D 3 , S 0  and S 1  are tied to known logic levels when not in use. An example of this is shown in  FIG. 6 , where all inputs of the multiplexer circuit  61  are tied down to ground (Vss). 
         [0021]      FIG. 7  diagrammatically illustrates an exemplary construction for each of the input nodes of  FIG. 6  according to exemplary embodiments of the invention. Thus, each of the nodes D 0  through D 3 , S 0  and S 1  of  FIG. 6  can be constructed as shown at  71  in  FIG. 7 . The example of  FIG. 7  assumes that the integrated circuit utilizes four metal layers M 1  through M 4  that are interconnected by vias in three via layers V 1  through V 3 . Each of the input nodes of  FIG. 6  is connected to Vss by the illustrated interconnection of metal layers and via layers. 
         [0022]    More specifically, Vss at metal layer M 1  is connected by via layer V 1  to metal layer M 2 , which is in turn connected by via layer V 2  to metal layer M 3 , which is in turn connected by via layer V 3  to metal layer M 4 . Thus, each of the input nodes of the multiplexer circuit  61  of  FIG. 6  is connected to Vss and is also connected to every metal layer utilized in the integrated circuit. 
         [0023]      FIG. 7  also illustrates a power rail structure  73  according to exemplary embodiments of the invention. The power rail structure  73  uses via layers V 1 , V 2  and V 3  to connect the power supply Vdd at metal layer M 1  to each of metal layers M 2 , M 3  and M 4 . Thus, the power supply voltage Vdd is available at every metal layer, as are each of the input nodes of the multiplexer circuit (spare logic gate)  61 . The input node and power-rail constructions  71  and  73  illustrated in  FIG. 7  permit the spare logic gate  61  to be configured and connected as desired by modifying only a single photolithographic mask of the photolithographic mask set utilized to produce the integrated circuit. 
         [0024]      FIGS. 8 through 10  illustrate an example of how the spare logic gate  61  of  FIG. 6  can be configured to perform an AND function as shown in  FIG. 4 , and can also be connected to a target logic circuit, by modifying only a single-photo-lithographic mask. The example of  FIGS. 8 through 10  assumes that the target circuit nodes A and B, which will drive the select inputs S 0  and S 1  of  FIG. 6 , are defined in metal layer M 2 . Therefore, the photolithographic mask associated with metal layer M 2  will be modified to configure and connect the spare logic gate  61  in the manner described hereinafter. In order to configure the spare logic gate  61  to perform the AND function, the construction of multiplexer data input D 3  (see also  FIGS. 4 and 6 ) must be modified to disconnect D 3  from Vss, and also to connect D 3  to the power supply voltage Vdd. 
         [0025]    Accordingly, as shown in  FIG. 8 , the photo-lithographic mask associated with metal layer M 2  is modified to form an open circuit  83  which disconnects input node D 3  from Vss. Also, the photolithographic mask associated with metal layer M 2  is modified to provide a connection  81  between the input node D 3  and the power supply voltage Vdd, which power supply voltage Vdd is already available in metal layer M 2  by virtue of the power rail structure  73  of  FIG. 7 . 
         [0026]    Referring still to  FIGS. 4 and 6 , and also referring now to  FIG. 9 , the input node S 0  can be disconnected from Vss by modifying the M 2  photolithographic mask to provide an open circuit  93  as shown in  FIG. 9 . The input node S 0  is also connected to the node A of the target circuit by modifying the M 2  photolithographic mask to provide the connection  91  illustrated in  FIG. 9 . 
         [0027]    Referring also to  FIG. 10 , the input node S 1  can be disconnected from Vss by modifying the M 2  photolithographic mask to provide an open circuit  103  as shown in  FIG. 10 . The input node S 1  is connected to the node B of the target circuit by modifying the M 2  photolithographic mask to provide the connection  101  illustrated in  FIG. 10 . 
         [0028]    Thus, and considering the example of  FIGS. 8 through 10  together with  FIGS. 4 and 6 , the spare logic gate  61  of  FIG. 6  can be configured ( FIG. 8 ) to perform the AND function and can be interconnected to the nodes A ( FIG. 9 ) and B ( FIG. 10 ) of a target circuit, by modifying only a single photolithographic mask, namely the mask associated with the M 2  metal layer. 
         [0029]      FIG. 11  illustrates an example of the physical structures represented by  FIG. 7 , and  FIG. 12  illustrates an example of the physical structures that result from  FIG. 11  when the M 2  photolithographic mask is modified to make the M 2  metal layer changes illustrated in  FIGS. 8 through 10 . 
         [0030]    Although the foregoing examples have been described with reference to the inputs of the multiplexer circuit  61  of  FIG. 6 , the output node of the multiplexer circuit  61  can also be constructed generally as shown at  71  in  FIG. 7 , and can be appropriately disconnected from Vss and connected to the target circuit in the same general fashion illustrated with respect to select inputs S 0  and S 1  of  FIGS. 9 and 10 . 
         [0031]    Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.

Technology Category: 5