Patent Document

BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates, in general, to the field of integrated circuit dynamic random access memories (“DRAMs”). More particularly, the present invention relates to a DRAM memory architecture that allows reading or writing from outside the integrated circuit while transferring or reading data from the same addressed memory cell to a second DRAM subarray.  
         [0002]     Conventional single port (“1T/1C”) DRAM cells and associated memory architectures are known in the art. Dual port (“2T/2C”) DRAM cells or dual port video RAMs are also known in the art. These dual port video RAMs contain a high speed serial port and a conventional multibit parallel port. One problem with prior art memory cells and architectures is that they only allow one operation such as reading or writing to occur at a time.  
         [0003]     Referring now to  FIG. 1 , a prior art memory architecture  10  is shown including a first set  22  of data lines (INT I/O and complementary INT I/O), DRAM subarrays  12 A and  12 B, sense amplifier blocks  14 A and  14 B, as well as row decoding circuits  16 A and  16 B, and column decoding circuits  18 A and  18 B. Selection transistors M 0  and M 1  are used to transfer the sensed data from DRAM subarrays  12 A and  12 B to data lines  22  upon operation of the “SEL  0 ” control signal. Similarly, selection transistors M 2  and M 3  are used to transfer the sensed data from DRAM subarray  12 B to data lines  22  upon operation of the “SEL  1 ” control signal. For the sake of clarity in  FIG. 1 , the interconnecting bit and word lines are not shown.  
         [0004]     Turning now to  FIG. 2 , a prior art block diagram shows further details of a sense amplifier block  14 . As is known in the art, sense amplifier block  14  includes a plurality of sense amplifiers  20 A through  20 N. Each sense amplifier is coupled to two coupling transistors for transferring the sensed data from the DRAM subarrays to lines  15  and  17 , which are coupled to the selection transistors as previously described.  
         [0005]     Referring back to  FIG. 1 , in the prior art memory architecture  10 , either the SEL  0  or SEL  1  signals go high to put data from one sense amplifier band  14 A or  14 B onto the data lines  22 . What is not possible is to internally read or transfer that same data, or other data, to any other DRAM subarray.  
         [0006]     What is desired, therefore, is a memory architecture that allows reading or writing from outside the integrated circuit while transferring or reading data from the same addressed memory cell to a second DRAM subarray or to transfer data between unrelated DRAM subarrays.  
       SUMMARY OF THE INVENTION  
       [0007]     According to the present invention by adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:  
         [0009]      FIG. 1  is a block diagram of a prior art memory architecture in which only one read or write operation is allowed at a time;  
         [0010]      FIG. 2  is a block diagram showing further detail of the sense amplifier blocks shown in  FIG. 1 ;  
         [0011]      FIG. 3  is a block diagram of a memory architecture according to the present invention including an additional set of data lines in which an additional data read or transfer operation is allowed in additional to the external read or write operation;  
         [0012]      FIG. 4  is a second block diagram of a memory architecture according to the present invention in which four DRAM subarrays and three sense amplifiers blocks are shown to demonstrate an additional operational mode;  
         [0013]      FIG. 5  is a schematic diagram of a portion of a memory array including sense amplifiers and first and second sets of data lines according to the present invention; and  
         [0014]      FIG. 6  is a schematic diagram of a sense amplifier block and two sets of selection transistors connected to two sets of data lines according to the present invention 
     
    
     DETAILED DESCRIPTION  
       [0015]     Referring now to  FIG. 3 , a memory architecture according to the present invention includes the same first set of data lines  22 , DRAM subarrays  12 A and  12 B, and sense amplifier blocks  14 A and  14 B as shown in  FIG. 1 . Additionally the same selection transistors M 0 , M 1 , M 2 , and M 3 , as well as corresponding selection control signals SEL  0  and SEL  1  are shown. However, note in  FIG. 3 , that a second set  24  of data lines is provided. Sense amplifier block  14 A is also coupled to the second set of data lines via selection transistors M 4  and M 5  under control of the “SEL  2 ” control signal. Sense amplifier block  14 B is also coupled to the second set of data lines via selection transistors M 6  and M 7  under control of the “SEL  3 ” control signal. The selection transistors are coupled between local data lines  15  and  17  and the second set of data lines  24 . A bi-directional data transfer register or buffer  19  is interposed into the second set of data lines  24  between M 4 /M 5  selection circuitry and the M 6 /M 7  selection circuitry. The row and column decoding circuitry is not shown in  FIG. 3  for sake of clarity.  
         [0016]     In operation, the second set of data lines  24  are used so that data can be transferred from a first DRAM subarray to a second DRAM subarray, while data from a third DRAM subarray can be written or read to the outside world via the first set of data lines  22 . Also, both sets of select control signals from a given sense amplifier block (for example, SEL  0  and SEL  2 ) can go valid so that data from one DRAM subarray can be transferred to another DRAM subarray and that data can be written to or read from the outside word at the same time. In this example, control signal SEL  3  is high and control signal SEL  1  is low. In this way, the same data that is being read or written to the first set of data lines  22  from DRAM subarray  12 A is also being transferred to DRAM subarray  12 B. The data transfer register  19  assures that there is sufficient drive capability to correctly write the transferred data.  
         [0017]     Referring now to  FIG. 4 , an expanded view of the memory architecture  40  of the present invention includes DRAM subarrays  12 A,  12 B, and  12 C, as well as sense amplifier blocks or columns  14 A,  14 B, and  14 C. The sense amplifier blocks  14 A,  14 B, and  14 C are coupled to the first and second data line sets  22  and  24  via select circuits SELECT  0 - 5 . The SELECT circuits include the same two selection transistors and control signals as shown in previous  FIG. 3 . Data transfer registers are shown interposed between the selection circuits associated with the second set  24  of data lines. Data transfer register  19  is interposed between the SELECT  4  and the SELECT  5  selection circuits. The actual select control signal nodes are not shown in  FIG. 4 .  
         [0018]     Still further functionality of memory architecture  40  can be demonstrated with reference to  FIG. 4 . In particular, while data can be read to or written from the outside world via the first set of data lines  22 , data can simultaneously be transferred between unrelated DRAM subarrays.  
         [0019]     For example, with proper switching of the appropriate SELECT circuits, data can be read from or written to sense amplifiers  14 C, while simultaneously transferring data from sense amplifiers  14 C to sense amplifiers  14 A or  14 B. Similarly, data can be read from or written to sense amplifiers  14 B, while simultaneously transferring data from sense amplifiers  14 C to sense amplifiers  14 A. Finally, data can be read from or written to sense amplifiers  14 A, while simultaneously transferring data from sense amplifiers  14 C to sense amplifiers  14 B.  
         [0020]     It will be apparent to those skilled in the art that many modes of operation can be effected with the memory architecture  40  of  FIG. 4  or variations thereof, including reading and writing of external data, coupled with transferring the same data or data between unrelated DRAM subarrays as desired. Of course, the number of DRAM subarrays and associated sense amplifier columns is limited only by the requirements of a specific application and the size of the integrated memory circuit.  
         [0021]     Referring now to  FIG. 5 , a schematic diagram of a portion  50  of a memory subarray including local and global data lines and selection circuitry according to the present invention is shown. In  FIG. 5 , it is possible to see the actual bit lines BL&lt; 0 &gt;, BLB&lt; 0 &gt;, BL&lt; 1 &gt;, BLB&lt; 1 &gt;, BL&lt; 2 &gt;, and BLB&lt; 2 &gt; that are coupled directly to sense amplifiers SA&lt; 0 &gt;, SA&lt; 1 &gt;, and SA&lt; 2 &gt;, respectively. Transistors M 7  and M 8 , for example, couple the full data levels on sense amplifier SA&lt; 0 &gt; to the DLB and DL lines. In  FIG. 5 , transistors M 1  and M 2  are used to couple the DLB and DL local data lines to the first set of global data lines, labeled CRW and CRWB. The first selection control signal is designated WBK. In  FIG. 5 , transistors M 5  and M 6  are used to couple the DLB and DL local data lines to the second set of global data lines, labeled GDQ and GDQB. The second selection control signal is designated RW. Only a portion of a representative DRAM subarray is shown and the numbers of rows and columns of memory cells (e.g. pass transistor M 16  and storage capacitor C 3 ) can be extended as required for a particular application.  
         [0022]     Another embodiment  60  of the present invention is shown in  FIG. 6 . In the embodiment shown in  FIG. 6 , first and second sets of selection transistors are used. This arrangement may provide benefits when the circuit is actually configured and laid out on an integrated circuit, as well as having other performance advantages. Note that in  FIG. 6 , selection transistors M 1  and M 2  are used to couple the data from sense amplifiers SA&lt; 0 &gt; through SA&lt; 7 &gt; to the first set of global data lines CRW and CRWB. Selection transistors M 3  and M 4  are used to couple the data from sense amplifiers SA&lt; 8 &gt; through SA&lt; 15 &gt; to the first set of global data lines CRW and CRWB. Selection transistors M 7  and M 8  are used to couple the data from sense amplifiers SA&lt; 0 &gt; through SA&lt; 7 &gt; to the second set of global data lines GDQ and GDQB. Selection transistors M 7  and M 8  are used to couple the data from sense amplifiers SA&lt; 8 &gt; through SA&lt; 15 &gt; to the second set of global data lines GDQ and GDQB. Note further that there are two select control signal associated with the first set of global data lines, namely WBK&lt; 0 &gt; for selecting transistors Ml and M 2 , and WBK&lt; 1 &gt; for selecting transistors M 3  and M 4 . Similarly, there are two select control signal associated with the second set of global data lines, namely RW&lt; 0 &gt; for selecting transistors M 5  and M 6 , and RW&lt; 1 &gt; for selecting transistors M 7  and M 8 .  
         [0023]     In  FIG. 6 a  data transfer register  62  is shown for transferring the data on the local data lines DL&lt; 0 &gt;, DL&lt; 1 &gt;, DLB&lt; 0 &gt;, and DLB&lt; 1 &gt; to other DRAM subarrays through global data lines GW and GWB. An I/O circuit block  64  is also shown for transferring the data on the GDQ and GDQB global data lines to the external data input and output terminals designated D and Q.  
         [0024]     In operation, data can be transferred to either the data transfer registers  62 , or the I/O circuit block  64 , or both. To transfer data to the data transfer registers  62  only, WBK&lt; 0 &gt; or WBK&lt; 1 &gt; are active, and RW&lt; 0 &gt; and RW&lt; 1 &gt; are inactive. To transfer data to the I/O circuit block only, WBK&lt; 0 &gt; and WBK&lt; 1 &gt; are inactive, and RW&lt; 0 &gt; or RW&lt; 1 &gt; are active. To transfer data to both the data transfer registers  62  and to the I/O circuit blocks, either WBK&lt;O&gt; and RW&lt; 0 &gt; are active and WBK&lt; 1 &gt; and RW&lt; 1 &gt; are inactive, or WBK&lt; 0 &gt; and RW&lt; 0 &gt; are inactive and WBK&lt; 1 &gt; and RW&lt; 1 &gt; are active.  
         [0025]     While there have been described above the principles of the present invention in conjunction with specific memory architectures and methods of operation, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Technology Category: 3