Patent Document

[0001]    This application claims the benefit of Taiwan application Serial No. 104103182, filed Jan. 30, 2015, the disclosure of which is incorporated by reference herein in its entirety. 
       TECHNICAL FIELD 
       [0002]    The disclosure relates in general to a system and a method for controlling a bias of a diode, and more particularly to a system and a method for controlling an excess bias of a single photon avalanche photo diode (SPAD). 
       BACKGROUND 
       [0003]    In general, the operation regions of photo detectors can be divided into three modes, including linear integration photo diodes (PD), linear-mode avalanche photo diodes (APD) and Geiger-mode avalanche photo diodes (APD) or namely single photon avalanche photo diodes (SPAD). 
         [0004]    Please refer to  FIG. 1 , which illustrates a bias operating region and an optical gain of varied photoelectric detectors. As the PD is operated at a low reverse bias region, the optical gain of the PD is not high and each photon induces at most one electron-hole pair. 
         [0005]    The PD operated just below its breakdown voltage is known as a linear-mode APD. A working voltage (also known as a bias voltage) of the APD is near and larger than a breakdown voltage level which is −V bd . That is to say, the absolute value of the bias voltage is smaller than the absolute value of the breakdown voltage level −V bd . 
         [0006]    The SPAD is operated at a Geiger mode. A bias voltage of the SPAD is smaller than a breakdown voltage level −V bd . That is to say, the absolute value of the bias voltage is larger than the absolute value of the breakdown voltage level −V bd . For example, the bias voltage is −(V bd +V e ), V e  is an excess bias level, and V e  is positive. Under a high electric field, an optical gain of the SPAD whose order of magnitude is as high as 10 6  is very good in its sensitivity. 
         [0007]    Please refer to  FIG. 2 , which illustrates a relationship between a load current I load  and the excess bias level V e  of the SPAD with the charge pump as the power supply. The SPAD and the load are cascoded between a supply voltage V op  and a ground voltage, and assume a temperature is kept at a particular value. As known from  FIG. 2 , when the load current I load  is quiescent, the excess bias level V e  is at a maximum; when the load current I load  is increased, the excess bias level V e  is decreased with the supply voltage V op . Furthermore, the excess bias level V e  will affect the sensitivity of the SPAD. As the load current I load  is increased, the excess bias level V e  will be decreased, then desensitizing the SPAD. 
         [0008]    Please refer to  FIG. 3 , which illustrates a relationship between the temperature T and the excess bias level V e  of the SPAD with the charge pump as the power supply. The SPAD and the load are cascoded between the supply voltage V op  and the ground voltage, and assume the load current I load  is kept at a particular value. As known from  FIG. 3 , as the temperature T is increased, the breakdown voltage level V bd  will be raised, thus decreasing the excess bias level V e . The reduced excess bias level V e  will deteriorate the sensitivity of the SPAD. When the temperature T is increased, the excess bias level V e  will be decreased, then desensitizing the SPAD. 
         [0009]    Based on the above, it is known that the breakdown voltage level V bd  and the supply voltage V op  may drift upon the environment. Therefore, it&#39;s very important to stabilize the bias voltage of the SPAD and keep a constant excess bias level V e  against process, voltage, and temperature (PVT) variations. 
         [0010]    Please refer to  FIG. 4 , which illustrates a bias adjusting circuit of an ordinary SPAD. The bias adjusting circuit adjusts the bias of the operating diode  54  according to the dark count rates (DCR) of a reference diode  26 , such that the excess bias is kept at a fixed value. 
         [0011]    As shown in  FIG. 4 , the reference diode  26  shielded by a light opaque housing  36  is electrically connected to an active quenching circuit (AQR)  44  and a reference voltage V ref . Further, a gate counter  46  can count the dark count rate (DCR) in a predefined time period. Then, the gate counter  46  outputs a first digital word to a controller  48  according to the DCR. The controller  48  outputs a second digital word to a digital-to-analog converter (DAC)  50  according to a lookup table. The DAC  50  controls a variable voltage source  52  to output a bias voltage V bias  to the operating diode  54 . 
         [0012]    Based on the above, the bias adjusting circuit of the ordinary SPAD estimates the level of the breakdown voltage according to the DCR of the reference diode  26 , and then adjusts the bias of the operating diode  54 . In the bias adjusting circuit of the ordinary SPAD, the reference diode  26  is independent from the operating diode and shielded by a light opaque housing  36 . 
         [0013]    Please refer to  FIG. 5 , which illustrates a temperature compensated and control circuit of an ordinary SPAD. The temperature compensated and control circuit measures a breakdown voltage of the reference diode  58  and adjusts the bias voltage of another operating diode. 
         [0014]    As shown in  FIG. 5 , the reference diode  58  is electrically connected to a recharging circuit  60 . An analog-to-digital converter (A/D)  62  measures the breakdown voltage of the reference diode  58  and outputs a first digital word to a bias control circuit  64 . The bias control circuit  64  outputs a second digital word to a DAC  66 . The DAC  66  can control a variable voltage source  68  to output the bias voltage V bias  to the operating diode  70 . 
         [0015]    Based on the above, the temperature compensated and control circuit of the ordinary SPAD adjusts the bias of the operating diode  70  according to the level of the breakdown voltage of the reference diode  58 . In the temperature compensated and control circuit of the ordinary SPAD, the reference diode  58  is independent from the operating diode and shielded. 
         [0016]    Please refer to  FIG. 6 , which illustrates a temperature and load compensated method performed in a SPAD. The temperature and load compensated method adjusts an output voltage of a digital charge pump (DCP)  80  to control the excess bias of the SPAD according to the DCR and the pulse width of the reference diodes. 
         [0017]    As shown in  FIG. 6 , the temperature and load compensated circuit includes the digital charge pump (DCP)  80 , an array emulator  82 , an environment monitor  84 , a FPGA and host  86 , and digital control oscillator (DCO)  88 . 
         [0018]    Since the DCR and the pulse width are related to the variations of the temperature and the excess bias, the FPGA and host  86  receives the signal generated by the environment monitor  84 , calculates the DCR and the pulse width, and controls the DCO  88  and the DCP  80  to output the supply voltage V op  for adjusting the excess bias of the reference diodes  89   a  to  89   c.    
         [0019]    Based on the above, the temperature and load compensated method of the SPAD adjusts the supply voltage V op  and accordingly the excess bias according to the variations of the DCR and the pulse width. To compensate the temperature and load variations of the ordinary SPAD, the reference SPADs  89   a  to  89   c  are independent from the operating diodes and shielded. 
         [0020]    Please refer to  FIGS. 7A and 7B , which illustrate an ordinary high dynamic photo detector and an operating method thereof. As shown in  FIG. 7A , the high dynamic photo detector includes a PIN diode  112 , a SPAD  116 , a sensing transistor  114 , a reading transistor  118  and a reset transistor  120 . The PIN diode  112  is operated at the linear integration mode, and the SPAD  116  is operated at the Geiger mode. The high dynamic photo detector switches the operation between the linear mode and the Geiger mode according to a light flux. 
         [0021]    As shown in  FIG. 7B , in step  180 , the high dynamic photo detector detects the light condition  180 . In step  188 , when the brightness is larger than or equal to the threshold value, then it is operated at the linear mode. 
         [0022]    In step  184 , when the brightness is not larger than or equal to the threshold value, then it is operated at the Geiger mode. In the step  186 , if the output is not saturated, it is kept at the Geiger mode. In the step  186 , if the output is saturated, it is switched to the linear mode (step  188 ). In step  190 , at the linear mode  188 , if the noise is less than or equal to a threshold value, then it is switched to the Geiger mode (step  184 ). If the noise is not less than or equal to the threshold value, then it is kept at the linear mode (step  188 ). 
         [0023]    Because the high dynamic photo detector achieves the performance by switching operation between the linear mode and the Geiger mode, the signal processing circuit is much complex. 
         [0024]    Please refer to  FIG. 8 , which illustrates an environment light detecting system and method. As shown in  FIG. 8 , a sensing element  200  includes a substrate  202 , a light emitting diode  204 , a SPAD array  206 , a filter  208 , an etalon filter  210 , a lens  209 , a lens  211  and a brown window  212 . An infrared light can pass the brown window  212 . The SPAD array  206  includes a Raw SPAD (i.e. a first unfading pixel  214 ), IR light passed SPAD (i.e. a second unfading pixel  216 , and an opaque metal SPAD (i.e. fading pixel  218 ). 
         [0025]    When the brightness of the environment is larger than a threshold value, the sensing element  200  can be performed by the fading pixel  218 . When the brightness of the environment is lower than the threshold value, the sensing element  200  can be performed by the first unfading pixel  214  and the second unfading pixel  216 . 
         [0026]    The sensing element  200  needs a calibration circuit calibrating the mismatch between the fading pixel  218  and the first unfading pixel  214  (or the second unfading pixel  216 ) to avoid an inaccuracy of the sensing element  200 . 
       SUMMARY 
       [0027]    The disclosure is directed to a system and a method for controlling an excess bias of a single photon avalanche photo diode (SPAD). A new circuit is used for accurately controlling the excess bias to obtain a high dynamic imager. 
         [0028]    According to a present disclosure, a system for controlling an excess bias of a single photon avalanche photo diode (SPAD) is provided. The system includes a power supply, a SPAD, a control circuit and a load. The power supply generates a supply voltage. The SPAD has a first terminal receiving the supply voltage and a second terminal generating an output voltage signal. The control circuit is connected to the second terminal of the SPAD. The control circuit obtains a reset level according to a swing of the output voltage signal and an excess bias level. The load has a first terminal connected to the second terminal of the SPAD and a second terminal connected to the control circuit for receiving the reset level. 
         [0029]    According to a present disclosure, a method for controlling an excess bias of a single photon avalanche photo diode (SPAD) is provided. The method includes the following steps. A SPAD being operated at a Geiger mode is controlled. A first terminal of the SPAD is connected to a power supply. A second terminal of SPAD generates an output voltage signal. A first terminal of a load is connected to the second terminal of the SPAD. A second terminal of the load receives a reset level. A swing of the output voltage signal is monitored and the reset level is obtained according to the swing of the output voltage signal and an excess bias level, when the SPAD induces a sensing current. The reset level is provided to the second terminal of the load. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]      FIG. 1  (prior art) illustrates a bias operating region and an optical gain of varied photoelectric detectors. 
           [0031]      FIG. 2  (prior art) illustrates a relationship between a load current and the excess bias level of a SPAD. 
           [0032]      FIG. 3  (prior art) illustrates a relationship between a temperature and the excess bias level of the SPAD. 
           [0033]      FIG. 4  (prior art) illustrates a bias adjusting circuit of an ordinary SPAD. 
           [0034]      FIG. 5  (prior art) illustrates a temperature compensated and control circuit of the ordinary SPAD. 
           [0035]      FIG. 6  (prior art) illustrates a temperature and load compensated method performed in the SPAD. 
           [0036]      FIGS. 7A and 7B  (prior art) illustrate an ordinary high dynamic photo detector and an operating method thereof. 
           [0037]      FIG. 8  (prior art) illustrates an environment light detecting system and a method thereof. 
           [0038]      FIGS. 9A to 9C  illustrate a SPAD detecting circuit and signals thereof. 
           [0039]      FIGS. 10A and 10B  illustrate a system for controlling an excess bias of a SPAD and a signal thereof according to a first embodiment. 
           [0040]      FIG. 11  illustrates a system for controlling an excess bias of a SPAD according to a second embodiment. 
           [0041]      FIG. 12  illustrates a system for controlling an excess bias of a SPAD according to a third embodiment. 
           [0042]      FIG. 13  illustrates a system for controlling an excess bias of a SPAD according to a fourth embodiment. 
           [0043]      FIG. 14  illustrates a system for controlling an excess bias of a SPAD according to the fifth embodiment. 
           [0044]      FIG. 15  illustrates a detail circuit diagram according to the fifth embodiment. 
           [0045]      FIG. 16  illustrates a method for controlling an excess bias of a SPAD. 
           [0046]    In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
       
    
    
     DETAILED DESCRIPTION 
       [0047]    Please referring to  FIGS. 9A to 9C , which illustrate a SPAD detecting circuit and signals thereof. The SPAD detecting circuit includes a power supply  310 , a SPAD and a load R. The power supply  310  can output a supply voltage V op . A cathode terminal of the SPAD receives the supply voltage V op . When the SPAD receives photons, the anode terminal outputs an output voltage signal V anode . A first terminal of the load is connected to the anode terminal of the SPAD. A second terminal of the load is connected to a ground voltage Gnd. 
         [0048]    If the SPAD is operated at the Geiger mode, the supply voltage V op =V bd +V e . V bd  is a breakdown voltage and V e  is an excess bias level. When the SPAD does not receive any photon, a sensing current I (or a load current) is quiescent. At this time period, the SPAD is off, and the output voltage signal V anode  of the anode terminal is kept at the Gnd level. 
         [0049]    At time t1, the SPAD receives the photons and the sensing current I is increased. At this time point, the SPAD is on and the sensing current I flows through the load which results in a voltage drop (I×R), such that the output voltage signal V anode  of the anode terminal is increased from the Gnd level. When the output voltage signal V anode  of the anode terminal is increased to a quenching level, i.e., the voltage drop of the SPAD is decreased to the breakdown voltage level V bd , the current of the SPAD is gradually to be cut-off and consequently the output voltage signal V anode  of the anode terminal is decreased to the Gnd level at time t2. 
         [0050]    When the SPAD receives the photons again, the operation from the time t1 to the time t2 is repeated. 
         [0051]      FIG. 10A  illustrates a system for controlling an excess bias of a SPAD according to a first embodiment. The system for controlling the excess bias of the SPAD includes a power supply  350 , a SPAD, a load  352  and a control circuit  360 . The control circuit  360  includes a sampling and holding circuit  362  and a level shifter  364 . 
         [0052]    The power supply  350  can output a supply voltage V op . A cathode terminal of the SPAD receives the supply voltage V op . After receiving photons, the anode terminal outputs related events at the output voltage signal V anode . A first terminal of the load  352  is connected to the anode terminal of the SPAD. The sampling and holding circuit  362  receives the output voltage signal V anode  from the anode terminal and outputs a quenching level V q . The level shifter  364  receives the excess bias level V e  and transfers the quenching level V q  to be a reset level V r , such that a second terminal of the load  352  receives the reset level V r . The reset level V r  is equal to a value obtained by subtracting the quenching level V q  from the excess bias level V e . The power supply  350  can be a charge pump circuit and the load  352  can be a resistor. 
         [0053]    The supply voltage V op  from the power supply  350  and the breakdown voltage level V bd  of the SPAD may shift with the conditions of the environment. In the present embodiment, the sampling and holding circuit  362  accurately obtains the quenching level V q  of the SPAD. The level shifter  364  adds the excess bias level V e  and the quenching level V q  together to obtain the reset level V r . The second terminal of the load  352  receives the reset level V r . 
         [0054]    Please refer to  FIG. 10B , which illustrates a signal of the system for controlling the excess bias of the SAPD. At time t1, the SPAD receives photons and is triggered on. A sensing current I is induced, such that the level of the output voltage signal V anode  at the anode terminal is increased and reached the quenching level V q . At this time point, the quenching level V q  is equal to a value obtained by subtracting the breakdown voltage level V bd  from the supply voltage V op    
         [0000]        V   q   =V   op   −V   bd    (1)
 
         [0055]    The extreme voltage level of the output voltage signal V anode  obtained from the anode terminal by the sampling and holding circuit  362  is the quenching level V q . When the output voltage signal V anode  of the anode terminal reaches the quenching level V q , the SPAD is turned off and the output voltage signal V anode  of the anode terminal is gradually decreased to the Gnd level at time t2. 
         [0056]    When the sampling and holding circuit  362  provides the quenching level V q  to the level shifter  364 , the level shifter  364  adds the excess bias level V e  and the quenching level V q  together to obtain the reset level V r , such that the second terminal of the load  352  receives the reset level V r . The reset level V r  is equal to a value obtained by subtracting the excess bias level V e  from the quenching level V q . 
         [0000]        V   r   =V   q   −V   e    (2)
 
         [0057]    According to the equations (1) and (2), an equation “V op −V r =V bd +V e ” can be obtained. That is to say, when the SPAD is off, the voltage drop of the SPAD is a value obtained by adding the breakdown voltage level V bd  and the excess bias level V e . 
         [0058]    Based on the above, no matter how much the supply voltage V op  provided from the power supply  350  and the breakdown voltage level V bd  of the SPAD are shifted, the quenching level will shift upon the variations and keeps the excess bias level of the SPAD always equal to V e . Therefore, the SPAD of the first embodiment can accurately provide the excess bias level V e . Furthermore, the excess bias level V e  received by the level shifter  364  can be tuned to adjust a Photon Detection Probability (PDP) of the SPAD, such that the system of the first embodiment is widely dynamic. 
         [0059]    Please refer to  FIG. 11 , which illustrates a system for controlling an excess bias of a SPAD according to a second embodiment. The system for controlling the excess bias of the SPAD includes a power supply  400 , a SPAD, a load  402  and a control circuit  420 . The control circuit  420  includes a level shifter  422  and a sampling and holding circuit  426 . 
         [0060]    The difference between the first embodiment and the second embodiment is in the control circuit  420 . The level shifter  422  adds the excess bias level V e  and the output voltage signal V anode  together to obtain a first voltage signal V q ′ (V q ′=V anode +V e ). The extreme voltage level of the first voltage signal V q ′ obtained by the sampling and holding circuit  426  is taken as the reset level V r . Similarly, an equation “V op −V r =V bd +V e ” can be also obtained. When the SPAD is off, the voltage drop of the SPAD is a value obtained by adding the breakdown voltage level V bd  and the excess bias level V e  together. 
         [0061]    Please refer to  FIG. 12 , which illustrates a system for controlling an excess bias of a SPAD according to a third embodiment. The system for controlling the excess bias of the SPAD includes a power supply  450 , a SPAD, a load  452  and a control circuit  460 . The control circuit  460  includes a sampling and holding circuit  462  and a level shifter  464 . 
         [0062]    The power supply  450  can generate a supply voltage V op . The anode terminal of the SPAD receives the supply voltage V op . The cathode terminal receives photons and outputs the events at the output voltage signal V cathode . The first terminal of the load  452  is connected to the cathode terminal of the SPAD. The sampling and holding circuit  462  receives the output voltage signal V cathode  of the cathode terminal and generates the quenching level V q . The level shifter  464  receives the excess bias level V e  and adds the quenching level V q  and the excess bias level V e  to obtain the reset level V r , such that the second terminal of the load  452  receives the reset level V r . The reset level V r  is equal to a value obtained by adding the quenching level V q  and the excess bias level V e , i.e., V r =V q +V e . The power supply  450  can be a charge pump circuit and the load  452  can be a resistor. 
         [0063]    Similarly, as the SPAD receives a photon and induces the sensing current I, the level of the output voltage signal V cathode  from the cathode terminal is decreased to the quenching level V q . At this time point, the extreme voltage level of the output voltage signal V cathode  obtained from the cathode terminal by the sampling and holding circuit  462  is taken as a quenching level V q . At this time point, the reset level V r  is a value obtained by adding the supply voltage V op  and the breakdown voltage level V bd . 
         [0000]        V   q   =V   op   +V   bd    (3)
 
         [0064]    When the sampling and holding circuit  462  provides the quenching level V q  to the level shifter  464 , the level shifter  464  add the excess bias level V e  and the quenching level V q  together to obtain the reset level V r , such that a second terminal of the load  452  receives the reset level V r . The reset level V r  is equal to a value obtained by adding the quenching level V q  and the excess bias level V e . 
         [0000]        V   r   =V   q   +V   e    (4)
 
         [0065]    According to the equations (3) and (4), an equation “V r −V op =V bd +V e  can be obtained. When the SPAD is off, the voltage drop of the SPAD is a value obtained by adding the breakdown voltage level V bd  and the excess bias level V e . 
         [0066]    Please refer to  FIG. 13 , which illustrates a system for controlling an excess bias of a SPAD according to a fourth embodiment. The system for controlling the excess bias of the SPAD includes a power supply  500 , a SPAD, a load  502  and a control circuit  520 . The control circuit  520  includes a level shifter  522  and a sampling and holding circuit  524 . 
         [0067]    The difference between the third embodiment and the fourth embodiment is in the control circuit  520 . The level shifter  522  adds the excess bias level V e  and the output voltage signal V cathode  of a cathode terminal to obtain the first voltage signal V q ′ (V q ′=V cathode +V e ). The sampling and holding circuit  524  obtains the extreme voltage level of the first voltage signal V q ′ to output the reset level V r . Similarly, an equation “V op −V r =V bd +V e ” can be also obtained. That is to say, when the SPAD is off, the voltage drop of the SPAD is a value obtained by adding the breakdown voltage level V bd  and the excess bias level V e . 
         [0068]    Please refer to  FIG. 14 , which illustrates a system for controlling an excess bias of a SPAD according to the fifth embodiment. The system for controlling the excess bias of the SPAD includes a power supply  600 , a SPAD, a load  602  and a control circuit  620 . The load  602  includes a transistor M 1  and a quenching reset circuit  606 . The control circuit  620  includes a sampling and holding circuit  622 , a level shifter  624  and a voltage regulator  626 . The power supply  600  can be a charge pump circuit. 
         [0069]    The power supply  600  can generate a supply voltage V op . A cathode terminal of the SPAD receives the supply voltage V op . The anode terminal generates the output voltage signal V anode . A first terminal of the load  602  is connected to the anode terminal of the SPAD. The sampling and holding circuit  622  receives the output voltage signal V anode  of the anode terminal and outputs the quenching level V q . The level shifter  624  receives the excess bias level V e  and adds the quenching level V q  and the excess bias level V e  together to obtain the reset level V r . The voltage regulator  626  receives the reset level V r  and outputs a regulating voltage V reg . The second terminal of the load  602  receives the regulating voltage V reg . The reset level V r  is equal to a value obtained by subtracting the excess bias level V e  from the quenching level V q . The reset level V r  is equal to the regulating voltage V reg . 
         [0070]    The voltage regulator  626  of the control circuit  620  can enhance an output driving ability, such that the second terminal of the load  602  can quickly settle at the reset level V r . The voltage regulator  626  includes an operational amplifier  628 . The positive input terminal of the operational amplifier  628  receives the reset level V r . The negative input terminal of the operational amplifier  628  generates the regulating voltage V reg . In the transistor M 2 , a source receives a supply voltage V DD , a drain is connected to the negative input terminal of the operational amplifier  628 , and a gate is connected to an output terminal of the operational amplifier  628 . The transistor R is connected between the negative terminal of the operational amplifier  628  and the ground voltage Gnd. In the fifth embodiment, the quenching reset circuit  606  of the load  602  generates a control signal for that the sampling and holding circuit  622  can accurately obtains the quenching level V q . The operations are described as below. 
         [0071]    When the SPAD receives photons and is triggered on, the sensing current I is induced. The output voltage signal V anode  of the anode terminal is increased to the quenching level V q . At this time point, the quenching reset circuit  606  generates a controlling signal Ctrl to a gate (control terminal) of the transistor M 1  for turning off the transistor M 1 , such that a path on the anode terminal of the SPAD is opened. Therefore, the quenching level V q  will be kept for a long time. The sampling and holding circuit  622  can accurately obtain the quenching level V q . 
         [0072]    In other words, the voltage regulator  626  of the fifth embodiment is used to enhance an output driving ability of the control circuit  620 . The second terminal of the load  602  receives the regulating voltage V reg  (i.e. the reset level V r ). The quenching reset circuit  606  of the fifth embodiment is used to keep the quenching level V q  for a longer time, such that the sampling and holding circuit  622  can accurately obtain the quenching level V q . When the SPAD is off, the voltage drop of the SPAD is a value obtained by adding the breakdown voltage level V bd  and the excess bias level V e  (i.e. V op −V r =V bd +V e ). 
         [0073]    Please refer to  FIG. 15 , which illustrates a detail circuit diagram according to the fifth embodiment. The sampling and holding circuit  622  and the level shifter  624  can be used in the first embodiment to the fifth embodiment. 
         [0074]    The quenching reset circuit  606  includes a comparator  712 , an inverter  714 , an inverter  716 , a NOR  718 , a capacitor C 1 , a transistor M 8  and a transistor M 3 . A negative terminal of the comparator  712  receives the output voltage signal V anode  of an anode terminal. A positive terminal of the comparator  712  receives a reference threshold voltage level V th1 . An output terminal of the comparator  712  outputs the controlling signal Ctrl. When the 
         [0075]    SPAD receives photons and is triggered on, the sensing current I is induced, such that the output voltage signal V anode  of the anode terminal raises across the threshold voltage V th1 . The comparator  712  generates the controlling signal Ctrl to the gate of the transistor M 1  to turn off the transistor M 1 , such that the path of the anode terminal of the SPAD is opened. 
         [0076]    The inverter  714 , the capacitor C 1 , and the transistor M 8  in the quenching reset circuit  606  realize a monostable circuit. When the controlling signal Ctrl is induced, the transistor M 8  generates a pulse signal and the output terminal of the inverter  716  outputs a control signal SH to the sampling and holding circuit  622 . A gate of the transistor M 8  receives a control voltage to adjust the current and correspondingly the width of the pulse signal. The output terminal of the NOR  718  is used for controlling the transistor M 3 . At a specific time, the transistor M 3  is turned on to reset the voltage level of the anode terminal of the SPAD to the Gnd level. 
         [0077]    The sampling and holding circuit  622  includes an inverter  722 , an inverter  724 , a transmission gate, and a capacitor C 2 . The transmission gate includes a transistor M 4  and a transistor M 5 . When the control signal SH is high, the transmission gate is turned on and the extreme voltage level of the output voltage signal V anode  of the anode terminal is sampled and hold in the capacitor C 2 . In other words, the voltage of the capacitor C 2  is equal to the quenching level V r . 
         [0078]    The level shifter  624  includes a transistor M 6  and a transistor M 7  which realize a source follower. A gate of the transistor M 6  receives the quenching level V q , and a gate of the transistor M 7  receives the excess bias level V e  and an output terminal generates the reset level V r . The reset level V r  is equal to a value obtained by subtracting the excess bias level V e  from the quenching level V q . 
         [0079]    The voltage regulator  626  includes the operational amplifier  628 . A positive terminal of the operational amplifier  628  receives the reset level V r , the negative terminal of the operational amplifier  628  connects to the regulating voltage V reg . A gate of the transistor M 2  is connected to the output terminal of the operational amplifier  628 . A source of the transistor M 2  receives the supply voltage V DD . The drain of the transistor M 2  and the negative terminal of the operational amplifier  628  are connected to a resistor R 2 . A resistor R 1  is connected between the negative terminal of the operational amplifier  628  and the ground level Gnd. The voltage regulator  626  can enhance an output driving ability, such that the second terminal of the load  602  can quickly settle at the reset level V r . 
         [0080]    The drain of the transistor M 2  can generate a threshold voltage V th1  to the quenching reset circuit  606 . V th1 =V reg  (1+R 2 /R 1 ). The threshold voltage can be adjusted by tuning the ratio of R 2  and R 1  and optimized to reduce timing jitter of SPADs. 
         [0081]    Please refer to  FIG. 16 , which illustrates a method for controlling an excess bias of a SPAD. A first terminal of the SPAD is connected to a power supply for receiving a supply voltage V op . A second terminal of the SPAD can generate an output voltage signal. A first terminal of a load is connected to a second terminal of the SPAD. A second terminal of the load receives a reset level. The method includes the following steps. 
         [0082]    In step S 810 , the SPAD is operated at a Geiger mode. In step S 820 , when the SPAD induces a sensing current, the swing of the output voltage signal is monitored and a reset level is obtained according to the swing of the output voltage signal and an excess bias level. In step S 830 , the reset level is provided to a second terminal of the load. 
         [0083]    In step S 820 , the swing of the output voltage signal from a second terminal of the SPAD is sampled to obtain an extreme voltage level which is defined and taken as a quenching level. The quenching level and the excess bias level are summed together to obtain the reset level. 
         [0084]    Or, in step S 820 , the output voltage signal and the excess bias level are summed together to obtain a first voltage signal. The swing of the first voltage signal is monitored to obtain an extreme voltage level which is defined and taken as a reset level. 
         [0085]    Or, in step S 820 , the excess bias is divided into a plurality of small excess biases. The step of adding the output voltage signal and the excess bias together can be performed by adding the output voltage signal and the small excess biases several times. 
         [0086]    Based on the above, no matter how much the supply voltage V op  provided from the power supply and the breakdown voltage level V bd  of the SPAD drift, a voltage drop of the SPAD can be accurately controlled at a value obtained by adding the breakdown voltage level V bd  and the excess bias level V e . 
         [0087]    Because the excess bias level of the SPAD can be accurately controlled, the excess bias level V e  received by the level shifter can be tuned to obtain a high dynamic range controlling system. 
         [0088]    It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.

Technology Category: 3