Patent Document

PRIORITY APPLICATION 
       [0001]    This application is a continuation of U.S. application Ser. No. 13/776,189, filed Feb. 25, 2013, which is a divisional of U.S. application Ser. No. 12/164,390, filed Jun. 30, 2008, now issued as U.S. Pat. No. 8,384,223, all of which are incorporated herein by reference in their entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    Embodiments of the present invention generally relate to the field of integrated circuit packages, and, more particularly to backside mold process for ultra thin substrate and package on package assembly. 
       BACKGROUND OF THE INVENTION 
       [0003]    As microelectronic components shrink in size, a trend has emerged to provide package substrates that may be characterized as thin core substrates (that is, substrates having a core with a thickness less than or equal to 400 microns and larger than zero), or no-core substrates (that is, substrates without cores). 
         [0004]    Disadvantageously, with a thin or no-core substrate, however, decrease in yield at first level chip attach due to warpage causing nonwets may occur during the package manufacturing process, such as, for example, during flip chip bonding where substrate flatness and rigidity are required. To address the above issue, the prior art sometimes provides substrates that may have a thickness of at least several tens of microns or more. However, the above measure disadvantageously detracts from further package size minimization. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 
           [0006]      FIG. 1  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; 
           [0007]      FIG. 2  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; 
           [0008]      FIG. 3  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; 
           [0009]      FIG. 4  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; 
           [0010]      FIG. 5  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; 
           [0011]      FIG. 6  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; 
           [0012]      FIG. 7  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention; and 
           [0013]      FIG. 8  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
         [0015]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0016]      FIG. 1  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. In accordance with the illustrated example embodiment, package  100  includes one or more of coreless substrate strip  102 , backside contacts  104 , topside contacts  106  and substrate thickness  108 . 
         [0017]    Coreless substrate strip  102  represents a thin substrate that may be rolled out and processed before being singulated. In one embodiment, coreless substrate strip  102  is a direct laser lamination generation 3 (DLL3) strip. In one embodiment, substrate thickness  108  is about 200 micrometers. 
         [0018]      FIG. 2  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  200 , mold compound  202  is dispensed as a liquid on backside  206  and compressed by mold form  204 . In one embodiment, mold form  204  is a jig designed to compress mold compound  202  adjacent to sites where solder balls are to be attached. Mold form  204  may be held in place for some time and may be heated to allow mold compound  202  to cure. 
         [0019]      FIG. 3  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  300 , stiffening mold  302  is cured and provides added stiffness to package  300 . In one embodiment, stiffening mold  302  has a mold thickness  304  of about 100 micrometers. 
         [0020]      FIG. 4  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  400 , solder balls  402  have been attached amongst stiffening mold  302 . In one embodiment, solder ball diameter  404  is about 10 mils. In one embodiment, solder balls  402  are made from a high melting point solder (higher than about 220 degrees Celsius) so as to maintain their integrity through subsequent reflows, for example, a reflow for attaching a topside integrated circuit device. In another embodiment, solder balls  402  are not attached until later in the process after an integrated circuit device has been attached. 
         [0021]      FIG. 5  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  500 , the package has been flipped over for topside processing. 
         [0022]      FIG. 6  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  600 , integrated circuit device  602  has been attached to topside  604  of coreless substrate strip  102 . Integrated circuit device  602  may represent any type of silicon processor or controller or logic. 
         [0023]      FIG. 7  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  700 , underfill material  702  has been dispensed under integrated circuit device  602 . 
         [0024]      FIG. 8  is a graphical illustration of a cross-sectional view of a partially formed IC package, in accordance with one example embodiment of the invention. As shown in package  800 , second integrated circuit device package  802  has been attached to topside  604  through solder balls  804 . Second integrated circuit device package  802  may be any type of package and need not be a flip chip package. 
         [0025]    In one embodiment, package  800  is processed further and singulated from other packages. 
         [0026]    In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. 
         [0027]    Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.

Technology Category: 5