Patent Document

This application claims the benefit of U.S. Provisional Application No. 61/622,158, filed Apr. 10, 2012, and is hereby incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to baluns generally and, more particularly, to a method and/or apparatus for implementing a broadband integrated single ended to differential active balun with an n-Way power splitter, a DC power shutdown circuit, and/or a default-on port. 
     BACKGROUND OF THE INVENTION 
     Conventional broadband receiver networks implement a number of components that split a single ended signal into multiple differential outputs. Such conventional receivers tend to consume power when the receiver is in a standby mode. Such standby power tends to deplete battery life and reduce operating times in the event of a consumer power failure. 
     It would be desirable to implement a circuit (or device) with an integrated active balun, default-on switch, power shutdown, and/or n-way splitter in an integrated circuit. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a switch, a balun and a splitter. The switch may be configured to provide (i) a first signal on a first path when a power signal is not present and (ii) a second signal on a second path when the power signal is present. The first path activates only the first signal and a ground signal. The second path activates only the second signal. The balun circuit may be configured to convert the second signal to a differential signal. The splitter circuit may be configured to generate a plurality of differential output signals in response to the differential signal. 
     The objects, features and advantages of the present invention include providing a broadband balun that may (i) implement an integrated single ended to differential active balun, (ii) provide an n-way power splitter, (iii) provide a DC power shutdown circuit, (iv) be implemented without compromising RF signal fidelity, (v) minimize distortion, (vi) provide a number of components on a single low cost Integrated Circuit, (vii) maintain linearity, (viii) provide a low noise figure performance, and/or (ix) provide a default-on path that may be useful during power failures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a block diagram of a context of the present invention; 
         FIG. 2  is a diagram of a balun and a power shutdown circuit; 
         FIG. 3  is a diagram of a splitter circuit; 
         FIG. 4  is a diagram of a filter; 
         FIG. 5  is a diagram of a filter; 
         FIG. 6  is a diagram of a switch; 
         FIG. 7  is a diagram of simulated output gain performance; 
         FIG. 8  is a diagram of simulated noise figure performance; 
         FIG. 9  is a diagram of simulated phase delta performance; and 
         FIG. 10  is a diagram of simulated amplitude delta performance. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 1 , a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises a block (or circuit)  102 , a block (or circuit)  104 , a block (or circuit)  106 , and a block (or circuit)  108 . The circuit  100  may be connected to a block (or circuit)  120  and/or a block (or circuit)  122 . The circuit  102  may be implemented as a switch. The circuit  104  may be implemented as an active balun. The circuit  106  may be implemented as a power shutdown circuit. The circuit  108  may be implemented as a splitter circuit. The circuit  108  generally comprises a number of blocks (or circuits)  110   a - 110   n . The circuit  110   a  may be implemented as a first portion of the splitter circuit  108 . The circuit  110   n  may be implemented as a second portion of the splitter circuit  108 . The particular number of circuits  110   a - 110   n  may be varied to meet the design criteria of a particular implementation. For example, an unrestricted number of splitters (e.g., a 3-way, 4-way, etc.) may be implemented. The circuit  100  may implement the circuit  102 , the circuit  104 , the circuit  106 , and/or the circuit  108  on a single Integrated Circuit. In one example, one or more of the circuit  102 , the circuit  104 , the circuit  106 , and/or the circuit  108  may be implemented as a first Integrated Circuit. Other portions of the circuit  102 , the circuit  104 , the circuit  106 , and/or the circuit  108  may be implemented as a second Integrated Circuit. 
     The circuit  102  may receive a signal (e.g., IN) and a signal (e.g., CONTROL). The signal CONTROL may be a power signal, such as a DC logic source (e.g., that may be generated in response to AC service provided to the premise). The circuit  102  may present a signal (e.g., SWA) and a signal (e.g., D_ON). The signal D_ON may represent a default on signal that may be available during a potential power failure condition. The signal IN may be a single ended input signal. The filter circuit  120  may receive the signal SWA and may present a signal AIN. The circuit  104  may receive the signal AIN and present a differential signal (e.g., AO+ and AO−). The circuit  104  may also receive a signal (e.g., C). The circuit  106  may receive a signal (e.g., VSHUT) and may present the signal C. The filter circuit  122  may receive the signals AO+ and AO− and may present a differential signal (e.g., AS− and AS+). The circuit  110   a  may generate a signal (e.g., O 1 +) and a signal (e.g., O 2 +) in response to the signal AS+. Similarly, the circuit  110   n  may generate a signal (e.g., O 1 −) and a signal (e.g., O 2 −) in response to the signal AS−. 
     Referring to  FIG. 2 , a more detailed diagram of the circuit  104  and the circuit  106  is shown. The circuit  104  generally comprises a resistor  130 , a transistor  132 , a transistor  134  and a resistor  136 . The circuit  106  generally comprises a transistor  138  and a resistor  140 . The transistor  132  may have a drain that may receive the signal AO+ and a source that may be connected to the resistor  136 . Similarly, the transistor  134  may have a drain that may receive the signal AO- and a source that is connected to the resistor  136 . A gate of the transistor  134  may be connected to ground. A gate of the transistor  132  may be connected through the resistor  130  to ground. Additionally, the gate of the transistor  134  may receive the signal AIN. The circuit  134  may convert the differential signal AIN into a differential signal AO+ and AO−. The signal C may be connected to the sources of the transistors  132  and  134  through the transistor  136 . 
     The circuit  106  may generate the signal C in response to the signal VSHUT. The signal VSHUT may be AC coupled to ground through a capacitor (e.g., C 1 ). The transistor  138  may receive the signal VSHUT through the resistor  140 . A source of the transistor  138  may be connected through an inductor (e.g., L 1 ) to ground. A drain of the transistor  138  may generate the signal C. The transistors  132 ,  134  and  138  may be implemented, in one example, as field-effect transistors (FETs). However, the particular type of transistor implemented may be varied to meet the design criteria of a particular implementation. For example, bi-polar transistors (or other transistor types) may be implemented. 
     Referring to  FIG. 3 , a more detailed diagram of the circuit  108  is shown. The circuit  110   a  generally comprises a resistor  150 , a resistor  152 , a resistor  154 , and a resistor  156 . The signal AS+ may be presented to a node between the resistor  150  and the resistor  152 . One side of the resistor  150  and one side of the resistor  154  may be used to generate the signal O 1 +. One side of the resistor  152  and one side of the resistor  156  may be used to generate the signal O 2 +. A capacitor (e.g., C 2 ) and a capacitor (e.g. C 3 ) may be connected to the signal O 1 + and the signal O 2 +, respectively. The capacitor C 2  and the capacitor C 3  may provide DC blocking or filtering. 
     The circuit  110   n  generally comprises a resistor  160 , a resistor  162 , a resistor  164 , and a resistor  166 . The signal AS− may be presented to a node between the resistor  160  and the resistor  162 . One side of the resistor  160  and one side of the resistor  164  may be used to generate the signal O 1 −. One side of the resistor  162  and one side of the resistor  166  may be used to generate the signal O 2 −. A capacitor (e.g., C 4 ) and a capacitor (e.g., C 5 ) may provide DC blocking and/or a filtering capacitor effect to the signal O 1 − and the signal O 2 −. 
     Referring to  FIG. 4 , a more detailed diagram of the circuit  120  is shown. The circuit  120  generally comprises a capacitor (e.g., C 6 ) and an inductor (e.g., L 2 ). The circuit  120  may be configured to generate the signal AIN in response to the signal SWA. 
     Referring to  FIG. 5 , a more detailed diagram of the circuit  122  is shown. The circuit  122  generally comprises a capacitor (e.g., C 7 ), a capacitor (e.g., C 8 ), a capacitor (e.g., C 9 ), a capacitor (e.g., C 10 ), an inductor (e.g., L 3 ), an inductor (e.g., L 4 ) and an inductor (e.g., L 5 ). The capacitor C 7  may be implemented as a bypass capacitor. The capacitor C 8  may be implemented as a blocking capacitor. The capacitor C 9  may be implemented as a bypass capacitor. The capacitor C 10  may be implemented as a blocking capacitor. The circuit  122  may generate the signal AO+ and AS+ in response to differential signals AO− and AS−. The circuit  122  may be configured to filter the signal VDD from the signal AS+ and the signal AS−. The circuit  122  may also be configured to filter the signal AO+ and the signal AO− from the signal AS+ and the signal AS−, respectively. 
     Referring to  FIG. 6 , an example of the switch  102  is shown. Details of the switch  102  may be found in co-pending application Ser. No. 13/402,340, filed Feb. 22, 2012, which is hereby incorporated by reference in its entirety. The transistor  106  is shown terminated by a resistor (e.g., Z 01 ) and a capacitor (e.g., DC_BLOCK 1 ). Similarly, the transistor  112  is shown terminated with a resistor (e.g., Z 02 ) and a capacitor (e.g., DC_BLOCK 2 ). 
     The circuit  100  may use the active balun circuit  104  to transform the single ended input signal IN into two output signals AO+ and AO− with 0°/180° phase differential. By implementing one or more of the circuits  102 ,  104 ,  106 , and/or  108  on a single Integrated Circuit, the circuit  100  may operate with very low phase and/or amplitude imbalance. The active balun circuit  104  may provide high gain and/or low input and output match across a broad frequency band. The active balun circuit  104  may be implemented using components that may provide a broadband low return loss on all RF ports, a DC bias setting resistor and/or low phase and amplitude imbalance. The FET size and/or operating current of the transistors  132  and/or  134  may be selected to operate at low DC power (e.g., &lt;250 mW) while maintaining low distortion and/or a high linearity, and low noise figure. The default-on switch  102 , the DC power shutdown circuit  106 , and/or the resistive splitter  108  may be used to provide an integrated circuit that provides a single ended to differential active balun, a default-on switch, a power shutdown, and/or an n-way power splitter functionality. 
     Referring to  FIG. 7 , a simulated output gain performance of the circuit  100  is shown. The simulation shows an output gain performance (e.g., an amplification) of the circuit  100  over a linear range of frequencies (e.g., 0 Hz-1.2 GHz). A point M 13  and a point M 23  are shown. The point M 13  is shown having a gain of 8.131 dB at a frequency of 63.2 MHz. The point M 26  is shown having a gain of 9.155 db at a frequency of 991.2 MHz. The output gain performance of the circuit  100  is shown maintaining linearity of an amplified signal over the range of frequencies. 
     Referring to  FIG. 8 , a simulated noise figure performance of the circuit  100  is shown. The simulation shows a noise figure performance of the circuit  100  over the linear range of frequencies (e.g., 0 Hz-1.2 GHz). The simulation shows the circuit  100  maintaining a low noise performance over the linear range. 
     Referring to  FIG. 9 , a simulated phase delta performance of the circuit  100  is shown. The simulation shows a phase delta performance of the circuit  100  over the linear range of frequencies (e.g., 0 Hz-1.2 GHz). The simulation shows the circuit  100  operating with a low phase imbalance over the linear range. 
     Referring to  FIG. 10 , a simulated amplitude delta performance of the circuit  100  is shown. The simulation shows an amplitude delta of the circuit  100  over the linear range of frequencies (e.g., 0 Hz-1.2 GHz). The simulation shows the circuit  100  operating with a low amplitude imbalance over the linear range. 
     The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.

Technology Category: 5