Patent Document

BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to converters and, more particularly, to a control device for quasi-resonant AC/DC off-line converters. 
         [0003]    2. Description of the Related Art 
         [0004]    Converters, and particularly offline drivers of LED-based lamps for bulb replacement, are often desired to have a power factor greater than 0.9, low total harmonic distortion (THD) and to provide safety isolation. At the same time, for cost reasons, it is desirable to regulate the output DC current required for proper LED driving without closing a feedback loop. 
         [0005]    High-power-factor (hi-PF) flyback converters are able to meet power factor and isolation specifications with a simple and inexpensive power stage. In a hi-PF flyback converter there is not an energy reservoir capacitor directly connected across the DC side of the input rectifier bridge, so that the voltage applied to the power stage is a rectified sinusoid. To achieve high-PF, the input current must track the input voltage, thus originating a time-dependent input-to-output power flow. As a result, the output current contains a large AC component at twice the main line&#39;s frequency. 
         [0006]    A quasi-resonant flyback converter has the power switch turn-on synchronized to the instant the transformer demagnetizes (i.e. the secondary current has become zero), normally after an appropriate delay. This allows the turn-on to occur on the valley of the drain voltage ringing that follows the demagnetization, often termed “valley-switching.” Most commonly, peak current mode control is used, so the turn-off of the power switch is determined by the current sense signal reaching the value programmed by the control loop that regulates the output voltage or current. 
         [0007]    In a flyback converter the input current is the average of the primary current, which flows only during the ON-time of the power switch, resulting in a series of triangles separated by voids corresponding to the OFF-time of the power switch. This “chopping” causes the average value of the primary current to be lower than half the peak value and depend on the mark-space ratio of the triangles. As a result, the input current is no longer proportional to the envelope of the peaks and unlike the envelope, which is sinusoidal, the input current is not sinusoidal. Although a sinusoidal-like shape is maintained, the input current is distorted. This distorted sinusoidal input current results in a flyback converter that fails to achieve low THD or unity power factor. 
         [0008]      FIG. 1  shows a schematic of a high power factor (Hi-PF) quasi resonant (QR) flyback converter  30  according to the prior art. On the primary side, the flyback converter  30  comprises a bridge rectifier  34  having inputs  32 , configured to receive an AC voltage from an AC power line, a first output connected to ground, and a second output at which the rectifier is configured to produce a rectified voltage V in (θ). The converter  30  also includes a capacitor C in , which serves as a high-frequency smoothing filter, connected across the output terminals of the bridge rectifier  34 , with a negative terminal connected to ground. A primary winding L p  of a transformer  36  has one end connected to the positive terminal of the capacitor C in  and the transformer  36  also includes an auxiliary winding L aux  coupled to a resistor R ZCD . The other end of the primary winding L p  is connected to the drain of a power switch M. The power switch M has a source terminal connected to ground via a sensing resistor Rs, the resistor R S  allowing reading of the current flowing through M (i.e. the current flowing through L p  when M is ON) as a positive voltage drop across the resistor Rs itself. A controller  38  controls the power switch M. The primary side of the converter also includes a resistive voltage divider, made up of resistors R a  and R b  connected in parallel with the capacitor C in , and a clamp circuit  39  that clamps the spikes on the drain voltage due to the leakage inductance of the primary winding L p . 
         [0009]    On the secondary side of the converter, a secondary winding L s  of the transformer  36  has one end connected to the secondary ground and the other end connected to the anode of a diode D having a cathode connected to the positive plate of a capacitor C out  that has its negative plate connected to the secondary ground. This flyback converter  30  generates at its output terminals across C out  a DC voltage V out  that will supply a load (not shown). The load is generally a string of high-brightness LEDs. 
         [0010]    The quantity to be regulated (either the output voltage V out  or the output current I out ) is compared to a reference value and an error signal I FB  depending on their difference is generated. This signal is transferred to the primary side by an isolated feedback block  40 , typically implemented by an optocoupler (or other means able to cross the isolation barrier complying with the safety requirements of IEC60950). On the primary side, this error signal is a current I FB  that is sunk from a dedicated pin FB in the controller  38 , producing a control voltage V c  on said pin FB. If the open-loop bandwidth of the overall control loop, determined by a frequency compensation network located inside the isolated feedback block  40 , is narrow enough—typically below 20 Hz—and a steady-state operation is assumed, the control voltage V c  can be regarded as a DC level, at least to a first approximation. 
         [0011]    Inside the controller  38 , control voltage V c  is internally fed into one input of a multiplier block  42 , having another input that receives, via a pin MULT and a midpoint of the resistive divider R a /R b  a portion of the instantaneous rectified line voltage V in (θ) sensed across C in . 
         [0012]    The output of the multiplier block  42  is the product of a rectified sinusoid times a DC level, then still a rectified sinusoid whose amplitude depends on the rms line voltage V in (θ) and the amplitude of the control voltage V c ; this will be the reference voltage Vcs REF (θ) for the peak primary current. 
         [0013]    The Vcs REF (θ) signal is fed to the inverting input of a pulse width modulation comparator  44  that receives at its non-inverting input the voltage Vcs(t, θ), sensed across the sense resistor Rs, which is a voltage proportional to the instantaneous current I p (t, θ) flowing through the primary winding L p  of the transformer  36  and the power switch M when the power switch is ON. Assuming power switch M is initially ON, the current through the primary winding L p  will be ramping up and so will the voltage across Rs. When Vcs(t, θ) equals Vcs REF (θ) the PWM comparator  44  resets a SR flip-flop  46 , which switches off the power switch M. Therefore, the output of the multiplier  42 , shaped as a rectified sinusoid, determines the peak value of the current in the primary winding L p  that, as a result, will be enveloped by a rectified sinusoid. 
         [0014]    When the power switch M is switched off, the energy stored in the primary winding L p  is transferred by magnetic coupling to the secondary winding L s  and then dumped into the output capacitor C out  and the load until the secondary winding L s  is completely demagnetized. At this point, the diode D opens and the drain node, which was fixed at V in (θ)+V R  while the secondary winding L s  and the diode D were conducting, becomes floating. The drain node voltage would tend to eventually reach the instantaneous line voltage V in (θ) through a damped ringing due to its parasitic capacitance that starts resonating with the primary winding L p . The quick drain voltage fall that follows transformer  36  demagnetizing is coupled to a pin ZCD of the controller  38  through the auxiliary winding L aux  and the resistor R ZCD . A zero-crossing detector (ZCD) block  48  releases a pulse every time it detects a negative-going edge falling below a threshold and this pulse sets the SR flip flop  46  and drives ON the power switch M, starting a new switching cycle. 
         [0015]    An OR gate  50  between the ZCD block  48  and the set input of the SR flip flop  46  allows the output of a starter block  52  to initiate a switching cycle. The starter block  52  produces a signal at power-on when no signal is available on the pin ZCD input and prevents the converter  30  from getting stuck in case the signal on the pin ZCD input is lost for any reason. 
         [0016]    Assuming θε(0, π), according to the control scheme under consideration the peak envelope of the primary current is given by: 
         [0000]        I   pkp (θ)= I   p ( T   ON ,θ)= I   PKp  sin θ.
 
         [0017]    It is worth noticing that this scheme results in a constant ON-time T ON  of the power switch M: 
         [0000]    
       
         
           
             
               T 
               ON 
             
             = 
             
               
                 Lp 
                  
                 
                   
                     
                       I 
                       PKp 
                     
                      
                     
                         
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                   
                   
                     
                       
                         V 
                         PK 
                       
                        
                       sin 
                        
                       
                           
                       
                        
                       θ 
                     
                      
                     
                         
                     
                   
                 
               
               = 
               
                 Lp 
                  
                 
                   
                     I 
                     PKp 
                   
                   
                     
                       V 
                       PK 
                     
                      
                     
                         
                     
                   
                 
               
             
           
         
       
     
         [0018]    For simplicity, the OFF-time T OFF (θ) of the power switch M will be considered coincident with the time T FW (θ) during which current circulates on the secondary side. In other words, the time interval T R  during which the voltage across the primary switch rings until reaching the valley of the ringing will be neglected. This is acceptable as long as T R &lt;&lt;T OFF (θ). 
         [0019]    The switching period T(θ) is therefore given by: 
         [0000]        T (θ)= T   ON   +T   FW (θ).
 
         [0020]    Considering volt-second balance across the primary winding L p  it is possible to write: 
         [0000]    
       
         
           
             
               
                 T 
                 FW 
               
                
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 T 
                 ON 
               
                
               
                 
                   
                     
                       V 
                       PK 
                     
                      
                     
                         
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                   
                   
                     V 
                     R 
                   
                 
                 . 
               
             
           
         
       
     
         [0021]    where V R  is the reflected voltage, i.e. the output voltage V out  times the primary-to-secondary turns ratio n=N p /N s , seen across the primary winding L p  of the transformer  36  in the time interval T FW (θ): 
         [0000]        V   R   =n ( V   out   +V   F ) 
         [0022]    wherein V F  is the forward drop on the secondary diode D. Therefore, T(θ) can be rewritten as: 
         [0000]        T (θ)= T   ON (1+ K   v  sin θ)
 
         [0023]    with K v =V PK /V R . 
         [0024]    The input current to the converter  30  is found by averaging the primary current I p (t,θ) in the primary winding L p  over a switching cycle. I p (t,θ) is the series of gray triangles in the right-hand side diagram of  FIG. 2  so it is found that: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       in 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         1 
                         2 
                       
                        
                       
                         I 
                         pkp 
                       
                        
                       
                           
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                        
                       
                         
                           T 
                           ON 
                         
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                     
                     = 
                     
                       
                         1 
                         2 
                       
                        
                       
                         I 
                         PKp 
                       
                        
                       
                         
                           
                             sin 
                              
                             
                                 
                             
                              
                             θ 
                           
                           
                             1 
                             + 
                             
                               
                                 K 
                                 v 
                               
                                
                               sin 
                                
                               
                                   
                               
                                
                               θ 
                             
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0025]    This shows that the input current is not a pure sinusoid. The function sin θ/(1+K v  sin θ), plotted in  FIG. 3 a    for different values of K v , is a periodic even function, at twice the line frequency. Conversely, the current drawn from the mains will be its “odd counterpart,” at the line frequency, as shown in  FIG. 3   b.    
         [0026]    This current is sinusoidal only for K v =0; when K v ≠0, although a sinusoidal-like shape is maintained, the input current is distorted, the higher K v  the higher the distortion. Since K v  cannot be zero (which would require the reflected voltage to tend to infinity), this prior art QR control scheme does not permit zero total harmonic distortion (THD) of the input current nor unity power factor in the flyback converter  30  even in the ideal case. 
         [0027]      FIG. 4 , shows the plots of the THD of the input current and of the Power Factor vs. K v  for the converter  30  of  FIG. 1 . 
         [0028]    Although the distortion is significant, especially at high line (i.e. high K v ), the individual harmonics are still well within the limits considered by the regulation on the limits for harmonic current emissions, the IEC61000-3-2 (or its Japanese homologous, the JEIDA-MITI). An example of harmonic measurements on a real-world application is shown in  FIG. 5 . For this reason the Hi-PF QR flyback converter is currently widely used, especially in solid stating lighting (SSL) applications where safety isolation from the power line is required by regulations. These include LED drivers from few watts to few ten watts for residential and professional lighting. 
         [0029]    Still considering the SSL market, recently this inherent distortion is becoming a problem. In fact, as shown in the plot of  FIG. 4 , it is difficult to meet the target THD&lt;10% (or even lower) that is becoming a market specification in some geographical areas. Low values of Kv should be used even at high line, which means a high reflected voltage V R ; since the power MOSFET in a flyback converter should be rated for a breakdown voltage significantly larger than V PKmax +V R , in principle a high V R  is provided using a high voltage rating MOSFET, which is more expensive and has higher parasitic losses. In practice, the target V R  might be so high that a MOSFET with adequate voltage rating could be prohibitive in terms of cost or originate too much power loss, or even be unavailable. 
       BRIEF SUMMARY 
       [0030]    One embodiment of the present disclosure is a quasi-resonant flyback converter having a sinusoidal input current that achieves low total harmonic distortion and high power factor. 
         [0031]    One embodiment of the present disclosure is directed to a control circuit that enables Hi-PF QR flyback converters with peak current mode control to draw a sinusoidal current from the input source. 
         [0032]    One embodiment of the present disclosure is directed to a device for controlling a power transistor of a power circuit. The device has a driver circuit, the driver circuit including a first input configured to receive a voltage reference signal, and an output configured to drive the power transistor based on the voltage reference signal. A driver control circuit is configured to provide the voltage reference signal to the driver circuit, with the driver control circuit including a multiplier having a first input configured to receive a first signal based on an feedback signal from the power circuit, a second input configured to receive a second signal, and an output, the multiplier being configured to produce a multiplier signal based on a multiplication of the first and second signals. The driver control circuit also includes a first current generator coupled to the multiplier and configured to produce a current reference signal, a resistor coupled to an output of the first current generator, and a switch configured to couple the resistor in parallel with a capacitor when the power transistor is on. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0033]      FIG. 1  shows a schematic of a Hi-PF QR flyback converter according to the prior art. 
           [0034]      FIG. 2  shows the waveforms of the circuit in  FIG. 1  during normal operation. 
           [0035]      FIG. 3 a    shows the shape of the average primary current in the circuit of  FIG. 1 . 
           [0036]      FIG. 3 b    shows the shape of the input current in the circuit of  FIG. 1 . 
           [0037]      FIG. 4  shows the plot of the THD of the input current and the power factor obtained with the circuit of  FIG. 1 . 
           [0038]      FIG. 5  shows a harmonic test results in a Hi-PF QR Flyback converter of  FIG. 1 . 
           [0039]      FIG. 6  shows a boost converter and the current waveforms on a line cycle time scale. 
           [0040]      FIG. 7  illustrates the schematic of a Hi-PF QR flyback converter according to the present disclosure. 
           [0041]      FIG. 8  illustrates waveforms of the circuit in  FIG. 7  during normal operation. 
           [0042]      FIG. 9  shows an alternative embodiment of a Hi-PF QR flyback converter according to the present disclosure. 
           [0043]      FIG. 10  illustrates waveforms of the circuit in  FIG. 9  during normal operation. 
           [0044]      FIG. 11  shows an alternative embodiment of the present disclosure using an existing PFC controller. 
           [0045]      FIG. 12  shows the simulation results for the circuit in  FIG. 7  at V in =90 VAC and full load. 
           [0046]      FIG. 13  shows the simulation results for the circuit in  FIG. 7  at V in =265 Vac and full load. 
           [0047]      FIG. 14  shows the experimental results on the converter according to the prior art at V in =110 Vac (left), and V in =230 Vac (right). 
           [0048]      FIG. 15  shows the experimental results on the converter of  FIG. 11  at V in =110 Vac (left) and at V in =230 Vac (right). 
           [0049]      FIG. 16  shows the experimental performance comparison between the prior art method and the embodiment of  FIG. 11 . 
       
    
    
     DETAILED DESCRIPTION 
       [0050]    This disclosure presents a novel control method that enables Hi-PF QR flyback converters with peak current mode control to ideally draw a sinusoidal current from the input source, thus performing like boost converters operated in the same way. 
         [0051]    One idea of the present disclosure stems from observing the waveforms shown on the right-hand side of  FIG. 2  and comparing them to those of a boost converter (shown in  FIG. 6  along with the topology). In the boost converter, the input current is the average of the inductor current, which flows both during the ON-time and the OFF-time of the power switch. As a result, being a series of contiguous triangles, the average value of the inductor current is half the peak. Also, given that the envelope of the peaks is sinusoidal, the input current will be sinusoidal. 
         [0052]    In contrast, in the prior art flyback converter of  FIG. 1 , the input current is the average of the primary current, which flows only during the ON-time of the power switch and is a series of triangles separated by voids corresponding to the OFF-time of the power switch, as shown in  FIG. 2 . This “chopping” causes the average value of the primary current to be lower than half the peak value and depending on the mark-space ratio of the triangles. As a result, the input current is no longer proportional to the envelope of the peaks and, unlike the envelope that is sinusoidal, the input current will not be sinusoidal. 
         [0053]    To express this quantitatively, it is worth re-examining (1): 
         [0000]    
       
         
           
             
               
                 I 
                 in 
               
                
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 1 
                 2 
               
                
               
                 I 
                 pkp 
               
                
               
                   
               
                
               
                 ( 
                 θ 
                 ) 
               
                
               
                 
                   
                     T 
                     ON 
                   
                   
                     T 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 . 
               
             
           
         
       
     
         [0054]    The term I pkp (θ), which represents the peak envelope of the primary current, is sinusoidal so the distortion is originated by the term T ON /T(θ), introduced by the primary current being chopped, which is not constant (T ON  is constant but T(θ) is not). 
         [0055]    The inventors discovered that if the current reference Vcs REF (θ) that determines I pkp (θ) is distorted with a term T(θ)/T ON , this will cancel out the term T ON /T(θ) introduced by averaging and result in a sinusoidal average primary current, i.e. in a sinusoidal input current. Then, the control objective can be expressed in the following terms: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Vcs 
                       REF 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       Vcs 
                       x 
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0056]    wherein T ON  is denoted as a function of the instantaneous line phase θ. In fact, with a method different from that of the prior art it is not necessarily constant. 
         [0057]      FIG. 7  shows a hi-PF flyback converter  100 A according to one embodiment of the present disclosure. The converter  100 A of  FIG. 7  has on the primary side a bridge rectifier  104  having inputs  106 , configured to receive an AC voltage from an AC power line, a first output connected to ground, and a second output at which the rectifier is configured to produce a rectified voltage V in (θ). The converter  100 A also includes a capacitor C in , which serves as a high-frequency smoothing filter, connected across the output terminals of the bridge rectifier  104 , with a negative terminal connected to ground. A primary winding L p  of a transformer  108  has one end connected to the positive terminal of the capacitor C in  and includes an auxiliary winding L aux . The other end of the primary winding L p  is connected to the drain of a power switch M. The power switch M has a source terminal connected to ground via a sensing resistor Rs, the resistor R S  allowing reading of the current flowing through M (i.e. the current flowing through L p  when M is ON) as a positive voltage drop across the resistor Rs itself. A controller  102 A controls the power switch M. As in the converter  30  of  FIG. 1 , the converter  100 A includes the resistive voltage divider R a /R b  connected in parallel with the capacitor C in , and the clamp circuit  39 . 
         [0058]    On the secondary side of the converter  100 A, a secondary winding L s  of the transformer  108  has one end connected to a secondary ground and the other end connected to the anode of a diode D having the cathode connected to the positive plate of a capacitor C out  that has its negative plate connected to the secondary ground. An output voltage V out  supplies power to a load (not shown). The quantity to be regulated (either the output voltage V out  or the output current I out ) is compared to a reference value and an error signal I FB  is generated. This signal is transferred to the primary side by an isolated feedback block  134 , typically implemented by an optocoupler (or other means able to cross the isolation barrier complying with the safety requirements of IEC60950). On the primary side, this error signal I FB  is sunk from a dedicated pin FB in the controller  102 A, producing a control voltage V c  on said pin FB. The open-loop bandwidth of the overall control loop is determined by a frequency compensation network located inside the isolated feedback block  134 . 
         [0059]    The controller  102 A has a shaper circuit  120 A, a PWM comparator  122 , an SR flip flop  124 , an OR gate  126 , a starter block  128 , a ZCD block  130 , and a driver  132 . The shaper circuit  120 A is configured to produce a reference voltage V CSREF  based on a voltage V c  and a portion of the instantaneous rectified line voltage V in (θ) received from the midpoint of the resistive divider R a /R b  via the pin MULT. The PWM comparator  122  is configured to receive as inputs the reference voltage V CSREF  and the voltage V CS  sensed at the resistor R S . The SR flip flop  124  has reset and set inputs R, S that respectively receive the output of the PWM comparator  122  and the output of the OR gate  126 . The driver  132  receives as an input the output of the SR flip flop  124 , and configured to drive the power switch M via an output signal provided to a terminal GD coupled to the gate of the power switch M. The ZCD block  130  is configured to release a pulse when a detected falling edge of a signal, received from the auxiliary winding L aux  and resistor R ZCD  via the terminal ZCD, goes below a threshold value. The starter block  128  is configured to release a pulse on start-up or when the ZCD block  130  receives no input signal. The OR gate  126  has inputs that respectively receive the outputs of the starter block  128  and ZCD block  130  and provides a set signal to the set input S of the flip-flop  124  when either of the outputs from the starter block  128  and ZCD block  130  is positive. 
         [0060]    A multiplier  140  is coupled to the shaper circuit  120 A. The shaper circuit  120 A has a current generator  142 , a resistor R t , and a switch  143  that switchably couples the resistor R t  to ground. The multiplier  140  has a first input that receives the voltage V c , a second input that receives the portion of the line voltage V in (θ) from the terminal MULT, and an output at which the multiplier produces a multiplied voltage that is the product of the two voltages received at the inputs. The current generator  142  is controlled by the output of the multiplier  140  and is configured to output a current I ch (θ) that acts on the switched resistor R t  and an external capacitor C t  having one terminal connected to ground. 
         [0061]    The resistor R t  is connected in parallel to the capacitor C t  when a signal Q provided to the control terminal of the switch  143  is high. The signal Q is provided by the output of the SR flip-flop  124  and is high during the on-time of the power switch M. The switch  143  disconnects the resistor R t  from ground when the signal Q is low, i.e. during the off-time of the power switch M. The voltage developed across C t  is the reference voltage Vcs REF (θ) and is fed to the inverting input of the PWM comparator  122 . 
         [0062]    In one embodiment of the present disclosure C t  is integrated in a semiconductor chip with the controller  102 A, thus saving one pin of the controller  102 A and one external component. 
         [0063]    The current I ch (θ) provided by the current generator  142  can be expressed as: 
         [0000]        I   ch (θ)= g   m   K   M   K   p ( V   PK  sin θ) V   c  
 
         [0064]    where g m  is the voltage-to-current gain of the current generator  142 , K M  is the gain of the multiplier, K p  is the divider ratio of the resistive divider R a /R b , and V PK  sin (θ) is the peak value of the line voltage V in (θ). Note that the control voltage V c  is nearly constant along a line half-cycle, thus the charging current I ch (θ) has a sinusoidal shape. 
         [0065]    An assumption for the following analysis is that T(θ)&lt;&lt;R t  C t &lt;&lt;1/f L . In this way, the switching frequency ripple across the capacitor C t  is negligible and the current I ch (θ) can be considered constant within each switching cycle. 
         [0066]    The reference voltage Vcs REF (θ) developed across the capacitor C t  by charge balance is therefore: 
         [0000]    
       
         
           
             
               
                 
                   Vcs 
                   REF 
                 
                  
                 
                   ( 
                   θ 
                   ) 
                 
               
               = 
               
                 
                   
                     R 
                     t 
                   
                    
                   
                     
                       I 
                       ch 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                    
                   
                     
                       T 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     
                       
                         T 
                         ON 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                 
                 = 
                 
                   
                     R 
                     t 
                   
                    
                   
                     g 
                     m 
                   
                    
                   
                     K 
                     M 
                   
                    
                   
                     K 
                     p 
                   
                    
                   
                     
                       V 
                       c 
                     
                      
                     
                       ( 
                       
                         
                           V 
                           PK 
                         
                          
                         sin 
                          
                         
                             
                         
                          
                         θ 
                       
                       ) 
                     
                   
                    
                   
                     
                       T 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     
                       
                         T 
                         ON 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                 
               
             
             , 
           
         
       
     
         [0067]    The control circuit in  FIG. 7  therefore meets the control objective (2) and achieves a sinusoidal input current in the Hi-PF QR flyback converter  100 A, resulting in high power factor and low total harmonic distortion. 
         [0068]      FIG. 8  shows the waveforms of the converter  100 A of  FIG. 7 . On the left-hand side are the waveforms on a switching period time scale, on the right-hand side the waveforms on a line cycle time scale. 
         [0069]      FIG. 9  shows another embodiment of a QR flyback converter  100 B according to the present disclosure. The converter  100 B is identical to the converter  100 A of  FIG. 7  except that the converter  100 B includes a controller  102 B instead of the controller  102 A. The controller  102 B includes a shaper circuit  120 B that has the same components as the shaper circuit  120 A of  FIG. 7 , but the multiplier  140  is connected differently to the components in the two shaper circuits  120 A,  120 B. In particular, the output of the multiplier  140  is connected to the inverting input of the PWM comparator  122  of the shaper circuit  120 B, while the input of the multiplier  140  that is connected to the resistor divider Ra-Rb by the terminal MULT in  FIG. 7  is connected to one terminal of the external capacitor C t  in  FIG. 9 . Unlike the shaper circuit  120 A of  FIG. 7 , the current generator  142  of the shaper circuit  120 B of  FIG. 9  is directly controlled by the portion of the line voltage V in (θ) received from the resistor divider Ra-Rb via the pin MULT in the controller  102 B. As a result, the current I ch (θ) produced by the current generator  142  is proportional to the sensed input voltage: 
         [0000]        I   ch (θ)= g   m   K   p ( V   PK  sin θ).
 
         [0070]    As in the controller  102 A, the capacitor C t  is charged by the current generator  142  and discharged by the switched resistor R t  in the controller  102 B. Also in this controller  102 B the connection of the input voltage V c  is unchanged from the control voltage V c  of the controller  102 A. Similar to the controller  102 A, the resistor R t  is connected in parallel to the capacitor C t  by the switch  143  only when the signal Q is high, i.e. during the on-time of the power switch M. 
         [0071]    At this point it is clear that a third possible embodiment would have the current generator  142 , resistor R t , switch  143 , and capacitor C t  connected to the multiplier  140  input where the control voltage V c  is applied, with the current I ch (θ) of current generator  142  proportional to the control voltage V c . This will be taken for granted and will not be further considered. 
         [0072]      FIG. 10  illustrates the waveforms of the circuit of  FIG. 9 . On the left-hand side are the waveforms on a switching period time scale, on the right-hand side the waveforms on a line cycle time scale. 
         [0073]      FIG. 11  shows another embodiment of a flyback converter  100 C, using an existing PFC controller  102 C, such as the L6561 available from STMicroelectronics. 
         [0074]    In this embodiment, a shaper circuit  120 C is implemented with a small-signal MOSFET Ma, its gate resistor Rg, the capacitor C t  and the resistor Rb. A small-signal BJT is also considered for the switch, in place of the small-signal MOSFET. 
         [0075]    The MOSFET Ma is driven by the gate driver GD of the power switch M, thus connecting the lower resistor Rb of the divider Ra-Rb to ground during the on-time of the power switch M. Since the input voltage is much larger than the voltage on pin MULT for most of the line cycle, resistor Ra performs as the current generator, producing current I ch (θ) as: 
         [0000]    
       
         
           
             
               
                 I 
                 ch 
               
                
               
                 ( 
                 θ 
                 ) 
               
             
             ≈ 
             
               
                 1 
                 Ra 
               
                
               
                 
                   ( 
                   
                     
                       V 
                       PK 
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
         [0076]    It is a common practice to have a bypass capacitor connected between pins MULT and GND to reduce noise pick-up in a sensitive point such as the multiplier input. The very same capacitor can serve as the capacitor C t  in  FIG. 11 . The value of the capacitor C t  will preferably be such that T(θ)&lt;&lt;Rb C t &lt;&lt;1/f L  is fulfilled under all operating conditions. 
         [0077]      FIGS. 12 and 13  show computer simulated timing diagrams for the circuit of  FIG. 7 . These diagrams show a very low distortion level of the input current (around 1% at V in =90 Vac, around 3.5% at V in =264 Vac), due to the input EMI filter and the nonidealities considered both in the controller  102 A and the power elements transformer  108 , bridge rectifier  104 , and power transistor M. 
         [0078]      FIG. 14  shows an oscilloscope picture with some waveforms taken with the flyback converter  30  of  FIG. 1 . Note the shape of the input current (green trace), which is a bit more rounded than, a sinusoid @ 110 Vac, while it is more heavily distorted at 230 Vac. 
         [0079]      FIG. 15  shows the same waveforms as in  FIG. 14  on the same controller  38  of  FIG. 1  with the addition of the external components switch Ma and gate resistor R g  of  FIG. 11 . The shape of the input current (the green trace) is almost perfectly sinusoidal both at 110 Vac and 230 Vac. 
         [0080]    These results are confirmed by the measurements summarized in  FIG. 16 , which shows a comparison of the values of THD of the input current and the PF in the original and the modified board. The improvement offered by the novel method over the prior art one is dramatic, with a THD less than 4% over the entire input voltage range. 
         [0081]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Technology Category: 5