Patent Document

CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of U.S. application Ser. No. 13/837,796, filed on Mar. 15, 2013, the contents of which are hereby incorporated by reference in their entirety. 
     
    
     BACKGROUND 
       [0002]    This invention relates to switched capacitor converters, and more particularly to efficient gate drivers for such converters. 
         [0003]    A switch-mode power converter is a specific type of power converter that produces an output voltage by switching energy storage elements (i.e. inductors and capacitors) into different electrical configurations using a switch network. A switched capacitor power converter is a type of switch-mode power converter that primarily utilizes capacitors to transfer energy. In such converters, the number of capacitors and switches increases as the conversion gain increases. 
         [0004]    As used herein, conversion gain represents a voltage gain if the switched capacitor power converter produces an output voltage that is larger than the input voltage or a current gain if the switched capacitor power converter produces an output voltage that is smaller than the input voltage. 
         [0005]      FIGS. 1-2  show two examples of switched capacitor power converters that receive an input voltage VI from a voltage source  16  and provide an output voltage VO to a load  18 . Both of the examples are also known as cascade multipliers. Note that in  FIG. 2 , a number of the switching devices of the circuit in  FIG. 1  are replaced with series of multiple devices, thereby reducing the maximum voltage across individual devices in the circuit. 
         [0006]    In normal operating, packets of charge are pumped along a chain of diode-connected NMOS transistors M 0 -M 5  as pump capacitors C 1 -C 3  are successively being charged and discharged. As shown in  FIGS. 1-2 , phase voltages VP 1 , VP 2  are one hundred and eighty degrees out of phase. Each of the NMOS transistors M 0 -M 5  is diode-connected, thereby only permitting boost operation (i.e. VO greater than VI). Additionally, the efficiency is severely impacted because a significant amount of voltage is dropped across each of the transistors M 0 -M 5  during normal operation. Therefore, there is a desire to operate the NMOS transistors M 0 -M 5  in their ohmic region, but due difficulty and/or complexity of driving the transistors M 0 -M 5 , a combination of both PMOS transistors and high-voltage transistors are typically used. 
         [0007]    If the transistors in the switched capacitor power converter are integrated on a single substrate then it can be desirable to use as few different types of devices as possible. For a given semiconductor process, cost is related to the number of mask layers. As the number of different types of devices in a semiconductor process increases so does the number of mask layers and hence the cost. 
         [0008]    Furthermore, it is well-known that electrons have a higher mobility than holes in silicon. Consequently, a NMOS device with a given on-resistance has a smaller gate capacitance than a PMOS device with the same on-resistance. It is also true that a NMOS device with a given gate capacitance has a smaller on-resistance than a PMOS device with the same gate capacitance. In a power converter, it is therefore desirable to replace as many PMOS devices in the main power path with NMOS devices and replace as many high-voltage devices with low-voltage devices. 
       SUMMARY 
       [0009]    In one aspect, in general, a switched capacitor power converter has a first terminal for coupling to a first external circuit at substantially a high voltage (e.g., 20 v), and a second terminal for coupling to a second external circuit at substantially a low voltage (e.g., 5 v) less than the high voltage in magnitude. A first plurality of active semiconductor switch elements are configured to electrically interconnect capacitors to one another and/or to the first or second terminal, in successive states. The switch elements are configured to interconnect at least some capacitors to one another through a series of multiple of the switch elements. A plurality of switch driving circuits are coupled to and for control by a drive output of one of the switch driving circuits. Each driving circuit has a control input, power connections, and a drive output coupled to and for control of one or more of the switch elements. At least some switch driving circuits are configured to be powered via the power connections of said driving circuits from one or more of the capacitors such that the voltage across the power connections of said driving circuit is substantially less than the high voltage. 
         [0010]    In another aspect, in general, a switched capacitor power converter has a first terminal for coupling to a first external circuit at substantially a high voltage and a second terminal for coupling to a second external circuit at substantially a low voltage less than the high voltage in magnitude. A plurality of active semiconductor switch elements is configured to electrically interconnect capacitors to one another and to the first or second terminal, in successive states. The switch elements and capacitors are configured to form multiple distinct charge transfer paths between the first terminal and the second terminal. A plurality of switch driving circuits are coupled to and for control by a drive output of one of the switch driving circuits, with each driving circuit having a control input, power connections, and a drive output coupled to and for control of one or more of the switch elements. At least some switch driving circuits are configured to be powered via the power connections of said driving circuits from one or more of the capacitors such that the voltage across the power connections of said driving circuit is substantially less than the high voltage. At least some of the switch driving circuits that control switch elements of one of the distinct charge transfer paths are powered from capacitors of one or more other charge transfer paths. 
         [0011]    Aspects can include one or more of the following features. 
         [0012]    The switched capacitor power converter further comprises a plurality of capacitors coupled to the first plurality of switch elements controllably coupled via the semiconductor switches, or comprises a plurality of terminals coupled to the first plurality of switch elements for connecting to the capacitors. 
         [0013]    The converted is configured to provide time varying voltages relative to the low voltage to at least some of the driving circuits. 
         [0014]    Each switch element has a maximum voltage rating less than the high voltage. 
         [0015]    Each of the series of switch elements comprises N elements, N&gt;1, and wherein the maximum voltage ratings of the switch elements is no greater than 2/N times the low voltage. 
         [0016]    The voltage across the power connections of the driving circuit is configured to be driven from the capacitors with less than or substantially equal to two times the low voltage. 
         [0017]    Each switch element in the series of multiple of the switch elements is driven by a corresponding driving circuit a plurality of switch driving circuits, each of said driving circuits are configured to be powered via the power connections of said driving circuits from different capacitors of the plurality of capacitors that in operation have different voltages. 
         [0018]    The switch elements and capacitors are configured to form multiple distinct charge transfer paths between the first terminal and the second terminal, and wherein at least some of the switch driving circuits that control the switch elements of one of the distinct charge transfer paths are powered from the capacitors of one or more other charge transfer paths. 
         [0019]    The switched capacitor power converter further comprises a phase generator comprising a second plurality of switch elements. The phase generator is configured to provide a time varying voltage level to one terminal of each of the plurality of the capacitors, and configured to generate a voltage level for at least one capacitor in one charge transfer path using a voltage from a capacitor in the other charge transfer path. 
         [0020]    Advantages of one or more aspects may include the following. 
         [0021]    Overall efficiency of the converter is increased by reducing the losses in generating the gate driving signals that repeatedly charge and discharge the gates of the transistors in the switched capacitor power converter. 
         [0022]    Low-voltage transistors can be used by limiting the gate-to-source voltages. 
         [0023]    Cascoded configurations can be efficiently driven with different transistors in a cascoded series being driven with different voltages. 
         [0024]    In the case of a converter that makes use of external (e.g., discrete) capacitors, using those same capacitors to power internal gate driver circuits avoids the need to provide additional intermediate power terminals to the device. 
         [0025]    An integrated circuit is typically limited by the number of pins it is allowed to have. Each pin consumes a certain amount of area on a silicon die and if the pin count is very large it is possible that the area consumed by the pins is larger than the area consumed by the active devices on the silicon die. Each capacitor will require at least one pin and in some cases require two pins. Using the voltages available on the capacitors used in the charge transfer path to power gate drivers is preferable to providing these voltages through additional pins on the device because the total pin count does not have to be increased. 
         [0026]    Other features and advantages of the invention are apparent from the following description, and from the claims. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0027]      FIG. 1  is a schematic of a single-phase step-up cascade multiplier; 
           [0028]      FIG. 2  is a schematic of a single-phase step-up cascade multiplier with cascoded switches; 
           [0029]      FIG. 3  is a schematic of a single-phase cascade multiplier with cascoded switches and corresponding gate drivers and pre-charging circuit; 
           [0030]      FIGS. 4-5  are annotated schematics of the circuit of  FIG. 3  in two phases of operation, respectively; 
           [0031]      FIG. 6  is a schematic of a tapered gate driver; 
           [0032]      FIG. 7  is a schematic of a cascoded gate driver; 
           [0033]      FIG. 8  is a schematic of a dual-phase cascade multiplier with cascoded switches and corresponding gate drivers; 
           [0034]      FIG. 9  is an annotated schematic of the circuit of  FIG. 8  in one of two phases of operation; 
           [0035]      FIG. 10  is a schematic of a dual-phase cascade multiplier and corresponding gate drivers; 
           [0036]      FIGS. 11-12  are schematics of two alternative phase generators for use with the circuit of  FIG. 10 ; and 
           [0037]      FIG. 13  is a schematic of a dual-phase series-parallel switched capacitor converter and corresponding gate drivers. 
       
    
    
     DESCRIPTION 
     1. Overview 
       [0038]    A number of approaches are described below for use in the context of active control of switched capacitor power converters. The approaches address one or more of the following goals: 
         [0039]    Increase in efficiency of the converter by reducing the charge deposited and discharged from the gates of control transistors 
         [0040]    Permitting use of low-voltage transistors for switching. 
         [0041]    Generally, an approach to achieving these goals is by efficiently limiting the gate-to-source voltages though the design and powering of circuits driving the switching transistors during operation. A number of specific approaches, some of which are described below, use control circuitry for switching transistors, which couple the capacitors in the charge transfer path, that are themselves powered by capacitors in the same path, and/or by capacitors in different parallel paths in the case of multi-phase converters. 
       2. Single-Phase Cascade Multiplier 
       [0042]    Referring to  FIG. 3 , a single-phase cascade multiplier circuit  30  makes use of transistors M 0 -M 5  coupling to first, second, and third pump capacitors C 1 -C 3  on the charge transfer path between a high-voltage terminal (i.e. VO) and a low-voltage terminal (i.e. VI). In the embodiment illustrated in  FIG. 3 , the pump capacitors C 1 -C 3  are coupled by cascoded transistor switches (e.g., M 1  and M 2  in series), but it should be understood that single transistors could also be used while still achieving at least some of the advantages of the configuration shown. 
         [0043]    Each transistor is driven by a corresponding gate driver circuit. As described in more detail below, at least some of the gate driving circuits are powered from the pump capacitors C 1 -C 3  in the charge transfer path between the high-voltage terminal and the low-voltage terminal. The voltage across each of the pump capacitors C 1 -C 3  is a fraction of the high voltage, thereby permitting efficient generation of gate driving signals that maintain desired limits on the gate-to-source voltages of the transistors. 
         [0044]    A driver set  32  provides the gate signals to activate or de-activate each transistor in the cascade multiplier circuit  30 . The driver set  32  includes four low-voltage gate driver circuits  34 , two high-voltage gate driver circuits  35 , and four voltage followers  36 A- 36 D. Each gate driver circuit receives a driver signal with a label either beginning with an “A” or a “B”. The driver signals A 0 , B 0 , B 1 , A 1 , A 2 , B 2  control transistors M 0 , M 1 , M 2 , M 3 , M 4 , M 5 , respectively. Furthermore, the voltage followers  36 A- 36 D receive corresponding bias voltages V 1 -V 4 , respectively. A control circuit (not shown in  FIG. 3 ) generates the driver signals A 0 -B 2  and the bias voltages V 1 -V 4 . 
         [0045]    The low-voltage gate driver circuits  34  are coupled to the transistors M 0 , M 2 , M 4 , M 5 , whereas, the high-voltage gate driver circuits  35  are coupled to the transistors M 1 , M 3 . The high-voltage gate driver circuits  35  support twice the supply voltage of the low-voltage gate driver circuits  34 . Each of the voltage followers  36 A- 36 D receive a voltage from one of the pump capacitors C 1 -C 3  and provides a constant voltage to their corresponding gate driver circuit (i.e.  34  or  35 ) that is equal to or lower in value. When the received voltage is equal to the provided voltage, the corresponding voltage follower (e.g.  36 A) behaves like a switch. To achieve this behavior, the bias voltages V 1 -V 3  are at least a threshold voltage above the corresponding source voltage while the bias voltage V 4  is at least a threshold voltage below the corresponding source voltage. Furthermore, the voltage followers  36 A- 36 D experience the same voltage stress as the transistors M 0 -M 5  in the cascade multiplier circuit  30 . 
         [0046]    Also illustrated in  FIG. 3  is an example of a pre-charge circuit  38  that is used to initialize the voltages on the pump capacitors C 1 -C 3  prior to clocked operation of the cascade multiplier circuit  30 . By pre-charging the pump capacitors C 1 -C 3 , the drain-to-source voltages across the transistors M 0 -M 5  within the cascade multiplier circuit  30  can be maintained within required limits during startup, and further, the pre-charged pump capacitors C 1 -C 3  can provide the needed power to the gate driving circuits immediately upon the start of clocked operation of the cascade multiplier circuit  30 . Upon clocked operation, the pre-charge circuit  38  can be disabled. 
         [0047]    To facilitate the use of low-voltage transistors throughout the whole power converter, the pre-charge circuit  38  uses a combination of low-voltage transistors and bias resistors. A resistor divider sets up the pre-charge voltage for each of the pump capacitors C 1 -C 3  during startup, wherein the source voltage of each transistor within the pre-charge circuit  38  is at least a threshold voltage below its corresponding gate voltage. As a result, none of the transistors within either the pre-charge circuit  38  or the cascade multiplier circuit  30  are exposed to voltage stresses that can damage the devices during startup or clocked operation. 
         [0048]    Operation of the cascade multiplier circuit  30  and the resulting voltage levels powering the gate driving circuits can be understood with reference to  FIGS. 4-5  that show the two states of operation. The cascade multiplier circuit  30  transfers energy from a source  16  to a load  18  by cycling between a first state and a second state at a specific frequency. All of the transistors coupled with the “A” signals are activated and de-activated at the same time; as is the case for all of the transistors coupled with the “B” signals. To ensure a clean transition between the first and second state, the “A” signals and “B” signals are non-overlapping. Furthermore, first and second phase voltages VP 1 , VP 2  are synchronized with the “A” signals and “B” signals. 
         [0049]    Assuming an input voltage VI of five volts, then the cascade multiplier circuit  30  produces an output voltage VO that is twenty volts. The maximum voltage across any transistor is five volts. Furthermore, the low-voltage gate driver circuits  34  support five volts while the high-voltage gate driver circuits  35  must support ten volts. 
         [0050]      FIG. 4  illustrates the first state, wherein the first phase voltage VP 1  is at five volts while the second phase voltage VP 2  is at zero volts. The gate driver circuits that receive a “B” signal activate their corresponding transistors and the gate driver circuits that receive an “A” signal de-activate their corresponding transistors. Consequently, a gate voltage of fifteen volts activates the transistors M 1 , M 2 , M 5  while gate voltages of five volts, ten volts, and fifteen volts de-activate the transistors M 0 , M 3 , M 4 , respectively. 
         [0051]    In contrast,  FIG. 5  illustrates the second state, wherein the first phase voltage VP 1  is at zero volts while the second phase voltage VP 2  is at five volts. The gate driver circuits that receive an “A” signal activate their corresponding transistors and the gate driver circuits that receive a “B” signal de-activate their corresponding transistors. Consequently, gate voltages of five volts, ten volts, and twenty volts de-activate the transistors M 1 , M 2 , M 5 , respectively; while gate voltages of ten volts, twenty volts, and twenty volts activate the transistors M 0 , M 3 , M 4 , respectively. 
         [0052]    Unfortunately, the voltage followers  36 A- 36 D associated with the transistors M 0 , M 1 , M 2 , M 5  consume power. Each voltage follower drops five volts across its drain and source terminals while sinking or source current for its corresponding gate driver. In the case of the transistors M 1 , M 2 , M 5 , this occurs during the first state while for transistor M 0  this occurs during the second state. 
         [0053]    In the cascade multiplier circuit  30 , charge transfers to the load  18  from the source  16  at a rate dictated by the load  18 . Because this is a single-phase design, there is only one charge transfer path that a unit of charge can follow. For example, at the start of a first clock cycle, the unit of charge leaves the source  16  and flows into the first pump capacitor C 1 . After a state transition, the unit of charge moves to the second pump capacitor C 2 . When a second clock cycle begins, the unit of charge then moves from the second pump capacitor C 2  to the third pump capacitor C 3  and after one more state transition, the unit of charge finally reaches the load  18 . It took two full clock cycles (i.e. four consecutive states) for the initial charge to reach the load  18  from the source  16 . 
         [0054]    In general, as the conversion gain of a cascade multiplier increases, the number of pump capacitors increases. Consequently, it takes a longer time for a unit of charge from the source  16  to reach the load  18  because the unit of charge needs to bounce between more pump capacitors. The number of clock cycles in the charge transfer path is M- 2 , where M is equal to the conversion gain. In this example, M is equal to four; therefore, the number of clock cycles is two. 
         [0055]      FIGS. 6-7  illustrate two alternative designs of the gate driving circuits. Both of which can be used for the high-voltage gate driver circuits  35  and the low-voltage gate driver circuits  34 . However, as will be made clear in the following description, the gate driver in  FIG. 6  is more suitable for the low-voltage gate driver  34  while the gate driver in  FIG. 7  is more suitable for the high-voltage gate driver  35 . 
         [0056]    As illustrated in  FIG. 6 , a tapered gate driver features an input terminal IN, an output terminal OUT, and supply terminals VDD, VSS. The input terminal IN couples with the output terminal OUT through first, second, third, and fourth inverters, in that order. The four inverters include high-side PMOS transistors MP 1 -MP 4  and low-side NMOS transistors MN 1 -MN 4 . Due to the difference in electron and hole mobilities, each of the PMOS transistors MP 1 -MP 4  is typically sized larger than their corresponding NMOS transistors MN 1 -MN 4 . 
         [0057]    Starting at the input terminal IN, each subsequent inverter is k times larger than the previous inverter. For example, if k is equal to five and the width of the first inverter is one micron, then the width of the second, third, and fourth inverters is five microns, twenty-five microns, and one hundred and twenty-five microns, respectively. By tapering the inverters, a small logic gate coupled to the input terminal IN is able to drive a large power transistor coupled to the output terminal OUT. 
         [0058]    The maximum supply voltage of the tapered gate driver is equal to or less than the breakdown voltage of the transistors. Therefore, the tapered gate driver is a good choice for the low-voltage gate driver circuits  34  in the cascade multiplier circuit  30 . Unfortunately, due to the higher voltage requirements of the high-voltage gate driver circuit  35  in  FIGS. 3-5 , the tapered gate driver circuit requires transistors with twice the breakdown voltage. 
         [0059]    An alternative method of increasing the supply voltage without the need of higher voltage transistors is to use a cascoded gate driver. As illustrated in  FIG. 7 , a cascoded gate driver includes an input terminal IN, an output terminal OUT, and supply terminals VDD, VSS. The cascoded gate driver features an output stage that includes first and second high-side transistors MP 5 , MP 6  and first and second low-side transistors MN 5 , MN 6 . The output stage requires additional support circuitry, such as a level shifter, two gate drivers, a delay block, and a voltage regulator, all of which can be designed using transistors with the same breakdown voltage as that of the transistors in the output stage. 
         [0060]    During normal operation of the cascoded gate driver, the high-side transistors MP 5 , MP 6  are activated when the low-side transistors MN 5 , MN 6  are de-activated and vice-versa. Therefore, the cascoded gate driver can support twice the supply voltage because the differential voltage across the supply terminals VDD, VSS is always supported by two de-activated transistors. In general, a larger number of transistors can be cascoded to increase the supply voltage further. For example, if the output stage included three high-side transistors and three low-side transistors then the maximum supply voltage would be tripled and so on. Unfortunately, as the number of cascoded transistors increases, so does the complexity of the support circuitry. 
       3. Dual-Phase Cascade Multiplier 
       [0061]    In general, a single-phase cascade multiplier can be converted into a multi-phase cascade multiplier featuring multiple charge transfer paths that are shifted in time. As illustrated in  FIG. 8 , a dual-phase cascade multiplier circuit  40  can be constructed by placing two copies, of the single-phase cascade multiplier circuit  30  in parallel. Each copy is referred to as a phase (not to be confused with state), therefore, the cascade multiplier circuit  30  features a first phase and a second phase. The first phase includes capacitors C 1 A-C 3 A, transistors M 0 A-M 5 A, and phase voltages VP 1 , VP 2  while the second phase includes capacitors C 1 B-C 3 B, transistors M 0 B-M 5 B, and phase voltages VP 3 , VP 4 . Each of the transistors M 0 A-M 5 B has a corresponding gate driver circuit  34  that receives a driver signal with a label either beginning with an “A” or a “B”. The first phase includes driver signals A 0   a -B 2   a  while the second phase includes driver signals A 0   b -B 2   b.    
         [0062]    The control signals of the first phase and the second phase are shifted by one-hundred and eighty degrees. This can be achieved by swapping the “A” and “B” signals in one of the two phases and then inverting the corresponding phase voltages. For example, in normal operation, the phase voltages VP 1 , VP 3  are high when the phase voltages VP 2 , VP 4  are low and vice versa. Furthermore, the voltage followers in the first phase receive bias voltages V 1   a -V 4   a  while the voltage followers in the second phase receive bias voltage V 1   b -V 4   b.  As in the previous single-phase example, a control circuit (not shown in  FIG. 8 ) can generate the drivers signals A 0   a -B 2   b  and the bias voltages V 1   a -V 4   b.    
         [0063]    Additionally, by having the source  16  and the load  18  trade places, a step-down power converter can be converted into a step-up converter and vice versa. Therefore, the cascade multiplier circuit  40  is step-down power converter instead of a step-up power converter as in  FIG. 3 . 
         [0064]    There are several benefits of a dual-phase construction over a single-phase construction. The most obvious benefit is that there is always a charge transfer path between the source  16  and the load  18  regardless of the state of operation (first or second). A less obvious benefit is that the one phase can derive energy from an alternate phase to power circuitry and vice versa. Furthermore, this technique allows the cascade multiplier circuit  40  to only use low-voltage gate driver circuits  34 . 
         [0065]    Since a dual-phase converter is essentially two single-phase converters operated in parallel, the cascade multiplier circuit  40  operates as described in connection with  FIGS. 3-5 . Assuming the input voltage VI is twenty volts, the resulting voltage levels powering the gate driving circuits can be understood with reference to  FIG. 9  that show one state of operation. The other state of operation is not shown because it is simply a mirror image of the state shown in  FIG. 9 . 
         [0066]    In the cascade multiplier circuit  40 , the transistors M 0 A-M 3 B derive power from opposing phases while the transistors M 4 A-M 5 B derive power from the input voltage VI. Powering the gate drivers from a parallel charge transfer path (i.e. opposing phase) results in one less voltage follower per phase and the voltage followers do not consume power. This is because the transistors M 0 A, M 2 A, M 5 A, M 0 B, M 2 B, M 5 B are de-activated while voltage is being dropped across their corresponding voltage followers. Because of the more efficient voltage followers and the lack of high-voltage gate driver circuits  35 , the energy required to drive the gates in a dual-phase design is less than a single-phase design. 
         [0067]    As in the single-phase construction of  FIG. 3 , it takes two full clock cycles for the initial charge into the cascade multiplier circuit  40  to reach the load  18 . However, in the dual-phase construction, there are two charge transfer paths between the source  16  and the load  18 , instead of one, as in the single-phase construction. Furthermore, the two distinct charge transfer paths are shifted in time with respect to each other. 
         [0068]    For example, a first unit of charge from the source  16  enters a first charge transfer path at the input of the cascade multiplier circuit  40 . During each state transition, the first unit of charge hops between the positive terminals of the capacitors C 3 B, C 2 B, C 1 B, in that order, thereby being delivered to the load  18  after four state transitions. Similarly, in a second charge transfer path, a second unit of charge leaves the source  16  and then precedes to hop between the positive terminals of the capacitors C 3 B, C 2 B, C 1 B each state transition. After the fourth state transition, the second unit of charge is delivered to the load  18 . By shifting the first and second charge transfer paths one hundred and eighty out of phase, a path for charge always exists between the source  16  and the load  18 . 
         [0069]    It should be appreciated that the above described dual-phase cascade multiplier circuit  40  is one of many different implementations.  FIG. 10  illustrates an alternative dual-phase cascade multiplier circuit  50 , formed by removing the cascode switches M 2 A, M 4 A, M 2 B, M 4 B in the cascade multiplier circuit  40 , thereby reducing control complexity and perhaps improving robustness. Unfortunately, without the cascode switches, all of the inner switches M 1 A, M 3 A, M 1 B, M 3 B need to support twice the output voltage VO as well as their corresponding gate drivers  35 . 
         [0070]    Additionally, the pump capacitors C 3 A, C 3 B in the cascade multiplier circuit  50  are pumped in series with their corresponding pump capacitors C 1 A, C 1 B, compared to being pumped in parallel as in the cascade multiplier circuit  40 . The series arrangement reduces the voltage across the pump capacitors C 3 A, C 3 B. For example, if the output voltage VO is five volts, then the voltage across the capacitors C 3 A, C 3 B is ten volts in  FIG. 10  compared to fifteen volts in  FIG. 8 . Due to the similarity between the cascade multiplier circuits  40 ,  50 , the cascade multiplier circuit  50  operates as described in connection with  FIG. 10   
       4. Phase Generation 
       [0071]    In addition to efficient generation of gate driving signals, the capacitor voltages can also be used to efficiently drive the phase signals that drive the capacitors. Two examples of the phase generator  110  are shown in  FIGS. 11-12 , suitable to use with the dual-phase cascade multiplier circuit  50  shown in  FIG. 10 . 
         [0072]      FIG. 11  illustrates a phase generator  110  that receives an output voltage VO and produces first, second, third, and fourth phase voltages VP 1 -VP 4 . The first and second phase voltages VP 1 , VP 2  correspond to the first phase of the cascade multiplier circuit  50  while the third and fourth phase voltages VP 3 , VP 4  correspond to the second phase of the cascade multiplier circuit  50 . 
         [0073]    The phase generator  110  features four transistor pairs, wherein each transistor pair generates one of the phase voltages VP 1 -VP 4 . A first pair of transistors MH 1 , ML 1  generates the first phase voltage VP 1 ; a second pair of transistors MH 2 , ML 2  generates the second phase voltage VP 2 ; a third pair of transistors MH 3 , ML 3  generates the third phase voltage VP 3 ; and a fourth pair of transistors MH 4 , ML 4  generates the fourth phase voltage VP 4 . In each transistor pair, the high-side transistor (e.g. MH 1 ) is a PMOS device while the low-side transistor (e.g. ML 1 ) is a NMOS device. 
         [0074]    Separate gate driver circuits control each transistor in the phase generator  110 , thereby allowing tri-state operation of each transistor pair. The output voltage VO powers each gate driver circuit. The gate driver circuits can be implemented using numerous circuit topologies, such as the tapered gate driver illustrated in  FIG. 6 . Each gate driver circuit receives a driver signal with a label beginning with either an “A” or a “B”. The driver signals AL 1 , BL 1 , AL 2 , BL 2  control low-side transistors ML 1 , ML 2 , ML 3 , ML 4 , respectively while the driver signals BH 1 , AH 1 , BH 2 , AH 2  control high-side transistors MH 1 , MH 2 , MH 3 , MH 4 , respectively. 
         [0075]    In normal operation, the phase generator  110  cycles between a first state and a second state at a specific frequency. During the first state, the gate driver circuits that receive a “B” signal activate their corresponding transistors and the gate driver circuits that receive an “A” signal de-activate their corresponding transistors. Consequently, the first and third phase voltages VP 1 , VP 3  are equal to the output voltage VO while the second and fourth phase voltages VP 2 , VP 4  are equal to zero volts. 
         [0076]    In contrast, during the second state, the gate driver circuits that receive a “B” signal de-activate their corresponding transistors and the gate driver circuits that receive an “A” signal activate their corresponding transistors. Consequently, the first and third phase voltages VP 1 , VP 3  are equal to zero volts while the second and fourth phase voltages VP 2 , VP 4  are equal to the output voltage VO. 
         [0077]      FIG. 12  illustrates an alternative phase generator  110  that receives an output voltage VO and produces first, second, third, and fourth phase voltages VP 1 -VP 4 . In a dual-phase design, the first and third phase voltages VP 1 , VP 3  are in phase; and the second and fourth phase voltages VP 2 , VP 2  are in phase. Consequently, as illustrated in  FIG. 12 , the first and third phase voltages VP 1 , VP 3  can be shorted together and the second and fourth phase voltages VP 2 , VP 4  can be shorted together. 
         [0078]    Additionally, high-side transistors MH 1 , MH 2  can utilize NMOS transistors instead of PMOS transistors as in  FIG. 11 . The higher mobility of electrons in NMOS transistors allows for the use of smaller high-side transistors MH 1 , MH 2 , thereby reducing the energy required to activate. Because NMOS transistors require a gate voltage higher than their source to activate, the high-side transistors MH 1 , MH 2  derive this boost voltage from the pump capacitors within the cascade multiplier that the phase generator  110  is driving. 
         [0079]    For example, if the phase generator  110  is coupled to the cascade multiplier circuit  50 , then the gate driver of the high-side transistor MH 1  is coupled to the positive terminal of the pump capacitor C 1 A from phase one. In contrast, the gate driver of the high-side transistor MH 2  is coupled to the positive terminal of the pump capacitor C 1 B from phase two. Therefore, each gate driver and its corresponding high-side transistor is powered by a pump capacitor from a distinct parallel charge transfer path. 
         [0080]    Because of the similarity of the phase generators  110  in  FIGS. 11-12 , the operation of the phase generator  110  in  FIG. 12  operates as described in connection with  FIG. 11 . The differences mainly being the shorted phase voltages and boosted high-side transistors MH 1 , MH 2 . 
       5. Alternatives 
       [0081]    A number of alternatives to the switched capacitor power converter designs discussed make use of the approaches embodied in those designs. For example, the converter illustrated in  FIG. 13  is a dual-phase series-parallel switched capacitor circuit  60  that includes some gate drivers that are powered by capacitors in either the same charge transfer path or a parallel charge transfer path. 
         [0082]    The switched capacitor circuit  60  includes a pair of phases. A first phase includes capacitors C 1 C-C 3 C, odd transistors M 1 C-M 7 C, and even transistors M 2 C-M 12 C. Similarly, a second phase includes capacitors CM-C 3 D, odd transistors M 1 D-M 7 D, and even transistors M 2 D-M 12 D. All of the transistors coupled with signals having an “A” prefix through corresponding gate drivers are activated and de-activated at the same time; as is the case for all of the transistors coupled with signals having a “B” prefix through corresponding gate drivers. 
         [0083]    The switched capacitor circuit  60  produces an output voltage VO that is four times lower than an input voltage VI by cycling between a first state and a second state at a specific frequency. During the first state, the first phase odd transistors M 1 C-M 7 C and the second phase even transistors M 2 D-M 12 D are activated while the first phase even transistors M 2 C-M 12 C and the second phase odd transistors M 1 D-M 7 D are de-activated. This switch activation pattern places the second phase capacitors C 1 D-C 3 D in parallel with the load  18  and places a series arrangement of the first phase capacitors C 1 C-C 3 C in between the source  16  and the load  18 . 
         [0084]    In contrast, during the second state, the first phase odd transistors M 1 C-M 7 C and the second phase even transistors M 2 D-M 12 D are de-activated while the first phase even transistors M 2 C-M 12 C and the second phase odd transistors M 1 D-M 7 D are activated. This switch activation pattern places the first phase capacitors C 1 C-C 3 C in parallel with the load  18  and places a series arrangement of the second phase capacitors C 1 D-C 3 D in between the source  16  and the load  18 . 
         [0085]    Unlike either of the dual-phase cascade multiplier circuits  40  or  50 , within a single phase of the switched capacitor circuit  60 , the gate drivers derive their power from capacitors in both phases. For example, the gate drivers for the corresponding transistors M 1 C, M 3 C, M 5 C are powered from the capacitors C 1 C, C 2 C, C 3 C, respectively while the gate drivers for the corresponding transistors M 4 C, M 8 C, M 12 C are powered from the capacitor C 1 D. 
         [0086]    Furthermore, the voltage stress across the transistors in a series-parallel switched capacitor power converter can be quite high in comparison to cascade multipliers. Assuming the input voltage VI is equal to twenty volts then the maximum voltage across the transistors M 12 C, M 12 D is fifteen volts. In this embodiment, the gate-to-source voltage is always five volts and the gate drivers for the top PMOS transistors require two series connected voltage followers that are biased using voltages V 1   c -V 2   d.    
         [0087]    Although described in the context of single-phase and dual-phase converters, it should be understood that other multi-phase converter configurations can be used. For example, a four-phase cascade multiplier can be constructed by placing two copies of the cascade multiplier circuit  40  in parallel and shifting their respective clocks by ninety degrees. Adding an even number of phases is straightforward because every subsequent pair of phases can be run in isolation. 
         [0088]    However, if the switched capacitor power converter includes an odd number of phases, it is a little more difficult to power gate drivers from capacitors in different parallel charge transfer paths. In this case, each gate driver draws power from capacitors in multiple parallel charge transfer paths, as compared to a single parallel charge transfer path in the even-numbered phase case. 
         [0089]    In general, switched capacitor converters feature a large number of switches and capacitors. By necessity, at least a few of the switches are floating, which means that neither switch terminal is attached to a constant electric potential. It should be appreciated that switched capacitor converters that have at least one floating switch can benefit by deriving power from the same charge transfer path or a parallel charge transfer path. Examples of such switched capacitor converters include the cascade multiplier, series-parallel, parallel-series, Fibonacci, and voltage doubler topologies. 
       6. Implementations 
       [0090]    The switched capacitor power converters and the associated gate drivers illustrated herein can all be integrated on one or multiple semiconductor substrates. If all of the transistors are integrated on a single substrate and any of the transistors are floating then the transistors must be isolated from the substrate. For example, in a CMOS process, NMOS transistors are typically formed in a p-type substrate. These devices can only float if the bulk of the NMOS transistors is isolated from the substrate. If this were not the case, then an alternative possibility would be to use multiple semiconductor substrates. 
         [0091]    The capacitors in a switched capacitor power converter can either be integrated, discrete, or a combination thereof. The discrete capacitors are typically multi-layer ceramic capacitors while the integrated capacitors are typically planar or trench capacitors. If the capacitors are integrated, then they can be integrated on the same wafer with their switches, or they can be integrated on a separate wafer, or a combination thereof. Furthermore, if the capacitors and switches are on different wafers then there are various attachment methods, some of which remove the pin count limitation of the overall converter. 
         [0092]    The ability to re-purpose the pump capacitors is of benefit when the switched capacitor power converter uses either integrated capacitors or discrete capacitors. If discrete capacitors are used, then each capacitor uses at least one pin. Adding extra pins for the gate driver circuitry is quite painful because pins on an integrated circuit are of limited supply for a given die area. On the other hand, integrated capacitors do not eat into your pin count, but they are quite expensive and have a low capacitance per area so it is valuable to limit their use. 
         [0093]    Typically, a controller produces control signals for activating and de-activating the switches within a switched capacitor power converter. For example, in most of the embodiments described above, a controller could have generated the driver signals that are labeled with an “A” or a “B” prefix. By controlling the on and off time of the individual switches, a controller can provide many functions. A few such functions include the ability to regulate the output voltage, the ability to shut off the power converter in the event of a fault condition, and the ability to change the gain of the switched capacitor network. 
         [0094]    Various features, aspects, and embodiments of switched capacitor power converters have been described herein. The features, aspects, and numerous embodiments described are susceptible to combination with one another as well as to variation and modification, as will be understood by those having ordinary skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. Additionally, the terms and expressions which have been employed herein are used as terms of description and not of limitation. There is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents. 
         [0095]    It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims.

Technology Category: 5