Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation-in-part of patent application Ser. No. 90/008,190 filed Aug. 25, 2006. 
     
    
     BACKGROUND OF INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to Wireless Baseband Processors (Baseband Decoder) and Forward Error-Correction (FEC) Codes for 3 rd  Generation (3G) Wireless Mobile Communications. More particularly, the invention relates to a very high speed Turbo Codes Decoder implementing diversity processing and pipelined Max Log-MAP decoders for 3G Code Division Multiple Access (CDMA2000) and 3G Wideband Code Division Multiple Access (WCDMA). 
         [0004]    2. Description of Prior Art 
         [0005]    Diversity processing computes signals from two or more separate antennas using so-called “multipath” signals that arrive at the terminal via different routes after being reflected from buildings, trees or hills. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to deliver data rates up to 2 Mbit/s. 
         [0006]    Turbo Codes decoding is based upon the classic forward error correction concepts that include the use of concatenated Decoders and Interleavers to reduce E b /N 0  for power-limited wireless applications such as digital 3G Wireless Mobile Communications. 
         [0007]    A Turbo Codes Decoder is an important part of baseband processor of the digital wireless communication Receiver, which was used to reconstruct the corrupted and noisy received data and to improve BER (10 −6 ) throughput.  FIG. 1  shows an example of a diversity processing 3G Receiver with a Turbo Codes Decoder  13  which decodes data RXDa and RXDb from Demodulators  11  and Soft Decoders  12 , and sends decoded data to the Media Access Control (MAC) layer  14 . The data from the two or more received data paths pass through two or more diversity antennas, two or more Demodulators  11 , and two or more Soft Decoders  12  to produce soft decoded data RXDa and RXDb for the Turbo Codes Decoder  13 . 
         [0008]    A widely used Forward Error Correction (FEC) scheme is the Viterbi Algorithm Decoder in both wired and wireless applications. A drawback of the Viterbi Algorithm Decoder is that it requires a long wait for decisions until the whole sequence has been received. A delay of six times the memory processing speed of the received data is required for decoding. One of the more effective FEC schemes, with higher complexity, uses a maximum a posteriori (MAP) algorithm to decode received messages. The MAP algorithm is computationally complex, requiring many multiplications and additions per bit to compute the posteriori probability. A major difficulty with the use of the MAP algorithm has been the implementation in semiconductor ASIC devices. The complexity of the multiplications and additions slow down the decoding process and reduce the throughput data rates. Furthermore, even under the best conditions, multiplication operations in the MAP algorithm require implementation using large circuits in the ASIC. The result is costly design and low performance in bit rates throughput. 
         [0009]    Recently, the 3 rd  Generation Partnership Project (3GPP) organization introduced a new class of error correction codes using parallel concatenated codes (PCCC) that include the use of the classic recursive systematic constituent (RSC) Encoders and Interleavers as shown in  FIG. 2 . An example of the 3GPP Turbo Codes PCCC with 8-states and rate 1/3 is shown in  FIG. 2 . Data enters the two systematic encoders  31  and  33  separated by an interleaver  32 . An output codeword consists of the source data bit followed by the output bits of the two encoders. 
         [0010]    Other prior work relating to error correction codes was performed by Berrou et al., describing parallel concatenated codes which are complex encoding structures that are not suitable for portable wireless device. Another patent U.S. Pat. No. 6,023,783 to Divsalar et al. describes an improved encoding method over Berrou et al., using mathematical concepts of parallel concatenated codes. However, patents by Berrou et al., Divsalar et al., and others only describe the concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects, but are not feasible, economical, and suitable for consumer portable wireless devices. In these prior systems, the encoding of data is simple and can be easily implemented with a few xor and flip-flop logic gates. But decoding the Turbo Codes is much more difficult to implement in ASIC or software. The prior art describes briefly the implementation of the Turbo Codes Decoder which are mostly for deep space communications and requires much more hardware, power consumption and costs. 
         [0011]    All the prior art Turbo Codes fail to provide simple and suitable methods and architectures for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices, including the features of high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environments. 
       SUMMARY OF INVENTION 
       [0012]    The present invention is directed to Baseband Processor using diversity processing to implement a more efficient, practical and suitable architecture and method to achieve the requirements for 3 G wireless systems, including the features of higher speed data throughput, lower power consumptions, lower costs, and suitable for implementation in ASIC or DSP codes. The present invention encompasses several improved and simplified Turbo Codes Decoder methods and devices to deliver higher speed and lower power consumption, especially for 3G applications. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to deliver data rates up to 2 Mbit/s. As shown in  FIG. 3 , an exemplary embodiment of the Turbo Codes Decoder utilizes two parallel Turbo Codes Decoders for diversity processing. Each Turbo Codes Decoder has serially concatenated Soft-input Soft-output logarithm maximum a posteriori (SISO Log-MAP) Decoders. The two decoders function in a pipelined scheme with delay latency N. While the first decoder is decoding data stored in the second-decoder-Memory, the second decoder performs decoding for data stored in the first-decoder-Memory, which produces a decoded output every clock cycle. As shown in  FIG. 5 , the Turbo Codes Decoder utilizes a Sliding Window of Block N on the input buffer memory to decode data per block N, which improves processing efficiency. Accordingly, several objects and advantages of the Turbo Codes Decoder are: 
         [0013]    To implement diversity processing to increase the signal to noise ratio (SNR). 
         [0014]    To deliver higher speed throughput and be suitable for implementation in application specific integrated circuit (ASIC) designs or digital signal processor (DSP) codes. 
         [0015]    To utilize SISO Log-MAP decoders for best result and faster decoding and simplified implementation in ASIC circuits and DSP codes with the use of binary adders for computation. 
         [0016]    To perform re-iterative decoding of data back-and-forth between the two Log-MAP decoders in a pipelined scheme until a decision is made. In such pipelined scheme, decoded output data is produced each clock cycle. 
         [0017]    To utilize a Sliding Window of Block N on the input buffer memory to decode data per block N for improved pipeline processing efficiency 
         [0018]    To provide higher performance in term of symbol error probability and low BER (10 −6 ) for 3G applications such as 3G WCDMA, and 3G CDMA2000 operating at very high bit-rate up to 100 Mbps, in a low power, noisy environment. 
         [0019]    To utilize a simplified and improved SISO Log-MAP decoder architecture, including a branch-metric (BM) calculations module, a recursive state-metric (SM) forward/backward calculations module, an Add-Compare-Select (ACS) circuit, a Log-MAP posteriori probability calculations module, and an output decision module. 
         [0020]    To reduce complexity of multiplier circuits in MAP algorithm by performing the entire MAP algorithm in Log Max approximation using binary adder circuits, which are more suitable for ASIC and DSP codes implementation, while still maintaining a high level of performance output. 
         [0021]    To design an improve Log-MAP Decoder using high level design language (HDL) such as Verilog, system-C and VHDL, which can be synthesized into custom ASIC and Field Programmable Gate Array (FPGA) devices. 
         [0022]    To implement an improve Log-MAP Decoder in DSP (digital signal processor) using optimized high level language C, C++, or assembly language. 
         [0023]    Still further objects and advantages will become apparent to one skill in the art from a consideration of the ensuing descriptions and accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0024]      FIG. 1  illustrates a conventional 3G Receiver Functional Block Diagram which uses Turbo Codes Decoder for error-correction. 
           [0025]      FIG. 2  illustrates a block diagram of a conventional 8-states 3GPP Parallel Concatenated Convolutional Codes. 
           [0026]      FIG. 3  illustrates the Turbo Codes Decoder System Block Diagram showing Log-MAP Decoders, Interleavers, Memory Buffers, and control logics, according to an embodiment of the invention. 
           [0027]      FIG. 4  illustrates a Turbo Codes Decoder State Diagram, according to an embodiment of the invention. 
           [0028]      FIG. 5  illustrates the Block N Sliding Window Diagram, according to an embodiment of the invention. 
           [0029]      FIG. 6  illustrates a block diagram of the SISO Log-MAP Decoder showing Branch Metric module, State Metric module, Log-MAP module, and State and Branch Memory modules, according to an embodiment of the invention. 
           [0030]      FIG. 7  illustrates the 8-States Trellis Diagram of a SISO Log-MAP Decoder using the 3GPP 8-state PCCC Turbo codes, according to an embodiment of the invention. 
           [0031]      FIG. 8  illustrates a block diagram of the BRANCH METRIC COMPUTING module, according to an embodiment of the invention. 
           [0032]      FIG. 9  illustrates a block diagram of the Log-MAP computing for u= 0 , according to an embodiment of the invention. 
           [0033]      FIG. 10  illustrates a block diagram of the Log-MAP computing for u= 1 , according to an embodiment of the invention. 
           [0034]      FIG. 11  illustrates a block diagram of the Log-MAP Compare &amp; Select 1 maximum logic for each state, according to an embodiment of the invention. 
           [0035]      FIG. 12  illustrates a block diagram of the Soft Decode module, according to an embodiment of the invention. 
           [0036]      FIG. 13  illustrates a block diagram of the Computation of Forward Recursion of State Metric module (FACS), according to an embodiment of the invention. 
           [0037]      FIG. 14  illustrates a block diagram of the Computation of Backward Recursion of State Metric module (BACS), according to an embodiment of the invention. 
           [0038]      FIG. 15  illustrates State Metric Forward computing of Trellis state transitions, according to an embodiment of the invention. 
           [0039]      FIG. 16  illustrates State Metric Backward computing of Trellis state transitions, according to an embodiment of the invention. 
           [0040]      FIG. 17  illustrates a block diagram of the State Machine operations of Log-MAP Decoder, according to an embodiment of the invention. 
           [0041]      FIG. 18  illustrates a block diagram of the BM dual-port Memory Module, according to an embodiment of the invention. 
           [0042]      FIG. 19  illustrates a block diagram of the SM dual-port Memory Module, according to an embodiment of the invention. 
           [0043]      FIG. 20  illustrates a block diagram of the De-Interleaver dual-port RAM Memory Memory Module, according to an embodiment of the invention. 
           [0044]      FIG. 21  illustrates a block diagram of the De-Interleaver dual RAM Memory Module, according to an embodiment of the invention. 
           [0045]      FIG. 22  illustrates a flow chart of an exemplary state machine operation, according to an embodiment of the invention. 
           [0046]      FIG. 23  illustrates a block diagram of the Iterative decoding feedback control, according to an embodiment of the invention. 
           [0047]      FIG. 24  illustrates a block diagram of the intrinsic feedback Adder of the Turbo Codes Decoder, according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION  
     Turbo Codes Decoder 
       [0048]    An illustration of a 3GPP 8-state Parallel Concatenated Convolutional Code (PCCC), with coding rate 1/3, constraint length K= 4  is illustrated in  FIG. 2 . An implementation using SISO Log-MAP Decoders is illustrated in  FIG. 3 . 
         [0049]    In accordance with an exemplary embodiment, a diversity processing Turbo Codes Decoder includes two parallel blocks  40   a ,  40   b  of Turbo Codes Decoders for each path of received data RXDa and RXDb. Each identical Turbo Codes Decoder block  40   a ,  40   b  has concatenated max Log-MAP SISO Decoders A  42  and B  44  connected in a feedback loop with Interleaver Memory  43  and Interleaver Memory  45 . The Soft output of Turbo Codes Decoder block  40   a  is fed into the input of the Diversified Logic block  48 . Conversely, the Soft output of Turbo Codes Decoder block  40   b  is fed-back into the input of the Diversified Logic block  48 . The sum of the two outputs Z 1 , Z 3  of the Turbo Codes Decoder block  40   a ,  40   b  is fed into the Hard-Decoder to generate output Y data. The Diversified Logic block  48  computes the intrinsic feedback values Z 5  for the input into the Turbo Codes Decoder blocks  40   a  and  40   b  through Adder  231 . 
         [0050]    Signals Ra 2 , Ra 1 , Ra 0  are received soft decision signals of data path A from the system receiver. Signals XO 1  and XO 2  are output soft decision signals of the Log-MAP Decoders A  42  and B  44 , respectively, which are stored in the Interleaver Memory  43  and Memory  45  module. Signals Z 2  and Z 1  are the output of the Interleaver Memory  43  and Interleaver Memory  45 . Z 2  is fed into Log-MAP decoder B  44  and Z 1  is looped back into Log-MAP decoder A  42  through Adder  231 . 
         [0051]    Signals Rb 2 , Rb 1 , Rb 0  are received soft decision signals of data path B from the system receiver. Signals XO 1  and XO 2  are output soft decision of the Log-MAP Decoders A  42  and B  44 , respectively, which are stored in the Interleaver Memory  43  and Memory  45  module. Signals Z 4  and Z 3  are the output of the Interleaver Memory  43  and Interleaver Memory  45 . Z 4  is fed into Log-MAP decoder B  44  and Z 3  is looped back into Log-MAP decoder A  42  through Adder  231 . 
         [0052]    In accordance with the invention, signal Z 5  is fed back into Log-MAP decoder A  42  of block  40   a  through Adder  231 , and Signal Z 5  is fed back into Log-MAP decoder A  42  of block  40   b  through Adder  231  for diversity processing. 
         [0053]    Each Interleaver Memory  43 ,  45 , shown in  FIG. 20 , includes one interleaver  201  and a dual-port RAM memory  202 . Input Memory blocks  41 ,  48 ,  49 , shown in  FIG. 21 , includes dual-port RAM memory  211 . Control logic module (CLSM)  47  consists of various state-machines, which control all the operations of the Turbo Codes Decoder. The hard-decoder module  46  outputs the final decoded data. 
         [0054]    More particularly, as illustrated in  FIG. 3 , Ra 0 , Rb 0  are data bits corresponding to the transmit data bit u, Ra 1 , Rb 1  are the first parity bits corresponding to the output bit of the first RSC encoder, and Ra 2 , Rb 2  are interleaved second parity bits corresponding to the output bit of the second RSC encoder. 
         [0055]    In accordance with the invention, corresponding ones of data bits Ra 0 , Rb 0  are added to the feedback signals Z 5 , Z 1  and Z 3 , then fed into the decoder A. Corresponding ones of data bits Ra 1 , Rb 1  are also fed into decoder A for decoding the first stage of decoding output X 01 . Z 2  and corresponding ones of Ra 2 , Rb 2  are fed into decoder B for decoding the second stage of decoding output X 02 . 
         [0056]    In accordance with the invention, as shown in  FIG. 5 , the Turbo Codes Decoder utilizes a Sliding Window of Block N  61  on the input buffers  62  to decode one block N data at a time, the next block N of data is decoded after the previous block N is done in a circular wrap-around scheme for pipeline operations. In another embodiment, the Sliding Window of Block N is used on the input buffer Memory so that each block N data is decoded at a time one block after another in a pipeline scheme. 
         [0057]    In accordance with the invention, the Turbo Codes Decoder decodes an 8-state Parallel Concatenated Convolutional Code (PCCC). The Turbo Codes Decoder also decodes a higher n-state Parallel Concatenated Convolutional Code (PCCC) 
         [0058]    As illustrated in  FIG. 3 , the Turbo Codes Decoder functions effectively as follows: 
         [0059]    Received soft decision data (RXDa[2:0]) is stored in three input buffers Memory blocks  48 ,  49 ,  41  to produce data bits Ra 0 , Ra 1 , and Ra 2  that correspond to data words. Each output data word Ra 0 , Ra 1 , Ra 2  contains a number of binary bits. 
         [0060]    Received soft decision data (RXDb[2:0]) is stored in three input buffers Memory blocks  48 ,  49 ,  41  to produce Rb 0 , Rb 1 , and Rb 2  that correspond to data words. Each output data word Rb 0 , Rb 1 , Rb 2  contains a number of binary bits. 
         [0061]    A Sliding Window of Block N is imposed onto each input memory to produce corresponding ones of Ra 0 , Rb 0 , Ra 1 , Rb 1 , Ra 2 , and Rb 2  output data words. 
         [0062]    In accordance with the method of the invention, when an input data block of size N is ready, the Turbo Decoder starts the Log-MAP Decoder A, in block  40   a , to decode the N input data based on the soft-values of Ra 0 , Z 1 , Z 5  and Ra 1 , then stores the outputs in the Interleaver Memory A. 
         [0063]    The Turbo Decoder also starts the Log-MAP Decoder B, in block  40   a , to decode the N input data based on the soft-values of Ra 2  and Z 2 , in pipelined mode with a delay latency of N, then stores the output in the Interleaver Memory. 
         [0064]    When an input data block of size N is ready, the Turbo Decoder starts the Log-MAP Decoder A, in block  40   b , to decode the N input data based on the soft-values of Rb 0 , Z 5 , Z 3  and Rb 1 , then stores the outputs in the Interleaver Memory A. 
         [0065]    The Turbo Decoder also starts the Log-MAP Decoder B, in block  40   b , to decode the N input data based on the soft-values of Rb 2  and Z 4 , in pipelined mode with a delay latency of N, then store the outputs in the Interleaver Memory. 
         [0066]    The Turbo Decoder performs iterative decoding for L number of times (L=1, 2, . . . , M). The Log-MAP Decoder A receives the sum of (Z 1  and Z 3  and corresponding ones of Ra 0 , Rb 0  as inputs. The Log-MAP Decoder A also receives corresponding ones of Ra 1 , Rb 1  as inputs. The Log-MAP Decoder B receives the data Z 2  and R 2  as inputs. 
         [0067]    When the iterative decoding sequence is complete, the Turbo Decoder starts the hard-decision operations to compute and produce soft-decision outputs. 
       SISO Log-MAP Decoder 
       [0068]    As shown in  FIG. 6 , SISO Log-MAP Decoders  42 ,  44  include a Branch Metric (BM) computation module  71 , a State Metric (SM) computation module  72 , a Log-MAP computation module  73 , a BM Memory module  74 , a SM Memory module  75 , and a Control Logic State Machine module  76 . Soft-value inputs enter the Branch Metric (BM) computation module  71 , where Euclidean distance is calculated for each branch, the output branch metrics are stored in the BM Memory module  74 . The State Metric (SM) computation module  72  reads branch metrics from the BM Memory  74  and computes the state metric for each state; the output state-metrics are stored in the SM Memory module  75 . The Log-MAP computation module  73  reads both branch-metrics and state-metrics from BM memory  74  and SM memory  75  modules to compute the Log Maximum a Posteriori probability and produce soft-decision output. The Control Logic State-machine module  76  provides the overall operations of the decoding process. 
         [0069]    As shown in  FIG. 6  which is one example of 3GPP Turbo Codes Decoder, the Log-MAP Decoder  42   44  functions effectively as follows: 
         [0070]    The Log-MAP Decoder  42 ,  44  reads each soft-values (SD) data pair input, then computes branch-metric (BM) values for all paths in the Turbo Codes Trellis  80  as shown in  FIG. 7 . The computed BM data is stored into BM Memory  74 . The process of computing BM values is repeated for each input data until all N samples are calculated and stored in BM Memory  74 . 
         [0071]    The Log-MAP Decoder  42   44  reads BM values from BM Memory  74  and SM values from SM Memory  75 , and computes the forward state-metric (SM) for all states in the Trellis  80  as shown in  FIG. 7 . The computed forward SM data is stored into SM Memory  75 . The process of computing forward SM values is repeated for each input data until all N samples are calculated and stored in SM Memory  75 . 
         [0072]    The Log-MAP Decoder  42   44  reads BM values from BM Memory  74  and SM values from SM Memory  75 , and computes the backward state-metric (SM) for all states in the Trellis  80  as shown in  FIG. 7 . The computed backward SM data is stored into the SM Memory  75 . The process of computing backward SM values is repeated for each input data until all N samples are calculated and stored in SM Memory  75 . 
         [0073]    The Log-MAP Decoder  42   44  then computes Log-MAP posteriori probability for u= 0  and u= 1  using the BM values and SM values from BM Memory  74  and SM Memory  75 . The process of computing Log-MAP posteriori probability is repeated for each input data until all N samples are calculated. The Log-MAP Decoder then decodes data by making soft decision based on the posteriori probability for each stage and produces soft-decision output, until all N inputs are decoded. 
       Branch Metric Computation Module 
       [0074]    The Branch Metric (BM) computation module  71  computes the Euclidean distance for each branch in the 8-states Trellis  80  as shown in the  FIG. 7  based on the following equations: 
         [0000]      Local Euclidean distances values= SD 0* G 0+ SD 1* G 1 
         [0075]    where SD 0  and SD 1  are soft-value input data and G 0  and G 1  are the expected input for each path in the Trellis  80 . G 0  and G 1  are coded assigned antipodal values, meaning that 0 corresponds to +1 and 1 corresponds to −1. Therefore, the local Euclidean distances for each path in the Trellis  80  are computed by the following equations: 
         [0000]        M 1= SD 0+ SD 1 
         [0000]        M 2=− M 1 
         [0000]      M3=M2 
         [0000]      M4=M1 
         [0000]        M 5=− SD 0+ SD 1 
         [0000]        M 6=− M 5 
         [0000]      M7=M6 
         [0000]      M8=M5 
         [0000]      M9=M6 
         [0000]      M10=M5 
         [0000]      M11=M5 
         [0000]      M12=M6 
         [0000]      M13=M2 
         [0000]      M14=M1 
         [0000]      M15=M1 
         [0000]      M16=M2 
         [0076]    As shown in the exemplary embodiment of  FIG. 8 , the Branch Metric Computing module includes one L-bit Adder  91 , one L-bit Subtracter  92 , and a 2′complementer  93 . The Euclidean distances are computed for path M1 and M5. Path M2 is 2′complement of path M1. Path M6 is 2′complement of M5. Path M3 is the same path M2, path M4 is the same as path M1, path M7 is the same as path M6, path M8 is the same as path M5, path M9 is the same as path M6, path M10 is the same as path M5, path M11 is the same as path M5, path M12 is the same as path M6, path M13 is the same as path M2, path M14 is the same as path M1, path M15 is the same as path M1, and path M16 is the same as path M2. 
       State Metric Computing Module 
       [0077]    The State Metric Computing module  72  calculates the probability A(k) of each state transition in forward recursion and the probability B(k) in backward recursion.  FIG. 13  shows the implementation of state-metric in forward recursion with Add-Compare-Select (ACS) logic.  FIG. 14  shows the implementation of state-metric in backward recursion with Add-Compare-Select (ACS) logic. The calculations are performed at each node in the Turbo Codes Trellis  80  ( FIG. 7 ) in both forward and backward recursion.  FIG. 15  shows the forward state transitions in the Turbo Codes Trellis  80  ( FIG. 7 ).  FIG. 16  shows the backward state transitions in the Turbo Codes Trellis  80  ( FIG. 7 ). Each node in the Trellis  80  as shown in  FIG. 7  has two entering paths: one-path  84  and zero-path  83 , from the two nodes in the previous stage. 
         [0078]    In an exemplary embodiment, the ACS logic includes an Adder  132 , an Adder  134 , a Comparator  131 , and a Multiplexer  133 . In the forward recursion, the Adder  132  computes the sum of the branch metric and state metric in the one-path  84  from the state s(k−1) of previous stage (k−1). The Adder  134  computes the sum of the branch metric and state metric in the zero-path  83  from the state (k−1) of previous stage (k−1). The Comparator  131  compares the two sums and the Multiplexer  133  selects the larger sum for the state s(k) of current stage (k). In the backward recursion, the Adder  142  computes the sum of the branch metric and state metric in the one-path  84  from the state s(j+1) of previous stage (J+1). The Adder  144  computes the sum of the branch metric and state metric in the zero-path  83  from the state s(j+1) of previous stage (J+1). The Comparator  141  compares the two sums and the Multiplexer  143  selects the larger sum for the state s(j) of current stage (j). 
         [0079]    The Equations for the ACS are shown below: 
         [0000]        A ( k )=MAX [( bm 0+ sm 0( k− 1)), ( bm 1+ sm 1( k− 1)] 
         [0000]        B ( j )=MAX [( bm 0+ sm 0( j+ 1)), ( bm 1+ sm 1( j+ 1)] 
         [0080]    Time (k−1) is the previous stage of (k) in forward recursion as shown in  FIG. 15 , and time (j+1) is the previous stage of (j) in backward recursion as shown in  FIG. 16 . 
       Log-MAP Computing Module 
       [0081]    The Log-MAP computing module calculates the posteriori probability for u= 0  and u= 1 , for each path entering each state in the Turbo Codes Trellis  80  corresponding to u= 0  and u= 1  or referred as zero-path  83  and one-path  84 . The accumulated probabilities are compared and the u with larger probability is selected. The soft-decisions are made based on the final probability selected for each bit.  FIG. 9  shows the implementation for calculating the posteriori probability for u= 0 .  FIG. 10  shows the implementation for calculating the posteriori probability for u= 1 .  FIG. 11  shows the implementation of compare-and-select for the u with larger probability.  FIG. 12  shows the implementation of the soft-decode compare logic to produce output bits based on the posteriori probability of u= 0  and u= 1 . The equations for calculating the accumulated probabilities for each state and compare-and-select are shown below: 
         [0000]      sum —   s 00= sm 0 i+bm 1+ sm 0 j    
         [0000]      sum —   s 01= sm 3 i+bm 7+ sm 1 j    
         [0000]      sum —   s 02= sm 4 i+bm 9+ sm 2 j    
         [0000]      sum —   s 03= sm 7 i+bm 15+ sm 3 j    
         [0000]      sum —   s 04= sm 1 i+bm 4+ sm 4 j    
         [0000]      sum —   s 05= sm 2 i+bm 6+ sm 5 j    
         [0000]      sum —   s 06= sm 5 i+bm 12+ sm 6 j    
         [0000]      sum —   s 07= sm 6 i+bm 14+ sm 7 j    
         [0000]      sum —   s 10= sm 1 i+bm 3+ sm 0 j    
         [0000]      sum —   s 11= sm 2 i+bm 5+ sm 1 j    
         [0000]      sum —   s 12= sm 5 i+bm 11+ sm 2 j    
         [0000]      sum —   s 13= sm 6 i+bm 13+ sm 3 j    
         [0000]      sum —   s 14= sm 0 i+bm 2+ sm 4 j    
         [0000]      sum —   s 15= sm 3 i+bm 8+ sm 5 j    
         [0000]      sum —   s 16= sm 4 i+bm 10+ sm 6 j    
         [0000]      sum —   s 17= sm 7 i+bm 16+ sm 7 j    
         [0000]        s 00sum=MAX[sum —   s 00, 0] 
         [0000]        s 01sum=MAX[sum —   s 01,  s 00sum] 
         [0000]        s 02sum=MAX[sum —   s 02,  s 01sum] 
         [0000]        s 03sum=MAX[sum —   s 03,  s 02sum] 
         [0000]        s 04sum=MAX[sum —   s 04,  s 03sum] 
         [0000]        s 05sum=MAX[sum —   s 05,  s 04sum] 
         [0000]        s 06sum=MAX[sum —   s 06,  s 05sum] 
         [0000]        s 07sum=MAX[sum —   s 07,  s 06sum] 
         [0000]        s 10sum=MAX[sum —   s 10, 0] 
         [0000]        s 11sum=MAX[sum —   s 11,  s 10sum] 
         [0000]        s 12sum=MAX[sum —   s 12,  s 11sum] 
         [0000]        s 13sum=MAX[sum —   s 13,  s 12sum] 
         [0000]        s 14sum=MAX[sum —   s 14,  s 13sum] 
         [0000]        s 15sum=MAX[sum —   s 15,  s 14sum] 
         [0000]        s 16sum=MAX[sum —   s 16,  s 15sum] 
         [0000]        s 17sum=MAX[sum —   s 17,  s 16sum] 
       Control Logics-State Machine (CLSM) Module 
       [0082]    As shown in  FIG. 6 , the Control Logic module controls the overall operations of the Log-MAP Decoder. The control logic state machine  171 , referred as CLSM, is shown in  FIG. 17 . The CLSM module  171  ( FIG. 17 ) operates effectively as follows. Initially, the CLSM module  171  operates in IDLE state  172 . When the decoder is enabled, the CLSM module  171  transitions to CALC-BM state  173 , where the Branch Metric (BM) module starts operations and monitors for completion. When Branch Metric calculations are completed, referred to as bm-done, the CLSM transitions to CALC-FWD-SM state  174 , where the State Metric module (SM) begins forward recursion operations. When the forward SM state metric calculations are completed, referred to as fwd-sm-done, the CLSM transitions to CALC-BWD-SM state  175 , where the State Metric module (SM) begins backward recursion operations. When backward SM state metric calculations are completed, referred to as bwd-sm-done, the CLSM transitions to CALC-Log-MAP state  176 , where the Log-MAP computation module begins calculating the maximum a posteriori (MAP) probability to produce soft decode output. When Log-MAP calculations are completed, referred to as log-map-done, the CLSM module  171  transitions back to IDLE state  172 . 
       BM Memory and SM Memory 
       [0083]    The Branch-Metric Memory  74  and the State-Metric Memory  75  are shown in  FIG. 6  as the data storage components for BM module  71  and SM module  72 . The Branch Metric Memory module is a dual-port RAM that contains M-bits of N memory locations as shown in  FIG. 18 . The State Metric Memory module is a dual-port RAM that contains K-bits of N memory locations as shown in  FIG. 19 . Data can be written into one port while reading at the other port. 
       Interleaver Memory 
       [0084]    As shown in  FIG. 3 , the Interleaver Memory A  43  stores data for the first decoder A  42  and Interleaver Memory B  45  stores data for the second decoder B  44 . In iterative pipelined decoding, the decoder A  42  reads data from Interleaver Memory B  45  and writes results data into Interleaver Memory B  43 , the decoder B  44  reads data from Interleaver Memory A  43  and write results into Interleaver Memory B  45 . 
         [0085]    As shown in  FIG. 20 , the De-Interleaver memory  41  includes a De-Interleaver module  201  and a dual-port RAM  202 , which contains M-bits of N memory locations. The Interleaver is a Turbo code internal interleaver as defined by 3GPP standard ETSI TS 125 222 V3.2.1 (2000-05), or other source. The Interleaver permutes the address input port A for all write operations into dual-port RAM module. Reading data from output port B are done with normal address input. 
         [0086]    The Interleaver Memory module uses an interleaver to generate the write-address sequences of the Memory core in write-mode. In read-mode, the memory core read-address is normal sequences. 
         [0087]    As shown in  FIG. 21 , the Input Buffer Memory  43   45  comprises of a dual-port RAM  211 , which contains M-bits of N memory locations. 
       Turbo Codes Decoder Control Logics-State Machine (TDCLSM 
       [0088]    As shown in  FIG. 3 , the Turbo Decoder Control Logics module  47 , referred to as TDCLSM, controls the overall operations of the Turbo Codes Decoder. Log-MAP A  42  starts the operations of data in Memory B  45 . At the same time, Log-MAP B starts the operations in Memory A  43 . When Log-MAP A  42  and Log-MAP B  44  finish with block N of data, the TDCLSM  47  starts the iterative decoding for L number of times. When the iterative decoding sequences are completed, the TDCLSM  47  transitions to HARD-DEC to generate the hard-decode outputs. Then the TDCLSM  47  transitions to start decoding another block of data. 
       Iterative Decoding and Diversity Processing 
       [0089]    Turbo Codes decoder performs iterative decoding and diversity processing by feeding back the output Z 1 , Z 3  of the second Log-MAP decoder B into the corresponding first Log-MAP decoder A before making decision for hard-decoding output. As shown in  FIG. 23 , the Counter  233  counts the preset number L times. 
       Diversity Logic 
       [0090]    As shown in FIG. [[ 4 ]] 3 , the Diversified Logic module  48  computes the feedback intrinsic values Z 5  into the decoders  40   a  and  40   b  inputs through Adder  231 . In accordance with the method of the invention, the Diversified Logics module  48  performs the following calculations to produce the intrinsic value Z 5 . 
         [0091]    Computes the soft-decision error value: 
         [0000]        x=Z 1− Z 3 
         [0092]    Computes the “Running-Average Filter” over windows N of all error values to produce current average error value y(i) as shown in equation below: 
         [0000]    
       
         
           
             
               y 
                
               
                 ( 
                 i 
                 ) 
               
             
             = 
             
               
                 1 
                 N 
               
                
               
                 
                   ∑ 
                   
                     j 
                     = 
                     0 
                   
                   
                     N 
                     - 
                     1 
                   
                 
                  
                 
                   x 
                    
                   
                     ( 
                     
                       i 
                       - 
                       j 
                     
                     ) 
                   
                 
               
             
           
         
       
     
         [0093]    Finally, produces the intrinsic feedback value: 
         [0000]        Z 5= y ( i ) 
         [0094]    As shown in FIG. [[ 4 ]] 3 , the Diversified Logic module  48  also computes the sum Z 1 +Z 3  for output to the Hard-Decoder block.

Technology Category: 5