Patent Document

BACKGROUND 
   The present invention relates to an electronic device, and more particularly, to a signal amplifying apparatus. 
   Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional operating amplifier  10 . The prior art operating amplifier  10  comprises an input differential stage  11  and an output stage  12 . In brief, transistors M a -M e  form the input differential stage  11 , and transistors M f -M g  form the output stage  12 . According to the related art, the operating amplifier  10  has a dominant pole, two complex high frequency poles, and a zero. Due to the feed-forward path, which is formed by compensation resistor R z  and compensation capacitor C c , with no inversion from the input differential stage  11  to the output stage  12  at high frequency, the performance of the operating amplifier displays two degradations. The first is severe degradation of the operating amplifier  10  for capacitive loads C L  of the same order as compensation capacitor C c . The second is the negative power supply V BB  displaying a zero at the dominant pole frequency of the operating amplifier  10  in unity gain configuration due to the PMOS transistors in the input differential stage  11 . This results in serious performance degradation for sampled data systems that use high-frequency switching regulators to generate their power supplies. 
   Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating another conventional operating amplifier  20 . The operating amplifier  20  comprises an input differential stage  21 , a current transformer  22 , and an output stage  23 . The input differential stage  21  formed by transistors M a ′-M e ′ uses cascade devices M c1 -M c2  to reduce supply capacitance from the negative power supply V BB  for switched-capacitor applications. The current transformer  22  is formed by M h ′-M j ′, in which the technique has been referred to as the “grounded gate cascade compensation”. The output stage  23  is formed by M f ′-M g ′. Compared with the operating amplifier  10  shown in  FIG. 1 , the operating amplifier  20  provides a virtual ground at node N 1  to eliminate the feed-forward path but still produces a dominant pole due to the Miller effect. Therefore, the compensation capacitor C c ′ is connected between the output node N 2  and a virtual ground at N 1 . When designing a high-bandwidth operating amplifier, however, the operating amplifier  20  usually suffers from pole-zero doublet near unity-gain frequency. This is because the pole-zero doublet in the amplifier&#39;s unity-gain bandwidth elongates the amplifier&#39;s settling time, and consequently limits the amplifier&#39;s high-speed performance. 
   SUMMARY 
   Therefore, the present invention discloses a signal amplifying apparatus having higher settling time by using I/O devices in conjunction with core devices. 
   According to an embodiment of the present invention, a signal amplifying apparatus is disclosed for converting a first input signal into a first output signal. The signal amplifying apparatus includes an input stage circuit, a cascoded circuit, an output stage circuit, and a first capacitor. The input stage circuit is utilized for receiving the first input signal; the cascoded circuit, coupled to the input stage circuit, comprises a plurality of first cascoded transistors, wherein equivalent oxide thicknesses of the first cascoded transistors are not the same; the output stage circuit has a first input port coupled to the cascoded circuit, and a first output port for outputting the first output signal; and the first capacitor has a first terminal connected to the first output port of the output stage circuit and a second terminal coupled to the cascaded circuit, wherein the second terminal is not connected to the first input port of the output stage circuit. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram illustrating a conventional operating amplifier. 
       FIG. 2  is a diagram illustrating another conventional operating amplifier. 
       FIG. 3  is a diagram illustrating a signal amplifying apparatus according to a first embodiment of the present invention. 
       FIG. 4  is a Bode plot diagram illustrating the frequency response of the transfer function between the first input signal and the first output signal. 
       FIG. 5  is a diagram illustrating a signal amplifying apparatus according to a second embodiment of the present invention. 
       FIG. 6  is a diagram illustrating a signal amplifying apparatus according to a third embodiment of the present invention. 
       FIG. 7  is a diagram illustrating a signal amplifying apparatus according to a fourth embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating a signal amplifying apparatus  100  according to a first embodiment of the present invention. The signal amplifying apparatus  100  is utilized for converting a first input signal V in  into a first output signal V out , and comprises an input stage circuit  101 , a cascoded circuit  102 , an output stage circuit  103  and a first capacitor C a . The input stage circuit  101  comprises a P-type transistor M 1  having a gate terminal (node N 1 ) for receiving the first input signal V in ; the cascoded circuit  102  comprises a P-type transistor M 2  and an N-type transistor M 3 , in which a source terminal of the P-type transistor M 2  is coupled to a drain terminal of the P-type transistor M 1 ; and the N-type transistor M 3  has a drain terminal N 2  coupled to a drain terminal of the P-type transistor M 2 . The output stage circuit  103  comprises an N-type transistor M 4  having a gate terminal coupled to the drain terminal (node N 2 ) of the N-type transistor M 3 , and the first output signal V out  is outputted at a drain terminal (node N 3 ) of the N-type transistor M 4 . As shown in  FIG. 3 , the capacitor C a  has a first terminal connected to the drain terminal (node N 3 ) of the N-type transistor M 4  and a second terminal coupled to a source terminal (node N 4 ) of the N-type transistor M 3 . An equivalent oxide thickness of the N-type transistor M 3  is smaller than an equivalent oxide thickness of the P-type transistor M 1 , the P-type transistor M 2 , and the N-type transistor M 4 . Please note that, in the embodiment, transistors having different equivalent oxide thicknesses correspond to different transistor types in a semiconductor process; for example, an I/O device in the semiconductor process has an equivalent oxide thickness that is thicker than an equivalent oxide thickness of a core device. Furthermore, the source terminal of the P-type transistor M 1  is connected to a supply source V dd ; a current source I 1  is coupled between the node N 4  and ground V gnd ; a current source I 2  is coupled between the node N 3  and the supply source V dd ; a capacitor C P  is coupled to node N 2 ; and a loading capacitor C L1  exists at node N 3  as shown in  FIG. 3 . 
   Please refer to  FIG. 4 .  FIG. 4  is a Bode plot diagram illustrating the frequency response of the transfer function between the first input signal V in  and the first output signal V out . In  FIG. 4 , the x-axis represents frequency positions of poles and a zero of the signal amplifying apparatus  100 ; and the y-axis represents open loop gain between node N 3  and node N 1  of the signal amplifying apparatus  100 . Accordingly, there are three main poles and one main zero existing in the signal amplifying apparatus  100 . The first pole P 1  therein exists at frequency f 1 , the second pole P 2  exists at frequency f 2 , the third pole P 3  exists at frequency f 3 , and the main zero Z 1  exists at frequency f 4  as shown in  FIG. 4 . Accordingly, at frequency f 1 , a −20 dB/decade slope (line  201 ) will appear, and line  201  will then pass through the unity-gain frequency. Then, as the frequency f 3  of the third pole P 3  is close to the frequency f 4  of the main zero Z 1 , which is a pole-zero doublet frequency, the −20 dB/decade slope (line  202 ) will continue until it reaches the frequency f 2 . Then, a −40 dB/decade slope (line  203 ) will continue to the higher frequency. Please note that the detailed calculation of the frequencies f 1 , f 2 , f 3 , and f 4  can be easily performed by one skilled in this art, and so further description is omitted here. Furthermore, because the pole-zero doublet frequency will dictate the operating speed of the signal amplifying apparatus  100 , the higher the frequency f 3  of the third pole P 3  and the frequency f 4  of the main zero Z 1 , the lower the settling time of the signal amplifying apparatus  100  that will be obtained. According to the present invention, the frequency f 3  of the third pole P 3  and the frequency f 4  of the main zero Z 1  are mainly decided by the transconductance of the N-type transistor M 3 , therefore if the transconductance of the N-type transistor M 3  is increased, the pole-zero doublet frequency of the signal amplifying apparatus  100  also increases. In other words, the settling time of the N-type transistor M 4  gets smaller. Therefore, in this embodiment, the N-type transistor M 3  is implemented using a core device, in which the core device has a higher transconductance than the I/O device. Furthermore, because the core device can bear a lower cross voltage than the I/O device, the N-type transistor M 3  should be carefully designed. Accordingly, the newly pole-zero doublet frequency is moved right while the original bode plot of the signal amplifying apparatus  100 , as shown in of  FIG. 4 , is unchanged. 
   Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating a signal amplifying apparatus  300  according to a second embodiment of the present invention. The signal amplifying apparatus  300  is a differential input single output amplifier for converting a differential input signal V in1  and V in2  into an output signal V out1 . The signal amplifying apparatus  300  comprises a differential input stage circuit  301 , a differential cascoded circuit  302 , an output stage circuit  303  and a capacitor C b . The differential input stage circuit  301  comprises an N-type transistor M 1  having a gate terminal (node N 1 ) to receive the first input signal V in1  and an N-type transistor M 2  having a gate terminal (node N 2 ) to receive the second input signal V in2 . The differential cascoded circuit  302  comprises a P-type transistor M 3 , an N-type transistor M 4 , a P-type transistor M 5 , and an N-type transistor M 6 , in which a source terminal of the P-type transistor M 3  is coupled to a drain terminal of the N-type transistor M 1 , the N-type transistor M 4  has a drain terminal N 3  coupled to a drain terminal of the P-type transistor M 3 , a source terminal of the P-type transistor M 5  is coupled to a drain terminal of the N-type transistor M 2 , and the N-type transistor M 6  has a drain terminal N 4  coupled to a drain terminal of the P-type transistor M 5 . The output stage circuit  303  comprises an N-type transistor M 7  having a gate terminal coupled to the drain terminal (node N 3 ) of the N-type transistor M 4 , and the output signal V out1  is outputted at a drain terminal (node N 5 ) of the N-type transistor M 7 . As shown in  FIG. 5 , the capacitor C b  has a first terminal connected to the drain terminal (node N 5 ) of the N-type transistor M 7  and the second terminal of the capacitor C b  is coupled to a source terminal (node N 6 ) of the N-type transistor M 4 . 
   Furthermore, an N-type transistor M 8  and an N-type transistor M 9  are connected as a current mirror configuration coupled to the N-type transistors M 4  and M 6  as shown in  FIG. 5 . The equivalent oxide thicknesses of each of the N-type transistors M 4  and M 6  is smaller than an equivalent oxide thickness of each of the N-type transistors M 1  and M 2 , the P-type transistors M 3  and M 5 , and the N-type transistor M 7 . Please note that, as in the above first embodiment, the transistors having different equivalent oxide thicknesses correspond to different transistor types in a semiconductor process. In this embodiment, the N-type transistor M 4  and M 6  are core devices, and the others are I/O devices. Furthermore, a current source I 1  is coupled between the source terminal of the N-type transistor M 1  and M 2  and a ground V ss ; a current source I 2  is coupled between the differential cascoded circuit  302  and a supply source V dd ; a P-type transistor M 10  is coupled between the output stage circuit  303  and the supply source V dd , in which the P-type transistor M 10  is controlled by a control voltage V p1 , and a loading capacitor C L2  exists at node N 5  as shown in  FIG. 5 . Please note that the operation of increasing the operating speed of the signal amplifying apparatus  300  is mostly the same as the signal amplifying apparatus  100  and can be readily understood by a person skilled in this art after reading the above disclosure, thus the detailed description is omitted here for brevity. 
   Please refer to  FIG. 6 .  FIG. 6  is a diagram illustrating a signal amplifying apparatus  400  according to a third embodiment of the present invention. The signal amplifying apparatus  400  is a differential input differential output amplifier for converting a differential input signal V in1  and V in2  into a differential output signal V out1  and V out2 . The signal amplifying apparatus  400  comprises a differential input stage circuit  401 , a differential cascoded circuit  402 , a differential output stage circuit  403  and capacitors C c1  and C c2 . The differential input stage circuit  401  comprises an N-type transistor M 1 ″ having a gate terminal (node N 1 ) to receive the first input signal V in1  and an N-type transistor M 2  having a gate terminal (node N 2 ) to receive the second input signal V in2 . The differential cascoded circuit  402  comprises a P-type transistor M 3 ′, an N-type transistor M 4 ′, a P-type transistor M 5 ′, and an N-type transistor M 6 ′, in which a source terminal of the P-type transistor M 3 ′ is coupled to a drain terminal of the N-type transistor M 1 ″, the N-type transistor M 4 ′ has a drain terminal N 3  coupled to a drain terminal of the P-type transistor M 3 , a source terminal of the P-type transistor M 5 ′ is coupled to a drain terminal of the N-type transistor M 2 ′, and the N-type transistor M 6 ′ has a drain terminal N 4  coupled to a drain terminal of the P-type transistor M 5 ′. The differential output stage circuit  403  comprises an N-type transistor M 7 ′ having a gate terminal coupled to the drain terminal (node N 3 ) of the N-type transistor M 4 ′, an N-type transistor M 8 ′ having a gate terminal coupled to the drain terminal (node N 4 ) of the N-type transistor M 6 ′, where the first output signal V out1  is outputted at a drain terminal (node N 5 ) of the N-type transistor M 7 ′, the second output signal V out2  is outputted at a drain terminal (node N 6 ) of the N-type transistor M 8 ′. As shown in  FIG. 6 , the capacitor C c1  has a first terminal connected to the drain terminal (node N 5 ) of the N-type transistor M 7  and a second terminal coupled to a source terminal (node N 7 ) of the N-type transistor M 4 ′. The capacitor C c2  has a first terminal connected to the drain terminal (node N 6 ) of the N-type transistor M 8 ′ and a second terminal coupled to a source terminal (node N 8 ) of the N-type transistor M 8 ′. 
   Furthermore, a current source I 1  is coupled between the source terminal of the N-type transistor M 1 ″ and M 2 ′ and a ground V ss ; a current source I 2  is coupled between the differential cascoded circuit  402  and a supply source V dd ; a current source I 3  is coupled between the differential cascoded circuit  402  and a ground V ss ; a P-type transistor M 9 ′ is coupled between the N-type transistor M 7 ′ and the supply source V dd , in which the P-type transistor M 9 ′ is controlled by a control voltage V p1′ ; a P-type transistor M 10 ′ is coupled between the N-type transistor M 8 ′ and the supply source V dd , in which the P-type transistor M 10 ′ is controlled by a control voltage V p2 ′; a loading capacitor C L3  exists at node N 5  and a loading capacitor C L4  exists at node N 6  as shown in  FIG. 6 . In this embodiment, the equivalent oxide thicknesses of the N-type transistors M 4 ′ and M 6 ′ are smaller than an equivalent oxide thickness of each of the N-type transistors M 1 ″ and M 2 ′, the P-type transistors M 3 ′ and M 5 ′, the N-type transistors M 7 ′ and M 8 ′, and the P-type transistors M 9 ′ and M 10 ′. Please note that, as in the first and second embodiments, the transistors having different equivalent oxide thicknesses correspond to different transistor types in a semiconductor process. In this embodiment, the N-type transistors M 4 ′ and M 6 ′ are core devices, and the others are I/O devices. Please note that the operation of increasing the operating speed of signal amplifying apparatus  400  is mostly the same as signal amplifying apparatuses  100 ,  300  and can be readily realized by a person skilled in this art after reading the above disclosure, thus the detailed description is omitted here for brevity. 
   Please refer to  FIG. 7 .  FIG. 7  is a diagram illustrating a signal amplifying apparatus  500  according to a fourth embodiment of the present invention. The signal amplifying apparatus  500  is a differential input single output amplifier for converting a differential input signal V in1  and V in2  into an output signal V out . The signal amplifying apparatus  500  comprises a differential input stage circuit  501 , a differential cascoded circuit  502 , an output stage circuit  503 , and capacitors C c3  and C c4 . The differential input stage circuit  501  comprises an N-type transistor M 1 ″ and a P-type transistor M 10 ″ having gate terminals (node N 1 ) to receive the first input signal V in1 ; and an N-type transistor M 2 ′ and a P-type transistor M 11 ″ having gate terminals (node N 2 ) to receive the second input signal V in2 . The differential cascoded circuit  502  comprises a P-type transistor M 3 ″, an N-type transistor M 4 ″, a P-type transistor M 5 ′, and an N-type transistor M 6 ″, in which a source terminal of the P-type transistor M 3 ′ is coupled to a drain terminal of the N-type transistor M 1 ″, the N-type transistor M 4 ′ has a drain terminal N 3  coupled to a drain terminal of the P-type transistor M 3 ″, a source terminal of the P-type transistor M 5 ″ is coupled to a drain terminal of the N-type transistor M 2 ″, and the N-type transistor M 6 ″ has a drain terminal N 4  coupled to a drain terminal of the P-type transistor M 5 ″. Furthermore, a DC level shifter  5021  is coupled between the P-type transistor M 3 ″ and N-type transistor M 4 ″ and between the P-type transistor M 5 ″ and N-type transistor M 6 ″. In this embodiment, the DC level shifter  5021  comprises two P-type transistors and two N-type transistors and is controlled by voltage V p3  and V n3 , respectively as shown in  FIG. 7 . Please note that the DC level shifter  5021  is a well-known component, thus the detailed description is omitted here for brevity. The output stage circuit  503  comprises an N-type transistor M 7 ″ having a gate terminal coupled to the drain terminal (node N 3 ) of the N-type transistor M 4 ″, and the output signal V out  is outputted at a drain terminal (node N 5 ) of the N-type transistor M 7 ″; similarly, a P-type transistor M 14 ″ has a gate terminal coupled to the drain terminal (node N 6 ) of the P-type transistor M 3 ″, and the output signal V out  is outputted at a drain terminal (node N 5 ) of the P-type transistor M 14 ″. As shown in  FIG. 7 , the capacitor C c3  has a first terminal connected to the drain terminal (node N 5 ) of the N-type transistor M 7 ″ and a second terminal coupled to a source terminal (node N 8 ) of the N-type transistor M 4 ″. Additionally, the capacitor C c4  has a first terminal connected to the drain terminal (node N 5 ) of the N-type transistor M 7 ″ and a second terminal coupled to a source terminal (node Ng) of the P-type transistor M 3 ″. 
   Furthermore, an N-type transistor M 8 ″ and an N-type transistor M 9 ″ are connected as a current mirror configuration coupled to the N-type transistors M 4 ″ and M 6 ″; similarly, a P-type transistor M 12 ″ and a P-type transistor M 13 ″ are connected as another current mirror configuration coupled to the P-type transistors M 3 ″ and M 5 ″. The equivalent oxide thicknesses of the N-type transistors M 4 ″ and M 6 ″, and the P-type transistors M 3 ″ and M 5 ″ are smaller than an equivalent oxide thickness of each of the N-type transistors M 1 ″, M 2 ″, M 7 ″, M 8 ″, M 9 ″, the P-type transistors M 10 ″, M 11 ″, M 12 ″, M 13 ″, M 14 ″ and transistors within the DC level shifter  5021 . Please note that, as mentioned above, the transistors having different equivalent oxide thicknesses correspond to different transistor types in a semiconductor process. In this embodiment, the N-type transistors M 4 ″, M 6 ″ and the P-type transistors M 3 ″, M 5 ″ are core devices, and the others are I/O devices. Furthermore, a current source I 1  is coupled between the source terminal of the N-type transistor M 1 ″ and M 2 ″ and a ground V ss ; a current source I 2  is coupled between the source terminal of the P-type transistor M 10 ″ and M 11 ″ and a supply voltage V dd ; and a loading capacitor C L4  exists at node N 5  as shown in  FIG. 7 . Please note that the operation of increasing the operating speed of the signal amplifying apparatus  500  is mostly the same as the signal amplifying apparatus  100  and can be readily understood by a person skilled in this art after reading the above-mentioned disclosure, thus the detailed description is omitted here for brevity. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Category: 5