Patent Document

TECHNICAL FIELD OF THE INVENTION 
       [0001]    The technical field of this invention is detection of very fast voltage drops in power supplies. 
       BACKGROUND OF THE INVENTION 
       [0002]    In systems having internal voltage regulators providing an internal power supply for a digital core, the internal power supply VDD may act totally independently from the power supply HDVDD for I/O functional elements. Often this internal power supply VDD is connected to an external capacitor and VDD is subject to external short circuits. Short circuit at VDD could result in a floating condition at the inputs to the I/O circuits and harmful extraneous currents flowing through the I/O from its power supply. It is imperative to detect this short circuit condition on the internal supply to set the I/O functions into a high impendence (HiZ) state eliminating floating inputs. 
         [0003]      FIG. 1  illustrates a typical protection circuit of prior art. The internal voltage regulator  101 , often based on a band gap temperature compensated reference, provides the power VDD  105  for core logic  108 . External supply voltage HVDD  110  supplies all circuitry operating at nominal VDD range including I/O circuits  104  supplied from a separate external device pin HVDD  112 . The power supply includes an internal capacitor  111  and an external pin  113  for attachment of an external capacitor. Internal voltage regulator  101  and I/O circuits  104  are powered between HVDD supply  110  and ground  100 . Core logic  108  is powered between VDD supply and ground  100 . Differential analog comparator  102  detects a low voltage on VDD at input  105 . Differential analog comparator  102  has an inverting input  105  receiving VDD and a non-inverting input  109  receiving a reference voltage VREF. Upon the occurrence of a low voltage at input  105 , analog comparator  102  produces a rapid high going signal at output  106 . This drives inverter  103  producing a low at node  107 , the active low HiZ input to I/O circuits  104 . This active low HiZ input places I/O circuits  104  in an off condition. 
         [0004]    There are two conceivable scenarios for VDD supply failures. The first scenario is DROOP, where supply VDD drops so slowly there is enough time to develop reset signals of sufficient amplitude. The second scenario is SHORT, where VDD drops immediately as by a short circuit. This drop is so fast that reset signals do not have enough time to attain sufficient amplitude. In this case no circuit supplied from VDD is reliable. The I/O control signals from the core logic  108  are then considered as invalid. 
         [0005]    Protection against unsafe power supply conditions requires effective detection that operates under failing VDD conditions that include extremely slow decay of VDD or moderate to fast changes resulting in VDD approaching 0.0 volts. Protection also must gate all I/O circuits into a HiZ condition when any potentially destructive power supply failure mechanisms in either VDD or HVDD are detected. 
       SUMMARY OF THE INVENTION 
       [0006]    The power supply supervision circuit arrangement of this invention uses a voltage detection circuit to detect fast decay of main circuit supply voltage. Additional analog comparators distinguish between short circuit conditions on the internal core logic supply at various ramp down rates. Power supply control circuitry acts upon carefully determined conditions and forces I/O circuits into a HiZ mode protecting them from exposure to high currents as a result of possible floating gate conditions in the output circuitry. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0008]      FIG. 1  illustrates a circuit diagram detecting a short circuit on the internal voltage supply and initiating action to place the I/O circuitry in a tri-stated condition (Prior Art); 
           [0009]      FIG. 2  illustrates in block diagram form the power supply safety system of this invention describing conditions for generation of the low ports_on signal to cause I/O circuitry to assume a HiZ state; 
           [0010]      FIG. 3  illustrates the simplified circuit of a portion of the power supply system of this invention using a multiplicity of analog comparators detecting the occurrence of conditions described in  FIG. 2  for responding to all unsafe power supply conditions; 
           [0011]      FIG. 4  illustrates waveforms describing voltage changes on HVDD and VDD and the generation of SVSH, SVSL, and BOR signals responding to the threshold levels described in  FIG. 2 ; 
           [0012]      FIG. 5  illustrates the logic diagram of the circuit used in the preferred embodiment of this invention to respond to all unsafe power supply conditions anticipated in both the VDD voltage supply for core logic circuits and the HVDD voltage supply for I/O circuitry; 
           [0013]      FIG. 6  illustrates the response of signals BOR, SUPon, VDDon, and ports on to a slow falling VDD ramp voltage, the Droop condition; 
           [0014]      FIG. 7  illustrates the response of signals BOR, SUPon, VDDon, and ports on to a medium range VDD step input, a mixture of Droop and short conditions; and 
           [0015]      FIG. 8  illustrates the response of signals BOR, SUPon, VDDon, and ports_n to a fast range VDD step input, a short circuit. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0016]      FIG. 2  illustrates in block diagram form the power supply safety system (PSSS) of this invention.  FIG. 2  describes conditions for generation of the ports_n signal to cause I/O circuitry to assume a HiZ state. 
         [0017]    In  FIG. 2  external power is supplied by HVDD  210 , supplying power for PSSS  229  and I/O circuits  104  ( FIG. 1 ). Temperature compensated voltage regulator  200  generates VDD  201  supplying power to core logic  230 . Analog scalar circuits are used in voltage generator block  235  to generate references voltages VREFH, VREFL, VREF 1 , VREF 2 , and VREF 3  used in the PSSS block  229 . 
         [0018]    Detection circuit  233  monitors VDD  201  and generates a high-going signal at Vx  208  upon detecting a degradation in VDD  201 . Inverter  227  drives the VDDon signal low at  209  to the ports_on control logic  231 . 
         [0019]    PSSS circuits  229  are divided into PSSL section  236 , PSSB section  232 , and PSSH section  234 . PSSH  234  contains precision analog comparators detecting the range of HVDD. PSSH  234  generates SCSH as 0 if HVDD is greater than 3.0 V. PSSH  234  generates SCSH as 1 if HVDD is less than 2.8 V. PSSB circuit  232  produces output BOR  221  from the VDD signal  201 . PSSL  232  generates BOR  221  as 0 if VDD is greater than the threshold voltage of a NMOS transistor. PSSL  232  generates BOR  221  as 1 if VDD is less than 1.3 V. PSSL  232  produces output SVSL  222  from the VDD signal  201 . PSSL  232  generates SVSL  222  as 0 if VDD is greater than 2.35 V. PSSL  232  generates SVSL  222  as 1 if VDD is less than 2.25 V. Signals BOR  221 , SVSL  222 , SVSH  223  and VDDon  209  supply ports ON Control Logic  231  which determines ports on signal  214 . A low state in ports_n signal  214  forces I/O circuitry into a HiZ condition. 
         [0020]    Both supplies VDD  201  and HVDD  210  are supervised by power supply safety system (PSSS)  229 . PSSS  229  includes: a) PSSB circuits  232  generating BOR  221 ; PSSL circuit  236  generating SVSL  222 ; and PSSH circuit  234  generating SVSH  223 . The following unsafe Power Supply Conditions are of interest. 
         [0021]    For a brownout decaying VDD: brownout reset circuit PSSB  232  senses VDD; low supply supervisor PSSL  232  generates BOR; and PSSB  232  is powered by VDD. This brownout feature is always active when VDD&gt;Vth, where Vth is NMOS threshold voltage, 1.0 V nom. 
         [0022]    For a short circuit on VDD having a medium to high rate ramp down, low supply supervisor PSSL  236  VDD senses and generates an active SVSL  222 . PSSL  236  uses precision comparators powered by VDD. PSSL  236  and internal reference voltage source  235  are powered by HVDD. For PSSL  236  to produce an active signal SVSL  222  it must have HVDDmin&gt;2.0 V. 
         [0023]    For a decaying HVDD with a medium to high rate ramp down: high supply supervisor PSSH  234  senses HVDD and generates SVSH. PSSH  234  uses precision comparators powered by HVDD. PSSH  234  employs an internal reference voltage source  235  is powered by HVDD. PSSH  234  must have HVDDmin&gt;2.0 V to operate properly. 
         [0024]      FIG. 3  illustrates the simplified circuit of a portion of the power supply system of this invention using multiple precision analog comparators detecting the occurrence of conditions described in conjunction with  FIG. 2 . 
         [0025]    Analog comparators  304  and  305  act as a pair to generate respective set signal  302  and reset set signal  303  for RS latch  300 . In latch  300 , a reset signal  302  overrides a set signal  303 . If both signals are low at the same time, reset signal  303  places latch  300  in a low state (Q=0). Initially, with HVDD above VREFH at terminal  309  (preferably 3.0 V) latch  300  is reset by a low signal at reset signal  303 . If HVDD falls below VREFH but remains above VREF 1  at terminal  306  (preferably 2.8 V), reset signal  303  goes high but latch  300  remains in the reset condition (SVSH=0). If HVDD falls below VREF 1 , set signal  302  goes low placing the latch in the set condition (SVSH=1). Table 1 describes the response of SVSH  301  to degradation in HVDD over the full range of voltage. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 HVDD 
                 R 303 
                 S 302 
                 SVSH 301 
               
               
                   
                   
               
             
             
               
                   
                 HVDD &gt; VREFH 
                 LOW 
                 HIGH 
                 LOW 
               
               
                   
                 VREF1 &lt; HVDD &lt; VREFH 
                 HIGH 
                 HIGH 
                 LOW 
               
               
                   
                 HVDD &lt; VREF1 
                 HIGH 
                 LOW 
                 HIGH 
               
               
                   
                   
               
             
          
         
       
     
         [0026]    Analog comparators  314  and  315  act as a pair to generate respective set signal  312  and reset signal  313  for latch  310 . In latch  310 , a reset signal  313  overrides a set signal  312 . If both signals are low at the same time, reset signal  313  places the latch in a low state (Q=0). Initially, with VDD above VREFL at terminal  319  (preferably 2.35 V) latch  310  is reset by a low at signal input  313 . If VDD falls below VREFL but remains above VREF 2  at terminal  316  (preferably 2.25 V), reset signal  313  goes high but the latch remains in the reset condition (SVSL=low). If VDD falls below VREF 2 , set signal  312  goes low placing the latch in the set condition (SVSL=high). Table 2 describes the response of SVSL  311  to degradation in VDD over the full range of voltage. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 VDD 
                 R_313 
                 S_312 
                 SVSL 311 
               
               
                   
                   
               
             
             
               
                   
                 VDD &gt; VREFL 
                 LOW 
                 HIGH 
                 LOW 
               
               
                   
                 VREF2 &lt; VDD &lt; VREFL 
                 HIGH 
                 HIGH 
                 LOW 
               
               
                   
                 VDD &lt; VREF2 
                 HIGH 
                 LOW 
                 HIGH 
               
               
                   
                   
               
             
          
         
       
     
         [0027]    Analog comparators  324  and  325  act as a pair to generate respective control signals for BOR output gate  320 . Comparator  324  compares the output voltage VDD with VREF 2  (X*Vth preferably 2.25 V) input at terminal  328 . This comparison signal is inverted by inverter  326 . Comparator  325  compares the output voltage VDD with VREF 3  (Y*Vth) input at terminal  329 . This comparison signal is inverted by inverter  327 . Table 3 describes the response of BOR  321  to degradation in VDD over the full range of voltage. 
         [0000]                                        TABLE 3                       VDD   322   323   BOR 321                           VDD &gt; X * Vth   HIGH   HIGH   LOW           Y * Vth &lt; VDD &lt; X * Vth   LOW   HIGH   HIGH           VDD &lt; Y * Vth   LOW   LOW   HIGH                        
BOR  321  is not driven by a latch, but is determined only by the conditions described in Table 3. BOR  321  is low if VDD is greater than VREF 2  (X*Vth preferably 2.25 V) and high if VDD is less than VREF 3  (Y*Vth) where X&gt;1, Y&gt;1 and X&gt;Y.
 
         [0028]      FIG. 4  illustrates the waveforms showing response of SVSH, SVSL, and BOR to degradation in HVDD and VDD described in Tables 1 to 3. 
         [0029]      FIG. 5  illustrates the complete logic diagram of the circuit used in this invention to respond to all unsafe power supply conditions. Current source  502  supplies current Ibn 1   511  from the HVDD supply  510  to the drain of an NMOS transistor  516 . The gate of NMOS transistor  516  is connected to VDD  501  which is the supervised internal supply. Node Vx  508  at drain of NMOS transistor  516  is connected to the input of an inverter  527  supplied from HVDD  520 . Transistors  506  and  507  produce a hysteresis in the response of the detection circuit. Capacitor  528  performs filtering on the HVSS supply  510 . 
         [0030]    If VDD  501  remains larger than the threshold voltage Vth of the NMOS switch composed of transistors  506 ,  507 , and  516 , node VX  508  is pulled down to VSS (ground)  525 . Inverter  527  causes VDDon  509  to high. When VDD  501  drops below Vth, current Ibn 1   511  pulls up node Vx  508 . Inverter  572  forces VDDon  509  low. The rate at which VDD falls is not significant because this circuit operates from HVD  510 . 
         [0031]    The drain of PMOS transistor  505  of current source  502  is connected to the drain of NMOS transistor  516 . The gate of transistor  516  receives VDD  501 . IREF  504  sets a bias current Ibn 2   503  to approximately 10 nA. Current source  505  supplies node Vx  508  with 40 nA driving node Vx  508  high and inverter  527  drives VDDon  509  low. Note that current ibn 2   503  set by IREF  504 , must be stable before there is action on node Vx  508 . Note that current ibn 1   511  is N times current ibn 2   503 . 
         [0032]    Whenever VDD exceeds the threshold voltage of NMOS transistor  506 , node Vx  508  is pulled towards VSS and inverter  527  drives node VDDon  509  high. Node SUPon  512  is high only when inputs BOR  521 , SVSL  522  and SVSH  523  of NOR gate  513  are all low. Output ports_n  514  of AND gate  515  is low when both VDDon  509  and SUPon  512  are both high. Output ports_on  514  functions to disable the I/O circuits. 
         [0033]    The two scenarios for VDD supply failures have an effect on the circuit. In the first scenario supply VDD  501  drops slowly so that there is enough time for SVS and BOR to disable the I/Os via SUPon  512 . In the second scenario supply VDD  501  drops immediately caused by a short, so fast that SVS and BOR do not have enough time to provide a pulse of sufficient amplitude to drive reset SUPon low. In this case, the inverter  537  will drive VDDon  509  low and disable the I/Os. 
         [0034]    The circuit of  FIG. 5  has these additional characteristics. This circuit draws a quiescent current of approximately 50 nA (Ibn 1 +Ibn 2 ) from the HVDD supply. The preferred embodiment of this circuit employs metal options to increase or decrease the quiescent current (Ibn 1 +Ibn 2 ) by about 50%. Capacitor (C_SLOW)  526  which slows the response of VDDon can be connected via a metal option. Capacitor (C_FAST)  524  which speeds up the response of VDDon can be connected via metal option. Since circuits generating BOR  521  and SVSL  522  are in the low supply domain (VDD), level shifters are needed to translate these signals properly in the HVDD domain. 
         [0035]      FIG. 6  illustrates the response of signals BOR  521 , SUPon  512 , VDDon  509  and ports on signal  514  to a slow falling ramp voltage in VDD  501 . Event  601  coincides with VDD=1.0 V and event  602  coincides with VDD=0.4 V. With VDD falling slowly (this example takes 300 milliseconds to ramp down from 2.5 V to 0.0 V) ports_on  514  is triggered by the BOR event  603 , which causes SUPon event  604  via NOR gate  513 . VDDon  509  falls abruptly at  605  and ports_on  514  responds to the BOR event  603  at  606 . BOR  521  works as intended and causes a high going output properly. Ports_on  514  goes low. This is called DROOP. 
         [0036]      FIG. 7  illustrates the response of signals BOR  521 , SUPon  512 , VDDon  509  and ports on  514  to a medium range VDD  501  step input. This example takes  200  nanoseconds to ramp down from 2.5 V to 0.0 V. Event  701  coincides with VDD=1.0 V where VDDon experiences a trigger event  710 . BOR  521  responds with only a spike  703  causing no further action. Event  702  coincides with VDD=0.4 V, resulting in a slow falling VDDon  705 . With VDD falling slowly (200 milliseconds to ramp down from 2.5 V to 0.0 V) ports_on falls at  706  as a result of VDDon crossing trip point  705  (VDD&lt;Vth). 
         [0037]    In  FIG. 7  the ramp is steeper and BOR  521  does not work in an ideal manner. The circuit produces just a spike or glitch allowing this state to pass unnoticed if no other part of the system recognizes it.  FIG. 2  includes detection circuit  233  and this circuit detects the failure condition when both VDDon and ports_on  706  go low. This presents a different failure condition, mastered as effectively as the first condition. This condition is a mixture between DROOP and SHORT. 
         [0038]      FIG. 8  illustrates the response of signals BOR  521 , SUPon  512 , VDDon  509  and ports_on  514  to a fast range VDD step input taking 10 nanoseconds to ramp down from 2.5 V to 0.0 V. Event  801  coincides with VDD rapidly passing through the trip point VDD=1.0 V. VDDon experiences a trigger trigger event  810  (VDD&lt;1.0 V). BOR  521  and SUPon  512  do not respond. Event  802  coincides with VDD=0.4 V, resulting in a slow falling VDDon  805 . With VDD falling slowly ports_on  514  falls at time  806  when the voltage at node Vx  508  crosses the input threshold of inverter  527 . 
         [0039]      FIG. 8  presents a third failure condition where the drop is so fast that there is no BOR reaction at all. Detection circuit  233  also reacts here and the result is like in the other 2 cases that ports_on  514  goes low. This is the SHORT case. The BOR spike is not intended, but due to the system design there is always a correct response (ports_n  514  going low).

Technology Category: 3