Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Patent Application No. 60/897,415 filed Jan. 24, 2007. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the High Definition Multimedia Interface (HDMI), and specifically to the conversion between different formats of HDMI video signals. 
     2. Prior Art 
     There are many component video formats in use. The most commonly used component video formats are RGB, YPbPr and YCbCr. The RGB format is the basic format in which the signal is generated in the video camera. In other formats the Y component of this signal is the black and white information contained within the original RGB signal. The Pb and Pr signal are color difference signals, which are mathematically derived from the original RGB signal. It is important to realize that what is commonly called “component video” (YPbPr or YCbCr) output and RGB video output are not the same and are not directly compatible with each other, however, they can be converted either way. 
     Advanced Television Systems Committee (ATSC) is a committee which specifies the digital TV broadcasting system in use in the USA. This standard supports both standard definition (SD) and (HD) broadcasts. There are 18 approved formats for digital TV broadcasts covering both SD (640×480 and 704×480 at 24p, 30p, 60p, 60i) and HD (1280×720 at 24p, 20p, and 60p; 1920×1080 at 24p, 30p and 60i). 
     HDMI has the capacity to support existing high-definition video frame and display formats (720p, 1080i, and 1080p/60). It also has the flexibility to support enhanced definition video frame and display formats such as 480p, as well as standard definition formats such as NTSC or PAL. 
     Currently there are a number of Video formats, each with its own ordered data streams having a specific sequence. There has been no common mapping facility which can be easily implemented as part of an integrated circuit to map these sequences into other usable video data sequences. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a conceptual diagram of a mapping matrix. 
         FIG. 2  is a tabular form of an exemplary mapping according to the disclosed invention. 
         FIG. 3  is a structural diagram of an “n” input to “n” output video pixel mapping matrix. 
         FIG. 4  is a hierarchical implementation of a multiplexer using a plurality of smaller multiplexers. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     There are today a number of formats for Video signals and the list of formats is growing to accommodate larger screens and higher definitions. Disclosed is an n×n Video data pixel mapping matrix implemented as a n×n crossbar mapping matrix, for example as an integrated circuit (IC), that enables the mapping of any of the n-data inputs to any of the n-data outputs. This mapping matrix allows the mapping of any existing video formats to any other existing or future video format, and allows flexibility of connectivity to any transmitter or receiver. This solution enables the achieving of the necessary mapping of video data sequences in one video format into other video data sequences corresponding to other video formats, including mapping of older video formats to newer formats and vice versa. 
     This invention allows all of today&#39;s known formats to be mapped to alternate formats efficiently. Today typical video data does not exceed 36 bits. Next generation Video formats may require a 48×48 mapping matrix, or even a 64×64 mapping matrix. Such matrices implemented in accordance with the disclosed invention can be easily implemented using currently available IC manufacturing technology. Even though the current and immediate future requirements will be met by a mapping matrix of 48×48, it is expected that future formats will require further extensions of the mapping matrix. There is no limitation to the possible extension of the mapping matrix to meet the needs of the future formats as they arise. 
     The current implementation requirement of this mapping matrix is a 36 input to 36 output unit. This allows all of today&#39;s commonly used formats to be mapped to alternate formats efficiently (as long as the video data does not exceed 36 bits). Next generation Video formats will require a 48×48 mapping matrix or 64×64 mapping matrix. These and even larger matrices can easily be implemented as an extension of the current 36 to 36 mapping matrix. 
     According to the disclosed invention, shown in  FIG. 1 , the mapping matrix is designed specifically for video data bit or pixel mapping. The mapping matrix has ‘n’ input signals  111  and ‘n’ output signals  121 . Each of the ‘n’ input signals  111  may be mapped by the mapping matrix  100  to any one of the ‘n’ output signals  121 . However, two input signals  111  cannot be mapped simultaneously to a single output signal  121 . For an ‘n’ pixel input having bit ( 0 ) to bit (n−1), the invention is shown pictorially in  FIG. 1  where the mapping matrix  100  with cross connects  110  is capable of interconnecting any one of the ‘n’ inputs  111  to any one, and only one, of the ‘n’ outputs  121  based on a specific and non-repeating select control or select signal value S[i] input  105  which is derived from a formatting signal. The formatting signal is decoded to produce the necessary control input values S[i] where [i] being integer values 0 to (n−1), associated with each input  111  of the 0 to (n−1) inputs of the mapping matrix  100 . These control S[i] inputs  105  thus enables the necessary connection through the mapping matrix  100  to the output  121 , each one input  111  of the 0 to (n−1) inputs connecting to one and only one of the 0 to (n−1) outputs  121  as designated by the control S[i] input  105 . 
     The value of each output decided using this characteristic is as follows: 
                       S   i     =     0   :       Dataout   ⁡     [   i   ]       ⇐     Datain   ⁡     [   0   ]             ⁢     
     ⁢       S   i     =     1   :       Dataout   ⁡     [   i   ]       ⇐     Datain   ⁡     [   1   ]             ⁢     
     ⁢   ⋮   ⁢     
     ⁢     Si   =       n   -   1     :       Dataout   ⁡     [   i   ]       ⇐     Datain   ⁡     [     n   -   1     ]                     (   1   )               
where i=0, 1, . . . n−1
 
     As a simple non-limiting example, a 24 to 24 conversion is shown. If the input video pixel is 24-bit RGB, the format is as follows: 
     Bit  0 —Red bit  1   
     Bit  1 —Red bit  2   
     Bit  2 —Red bit  3   
     Bit  3 —Red bit  4   
     Bit  4 —Red bit  5   
     Bit  5 —Red bit  6   
     Bit  6 —Red bit  7   
     Bit  7 —Red bit  8   
     Bit  8 —Green bit  1   
     Bit  9 —Green bit  2   
     Bit  10 —Green bit  3   
     Bit  11 —Green bit  4   
     Bit  12 —Green bit  5   
     Bit  13 —Green bit  6   
     Bit  14 —Green bit  7   
     Bit  15 —Green bit  8   
     Bit  16 —Blue bit  1   
     Bit  17 —Blue bit  2   
     Bit  18 —Blue bit  3   
     Bit  19 —Blue bit  4   
     Bit  20 —Blue bit  5   
     Bit  21 —Blue bit  6   
     Bit  22 —Blue bit  7   
     Bit  23 —Blue bit  8   
     and the desired output bit mapping, each input to a unique output, is to be as follows: 
     Bit  0 —Green bit  1   
     Bit  1 —Green bit  2   
     Bit  2 —Green bit  3   
     Bit  3 —Green bit  4   
     Bit  4 —Green bit  5   
     Bit  5 —Green bit  6   
     Bit  6 —Green bit  7   
     Bit  7 —Green bit  8   
     Bit  8 —Blue bit  1   
     Bit  9 —Blue bit  2   
     Bit  10 —Blue bit  3   
     Bit  11 —Blue bit  4   
     Bit  12 —Blue bit  5   
     Bit  13 —Blue bit  6   
     Bit  14 —Blue bit  7   
     Bit  15 —Blue bit  8   
     Bit  16 —Red bit  1   
     Bit  17 —Red bit  2   
     Bit  18 —Red bit  3   
     Bit  19 —Red bit  4   
     Bit  20 —Red bit  5   
     Bit  21 —Red bit  6   
     Bit  22 —Red bit  7   
     Bit  23 —Red bit  8   
     Then, in accordance with equations (1) above the values of S[i] are as follows: 
     S 0 =8 
     S 1 =9 
     S 2 =10 
     S 3 =11 
     S 4 =12 
     S 5 =13 
     S 6 =14 
     S 7 =15 
     S 8 =16 
     S 9 =17 
     S 10 =18 
     S 11 =19 
     S 12 =20 
     S 13 =21 
     S 14 =22 
     S 15 =23 
     S 16 =0 
     S 17 =1 
     S 18 =2 
     S 19 =3 
     S 20 =4 
     S 21 =5 
     S 22 =6 
     S 23 =7 
     The information is shown in a tabular form in  FIG. 2 . 
       FIG. 3  is an exemplary and non-limiting block diagram  300  of a ‘n’ input  111 , datain[ 0 ] to datain [n−1], and ‘n’ output  121 , dataout[ 0 ] to dataout[n−1] of mapping matrix  100 . Each block comprise of ‘n’ n-to-1 multiplexers  310 ( 0 ) to  310 ( n− 1). Each multiplexer  310  is associated with a corresponding select signal S [i], which decodes which input gets to be connected to which output as explained in more detail above. For each pixel format mapping configuration there will be one and only one non-repeating select signal value S[i] associated with each multiplexer. This ensures that only one input signal gets connected to an output. The select signals may be provided by a control unit  320  that generates the desired select signals. By providing a mapping of the ‘n’ inputs to the ‘n’ outputs according to the specific select input signal values, the mapping matrix  100  can change the input video pixel format to any desired output pixel format. The control unit  320  may be preprogrammed with currently known mapping schemes. The selection of a specific conversion would result in the use of the appropriate select signals, for example those shown in  FIG. 2 . The out put of the control unit  320  is also shown in example in  FIG. 3  as select signals S( 0 ) to S(n−1). The control unit  320  is designed so that a no two inputs may be simultaneously connected through the multiplexers to a single output. 
       FIG. 4  shows a hierarchical implementation of a multiplexer  310  from a plurality of smaller multiplexers, i.e., multiplexers having a lesser number of inputs, and enabled in accordance with the disclosed invention. In this exemplary and non-limiting implementation, the path of a single output signal in a 64×64 mapping matrix is implemented by 64 multiplexers  310 . Each of the 64-to-1 multiplexers  310 , can be comprised of three levels of hierarchy,  410 ,  420  and  430  using 4-input multiplexers as shown in  FIG. 4 . The first hierarchy level  410  is comprised of sixteen 4-input multiplexers  410 - 0  to  410 - 15 . There are hence 64 inputs into this multiplexer  310  at the first hierarchy level, one from each input, i.e., input[ 0 ] to input [ 63 ]. The selected outputs of the 16 multiplexers of hierarchy level  410  are fed into the second hierarchy level  420  where there are four 4-input multiplexers  420 - 0  to  420 - 3 . The outputs from the second hierarchy level  420  are fed into a single 4-input multiplexer  430 - 0  that comprises the third hierarchical level  430 . The third hierarchy level  430  has a single output signal that is connected to the designated output of multiplexer  310 . The 64-to-1 multiplexer uses the decoded select signal S[i] as input into each of the 4-input multiplexers of multiplexer  310  for selection of the path from input to output. 
     The use of this simple configurable mapping matrix scheme for mapping data from one video format to another will greatly reduce the need for dedicated video transmission or reception. It will help make the systems compatible with one another, irrespective of the formats used. This will also help to map old formats to new formats and vice versa, allowing use of older transmissions to be viewed on new display devices and new transmissions to be viewed on older display devices. This will reduce the hardship to the consumer in requiring new display devices every time new formats are introduced. In a typical implementation, this mapping matrix can be a stand alone IC, or be integrated as a part of an IC used for handling video data. 
     The use of the configurable mapping matrix for video format mapping will reduce the need for the equipment manufacturers to have a number of versions of dedicated display equipment, each covering at best a limited number of formats. The use of the mapping matrix, implemented as part of a video handling IC, to convert any system for use with any available format is disclosed. This will enable reduction of the number of system types and reduce the cost of inventory and stocking. On a chip level manufacturing of the IC, a standard chip set that is configurable will be able to take advantage of the economy of scale that will be available to improve profitability and reduce costs. Even though the disclosure is for a hardware implementation, it is not limiting and the inventions herein may be implemented in hardware, software, firmware or any combination thereof. 
     Thus the present invention introduces the concept of using a configurable mapping matrix for mapping data from one format to another in the Video field-unique solution for the industry. The invention will allow the mapping from any of the old formats to new formats as new formats arise as long as the number of Video bits is limited to N, currently  36  in the present implementation. The idea of the expandable mapping matrix for the above purpose makes the future conversion mapping matrix development simple and easy. In addition, there is a cost advantage for equipment manufacturers in using such a mapping matrix, allowing reconfiguration between old and/or new formats as required. There is also a cost reduction of the chip due to economy of scale. 
     Thus while certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Technology Category: 5