Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates generally to a data output buffer and, more particularly, to a data output buffer capable of reducing the power consumption of a circuit using a low power, by turning off a data output buffer driver to make output data become a HIGH impedance in a deep power down mode.  
           [0003]    2. Description of the Related Art  
           [0004]    Generally, in memory devices such as DRAM, a data signal of a cell amplified by a bit line sense amplifier in a row address path is transmitted from a bit line to a data bus line when a column select signal outputted from a column decoder turns on a data bus line gate. Then, if the data is inputted to a data bus line sense amplifier, the data bus line sense amplifier is activated to amplify the data again and sends the data to a read driver. Only a read driver selected to a bit combination of the data output is activated so that data is transmitted to a data output buffer. The data output buffer is activated under the control of an output enable signal (OE: output enable) and a /CAS signal. The output path for the data is called a ‘read path’. Of this output path, a dual data output buffer will be described in detail with reference to FIG. 1.  
           [0005]    [0005]FIG. 1 is a circuit diagram of a conventional data output buffer.  
           [0006]    The conventional data output buffer includes a driver driving control unit  10  for controlling an output of a data output driver  20 . The data output driver  20  transmits read data to a data output terminal according to a control signal from the driver driving control unit  10 .  
           [0007]    The driver driving control unit  10  includes a first level shifter  11  and a first output control unit  12 . First, the first level shifter  11  includes PMOS transistors P 1  and P 2  having a cross coupled structure and NMOS transistors N 1  and N 2  receiving an output enable signal OE and an output enable signal /OE inverted by an inverter IV 1 , respectively. Also, the first output control unit  12  includes an inverter IV 2  for inverting an output control signal DOFFZ outputted from the first level shifter II to produce an output control signal DOFF.  
           [0008]    The data output driver  20  includes a second level shifter  21 , a third level shifter  22 , a first pull-up control unit  23 , a first pull-down control unit  24  and a first output driver  25 . First, the second level shifter  21  includes PMOS transistors P 3  and P 4 , NMOS transistors N 3  and N 4 , and NMOS transistor N 5 . PMOS transistors P 3  and P 4  have a cross coupled structure, NMOS transistors N 3  and N 4  receive a data signal RDO and an inverted data signal /RDO inverted by an inverter IV 3 , and NMOS transistor N 5  controls the output of the data signal RDO depending on the input of a pipe counter signal PCNT.  
           [0009]    Also, the third level shifter  22  includes PMOS transistors P 5  and P 6 , NMOS transistors N 6  and N 7 , and NMOS transistor N 8 . PMOS transistors P 5  and P 6  have a cross coupled structure, NMOS transistors N 6  and N 7  receive the data signal RDO and an inverted data signal /RDO inverted by an inverter IV 4 , and a NMOS transistor N 8  controls the output of the data signal RDO depending on an input of the pipe counter signal PCNT. The first pull-up control unit  23  includes a PMOS transistor P 7  for outputting a pull-up signal depending on the output control signal DOFFZ applied from the first output control unit  12  of the driver driving control unit  10 .  
           [0010]    The first pull-down control unit  24  includes a NMOS transistor P 9  for outputting a pull-down signal depending on the output control signal DOFF applied from the first output control unit  12  of the driver driving control unit  10 . The first output driver  25  includes a PMOS transistor P 8  and a NMOS transistor N 10 . The PMOS transistor P 8  outputs the output data to a data output pin DQ depending on a pull-up signal UPZ applied from the pull-up control unit  20 . Also, the NMOS transistor N 10  outputs the output data to a data output pin DQ depending on a pull-down signal DN applied from the pull-down control unit  24 .  
           [0011]    An operation of the conventional data output buffer with this construction will be described with reference to the timing diagram of FIG. 2.  
           [0012]    First, if a read command READ is inputted, the output enable signal OE becomes HIGH and the output of the first level shifter  12  becomes HIGH, so that the output control signal DOFFZ is inputted to the first output control unit  12 . The first output control unit  12  inverts the output control signal DOFFZ using the inverter IV 2  to produce the output control signal DOFF with a LOW level. The data signal RDO applied from the memory cell is applied to the data output terminal of the data output driver  20 .  
           [0013]    Next, during a NOP period where the read command READ is not applied, the output control signal DOFF becomes HIGH. The output of the first output driver  25  then moves to a HIGH impedance state.  
           [0014]    Thereafter, when the semiconductor device is not driven, such as if a deep power down mode is set in order to reduce the power consumption, all internal supply voltages within the semiconductor memory device are not supplied. At this time, the levels of the output control signal DOFF and the output control signal DOFFZ, which control the output of the data output driver  20 , become unstable. Therefore, the pull-up signal UPZ and the pull-down signal DN of the first pull-up control unit  23  and the first pull-down control unit  24 , respectively, cannot maintain a stable level state.  
           [0015]    In the case where an external power is used in the data output driver  20 , and the pull-up signal UPZ becomes LOW, the output data becomes HIGH since the PMOS transistor P 8  of the first output driver  25  is turned on (Case 1). Also, if the pull-down signal DN becomes HIGH, the output data becomes LOW since the NMOS transistor N 10  of the first output driver  25  is turned on (Case 2). Further, if the pull-up signal UPZ is LOW and the pull-down signal DN is HIGH, since the PMOS transistor P 8  and the NMOS transistor N 10  are turned on (Case 3), a current path is formed at the output terminal of the output driver  25 .  
           [0016]    On the contrary, in the case where an internal power voltage is used in the data output driver  20 , a current path is formed through the data bus line, the PMOS transistor P 8  and the NMOS transistor N 10  in the above mentioned Cases 1 and 2. Also, in the above Case 3, a current path is formed between the data bus line and the internal power voltage.  
           [0017]    Upon initiation of a deep power down mode, it is required that the output data be kept to be a HIGH impedance. However, due to formation of the current path, the output data does not keep HIGH impedance and the output data is transmitted to the output terminal. As a result, current is consumed in the data bus line.  
         SUMMARY OF THE INVENTION  
         [0018]    The present disclosed apparatus reduces unnecessary power consumption by preventing a current path, thereby improving an output control unit for controlling a data output driver upon a deep power down mode to maintain a HIGH impedance.  
           [0019]    A data output buffer is disclosed including a driver driving control unit configured to control an output of data depending on the a state of an output enable signal. The data output buffer also includes a data output driver configured to transmit the data to a data output terminal according to the driving control unit. The driver driving control unit also includes a level shifter for shifting the level of an input voltage depending on the output enable signal. The driver driving control unit also includes an output control unit for controlling the output of the data output driver to be placed in a high impedance state depending on the state of an output signal of the level shifter and a deep power down signal that is enabled upon initiation of a deep power down mode.  
           [0020]    Further disclosed is a data output buffer comprising a driver driving control unit configured to output an output control signal to control an output of data depending on a state of an output enable signal. Further included is a data output driver configured to logically combine an output control signal from the driver driving control unit and the data signal and control an output terminal of the data to be placed in a high impedance state upon initiation of a deep power down mode depending on a state of a deep power down signal enabled upon initiation of the deep power down mode.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    [0021]FIG. 1 is a circuit diagram of a conventional data output buffer.  
         [0022]    [0022]FIG. 2 is a timing diagram of the data output buffer in FIG. 1.  
         [0023]    [0023]FIG. 3 is a circuit diagram of a data output buffer according to the present disclosed apparatus.  
         [0024]    [0024]FIG. 4 is a timing diagram of the data output buffer illustrated in FIG. 3.  
         [0025]    [0025]FIG. 5 is a circuit diagram of a data output buffer according to another embodiment of the present disclosure.  
         [0026]    [0026]FIG. 6 is a circuit diagram of a data output buffer according to still another embodiment of the present disclosure. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0027]    [0027]FIG. 3 is a circuit diagram of a data output buffer that includes a driver driving control unit  100  for controlling an output of a data output driver  200 , which transmits read data to a data output terminal according to a control signal of the driver driving control unit  100 .  
         [0028]    The driver driving control unit  100  includes a fourth level shifter  111  and a second output control unit  112 . Fourth level shifter  111  includes PMOS transistors P 9  and P 10  having a cross coupled structure and NMOS transistors N 11  and N 12  receiving an output enable signal OE and an inverted output enable signal /OE inverted by an inverter IV 5 , respectively. Also, the second output control unit  112  includes an inverter IV 6 , a NAND gate ND 1  and an inverter IV 7 . An inverter IV 6  inverts a deep power down signal DPD, a NAND gate ND 1  performs a NAND logic function on an inverted deep power down signal /DPD inverted through an inverter IV 6  and an output signal of the fourth level shifter  111  to produce an output control signal DOFF, and an inverter IV 7  inverts an output control signal DOFF of the NAND gate ND 1  to produce an output control signal DOFFZ. The second output control unit  112  for controlling an output of the data output driver  200  uses an external power voltage since all the internal power voltages are off upon a deep power down mode.  
         [0029]    Further, the data output driver  200  includes a fifth level shifter  201 , a sixth level shifter  202 , a second pull-up control unit  203 , a second pull-down control unit  204  and a second output driver  205 . First, the fifth level shifter  201  includes PMOS transistors P 11  and P 12  having a cross coupled structure, NMOS transistors N 13  and N 14  for respectively receiving a data signal RDO and an inverted data signal /RDO inverted by an inverter IV 8  and a NMOS transistor N 15  for controlling the output of the data signal RDO depending on an input of a pipe counter signal PCNT. Also, the sixth level shifter  202  includes PMOS transistors P 13  and P 14  having a cross coupled structure, NMOS transistors N 16  and N 17  for respectively receiving the data signal RDO and the inverted data signal /RDO inverted by an inverter IV 9  and a NMOS transistor N 18  for controlling an output of the data signal RDO depending on an input of the pipe counter signal PCNT. The second pull-up control unit  203  includes a PMOS transistor P 15  for outputting a pull-up signal UPZ depending on the output control signal DOFFZ applied from the second output control unit  112  in the driver driving control unit  100 . The second pull-down control unit  204  includes a NMOS transistor P 19  for outputting a pull-down signal DN depending on the output control signal DOFF applied from the second output control unit  112  in the driver driving control unit  100 . The second output driver  205  includes a PMOS transistor P 16  and a NMOS transistor N 20 , and receives the pull-up signal UPZ and the pull-down signal DN to output an output data.  
         [0030]    An operation of the data output buffer having the construction illustrated in FIG. 3 will be described with reference to the timing diagram of FIG. 4.  
         [0031]    First, in the case where the data output buffer is not the deep power down mode, and a read command READ is inputted, the output enable signal OE is enabled to be HIGH and the output of the fourth level shifter  111  becomes a HIGH level. Also, in the case where the data output buffer is in the deep power down mode, the deep power down signal DPD enabled to be HGIH is inputted with LOW and is then inverted by the inverter IV 6  so that a signal of HIGH is inputted to the NAND gate ND 1 . The NAND gate ND 1  in the second output control unit  112  performs a NAND logic function on the signals from the fourth level shifter  111  and the inverter IV 6  to produce the output control signal DOFF with a LOW level. The output control signal DOFF is inputted to the inverter IV 7  and the output control signal DOFFZ becomes a HIGH level. Therefore, the second pull-up unit  203  and the second pull-down unit  204  in the data output driver  200  are turned off depending on the output control signal DOFF and the output control signal DOFFZ. Also, the data signal RDO applied from a memory cell of a semiconductor device is applied to the output driver  205  through the fifth level shifter  201  and the sixth level shifter  202 , respectively, so that data is outputted by the output driver  205 .  
         [0032]    Further, in the case where the data output buffer is not the deep power down mode, the deep power down signal DPD is inputted with LOW and a signal of HIGH inverted by the inverter IV 6  is inputted to the NAND gate ND 1 . Also, in case of NOP, when a command that does not include a read is inputted, the output enable signal OE is disabled to be LOW so that the output of the fourth level shifter  111  with a LOW level is inputted to the NAND gate ND 1  of the second output control unit  112 . Due to this operation, the NAND gate ND 1  outputs a HIGH signal as the output control signal DOFF and the output control signal DOFFZ becomes LOW by the inverter IV 7 . Therefore, a LOW signal is inputted to the second pull-up unit  203  in the data output driver  200  and a HIGH signal is inputted to the second pull-down unit  204 , so that the pull-up signal UPZ and the pull-down signal DN are inputted with HIGH and LOW, respectively. As a result, the PMOS transistor P 16  and the NMOS transistor N 20  in the output driver  205  are turned off so that the output data becomes a HIGH impedance state.  
         [0033]    Meanwhile, when the data output buffer is set into the deep power down mode, all the internal power voltages become off. If the deep power down signal DPD is enabled to HIGH, a LOW signal is applied to the NAND gate ND 1  via the inverter IV 6 . Therefore, the NAND gate ND 1  outputs a HIGH signal as the output control signal DOFF and the output control signal DOFFZ is inverted by the inverter IV 7 , which is then outputted as a LOW level. If the output control signal DOFF and the output control signal DOFFZ in the second output control unit  112  become HIGH and LOW respectively, the PMOS transistor P 15  and the NMOS transistor N 19  in the second pull-up control unit  203  and the second pull-down control unit  204  are turned on. If the pull-up signal UPZ having a HIGH level is inputted to the PMOS transistor P 16  of the output driver  205  and a pull-down signal DN having a LOW level is inputted to the NMOS transistor N 20  of the output driver  205 , the PMOS transistor P 16  and the NMOS transistor N 20  are all turned off. Therefore, upon a deep power down mode, it is possible to maintain the output of the output driver  205  at a HIGH impedance state. As a result, upon a deep power down mode, it is possible to prevent the generation of unnecessary output data, thereby reducing consumption of current.  
         [0034]    [0034]FIG. 5 is a circuit diagram of a data output buffer according to another embodiment of the disclosure.  
         [0035]    The data output buffer of FIG. 5 includes a driver driving control unit  300  for controlling an output of a data output driver  400 , which transmits read data to a data output terminal depending on a control signal of the driver driving control unit  300 . The driver driving control unit  300  includes a seventh level shifter  301  and a third output control unit  302 . First, the seventh level shifter  301  includes PMOS transistors P 17  and P 18  having a cross coupled structure, and NMOS transistors N 21  and N 22  for respectively receiving an output enable signal OE and an output enable signal /OE inverted by an inverter IV 10 . Also, the third output control unit  302  includes a NMOS transistor N 23  and an inverter IV 11  connected between an output terminal of a seventh level shifter  301  and ground. The NMOS transistor N 23  receives a deep power down signal DPD through its gate, and an inverter IV 11  inverts an output control signal DOFFZ from the seventh level shifter  301  to produce an output control signal DOFF.  
         [0036]    Further, the data output driver  400  includes an eighth level shifter  401 , a ninth level shifter  402 , a third pull-up control unit  403 , a third pull-down control unit  404  and a third output driver  405 . First, the eighth level shifter  401  includes PMOS transistors P 19  and P 20  having a cross coupled structure, NMOS transistors N 24  and N 25  for respectively receiving the data signal RDO and an inverted data signal /RDO inverted by an inverter IV 12  and a NMOS transistor N 26  for controlling the output of the data signal RDO depending on an input of the pipe counter signal PCNT. Also, the ninth level shifter  402  includes PMOS transistors P 21  and P 22  having a cross coupled structure, NMOS transistors N 27  and N 28  for respectively receiving the data signal RDO and an inverted data signal /RDO inverted by an inverter IV 13  and a NMOS transistor N 29  for controlling the output of the data signal RDO depending on an input of the pipe counter signal PCNT. The third pull-up control unit  403  includes a PMOS transistor P 23  for outputting a pull-up signal UPZ depending on an output control signal DOFFZ applied from the third output control unit  302  of the driver driving control unit  300 . The third pull-down control unit  404  includes a NMOS transistor P 30  for outputting a pull-down signal DN depending on the output control signal DOFF applied from the third output control unit  302  of the driver driving control unit  300 . The third output driver  405  includes a PMOS transistor P 24  and a NMOS transistor N 31  both of which are serially connected between the power voltage terminal and the ground voltage terminal. And PMOS transistor P 24  receives the pull-up signal UPZ and A NMOS transistor N 31  receives the pull-down signal DN to produce an output data.  
         [0037]    In the data output buffer having the construction of FIG. 5, the deep power down signal DPD is enabled to be HIGH so that the NMOS transistor N 23  is turned on, upon the deep power down mode. At this time, the output control signal DOFFZ is disabled to be at a LOW level and the output control signal DOFF is enabled to be at a HIGH level by the inverter IV 11 . Also, if a LOW level signal is inputted to the third pull-up unit  403 , the PMOS transistor P 23  is turned on. Further, if a HIGH level signal is inputted to the third pull-down unit  404 , the NMOS transistor N 30  is turned on. As a result, the PMOS transistor P 24  and the NMOS transistor N 31  in the output driver  405  are turned off by the pull-up signal UPZ and the pull-down signal DN so that the output of the output driver  405  can be maintained at a HIGH impedance state during the deep power down mode.  
         [0038]    [0038]FIG. 6 is a circuit diagram of a data output buffer according to still another embodiment of the disclosure.  
         [0039]    The data output driver  500  of FIG. 6 includes a logic unit  501 , a fourth output control unit  502  and a fourth output driver  503 . A logic unit  501  logically combines the output control signal DOFF and the data signal DO to output the pull-up signal UPZ and the pull-down signal DN, a fourth output control unit  502  controls the output of the output driver  503  depending on the pull-up signal UPZ and the pull-down signal DN applied from the logic unit  501 , and the deep power down signal DPD, and a fourth output driver  503  controls the output of the output data depending on a control signal from the fourth output control unit  502 .  
         [0040]    The logic unit  501  includes an inverter IV 14 , a NAND gate ND 2  and a NOR gate NOR 1 . The inverter IV 14  inverts an output control signal DOFF, a NAND gate ND 2  performs a NAND logic function on a signal applied from the inverter IV 14  and the data signal DO to output a pull-up signal UPZ, and a NOR gate NOR 1  performs a NOR logic function on the output control signal DOFF and the data signal DO to output a pull-down signal DN.  
         [0041]    Also, the fourth output control unit  502  includes an inverter IV 15 , a PMOS transistor P 25  and a NMOS transistor N 32 . The inverter IV 15  inverts the deep power down signal DPD. A PMOS transistor P 25  is connected between the power voltage terminal and the output terminal of the NAND gate ND 2  and has a gate to which is inputted an inverted deep power down signal /DPD. NMOS transistor N 32  is connected between an output terminal of the NOR gate NOR 1  and a ground voltage terminal and has a gate to which is inputted the deep power down signal DPD.  
         [0042]    Further, the fourth output driver  503  includes a PMOS transistor P 26  and a NMOS transistor N 33  serially connected between the power voltage terminal and the ground voltage terminal. The fourth output driver  503  receives the pull-up signal UPZ and the pull-down signal DN from the fourth output control unit  502  via a gate of PMOS transistor P 26  and a gate of NMOS transistor N 33 , respectively, to produce an output data.  
         [0043]    The logic unit  501  with the above-described construction outputs the pull-up signal UPZ and the pull-down signal DN due to a logic combination of the output control signal DOFF and the data signal DO. Upon a deep power down mode, the deep power down signal DPD is enabled to be HIGH. Thus, the NMOS transistor N 32  in the fourth output control unit  502  is turned on and the PMOS transistor P 25  is turned off by the inverted deep power down signal /DPD inverted by the inverter IV 15 . Therefore, a HIGH signal is inputted to the PMOS transistor N 26  of the output driver  503  and a LOW signal is inputted to the NMOS transistor N 33  so that the output data can be kept at a HIGH impedance state.  
         [0044]    As mentioned above, according to the present disclosure, the final driver of a data output driver is placed in an OFF state in a deep power down mode wherein all power voltage devices internally used are in OFF states in order to reduce the power consumption in a device using a low power. Therefore, the presently disclosed devices can prevent a data problem at a data output terminal by placing the output data at a HIGH impedance state and prevent unnecessary power consumption by preventing a formation of a current path.  
         [0045]    While the teachings of the invention have been explained with respect to particular examples, it will be apparent to-those of ordinary skill in the art that the scope of this patent is not limited to those examples. On the contrary, this patent covers all apparatuses and methods falling within the spirit and scope of the appended claims, either literally or under the doctrine of equivalents.

Technology Category: 5