Patent Document

FIELD OF INVENTION 
   The present invention relates to an apparatus and method for generating adaptive idle voltage signals in electronic devices. The electronic device may be a memory device, an automotive component, a mobile phone, a pager, or any electronic circuit that requires the generation of voltage signals, such as by a charge pump, higher than supply voltage levels. 
   BACKGROUND 
   A need exists for voltages higher than supply voltage levels in electronic devices. For instance, in order to modify non-volatile memory, such as flash memory, a high voltage level signal is needed for providing Fowler-Nordheim (FN) tunneling. High voltage levels may also be used for reading information stored in a memory cell or memory matrix in circuits otherwise operating at lower power supply voltage levels. 
   In electronic devices, high voltage signals are typically provided by charge pumps. Charge pumps are switched capacitor circuits which can provide a voltage level to a capacitive load up to (N+1)*V dd , where N can be any number of stages in the charge pump and V dd  is the supply voltage. The supply voltage V dd  is typically 1.8 to 5.5 volts, but can be any other voltage level. 
   Charge pumps may be controlled by a plurality of clock signals or regulator circuits which control the desired charge pump output voltage level. Methods for regulating a charge pump include pulse-skip regulation and serial or linear regulation. In pulse-skip regulation, charge pump clock signals are enabled when the charge pump output voltage is lower than a desired value and disabled when the charge pump output voltage exceeds the desired value. In linear regulation, the charge pump output voltage is regulated by a closed-loop error amplifier and a pass device, such as a transistor. Linear regulation may provide a continuous adjustment of the charge pump output voltage, rather than the incremental and periodic adjustments provided by pulse-skip regulation. 
     FIG. 1A  illustrates an example of a conventional high voltage level generator circuit  100  with pulse-skip regulation. Supply voltage V dd  is coupled to charge pump  102  which provides a high voltage level signal to load capacitance C load    104 . Operational amplifier (OP-AMP)  114  provides regulation by comparing the voltage divider level V 1  at node  110  to voltage level V BGAP  at node  112 , which may be a predetermined band-gap voltage level. The band-gap reference voltage V BGAP  may be dependent on the materials used to fabricate an electronic device. The voltage level V 1  is dependent upon the values of variable resistors R 1    106  and R 2    108 . If V 1 &gt;V BGAP , a signal  116  is generated and an internal clock signal (not shown) in charge pump  102  is turned OFF, thereby disabling charge pump  102 . If V 1 &lt;V BGAP , a signal is generated on node  116  for enabling the internal clock signal to enable charge pump  102  to provide a high voltage level signal to V out  and capacitance C load    104 . 
     FIG. 1B  illustrates an example of a conventional high voltage level generator circuit  101  with linear regulation. In circuit  101 , a p-type metal-oxide semiconductor (PMOS) transistor  124  is coupled between node  122  and output node  126  which drives load capacitance C load    128  with a high voltage level signal. A closed-loop amplifier configuration is provided by amplifier  134 , transistor  124 , and adjustable resistors R 1    130  and R 2    132 . Voltage level V BGAP  at node  138  is the band-gap voltage level and V 1  at node  136  is the voltage divider level. The high voltage level signal provided to V out  node  126  and capacitance C out    128  is regulated using linear adjustment provided by the closed-loop configuration. The charge pump  120  provides the necessary supply voltage at node  122  for PMOS transistor  124 . 
   In circuits  100  and  101 , the high voltage level V out  provided by the charge pumps  102  and  120  is given by Equation(1) as follows:
 
 V   out   =R   eq   ×V   BGAP   Equation(1)
 
R eq  is given by Equation(2) as follows:
 
                   R   eq     =           R   1     +     R   2         R   2       .             Equation   ⁢           ⁢     (   2   )                 
Therefore, the high voltage output V out  may be adjusted by changing the values of the variable resistors in circuits  100  and  101 . The variable resistors may be configurable by using selection transistors which can enable or disable a resistor in series in a circuit, as desired, and provide real time selection of output voltages.
 
   Problems may arise when providing the high voltage signal V out  to circuit elements across an electronic device. For example, in memory devices high voltage signals may be used on word-lines, bit-lines, source lines, a common transistor node, or any other node for programming or erasing information in a plurality of memory cells. The high voltage signals are supplied to these lines or nodes by controlled switches. Undesirable switching disturbances on supply lines in a memory device may be caused when a read operation takes place in at least one memory cell while a write or erase operation takes place in at least one other memory cell. Therefore, a need exists for improving electronic device operation by compensating for undesirable voltage supply line effects or disturbances. 
   SUMMARY 
   An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more detailed understanding of the invention may be had from the following description, given by way of example and to be understood in conjunction with the accompanying drawings wherein: 
       FIG. 1A  is an example of a conventional high voltage level generator circuit with pulse-skip regulation; 
       FIG. 1B  is an example of a conventional high voltage level generator circuit with linear regulation; 
       FIG. 2  is an illustration of a device for providing a high voltage signal to a memory device in accordance with an embodiment of the present invention; 
       FIG. 3  is an illustration of a device for providing a high voltage signal to a memory device with idle state voltage regulation using two stage switching in accordance with another embodiment of the present invention; 
       FIG. 4  is an illustration of an adaptive voltage generator for providing an idle state voltage in accordance with another embodiment of the present invention; 
       FIG. 5A  is an illustration of an adaptive voltage generator for providing an idle state voltage with a pulse-skip charge pump regulator in accordance with another embodiment of the present invention; 
       FIG. 5B  is an illustration of an adaptive voltage generator for providing an idle state voltage with a linear charge pump regulator in accordance with another embodiment of the present invention; 
       FIG. 6A  is an illustration of an adaptive voltage generator for providing an idle state voltage with pulse-skip regulation and disturbance sensitivity in accordance with another embodiment of the present invention; 
       FIG. 6B  is an illustration of an adaptive voltage generator for providing an idle state voltage with linear regulation and disturbance sensitivity in accordance with another embodiment of the present invention; 
       FIG. 7  is a flow diagram of a process for providing an idle state voltage to a memory device in accordance with another embodiment of the present invention; and 
       FIG. 8  is a flow diagram of a process for providing an idle state voltage to an electronic device in accordance with another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention will be described with reference to the drawing figures wherein like numerals represent like elements throughout. For purposes of describing the present invention, the phrase low, medium, or high voltage levels are used. It will be appreciated that the words “low”, “medium”, and “high” are relative terms and not necessarily a fixed voltage. Accordingly, the phrase low, medium, or high voltage level may be any voltage and may vary, for example, based on the processing technology and/or the material in which an electronic device is implemented. The word “level” may represent a fixed voltage or a voltage range, as desired. Moreover, predetermined voltage levels in the description forthcoming can be any voltage level and may be dependent on the design, structure, and materials used to configure a circuit element. 
   A node, a voltage at a node, or a current at a node may be used interchangeably and a load capacitance may be a parasitic capacitance in the description forthcoming. A line may be a bus line, a node, an interconnect, a connection, or an electric coupling, as desired. In addition, a closed switch may be similar to digital switch being enabled while an open switch may be similar to a digital switch being disabled. 
   The present invention may be used in any electronic device, such as a memory device or module. Examples of memory devices include parallel or serial Electrically Erasable Programmable Read-Only Memories (EEPROMs), Flash memories, serial Flash memories, and stacked Flash and Random Access Memory (RAM) modules. 
     FIG. 2  is an illustration of a device  200  for providing a high voltage signal to a memory device. Purely as an example, device  200  may be implemented in a memory device for providing read-while-write (RWW) capability. RWW provides the ability to read information from at least one memory cell or element while writing information in at least one other memory cell coupled to node  220 . READ LINE node  202  may be a global read voltage line which provides the ability to selectively read or receive information stored in at least one memory cell. MODIFY LINE node  204  may be a global write or erase voltage line which provides the ability to selectively communicate information to at least one memory cell and change the state of a memory cell which represents binary values 0 or 1, as desired. 
   A memory cell, part of a memory cell, or a plurality of memory cells may be coupled to any one of nodes  202 ,  204 , or  220 . A low or medium voltage signal on READ LINE node  202  or a high voltage signal applied to MODIFY LINE node  204  may be undesirably disturbed by charge sharing between capacitances C 1    212 , C 2    210 , and C 3    214  when switching between a read or modify operation in at least one memory element. The high voltage signal applied to node  204  may be provided by a high voltage generator, such as circuits  100  and  101 , (shown in  FIGS. 1A and 1B , respectively). 
   Switching between a read or modify operation is provided by switches  206  and  208 , which may be transistors, that are controlled by CTRL signal on node  216 . READ LINE and MODIFY LINE may be bus lines coupled to additional switches for accessing or modifying information in each memory element in a memory device, as desired. Control signal CTRL at node  216  and inverter  218  selectively control switches  206  and  208  such that only one switch is simultaneously opened or closed. Charge sharing is increased when the difference in voltages levels of nodes  202  and  204  are increased, such as when suddenly switching between read and program operations in at least one memory element coupled to node  220 . 
   Purely as an example, charge sharing can cause a positive voltage variation on node  202  when capacitance C 1    212  is discharged to capacitance C 2    210 . A positive voltage disturbance, such as a voltage spike, could damage components coupled to node  202  since the components may be designed to operate at lower voltage levels. Similarly, a negative voltage variation can occur on node  202  by charging capacitance C 1    212  by capacitance C 2    210  which can degrade a read operation performed by other components in the memory device during RWW operation. A negative voltage disturbance on node  204  could degrade programming or erasing performance and speed of a memory device. 
   Supply line voltage disturbances can be reduced and compensated for if substantially equal voltage levels on nodes  202 ,  204 , and  220  are maintained when switching between read or modify operations. The substantially equal voltage levels may be provided by an adaptive voltage generator that maintains the voltage level on node  220  at a predetermined voltage level substantially equal to the READ LINE voltage level, such as 4.5 volts, until switching communication along lines  202 ,  204 , and  220  is completed in at least one memory cell. Once switching is completed, the high voltage level generator may ramp up the voltage level on nodes  204  and  220  to a predetermined high voltage level, such as 15 volts. A similar idle state may be introduced when node  220  is switched from a high voltage level provided by the MODIFY LINE node  204  to a lower voltage level by first discharging capacitances C 1    212  and C 3    214  to a predetermined level prior to switching. 
     FIG. 3  is an illustration of a device  300  for providing a high voltage level in a memory device with idle state regulation to reduce supply line disturbances using two stage switching. A first stage of switches  312  comprises switches  314  and  316 . A second stage of switches  322  comprises switches  324  and  326 . Switches  314 ,  316 ,  324 , and  326  may be transistors or any other devices that perform a switching function. Although only stages  312  and  322  are shown, each memory element in a memory array may have two stages of switches similar to  312  and  322  coupled to any one of READ LINE node  302 , MODIFY LINE node  328 , and node  320 . The control signals, similar to CTRL in  FIG. 2 , for switches  314 ,  316 ,  324 , and  326  are not shown for simplicity. Device  300  may provide functionality for reading or programming at least one memory element, part of a memory element, or a plurality of memory elements coupled to any one of nodes  302 ,  318 , or  320 . 
   During a read operation, switches  314  and  324  are closed with READ LINE node  302 , capacitances C 2    304 , C 1    306 , C 4    308  and node  320  having a predetermined voltage level. Accordingly, switches  316  and  326  are open during a read operation. If a modify operation is desired, an adaptive voltage generator  330  is initiated to an idle state and selectively provides the predetermined voltage level to MODIFY LINE node  328  and line capacitance C 3    310 . An example of the predetermined voltage level is 4.5 volts, although any voltage level may be used. Switch  316  is then closed and switch  314  is opened with generator  330  providing the predetermined voltage level to node  320 . Since the voltage levels at nodes  302  and  328  were substantially equal prior to switches  314  and  316  changing states, no disturbances will occur on the READ and MODIFY lines. The adaptive voltage generator  330  then exits its idle state and raises the MODIFY LINE node  328  to a predetermined high voltage level, such as 15 volts, to modify at least one memory element coupled to node  320 . 
   If a discharge to ground of  320  is needed in any modifying operation with switch  316  and  324  maintained closed (i.e. switch  314  and  326  open), the adaptive voltage generator  330  is lowered to a predetermined lower voltage level. Capacitance C 4    308  and node  320  are then discharged to ground by closing switch  326  and opening switch  324  in order to prevent any voltage disturbances to MODIFY LINE node  328 . After discharging is complete, switch  324  is closed and switch  326  is opened providing the predetermined lower level to node  320  by adaptive voltage generator  330 . Nodes  318  and  320  are then switched to the READ LINE node  302  by closing switch  314  and opening switch  316  without any supply line disturbances. Table 1 shows a summary of a switching cycle for circuit  300 . 
   
     
       
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               STATE 
               Switch 314 
               Switch 316 
               Switch 324 
               Switch 326 
             
             
                 
             
           
           
             
               READ 
               CLOSED 
               OPEN 
               CLOSED 
               OPEN 
             
             
               IDLE/ 
               OPEN 
               CLOSED 
               CLOSED 
               OPEN 
             
             
               MODIFY 
             
             
               MODIFY 
               OPEN 
               CLOSED 
               CLOSED 
               OPEN 
             
             
               IDLE/ 
               OPEN 
               CLOSED 
               OPEN 
               CLOSED 
             
             
               DISCHARGE 
             
             
               IDLE 
               OPEN 
               CLOSED 
               CLOSED 
               OPEN 
             
             
               READ 
               CLOSED 
               OPEN 
               CLOSED 
               OPEN 
             
             
                 
             
           
        
       
     
   
     FIG. 4  is an illustration of an adaptive voltage generator  400  for providing an idle state voltage to MODIFY LINE  328  and node  320 . Charge pump  402  is controlled by regulator  404  and regulator  406 . Regulators are electronic circuits that control the desired output level of charge pump  402 . Regulator  404  controls charge pump  402  to provide a predetermined high voltage level while regulator  406  controls charge pump  402  to provide a predetermined idle state voltage, which is lower than the high voltage level. The output or target node  410  is switched between the high and idle state voltage levels by multiplexer  408  depending on the desired mode of operation of circuit  300 . 
   In comparison to the embodiment shown in  FIG. 4 , the following embodiments have the added advantages of occupying reduced device area and providing enhanced configurability.  FIG. 5A  is an illustration of an adaptive voltage generator  500  for providing an idle state voltage to node  320  with a pulse-skip charge pump regulator. Device  500  comprises charge pump  502 , pulse-skip regulator  504 , comparator  506 , capacitance C load    508 , and multiplexer  510 . The comparator  506 , and any others forthcoming, may be either a voltage sensing comparator or a current sensing comparator or any other circuit element that performs a comparison function, as desired. 
   Multiplexer  510  switches the charge pump  502  from high voltage mode to a lower idle mode voltage depending on the desired mode of operation of circuit  300 . During modify mode, pulse-skip regulator  504  controls charge pump  502  to provide a high voltage level to output or target node  512 . During idle state operation, comparator  506  adjusts node  512  accordingly during clock pulses with control signal  516  by raising or lowering the voltage level of V out  at node  512  to substantially equal reference voltage level V idle  at node  514 . 
     FIG. 5B  is an illustration of an adaptive voltage generator  501  for providing an idle state voltage to node  320  with a linear charge pump regulator. Device  501  comprises charge pump  522 , comparator  524 , linear regulator  526 , p-type metal-oxide semiconductor (PMOS) transistor  528 , and capacitance C load    534 . Comparator  524  compares the voltage level V out  at target node  530  to reference voltage level V idle  at node  532 . During idle state operation, comparator  524  and PMOS transistor adjust node  530  accordingly by raising or lowering the voltage level of V out  to substantially equal reference voltage level V idle . During modify mode, linear regulator  526  controls charge pump  522  to provide a high voltage level to output node  530 . 
     FIG. 6A  is an illustration of an adaptive voltage generator  600  for providing an idle state voltage to node  320  with pulse-skip regulation and disturbance sensitivity. The disturbance sensitivity may be a predetermined sensitivity voltage range of the READ and MODIFY supply lines, as desired. Device  600  comprises charge pump  602 , pulse-skip regulator  604 , comparator  606 , comparator  608 , multiplexer  610 , and load capacitance C load    612 . Multiplexer  610  switches the charge pump  602  from high voltage mode to idle voltage mode depending on the desired mode of operation of circuit  300 . During modify mode, pulse-skip regulator  604  controls charge pump  602  to provide a high voltage level to output or target node  616 . 
   During idle mode operation, comparator  606  compares the output voltage V out  at node  616  to a reference voltage level V idle −δ at node  618 , where delta −δ may be any desired decremental sensitivity value. The value delta δ may also be the maximum allowed supply line voltage disturbance in circuit  300 . If V out &lt;V idle −δ, comparator  606  generates a signal  622  to control charge pump  602  to raise the level of node  616 . Also during idle mode operation, comparator  608  compares the output voltage V out  at node  616  to a reference voltage level V idle +δ at node  620 , where delta +δ may be any desired incremental sensitivity value. If V out &gt;V idle +δ, comparator  608  activates n-type metal-oxide semiconductor (NMOS) transistor  614  to pull down the voltage level of node  616  by coupling it to ground. 
     FIG. 6B  is an illustration of an adaptive voltage generator  601  for providing an idle state voltage to node  320  with linear regulation and disturbance sensitivity. Device  601  comprises charge pump  630 , linear regulator  632 , comparator  634 , comparator  636 , PMOS transistor  638 , NMOS transistor  640 , and load capacitance C load    642 . 
   During idle mode operation, comparator  634  compares the output voltage V out  at node  644  to a reference voltage level V idle −δ at node  646 , where delta −δ may be any desired decremental sensitivity value. If V out &lt;V idle −δ, comparator  634  activates charge pump  630  to raise the level of node  644  by controlling PMOS transistor  638 . Also during idle mode operation, comparator  648  compares the output voltage V out  at node  644  to a reference voltage level V idle +δ at node  648 , where delta +δ may be any desired incremental sensitivity value. If V out &gt;V idle +δ, comparator  636  activates NMOS transistor  640  to pull down the voltage level of node  644  by coupling to ground. During modify mode, linear regulator  632  controls charge pump  630  to provide a high voltage level to output or target node  644 . 
     FIG. 7  is a flow diagram of a process  700  for providing an idle state voltage to a memory device comprising steps  710 ,  720 , . . .  792 . Process  700  illustrates steps for switching from a read to modify mode and then back to a read mode in at least one memory cell. However, it should be appreciated to one skilled in the art that process  700  can begin at step  760  if at least one memory cell is already in modify mode and switch to read mode is desired. In process  700 , a switch to modify mode operation is desired for at least one memory element in a memory device (step  720 ). An adaptive voltage generator is set to output a predetermined idle voltage level to a target node (step  730 ). At least one memory element in the memory device is then switched from a read line to a modify line (step  740 ). The adaptive voltage generator then raises the target node voltage level from the predetermined idle voltage level to a higher predetermined voltage level (step  750 ). 
   Still referring to  FIG. 7 , a switch to read mode may then be desired for at least one memory element, which may be after a certain time period in modify mode (step  760 ). The adaptive voltage generator first lowers its output and the target node to the lower predetermined idle voltage level (step  770 ). Any capacitances coupled to the modify line, if any, are discharged (step  780 ). At least one memory element is then switched from the modify line to the read line (step  790 ). The idle state described in  700  provides better flexibility and robust RWW operation since the read operation on the read line in at least one memory element is not disturbed by the simultaneous write or erase operation on the modify line by at least one other memory element. 
     FIG. 8  is a flow diagram of a process for providing an idle state voltage to any electronic device comprising steps  810 ,  820 , . . .  892 . Process  800  illustrates steps for switching from a first node to a second node and back to the first node in an electronic device. However, it should be appreciated to one skilled in the art that process  800  can begin at step  860  with a circuit element switching from a second node to a first node. In process  800 , switching a circuit element coupled to a first node having a predetermined voltage level to a second node is desired (step  820 ). An adaptive voltage generator provides the predetermined voltage level to the second node prior to switching the circuit element from the first node to the second node (step  830 ). The circuit element may then switch to the second node and couple to the adaptive voltage generator without any voltage disturbances on the first node (step  840 ). An adaptive voltage generator proceeds by raising the second node voltage level to a high voltage level (step  850 ). 
   Still referring to  FIG. 8 , switching the circuit element from the second node to the first node may be desired (step  860 ). The adaptive voltage generator lowers the second node voltage level to the predetermined voltage level (step  870 ). Any capacitances, including parasitic capacitances, on the second node are discharged (step  880 ). The circuit element may then be switched from the second node to the first node without any voltage disturbances on the second node (step  890 ). 
   Although the features and elements of the present invention are described in the preferred embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the preferred embodiments or in various combinations with or without other features and elements of the present invention. The method for switching nodes provided in the present invention may be implemented in a computer program tangibly embodied in a computer-readable storage medium for execution by a processor or a general purpose computer for use with or by any non-volatile memory device. Suitable processors include, by way of example, both general and special purpose processors. 
   Typically, a processor will receive instructions and data from a read only memory (ROM), a RAM, and/or a storage device. Storage devices suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs). Types of hardware components or processors which may be used by or in conjunction with the present invention include Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), microprocessors, or any integrated circuit.

Technology Category: 3