Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority from U.S. Provisional Application Serial Nos. 61/534,787, filed on Sep. 14, 2011 and 61/535,852, filed on Sep. 16, 2011. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates generally to the electrode field, and more specifically to new and useful methods for forming an electrode device with reduced impedance. Such electrode are useful when fabricated into neural electrode assemblies for electrically stimulating body tissue or for recording physiological conditions of the body tissue. 
         [0004]    2. Description of Related Art 
         [0005]    Ideally, conductive electrodes, such as electrodes for sensing and/or stimulation in neural probes, or other neural interface devices, have minimal impedance magnitude and impedance variance (e.g., for an electrode at different times). High impedance generally corresponds with several disadvantages. Sensing and recording electrodes with high impedance typically experience high thermal noise. Stimulation electrodes with high impedance require larger amounts of power during stimulation. Furthermore, a large amount of variance in impedance typically results in poor reliability and predictability during both sensing and stimulation modes of operation. 
         [0006]    Increasing the geometric surface area or “footprint” of an electrode is one technique to reduce impedance magnitude and variance, but that approach reduces the electrode&#39;s spatial resolution. Increasing the electrochemical surface area of an electrode is another technique for reducing impedance magnitude and variance, but at significant cost and resources. Current methods, such as electrodeposition or electroplating, for increasing a neural electrode&#39;s electrochemical surface area are often performed post-process on individual devices after microfabrication and, therefore, are relatively expensive. Electrodeposition can also be performed in batch processes, but this usually has issues with uniformity and repeatability. Also, reliability issues, such as changes in the charge carrying capacity over time or delamination between the modified electrode material and the underlying substrate, can be a concern. 
         [0007]    Thus, there is a need in the electrode field to create a new and useful method for reducing the impedance of a neural electrode device. The present invention provides such new and useful methods for manufacturing electrode device, particularly those that are adapted for useful in neural interface applications. 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention relates to improved low-cost, highly reliable methods for increasing the electrochemical surface area of neural electrodes. In particular, the invention relates to the deposition of a mono-layer of polymeric nanospheres on a dielectric substrate. The nanospheres self-assemble into generally repeating lattice forms with interstitial space between them. In one embodiment, the metallization material that is left exposed between adjacent nanospheres is etched. Etching is only part-way through the thickness of the metallization. In another embodiment, metallization material that are suitable for subsequent use as electrode in neural probes, and the like, are deposited on the dielectric substrate, filling in the interstitial space between the arrayed nanospheres. The deposited metallization material builds into pyramidal-type structures that are shaped by the size of the nanospheres and the interstitial spacing between them. The nanospheres are then removed leaving behind the shaped metallization deposits of relatively high surface area. Such metallization deposits help to minimize impedance magnitude and impedance variance from one electrode to the next. 
         [0009]    A further improvement is to deposit alternating layers of metals into the interstitial space between the nanospheres. One of the metals, for example gold, is more readily etched than the other, for example platinum or iridium. The gold layers are then selectively etched to expose additional platinum surface area that was previously covered by the gold. This additional surface area is that which previously had gold both immediately above and below it 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The present invention will be described by reference to the following drawings, in which like numerals refer to like elements, and in which: 
           [0011]      FIG. 1  is a perspective view of a neural interface system  10  according to the present invention. 
           [0012]      FIG. 2  is a schematic drawing showing a metallization layer  22  supported on a dielectric substrate  16  supported on a release layer  18  and a carrier layer  20  for forming an electrode  14 A,  14 B according to one embodiment of the present invention. 
           [0013]      FIG. 3  is a schematic drawing showing a plurality of metallization layers  22 A to  22 E that are the result of etching the metallization layer  22  shown in  FIG. 2A  or after the mask layers  24 A to  24 F have been removed from  FIG. 2C . 
           [0014]      FIG. 4  is a schematic drawing showing deposition of a mono-layer of nanospheres  26  being deposited on the metallizations  22 A to  22 E of  FIG. 3 . 
           [0015]      FIGS. 5 ,  5 A and  5 A′ are schematic drawings showing a method according to the present invention where undulations are formed in the metallizations  22 A to  22 E by etching recesses  30  into their thicknesses. 
           [0016]      FIG. 6 ,  6 A and  6 A′ are schematic drawings showing a method according to the present invention where undulations are formed by depositing metallization material  32  onto the metallizations  22 A to  22 E. 
           [0017]      FIG. 7A  is a schematic showing deposition of metallization material  32  between adjacent nanospheres  26 . 
           [0018]      FIG. 7B  is a partial photographic image of an exemplary electrode resulting from the method of the present invention depicted in  FIGS. 6 ,  6 A and  6 A′. 
           [0019]      FIG. 8  is a schematic of nanosphere packing and calculation of increased electrochemical surface area resulting from the methods of the present invention. 
           [0020]      FIG. 9  is a table of results from one example of the method of the present invention. 
           [0021]      FIG. 10A  are a flow chart of the steps used to increase the effective surface area of deposited platinum layers  40  by etching an intermediate gold layer  42 . 
           [0022]      FIG. 10B  is a schematic drawing showing e steps described in the flowchart of  FIG. 10A . 
           [0023]      FIG. 11A  are a flow chart of the steps used to increase the effective surface area of deposited platinum layers  40  by etching an intermediate gold layer  42  in a deposition profile of Pt/Au/Pt/Au/Pt. 
           [0024]      FIG. 11B  is a schematic drawing showing the steps described in the flowchart of  FIG. 11A . 
       
    
    
       [0025]    The present invention will be described in connection with a preferred embodiments, however, it should be understood that there is no intent to limit the invention to the embodiment described. On the contrary, the intent is to cover all alternatives, modifications, and equivalents as may be included within the scope of the invention as defined by the appended claims. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    The present methods described herein are primarily referenced to forming a single electrode device, and in particular a neural electrode device. However, it should be understood that the present methods can be configured to form a plurality of electrode devices that are suitable for medical sensing or stimulation applications. In a preferred embodiment, the present methods can be adapted to manufacture an electrode that is suitable for any electrical stimulation technology and any recording or sensing technology having conductive electrodes, such as electrodes that are useful in physiological solutions. In that light, the methods described herein are readily adaptable to scaling to batch processes for forming a plurality of electrode devices with reduced impedance at relatively low cost and high uniformity from one electrode to the next. 
         [0027]    Turning now to the drawings,  FIG. 1  illustrates a neural interface system  10  according to the present invention. The neural interface system  10  comprises an electrode array  12  having a plurality of electrode sites  14 A and  14 B. The electrodes may be adapted to optimally sample (record)  14 A or selectively activate (stimulate)  14 B neural populations and may be individually or simultaneously activatable to create an activation pattern. The neural interface system  10  may further include a pre-molded component  15  onto which the neural interface array is attached or assembled that supports the electrode array  12 . The electrode array  12  is coupled to the pre-molded component  15  such that the electrodes  14 A,  14 B are arranged both circumferentially around and axially there along. Alternatively the electrode array  12  may be kept in its original planar form and attached to another planar component for mechanical support. The neural interface system  10  of the present invention is preferably designed for deep brain stimulation and, more specifically, for deep brain stimulation with fine electrode site positioning, selectivity, tunability, and precise activation patterning. The neural interface system  10 , however, may be alternatively used in any suitable environment (such as the spinal cord, peripheral nerve, muscle, or any other suitable anatomical location) and for any suitable reason. 
         [0028]    Methods for building the electrode array  12  comprising the electrodes  14 A,  14 B formed from shaped metallizations with reduced impedance will now be described. 
         [0029]      FIG. 2  shows the dielectric substrate  16  contacting a release layer  18  that is directly supported on a carrier  20 . The dielectric layer  16  can be of a flexible thin material, preferably parylene, polyimide, silicone, or even a thin-film of silicon, or some combination of organic and inorganic dielectrics, but may alternatively be of any suitable material. 
         [0030]    The carrier  20  is preferably made of glass or silicon, but may alternatively be made from any other suitable material. The carrier  20  is may be flexible, rigid, or semi rigid depending on the microfabrication tooling (organic electronics equipment can increasingly use flexible substrates without a carrier layer such as in roll-to-roll manufacturing, whereas IC and MEMS microfabrication equipment use a rigid silicon carrier). A rigid carrier layer  20  has a thickness ranging from about 200 microns to about 925 microns, preferably greater than 500 microns. 
         [0031]    A metallization layer  22  in  FIG. 2  is deposited on the upper or outer surface  16 A of the dielectric substrate  16 . The metallization  22  is shown as a continuous layer and can be patterned using any suitable wet etch or dry etch wherein the mask is a photodefined resist or any other masking material patterned directly or indirectly using standard photolithography techniques having a perimeter extending from a lower metallization surface supported on the upper substrate surface  16 A to an upper metallization surface spaced from the lower metallization surface by a thickness of the perimeter. The metallizations  22  can be deposited using any suitable thin film, semiconductor, microelectromechanical systems (MEMS) manufacturing technique or other microfabrication process, such as physical vapor deposition. Exemplary techniques and processes include evaporation and sputtering deposition. The metallizations layer  22  preferably includes a conductive material such as of gold (Au), platinum (Pt) or platinum-iridium, iridium  oxide, titanium nitride, or any other metal, metal oxide, or conductive polymer having suitable electrically conductive properties. 
         [0032]      FIG. 3  shows where the continuous metallization  22  has been patterned into a plurality of discrete metallization structures  22 A,  22 B,  22 C,  22 D,  22 E, etc. The metallization layer  22  can be patterned through etching, liftoff deposition (not shown), or any other suitable thin film, semiconductor manufacturing, MEMS manufacturing, or other microfabrication process. 
         [0033]    Depending on the particular application for the finished neural interface system  10 , the dielectric substrate  16 , the release layer  18  and the carrier  20  can be flexible, semi-flexible, or rigid. The present method can further include patterning the metallization structures  22 A,  22 B,  22 C,  22 D,  22 E, etc. to include conductive traces, bond pads, and other suitable conductive elements. 
         [0034]    In  FIG. 4 , a layer of nanospheres  26  has been deposited onto the dielectric substrate  16  to cover both the shaped metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. and the substrate surface  16 A between adjacent metallizations. The nanospheres  26  form a high-density, high-resolution spatial pattern serving as a substantially uniform mask or template over the surface of the individual metallizations. That is because the nanospheres  26  are substantially identical in size and shape. When they are deposited in a monolayer onto the metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc., the nanospheres  26  self-assemble into a tightly packed, uniform pattern. 
         [0035]    For example, the present method can include depositing a monolayer of nanospheres  26  onto the metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. by drop wetting (direct application of the nanospheres in solution) and then allowing them to self-assemble into hexagonally packed patterns ( FIG. 8 ) upon de-wetting. This embodiment includes depositing a nanosphere solution including nanospheres and a solvent onto the metallization structures  22 A,  22 B,  22 C,  22 D,  22 E, etc. The solvent is then evaporated. The solvent is preferably selected based on its viscosity, evaporation rate, and wettability on the metallizations patterned on the dielectric substrate  16 . 
         [0036]    In one illustrative example, the solution includes polystyrene spheres mixed in a solvent of ethanol and de-ionized water. The ratio of ethanol to de-ionized water is approximately 4:1. However, the solution can include nanospheres  26  other than those of polystyrene, such as glass, and a suitable solvent other than a mixture of ethanol and de-ionized water. The solution is preferably dropped onto the dielectric substrate  16  such that a monolayer of nanospheres  26  is distributed substantially uniformly on the metallization structures  22 A,  22 B,  22 C,  22 D,  22 E, etc. 
         [0037]    Depositing the nanosphere solution may be performed by using the Langmuir-Blodgett technique to transfer a pre-fabricated monolayer of nanospheres  26  onto the metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. patterned on the dielectric substrate  16 . In an example, nanospheres  26  having a surface tension of γ -NS  are in a solvent having a surface tension of γ-solvent. It is given that γ-NS is less than γ-solvent. Then, a monolayer of nanospheres  26  forms at the exposed surface of metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. patterned on the dielectric substrate  16 . The substrate  16  supported on the carrier  20  can be moved through the solution to transfer the monolayer of the nanospheres  26  thereto. 
         [0038]    Illustratively, one can use the drop wetting method by mixing a nanosphere solution (e.g., 5% w/v solution) into a 4:1 volume mixture of ethanol to de-ionized water. When applied to a patterned dielectric substrate  16  at room temperature on a horizontal surface, the nanospheres  26  will self-assemble along a contact line during the evaporation or de-wetting process. 
         [0039]    Evaporation of the solvent can occur unassisted or be accelerated with environmental changes, such as in temperature and pressure from that of an ambient atmosphere. 
         [0040]    A second preferred embodiment is where the nanospheres  26  are deposited onto the metallization structures  22 A,  22 B,  22 C,  22 D,  22 E, etc. via spin-coating the above described nanosphere solution. If desired, the nanosphere solution can have a different viscosity, wettability, or other mixture ratio than that used with the drop-wetting or Langmuir-Elodgett technique. Furthermore, depending on the nature of the nanosphere solution, spin-coating can include a particular rate of spinning and/or acceleration. 
         [0041]    According to the present invention, a series of recessed undulations  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc. or upstanding undulations  22 A″,  22 B″,  22 C″,  22 D″,  22 E″, etc. are formed on the surface of the metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. The recessed or upstanding undulations can be approximately pyramidal wave undulations, square wave undulations, approximately triangular wave undulations, or an undulation of any other suitable shape. 
         [0042]      FIGS. 5 ,  5 A and  5 A′ show recessed undulations  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc. that have been formed by etching  28  recesses  30  into the thickness of the respective metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. Etching  28  the recesses  30  into the metallizations takes place beneath the interstitial spaces of the layer of assembled nanospheres  26 . The result is undulations  22 A″,  22 B″,  22 C″,  22 D″,  22 E″, etc. comprising recesses extending into the original thickness or height (h) of the metallization layers supported on the substrate  16 . 
         [0043]    For etching, it is preferred that the nanospheres  26  a diameter ranging from about 20 nanometer (nm) to about 1,000 nm. Etching can be performed with any suitable etching process. One advantage of etching is that it does not require any adhesion between the existing metallization layer and newly deposited conductive material. Platinum, for example, is a commonly used biocompatible metal that can be dry etched using techniques described in U.S. Pat. No. 6,323,132 with a reactive ion etcher. The contents of this patent are incorporated herein by reference. 
         [0044]    In that manner, etching forms the recesses  30  having a depth extending part-way through the thickness of the metallization  22 B from that portion of its upper surface of the metallization not contacted or otherwise covered by a nanosphere  26 . The recesses  30  can extend from about 1% to about 99% into the thickness of the metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. More preferably, the recesses are from about 50% to about 90% into the original metallization thickness. The metallizations shown in  FIG. 5A  have a thickness measured from the upper surface  16 A of the dielectric  18  to the upper surface of the as-deposited metallization of from about 0.25 micron to about 20 microns, more preferably from about 10 microns to about 20 microns. 
         [0045]      FIGS. 6 ,  6 A and  6 A′ relate to an alternative method where the upstanding undulations  22 A″,  22 B″,  22 C″,  22 D″,  22 E″, etc. are formed by depositing  30  additional metallization material (e.g., in a lift-off deposition) onto the metallizations  22 A,  225 ,  22 C,  22 D,  22 E, etc. through the interstitial spaces between the nanospheres  26 . Deposition  30  continues until the desired height of the added metallization material  32  measured from its base  32 A supported on the upper surface of the original metallization  22 B is achieved. For this technique, it is preferred that that the nanospheres have a diameter ranging from about 500 nm to about 5,000 nm. 
         [0046]    One advantage of this variation is that depositing material preferably results in metal-metal bonds and predictable surface properties.  FIG. 7A  illustrates a representative one of the undulations where the additional metallization material  32  forms a base on the upper surface of the metallization  22 B and build-up in a pyramidal manner. That is without contacting the adjacent nanospheres  26 , but while following their generally circular contour. In that respect, the height of the upstanding undulations is preferably about 90% of the radius of the nanosphere. It has been discovered that this ratio provides maximum. added surface area for the added metallization. That means the upstanding additional or secondary metallization material has a height ranging from about 225 nm to about 2,250 nm above the upper surface of the primary metallization  22 . 
         [0047]    Moreover, the added metallization does not grow so high as to prevent the subsequent removal of the nanospheres. In order for nanosphere removal, it is important that the added metallization not extend past the imaginary equator and over the upper half of the hemisphere. With this rule, it has been determined that approximately a. four-fold increase in the geometric surface area (GSA) is achievable. 
         [0048]      FIG. 7B  is a photograph showing how the deposited metallization material builds up from the upper surface of a metallization without contacting the nanospheres  26 . The nanospheres  26  have been removed in the photograph, but the generally circular shape of one of them is delineated by the circle bordered by the deposited metallization material, which is seen as the off-white pyramidal bodies having somewhat triangular bases. 
         [0049]    In both embodiments, the recessed undulations  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc and extending  22 A″,  22 B″,  22 C″,  22 D″,  22 E″, etc on the respective metallizations are preferably bounded by the interstitial spaces of the nanospheres  26 . Since the nanospheres  26  are substantially uniform in shape and arranged in a substantially uniform distribution in the layers of  FIGS. 5 and 6  supported on the upper surface of the metallization  22 A,  22 B,  22 C,  22 D,  22 E, etc., there is a substantially uniform distribution of interstitial spaces between the nanospheres  26 . Consequently, the undulations  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc. and  22 A″,  22 B″,  22 C″,  22 D″,  22 E”, etc. are substantially uniformly distributed throughout the surface area of the shaped metallization. 
         [0050]    If desired, the nanospheres  26  are removed from the dielectric substrate  18  after forming recessed or extending the undulations  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc. and  22 A″,  22 B″,  22 C″,  22 D″,  22 E″, etc. on the respective metallizations  22 A,  22 B,  22 C,  22 D,  22 E, etc. or, the nanospheres  26  can be left on the metallizations. 
         [0051]    The undulations  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc and  22 A″,  22 B″,  22 C″,  22 D″,  22 E″, etc significantly increase the electrochemical surface area (ESA) of the electrode, particularly relative to the geometric surface area (GSA) of an electrode formed from one of the metallization according to the present invention. The interstitial spaces of the nanospheres (or “pores” of the layers of the nanospheres) are preferably arranged in a. substantially uniform distribution, thereby enabling substantially uniform arrangement of the undulations. 
         [0052]    The particular form of the undulation, whether they be of the recessed or the extending form (etching or deposition) of the metallizations depends on the functional application of the electrode that will be manufactured from the metallization device, desired dimensions of the electrode, extensions, and/or recesses, materials within the metallization, and/or any suitable factor. In any event, the undulating surface provides an increased ESA predicated on the diameter and packing arrangement of the nanospheres  26 , and the depth of recess  30  for the recessed undulation  22 A′,  22 B′,  22 C′,  22 D′,  22 E′, etc. or the increased thickness of the deposited metallization material  32  for the extending undulations  22 A″,  22 B″,  22 C″,  22 D″,  22 E″ etc. 
         [0053]    As shown in  FIG. 8 , the amount that the ESA increases as is inversely proportional to the diameter of the sphere: 
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         [0000]    where A inc =additional area additional area created inside the fundamental unit of the equilateral triangle formed by 3 adjacent spheres when hexagonally packed, D s =diameter of a sphere, d m =height of deposition or the depth of etch, and A e =geometric area of electrode (derived from the metallizations  22 ). Estimated area change in various illustrative examples of etched metallization electrode sites ( FIGS. 5 ,  5 A and  5 A′) are shown in Table 1 of  FIG. 9 . 
         [0054]    In some preferred embodiments, the present invention methods additionally or alternatively include one or more of several variations described below. 
         [0055]    As shown in  FIGS. 10A and 10B , a further surface area increase can be achieved according to the present invention by undercutting one or more alternating layers of patterned metal. In one version of this embodiment, the method includes: depositing a planar metallization layer stack (e.g., Au/Pt, Au/Ir, or other Au stack) onto the dielectric substrate  16 , and then selectively wet etching the Au metal. 
         [0056]    An example of this is to deposit a layer of platinum  40  onto the dielectric layer (not shown in  FIG. 10B ) using one of the methods previously described with respect to  FIGS. 3 and 4 . Without removing the nanospheres  26 , a layer of gold  42  is deposited on top of the platinum  40  followed by a second layer of platinum. The nanospheres  26  and the underlying photoresist pattern  24  are then removed and the gold  42  is wet etched. Etching serves to expose additional surface area of the platinum  40  that was previously positioned both above and below the gold. This is shown by the exposed surface  42 A of the platinum layers  42  in  FIG. 10B . 
         [0057]    It is important to not etch too much of the gold  42  so that it can no longer act as a structural support for the platinum.  40 . In  FIG. 10B , the depth of etch is depicted as d Au , which is less than the original thickness of the gold layer measured parallel to the plane of the dielectric substrate  16 . In addition to platinum, iridium, iridium oxide, and titanium nitride are suitable metallization materials for use with this gold etching process. In that manner, gold etching serves to expose more of the non-Au metal surface area. 
         [0058]      FIGS. 11A and 11B  relate to another embodiment of the method according to the present invention. This embodiment additionally or alternatively includes depositing an alternating combination of layers on the dielectric substrate (not shown in  FIG. 11B ). In one specific embodiment alternating layer of platinum  40  and gold  42  are deposited one on top of the other until a stack of a desired height is achieved. In a similar manner as described above with respect to  FIGS. 10A and 10B , the gold layers are wet etched to undercut and expose addition platinum surface area. As described above, it is important not to etch too much of the gold  42 . In  FIG. 11B , the depth of etch is depicted as d Au , which is less than the original thickness of the gold layer measured parallel to the plane of the dielectric substrate  16 . Enough gold must be left to serve as a structural pillar supporting the above platinum and gold layers. An example of this embodiment is alternating layers of Au/Pt/Au/Pt/Au/Pt stacked one on top of the other. Gold. etching preferably forms more ESA. 
         [0059]    Although omitted for clarity, the preferred embodiments of the present methods include every combination and permutation of the various processes described above. Furthermore, the preferred embodiments of the present method can be executed by a computer program or other system including computer program code for controlling hardware (e.g., machines for deposition, sputtering) in an automated fashion. 
         [0000]    Neural Interface Device with Reduced Impedance 
         [0060]    As previously discussed with respect to  FIG. 1 , a neural interface device  10  with reduced impedance according to the present invention includes the dielectric substrate  16  supporting the electrode array  12  comprising the plurality of electrodes  14 A,  14 B. After the metallization material  22  has been provided with an undulating surface characteristic, whether the undulations are recessed or upstanding the neural array is further completed with the addition of top dielectric, bond pads if necessary, vias, and other desired features (none of these are shown here). Finally the neural array including the dielectric substrate  16  is removed from the carrier  20 . The release layer  18  facilitates this separation in some cases but not always required especially if the dielectric substrate  16  only has weak bonding to the carrier  18 . The dielectric substrates (top and bottom) and the electrode array  12  are then formed into a desired shape of the neural interface system  10 , which can be either planar or three-dimensional such as the cylindrical shape shown. The neural interface device  10  can be a planar probe with the electrode array  12 , a cylindrical probe with the electrode array, a substantially planar or curved substrate with the electrode array, or any suitable electrode device. 
         [0061]    At least a portion of each electrode  14 A,  14 B has a substantially uniform undulating surface described above. At least a portion. of the substantially uniform undulating surfaces of the electrodes  14 A,  14 B includes peaks and/or crevices (e.g., recesses) that are preferably distributed in a regular arrangement and, more preferably, in an approximately hexagonal arrangement as shown in  FIGS. 5A ,  5 A′,  6 A and  6 A′. The undulating surfaces increases the electrochemical surface area of the electrodes  14 A,  14 B, thereby reducing their impedance and improving their functionality for stimulation and sensing purposes. 
         [0062]    While this invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variations that fall within the broad scope of the appended claims.

Technology Category: 1