Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to the field of bandgap voltage references. 
         [0003]    2. Prior Art 
         [0004]    Low noise bandgap references have long been a goal of the industry and have been written about often in the technical journals. 
         [0005]    It is well known that a bandgap reference is generated by adding two voltages together, a bipolar transistor Vbe and a delta Vbe. The Vbe has a negative TC and the delta Vbe has a positive TC. When these voltages are added together and their sum is equal to the bandgap voltage, approximately 1.2V, the TC of the sum of the voltages is close to zero. 
         [0006]    Since the Vbe is usually close to 600 mV, this means that the delta Vbe must also be in the order of 600 mV. This 600 mV of delta Vbe is hard to generate with a single pair of transistors because it would take very big transistor ratios to do it. Most bandgap references use an amplifier to gain up these transistor ratios. For example, if you have a 10 A to A transistor emitter area ratio (60 mV) you would use an amplifier with a gain of ˜10 to get to 600 mV so you could add this to a 600 mV Vbe to get to the bandgap voltage of 1.2V. This works very well, but the problem with this approach is that the noise is also gained up by 10, which in some cases is undesirable. 
         [0007]    A few papers have been written (“Low Noise Bandgap Reference Using Multiple Delta Vbe” by Petr Kadanka, for example) which shows that by using multiple connections of bipolar devices to multiply up the delta Vbe and then gain up the result the noise will be lower. For example, if you can connect two  10 A to A devices and then another  10 A to A device you would have 120 mV of delta Vbe and a gain of only 5 would be necessary to achieve the ˜600 mV. The noise will be lower in this case. This is what is also done in the “stacked bandgap references that use about 1.2V of Vbe and 1.2V of delta Vbe to get an output voltage of −2.4V. One of the problems here is that as you stack devices, you may run out of headroom voltage, which is not desirable for low voltage operation. 
         [0008]    A particularly well known bandgap reference is commonly referred to as the Brokaw bandgap reference.  FIG. 1  presents the circuit diagram of the basic Brokaw bandgap reference. This Figure shows the basic circuit of the reference. In this circuit, resistors R 1  and R 2  are equal resistors, while the emitter of transistor T 1  is much larger than the emitter of transistor T 2 . The inputs of amplifier A are connected to resistors R 1  and R 2 . The output of amplifier A is the reference voltage V ref , which is also coupled to the bases transistors T 1  and T 2 . Thus the output of the amplifier A seeks a voltage output V ref  such that the collector voltages for transistors T 1  and T 2  and equal, i.e., so that the voltages across and current through the two resistors R 1  and R 2  are equal. However the transistors T 1  and T 2  are not of equal size, with transistor T 1  being much larger than transistor T 2 , typically on the order of ten times the size of transistor T 2 . Thus, while the currents in the two transistors are equal, transistor T 1  has a lower base emitter voltage because of its lower current density than transistor T 2 . Since the bases of transistors T 1  and T 2  are both coupled to the output voltage V ref , the difference in their base emitter voltages appears across resistor R 3 . Thus the current through resistor R 3  is equal to the difference in base emitter voltages between transistor T 2  and transistor T 1  divided by the resistance of resistor R 3 . Also since resistors R 1  and R 2  are equal, the currents through resistors R 1  and R 2  and transistors T 1  and T 2  are made equal by the feedback of the output of amplifier A, the current through resistor R 4  is twice the current through resistor R 3 . From the Ebers-Moll model of a transistor, the difference in base emitter voltages of two transistors (pn junctions) operating at different current densities has a positive temperature coefficient, whereas the base emitter voltage (pn junction) of a single transistor has a negative temperature coefficient. Because the current through resistor R 3  has a positive temperature coefficient (PIAT) and the current through transistor T 2  is equal to the current through resistor R 3 , the voltage across resistor R 4  also has a positive temperature coefficient (PIAT). Consequently, tracing from the ground connection through resistor R 4  and the emitter-base voltage of transistor T 2 , it may be seen that the output voltage V ref  is the sum of the PIAT voltage across resistor R 4  and the negative temperature coefficient voltage (CTAT) from the emitter to the base of transistor T 2 . By appropriate selection of component values, the output voltage V ref  can be made equal to the bandgap voltage of the semiconductor material (silicon) with very little temperature sensitivity or power supply sensitivity in the output voltage V ref . 
         [0009]    A Brokaw bandgap reference may also be realized by using transistors T 1  and T 2  of the same emitter area but with unequal resistors R 1  and R 2 . Similarly, circuits are also known which use pn junction diodes as opposed to transistors and/or which use three devices, two to generate the PIAT voltage (the difference in voltage across two pn junctions operating with different current densities) and a third device for providing the negative temperature coefficient of a pn junction. 
         [0010]    Numerous variations and improvements have been made in the basic Brokaw bandgap reference. These variations and improvements include techniques for curvature correction to reduce the remaining temperature sensitivity, to broaden the temperature range over which a given temperature sensitivity is achieved, to reduce noise and to achieve similar voltage references using field effect devices. See for instance U.S. Pat. Nos. 5,051,686, 5,619,163, 6,462,526, 6,563,370, 6,765,431 and 7,301,389, all assigned to the assignee of the present invention. 
         [0011]    In a Brokaw bandgap reference, the difference in pn junction voltages (base-emitter voltages of transistors T 1  and T 2  in  FIG. 1 ) operating at different current densities is typically on the order of one-tenth the voltage needed to add to the negative temperature coefficient pn junction voltage to provide the desired temperature insensitive bandgap voltage of approximately 1.23 volts. To be more specific, typically the difference in voltage of two pn junctions operating at different current densities is on the order of 60 millivolts (depending on the current density ratio) while the pn junction voltage is on the order of 600 millivolts. Accordingly, the difference in the pn junction voltages of the two pn junctions operating at different current densities must be voltage amplified by approximately 10 to 1, which in turn amplifies the noise generated by the two transistors. Consequently, while Brokaw type bandgap references still find wide application, there is an increasing need for bandgap references of improved performance, particularly having substantially reduced output noise. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a circuit drawing for a prior art Brokaw bandgap reference. 
           [0013]      FIG. 2  is a circuit drawing for an Xpl loop used in bandgap references in accordance with the present invention. 
           [0014]      FIG. 3  illustrates a cascading of multiple Xp 1  loops, each in accordance with  FIG. 2 . 
           [0015]      FIGS. 4-1  and  4 - 2  provide a diagram of an exemplary one bandgap voltage reference using the cascading of multiple Xp 1  loops as in  FIG. 3 . 
           [0016]      FIG. 5  is a circuit diagram of one embodiment of a summing amplifier for summing a VBE (QN 5 ) with the PTAT output voltage of the cascaded Xp 1  loops, all in accordance with the embodiment of  FIGS. 4-1  and  4 - 2 . 
           [0017]      FIGS. 6-1  through  6 - 3  provide a diagram of an exemplary two bandgap voltage reference using the cascading of a greater number of Xp 1  loops. 
           [0018]      FIGS. 7-1  and  7 - 2  provide a diagram similar to that of  FIGS. 4-1  and  4 - 2 , but using active current sources instead of resistors at each Xp 1  loop and summing amplifier output. 
           [0019]      FIGS. 8-1  through  8 - 3  provide a diagram of an exemplary two bandgap voltage reference using the cascading of a greater number of Xp 1  loops, but using active current sources instead of resistors at each Xp 1  loop output. 
           [0020]      FIG. 9  is a Figure similar to  FIG. 3 , but using diodes (diode connected transistors for both transistors QN 2  and QN 3 . 
           [0021]      FIGS. 10-1  and  10 - 2  provide a diagram similar to that of  FIGS. 4-1  and  4 - 2 , but using two diodes (diode connected transistors) in each Xp 1  loop. 
           [0022]      FIGS. 11-1  through  11 - 3  provide a diagram similar to that of  FIGS. 6-1  through  6 - 3 , but using two diodes (diode connected transistors) in each Xp 1  loop. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    Now referring to  FIG. 2 , a building block of the present invention may be seen. The circuit shown shall be referred to herein as an Xp 1  loop comprising four bipolar transistors of the same conductivity type, namely in this embodiment, NPN transistors QN 1 , QN 2 , QN 3  and QN 4 . In a preferred embodiment, transistors QN 1  and QN 2  are matched transistors, each having an emitter area A, with transistors QN 3  and QN 4  also being matched transistors each having an emitter area NA, i.e., each having an emitter area that is N times the emitter area of each of transistors QN 1  and QN 2 . In the circuit shown, a current IB is applied to the collector and base of transistor QN 3 , which passes through transistor QN 1  and through R 2 . The voltage across resistor R 2  is labeled VIN for reasons which will subsequently become apparent. Also a voltage VB is applied to the collector of transistor QN 2 , which provides current through transistors QN 2  and QN 4  and resistor R 3 .  FIG. 2  shows the common connection of the emitter of transistor QN 3  and the collector of QN 1  is connected to the base of transistor QN 4 , and the common connection of the emitter of transistor QN 2  and the collector of transistor QN 4  is connected to the base of transistor QN 1 . 
         [0024]    With the connections shown in  FIG. 2 , starting at voltage VIN, the voltage of node  1  is equal to the voltage VIN plus the base emitter voltage of transistor QN 1  plus the base emitter voltage of transistor QN 2 , with the voltage VOUT being equal to the voltage at node  1  minus the base emitter voltage of transistor QN 3  minus the base emitter voltage of transistor QN 4 . Thus in equation form, the output voltage VOUT can be written as follows: 
         [0000]    
       
      
       VOUT=VIN+VBE 
       QN1 
       +VBE 
       QN2 
       −VBE 
       QN3 
       −VBE 
       QN4  
      
     
         [0025]    This may be rearranged as follows: 
         [0000]        VOUT=VIN+ ( VBE   QN1   −VBE   QN3 )+( VBE   QN2   −VBE   QN4 ) VOUT=VIN+ 2 ΔVBE    
         [0026]    Assuming for the moment that the base currents in the four transistors QN 1 -QN 4  are relatively negligible, the voltage term VBE QN1 -VBE QN3  represents the difference in base emitter voltages (ΔVBE) between two transistors operating with the same collector current (IB), but with different current densities because of their different emitter areas. Similarly, the voltage term VBE QN2 -VBE QN4  also represents the difference in base emitter voltages (ΔVBE) between two transistors operating with the same collector current, but with different current densities because of their different emitter areas. Assuming the emitter area ratio N is the same for transistors QN 2  and QN 4  and for transistors QN 1  and QN 3 , VOUT can be expressed as: 
         [0000]        VOUT=VIN+ (2 kT/Q ) ln ( N ) 
         [0000]    where:
       T=absolute temperature   k=Boltzmann constant   Q=the electrical charge on an electron       
 
         [0030]    Thus each of these AVBE voltages is a PTAT voltage suitable for use as a PIAT voltage in a bandgap reference. 
         [0031]    In particular, assume for the moment that R 2  is zero so that VIN is at ground potential. The voltage VOUT will be a PTAT voltage 2ΔVBE increments above ground potential. The circuit of  FIG. 2  may be cascaded with additional Xp 1  PTAT voltage circuits, also in accordance with  FIG. 2 , as shown in  FIG. 3 . As shown therein, the output VOUT ( FIG. 2 ) for the first Xp 1  loop forms what will be the input voltage VIN for the second Xp 1  loop, with the 2ΔVBE voltage generated by the second Xp 1  loop being added to the 2ΔVBE PTAT voltage generated by the first Xp 1  circuit. Thus in the circuit of  FIG. 3 , the output voltage of the first Xp 1  loop will be equal to the PTAT voltage 2ΔVBE. The current through R 2 , namely the desired current through transistors QN 2  and QN 4  of the first Xp 1  loop plus the bias current IB through the transistors QN 3  and QN 1  of the second Xp 1  loop, will be equal to the PTAT voltage 2ΔVBE divided by the resistance of resistor R 2 . Thus resistor R 2  acts as a current source equal to 2ΔVBE/R 2 , and resistors R 3  and R 4 , and corresponding resistors in other embodiments described herein, act as current sources, and may be replaced by active current sources if desired. Similarly, current is pulled from the voltage source VB, in that the current supplied by each connection to VB is the current required to provide the PTAT voltage drop across the respective resistor (or current for the current source used in place of the respective resistor) connected to the respective emitter of transistor QN 4 . In that regard, in the preferred embodiment, all Xp 1  loops have the same bias current, with the currents through transistors QN 2  and QN 4  equal to the currents through transistors QN 3  and QN 1 , in a preferred embodiment both currents being on the order of 4 microamps. 
         [0032]    Note that any noise on the voltage VB or in the bias current IB does not substantially change the PTAT voltages generated or their temperature sensitivity, as the PTAT voltages are only sensitive to the difference in current densities in the two series connected pairs of transistors, and is essentially independent of the magnitude of the current (IB) itself. These small current variations have little effect on the cumulative PTAT voltage VOUT that is obtained by cascading Xp 1  loops as shown in  FIG. 3 . Thus the PTAT voltage VOUT of  FIG. 3  is substantially immune to noise in the bias currents IB of the cascaded Xp 1  loops due to the cross coupled nature of each Xp 1  loop. Consequently, substantially the only noise on the output voltages VOUT is the noise generated within the four transistor Xp 1  circuits themselves. Since this noise is not correlated between Xp 1  loops, the output noise VOUT of the final Xp 1  loop in a cascaded series of Xp 1  circuits is equal to the square root of the sum of the squares of the noise in each Xp 1  loop, not the noise of one Xp 1  loop times the number of Xp 1  loops cascaded. Thus not only is each Xp 1  loop substantially immune to the bias current noise, but the noise in one Xp 1  loop does not linearly add like the PTAT AVBE voltage itself does when multiple loops are cascaded. 
         [0033]    Now referring to  FIG. 3  again, three cascaded Xp 1  loops are shown. In the first loop, the emitter of transistor QN 1  is connected to ground so that the emitter of transistor QN 4  will be at a voltage of 2ΔVBE above ground. Since this voltage is essentially clamped by the first Xp 1  loop, the value of resistor R 2  will determine the current through transistors QN 2  and QN 4 . In particular, assuming the same currents are desired through transistors QN 2  and QN 4  as through transistors QN 3  and QN 1  so that each Xp 1  loop is to have the same current bias, resistor R 2  would be selected to conduct twice that current bias, i.e. the current through transistors QN 2  and QN 4  of the first Xp 1  loop plus the current though transistors QN 3  and QN 1  of the second Xp 1  loop ( 2 IB), with a voltage across resistor R 2  of 2ΔVBE. The same considerations apply to determining the value of resistor R 3 , although that resistor will nominally be twice the value of resistor R 2 , as the voltage on the emitter of transistor QN 4  will be 4ΔVBE, i.e., twice the voltage on the emitter of transistor QN 4  in the first Xp 1  loop. Similarly, VOUT will be 6ΔVBE, with resistor R 4  being selected to conduct a bias current approximately equal to IB, plus whatever current is required by the circuit connected to VOUT. Thus there is a progression in resistor values tending to equalize the currents through transistors QN 2  and QN 4  of all Xp 1  loops. In these Xp 1  loops, the R 1 , C 1  circuits are optional. Again, since the 2ΔVBE (at R 2 ), 4ΔVBE (at R 4 ) and 6ΔVBE (at R 5 ) voltages are PTAT voltages and thus vary with temperature. 
         [0034]    Now referring to  FIGS. 4-1  and  4 - 2 , an overall diagram showing a bandgap reference using cascaded Xp 1  loops in accordance with  FIG. 3  may be seen. In these Figures and in other Figures to be described, the signal EN is a conventional enable signal. In the embodiment of  FIGS. 4-1  and  4 - 2 , a low noise Bias current generator  20  provides a bias current to low noise buffered current mirrors  22 , which in turn provide the bias currents IB to each of the Xp 1  loops, specifically loop  1 , loop  2  and loop  3 . Similarly, a bias voltage generator  24  generates the bias voltage VB that is applied to each of the Xp 1  loops. In that regard, the bias voltage VB is applied through resistors R 6  and R 7  to Xp 1  loops  1  and  2 , respectively. In particular, note that the emitter of transistor Q 1  in loop  1  is at a circuit ground potential, the emitter of transistor QN 1  of Xp 1  loop  2  is at a potential of 2ΔVBE (approximately 200 mV in the exemplary embodiment) and the voltage of the emitter of transistor QN 1  in the third Xp 1  loop is at 4ΔVBE (approximately 400 mV). Thus resistors R 6  and R 7  are provided in a progression of values to provide a voltage drop of 4ΔVBE and 2ΔVBE, respectively, so that the collector-base voltage of transistors QN 2  in all three loops are equal to zero. These resistors are optional, and not shown in the embodiment of  FIGS. 6-1 ,  6 - 2  and  6 - 3 . 
         [0035]    Also connected to the Bias voltage generator  24  and one of the current outputs of the buffered Current mirrors  22  is a Summing amplifier  26 . This amplifier is referred to herein as a summing amplifier, as the output thereof is the sum of the 6ΔVBE output of Xp 1  loop  3  plus the VBE of a bipolar transistor in the summing amplifier itself. The summing amplifier is shown in detail in  FIG. 5 . This amplifier uses four transistors Q 5  through Q 8 , of the same conductivity type and connected the same as the transistors in one of the Xp 1  loops. However, in the Summing amplifier of  FIG. 5 , all transistors preferably have the same emitter area. The output OUT of the amplifier is coupled through resistor R 5  to ground, as shown in  FIG. 4-1 , with the input IN being coupled to resistor R 4  and the output OUT of Xp 1  loop  3 , also as shown in  FIG. 4-1 . As may be seen in  FIG. 5 , the output BG is 1VBE above the input IN, specifically, the base emitter voltage (VBE) of transistor QN 5 . The input IN, of course, is the accumulated PTAT voltage 6ΔVBE. In a preferred embodiment each ΔVBE is approximately 100 millivolts, so that at least nominally the sum of the 6ΔVBE (approximately 600 mv) on the input IN plus the base emitter voltage of transistor Q 5  (approximately 600 mv) provides the nominal bandgap output voltage of 1.2 volts at BG. 
         [0036]    As may be seen in  FIGS. 4-1  and  4 - 2 , the nominal bandgap voltage BG output of the Summing amplifier  26  is coupled to a Trim network  28 , which may be of conventional design. In the preferred embodiment, the actual Trim network is a Trim network capable of providing both positive and negative trim increments to the bandgap voltage for calibration purposes. Those trim increments, controlled by the 8 bit input BGT[7:0], are PTAT trim voltage increments to make up for ratio deviations in the components of the Xp 1  loops based on the accumulated PTAT voltage input, as shown. In that regard, assuming that the only significant temperature variations in the bandgap voltage are caused by the negative temperature coefficient of an emitter base (E-B) junction and the positive temperature coefficient ΔVBE of pairs transistors operating with different current densities. Whatever the base emitter voltage is of transistor QN 5  of  FIG. 5 , a substantially temperature insensitive bandgap voltage will be achieved if a PTAT voltage is added thereto to provide a sum equal to the actual bandgap voltage (for silicon −1.23 volts). 
         [0037]    While the Trim network used in the preferred embodiment uses digital PTAT trim voltages increments in both positive and negative directions, the Xp 1  loops could be nominally set to provide a PTAT voltage component somewhat below (or above) the desired value, with the trim network adjusting that PTAT voltage component up (or down) for calibration purposes, or as a further alternative, an analog trim network could be used, again with either positive and negative trimming capabilities, or alternatively, with the ability to either increase or decrease the incremental calibration in a unidirectional manner. 
         [0038]    The output of the Trim network  28  ( FIG. 4-2 ), which is the bandgap voltage, goes through a resistor network of resistors R 8  though R 11  to provide an input to a transconductance operational amplifier  30  (alternatively a regular operational amplifier may be used). The desired bandgap reference voltage (1.23 volts) appears at the top of resistor R 15 . Therefore the output voltage REF appears at the output of the transconductance operational amplifier. Feedback for the transconductance amplifier is provided by resistor network comprising resistors R 12  through R 16 . Resistors R 12  through R 14  are of the same value as resistors R 8  through R 10 , respectively, with the nominal combination of resistors R 15  and R 16  being the same value as resistor R 11 . 
         [0039]    In the exemplary embodiment being explained, the two resistor networks shown in  FIG. 4-2  provide a selection of outputs set during fabrication by appropriate masking. In particular, with a bandgap voltage of 1.23 volts out of the trim network  28 , the first resistor network will provide that voltage to the positive input to the transconductance operational amplifier  30 . The negative input through resistor R 17  is taken from the node between resistors R 14  and R 15 . The transconductance operational amplifier provides an output REF which provides the current through resistors R 12 , R 13  and R 14 . More importantly, through resistors R 12  and R 16  to provide the negative feedback voltage equal to the bandgap voltage provided to the positive transconductance amplifier input. In the exemplary embodiment, resistors R 12  through R 16  are selected such that with the configuration shown in  FIG. 4-2 , the feedback of 1.23 volts provides an output voltage REF of 2.048 volts. If, on the other hand, resistors R 8  and R 12  are effectively shorted out during fabrication (by masking or otherwise), the transconductance amplifier  30  will readjust the output REF to again provide a feedback of 1.23 volts, in the exemplary embodiment readjusting the output REF to 1.8 volts. Shorting out resistors R 8 , R 9 , R 12  and R 13  in the exemplary embodiment provides an output of 1.25 volts. 
         [0040]    And finally, shorting out resistors R 8  through R 10  and R 12  through R 14  will provide the basic bandgap voltage output of 1.23 volts. Resistor R 16  is a variable resistor that acts as the gain trim. In that regard, the resistor network R 8  through R 11  is provided to adjust the resistance coupled to the positive input of the transconductance amplifier  30  to match the resistance to the negative input of the transconductance amplifier from resistor network R 12  through R 16 . 
         [0041]    As an alternative, rather than use a variable resistor (R 16 ) in the output resistor network, after the PTAT voltage component in the output of summing amplifier  26  ( FIG. 4-1 ) has been trimmed, one can use a separate additional trim circuit (as part of the Trim block  28 — FIG. 4-2 ) to add (or subtract) a temperature insensitive voltage component to what would have been the output of the Trim block  28 . In one embodiment, these trims are done by providing a voltage component to the output of the summing amplifier  26  by pushing a current into one end of a series resistor and drawing an equal current out of the other end of the series resistor. As before these trims may be preferably bidirectional digital trims, but could be unidirectional or analog trims. 
         [0042]    Referring again to  FIG. 4-2 , the output REF may be increased above 2.048 volts to even higher voltages by simply increasing the total resistances of resistors R 12  through R 14  and R 8  through R 10  relative to the sum of resistors R 15  and R 16 . However, doing so, at least by very much, has the disadvantage of simply multiplying (gaining up) the noise on the 1.23 volt bandgap voltage generated. Instead, it is more desirable to create a bandgap reference that generates two times the bandgap, specifically 2.46 volts, using the present invention. Such a circuit is shown in  FIGS. 6-1 ,  6 - 2  and  6 - 3 . 
         [0043]    In the circuit of  FIG. 6  ( FIGS. 6-1 ,  6 - 2  and  6 - 3 ), a low noise Bias current generator  20  and low noise Voltage bias generator  24 , which may be identical to those used in  FIG. 4-1 , together with the buffered Current mirrors  22  provide the required current and voltage biases to the six Xp 1  loops used. This provides a total of 12ΔVBE output to the Summing amplifier  26 , which again may be the same as that used in the embodiment of  FIGS. 4-1  and  4 - 2 . In that regard, note that Summing amplifier  26  adds 1VBE to the total PTAT voltage component, to which another VBE must be added to obtain a voltage equal to twice the bandgap voltage. To achieve this, another transistor might be added to the Summing amplifier  26  so that 2VBE is added to the 12ΔVBE of the six Xp 1  loops. This is undesirable as it adds to the minimum power supply voltage required to provide the headroom required to operate the entire circuit. Accordingly, as a preferred alternative, transistor QN 9  ( FIG. 6-3 ) is added. The second VBE will be the base emitter voltage of transistor QN 9 . Since the transconductance amplifier is effectively an operational amplifier, its output will seek a level such that its negative input is equal to its positive input of approximately a PTAT voltage of 1.2 volts plus approximately 0.6 volt of the negative temperature coefficient term (VBE term added by the summing amplifier  26 ). Consequently the voltage at node  2  will be will be one VBE higher than the feedback voltage at INM and thus one VBE higher than the positive input to the transconductance amplifier, or approximately 1.2 volts (2VBE) plus approximately 1.2 volts of PTAT voltage for a total voltage of 2.4V (2 bandgap voltages will now be at node  2 ). In one embodiment, the resistor networks, similar to those of  FIG. 4-2 , are selected to provide outputs of 5.00 volts, 4.5 volts, 4.096 volts, 3.30 volts, 3.00 volts, 2.5 volts and the twice bandgap voltage (2BG) of 2.46 volts. As before, trimming may be by way of the variable resistor on the output resistor network as shown, or as part of the Trim block as previously explained with respect to  FIGS. 4-1  and  4 - 2 . 
         [0044]    It should be noted that the embodiments disclosed herein use low noise current sources and a low noise voltage source to bias the Xp 1  loops. This is, in effect, an embellishment as opposed to a necessity in that because the Xp 1  loops are substantially immune to noise in their biasing currents, a relatively low noise bandgap reference (compared to the prior art) would still be provided without the use of such low noise current and voltage sources. Similarly, the resistors R 1  and capacitors C 1  in each Xp 1  loop are also optional, but are desirable to provide frequency compensation and prevent peaking in the Xp 1  loop. In a preferred embodiment the low noise bias Current source  20 , the Current mirrors  22  and the Bias voltage generator  24 , as well as the six Xp 1  loops of the embodiment of  FIGS. 6-1  through  6 - 3  for the 2BG reference are also used for the 1BG reference of  FIGS. 4-1  and  4 - 2 . In that regard, it may be seen in  FIG. 4-1  that three of the current mirror outputs are merely coupled to ground for the 1BG reference, whereas in  FIG. 6-1  those same three current mirrors are used to bias the three additional Xp 1  loops for the 2BG reference. Thus the same chip may be used for both references as determined by specific masking during the fabrication process. The key, of course, to the low noise characteristics of the present invention is based primarily on the Xp 1  loops themselves, each of which is relatively low noise and substantially immune to noise in its biasing current IB. Thus the noise of the cascaded loops is not additive, but rather only accumulates as the square root of the sum of the squares of the noise of each transistor in each of the Xp 1  loops. While the PTAT output voltage of the first Xp 1  loop has relatively low noise, the PTAT output voltage of the second cascaded Xp 1  loop will have twice the PTAT output voltage of the first Xp 1  loop, but will have a noise of only √{square root over (2)} times the noise voltage signal to noise ratio. Therefore the signal to noise ratio (S/N) is improved by √{square root over (5)}. 
         [0045]    In  FIG. 4-1 , resistors R 2  through R 5  actually serve as passive current sources (the words “current sources” are used generically herein to include current sinks). Similarly, the corresponding resistors in  FIGS. 6-1  and  6 - 2  serve as passive current sources. As an alternative, active current sources may be used for some or all of these resistors. This is illustrated in  FIG. 7-1 , and  FIGS. 8-1  and  8 - 2 .  FIGS. 7-2  and  8 - 3  are merely repeats of  FIGS. 4-2  and  6 - 3 , but are provided for completeness of these illustrations. Use of active current sources is not preferred however, as simulations indicate that active current sources increase noise in the references, and that the head room for the bipolar current source for the first Xp 1  loop in a cascaded series of Xp 1  loops may be marginal. 
         [0046]    In a most general sense, each of the cascaded Xp 1  loops is comprised of four E-B junctions physically connected in first and second pairs so that bias currents flow through each pair, but electrically cross coupled so that the voltage from an end or output of the first pair of the E-B junctions to an end or output of the second pair of E-B junctions is equal to the voltage drop across a first E-B junction in the first pair of E-B junctions plus the voltage drop across a second E-B junction in the second pair of E-B junctions, minus the sum of the voltage drop across a third E-B junction in the first pair of E-B junctions and the voltage drop across a fourth E-B junction in the second pair of E-B junctions. In the embodiments of cascaded Xpl loops disclosed so far, four transistors have been cross coupled, with one (QN 3 ) being diode connected and another (QN 4 ) being preferably operated with a zero collector base voltage. However, QN 2  and QN 3  could be diode connected transistors, as shown in  FIG. 9 . Here, rather than biasing QN 2  with a voltage, the bias current to the now two diode connected transistors is increased to provide the bias current IB to each side of the Xp 1  loops, as shown in  FIG. 9 . With this change,  FIGS. 4-1  and  4 - 2  become  FIGS. 10-1  and  10 - 2 , and  FIGS. 6-1  through  6 - 3  become  FIGS. 11-1  through  11 - 3 . In that regard, any mismatch in current sources between the top and bottom of the Xp 1  circuits will merely accumulate and pass to the ends of the cascaded loops, or at least pass to the side of the first cascaded Xp 1  loop that is connected to the circuit ground. Note that the biasing of the summing amplifier is preferably not changed so as to be able to better drive the trim circuit coupled thereto. 
         [0047]    Also in the embodiments described, the summing amplifier is a circuit like an Xp 1  loop as shown in  FIG. 10-1 , but simply generates a CTAT voltage (VBE) component by adding the base emitter voltage of transistor QN 5  to the total PTAT voltage component of the cascaded Xp 1  loops. As an alternative, by way of example, the common connection between the emitter of the transistor QN 2 , the base of transistor QN 1  and the collector of transistor QN 4  of the last PTAT voltage component generating Xp 1  loop may be also be used as the sum of the PTAT voltage components and the VBE of transistor QN 1  of the last cascaded Xp 1  loop. Thus in this alternative, the so called summing amplifier may have the E-B junction area ratios as the other Xp 1  loops. However, the PTAT voltage component generated by such a loop will not be added to the total PTAT voltage output of the cascaded loops, as the common connection merely adds the VBE of transistor QN 1  to the total PTAT voltage component of the prior loops, and in the claims to follow, would not be considered to be one of the cascaded PTAT voltage circuits. 
         [0048]    Finally, while the present invention has been disclosed and described with respect to basic bandgap references, one may readily include what is referred to as a curvature correction circuit to further flatten the temperature sensitivity of the bandgap voltages generated, if desired. Curvature correction circuitry is well known in the prior art and does not form a part of the present invention. Some embodiments wherein maximum performance is desired will include curvature correction, while other embodiments where minimum die size is the controlling factor, will not include curvature correction. In one embodiment where curvature correction is used, the correction is obtained by varying with temperature, the bias current IB through transistors QN 7  and QN 5  of the summing amplifier ( FIG. 5 ) for the one BG embodiment of  FIGS. 4-1  and  4 - 2 , or varying with temperature, the bias current IB through transistors QN 7  and QN 5  of the summing amplifier ( FIG. 5 ) and through transistor QN 9  ( FIG. 6-3 ) for the two BG embodiment of  FIGS. 6-1  through  6 - 3 . 
         [0049]    Thus while certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Technology Category: 3