Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention generally relates to chip packaging, and more particularly relates to wafer level chip scale packaging.  
       BACKGROUND OF THE INVENTION  
       [0002]     Sensors are used in myriad applications and may be employed to collect any one of numerous types of data. Some sensors are used in determining pressure differentials, for example, between a reference pressure and a measured pressure or between two measured pressures. Typically, these pressure sensors include an integrated chip having circuitry printed thereon and/or sensing or other components mounted thereto. In some sensor configurations, the chip is disposed within a hard case that is configured to protect the sensing components and dissipate heat produced by the circuitry during a chip operation. In other sensor configurations, the chip also includes a plurality of bond wires that are used to couple the die to a circuit board. The bond wires typically extend from the chip and out of the case.  
         [0003]     Although the aforementioned sensor configurations generally operate well in most applications, they may suffer from certain drawbacks in other applications. For instance, in a medical device context, components used in implantable medical devices are preferably extremely small in order to reduce discomfort that may be experienced by an implant patient. However, conventional sensors having cases, such as those described above, may have a relatively high elevation and/or large footprint geometry, thereby needlessly occupying space that could be eliminated from the implantable medical device. In another example, the aforementioned chips may be relatively expensive to manufacture. As a result, relatively inexpensive components may not incorporate sensor chip technology, or alternatively, if the chip is incorporated, the cost of the component is increased.  
         [0004]     Accordingly, it is desirable to have an integrated chip package that is relatively small compared to conventional integrated chip packages. In addition, it is desirable to have a method for making the integrated component that is relatively simple to manufacture and inexpensive. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and  
         [0006]      FIG. 1  is a cross section of an exemplary sensor;  
         [0007]      FIG. 2  is a flowchart illustrating an exemplary method of manufacturing the sensor illustrated in  FIG. 1 ;  
         [0008]      FIG. 3  is an illustration of a step of the method illustrated in  FIG. 2 ;  
         [0009]      FIG. 4  is an illustration of another step of the method illustrated in  FIG. 2 ;  
         [0010]      FIG. 5  is an illustration of yet another step of the method illustrated in  FIG. 2 ; and  
         [0011]      FIG. 6  is an illustration of still another step of the method illustrated in  FIG. 2 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]     The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.  
         [0013]     Turning now to  FIG. 1 , a cross-sectional view of an exemplary integrated component or sensor  100  is illustrated. Sensor  100  includes a substrate layer  102 , circuitry  104 , a sense element  106 , an interconnect  108 , and an encapsulant layer  110 . Substrate layer  102  provides a base to which sensor components are coupled. It will be appreciated that substrate layer  102  may be any one of numerous types of materials conventionally used for a substrate, including for example, silicon, silicon germanium, gallium arsenide, silicon-on-insulator, insulating glass, sapphire, or any other type of suitable material. Circuitry  104  is disposed on at least a portion of substrate layer  102  and may be configured for various integrated circuit applications, such as for example, communications, transportation, general computation, and the like. For example, in the exemplary embodiment, circuitry  104  is configured to communicate pressure data. Circuitry  104  may be formed on substrate layer  102  in any one of numerous conventional manners, for example, screen printing, and photolithography.  
         [0014]     Sense element  106  is configured to sense an ambient characteristic of the surroundings of sensor  100 . Sense element  106  may be any one of numerous types of devices that may be used for sensing particular characteristics of ambient. For example, in the embodiment illustrated in  FIG. 1 , sense element  106  is a thin dome-shaped diaphragm defining a cavity  112  thereunder that expands or contracts in response to a pressure differential between a pressure within cavity  112  and ambient pressure. In order to process the sensed characteristic, sense element  106  is coupled to circuitry  104 . Sense element  106  may be directly or indirectly coupled to circuitry  104  in any one of numerous conventional manners. Sense element  106  may also be coupled to a reference element  107  that provides reference data. Reference element  107  may be any one of numerous devices suitable for providing reference data. In the embodiment depicted in  FIG. 1 , reference element  107  is a dome-shaped diaphragm that is configured to provide a reference pressure. Additionally, reference element  107  is shown disposed next to sense element  106 ; however, it will be appreciated that reference element  107  may be coupled to any other portion of sensor  100 . In the embodiment in  FIG. 1 , circuitry  104  is configured to calculate a differential between the reference pressure and the sensed ambient pressure.  
         [0015]     Interconnect  108  allows circuitry  104  to communicate data sensed by sense element  106  and/or a differential calculated between sense element  106  and reference element  106  to other non-illustrated external components. In this regard, interconnect  108  is constructed of any one of numerous materials suitable for transmitting and receiving data, for example, metal or polysilicon. Interconnect  108  is at least partially disposed within a via  120  formed through substrate layer  102 . However, interconnect  108  may be positioned in any section of sensor  100 . Although a single interconnect  108  and via  120  are illustrated, it will be appreciated that more than one of each may be incorporated in sensor  100 .  
         [0016]     Interconnect  108  has a first end  114  and a second end  116 . First end  114  is coupled to circuitry  104  and may be formed at one end of interconnect  108  or, as illustrated in  FIG. 1 , may be a separately formed piece that is subsequently coupled to interconnect  108 . In either case, first end  114  is constructed of conductive material capable of electrical communication. Second end  116  extends external to sensor  100  and provides an interface between sensor  100  and any external components to which sensor  100  may be coupled, such as, for instance, a circuit board, module housing, or substrate. Similar to first end  114 , second end  116  maybe formed as part of interconnect  108 , or alternatively, and as shown in  FIG. 1 , may be a separately formed piece. In the depicted embodiment in  FIG. 1 , second end  116  is a piece of conductive material having a flat section  122  coupled to interconnect  108  and a conductive section  124  coupled to the flat section  122 . Conductive section  124  is bumped outward from sensor  100 . To prevent crossing electrical connections that may potentially occur between interconnect  108  and: circuitry  104 , a passivation layer  126  overlies substrate layer  102  and via  120 . Passivation layer  126  may be constructed of any one of a number of insulating materials, such as, for example, parylene, silicon dioxide, silicon nitride, and the like.  
         [0017]     Encapsulant layer  110  is employed to protect circuitry  104  from chemical, physical, thermal and/or any other type of damage. In this regard, encapsulant layer  110  is constructed of any one of numerous types of encapsulating material capable of withstanding any chemical, physical, or thermal environment within which sensor  100  may be placed. Suitable materials include, but are not limited to, plastic, rigid polymers, polyimide, and the like. To allow sense element  106  to contact ambient, an opening  128  is provided therein. Opening  128  is disposed over sense element  106  such that sense element  106  is substantially exposed. Alternatively, sense element  106  is disposed within opening  128 , as shown in  FIG. 1 . Additionally, opening  128  may be disposed over reference element  107 , or reference element  107  may be disposed within opening  128 . In one exemplary embodiment, opening  128  is sized such that encapsulant layer  110  does not contact sense element  106 .  
         [0018]     With reference now to  FIGS. 2-6 , an exemplary method by which integrated component  100  may be manufactured will now be discussed. The overall process  200  will first be described generally. It should be understood that the parenthetical references in the following description correspond to the reference numerals associated with the flowchart blocks shown in  FIG. 2 . First, a wafer  300  having substrate layer  302 , circuitry  304 , at least one sense element  306  and at least one interconnect  308  is obtained ( 202 ). Then, a sacrificial layer  330  is deposited over each of the sense elements  306  ( 204 ). Next, an encapsulant layer  332  is applied to the wafer  300  ( 206 ). The wafer  300  may then be diced ( 208 ). Lastly, the sacrificial layer  330  is removed ( 210 ). These steps will now be described in further detail below.  
         [0019]     Turning to  FIG. 3 , a section of an exemplary wafer  300  that may be obtained ( 202 ) is illustrated. The wafer section  300  includes a substrate layer  302 , circuitry  304  that is printed or screened thereon, at least one sense element  306  coupled to the circuitry  304 , and an interconnect  308  that extends through the wafer section  300 . The wafer section  300  is part of a wafer that includes more than one wafer sections  300 . The wafer may be manufactured as part of process  200  in any one of numerous conventional manners for fabricating a wafer, such as, for example, using front-end manufacturing techniques, including, but not limited to photolithography, chemical vapor deposition (“CVD”), physical CVD, chemical mechanical planarization, and/or chemical etching, and back-end manufacturing techniques. Alternatively, the wafer  300  may be obtained prior to process  200 .  
         [0020]     As briefly mentioned above, next, a sacrificial layer  330 , shown in  FIG. 4 , is deposited over each sense element  306  ( 204 ). Deposition may be performed in any one of numerous manners. For example, in one embodiment, the sacrificial layer material is dispensed over each sense element  306  using an appropriately configured needle. In another exemplary embodiment, a suitably configured mask is placed over the wafer  300  and sacrificial layer material is screened onto the mask and wafer  300 . In still another exemplary embodiment, the sacrificial layer material may deposited using a shadow mask and spray, or spin on application The sacrificial layer  330  is preferably deposited such that at least the sense element  106  is completely covered. In one exemplary embodiment, the sacrificial layer  330  is deposited at a thickness of between about 0.020 and 2 mm. Alternatively, the sacrificial layer  330  may be at thickness of about 10% of the thickness of the resultant sensor  100 . However, it will be appreciated that any other suitable thickness may be employed as well.  
         [0021]     The sacrificial layer material may be any one of a number of materials suitable for temporarily adhering to sense element  306  without damage. Preferably, the material is thixotropic, able to withstand curing temperatures of at least about 140° C. or any other temperature that may be employed in process  200 , and able to endure the subsequent dicing step without decomposing ( 208 ). Additionally, the material is preferably easily removable upon the application of a removal solution or removal process. In one exemplary embodiment, the sacrificial material is water soluble and removable with the application of deionized water. In another exemplary embodiment, the material is removable by using photoresist stripper, or another chemical or plasma material. Suitable sacrificial layer materials include, but are not limited to adhesives Dymax 9-20553 provided by Dymax Corporation of Torrington, Conn. or Aquabond S65 provided by Aquabond, LLC of Placentia, Calif. For some materials, curing may need to occur in order to sufficiently set sacrificial layer  330  over sense element  306 . It will be appreciated that although-sacrificial layer  330  is described herein as being deposited over sense element  306 , deposition may also occur on any other wafer-mounted component that does not need to be protected.  
         [0022]     After the sacrificial layer material is deposited, an encapsulant layer  332  is formed over the wafer  300  ( 206 ). The encapsulant layer  332 , illustrated in  FIG. 5 , may be formed using any one of numerous conventional methods for encapsulating a wafer, including, but not limited to liquid molding technology. For example, any wafer level molding technology may be used. In one exemplary embodiment, a pellet made of encapsulant layer material is placed on the wafer  300  while the wafer  300  is mounted between two hot platens. As the hot platens come together, heat from the platens melts the pellet causing the encapsulant layer material to flow over the wafer  300 . Preferably, an amount of encapsulant layer material is used such that the material flows in the spaces between the sacrificial layer  330 , but does not envelop the sacrificial layer  330 . The material used to make the encapsulant layer  332  may be any one of a number of materials typically used as a protective coating over circuitry. For instance, the encapsulant layer  332  may be any type of plastic, epoxy, polyimide, or any other type of suitable insulating material.  
         [0023]     After the encapsulant layer  332  is appropriately formed over the wafer  300 , the wafer  300  may be diced ( 208 ). During the dicing step ( 208 ), the wafer  300  is cut into a plurality of die or chips  300   a ,  300   b ,  300   c , as illustrated in  FIG. 6 . Dicing may be performed using any conventional method of dicing, such as employing any saw technology. Although the dicing step ( 208 ) is described here as taking place after the encapsulating step ( 206 ), it will be appreciated that dicing may occur at any other suitable junction during process ( 200 ), for example, at the end of process ( 200 ).  
         [0024]     Next, sacrificial layer  330  is removed from chip  300   a  ( 210 ). Sacrificial layer  330  may be removed using any appropriate removal solution, such as deionized water, plasma, or other chemical, depending on the sacrificial layer material employed. In one example, the removal solution is placed under high pressure and subsequently sprayed at the sacrificial layer  330 . When sacrificial layer  300  material is removed, an opening  338  is formed exposing sense element  308 , resulting in sensor  100 , illustrated in  FIG. 1 . The chip  300   a  can then be mounted to a circuit board or any other external device.  
         [0025]     Thus, there has now been provided an integrated chip scale package that is relatively small in comparison to conventional integrated chip packages. Additionally, a method has been provided for processing the chip scale packaging that is relatively inexpensive and simple.  
         [0026]     While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.

Technology Category: 7