Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a compound logic circuit which is composed of a NAND gate circuit and a NOR gate circuit. 
     2. Description of the Related Art 
     For example, consider a compound logic circuit formed on one integrated circuit chip. In case the compound logic circuit is composed of a NAND gate circuit and a NOR gate circuit both of which is formed of CMOS transistors, in general, the NAND gate circuit is formed of quite different transistors from the NOR gate circuit. 
     FIG. 2 is a circuit diagram showing this type of compound logic circuit composed of a NAND gate circuit and a NOR gate circuit according to the related art of the invention. 
     As shown in the upper part of FIG. 2, one NAND gate circuit 10 is composed of four transistors 11 to 14, that is, two p-channel MOS transistors 11, 12 (referred to as a PMOS transistor) and two n-channel MOS transistors 13, 14 (referred to as a NMOS transistor). 
     AS shown in the lower part of FIG. 2, one NOR gate circuit 20 is also composed of four transistors 21 to 24, that is, two PMOS transistors 21, 22 and two NMOS transistors 23, 24. 
     As will be obvious from FIG. 2, the NAND gate circuit 10 is composed of the dedicated transistors which are independent of the transistors composing the NOR gate circuit 20. 
     This type of compound logic circuit according to the related art of the invention requires each two PMOS transistors and each two NMOS transistors, that is, eight transistors in total for composing one NAND gate circuit and one NOR gate circuit. It means that the type of compound logic circuit needs a larger area on the integrated circuit chip occupied by the compound logic circuit. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a compound logic circuit which needs a less area on the integrated circuit chip occupied by the compound logic circuit itself. 
     In carrying out the object in a preferred mode, the present invention provides a compound logic circuit which includes a NAND gate comprising two p-channel transistors and two n-channel transistors and a NOR gate comprising two p-channel transistors and two n-channel transistors, one of the two p-channel transistors contained in the NAND gate being same as one of the two p-channel transistors contained in the NOR gate, and one of the two n-channel transistors contained in the NAND gate being same as one of the two n-channel transistors contained in the NOR gate. 
     According to the compound logic circuit of the present invention, as stated above, one of the p-channel transistors contained in the NAND gate circuit is the same as one of the p-channel transistors contained in the NOR gate circuit and one of the n-channel transistors contained in the NAND gate circuit is the same as one of the n-channel transistors contained in the NOR gate circuit. The present compound logic circuit needs only six transistors though it has a NAND gate circuit and a NOR gate circuit like the foregoing related art, resulting in reducing its occupation area on the integrated circuit chip area. 
     Further objects and advantages of the present invention will be apparent from the following description, reference being had to the accompanying drawings wherein a preferred embodiment of the present invention is clearly shown. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a compound logic circuit according to an embodiment of the present invention; and 
     FIG. 2 is a circuit diagram showing a compound logic circuit according to a related art of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a circuit diagram showing a compound logic circuit according to an embodiment of the present invention. 
     As shown, between a supply voltage line VDD and a ground wire is connected a circuit which includes a PMOS transistor 31, an NMOS transistor 32, and an NMOS transistor 51 connected in series in the referenced sequence. Between the supply voltage line VDD and the ground wire is also connected a circuit which includes a PMOS transistor 52, a PMOS transistor 41, and an NMOS transistor 42 connected in series in the referenced sequence. 
     A contact point between the PMOS transistor 31 and the NMOS transistor 32 is connected to a contact point between the PMOS transistor 52 and the PMOS transistor 41. 
     Likewise, a contact point between the NMOS transistor 32 and the NMOS transistor 51 is connected to a contact point between the PMOS transistor 41 and the NMOS transistor 42. 
     A NAND gate circuit 30 is composed of the PMOS transistor 31, the NMOS transistor 32, the NMOS transistor 51, and the PMOS transistor 52. 
     Likewise, a NOR gate circuit 40 is composed of the PMOS transistor 52, the PMOS transistor 41, the NMOS transistor 42, and the NMOS transistor 51. 
     As will be appreciated from the above description, the NMOS transistor 51 and the PMOS transistor 52 are used in both the NAND gate circuit 30 and the NOR gate circuit 40. 
     The NAND gate circuit 30 includes two input terminals, that is, an input terminal 33 connected to the gate electrodes of the PMOS transistor 31 and the NMOS transistor 32 and a common input terminal 53 connected to the gate electrodes of the NMOS transistor 51 and the PMOS transistor 52 commonly used in the NOR gate circuit 40. The NAND gate circuit 30 supplies an output at an output terminal 34 connected to the contact point between the PMOS transistor 31 and the NMOS transistor 32. 
     The NOR gate circuit 40 includes two input terminals, that is, an input terminal 43 connected to the gate electrodes of the PMOS transistor 41 and the NMOS transistor 42 and the common input terminal 53. The NOR gate circuit 40 supplies an output at an output terminal 44 connected to the contact between the NMOS transistor 32 and the NMOS transistor 51. 
     In the present embodiment, as stated above, the NMOS transistor 51 and the PMOS transistor 52 are commonly used in both the NAND gate circuit 30 and the NOR gate circuit 40 and the number of the transistors is reduced accordingly. It results in reducing the occupation area of the compound logic circuit on the integrated circuit chip. 
     Then, the description will be directed to how the compound logic circuit operates. 
     At first, the NAND gate circuit 30 will be described. 
     Assume that a logic signal of &#34;0&#34; level is applied to the input terminal 33 and the common input terminal 53. In this case, the PMOS transistor 31 and the commonly used PMOS transistor 52 are both switched on and the NMOS transistor 32 and the commonly used NMOS transistor 51 are both switched off. As a result, a voltage close to the supply voltage VDD appears on the output terminal 34 so that the logic signal of &#34;1&#34; level is supplied at the output terminal 34. 
     Assume that a logic signal of &#34;0&#34; is applied to the input terminal 33 and a logic signal of &#34;1&#34; is applied to the commonly used terminal 53. In this case, the PMOS transistor 31 is switched on, the commonly used PMOS transistor 52 is switched off, the NMOS transistor 32 is switched off, and the commonly used NMOS transistor 51 is switched on. As a result, a voltage close to the supply voltage VDD appears at the output terminal 34 so that a logic signal of &#34;1&#34; is supplied at the output terminal 34. 
     Assume that a logic signal of &#34;1&#34; is applied to the input terminal 33 and a logic signal of &#34;0&#34; is applied to the common input terminal 53. In this case, the PMOS transistor 31 is switched off, the commonly used PMOS transistor 52 is switched on, the NMOS transistor 32 is switched on, and the commonly used NMOS transistor 51 is switched off. As a result, a voltage close to the supply voltage VDD appears at the output terminal 34 so that a logic signal of &#34;1&#34; level is supplied at the output terminal 34. 
     Assume that a logic signal of &#34;1&#34; is applied to the input terminal 33 and a logic signal of &#34;1&#34; is applied to the common input terminal 53. In this case, the PMOS transistor 31 and the commonly used PMOS transistor 52 are both switched off and the NMOS transistor 32 and the commonly used NMOS transistor 51 are both switched off. As a result, a voltage close to a ground voltage appears at the output terminal 34 so that the logic signal of &#34;0&#34; level is supplied at the output terminal 34. 
     Next, the NOR gate circuit 40 will be described. 
     Assume that a logic signal of &#34;0&#34; is applied to the input terminal 43 and a logic signal of &#34;0&#34; is applied to the common input terminal 53. In this case, the PMOS transistor 41 and the commonly used PMOS transistor 52 are both switched on and the NMOS transistor 42 and the commonly used NMOS transistor 51 are both switched off. As a result, the voltage close to the supply voltage VDD appears at the output terminal 44 so that the logic signal of &#34;1&#34; level is supplied at the output terminal 44. 
     Assume that a logic signal of &#34;0&#34; is applied to the input terminal 43 and a logic signal of &#34;1&#34; is applied to the common input terminal 53. In this case, the PMOS transistor 41 is switched on, the commonly used PMOS transistor 52 is switched off, the NMOS transistor 42 is switched off, and the commonly used NMOS transistor 51 is switched on. As a result, a voltage close to the earth voltage appears at the output terminal 44 so that a logic signal of &#34;0&#34; level is supplied at the output terminal 44. 
     Assume that a logic signal of &#34;1&#34; is applied to the input terminal 43 and a logic signal of &#34;0&#34; is applied to the common input terminal 53. In this case, the PMOS transistor 41 is switched off, the commonly used PMOS transistor 52 is switched on, the NMOS transistor 42 is switched on, and the commonly used NMOS transistor 51 is switched off. As a result, a voltage close to the ground voltage appears at the output terminal 44 so that a logic signal of&#34;1&#34; level is supplied at the output terminal 44. 
     Assume that a logic signal of &#34;1&#34; is applied to the input terminal 43 and a logic signal of &#34;1&#34; is applied to the common input terminal 53. In this case, the PMOS transistor 41 and the commonly used PMOS transistor 52 are both switched off and the NMOS transistor 42 and the commonly used NMOS transistor 51 are both switched on. As a result, a voltage close to the earth voltage appears at the output terminal 44 so that the logic signal of &#34;0&#34; level is supplied at the output terminal 44. 
     Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiment described in this specification, except as defined in the appended claims.

Technology Category: 5