Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention is related to techniques for clock and data recovery (CDR) techniques and, more particularly, to techniques for improving the linearity of phase interpolators.  
       BACKGROUND OF THE INVENTION  
       [0002]     In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.  
         [0003]     A number of existing digital CDR circuits use one or more analog phase interpolators to generate a clock signal of a desired phase between the phase of two input signals. It has been found that most analog phase interpolators demonstrate a non-linear phase output in response to a control input. This, in turn, adversely affects the performance of the CDR circuit. The interpolator non-linearity is often attributed to variations in process, voltage, temperature or aging (PVTA).  
         [0004]     A need therefore exists for improved techniques for interpolating two input clock signals to generate a clock signal having a phase between the phase of the two input clock signals. A further need exists for improved techniques for linearizing the phase output of an analog interpolator in response to a control input.  
       SUMMARY OF THE INVENTION  
       [0005]     Generally, methods and apparatus are provided for digital linearization of an analog phase interpolator. According to one aspect of the invention, up to 2 N  desired phase values are mapped to a corresponding M bit value, where M is greater than N. Thereafter, a corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2 N  desired phase values. An M bit value corresponding to a given one of the 2 N  desired phase values can be stored in a storage element indexed by an N bit value. The mapping of M bit values to N bit values is obtained by evaluating a plurality of phases of an interpolated clock signal generated by the phase interpolator as a function of a pluarlity of applied interpolation control codes.  
         [0006]     According to another aspect of the invention, a linearized phase interpolator is provided that can account for process, voltage, temperature or aging (PVTA) variations. Thus, for each of a plurality of possible PVTA conditions, up to 2 N  desired phase values are mapped to a corresponding M bit value, where M is greater than N. A mapping is then selected for a current PVTA condition, and based on the selected mapping, a corresponding M bit value is applied to the phase interpolator to obtain a desired one of the  2 N desired phase values.  
         [0007]     A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is a schematic block diagram of a conventional phase interpolator;  
         [0009]      FIG. 2  is a characteristic curve illustrating the phase of the interpolated clock signal of  FIG. 1  as a function of the applied interpolation control code;  
         [0010]      FIG. 3  illustrates the non-linear phase of the interpolated clock signal of  FIG. 1  for each applied interpolation control code;  
         [0011]      FIG. 4  illustrates the mapping of the desired phase of the interpolated clock signal to the corresponding interpolation control code according to the linearization of the present invention;  
         [0012]      FIG. 5  is a schematic block diagram of a linearized phase interpolator incorporating features of the present invention; and  
         [0013]      FIG. 6  is a schematic block diagram of an alternative linearized phase interpolator incorporating features of the present invention to account for process, voltage, temperature or aging (PVTA) variations. 
     
    
     DETAILED DESCRIPTION  
       [0014]     The present invention provides methods and apparatus for digital linearization of an analog phase interpolator.  FIG. 1  is a schematic block diagram of a conventional phase interpolator  100 . As shown in  FIG. 1 , an input clock signal is applied to a delay stage  110  to generate two phase offset clock signals that are applied to the input of the analog phase interpolator  100 . The input clock signal may be generated, for example, by a local voltage controlled oscillator (VCO) or a voltage controlled delay loop (VCDL). The analog phase interpolator  100  generates an interpolated clock signal  130  having a desired phase in response to an interpolation control code  140 , in a known manner.  
         [0015]      FIG. 2  is a characteristic curve  200  illustrating the phase of the interpolated clock signal  130  of  FIG. 1  as a function of the applied interpolation control code  140 . As shown in  FIG. 2 , while it desired for the analog phase interpolator  100  to exhibit the ideal linear characteristic curve  210 , an analog phase interpolator  100  will typically demonstrate a non-linear characteristic curve  220 . For example, for an interpolation control code  140  of  011 , it is desired that the analog phase interpolator  100  generates an interpolated clock signal  130  having a phase of 3Φ. Similarly, for an interpolation control code  140  of  101 , it is desired that the analog phase interpolator  100  generates an interpolated clock signal  130  having a phase of 5Φ.  
         [0016]     As shown more clearly in  FIG. 3 , however, for an interpolation control code  140  of  011 , the analog phase interpolator  100  actually generates an interpolated clock signal  130  having a phase closer to 4Φ (as opposed to 3Φ). Similarly, for an interpolation control code  140  of  101 , the analog phase interpolator  100  actually generates an interpolated clock signal  130  having a phase just above 4Φ (as opposed to 5Φ).  
         [0017]     The present invention recognizes that the analog phase interpolator  100  can be linearized by employing an over-sampled phase interpolator and then selecting the desired phase through code mapping.  FIG. 4  illustrates the mapping of the desired phase of the interpolated clock signal to the corresponding interpolation control code. As shown in  FIG. 4 , the 3 bit interpolation control code is mapped, for example, to a corresponding 6 bit interpolation control code that controls an over-sampled phase interpolator. For example, to obtain an interpolated clock signal having a phase of 2Φ, a 6 bit interpolation control code ( 000011 ) corresponding to  010  should be applied to the analog phase interpolator  100 . Likewise, to obtain an interpolated clock signal having a phase of 6Φ, a 6 bit interpolation control code corresponding to  110  should be applied to the analog phase interpolator  110 .  
         [0018]      FIG. 5  is a schematic block diagram of a linearized phase interpolator  500  incorporating features of the present invention. As shown in  FIG. 5 , an input clock signal is applied to a delay stage  510  to generate two phase offset clock signals that are applied to the inputs of the analog phase interpolator  520 , in the same manner as  FIG. 1 . The linearized phase interpolator  500  includes an exemplary code mapper circuit  525  that maps the desired phase of the interpolated clock signal  530  to the corresponding 6 bit interpolation control code. As shown in  FIG. 5 , the code mapper circuit  525  includes a multiplexer  560  that is indexed by a 3 bit control input  545 . The 3 bit value corresponding to a desired phase is applied to the multiplexer  560  and the corresponding 6 bit value is obtained from a storage element  540  that is selected by the multiplexer  560 .  
         [0019]     For example, to obtain an interpolated clock signal  530  having a phase of 2Φ, the code mapper circuit  525  should generate a 6 bit interpolation control code  535  of  000011  that is applied to the analog phase interpolator  520 . In particular, to obtain an interpolated clock signal  530  having a phase of  24 ), the corresponding 3 bit value of  010  is applied to the multiplexer  560 , and the multiplexer  560  retrieves the corresponding 6 bit interpolation control code of  000011  that is stored in storage element  540 - 2 .  
         [0020]     Likewise, to obtain an interpolated clock signal  530  having a phase of 6Φ, the code mapper circuit  525  should generate a 6 bit interpolation control code  535  that corresponds to the 3 bit code  010 . In particular, to obtain an interpolated clock signal  530  having a phase of 6Φ, the corresponding 3 bit value of 10 is applied to the multiplexer  560 , and the multiplexer  560  retrieves the corresponding 6 bit interpolation control code that is stored in storage element  540 - 6 .  
         [0021]      FIG. 6  is a schematic block diagram of an alternative linearized phase interpolator  600  incorporating features of the present invention to account for process, voltage, temperature or aging (PVTA) variations. In the embodiment of  FIG. 6 , characteristic curve of the phase interpolator is evaluated under various PVTA conditions. In particular, for each PVTA condition, a mapping is obtained that maps the 3 bit interpolation control code, for example, to a corresponding 6 bit interpolation control code that controls an over-sampled phase interpolator.  
         [0022]     Thus, in the exemplary implementation shown in  FIG. 6 , the code mapper circuit  625  provides an additional level of code mapping that allows the PVTA variations to be addressed. A second set of multiplexers  650  is indexed by, for example, a 3 bit PVTA code  655  that characterizes the current PVTA conditions. The 3 bit PVTA code  655  can be applied to each multiplexer, such as multiplexer  650 - 0 , in the second set of multiplexers  650 . It is noted that PVTA conditions can be obtained using one or more well known techniques.  
         [0023]     Each multiplexer  650 -i in the set of multiplexers  650  selects the appropriate 6 bit interpolator control code from a corresponding storage element  640 -i, based on the the 3 bit PVTA code. In an implementation where the PVTA code is a 3 bit value, each multiplexer  650 -i selects a value from one of eight storage elements  640 -i. For example, multiplexer  650 - 0  selects a 6 bit value from one of eight storage elements  640 - 0  (there would be 8 individual storage elements  640 - 0  that are applied to multiplexer  650 - 0  although only one is shown in  FIG. 6  for ease of illustration). In this manner, the set of multiplexers  650  presents the appropriate 6-bit to 3-bit mapping for the current PVTA condition.  
         [0024]     A plurality of identical die are typically formed in a repeated pattern on a surface of the wafer. Each die includes a device described herein, and may include other structures or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.  
         [0025]     It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.

Technology Category: 5