Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 USC §119 to Patent Application No. 2009-0132764 filed on Dec. 29, 2009 with the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Example embodiments relate to semiconductor devices; in particular, a memory interface device and method with noise reduction. 
         [0004]    2. Discussion of the Related Art 
         [0005]    As operating speed of semiconductor devices increases, coupled with higher rate of integration of semiconductor devices, signal lines for transferring signals internally or between semiconductor devices are disposed near one another. Accordingly, when a signal is transmitted through one signal line, noise such as crosstalk noise or coupling noise may be induced in other nearby signal lines. 
       SUMMARY 
       [0006]    According to an aspect of the present inventive concept, a memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line. 
         [0007]    According to another aspect, a third signal output circuit is configured to output a third signal via a third signal line to a third I/O terminal, wherein the output of the noise cancellation circuit is also used to reduce noise due to the presence of the first signal on the first signal line. 
         [0008]    According to another aspect, a delay unit is connected to the first signal line configured to adjust the phase of the first signal. 
         [0009]    According to another aspect, the noise cancellation circuit includes more than one phase adjusting element and more than one gain adjusting element, wherein each of the more than one phase adjusting elements and gain adjusting elements is independently adjustable. 
         [0010]    A memory system is also provided, comprising: a first semiconductor device that interfaces with a second semiconductor device via respective I/O terminals, the first semiconductor device comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a first noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line; and a second semiconductor device comprising: a third signal output circuit configured to output a third signal via a third signal line to a third I/O terminal; a fourth signal output circuit configured to output a fourth signal via a fourth signal line to a fourth I/O terminal; and a second noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to cancel a noise signal induced on the fourth signal line due to the presence of the third signal on the third signal line. 
         [0011]    According to another aspect, the second signal line is disposed adjacent to the first signal line, and a third signal line is disposed adjacent to the fourth signal line. 
         [0012]    According to another aspect, the first semiconductor device is a memory controller, and the second semiconductor device is a memory device. 
         [0013]    According to another aspect, the first noise cancellation circuit includes more than one phase adjusting element and more than one gain adjusting element. 
         [0014]    According to another aspect, the output of the first noise cancellation circuit is applied to a plurality of signal lines, and the output of the second noise cancellation circuit is applied to a plurality of signal lines. 
         [0015]    According to another aspect, the first semiconductor device includes more than one noise cancellation circuits, and the second semiconductor device includes more than one noise cancellation circuits. 
         [0016]    A memory interface method is also provided, comprising: detecting a noise signal at a second signal line induced from a signal on a first signal line disposed adjacent to the second signal line; measuring the phase and magnitude of the noise signal; adjusting delay and gain values of a noise cancellation circuit based on the measured phase and magnitude of the noise signal to output a noise reduction signal; and applying the noise reduction signal to the second signal line to reduce the noise signal present at the second signal line. 
         [0017]    According to another aspect, the method further includes applying the noise reduction signal to a third signal line. 
         [0018]    A method of noise reduction training in a memory device is also provided, comprising: transmitting a signal through a first signal line; measuring characteristics of a noise signal generated on a second signal line; generating a noise reduction signal by adjusting the phase of the measured noise signal; repeating the measuring and generating steps until the noise level is within a predetermined level; and applying the noise reduction signal to the second signal line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
           [0020]      FIG. 1  is a block diagram illustrating a memory system according to some example embodiments. 
           [0021]      FIG. 2  is a block diagram illustrating a memory system according to some example embodiments. 
           [0022]      FIG. 3  is a block diagram of a signal output circuit and a noise cancelling signal generator connected in a memory device. 
           [0023]      FIG. 4  is a waveform diagram illustrating various signals output from the circuits of  FIG. 3 . 
           [0024]      FIG. 5  is a block diagram of signal output circuits connected to a noise cancelling signal generator according to other example embodiments. 
           [0025]      FIG. 6A  is a block diagram illustrating a noise cancelling signal generator according to some example embodiments. 
           [0026]      FIG. 6B  is a block diagram illustrating a noise cancelling signal generator according to other example embodiments. 
           [0027]      FIG. 7  is a flow chart illustrating a training method of a semiconductor memory device according to some example embodiments. 
           [0028]      FIG. 8  illustrates a memory system having signal output circuits and noise cancelling signal generators according to some example embodiments. 
           [0029]      FIG. 9  illustrates another memory system having signal output circuits and noise cancelling signal generators according to other example embodiments. 
           [0030]      FIG. 10  illustrates still another memory system having signal output circuits and noise cancelling signal generators. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0031]    Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present inventive concept may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present inventive concept to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like numerals refer to like elements throughout. 
         [0032]    It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present inventive concept. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0033]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
         [0034]      FIG. 1  is a block diagram illustrating a memory system according to some example embodiments. 
         [0035]    Referring to  FIG. 1 , a memory system  10  includes a control unit  20  and a memory module  30  which has a plurality of memory devices  40  and  50 . The control unit  20  exchanges data DQ with each of the memory devices  40  and  50 , and the control unit  20  applies a command/address signal CA to each of memory devices  40  and  50 . The control unit  20  may be one of a memory controller, a micro processor, a central processing unit (CPU) and a graphic processing unit (GPU). Each of the memory devices  40  and  50  may be a memory device for storing data such as DRAM, RRAM, MRAM, PRAM, a graphic memory and a flash memory. 
         [0036]      FIG. 2  is a block diagram illustrating a memory system according to some example embodiments. 
         [0037]    Referring to  FIG. 2 , a memory system  100  includes a first semiconductor device  110  and a second semiconductor device  150 . The first semiconductor device  110  may be a control unit and the second semiconductor device  150  may be a memory device. An interface unit transmits/receives signals between the control unit  110  and the memory device  150 . Each of input/output (I/O) terminals  141 ˜ 144  of the control unit  110  is connected to each of I/O terminals  181 ˜ 184  of the memory device  150  through each of channels CH 1 ˜CH 4 . Each of the channels CH 1 ˜CH 4  may be a transmission line. 
         [0038]    The control unit  110  includes a signal output circuit  120  and a noise cancelling signal generator  130 . The signal output circuit  120  provides a signal SIG 1  to the I/O terminal  142  through a first signal line  131 . The memory device  150  also includes a signal output circuit  160  and a noise cancelling signal generator  170 . The signal output circuit  160  provides a signal SIG 2  to the I/O terminal  183  through a second signal line  171 . In some embodiments, the signal output circuit  120  may be one of a data signal output circuit, a command signal output circuit and an address signal output circuit. In addition, the first signal line  131  may be one of a data signal line, a command signal line and an address signal line. The signal output circuit  160  may be a data signal output circuit. 
         [0039]    When the signal SIG 1  is transmitted to the I/O terminal  142  through the first signal line  131 , a noise (a crosstalk noise or a coupling noise) due to the signal SIG 1  in the first signal line  131  may be induced in signal lines (not illustrated) connected to the I/O terminals  141 ,  143  and  144  adjacent to the I/O terminal  142 . The noise in signal lines (not illustrated) connected to the I/O terminals  141 ,  143  and  144  adjacent to the I/O terminal  142  may be induced when a transition of the signal SIG 1  in the first signal line  131  occurs. In some instances, such induced noise interrupts the transition of the signal SIG 1  in the first signal line  131  when the signal SIG 1  transitions from a logic low level to a logic high level or transitions from a logic high level to a logic low level. 
         [0040]    The noise cancelling signal generator  130  detects the transition of the signal SIG 1  transmitted through the first signal line  131 , generates a noise cancelling signal NCS 1  for cancelling the noise in signal lines (not illustrated) connected to the I/O terminals  141 ,  143  and  144  adjacent to the I/O terminal  142 , and applies the noise cancelling signal NCS 1  to the adjacent signal lines or the I/O terminals  141 ,  143  and  144  through a signal line  133 . Therefore, signals are transmitted with the noise due to the signal SIG 1  being minimized in the channels CH 1 ˜CH 4 . 
         [0041]    Similarly, the noise cancelling signal generator  160  in the memory device  150  detects a transition of the signal SIG 2  transmitted through the second signal line SIG 2 , generates a noise cancelling signal NCS 2  for cancelling the noise in signal lines (not illustrated) connected to the I/O terminals  181 ,  183  and  184  adjacent to the I/O terminal  182 , and applies the noise cancelling signal NCS 2  to the adjacent signal lines or the I/O terminals  181 ,  183  and  184  through a signal line  173 . Therefore, signals are transmitted with the noise due to the signal SIG 2  being minimized in the channels CH 1 ˜CH 4 . 
         [0042]    Although the signal output circuits  120  and  160  are shown as connected to I/O terminals  142  and  183  as illustrated in  FIG. 2 , other signal output circuits may be respectively connected to each of I/O terminals  141 ,  143 ,  144 ,  181 ,  182  and  184 . In addition, corresponding noise cancelling signal generator may be connected to each of other signal output circuits which are not illustrated. In addition, the noise cancelling signal NCS 1  is not applied to the first signal line  131 , because the noise cancelling signal NCS 1  is for cancelling the noise induced in other signal lines connected to the I/O terminals  141 ,  143  and  144  adjacent to the I/O terminal  142 . Similarly, the noise cancelling signal NCS 2  is not applied to the second signal line  171 , because the noise cancelling signal NCS 2  is for cancelling the noise induced in other signal lines connected to the I/O terminals  181 ,  182  and  184  adjacent to the I/O terminal  183 . 
         [0043]      FIG. 3  is a block diagram of a signal output circuit and a noise cancelling signal generator connected in a memory device. Referring to  FIG. 3 , a semiconductor device  200  includes a plurality of signal output circuits  211 ˜ 213  and a noise cancelling signal generator  230 . Each of the signal output circuits  211 ˜ 213  is connected to each of I/O terminals  251 ˜ 253  through signal lines  221  and  261 ,  222  and  262  and  223  and  263 , and each of the signal output circuits  211 ˜ 213  outputs each of signals SIG 1 ˜SIG 3 . In some embodiments, each of the signal lines  221  and  261 ,  222  and  262  and  223  and  263  may be one of a data signal line, a command signal line and an address signal line. Each of the signal output circuits  211 ˜ 213  may be connected to each of the I/O terminals  251 ˜ 253  via respective delay units  231 ˜ 233  and drivers  241 ˜ 243 . Each of the delay units  231 ˜ 233  may be included for synchronizing each first time when each of signals SIG 1 ˜SIG 3  is applied to each of the signal lines  261 ˜ 263  or the I/O terminals  251 ˜ 253  with a second time when a noise cancelling signal NCS generated from the noise cancelling signal generator  230  is applied to each of the signal lines  261 ˜ 263  or the I/O terminals  251 ˜ 253 . The delay units  231 ˜ 233  may have different delay times with respect to each other, the first time and the second time may be different. 
         [0044]    Each of the drivers  241 ˜ 243  may be an output driver commonly employed in a semiconductor device, and each of the drivers  241 ˜ 243  amplifies an input signal and applies the amplified signal to a signal line connected to an I/O terminal. The noise cancelling signal generator  230  performs noise cancellation, for example, by detecting the signal SIG 2  transmitted through the signal lines  222  and  263  from the signal output circuit  212  to the I/O terminal  252 , and generating noise cancelling signal NCS. Such noise cancelling signal NCS is applied to the adjacent signal lines for cancelling the noise induced in these other signal lines ( 221  and  261  and  223  and  263 ) or the I/O terminals  251  and  253  through a signal line  270 . 
         [0045]      FIG. 4  is a waveform diagram illustrating various signals output from the circuits of  FIG. 3 . 
         [0046]    In  FIG. 4 , (a) illustrates a signal, from each of the signal output circuits  211 ˜ 213 , to be applied to each of the I/O terminals  251 ˜ 253  without being influenced by the noise. 
         [0047]    In  FIG. 4 , (b) illustrates a noise such as a coupling noise or a crosstalk noise which is induced in the signal lines  221  and  261  and  223  and  263  due to the signal SIG 2  in the signal line  222  and  226 . 
         [0048]    In  FIG. 4 , (c) illustrates a signal, from each of the signals SIG 1  and SIG 2  in each of the signal lines  221  and  261  and  223  and  263 , to be applied to each of the I/O terminals  251 ˜ 253  as affected by noise due to the presence of signal SIG 2  in the signal line  222  and  226 . It is noted that when the signal in (a) is influenced by the noise in (b), the signal is distorted as shown in (c) and may be outputted through each of the I/O terminals  251 ˜ 253 . In some instances wherein the noise signal is severe, the distorted signal may be transmitted and received incorrectly. 
         [0049]    In  FIG. 4 , (d) illustrates a noise cancelling signal NCS applied to the signal lines  261  and  263  after the noise cancelling signal NCS is amplified in the driver  244 . When the noise cancelling signal NCS has a phase difference of about 180° with respect to the noise in (b), the noise may be entirely cancelled by the noise cancelling signal NCS. When the noise cancelling signal NCS in (d) is applied to the adjacent signal lines  261  and  263 , the noise in (b) induced in the adjacent signal lines  261  and  263  may be cancelled. Therefore, the signal (a) may be outputted through each of the I/O terminals  251 ˜ 253  without distortion from the noise. 
         [0050]      FIG. 5  is a block diagram of signal output circuits connected to a noise cancelling signal generator according to other example embodiments. 
         [0051]    Referring to  FIG. 5 , a semiconductor device  300  includes a plurality of signal output circuits  311 ˜ 313 , noise cancelling signal generators  330  and  340 . Each of the signal output circuits  231 ˜ 313  outputs each of signals SIG 1 ˜SIG 3 , and each of the noise cancelling signal generators  330  and  340  generates each of noise cancelling signals NCS 1  and NCS 2 . Each of the signal output circuits  311 ˜ 313  is connected to each of I/O terminals  361 ˜ 363  through respective signal lines  321  and  371 ,  322  and  372  and  323  and  373 . The signal SIG 1  is transferred to the I/O terminal  361  via the signal line  321 , a driver  351  and the signal line  371 . The signal SIG 2  is transferred to the I/O terminal  362  via the signal line  322 , a delay unit  331 , a driver  353  and the signal line  372 . The signal SIG 3  is transferred to the I/O terminal  363  via the signal line  323 , a delay unit  332 , a driver  354  and the signal line  373 . 
         [0052]    The noise cancelling signal generator  330  generates the noise cancelling signal NCS 1  for cancelling noises induced in other signal lines ( 321  and  371  and  323  and  373 ) due to the signal SIG 2  in the signal lines  322  and  372  and applies the noise cancelling signal NCS 1  to the adjacent signal lines ( 371  and  373 ) via the driver  352 . The noise cancelling signal generator  340  generates the noise cancelling signal NCS 2  for cancelling noises induced in other signal lines ( 322  and  372  and  322  and  372 ) due to the signal SIG 3  and applies the noise cancelling signal NCS 2  to the adjacent signal lines ( 372  and  371 ) via the driver  355 . 
         [0053]    The example embodiment of  FIG. 5  is different from the example embodiment of  FIG. 3  in that the example embodiment of  FIG. 5  further includes the noise cancelling signal generator  340 , and the signal SIG 1  on the signal line  321  is directly applied to the driver  351  without passing through a delay unit. As shown in  FIG. 5 , the signal SIG 1  on the signal line  321  is applied to the I/O terminal  361  without passing through a delay unit. As such, the signal SIG 1  applied to the I/O terminal  361  may not be synchronized with a the signals SIG 2  and SIG 3  when they are applied to the I/O terminals  362  and  363 . An additional delay unit may be placed in the signal line  321  for synchronization. In  FIG. 5 , the noise cancelling signal NCS 1  for cancelling noises induced in other signal lines ( 321  and  371  and  323  and  373 ) due to the signal SIG 2  in the signal lines  322  and  372  is applied to the adjacent signal lines ( 371  and  373 ), and the noise cancelling signal NCS 2  for cancelling noises induced in other signal lines ( 322  and  372  and  322  and  372 ) due to the signal SIG 3  is applied to the adjacent signal lines ( 372  and  371 ). Therefore, the noise cancelling signals NCS 1  and NCS 2  are applied to the signal line  371  to cancel the noise induced due to the adjacent signal lines. 
         [0054]      FIGS. 6A and 6B  are block diagrams illustrating a noise cancelling signal generator according to some example embodiments. The noise cancelling signal generator may include a transition detection unit as illustrated in  FIG. 6A , or the noise cancelling signal generator may filter the signal to generate the noise cancelling signal. 
         [0055]      FIG. 6A  is a block diagram of a noise cancelling signal generator according to some example embodiments. 
         [0056]    Referring to  FIG. 6A , a noise cancelling signal generator  400   a  includes a transition detection unit  410  and a cancelling signal generation unit  415 . The transition detection unit  410  detects a transition of a signal SIG and provides an enable signal EN which is activated when the transition of the signal SIG occurs. According to some embodiments, the signal SIG is the SIG 1  signal that appears on the signal lines  131 ,  221 , and  321  in  FIGS. 2 ,  3 , and  5 . The transition detection unit  410  provides the cancelling signal generation unit  415  with the enable signal EN which is activated when the signal SIG transitions from a logic high level to a logic low level or from a logic low level to a logic high level. The cancelling signal generation unit  415  is enabled by the enable signal EN to generate the noise cancelling signal NCS. 
         [0057]    As described above and in connection with  FIG. 4 , when the signal SIG transitions, the noise such as crosstalk noise or coupling noise such as a signal shown in  FIG. 4   b  is induced in the adjacent signal lines. The cancelling signal generation unit  415  generates a noise cancelling signal NCS that has a phase difference of about 180° with respect to the noise signal, as appears substantially as shown in  FIG. 4   d.    
         [0058]      FIG. 6B  is a block diagram illustrating a noise cancelling signal generator according to other example embodiments. 
         [0059]    Referring to  FIG. 6B , a noise cancelling signal generator  400   b  includes delay units  421 ,  422 , amplifiers  423 ,  424  and  425  and a summer  426 . The amplifier  423  has a gain (or coefficient) of n (n is a real number which is not zero), the amplifier  424  has a gain (or coefficient) of m (m is a real number which is not zero), and the amplifier  425  has a gain (or coefficient) of k (k is a real number which is not zero). The signal SIG is amplified by the amplifier  423 , and is provided to the summer  426 . The signal SIG is delayed by the delay unit  421 , and then is amplified by the amplifier  424 , and then is provided to the summer  426 . As a further option, the signal SIG delayed by the delay unit  421  is further delayed by delay unit  422 , and then is amplified by the amplifier  425 , and then is provided to the summer  426 . The summer  426  sums outputs of the amplifiers  423 ,  424  and  425  to provide the noise cancelling signal NCS. According to at least one embodiment, the noise cancelling signal NCS is provided to the signal lines except the signal line which carries the signal SIG 1 . Delay times of the delay units  421  and  422  and the gains (coefficients) of the amplifiers  423 ,  424  and  425  are adjustable, and thus, a magnitude and a phase of the noise cancelling signal SIG may be set as desired. According to another embodiment of the present inventive concept, the delay unit  422  and amplifier  425  may not be needed if adjustment of the delay unit  421  and amplifier  424  suffices to produce the noise cancelling signal NCS to cancel the noise signal to within a predetermined level. 
         [0060]      FIG. 7  is a flow chart illustrating a training method of a semiconductor memory device according to some example embodiments. 
         [0061]    In a training method of a semiconductor memory device of  FIG. 7 , a noise such as crosstalk noise which is induced in signal lines is measured and gains (coefficients) of at least one amplifier or at least one delay unit included in the noise cancelling generator or gains (coefficients) of delay units connected to signal lines are adjusted such that the noise induced in adjacent signal lines may be minimized. Although in  FIG. 7 , the crosstalk noise is presented, the training method of  FIG. 7  is applicable to a coupling or other noise as well. 
         [0062]    Hereinafter, the training method of a semiconductor memory device will be explained with reference to  FIGS. 2 through 7 . 
         [0063]    When the signal output circuit  212  outputs the signal SIG 2  through the signal line  222 , a crosstalk noise is generated in the signal lines  221  and  223  (S 510 ). The crosstalk noise generated in the signal lines  221  and  223  is measured (S 520 ). Coefficients (delay times) of the delay units  231 ,  232 ,  233  connected to the signal lines  221 ,  222  and  223  are adjusted or coefficients of the amplifiers  423 ,  424  and  425  and/or delay units  421  and  422  are adjusted (S 530 ). Delay times of the delay units  231 ,  232 ,  233  are adjusted such that the induced crosstalk is minimized. The crosstalk noise induced in the signal lines  221  and  223  is measured (S 540 ). If the measured noise value is not within an acceptable range (NO in S 550 ), the adjustment, measurement, and test steps (S 530 ,  5540 ,  5550 ) are repeated, until when a preset maximum repetition number is reached (S 560 ). When the measured noise value is within an acceptable range (YES in S 550 ), the training is completed. 
         [0064]      FIG. 8  illustrates a memory system having signal output circuits and noise cancelling signal generators according to some example embodiments. 
         [0065]    Referring to  FIG. 8 , a memory system  600  includes a control unit  605  and a memory device  650 . The control unit  605  includes a signal output circuit  610  and noise cancelling signal generators  621  and  625 , and the memory device  650  includes a signal output circuit  660  and a noise cancelling signal generator  670 . The signal output circuit  610  outputs a signal SIG 1  to be provided to I/O terminal  642  through a signal line  611 . The signal output circuit  610  is connected to two noise cancelling signal generators  621  and  625 . 
         [0066]    The noise cancelling signal generator  621  applies a noise cancelling signal NCS 1  for cancelling a noise induced due to the signal SIG 1  to the I/O terminals  641  and  643  or to signal lines (not illustrated) connected to the I/O terminals  641  and  643  through a signal line  631 . The noise cancelling signal generator  625  applies a noise cancelling signal NCS 2  for cancelling a noise induced due to the signal SIG 1  to the I/O terminals  644 ,  645  and  646  or to signal lines (not illustrated) connected to the I/O terminals  644 ,  645  and  646  through a signal line  632 . 
         [0067]    In  FIG. 8 , signal lines and signal output circuits can be connected to I/O terminals  691 ,  692 ,  693 ,  695 , and  696  but are not illustrated for the sake of convenience. The signal output circuit  660  outputs a signal SIG 2  to be provided to I/O terminal  694  through a signal line  661 . The noise cancelling signal generator  670  applies a noise cancelling signal NCS 3  for cancelling a noise induced due to the signal SIG 3  to the I/O terminals  691 ,  692 ,  693 ,  695 , and  696  or to signal lines (not illustrated) connected to the I/O terminals  691 ,  692 ,  693 ,  695 , and  696  through a signal line  681 . Each of the I/O terminals  641 ˜ 646  of the control unit  605  is connected to the respective I/O terminals  691 ˜ 696  of the memory device  650  through respective channels CH 1 ˜CH 6 . 
         [0068]    In  FIG. 8 , two noise cancelling signal generators  621  and  625  respectively apply the noise cancelling signals NCS 1  and NCS 2  to respective corresponding signal lines according to intensity of the induced noise in the signal lines, because the intensity of the induced noise may be different according to a relative distance between the signal line  611  (noise source) and each of the adjacent signal lines (not illustrated). 
         [0069]      FIG. 9  illustrates another memory system having signal output circuits and noise cancelling signal generators according to other example embodiments. 
         [0070]    Referring to  FIG. 9 , a memory system  700  includes a control unit  705  and a memory device  750 . The control unit  705  includes a signal output circuit  710  and noise cancelling signal generators  721  and  725 , and the memory device  750  includes a signal output circuit  760  and noise cancelling signal generators  771 ˜ 775 . The signal output circuit  710  outputs a signal SIG 1  to be provided to I/O terminal  742  through a signal line  711 . In  FIG. 9 , signal lines and signal output circuits connected to I/O terminals  741 ,  743 ,  744 ,  745  and  746  are not illustrated for the sake of convenience. 
         [0071]    The signal output circuit  710  is connected to two noise cancelling signal generators  721  and  725 . The noise cancelling signal generator  721  applies a noise cancelling signal NCS 1  for cancelling a noise induced due to the signal SIG 1  to the I/O terminals  741  and  743  or to signal lines (not illustrated) connected to the I/O terminals  741  and  743  through a signal line  731 . The noise cancelling signal generator  725  applies a noise cancelling signal NCS 2  for cancelling a noise induced due to the signal SIG 1  to the I/O terminals  744 ,  745  and  746  or to signal lines (not illustrated) connected to the I/O terminals  744 ,  745  and  746  through a signal line  732 . 
         [0072]    In  FIG. 9 , signal lines and signal output circuits connected to I/O terminals  791 ,  792 ,  793 ,  795 , and  796  is not illustrated for the sake of convenience. The signal output circuit  760  outputs a signal SIG 2  to be provided to I/O terminal  794  through a signal line  761 . The signal output circuits  760  is connected to the noise cancelling signal generators  771 ˜ 775 . Each of the noise cancelling signal generators  771 ˜ 775  applies each of noise cancelling signals NCS 3 ˜NCS 7  for cancelling noise induced due to the signal SIG 2  to each of the I/O terminals  791 ,  792 ,  793 ,  795 , and  796  or to signal lines (not illustrated) connected to the I/O terminals  791 ,  792 ,  793 ,  795 , and  796  through respective signal lines  781 ,  782 ,  783 ,  784  and  785 . Each of the I/O terminals  741 ˜ 746  of the control unit  705  is connected to the respective I/O terminals  791 ˜ 796  of the memory device  750  through respective channels CH 1 ˜CH 6 . 
         [0073]    In  FIG. 9 , the control unit  705  has a same configuration as the control unit  605  in  FIG. 8 , and the memory device  750  is different from the memory device  650  in  FIG. 8  in that each of the noise cancelling signal generators  771 ˜ 775  applies each of noise cancelling signals NCS 3 ˜NCS 7  for cancelling noise that may be differently induced due to the signal SIG 2  on each of the I/O terminals  791 ,  792 ,  793 ,  795 , and  796 . This is because intensity of the induced noise may be different according to a relative distance between the signal line  761  (noise source) and each of the signal lines  781 ,  782 ,  783 ,  784  and  785 . 
         [0074]      FIG. 10  illustrates still another memory system having signal output circuits and noise cancelling signal generators. 
         [0075]    Referring to  FIG. 10 , a memory system  800  includes a control unit  805  and a memory device  850 . The control unit  805  includes a signal output circuit  810  and noise cancelling signal generators  821  and  823 , and the memory device  850  includes signal output circuits  861  and  862  and a noise cancelling signal generator  870 . The signal output circuit  811  outputs a signal SIG 1  to be provided to I/O terminal  842  through a signal line  813 . The signal output circuit  812  outputs a signal SIG 2  to be provided to I/O terminal  844  through a signal line  814 . In  FIG. 10 , signal lines and signal output circuits connected to I/O terminals  841 ,  843 ,  84  and  846  are not illustrated for the sake of convenience. 
         [0076]    The signal output circuit  811  is connected to two noise cancelling signal generators  821  and  822 . In addition, the signal output circuit  812  is connected to two noise cancelling signal generators  821  and  822 . The noise cancelling signal generator  821  applies a noise cancelling signal NCS 1  for cancelling a noise induced due to the signal SIG 1  in the signal line  813  and a noise induced due to the signal SIG 2  in the signal line  814  to the I/O terminals  841  and  843  or to signal lines (not illustrated) connected to the I/O terminals  841  and  843  through a signal line  831 . The noise cancelling signal generator  822  applies a noise cancelling signal NCS 2  for cancelling a noise induced due to the signal SIG 1  in the signal line  813  and a noise induced due to the signal SIG 2  in the signal line  814  to the I/O terminals  845  and  845  or to signal lines (not illustrated) connected to the I/O terminals  845  and  846  through a signal line  832 . 
         [0077]    The signal output circuit  861  in the memory device  850  outputs a signal SIG 3  to be provided to I/O terminal  892  through a signal line  863 . The signal output circuit  862  in the memory device  850  outputs a signal SIG 4  to be provided to I/O terminal  894  through a signal line  864 . In  FIG. 10 , signal lines and signal output circuits connected to I/O terminals  891 ,  893 ,  895 , and  896  is not illustrated for the sake of convenience. The signal output circuits  861  and  862  are connected to the noise cancelling signal generator  870 . The noise cancelling signal generator  870  applies a noise cancelling signal NCS 3  for cancelling a noise induced due to the signal SIG 3  in the signal line  863  and due to the signal SIG 4  in the signal line  864  to the I/O terminals  891 ,  893 ,  895  and  896  or to signal lines (not illustrated) connected to the I/O terminals  891 ,  893 ,  895  and  896  through a signal line  881 . Each of the I/O terminals  841 ˜ 846  of the control unit  805  is connected to the respective I/O terminals  891 ˜ 896  of the memory device  850  through respective channels CH 1 ˜CH 6 . 
         [0078]    In  FIG. 10 , the control unit (or interface)  805  includes the signal output circuits  811  and  813 , and each of the signal output circuits  811  and  813  is connected to the respective noise cancelling signal generators  821  and  822 . The noise cancelling signal generator  821  generates and applies the noise cancelling signal NCS 1  for cancelling the noise induced in the adjacent signal lines due to the signal SIG 1  to the I/O terminals  841  and  843  or to signal lines (not illustrated) connected to the I/O terminals  841  and  843 . The noise cancelling signal generator  822  generates and applies the noise cancelling signal NCS 2  for cancelling the noise induced in the adjacent signal line due to the signal SIG 2  to the I/O terminals  845  and  846 . 
         [0079]    In  FIG. 10 , the memory device (or interface)  850  includes the noise cancelling signal generator  870  which generates the noise cancelling signal NCS 3  to the adjacent signal lines such that an influence due to the noise may be canceled or reduced. 
         [0080]    As illustrated in  FIGS. 8 ,  9  and  10 , configuration and connection relationship of the control unit and the memory device in the semiconductor device may be varied according to various example embodiments. 
         [0081]    As mentioned above, when a signal is transmitted via one signal line, noise induced in other signal lines due to the transmitted signal may be cancelled by a noise cancelling signal, and thus, signal distortion may be prevented. Therefore, noise characteristics and signal integrity may be enhanced. 
         [0082]    The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.

Technology Category: 3