Patent Document

TECHNICAL FIELD 
     The present disclosure generally relates to electronic circuit technology, in particularly to a reference power supply circuit. 
     TECHNICAL BACKGROUND 
     A reference source can generate a reference voltage (VREF) and/or a reference current which is independent of power supply and techniques and have an assured temperature characteristic regards of the temperature varies. It would be a criteria to provide a reference source with a low temperature coefficient (TC), low power dissipation and high power supply rejection ratio (PSRR) in the design of integrate circuits, such as an analog-digital converter (ADC), a digital-analog converter (DAC), a dynamic random access memory (DRAM) and a flash memory. 
     Referring to  FIG. 1 , a bandgap reference power supply circuit which may carry a curvature compensation for the temperature characteristic. In the power supply circuit, a branch current flowing through a triode Q 01  and a branch current flowing through a triode Q 02  are positive proportional to absolute temperature (PTAT) currents, while a branch current flowing through resistors R 01  and R 02  and a branch current flowing through resistors R 03  and R 04  are negative PTAT currents. Due to the positive and negative PTAT current compensation, the reference voltage VREF has a well temperature drift characteristic. However, the reference voltage may not be very precise because a plurality of resistors is incorporated in the circuit. In case there is a variation in the fabrication process, particularly when the range of the machining angle is exceeded, the resistance of the resistors varies in a rather wide range, such that a significant deviation of the slope for the positive PTAT current to the negative PTAT current occurs, which further leads to the increasing of the PTAT and a lower precised VREF, thus cutting down the performance of the bandgap reference power supply circuit. 
     One solution for the problems described above is to carry out a second-order curvature compensation for the temperature characteristic to improve the precision of a VREF. Referring to  FIG. 2 , a bandgap reference power supply circuit with second-order curvature compensation adopting PTAT voltage compensation method is shown. The power supply circuit includes two bandgap reference voltage sources. A first bandgap reference voltage source includes triodes Q 1 , Q 2 , Q 3  and Q 4  and resistors R 1 , R 2  and R 3 , for generating a PTAT current I PTAT . A second bandgap reference voltage source includes triodes Q 5 , Q 6 , Q 7  and Q 8  and resistors R 4 , R 5  and R 6 , for generating a reference voltage Vref of the first-order temperature compensation. 
     Referring to  FIG. 2 , when a voltage between a base and an emitter of a triode Q 10  is lower than its on-state voltage, the two bandgap reference voltage sources are disconnected, and the output reference voltage Vref refers to 
               Vref   =       V     BE   ⁢           ⁢   6       +           V   T     ⁢   ln   ⁢           ⁢     n   2         R   4       ⁢     (       R   4     +     2   ⁢     R   5       +     2   ⁢     R   6         )           ,         
in which V BE6  indicates the voltage between a base and an emitter of the triode Q 6 .
 
     When the voltage between the base and the emitter of the triode Q 10  is higher than its on-state voltage, both of the two bandgap reference voltage sources are communicated and the current I PTAT  flowing through the triode Q 10  can be referred as I PTAT =V T  ln n 1 /R 1 , therefore, the output reference voltage Vref is 
     
       
         
           
             Vref 
             = 
             
               
                 V 
                 
                   BE 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   6 
                 
               
               + 
               
                 
                   
                     
                       V 
                       T 
                     
                     ⁢ 
                     ln 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       n 
                       2 
                     
                   
                   
                     R 
                     4 
                   
                 
                 ⁢ 
                 
                   ( 
                   
                     
                       R 
                       4 
                     
                     + 
                     
                       2 
                       ⁢ 
                       
                         R 
                         5 
                       
                     
                     + 
                     
                       2 
                       ⁢ 
                       
                         R 
                         6 
                       
                     
                   
                   ) 
                 
               
               + 
               
                 
                   
                     
                       V 
                       T 
                     
                     ⁢ 
                     ln 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       n 
                       1 
                     
                   
                   
                     R 
                     1 
                   
                 
                 ⁢ 
                 
                   
                     R 
                     6 
                   
                   . 
                 
               
             
           
         
       
     
     The triode Q 10  is conducted at a predetermined temperature T 0 , and is cut off when the temperature is lower than T 0 . The currents flowing through the resistors R 3  and R 6  both are the PTAT currents, which increased as the temperature rises. When the temperature is lower than T 0 , a voltage V BE10  between the base and the emitter of the triode Q 10  is: 
                 V     BE   ⁢           ⁢   10       =       2   ⁢         V   T     ⁢   ln   ⁢           ⁢     n   1         R   1       ⁢     R   3       -     2   ⁢         V   T     ⁢   ln   ⁢           ⁢     n   2         R   4       ⁢     R   6           ,         
in which n 1 =S Q2 /S Q1 , n 2 =S Q6 /S Q5 , V T  is a threshold voltage, and S Q1 , S Q2 , S Q5  and S Q6  indicate the cross section areas of the triodes Q 1 , Q 2 , Q 5  and Q 6 , respectively. Accordingly, when n 1 =n 2  and (R 3 /R 1 −R 6 /R 4 )&gt;0, V BE10  is increased as the temperature rises. When the temperature equals to T 0 , V BE10  is equal to the on-state voltage of Q 10 .
 
     However, the bandgap reference power supply circuit in  FIG. 2  has the following problems: (1) there is also a plurality of resistors adopted, when a deviation is caused by variation of the fabrication process, the the resistance of the resistors would widely differs, such that the error coming from the circuit itself may exceed the precision of the second-order curvature compensation, resulting in the failure of the second-order curvature compensation; (2) when the resistance of the resistor R 16  wide varies, the triode Q 10  may fail to be conducted or there would be an offset for its on-state temperature point; (3) the PSRR performance of the circuit in high frequency section may become worse and therefore could not be incorporated in a high frequency analog circuits (for example, a high-speed ADC circuit); (4) the topological structure of the circuit is relatively complicated. 
     SUMMARY 
     A reference power supply circuit includes: 
     an adjustable resistance network including a first resistor end and a second resistor end, the resistance between the first resistor end and the second resistor end varies with a process deviation; 
     a bandgap reference power supply circuit connected the first resistor end with the second resistor end, for generating a positive proportional to absolute temperature current flowing through the first resistor end and the second resistor end and for outputting a reference voltage related to the positive proportional to absolute temperature current. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic drawing of a bandgap reference power supply circuit incorporating a curvature compensation; 
         FIG. 2  is a schematic drawing of a bandgap reference power supply circuit with a second-order curvature compensation; 
         FIG. 3  is a schematic drawing of a reference power supply circuit according to an exemplary embodiment of the present disclosure; 
         FIG. 4  is a schematic diagram for comparing a simulation curve of PSRR characteristic of the reference power supply circuit shown in  FIG. 3  and a simulation curve of PSRR characteristic of a reference power supply circuit without a compensation capacity. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 3  is a schematic drawing of the reference power supply circuit according to an exemplary embodiment, in which the reference power supply circuit at least includes an adjustable resistance network  12  and a bandgap reference power supply circuit  13 . 
     The adjustable resistance network  12  includes a first resistor end P 1  and a second resistor end P 2 , and the resistance between the first resistor end P 1  and the second resistor end P 2  can vary with the process deviation. 
     The adjustable resistance network  12  of the embodiment includes three sets of selection unit having identical structures for selecting resistors from those with different resistances to be connected, according to an input control signal. Each set of selection unit includes a resistor, two switch NMOS transistors. A pair of control signals being inversed with respect to each other may be applied to the selection unit. Specifically, the first set of the selection unit includes a first resistor R 11 , a first switch NMOS transistor M 1 , a second switch NMOS transistor M 2 ; the second set of selection unit includes a second resistor R 12 , a third switch NMOS transistor M 3 , a fourth switch NMOS transistor M 4 ; the third set of selection unit includes a third resistor R 13 , a fifth switch NMOS transistor M 5 , a sixth switch NMOS transistor M 6 . The pair of control signals that might be applied to the first set of selection unit is a first control signal A and a first inversed control signal ˜A; the pair of control signals that might be applied to the second set of selection unit is a second control signal B and a second inversed control signal ˜B; and the pair of control signals that might be applied to the third set of selection unit is a third control signal C and a third inversed control signal ˜C. 
     For the first switch NMOS transistor M 1 , the first control signal A is connected at the gate, the drain is connected with the first resistor end P 1  and the source is connected with a first end of the first resistor R 11 . 
     For the second switch NMOS transistor M 2 , the first inversed control signal ˜A is fed at the gate, the drain thereof is connected with the first resistor end P 1  and the source is connected with a second end of the first resistor R 11 . 
     For the third switch NMOS transistor M 3 , the second control signal B is connected at the gate, the drain is connected with the second end of the first resistor R 11  and the source is connected with a first end of the second resistor R 12 . 
     For the fourth switch NMOS transistor M 4 , the second inversed control signal ˜B is coupled at the gate, the drain is connected with the second end of the first resistor R 11  and the source is connected with a second end of the second resistor R 12 . 
     For the fifth switch NMOS transistor M 5 , the third control signal C is coupled at the gate, the drain is connected with the second end of the second resistor R 12  and the source is connected with a first end of the third resistor R 13 . 
     For the sixth switch NMOS transistor M 6 , the third inversed control signal ˜C is connected at the gate, the drain is connected with the second end of the second resistor R 12  and the source is connected with a second end of the third resistor R 13  and the second resistor end P 2 . 
     The switch MOS transistors in the adjustable resistance network  12  may degrade the PSRR performance of the reference power supply circuit. Therefore, in practice, according to the actual technique situation, the switch NMOS transistors might be fabricated to have large area to reduce the influence on the PSRR performance. Moreover, the on-state resistance of the switch NMOS transistors might be less than 5% of the resistances of the resistors connected in series therewith. In detail, the on-state resistances of the first NMOS transistor M 1  and the second NMOS transistor M 2  are less than 5% of the resistance of the first resistor R 11 , the on-state resistances of the third NMOS transistor M 3  and the fourth NMOS transistor M 4  are less than 5% of the resistance of the second resistor R 12 , and the on-state resistances of the fifth NMOS transistor M 5  and the sixth NMOS transistor M 6  are less than 5% of the resistance of the third resistor R 13 . 
     The first control signal A, the second control signal B and the third control signal C might be set according to actual process deviation. The switch NMOS transistors are controlled to be on-state or off-state by the control signals, so as to get different combinations of the resistances between the first resistor end P 1  and the second resistor end P 2  of the adjustable resistance network  12 . In the present embodiment, the corresponding relationship between the logic value of the control signals and resistance R 0  between the first resistor end P 1  and the second resistor end P 2  is shown in table 1, which is: 
     
       
         
               
               
               
               
               
               
             
           
               
                   
               
               
                   
                 No. 
                 A 
                 B 
                 C 
                 R 0   
               
               
                   
               
             
             
               
                   
                 (1) 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 (2) 
                 0 
                 0 
                 1 
                 R 13   
               
               
                   
                 (3) 
                 0 
                 1 
                 0 
                 R 12   
               
               
                   
                 (4) 
                 0 
                 1 
                 1 
                 R 12  + R 13   
               
               
                   
                 (5) 
                 1 
                 0 
                 0 
                 R 11   
               
               
                   
                 (6) 
                 1 
                 0 
                 1 
                 R 11  + R 13   
               
               
                   
                 (7) 
                 1 
                 1 
                 0 
                 R 11  + R 12   
               
               
                   
                 (8) 
                 1 
                 1 
                 1 
                 R 11  + R 12  + R 13   
               
               
                   
               
             
          
         
       
     
     In the present embodiment, the relation of the resistance R 11  of the first resistor R 11 , the resistance R 12  of the first resistor R 12  and the resistance R 13  of the first resistor R 13  is R 12 &gt;R 13 &gt;R 11 , such that the adjustable range of the resistance between the first resistor end P 1  and the second resistor end P 2  could be increased. 
     The resistance R 0  is corresponding to “(3)” in table 1, when there is no process deviation. 
     When the integrated resistance of the resistors in the circuit is relatively high duo to the process deviation (for example, the process corner deviating from tt to ss), there are three ways for reducing the resistance R 0 , which are: 
     (A1) turning off the first switch NMOS transistor M 1 , the third switch NMOS transistor M 3  and the fifth switch NMOS transistor M 5 , and turning on the second switch NMOS transistor M 2 , the fourth switch NMOS transistor M 4  and the sixth switch NMOS transistor M 6 , which are corresponding to the “(1)” in table 1; 
     (A2) turning off the first switch NMOS transistor M 1 , the third switch NMOS transistor M 3  and the sixth switch NMOS transistor M 6 , and turning on the second switch NMOS transistor M 2 , the fourth switch NMOS transistor M 4  and the fifth switch NMOS transistor M 5 , which are corresponding to the “(2)” in table 1; 
     (A3) turning off the second switch NMOS transistor M 2 , the third switch NMOS transistor M 3  and the fifth switch NMOS transistor M 5 , and turning on the first switch NMOS transistor M 1 , the fourth switch NMOS transistor M 4  and the sixth switch NMOS transistor M 6 , which are corresponding to the “(5)” in table 1; 
     When the integrated resistance of the resistors in the circuit is relatively low duo to the process deviation (for example, the process corner deviating from tt to ff), there are three ways for increasing the resistance R 0 , which are: 
     (B1) turning off the first switch NMOS transistor M 1 , the fourth switch NMOS transistor M 4  and the sixth switch NMOS transistor M 6 , and turning on the second switch NMOS transistor M 2 , the third switch NMOS transistor M 3  and the fifth switch NMOS transistor M 5 , which are corresponding to the “(4)” in table 1; 
     (B2) turning off the second switch NMOS transistor M 2 , the fourth switch NMOS transistor M 4  and the fifth switch NMOS transistor M 5 , and turning on the first switch NMOS transistor M 1 , the third switch NMOS transistor M 3  and the sixth switch NMOS transistor M 6 , which are corresponding to the “(7)” in table 1; 
     (B3) turning off the second switch NMOS transistor M 2 , the fourth switch NMOS transistor M 4  and the sixth switch NMOS transistor M 6 , and turning on the first switch NMOS transistor M 1 , the third switch NMOS transistor M 3  and the fifth switch NMOS transistor M 5 , which are corresponding to the “(8)” in table 1. 
     “(6)” in table 1 can be a method for reducing or increasing the resistance R 0  which depends on whether the “(R 11 +R 13 )” is greater than R 0 . 
     It should be understood by those skilled in the art that, according to corresponding relationship among the process deviation, the control signal and the resistance R 0  described above, the first control signal A, the second control signal B and the third control signal C can be obtained by adopting a digital circuit design (for example, a decoding circuit), and thus the circuit for generating the first control signal A, the second control signal B and the third control signal C will not be described in detail herein. 
     The bandgap reference power supply circuit  13  of the embodiment includes a first PMOS transistor MP 1 , a second PMOS transistor MP 2 , a third PMOS transistor MP 3 , a fourth PMOS transistor MP 4 , a fifth PMOS transistor MP 5 , a sixth PMOS transistor MP 6 , an operational amplifier A 1 , a fourth resistor R 14 , a fifth resistor R 15 , a sixth resistor R 16 , a seventh resistor R 17 , a first NMOS transistor MN 1 , a second NMOS transistor MN 2 , a first PNP transistor QP 1 , and a second PNP transistor QP 2 . 
     For the first PMOS transistor MP 1 , the gate is connected with the output end of the operational amplifier A 1 , the source is connected with a reference voltage source VDD, and the drain is connected with the source of the third PMOS transistor MP 3 . 
     For the second PMOS transistor MP 2 , the gate is connected with the output end of the operational amplifier A 1 , the source is connected with the reference voltage source VDD, and the drain is connected with the source of the fourth PMOS transistor MP 4 . 
     For the third PMOS transistor MP 3 , the gate is connected with the output end of the operational amplifier A 1 , the source is connected with the drain of the first PMOS transistor MP 1 , and the drain is connected with the positive input end of the operational amplifier A 1 . 
     For the fourth PMOS transistor MP 4 , the gate is connected with the output end of the operational amplifier A 1 , the source is connected with the drain of the second PMOS transistor MP 2 , and the drain is connected with the negative input end of the operational amplifier A 1 . 
     A first end of the fourth resistor R 14  is connected with the drain of the third PMOS transistor MP 3 , and a second end thereof is connected with the first resistor end P 1  of the adjustable resistance network  12 . 
     A first end of the fifth resistor R 15  is connected with the drain of the third PMOS transistor MP 3 , and a second end thereof is grounded. 
     A first end of the sixth resistor R 16  is connected with the drain of the fourth PMOS transistor MP 4 , and a second end thereof is grounded. 
     For the first NMOS transistor MN 1 , a first bias voltage PD is inputted at the gate, the drain is connected with the second resistor end P 2  of the adjustable resistance network  12 , and a source is grounded. 
     For the second NMOS transistor MN 2 , the first bias voltage PD is inputted at the gate, the drain is connected with the drain of the fourth PMOS transistor MP 4 , and the source is grounded. 
     For the first PNP transistor QP 1 , the emitter is connected with the drain of the first NMOS transistor MN 1 , and the base and the collector are grounded. 
     For the second PNP transistor QP 2 , the emitter is connected with the drain of the second NMOS transistor MN 2 , and the base and the collector are grounded. 
     For the fifth PMOS transistor MP 5 , the gate is connected with the output end of the operational amplifier A 1 , the source is connected with the reference voltage source VDD, and the drain is connected with a source of the sixth PMOS transistor MP 6 . 
     For the sixth PMOS transistor MP 6 , the gate is connected with the output end of the operational amplifier A 1 , the source is connected with the drain of the fifth PMOS transistor MP 5 , and the drain is used as an output end of a reference voltage Vout. 
     A first end of the seventh resistor R 17  is connected with the drain of the sixth PMOS transistor MP 6 , and a second end thereof is grounded. 
     The adjustable resistance network  12  is connected in series between the fourth resistor R 14  and the first PNP transistor QP 1  of the bandgap reference power supply circuit  13 , and the current flowing through the adjustable resistance network  12  is the PTAT current. 
     When there is no process deviation, the first switch NMOS transistor M 1 , the fourth switch NMOS transistor M 4  and the fifth switch NMOS transistor M 5  are turned off, and the second switch NMOS transistor M 2 , the third switch NMOS transistor M 3  and the sixth switch NMOS transistor M 6  are turned on, the PTAT current flows through the second resistor R 12 . In this case, a best temperature drift characteristic is obtained and the top point of the TC characteristic curve situates at the middle point of the testing temperature range. 
     When the process deviation occurs, the PTAT current can be adjusted to be increased or decreased, in which: 
     when the integrated resistance of the resistors in the circuit are relatively high due to the process deviation (for example, the process corner deviating from tt to ss), the PTAT current can be adjusted by reducing the resistance R 0  in three ways which are respectively corresponding to the “(1)”, “(2)” or “(5)” in table 1, and thus the resistance of the adjustable resistance network  12  is reduced. In other words, the resistances of the resistors in the PTAT current branch of the bandgap reference power supply circuit  13  are reduced, therefore the PTAT current is increased and the top point of the TC characteristic curves can move towards the low temperature area; 
     When the integrated resistance of the resistors in the circuit are relatively low due to the process deviation (for example, the process corner deviating from tt to ff), the PTAT current can be adjusted by increasing the resistance R 0  in three ways which are respectively corresponding to the “(4)”, “(7)” or “(8)” in table 1, and thus the resistance of the adjustable resistance network  12  can be increased. In other words, the resistances of the resistors in the PTAT current branch circuit of the bandgap reference power supply circuit  13  are increased, therefore the PTAT current is decreased and the top point of the TC characteristic curves can move towards the high temperature area. 
     Therefore, the adjustable resistance network  12  can effectively inhibit the impact that the fluctuation of the fabrication process of the resistors, the BJTs, and the MOSs in the reference power supply circuit  13  have on the temperature drift characteristic of the reference voltage. 
     It is to be notated that the adjustable resistance network shall not be limited to the circuit structure described in the embodiment. In other exemplary embodiments, for example, a switch PMOS transistor can be used as the switch NMOS transistor, or one or more sets of selection unit can be added for increasing the adjustable range of the resistance. The bandgap reference power supply circuit shall not be limited to the circuit structure described in the embodiment. In other exemplary embodiment, other bandgap reference power supply circuits with curvature compensations could be used, and the resistors in the branch circuit, through which the PTAT current flows, of the bandgap reference power supply circuit can be substituted by the resistors in the adjustable resistance network  12 . In the case of the process change, the PTAT current can be adjusted by changing the resistance of the adjustable resistance network  12 , so as to improve the temperature drift characteristic of the output reference voltage and increase the precision and stability of the reference voltage. 
     The above-mentioned reference power supply circuit including the adjustable resistance network  12  and the bandgap reference power supply circuit  13  can provide the reference voltage with high precision and high stability for analog circuits, such as ADC, DAC, DRAM, Flash memory. However, in the case of high frequency analog circuits (such as a ADC of 10 bits and 100 MHz), the PSRR in high frequency condition can be improved by adding one pole in the PSRR transmission function for eliminating one zero point. Specifically, the PSRR characteristic of the reference power supply circuit in high frequency condition can be enhanced by adding a compensation circuit  14  to the output end of the bandgap reference power supply circuit  13 . 
     As shown in  FIG. 3 , in accordance with the exemplary embodiment, the reference power supply circuit further includes a compensation circuit  14  which is connected with the output end of the reference voltage for improving the PSRR characteristic of the reference voltage in high frequency condition. The compensation circuit  14  includes a compensation capacity C and a third NMOS transistor MN 3 , the compensation capacity C is connected in parallel with the seventh resistor R 17 , that is, a first end of the compensation capacity C is connected with the drain of the sixth PMOS transistor MP 6  and a second end thereof is grounded. For the third NMOS transistor MN 3 , the first bias voltage PD is coupled at the gate, the drain is connected with the drain of the sixth PMOS transistor MP 6  and the source is grounded. 
     The PSRR characteristic of the reference power supply circuit in high frequency can be improved by adding the compensation capacity C to the output end of the bandgap reference power supply circuit  13 . The principle could be: in case that reference power supply circuit does not include the compensation capacity C, the PSRR transmission function is H PSRR =H 0 ·(s−Z), in which s indicates the frequency and z indicates the frequency at the zero point. When the working frequency is higher than the frequency at the zero point, the PSRR will be increased with the increase of s. After adding the compensation capacity C, i.e., adding poles in the PSRR transmission function, the PSRR transmission function is 
                 H   PSRR     =       H   0     ·       (     s   -   Z     )       (     s   -   P     )           ,         
in which P indicates the frequency at the pole, and when P=Z, the pole eliminates the zero point, the transmission function is approximately a constant, thus inhibiting the increase of the PSRR in high frequency conditions.
 
       FIG. 4  is a schematic diagram for comparing a simulation curve “b” of the PSRR characteristic of a reference power supply circuit with a compensation capacity (in  FIG. 3 ) and a simulation curve “a” of the PSRR characteristic of a reference power supply circuit without a compensation capacity, and which are obtained by circuit simulation under the process conditions that VDD=1.8V, temp=27° C., and 0.18 μm Logic. Referring to the simulation curve “a”, PSRR (Y 0 ) is increased with the increasing of frequency, and the PSRR approximately approaches to 0 dB at a frequency of 1 GHz. Referring to the simulation curve “b”, in high frequency conditions (which is greater than 10 MHz), the PSRR becomes substantially stable to about −60 dB. Apparently by comparing the simulation curve “a” with the simulation curve “b”, in high frequency conditions, the PSRR characteristic of the reference power supply circuit with a compensation capacity is better than that of the reference power supply circuit without a compensation capacity. 
     The above-mentioned first bias voltage PD is applied on the gate of the NMOS transistor for ensuring the normal operations of the bandgap reference power supply circuit  13  and the compensation circuit  14 , and the first bias voltage PD can be preset according to the actual circuit structure, the fabrication process of NMOS transistor, ect., and also can be supplied by a starting circuit  11  as shown in  FIG. 3 . 
     As shown in  FIG. 3 , the reference power supply circuit of the embodiment further includes a starting circuit  11  which is connected with the bandgap reference power supply circuit  13  and the compensation circuit  14  for supplying the first bias voltage PD, thus ensuring that the bandgap reference power supply circuit  13  and the compensation circuit  14  can be operated at normal mode when the system is started (power on). 
     The starting circuit  11  includes an inverter  11   a , a seventh PMOS transistor MP 7 , an eighth PMOS transistor MP 8 , a ninth PMOS transistor MP 9 , a fourth NMOS transistor MN 4  and a first capacity C 1 . 
     A bias signal PDB is coupled at the input end of the inverter  11   a  and an inversed bias signal is output at the output end thereof, in which the inverter  11   a  has the first bias voltage PD. The inverter  11   a  is a CMOS inverter which includes a PMOS transistor and a NMOS transistor. 
     For the seventh PMOS transistor MP 7 , the gate is connected with the input end of the inverter  11   a  (i.e. inputting the bias signal PDB), the source is connected with the voltage source VDD and the drain is connected with the drain of the eighth PMOS transistor MP 8 . 
     For the eighth PMOS transistor MP 8 , the gate is connected with the output end of the operational amplifier A 1  of the bandgap reference power supply circuit  13 , the source is connected with the voltage source VDD and the drain is connected with the gate of the ninth PMOS transistor MP 9 . 
     For the ninth PMOS transistor MP 9 , the gate is connected with the drain of the eighth PMOS transistor MP 8 , the source is connected with the voltage source VDD and the drain is connected with the drain of the fourth PMOS transistor MP 4  of the bandgap reference power supply circuit  13 . 
     For the fourth NMOS transistor MN 4 , a second bias voltage VN is inputted at the gate, the drain is connected with the gate of the ninth PMOS transistor MP 9  and a source is grounded. 
     A first end of the first capacity C 1  is connected with the drain of the fourth NMOS transistor MN 4 , and a second end thereof is grounded. 
     It should be understood by those skilled in the art that the bias signal PDB and the second bias voltage VN provided for the starting circuit  11  can be preset according to the circuit structure and the MOS transistor fabrication process, which will not be described in detail herein. 
     Overall, in the reference power supply circuit described above, the adjustable design of the resistance in the branch circuit, through which the positive PTAT current flows, of the bandgap reference power supply circuit, is implemented by utilizing the adjustable resistance network, so that the fluctuating range of the resistance can meet the design requirement, and the adjustable design of the resistance of the adjustable resistance network is implemented by adopting a digital circuit, which is of simple structure and easy to be realized, so as to facilitate the adjustment and test of the circuit. 
     The above preferred embodiments are used to describe the present invention and are not tend to limit the present invention. Possible variations and modifications can be made by those skilled in the art without departing from the principle of the present invention. Accordingly, the scope of protection of the present invention is intended to be defined by the scope of the following claims.

Technology Category: 3