Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method for programming a plurality of memory cells of a nonvolatile semiconductor memory device. 
         [0003]    2. Description of the Related Art 
         [0004]    Semiconductor memory devices are devices in which data can be stored and from which stored data can be retrieved. Semiconductor memory devices can be classified into volatile memory and nonvolatile memory. The volatile memory needs a power supply to retain data while the nonvolatile memory can retain data even when power is removed. Therefore, nonvolatile memory devices have been widely used in applications in which power can be interrupted suddenly. 
         [0005]    Nonvolatile memory devices comprise electrically erasable and programmable ROM cells, known as flash EEPROM cells.  FIG. 1  shows a vertical cross-section of the flash EEPROM cell  10 . Referring to  FIG. 1 , a deep n-type well  12  is formed in a bulk region or a P-type substrate  11 , and a p-type well  13  is formed in the n-type well  12 . An N-type source region  14  and an N-type drain region  15  are formed in the P-type well  13 . A p-type channel region is formed between the source region  14  and the drain region  15 . A floating gate  17 , which is insulated by an insulating layer  16 , is formed on the P-type channel region. A control gate  19 , which is insulated by another insulating layer  18 , is formed on the floating gate  17 . 
         [0006]      FIG. 2  shows threshold voltages of the flash EEPROM cell  10  during program and erase operations. Referring to  FIG. 2 , the flash EEPROM cell  10  has a higher threshold voltage range (about 6 to 7V) during the program operation, and has a lower threshold voltage range (about 1 to 3V) during the erase operation. 
         [0007]    Referring to  FIGS. 1 and 2 , during the program operation, hot electrons need to be injected from the channel region adjacent to the drain region  15  to the floating gate electrode, so that the threshold voltage of the EEPROM cell increases. In contrast, during the erase operation, the hot electrons injected into the floating gate  17  during the program operation need to be removed, so that the threshold voltage of the EEPROM cell will decrease. Therefore, the threshold voltages of the EEPROM cell are varied after the program and erase operation. 
         [0008]      FIG. 3  shows a block diagram of a prior art nonvolatile semiconductor memory device  30 . Referring to  FIG. 3 , the memory device  30  comprises a memory array  32 , a column decode and level shift circuit  34 , a row decode and level shift circuit  36 , an I/O circuit  38 , and a pump circuit  39 . 
         [0009]      FIG. 4  shows a part of the memory array  32  of  FIG. 3 . Referring to  FIG. 4 , the memory array includes a plurality of word lines WL 0  to WL 2 , a plurality of bit lines BL 0  to BL 7 , and a plurality of memory cell transistors MX,Y arranged in the form of a matrix, wherein letters X and Y respectively stand for a cell position in the horizontal direction and a cell position in the vertical direction. The memory cell transistors MX,Y are connected to word lines in rows and to bit lines in columns. For example, a cell transistor M 1 , 1  has a drain connected to the first bit line BL 0  and has a gate connected to the first word line WL 0 , and a cell transistor M 1 , 2  has a drain connected to the second bit line BL 1  and has a gate connected to the first word line WL 0 . 
         [0010]    Referring now to  FIG. 3 , the I/O circuit  38  receives address signals ADDRESS, data signals DATA, and a clock signal XCLK from a processor or memory controller (not shown). The column decode and level shift circuit  34  receives a column address AC from the I/O circuit  38  for selecting a single bit line from the memory array  32 . The row decode and level shift circuit  36  receives a row address AR from the I/O circuit  38  for selecting a single word line from the memory array  32 . 
         [0011]    During a program operation, the pump circuit  39  receives a mode signal PGM from the I/O circuit  38  for generating pumped output voltages to the circuits  34  and  36 . In response to the column address AC, the circuit  34  provides the pumped output voltage to the selected bit line. In response to the row address AR, the circuit  36  provides the pumped output voltage to the selected word line. 
         [0012]      FIG. 5  shows a plot of voltage and current waveforms versus time of a typical prior art programming operation. Referring to  FIG. 4  and  FIG. 5 , four memory cell transistors M 1 , 1 , M 1 , 2 , M 1 , 3 , and M 1 , 4  in  FIG. 4  are selected to be programmed in response to a column address AC and a row address AR. At time t0, the pump circuit  39  generates a pumped output voltage VC having a level higher than a power supply VDD (e.g., 1.8VDC) and provides the high voltage (e.g., 4VDC) to the drains of the selected memory cell transistors through the bit lines. Upon receiving the pumped voltage VC, the total current IC flowing through the selected memory cell transistors increases to about 220 μA. The voltage VC is maintained at its high level until a time t1 is reached. At time t1, the total current IC flowing through selected memory cell transistors reduces to about 50 μA. After the time t1, the pump circuit  39  stops its operation, and a level of its output voltage VC drops to the power supply VDD. The time period t0 to t1 shown in  FIG. 5  is the pulse width, which is the effective time duration for the programming operation. In this example, the time period t0 to t1 is about 1 μS. 
         [0013]    As shown in  FIG. 5 , four memory cell transistors are selected to be programmed during the time period t0 to t1, so that the instant current of about 220 μA is required for the program operation. Presently, semiconductor memory devices have become highly integrated. More than tens of thousands of memory cells are integrated into a single semiconductor memory device so that much more data can be stored. To program a 16K-bit memory device comprising an array of 128×128 memory cells, relatively large amounts of power is required during the operation and the duration of the entire program can be rather long. In order to solve the foregoing problems, there is a need to provide an improved programming method. 
       SUMMARY OF THE INVENTION 
       [0014]    One aspect of the present invention is to provide a method for programming a plurality of memory cells of a nonvolatile semiconductor memory device. 
         [0015]    According to one embodiment of the present invention, the method comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals. 
         [0016]    Another aspect of the present invention is to provide a nonvolatile semiconductor memory device. 
         [0017]    According to one embodiment of the present invention, the nonvolatile semiconductor memory device comprises a plurality of memory cells divided into M number of groups, a decoder, and a timing circuit. The decoder successively selects each of the M number of groups. The timing circuit generates M number of successive overlapping pulse signals. The memory cells of the M number of groups are configured so as to be programmable in response to the respective M number of successive overlapping pulse signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    The invention will be described according to the appended drawings in which: 
           [0019]      FIG. 1  shows a vertical cross-section of a flash EEPROM cell; 
           [0020]      FIG. 2  shows threshold voltages of the flash EEPROM cell during program and erase operations; 
           [0021]      FIG. 3  shows a block diagram of a prior art nonvolatile semiconductor memory device; 
           [0022]      FIG. 4  shows a part of the memory array of  FIG. 3 ; 
           [0023]      FIG. 5  shows a plot of voltage and current waveforms versus time of a typical prior art programming operation; 
           [0024]      FIG. 6  shows a block diagram of a nonvolatile semiconductor memory device according to one embodiment of the present invention; 
           [0025]      FIG. 7  shows a part of the memory array of  FIG. 6 ; 
           [0026]      FIG. 8  is a block diagram showing an embodiment of the control circuit of  FIG. 6 ; 
           [0027]      FIG. 9  is a circuit diagram showing an embodiment of the timing circuit of  FIG. 6 ; 
           [0028]      FIG. 10  is a timing diagram showing an embodiment of an operation of the timing circuit of  FIG. 9 ; and 
           [0029]      FIG. 11  is a timing diagram showing an embodiment of an operation of the memory device during the programming operation. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0030]    In order to explain the method for programming a plurality of memory cells of a nonvolatile semiconductor memory device of the present invention, the nonvolatile semiconductor memory device that performs the method of the present invention will be described herein.  FIG. 6  shows a block diagram of a nonvolatile semiconductor memory device  60  according to one embodiment of the present invention. Referring to  FIG. 6 , the memory device  60  comprises the memory array  32 , the column decode and level shift circuit  34 , the row decode and level shift circuit  36 , and the I/O circuit  38  as shown in  FIG. 3 , and further comprises a control circuit  64 . 
         [0031]      FIG. 7  shows a part of the memory array  32  of  FIG. 6 . For the purpose of conciseness, the memory array  32  shown in  FIG. 7  comprising a single word line WL 0 , first to sixteenth bit lines BL 0  to BL 15 , and first to sixteenth memory cell transistors M 1 , 1  to M 1 , 16  is exemplified. However, the present invention is not limited to such a configuration. Referring to In another embodiment as shown in  FIG. 7 , the first to sixteenth memory cell transistors M 1 , 1  to M 1 , 16  are arranged in the form of a matrix, and each memory cell transistor is connected to the word line WL 0  and to one of the bit lines BL 0  to BL 15 . As shown in  FIG. 7 , the first to sixteenth memory cell transistors M 1 , 1  to M 1 , 16  are divided into first to fourth groups GROUP 1 , GROUP 2 , GROUP 3 , and GROUP 4 . In this embodiment, each of the groups is composed of four memory cell transistors. 
         [0032]    Referring now to  FIG. 6 , to program the first to sixteenth memory cell transistors M 1 , 1  to M 1 , 16  in the memory array  32 , the control circuit  64  generates a pumped output voltage VH to the column decode and level shift circuit  34  in response to a mode signal PGM issued from the I/O circuit  38 . During the program operation, the row decode and level shift circuit  36  selects one of the word lines from the memory array  32  in response to an address signal AR output form the I/O circuit  38 , and the column decode and level shift circuit  34  selects a plurality of bit lines from the memory array in response to an address signal AC output form the I/O circuit  38 . In this manner, the memory cells of the first to fourth groups GROUP 1 , GROUP 2 , GROUP 3 , and GROUP 4  are successively selected, and the pumped voltage VH is applied to the memory cells of the selected group through the selected bit lines. 
         [0033]      FIG. 8  is a block diagram showing an embodiment of the control circuit  64  of  FIG. 6 . Referring to  FIG. 8 , the control circuit  64  comprises a timing circuit  642  and a pump circuit  644 . The timing circuit  642  receives the mode signal PGM and an internal clock CLK synchronized with an external clock signal XCLK for generating a plurality of successive overlapping pulse signals PH 1 , PH 2 , PH 3 , and PH 4  during the program operation. The pump circuit  644  generates the pumped output voltage VH in response to the pulse signals PH 1 , PH 2 , PH 3 , and PH 4 , wherein the level of the voltage VH is higher than a power supply VDD when the pump circuit  644  is activated. In this embodiment, the pump circuit  644  is an internal circuit. In an alternative embodiment of the present invention, the pump circuit  644  may be implemented outsize the memory device  60  so as to minimize circuit size and complexity. 
         [0034]      FIG. 9  is a circuit diagram showing an embodiment of the timing circuit  642  of  FIG. 6 . Referring to  FIG. 9 , the timing circuit  642  comprises a logic circuit  6422  and a delay circuit  6424 . The logic circuit  6422  receives the clock signals CLK and the mode signal PGM for generating the first pulse signal PH 1 . The delay circuit  6424  is composed of three serial-connected D flip-flops D 1 , D 2 , and D 3 . The delay circuit  6424  is used to generate a plurality of delayed versions of the input signal PH 1  at a predetermined delay as successive overlapping pulse signals. 
         [0035]      FIG. 10  is a timing diagram showing an embodiment of an operation of the timing circuit  642  of  FIG. 9 . Referring to  FIG. 10 , at time t1, the first pulse signal PH 1  is activated in response to the rising edge of the clock signal CLK when the mode signal PGM is activated. In this embodiment, the pulse width of the pulse signal PHI is equal to 2×T, wherein T is the time period of the clock signal CLK. 
         [0036]    Referring to  FIG. 9  and  FIG. 10 , upon receiving the pulse signal PH 1 , the D flip-flop D 1  of the delay circuit  6424  generates a delayed version of the input signal PH 1  at a predetermined delay T at time t2. Thereafter, the D flip-flop D 2  receives the delayed signal PH 2  from the D flip-flop D 1  for generating a delayed version of the signal PH 2  at a predetermined delay T at time t3. Then, the D flip-flop D 3  receives the delayed signal PH 3  from the D flip-flop D 2  for generating a delayed version of the signal PH 3  at a predetermined delay T at time t4. In this manner, the delay circuit can generate successive pulse signals PH 1 , PH 2 , PH 3 , and PH 4  having the same overlapping amount of T as shown in  FIG. 10 . 
         [0037]    In the above embodiment, each pulse width of the pulse signals PH 1  to PH 4  is equal to 2×T and the overlapping amount of the pulse signals PHI to PH 4  is equal to T. However, the pulse width and the overlapping amount of the pulse signals can be adjusted to any value. For example, the pulse width of the pulse signals PH 1  to PH 4  can be designed to be a multiple of the time period T, and the overlapping amount between two successive pulse signals can be varied. 
         [0038]      FIG. 11  is a timing diagram showing an embodiment of an operation of the memory device  60  during the programming operation. Hereinafter, the detailed program operation in accordance with one embodiment of the present invention is introduced with reference to  FIG. 6  to  FIG. 11 . Referring to  FIG. 6  and  FIG. 11 , during the time period t1 to t3, the first group GROUP 1  in the memory array  32  is selected by the circuits  32  and  34  first. Therefore, the pumped voltage VH is applied to the memory cells M 1 , 1 , M 1 , 2 , M 1 , 3 , and M 1 , 4  of the group GROUP 1  through the bit lines BL 0 , BL 1 , BL 2 , and BL 3  shown in  FIG. 7 . Thereafter, the second group GROUP 2  is selected by the circuits  32  and  34  during the time period t2 to t4, and the pumped voltage VH is applied to the memory cells M 1 , 5 , M 1 , 6 , M 1 , 7 , and M 1 , 8  of the group GROUP 2  through the bit lines BL 4 , BL 5 , BL 6 , and BL 7 . During the time period t3 to t5, the third group GROUP 3  is selected by the circuits  32  and  34 , and the pumped voltage VH is applied to the memory cells M 1 , 9 , M 1 , 10 , M 1 , 11 , and M 1 , 12  of the group GROUP 3  through the bit lines BL 8 , BL 9 , BL 10 , and BL 11 . In this manner, the groups of the memory devices  60  are successively selected, and the pumped voltage VH is applied to the memory cells of the selected group during the program operation. 
         [0039]    Referring to  FIG. 11 , since the memory cell transistors M 1 , 1  to M 1 , 16  in  FIG. 7  are divided into a plurality of groups and the program operations for the memory cells in each group are performed in turn, the instantaneous power consumption of the entire operation can be relatively low. Furthermore, because the pulse signals for programming each group are overlapping each other, the entire program duration of the memory cells can is be significantly reduced according to the present invention. 
         [0040]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.

Technology Category: 3