Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention relates to a DRAM manufacturing process and, more particularly, to a method for pre-retaining CB openings in a DRAM manufacturing process.  
       BACKGROUND OF THE INVENTION  
       [0002]     Dynamic random access memory (DRAM) is a widely used IC component, particularly in the IT products. Conventional DRAM usually comprises a plurality of bit lines and a plurality of word lines, cross-intersecting with each other.  
         [0003]     The recent IC manufacturing technology moves towards shrinking the width of the interconnecting lines to reduce the horizontal size of IC. As this increases the aspect ratio, manufacturing the vertical size of IC becomes more difficult.  
         [0004]     Conventionally, it is easy to damage the gate conductor (GC), i.e., word line, during the manufacturing of bit line opening. This type of damage will cause the short-circuit problem between word lines and bit lines, and the open-circuit problem of bit line opening.  
       SUMMARY OF THE INVENTION  
       [0005]     The first object of the present invention is to provide a method to avoid the short-circuit problem between word lines and bit lines.  
         [0006]     The second object of the present invention is to provide a method to avoid the open-circuit problem of the bit line openings.  
         [0007]     To achieve the aforementioned objects, the present invention provides a method for pre-retaining CB openings. The present invention discloses a method comprising the following steps: forming a plurality of gate conductors (GC) on a substrate, with a gap between two adjacent GCs, forming a photo-resist layer on the GCs and the gaps between them, removing a part of the photo-resist layer to expose a part of substrate and part of GC surfaces, while keeping the gaps and part of the GC surfaces still covered with the photo-resist layer, using the liquid phase deposition (LPD) method to form an oxidation layer at the locations of removed photo-resist layer, removing the photo-resist layer on the pre-retained gaps and part of the GC surfaces to form a bit line CB opening, forming a polysilicon layer in the bit line CB opening and the LPD oxidation layer, removing the polysilicon layer to expose the LPD oxidation layer, removing the LPD oxidation layer to expose a part of substrate and part of GC surfaces, uniformly forming a nitrogen compound layer on the exposed substrate and GC surfaces, forming a BPSG layer on the nitrogen compound layer, and finally, removing the BPSG layer to expose the nitrogen compound layer on top of the polysilicon layer.  
         [0008]     The method disclosed in the present invention can avoid the short-circuit problem between the bit lines and word lines, and the open-circuit problem of bit line CB openings.  
         [0009]     These and other objects, features and advantages of the invention will be apparent to those skilled in the art, from a reading of the following brief description of the drawings, the detailed description of the preferred embodiment, and the appended claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIGS. 1A-1M  show the steps of the method for pre-retaining CB openings in the DRAM manufacturing process.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]     As shown in  FIG. 1A , a plurality of gate conductors (GC)  20   a ,  20   b ,  20   c    20   d  are formed on a substrate  10 . A gap is re-retained between each pair of  20   a  and  20   b ,  20   b  and  20   c ,  20   c  and  20   d . Gap  21  denotes the gap between  20   a  and  20   b.    
         [0012]     A photo-resist layer  22  is formed on GCs  20   a ,  20   b ,  20   c ,  20   d  and the gaps between GCs, including gap  21 , so that GCs  20   a ,  20   b ,  20   c ,  20   d  are entirely covered with photo-resist layer  22 , as shown in  FIG. 1B .  
         [0013]     In the next step, as shown in  FIG. 1C , a part of photo-resist layer  22  is removed to expose the gap, i.e., substrate  10 , between  20   c  and  20   a , the gap between  20   b  and  20   d , GC  20   c , GC  20   d , the left half of GC  20   a , and the right half of GC  20   b . The remaining photo-resist layer  22  still fills gap  21 , and covers the right half of GC  20   a  and the right half of GC  20   b.    
         [0014]     It is worth noticing that photo-resist layer  22  is easy for removal in the above step, so that gap  21  can use photo-resist layer  22  in  FIG. 1C  to pre-retain a bit line CB opening in order to avoid the drawbacks of etching techniques used in conventional bit line CB opening manufacturing process, which usually causes damage to the surfaces of the right half of GC  20   a  and the left half of GC  20   b . Therefore, the remaining photo-resist layer  22  is where the bit line CB opening of the DRAM will be located.  
         [0015]     The removal of photo-resist layer  22  can be accomplished by either a dry approach or a wet approach. The wet approach usually uses the SPM to remove photo-resist layer  22 . The SPM is a mixed solution of H 2 SO 4  and H 2 O 2 .  
         [0016]     As shown in  FIG. 1D , the next step is to form a liquid phase deposition (LPD) oxidation layer  24  at around room temperature (25-40° C.) at the exposed location of the removed photo-resist layer  22 . The exposed locations of the removed photo-resist layer  22  refer to the gap between  20   a  and  20   c , the gap between  20   b  and  20   d , the exposed GCs  20   c ,  20   d , and the exposed part of GCs  20   a ,  20   b , as shown in  FIG. 1C . It is worth noticing that the height of LPD oxidation layer  24  could be slightly lower than that of photo-resist layer  22 .  
         [0017]     Although photo-resist layer  22  is prone to damage in an environment with a slightly high temperature, the bit line opening pre-retained by photo-resist layer  22  is, however, still well preserved during the aforementioned step because the aforementioned step of forming LPD oxidation layer  24  is carried out at room temperature.  
         [0018]     The next step, as shown in  FIG. 1E , is to remove the remained photo-resist layer  22  on gap  21  and partly covered GC  20   a ,  20   b . This step forms a bit line CB opening  26 .  
         [0019]     Then, as shown in  FIG. 1F , a polysilicon layer  28  is formed on bit line CB opening  26  and LPD oxidation layer  24 .  
         [0020]     The next step is to remove a part of polysilicon layer  28  to expose the upper surface of LPD oxidation layer  24  at the edge adjacent to filled-with-polysilicon bit line CB opening  26 , as shown in  FIG. 1G . The removal of polysilicon layer  28  is usually accomplished by chemical mechanical polishing (CMP) or etching.  
         [0021]     As shown in  FIG. 1H , the next step is to remove LPD oxidation layer  24  to expose a part of substrate  10  and a part of GCs. The removal of LPD oxidation layer  24  can be accomplished by diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). The DHF is a mixed solution of hydrofluoric acid and water at the ratio of 1:30 to 1:500, and the BHF is a mixed solution of ammonium fluoride, hydrofluoric acid, and water. The ratio between ammonium fluoride and hydrofluoric acid is 6:1 to 5:1.  
         [0022]     The next step, as shown in  FIG. 11 , is to form a nitrogen compound layer  30 , which may have a thickness of 120 Å±10%, on polysilicon layer  28  and on the exposed surfaces of substrate  10  and GCs  20   c ,  20   d , and part of GCs  20   a ,  20   b.    
         [0023]     The next step, as shown in  FIG. 1J , is to form a BPSG layer  32  on nitrogen compound layer  30 , followed by the step of removing BPSG layer  32  to expose nitrogen compound layer  30  on top of polysilicon layer  28 , as shown in  FIG. 1K .  
         [0024]     Then, a tetra-ethyl-oetho-silicate (TEOS) layer  34  is formed on the exposed nitrogen compound layer  30  on top of polysilicon layer  28 , and BPSG layer  32 , as shown in  FIG. 1L . And finally, as shown in  FIG. 1M , a tungsten plug  36  is formed inside TEOS layer  34  on top of polysilicon layer  28 .  
         [0025]     From the aforementioned disclosure, the present invention, using an LPD oxidation layer  24  and photo-resist layer  22  to pre-retain a bit line CB opening, does not require etching for manufacturing bit line CB opening, as conventional techniques. Therefore, the present invention avoids the potential damage on the surface of the right half of GC  20   a  and the surface of left half of GC  20   b  caused by etching. This also avoids the short-circuit problem between bit lines and word lines, as well as the open-circuit problem of bit line CB openings.  
         [0026]     While the invention has been described in connection with what is presently considered to the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangement included within the spirit and scope of the appended claims.

Technology Category: 5