Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a video coding technology, and more particularly to a block matching method for fast motion estimation. 
     2. The Prior Arts 
     In order to save the storage medium space for storing image data and reduce the bandwidth used for transmitting the image data, original image data is often compressed to obtain compressed image data. When the image data is to be displayed, the compressed image data is recovered to displayable image data by executing a decompression process. The compression process is known as a coding process, while the decompression process is known as a decoding process. 
     The H.264/AVC video coding standard is a widely used coding method, which is often applied in image compression required by network image transmission. The image data coding system of the H.264/AVC standard includes motion estimation, motion compensation, block codes, and variable length codes, by which P-frame bitstream, i.e., the compressed data, can be generated. Among the foregoing, the motion estimation occupies very much system resources, such as memory space, computation time, and power consumption. Generally speaking, the motion estimation may occupy 76% of memory access, 77% of memory bandwidth, and 78% of computation time. As such, it is very highly desired to enhance the efficiency of the motion estimation and improve the entire coding efficiency. 
     Regarding a motion estimation approach, a search window is selected from a reference frame according to a current block in a current frame. Then, a best matching algorithm (BMA) is utilized to find out a best matched block from all reference blocks in the search window, thus obtaining a corresponding motion vector provided for subsequent variable length codes. The BMA typically determines a best matched block having a minimum sum of absolute differences (SAD) according to the SAD defined by the following equation. 
               S   ⁢           ⁢   A   ⁢           ⁢     D   ⁡     (     i   ,   j     )         =       ∑     m   =   0     15     ⁢       ∑     n   =   0     15     ⁢            X   ⁡     (     m   ,   n     )       -     Y   ⁡     (       m   +   i     ,     n   +   j       )                        
In the equation, X(m, n) represents the image data of the current block at coordinates (m,n), Y(m+i, n+j) represents the image data of the reference block at coordinates (m+i, n+j), in which i is a horizontal coordinate, and j is a vertical coordinate, and i and j are integers.
 
       FIG. 1  is a schematic diagram illustrating a conventional video coding hardware system. Referring to  FIG. 1 , a conventional video coding hardware system  1  includes an encoder  10 , for searching for a best matched block in the search window of the reference frame. The encoder  10  loads data stored in an external memory  17  via an external bus  19  and a memory interface  16 . The data stored in the external memory  17  is the data of the reference block in the search window. The encoder  10  includes an encoding engine  11 , an internal memory  12 , and a computation engine  13 . The internal memory is adapted for storing the data loaded from the external memory  17 . The computation engine  13  executes a logical computation to obtain the SADs. The encoding engine  11  finds out the best matched block having the minimum SAD according to the SADs obtained by the computation engine  13 . 
     Referring to  FIG. 2 , there is shown a schematic diagram illustrating the search window of the conventional BMA. As shown in  FIG. 2 , the search window  50  has a width of SR V +N−1, a height SR V +N−1, a horizontal searching range SR H , and a vertical searching range SR V . A reference block  61  positioned at a center point of the search window  50  is a N×N block, in which each of the values is counted by pixel as the unit thereof, and SR H =2P H , and SR V =2P V . 
     The H.264/AVC video coding standard is featured with the fast motion estimation approach of a specific multiple reference frames scheme, for providing a standard operation for further compression of the image data. 
     Referring to  FIG. 3 , there is shown a conventional multiple reference frames scheme. As shown in  FIG. 3 , regarding a current block  30  of the current frame  20 , according to the BMA, best matched blocks are found out from a first search window  51 , a second search window  52 , a third search window  53 , and a fourth search window  54  of a first reference frame  41 , a second reference frame  42 , a third reference frame  43 , and a fourth reference frame  44 , respectively. The current block  30  is at a time t, the first search window is at a time t−T, the second search window is at a time t−2T, the third search window is at a time t−3T, and the fourth search window is at a time t−4T, in which T is a frame time interval, i.e., a spacing time between two consecutive frames. The time t−4T is ahead to the time t−3T for a frame time interval T. 
     Referring to  FIG. 4 , there is shown a flow chart illustrating the conventional multiple reference frames scheme. As shown in  FIG. 4 , first at step S 10 , the current block is loaded. Then at step S 12 , the search windows of a reference frame are loaded. Then, at step S 14 , the best matched blocks of the search windows are searched according to the BMA. Then, at step S 16 , when the best matched blocks of the search windows of the reference frame are not all obtained yet, the flow goes to step S 18 . At step S 18 , search windows of a next reference frame are loaded, and the flow then goes back to step S 14 . At step S 20 , the flow ends. 
     It should be noted that the operation of loading the search windows of the reference frame at steps S 12  and S 18  means loading all data of the search windows into the internal memory  12  from the external memory  17 . At step S 14 , the best matched blocks are found out according to the BMA. Therefore, the flow shown in  FIG. 4  can complete the motion estimation of the current block. The entire motion estimation can be achieved by repeating the foregoing steps regarding all current blocks in the current frame. Steps S 12  and S 18  unfortunately increase the bandwidth for data transmission. Particularly, in this circumstance, in order to complete the motion estimation of a single current block, all of the first search window  51 , the second search window  52 , the third search window  53 , and the fourth search window  54  have to be downloaded, so that more data have to be transmitted via the external bus  19 , thus consuming more power. This seriously affects the performance of the electronic product, especially those using batteries for power supplying. 
     As such, a high-performance block-matching VLSI architecture with low memory bandwidth is high desired. 
     SUMMARY OF THE INVENTION 
     A primary objective of the present invention is to provide a high-performance block-matching VLSI architecture with low memory bandwidth for a power-efficient multimedia device. According to the present invention, a plurality of current blocks having a same spatial current block address in a plurality of current frames share a same predicting search path for searching for corresponding best matched blocks in the search window of reference frames. In such a way, motion vectors of the current blocks relative to the corresponding best matched blocks can be obtained, and thus the motion estimation of the video codes can be achieved. Meanwhile, the frequency of downloading the data of the search windows can be drastically reduced, and the data bandwidth can be reduced, so that the entire motion estimation can be accelerated. 
     The present invention further provides a block-matching method. According to the block-matching method of the embodiment of the present invention, motion vectors, adaptive search ranges, and a search path of adjacent blocks of the current block are obtained from the related data of the H.264/AVC video coding standard, for predicting a motion vector, an adaptive search range, and a search path of the current block. According to the predicted motion vector, the adaptive search range, the current search pattern, and the search path of the adjacent blocks of the current block, the search path of the current block are predicted. Data designated by the predicated search path are loaded from the external memory into the internal memory. A BMA process is executed and the predicated search path is updated at the same time, thus allowing other current blocks sharing the predicated search path. In such a way, the memory bandwidth and required internal memory capacity are drastically reduced. 
     Therefore, the block-matching VLSI architecture and the block-matching method provided by the present invention are adapted for providing a solution for solving all disadvantages of the conventional technologies, reducing the data bandwidth, accelerating the motion estimation, and improving the overall efficiency of the video coding process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be apparent to those skilled in the art by reading the following detailed description of a preferred embodiment thereof, with reference to the attached drawings, in which: 
         FIG. 1  is a schematic diagram illustrating a conventional video coding hardware system; 
         FIG. 2  is a schematic diagram illustrating the search window of the conventional BMA; 
         FIG. 3  is a schematic diagram illustrating a conventional multiple reference frames scheme; 
         FIG. 4  is a flow chart illustrating the conventional multiple reference frames scheme; 
         FIG. 5  is a schematic diagram illustrating a high-performance block-matching VLSI architecture according to an embodiment of the present invention; 
         FIG. 6  is a schematic diagram illustrating the block-matching of the high-performance block-matching VLSI architecture according to an embodiment of the present invention; 
         FIG. 7  is a flow chart illustrating the high-performance block-matching VLSI architecture according to an embodiment of the present invention; 
         FIG. 8  is a flow chart illustrating a process of predicating the search path of the high-performance block-matching VLSI architecture according to an embodiment of the present invention; 
         FIG. 9  is a flow chart illustrating a process of predicating the motion vectors of the high-performance block-matching VLSI architecture according to an embodiment of the present invention; and 
         FIG. 10  is another flow chart illustrating a high-performance block-matching VLSI architecture according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
       FIG. 5  is a schematic diagram illustrating a high-performance block-matching VLSI architecture according to an embodiment of the present invention. Referring to  FIG. 5 , the present invention provides a high-performance block-matching VLSI architecture. The high-performance block-matching VLSI architecture includes a block-matching circuit architecture  70 . The block-matching circuit architecture  70  includes an external memory  71 , a data bus  73 , and a motion estimation processor  80 . The external memory  71  includes data of a plurality of reference frames and a plurality of current frames saved therein. The data bus  73  is connected with the external memory  71  and the motion estimation processor  80 . The motion estimation processor  80  includes an internal memory  82 , a memory processing block  84 , an address selection processing block  86 , a predicting search path processing block  88 , a BMA processing block  90 , and a motion estimation result processing block  92 . The memory processing block  84  is adapted for controlling a data access operation between the internal memory  82  and the external memory  71 . The address selection processing block  86  is adapted for selecting a current block address in a current frame. The predicting search path processing block  88  is adapted for executing a prediction of a search path regarding the current block according to the current block address selected by the address selection processing block  86 , so as to predict the search path corresponding to the current block in the search window. The BMA processing block  90  is adapted for loading corresponding data of the search window from the external memory  71  to the internal memory  82 , and finding out the best matched blocks by the BMA, according to the search path predicted by the predicting search path processing block  88 . In such a way, the motion estimation of a single current block is completed, and motion vectors of the current block and the best matched block are obtained, and recorded by the motion estimation result processing block  92 . 
     Further, the memory processing block  84  loads a current block of another frame having the same current block address. The current block of the current frame is saved in the external memory  71 . The predicated search path is updated by the predicting search path processing block  88 , and the best matched block and the motion vector are found out by the BMA processing block  90 . Meanwhile, the motion estimation result processing block  92  records the motion vector, until motion estimations of all current blocks having the same current block address are completed. Therefore, the data of the same search window can be shared by a plurality of current blocks, for improving the utilization efficiency of the data, and reducing the data bandwidth of the data bus  73 . 
     Then, the motion estimation result processing block  92  restarts the address selection processing block  86  to select another address, and updates the predicted search path by the memory processing block  84  and the predicting search path processing block  88 . The BMA processing block  90  finds out the best matched block and the motion vector. Meanwhile, the motion estimation result processing block  92  records the motion vector, until motion estimations of all current blocks having the same current block address are completed. Therefore, the block-matching circuit architecture  70  of the present invention is adapted for carrying out the motion estimation of the H.264/AVC video coding standard data. 
       FIG. 6  is a schematic diagram illustrating the block-matching of the high-performance block-matching VLSI architecture according to an embodiment of the present invention. Referring to  FIG. 6 , a search window  50  of a reference frame  40  of a time t−4T is a first current block  31  of a first current frame  21  provided for a time t−3T, a second current block  32  of a second current frame  22  provided for a time t−2T, a third current block  33  of a third current frame  23  provided for a time t−T, and a fourth current block  34  of a fourth current frame  24  provided for a time t, for carrying out the motion estimation to find out the best matched blocks. The first current block  31 , the second current block  32 , the third current block  33 , and the fourth current block  34  are positioned at a same spatial address of different current frames. As such, the first current block  31 , the second current block  32 , the third current block  33 , and the fourth current block  34  are highly time correlated in a time axis. 
     Comparing with the present invention, the conventional technology as shown in  FIG. 3  differs in that it requires to load four search windows and the data of a current block for carrying out the motion estimation. On the contrary, the present invention requires to load only one search window and data of four current blocks. Since the data amount of a search window is much more than the data amount of a current block, the present invention is adapted for drastically reducing the data transmission bandwidth. For example, supposing that a data amount of a search window is 3×3 times of a current block, the data amount processed by the conventional technology is 37 times of the current block, i.e., 9×4+1=37, while the data amount processed by the present invention is 13 times of the current block, i.e., 9+1×4=13. As such, according to the present invention, the data transmission bandwidth can be reduced up to 13/37 (about 35%) of the conventional technology. Therefore, about 65% of the data transmission bandwidth can be saved. Correspondingly, the power consumption of the battery can be decrease, and the battery can thus maintain the power supply for a longer time. 
     It should be noted that, although four current blocks are exemplified for sharing the same search window in the current embodiment, the scope of the present invention is not restricted by quantity of the exemplified current blocks. In other words, the present invention can select N current blocks for sharing the same search window, in which N is a positive integer. 
       FIG. 7  is a flow chart illustrating the high-performance block-matching VLSI architecture according to an embodiment of the present invention. Referring to  FIG. 7 , at step S 100 , the motion estimation is started, in which the search window and the current blocks are saved in the external memory  84 . At step S 110 , a current block address of a current frame is selected. Then, at step S 120 , data of the current block of the current block address is loaded to the internal memory  74 . Then, at step S 140 , a predicated search path is obtained. Then, at step S 160 , data designated according to the predicated search path is loaded from the external memory  84  to the internal memory  74 . Then at step S 180 , a BMA matching operation is executed to find out a best matched block. Then, at step S 200 , it is determined whether the BMA matching operation has been executed to all of the current blocks having the same address. If no, then the flow goes to step S 220 , or otherwise if yes, then the flow goes to step S 240 . At step S 220 , another current bock having the same address is loaded, and the flow goes back to step S 140 , and the steps from S 160  to S 200  are repeated. At step S 240 , according to the BMA matching operation result of the same address, the motion estimation of the current blocks at the same spatial address is completed. Then, at step S 260 , it is determined whether BMA matching operations of current blocks of all spatial addresses have been completed. If no, then the flow goes to step S 280 , or otherwise if yes, then the flow goes to step S 300 . At step S 280 , another address is selected, and the flow goes back to step S 120 , and the steps S 140  to S 260  are repeated. At step S 300 , the motion estimation result is obtained. Then, at step S 320 , the motion estimation operation is completed. 
     As such, prior to the BMA matching operation, the present invention searches a more suitable predicated search path, i.e., updates the predicated search path, when loading a next current block. 
       FIG. 8  is a flow chart illustrating a process of predicating the search path of the high-performance block-matching VLSI architecture according to an embodiment of the present invention. The flow chart of the process of predicating the search path of  FIG. 8  depicts the details of step S 140  of  FIG. 7 . Referring to  FIG. 8 , first at step S 142 , motion vectors, adaptive search ranges and a search path of adjacent blocks of the current block are obtained according to the H.264/AVC video coding standard. Then, at step S 144 , a motion vector and an adaptive search range of the current block are predicted. Then, at step S 146 , a search path of the current block is predicted, according to the predicted motion vector, the predicted adaptive search range, the current search pattern, and the search path of the adjacent blocks of the current block. 
       FIG. 9  is a flow chart illustrating a process of predicating the motion vectors of the high-performance block-matching VLSI architecture according to an embodiment of the present invention.  FIG. 9  is provided for further illustrating steps S 144  and S 146  of  FIG. 8 . Referring to  FIG. 9 , a first adjacent block  30 A, a second adjacent block  30 B, a third adjacent block  30 C are adjacently positioned at a left side, an upper left side, and an upper side of a current block  30 . The first adjacent block  30 A, the second adjacent block  30 B, and the third adjacent block  30 C have motion vectors MV 1 , MV 2 , and MV 3 , respectively. According to an aspect of the current embodiment, a predicted motion vector MVP of the current block  30  can be determined by averaging the motion vectors MV 1 , MV 2 , and MV 3 . Further, according to another aspect of the current embodiment, the predicted motion vector MVP of the current block  30  can be determined by executing an extrapolation calculation upon a motion vector plane constructed according to the motion vectors MV 1 , MV 2 , and MV 3 . It should be noted that the present invention the above mentioned aspects of the current embodiment are exemplified for illustration purpose without restricting the scope of the present invention. 
     The predicted adaptive search range for example can be a maximum value of the adaptive search ranges of the adjacent blocks, or an average of the of the adaptive search ranges of the adjacent blocks. 
       FIG. 10  is another flow chart illustrating a high-performance block-matching VLSI architecture according to an embodiment of the present invention.  FIG. 10  is provided for further illustrating steps S 120  to S 240  of  FIG. 7 , facilitated with  FIG. 6 . 
     Referring to  FIG. 10 , at step S 500 , a search path of the reference frame at the time t−4T is loaded. Then, at step S 510 , the first current block of the first current frame at the time t−3T is loaded. Then, at step S 512 , the search path is updated, i.e., at step S 140  of  FIG. 7  in which the search path is predicted. Then, at step S 514 , a first best matched block is found out. Then, at step S 520 , the second current block of the second current frame at the time t−2T is loaded. Then, at step S 522 , the search path is updated, i.e., at step S 140  of  FIG. 7  in which the search path is predicted. Then, at step S 524 , a second best matched block is found out. Then, at step S 530 , the third current block of the third frame at the time t−T is loaded. Then, at step S 532 , the search path is updated, i.e., at step S 140  of  FIG. 7  in which the search path is predicted. Then, at step S 534 , a third best matched block is found out. Then, at step S 540 , the fourth current block of the fourth current frame is loaded. Then, at step S 542 , the search path is updated, i.e., at step S 140  of  FIG. 7  in which the search path is predicted. The, at step S 544 , a fourth best matched block is found out. Then, at step S 550 , the first best matched block, the second best matched block, the third best matched block, and the fourth best matched block are combined. As such, according to the present invention, best matched blocks and motion vectors corresponding to four current blocks having the same address are searched, so as to improve the reusability of the data, and drastically reduce the power consumed upon the overall motion estimation operation, and improve the operation speed and the performance thereof. 
     Although the present invention has been described with reference to the preferred embodiments thereof, it is apparent to those skilled in the art that a variety of modifications and changes may be made without departing from the scope of the present invention which is intended to be defined by the appended claims.

Technology Category: 5