Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention relates to a semiconductor design technology; and, more particularly, to an internal voltage generating circuit for maintaining a stable internal voltage level because of a fast response time.  
       DESCRIPTION OF RELATED ART  
       [0002]     In semiconductor memory devices, an internal voltage generating circuit receives an external voltage VDD to generate various levels of an internal voltage.  
         [0003]     With low voltage and low power consumption of the semiconductor memory devices, internal voltage generating circuits are increasingly employed in DRAMs.  
         [0004]     Meanwhile, since the voltages used in the semiconductor memory devices are internally generated, many attempts have been made to generate stable internal voltages regardless of ambient temperature, process, or pressure.  
         [0005]      FIG. 1  is a block diagram of a conventional internal voltage generating circuit.  
         [0006]     Referring to  FIG. 1 , the conventional internal voltage generating circuit includes a level detector  10 , an oscillator  20 , a pumping control signal generator  30 , and a charge pump  40 .  
         [0007]     The charge pump  40  negatively pumps an external voltage VDD to generate an internal voltage VBB lower than the external voltage VDD. The level detector  10  detects a level increase of the internal voltage VBB. The oscillator  20  generates a periodic signal OSC in response to a detection signal BBE of the level detector  10 . The pumping control signal generator  30  controls a driving of the charge pump  40  in response to the periodic signal OSC.  
         [0008]     In such an internal voltage generating circuit, when the level of the internal voltage VBB increases, its level increase is detected through the level detector  10  and then the charge pump  40  is driven by the pumping control signal generator  30 . Therefore, the internal voltage VBB is maintained to a constant level.  
         [0009]     The charge pump  40  may be configured with a doubler-type charge pump.  
         [0010]      FIG. 2  is a circuit diagram of the level detector  10  shown in  FIG. 1 .  
         [0011]     Referring to  FIG. 2 , the level detector  10  includes a voltage divider  12 , an inverter I 1 , an inverter I 2 , and a differential amplifier  14 , and an inverter I 3 .  
         [0012]     The voltage divider  12  is configured with serially connected resistors and divides a level difference between a reference voltage VBB_high and the internal voltage VBB. The inverter I 1  receives the reference voltage VBB_high and a ground voltage VSS as a driving voltage, and inverts an output voltage of the voltage divider  12 . The inverter I 2  receives the reference voltage VBB_high and the ground voltage VSS as a driving voltage, and inverts an output voltage A of the inverter I 1 . The differential amplifier  14  amplifiers a level difference between the output voltages A and B of the inverters I 1  and I 2 . The inverter I 3  receives the external voltage VDD and the ground voltage VSS as a driving voltage, and outputs an output voltage of the differential amplifier  14  as the detection signal BBE.  
         [0013]     When the internal voltage VBB increases higher than the reference voltage (VBB_high) level, the inverter I 1  outputs the ground voltage VSS level as the output voltage A. Then, the inverter I 2  outputs the VSS_high level voltage as the output voltage B. The differential amplifier  14  differentially receives the output voltages A and B of the inverters I 1  and I 2  to output the VSS level voltage. Therefore, the inverter I 3  inverts the output voltage of the differential amplifier  14  to output the external voltage VDD level, that is, a logic high level.  
         [0014]     On the contrary, when the internal voltage VBB maintains the VBB_high level, the inverter I 1  outputs the VBB_high level and the inverter I 2  outputs the VSS level. Therefore, the differential amplifier  14  outputs the VDD level and finally the inverter I 3  outputs the VSS level, that is, a logic low level.  
         [0015]      FIG. 3  is a circuit diagram of the oscillator  20  shown in  FIG. 1 . The oscillator  20  includes a first inverter chain  22 , a NAND gate ND 1 , and a second inverter chain  24 .  
         [0016]     The first inverter chain  22  delays and inverts the periodic signal OSC to generate a feedback periodic signal. The NAND gate ND 1  receives the feedback periodic signal and the detection signal BBE. The second inverter chain  24  delays and inverts an output signal of the NAND gate ND 1  to generate the periodic signal OSC.  
         [0017]     The oscillator  20  is controlled by the detection signal BBE to generate the periodic signal OSC. That is, when the detection signal BBE is a logic high level, the oscillator  20  generates the periodic signal OSC that is toggled at a constant period. On the contrary, when the detection signal BBE is a logic low level, the oscillator  20  generates a logic low level signal as the periodic signal OSC.  
         [0018]      FIG. 4A  is a circuit diagram of the pumping control signal generator  30  shown in  FIG. 1 .  
         [0019]     Referring to  FIG. 4A , the pumping control signal generator  30  includes first to third delay units  32 ,  34  and  36  and a signal generating unit  38 .  
         [0020]     The first to third delay units  32 ,  34  and  36  are connected in series to output first to third delay periodic signals T 1 , T 2  and T 3 . That is, the first delay unit  32  receives the periodic signal OSC to output the first delay periodic signal T 1 , and the second delay unit  34  delays an output of the first delay unit  32  to output the second delay periodic signal T 2 . Also, the third delay unit  36  delays an output of the second delay unit  34  to output the third delay periodic signal T 3 . The signal generating unit  38  receives the first to third delay periodic signals T 1 , T 2  and T 3  to output a plurality of pumping control signals P 1 , P 2 , G 1  and G 2 .  
         [0021]      FIG. 4B  is an operational waveform of the pumping control signal generator shown in  FIG. 4A .  
         [0022]     Referring to  FIG. 4B , the pumping control signal generator  30  generates the pumping control signal P 2  by delaying the periodic signal OSC by a predetermined time, the pumping control signal P 1  having an opposite phase to the pumping control signal P 2 , the pumping control signal G 1  containing an activation period of the pumping control signal P 2 , and the pumping control signal G 2  having a phase difference of 90° with respect to the pumping control signal G 1 .  
         [0023]     The waveform of  FIG. 4B  shows the operation of the pumping control signal generator  30  when the level of the internal voltage VBB increases higher than the reference voltage VBB_high, the detection signal BBE of the level detector  10  is activated to a logic high level, and the oscillator  20  generates the periodic signal OSC.  
         [0024]      FIG. 5  is a circuit diagram of the charge pump  40  shown in  FIG. 1 .  
         [0025]     In the charge pump  40  shown in  FIG. 5 , a capacitor C 1  has one terminal receiving the pumping control signal P 1  and the other terminal connected to a node P 1 _BT, and a capacitor C 3  has one terminal receiving the pumping control signal P 2  and the other terminal connected to a node P 2 _BT. An NMOS transistor NM 2  has a gate receiving a voltage of the node P 1 _BT and a drain-source path between the internal voltage VBB and the node P 2 _BT, and an NMOS transistor NM 1  has a gate receiving a voltage of the node P 2 _BT and a drain-source path between the internal voltage VBB and the node P 1 _BT. A capacitor C 2  has one terminal receiving the pumping control signal G 2  and the other terminal connected to a node G 1 _BT, and a capacitor C 4  has one terminal receiving the pumping control signal G 2  and the other terminal connected to a node G 2 _BT. A PMOS transistor PM 1  has a gate receiving a voltage of the node G 1 _BT and a source-drain path between the node P 1 _BT and a ground voltage VSS supply, and a PMOS transistor PM 4  has a gate receiving a voltage of the node G 2 _BT and a source-drain path between the node P 2 _BT and the VSS supply. A PMOS transistor PM 2  has a source connected to the node G 1 _BT, and a drain and a gate commonly connected to the drain of the PMOS transistor PM 1 . A PMOS transistor PM 3  has a source and a gate commonly connected to the node G 1 _BT, and a drain connected to the drain of the PMOS transistor PM 1 . A PMOS transistor PM 6  has a source connected to the node G 2 _BT, and a drain and a gate commonly connected to the drain of the PMOS transistor PM 4 . A PMOS transistor PM 5  has a source and a gate commonly connected to the node G 2 _BT, and a drain connected to the drain of the PMOS transistor PM 4 .  
         [0026]     The operation of the charge pump  40  receiving the pumping control signals P 1 , P 2 , G 1  and G 2  will be described with reference to a time point ‘P’ in  FIG. 4B .  
         [0027]     First, the pumping control signals P 1 , G 1  and G 2  have a logic high level, a logic low level, and a logic high level, respectively.  
         [0028]     Since the node G 1 _BT is set to the VSS level due to the pumping control signal G 1 , the PMOS transistor PM 1  is turned on in response to the pumping control signal G 1 , so that the node P 1 _BT is also set to the VSS level.  
         [0029]     In addition, the node G 2 _BT is set to the external voltage VDD level due to the pumping control signal G 2 .  
         [0030]     Then, the pumping control signal G 1  changes to a logic high level, so that the node G 1 _BT increases to the VDD level. Therefore, the PMOS transistor PM 1  is turned on so that the node P 1 _BT is opened from the VSS supply.  
         [0031]     Next, the pumping control signal P 1  changes to a logic low level, so that the node P 1 _BT is set to −VDD level by the capacitor C 1  of which one terminal receives the pumping control signal P 1 . The pumping control signal P 2  changes to a logic high level, so that the node P 2 _BT is se to the VDD level by the capacitor C 3  of which one terminal receives the pumping control signal P 2 .  
         [0032]     Accordingly, the NMOS transistor NM 1  is turned on in response to the voltage of the node P 2 _BT so that −VDD level applied to the node P 1 _BT is outputted as the internal voltage VBB.  
         [0033]     Then, the pumping control signal G 2  changes to a logic low level, so that the node P 2 _BT is precharged to the VSS level by the PMOS transistor PM 4  of which gate receives the voltage of the node G 2 _BT.  
         [0034]     The pumping control signal G 2  again changes to a logic high level. Therefore, the PMOS transistor PM 4  is turned off so that the node P 2 _BT is opened from the VSS supply.  
         [0035]     Thereafter, the pumping control signal P 1  changes to a logic high level and the node P 1 _BT increases up to the VDD level. The pumping control signal P 2  changes to a logic low level, so that the node P 2 _BT decreases up to −VDD level.  
         [0036]     Accordingly, the NMOS transistor NM 2  is turned on in response to the voltage of the node P 1 _BT, so that −VDD voltage level applied to the node P 2 _BT is outputted as the internal voltage VBB.  
         [0037]     Meanwhile, the problem that the conventional internal voltage generating circuit cannot stably maintain the internal voltage VBB will be described below with reference to  FIG. 6 .  
         [0038]     Referring to  FIG. 6 , a large amount of a high voltage is dissipated in a memory region at a time point when a word line WL is activated and deactivated by an active command ACT and a precharge command PCG.  
         [0039]     When the VBB level increases higher than the VBB_high level, the conventional internal voltage generating circuit detects the increased VBB level to increase a supply of the VBB voltage. Therefore, a response time becomes long and the VBB level increases while not maintaining it stably.  
         [0040]     That is, even if the level increase of the internal voltage VBB is detected, some time is necessary until an additional supply from the charge pump. Consequently, the level of the internal voltage VBB continues to increase during the necessary time.  
         [0041]     As described above, the level of the internal voltage is not maintained stably. Also, if the level of the internal voltage changes depending on the internal operation, noise is generated from the semiconductor memory device using the interval voltage, reducing the operational reliability of the device.  
       SUMMARY OF THE INVENTION  
       [0042]     It is, therefore, an object of the present invention to provide an internal voltage generating circuit for providing a stable internal voltage by supplying the internal voltage before a time point when it is used.  
         [0043]     In accordance with an aspect of the present invention, there is provided an internal voltage generating circuit including: a charge pump unit for generating an internal voltage lower than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.  
         [0044]     In accordance with another aspect of the present invention, there is provided a semiconductor memory device for stably supplying an internal voltage including: a charge pump unit for generating the internal voltage being lower than an external voltage in response to pumping control signals and a supply driving control signal; an oscillator for generating a periodic signal in response to a driving signal, without detecting a level change of the internal voltage; a pumping control signal generating unit for generating the pumping control signals for outputting the pumping control signals to the charge pump unit based on the periodic signal; and a supply driving control unit for receiving the periodic signal to generate the supply driving control signal to the charge pump unit 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0045]     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0046]      FIG. 1  is a block diagram of a conventional internal voltage generating circuit;  
         [0047]      FIG. 2  is a circuit diagram of a level detector shown in  FIG. 1 ;  
         [0048]      FIG. 3  is a circuit diagram of an oscillator shown in  FIG. 1 ;  
         [0049]      FIG. 4A  is a circuit diagram of a pumping control signal generator shown in  FIG. 1 ;  
         [0050]      FIG. 4B  is an operational waveform of the pumping control signal generator shown in  FIG. 4A ;  
         [0051]      FIG. 5  is a circuit diagram of a charge pump shown in  FIG. 1 ;  
         [0052]      FIG. 6  is a graph for explaining problems of the conventional internal voltage generating circuit;  
         [0053]      FIG. 7  is a block diagram of an internal voltage generating circuit in accordance with a first embodiment of the present invention;  
         [0054]      FIG. 8  is a block diagram of an internal voltage generating circuit in accordance with a second embodiment of the present invention;  
         [0055]      FIG. 9  is a circuit diagram of a pumping control signal generator shown in  FIG. 7 ;  
         [0056]      FIG. 10  is a circuit diagram of an output control signal generator shown in  FIG. 7 ;  
         [0057]      FIG. 11  is a circuit diagram of a level shifter shown in  FIG. 7 ;  
         [0058]      FIG. 12  is a circuit diagram of a charge pump shown in  FIG. 7 ; and  
         [0059]      FIG. 13  is an operational waveform of the internal voltage generating circuit shown in  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0060]     Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter.  
         [0061]      FIG. 7  is a block diagram of an internal voltage generating circuit in accordance with a first embodiment of the present invention.  
         [0062]     Referring to  FIG. 7 , the internal voltage generating circuit includes a pumping control signal generator  100 , a charge pump  200 , and a supply driving controller  300 .  
         [0063]     The charge pump  200  negatively pumps an external voltage VDD to generate an internal voltage VBB lower than the VDD level. The pumping control signal generator  100  generates a plurality of pumping control signals CNT_A 1 , CNT_A 2  and BT_A 0  for controlling a driving of the charge pump  200  when an active command ACT is applied. The supply driving controller  300  receives the active command ACT and controls a supply of the internal voltage VBB of the charge pump  200 .  
         [0064]     The supply driving controller  300  includes an output control signal generator  320  for receiving the active command ACT to generate an output control signal BB, and a level shifter  340  for shifting a level of the output control signal BB.  
         [0065]     In this embodiment, the internal voltage generating circuit negatively pumps the external voltage VDD when the active command ACT is applied, and generates the internal voltage VBB.  
         [0066]     That is, the internal voltage generating circuit supplies the internal voltage VBB much more in response to the active command ACT, before a large amount of a current is rapidly dissipated in a memory region when the active command ACT is applied. Therefore, the level of the internal voltage VBB can be maintained stably.  
         [0067]      FIG. 8  is a block diagram of an internal voltage generating circuit in accordance with a second embodiment of the present invention.  
         [0068]     Referring to  FIG. 8 , the internal voltage generating circuit includes an oscillator  400 , a pumping control signal generator  500 , a charge pump  600 , and a supply driving controller  700 .  
         [0069]     The charge pump  600  negatively pumps an external voltage VDD to generate an internal voltage VBB lower than the VDD level. The oscillator  400  generates a periodic signal OSC in response to an active command ACT. The pumping control signal generator  500  generates a plurality of pumping control signals CNT_A 1 , CNT_A 2  and BT_A 0  for controlling a driving of the charge pump  600  in response to the periodic signal OSC. The supply driving controller  700  controls a supply of the internal voltage VBB of the charge pump  600  in response to the periodic signal OSC.  
         [0070]     Compared with the first embodiment, the internal voltage generating circuit shown in  FIG. 8  further includes the oscillator  400 . When the active command ACT is applied, the oscillator  400  generates the periodic signal OSC for a predetermined time. Then pumping control signal generator  500  and the supply driving controller  700  are driven in response to the periodic signal OSC. By controlling the period of the periodic signal OSC and the generating time of the period, the driving time of the charge pump  600  can be controlled.  
         [0071]     In the case of the first embodiment, because the charge pump is driven only when the active command ACT is applied, the internal voltage generating circuit in accordance with the first embodiment of the present invention can be used when the drivability is large enough to compensate for the internal current consumption. Also, the internal voltage generating circuit in accordance with the second embodiment of the present invention can be used by controlling the period of the periodic signal OSC according to an amount of the consumed internal voltage VBB and a driving amount of the charge pump  600 .  
         [0072]     At this point, the active command ACT means a command that causes the elements to consume a large amount of the internal voltage VBB. When the internal voltage generating circuit is used in the semiconductor memory device, the precharge command is also applied. Therefore, the internal voltage generating circuit can also be driven when the precharge command PCG is applied.  
         [0073]     In the second embodiment, the only difference from the first embodiment is that the oscillator  400  is further provided. Therefore, the configuration and operation of the internal voltage generating circuit shown in  FIG. 7  will be described below.  
         [0074]      FIG. 9  is a circuit diagram of the pumping control signal generator  100  shown in  FIG. 7 .  
         [0075]     Referring to  FIG. 9 , the pumping control signal generator  100  includes a pulse width extending unit  120  for extending a pulse width of the active command ACT, a first buffer  140  for buffering an output signal of the pulse width extending unit  120  to generate the pumping control signal CNT_A 2 , a second buffer  160  for buffing an output signal of the pulse width extending unit  120  to generate the pumping control signal CNT_A 1 , and an inverter I 4  for inverting an output signal of the second inverter I 60  to generate the pumping control signal BT_A 0 .  
         [0076]     Also, the pulse width extending unit  120  includes an inverter I 5  for inverting the active command ACT, a delay unit  122  for delaying an output signal of the inverter I 5 , and a NAND gate ND 2  receiving the output signals of the inverter I 5  and the delay unit  122 .  
         [0077]     When the active command ACT has a logic high level, the pumping control signal generator  100  outputs the pumping control signals CNT_A 1  and CNT_A 2  of a logic high level and the pumping control signal BT_A 0  of a logic low level.  
         [0078]     Meanwhile, when the active command ACT has a logic low level, the pumping control signal generator  100  outputs the pumping control signals CNT_A 1  and CNT_A 2  of a logic low level and the pumping control signal BT_A 0  of a logic high level.  
         [0079]      FIG. 10  is a circuit diagram of the output control signal generator  320 .  
         [0080]     Referring to  FIG. 10 , the output control signal generator  320  includes an inverter I 6  for inverting the active command ACT, a delay unit  322  for delaying an output signal of the inverter I 6 , and a NOR gate NR 1  for receiving the output signals of the inverter I 6  and the delay unit  322  to output the output control signal BB.  
         [0081]     When the active command ACT is applied, the output control signal generator  320  generates the output control signal BB of a pulse form, which has an activation period of a logic high level after a delay time of the delay unit  322 .  
         [0082]      FIG. 11  is a circuit diagram of the level shifter  340  shown in  FIG. 7 .  
         [0083]     Referring to  FIG. 11 , the level shifter  340  includes an inverter I 7  for inverting the output control signal BB, a differential amplifier  342  receiving the output control signal and an output signal of the inverter I 7 , an inverter I 7 , connected between the external voltage VDD and the internal voltage VBB as the driving voltages, for inverting an output signal of the differential amplifier  342 , and an inverter I 8  for inverting an output signal of the inverter I 7  to output the output driving control signal TR.  
         [0084]     The level shifter  340  outputs the output control signal BB swing between the external voltage VDD and the internal voltage VBB.  
         [0085]      FIG. 12  is a circuit diagram of the charge pump  200  shown in  FIG. 7 .  
         [0086]     Referring to  FIG. 12 , the charge pump  200  includes a first charging unit  220 , a first pumping unit C 5 , a second charging unit  240 , a second pumping unit C 6 , and an NMOS transistor NM 7 .  
         [0087]     The first charging unit  220  charges a node BT_A 1  and a node BT_A 2  to different levels in response to an activation of the pumping control signal CNT_A 1 . The first pumping unit C 5  pumps the node BT_A 1  in response to the pumping control signal BT_A 0  activated when the pumping control signal CNT_A 1  is deactivated. The second charging unit  240  charges a node TR_A 0  and a node BT_A 3  to different levels in response to an activation of the pumping control signal CNT_A 2 . The second pumping unit C 6  pumps a node BT_A 3  in response to a voltage of the node BT_A 2 . The NMOS transistor NM 7  outputs a voltage of the node BT_A 3  as the internal voltage VBB in response to the supply driving control signal TR.  
         [0088]     In the first charging unit  220 , a PMOS transistor PM 8  has a gate receiving the pumping control signal CNT_A 1  and a source-drain path between the VDD supply and the node BT_A 2 . An NMOS transistor NM 3  has a gate receiving the pumping control signal CNT_A 1  and a drain-source path between the node BT_A 2  and the node BT_A 1 . An NMOS transistor NM 4  has a gate receiving the voltage of the node BT_A 2  and a drain-source path between the node BT_A 1  and the VSS supply.  
         [0089]     In the second charging unit  240 , a PMOS transistor PM 7  has a gate receiving the pumping control signal CNT_A 2  and a source-drain path between the VDD supply and the node TR_A 0 . An NMOS transistor NM 5  has a gate receiving the pumping control signal CNT_A 2  and a drain-source path between the node TR_A 0  and the node TR_A 3 . An NMOS transistor NM 6  has a gate receiving the voltage of the node TR_A 0  and a drain-source path between the node BT_A 3  and the VSS supply.  
         [0090]     The first pumping unit C 5  includes a capacitor having one terminal receiving the pumping control signal BT_A 0  and the other terminal connected to the node BT_A 1 . the second pumping unit C 6  includes a capacitor connected between the node BT_A 2  and the node BT_A 3 .  
         [0091]     An operation of the internal voltage generating circuit in accordance with the first embodiment of the present invention will be described below with reference to FIGS.  9  to  12 .  
         [0092]     First, when the active command ACT is not activated, the pumping control signal generator  100  outputs the pumping control signals CNT_A 1  and CNT_A 2  of a logic low level and the pumping control signal BT_A 0  of a logic high level.  
         [0093]     Accordingly, the PMOS transistors PM 8  and PM 7  of the charge pump  200  receive the pumping control signals CNT_A 1  and CNT_A 2  and precharge the nodes BT_A 2  and TR_A 0  to the VDD level and the nodes BT_A 1  and BT_A 3  to the VSS level.  
         [0094]     Also, since the supply driving controller  300  outputs the supply driving control signal TR of the low VBB level in response to the deactivation of the active command ACT, the NMOS transistor NM 7  of the charge pump  200  is turned off. Consequently, the internal voltage VBB is not supplied.  
         [0095]     Meanwhile, when the active command ACT is applied, the pumping control signal generator  100  changes the pumping control signals CNT_A 1  and CNT_A 2  to a logic high level. Thus, the PMOS transistors PM 8  and PM 7  are turned off and the NMOS transistors NM 3  and NM 5  are turned on in response to the pumping control signals CNT_A 1  and CNT_A 2 , so that the nodes BT_A 2  and TR_A 0  are opened from the VDD supply. Then, the NMOS transistors NM 4  and NM 6  are turned off in response to the voltages of the nodes BT_A 2  and TR_A 0 , so that the nodes BT_A 1  and BT_A 3  are opened from the VSS supply.  
         [0096]     Also, since the pumping control signal BT_A 0  changes to a logic low level, the node BT_A 1  is set to −VDD level and the node BT_A 2  is set to −VDD level through the turned-on NMOS transistor NM 3 . Accordingly, the capacitor C 6  receiving the voltage of the node BT_A 2  negatively pumps the node BT_A 3 , so that the node BT_A 3  decreases to −2VDD level.  
         [0097]     Since the supply driving controller  300  activates the supply driving control signal TR to a logic high level in response to the active command ACT, the NMOS transistor NM 7  of the charge pump  200  is turned on, so that −2VDD voltage applied to the node BT_A 3  is supplied as the internal voltage VBB.  
         [0098]     In the case of the internal voltage generating circuit in accordance with the second embodiment of the present invention, if the active command ACT is not applied, the oscillator  400  deactivates the periodic signal OSC to a logic low level. Thus, the pumping control signal generator  500 , the supply driving controller  700 , and the charge pump  600  are deactivated. When the active command ACT is applied, the oscillator  400  activates the periodic signal OSC to a logic high level. Therefore, the charge pump  600  outputs the internal voltage VBB by negatively pumping the external voltage VDD in response to the control signals CNT_A 1 , CNT_A 2  and BT_A 0  outputted from the activated pumping control signal generator  500  and the activated supply driving controller  700 .  
         [0099]     In the above operation, it is assumed that a threshold voltage of the MOS transistors is Vt.  
         [0100]      FIG. 13  is an operational waveform of the internal voltage generating circuit shown in  FIG. 7 .  
         [0101]     Referring to  FIG. 13 , a large of a current is dissipated in a memory region at a time point when a word line (WL) is activated by the active command ACT, and a time point when a word line (WL) is deactivated by a precharge command PCG.  
         [0102]     As described above, since the internal voltage VBB is supplied at the large drivability, the level of the internal voltage VBB can be stably maintained.  
         [0103]     Therefore, the internal voltage generating circuit supplies in advance the internal voltage at the large drivability when applying the command causing a large current consumption inside the device. Thus, even when the current is substantially consumed by the command, the level of the internal voltage can be stably maintained. Unlike the prior art in which the internal voltage is supplied after the detection of the level decrease, an amount of a current supply is previously increased before the current is consumed, thus reducing the response time.  
         [0104]     In addition, compared with the prior art, the internal voltage generating circuit in accordance with the present invention occupies a smaller area.  
         [0105]     In the above embodiments, the active command is exemplarily described because the semiconductor memory device using the internal voltage generating circuit consumes a large amount of a current when the active command is applied. That is, other driving signals expected to consume a large amount of a current can be applied instead of the active command. Therefore, the present invention is not limited by the driving signal for driving the internal voltage generating circuit.  
         [0106]     As described above, before a large amount of a current is consumed by the command, an amount of a current supply is increased. Therefore, the response time is reduced to thereby maintain a high voltage level stably. In addition, the occupied area can be reduced.  
         [0107]     The present application contains subject matter related to Korean patent application No. 2005-36549, filed in the Korean Intellectual Property Office on Apr. 30, 2005, the entire contents of which is incorporated herein by reference.  
         [0108]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.

Technology Category: 3