Patent Document

BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The invention disclosed and claimed herein generally relates to a method that uses interrupt coalescing selectively, according to the lengths of respective incoming interrupt messages. More particularly, the invention relates to a balanced method of the above type, wherein an interrupt coalescing technique is applied to long interrupt messages received by a data processing network system, whereas the system is interrupted immediately upon receipt of selected short interrupt messages. Even more particularly, the invention relates to a method of the above type wherein one or more criteria are used to determine whether or not a particular message is sufficiently short and important to warrant immediate interruption of the system processor.  
         [0003]     2. Description of Related Art  
         [0004]     As is known by those of skill in the art, an interrupt is a signal or message that seeks to redirect operation of a processor in a computer system to a task specified by the interrupt. An interrupt may be sent to the system in the form of packets from a file server, a router, a workstation or the like. However, as is further well known, significant processor overhead is required in processing each interrupt. Accordingly, a number of interrupt coalescing techniques have been developed, to reduce the associated overheads. These interrupt coalescing techniques generally delay delivery of a group of packets until a particular event has occurred, such as receipt of a prespecified total number of packets, receipt of a prespecified number of bytes, or expiration of a prespecified time period. The event could also be receipt of a prespecified number of packets, in combination with expiration of a time period.  
         [0005]     A switched Ethernet local area network (LAN) is a typical environment for application of the above interrupt coalescing techniques, although use of these techniques is by no means limited to such environment. An Ethernet LAN is generally provided with an adapter, or network interface card (NIC), that receives incoming packets containing interrupt messages. Interrupt coalescing support is typically implemented in an NIC, either by means of specialized hardware time counters, or by firmware delay loops. In interrupt coalescing, the NIC “saves up” or stores a group of pending interrupts, and then delivers them all at the same time to the computer system or other node intended to receive them. Thus, the overhead required in processing each interrupt individually is avoided.  
         [0006]     While the interrupt coalescing techniques described above are useful in reducing overhead or consumption of a computer system processor, such techniques result in increased per packet latency. Moreover, such techniques are not typically well suited for use with smaller packets, particularly packets such as locking packets, that carry important interrupt messages. A locking packet generally directs a computer system to receive data that follows the locking packet without delay. Thus, it would be desirable to interrupt the system processor immediately upon receiving packets of this type, and not subject such packets to the delays associated with interrupt coalescing techniques of the type described above.  
       SUMMARY OF THE INVENTION  
       [0007]     The invention provides a balanced approach for the use of interrupt coalescing. More particularly, interrupt coalescing is applied to large data segments, whereas interrupts contained by locking or other small size packets are implemented immediately. Embodiments of the invention thus simultaneously achieve the goal of maximizing locking and other small packet interrupts, while minimizing large data segment interrupts. A useful embodiment is directed to a method for a data processing system having a processor and an adapter connecting the system to receive incoming packets of varying size, wherein the incoming packets respectively carry interrupt messages disposed to interrupt the processor in performing prior assigned tasks. The method includes the step of determining whether or not a particular incoming packet meets one or more prespecified criteria, at least a first criterion being related to the size of the particular incoming packet. The method further comprises immediately interrupting the processor in accordance with the interrupt message carried by the particular packet, if the particular packet meets all the prespecified criteria, and interrupting the processor in accordance with a specified interrupt coalescing technique, if the incoming particular packet does not meet all of the prespecified criteria.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0009]      FIG. 1  is a schematic diagram showing a network environment such as an Ethernet LAN for implementing embodiments of the invention.  
         [0010]      FIG. 2  is a block diagram showing a data processing system included in the network of  FIG. 1  that is disposed to receive interrupt request packets.  
         [0011]      FIG. 3  is a block diagram showing an adapter or NIC for the data processing system of  FIG. 2  that is configured to implement embodiments of the invention.  
         [0012]      FIG. 4  is a flowchart showing principal steps of an embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0013]     Referring to  FIG. 1 , there is shown a simplified Ethernet LAN  100 , wherein data processing systems  102 - 106 , such as computers or the like, respectively comprise three of the network nodes. Device  108 , such as a printer or the like, comprises a fourth node and respective nodes are interconnected to one other by means of a network transmission path or channel  110 . Path  110  comprises an Ethernet transmission medium, such as a conductive cable or a wireless transmission path. Packets of varying length that convey information, including interrupt request message signals, are routed from one node to another by means of transmission path  110 . Data processing system  100  is configured to implement an embodiment of the invention, when packets containing interrupt messages are coupled thereto.  
         [0014]     Referring to  FIG. 2 , there is shown a simplified block diagram of data processing system  102 . System  102  is provided with a LAN adapter  200 , comprising a network interface card (NIC) that is connected to receive data and instruction information from, and to transmit information into, the Ethernet transmission path  110 . Adapter  200  is configured to implement embodiments of the invention, as described hereinafter. Thus, adapter  200  is disposed to receive incoming external requests to interrupt processor  202  as it is carrying out successive assigned tasks, generally associated with operation of data processing system  102 .  
         [0015]     Data processing system  102  employs a peripheral component interconnect (PCI) local bus architecture. Although the depicted example employs a PCI bus, other bus architectures such as Accelerated Graphics Port (AGP) and Industry Standard Architecture (ISA) may be used. Processor  202  and main memory  204  are connected to PCI local bus  206  through PCI bridge  208 . PCI bridge  208  also may include an integrated memory controller and cache memory for processor  202 . Additional connections to PCI local bus  206  may be made through direct component interconnection or through add-in connectors. In contrast, audio adapter  212 , graphics adapter  214 , and audio/video adapter  218  are connected to PCI local bus  206  by add-in boards inserted into expansion slots. An operating system runs on processor  202  and is used to coordinate and provide control of various components within data processing system  102  in  FIG. 2 . The operating system may be a commercially available operating system such as Windows XP, which is available from Microsoft Corporation. An object oriented programming system such as Java may run in conjunction with the operating system and provides calls to the operating system from Java programs or applications executing on data processing system  102 . “Java” is a trademark of Sun Microsystems, Inc. Instructions for the operating system, the object-oriented programming system may be loaded into main memory  204  for execution by processor  202 .  
         [0016]     Those of ordinary skill in the art will appreciate that the hardware in  FIG. 2  may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash read-only memory (ROM), equivalent nonvolatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in  FIG. 2 . Also, the processes of the present invention may be applied to a multiprocessor data processing system.  
         [0017]     Referring to  FIG. 3 , there is shown LAN adapter or NIC  200  provided with a processor  302 , memory  304  and a storage device  306 , respectively connected to a bus  308 . Bus  308  is disposed to receive packets that are incoming to data processing system  102  from Ethernet transmission path  110 , and is further disposed to provide data and other information to bus  206  of system  102 . Thus, adapter  200  receives the interrupt request packets referred to above in connection with  FIG. 2 . Components  302 - 306  may be readily configured to collectively interact with one other, in order to implement embodiments of the invention described hereinafter. A firmware delay loop  310 , as currently used in conventional interrupt coalescing applications, is also coupled to bus  308 . Other conventional NIC components well known to those skilled in the art are not shown in  FIG. 3 , in order to simplify illustration of embodiments of the invention.  
         [0018]     In a first embodiment of the invention, the length of a locking packet, which typically may be on the order of less than 100 bytes, is stored in memory device  304  or otherwise entered into adapter  200 . Thereafter, each time an incoming packet containing an interrupt signal is received by adapter  200 , respective components thereof cooperatively interact to determine whether the size of the incoming packet is equal to or less than the stored locking packet length. If the size of the incoming packet is equal to or less than such stored length, adapter  200  reads the packet header, to determine whether or not the packet is a broadcast message. If the incoming packet is found not to comprise a broadcast message, the packet is considered to be a locking packet. Thereupon, adapter  200  signals the data processing system  110  to interrupt the processor  202  immediately. As stated above, a locking packet contains a message instructing the data processing system to receive data that immediately follows the locking packet without delay.  
         [0019]     It is thus seen that the above embodiment specifies two criteria that must both be met, in order to interrupt the processor immediately, namely (1) the incoming packet size must be no greater than the prespecified size of a known locking packet, and (2) the incoming packet must not be a broadcast message packet. A broadcast packet should not be used to generate an immediate interrupt, since such packets occur frequently on an Ethernet network, and tend to generate false positives in analyzing the comparative urgency of interrupt messages. A further criterion could be that the packet contains a non-zero payload size.  
         [0020]     In the above embodiment of the invention, if one or both of the stated criteria are not met, the adapter  200  will process the incoming packet in accordance with an interrupt coalescing technique, whereby the interrupt message of the packet will be delayed. Usefully, adapter  200  implements a conventional coalescing technique of a type described above. In accordance therewith, an interrupt of processor  202  will not occur until (1) a prespecified total number of packets have been received by the adapter; (2) a prespecified total number of bytes have been received; (3) a prespecified time period has expired; or (4) a prespecified number of packets have been received, in combination with expiration of a prespecified time period. The firmware delay loop  310  of adapter  200  could be used in implementing one or the other of these techniques. Alternatively, a time counter (not shown) could be substituted for delay loop  310 . It is anticipated that other interrupt coalescing techniques occurring to those of skill in the art could also be used.  
         [0021]     In a further embodiment of the invention, packet points Pt are computed as a function of the actual size Sact of a packet containing an interrupt message that is received by adapter  200 . If S max  and S min  are the maximum and the minimum sizes, respectively, of incoming packets that can be received by adapter  200  from transmission path  110 , and if B v  is a preselected base value, the packet point value P pt  for an incoming packet is computed from the following relationship: 
 
 P   pt =( S   max   −S   min   +B   v )/( S   max   −S   min )  Eqn. (1) 
 
         [0022]     In this embodiment of the invention, a packet point criterion value C v  is selected. The criterion value 1.0 has been found to be particularly useful, but other criterion values could be used as well. Each time an interrupt packet is received by adapter  200 , adapter  200  computes the point value Ppt therefor, from Equation (1). Adapter  200  then adds the computed value to the cumulative sum of the packet points of all previous interrupt packets received by adapter  200 , since the last processor interrupt occurred.  FIG. 3  shows a counter  312  that may be used to keep track of this cumulative sum. When the cumulative packet point sum exceeds the criterion value C v , a processor interrupt will occur. The counter  312  will thereupon also be cleared.  
         [0023]     To illustrate this embodiment of the invention, base value B v  is selected to be 140, S max  is 1500 bytes and S min  is 100 bytes. Each of these values is initially entered into adapter  200 . Upon receiving a small packet having a size of 100 bytes, adapter  200  computes the packet point value P pt  therefor, from Equation (1): 
 
 P   pt =(1500−100+140)/(1500−100)=1.1 points  Eqn. (2) 
 
         [0024]     It will be readily apparent that the point value of 1.1 exceeds the criterion point value of point 1.0. Accordingly, the processor  202  of data processing system  102  will be interrupted immediately, upon receipt of the small packet. On the other hand, if a large incoming packet of 1500 bytes is received by adapter  200 , the following packet point value will result: 
 
 P   pt =(1500−1500+140)/(1500−100)=0.1 points  Eqn. (3) 
 
         [0025]     Thus, when large packets are received, interrupt coalescing occurs so that ten (10) successive large packets will need to be received, in order for the cumulative packet point sum to reach 1.0, and thus generate a processor interrupt.  
         [0026]     It is to be understood that the number of packets required to generate a packet interrupt can be selectively varied by varying the base value B v . Reducing the base value increases the number of packets needed to generate an interrupt, as illustrated by the following, wherein the base value is 99: 
 
 P   pt =(1500−1500+99)/(1500−100)=0.07 points  Eqn. (4) 
 
         [0027]     If each large packet produces a packet point value of 0.07, fourteen (14) packets must be received by adapter  200  before the processor interrupt is generated. However, a small 100 byte packet will produce 1.07 points, so that the processor will be interrupted immediately, in response thereto.  
         [0028]     Increasing the base value decreases the number of packets needed to generate an interrupt, as illustrated by the following, wherein the base value is 650: 
 
 P   pt =(1500−1500+650)/(1500−100)=0.46 points  Eqn. (5) 
 
         [0029]     If each large packet produces a point value of 0.46, three (3) packets must be received by adapter  200  before the processor interrupt is generated. A small 100 byte packet will produce 1.4 points, so that the processor will be interrupted immediately upon receiving the small packet.  
         [0030]     In further embodiments of the invention, minimum packet size S min  could be 64 octets and maximum packet size could be 1518 octets. These sizes include all the frames apart from the preamble. Because of the frame header fields, the CRC and the overhead of the IP and TCP or UDP higher layer protocols, the amount left for useful application data is less then 1518. It is to be emphasized that the above values for S min  and S max  are representative values only, so that other values can be used for S min  and S max  as well. One could incorporate only the actual payload values, for example, excluding Ethernet source and destination addresses.  
         [0031]     Referring to  FIG. 4 , there is shown a flowchart setting forth principal steps of embodiments of the invention. After a packet carrying an interrupt message has been received by the data processing system, as indicated by function block  402 , an analysis must be made to determine whether the packet does or does not meet all criteria for a packet that is sufficiently small and significant to warrant an immediate interrupt. This is shown in  FIG. 4  by decision block  404 . If the packet does meet all criteria, the processor is immediately interrupted, in accordance with the interrupt message carried by the packet, as indicated by function block  406 . Otherwise, an interrupt coalescing technique is applied to the packet, as indicated by function block  408 . Function block  410  shows that after the event of either block  406  or  408 , the system prepares to receive the next incoming packet.  
         [0032]     While the above embodiments have been described with an Ethernet LAN network, it is to be understood that embodiments of the invention could readily be used in connection with a token ring network, as well as with other networks known to those of skill in the art.  
         [0033]     The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Technology Category: 4