Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to memory cells and methods for manufacture thereof. Specifically, the invention relates to a method for manufacturing memory cells free of ONO fence material. 
     2. Discussion of Related Art 
     FIG. 1 shows a cross-sectional view of a portion of a core cell in a NAND-type flash memory device. Fabrication of a NAND-type flash memory device involves depositing a lower polysilicon (“poly I”) layer  2  over tunnel oxide layer  8  and etching it so as to provide the structure shown over active region  10  of FIG.  2 . 
     The exact profile of the etched structure of poly I layer  2  is hard to control. The profile depends on the photoresist profile and the etch process. Consequently, the overlap between the structure of poly I layer  2  and the underlying core field oxide regions  12  vary. FIG. 2 depicts, for example, an edge of the structure of poly I layer  2  not overlapping a flat region of a core field oxide region  12 . Consequently, a recess  14  forms in poly I layer  2  over a sloping portion of core field oxide region  12  that may appear along the entire edge of poly I layer  2 . For example, recess  14  can be caused by a horizontal etching of poly I layer  2 . Recess  14  harbors ONO  4  and poly II layer  6  materials from subsequent ONO  4  and poly II layer  6  depositions. 
     After depositing and etching poly I layer  2 ; as shown in FIG. 1, a triple layer consisting of an oxide-nitride-oxide (“ONO”) stack, shown as ONO  4 , and polysilicon (“poly II”) layer  6  are provided above the poly I layer  2  structure. A tungsten silicide layer  93  and a silicon oxy-nitride (SiON) layer  94  are formed next. 
     FIG. 3 corresponds to a top view of the structure of FIG.  1 . In FIG. 3, core field oxide regions  40   a  and  40   b  correspond to portions of core field oxide regions  12  of FIG. 1; active region  42  corresponds to a portion of active region  10  of FIG. 1; and poly I layer  66  corresponds to a portion of poly I layer  2  of FIG.  1 . 
     Next, successive layers of material are removed from shaded region  100  of the structure  58  of FIG. 3 (“removal steps”): SiON layer  94 , tungsten silicide layer  93 , poly II layer  6 , ONO  4 , and poly I layer  2 . The ONO  4  layer and poly I layer  2  may be removed by “anisotropic” etching techniques. 
     However, if the poly II layer  6  forms in the recess  14 , it may not be removed from the recess  14  in shaded region  100  of FIG.  3 . The poly II layer  6  in the recess  14  also may shield ONO  4  from removal from the recess  14  present in shaded region  100  of FIG.  3 . Remaining ONO  4  (“ONO fence”  16 ) further shields poly I layer  2  from removal from the shaded region  100  of FIG.  3 . 
     Alternatively, edges of the etched poly I layer  2  may overlap with top, flat portions of core field oxide regions  12  and consequently recesses  14  may be absent from the poly I layer  2  as shown in FIG.  4 . However, because of anisotropic etching of ONO  4  layer, following removal of the ONO  4  from shaded region  100  of the structure  58  of FIG. 3, ONO fences  16  may remain. 
     FIG. 5A shows a top view of the structure  60  of FIG. 4 after the removal steps described earlier. ONO fences  16  appear, for example, at positions  48   a ,  48   b ,  48   c , and  48   d  of FIG.  5 A. ONO fences  16  shield some poly I layer  2  material from removal during the removal steps. Remaining poly I materials present, for example, at positions  48   a ,  48   b ,  48   c , and  48   d  of FIG. 5A (“polystringers”  18 ) electrically short NAND-type memory cells. 
     FIG. 5B depicts a cross section of the structure  62  of FIG. 5A showing ONO fence  16  and polystringers  18 . Structure  70  of FIG. 5B corresponds, for example, to a cross section along line X 2 —X 2  of structure  62  of FIG.  5 A. In that cross section, core field oxide regions  12  correspond to portions of core field oxide regions  40   a  and  40   b  of FIG. 5A, and active region  10  corresponds to a portion of active region  42  of FIG.  5 A. Poly I layer  46  of FIG. 5A corresponds to a portion of poly I layer  2  of FIG.  4 . 
     FIG. 6A depicts a matrix of NAND-type flash memory core cells  22  with polystringers occurring, for example, at positions  20 . Consequently, as shown in FIGS. 6A and 6B, following etching, an “ONO fence”  16 , portions of poly II layer  6 , and portions of poly I layer  2  may remain at positions  20 . 
     FIG. 6B corresponds, for example, to a cross section along line X—X of the structure of FIG.  6 A. FIG. 6B depicts a position  20  that may include portions of poly II layer  6  and portions of poly I layer  2  that constitute polystringers  18  that. electrically short NAND-type flash memory core cells  22 , thereby rendering the flash memory core cells inoperable. 
     SUMMARY OF THE INVENTION 
     The present invention removes ONO fence that shield polystringers from removal. Polystringers that cause NAND-type memory core cells to malfunction may then be removed more readily. 
     After a SiON layer, a tungsten silicide layer, a second polysilicon layer, an ONO layer, and a previously etched first polysilicon layer on the surface of an oxide coated silicon substrate have been removed from between NAND-type flash memory core cells, ONO fence and polystringers may remain. In accordance with the present invention, device is exposed to an HF solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily. 
     The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a cross section of a portion of a NAND-type flash memory core cell. 
     FIG. 2 depicts a cross section of a portion of a NAND-type flash memory core cell and a recess  14  formed in the etched poly I layer  2  that may run along the entire edge of the etched poly I layer  2 . 
     FIG. 3 depicts a top view of the structure of FIG. 1 showing shaded region  100  where SiON layer  94 , tungsten silicide layer  93 , poly II layer  6 , ONO  4  layer, and poly I layer  2  are removed. 
     FIG. 4 depicts a cross section of a portion of a NAND-type flash memory core cell where edges of the etched poly I layer  2  overlap with portions of the top, flat regions of the core field oxide regions  12  and no recesses  14  are present. 
     FIG. 5A depicts a structure  62 , that corresponds to a top view of the structure  60  of FIG. 4, after material has been removed, with positions  48   a ,  48   b ,  48   c , and  48   d  where ONO fences  16  and polystringers  18  of FIG. 4B may appear. 
     FIG. 5B depicts a structure  70  that corresponds to a cross section of the structure  62  of FIG. 5A along line X 2 —X 2  showing ONO fence  16  and polystringers  18 . 
     FIG. 6A depicts a prospective view of four NAND-type flash memory core cells  22  and the polystringers  18  at positions  20  that cause electrical short circuits among NAND-type flash memory core cells  22 . 
     FIG. 6B depicts a cross-sectional view of the structure of FIG. 6A showing polystringers at position  20  between NAND-type flash memory core cells  22 . 
     FIG. 7 depicts a cross-sectional view of a structure  75  showing a core cell of a NAND-type flash memory devices including a poly I layer  2  and an oxide mask layer  26 . 
     FIG. 8 depicts a cross-sectional view of structure  80  showing structure  75  of FIG. 7 after the oxide mask  26  has been etched. 
     FIG. 9A depicts a top view of core field oxide regions  61   a ,  61   b , and  61   c  and active regions  62   a  and  62   b  overlapped by patterned poly I structures  63   a  and  63   b  with oxide mask coating. 
     FIG. 9B depicts a structure  85  that corresponds to a cross-sectional view of the structure of FIG. 9A along line X—X. 
     FIG. 10 depicts a cross-sectional view of a structure  90  showing structure  85  after a second layer  28  of polysilicon has been deposited. 
     FIG. 11 depicts a cross-sectional view of structure  95  showing polysilicon spacers  24  formed on sides of poly I layer  2 . 
     FIG. 12 depicts a prospective view of completed NAND-type flash memory core cells  22  with source/drain region  102 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     One embodiment of the present invention is provided in a NAND-type flash memory core cell formed on a silicon substrate  38  having an active region  10  between core field oxide regions  12 , as shown in FIG.  7 . 
     In FIG. 7, tunnel oxide layer  8  is grown over silicon substrate  38  by directing a stream consisting of argon and O 2  gases over the surface of silicon substrate  38  at flow rates of 12.6 L/min and 1.33 L/min, respectively, which silicon substrate  38  is heated to a temperature of 1050 degrees Celsius. In this embodiment, a tunnel oxide layer  8  is formed to 87 angstroms in thickness. 
     Next, a layer of amorphous silicon is deposited over tunnel oxide layer  8  using a low pressure chemical vapor deposition (LPCVD) process at a temperature of 530 degrees Celsius. The LPCVD process directs a mixture of silane gas (SiH 4 ) and phosphene gas (PH 3 ) towards tunnel oxide layer  8  at flow rates of 2000 sccm and 2.2 sccm, respectively. The amorphous silicon is thereby doped in situ by the phosphene gas to become an N-type amorphous silicon region that corresponds to an intermediate form of polysilicon (poly I) layer  2 . In this embodiment, the poly I layer  2  is formed to 700 angstroms in thickness. 
     An oxide layer  26  is next formed over poly I layer  2  using a CVD process. In the CVD process, a mixture of silane (SiH 4 ) and N 2 O gases with flow rates of 1 L/min and 60 L/min, respectively, are directed towards the surface of the poly I layer  2 , at a temperature between 400 to 800 degrees Celsius. A temperature of 800 degrees Celsius is suitable. In this embodiment, oxide layer  26  is 300 to 400 angstroms thick. 
     Thereafter, a photoresist material is applied and patterned over the structure  75  of FIG. 7, including the portion of oxide layer  26  over active region  10 . 
     Next, as shown in FIG. 8, oxide mask  36  is formed over active region  10  using either a dry or wet etch technique. If a wet etch technique is used, structure  75  of FIG. 7, is exposed to a 40:1 hydrogen-fluoride (HF) solution for a suitable time such as 80 seconds. 
     Several dry etch techniques are suitable. In one dry etch technique, methyl-trifluoride (CHF 3 ) and helium (He) gases having flow rates of 75 sccm and 6000 sccm, respectively, are directed at structure  75  for 6 seconds. An alternate dry etch technique is to expose the device to fluoro-form (CF 4 ) and CHF 3  at flow rates of 15 sccm and 35 sccm, respectively, for 10 seconds. 
     Next, poly I layer  2  is etched using an anisotropic dry etch technique so as to remove the portion of poly I layer  2  above core field oxide regions  12 . A suitable dry etch for this purpose directs chlorine (Cl 2 ) and hydrogen bromide (HBr) gases at flow rates of 30 sccm and 70 sccm, respectively, at structure  80  of FIG. 8 until etching of tunnel oxide layer  8  is detected. Tunnel oxide layer  8  thereby acts as the “stop layer”. In this embodiment, the RF power of the etcher is set to 120 W at a pressure of 125 millitorr. 
     FIG. 9A shows a top view of core field oxide regions  61   a ,  61   b , and  61   c  and active regions  62   a  and  62   b  over silicon substrate  38 . Structure  85  of FIG. 9B corresponds, for example, to a cross section along line X—X of FIG.  9 A. In that cross-section, core field oxide regions  12  correspond to portions of core field oxide regions  61   a  and  61   b , and active region  10  corresponds to a portion of active region  62   a.    
     Poly I layer  2  is protected by photoresist during the polysilicon etch step described above. Ideally, patterned poly I structures  63   a  and  63   b  are provided covering the sloped “bird&#39;s beaks” portions of core field oxide regions  61   a ,  61   b , and  61   c  thereby exposing “flat” regions  64   a ,  64   b , and  64   c  of core field oxide regions  61   a ,  61   b , and  61   c . However, a misalignment may occur so that patterned poly I structures  63   a  and  63   b  expose the sloped bird&#39;s beak regions of core field oxide regions of  61   a ,  61   b , and  61   c.    
     As discussed above, such misalignment may lead to a recess and polystringer formation. As shown in FIG. 10, the present invention provides a second layer of amorphous silicon over the structure  85  of FIG.  9 B. Amorphous silicon layer is formed directing a mixture of silane gas (SiH 4 ) and phosphene (PH 3 ) over structure  85  at rates of 2000 sccm and 2.8 sccm, respectively, using a CVD process with a temperature of 530 degrees. The second layer of amorphous silicon is thereby doped in situ by the phosphene becoming an N-type amorphous silicon region much like poly I layer  2  The second layer of amorphous silicon corresponds to an intermediate form of second layer  28  of polysilicon. In this embodiment, second layer  28  has a thickness between 800 and 900 angstroms. 
     Second layer  28  is next etched anisotropically leaving structure  95  with polysilicon spacers  24 , as shown in FIG.  11 . In this etching step, etched oxide mask region  36  acts as a “stop layer”. Polysilicon spacers  24  extend the portions of poly I layer  2  in structure  85  of FIG. 9B sealing any recesses, such as recess  14 , that lead to polystringer formation in the prior art. 
     Oxide mask  36  is then removed. A suitable technique is a wet etch technique whereby the structure  95  of FIG. 11 is exposed to a 40:1 HF solution for 80 seconds. 
     Next, an ONO  4  dielectric layer is deposited conventionally. In this embodiment, ONO  4  layer includes a 50 angstroms thick lower oxide layer, an 80 angstroms thick middle nitride layer, and a between 40 and 45 angstroms thick upper oxide layer  4   a . The upper oxide layer  4   a  (not separately shown in the Figures) is achieved by oxidizing approximately 25 angstroms of the nitride layer. In this embodiment, the thickness of NO  4  is approximately 130 angstroms. 
     Next, a third layer of amorphous silicon is deposited over the ONO layer using a mixture of silane gas (SiH 4 ) and phosphene (PH 3 ) in an LPCVD process. This third layer of amorphous silicon corresponds to an intermediate form of a third layer of polysilicon (poly II layer)  6 . In this embodiment, the thickness of the poly II layer  6  is 1200 angstroms. 
     Next a layer of tungsten silicide  93  is deposited conventionally over the device by a mixture of silane and WF 6  using a CVD process In this embodiment, the thickness of the tungsten silicide layer is 1500 angstroms. 
     Next a layer of silicon oxy-nitride  94  (SiON) is deposited conventionally over the tungsten silicide layer using a mixture of silane and N 2 O in a CVD process. In this embodiment, the thickness of the SiON layer is 1500 angstroms. 
     FIG. 3 depicts a top view of the structure of FIG.  1 . In FIG. 3, core field oxide regions  40   a  and  40   b  correspond to portions of core field oxide regions  12  of FIG. 1; active region  42  corresponds to a portion of active region  10  of FIG. 1; and poly I layer  66  corresponds to poly I layer  2  of FIG.  1 . 
     The SiON layer  94 , tungsten silicide layer  93 , poly II layer  6 , the ONO  4  layer, and poly I layer  2  with polysilicon spacers  24  are then removed successively from region  100  of the structure  58  of FIG.  3 . Suitable techniques to remove SiON layer  94 , tungsten silicide layer  93 , poly II layer  6  are separate etches. To remove poly II layer  6 , the stop layer may be set as the upper oxide layer  4   a  of ONO  4 . Suitable techniques to remove ONO  4  layer and poly I layer  2  are separate “self align etches”. 
     Any ONO fences, for example, ONO fence  16  present at positions  48   a ,  48   b ,  48   c , and  48   d  of FIG. 5A, are next removed (“ONO fence removal step”). A suitable technique is to expose the structure  62  of FIG. 5A to a 100:1 hydrogen fluoride (HF) solution at room temperature for a maximum duration of 60 seconds. An alternative technique is to expose the structure  62  of FIG. 5A to a 40:1 hydrogen fluoride (HF) solution at room temperature for a maximum duration of 35 seconds. A second alternative technique is to perform a conventional buffer oxide etch for 25 seconds. 
     The device is then cleaned using a conventional RCA clean process. A suitable technique involves dipping the device in a 5:1:1 water, hydrogen peroxide, and ammonia (H 2 O:H 2 O 2 :NH 4 OH) solution with a temperature of 60 degrees Celsius for 5 minutes and then rinsing conventionally. Alternatively, the structure may be dipped in a 6:1:1 water, hydrogen peroxide, and hydrogen chloride (H 2 O:H 2 O 2 :HCl) solution with a temperature of 60 degrees Celsius for 5 minutes and then rinsed conventionally. 
     Absent an ONO fence removal step above or in addition to the ONO fence removal step, polystringers such as at positions  48   a ,  48   b ,  48   c , and  48   d  of FIG. 5A are next removed (hereinafter “oxidation step”). A suitable technique involves heating the wafer to approximately 900 degrees Celsius. O 2  gas is then directed towards the wafer with a flow rate of 14 L/min for 45 minutes. 
     Almost all polystringers are thereby removed by oxidation. For example, on an 8 inch wafer including NAND-type memory device core cells, very few polystringers may remain on the outside edges. 
     An additional benefit of the oxidation step is that poly I layer  2  rounds at the lower edges. As a result, the coupling ratio improves between a control gate and floating gate in a NAND-type memory device. The advantage is that with a higher coupling ratio, a smaller voltage is required at the control gate to achieve a desired voltage at the floating gate. For example, in a NAND-type memory device, less control gate voltage will be required to perform channel program and erase functions. 
     An additional advantage results from the rounded lower edges of the floating gate. The lower edges of the floating gate become thicker thus increasing the breakdown voltage and hence improving the reliability of the floating gate. 
     The remaining processing steps (“remaining steps”) include: an MDD implant to form source/drain regions  102 ; a spacer deposition and etch; an HTO deposition; a contact mask and etch; a contact implant; a metal deposition and etch; and nitride deposition. The remaining steps proceed in the conventional manner. Completed NAND-type memory cells  22  are shown in FIG.  12 . 
     The foregoing description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Numerous modifications or variations are possible in light of the above teachings. The embodiments were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications which are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are legally and equitably entitled.

Technology Category: 5