Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to a multi-jack detector, and more particularly to a multi-jack detector for detecting states of jacks using a single I/O pin.  
           [0003]    2. Description of the Related Art  
           [0004]    Along with advances in technologies, a variety of types of jacks, such as Line, Surround, Center, and LFE-Out output jacks are often disposed in a single apparatus. As a result, an electronic device such as an audio card (i.e., a sound card) usually needs a jack detector to detect the state of each jack in order to detect whether external terminals are inserted into the output jacks.  
           [0005]    [0005]FIG. 1 is a schematic illustration showing the connection between a control unit and multiple phone-jacks. As shown in FIG. 1, the control unit  11  mainly outputs audio signals to each of the phone-jacks PJ 1 , PJ 2  and PJ 3 , and detects the connection state of each jack. The jack PJ 1  outputs main audio signals (Line-out R &amp; L), the jack PJ 2  outputs LFE-out audio signals (LFE-out) and the center output audio signals (CEN-out), and the jack PJ 3  outputs surround audio signals (Surround-out R &amp; L). Each of the phone-jacks PJ 1 , PJ 2  and PJ 3  of the system has at least one switch (e.g., pins  2  and  3  of each jack) to indicate the insertion states of the external terminals. Because in FIG. 1 the system has three phone-jacks PJ 1 , PJ 2  and PJ 3 , the control unit  11  needs three I/O pins DT 1 , DT 2  and DT 3  to receive insertion state signals of the phone-jacks PJ 1 , PJ 2  and PJ 3 . If the system has five phone-jacks, the control unit  11  needs five I/O pins to receive the insertion state signals of the five jacks. In the integrated circuit (IC) manufacturing processes, the more the number of I/O pins is, the more the manufacturing process costs. Therefore, if the number of I/O pins is reduced, the manufacturing cost of the control unit may be decreased.  
         SUMMARY OF THE INVENTION  
         [0006]    It is therefore one of the many objects of the invention to provide a multi-jack detector for detecting states of jacks using a single I/O pin according to impedance distribution.  
           [0007]    To achieve the above-mentioned object, a multi-jack detector for detecting states of a plurality of jacks is disclosed. Each jack comprises a first switch having a first normally closed terminal and a first output terminal. The multi-jack detector comprises a plurality of bias resistors each coupled to one of the first output terminals, respectively; a control unit for determining the states of the plurality of jacks; wherein the first normally closed terminals are commonly coupled to a first node and the control unit determines the states of the plurality of jacks according to a voltage at the first node.  
           [0008]    Because the voltage at the first node is different for each state of the jacks, the detector can detects the states of the jacks using a single I/O pin. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a schematic illustration showing the connection between a control unit and multiple phone-jacks.  
         [0010]    [0010]FIG. 2 shows a multi-jack detector applied to multiple phone-jacks according to a first embodiment of the invention.  
         [0011]    [0011]FIG. 3 is a partial block diagram showing an equivalent circuit and the control unit.  
         [0012]    [0012]FIG. 4 shows the resistance of the load resistor RL and the magnitude of the input voltage Vin corresponding to the states of the phone-jacks PJ 1 , PJ 2  and PJ 3 .  
         [0013]    [0013]FIG. 5 shows a multi-jacks detector applied to multiple phone-jacks according to a second embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]    The multi-jack detector of the invention will be described hereinafter with reference to the accompanying drawings.  
         [0015]    [0015]FIG. 2 shows a multi-jack detector applied to multiple phone-jacks according to a first embodiment of the invention. Referring to FIG. 2, an audio signal output system includes three phone-jacks PJ 1 , PJ 2  and PJ 3 , and a control unit  21 . The phone-jacks PJ 1 , PJ 2  and PJ 3  have pins  1  and  4  serving as output terminals for audio signals, pins  5  serving as grounded terminals, and pins  2  and  3  serving as NC (normally closed) terminals. When an external terminal is not inserted into the phone-jack, the NC terminal is electrically connected to the output terminal. When the external terminal is inserted into the phone-jack, the NC terminal is not electrically connected to the output terminal. The pins  1  and  4  of the phone-jack PJ 1  are grounded via a bias resistor R 1  and a matching resistor R 2 , respectively. The pins  1  and  4  of the phone-jack PJ 2  are grounded via a bias resistor R 3  and a matching resistor R 4 , respectively. The pins  1  and  4  of the phone-jack PJ 3  are grounded via a bias resistor R 5  and a matching resistor R 6 , respectively. The matching resistors R 2 , R 4  and R 6  are resistors for matching the two output terminals of each jack, and have resistances equal to those of the bias resistors R 1 , R 3  and R 5 , respectively. Of course, if resistance matching is not an issue, the matching resistors may also be omitted. The pins  2  of the phone-jacks PJ 1 , PJ 2  and PJ 3  are connected together, and connected to a state detection I/O pin (I/O Pin) DT 1  of the control unit  21  via a filter resistor Rf, which may also be omitted. If the resistance of each bias resistor is properly selected to make the voltages at the I/O pin DT 1  in various states different from each other or one another, the system may detect the terminal insertion state of each of the phone-jacks PJ 1 , PJ 2  and PJ 3  using a single I/O pin, thereby reducing the number of I/O pins.  
         [0016]    [0016]FIG. 3 is a partial block diagram showing an equivalent circuit of the multiple phone-jacks and the control unit  21  in FIG. 2. As shown in FIG. 3, the equivalent circuit obtained by viewing outwardly from the detection pin DT 1  of the control unit  21  includes a pull-up resistor Rp, a filter resistor Rf and a load resistor RL, which are connected in series, and a filter capacitor Cf, which is connected in parallel with the filter resistor Rf and the load resistor RL, wherein the load resistor RL is defined as the resistance by viewing outwardly from the filter resistor Rf. If the resistance of the filter resistor Rf is far smaller than that of the load resistor RL, the filter resistor Rf may be neglected. Thus, the input voltage Vin may be regarded as a bias voltage between the pull-up resistor Rp and the load resistor RL. Because the resistances of the load resistor RL are different in various connection states of the jacks, the detected input voltages Vin at the pin DT 1  are also different. Consequently, the control unit  21  according to this embodiment of the invention utilizes the converter  41  to convert the input voltage Vin at the detection pin DT 1  into a decoding signal, and then utilizes the decoder  42  to generate detection signals S 1 , S 2  and S 3  according to the decoding signal. The converter  41  may be an analog-to-digital converter.  
         [0017]    If the resistances of the bias resistors R 1 , R 3  and R 5  are 2R, 4R and 8R, respectively, the resistance of the pull-up resistor Rp is R, and the voltage source Vdd is 5V, then the listing of the states of the phone-jacks PJ 1 , PJ 2 , and PJ 3  corresponding to the resistance of the load resistor RL and the magnitude of the input voltage Vin are shown in FIG. 4. Because there are three phone-jacks PJ 1 , PJ 2  and PJ 3 , there are eight connection states of the jacks in total. The states are described in the following.  
         [0018]    In state 0, there is no external terminal being inserted into the phone-jacks PJ 1 , PJ 2  and PJ 3 . Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistors R 1 , R 3  and R 5  connected in parallel. That is, the load resistor RL is 8/7R and the input voltage Vin is 2.67V.  
         [0019]    In state 1, there is an external terminal being inserted into the phone-jack PJ 3 . Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistors R 1  and R 3  connected in parallel. That is, the load resistor RL is 8/6R and the input voltage Vin is 2.86V.  
         [0020]    In state 2, there is an external terminal being inserted into the phone-jack PJ 2 . Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistors R 1  and R 5  connected in parallel. That is, the load resistor RL is 8/5R and the input voltage Vin is 3.08V.  
         [0021]    In state 3, there are two external terminals being inserted into the phone-jack PJ 2  and PJ 3 , respectively. Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistor R 1 . That is, the load resistor RL is 8/4R and the input voltage Vin is 3.33V.  
         [0022]    In state 4, there is an external terminal being inserted into the phone-jack PJ 1 . Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistors R 3  and R 5  connected in parallel. That is, the load resistor RL is 8/3R and the input voltage Vin is 3.64V.  
         [0023]    In state 5, there are two-external terminals being inserted into the phone-jack PJ 1  and PJ 3 , respectively. Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistor R 3 . That is, the load resistor RL is 8/2R and the input voltage Vin is 4V.  
         [0024]    In state 6, there are two external terminals being inserted into the phone-jack PJ 1  and PJ 2 , respectively. Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  equals to that of the bias resistor R 5 . That is, the load resistor RL is 8/1R and the input voltage Vin is 4.4V.  
         [0025]    In state 7, there are three external terminals being inserted into the phone-jack PJ 1 , PJ 2  and PJ 3 , respectively. Therefore, the equivalent resistance formed by the phone-jacks PJ 1 , PJ 2  and PJ 3  is infinite. That is, the load resistor RL is cut off and the input voltage Vin is 5V.  
         [0026]    In this embodiment, when the detection signal S 1  is H, it means that an external terminal is inserted into the phone-jack PJ 1 . The same interpretation can be applied to the output states of the detection signals S 2  and S 3  and will be readily appreciated by one skilled in the art without further descriptions.  
         [0027]    Consequently, it can be understood from FIG. 4 that the resistances of the load resistor RL and the input voltages Vin are different no matter which of the phone-jacks PJ 1 , PJ 2  and PJ 3  has been inserted with an external terminal. So, the control unit  21  is capable of detecting which of the phone-jacks PJ 1 , PJ 2  and PJ 3  has been inserted with an external terminal accordingly.  
         [0028]    [0028]FIG. 5 shows a multi-jack detector applied to multiple phone-jacks according to a second embodiment of the invention. In the first embodiment of FIG. 2, the pins  2  of the phone-jacks PJ 1 , PJ 2  and PJ 3  are connected together. However, in the second embodiment of FIG. 5, the pins  2  of the phone-jacks PJ 1 , PJ 2  and PJ 3  are coupled together through adjusting resistors R 7 , R 8  and R 9 , respectively. By utilizing resistors positioned at different locations, such as R 1 , R 3 , R 5  at pin  1 &#39;s, R 2 , R 4 , R 6  at pin  4 &#39;s, and R 7 , R 8 , R 9  at pin  2 &#39;s, the resistances needed may be adjusted with more flexibility. In the second embodiment, for example, the resistances of the bias resistors R 1 , R 3  and R 5  and the pull-up resistor Rp are set to be R, and the resistances of the adjusting resistors R 7 , R 8  and R 9  are set to be R, 3R and 7R, respectively. Thus, it is possible to generate different load resistances and input voltages under different states.  
         [0029]    While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.

Technology Category: 5