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0
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stringclasses 1
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stringlengths 24
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0 | rasdaemon-master | rasdaemon-master/mce-intel-tulsa.c | /*
* The code below came from Andi Kleen/Intel/SuSe mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <stdio.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
/* See IA32 SDM Vol3B Appendix E.4.1 ff */
static struct numfield corr_numbers[] = {
NUMBER(32, 39, "Corrected events"),
{}
};
static struct numfield ecc_numbers[] = {
HEXNUMBER(44, 51, "ECC syndrome"),
{},
};
static struct field tls_bus_status[] = {
SBITFIELD(16, "Parity error detected during FSB request phase"),
SBITFIELD(17, "Partity error detected on Core 0 request's address field"),
SBITFIELD(18, "Partity error detected on Core 1 request's address field"),
FIELD_NULL(19),
SBITFIELD(20, "Parity error on FSB response field detected"),
SBITFIELD(21, "FSB data parity error on inbound date detected"),
SBITFIELD(22, "Data parity error on data received from Core 0 detected"),
SBITFIELD(23, "Data parity error on data received from Core 1 detected"),
SBITFIELD(24, "Detected an Enhanced Defer parity error phase A or phase B"),
SBITFIELD(25, "Data ECC event to error on inbound data correctable or uncorrectable"),
SBITFIELD(26, "Pad logic detected a data strobe glitch or sequencing error"),
SBITFIELD(27, "Pad logic detected a request strobe glitch or sequencing error"),
FIELD_NULL(28),
FIELD_NULL(31),
{}
};
static char *tls_front_error[0xf] = {
[0x1] = "Inclusion error from core 0",
[0x2] = "Inclusion error from core 1",
[0x3] = "Write Exclusive error from core 0",
[0x4] = "Write Exclusive error from core 1",
[0x5] = "Inclusion error from FSB",
[0x6] = "SNP stall error from FSB",
[0x7] = "Write stall error from FSB",
[0x8] = "FSB Arbiter Timeout error",
[0x9] = "CBC OOD Queue Underflow/overflow",
};
static char *tls_int_error[0xf] = {
[0x1] = "Enhanced Intel SpeedStep Technology TM1-TM2 Error",
[0x2] = "Internal timeout error",
[0x3] = "Internal timeout error",
[0x4] = "Intel Cache Safe Technology Queue full error\n"
"or disabled ways in a set overflow",
};
struct field tls_int_status[] = {
FIELD(8, tls_int_error),
{}
};
struct field tls_front_status[] = {
FIELD(0, tls_front_error),
{}
};
struct field tls_cecc[] = {
SBITFIELD(0, "Correctable ECC event on outgoing FSB data"),
SBITFIELD(1, "Correctable ECC event on outgoing core 0 data"),
SBITFIELD(2, "Correctable ECC event on outgoing core 1 data"),
{}
};
struct field tls_uecc[] = {
SBITFIELD(0, "Uncorrectable ECC event on outgoing FSB data"),
SBITFIELD(1, "Uncorrectable ECC event on outgoing core 0 data"),
SBITFIELD(2, "Uncorrectable ECC event on outgoing core 1 data"),
{}
};
static void tulsa_decode_bus(struct mce_event *e, uint64_t status)
{
decode_bitfield(e, status, tls_bus_status);
}
static void tulsa_decode_internal(struct mce_event *e, uint64_t status)
{
uint32_t mca = (status >> 16) & 0xffff;
if ((mca & 0xfff0) == 0)
decode_bitfield(e, mca, tls_front_status);
else if ((mca & 0xf0ff) == 0)
decode_bitfield(e, mca, tls_int_status);
else if ((mca & 0xfff0) == 0xc000)
decode_bitfield(e, mca, tls_cecc);
else if ((mca & 0xfff0) == 0xe000)
decode_bitfield(e, mca, tls_uecc);
}
void tulsa_decode_model(struct mce_event *e)
{
decode_numfield(e, e->status, corr_numbers);
if (e->status & (1ULL << 52))
decode_numfield(e, e->status, ecc_numbers);
/* MISC register not documented in the SDM. Let's just dump hex for now. */
if (e->status & MCI_STATUS_MISCV)
mce_snprintf(e->mcistatus_msg, "MISC format %llx value %llx\n",
(long long)(e->status >> 40) & 3,
(long long)e->misc);
if ((e->status & 0xffff) == 0xe0f)
tulsa_decode_bus(e, e->status);
else if ((e->status & 0xffff) == (1 << 10))
tulsa_decode_internal(e, e->status);
}
|
0 | rasdaemon-master | rasdaemon-master/ras-report.c | /*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/utsname.h>
#include <sys/socket.h>
#include <sys/un.h>
#include "ras-report.h"
static int setup_report_socket(void)
{
int sockfd = -1;
int rc = -1;
struct sockaddr_un addr;
sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
if (sockfd < 0) {
return -1;
}
memset(&addr, 0, sizeof(struct sockaddr_un));
addr.sun_family = AF_UNIX;
strncpy(addr.sun_path, ABRT_SOCKET, sizeof(addr.sun_path));
addr.sun_path[sizeof(addr.sun_path) - 1] = '\0';
rc = connect(sockfd, (struct sockaddr *)&addr, sizeof(struct sockaddr_un));
if (rc < 0) {
close(sockfd);
return -1;
}
return sockfd;
}
static int commit_report_basic(int sockfd)
{
char buf[INPUT_BUFFER_SIZE];
struct utsname un;
int rc = -1;
if (sockfd < 0) {
return rc;
}
memset(buf, 0, INPUT_BUFFER_SIZE);
memset(&un, 0, sizeof(struct utsname));
rc = uname(&un);
if (rc < 0) {
return rc;
}
/*
* ABRT server protocol
*/
sprintf(buf, "PUT / HTTP/1.1\r\n\r\n");
rc = write(sockfd, buf, strlen(buf));
if (rc < strlen(buf)) {
return -1;
}
sprintf(buf, "PID=%d", (int)getpid());
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
return -1;
}
sprintf(buf, "EXECUTABLE=/boot/vmlinuz-%s", un.release);
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
return -1;
}
sprintf(buf, "TYPE=%s", "ras");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
return -1;
}
return 0;
}
static int set_mc_event_backtrace(char *buf, struct ras_mc_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"error_count=%d\n" \
"error_type=%s\n" \
"msg=%s\n" \
"label=%s\n" \
"mc_index=%c\n" \
"top_layer=%c\n" \
"middle_layer=%c\n" \
"lower_layer=%c\n" \
"address=%llu\n" \
"grain=%llu\n" \
"syndrome=%llu\n" \
"driver_detail=%s\n", \
ev->timestamp, \
ev->error_count, \
ev->error_type, \
ev->msg, \
ev->label, \
ev->mc_index, \
ev->top_layer, \
ev->middle_layer, \
ev->lower_layer, \
ev->address, \
ev->grain, \
ev->syndrome, \
ev->driver_detail);
strcat(buf, bt_buf);
return 0;
}
static int set_mce_event_backtrace(char *buf, struct mce_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"bank_name=%s\n" \
"error_msg=%s\n" \
"mcgstatus_msg=%s\n" \
"mcistatus_msg=%s\n" \
"mcastatus_msg=%s\n" \
"user_action=%s\n" \
"mc_location=%s\n" \
"mcgcap=%lu\n" \
"mcgstatus=%lu\n" \
"status=%lu\n" \
"addr=%lu\n" \
"misc=%lu\n" \
"ip=%lu\n" \
"tsc=%lu\n" \
"walltime=%lu\n" \
"cpu=%u\n" \
"cpuid=%u\n" \
"apicid=%u\n" \
"socketid=%u\n" \
"cs=%d\n" \
"bank=%d\n" \
"cpuvendor=%d\n", \
ev->timestamp, \
ev->bank_name, \
ev->error_msg, \
ev->mcgstatus_msg, \
ev->mcistatus_msg, \
ev->mcastatus_msg, \
ev->user_action, \
ev->mc_location, \
ev->mcgcap, \
ev->mcgstatus, \
ev->status, \
ev->addr, \
ev->misc, \
ev->ip, \
ev->tsc, \
ev->walltime, \
ev->cpu, \
ev->cpuid, \
ev->apicid, \
ev->socketid, \
ev->cs, \
ev->bank, \
ev->cpuvendor);
strcat(buf, bt_buf);
return 0;
}
static int set_aer_event_backtrace(char *buf, struct ras_aer_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"error_type=%s\n" \
"dev_name=%s\n" \
"msg=%s\n", \
ev->timestamp, \
ev->error_type, \
ev->dev_name, \
ev->msg);
strcat(buf, bt_buf);
return 0;
}
static int set_non_standard_event_backtrace(char *buf, struct ras_non_standard_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"severity=%s\n" \
"length=%d\n", \
ev->timestamp, \
ev->severity, \
ev->length);
strcat(buf, bt_buf);
return 0;
}
static int set_arm_event_backtrace(char *buf, struct ras_arm_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"error_count=%d\n" \
"affinity=%d\n" \
"mpidr=0x%lx\n" \
"midr=0x%lx\n" \
"running_state=%d\n" \
"psci_state=%d\n", \
ev->timestamp, \
ev->error_count, \
ev->affinity, \
ev->mpidr, \
ev->midr, \
ev->running_state, \
ev->psci_state);
strcat(buf, bt_buf);
return 0;
}
static int set_devlink_event_backtrace(char *buf, struct devlink_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"bus_name=%s\n" \
"dev_name=%s\n" \
"driver_name=%s\n" \
"reporter_name=%s\n" \
"msg=%s\n", \
ev->timestamp, \
ev->bus_name, \
ev->dev_name, \
ev->driver_name, \
ev->reporter_name, \
ev->msg);
strcat(buf, bt_buf);
return 0;
}
static int set_diskerror_event_backtrace(char *buf, struct diskerror_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"dev=%s\n" \
"sector=%llu\n" \
"nr_sector=%u\n" \
"error=%s\n" \
"rwbs=%s\n" \
"cmd=%s\n", \
ev->timestamp, \
ev->dev, \
ev->sector, \
ev->nr_sector, \
ev->error, \
ev->rwbs, \
ev->cmd);
strcat(buf, bt_buf);
return 0;
}
static int set_mf_event_backtrace(char *buf, struct ras_mf_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"pfn=%s\n" \
"page_type=%s\n" \
"action_result=%s\n", \
ev->timestamp, \
ev->pfn, \
ev->page_type, \
ev->action_result);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_poison_event_backtrace(char *buf, struct ras_cxl_poison_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"trace_type=%s\n" \
"region=%s\n" \
"region_uuid=%s\n" \
"hpa=0x%lx\n" \
"dpa=0x%lx\n" \
"dpa_length=0x%x\n" \
"source=%s\n" \
"flags=%u\n" \
"overflow_timestamp=%s\n", \
ev->timestamp, \
ev->memdev, \
ev->host, \
ev->serial, \
ev->trace_type, \
ev->region, \
ev->uuid, \
ev->hpa, \
ev->dpa, \
ev->dpa_length, \
ev->source, \
ev->flags, \
ev->overflow_ts);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_aer_ue_event_backtrace(char *buf, struct ras_cxl_aer_ue_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"error_status=%u\n" \
"first_error=%u\n", \
ev->timestamp, \
ev->memdev, \
ev->host, \
ev->serial, \
ev->error_status, \
ev->first_error);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_aer_ce_event_backtrace(char *buf, struct ras_cxl_aer_ce_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"error_status=%u\n", \
ev->timestamp, \
ev->memdev, \
ev->host, \
ev->serial, \
ev->error_status);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_overflow_event_backtrace(char *buf, struct ras_cxl_overflow_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"log_type=%s\n" \
"count=%u\n" \
"first_ts=%s\n" \
"last_ts=%s\n", \
ev->timestamp, \
ev->memdev, \
ev->host, \
ev->serial, \
ev->log_type, \
ev->count, \
ev->first_ts, \
ev->last_ts);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_generic_event_backtrace(char *buf, struct ras_cxl_generic_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"log_type=%s\n" \
"hdr_uuid=%s\n" \
"hdr_flags=0x%x\n" \
"hdr_handle=0x%x\n" \
"hdr_related_handle=0x%x\n" \
"hdr_timestamp=%s\n" \
"hdr_length=%u\n" \
"hdr_maint_op_class=%u\n", \
ev->hdr.timestamp, \
ev->hdr.memdev, \
ev->hdr.host, \
ev->hdr.serial, \
ev->hdr.log_type, \
ev->hdr.hdr_uuid, \
ev->hdr.hdr_flags, \
ev->hdr.hdr_handle, \
ev->hdr.hdr_related_handle, \
ev->hdr.hdr_timestamp, \
ev->hdr.hdr_length, \
ev->hdr.hdr_maint_op_class);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_general_media_event_backtrace(char *buf, struct ras_cxl_general_media_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"log_type=%s\n" \
"hdr_uuid=%s\n" \
"hdr_flags=0x%x\n" \
"hdr_handle=0x%x\n" \
"hdr_related_handle=0x%x\n" \
"hdr_timestamp=%s\n" \
"hdr_length=%u\n" \
"hdr_maint_op_class=%u\n" \
"dpa=0x%lx\n" \
"dpa_flags=%u\n" \
"descriptor=%u\n" \
"type=%u\n" \
"transaction_type=%u\n" \
"channel=%u\n" \
"rank=%u\n" \
"device=0x%x\n", \
ev->hdr.timestamp, \
ev->hdr.memdev, \
ev->hdr.host, \
ev->hdr.serial, \
ev->hdr.log_type, \
ev->hdr.hdr_uuid, \
ev->hdr.hdr_flags, \
ev->hdr.hdr_handle, \
ev->hdr.hdr_related_handle, \
ev->hdr.hdr_timestamp, \
ev->hdr.hdr_length, \
ev->hdr.hdr_maint_op_class, \
ev->dpa, \
ev->dpa_flags, \
ev->descriptor, \
ev->type, \
ev->transaction_type, \
ev->channel, \
ev->rank, \
ev->device);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_dram_event_backtrace(char *buf, struct ras_cxl_dram_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"log_type=%s\n" \
"hdr_uuid=%s\n" \
"hdr_flags=0x%x\n" \
"hdr_handle=0x%x\n" \
"hdr_related_handle=0x%x\n" \
"hdr_timestamp=%s\n" \
"hdr_length=%u\n" \
"hdr_maint_op_class=%u\n" \
"dpa=0x%lx\n" \
"dpa_flags=%u\n" \
"descriptor=%u\n" \
"type=%u\n" \
"transaction_type=%u\n" \
"channel=%u\n" \
"rank=%u\n" \
"nibble_mask=%u\n" \
"bank_group=%u\n" \
"bank=%u\n" \
"row=%u\n" \
"column=%u\n", \
ev->hdr.timestamp, \
ev->hdr.memdev, \
ev->hdr.host, \
ev->hdr.serial, \
ev->hdr.log_type, \
ev->hdr.hdr_uuid, \
ev->hdr.hdr_flags, \
ev->hdr.hdr_handle, \
ev->hdr.hdr_related_handle, \
ev->hdr.hdr_timestamp, \
ev->hdr.hdr_length, \
ev->hdr.hdr_maint_op_class, \
ev->dpa, \
ev->dpa_flags, \
ev->descriptor, \
ev->type, \
ev->transaction_type, \
ev->channel, \
ev->rank, \
ev->nibble_mask, \
ev->bank_group, \
ev->bank, \
ev->row, \
ev->column);
strcat(buf, bt_buf);
return 0;
}
static int set_cxl_memory_module_event_backtrace(char *buf, struct ras_cxl_memory_module_event *ev)
{
char bt_buf[MAX_BACKTRACE_SIZE];
if (!buf || !ev)
return -1;
sprintf(bt_buf, "BACKTRACE=" \
"timestamp=%s\n" \
"memdev=%s\n" \
"host=%s\n" \
"serial=0x%lx\n" \
"log_type=%s\n" \
"hdr_uuid=%s\n" \
"hdr_flags=0x%x\n" \
"hdr_handle=0x%x\n" \
"hdr_related_handle=0x%x\n" \
"hdr_timestamp=%s\n" \
"hdr_length=%u\n" \
"hdr_maint_op_class=%u\n" \
"event_type=%u\n" \
"health_status=%u\n" \
"media_status=%u\n" \
"life_used=%u\n" \
"dirty_shutdown_cnt=%u\n" \
"cor_vol_err_cnt=%u\n" \
"cor_per_err_cnt=%u\n" \
"device_temp=%d\n" \
"add_status=%u\n", \
ev->hdr.timestamp, \
ev->hdr.memdev, \
ev->hdr.host, \
ev->hdr.serial, \
ev->hdr.log_type, \
ev->hdr.hdr_uuid, \
ev->hdr.hdr_flags, \
ev->hdr.hdr_handle, \
ev->hdr.hdr_related_handle, \
ev->hdr.hdr_timestamp, \
ev->hdr.hdr_length, \
ev->hdr.hdr_maint_op_class, \
ev->event_type, \
ev->health_status, \
ev->media_status, \
ev->life_used, \
ev->dirty_shutdown_cnt, \
ev->cor_vol_err_cnt, \
ev->cor_per_err_cnt, \
ev->device_temp, \
ev->add_status);
strcat(buf, bt_buf);
return 0;
}
static int commit_report_backtrace(int sockfd, int type, void *ev)
{
char buf[MAX_BACKTRACE_SIZE];
char *pbuf = buf;
int rc = -1;
int buf_len = 0;
if (sockfd < 0 || !ev) {
return -1;
}
memset(buf, 0, MAX_BACKTRACE_SIZE);
switch (type) {
case MC_EVENT:
rc = set_mc_event_backtrace(buf, (struct ras_mc_event *)ev);
break;
case AER_EVENT:
rc = set_aer_event_backtrace(buf, (struct ras_aer_event *)ev);
break;
case MCE_EVENT:
rc = set_mce_event_backtrace(buf, (struct mce_event *)ev);
break;
case NON_STANDARD_EVENT:
rc = set_non_standard_event_backtrace(buf, (struct ras_non_standard_event *)ev);
break;
case ARM_EVENT:
rc = set_arm_event_backtrace(buf, (struct ras_arm_event *)ev);
break;
case DEVLINK_EVENT:
rc = set_devlink_event_backtrace(buf, (struct devlink_event *)ev);
break;
case DISKERROR_EVENT:
rc = set_diskerror_event_backtrace(buf, (struct diskerror_event *)ev);
break;
case MF_EVENT:
rc = set_mf_event_backtrace(buf, (struct ras_mf_event *)ev);
break;
case CXL_POISON_EVENT:
rc = set_cxl_poison_event_backtrace(buf, (struct ras_cxl_poison_event *)ev);
break;
case CXL_AER_UE_EVENT:
rc = set_cxl_aer_ue_event_backtrace(buf, (struct ras_cxl_aer_ue_event *)ev);
break;
case CXL_AER_CE_EVENT:
rc = set_cxl_aer_ce_event_backtrace(buf, (struct ras_cxl_aer_ce_event *)ev);
break;
case CXL_OVERFLOW_EVENT:
rc = set_cxl_overflow_event_backtrace(buf, (struct ras_cxl_overflow_event *)ev);
break;
case CXL_GENERIC_EVENT:
rc = set_cxl_generic_event_backtrace(buf, (struct ras_cxl_generic_event *)ev);
break;
case CXL_GENERAL_MEDIA_EVENT:
rc = set_cxl_general_media_event_backtrace(buf, (struct ras_cxl_general_media_event *)ev);
break;
case CXL_DRAM_EVENT:
rc = set_cxl_dram_event_backtrace(buf, (struct ras_cxl_dram_event *)ev);
break;
case CXL_MEMORY_MODULE_EVENT:
rc = set_cxl_memory_module_event_backtrace(buf, (struct ras_cxl_memory_module_event *)ev);
break;
default:
return -1;
}
if (rc < 0) {
return -1;
}
buf_len = strlen(buf);
for (; buf_len > INPUT_BUFFER_SIZE - 1; buf_len -= (INPUT_BUFFER_SIZE - 1)) {
rc = write(sockfd, pbuf, INPUT_BUFFER_SIZE - 1);
if (rc < INPUT_BUFFER_SIZE - 1) {
return -1;
}
pbuf = pbuf + INPUT_BUFFER_SIZE - 1;
}
rc = write(sockfd, pbuf, buf_len + 1);
if (rc < buf_len) {
return -1;
}
return 0;
}
int ras_report_mc_event(struct ras_events *ras, struct ras_mc_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = -1;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return -1;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto mc_fail;
}
rc = commit_report_backtrace(sockfd, MC_EVENT, ev);
if (rc < 0) {
goto mc_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-mc");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto mc_fail;
}
sprintf(buf, "REASON=%s", "EDAC driver report problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto mc_fail;
}
done = 1;
mc_fail:
if (sockfd >= 0) {
close(sockfd);
}
if (done) {
return 0;
} else {
return -1;
}
}
int ras_report_aer_event(struct ras_events *ras, struct ras_aer_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return -1;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto aer_fail;
}
rc = commit_report_backtrace(sockfd, AER_EVENT, ev);
if (rc < 0) {
goto aer_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-aer");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto aer_fail;
}
sprintf(buf, "REASON=%s", "PCIe AER driver report problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto aer_fail;
}
done = 1;
aer_fail:
if (sockfd >= 0) {
close(sockfd);
}
if (done) {
return 0;
} else {
return -1;
}
}
int ras_report_non_standard_event(struct ras_events *ras, struct ras_non_standard_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return rc;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto non_standard_fail;
}
rc = commit_report_backtrace(sockfd, NON_STANDARD_EVENT, ev);
if (rc < 0) {
goto non_standard_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-non-standard");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto non_standard_fail;
}
sprintf(buf, "REASON=%s", "Unknown CPER section problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto non_standard_fail;
}
rc = 0;
non_standard_fail:
if (sockfd >= 0) {
close(sockfd);
}
return rc;
}
int ras_report_arm_event(struct ras_events *ras, struct ras_arm_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return rc;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto arm_fail;
}
rc = commit_report_backtrace(sockfd, ARM_EVENT, ev);
if (rc < 0) {
goto arm_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-arm");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto arm_fail;
}
sprintf(buf, "REASON=%s", "ARM CPU report problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto arm_fail;
}
rc = 0;
arm_fail:
if (sockfd >= 0) {
close(sockfd);
}
return rc;
}
int ras_report_mce_event(struct ras_events *ras, struct mce_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return -1;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto mce_fail;
}
rc = commit_report_backtrace(sockfd, MCE_EVENT, ev);
if (rc < 0) {
goto mce_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-mce");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto mce_fail;
}
sprintf(buf, "REASON=%s", "Machine Check driver report problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto mce_fail;
}
done = 1;
mce_fail:
if (sockfd >= 0) {
close(sockfd);
}
if (done) {
return 0;
} else {
return -1;
}
}
int ras_report_devlink_event(struct ras_events *ras, struct devlink_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return -1;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto devlink_fail;
}
rc = commit_report_backtrace(sockfd, DEVLINK_EVENT, ev);
if (rc < 0) {
goto devlink_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-devlink");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto devlink_fail;
}
sprintf(buf, "REASON=%s", "devlink health report problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto devlink_fail;
}
done = 1;
devlink_fail:
if (sockfd >= 0) {
close(sockfd);
}
if (done) {
return 0;
} else {
return -1;
}
}
int ras_report_diskerror_event(struct ras_events *ras, struct diskerror_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0) {
return -1;
}
rc = commit_report_basic(sockfd);
if (rc < 0) {
goto diskerror_fail;
}
rc = commit_report_backtrace(sockfd, DISKERROR_EVENT, ev);
if (rc < 0) {
goto diskerror_fail;
}
sprintf(buf, "ANALYZER=%s", "rasdaemon-diskerror");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto diskerror_fail;
}
sprintf(buf, "REASON=%s", "disk I/O error");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1) {
goto diskerror_fail;
}
done = 1;
diskerror_fail:
if (sockfd >= 0) {
close(sockfd);
}
if (done) {
return 0;
} else {
return -1;
}
}
int ras_report_mf_event(struct ras_events *ras, struct ras_mf_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto mf_fail;
rc = commit_report_backtrace(sockfd, MF_EVENT, ev);
if (rc < 0)
goto mf_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-memory_failure");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto mf_fail;
sprintf(buf, "REASON=%s", "memory failure problem");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto mf_fail;
done = 1;
mf_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_poison_event(struct ras_events *ras, struct ras_cxl_poison_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_poison_fail;
rc = commit_report_backtrace(sockfd, CXL_POISON_EVENT, ev);
if (rc < 0)
goto cxl_poison_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl-poison");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_poison_fail;
sprintf(buf, "REASON=%s", "CXL poison");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_poison_fail;
done = 1;
cxl_poison_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_aer_ue_event(struct ras_events *ras, struct ras_cxl_aer_ue_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_aer_ue_fail;
rc = commit_report_backtrace(sockfd, CXL_AER_UE_EVENT, ev);
if (rc < 0)
goto cxl_aer_ue_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl-aer-uncorrectable-error");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_aer_ue_fail;
sprintf(buf, "REASON=%s", "CXL AER uncorrectable error");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_aer_ue_fail;
done = 1;
cxl_aer_ue_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_aer_ce_event(struct ras_events *ras, struct ras_cxl_aer_ce_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_aer_ce_fail;
rc = commit_report_backtrace(sockfd, CXL_AER_CE_EVENT, ev);
if (rc < 0)
goto cxl_aer_ce_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl-aer-correctable-error");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_aer_ce_fail;
sprintf(buf, "REASON=%s", "CXL AER correctable error");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_aer_ce_fail;
done = 1;
cxl_aer_ce_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_overflow_event(struct ras_events *ras, struct ras_cxl_overflow_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_overflow_fail;
rc = commit_report_backtrace(sockfd, CXL_OVERFLOW_EVENT, ev);
if (rc < 0)
goto cxl_overflow_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl-overflow");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_overflow_fail;
sprintf(buf, "REASON=%s", "CXL overflow");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_overflow_fail;
done = 1;
cxl_overflow_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_generic_event(struct ras_events *ras, struct ras_cxl_generic_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_generic_fail;
rc = commit_report_backtrace(sockfd, CXL_GENERIC_EVENT, ev);
if (rc < 0)
goto cxl_generic_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl_generic_event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_generic_fail;
sprintf(buf, "REASON=%s", "CXL Generic Event ");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_generic_fail;
done = 1;
cxl_generic_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_general_media_event(struct ras_events *ras, struct ras_cxl_general_media_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_general_media_fail;
rc = commit_report_backtrace(sockfd, CXL_GENERAL_MEDIA_EVENT, ev);
if (rc < 0)
goto cxl_general_media_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl_general_media_event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_general_media_fail;
sprintf(buf, "REASON=%s", "CXL General Media Event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_general_media_fail;
done = 1;
cxl_general_media_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_dram_event(struct ras_events *ras, struct ras_cxl_dram_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_dram_fail;
rc = commit_report_backtrace(sockfd, CXL_DRAM_EVENT, ev);
if (rc < 0)
goto cxl_dram_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl_dram_event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_dram_fail;
sprintf(buf, "REASON=%s", "CXL DRAM Event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_dram_fail;
done = 1;
cxl_dram_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
int ras_report_cxl_memory_module_event(struct ras_events *ras, struct ras_cxl_memory_module_event *ev)
{
char buf[MAX_MESSAGE_SIZE];
int sockfd = 0;
int done = 0;
int rc = -1;
memset(buf, 0, sizeof(buf));
sockfd = setup_report_socket();
if (sockfd < 0)
return -1;
rc = commit_report_basic(sockfd);
if (rc < 0)
goto cxl_memory_module_fail;
rc = commit_report_backtrace(sockfd, CXL_MEMORY_MODULE_EVENT, ev);
if (rc < 0)
goto cxl_memory_module_fail;
sprintf(buf, "ANALYZER=%s", "rasdaemon-cxl_memory_module_event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_memory_module_fail;
sprintf(buf, "REASON=%s", "CXL Memory Module Event");
rc = write(sockfd, buf, strlen(buf) + 1);
if (rc < strlen(buf) + 1)
goto cxl_memory_module_fail;
done = 1;
cxl_memory_module_fail:
if (sockfd >= 0)
close(sockfd);
if (done)
return 0;
else
return -1;
}
|
0 | rasdaemon-master | rasdaemon-master/rasdaemon.c | /*
* Copyright (C) 2013 Mauro Carvalho Chehab <mchehab+redhat@kernel.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <argp.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-events.h"
/*
* Arguments(argp) handling logic and main
*/
#define TOOL_NAME "rasdaemon"
#define TOOL_DESCRIPTION "RAS daemon to log the RAS events."
#define ARGS_DOC "<options>"
#define DISABLE "DISABLE"
char *choices_disable;
const char *argp_program_version = TOOL_NAME " " VERSION;
const char *argp_program_bug_address = "Mauro Carvalho Chehab <mchehab@kernel.org>";
struct arguments {
int record_events;
int enable_ras;
int foreground;
int offline;
};
enum OFFLINE_ARG_KEYS {
SMCA = 0x100,
MODEL,
FAMILY,
BANK_NUM,
IPID_REG,
STATUS_REG,
SYNDROME_REG
};
struct ras_mc_offline_event event;
static error_t parse_opt(int k, char *arg, struct argp_state *state)
{
struct arguments *args = state->input;
switch (k) {
case 'e':
args->enable_ras++;
break;
case 'd':
args->enable_ras--;
break;
#ifdef HAVE_SQLITE3
case 'r':
args->record_events++;
break;
#endif
case 'f':
args->foreground++;
break;
#ifdef HAVE_MCE
case 'p':
if (state->argc < 4)
argp_state_help(state, stdout, ARGP_HELP_LONG | ARGP_HELP_EXIT_ERR);
args->offline++;
break;
#endif
default:
return ARGP_ERR_UNKNOWN;
}
return 0;
}
#ifdef HAVE_MCE
static error_t parse_opt_offline(int key, char *arg,
struct argp_state *state)
{
switch (key) {
case SMCA:
event.smca = true;
break;
case MODEL:
event.model = strtoul(state->argv[state->next], NULL, 0);
break;
case FAMILY:
event.family = strtoul(state->argv[state->next], NULL, 0);
break;
case BANK_NUM:
event.bank = atoi(state->argv[state->next]);
break;
case IPID_REG:
event.ipid = strtoull(state->argv[state->next], NULL, 0);
break;
case STATUS_REG:
event.status = strtoull(state->argv[state->next], NULL, 0);
break;
case SYNDROME_REG:
event.synd = strtoull(state->argv[state->next], NULL, 0);
break;
default:
return ARGP_ERR_UNKNOWN;
}
return 0;
}
#endif
long user_hz;
int main(int argc, char *argv[])
{
struct arguments args;
int idx = -1;
choices_disable = getenv(DISABLE);
#ifdef HAVE_MCE
const struct argp_option offline_options[] = {
{"smca", SMCA, 0, 0, "AMD SMCA Error Decoding"},
{"model", MODEL, 0, 0, "CPU Model"},
{"family", FAMILY, 0, 0, "CPU Family"},
{"bank", BANK_NUM, 0, 0, "Bank Number"},
{"ipid", IPID_REG, 0, 0, "IPID Register (for SMCA systems only)"},
{"status", STATUS_REG, 0, 0, "Status Register"},
{"synd", SYNDROME_REG, 0, 0, "Syndrome Register"},
{0, 0, 0, 0, 0, 0},
};
struct argp offline_argp = {
.options = offline_options,
.parser = parse_opt_offline,
.doc = TOOL_DESCRIPTION,
.args_doc = ARGS_DOC,
};
struct argp_child offline_parser[] = {
{&offline_argp, 0, "Post-Processing Options:", 0},
{0, 0, 0, 0},
};
#endif
const struct argp_option options[] = {
{"enable", 'e', 0, 0, "enable RAS events and exit", 0},
{"disable", 'd', 0, 0, "disable RAS events and exit", 0},
#ifdef HAVE_SQLITE3
{"record", 'r', 0, 0, "record events via sqlite3", 0},
#endif
{"foreground", 'f', 0, 0, "run foreground, not daemonize"},
#ifdef HAVE_MCE
{"post-processing", 'p', 0, 0,
"Post-processing MCE's with raw register values"},
#endif
{ 0, 0, 0, 0, 0, 0 }
};
const struct argp argp = {
.options = options,
.parser = parse_opt,
.doc = TOOL_DESCRIPTION,
.args_doc = ARGS_DOC,
#ifdef HAVE_MCE
.children = offline_parser,
#endif
};
memset(&args, 0, sizeof(args));
user_hz = sysconf(_SC_CLK_TCK);
argp_parse(&argp, argc, argv, 0, &idx, &args);
if (idx < 0) {
argp_help(&argp, stderr, ARGP_HELP_STD_HELP, TOOL_NAME);
return -1;
}
if (args.enable_ras) {
int enable;
enable = (args.enable_ras > 0) ? 1 : 0;
toggle_ras_mc_event(enable);
return 0;
}
#ifdef HAVE_MCE
if (args.offline) {
ras_offline_mce_event(&event);
return 0;
}
#endif
openlog(TOOL_NAME, 0, LOG_DAEMON);
if (!args.foreground)
if (daemon(0, 0))
exit(EXIT_FAILURE);
handle_ras_events(args.record_events);
return 0;
}
|
0 | rasdaemon-master | rasdaemon-master/mce-intel.c | /*
* Copyright (C) 2013 Mauro Carvalho Chehab <mchehab+redhat@kernel.org>
*
* The code below were adapted from Andi Kleen/Intel/SuSe mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <errno.h>
#include <fcntl.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "ras-logger.h"
#include "ras-mce-handler.h"
#include "bitfield.h"
#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
#define MCE_TIMEOUT_BANK (MCE_EXTENDED_BANK + 90)
#define TLB_LL_MASK 0x3 /*bit 0, bit 1*/
#define TLB_LL_SHIFT 0x0
#define TLB_TT_MASK 0xc /*bit 2, bit 3*/
#define TLB_TT_SHIFT 0x2
#define CACHE_LL_MASK 0x3 /*bit 0, bit 1*/
#define CACHE_LL_SHIFT 0x0
#define CACHE_TT_MASK 0xc /*bit 2, bit 3*/
#define CACHE_TT_SHIFT 0x2
#define CACHE_RRRR_MASK 0xF0 /*bit 4, bit 5, bit 6, bit 7 */
#define CACHE_RRRR_SHIFT 0x4
#define BUS_LL_MASK 0x3 /* bit 0, bit 1*/
#define BUS_LL_SHIFT 0x0
#define BUS_II_MASK 0xc /*bit 2, bit 3*/
#define BUS_II_SHIFT 0x2
#define BUS_RRRR_MASK 0xF0 /*bit 4, bit 5, bit 6, bit 7 */
#define BUS_RRRR_SHIFT 0x4
#define BUS_T_MASK 0x100 /*bit 8*/
#define BUS_T_SHIFT 0x8
#define BUS_PP_MASK 0x600 /*bit 9, bit 10*/
#define BUS_PP_SHIFT 0x9
#define MCG_TES_P BIT_ULL(11) /* Yellow bit cache threshold supported */
static char *TT[] = {
"Instruction",
"Data",
"Generic",
"Unknown"
};
static char *LL[] = {
"Level-0",
"Level-1",
"Level-2",
"Level-3"
};
static struct {
uint8_t value;
char *str;
} RRRR[] = {
{0, "Generic"},
{1, "Read"},
{2, "Write" },
{3, "Data-Read"},
{4, "Data-Write"},
{5, "Instruction-Fetch"},
{6, "Prefetch"},
{7, "Eviction"},
{8, "Snoop"}
};
static char *PP[] = {
"Local-CPU-originated-request",
"Responed-to-request",
"Observed-error-as-third-party",
"Generic"
};
static char *T[] = {
"Request-did-not-timeout",
"Request-timed-out"
};
static char *II[] = {
"Memory-access",
"Reserved",
"IO",
"Other-transaction"
};
static char *mca_msg[] = {
[0] = "No Error",
[1] = "Unclassified",
[2] = "Microcode ROM parity error",
[3] = "External error",
[4] = "FRC error",
[5] = "Internal parity error",
[6] = "SMM Handler Code Access Violation",
};
static char *tracking_msg[] = {
[1] = "green",
[2] = "yellow",
[3] = "res3"
};
static const char *arstate[4] = {
[0] = "UCNA",
[1] = "AR",
[2] = "SRAO",
[3] = "SRAR"
};
static char *mmm_mnemonic[] = {
"GEN", "RD", "WR", "AC",
"MS", "RES5", "RES6", "RES7"
};
static char *mmm_desc[] = {
"Generic undefined request",
"Memory read error",
"Memory write error",
"Address/Command error",
"Memory scrubbing error",
"Reserved 5",
"Reserved 6",
"Reserved 7"
};
static void decode_memory_controller(struct mce_event *e, uint32_t status)
{
char channel[30];
if ((status & 0xf) == 0xf)
sprintf(channel, "unspecified");
else
sprintf(channel, "%u", status & 0xf);
mce_snprintf(e->error_msg, "MEMORY CONTROLLER %s_CHANNEL%s_ERR",
mmm_mnemonic[(status >> 4) & 7], channel);
mce_snprintf(e->error_msg, "Transaction: %s",
mmm_desc[(status >> 4) & 7]);
}
static void decode_termal_bank(struct mce_event *e)
{
if (e->status & 1) {
mce_snprintf(e->mcgstatus_msg, "Processor %d heated above trip temperature. Throttling enabled.", e->cpu);
mce_snprintf(e->user_action, "Please check your system cooling. Performance will be impacted");
} else {
mce_snprintf(e->error_msg, "Processor %d below trip temperature. Throttling disabled", e->cpu);
}
}
static void decode_mcg(struct mce_event *e)
{
uint64_t mcgstatus = e->mcgstatus;
mce_snprintf(e->mcgstatus_msg, "mcgstatus=%lld",
(long long)e->mcgstatus);
if (mcgstatus & MCG_STATUS_RIPV)
mce_snprintf(e->mcgstatus_msg, "RIPV");
if (mcgstatus & MCG_STATUS_EIPV)
mce_snprintf(e->mcgstatus_msg, "EIPV");
if (mcgstatus & MCG_STATUS_MCIP)
mce_snprintf(e->mcgstatus_msg, "MCIP");
if (mcgstatus & MCG_STATUS_LMCE)
mce_snprintf(e->mcgstatus_msg, "LMCE");
}
static void bank_name(struct mce_event *e)
{
char *buf = e->bank_name;
switch (e->bank) {
case MCE_THERMAL_BANK:
strcpy(buf, "THERMAL EVENT");
break;
case MCE_TIMEOUT_BANK:
strcpy(buf, "Timeout waiting for exception on other CPUs");
break;
default:
break;
}
}
static char *get_RRRR_str(uint8_t rrrr)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(RRRR); i++) {
if (RRRR[i].value == rrrr) {
return RRRR[i].str;
}
}
return "UNKNOWN";
}
#define decode_attr(arr, val) ({ \
char *__str; \
if ((unsigned int)(val) >= ARRAY_SIZE(arr)) \
__str = "UNKNOWN"; \
else \
__str = (arr)[val]; \
__str; \
})
static void decode_mca(struct mce_event *e, uint64_t track, int *ismemerr)
{
uint32_t mca = e->status & 0xffffL;
if (mca & (1UL << 12)) {
mce_snprintf(e->mcastatus_msg,
"corrected filtering (some unreported errors in same region)");
mca &= ~(1UL << 12);
}
if (mca < ARRAY_SIZE(mca_msg)) {
mce_snprintf(e->mcastatus_msg, "%s", mca_msg[mca]);
return;
}
if ((mca >> 2) == 3) {
mce_snprintf(e->mcastatus_msg,
"%s Generic memory hierarchy error",
decode_attr(LL, mca & 3));
} else if (test_prefix(4, mca)) {
mce_snprintf(e->mcastatus_msg, "%s TLB %s Error",
decode_attr(TT, (mca & TLB_TT_MASK) >> TLB_TT_SHIFT),
decode_attr(LL, (mca & TLB_LL_MASK) >> TLB_LL_SHIFT));
} else if (test_prefix(8, mca)) {
unsigned int typenum = (mca & CACHE_TT_MASK) >> CACHE_TT_SHIFT;
unsigned int levelnum = (mca & CACHE_LL_MASK) >> CACHE_LL_SHIFT;
char *type = decode_attr(TT, typenum);
char *level = decode_attr(LL, levelnum);
mce_snprintf(e->mcastatus_msg,
"%s CACHE %s %s Error", type, level,
get_RRRR_str((mca & CACHE_RRRR_MASK) >> CACHE_RRRR_SHIFT));
#if 0
/* FIXME: We shouldn't mix parsing with actions */
if (track == 2)
run_yellow_trigger(e->cpu, typenum, levelnum, type, level, e->socket);
#endif
} else if (test_prefix(10, mca)) {
if (mca == 0x400)
mce_snprintf(e->mcastatus_msg,
"Internal Timer error");
else
mce_snprintf(e->mcastatus_msg,
"Internal unclassified error: %x",
mca);
} else if (test_prefix(11, mca)) {
mce_snprintf(e->mcastatus_msg, "BUS %s %s %s %s %s Error",
decode_attr(LL, (mca & BUS_LL_MASK) >> BUS_LL_SHIFT),
decode_attr(PP, (mca & BUS_PP_MASK) >> BUS_PP_SHIFT),
get_RRRR_str((mca & BUS_RRRR_MASK) >> BUS_RRRR_SHIFT),
decode_attr(II, (mca & BUS_II_MASK) >> BUS_II_SHIFT),
decode_attr(T, (mca & BUS_T_MASK) >> BUS_T_SHIFT));
} else if (test_prefix(7, mca)) {
decode_memory_controller(e, mca);
*ismemerr = 1;
} else
mce_snprintf(e->mcastatus_msg, "Unknown Error %x", mca);
}
static void decode_tracking(struct mce_event *e, uint64_t track)
{
if (track == 1)
mce_snprintf(e->user_action,
"Large number of corrected cache errors. System operating, but might leadto uncorrected errors soon");
if (track)
mce_snprintf(e->mcistatus_msg, "Threshold based error status: %s",
tracking_msg[track]);
}
static void decode_mci(struct mce_event *e, int *ismemerr)
{
uint64_t track = 0;
if (!(e->status & MCI_STATUS_VAL))
mce_snprintf(e->mcistatus_msg, "MCE_INVALID");
if (e->status & MCI_STATUS_OVER)
mce_snprintf(e->mcistatus_msg, "Error_overflow");
/* FIXME: convert into severity */
if (e->status & MCI_STATUS_UC)
mce_snprintf(e->mcistatus_msg, "Uncorrected_error");
else
mce_snprintf(e->mcistatus_msg, "Corrected_error");
if (e->status & MCI_STATUS_EN)
mce_snprintf(e->mcistatus_msg, "Error_enabled");
if (e->status & MCI_STATUS_PCC)
mce_snprintf(e->mcistatus_msg, "Processor_context_corrupt");
if (e->status & (MCI_STATUS_S | MCI_STATUS_AR))
mce_snprintf(e->mcistatus_msg, "%s",
arstate[(e->status >> 55) & 3]);
if ((e->mcgcap == 0 || (e->mcgcap & MCG_TES_P)) &&
!(e->status & MCI_STATUS_UC)) {
track = (e->status >> 53) & 3;
decode_tracking(e, track);
}
decode_mca(e, track, ismemerr);
}
int parse_intel_event(struct ras_events *ras, struct mce_event *e)
{
struct mce_priv *mce = ras->mce_priv;
int ismemerr;
bank_name(e);
if (e->bank == MCE_THERMAL_BANK) {
decode_termal_bank(e);
return 0;
}
decode_mcg(e);
decode_mci(e, &ismemerr);
/* Check if the error is at the memory controller */
if (((e->status & 0xffff) >> 7) == 1) {
unsigned int corr_err_cnt;
corr_err_cnt = EXTRACT(e->status, 38, 52);
mce_snprintf(e->mc_location, "n_errors=%d", corr_err_cnt);
}
if (test_prefix(11, (e->status & 0xffffL))) {
switch (mce->cputype) {
case CPU_P6OLD:
p6old_decode_model(e);
break;
case CPU_DUNNINGTON:
case CPU_CORE2:
case CPU_NEHALEM:
case CPU_XEON75XX:
core2_decode_model(e);
break;
case CPU_TULSA:
case CPU_P4:
p4_decode_model(e);
break;
default:
break;
}
}
switch (mce->cputype) {
case CPU_NEHALEM:
nehalem_decode_model(e);
break;
case CPU_XEON75XX:
xeon75xx_decode_model(e);
break;
case CPU_DUNNINGTON:
dunnington_decode_model(e);
break;
case CPU_TULSA:
tulsa_decode_model(e);
break;
case CPU_SANDY_BRIDGE:
case CPU_SANDY_BRIDGE_EP:
snb_decode_model(ras, e);
break;
case CPU_IVY_BRIDGE_EPEX:
ivb_decode_model(ras, e);
break;
case CPU_HASWELL_EPEX:
hsw_decode_model(ras, e);
break;
case CPU_KNIGHTS_LANDING:
case CPU_KNIGHTS_MILL:
knl_decode_model(ras, e);
break;
case CPU_BROADWELL_DE:
broadwell_de_decode_model(ras, e);
break;
case CPU_BROADWELL_EPEX:
broadwell_epex_decode_model(ras, e);
break;
case CPU_SKYLAKE_XEON:
skylake_s_decode_model(ras, e);
break;
case CPU_ICELAKE_XEON:
case CPU_ICELAKE_DE:
case CPU_TREMONT_D:
case CPU_SAPPHIRERAPIDS:
case CPU_EMERALDRAPIDS:
i10nm_decode_model(mce->cputype, ras, e);
default:
break;
}
return 0;
}
/*
* Code to enable iMC logs
*/
static int domsr(int cpu, int msr, int bit)
{
char fpath[32];
unsigned long long data;
int fd;
sprintf(fpath, "/dev/cpu/%d/msr", cpu);
fd = open(fpath, O_RDWR);
if (fd == -1) {
switch (errno) {
case ENOENT:
log(ALL, LOG_ERR,
"Warning: cpu %d offline?, imc_log not set\n", cpu);
return -EINVAL;
default:
log(ALL, LOG_ERR,
"Cannot open %s to set imc_log\n", fpath);
return -EINVAL;
}
}
if (pread(fd, &data, sizeof(data), msr) != sizeof(data)) {
log(ALL, LOG_ERR,
"Cannot read MSR_ERROR_CONTROL from %s\n", fpath);
return -EINVAL;
}
data |= bit;
if (pwrite(fd, &data, sizeof(data), msr) != sizeof(data)) {
log(ALL, LOG_ERR,
"Cannot write MSR_ERROR_CONTROL to %s\n", fpath);
return -EINVAL;
}
if (pread(fd, &data, sizeof(data), msr) != sizeof(data)) {
log(ALL, LOG_ERR,
"Cannot re-read MSR_ERROR_CONTROL from %s\n", fpath);
return -EINVAL;
}
if ((data & bit) == 0) {
log(ALL, LOG_ERR,
"Failed to set imc_log on cpu %d\n", cpu);
return -EINVAL;
}
close(fd);
return 0;
}
int set_intel_imc_log(enum cputype cputype, unsigned int ncpus)
{
int cpu, msr, bit, rc;
switch (cputype) {
case CPU_SANDY_BRIDGE_EP:
case CPU_IVY_BRIDGE_EPEX:
case CPU_HASWELL_EPEX:
case CPU_KNIGHTS_LANDING:
case CPU_KNIGHTS_MILL:
msr = 0x17f; /* MSR_ERROR_CONTROL */
bit = 0x2; /* MemError Log Enable */
break;
default:
return 0;
}
for (cpu = 0; cpu < ncpus; cpu++) {
rc = domsr(cpu, msr, bit);
if (rc)
return rc;
}
return 0;
}
|
0 | rasdaemon-master | rasdaemon-master/mce-intel-nehalem.c | /*
* The code below came from Andi Kleen/Intel/SuSe mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <stdio.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
/* See IA32 SDM Vol3B Appendix E.3.2 ff */
/* MC1_STATUS error */
static struct field qpi_status[] = {
SBITFIELD(16, "QPI header had bad parity"),
SBITFIELD(17, "QPI Data packet had bad parity"),
SBITFIELD(18, "Number of QPI retries exceeded"),
SBITFIELD(19, "Received QPI data packet that was poisoned by sender"),
SBITFIELD(20, "QPI reserved 20"),
SBITFIELD(21, "QPI reserved 21"),
SBITFIELD(22, "QPI received unsupported message encoding"),
SBITFIELD(23, "QPI credit type is not supported"),
SBITFIELD(24, "Sender sent too many QPI flits to the receiver"),
SBITFIELD(25, "QPI Sender sent a failed response to receiver"),
SBITFIELD(26, "Clock jitter detected in internal QPI clocking"),
{}
};
static struct field qpi_misc[] = {
SBITFIELD(14, "QPI misc reserved 14"),
SBITFIELD(15, "QPI misc reserved 15"),
SBITFIELD(24, "QPI Interleave/Head Indication Bit (IIB)"),
{}
};
static struct numfield qpi_numbers[] = {
HEXNUMBER(0, 7, "QPI class and opcode of packet with error"),
HEXNUMBER(8, 13, "QPI Request Transaction ID"),
NUMBERFORCE(16, 18, "QPI Requestor/Home Node ID (RHNID)"),
HEXNUMBER(19, 23, "QPI miscreserved 19-23"),
{},
};
static struct field nhm_memory_status[] = {
SBITFIELD(16, "Memory read ECC error"),
SBITFIELD(17, "Memory ECC error occurred during scrub"),
SBITFIELD(18, "Memory write parity error"),
SBITFIELD(19, "Memory error in half of redundant memory"),
SBITFIELD(20, "Memory reserved 20"),
SBITFIELD(21, "Memory access out of range"),
SBITFIELD(22, "Memory internal RTID invalid"),
SBITFIELD(23, "Memory address parity error"),
SBITFIELD(24, "Memory byte enable parity error"),
{}
};
static struct numfield nhm_memory_status_numbers[] = {
HEXNUMBER(25, 37, "Memory MISC reserved 25..37"),
NUMBERFORCE(38, 52, "Memory corrected error count (CORE_ERR_CNT)"),
HEXNUMBER(53, 56, "Memory MISC reserved 53..56"),
{}
};
static struct numfield nhm_memory_misc_numbers[] = {
HEXNUMBERFORCE(0, 7, "Memory transaction Tracker ID (RTId)"),
NUMBERFORCE(16, 17, "Memory DIMM ID of error"),
NUMBERFORCE(18, 19, "Memory channel ID of error"),
HEXNUMBERFORCE(32, 63, "Memory ECC syndrome"),
{}
};
static char *internal_errors[] = {
[0x0] = "No Error",
[0x3] = "Reset firmware did not complete",
[0x8] = "Received an invalid CMPD",
[0xa] = "Invalid Power Management Request",
[0xd] = "Invalid S-state transition",
[0x11] = "VID controller does not match POC controller selected",
[0x1a] = "MSID from POC does not match CPU MSID",
};
static struct field internal_error_status[] = {
FIELD(24, internal_errors),
{}
};
static struct numfield internal_error_numbers[] = {
HEXNUMBER(16, 23, "Internal machine check status reserved 16..23"),
HEXNUMBER(32, 56, "Internal machine check status reserved 32..56"),
{},
};
/* Generic architectural memory controller encoding */
void nehalem_decode_model(struct mce_event *e)
{
uint64_t status = e->status;
uint32_t mca = status & 0xffff;
uint64_t misc = e->misc;
unsigned int channel, dimm;
if ((mca >> 11) == 1) { /* bus and interconnect QPI */
decode_bitfield(e, status, qpi_status);
if (status & MCI_STATUS_MISCV) {
decode_numfield(e, misc, qpi_numbers);
decode_bitfield(e, misc, qpi_misc);
}
} else if (mca == 0x0001) { /* internal unspecified */
decode_bitfield(e, status, internal_error_status);
decode_numfield(e, status, internal_error_numbers);
} else if ((mca >> 7) == 1) { /* memory controller */
decode_bitfield(e, status, nhm_memory_status);
decode_numfield(e, status, nhm_memory_status_numbers);
if (status & MCI_STATUS_MISCV)
decode_numfield(e, misc, nhm_memory_misc_numbers);
}
if ((((status & 0xffff) >> 7) == 1) && (status & MCI_STATUS_MISCV)) {
channel = EXTRACT(e->misc, 18, 19);
dimm = EXTRACT(e->misc, 16, 17);
mce_snprintf(e->mc_location, "channel=%d, dimm=%d",
channel, dimm);
}
}
/* Only core errors supported. Same as Nehalem */
void xeon75xx_decode_model(struct mce_event *e)
{
uint64_t status = e->status;
uint32_t mca = status & 0xffff;
if (mca == 0x0001) { /* internal unspecified */
decode_bitfield(e, status, internal_error_status);
decode_numfield(e, status, internal_error_numbers);
}
}
|
0 | rasdaemon-master | rasdaemon-master/ras-cpu-isolation.c | /*
* Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <fcntl.h>
#include <errno.h>
#include <unistd.h>
#include <limits.h>
#include <ctype.h>
#include "ras-logger.h"
#include "ras-cpu-isolation.h"
#define SECOND_OF_MON (30 * 24 * 60 * 60)
#define SECOND_OF_DAY (24 * 60 * 60)
#define SECOND_OF_HOU (60 * 60)
#define SECOND_OF_MIN (60)
#define LIMIT_OF_CPU_THRESHOLD 10000
#define INIT_OF_CPU_THRESHOLD 18
#define DEC_CHECK 10
#define LAST_BIT_OF_UL 5
static struct cpu_info *cpu_infos;
static unsigned int ncores;
static unsigned int enabled = 1;
static const char *cpu_path_format = "/sys/devices/system/cpu/cpu%d/online";
static const struct param normal_units[] = {
{"", 1},
{}
};
static const struct param cycle_units[] = {
{"d", SECOND_OF_DAY},
{"h", SECOND_OF_HOU},
{"m", SECOND_OF_MIN},
{"s", 1},
{}
};
static struct isolation_param threshold = {
.name = "CPU_CE_THRESHOLD",
.units = normal_units,
.value = INIT_OF_CPU_THRESHOLD,
.limit = LIMIT_OF_CPU_THRESHOLD
};
static struct isolation_param cpu_limit = {
.name = "CPU_ISOLATION_LIMIT",
.units = normal_units
};
static struct isolation_param cycle = {
.name = "CPU_ISOLATION_CYCLE",
.units = cycle_units,
.value = SECOND_OF_DAY,
.limit = SECOND_OF_MON
};
static const char * const cpu_state[] = {
[CPU_OFFLINE] = "offline",
[CPU_ONLINE] = "online",
[CPU_OFFLINE_FAILED] = "offline-failed",
[CPU_UNKNOWN] = "unknown"
};
static int open_sys_file(unsigned int cpu, int __oflag, const char *format)
{
int fd;
char path[PATH_MAX] = "";
char real_path[PATH_MAX] = "";
snprintf(path, sizeof(path), format, cpu);
if (strlen(path) > PATH_MAX || realpath(path, real_path) == NULL) {
log(TERM, LOG_ERR, "[%s]:open file: %s failed\n", __func__, path);
return -1;
}
fd = open(real_path, __oflag);
if (fd == -1) {
log(TERM, LOG_ERR, "[%s]:open file: %s failed\n", __func__, real_path);
return -1;
}
return fd;
}
static int get_cpu_status(unsigned int cpu)
{
int fd, num;
char buf[2] = "";
fd = open_sys_file(cpu, O_RDONLY, cpu_path_format);
if (fd == -1)
return CPU_UNKNOWN;
if (read(fd, buf, 1) <= 0 || sscanf(buf, "%d", &num) != 1)
num = CPU_UNKNOWN;
close(fd);
return (num < 0 || num > CPU_UNKNOWN) ? CPU_UNKNOWN : num;
}
static int init_cpu_info(unsigned int cpus)
{
ncores = cpus;
cpu_infos = (struct cpu_info *)malloc(sizeof(*cpu_infos) * cpus);
if (!cpu_infos) {
log(TERM, LOG_ERR,
"Failed to allocate memory for cpu infos in %s.\n", __func__);
return -1;
}
for (unsigned int i = 0; i < cpus; ++i) {
cpu_infos[i].ce_nums = 0;
cpu_infos[i].uce_nums = 0;
cpu_infos[i].state = get_cpu_status(i);
cpu_infos[i].ce_queue = init_queue();
if (!cpu_infos[i].ce_queue) {
log(TERM, LOG_ERR,
"Failed to allocate memory for cpu ce queue in %s.\n", __func__);
return -1;
}
}
/* set limit of offlined cpu limit according to number of cpu */
cpu_limit.limit = cpus - 1;
cpu_limit.value = 0;
return 0;
}
static void check_config(struct isolation_param *config)
{
if (config->value > config->limit) {
log(TERM, LOG_WARNING, "Value: %lu exceed limit: %lu, set to limit\n",
config->value, config->limit);
config->value = config->limit;
}
}
static int parse_ul_config(struct isolation_param *config, char *env, unsigned long *value)
{
char *unit = NULL;
int env_size, has_unit = 0;
if (!env || strlen(env) == 0)
return -1;
env_size = strlen(env);
unit = env + env_size - 1;
if (isalpha(*unit)) {
has_unit = 1;
env_size--;
if (env_size <= 0)
return -1;
}
for (int i = 0; i < env_size; ++i) {
if (isdigit(env[i])) {
if (*value > ULONG_MAX / DEC_CHECK ||
(*value == ULONG_MAX / DEC_CHECK && env[i] - '0' > LAST_BIT_OF_UL)) {
log(TERM, LOG_ERR, "%s is out of range: %lu\n", env, ULONG_MAX);
return -1;
}
*value = DEC_CHECK * (*value) + (env[i] - '0');
} else
return -1;
}
if (!has_unit)
return 0;
for (const struct param *units = config->units; units->name; units++) {
/* value character and unit character are both valid */
if (!strcasecmp(unit, units->name)) {
if (*value > (ULONG_MAX / units->value)) {
log(TERM, LOG_ERR,
"%s is out of range: %lu\n", env, ULONG_MAX);
return -1;
}
*value = (*value) * units->value;
return 0;
}
}
log(TERM, LOG_ERR, "Invalid unit %s\n", unit);
return -1;
}
static void init_config(struct isolation_param *config)
{
char *env = getenv(config->name);
unsigned long value = 0;
if (parse_ul_config(config, env, &value) < 0) {
log(TERM, LOG_ERR, "Invalid %s: %s! Use default value %lu.\n",
config->name, env, config->value);
return;
}
config->value = value;
check_config(config);
}
static int check_config_status(void)
{
char *env = getenv("CPU_ISOLATION_ENABLE");
if (!env || strcasecmp(env, "yes"))
return -1;
return 0;
}
void ras_cpu_isolation_init(unsigned int cpus)
{
if (init_cpu_info(cpus) < 0 || check_config_status() < 0) {
enabled = 0;
log(TERM, LOG_WARNING, "Cpu fault isolation is disabled\n");
return;
}
log(TERM, LOG_INFO, "Cpu fault isolation is enabled\n");
init_config(&threshold);
init_config(&cpu_limit);
init_config(&cycle);
}
void cpu_infos_free(void)
{
if (cpu_infos) {
for (int i = 0; i < ncores; ++i)
free_queue(cpu_infos[i].ce_queue);
free(cpu_infos);
}
}
static int do_cpu_offline(unsigned int cpu)
{
int fd, rc;
char buf[2] = "";
cpu_infos[cpu].state = CPU_OFFLINE_FAILED;
fd = open_sys_file(cpu, O_RDWR, cpu_path_format);
if (fd == -1)
return HANDLE_FAILED;
strcpy(buf, "0");
rc = write(fd, buf, strlen(buf));
if (rc < 0) {
log(TERM, LOG_ERR, "cpu%u offline failed, errno:%d\n", cpu, errno);
close(fd);
return HANDLE_FAILED;
}
close(fd);
/* check wthether the cpu is isolated successfully */
cpu_infos[cpu].state = get_cpu_status(cpu);
if (cpu_infos[cpu].state == CPU_OFFLINE)
return HANDLE_SUCCEED;
return HANDLE_FAILED;
}
static int do_ce_handler(unsigned int cpu)
{
struct link_queue *queue = cpu_infos[cpu].ce_queue;
unsigned int tmp;
/*
* Since we just count all error numbers in setted cycle, we store the time
* and error numbers from current event to the queue, then everytime we
* calculate the period from beginning time to ending time, if the period
* exceeds setted cycle, we pop the beginning time and error until the period
* from new beginning time to ending time is less than cycle.
*/
while (queue->head && queue->tail && queue->tail->time - queue->head->time > cycle.value) {
tmp = queue->head->value;
if (pop(queue) == 0)
cpu_infos[cpu].ce_nums -= tmp;
}
log(TERM, LOG_INFO,
"Current number of Corrected Errors in cpu%d in the cycle is %lu\n",
cpu, cpu_infos[cpu].ce_nums);
if (cpu_infos[cpu].ce_nums >= threshold.value) {
log(TERM, LOG_INFO,
"Corrected Errors exceeded threshold %lu, try to offline cpu%u\n",
threshold.value, cpu);
return do_cpu_offline(cpu);
}
return HANDLE_NOTHING;
}
static int do_uce_handler(unsigned int cpu)
{
if (cpu_infos[cpu].uce_nums > 0) {
log(TERM, LOG_INFO, "Uncorrected Errors occurred, try to offline cpu%u\n", cpu);
return do_cpu_offline(cpu);
}
return HANDLE_NOTHING;
}
static int error_handler(unsigned int cpu, struct error_info *err_info)
{
int ret = HANDLE_NOTHING;
switch (err_info->err_type) {
case CE:
ret = do_ce_handler(cpu);
break;
case UCE:
ret = do_uce_handler(cpu);
break;
default:
break;
}
return ret;
}
static void record_error_info(unsigned int cpu, struct error_info *err_info)
{
switch (err_info->err_type) {
case CE:
{
struct queue_node *node = node_create(err_info->time, err_info->nums);
if (!node) {
log(TERM, LOG_ERR, "Fail to allocate memory for queue node\n");
return;
}
push(cpu_infos[cpu].ce_queue, node);
cpu_infos[cpu].ce_nums += err_info->nums;
break;
}
case UCE:
cpu_infos[cpu].uce_nums++;
break;
default:
break;
}
}
void ras_record_cpu_error(struct error_info *err_info, int cpu)
{
int ret;
if (enabled == 0)
return;
if (cpu >= ncores || cpu < 0) {
log(TERM, LOG_ERR,
"The current cpu %d has exceed the total number of cpu:%u\n", cpu, ncores);
return;
}
log(TERM, LOG_INFO, "Handling error on cpu%d\n", cpu);
cpu_infos[cpu].state = get_cpu_status(cpu);
if (cpu_infos[cpu].state != CPU_ONLINE) {
log(TERM, LOG_INFO, "Cpu%d is not online or unknown, ignore\n", cpu);
return;
}
record_error_info(cpu, err_info);
/*
* Since user may change cpu state, we get current offlined
* cpu numbers every recording time.
*/
if (ncores - sysconf(_SC_NPROCESSORS_ONLN) >= cpu_limit.value) {
log(TERM, LOG_WARNING,
"Offlined cpus have exceeded limit: %lu, choose to do nothing\n",
cpu_limit.value);
return;
}
ret = error_handler(cpu, err_info);
if (ret == HANDLE_NOTHING)
log(TERM, LOG_WARNING, "Doing nothing in the cpu%d\n", cpu);
else if (ret == HANDLE_SUCCEED) {
log(TERM, LOG_INFO, "Offline cpu%d succeed, the state is %s\n",
cpu, cpu_state[cpu_infos[cpu].state]);
clear_queue(cpu_infos[cpu].ce_queue);
cpu_infos[cpu].ce_nums = 0;
cpu_infos[cpu].uce_nums = 0;
} else
log(TERM, LOG_WARNING, "Offline cpu%d fail, the state is %s\n",
cpu, cpu_state[cpu_infos[cpu].state]);
}
|
0 | rasdaemon-master | rasdaemon-master/mce-intel-dunnington.c | /*
* The code below came from Andi Kleen/Intel/SuSe mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <stdio.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
/* Follows Intel IA32 SDM 3b Appendix E.2.1 ++ */
static struct field dunnington_bus_status[] = {
SBITFIELD(16, "Parity error detected during FSB request phase"),
FIELD_NULL(17),
SBITFIELD(20, "Hard Failure response received for a local transaction"),
SBITFIELD(21, "Parity error on FSB response field detected"),
SBITFIELD(22, "Parity data error on inbound data detected"),
FIELD_NULL(23),
FIELD_NULL(25),
FIELD_NULL(28),
FIELD_NULL(31),
{}
};
static char *dnt_front_error[0xf] = {
[0x1] = "Inclusion error from core 0",
[0x2] = "Inclusion error from core 1",
[0x3] = "Write Exclusive error from core 0",
[0x4] = "Write Exclusive error from core 1",
[0x5] = "Inclusion error from FSB",
[0x6] = "SNP stall error from FSB",
[0x7] = "Write stall error from FSB",
[0x8] = "FSB Arbiter Timeout error",
[0xA] = "Inclusion error from core 2",
[0xB] = "Write exclusive error from core 2",
};
static char *dnt_int_error[0xf] = {
[0x2] = "Internal timeout error",
[0x3] = "Internal timeout error",
[0x4] = "Intel Cache Safe Technology Queue full error\n"
"or disabled ways in a set overflow",
[0x5] = "Quiet cycle timeout error (correctable)",
};
struct field dnt_int_status[] = {
FIELD(8, dnt_int_error),
{}
};
struct field dnt_front_status[] = {
FIELD(0, dnt_front_error),
{}
};
struct field dnt_cecc[] = {
SBITFIELD(1, "Correctable ECC event on outgoing core 0 data"),
SBITFIELD(2, "Correctable ECC event on outgoing core 1 data"),
SBITFIELD(3, "Correctable ECC event on outgoing core 2 data"),
{}
};
struct field dnt_uecc[] = {
SBITFIELD(1, "Uncorrectable ECC event on outgoing core 0 data"),
SBITFIELD(2, "Uncorrectable ECC event on outgoing core 1 data"),
SBITFIELD(3, "Uncorrectable ECC event on outgoing core 2 data"),
{}
};
static void dunnington_decode_bus(struct mce_event *e, uint64_t status)
{
decode_bitfield(e, status, dunnington_bus_status);
}
static void dunnington_decode_internal(struct mce_event *e, uint64_t status)
{
uint32_t mca = (status >> 16) & 0xffff;
if ((mca & 0xfff0) == 0)
decode_bitfield(e, mca, dnt_front_status);
else if ((mca & 0xf0ff) == 0)
decode_bitfield(e, mca, dnt_int_status);
else if ((mca & 0xfff0) == 0xc000)
decode_bitfield(e, mca, dnt_cecc);
else if ((mca & 0xfff0) == 0xe000)
decode_bitfield(e, mca, dnt_uecc);
}
void dunnington_decode_model(struct mce_event *e)
{
uint64_t status = e->status;
if ((status & 0xffff) == 0xe0f)
dunnington_decode_bus(e, status);
else if ((status & 0xffff) == (1 << 10))
dunnington_decode_internal(e, status);
}
|
0 | rasdaemon-master | rasdaemon-master/mce-amd.c | /*
* Copyright (c) 2018, The AMD, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <string.h>
#include "ras-mce-handler.h"
/* Error Code Types */
#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
/* Error code: transaction type (TT) */
static char *transaction[] = {
"instruction", "data", "generic", "reserved"
};
/* Error codes: cache level (LL) */
static char *cachelevel[] = {
"reserved", "L1", "L2", "L3/generic"
};
/* Error codes: memory transaction type (RRRR) */
static char *memtrans[] = {
"generic", "generic read", "generic write", "data read",
"data write", "instruction fetch", "prefetch", "evict", "snoop",
"?", "?", "?", "?", "?", "?", "?"
};
/* Participation Processor */
static char *partproc[] = {
"local node origin", "local node response",
"local node observed", "generic participation"
};
/* Timeout */
static char *timeout[] = {
"request didn't time out",
"request timed out"
};
/* internal unclassified error code */
static char *internal[] = { "reserved",
"reserved",
"hardware assert",
"reserved" };
#define TT(x) (((x) >> 2) & 0x3) /*bit 2, bit 3*/
#define TT_MSG(x) transaction[TT(x)]
#define LL(x) ((x) & 0x3) /*bit 0, bit 1*/
#define LL_MSG(x) cachelevel[LL(x)]
#define R4(x) (((x) >> 4) & 0xF) /*bit 4, bit 5, bit 6, bit 7 */
#define R4_MSG(x) ((R4(x) < 9) ? memtrans[R4(x)] : "Wrong R4!")
#define TO(x) (((x) >> 8) & 0x1) /*bit 8*/
#define TO_MSG(x) timeout[TO(x)]
#define PP(x) (((x) >> 9) & 0x3) /*bit 9, bit 10*/
#define PP_MSG(x) partproc[PP(x)]
#define UU(x) (((x) >> 8) & 0x3) /*bit 8, bit 9*/
#define UU_MSG(x) internal[UU(x)]
void decode_amd_errcode(struct mce_event *e)
{
uint16_t ec = e->status & 0xffff;
uint16_t ecc = (e->status >> 45) & 0x3;
if (e->status & MCI_STATUS_UC) {
if (e->status & MCI_STATUS_PCC)
strcpy(e->error_msg, "System Fatal error.");
if (e->mcgstatus & MCG_STATUS_RIPV)
strcpy(e->error_msg,
"Uncorrected, software restartable error.");
strcpy(e->error_msg,
"Uncorrected, software containable error.");
} else if (e->status & MCI_STATUS_DEFERRED)
strcpy(e->error_msg, "Deferred error, no action required.");
else
strcpy(e->error_msg, "Corrected error, no action required.");
if (!(e->status & MCI_STATUS_VAL))
mce_snprintf(e->mcistatus_msg, "MCE_INVALID");
if (e->status & MCI_STATUS_OVER)
mce_snprintf(e->mcistatus_msg, "Error_overflow");
if (e->status & MCI_STATUS_PCC)
mce_snprintf(e->mcistatus_msg, "Processor_context_corrupt");
if (ecc)
mce_snprintf(e->mcistatus_msg,
"%sECC", ((ecc == 2) ? "C" : "U"));
if (INT_ERROR(ec)) {
mce_snprintf(e->mcastatus_msg, "Internal '%s'", UU_MSG(ec));
return;
}
if (TLB_ERROR(ec))
mce_snprintf(e->mcastatus_msg,
"TLB Error 'tx: %s, level: %s'",
TT_MSG(ec), LL_MSG(ec));
else if (MEM_ERROR(ec))
mce_snprintf(e->mcastatus_msg,
"Memory Error 'mem-tx: %s, tx: %s, level: %s'",
R4_MSG(ec), TT_MSG(ec), LL_MSG(ec));
else if (BUS_ERROR(ec))
mce_snprintf(e->mcastatus_msg,
"Bus Error '%s, %s, mem-tx: %s, level: %s'",
PP_MSG(ec), TO_MSG(ec),
R4_MSG(ec), LL_MSG(ec));
return;
}
|
0 | rasdaemon-master | rasdaemon-master/mce-intel-ivb.c | /*
* The code below came from Tony Luck mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <stdio.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
/* See IA32 SDM Vol3B Table 16-17 */
static char *pcu_1[] = {
[0] = "No error",
[1] = "Non_IMem_Sel",
[2] = "I_Parity_Error",
[3] = "Bad_OpCode",
[4] = "I_Stack_Underflow",
[5] = "I_Stack_Overflow",
[6] = "D_Stack_Underflow",
[7] = "D_Stack_Overflow",
[8] = "Non-DMem_Sel",
[9] = "D_Parity_Error"
};
static char *pcu_2[] = {
[0x00] = "No Error",
[0x0D] = "MC_IMC_FORCE_SR_S3_TIMEOUT",
[0x0E] = "MC_MC_CPD_UNCPD_ST_TIMEOUT",
[0x0F] = "MC_PKGS_SAFE_WP_TIMEOUT",
[0x43] = "MC_PECI_MAILBOX_QUIESCE_TIMEOUT",
[0x44] = "MC_CRITICAL_VR_FAILED",
[0x45] = "MC_ICC_MAX-NOTSUPPORTED",
[0x5C] = "MC_MORE_THAN_ONE_LT_AGENT",
[0x60] = "MC_INVALID_PKGS_REQ_PCH",
[0x61] = "MC_INVALID_PKGS_REQ_QPI",
[0x62] = "MC_INVALID_PKGS_RES_QPI",
[0x63] = "MC_INVALID_PKGC_RES_PCH",
[0x64] = "MC_INVALID_PKG_STATE_CONFIG",
[0x70] = "MC_WATCHDG_TIMEOUT_PKGC_SLAVE",
[0x71] = "MC_WATCHDG_TIMEOUT_PKGC_MASTER",
[0x72] = "MC_WATCHDG_TIMEOUT_PKGS_MASTER",
[0x7A] = "MC_HA_FAILSTS_CHANGE_DETECTED",
[0x7B] = "MC_PCIE_R2PCIE-RW_BLOCK_ACK_TIMEOUT",
[0x81] = "MC_RECOVERABLE_DIE_THERMAL_TOO_HOT",
};
static struct field pcu_mc4[] = {
FIELD(16, pcu_1),
FIELD(24, pcu_2),
{}
};
/* See IA32 SDM Vol3B Table 16-18 */
static char *memctrl_1[] = {
[0x001] = "Address parity error",
[0x002] = "HA Wrt buffer Data parity error",
[0x004] = "HA Wrt byte enable parity error",
[0x008] = "Corrected patrol scrub error",
[0x010] = "Uncorrected patrol scrub error",
[0x020] = "Corrected spare error",
[0x040] = "Uncorrected spare error",
[0x080] = "Corrected memory read error",
[0x100] = "iMC, WDB, parity errors",
};
static struct field memctrl_mc9[] = {
FIELD(16, memctrl_1),
{}
};
void ivb_decode_model(struct ras_events *ras, struct mce_event *e)
{
struct mce_priv *mce = ras->mce_priv;
uint64_t status = e->status;
uint32_t mca = status & 0xffff;
unsigned int rank0 = -1, rank1 = -1, chan;
switch (e->bank) {
case 4:
// Wprintf("PCU: ");
decode_bitfield(e, e->status, pcu_mc4);
// Wprintf("\n");
break;
case 5:
if (mce->cputype == CPU_IVY_BRIDGE_EPEX) {
/* MCACOD already decoded */
mce_snprintf(e->bank_name, "QPI");
}
break;
case 9: case 10: case 11: case 12:
case 13: case 14: case 15: case 16:
// Wprintf("MemCtrl: ");
decode_bitfield(e, e->status, memctrl_mc9);
break;
}
/*
* Memory error specific code. Returns if the error is not a MC one
*/
/* Check if the error is at the memory controller */
if ((mca >> 7) != 1)
return;
/* Ignore unless this is an corrected extended error from an iMC bank */
if (e->bank < 9 || e->bank > 16 || (status & MCI_STATUS_UC) ||
!test_prefix(7, status & 0xefff))
return;
/*
* Parse the reported channel and ranks
*/
chan = EXTRACT(status, 0, 3);
if (chan == 0xf)
return;
mce_snprintf(e->mc_location, "memory_channel=%d", chan);
if (EXTRACT(e->misc, 62, 62))
rank0 = EXTRACT(e->misc, 46, 50);
if (EXTRACT(e->misc, 63, 63))
rank1 = EXTRACT(e->misc, 51, 55);
/*
* FIXME: The conversion from rank to dimm requires to parse the
* DMI tables and call failrank2dimm().
*/
if (rank0 >= 0 && rank1 >= 0)
mce_snprintf(e->mc_location, "ranks=%d and %d",
rank0, rank1);
else if (rank0 >= 0)
mce_snprintf(e->mc_location, "rank=%d", rank0);
else
mce_snprintf(e->mc_location, "rank=%d", rank1);
}
/*
* Ivy Bridge EP and EX processors (family 6, model 62) support additional
* logging for corrected errors in the integrated memory controller (IMC)
* banks. The mode is off by default, but can be enabled by setting the
* "MemError Log Enable" * bit in MSR_ERROR_CONTROL (MSR 0x17f).
* The SDM leaves it as an exercise for the reader to convert the
* faling rank to a DIMM slot.
*/
#if 0
static int failrank2dimm(unsigned int failrank, int socket, int channel)
{
switch (failrank) {
case 0: case 1: case 2: case 3:
return 0;
case 4: case 5:
return 1;
case 6: case 7:
if (get_memdimm(socket, channel, 2, 0))
return 2;
else
return 1;
}
return -1;
}
#endif
|
0 | rasdaemon-master | rasdaemon-master/ras-non-standard-handler.c | /*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include <unistd.h>
#include <traceevent/kbuffer.h>
#include "ras-non-standard-handler.h"
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-report.h"
static struct ras_ns_ev_decoder *ras_ns_ev_dec_list;
void print_le_hex(struct trace_seq *s, const uint8_t *buf, int index)
{
trace_seq_printf(s, "%02x%02x%02x%02x", buf[index + 3], buf[index + 2], buf[index + 1], buf[index]);
}
static char *uuid_le(const char *uu)
{
static char uuid[sizeof("xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx")];
char *p = uuid;
int i;
static const unsigned char le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15};
for (i = 0; i < 16; i++) {
p += sprintf(p, "%.2x", (unsigned char)uu[le[i]]);
switch (i) {
case 3:
case 5:
case 7:
case 9:
*p++ = '-';
break;
}
}
*p = 0;
return uuid;
}
int register_ns_ev_decoder(struct ras_ns_ev_decoder *ns_ev_decoder)
{
struct ras_ns_ev_decoder *list;
if (!ns_ev_decoder)
return -1;
ns_ev_decoder->next = NULL;
#ifdef HAVE_SQLITE3
ns_ev_decoder->stmt_dec_record = NULL;
#endif
if (!ras_ns_ev_dec_list) {
ras_ns_ev_dec_list = ns_ev_decoder;
ras_ns_ev_dec_list->ref_count = 0;
} else {
list = ras_ns_ev_dec_list;
while (list->next)
list = list->next;
list->next = ns_ev_decoder;
}
return 0;
}
int ras_ns_add_vendor_tables(struct ras_events *ras)
{
struct ras_ns_ev_decoder *ns_ev_decoder;
int error = 0;
#ifdef HAVE_SQLITE3
if (!ras)
return -1;
ns_ev_decoder = ras_ns_ev_dec_list;
if (ras_ns_ev_dec_list)
ras_ns_ev_dec_list->ref_count++;
while (ns_ev_decoder) {
if (ns_ev_decoder->add_table && !ns_ev_decoder->stmt_dec_record) {
error = ns_ev_decoder->add_table(ras, ns_ev_decoder);
if (error)
break;
}
ns_ev_decoder = ns_ev_decoder->next;
}
if (error)
return -1;
#endif
return 0;
}
static int find_ns_ev_decoder(const char *sec_type, struct ras_ns_ev_decoder **p_ns_ev_dec)
{
struct ras_ns_ev_decoder *ns_ev_decoder;
int match = 0;
ns_ev_decoder = ras_ns_ev_dec_list;
while (ns_ev_decoder) {
if (strcmp(uuid_le(sec_type), ns_ev_decoder->sec_type) == 0) {
*p_ns_ev_dec = ns_ev_decoder;
match = 1;
break;
}
ns_ev_decoder = ns_ev_decoder->next;
}
if (!match)
return -1;
return 0;
}
void ras_ns_finalize_vendor_tables(void)
{
#ifdef HAVE_SQLITE3
struct ras_ns_ev_decoder *ns_ev_decoder = ras_ns_ev_dec_list;
if (!ras_ns_ev_dec_list)
return;
if (ras_ns_ev_dec_list->ref_count > 0)
ras_ns_ev_dec_list->ref_count--;
else
return;
if (ras_ns_ev_dec_list->ref_count > 0)
return;
while (ns_ev_decoder) {
if (ns_ev_decoder->stmt_dec_record) {
ras_mc_finalize_vendor_table(ns_ev_decoder->stmt_dec_record);
ns_ev_decoder->stmt_dec_record = NULL;
}
ns_ev_decoder = ns_ev_decoder->next;
}
#endif
}
static void unregister_ns_ev_decoder(void)
{
#ifdef HAVE_SQLITE3
if (!ras_ns_ev_dec_list)
return;
ras_ns_ev_dec_list->ref_count = 1;
ras_ns_finalize_vendor_tables();
#endif
ras_ns_ev_dec_list = NULL;
}
int ras_non_standard_event_handler(struct trace_seq *s,
struct tep_record *record,
struct tep_event *event, void *context)
{
int len, i, line_count;
unsigned long long val;
struct ras_events *ras = context;
time_t now;
struct tm *tm;
struct ras_non_standard_event ev;
struct ras_ns_ev_decoder *ns_ev_decoder;
/*
* Newer kernels (3.10-rc1 or upper) provide an uptime clock.
* On previous kernels, the way to properly generate an event would
* be to inject a fake one, measure its timestamp and diff it against
* gettimeofday. We won't do it here. Instead, let's use uptime,
* falling-back to the event report's time, if "uptime" clock is
* not available (legacy kernels).
*/
if (ras->use_uptime)
now = record->ts / user_hz + ras->uptime_diff;
else
now = time(NULL);
tm = localtime(&now);
if (tm)
strftime(ev.timestamp, sizeof(ev.timestamp),
"%Y-%m-%d %H:%M:%S %z", tm);
trace_seq_printf(s, "%s ", ev.timestamp);
if (tep_get_field_val(s, event, "sev", record, &val, 1) < 0)
return -1;
switch (val) {
case GHES_SEV_NO:
ev.severity = "Informational";
break;
case GHES_SEV_CORRECTED:
ev.severity = "Corrected";
break;
case GHES_SEV_RECOVERABLE:
ev.severity = "Recoverable";
break;
default:
case GHES_SEV_PANIC:
ev.severity = "Fatal";
}
trace_seq_printf(s, " %s", ev.severity);
ev.sec_type = tep_get_field_raw(s, event, "sec_type",
record, &len, 1);
if (!ev.sec_type)
return -1;
if (strcmp(uuid_le(ev.sec_type),
"e8ed898d-df16-43cc-8ecc-54f060ef157f") == 0)
trace_seq_printf(s, " section type: %s",
"Ampere Specific Error");
else
trace_seq_printf(s, " section type: %s",
uuid_le(ev.sec_type));
ev.fru_text = tep_get_field_raw(s, event, "fru_text",
record, &len, 1);
ev.fru_id = tep_get_field_raw(s, event, "fru_id",
record, &len, 1);
trace_seq_printf(s, " fru text: %s fru id: %s ",
ev.fru_text, uuid_le(ev.fru_id));
if (tep_get_field_val(s, event, "len", record, &val, 1) < 0)
return -1;
ev.length = val;
trace_seq_printf(s, " length: %d", ev.length);
ev.error = tep_get_field_raw(s, event, "buf", record, &len, 1);
if (!ev.error)
return -1;
if (!find_ns_ev_decoder(ev.sec_type, &ns_ev_decoder)) {
ns_ev_decoder->decode(ras, ns_ev_decoder, s, &ev);
} else {
len = ev.length;
i = 0;
line_count = 0;
trace_seq_printf(s, " error:\n %08x: ", i);
while (len >= 4) {
print_le_hex(s, ev.error, i);
i += 4;
len -= 4;
if (++line_count == 4) {
trace_seq_printf(s, "\n %08x: ", i);
line_count = 0;
} else
trace_seq_printf(s, " ");
}
}
/* Insert data into the SGBD */
#ifdef HAVE_SQLITE3
ras_store_non_standard_record(ras, &ev);
#endif
#ifdef HAVE_ABRT_REPORT
/* Report event to ABRT */
ras_report_non_standard_event(ras, &ev);
#endif
return 0;
}
__attribute__((destructor))
static void ns_exit(void)
{
unregister_ns_ev_decoder();
}
|
0 | rasdaemon-master | rasdaemon-master/non-standard-hisilicon.c | /*
* Copyright (c) 2020 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-report.h"
#include "non-standard-hisilicon.h"
#define HISI_BUF_LEN 2048
#define HISI_PCIE_INFO_BUF_LEN 256
struct hisi_common_error_section {
uint32_t val_bits;
uint8_t version;
uint8_t soc_id;
uint8_t socket_id;
uint8_t totem_id;
uint8_t nimbus_id;
uint8_t subsystem_id;
uint8_t module_id;
uint8_t submodule_id;
uint8_t core_id;
uint8_t port_id;
uint16_t err_type;
struct {
uint8_t function;
uint8_t device;
uint16_t segment;
uint8_t bus;
uint8_t reserved[3];
} pcie_info;
uint8_t err_severity;
uint8_t reserved[3];
uint32_t reg_array_size;
uint32_t reg_array[];
};
enum {
HISI_COMMON_VALID_SOC_ID,
HISI_COMMON_VALID_SOCKET_ID,
HISI_COMMON_VALID_TOTEM_ID,
HISI_COMMON_VALID_NIMBUS_ID,
HISI_COMMON_VALID_SUBSYSTEM_ID,
HISI_COMMON_VALID_MODULE_ID,
HISI_COMMON_VALID_SUBMODULE_ID,
HISI_COMMON_VALID_CORE_ID,
HISI_COMMON_VALID_PORT_ID,
HISI_COMMON_VALID_ERR_TYPE,
HISI_COMMON_VALID_PCIE_INFO,
HISI_COMMON_VALID_ERR_SEVERITY,
HISI_COMMON_VALID_REG_ARRAY_SIZE,
};
enum {
HISI_COMMON_FIELD_ID,
HISI_COMMON_FIELD_TIMESTAMP,
HISI_COMMON_FIELD_VERSION,
HISI_COMMON_FIELD_SOC_ID,
HISI_COMMON_FIELD_SOCKET_ID,
HISI_COMMON_FIELD_TOTEM_ID,
HISI_COMMON_FIELD_NIMBUS_ID,
HISI_COMMON_FIELD_SUB_SYSTEM_ID,
HISI_COMMON_FIELD_MODULE_ID,
HISI_COMMON_FIELD_SUB_MODULE_ID,
HISI_COMMON_FIELD_CORE_ID,
HISI_COMMON_FIELD_PORT_ID,
HISI_COMMON_FIELD_ERR_TYPE,
HISI_COMMON_FIELD_PCIE_INFO,
HISI_COMMON_FIELD_ERR_SEVERITY,
HISI_COMMON_FIELD_REGS_DUMP,
};
struct hisi_event {
char error_msg[HISI_BUF_LEN];
char pcie_info[HISI_PCIE_INFO_BUF_LEN];
char reg_msg[HISI_BUF_LEN];
};
#ifdef HAVE_SQLITE3
void record_vendor_data(struct ras_ns_ev_decoder *ev_decoder,
enum hisi_oem_data_type data_type,
int id, int64_t data, const char *text)
{
if (!ev_decoder->stmt_dec_record)
return;
switch (data_type) {
case HISI_OEM_DATA_TYPE_INT:
sqlite3_bind_int(ev_decoder->stmt_dec_record, id, data);
break;
case HISI_OEM_DATA_TYPE_INT64:
sqlite3_bind_int64(ev_decoder->stmt_dec_record, id, data);
break;
case HISI_OEM_DATA_TYPE_TEXT:
sqlite3_bind_text(ev_decoder->stmt_dec_record, id, text, -1, NULL);
break;
}
}
int step_vendor_data_tab(struct ras_ns_ev_decoder *ev_decoder, const char *name)
{
int rc;
if (!ev_decoder->stmt_dec_record)
return 0;
rc = sqlite3_step(ev_decoder->stmt_dec_record);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to do %s step on sqlite: error = %d\n", name, rc);
rc = sqlite3_reset(ev_decoder->stmt_dec_record);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to reset %s on sqlite: error = %d\n", name, rc);
rc = sqlite3_clear_bindings(ev_decoder->stmt_dec_record);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to clear bindings %s on sqlite: error = %d\n",
name, rc);
return rc;
}
#else
void record_vendor_data(struct ras_ns_ev_decoder *ev_decoder,
enum hisi_oem_data_type data_type,
int id, int64_t data, const char *text)
{ }
int step_vendor_data_tab(struct ras_ns_ev_decoder *ev_decoder, const char *name)
{
return 0;
}
#endif
#ifdef HAVE_SQLITE3
static const struct db_fields hisi_common_section_fields[] = {
{ .name = "id", .type = "INTEGER PRIMARY KEY" },
{ .name = "timestamp", .type = "TEXT" },
{ .name = "version", .type = "INTEGER" },
{ .name = "soc_id", .type = "INTEGER" },
{ .name = "socket_id", .type = "INTEGER" },
{ .name = "totem_id", .type = "INTEGER" },
{ .name = "nimbus_id", .type = "INTEGER" },
{ .name = "sub_system_id", .type = "INTEGER" },
{ .name = "module_id", .type = "TEXT" },
{ .name = "sub_module_id", .type = "INTEGER" },
{ .name = "core_id", .type = "INTEGER" },
{ .name = "port_id", .type = "INTEGER" },
{ .name = "err_type", .type = "INTEGER" },
{ .name = "pcie_info", .type = "TEXT" },
{ .name = "err_severity", .type = "TEXT" },
{ .name = "regs_dump", .type = "TEXT" },
};
static const struct db_table_descriptor hisi_common_section_tab = {
.name = "hisi_common_section_v2",
.fields = hisi_common_section_fields,
.num_fields = ARRAY_SIZE(hisi_common_section_fields),
};
#endif
static const char *soc_desc[] = {
"Kunpeng916",
"Kunpeng920",
"Kunpeng930",
};
static const char *module_name[] = {
"MN",
"PLL",
"SLLC",
"AA",
"SIOE",
"POE",
"CPA",
"DISP",
"GIC",
"ITS",
"AVSBUS",
"CS",
"PPU",
"SMMU",
"PA",
"HLLC",
"DDRC",
"L3TAG",
"L3DATA",
"PCS",
"MATA",
"PCIe Local",
"SAS",
"SATA",
"NIC",
"RoCE",
"USB",
"ZIP",
"HPRE",
"SEC",
"RDE",
"MEE",
"L4D",
"Tsensor",
"ROH",
"BTC",
"HILINK",
"STARS",
"SDMA",
"UC",
"HBMC",
};
static const char *get_soc_desc(uint8_t soc_id)
{
if (soc_id >= sizeof(soc_desc) / sizeof(char *))
return "unknown";
return soc_desc[soc_id];
}
static void decode_module(struct ras_ns_ev_decoder *ev_decoder,
struct hisi_event *event, uint8_t module_id)
{
if (module_id >= sizeof(module_name) / sizeof(char *)) {
HISI_SNPRINTF(event->error_msg, "module=unknown(id=%hhu) ", module_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_TEXT,
HISI_COMMON_FIELD_MODULE_ID,
0, "unknown");
} else {
HISI_SNPRINTF(event->error_msg, "module=%s ", module_name[module_id]);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_TEXT,
HISI_COMMON_FIELD_MODULE_ID,
0, module_name[module_id]);
}
}
static void decode_hisi_common_section_hdr(struct ras_ns_ev_decoder *ev_decoder,
const struct hisi_common_error_section *err,
struct hisi_event *event)
{
HISI_SNPRINTF(event->error_msg, "[ table_version=%hhu", err->version);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_VERSION,
err->version, NULL);
if (err->val_bits & BIT(HISI_COMMON_VALID_SOC_ID)) {
HISI_SNPRINTF(event->error_msg, "soc=%s", get_soc_desc(err->soc_id));
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_SOC_ID,
err->soc_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_SOCKET_ID)) {
HISI_SNPRINTF(event->error_msg, "socket_id=%hhu", err->socket_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_SOCKET_ID,
err->socket_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_TOTEM_ID)) {
HISI_SNPRINTF(event->error_msg, "totem_id=%hhu", err->totem_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_TOTEM_ID,
err->totem_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_NIMBUS_ID)) {
HISI_SNPRINTF(event->error_msg, "nimbus_id=%hhu", err->nimbus_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_NIMBUS_ID,
err->nimbus_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_SUBSYSTEM_ID)) {
HISI_SNPRINTF(event->error_msg, "subsystem_id=%hhu", err->subsystem_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_SUB_SYSTEM_ID,
err->subsystem_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_MODULE_ID))
decode_module(ev_decoder, event, err->module_id);
if (err->val_bits & BIT(HISI_COMMON_VALID_SUBMODULE_ID)) {
HISI_SNPRINTF(event->error_msg, "submodule_id=%hhu", err->submodule_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_SUB_MODULE_ID,
err->submodule_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_CORE_ID)) {
HISI_SNPRINTF(event->error_msg, "core_id=%hhu", err->core_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_CORE_ID,
err->core_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_PORT_ID)) {
HISI_SNPRINTF(event->error_msg, "port_id=%hhu", err->port_id);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_PORT_ID,
err->port_id, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_ERR_TYPE)) {
HISI_SNPRINTF(event->error_msg, "err_type=%hu", err->err_type);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_INT,
HISI_COMMON_FIELD_ERR_TYPE,
err->err_type, NULL);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_PCIE_INFO)) {
HISI_SNPRINTF(event->error_msg, "pcie_device_id=%04x:%02x:%02x.%x",
err->pcie_info.segment, err->pcie_info.bus,
err->pcie_info.device, err->pcie_info.function);
HISI_SNPRINTF(event->pcie_info, "%04x:%02x:%02x.%x",
err->pcie_info.segment, err->pcie_info.bus,
err->pcie_info.device, err->pcie_info.function);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_TEXT,
HISI_COMMON_FIELD_PCIE_INFO,
0, event->pcie_info);
}
if (err->val_bits & BIT(HISI_COMMON_VALID_ERR_SEVERITY)) {
HISI_SNPRINTF(event->error_msg, "err_severity=%s", err_severity(err->err_severity));
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_TEXT,
HISI_COMMON_FIELD_ERR_SEVERITY,
0, err_severity(err->err_severity));
}
HISI_SNPRINTF(event->error_msg, "]");
}
static int add_hisi_common_table(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder)
{
#ifdef HAVE_SQLITE3
if (ras->record_events &&
!ev_decoder->stmt_dec_record) {
if (ras_mc_add_vendor_table(ras, &ev_decoder->stmt_dec_record,
&hisi_common_section_tab) != SQLITE_OK) {
log(TERM, LOG_WARNING, "Failed to create sql hisi_common_section_tab\n");
return -1;
}
}
#endif
return 0;
}
static int decode_hisi_common_section(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
const struct hisi_common_error_section *err =
(struct hisi_common_error_section *)event->error;
struct hisi_event hevent;
memset(&hevent, 0, sizeof(struct hisi_event));
trace_seq_printf(s, "\nHisilicon Common Error Section:\n");
decode_hisi_common_section_hdr(ev_decoder, err, &hevent);
trace_seq_printf(s, "%s\n", hevent.error_msg);
if (err->val_bits & BIT(HISI_COMMON_VALID_REG_ARRAY_SIZE) && err->reg_array_size > 0) {
unsigned int i;
trace_seq_printf(s, "Register Dump:\n");
for (i = 0; i < err->reg_array_size / sizeof(uint32_t); i++) {
trace_seq_printf(s, "reg%02u=0x%08x\n", i,
err->reg_array[i]);
HISI_SNPRINTF(hevent.reg_msg, "reg%02u=0x%08x",
i, err->reg_array[i]);
}
}
if (ras->record_events) {
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_TEXT,
HISI_COMMON_FIELD_TIMESTAMP,
0, event->timestamp);
record_vendor_data(ev_decoder, HISI_OEM_DATA_TYPE_TEXT,
HISI_COMMON_FIELD_REGS_DUMP, 0, hevent.reg_msg);
step_vendor_data_tab(ev_decoder, "hisi_common_section_tab");
}
return 0;
}
static struct ras_ns_ev_decoder hisi_section_ns_ev_decoder[] = {
{
.sec_type = "c8b328a8-9917-4af6-9a13-2e08ab2e7586",
.add_table = add_hisi_common_table,
.decode = decode_hisi_common_section,
},
};
static void __attribute__((constructor)) hisi_ns_init(void)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(hisi_section_ns_ev_decoder); i++)
register_ns_ev_decoder(&hisi_section_ns_ev_decoder[i]);
}
|
0 | rasdaemon-master | rasdaemon-master/ras-arm-handler.c | /*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <traceevent/kbuffer.h>
#include "ras-arm-handler.h"
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-report.h"
#include "ras-non-standard-handler.h"
#include "non-standard-ampere.h"
#include "ras-cpu-isolation.h"
#define ARM_ERR_VALID_ERROR_COUNT BIT(0)
#define ARM_ERR_VALID_FLAGS BIT(1)
#define BIT2 2
void display_raw_data(struct trace_seq *s,
const uint8_t *buf,
uint32_t datalen)
{
int i = 0, line_count = 0;
trace_seq_printf(s, " %08x: ", i);
while (datalen >= 4) {
print_le_hex(s, buf, i);
i += 4;
datalen -= 4;
if (++line_count == 4) {
trace_seq_printf(s, "\n %08x: ", i);
line_count = 0;
} else
trace_seq_printf(s, " ");
}
}
#ifdef HAVE_CPU_FAULT_ISOLATION
static int is_core_failure(struct ras_arm_err_info *err_info)
{
if (err_info->validation_bits & ARM_ERR_VALID_FLAGS) {
/*
* core failure:
* Bit 0\1\3: (at lease 1)
* Bit 2: 0
*/
return (err_info->flags & 0xf) && !(err_info->flags & (0x1 << BIT2));
}
return 0;
}
static int count_errors(struct ras_arm_event *ev, int sev)
{
struct ras_arm_err_info *err_info;
int num_pei;
int err_info_size = sizeof(struct ras_arm_err_info);
int num = 0;
int i;
int error_count;
if (ev->pei_len % err_info_size != 0) {
log(TERM, LOG_ERR,
"The event data does not match to the ARM Processor Error Information Structure\n");
return num;
}
num_pei = ev->pei_len / err_info_size;
err_info = (struct ras_arm_err_info *)(ev->pei_error);
for (i = 0; i < num_pei; ++i) {
error_count = 1;
if (err_info->validation_bits & ARM_ERR_VALID_ERROR_COUNT) {
/*
* The value of this field is defined as follows:
* 0: Single Error
* 1: Multiple Errors
* 2-65535: Error Count
*/
error_count = err_info->multiple_error + 1;
}
if (sev == GHES_SEV_RECOVERABLE && !is_core_failure(err_info))
error_count = 0;
num += error_count;
err_info += 1;
}
log(TERM, LOG_INFO, "%d error in cpu core catched\n", num);
return num;
}
static int ras_handle_cpu_error(struct trace_seq *s,
struct tep_record *record,
struct tep_event *event,
struct ras_arm_event *ev, time_t now)
{
unsigned long long val;
int cpu;
char *severity;
struct error_info err_info;
if (tep_get_field_val(s, event, "cpu", record, &val, 1) < 0)
return -1;
cpu = val;
trace_seq_printf(s, "\n cpu: %d", cpu);
/* record cpu error */
if (tep_get_field_val(s, event, "sev", record, &val, 1) < 0)
return -1;
/* refer to UEFI_2_9 specification chapter N2.2 Table N-5 */
switch (val) {
case GHES_SEV_NO:
severity = "Informational";
break;
case GHES_SEV_CORRECTED:
severity = "Corrected";
break;
case GHES_SEV_RECOVERABLE:
severity = "Recoverable";
break;
default:
case GHES_SEV_PANIC:
severity = "Fatal";
}
trace_seq_printf(s, "\n severity: %s", severity);
if (val == GHES_SEV_CORRECTED || val == GHES_SEV_RECOVERABLE) {
int nums = count_errors(ev, val);
if (nums > 0) {
err_info.nums = nums;
err_info.time = now;
err_info.err_type = val;
ras_record_cpu_error(&err_info, cpu);
}
}
return 0;
}
#endif
int ras_arm_event_handler(struct trace_seq *s,
struct tep_record *record,
struct tep_event *event, void *context)
{
unsigned long long val;
struct ras_events *ras = context;
time_t now;
struct tm *tm;
struct ras_arm_event ev;
int len = 0;
memset(&ev, 0, sizeof(ev));
/*
* Newer kernels (3.10-rc1 or upper) provide an uptime clock.
* On previous kernels, the way to properly generate an event would
* be to inject a fake one, measure its timestamp and diff it against
* gettimeofday. We won't do it here. Instead, let's use uptime,
* falling-back to the event report's time, if "uptime" clock is
* not available (legacy kernels).
*/
if (ras->use_uptime)
now = record->ts / user_hz + ras->uptime_diff;
else
now = time(NULL);
tm = localtime(&now);
if (tm)
strftime(ev.timestamp, sizeof(ev.timestamp),
"%Y-%m-%d %H:%M:%S %z", tm);
trace_seq_printf(s, "%s", ev.timestamp);
if (tep_get_field_val(s, event, "affinity", record, &val, 1) < 0)
return -1;
ev.affinity = val;
trace_seq_printf(s, " affinity: %d", ev.affinity);
if (tep_get_field_val(s, event, "mpidr", record, &val, 1) < 0)
return -1;
ev.mpidr = val;
trace_seq_printf(s, " MPIDR: 0x%llx", (unsigned long long)ev.mpidr);
if (tep_get_field_val(s, event, "midr", record, &val, 1) < 0)
return -1;
ev.midr = val;
trace_seq_printf(s, " MIDR: 0x%llx", (unsigned long long)ev.midr);
if (tep_get_field_val(s, event, "running_state", record, &val, 1) < 0)
return -1;
ev.running_state = val;
trace_seq_printf(s, " running_state: %d", ev.running_state);
if (tep_get_field_val(s, event, "psci_state", record, &val, 1) < 0)
return -1;
ev.psci_state = val;
trace_seq_printf(s, " psci_state: %d", ev.psci_state);
if (tep_get_field_val(s, event, "pei_len", record, &val, 1) < 0)
return -1;
ev.pei_len = val;
trace_seq_printf(s, " ARM Processor Err Info data len: %d\n",
ev.pei_len);
ev.pei_error = tep_get_field_raw(s, event, "buf", record, &len, 1);
if (!ev.pei_error)
return -1;
display_raw_data(s, ev.pei_error, ev.pei_len);
if (tep_get_field_val(s, event, "ctx_len", record, &val, 1) < 0)
return -1;
ev.ctx_len = val;
trace_seq_printf(s, " ARM Processor Err Context Info data len: %d\n",
ev.ctx_len);
ev.ctx_error = tep_get_field_raw(s, event, "buf1", record, &len, 1);
if (!ev.ctx_error)
return -1;
display_raw_data(s, ev.ctx_error, ev.ctx_len);
if (tep_get_field_val(s, event, "oem_len", record, &val, 1) < 0)
return -1;
ev.oem_len = val;
trace_seq_printf(s, " Vendor Specific Err Info data len: %d\n",
ev.oem_len);
ev.vsei_error = tep_get_field_raw(s, event, "buf2", record, &len, 1);
if (!ev.vsei_error)
return -1;
#ifdef HAVE_AMP_NS_DECODE
//decode ampere specific error
decode_amp_payload0_err_regs(NULL, s,
(struct amp_payload0_type_sec *)ev.vsei_error);
#else
display_raw_data(s, ev.vsei_error, ev.oem_len);
#endif
#ifdef HAVE_CPU_FAULT_ISOLATION
if (ras_handle_cpu_error(s, record, event, &ev, now) < 0)
return -1;
#endif
/* Insert data into the SGBD */
#ifdef HAVE_SQLITE3
ras_store_arm_record(ras, &ev);
#endif
#ifdef HAVE_ABRT_REPORT
/* Report event to ABRT */
ras_report_arm_event(ras, &ev);
#endif
return 0;
}
|
0 | rasdaemon-master | rasdaemon-master/non-standard-jaguarmicro.c | /*
* Copyright (c) 2023, JaguarMicro
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-report.h"
#include "ras-non-standard-handler.h"
#include "non-standard-jaguarmicro.h"
#include "ras-mce-handler.h"
#define JM_BUF_LEN 256
#define JM_REG_BUF_LEN 2048
#define JM_SNPRINTF mce_snprintf
static void record_jm_data(struct ras_ns_ev_decoder *ev_decoder,
enum jm_oem_data_type data_type,
int id, int64_t data, const char *text);
struct jm_event {
char error_msg[JM_BUF_LEN];
char reg_msg[JM_REG_BUF_LEN];
};
/*ras_csr_por Payload Type 0*/
static const char * const disp_payload0_err_reg_name[] = {
"LOCK_CONTROL:",
"LOCK_FUNCTION:",
"CFG_RAM_ID:",
"ERR_FR_LOW32:",
"ERR_FR_HIGH32:",
"ERR_CTLR_LOW32:",
"ECC_STATUS_LOW32:",
"ECC_ADDR_LOW32:",
"ECC_ADDR_HIGH32:",
"ECC_MISC0_LOW32:",
"ECC_MISC0_HIGH32:",
"ECC_MISC1_LOW32:",
"ECC_MISC1_HIGH32:",
"ECC_MISC2_LOW32:",
"ECC_MISC2_HIGH32:",
};
/*SMMU IP Payload Type 1*/
static const char * const disp_payload1_err_reg_name[] = {
"CSR_INT_STATUS:",
"ERR_FR:",
"ERR_CTLR:",
"ERR_STATUS:",
"ERR_GEN:",
};
/*HAC SRAM, Payload Type 2 */
static const char * const disp_payload2_err_reg_name[] = {
"ECC_1BIT_INFO_LOW32:",
"ECC_1BIT_INFO_HIGH32:",
"ECC_2BIT_INFO_LOW32:",
"ECC_2BIT_INFO_HIGH32:",
};
/*CMN IP, Payload Type 5 */
static const char * const disp_payload5_err_reg_name[] = {
"CFGM_MXP_0:",
"CFGM_HNF_0:",
"CFGM_HNI_0:",
"CFGM_SBSX_0:",
"ERR_FR_NS:",
"ERR_CTLRR_NS:",
"ERR_STATUSR_NS:",
"ERR_ADDRR_NS:",
"ERR_MISCR_NS:",
"ERR_FR:",
"ERR_CTLR:",
"ERR_STATUS:",
"ERR_ADDR:",
"ERR_MISC:",
};
/*GIC IP, Payload Type 6 */
static const char * const disp_payload6_err_reg_name[] = {
"RECORD_ID:",
"GICT_ERR_FR:",
"GICT_ERR_CTLR:",
"GICT_ERR_STATUS:",
"GICT_ERR_ADDR:",
"GICT_ERR_MISC0:",
"GICT_ERR_MISC1:",
"GICT_ERRGSR:",
};
static const char * const soc_desc[] = {
"Corsica1.0",
};
/* JaguarMicro sub system definitions */
#define JM_SUB_SYS_CSUB 0
#define JM_SUB_SYS_CMN 1
#define JM_SUB_SYS_DDRH 2
#define JM_SUB_SYS_DDRV 3
#define JM_SUB_SYS_GIC 4
#define JM_SUB_SYS_IOSUB 5
#define JM_SUB_SYS_SCP 6
#define JM_SUB_SYS_MCP 7
#define JM_SUB_SYS_IMU0 8
#define JM_SUB_SYS_DPE 9
#define JM_SUB_SYS_RPE 10
#define JM_SUB_SYS_PSUB 11
#define JM_SUB_SYS_HAC 12
#define JM_SUB_SYS_TCM 13
#define JM_SUB_SYS_IMU1 14
static const char * const subsystem_desc[] = {
"N2",
"CMN",
"DDRH",
"DDRV",
"GIC",
"IOSUB",
"SCP",
"MCP",
"IMU0",
"DPE",
"RPE",
"PSUB",
"HAC",
"TCM",
"IMU1",
};
static const char * const cmn_module_desc[] = {
"MXP",
"HNI",
"HNF",
"SBSX",
"CCG",
"HND",
};
static const char * const ddr_module_desc[] = {
"DDRCtrl",
"DDRPHY",
"SRAM",
};
static const char * const gic_module_desc[] = {
"GICIP",
"GICSRAM",
};
/* JaguarMicro IOSUB sub system module definitions */
#define JM_SUBSYS_IOSUB_MOD_SMMU 0
#define JM_SUBSYS_IOSUB_MOD_NIC450 1
#define JM_SUBSYS_IOSUB_MOD_OTHER 2
static const char * const iosub_module_desc[] = {
"SMMU",
"NIC450",
"OTHER",
};
static const char * const scp_module_desc[] = {
"SRAM",
"WDT",
"PLL",
};
static const char * const mcp_module_desc[] = {
"SRAM",
"WDT",
};
static const char * const imu_module_desc[] = {
"SRAM",
"WDT",
};
/* JaguarMicro DPE sub system module definitions */
#define JM_SUBSYS_DPE_MOD_EPG 0
#define JM_SUBSYS_DPE_MOD_PIPE 1
#define JM_SUBSYS_DPE_MOD_EMEP 2
#define JM_SUBSYS_DPE_MOD_IMEP 3
#define JM_SUBSYS_DPE_MOD_EPAE 4
#define JM_SUBSYS_DPE_MOD_IPAE 5
#define JM_SUBSYS_DPE_MOD_ETH 6
#define JM_SUBSYS_DPE_MOD_TPG 7
#define JM_SUBSYS_DPE_MOD_MIG 8
#define JM_SUBSYS_DPE_MOD_HIG 9
#define JM_SUBSYS_DPE_MOD_DPETOP 10
#define JM_SUBSYS_DPE_MOD_SMMU 11
static const char * const dpe_module_desc[] = {
"EPG",
"PIPE",
"EMEP",
"IMEP",
"EPAE",
"IPAE",
"ETH",
"TPG",
"MIG",
"HIG",
"DPETOP",
"SMMU",
};
/* JaguarMicro RPE sub system module definitions */
#define JM_SUBSYS_RPE_MOD_TOP 0
#define JM_SUBSYS_RPE_MOD_TXP_RXP 1
#define JM_SUBSYS_RPE_MOD_SMMU 2
static const char * const rpe_module_desc[] = {
"TOP",
"TXP_RXP",
"SMMU",
};
/* JaguarMicro PSUB sub system module definitions */
#define JM_SUBSYS_PSUB_MOD_PCIE0 0
#define JM_SUBSYS_PSUB_MOD_UP_MIX 1
#define JM_SUBSYS_PSUB_MOD_PCIE1 2
#define JM_SUBSYS_PSUB_MOD_PTOP 3
#define JM_SUBSYS_PSUB_MOD_N2IF 4
#define JM_SUBSYS_PSUB_MOD_VPE0_RAS 5
#define JM_SUBSYS_PSUB_MOD_VPE1_RAS 6
#define JM_SUBSYS_PSUB_MOD_X2RC_SMMU 7
#define JM_SUBSYS_PSUB_MOD_X16RC_SMMU 8
#define JM_SUBSYS_PSUB_MOD_SDMA_SMMU 9
static const char * const psub_module_desc[] = {
"PCIE0",
"UP_MIX",
"PCIE1",
"PTOP",
"N2IF",
"VPE0_RAS",
"VPE1_RAS",
"X2RC_SMMU",
"X16RC_SMMU",
"SDMA_SMMU",
};
static const char * const hac_module_desc[] = {
"SRAM",
"SMMU",
};
#define JM_SUBSYS_TCM_MOD_SRAM 0
#define JM_SUBSYS_TCM_MOD_SMMU 1
#define JM_SUBSYS_TCM_MOD_IP 2
static const char * const tcm_module_desc[] = {
"SRAM",
"SMMU",
"IP",
};
static const char * const iosub_smmu_sub_desc[] = {
"TBU",
"TCU",
};
static const char * const iosub_other_sub_desc[] = {
"RAM",
};
static const char * const smmu_sub_desc[] = {
"TCU",
"TBU",
};
static const char * const psub_pcie0_sub_desc[] = {
"RAS0",
"RAS1",
};
static const char * const csub_dev_desc[] = {
"CORE",
};
static const char * const cmn_dev_desc[] = {
"NID",
};
static const char * const ddr_dev_desc[] = {
"CHNL",
};
static const char * const default_dev_desc[] = {
"DEV",
};
static const char *get_jm_soc_desc(uint8_t soc_id)
{
if (soc_id >= sizeof(soc_desc) / sizeof(char *))
return "unknown";
return soc_desc[soc_id];
}
static const char *get_jm_subsystem_desc(uint8_t subsys_id)
{
if (subsys_id >= sizeof(subsystem_desc) / sizeof(char *))
return "unknown";
return subsystem_desc[subsys_id];
}
static const char *get_jm_module_desc(uint8_t subsys_id, uint8_t mod_id)
{
const char * const*module;
int tbl_size;
switch (subsys_id) {
case JM_SUB_SYS_CMN:
module = cmn_module_desc;
tbl_size = sizeof(cmn_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_DDRH:
case JM_SUB_SYS_DDRV:
module = ddr_module_desc;
tbl_size = sizeof(ddr_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_GIC:
module = gic_module_desc;
tbl_size = sizeof(gic_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_IOSUB:
module = iosub_module_desc;
tbl_size = sizeof(iosub_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_SCP:
module = scp_module_desc;
tbl_size = sizeof(scp_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_MCP:
module = mcp_module_desc;
tbl_size = sizeof(mcp_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_IMU0:
case JM_SUB_SYS_IMU1:
module = imu_module_desc;
tbl_size = sizeof(imu_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_DPE:
module = dpe_module_desc;
tbl_size = sizeof(dpe_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_RPE:
module = rpe_module_desc;
tbl_size = sizeof(rpe_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_PSUB:
module = psub_module_desc;
tbl_size = sizeof(psub_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_HAC:
module = hac_module_desc;
tbl_size = sizeof(hac_module_desc) / sizeof(char *);
break;
case JM_SUB_SYS_TCM:
module = tcm_module_desc;
tbl_size = sizeof(tcm_module_desc) / sizeof(char *);
break;
default:
module = NULL;
break;
}
if ((!module) || (mod_id >= tbl_size))
return "unknown";
return module[mod_id];
}
static const char *get_jm_submod_desc(uint8_t subsys_id, uint8_t mod_id, uint8_t sub_id)
{
const char * const*sub_module;
int tbl_size;
if (subsys_id == JM_SUB_SYS_IOSUB && mod_id == JM_SUBSYS_IOSUB_MOD_SMMU) {
sub_module = iosub_smmu_sub_desc;
tbl_size = sizeof(iosub_smmu_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_IOSUB && mod_id == JM_SUBSYS_IOSUB_MOD_OTHER) {
sub_module = iosub_other_sub_desc;
tbl_size = sizeof(iosub_other_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_DPE && mod_id == JM_SUBSYS_DPE_MOD_SMMU) {
sub_module = smmu_sub_desc;
tbl_size = sizeof(smmu_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_RPE && mod_id == JM_SUBSYS_RPE_MOD_SMMU) {
sub_module = smmu_sub_desc;
tbl_size = sizeof(smmu_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_PSUB && mod_id == JM_SUBSYS_PSUB_MOD_PCIE0) {
sub_module = psub_pcie0_sub_desc;
tbl_size = sizeof(psub_pcie0_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_PSUB && mod_id == JM_SUBSYS_PSUB_MOD_X2RC_SMMU) {
sub_module = smmu_sub_desc;
tbl_size = sizeof(smmu_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_PSUB && mod_id == JM_SUBSYS_PSUB_MOD_X16RC_SMMU) {
sub_module = smmu_sub_desc;
tbl_size = sizeof(smmu_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_PSUB && mod_id == JM_SUBSYS_PSUB_MOD_SDMA_SMMU) {
sub_module = smmu_sub_desc;
tbl_size = sizeof(smmu_sub_desc) / sizeof(char *);
} else if (subsys_id == JM_SUB_SYS_TCM && mod_id == JM_SUBSYS_TCM_MOD_SMMU) {
sub_module = smmu_sub_desc;
tbl_size = sizeof(smmu_sub_desc) / sizeof(char *);
} else {
sub_module = NULL;
tbl_size = 0;
}
if ((!sub_module) || (sub_id >= tbl_size))
return "unknown";
return sub_module[sub_id];
}
static const char *get_jm_dev_desc(uint8_t subsys_id, uint8_t mod_id, uint8_t sub_id)
{
if (subsys_id == JM_SUB_SYS_CSUB)
return csub_dev_desc[0];
else if (subsys_id == JM_SUB_SYS_DDRH || subsys_id == JM_SUB_SYS_DDRV)
return ddr_dev_desc[0];
else if (subsys_id == JM_SUB_SYS_CMN)
return cmn_dev_desc[0];
else
return default_dev_desc[0];
}
#define JM_ERR_SEVERITY_NFE 0
#define JM_ERR_SEVERITY_FE 1
#define JM_ERR_SEVERITY_CE 2
#define JM_ERR_SEVERITY_NONE 3
/* helper functions */
static inline char *jm_err_severity(uint8_t err_sev)
{
switch (err_sev) {
case JM_ERR_SEVERITY_NFE: return "recoverable";
case JM_ERR_SEVERITY_FE: return "fatal";
case JM_ERR_SEVERITY_CE: return "corrected";
case JM_ERR_SEVERITY_NONE: return "none";
default:
break;
}
return "unknown";
}
static void decode_jm_common_sec_head(struct ras_ns_ev_decoder *ev_decoder,
const struct jm_common_sec_head *err,
struct jm_event *event)
{
if (err->val_bits & BIT(JM_COMMON_VALID_SOC_ID)) {
JM_SNPRINTF(event->error_msg, "[ table_version=%hhu decode_version:%hhu",
err->version, PAYLOAD_VERSION);
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_INT,
JM_PAYLOAD_FIELD_VERSION,
err->version, NULL);
}
if (err->val_bits & BIT(JM_COMMON_VALID_SOC_ID)) {
JM_SNPRINTF(event->error_msg, " soc=%s", get_jm_soc_desc(err->soc_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_INT,
JM_PAYLOAD_FIELD_SOC_ID,
err->soc_id, NULL);
}
if (err->val_bits & BIT(JM_COMMON_VALID_SUBSYSTEM_ID)) {
JM_SNPRINTF(event->error_msg, " sub system=%s",
get_jm_subsystem_desc(err->subsystem_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
JM_PAYLOAD_FIELD_SUB_SYS,
0, get_jm_subsystem_desc(err->subsystem_id));
}
if (err->val_bits & BIT(JM_COMMON_VALID_MODULE_ID)) {
JM_SNPRINTF(event->error_msg, " module=%s",
get_jm_module_desc(err->subsystem_id, err->module_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
JM_PAYLOAD_FIELD_MODULE,
0, get_jm_module_desc(err->subsystem_id, err->module_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_INT,
JM_PAYLOAD_FIELD_MODULE_ID,
err->module_id, NULL);
}
if (err->val_bits & BIT(JM_COMMON_VALID_SUBMODULE_ID)) {
JM_SNPRINTF(event->error_msg, " sub module=%s",
get_jm_submod_desc(err->subsystem_id, err->module_id, err->submodule_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
JM_PAYLOAD_FIELD_SUB_MODULE,
0,
get_jm_submod_desc(err->subsystem_id, err->module_id, err->submodule_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_INT,
JM_PAYLOAD_FIELD_MODULE_ID,
err->submodule_id, NULL);
}
if (err->val_bits & BIT(JM_COMMON_VALID_DEV_ID)) {
JM_SNPRINTF(event->error_msg, " dev=%s",
get_jm_dev_desc(err->subsystem_id, err->module_id, err->submodule_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
JM_PAYLOAD_FIELD_DEV,
0, get_jm_dev_desc(err->subsystem_id, err->module_id, err->submodule_id));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_INT,
JM_PAYLOAD_FIELD_DEV_ID,
err->dev_id, NULL);
}
if (err->val_bits & BIT(JM_COMMON_VALID_ERR_TYPE)) {
JM_SNPRINTF(event->error_msg, " err_type=%hu", err->err_type);
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_INT,
JM_PAYLOAD_FIELD_ERR_TYPE,
err->err_type, NULL);
}
if (err->val_bits & BIT(JM_COMMON_VALID_ERR_SEVERITY)) {
JM_SNPRINTF(event->error_msg, " err_severity=%s",
jm_err_severity(err->err_severity));
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
JM_PAYLOAD_FIELD_ERR_SEVERITY,
0, jm_err_severity(err->err_severity));
}
JM_SNPRINTF(event->error_msg, "]");
}
static void decode_jm_common_sec_tail(struct ras_ns_ev_decoder *ev_decoder,
const struct jm_common_sec_tail *err,
struct jm_event *event, uint32_t val_bits)
{
if (val_bits & BIT(JM_COMMON_VALID_REG_ARRAY_SIZE) && err->reg_array_size > 0) {
int i;
JM_SNPRINTF(event->reg_msg, "Extended Register Dump:");
for (i = 0; i < err->reg_array_size; i++) {
JM_SNPRINTF(event->reg_msg, "reg%02d=0x%08x",
i, err->reg_array[i]);
}
}
}
#ifdef HAVE_SQLITE3
/*key pair definition for jaguar micro specific error payload type 0*/
static const struct db_fields jm_payload0_event_fields[] = {
{ .name = "id", .type = "INTEGER PRIMARY KEY" },
{ .name = "timestamp", .type = "TEXT" },
{ .name = "version", .type = "INTEGER" },
{ .name = "soc_id", .type = "INTEGER" },
{ .name = "subsystem", .type = "TEXT" },
{ .name = "module", .type = "TEXT" },
{ .name = "module_id", .type = "INTEGER" },
{ .name = "sub_module", .type = "TEXT" },
{ .name = "submodule_id", .type = "INTEGER" },
{ .name = "dev", .type = "TEXT" },
{ .name = "dev_id", .type = "INTEGER" },
{ .name = "err_type", .type = "INTEGER" },
{ .name = "err_severity", .type = "TEXT" },
{ .name = "regs_dump", .type = "TEXT" },
};
static const struct db_table_descriptor jm_payload0_event_tab = {
.name = "jm_payload0_event",
.fields = jm_payload0_event_fields,
.num_fields = ARRAY_SIZE(jm_payload0_event_fields),
};
/*Save data with different type into sqlite3 db*/
static void record_jm_data(struct ras_ns_ev_decoder *ev_decoder,
enum jm_oem_data_type data_type, int id,
int64_t data, const char *text)
{
switch (data_type) {
case JM_OEM_DATA_TYPE_INT:
sqlite3_bind_int(ev_decoder->stmt_dec_record, id, data);
break;
case JM_OEM_DATA_TYPE_INT64:
sqlite3_bind_int64(ev_decoder->stmt_dec_record, id, data);
break;
case JM_OEM_DATA_TYPE_TEXT:
sqlite3_bind_text(ev_decoder->stmt_dec_record, id, text,
-1, NULL);
break;
default:
break;
}
}
static int store_jm_err_data(struct ras_ns_ev_decoder *ev_decoder,
const char *tab_name)
{
int rc;
rc = sqlite3_step(ev_decoder->stmt_dec_record);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to do step on sqlite. Table = %s error = %d\n",
tab_name, rc);
rc = sqlite3_reset(ev_decoder->stmt_dec_record);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to reset on sqlite. Table = %s error = %d\n",
tab_name, rc);
rc = sqlite3_clear_bindings(ev_decoder->stmt_dec_record);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to clear bindings on sqlite. Table = %s error = %d\n",
tab_name, rc);
return rc;
}
/*save all JaguarMicro Specific Error Payload type 0 to sqlite3 database*/
static void record_jm_payload_err(struct ras_ns_ev_decoder *ev_decoder,
const char *reg_str)
{
if (ev_decoder) {
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
JM_PAYLOAD_FIELD_REGS_DUMP, 0, reg_str);
store_jm_err_data(ev_decoder, "jm_payload0_event_tab");
}
}
#else
static void record_jm_data(struct ras_ns_ev_decoder *ev_decoder,
enum jm_oem_data_type data_type,
int id, int64_t data, const char *text)
{
}
static void record_jm_payload_err(struct ras_ns_ev_decoder *ev_decoder,
const char *reg_str)
{
}
#endif
/*decode JaguarMicro specific error payload type 0, the CPU's data is save*/
/*to sqlite by ras-arm-handler, others are saved by this function.*/
static void decode_jm_payload0_err_regs(struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
const struct jm_payload0_type_sec *err)
{
int i = 0;
const struct jm_common_sec_head *common_head = &err->common_head;
const struct jm_common_sec_tail *common_tail = &err->common_tail;
struct jm_event jmevent;
memset(&jmevent, 0, sizeof(struct jm_event));
trace_seq_printf(s, "\nJaguar Micro Common Error Section:\n");
decode_jm_common_sec_head(ev_decoder, common_head, &jmevent);
trace_seq_printf(s, "%s\n", jmevent.error_msg);
//display lock_control
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->lock_control);
//display lock_function
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->lock_function);
//display cfg_ram_id
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->cfg_ram_id);
//display err_fr_low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->err_fr_low32);
//display err_fr_high32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->err_fr_high32);
//display err_ctlr_low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->err_ctlr_low32);
//display ecc_status_low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_status_low32);
//display ecc_addr_low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_addr_low32);
//display ecc_addr_high32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_addr_high32);
//display ecc_misc0_low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_misc0_low32);
//display ecc_misc0_high32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_misc0_high32);
//display ecc_misc1_low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_misc1_low32);
//display ecc_misc1_high32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_misc1_high32);
//display ecc_misc2_Low32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_misc2_Low32);
//display ecc_misc2_high32
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload0_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x\n", err->ecc_misc2_high32);
trace_seq_printf(s, "Register Dump:\n");
decode_jm_common_sec_tail(ev_decoder, common_tail, &jmevent, common_head->val_bits);
record_jm_payload_err(ev_decoder, jmevent.reg_msg);
trace_seq_printf(s, "%s\n", jmevent.reg_msg);
}
/*decode JaguarMicro specific error payload type 1 and save to sqlite db*/
static void decode_jm_payload1_err_regs(struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
const struct jm_payload1_type_sec *err)
{
int i = 0;
const struct jm_common_sec_head *common_head = &err->common_head;
const struct jm_common_sec_tail *common_tail = &err->common_tail;
struct jm_event jmevent;
memset(&jmevent, 0, sizeof(struct jm_event));
trace_seq_printf(s, "\nJaguarMicro Common Error Section:\n");
decode_jm_common_sec_head(ev_decoder, common_head, &jmevent);
trace_seq_printf(s, "%s\n", jmevent.error_msg);
//display smmu csr(Inturrpt status)
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload1_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->smmu_csr);
//display ERRFR
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload1_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->errfr);
//display ERRCTLR
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload1_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->errctlr);
//display ERRSTATUS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload1_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->errstatus);
//display ERRGEN
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload1_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x\n", err->errgen);
trace_seq_printf(s, "Register Dump:\n");
decode_jm_common_sec_tail(ev_decoder, common_tail, &jmevent, common_head->val_bits);
record_jm_payload_err(ev_decoder, jmevent.reg_msg);
trace_seq_printf(s, "%s\n", jmevent.reg_msg);
}
/*decode JaguarMicro specific error payload type 2 and save to sqlite db*/
static void decode_jm_payload2_err_regs(struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
const struct jm_payload2_type_sec *err)
{
int i = 0;
const struct jm_common_sec_head *common_head = &err->common_head;
const struct jm_common_sec_tail *common_tail = &err->common_tail;
struct jm_event jmevent;
memset(&jmevent, 0, sizeof(struct jm_event));
trace_seq_printf(s, "\nJaguarMicro Common Error Section:\n");
decode_jm_common_sec_head(ev_decoder, common_head, &jmevent);
trace_seq_printf(s, "%s\n", jmevent.error_msg);
//display ecc_1bit_error_interrupt_low
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload2_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_1bit_int_low);
//display ecc_1bit_error_interrupt_high
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload2_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_1bit_int_high);
//display ecc_2bit_error_interrupt_low
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload2_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x; ", err->ecc_2bit_int_low);
//display ecc_2bit_error_interrupt_high
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload2_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%x\n", err->ecc_2bit_int_high);
trace_seq_printf(s, "Register Dump:\n");
decode_jm_common_sec_tail(ev_decoder, common_tail, &jmevent, common_head->val_bits);
record_jm_payload_err(ev_decoder, jmevent.reg_msg);
trace_seq_printf(s, "%s\n", jmevent.reg_msg);
}
/*decode JaguarMicro specific error payload type 5 and save to sqlite db*/
static void decode_jm_payload5_err_regs(struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
const struct jm_payload5_type_sec *err)
{
int i = 0;
const struct jm_common_sec_head *common_head = &err->common_head;
const struct jm_common_sec_tail *common_tail = &err->common_tail;
struct jm_event jmevent;
memset(&jmevent, 0, sizeof(struct jm_event));
trace_seq_printf(s, "\nJaguarMicro Common Error Section:\n");
decode_jm_common_sec_head(ev_decoder, common_head, &jmevent);
trace_seq_printf(s, "%s\n", jmevent.error_msg);
//display cfgm_mxp_0
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->cfgm_mxp_0);
//display cfgm_hnf_0
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->cfgm_hnf_0);
//display cfgm_hni_0
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->cfgm_hni_0);
//display cfgm_sbsx_0
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->cfgm_sbsx_0);
//display errfr_NS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errfr_NS);
//display errctlrr_NS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errctlrr_NS);
//display errstatusr_NS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errstatusr_NS);
//display erraddrr_NS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->erraddrr_NS);
//display errmiscr_NS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errmiscr_NS);
//display errfr
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errfr);
//display errctlr
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errctlr);
//display errstatus
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->errstatus);
//display erraddr
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->erraddr);
//display errmisc
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload5_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx\n", (unsigned long long)err->errmisc);
trace_seq_printf(s, "Register Dump:\n");
decode_jm_common_sec_tail(ev_decoder, common_tail, &jmevent, common_head->val_bits);
record_jm_payload_err(ev_decoder, jmevent.reg_msg);
trace_seq_printf(s, "%s\n", jmevent.reg_msg);
}
/*decode JaguarMicro specific error payload type 6 and save to sqlite db*/
static void decode_jm_payload6_err_regs(struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
const struct jm_payload6_type_sec *err)
{
int i = 0;
const struct jm_common_sec_head *common_head = &err->common_head;
const struct jm_common_sec_tail *common_tail = &err->common_tail;
struct jm_event jmevent;
memset(&jmevent, 0, sizeof(struct jm_event));
trace_seq_printf(s, "\nJaguarMicro Common Error Section:\n");
decode_jm_common_sec_head(ev_decoder, common_head, &jmevent);
trace_seq_printf(s, "%s\n", jmevent.error_msg);
//display RECORD_ID
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->record_id);
//display GICT_ERR_FR
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->gict_err_fr);
//display GICT_ERR_CTLR
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->gict_err_ctlr);
//display GICT_ERR_STATUS
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->gict_err_status);
//display GICT_ERR_ADDR
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->gict_err_addr);
//display GICT_ERR_MISC0
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->gict_err_misc0);
//display GICT_ERR_MISC1
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx; ", (unsigned long long)err->gict_err_misc1);
//display GICT_ERRGSR
JM_SNPRINTF(jmevent.reg_msg, " %s", disp_payload6_err_reg_name[i++]);
JM_SNPRINTF(jmevent.reg_msg, " 0x%llx\n", (unsigned long long)err->gict_errgsr);
trace_seq_printf(s, "Register Dump:\n");
decode_jm_common_sec_tail(ev_decoder, common_tail, &jmevent, common_head->val_bits);
record_jm_payload_err(ev_decoder, jmevent.reg_msg);
trace_seq_printf(s, "%s\n", jmevent.reg_msg);
}
/* error data decoding functions */
static int decode_jm_oem_type_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event,
int payload_type)
{
int id = JM_PAYLOAD_FIELD_TIMESTAMP;
record_jm_data(ev_decoder, JM_OEM_DATA_TYPE_TEXT,
id, 0, event->timestamp);
if (payload_type == PAYLOAD_TYPE_0) {
const struct jm_payload0_type_sec *err =
(struct jm_payload0_type_sec *)event->error;
decode_jm_payload0_err_regs(ev_decoder, s, err);
} else if (payload_type == PAYLOAD_TYPE_1) {
const struct jm_payload1_type_sec *err =
(struct jm_payload1_type_sec *)event->error;
decode_jm_payload1_err_regs(ev_decoder, s, err);
} else if (payload_type == PAYLOAD_TYPE_2) {
const struct jm_payload2_type_sec *err =
(struct jm_payload2_type_sec *)event->error;
decode_jm_payload2_err_regs(ev_decoder, s, err);
} else if (payload_type == PAYLOAD_TYPE_5) {
const struct jm_payload5_type_sec *err =
(struct jm_payload5_type_sec *)event->error;
decode_jm_payload5_err_regs(ev_decoder, s, err);
} else if (payload_type == PAYLOAD_TYPE_6) {
const struct jm_payload6_type_sec *err =
(struct jm_payload6_type_sec *)event->error;
decode_jm_payload6_err_regs(ev_decoder, s, err);
} else {
trace_seq_printf(s, "%s : wrong payload type\n", __func__);
log(TERM, LOG_ERR, "%s : wrong payload type\n", __func__);
return -1;
}
return 0;
}
/* error type0 data decoding functions */
static int decode_jm_oem_type0_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
return decode_jm_oem_type_error(ras, ev_decoder, s, event, PAYLOAD_TYPE_0);
}
/* error type1 data decoding functions */
static int decode_jm_oem_type1_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
return decode_jm_oem_type_error(ras, ev_decoder, s, event, PAYLOAD_TYPE_1);
}
/* error type2 data decoding functions */
static int decode_jm_oem_type2_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
return decode_jm_oem_type_error(ras, ev_decoder, s, event, PAYLOAD_TYPE_2);
}
/* error type5 data decoding functions */
static int decode_jm_oem_type5_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
return decode_jm_oem_type_error(ras, ev_decoder, s, event, PAYLOAD_TYPE_5);
}
/* error type6 data decoding functions */
static int decode_jm_oem_type6_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
return decode_jm_oem_type_error(ras, ev_decoder, s, event, PAYLOAD_TYPE_6);
}
static int add_jm_oem_type0_table(struct ras_events *ras, struct ras_ns_ev_decoder *ev_decoder)
{
#ifdef HAVE_SQLITE3
if (ras->record_events && !ev_decoder->stmt_dec_record) {
if (ras_mc_add_vendor_table(ras, &ev_decoder->stmt_dec_record,
&jm_payload0_event_tab) != SQLITE_OK) {
log(TERM, LOG_WARNING, "Failed to create sql jm_payload0_event_tab\n");
return -1;
}
}
#endif
return 0;
}
struct ras_ns_ev_decoder jm_ns_oem_type_decoder[] = {
{
.sec_type = "82d78ba3-fa14-407a-ba0e-f3ba8170013c",
.add_table = add_jm_oem_type0_table,
.decode = decode_jm_oem_type0_error,
},
{
.sec_type = "f9723053-2558-49b1-b58a-1c1a82492a62",
.add_table = add_jm_oem_type0_table,
.decode = decode_jm_oem_type1_error,
},
{
.sec_type = "2d31de54-3037-4f24-a283-f69ca1ec0b9a",
.add_table = add_jm_oem_type0_table,
.decode = decode_jm_oem_type2_error,
},
{
.sec_type = "dac80d69-0a72-4eba-8114-148ee344af06",
.add_table = add_jm_oem_type0_table,
.decode = decode_jm_oem_type5_error,
},
{
.sec_type = "746f06fe-405e-451f-8d09-02e802ed984a",
.add_table = add_jm_oem_type0_table,
.decode = decode_jm_oem_type6_error,
},
};
static void __attribute__((constructor)) jm_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(jm_ns_oem_type_decoder); i++)
register_ns_ev_decoder(&jm_ns_oem_type_decoder[i]);
}
|
0 | rasdaemon-master | rasdaemon-master/bitfield.c | /*
* Copyright (C) 2013 Mauro Carvalho Chehab <mchehab+redhat@kernel.org>
*
* The code below were adapted from Andi Kleen/Intel/SuSe mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <stdio.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
unsigned int bitfield_msg(char *buf, size_t len, const char **bitarray,
unsigned int array_len,
unsigned int bit_offset, unsigned int ignore_bits,
uint64_t status)
{
int i, n;
char *p = buf;
len--;
for (i = 0; i < array_len; i++) {
if (status & ignore_bits)
continue;
if (status & (1 << (i + bit_offset))) {
if (p != buf) {
n = snprintf(p, len, ", ");
if (n < 0)
break;
len -= n;
p += n;
}
if (!bitarray[i])
n = snprintf(p, len, "BIT%d", i + bit_offset);
else
n = snprintf(p, len, "%s", bitarray[i]);
if (n < 0)
break;
len -= n;
p += n;
}
}
*p = 0;
return p - buf;
}
static uint64_t bitmask(uint64_t i)
{
uint64_t mask = 1;
while (mask < i)
mask = (mask << 1) | 1;
return mask;
}
void decode_bitfield(struct mce_event *e, uint64_t status,
struct field *fields)
{
struct field *f;
for (f = fields; f->str; f++) {
uint64_t v = (status >> f->start_bit) & bitmask(f->stringlen - 1);
char *s = NULL;
if (v < f->stringlen)
s = f->str[v];
if (!s) {
if (v == 0)
continue;
mce_snprintf(e->error_msg, "<%u:%llx>",
f->start_bit, (long long)v);
} else
mce_snprintf(e->error_msg, "%s", s);
}
}
void decode_numfield(struct mce_event *e, uint64_t status,
struct numfield *fields)
{
struct numfield *f;
for (f = fields; f->name; f++) {
uint64_t mask = (1ULL << (f->end - f->start + 1)) - 1;
uint64_t v = (status >> f->start) & mask;
if (v > 0 || f->force) {
char fmt[32] = {0};
snprintf(fmt, 32, "%%s: %s\n", f->fmt ? f->fmt : "%Lu");
mce_snprintf(e->error_msg, fmt, f->name, v);
}
}
}
|
0 | rasdaemon-master | rasdaemon-master/ras-page-isolation.c | /*
* Copyright (c) Huawei Technologies Co., Ltd. 2020-2020. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <errno.h>
#include "ras-logger.h"
#include "ras-page-isolation.h"
#define PARSED_ENV_LEN 50
static const struct config threshold_units[] = {
{ "m", 1000 },
{ "k", 1000 },
{ "", 1 },
{}
};
static const struct config cycle_units[] = {
{ "d", 24 },
{ "h", 60 },
{ "m", 60 },
{ "s", 1 },
{}
};
static struct isolation threshold = {
.name = "PAGE_CE_THRESHOLD",
.units = threshold_units,
.env = "50",
.unit = "",
};
static struct isolation cycle = {
.name = "PAGE_CE_REFRESH_CYCLE",
.units = cycle_units,
.env = "24h",
.unit = "h",
};
static const char *kernel_offline[] = {
[OFFLINE_SOFT] = "/sys/devices/system/memory/soft_offline_page",
[OFFLINE_HARD] = "/sys/devices/system/memory/hard_offline_page",
[OFFLINE_SOFT_THEN_HARD] = "/sys/devices/system/memory/soft_offline_page",
};
static const struct config offline_choice[] = {
{ "off", OFFLINE_OFF },
{ "account", OFFLINE_ACCOUNT },
{ "soft", OFFLINE_SOFT },
{ "hard", OFFLINE_HARD },
{ "soft-then-hard", OFFLINE_SOFT_THEN_HARD },
{}
};
static const char *page_state[] = {
[PAGE_ONLINE] = "online",
[PAGE_OFFLINE] = "offlined",
[PAGE_OFFLINE_FAILED] = "offline-failed",
};
static enum otype offline = OFFLINE_SOFT;
static struct rb_root page_records;
static void page_offline_init(void)
{
const char *env = "PAGE_CE_ACTION";
char *choice = getenv(env);
const struct config *c = NULL;
int matched = 0;
if (choice) {
for (c = offline_choice; c->name; c++) {
if (!strcasecmp(choice, c->name)) {
offline = c->val;
matched = 1;
break;
}
}
}
if (!matched)
log(TERM, LOG_INFO, "Improper %s, set to default soft\n", env);
if (offline > OFFLINE_ACCOUNT && access(kernel_offline[offline], W_OK)) {
log(TERM, LOG_INFO, "Kernel does not support page offline interface\n");
offline = OFFLINE_ACCOUNT;
}
log(TERM, LOG_INFO, "Page offline choice on Corrected Errors is %s\n",
offline_choice[offline].name);
}
static void parse_isolation_env(struct isolation *config)
{
char *env = getenv(config->name);
char *unit = NULL;
const struct config *units = NULL;
int i, no_unit;
int valid = 0;
int unit_matched = 0;
unsigned long value, tmp;
/* check if env is valid */
if (env && strlen(env)) {
/* All the character before unit must be digit */
for (i = 0; i < strlen(env) - 1; i++) {
if (!isdigit(env[i]))
goto parse;
}
if (sscanf(env, "%lu", &value) < 1 || !value)
goto parse;
/* check if the unit is valid */
unit = env + strlen(env) - 1;
/* no unit, all the character are value character */
if (isdigit(*unit)) {
valid = 1;
no_unit = 1;
goto parse;
}
for (units = config->units; units->name; units++) {
/* value character and unit character are both valid */
if (!strcasecmp(unit, units->name)) {
valid = 1;
no_unit = 0;
break;
}
}
}
parse:
/* if invalid, use default env */
if (valid) {
config->env = env;
if (!no_unit)
config->unit = unit;
} else {
log(TERM, LOG_INFO, "Improper %s, set to default %s.\n",
config->name, config->env);
}
/* if env value string is greater than ulong_max, truncate the last digit */
sscanf(config->env, "%lu", &value);
for (units = config->units; units->name; units++) {
if (!strcasecmp(config->unit, units->name))
unit_matched = 1;
if (unit_matched) {
tmp = value;
value *= units->val;
if (tmp != 0 && value / tmp != units->val)
config->overflow = true;
}
}
config->val = value;
/* In order to output value and unit perfectly */
config->unit = no_unit ? config->unit : "";
}
static void parse_env_string(struct isolation *config, char *str, unsigned int size)
{
int i;
if (config->overflow) {
/* when overflow, use basic unit */
for (i = 0; config->units[i].name; i++)
;
snprintf(str, size, "%lu%s", config->val, config->units[i - 1].name);
log(TERM, LOG_INFO, "%s is set overflow(%s), truncate it\n",
config->name, config->env);
} else {
snprintf(str, size, "%s%s", config->env, config->unit);
}
}
static void page_isolation_init(void)
{
char threshold_string[PARSED_ENV_LEN];
char cycle_string[PARSED_ENV_LEN];
/**
* It's unnecessary to parse threshold configuration when offline
* choice is off.
*/
if (offline == OFFLINE_OFF)
return;
parse_isolation_env(&threshold);
parse_isolation_env(&cycle);
parse_env_string(&threshold, threshold_string, sizeof(threshold_string));
parse_env_string(&cycle, cycle_string, sizeof(cycle_string));
log(TERM, LOG_INFO, "Threshold of memory Corrected Errors is %s / %s\n",
threshold_string, cycle_string);
}
void ras_page_account_init(void)
{
page_offline_init();
page_isolation_init();
}
static int do_page_offline(unsigned long long addr, enum otype type)
{
int fd, rc;
char buf[20];
fd = open(kernel_offline[type], O_WRONLY);
if (fd == -1) {
log(TERM, LOG_ERR, "[%s]:open file: %s failed\n", __func__, kernel_offline[type]);
return -1;
}
sprintf(buf, "%#llx", addr);
rc = write(fd, buf, strlen(buf));
if (rc < 0) {
log(TERM, LOG_ERR, "page offline addr(%s) by %s failed, errno:%d\n", buf, kernel_offline[type], errno);
}
close(fd);
return rc;
}
static void page_offline(struct page_record *pr)
{
unsigned long long addr = pr->addr;
int ret;
/* Offlining page is not required */
if (offline <= OFFLINE_ACCOUNT) {
log(TERM, LOG_INFO, "PAGE_CE_ACTION=%s, ignore to offline page at %#llx\n",
offline_choice[offline].name, addr);
return;
}
/* Ignore offlined pages */
if (pr->offlined == PAGE_OFFLINE) {
log(TERM, LOG_INFO, "page at %#llx is already offlined, ignore\n", addr);
return;
}
/* Time to silence this noisy page */
if (offline == OFFLINE_SOFT_THEN_HARD) {
ret = do_page_offline(addr, OFFLINE_SOFT);
if (ret < 0)
ret = do_page_offline(addr, OFFLINE_HARD);
} else {
ret = do_page_offline(addr, offline);
}
pr->offlined = ret < 0 ? PAGE_OFFLINE_FAILED : PAGE_OFFLINE;
log(TERM, LOG_INFO, "Result of offlining page at %#llx: %s\n",
addr, page_state[pr->offlined]);
}
static void page_record(struct page_record *pr, unsigned int count, time_t time)
{
unsigned long period = time - pr->start;
unsigned long tolerate;
if (period >= cycle.val) {
/**
* Since we don't refresh automatically, it is possible that the period
* between two occurences will be longer than the pre-configured refresh cycle.
* In this case, we tolerate the frequency of the whole period up to
* the pre-configured threshold.
*/
tolerate = (period / (double)cycle.val) * threshold.val;
pr->count -= (tolerate > pr->count) ? pr->count : tolerate;
pr->start = time;
pr->excess = 0;
}
pr->count += count;
if (pr->count >= threshold.val) {
log(TERM, LOG_INFO, "Corrected Errors at %#llx exceeded threshold\n", pr->addr);
/**
* Backup ce count of current cycle to enable next round, which actually
* should never happen if we can disable overflow completely in the same
* time unit (but sadly we can't).
*/
pr->excess += pr->count;
pr->count = 0;
page_offline(pr);
}
}
static struct page_record *page_lookup_insert(unsigned long long addr)
{
struct rb_node **entry = &page_records.rb_node;
struct rb_node *parent = NULL;
struct page_record *pr = NULL, *find = NULL;
while (*entry) {
parent = *entry;
pr = rb_entry(parent, struct page_record, entry);
if (addr == pr->addr) {
return pr;
} else if (addr < pr->addr) {
entry = &(*entry)->rb_left;
} else {
entry = &(*entry)->rb_right;
}
}
find = calloc(1, sizeof(struct page_record));
if (!find) {
log(TERM, LOG_ERR, "No memory for page records\n");
return NULL;
}
find->addr = addr;
rb_link_node(&find->entry, parent, entry);
rb_insert_color(&find->entry, &page_records);
return find;
}
void ras_record_page_error(unsigned long long addr, unsigned int count, time_t time)
{
struct page_record *pr = NULL;
if (offline == OFFLINE_OFF)
return;
pr = page_lookup_insert(addr & PAGE_MASK);
if (pr) {
if (!pr->start)
pr->start = time;
page_record(pr, count, time);
}
}
|
0 | rasdaemon-master | rasdaemon-master/non-standard-yitian.c | /*
* Copyright (C) 2023 Alibaba Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-report.h"
#include "ras-non-standard-handler.h"
#include "non-standard-yitian.h"
static const char * const yitian_ddr_payload_err_reg_name[] = {
"Error Type:",
"Error SubType:",
"Error Instance:",
"ECCCFG0:",
"ECCCFG1:",
"ECCSTAT:",
"ECCERRCNT:",
"ECCCADDR0:",
"ECCCADDR1:",
"ECCCSYN0:",
"ECCCSYN1:",
"ECCCSYN2:",
"ECCUADDR0:",
"ECCUADDR1:",
"ECCUSYN0:",
"ECCUSYN1:",
"ECCUSYN2:",
"ECCBITMASK0:",
"ECCBITMASK1:",
"ECCBITMASK2:",
"ADVECCSTAT:",
"ECCAPSTAT:",
"ECCCDATA0:",
"ECCCDATA1:",
"ECCUDATA0:",
"ECCUDATA1:",
"ECCSYMBOL:",
"ECCERRCNTCTL:",
"ECCERRCNTSTAT:",
"ECCERRCNT0:",
"ECCERRCNT1:",
"RESERVED0:",
"RESERVED1:",
"RESERVED2:",
};
struct yitian_ras_type_info {
int id;
const char *name;
const char * const *sub;
int sub_num;
};
static const struct yitian_ras_type_info yitian_payload_error_type[] = {
{
.id = YITIAN_RAS_TYPE_DDR,
.name = "DDR",
},
{
}
};
#ifdef HAVE_SQLITE3
static const struct db_fields yitian_ddr_payload_fields[] = {
{ .name = "id", .type = "INTEGER PRIMARY KEY" },
{ .name = "timestamp", .type = "TEXT" },
{ .name = "address", .type = "INTEGER" },
{ .name = "regs_dump", .type = "TEXT" },
};
static const struct db_table_descriptor yitian_ddr_payload_section_tab = {
.name = "yitian_ddr_reg_dump_event",
.fields = yitian_ddr_payload_fields,
.num_fields = ARRAY_SIZE(yitian_ddr_payload_fields),
};
int record_yitian_ddr_reg_dump_event(struct ras_ns_ev_decoder *ev_decoder,
struct ras_yitian_ddr_payload_event *ev)
{
int rc;
struct sqlite3_stmt *stmt = ev_decoder->stmt_dec_record;
log(TERM, LOG_INFO, "yitian_ddr_reg_dump_event store: %p\n", stmt);
sqlite3_bind_text(stmt, 1, ev->timestamp, -1, NULL);
sqlite3_bind_int64(stmt, 2, ev->address);
sqlite3_bind_text(stmt, 3, ev->reg_msg, -1, NULL);
rc = sqlite3_step(stmt);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed to do yitian_ddr_reg_dump_event step on sqlite: error = %d\n", rc);
rc = sqlite3_reset(stmt);
if (rc != SQLITE_OK && rc != SQLITE_DONE)
log(TERM, LOG_ERR,
"Failed reset yitian_ddr_reg_dump_event on sqlite: error = %d\n", rc);
log(TERM, LOG_INFO, "register inserted at db\n");
return rc;
}
#endif
static const char *oem_type_name(const struct yitian_ras_type_info *info,
uint8_t type_id)
{
const struct yitian_ras_type_info *type = &info[0];
for (; type->name; type++) {
if (type->id != type_id)
continue;
return type->name;
}
return "unknown";
}
static const char *oem_subtype_name(const struct yitian_ras_type_info *info,
uint8_t type_id, uint8_t sub_type_id)
{
const struct yitian_ras_type_info *type = &info[0];
for (; type->name; type++) {
const char * const *submodule = type->sub;
if (type->id != type_id)
continue;
if (!type->sub)
return type->name;
if (sub_type_id >= type->sub_num)
return "unknown";
return submodule[sub_type_id];
}
return "unknown";
}
void decode_yitian_ddr_payload_err_regs(struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
const struct yitian_ddr_payload_type_sec *err,
struct ras_events *ras)
{
char buf[1024];
char *p = buf;
char *end = buf + 1024;
int i = 0;
const struct yitian_payload_header *header = &err->header;
uint32_t *pstart;
time_t now;
struct tm *tm;
struct ras_yitian_ddr_payload_event ev;
const char *type_str = oem_type_name(yitian_payload_error_type,
header->type);
const char *subtype_str = oem_subtype_name(yitian_payload_error_type,
header->type, header->subtype);
now = time(NULL);
tm = localtime(&now);
if (tm)
strftime(ev.timestamp, sizeof(ev.timestamp),
"%Y-%m-%d %H:%M:%S %z", tm);
//display error type
p += snprintf(p, end - p, " %s", yitian_ddr_payload_err_reg_name[i++]);
p += snprintf(p, end - p, " %s,", type_str);
//display error subtype
p += snprintf(p, end - p, " %s", yitian_ddr_payload_err_reg_name[i++]);
p += snprintf(p, end - p, " %s,", subtype_str);
//display error instance
p += snprintf(p, end - p, " %s", yitian_ddr_payload_err_reg_name[i++]);
p += snprintf(p, end - p, " 0x%x,", header->instance);
//display reg dump
for (pstart = (uint32_t *)&err->ecccfg0; (void *)pstart < (void *)(err + 1); pstart += 1) {
p += snprintf(p, end - p, " %s", yitian_ddr_payload_err_reg_name[i++]);
p += snprintf(p, end - p, " 0x%x ", *pstart);
}
if (p > buf && p < end) {
p--;
*p = '\0';
}
ev.reg_msg = malloc(p - buf + 1);
memcpy(ev.reg_msg, buf, p - buf + 1);
ev.address = 0;
i = 0;
p = NULL;
end = NULL;
trace_seq_printf(s, "%s\n", buf);
#ifdef HAVE_SQLITE3
record_yitian_ddr_reg_dump_event(ev_decoder, &ev);
#endif
}
static int add_yitian_common_table(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder)
{
#ifdef HAVE_SQLITE3
if (ras->record_events && !ev_decoder->stmt_dec_record) {
if (ras_mc_add_vendor_table(ras, &ev_decoder->stmt_dec_record,
&yitian_ddr_payload_section_tab) != SQLITE_OK) {
log(TERM, LOG_WARNING,
"Failed to create sql yitian_ddr_payload_section_tab\n");
return -1;
}
}
#endif
return 0;
}
/* error data decoding functions */
static int decode_yitian710_ns_error(struct ras_events *ras,
struct ras_ns_ev_decoder *ev_decoder,
struct trace_seq *s,
struct ras_non_standard_event *event)
{
int payload_type = event->error[0];
if (payload_type == YITIAN_RAS_TYPE_DDR) {
const struct yitian_ddr_payload_type_sec *err =
(struct yitian_ddr_payload_type_sec *)event->error;
decode_yitian_ddr_payload_err_regs(ev_decoder, s, err, ras);
} else {
trace_seq_printf(s, "%s: wrong payload type\n", __func__);
return -1;
}
return 0;
}
struct ras_ns_ev_decoder yitian_ns_oem_decoder[] = {
{
.sec_type = "a6980811-16ea-4e4d-b936-fb00a23ff29c",
.add_table = add_yitian_common_table,
.decode = decode_yitian710_ns_error,
},
};
static void __attribute__((constructor)) yitian_ns_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(yitian_ns_oem_decoder); i++)
register_ns_ev_decoder(&yitian_ns_oem_decoder[i]);
}
|
0 | rasdaemon-master | rasdaemon-master/ras-devlink-handler.c | /*
* Copyright (C) 2019 Cong Wang <xiyou.wangcong@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define _GNU_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <traceevent/kbuffer.h>
#include "ras-devlink-handler.h"
#include "ras-record.h"
#include "ras-logger.h"
#include "ras-report.h"
int ras_net_xmit_timeout_handler(struct trace_seq *s,
struct tep_record *record,
struct tep_event *event, void *context)
{
unsigned long long val;
int len;
struct ras_events *ras = context;
time_t now;
struct tm *tm;
struct devlink_event ev;
if (ras->use_uptime)
now = record->ts / user_hz + ras->uptime_diff;
else
now = time(NULL);
tm = localtime(&now);
if (tm)
strftime(ev.timestamp, sizeof(ev.timestamp),
"%Y-%m-%d %H:%M:%S %z", tm);
trace_seq_printf(s, "%s ", ev.timestamp);
ev.bus_name = "";
ev.reporter_name = "";
ev.dev_name = tep_get_field_raw(s, event, "name",
record, &len, 1);
if (!ev.dev_name)
return -1;
ev.driver_name = tep_get_field_raw(s, event, "driver",
record, &len, 1);
if (!ev.driver_name)
return -1;
if (tep_get_field_val(s, event, "queue_index", record, &val, 1) < 0)
return -1;
if (asprintf(&ev.msg, "TX timeout on queue: %d\n", (int)val) < 0)
return -1;
/* Insert data into the SGBD */
#ifdef HAVE_SQLITE3
ras_store_devlink_event(ras, &ev);
#endif
#ifdef HAVE_ABRT_REPORT
/* Report event to ABRT */
ras_report_devlink_event(ras, &ev);
#endif
free(ev.msg);
return 0;
}
int ras_devlink_event_handler(struct trace_seq *s,
struct tep_record *record,
struct tep_event *event, void *context)
{
int len;
struct ras_events *ras = context;
time_t now;
struct tm *tm;
struct devlink_event ev;
if (ras->filters[DEVLINK_EVENT] &&
tep_filter_match(ras->filters[DEVLINK_EVENT], record) == FILTER_MATCH)
return 0;
/*
* Newer kernels (3.10-rc1 or upper) provide an uptime clock.
* On previous kernels, the way to properly generate an event would
* be to inject a fake one, measure its timestamp and diff it against
* gettimeofday. We won't do it here. Instead, let's use uptime,
* falling-back to the event report's time, if "uptime" clock is
* not available (legacy kernels).
*/
if (ras->use_uptime)
now = record->ts / user_hz + ras->uptime_diff;
else
now = time(NULL);
tm = localtime(&now);
if (tm)
strftime(ev.timestamp, sizeof(ev.timestamp),
"%Y-%m-%d %H:%M:%S %z", tm);
trace_seq_printf(s, "%s ", ev.timestamp);
ev.bus_name = tep_get_field_raw(s, event, "bus_name",
record, &len, 1);
if (!ev.bus_name)
return -1;
ev.dev_name = tep_get_field_raw(s, event, "dev_name",
record, &len, 1);
if (!ev.dev_name)
return -1;
ev.driver_name = tep_get_field_raw(s, event, "driver_name",
record, &len, 1);
if (!ev.driver_name)
return -1;
ev.reporter_name = tep_get_field_raw(s, event, "reporter_name",
record, &len, 1);
if (!ev.reporter_name)
return -1;
ev.msg = tep_get_field_raw(s, event, "msg", record, &len, 1);
if (!ev.msg)
return -1;
/* Insert data into the SGBD */
#ifdef HAVE_SQLITE3
ras_store_devlink_event(ras, &ev);
#endif
#ifdef HAVE_ABRT_REPORT
/* Report event to ABRT */
ras_report_devlink_event(ras, &ev);
#endif
return 0;
}
|
0 | rasdaemon-master | rasdaemon-master/mce-intel-skylake-xeon.c | /*
* The code below came from Tony Luck's mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <stdio.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
/* See IA32 SDM Vol3B Table 16-27 */
static char *pcu_1[] = {
[0x00] = "No Error",
[0x0d] = "MCA_DMI_TRAINING_TIMEOUT",
[0x0f] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT",
[0x10] = "MCA_MORE_THAN_ONE_LT_AGENT",
[0x1e] = "MCA_BIOS_RST_CPL_INVALID_SEQ",
[0x1f] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG",
[0x25] = "MCA_MESSAGE_CHANNEL_TIMEOUT",
[0x27] = "MCA_MSGCH_PMREQ_CMP_TIMEOUT",
[0x30] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT",
[0x31] = "MCA_PKGC_INVALID_RSP_PCH",
[0x33] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN",
[0x34] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP",
[0x38] = "MCA_PKGC_WATCHDOG_HANG_C3_UP_SF",
[0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE",
[0x41] = "MCA_SVID_COMMAND_TIMEOUT",
[0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE",
[0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR",
[0x44] = "MCA_SVID_CRITICAL_VR_FAILED",
[0x45] = "MCA_SVID_SA_ITD_ERROR",
[0x46] = "MCA_SVID_READ_REG_FAILED",
[0x47] = "MCA_SVID_WRITE_REG_FAILED",
[0x48] = "MCA_SVID_PKGC_INIT_FAILED",
[0x49] = "MCA_SVID_PKGC_CONFIG_FAILED",
[0x4a] = "MCA_SVID_PKGC_REQUEST_FAILED",
[0x4b] = "MCA_SVID_IMON_REQUEST_FAILED",
[0x4c] = "MCA_SVID_ALERT_REQUEST_FAILED",
[0x4d] = "MCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERROR",
[0x4e] = "MCA_SVID_UNEXPECTED_MCP_VR_DETECTED",
[0x51] = "MCA_FIVR_CATAS_OVERVOL_FAULT",
[0x52] = "MCA_FIVR_CATAS_OVERCUR_FAULT",
[0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SLAVE",
[0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MASTER",
[0x5a] = "MCA_WATCHDOG_TIMEOUT_PKGS_MASTER",
[0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT",
[0x63] = "MCA_PKGS_INVALID_REQ_PCH",
[0x64] = "MCA_PKGS_INVALID_REQ_INTERNAL",
[0x65] = "MCA_PKGS_INVALID_RSP_INTERNAL",
[0x6b] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT",
[0x81] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT",
};
static struct field pcu_mc4[] = {
FIELD(24, pcu_1),
{}
};
/* See IA32 SDM Vol3B Table 16-28 */
static char *upi[] = {
[0x00] = "UC Phy Initialization Failure",
[0x01] = "UC Phy detected drift buffer alarm",
[0x02] = "UC Phy detected latency buffer rollover",
[0x10] = "UC LL Rx detected CRC error: unsuccessful LLR: entered abort state",
[0x11] = "UC LL Rx unsupported or undefined packet",
[0x12] = "UC LL or Phy control error",
[0x13] = "UC LL Rx parameter exchange exception",
[0x1F] = "UC LL detected control error from the link-mesh interface",
[0x20] = "COR Phy initialization abort",
[0x21] = "COR Phy reset",
[0x22] = "COR Phy lane failure, recovery in x8 width",
[0x23] = "COR Phy L0c error corrected without Phy reset",
[0x24] = "COR Phy L0c error triggering Phy Reset",
[0x25] = "COR Phy L0p exit error corrected with Phy reset",
[0x30] = "COR LL Rx detected CRC error - successful LLR without Phy Reinit",
[0x31] = "COR LL Rx detected CRC error - successful LLR with Phy Reinit",
};
static struct field upi_mc[] = {
FIELD(16, upi),
{}
};
/* These apply to MSCOD 0x12 "UC LL or Phy control error" */
static struct field upi_0x12[] = {
SBITFIELD(22, "Phy Control Error"),
SBITFIELD(23, "Unexpected Retry.Ack flit"),
SBITFIELD(24, "Unexpected Retry.Req flit"),
SBITFIELD(25, "RF parity error"),
SBITFIELD(26, "Routeback Table error"),
SBITFIELD(27, "unexpected Tx Protocol flit (EOP, Header or Data)"),
SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"),
SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"),
SBITFIELD(30, "Link Layer reset initiated while protocol traffic not idle"),
SBITFIELD(31, "Link Layer Tx Parity Error"),
{}
};
/* See IA32 SDM Vol3B Table 16-29 */
static struct field mc_bits[] = {
SBITFIELD(16, "Address parity error"),
SBITFIELD(17, "HA write data parity error"),
SBITFIELD(18, "HA write byte enable parity error"),
SBITFIELD(19, "Corrected patrol scrub error"),
SBITFIELD(20, "Uncorrected patrol scrub error"),
SBITFIELD(21, "Corrected spare error"),
SBITFIELD(22, "Uncorrected spare error"),
SBITFIELD(23, "Any HA read error"),
SBITFIELD(24, "WDB read parity error"),
SBITFIELD(25, "DDR4 command address parity error"),
SBITFIELD(26, "Uncorrected address parity error"),
{}
};
static char *mc_0x8xx[] = {
[0x0] = "Unrecognized request type",
[0x1] = "Read response to an invalid scoreboard entry",
[0x2] = "Unexpected read response",
[0x3] = "DDR4 completion to an invalid scoreboard entry",
[0x4] = "Completion to an invalid scoreboard entry",
[0x5] = "Completion FIFO overflow",
[0x6] = "Correctable parity error",
[0x7] = "Uncorrectable error",
[0x8] = "Interrupt received while outstanding interrupt was not ACKed",
[0x9] = "ERID FIFO overflow",
[0xa] = "Error on Write credits",
[0xb] = "Error on Read credits",
[0xc] = "Scheduler error",
[0xd] = "Error event",
};
static struct field memctrl_mc13[] = {
FIELD(16, mc_0x8xx),
{}
};
/* See IA32 SDM Vol3B Table 16-30 */
static struct field m2m[] = {
SBITFIELD(16, "MscodDataRdErr"),
SBITFIELD(17, "Reserved"),
SBITFIELD(18, "MscodPtlWrErr"),
SBITFIELD(19, "MscodFullWrErr"),
SBITFIELD(20, "MscodBgfErr"),
SBITFIELD(21, "MscodTimeout"),
SBITFIELD(22, "MscodParErr"),
SBITFIELD(23, "MscodBucket1Err"),
{}
};
void skylake_s_decode_model(struct ras_events *ras, struct mce_event *e)
{
uint64_t status = e->status;
uint32_t mca = status & 0xffff;
unsigned int rank0 = -1, rank1 = -1, chan;
switch (e->bank) {
case 4:
switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) {
case 0x402: case 0x403:
mce_snprintf(e->mcastatus_msg, "Internal errors ");
break;
case 0x406:
mce_snprintf(e->mcastatus_msg, "Intel TXT errors ");
break;
case 0x407:
mce_snprintf(e->mcastatus_msg, "Other UBOX Internal errors ");
break;
}
if (EXTRACT(status, 16, 19))
mce_snprintf(e->mcastatus_msg, "PCU internal error ");
decode_bitfield(e, status, pcu_mc4);
break;
case 5:
case 12:
case 19:
mce_snprintf(e->mcastatus_msg, "UPI: ");
decode_bitfield(e, status, upi_mc);
if (EXTRACT(status, 16, 21) == 0x12)
decode_bitfield(e, status, upi_0x12);
break;
case 7: case 8:
mce_snprintf(e->mcastatus_msg, "M2M: ");
decode_bitfield(e, status, m2m);
break;
case 13: case 14: case 15:
case 16: case 17: case 18:
mce_snprintf(e->mcastatus_msg, "MemCtrl: ");
if (EXTRACT(status, 27, 27))
decode_bitfield(e, status, memctrl_mc13);
else
decode_bitfield(e, status, mc_bits);
break;
}
/*
* Memory error specific code. Returns if the error is not a MC one
*/
/* Check if the error is at the memory controller */
if ((mca >> 7) != 1)
return;
/* Ignore unless this is an corrected extended error from an iMC bank */
if (e->bank < 13 || e->bank > 18 || (status & MCI_STATUS_UC) ||
!test_prefix(7, status & 0xefff))
return;
/*
* Parse the reported channel and ranks
*/
chan = EXTRACT(status, 0, 3);
if (chan == 0xf)
return;
mce_snprintf(e->mc_location, "memory_channel=%d", chan);
if (EXTRACT(e->misc, 62, 62)) {
rank0 = EXTRACT(e->misc, 46, 50);
if (EXTRACT(e->misc, 63, 63))
rank1 = EXTRACT(e->misc, 51, 55);
}
/*
* FIXME: The conversion from rank to dimm requires to parse the
* DMI tables and call failrank2dimm().
*/
if (rank0 != -1 && rank1 != -1)
mce_snprintf(e->mc_location, "ranks=%d and %d",
rank0, rank1);
else if (rank0 != -1)
mce_snprintf(e->mc_location, "rank=%d", rank0);
}
|
0 | rasdaemon-master | rasdaemon-master/mce-amd-k8.c | /*
* Copyright (C) 2013 Mauro Carvalho Chehab <mchehab+redhat@kernel.org>
*
* The code below were adapted from Andi Kleen/Intel/SuSe mcelog code,
* released under GNU Public General License, v.2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdio.h>
#include <string.h>
#include "ras-mce-handler.h"
#include "bitfield.h"
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
#define K8_MCE_THRESHOLD_TOP (K8_MCE_THRESHOLD_BASE + 6 * 9)
#define K8_MCELOG_THRESHOLD_DRAM_ECC (4 * 9 + 0)
#define K8_MCELOG_THRESHOLD_LINK (4 * 9 + 1)
#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
static const char *k8bank[] = {
"data cache",
"instruction cache",
"bus unit",
"load/store unit",
"northbridge",
"fixed-issue reoder"
};
static const char *k8threshold[] = {
[0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknown threshold counter",
[K8_MCELOG_THRESHOLD_DRAM_ECC] = "MC4_MISC0 DRAM threshold",
[K8_MCELOG_THRESHOLD_LINK] = "MC4_MISC1 Link threshold",
[K8_MCELOG_THRESHOLD_L3_CACHE] = "MC4_MISC2 L3 Cache threshold",
[K8_MCELOG_THRESHOLD_FBDIMM] = "MC4_MISC3 FBDIMM threshold",
[K8_MCELOG_THRESHOLD_FBDIMM + 1 ...
K8_MCE_THRESHOLD_TOP - K8_MCE_THRESHOLD_BASE - 1] =
"Unknown threshold counter",
};
static const char *transaction[] = {
"instruction", "data", "generic", "reserved"
};
static const char *cachelevel[] = {
"0", "1", "2", "generic"
};
static const char *memtrans[] = {
"generic error", "generic read", "generic write", "data read",
"data write", "instruction fetch", "prefetch", "evict", "snoop",
"?", "?", "?", "?", "?", "?", "?"
};
static const char *partproc[] = {
"local node origin", "local node response",
"local node observed", "generic participation"
};
static const char *timeout[] = {
"request didn't time out",
"request timed out"
};
static const char *memoryio[] = {
"memory", "res.", "i/o", "generic"
};
static const char *nbextendederr[] = {
"RAM ECC error",
"CRC error",
"Sync error",
"Master abort",
"Target abort",
"GART error",
"RMW error",
"Watchdog error",
"RAM Chipkill ECC error",
"DEV Error",
"Link Data Error",
"Link Protocol Error",
"NB Array Error",
"DRAM Parity Error",
"Link Retry",
"Tablew Walk Data Error",
"L3 Cache Data Error",
"L3 Cache Tag Error",
"L3 Cache LRU Error"
};
static const char *highbits[32] = {
[31] = "valid",
[30] = "error overflow (multiple errors)",
[29] = "error uncorrected",
[28] = "error enable",
[27] = "misc error valid",
[26] = "error address valid",
[25] = "processor context corrupt",
[24] = "res24",
[23] = "res23",
/* 22-15 ecc syndrome bits */
[14] = "corrected ecc error",
[13] = "uncorrected ecc error",
[12] = "res12",
[11] = "L3 subcache in error bit 1",
[10] = "L3 subcache in error bit 0",
[9] = "sublink or DRAM channel",
[8] = "error found by scrub",
/* 7-4 ht link number of error */
[3] = "err cpu3",
[2] = "err cpu2",
[1] = "err cpu1",
[0] = "err cpu0",
};
#define IGNORE_HIGHBITS ((1 << 31) || (1 << 28) || (1 << 26))
static void decode_k8_generic_errcode(struct mce_event *e)
{
char tmp_buf[4092];
unsigned short errcode = e->status & 0xffff;
int n;
/* Translate the highest bits */
n = bitfield_msg(tmp_buf, sizeof(tmp_buf), highbits, 32,
IGNORE_HIGHBITS, 32, e->status);
if (n)
mce_snprintf(e->error_msg, "(%s) ", tmp_buf);
if ((errcode & 0xfff0) == 0x0010)
mce_snprintf(e->error_msg,
"LB error '%s transaction, level %s'",
transaction[(errcode >> 2) & 3],
cachelevel[errcode & 3]);
else if ((errcode & 0xff00) == 0x0100)
mce_snprintf(e->error_msg,
"memory/cache error '%s mem transaction, %s transaction, level %s'",
memtrans[(errcode >> 4) & 0xf],
transaction[(errcode >> 2) & 3],
cachelevel[errcode & 3]);
else if ((errcode & 0xf800) == 0x0800)
mce_snprintf(e->error_msg,
"bus error '%s, %s: %s mem transaction, %s access, level %s'",
partproc[(errcode >> 9) & 0x3],
timeout[(errcode >> 8) & 1],
memtrans[(errcode >> 4) & 0xf],
memoryio[(errcode >> 2) & 0x3],
cachelevel[(errcode & 0x3)]);
}
static void decode_k8_dc_mc(struct mce_event *e)
{
unsigned short exterrcode = (e->status >> 16) & 0x0f;
unsigned short errcode = e->status & 0xffff;
if (e->status & (3ULL << 45)) {
mce_snprintf(e->error_msg,
"Data cache ECC error (syndrome %x)",
(uint32_t)(e->status >> 47) & 0xff);
if (e->status & (1ULL << 40))
mce_snprintf(e->error_msg, "found by scrubber");
}
if ((errcode & 0xfff0) == 0x0010)
mce_snprintf(e->error_msg,
"TLB parity error in %s array",
(exterrcode == 0) ? "physical" : "virtual");
}
static void decode_k8_ic_mc(struct mce_event *e)
{
unsigned short exterrcode = (e->status >> 16) & 0x0f;
unsigned short errcode = e->status & 0xffff;
if (e->status & (3ULL << 45))
mce_snprintf(e->error_msg, "Instruction cache ECC error");
if ((errcode & 0xfff0) == 0x0010)
mce_snprintf(e->error_msg, "TLB parity error in %s array",
(exterrcode == 0) ? "physical" : "virtual");
}
static void decode_k8_bu_mc(struct mce_event *e)
{
unsigned short exterrcode = (e->status >> 16) & 0x0f;
if (e->status & (3ULL << 45))
mce_snprintf(e->error_msg, "L2 cache ECC error");
mce_snprintf(e->error_msg, "%s array error",
!exterrcode ? "Bus or cache" : "Cache tag");
}
static void decode_k8_nb_mc(struct mce_event *e, unsigned int *memerr)
{
unsigned short exterrcode = (e->status >> 16) & 0x0f;
mce_snprintf(e->error_msg, "Northbridge %s", nbextendederr[exterrcode]);
switch (exterrcode) {
case 0:
*memerr = 1;
mce_snprintf(e->error_msg, "ECC syndrome = %x",
(uint32_t)(e->status >> 47) & 0xff);
break;
case 8:
*memerr = 1;
mce_snprintf(e->error_msg, "Chipkill ECC syndrome = %x",
(uint32_t)((((e->status >> 24) & 0xff) << 8)
| ((e->status >> 47) & 0xff)));
break;
case 1:
case 2:
case 3:
case 4:
case 6:
mce_snprintf(e->error_msg, "link number = %x",
(uint32_t)(e->status >> 36) & 0xf);
break;
}
}
static void decode_k8_threashold(struct mce_event *e)
{
if (e->misc & MCI_THRESHOLD_OVER)
mce_snprintf(e->error_msg, "Threshold error count overflow");
}
static void bank_name(struct mce_event *e)
{
const char *s;
if (e->bank < ARRAY_SIZE(k8bank))
s = k8bank[e->bank];
else if (e->bank >= K8_MCE_THRESHOLD_BASE &&
e->bank < K8_MCE_THRESHOLD_TOP)
s = k8threshold[e->bank - K8_MCE_THRESHOLD_BASE];
else
return; /* Use the generic parser for bank */
mce_snprintf(e->bank_name, "%s (bank=%d)", s, e->bank);
}
int parse_amd_k8_event(struct ras_events *ras, struct mce_event *e)
{
unsigned int ismemerr = 0;
/* Don't handle GART errors */
if (e->bank == 4) {
unsigned short exterrcode = (e->status >> 16) & 0x0f;
if (exterrcode == 5 && (e->status & (1ULL << 61))) {
return -1;
}
}
bank_name(e);
switch (e->bank) {
case 0:
decode_k8_dc_mc(e);
decode_k8_generic_errcode(e);
break;
case 1:
decode_k8_ic_mc(e);
decode_k8_generic_errcode(e);
break;
case 2:
decode_k8_bu_mc(e);
decode_k8_generic_errcode(e);
break;
case 3: /* LS */
decode_k8_generic_errcode(e);
break;
case 4:
decode_k8_nb_mc(e, &ismemerr);
decode_k8_generic_errcode(e);
break;
case 5: /* FR */
decode_k8_generic_errcode(e);
break;
case K8_MCE_THRESHOLD_BASE ... K8_MCE_THRESHOLD_TOP:
decode_k8_threashold(e);
break;
default:
strcpy(e->error_msg, "Don't know how to decode this bank");
}
/* IP doesn't matter on memory errors */
if (ismemerr)
e->ip = 0;
return 0;
}
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