Source: http://dtsheet.com/doc/91309/ad-ad5663rbrmz-5
Timestamp: 2019-04-26 11:46:04+00:00

Document:
2.7 V to 5.5 V supply and are guaranteed monotonic by design.
The AD5623R/AD5643R/AD5663R have an on-chip reference.
devices can be operated from a single 2.7 V to 5.5 V supply.
The internal reference is turned on by writing to the DAC.
and provides software-selectable output loads while in powerdown mode.
makes it ideally suited to portable, battery-operated equipment.
enables rail-to-rail output swing to be achieved.
1. Dual 12-, 14-, and 16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
1.25 mW at 5 V.
5. 4.5 μs maximum settling time for the AD5623R.
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Temperature range: B grade = −40°C to +105°C.
Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064).
Interface inactive. All DACs active. DAC outputs unloaded.
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Temperature range: B grade = −40°C to +105°C, typical at +25°C.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground. Reference point for all circuitry on the part.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
a write sequence, the write is aborted.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
of the serial clock input.
a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
function. A typical INL vs. code plot is shown in Figure 5.
and the output amplifier. Zero-scale error is expressed in mV.
A plot of zero-scale error vs. temperature is shown in Figure 26.
in percent of full-scale range. A plot of full-scale error vs.
temperature is shown in Figure 25.
expressed as a percent of the full-scale range.
transition (0x7FFF to 0x8000). See Figure 38.
data bus, that is, from all 0s to all 1s and vice versa.
spectral density is shown in Figure 44.
kept at midscale. It is expressed in microvolts (μV).
which the output amplitude falls to 3 dB below the input.
measurement of the harmonics present on the DAC output.
It is measured in decibels (dB).
energy of the glitch is expressed in nanovolts-second (nV-s).
diagram of the DAC architecture.
Internal Reference Setup section for details.
reference, giving a full-scale output of 5 V. The internal reference associated with each part is available at the VREFOUT pin.
reference output and GND for reference stability.
N is the DAC resolution.
sink capabilities of the output amplifier can be seen in Figure 31.
the use of an external reference if the application requires it.
from a single 2.7 V to 5.5 V supply.
MICROWIRE interface standards, as well as with most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
in the mode of operation.
At this stage, the SYNC line can be kept low or be brought high.
can initiate the next write sequence.
16-, 14-, and 12-bit data-word.
on the 24th falling edge of SCLK.
24th falling edge, this acts as an interrupt to the write sequence.
change in the operating mode occurs (see Figure 54).
Table 13 for contents of the input shift register during powerdown/power-up operation.
CLR during power-on reset are ignored.
to the value held in the DAC register before power-down.
software reset mode of operation.
normally, with its normal power consumption of 250 μA at 5 V.
the output of the amplifier to a resistor network of known values.
resistor or left open-circuited (three-state) (see Figure 55).
setting the corresponding two bits (Bit DB1 and Bit DB0) to 1.
VDD = 3 V (see Figure 37).
used by the resistor strings.
registers are updated with the contents of the input register.
Access to the DAC registers is controlled by the LDAC pin.
LDAC pin. It effectively sees the LDAC pin as being pulled low.
the LDAC register setup command.
low or pulsed as shown in Figure 2.
how the state of the bit corresponds to the mode of operation.
register during the internal reference set-up command.
SCLK of the parts. The SYNC is driven from TFS0.
1ADDITIONAL PINS OMITTED FOR CLARITY.
the DAC. PC7 is taken high at the end of this procedure.
AD5643R/AD5663R and the 80C51/80L51 microcontroller.
of data. P3.3 is taken high following the completion of this cycle.
AD5643R/AD5663R and the 68HC11/68L11 microcontroller.
data line of the DAC.
falling clock edges occurring in the transmit cycle.
the AD5623R/AD5643R/AD5663R on the rising edge of the SK.
drawn from it. This corresponds to a 0.196 LSB error.
5 V supply required for the AD5663R.
a steady supply voltage for the AD5623R/AD5643R/ AD5663R.
where D represents the input code in decimal (0 to 65,535).
Figure 61. The circuit gives an output voltage range of ±5 V.
an AD820 or an OP295 as the output amplifier.
own area of the board.
always possible with a 2-layer board.

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