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Timestamp: 2019-04-22 04:56:08+00:00

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Collaborations: STMicroelectronics, Crolles, France; Infineon Technologies, Munich, Germany.
Collaborations: ISET Energia, Valle di Maddaloni, Italy; ENEA, Portici, Italy; University Paul Cezanne, Marseille, France.
A.1) A research activity was devoted to investigate the electrothermal effects in bipolar differential pairs subject to radical thermal feedback. It was experimentally found that a significant thermally-induced degradation of circuit characteristics may occur, eventually turning into the full disappearance of the linear amplifying region, which is replaced by a hysteresis behavior under voltage-controlled conditions. An analytical approach and a SPICE-based technique were developed to favor a reliable prediction of the distortion of the I-V curves, as well as to quantify the concurrent destabilizing action of electrothermal and impact-ionization effects and the beneficial influence of emitter ballasting resistors.
A.2) Another topic of interest concerns the analysis of the thermal behavior of AlGaN/GaN HEMTs, which might suffer from the low thermal conductivity of GaN. In particular, the investigation was focused on multifinger devices grown on SiC. Numerical simulations were performed by using a commercial software package enriched with an in-house tool developed to automatically draw the geometrically complex 3-D transistor structure and generate a smartly-refined mesh. This allowed determining the impact of the metallization pattern, as well as of various layout and technological choices concerning, e.g., the connection strategy of the individual source fingers and gate periphery. Accepted experimental techniques were also adopted to estimate the thermal resistance and determined the thermal impedance evolution in the time domain of the devices under test.
The research activity has been focused on the study and the design of improved power devices. Performance and modeling issues have been considered. Considered devices are vertical IGBT, Superjunction devices and lateral power devices for Smart Power applications. A.1) Reliability issues for vertical IGBT We show how lock-in thermography, that is the synchronous detection of temperature increase caused by current flow in an electron device, can be used as a reliable tool for failure analysis and localization of failures induced in power IGBTS during inductive load switch. The application of the technique is possible without any particular sample preparation and this makes the methodology attractive for the study of avalanche ruggedness of power devices A.2) Superjunction devices Aim of the research is the derivation of an analytical formulation for the Breakdown Voltage of balanced Superjunction power devices. The proposed solution takes into account the ionization integral without using the critical electric field approximation. A previously proposed exact solution if the electric field for the symmetrical SJ devices is used as a starting point for the analysis. The published models, with respect to the previous ones, provide more precise solutions in a wide range of design cases. Further extensions have been attempted for the case of lateral devices and for the case of non symmetrical, not balanced SJ devices. B) Testing of power devices Clamped and unclamped electrical switching tests on inductive loads have been used to this purpose. Contactless optical thermographic techniques have been used to characterize various power devices. Unclamped Inductive witching (UIS) is an extremely high stress test used to determine the maximum amount of avalanche energy a device can handle by forcing a charged unclamped inductor to discharge through the device under test. Generally, device ruggedness is referred to the amount of energy that can be absorbed prior to catastrophic device failure. Not only is it important to test these devices under UIS conditions, but it is also important to determine how to optimize devices for ruggedness. This can be accomplished only if the physics of failure mechanisms can be identified. C) Modeling of power devicesPower electronics is an expanding industry. Applications include: power conversion; power conditioning; and motion control. Power semiconductor characteristics include: efficient drive; fast switching; and high current. This research is focused on the development of power semiconductor models needed in circuit simulators for CAD which include: physics-based models for power semiconductors; models implemented into circuit simulators; extraction sequences to determine model parameters; and characterization procedures to verify model quality.
1) A novel approach to experimentally extract the bias-dependent base resistance in SiGe:C HBTs operated above BVCEO has been developed. The technique represents an extension of an approach available in the literature, and relies on simple preliminary parameter extraction procedures needed to account for self-heating, impact ionization, and high-injection effects in the transistor model. The avalanche-induced base resistance increase with collector voltage can be accurately monitored up to the occurrence of the pinch-in mechanism.
2) The influence of the (vertical and lateral) downscaling on the thermal behavior of SiGe:C HBTs has been examined by resorting to calibrated hydrodynamic simulations for the lowest frequency technological node, and to a deterministic solver of the Boltzmann Transport Equation relying on the spherical harmonics expansion of the distribution function for the more aggressively scaled devices. Among the various results, it was found that the sensitivity to temperature of both current gain and maximum cut-off frequency reduces with vertical scaling.
1) A non-intrusive approach to assess the shunt resistance of a chosen PV cell embedded in an installed string is proposed, which does not require preliminary evaluation of the parameters associated to the intrinsic diodes. The technique relies on the measurement of the current-voltage characteristic of the whole string while intentionally keeping the selected cell under ideally dark conditions. The shunt resistance is subsequently evaluated from the slope of the curve in the voltage range where the string exhibits a quasi-linear behavior.
2) A novel active bypass system for shaded solar panels has been developed, which is based on a bipolar transistor operated in saturation. This method allows a higher power production of the panel arrays compared to the traditional – and widespread – diode-based approach without a significant increase in circuit complexity, and a reduction in hot spot occurrences within the sub-panel.
3) A reliable monitoring system for PV panel in an installed string has been developed, which allows performing the measurement of the actual operating voltage, the short-circuit current, and the open-circuit voltage of the module at specified instant times during the day, without affecting energy production. An extensive experimental campaign was carried out, which demonstrated that the system is well-suited to detect partial shading effects, and can be adopted for long-term monitoring of PV plants.
Photonic devices design needs the prediction of the devices performance, like the trasmission coefficient, the reflection and the loss/gain during the propagation. This means that it is crucial to know how the ligth propagates inside the device. The Beam Propagation Methods (BPM) are the most powerful technique to investigate linear and nonlinear lightwave propagation phenomena, expecially for non linear geometry wave-guides such as curvilinear directional couplers, branching and combining wave- guides, S-shaped bent waveguides, and tapered waveguides. Even if actually powerfull, commercial tool based on these method are available, often a in-house simulator results to be more suitable. For this reason part of the group's activities is centred on the development of a in-house BPM simulator. To impruve and extend the capibilities, we are devoloping a 3D full-vector finite difference BP and a Finite Difference Time Domain propagation simulators that allows us to analyze and design polarization depending and photonic band-gap devices.
The research activity is focused on: high performances direct digital frequency synthesizers (DDFS), clock synthesis, fixed-width multiplier design, real time video processing and decoders for high-speed serial links.
DDFS circuits play a central role in modern digital communications because of their high frequency switching speed with continuous phase operation, their very high frequency resolution, and their capability to easily realize complex modulation techniques. The main block of a DDFS is a digital circuit, named as phase to sine mapper, which evaluates sine and cosine functions with high precision and speed. The research activity has brought to a novel Direct Digital Frequency Synthesizer architecture, based on piecewise linear approximation with segments of non-uniform length. The new approach allows reducing the total number of segments with respect to the well known uniform segmentation. In this way the size of the coefficient ROM is also reduced with beneficial effects in terms of speed and power. The optimal non uniform segmentation (that maximizes the spurious-free dynamic range for a given number of non-uniform segments) can be obtained as the solution of a mixed-integer linear programming problem. Three simple, sub-optimal, non-uniform segmentation schemes (which lend themselves to efficient hardware implementation) have been proposed. Several design examples and VLSI implementation results demonstrate the effectiveness of the developed technique.
Clock generators with frequency spreading technique are widely used in modern system-on-chip both to manage the large number of on chip clock domains and to reduce electromagnetic interference. In addition these circuits are becoming more and more important in low-power systems to realize dynamic-frequency and voltage scaling approaches.
A spread spectrum clock generator (SSCG) is commonly implemented with a PLL, with an appropriate frequency modulated output. This approach use many analog blocks, which require major redesign when the technology scales down. Moreover, analog techniques do not fully exploit the speed and power improvements of today CMOS processes. Finally, the bandwidth of PLL based techniques is usually limited and does not easily allow the generation of clocks with a large modulation frequency.
The research activity is focused on novel all-digital approaches to realize SSCG circuits. A first SSCG, implemented in 65nm CMOS technology, uses a couple of digitally-controlled delay-lines to generate an output clock signal up to 1.27GHz. A third delay-line, closed in a ring-oscillator configuration, is used to compensate process, voltage and temperature variations. The implemented SSCG allows to reach a maximum modulation frequency of more than 10 MHz. The silicon area occupation of only 0.044 mm2 makes this circuit very competitive against other PLL generators. The power dissipation is as low as 44mW @ 1.27GHz.
Fixed-width multipliers are basic building blocks of many digital circuits. The research activity is oriented to the use use of fixed-width multiplier for the implementation of FIR filters. The error introduced by the use of fixed-width multipliers in the realization of FIR filters is analytically calculated. The implementation of various FIR filters in TSMC 0.18um technology shows that fixed-width multipliers are a suitable replacement for the full-width multiplier. Furthermore the best trade-off between error, silicon area occupation and power is provided by the LMS fixed-width multiplier.
The ever growing need of smart systems able to extract meaningful information from images and video streams and the shift towards High Definition (1920x1080) video with high frame rates (60 Hz) requires an exponential growth of the processing power in order to process the growing amount of data. A very short list of applications is: medical images and video, earth and space monitoring, video based portable electronic systems and surveillance cameras. The research activity develops FPGA base video processing systems with the target of light weight, reduced power and real time processing power. The research is aimed to both the algorithmic and the implementation level of the circuits.
High-speed serial transmissions require channel coding in order to ensure adequate information reliability. The 10Gbps 802.3 GBase Ethernet standard requires the use of a Meggitt decoder while the 100Gbps 802.3 GBase Ethernet standard requires the use of a Reed-Solomon decoder. Future standards might require even more sophisticated channel decoding techniques, like LDPC and Soft-Algebraic Reed-Solomon decoders. The research activity has brought to the development of a novel low-latency architecture for Meggitt decoders. The research activity is also focused on the development of high-throughput (100Gbps) Reed-Solomon decoders with reduced power dissipation. State of the art 28nm CMOS technology is exploited to reach the required throughput.
1) V. d’Alessandro, L. La Spina, L. K. Nanver, and N. Rinaldi, “Analysis of electrothermal effects in bipolar differential pairs,” IEEE Transactions on Electron Devices, vol. 58, no. 4, pp. 966-978, 2011.
2) S. Russo, V. d’Alessandro, M. Costagliola, G. Sasso, and N. Rinaldi, “Analysis of the thermal behavior of AlGaN/GaN HEMTs,” in Proc. MICROTHERM, pp. 211-216, Lodz, Poland, 2011.
3) M. Costagliola, V. d’Alessandro, D. Céli, A. Chantre, P. Chevalier, T. Meister, K. Aufinger, and N. Rinaldi, “Experimental extraction of the base resistance of SiGe:C HBTs beyond BVCEO: An improved technique,” in Proc. IEEE BCTM, pp. 188-191, Atlanta, Georgia, USA, 2011.
4) G. Sasso, V. d’Alessandro, M. Costagliola, S. Russo, C. Jungemann, and N. Rinaldi, “Impact of scaling on the DC/RF thermal behavior of Terahertz SiGe HBTs,” in Proc. MICROTHERM, pp. 33-38, Lodz, Poland, 2011.
5) V. d’Alessandro, P. Guerriero, S. Daliento, and M. Gargiulo, “A straightforward method to extract the shunt resistance of photovoltaic cells from current-voltage characteristics of mounted arrays,” Solid-State Electronics, vol. 63, no. 1, pp. 130-136, 2011.
6) M. Costagliola, M. Riccio, A. Irace, G. Breglio, S. Daliento, ”Analytical modeling and experimental verification of the three-dimensional current distribution on the top surface of silicon solar cells operating under concentrated sunlight”, PHYSICA STATUS SOLIDI. C, vol.8, n.3, pp. 899-902, 2011.
8) O. Tari, M. L. Addonizio, E. Fanelli, S. Daliento, P. Pernice, A. Aronne, “Morphological, Optical and Electrical properties of ZnO Sol-Gel Transparent and Conductive films”, proceedings of E-MRS 2011 Spring Meeting, 2011.
9) V. d’Alessandro, S. Daliento, P. Guerriero, and M. Gargiulo, “A novel low-power active bypass approach for photovoltaic panels,” in Proc. IEEE 3rd International Conference on Clean Electrical Power (ICCEP), pp. 89-93, 2011.
10) V. d’Alessandro, P. Guerriero, S. Daliento, and M. Gargiulo, “Accurately extracting the shunt resistance of photovoltaic cells in installed module strings,” in Proc. IEEE 3rd International Conference on Clean Electrical Power (ICCEP), pp. 164-168, 2011.
11) P. Guerriero, V. d’Alessandro, L. Petrazzuoli, G. Vallone, and S. Daliento, “Effective real-time performance monitoring of individual panels in PV plants through an electronic disconnection/measurement system,” in Proc. EUPVSEC, 5BV.2.22, pp. 4272-4275, 2011.
19) D. De Caro, “Glitch-free NAND-based Digitally Controlled Delay-Lines”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2011.2181547.

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