Source: http://datasheet.eeworld.com.cn/part/LPC2388FBD144-551,NXP,9423151.html
Timestamp: 2019-04-18 16:29:12+00:00

Document:
Thumb mode reduces code by more than 30 % with minimal performance penalty.
 ARM7TDMI-S processor, running at up to 72 MHz.
 64 kB of SRAM on the ARM local bus for high performance CPU access.
 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
 16 kB SRAM for general purpose DMA use also accessible by the USB.
 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
card port, as well as for memory-to-memory transfers.
 USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller.
with IrDA support, all with FIFO.
 CAN controller with two channels.
 Three I2C-bus interfaces (one with open-drain and two with standard port pins).
 SD/MMC memory card interface.
 104 General purpose I/O pins with configurable pull-up/down resistors.
outputs. Each timer block has an external count input.
oscillator or the APB clock.
rest of the chip is powered off.
the RTC oscillator, or the APB clock.
 Standard ARM test/debug interface for compatibility with existing tools.
 Emulation trace module supports real-time trace.
 Single 3.3 V power supply (3.0 V to 3.6 V).
 Four reduced power modes: Idle, Sleep, Power-down and Deep power-down.
and Port 2 can be used as edge sensitive interrupt sources.
 Each peripheral has its own clock divider for further power saving.
 Brownout detect with separate thresholds for interrupt and forced reset.
 On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
LPC2388 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
 Boundary scan for simplified board testing.
P0/RD1/TXD3/ 66 I/O P0 — General purpose digital input/output pin.
SDA1 I RD1 — CAN1 receiver input.
O TXD3 — Transmitter output for UART3.
I/O SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0/TD1/RXD3/ 67 I/O P0 — General purpose digital input/output pin.
SCL1 O TD1 — CAN1 transmitter output.
I RXD3 — Receiver input for UART3.
I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P0/TXD0 141 I/O P0 — General purpose digital input/output pin.
O TXD0 — Transmitter output for UART0.
P0/RXD0 142 I/O P0 — General purpose digital input/output pin.
I RXD0 — Receiver input for UART0.
P0/ 116 I/O P0 — General purpose digital input/output pin.
I2SRX_CLK/ I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
RD2/CAP2 Corresponds to the signal SCK in the I2S-bus specification.
I RD2 — CAN2 receiver input.
I CAP2 — Capture input for Timer 2, channel 0.
P0/ 115 I/O P0 — General purpose digital input/output pin.
TD2/CAP2 slave. Corresponds to the signal WS in the I2S-bus specification.
O TD2 — CAN2 transmitter output.
I CAP2 — Capture input for Timer 2, channel 1.
P0/ 113 I/O P0 — General purpose digital input/output pin.
SSEL1/MAT2 receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O SSEL1 — Slave Select for SSP1.
O MAT2 — Match output for Timer 2, channel 0.
P0/ 112 I/O P0 — General purpose digital input/output pin.
I2STX_CLK/ I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
SCK1/MAT2 Corresponds to the signal SCK in the I2S-bus specification.
I/O SCK1 — Serial Clock for SSP1.
O MAT2 — Match output for Timer 2, channel 1.
P0/ 111 I/O P0 — General purpose digital input/output pin.
MISO1/MAT2 slave. Corresponds to the signal WS in the I2S-bus specification.
I/O MISO1 — Master In Slave Out for SSP1.
O MAT2 — Match output for Timer 2, channel 2.
P0/ 109 I/O P0 — General purpose digital input/output pin.
MOSI1/MAT2 receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O MOSI1 — Master Out Slave In for SSP1.
O MAT2 — Match output for Timer 2, channel 3.
P0/TXD2/ 69 I/O P0 — General purpose digital input/output pin.
SDA2/MAT3  O TXD2 — Transmitter output for UART2.
I/O SDA2 — I2C2 data input/output (this is not an open-drain pin).
O MAT3 — Match output for Timer 3, channel 0.
P0/RXD2/ 70 I/O P0 — General purpose digital input/output pin.
SCL2/MAT3 I RXD2 — Receiver input for UART2.
I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin).
O MAT3 — Match output for Timer 3, channel 1.
P0/ 29 I/O P0 — General purpose digital input/output pin.
USB_PPWR2/ O USB_PPWR2 — Port power enable signal for USB port 2.
I AD0 — A/D converter 0, input 6.
P0/ 32 I/O P0 — General purpose digital input/output pin.
host is enabled and has not detected a device on the bus, or during global suspend.
I AD0 — A/D converter 0, input 7.
P0/ 48 I/O P0 — General purpose digital input/output pin.
USB_HSTEN2/ O USB_HSTEN2 — Host Enabled status for USB port 2.
P0/TXD1/ 89 I/O P0 — General purpose digital input/output pin.
SCK0/SCK O TXD1 — Transmitter output for UART1.
I/O SCK0 — Serial clock for SSP0.
I/O SCK — Serial clock for SPI.
P0/RXD1/ 90 I/O P0 — General purpose digital input/output pin.
SSEL0/SSEL I RXD1 — Receiver input for UART1.
I/O SSEL0 — Slave Select for SSP0.
I/O SSEL — Slave Select for SPI.
P0/CTS1/ 87 I/O P0 — General purpose digital input/output pin.
MISO0/MISO I CTS1 — Clear to Send input for UART1.
I/O MISO0 — Master In Slave Out for SSP0.
I/O MISO — Master In Slave Out for SPI.
P0/DCD1/ 86 I/O P0 — General purpose digital input/output pin.
MOSI0/MOSI I DCD1 — Data Carrier Detect input for UART1.
I/O MOSI0 — Master Out Slave In for SSP0.
I/O MOSI — Master Out Slave In for SPI.
P0/DSR1/ 85 I/O P0 — General purpose digital input/output pin.
MCICLK/SDA1 I DSR1 — Data Set Ready input for UART1.
O MCICLK — Clock output line for SD/MMC interface.
P0/DTR1/ 83 I/O P0 — General purpose digital input/output pin.
MCICMD/SCL1 O DTR1 — Data Terminal Ready output for UART1.
I MCICMD — Command line for SD/MMC interface.
P0/RI1/ 82 I/O P0 — General purpose digital input/output pin.
MCIPWR/RD1 I RI1 — Ring Indicator input for UART1.
O MCIPWR — Power Supply Enable for external SD/MMC power supply.
I RD1 — CAN1 receiver input.
P0/RTS1/ 80 I/O P0 — General purpose digital input/output pin.
MCIDAT0/TD1 O RTS1 — Request to Send output for UART1.
O MCIDAT0 — Data line for SD/MMC interface.
O TD1 — CAN1 transmitter output.
P0/AD0/ 13 I/O P0 — General purpose digital input/output pin.
I2SRX_CLK/ I AD0 — A/D converter 0, input 0.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.
I CAP3 — Capture input for Timer 3, channel 0.
P0/AD0/ 11 I/O P0 — General purpose digital input/output pin.
I2SRX_WS/ I AD0 — A/D converter 0, input 1.
slave. Corresponds to the signal WS in the I2S-bus specification.
I CAP3 — Capture input for Timer 3, channel 1.
P0/AD0/ 10 I/O P0 — General purpose digital input/output pin.
I2SRX_SDA/ I AD0 — A/D converter 0, input 2.
receiver. Corresponds to the signal SD in the I2S-bus specification.
P0/AD0/ 8 I/O P0 — General purpose digital input/output pin.
AOUT/RXD3 I AD0 — A/D converter 0, input 3.
O AOUT — D/A converter output.
P0/SDA0 35 I/O P0 — General purpose digital input/output pin. The output is open-drain.
I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).
P0/SCL0 34 I/O P0 — General purpose digital input/output pin. The output is open-drain.
I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
P0/USB_D+1 42 I/O P0 — General purpose digital input/output pin.
I/O USB_D+1 — USB port 1 bidirectional D+ line.
P0/USB_D1 43 I/O P0 — General purpose digital input/output pin.
I/O USB_D1 — USB port 1 bidirectional D line.
P0/USB_D+2 36 I/O P0 — General purpose digital input/output pin.
I/O USB_D+2 — USB port 2 bidirectional D+ line.
block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.
P1/ 136 I/O P1 — General purpose digital input/output pin.
ENET_TXD0 O ENET_TXD0 — Ethernet transmit data 0.
P1/ 135 I/O P1 — General purpose digital input/output pin.
ENET_TXD1 O ENET_TXD1 — Ethernet transmit data 1.
P1/ 133 I/O P1 — General purpose digital input/output pin.
ENET_TX_EN O ENET_TX_EN — Ethernet transmit data enable.
P1/ 132 I/O P1 — General purpose digital input/output pin.
ENET_CRS I ENET_CRS — Ethernet carrier sense.
P1/ 131 I/O P1 — General purpose digital input/output pin.
ENET_RXD0 I ENET_RXD0 — Ethernet receive data.
P1/ 129 I/O P1 — General purpose digital input/output pin.
ENET_RXD1 I ENET_RXD1 — Ethernet receive data.
P1/ 128 I/O P1 — General purpose digital input/output pin.
ENET_RX_ER I ENET_RX_ER — Ethernet receive error.
P1/ 126 I/O P1 — General purpose digital input/output pin.
ENET_REF_CLK I ENET_REF_CLK/ENET_RX_CLK — Ethernet receiver clock.
P1/ 125 I/O P1 — General purpose digital input/output pin.
ENET_MDC O ENET_MDC — Ethernet MIIM clock.
P1/ 123 I/O P1 — General purpose digital input/output pin.
ENET_MDIO I/O ENET_MDIO — Ethernet MI data input and output.
P1/ 46 I/O P1 — General purpose digital input/output pin.
O PWM1 — Pulse Width Modulator 1, channel 1 output.
I CAP1 — Capture input for Timer 1, channel 0.
P1/ 47 I/O P1 — General purpose digital input/output pin.
USB_TX_E1/ O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).
CAP1 O USB_PPWR1 — Port Power enable signal for USB port 1.
I CAP1 — Capture input for Timer 1, channel 1.
P1/ 49 I/O P1 — General purpose digital input/output pin.
USB_TX_DP1/ O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).
O PWM1 — Pulse Width Modulator 1, channel 2 output.
P1/ 50 I/O P1 — General purpose digital input/output pin.
USB_TX_DM1/ O USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).
O PWM1 — Pulse Width Modulator 1, channel 3 output.
P1/ 51 I/O P1 — General purpose digital input/output pin.
USB_RCV1/ I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).
MAT1 I USB_PWRD1 — Power Status for USB port 1 (host power switch).
O MAT1 — Match output for Timer 1, channel 0.
P1/ 53 I/O P1 — General purpose digital input/output pin.
USB_RX_DP1/ I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).
O PWM1 — Pulse Width Modulator 1, channel 4 output.
P1/ 54 I/O P1 — General purpose digital input/output pin.
USB_RX_DM1/ I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).
O PWM1 — Pulse Width Modulator 1, channel 5 output.
P1/ 56 I/O P1 — General purpose digital input/output pin.
USB_LS1/ O USB_LS1 — Low-speed status for USB port 1 (OTG transceiver).
MAT1 O USB_HSTEN1 — Host Enabled status for USB port 1.
O MAT1 — Match output for Timer 1, channel 1.
P1/ 57 I/O P1 — General purpose digital input/output pin.
USB_SSPND1/ O USB_SSPND1 — USB port 1 bus suspend status (OTG transceiver).
CAP0 O PWM1 — Pulse Width Modulator 1, channel 6 output.
I CAP0 — Capture input for Timer 0, channel 0.
P1/ 61 I/O P1 — General purpose digital input/output pin.
USB_INT1/ I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).
CAP0 I USB_OVRCR1 — USB port 1 Over-Current status.
I CAP0 — Capture input for Timer 0, channel 1.
P1/ 63 I/O P1 — General purpose digital input/output pin.
USB_SCL1/ I/O USB_SCL1 — USB port 1 I2C-bus serial clock (OTG transceiver).
MAT0 I PCAP1 — Capture input for PWM1, channel 0.
O MAT0 — Match output for Timer 0, channel 0.
P1/ 64 I/O P1 — General purpose digital input/output pin.
USB_SDA1/ I/O USB_SDA1 — USB port 1 I2C-bus serial data (OTG transceiver).
MAT0 I PCAP1 — Capture input for PWM1, channel 1.
P1/ 30 I/O P1 — General purpose digital input/output pin.
USB_PWRD2/ I USB_PWRD2 — Power Status for USB port 2.
VBUS/AD0 I VBUS — Monitors the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.
I AD0 — A/D converter 0, input 4.
P1/ 28 I/O P1 — General purpose digital input/output pin.
USB_OVRCR2/ I USB_OVRCR2 — Over-Current status for USB port 2.
I AD0 — A/D converter 0, input 5.
block. Pins 14 through 31 of this port are not available.
P2/PWM1/ 107 I/O P2 — General purpose digital input/output pin.
TXD1/ O PWM1 — Pulse Width Modulator 1, channel 1 output.
O TXD1 — Transmitter output for UART1.
O TRACECLK — Trace Clock.
P2/PWM1/ 106 I/O P2 — General purpose digital input/output pin.
RXD1/ O PWM1 — Pulse Width Modulator 1, channel 2 output.
I RXD1 — Receiver input for UART1.
O PIPESTAT0 — Pipeline Status, bit 0.
P2/PWM1/ 105 I/O P2 — General purpose digital input/output pin.
CTS1/ O PWM1 — Pulse Width Modulator 1, channel 3 output.
I CTS1 — Clear to Send input for UART1.
O PIPESTAT1 — Pipeline Status, bit 1.
P2/PWM1/ 100 I/O P2 — General purpose digital input/output pin.
DCD1/ O PWM1 — Pulse Width Modulator 1, channel 4 output.
I DCD1 — Data Carrier Detect input for UART1.
O PIPESTAT2 — Pipeline Status, bit 2.
P2/PWM1/ 99 I/O P2 — General purpose digital input/output pin.
DSR1/ O PWM1 — Pulse Width Modulator 1, channel 5 output.
I DSR1 — Data Set Ready input for UART1.
O TRACESYNC — Trace Synchronization.
P2/PWM1/ 97 I/O P2 — General purpose digital input/output pin.
DTR1/ O PWM1 — Pulse Width Modulator 1, channel 6 output.
O DTR1 — Data Terminal Ready output for UART1.
O TRACEPKT0 — Trace Packet, bit 0.
P2/PCAP1/ 96 I/O P2 — General purpose digital input/output pin.
RI1/ I PCAP1 — Capture input for PWM1, channel 0.
I RI1 — Ring Indicator input for UART1.
O TRACEPKT1 — Trace Packet, bit 1.
P2/RD2/ 95 I/O P2 — General purpose digital input/output pin.
RTS1/ I RD2 — CAN2 receiver input.
O RTS1 — Request to Send output for UART1.
O TRACEPKT2 — Trace Packet, bit 2.
P2/TD2/ 93 I/O P2 — General purpose digital input/output pin.
TXD2/ O TD2 — CAN2 transmitter output.
O TXD2 — Transmitter output for UART2.
O TRACEPKT3 — Trace Packet, bit 3.
P2/ 92 I/O P2 — General purpose digital input/output pin.
I RXD2 — Receiver input for UART2.
I EXTIN0 — External Trigger Input.
P2/EINT0 76 I/O P2 — General purpose digital input/output pin.
control of the part after a reset.
I EINT0 — External interrupt 0 input.
P2/EINT1/ 75 I/O P2 — General purpose digital input/output pin.
MCIDAT1/ I EINT1 — External interrupt 1 input.
O MCIDAT1 — Data line for SD/MMC interface.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
P2/EINT2/ 73 I/O P2 — General purpose digital input/output pin.
MCIDAT2/ I EINT2 — External interrupt 2 input.
O MCIDAT2 — Data line for SD/MMC interface.
P2/EINT3/ 71 I/O P2 — General purpose digital input/output pin.
MCIDAT3/ I EINT3 — External interrupt 3 input.
O MCIDAT3 — Data line for SD/MMC interface.
block. Pins 8 through 22, and 27 through 31 of this port are not available.
P3/D0 137 I/O P3 — General purpose digital input/output pin.
I/O D0 — External memory data line 0.
P3/D1 140 I/O P3 — General purpose digital input/output pin.
I/O D1 — External memory data line 1.
P3/D2 144 I/O P3 — General purpose digital input/output pin.
I/O D2 — External memory data line 2.
P3/D3 2 I/O P3 — General purpose digital input/output pin.
I/O D3 — External memory data line 3.
P3/D4 9 I/O P3 — General purpose digital input/output pin.
I/O D4 — External memory data line 4.
P3/D5 12 I/O P3 — General purpose digital input/output pin.
I/O D5 — External memory data line 5.
P3/D6 16 I/O P3 — General purpose digital input/output pin.
I/O D6 — External memory data line 6.
P3/D7 19 I/O P3 — General purpose digital input/output pin.
I/O D7 — External memory data line 7.
P3/CAP0/ 45 I/O P3 — General purpose digital input/output pin.
PCAP1 I CAP0 — Capture input for Timer 0, channel 0.
I PCAP1 — Capture input for PWM1, channel 0.
P3/CAP0/ 40 I/O P3 — General purpose digital input/output pin.
PWM1 I CAP0 — Capture input for Timer 0, channel 1.
O PWM1 — Pulse Width Modulator 1, output 1.
P3/MAT0/ 39 I/O P3 — General purpose digital input/output pin.
PWM1 O MAT0 — Match output for Timer 0, channel 0.
O PWM1 — Pulse Width Modulator 1, output 2.
P3/MAT0/ 38 I/O P3 — General purpose digital input/output pin.
PWM1 O MAT0 — Match output for Timer 0, channel 1.
O PWM1 — Pulse Width Modulator 1, output 3.
block. Pins 16 through 23, 26, and 27 of this port are not available.
P4/A0 52 I/O P4 — ]General purpose digital input/output pin.
I/O A0 — External memory address line 0.
P4/A1 55 I/O P4 — General purpose digital input/output pin.
I/O A1 — External memory address line 1.
P4/A2 58 I/O P4 — General purpose digital input/output pin.
I/O A2 — External memory address line 2.
P4/A3 68 I/O P4 — General purpose digital input/output pin.
I/O A3 — External memory address line 3.
P4/A4 72 I/O P4 — General purpose digital input/output pin.
I/O A4 — External memory address line 4.
P4/A5 74 I/O P4 — General purpose digital input/output pin.
I/O A5 — External memory address line 5.
P4/A6 78 I/O P4 — General purpose digital input/output pin.
I/O A6 — External memory address line 6.
P4/A7 84 I/O P4 — General purpose digital input/output pin.
I/O A7 — External memory address line 7.
P4/A8 88 I/O P4 — General purpose digital input/output pin.
I/O A8 — External memory address line 8.
P4/A9 91 I/O P4 — General purpose digital input/output pin.
I/O A9 — External memory address line 9.
P4/A10 94 I/O P4 — General purpose digital input/output pin.
I/O A10 — External memory address line 10.
P4/A11 101 I/O P4 — General purpose digital input/output pin.
I/O A11 — External memory address line 11.
P4/A12 104 I/O P4 — General purpose digital input/output pin.
I/O A12 — External memory address line 12.
P4/A13 108 I/O P4 — General purpose digital input/output pin.
I/O A13 — External memory address line 13.
P4/A14 110 I/O P4 — General purpose digital input/output pin.
I/O A14 — External memory address line 14.
P4/A15 120 I/O P4 — General purpose digital input/output pin.
I/O A15 — External memory address line 15.
P4/OE 127 I/O P4 — General purpose digital input/output pin.
O OE — LOW active Output Enable signal.
P4/BLS0 124 I/O P4 — General purpose digital input/output pin.
O BLS0 — LOW active Byte Lane select signal 0.
P4/MAT2/ 118 I/O P4 — General purpose digital input/output pin.
TXD3 O MAT2 — Match output for Timer 2, channel 0.
P4/MAT2/ 122 I/O P4 — General purpose digital input/output pin.
RXD3 O MAT2 — Match output for Timer 2, channel 1.
P4/CS0 130 I/O P4 — General purpose digital input/output pin.
O CS0 — LOW active Chip Select 0 signal.
P4/CS1 134 I/O P4 — General purpose digital input/output pin.
O CS1 — LOW active Chip Select 1 signal.
USB_D2 37 I/O USB_D2 — USB port 2 bidirectional D line.
DBGEN 6 I DBGEN — JTAG interface control signal. Also used for boundary scanning.
TDO 1 O TDO — Test Data out for JTAG interface.
TDI 3 I TDI — Test Data in for JTAG interface.
TMS 4 I TMS — Test Mode Select for JTAG interface.
TRST 5 I TRST — Test Reset for JTAG interface.
clock (CCLK) for the JTAG interface to operate.
RTCK 143 I/O RTCK — JTAG interface control signal.
as Trace port after reset.
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 31 I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 33 O Output from the oscillator amplifier.
RTCX1 23 I Input to the RTC oscillator circuit.
RTCX2 25 O Output from the RTC oscillator circuit.
VSS 22, 44, I ground: 0 V reference.
but should be isolated to minimize noise and error.
VDD(3V3) 41, 62, I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
n.c. 21, 81, I Leave these pins unconnected.
power the ADC and DAC.
VBAT 27 I RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
digital section of the pad is disabled.
configuration applies to all functions on this pin.
 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
 Pad provides special analog functionality.
 This pin has a built-in pull-up resistor.
 This pin has no built-in pull-up and no built-in pull-down resistor.
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
 If the RTC is not used, these pins can be left floating.
includes the VIC, GPDMA controller, and EMC.
off-chip memory or unused space in memory residing on AHB1.
are the ARM7 and the Ethernet block.
AHB address space. Lower speed peripheral functions are connected to the APB bus.
peripheral is allocated a 16 kB address space within the APB address space.
impressive real-time interrupt response from a small and cost-effective processor core.
is being decoded, and a third instruction is being fetched from memory.
operates on the same 32-bit register set as ARM code.
running, allowing a great degree of flexibility for data storage field and firmware upgrades.
allow it to operate at SRAM speeds of 72 MHz.
as 8 bits, 16 bits, and 32 bits.
retains the content in the absence of the main power supply.
The LPC2388 memory map incorporates several distinct regions as shown in Figure 3.
flash memory (default), boot ROM, or SRAM (see Section 7.26.6).
identifies which FIQ source(s) is (are) requesting an interrupt.
jumping to the address supplied by that register.
pin and the on chip peripherals.
not mapped to a related pin should be considered undefined.
peripherals to have DMA support.
can be accessed through the AHB master.
• Two DMA channels. Each channel can support a unidirectional transfer.
SD/MMC, two SSP, and I2S-bus interfaces.
burst size is set by programming the GPDMA.
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
highest priority is serviced first.
DMA control registers over the AHB slave interface.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Internal four-word FIFO per channel.
• Supports 8-bit, 16-bit, and 32-bit wide transactions.
output register may be read back as well as the current state of the port pins.
• All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.
• Direction control of individual bits.
• All I/O default to inputs after reset.
Port 1 registers appearing at the original addresses on the APB bus.
with scatter-gather DMA off-loads many operations from the CPU.
memory, will slow Ethernet access to memory and increase the loading of its AHB.
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
– Multicast and broadcast frame support for both transmit and receive.
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
receive filters or a magic frame detection filter.
– Attachment of external PHY chip through standard RMII interface.
– PHY register access is available via the MIIM interface.
typical USB interfacing solutions can be found in Section 14.1.
• Fully compliant with USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Supports SoftConnect and GoodLink features.
power modes and wake up on USB activity.
• Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
• Allows dynamic switching between CPU-controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
register interface complies with the OHCI specification.
• Supports per-port power switching.
interface controls an external OTG transceiver.
• Hardware support for Host Negotiation Protocol (HNP).
application ranges from high-speed networks to low cost multiplex wiring.
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• FullCAN messages can generate interrupts.
value of the DAC is Vi(VREF).
lines, UART1 also provides a full modem control handshake interface.
can be achieved with any crystal frequency above 2 MHz.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
need for external crystals of particular values.
mechanism that enables software flow control implementation.
full support for hardware flow control (auto-CTS/RTS).
• UART3 includes an IrDA mode to support infrared communication.
always sends 8 bits to 16 bits of data to the master.
often only one of these data flows carries meaningful data.
• Conforms to Multimedia Card Specification v2.11.
• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
• DMA supported through the GPDMA controller.
The LPC2388 contains three I2C-bus controllers.
be controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2388 supports bit rates up to 400 kbit/s (Fast I2C-bus).
• I2C0 is a standard I2C compliant bus interface with open-drain pins.
devices connected to the same bus lines.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• The I2C-bus can be used for test and diagnostic purposes.
The I2S-bus provides a standard communication interface for digital audio applications.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Controls include reset, stop and mute options separately for I2S-bus input and output.
value when an input signal transitions, optionally generating an interrupt.
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
• Counter or Timer operation.
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
– Set LOW on match.
– Set HIGH on match.
– Do nothing on match.
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
edge occurs prior to the rising edge).
peripheral clock or one of the capture inputs as the clock source).
occur at the same repetition rate.
• May be used as a standard timer if the PWM mode is not enabled.
• Internally resets chip if not periodically reloaded.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
multiples of Tcy(WDCLK)  4.
supply used by the rest of the device.
require a minimum of power to operate, which can be supplied by an external battery.
• Ultra low power design to support battery powered systems.
• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
and selected fractional second values.
• 2 kB data SRAM powered by VBAT.
• RTC and battery RAM power supply is isolated from the rest of the chip.
chosen by software to drive the PLL and ultimately the CPU.
code to operate at a known frequency.
trimmed to 1 % accuracy.
Upon power-up or any chip reset, the LPC2388 uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
PCLK. Refer to Section 7.25.2 for additional information.
RTC oscillator can be used to drive the PLL and the CPU.
clock used by the CPU and the USB block.
output frequencies from the same input frequency.
error value is used to adjust the CCO frequency.
wait for the PLL to lock, then connect to the PLL as a clock source.
before they are used as a clock source.
allows a trade-off of power versus processing speed based on application requirements.
has its own clock divider which provides even better power control.
referred to as the battery RAM.
USB clock dividers automatically get reset to zero.
very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.
external oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
reconfigure the PLL and clock dividers accordingly.
caused by the RTC Alarm interrupt or by external Reset.
the LPC2388 will start up when external power is restored.
to the VBAT pin is maintained.
to have power removed while maintaining operation of the RTC and the battery RAM.
the CPU and most of the peripherals.
pad power supply “on the fly”, while the CPU and peripherals stay active.
and peripheral registers have been initialized to predetermined values.
which point the power-on reset circuitry maintains the overall Reset.
loop to sense the condition.
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
required and flash field updates are needed but all sectors can not be erased.
using a reduced set of the ISP commands.
JTAG pins and the ISP. This mode effectively disables ISP override using P2 pin, too.
calls or call reinvoke ISP command to enable flash update via UART0.
intended for use by the USB.
with access to AHB2 are the ARM7 and the Ethernet block.
inputs can optionally be used to wake up the processor from Power-down mode.
spaces to have control of the interrupts.
phase as they are when the application is run in the embedded system itself.
DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core.
resource. Trigger resources include address comparators, counters and sequencers.
RealMonitor software programmed into the on-chip ROM memory.
based on required shelf lifetime. Please refer to the JEDEC specification (J-STD-033B.1) for further details.
 Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
 Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
 The RTC typically fails when Vi(VBAT) drops below 1.6 V.
 VDD(DCDC)(3V3) = 3.3 V; VDD(3V3) = 3.3 V; Vi(VBAT) = 3.3 V; Tamb = 25 C.
 VDD(3V3) supply voltages must be present.
 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
 Please also see the errata note in errata sheet.
 Allowed as long as the current limit does not exceed the maximum current allowed by the device.
 Includes external resistors of 33   1 % on D+ and D.
Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C.
VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C.
VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C.
Conditions: VDD(3V3) = 3.3 V; standard port pins.
Tamb = 40 C to +85 C for commercial applications; VDD(3V3) over specified ranges.
Tamb = 40 C to +85 C; 3.0 V  VDD(3V3)  3.6 V.
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.
 Applies to standard I/O pins and RESET pin.
CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3),unless otherwise specified.
 Characterized but not implemented as production test. Guaranteed by design.
 Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
CL = 30 pF, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V.
 VOH = 2.5 V, VOL = 0.2 V.
 Latest of address valid, CS LOW, OE LOW to data valid.
 Earliest of CS HIGH, OE HIGH, address change to data invalid.
VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz.
 Conditions: VSSA = 0 V, VDDA = 3.3 V.
 The ADC is monotonic, there are no missing codes.
 The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17.
appropriate adjustment of gain and offset errors. See Figure 17.
ideal curve. See Figure 17.
error, and the straight line which fits the ideal transfer curve. See Figure 17.
ADC and the ideal transfer curve. See Figure 17.
(3) Differential linearity error (ED).
slave mode, a minimum of 200 mV (RMS) is needed.
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
specified in this table are calculated from the internal parasitic capacitances and the CL.
Parasitics from PCB and package are not taken into account.
accordingly to the increase in parasitics of the PCB layout.
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
– Updated description for USB_UP_LED1 and USB_UP_LED2.
– Added Table note 9 for DBGEN, TMS, TDI, TRST, and RTCK pins.
– Added Table note 10 for TCK and TDO pins.
– Table note 6: Changed glitch filter spec from 5 ns to 10 ns.
– Added “non-operating” to conditions of storage spec.
– Updated Table note 5.
• Added Table 6 “Thermal resistance value (C/W): ±15 %”.
• Table 7 “Static characteristics”: Changed Vhys Typ value of I2C-bus pins to 0.05VDD(3V3).
• Table 8 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.
• Table 12 “Dynamic characteristics of flash”: Updated table.
• Section 14.5 “Standard I/O pin configuration”: Updated bullets.
full information. For detailed and full information see the relevant full data specified use without further testing or modification.
Product data sheet. applications and products.
completeness of such information and shall have no liability for the customer(s). NXP does not accept any liability in this respect.
damages are based on tort (including negligence), warranty, breach of the quality and reliability of the device.
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
the product is not suitable for automotive use. It is neither qualified nor tested standard warranty and NXP Semiconductors’ product specifications.
automotive applications to automotive specifications and standards, customer are the property of their respective owners.
(a) shall use the product without NXP Semiconductors’ warranty of the I2C-bus — logo is a trademark of NXP B.V.

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