Source: https://patents.google.com/patent/EP0702871A4/en
Timestamp: 2019-04-19 18:59:19+00:00

Document:
The present invention relates to a communication system, protocol and method designed to facilitate information transfer including user and control information from CBR (Continuous Bit Rate) and/or non-CBR signal sources. Such a system, for example, is a CSS (Customer Switching System), a LAN network, a Key System, LAN hub, PABX or PBX. A number of aspects are disclosed in this specification. These include: A) a key system and/or LAN which utilizes ATM technology for the trafficking of CBR, non-CBR, or a combination thereof, B) a round robin feature which facilitates the operation of i. above, C) a cell format which facilitates the operation of i. above, D) an open and closed system architecture for i. above, E) an ATM-TP which serves as an interface for CBR to the architecture and an ATM-HP which serves as an interface for non-CBR to the architecture, F) partial cell filling for system efficiency and/or echo control, G) a staggering feature to facilitate system efficiency, H) a channel aggregation feature to reduce the requirement for external adaptor equipment, I) a by-pass feature to enhance system reliability and serviceability. An example of CBR is voice, video and "non-bursty" data. An example of non-CBR or "bursty" data is LAN data.
The present invention relates to a communication system, protocol and method designed to facilitate information transfer including user and control information from CBR (Continuous Bit Rate) and/or non-CBR signal sources.
Such a system, for example is a CSS (Customer Switching System), a LAN network, a Key System, LAN hub, PABX or PBX.
(xi) distinction between internally and externally sourced cells, (xii) connection of internal and external cell sources. In relation to "staggering", other problems may exist in prior art communication systems in respect of end to end delay of CBR channels, a significant component of which is caused by cell access delay. Prior art systems which use fixed-length packet techniques to transport CBR signals may suffer increased end to end delay when all CBR sources are in phase with each other. Cell access delay is longest when cells are generated in phase and the problem is most prevalent in the absence of non-CBR sources. This results in relatively high packet access delay. Thus, even though the average bandwidth of the system may be sufficient, instantaneous shortfalls can result in access delays, which delays may be nearly as large as the packetisation delay.
Prior art systems presently address this problem by providing surplus system bandwidth or by providing partial filling of cells (also requiring extra unusable bandwidth). This is considered to be inefficient and undesirable as it impacts on system performance and cost.
Particularly in relation to "channel aggregation", a problem also is perceived to exist where a number of bit streams are placed onto a first interface of a communication system e.g. a TDM based L1/N1 interface. The bit streams can emerge from a second system interface with a relative delay between separate streams. Currently expensive adaptor equipment is required in addition to the system to cater for such bit streams.
In relation to system reliability and serviceability, a problem has been identified in prior art architectures used in a number of communication systems.
The problem identified is in the area of system maintenance and/or reliability, and in particular the probability of complete system failure caused as a result of a part of the system failing.
I. A by-pass feature to enhance system reliability and serviceability. An example of CBR is voice, video and 'non-bursty' data.
An example of non-CBR or 'bursty' data is LAN data. One problem addressed by the present invention is the development of system technology which provides flexible and cost-effective support of a wide range of services (e.g. constant bit rate (CBR) such as voice, and non-CBR such as LAN data, etc.) applicable to business customers now and in the future.
When more than one contending node has more than one cell to send, the system may allow each contending node to monitor the requirement of other contending nodes. The first contending node can gain access and will, after transmitting a cell, not transmit any further cells until each contending node has had an opportunity (fair chance) to gain access before the first contending node again may access the backbone. This also accords with a round robin feature which has been found to be advantageous in the present system.
Access to the system is provided in accordance with a ranking of priority. Higher priority nodes gain access in precedence to lower priority nodes.
Due to the effect of the Fairness Basis of Group Contention Resolution described above competing nodes of the same service priority will have access to any remaining system bandwidth, not used by members of any group belonging to a higher priority service class, divided in predetermined (equal or unequal) proportions between them.
Surprisingly, it has been discovered that, by implementing the use of empty or idle cells in a communication system and allowing signal sources to compete for those empty or idle cells, a system is provided which has the capability of both CBR and/or non-CBR information transfer substantially without perceived or real substantial degradation of quality of service.
The cell format aspect relates to a communication protocol. The present aspect sees an external cell as a group of data that is sourced external to the backbone, from external network and/or user equipment. An external cell may also be a prior art protocol type, for example the CCITT UNI CELL. The present aspect sees an internal cell as a medium or cell that may travel on the backbone.
The present aspect is predicated on the realization that a cell format can be utilized which enables prior art type cell formats to be at least partially incorporated in the present cell format and substantially reconstructed upon emergence from a backbone. This facilitates the ability of the present protocol to enable the provision of a communication system, which includes CBR and/or non-CBR, whether in an external or internal format.
The present format, in one form, alters or overwrites a portion of an external cell in order to facilitate CBR and/or non-CBR traffic in the communication system.
Importantly, to one aspect, the present format utilizes a Req_Pri field for the trafficking of CBR and/ or non-CBR. This field provides one source of priority indication. A further field A may provide further assistance in the trafficking of CBR and non-CBR. This field provides one source of cell activity. The present format is further predicated on an assignment of a predetermined range of values to particular fields within the cell format, the values serving to substantially distinguish between internally and externally generated or sourced cells. Furthermore, a number of fields in the protocol of the present invention have been assigned different uses or outcomes. In some fields, numeric values may be assigned to provoke a predetermined outcome.
In particular, a new 'hub' applicable to LAN networks or systems may be provided in accordance with one aspect of the present invention. The 'hub' may be incorporated into existing LAN networks or systems to facilitate the modification of a network to enable CBR and/or non-CBR traffic in the network.
This implementation is accomplished, preferably in accordance with the 3 characteristics above, in such a way that each source, node or hub is adapted to compete for access to idle cells. The present invention seeks to adopt ATM technology principles in the environment of the system. Cells enter the network, and flow through the network. CBR and/or non-CBR sources, nodes or hubs may utilise the cells as required, and thus the network is able to traffic either CBR and/or non-CBR signals. In a most preferred form, the use of empty or idle cells is implemented in conjunction with a closed chain architecture and/or an open chain architecture.
LAN network and/or hubs for the LAN network.
The further invention is predicated on the discovery that a communication system, particularly a CSS Key System, LAN network and/or LAN hub, lends itself to traffic CBR and/or non-CBR signals because the active cells (packets) of user and control information are able to flow through the system, i.e. from originator to designation, substantially in an original form. In a preferred form substantially only the header information may be modified. The further invention is adapted to facilitate flow of a cell through the system, whether that cell is idle or active.
In another aspect, a further invention is also predicated on the realization that information from CBR and/or non-CBR services is capable of occupying cells in a manner which is not fixed in advance. Dynamic bandwidth is one exemplary outcome of the above realization.
The provision of dynamic bandwidth allocation facilitates the ability for user and control information to both use the same transmission medium.
Cell fill may be fixed, as is most preferred, or may vary from cell to cell.
The present aspect, in one form, provides a means and/or method of reducing access delay substantially without excessive increase in system bandwidth requirements. The present aspect, in this regard, provides 'staggering' between channels which have access to the system.
Staggering is predicated on the principle that it is possible to ensure that the sources of signals on a backbone system are not all in phase. In one form, the system forces a fixed phase difference between different sources. In this system, each node or module is preferably controlled to generate or fill cells at substantially even points of time.
The present aspect is directed to enable multiple bit streams to be placed onto a first interface and to have the bit streams emerge at a second interface without substantial, and preferably without any, relative delay between separate streams, and without the need for external adaptor equipment. The present invention is predicated on the discovery that multiple bit streams can be accommodated by enabling more than one bit stream to be carried within a given cell. It is preferred that channels which are to be carried can be predetermined or nominated upon demand or request. Each bit stream represents CBR and/or non-CBR signals.
The solution posed to the reliability and serviceability problem stems from identification of the fact that system reliability can be increased relatively significantly (relative to existing backbone architectures) by utilizing a by-pass architecture. The present invention therefore also contemplates in another form a 'self- heal' system adapted to alleviate or reduce communication system down time by controlling utilisation of the by-pass architecture. A self-heal system can automatically by-pass defective or system portions to be isolated without substantially inhibiting the performance of other portions of the system. The present invention is predicated on the provision of a by-pass architecture in conjunction with a communication system. The by-pass architecture enables portions of a communication system to be isolated and passed by whilst other portions of the system continue to function. As a result, system reliability is considered as a whole to be increased and it also lends itself to ease of maintenance of the system.
Figure 40 shows, as a summary, some of the features provided in a preferred embodiment of the system as disclosed.
Local Area Network CPE is already a global industry. This form of CPE is much more than a P.C. It includes bridges, frame relays, wiring systems etc. Medium to large scale businesses are, and will continue to be wired up for Local Area Networks. These businesses will also be wired for voice communications.
The present invention has been designed to support either or a mixture of the following two topologies: Topology 1 The customer can purchase one or more Hubs, with up to three "Hubs" being preferred. Each Hub can be configured to support a number of Network connections (e.g. PSTN and ISDN) and/or user extensions.
Individual Hubs have an internal bus which can be connected together to expand the system, with interconnection being over distances of 0 to 300m. The user extensions can be a mix of 2B+D for the normal voice station with a simultaneous 64 kbps (low speed) data capability. And High Speed Extensions which directly support LAN workstations or a Voice Station/LAN Workstation combination.
The design target is to make the resources of one Hub accessible to other Hubs. Therefore, one Hub may have only Network connections which are utilised by all other connected Hubs.
Figure 1 shows a plan view of the topology 1.
Figure 2 illustrates "sideways" view of Figure 1. The Hubs are either on different floors, or on different parts of the same floor.
With reference to Figure 1 , the basic system (also called Topology 1) is made up from a number of Hubs.
Each Hub can support a mixture of Network and User connections. A Network connection provides for a connection to a Telecommunications Service Providers Network. Another term for "Network Connection" is "Interface to Network Equipment". A User Connection provides for a connection to User terminal equipment, also called "Customer Premises Equipment" (CPE). Another term for "User Connection" is "Interface to User Equipment".
Connection", or a SIT offering a service over an analogue or digital "User Connection". These are typically sources of CBR user traffic.
LAN interface to the computer. This combination provides the user with integrated LAN and phone capabilities. This combination is connected to the Hub via a System specific "User Connection". This is a source of mixed CBR and non-CBR user traffic. A server is connected to the Hub via a standard LAN "User Connection".
This scenario is identical to the previously described "Computer Connection". Similar to the prior phone/computer combination except that the computer provides an interface for the phone.
Hub #1 is shown with typical "Network Connections".
Hub #1 also shows the use of the standard LAN "User Connections" for connecting to existing company Local Area Networks.
This is a bussed/star, where the centre of the Network is a switch, see Figure 3. The bussed star approach is meant for larger systems and to introduce more reliability. The Hub may be an "Open Chain" "daisy chained" bus arrangement that is used by 53 octet ATM cells based upon (but not identical to) the CCITT UNI cell format.
Regarding Figure 3, the System can be expanded by using a Switching Hub to interconnect a number of Topology 1 systems.
A preferred physical architecture of the system is based on an Open Loop Chain. A Closed Loop chain is also disclosed herein.
This Open Loop Chain resembles a Daisy Chain in which each Node is interconnected via a Transmit Bus and a Receive Bus.
Receive Bus Input. • Information is transmitted and received in Cells (packets of a fixed size) consisting of 53 Bytes.
Cells are passed along the Transmit Bus and then along the Receive Bus.
In the case of the System, Nodes compete for an "Idle" or empty Cell.
A Cell is identified as "Idle" or "In Use" by the state of bit(s) in the Cell. • A "Cell Generator" is used to generate Idle (empty) Cells.
Cell use is dictated by the use characteristics noted above. The relative priority of each Node requiring access to Idle Cells is indicated to other Nodes upstream (towards the Cell Generator) by using any Cell passed along the Receive Bus.
Figures 4a and 4b show, inter alia, the basic backbone architecture of the system in the open chain configuration. The switch is shown as optional. The system provides a means of multiplexing various traffic from CBR and/or non- CBR services.
The 'backbone', each 'card' or 'node' as shown in figures 4a and 4b may represent a LAN network, hub or node of a communications system.
The idle cell generator in Figures 4a and 4b produces a continuous stream of fixed length idle cells. The transmitter modules multiplex active cells from their associated sources onto the backbone by replacing idle cells with active cells. Active cells arriving on the backbone inputs of the transmitter modules are relayed to their outputs, may be with an (implementation dependent) fixed delay. That is, a node in order not to overwrite data transmitted by other nodes, waits, until an idle cell arrives on its backbone input before writing over the idle cell to create an active cell.
A receiver module relays cells arriving on its backbone input to its output.
Those cells passing through a receiver module which are addressed to that module are copied into an internal buffer as they pass through; the cell remains active as it moves along the backbone and thus can be received by many receiver modules.
In the absence of some access protocol, each transmitter module does not have equal access to the backbone in times of heavy load. The first transmitter directly after the idle cell generator is able to transmit at any time since it is always receiving idle cells on it's backbone input. However, subsequent transmitters must wait for all transmitters between them and the idle cell generator to stop transmitting before they can do so. Effectively a priority queue system operates with transmitters ordered in decreasing priority the further away they are placed from the idle cell generator. This implicit priority mechanism is not always desirable (especially for non-CBR sources). PROTOCOL The request protocol further enhances the system of the present invention to traffic CBR and/or non-CBR signals because the protocol or a predetermined routine may be used to prioritise CBR and/or non-CBR traffic flow and access. REQUEST PROTOCOL DESCRIPTION REQUEST BIT PROTOCOL The system may utilise a request bit protocol to grant active transmitter modules access to the backbone (those with cells waiting to be transmitted). The protocol behaves as if a token which bestows access rights was passed cyclically from one active transmitter to the next, skipping inactive ones. Therefore all active transmitters can obtain an equal fraction of the backbone bandwidth.
In order to ensure small cell delay variation for CBR services, it is desirable that requests can be made on at least two priority levels. The desired effect is that the presence or absence of low priority traffic should not affect the access delay experienced by the high priority transmitters and that bandwidth be evenly shared among those active transmitters on a particular priority level. The CBR traffic (e.g. voice) may be assigned the highest priority and variable bit rate traffic a lower priority.
Note that the distinction between priority levels (1 ) and (2) is of lesser importance than between (2) and (3). It represents no increase in complexity however. Nodes send requests equal to their assigned priority level and a higher priority node may replace a lower priority request by overwriting the value of a request field in the cell header but may not overwrite higher priority requests.
Figure 5 describes the behaviour of each node in detail. Each node is initially in the REQUEST state indicating that it is able to send requests if there are any cells queued to be transmitted. Nodes must also be in the REQUEST state if they are to transmit any of the cells queued, otherwise they must let idle cells pass through their transmitters unused. As shown in the legend, the right pointing signal boxes represent cells arriving from or going to bus A (the transmitter daisy chain) and the left pointing signals represent cells arriving from or going to bus B (the receiver daisy-chain).
In the REQUEST state, if an idle cell is received on bus A, the node will transmit one of its queued cells in place of the idle cell, if it has one waiting, and then enter the FAIR state. The FAIR state indicates that the module is now waiting for other nodes on the same priority level to transmit before it attempts to transmit another cell. It therefore allows both idle and active cells to pass along bus A unchanged until a null request is received from bus B (one with a lower priority than its assigned priority, my_pri) whereupon it returns to the REQUEST state. In the REQUEST state, if a cell with a null request is received from bus B and the node has cells queued for transmitting, then the node will make a request by overwriting the request field with its assigned priority. If the req field in the received cell is greater than the assigned priority, the node will enter a PENDING state in order to stop it transmitting a cell. In this case the node will not modify the req field.
The node will remain in the PENDING state until a request is received of the same or lower priority as my_pri, indicating that any higher priority nodes have stopped requesting. The node will then immediately return to the REQUEST state, using the same request field to make its own request if it has cells queued. Note that in the PENDING state, as in the FAIR state, transmission of queued cells is suppressed and both idle and active cells are passed along bus A unchanged.
It is necessary for the operation of the protocol that the request bits default to the no request value (0) at the beginning of the receiver chain (bus B) - i.e. upon exit from the switch or at the loop-back point in figure 4a. In order to achieve this, the transmitter modules may be designed in such a way that the request field of cells passing through them is always cleared to the value (0).
In all states, a received cell is copied for use by the node if the cell has one or more specified addresses. In the case of CBR nodes assigned the highest priority, the state diagram can be simplified in two ways as shown in figure 6. First, the PENDING state can be deleted because there will be no higher priority requests since the nodes are assigned to top priority. Secondly, the FAIR state can be removed because there is not a requirement for bandwidth sharing among CBR sources since their bandwidth is naturally constrained. Nodes further to the right in figures 4a, 4b can still be assured sufficient bandwidth provided the sum of the individual CBR bandwidths does not exceed the backbone capacity. Nodes still need to make requests even though others on this highest priority ignore them because the lower priority nodes must be forced into the PENDING state to prevent them transmitting when the CBR modules have cells to send. REQUEST BUS PROTOCOL The request bus protocol is an alternative to the request bit protocol described above. It places backbone access requests on a hardware bus instead of using request bits in the cell header. An example is shown in Figure 12.
This protocol also behaves as if a token were passed cyclically from one active node to the next, skipping inactive ones. Therefore all active nodes enjoy an equal fraction of the backbone bandwidth.
There is no token but rather a bus on which each node broadcasts it's request to every other one that it wishes to send a cell. The request is a wired-or configuration which is pulled high with terminating resistors and each node makes a request by driving it low using an 'open drain' transistor. When a node has a cell to transmit, it drives the request bus low and waits for an idle cell to be passed to it from the previous node (or the idle cell generator if it is the first module in the chain). When it receives one, it immediately releases its request and transmits the cell. It then enters a 'fair' state, waiting until there are no more requests (i.e. for a rising edge on the request bus) before requesting to transmit any more cells it may have queued.
One advantage of the open chain approach is that it can implement the 'request bit' protocol for backbone load sharing. This has the advantage over the request bus protocol that it does not require a separate wire for the request bus. The open chain architecture requires 4 backbone connections per multiplexer device (each consisting of clock, sync and data wires) as opposed to two in the closed chain case.
The receiver access logic is also simplified as there is no need to de- activate cells as they are received. Indeed, since a time slot is only ever used by one transmitter, the access need not be any more complex than an OR gate. In the closed chain case, when a cell is received, it must be converted into an inactive (idle) cell by resetting the activity bit in the header. Otherwise, the cell would circulate indefinitely around the loop. This simplification also means that there will be less delay through each receiver because, in order for the receiver to decide whether or not to de-activate a cell, it must examine the MUX port address in the header. Thus the activity bit cannot be sent out until the MUX port address field has been received.
C) BROADCASTING AND MULTI-CASTING Broadcasting (transmission of cell to all modules of the system) is more simply implemented in the open chain architecture since, as stated above, receiver modules would not de-activate cells and hence information would pass through every receiver on a backbone anyway. If cell address matches one or more specified address, the node will copy the cell for its own use. To implement broadcasting in the closed chain case would require the broadcasting device to transmit to itself, causing a cell to pass all the way around the loop. A special broadcasting bit in the cell would have to be set to indicate to the other receivers that the cell was meant to be received by them as well. Multi-casting group (where a cell is transmitted to more than one, but not all, of the other receivers) would require additional bits (enough to provide a unique pattern for each group) in the header for the closed chain but could be simply achieved by using reserved addresses in the open chain case.
Duplication may be done at source or destination, and preferably the destination. In figure 7, we see that at the receiver a match has occurred between the incoming Celljd (Address) and the Celljd held in location 2 of a table, called the Active Connection Table, which holds specified addresses to be received. The index value, Buffjd = 2, from the Active Connections Table points to buffer 2 and the cell payload is thus stored there. This achieves the selecting and storing functions which are necessary to implement broadcasting and multicasting.
As applied to an ATM-TP device as an example of a node with a TDM interface at L1/N1 interface, the remaining operation is the mapping function which takes the user payload now stored in a buffer and writes this to the appropriate time-slot on the TDM highway. To do this requires a logical table which contains the Buffjd values associated with each timeslot. A feature of the invention is the manner in which control (signalling) cells can be handled in the same way as information cells. Hence a control cell logical address to be matched also appears in the Active Connections Table of figure 7. Figure 7 shows this output mapping where user information referenced by Buffjd = 2, in the example, is to be written to timeslots 0 and 2 in the TDM frame, thus achieving the multicasting function. Note also that if the Celljd to be matched occurs in more than one entry of the Active Connections Table (corresponding to a time slot number in the TDM frame), then the output mapping logical table is no longer required, thus simplifying the implementation.
A further advantage of the open chain arises when a switch is used because the switch introduces a problem for the closed chain. The problem, illustrated in figure 8, is that remote traffic from the switch output effectively has priority over local traffic because it doesn't have to request access to the backbone. This means that bursty remote traffic destined for receivers near the switch input can prevent transmitters near the switch output accessing the backbone. (Note that cell alignment has not been shown for clarity).
An advantage of the closed chain configuration is that, at least for full duplex CBR services, the contribution to the backbone bandwidth per connection is halved, because the forward and return paths occupy separate halves of the loop whereas in the open chain case, the forward and return paths both must pass along the same segment of the backbone. Also, with non-CBR, bursty data type transmissions, the average contribution to the backbone usage of every cell will only traverse half of the loop to reach its destination receiver whereas in the open chain case, it effectively travels to all receivers. This implies that to obtain the same performance, in both open. and closed chain configurations, the closed chain configuration would need only half the backbone bandwidth.
In order to quantify this effect, consider the following table which estimates the required backbone capacity for a fully configured system (3 motherboards) assuming every CBR source is active and all traffic is outgoing.
This number of active channels sums to a total of 20.4 Mbit/s for the open chain architecture but would only represent 10.2 Mbit/s on a closed chain architecture. Given that approximately 10-2 Mbit s would be enough bandwidth to support at least the proposed 24 high speed data terminals, the open chain architecture would call for a backbone rate of 30-40 Mbit/s, where the closed chain architecture may only require perhaps 20-30 Mbit/s. Since a 50 Mbit/s backbone is quite feasible with current techniques, this implies that both open a and closed chain architectures are feasible.
If a switch is introduced, the difference between open and closed chain capacities no longer applies since in this situation, all of the transmitters on any backbone could be sending to receivers on other backbones, and hence both open and closed chain architectures would require capacity equal to the sum of the transmitter rates.
An advantage of the closed chain is that fewer I/O pins are required for an implementation of the nodes and hence fewer backbone connector pins - particularly if the alternate input scheme is to be used to provide for live card insertion/removal. Fewer backbone connector pins is an advantage both because it reduces the cost of connectors and increases the reliability of the system. The following table lists the number of connections given various options. Note each backbone data connection requires 3 wires (clock, cell sync. and data), assuming clock recovery and cell delineation are used, and the request bus adds one extra pin.
Preferably, 4 wires are used for data, 1 for clock and 1 for cell sync. Another possibility, not considered so far, is that live card insertion could be implemented by having some very simple active logic on the backbone as shown in figure 11. The purpose of the gates in the clock and sync, lines is to equalise the delay introduced by the or gate. This scheme would require 8 backbone connector pins while providing live insertion. Another advantage of this technique would be that jumpers would not be required in unused slots. Also, if a card were to fail, then provided that it always produced zeros on it's data output, it would not affect the operation of the rest of the system. Disadvantages of the scheme would be the need for 2 extra chips per slot and a requirement that the skew between delays on any of these chips be very small because the skew could accumulate along the chain. This requirement would be satisfied if ECL or perhaps FACT CMOS chips were used.
Cells circulating in the system may be provided with an age bit in the header. By using an age bit in the header which is set each time it passes a specific point in the loop (probably the point where cell alignment is carried out), a Cell passing that point with the age bit already set - because it had passed that point before - would be discarded (de-activated).
In one particular form, "round robin" can be implemented in order to facilitate access to the system and in accordance with the characteristics noted above. In another particular form, the round robin feature may be implemented by a predetermined protocol to enable access to the system bus for a number of CBR and / or non-CBR sources. Cyclical access rights may be utilized from one transmitter to the next, preferably skipping inactive transmitters. This feature has been found applicable to the system embodiments disclosed in Figures 1 to 6 above.
This aspect relates to a communication protocol. The protocol is suitable for, but not exclusive to, the communication system disclosed above.
The present aspect is predicated on the discovery of a new protocol. A protocol includes, without limitation, a predetermined sequence of events, instructions and/or methods, an exchange of 'tokens' (e.g. cells), an agreed set of standards for the transfer of data, signals, commands, in accordance with a particular transmission speed, format and synchronisation to facilitate the transfer. The protocol, in one form, facilitates at one of the following desirable features: i) CBR and/or non-CBR without substantial degradation to the quality of service; ii) control of echo; iii) connection of interfaces to enable cell and/or packet traffic between a backbone structure and external devices; iv) recognition of internally and externally sourced cells; and/or v) connection of external cell sources, such as ATM terminals and ATM LANS, in particular, connection in a relatively cost effective manner. The present invention sees an external cell as a group of data that is sourced external to the backbone, from external network and/or user equipment as exemplified in Figure 1. The backbone to which the present protocol has application may be hub #2, for example. An external cell may also be a prior art protocol type, for example the CCITT UNI CELL of Figure 13. In figure 13, at GFC, coding is for FS. It is to allow multiple terminals to share a single interface. VPI/VCI use is negotiated between network and terminal, or VPI is negotiated and VCI is treated transparently by the network. PT is payload type, with a default setting of 00 for user information. RES is reserved field, and has a default setting of 0. CLP is cell loss priority field. If this field is not set to 1 , then the cell is subject to be discarded. HEC is header error control and is used to cover the entire header. It allows for single bit error correction and multi-bit error detection.
The present invention sees an internal cell as a medium or cell that can travel on the backbone. The present invention utilizes a format which enables prior art type cell formats to be at least partially incorporated in the present cell format and substantially reconstructed upon emergence from a backbone. This facilitates the ability of the present protocol to enable the provision of a communication system as exemplified in Figure 1 , which includes CBR and/or non-CBR data, whether in an external or internal format. The present format, in one form, alters or overwrites a portion of an external cell in order to facilitate CBR and/or non- CBR traffic in the communication system. Importantly, to one aspect, the present format utilizes a Req_Pri field for the trafficking of CBR and/ or non-CBR.
In other fields of the cell, the provision of fresh fields enables the present system to support CBR and/or non-CBR traffic without substantial degradation to the quality of service. In one form, the provision of fields A, Req-Pri facilitates this.
The location of the fresh fields in the internal cell such that they can overwrite the GFC field of the CCITT UNI CELL also provides further cost effective connection of external cell sources, such as ATM terminals and ATM LANS.
The present protocol also enables fully filled, partially filled or a mixture of the two cells. Partially filled cells have been found to provide a degree of control over echo.
The present protocol facilitates communication within and between the communication system and external devices. Figure 1 shows an exemplary system to which the present protocol is suited.
The following brief disclosure outlines one use of the present protocol with reference to Figures 4a and 4b where use of the protocol of the present invention facilitates interaction of a backbone with an externally sourced cell. The cell of the present aspect disclosed has many applications and thus should not, however, be so limited in its application.
An external cell having the format of the CCITT UNI CELL (for example) comes in the card via the interface to terminal and/or network equipment. The relevant information from the user and/or network equipment, including user and control information relevant to the externally coupled device(s), or connections that source the external cell(s), is passed to the node by the line interface module and the node dumps the user information into an internal cell, which then travels along the backbone to one or more designated nodes.
Meanwhile, additional information from the external cell, such as control information, header information relevant to the externally coupled devices or connections that sourced the external cell is passed to the cards control module via the line interface module where it may be sent, if necessary, as a part of the Communication System Control or signalling information, to the designated card(s) so that the external cell can be substantially completely reconstructed for re-emergence from the network or terminal interface, node or hub and continue onto its end destination. When the node has dumped the relevant user information into the internal cell, that cell travels to the destination card(s) where a reconstruction process occurs, and in one form, the user information is joined to the relevant control information to complete the external cell reconstruction for its re-emergence. The reconstruction of the cell is undertaken to a level appropriate for use of the reconstructed cell by an external user and/or network equipment.
Knowledge of the type of external cell that has entered the interface and that must be reconstructed can be sent with the internal cell. Additionally, or alternatively, the destination card may have prior knowledge of what type of cell is to be reconstructed by having knowledge of the type of network or terminal equipment coupled to the designation card.
In the case of an internal cell, and for example where the card is presented with CBR data, the CBR data will come into the line interface module and in an appropriate form (such as digital form) the CBR data will be presented to the node. The node can then dump that form into an internal cell for carriage on the backbone. The cell may be partially or fully filled depending on the need for echo control.
In the case of an internal cell, and for example where the card is presented with non-CBR data, such as an Ethernet connection which uses packets. The packet comes into the line interface and depending on the amount or size of the packet, and where the packet is larger than a cell, the packet is segmented, the segments are placed into internal cell(s) and passed along the backbone. For example, an Ethernet packet may be 1000 octets long, it is then chopped into 47 octet lengths (for example) and put into internal cell(s) and sent along the backbone. With regard to external cells and their headers, the present protocol may not use or may only partially use that header information, yet the header information must still re-emerge from the system to the external network or terminal equipment. Some of the header information or control information is passed along to the destination via our system of signalling channels and some of the header information is mapped to the present format and over written, if needed, in accordance with the protocol. A preferred embodiment of the present invention will now be disclosed with reference to Figure 14, where Active Bit, if set to 0, the cell is then an Idle Cell. If it is set to 1 , then the cell is an Active Cell. Req-Pri, if set to 00 is no request, if set to 01 is Burst_Pri, if set to 10 is not defined, and if set to 11 is CBR_Pri. Set_Nw, if set to 0, then the cell is a normal cell, and if set to 1 , then the cell is a Select JMow_Cell. FP_VPI, if >=190, then the cell will be routed to a switch port. Note that to have a backbone looped back by a switch, this field is set to the value of the Switch Port to which the backbone is connected. If < 190, then the cell is an ATM cell using VPI addressing and it will be accessed by any interface programmed to listen to a cell with this VPI. The values of 190 are arbitrarily chosen, but may be any other number if desired.
Further for CellJD/VCI, if the FP VPI >= 190, then this field is interpreted as being a channel identifier. That is, for one Cell IDE value, there can be up to 1024 active channels per backbone. By way of example, an ATM-TP can have a maximum of 18 active channels. These being 2 signalling channels (one specific and one broadcast) and 16 CBR channels (each mapping to a CBR buffer). The output of a CBR buffer may be mapped to one or more timeslots. For CellJD_E/VCI, if the FP VPI >= 190, then this field is used to extend addressing, if necessary. In one form, all ATM TP nodes will have a Cell IDE field set to one value, all ATM HP's will have another group of values, etc. If FP_VPI < 189, then this field is assumed to be a VCI field being used between communicating ATM terminals and is transparent to the backbone. Userjnd, if set to 1 indicates that the last octets of the SAR PDU are carried in this cell, and only if the Data_OAM element is set to 0. Cong is generally not used. Data_OAM is used as noted above. # is generally not used. HEC is an ATM Header Check Sum.
Given the detail of information above in relation to Figure 14, and the allocation of bits in the Cell, then the Cell as exemplarily disclosed allows for a. 32 backbones to a Switch and b. 1024 active channels per backbone per CellJDE value.
The embodiment is disclosed with reference to the prior art CCITT cell format of Figure 13 to highlight the differences and advantages of the present 5 cell format as disclosed in Figure 14.
Re-packaging the payload (Segmentation Assembly and Reassembly).
Replacement of "Standard" GFC Field with other information, including 20 activity bits.
Need to have a place in the cell for proprietary fields which are used for backbone access and bandwidth sharing management information carried in the cell without: 25 • Increasing the size of the cell.
• . Using parts of the cell which may be interpreted by ATM networks in some other way.
Daisy Chain Architecture, Request Protocol.
Possibility of connection to "standard" ATM networks at relatively lower cost than that which would otherwise result from putting proprietary LSP bits elsewhere in the cell.
The problem with placing the proprietary backbone access control bits in another part of the cell is that it would necessitate the extraction (ie as a cell enters our system from an external ATM network) and transportation through the system by some other mechanism, the replaced field, followed by its re-insertion into the cell (ie as it leaves our system) at the interface to another external ATM network.
Increasing the size of the cell.
Using parts of the cell which may be interpreted by ATM networks in some other way.
Effecting the payload format or amount of user data which can be carried in each cell.
Use the Active bit to indicate that the cell is used. This also tells interfaces to the system that bandwidth is available. 3.2.1. Cross Impacts Daisy Chain Architecture, Request Protocol.
Providing a "bandwidth available" indication to interfaces through standard use of the active bit. Also, A and Req-Pri fields mark each cell with its priority and activity and enable implementation of 3 characteristics as noted above in relation to A.
This implementation is accomplished by the utilisation of ATM technology in the system, in such a way that each node whether it is supporting CBR and/or non-CBR services is adapted to compete for idle cells. Cells enter the system, and flow through the system. CBR and/or non-CBR nodes may utilise the cells as required, and thus the system is able to traffic either CBR and/or non-CBR signals. In a most preferred form, the use of empty or idle cells is implemented in conjunction with an open chain architecture and/or a closed chain architecture.
The present invention is also predicated on the realization that information from CBR and/or non-CBR services is capable of occupying cells in a manner which is not fixed in advance. Dynamic bandwidth is one exemplary outcome of the above realization. The provision of dynamic bandwidth allocation facilitates the ability for user and control information to both use the same transmission medium.
"Standard" ATM network nodes use arbitrarily allocated assignments of the VPI fields and (if usual mode addressing is used) this also applies to the VCI field (which is then effectively an extension of the VPI field). IF "VPI addressing" is used in a "standard" ATM network then the VCI field is carried intact through the ATM network and completely disregarded from the purpose of routing.
A controller is necessary for each system switch (cost implications). • An appropriate protocol must be implemented to deal with addressing.
Because the switch is connected effectively as a series connection to our daisy chain at the loopback point, no information can be transferred between interfaces on any particular backbone until addresses of entities have been assigned. This impacts adversely on operation and maintenance strategies (eg fault self-diagnosis) of the system.
Use the FP_VPI field in a dual mode. One mode assigns a separate fixed significance in terms of the intended destination switch port (ie destination backbone) to each value used. This means that for the routing of all cells within the system (except where the system is supporting more than one interface to external ATM networks and where such results in the requirement for transportation of "standard" VPI addressed cells from one ATM network interface to another) the FP_VPI field value preferably determines the destination backbone of any cells. The allocation of physical significance applies to a range of values of FP_VPI, which the system design reserves for this purpose.
The switch controller (which would now be required for this purpose) will be able to allocate (or have allocated) any previously unassigned FP_VPI values outside the range referred to above, to any required destination backbone (even though such a backbone could still otherwise be accessed using its "permanent" corresponding FP_VPI value).
Cost saving in system switch in all applications including those where the system has multiple interfaces to "standard" ATM networks which do not support "VPI Addressing".
This is achieved without adding to the complexity of the "standard" ATM network interface and also without additional complexity being required for the system Signalling (IMP) Protocol.
The solution is to partition the field into two sub fields (<CellJd> and <CellJd_E>) and keep the value of <CellJd_E> constant for the most commonly occurring services (ie constant bit rate and signalling). The process of cell selection at each channel of each interface can then, after rejection of cells whose FP_VPI values and <CellJd_E> do not meet the required value for the backbone in question (and this can be performed once for all channels being serviced by each interface device), simply be that of selection on the basis of <Cell Jd> value.
. Ensuring that the header field has not been corrupted by the network. . Cell delineation (ie finding the beginning of a cell when there is no specific separate signal which indicates this).
This HEC is not necessarily used for internal cells. Thus, the solution is firstly to ensure that switching of paths in the system backplane (ie for O&M purposes) does not introduce errors into the header of any used cells. (This is where the Select_Now bit can be used to mark cells which may be corrupted by path switching so that they are never used.) This means that the probability of cell header corruption (or more the point, the possibility that a cell with a corrupted payload or length due to path switching will be used or accepted as valid by some interface) becomes insignificant. The HEC field may be provided in external cells, but is not used in the present system open/closed architectures.
. The generation and checking of the sequence numbers has an associated cost. The cell delay variation in the system is bounded due to the LSP and, as a consequence, the occurrence of lost and misinserted cells are simply detectable by other means. However, if sequence number generation is to be reduced for all but connections via external ATM networks then it is desirable that it be made as easy as possible to insert sequence numbering at any standard ATM network interface and still gain some cost advantage.
. The packetisation delays associated with the accumulation of 47 voice samples when packetisation occurs in both the send and receive directions within the system produces an unacceptable echo delay performance when voice calls are made over networks which have significant delay, or where regulatory requirements require a lower voice echo delay performance of the cpe in all and/or private network applications.
The advantages achieved are respectively as follows: . Simplification of Reassembly hardware at each CBR channel receive end. . Improvement (by a factor of approximately 3) in echo delay performance for the system use of partial cells can enable control of echo. . Provision of full cells, partially filled cells, or a mixture of 47, 16 octet payloads. This facilitates accommodation of the 3 system characteristics noted above.
. Hardware simplifications also result.
The following section provides a functional description of each element. 1 -3.1 <A> Active Functional Element This element distinguishes active (information carrying) cells (when value is <Active_Cell>) from idle (empty) cells (when value is <ldle _Cell>).
<No_Req> is the default state of this element and indicates no Requests are being made.
Access for the purposes CBR payload transmission.
This element defines the destination Switch Port of a cell. This is intended to be used as a form of "fixed" Switch Port designation.
This element designates with what Priority a Cell must be transported to the Switch Port designated by <S_PortJD> in terms of either Normal Priority or CBR Priority.
The combination of <Cell_ld> and <CellJd_E> together are used as a 5 destination endpoint designator within a backbone. They are separated for ease of use (see §3.1.2.1 and §3.1.2.2).
This is provided for use by external ATM terminals wishing to pass cells through the system (ie CCITT or ATM Forum standard) when using VPI 10 addressing. It is passed through the system unchanged.
The Payload Type functional element contains three functional elements, including the <UserJnd> element which is described below. It is used only in association with cells carrying a <Ctrl_Payload>, ie system IMP protocol 15 signalling cells. Its use by the system for other purposes is not defined. The value of this element will not be changed for Cells passing through the system from one external ATM endpoint to another.
Used as described in §1.3.6.3. Otherwise use of this field internally by the 20 system is not defined.
The following defines in more detail (where required) the coding of the respective fields shown.
221 Control Field This consists of a Activity, Req_Priority and a Select_Now fields.
The FP_VPI field is carried by Octet 1 Bit 4 (most significant bit) to Octet 2 Bit 5.
The FP_VCI field is carried by Octet 2 Bit 4 (most significant bit) to Octet 4 Bit 5 and comprises the following sub-fields.
Octet 5 is reserved for this purpose. Coding is as per CCITT Standard.
223. Payload Field This is the last 48 octets (Octets 6 to 53) in the Cell.
Active bits) for every Cell generated.
The following section describes the use of address fields by the system Layer 1 when operating with only system equipment (ie interfaces and Switch).
Note that to cater for ATM cells with VPI addressing the switch would have to have additional intelligence which would allow it to map a VPI against a port as well.
All interfaces on a backbone will expect that any Cells for destination end points connected to this backbone, other than external ATM terminals (see §3.2.2), will have one of the <FP_VPI> field values according to the table in §3.2.1 above and will not accept any others.
In the case of an ATM network interface, where the connection requires Virtual Channel Switching, the interface will translate the ATM standard VPI. VCI address field of cells headed toward the system to a system Layer 1 <SP><Cell_ld><CellJd_E> value. The converse will apply for Cells headed in the opposite direction.
In the case of an ATM network interface, where the connection requires Virtual Path Switching, the interface will not necessarily translate the ATM standard VPI address field and will not modify the VCI field of cells passing through the interface. Since the transportation of such cells through the system is assumed to be servicing ATM terminal endpoints external to the system at both ends of the connection, the system ATM interface modules will need to have virtual path switching (filtering of cells based only on VPI field value) capability.
If such a connection is via a system switch, then the required VPI value and associated path through the switch will need to be set up in the switch's connection table. It is assumed that the VPI values used will not conflict with the range of values set aside for <SP>. If such a value was allocated by an ATM network interfaced to the system then the interface would need to translate the VPI field value so that an system switch unit would not incorrectly route the cells.
A number of embodiments of interfaces will now be described with reference to the accompanying drawings.
Although one of the disclosures relates particularly to a type of node for CBR signals (ATM-TP node), the disclosure (in principle and also by way of embodiment) equally applies to a node for CBR and/or non-CBR signals (ATM- HP node). In the case of ATM-HP, CBR and/or non-CBR signals may be packetized internal or external of the node.
The functional model of the ATM-TP (see Figure 15) provides Transmit and Receive interfaces to an ATM reticulator (reference RP) as well as a Microprocessor Bus interface (reference PDU1 ) and a multiplexed 64 Kbit Terminal Highway interface (reference L1/N1 ).
Essentially the ATM-TP provides the functions of the Physical Layer, ATM layer and the SAR and the CS sublayers of the AAL Layer of the B-ISDN Protocol Reference model (see CCITT Rec. 1.321) at any interface module on the ATM backbone (with the possible exception of the Ethernet Interface). The model provides AAL type 1 function at the L1/N1 interface and ATM Layer functionality at the PDU1 interface.
Rate cells, iii FPDX-1 inter-module signalling.
The following subsections describe the primary functions of each component shown on the functional model of the ATM-TP (see Figure 15). The format of the descriptions for each component consists of a functional summary in text, followed by an explanation of the output signals generated by each block.
The information received on the DATRXI inputs consists of a continuous stream of ATM cells structured in the format described in the section entitled Logical Cell Structure Definition.
3.2.2. Output To The Layer Manager The Hdr_Alarm signal marks the occurrence of the detection of a corrupted cell header.
All received ATM cells are forwarded to the Load Sharing Protocol.
3.2.4. Output To The ATM Cell Header Extractor All received ATM cells are forwarded to the ATM Cell Header Extractor.
The function of the NON-CBR LSP component is described in detail in the section entitled Request Protocol Description - Request Bit Protocol. Primarily, it provides bandwidth sharing on the ATM backbone by controlling the output of local signalling cells (ie Ctrl_Cells) onto the backbone. The built-in priority mechanism guarantees bandwidth for CBR traffic sources when bandwidth demand of both CBR and Non-CBR traffic sources exceeds the maximum bandwidth of the ATM backbone.
3.3.1. Ouptut to CBR Load Sharing Protocol All ATM cells received from the ATM Cell Receiver Input component are output to the CBR LSP component, however the Req_pri field of the cell header may be modified depending on whether there are local signalling cells (ie Ctrl_Cells) awaiting transmission.
DATTXO outputs unchanged, except for the case where the NON-CBR LSP has requested and is awaitng an idle cell, in which case the idle cell is consumed and replaced by a local Ctrl_Cell.
The function of the CBR LSP component is described in detail in the section entitled Request Protocol Description - Request Bit Protocol. Primarily, it provides bandwidth sharing on the ATM backbone by controlling the output of local CBR cells onto the backbone. The built-in priority mechanism guarantees bandwidth for CBR traffic sources when bandwidth demand of both CBR and NON-CBR traffic sources exceeds the maximum bandwidth of the ATM backbone. From a system point of view the CBR LSP components ensure small cell delay variation for CBR services leading to smaller receive buffer queue sizes.
All ATM cells received from the NON-CBR Load Sharing Protocol are forwarded to this component, however the Req_pri field of the cell header may be modified depending on whether there are local CBR cells awaiting transmission.
All ATM cells from the ATM Cell Transmitter Input component are output to the NON-CBR LSP component unchanged except for the case where the CBR LSP has requested and is awaitng an idle cell, in which case the idle cell is consumed and replaced by a local CBR_Cell.
The function of this component is to recompute and replace the header checksum (HEC) into the header of each cell and output to the ATM backbone all ATM cells received from the CBR Load Sharing Protocol component.
The received ATM cell is forwarded to the Payload Distributor.
10 Destination Controller (PDC) to command the Payload Distributor to either intercept or discard a cell.
The PDC maintains a list (of 18) entries in a table called the Cell Address Table where each entry (referred to by its Index value) comprises a FP_VPI.FP_VCI value of a desired virtual channel and an associated Buffjd 15 value which identifies one of the 17 cell receiver buffers (ie. 16 CBR buffers and 1 Control Channel buffer) internal to the ATM-TP into which the cell payload (or in the case of the Control Channel Buffer the entire cell) is to be loaded.
PDC to generate a buffer identifier which results in the cell being discarded by the Payload Distributor.
The Buff_Addr signal carries the Buffjd value which identifies one of the 25 16 CBR buffers or the Control Channel Buffer. In the case where an ATM cell needs to be discarded it provides a default value indicating a null or dummy buffer.
The Dist_Buff signal carries an entry of the Cell Address Table referred to 0 above.
Channel Buffer, the PD forwards the entire 53 byte ATM cell (ie Ctrl_Cell) to the Control Channel Buffer without removing the ATM Cell Header, c) Discarding Cells. ATM Cells are discarded whenever the Bufferjd value identifes the dummy buffer.
CBR_Payloads are sent to the SAR type-1 components.
This component strips off the 1 byte SAR Type-1 header field (as defined in CCITT Rec. I.363, §2.3.1.2) from the CBR payload as well as any padding. The header contains Sequence Number and Sequence Number Protection fields and the need to process these (ie for CBR cell loss recovery procedures) is For Further Study (FFS).
The main functions are: a) Assembly of SAR Type-1 PDU payloads (which may be 47 bytes or 16 bytes long depending on the cell Fill_Size) into a single 64Kbps CBR stream. b) Buffering for cell latency. c) Perform functions which ensure that there is something to transmit out to the L1/N1 interface in the case where the receive buffer underflows. For late cell arrivals, this may mean the injection of dummy payloads into the respective receive buffer and discarding the late payload on arrival. d) As a reference channel of an aggregated group of channels, issue the necessary timing signals to the slave channels of the aggregation (which may reside locally or on a remote ATM-TP device) in order to synchronise reception of cells. e) As a slave channel of an aggregated group of channels, perform a), b) and c) as defined above in synchronisation with the reference channel.
3.9.1. Output to the CS PDU Multiplexer The CBR_Byte signal is used to transfer the Byte parameter whose value is the byte value at the head of the receive buffer (ie the oldest element in the FIFO).
(ie Byte_Value) into up to 16 of the 32 timeslots of each frame of the TDM output. It directs (if the relevant B-Channel Assembler is enabled) the contents of the buffer in each B-Channel Assembler component to one of the timeslots one byte at a time. The set of timeslots (which 16 of the 32) serviced by the B-Channel Assemblers depends on the TS_Mode value similarly to that in the CS PDU De- Multiplexer. Timeslot information for a particular timeslot is sourced from a receive buffer belonging to one of the 16 B-Channel Assembler components.
The READJ3UFF signal is sent to a B-Channel Assembler to fetch a byte of timeslot information. The B-Channel Assembler returns a copy of the byte at the head of its buffer. This signal may be sent a maximum of 32 times per TDM frame period depending on the values in the mapping table.
Contig : Timeslots 0 thru 15 are mapped to Segmenters 1 thru 16 respectively. Contig_2: Timeslots 16 thru 31 are mapped to Segmenters 1 thru 16 respectively. Spaced: Timeslots 0,1 are mapped to Segmenters 1 and 2 respectively. Timeslots 4,5 are mapped to Segmenters 3 and 4 respectively.
Timeslots 8,9 are mapped to Segmenters 5 and 6 respectively. Timeslots 12,13 are mapped to Segmenters 7 and 8 respectively. Timeslots 16,17 are mapped to Segmenters 9 and 10 respectively. Timeslots 20,21 are mapped to Segmenters 11 and 12 respectively. Timeslots 24,25 are mapped to Segmenters 13 and 14 respectively.
This block controls each of the 16 CBR B-Channel Segmenters in two ways. Firstly, it provides a signal to a segmenter to change its segmentation process each time a new cell fill_size (fill_size may be 16 or 47 bytes) is allocated for the segmenter. Secondly, it issues periodic signals to each B- Channel Segmenter causing them to generate SAR-PDU payloads with the correct amount of fill. These actions result in a "smooth" (ie segmenters allocated the same cell fill_size do not simultaneously generate ATM payloads) stream of ATM payloads to flow from each of the SAR Header Adders towards the ATM CBR Cell Header Adders ensuring low backbone access and hence low Cell Delay Variation for the system.
Second device, whereupon the First device's FrNumMod47 counter is set to zero and the Second device's FrNumMod47 counter is set to 46. This creates an effective 1 TDM frame delay of the stagger pattern of the Second device with respect to the First device. The mechanism whereby this is achieved is by delaying (ie while waiting in the SCP_SYNC_OUT and SCP_SYNC_IN states respectively) the startup of the FrNumMod47 counters in both devices until the First device has sent an SC_SYNC message to the Second device which occurs between the receiving of the first and second F_SyncJn messages occurring in the First device.
An SC_SYNC message is sent from the First device's SCP to the Second device's SCP via the Layer Manager.
3.14. B-Channel Segmenter This component buffers the incoming CBR stream for a particular B- channel and breaks it into 47 or 16 byte (depending on Fill_Size) SAR PDU payloads and then generates the payload. Its timing is controlled by the Stagger Controller which determines when the Segmenter should send a SAR Payload. 3.14.1. Output to SAR Header Adder A SAR type 1 PDU payload is generated towards the SAR Header Adder.
This component adds the SAR PDU Header (in this case a dummy byte), and in the case of Fill_Size = 16, appends 17 dummy Octets, to form a 48 octet cell payload creating a CBR_Payload which it then forwards to the ATM CBR Cell Header Adder.
3.15.1. Output to the ATM CBR Cell Header Adder See 3.16 below.
3.16.1. Output to CBR Load Sharing Protocol component A stream of CBR cells.
Figure 39 shows the high speed terminal architecture. In figure 39, the open chain architecture is shown - all of the transmit sections are connected in a chain connected to the input of the main equipment and all of the receive sections connected to the output. This is the most appropriate configuration for the terminal as all of the traffic generated by the terminal will be sent to the main equipment and so would not have to compete with traffic coming from the main equipment as it would if the transmit and receive sections were mixed as with the 'closed chain' scenario. Only idle cells should be passing around the loopback section of the transmission path.
The transmission line driver and clock recovery functions would be performed by commercially available chips (for example primary rate ISDN or twisted ethernet chips as discussed in the section on the main equipment module could be used). Similarly standard voice codec chips would be used. The larger of the dashed boxes represents the functionality that this terminal has in common with the low speed extension (LSPX) and would conceivably be implemented on one chip. The type 1 (continuous bit rate) SAR functions is considerably less complex than the corresponding type 3/4 module needed for the ethernet port and would thus be easily integrated with other functions on the chip. Synchronous 64kbit/s clock recovery could be performed by deriving the clock from the backbone clock rate (which would have to be an integral multiple of 64kbit/s). The clock labelled 'simple register control unit' would consist of a single register storing the state of each function of the telephone handset. Control of every feature (LED's, ringer, LCD, buttons, receiver hook etc.,) of the handset would be centralised in the main processor. Whenever a feature of the station had to change state (e.g. turn on an LED), a signalling cell could be sent to the key station by the CPU and the cell would be latched into the register, each bit of the cell controlling the state of one feature.
The mechanism of staggering is, in one form, a mechanism in which all the CBR sources (at least all the sources which are using the same fill factor) at each interface, generate cells at regularly spaced intervals. In addition to this, the adoption of a further mechanism of bit reversal channel numbering ensures that when an interface is only partially equipped (e.g. has only 4 or 8 channel sources but uses a 16 channel interface device), the generation of cells is more optimally spread in the cycle (where cell generation otherwise might be bunched in a manner of 4 or 8 consecutive intervals then 12 or 16, respectively, intervals with no cells transmitted). This further reduces the cell delay variation.
Cell delay variation could also be reduced by increasing the system bandwidth well beyond that which is occupied by the total CBR traffic (and this excess bandwidth may virtually all be used for non-CBR traffic). The use, however, of staggering, partial/mix cells and bit reversal channel numbering has been found to dramatically reduce this requirement.
A preferred embodiment will now be described, with reference to a key communication system adapted to traffic both CBR and non-CBR signals, the subject of co-pending application(s) filed by the present applicant. It is contemplated that the present invention has application in a wide variety of communication systems, adapted to traffic only CBR or non-CBR, or both CBR and non-CBR signals, and should thus not be limited only to the following example. Even if there is enough bandwidth available on the system backbone for the CBR traffic, it is possible that a CBR transmitter may have to wait some time for an idle slot to become available before it is able to send a cell. CBR sources, 65 the (worst case) burst at the beginning of the cycle is equal to the number of 64 kbit/s channels that are active as one cell is generated per channel per metaframe. Hence we can calculate the maximum access delay given the backbone bandwidth, the number of active channels on a backplane and the overhead per cell (due to headers and padding for partially filled cells). Let T^, be the length of a backbone timeslot, R be the backbone bit rate and Nch be the number of active 64 kbit/s channels. Then, = 424/R, and t^ = Nch.424/R since there are 424 bits in a cell. Figure 18 shows a plot of calculated access delay values for both this (non staggered) case and one of the other staggering schemes to be discussed below.
Local staggering, as stated before, is where the segmenters in a particular module generate their cells at evenly distributed points in the metaframe. Note that (at least on a single source device) the cell generation times can only fall on certain instants within the metaframe because the segmenters receive octets of information once each 125 μs frame. Since by definition a cell is generated once the last octet of data has been collected in the buffer, the cell generation times must fall on one of the octet arrival times. The number of arrival times in a metaframe is equal to the number of information-carrying octets of the cell, L^i, since the metaframe length = L^, x (125μs).
The upper diagram in figure 4 shows a local staggering scheme where each source device generates cells at times within the metaframe separated by 3 TDM frames. The arrows represent the arrival times of cells from each of the segmenters in the device. Notice that since there are 47 TDM frames in a metaframe and this is not a multiple of 3, the spacing at the end of the metaframe is only 2 frames. This discontinuity represents a slight increase in the instantaneous arrival rate at that point, and causes a maximum in the graph of cells waiting, though not as severe as when all cells are generated at the beginning of the metaframe as in the non-staggered case.
Cells arriving from two devices are shown to illustrate the fact that two devices can be paired so that they interface to a single 32 channel TDM highway 66 in the system. In this case the devices may be expected to have a fixed phase relationship because they are effectively behaving as one device. The optimal relationship for these two devices is shown in the lower half of the figure 19. Here the discontinuities mentioned in the previous paragraph for the two devices are separated as much as possible across the metaframe in order to allow the system to recover from them as much as possible before the next one.
In the staggering schemes above, when an source module only uses a small number of the available channels these have been assumed to be numbered consecutively from channel 0 (e.g. the PSTN card only uses channels 0-8). This means that the phases of these channels are not spread as evenly across the metaframe as they could be. In fact they are separated by only 3 TDM frames when they could be separated by a greater amount since there is less than 16 channels. If the channel numbers were not allocated consecutively, then the (worst case) burst at the beginning of the cycle is equal to the number of 64 kbit/s channels that are active as one cell is generated per channel per metaframe. Hence we can calculate the maximum access delay given the backbone bandwidth, the number of active channels on a backplane and the overhead per cell (due to headers and padding for partially filled cells). Let T^, be the length of a backbone timeslot, R be the backbone bit rate and Nch be the number of active 64 kbit s channels. Then, tteto, = 424/R, and t = Nch.424/R since there are 424 bits in a cell. Figure 18 shows a plot of calculated access delay values for both this (non staggered) case and one of the other staggering schemes to be discussed below.
Local staggering, as stated before, is where the segmenters in a particular module generate their cells at evenly distributed points in the metaframe. Note that (at least on a single source device) the cell generation times can only fall on certain instants within the metaframe because the segmenters receive octets of information once each 125 μs frame. Since by definition a cell is generated once the last octet of data has been collected in the buffer, the cell generation times must fall on one of the octet arrival times. The number of arrival times in a metaframe is equal to the number of information-carrying octets of the cell, L∞n, since the metaframe length = L^,, x (125μs).
Cells arriving from two devices are shown to illustrate the fact that two devices can be paired so that they interface to a single 32 channel TDM highway in the system. In this case the devices may be expected to have a fixed phase relationship because they are effectively behaving as one device. The optimal relationship for these two devices is shown in the lower half of the figure 19. Here the discontinuities mentioned in the previous paragraph for the two devices are separated as much as possible across the metaframe in order to allow the system to recover from them as much as possible before the next one.
In the staggering schemes above, when an source module only uses a small number of the available channels these have been assumed to be numbered consecutively from channel 0 (e.g. the PSTN card only uses channels 0-8). This means that the phases of these channels are not spread as evenly across the metaframe as they could be. In fact they are separated by only 3 TDM frames when they could be separated by a greater amount since there is less than 16 channels. If the channel numbers were not allocated consecutively, then a better spread could be found. For example, if only two channels are required, then channels 0 and 7 could be chosen instead of 0 and 1.
Notice that the spaces between the already allocated numbers are successively divided in half as new numbers are added in between. Figure 21 shows this numbering scheme applied to the non-offset staggering scheme.
16 octets. This results in a 16x(125μs) metaframe period as well as increasing the backbone bandwidth required by these connections by a factor of approximately 3. The staggering pattern for 16 channel ATM-TDM modules using the 16 possible positions in this metaframe is shown in figure 23.
We have so far considered the cases where the information field contains either 16 or 47 octets (i.e. partially filled and full cells). We have noted that the access delay variation for partially filled cells can be made equal to or less than that for full cells provided that the backbone bandwidth is approximately 3 times that for full cells. Only certain long distance voice calls would need to have the packetisation delay reduced by partially filling cells. In one form, it would appear that the bandwidth could be more efficiently used by using partially filled cells only for those calls. We consider here worst-case the performance of a system employing a mixture of 16 and 47 octet cells.
Mixing two cell fill values gives rise to two metaframes of different lengths, one 16 TDM frames long and another 47 frames long. Since 3 of the 16 frame metaframes is one frame longer than the 47 frame metaframe, during the length of a call, the 16 frame metaframes will phase slip with respect to the 47 frame ones and hence every relative phase will have occurred after 47 of the larger metaframes has passed. Therefore it is unlikely to ensure a favourable phase relationship between two segmenters using 16 and 47 octet cells and the worst case phase relationship must be considered, even when the segmenters are in the same source module. A worst case situation would be where those channels using the 16 frame metaframe are grouped together and the remaining channels are grouped together in the 47 byte metaframe around frames 45 and 0 (which are closer together than the other points in the 47 frame metaframe). This would result in the maximum burst of cell arrivals and hence the longest busy period. Figure 25 shows the worst case described above in a module with 16 channels active. In modules with less than 16 channels active, a similar process is used to determine the worst case except that the worst case separation in the staggering pattern is 3 frames instead of 2 since channel 15 is assumed not to be active.
The performance of the above worst case mix of traffic is plotted in figure 26 for both consecutive and bit reversal channel numbering. As can be seen better performance can be obtained when only 16 octet cells are employed. This implies that where a large percentage. of the traffic consists of partially filled cells, it is preferable to use partially filled cells for all channels. (Where 87 channels are using full cells and 258 are using partially filled cells, so 258/345 = 75% of the input traffic consists of partially filled traffic). In situations where only a small number of channels are using partially filled cells, it may be preferable to use a mix, however.
The performance of the differing staggering schemes can be summarised by quoting the backbone bandwidth required to ensure access delay variation is less than 1 ms given the offered load of a fully configured system as described in table 2. The total offered traffic is 345x64 kbit/s = 22Mbit/s. Given the header overhead of 53/47, this translates to 24Mbit/s. For partial filled cells with an overhead of 53/16 it corresponds to 73Mbit s. Note that 1 ms may be too great in the presence of a 'switch' which may contribute an additional component of cell delay variation as well and so that the access delay variation would need to be decreased by reducing the load on each switch port.
16 byte cells only when most of the traffic is using the 16 byte cells. Therefore, the combination is considered most effective in systems where the bulk of devices are using 47 byte cells and a few delay sensitive channels are using 16 byte cells.
A preferred embodiment of the present invention will now be described. The example is made with reference to a system as shown in Figure 4a, for exemplary purposes only. In the system shown, there is provided a n x 64 kbit/s TDM channel, where n = 2 to 32, thus allowing 2.048 Mbit/s streams. The present invention nevertheless is adapted to channels of any band width. The streams are preferably CBR, but the invention is found to equally apply to CBR and/or non-CBR signals. The following embodiment is made with reference to CBR services, without meaning to exclude application of the present invention to non-CBR or CBR/non-CBR services. Channel aggregation in accordance with the present invention provides the ability to carry a group of nx64 kbit/s TDM channels from source to destination as if they were a single nx64 kbit/s channel thus allowing a system or device in which the present invention is implemented for exemplary purposes to carry up to 2.048 Mbit/s CBR streams. The set of n channels (n=2 to 32) is referred to as an aggregate group.
All of the octets in an aggregated group may be carried over a single ATM connection as shown in figure 29. Preservation of the order of octets is provided because they are placed in the cells in particular order and the order of arrival of cells is substantially preserved by the system.
This implementation advantageous enables direct CBR-ATM connections to operate in this way. This can imply easy interworking between these two types of interfaces over one ATM connection as shown in figure 30. Reduced packetisation delay resultant from the following technique may also be provided advantageously. The packetisation delay is the time it takes to fill up a cell with input date. In this technique, the packetisation is reduced by a factor of n (where n is the number of channels in the group) because the input date rate is increased by a factor of n. This may be the most significant of the advantages, particularly in the case of large aggregated groups.
A single buffer for the aggregated channel would be also preferably be required. The required size of this buffer may increase with the total bit rate of the aggregate channel (for a given access delay variation). The length of the segmentation buffer is given by: Lb-jf = Lcβii + r.tacc where tacc is the access delay and r=nx64 kbit/s is the rate of the aggregated channel and Lce)| is the length of the cell. This is calculated in the exemplary system to be L^ + 8 octets when tacc = 1 ms and r - 64 kbit/s. With an aggregated channel, however, r could be up to 2.048 Mbit/s or more, and the buffer would need to be LCθn + 32x8 octets = Lcβn + 256 octets. To allow this amount of additional space in every buffer would represent a significant increase in the total buffer space (if L^n - 47 octets, then 311 octets would be required vs. 55 octets for non-aggregated channels). One possibility to reduce this increase in space would be the grouping together of several buffers by providing more complex control (especially if the buffers were not consecutively located in the memory block). Also, the system card may be split into two 16 channel devices operating in parallel.
The same buffer sharing would also be encountered at the receiver end, except that the buffer size is: uf = Lceii + 2r.tCDV Bits where tCDV is the cell delay variation (consisting of the access variation tacc and any other variable cell delay component such as switch buffer delays). Since the maximum value of tCDV is also 1 ms, the maximum buffer requirement would be Lee,, + 2x32x8 = Lee,, + 1024 octets where it would only be L^,, + 2x8 = Lce,| + 16 octets for a single channel.
A more preferred approach to the problem is to use a separate ATM connection per 64 kbit/s channel within the aggregated group, instead of using a single ATM cell stream for the whole aggregated group as described in figure 31. This would be the same situation as when the channels were not aggregated but just happen to be going to the same output. The only difference is that it is necessary to make the delay experienced by each of the channels equal to the same number of frame periods in order that the octets from one input frame arrive at the same output frame. This would not be guaranteed in the normal case because the end-to-end delay is dependent on the arrival time of the first cell in each of the channels, as this is used to determine the start of the reading out of information in the smoothing buffer (re-assembly). Since the delay of the first cell in each channel may differ by several frame periods, some special provision may be required for aggregated channels. A way of providing that the end delays in a group are substantially equal is to reference the start of re-assembly for each channel to the arrival of a cell in one channel only out of the group instead of starting each re-assembly process independently. [The arrival of the first cell, along with a knowledge of the maximum cell delay variation, may be used in the re-assembly process to determine the appropriate start time for the read clock on the smoothing buffer such that the buffer will not under-flow].
Ignoring the use of staggering initially it can be seen from figure 32 that use of a single 'referenced channel' to determine the start time will ensure the same delay between the generation of the cell payloads in each ATM stream and their subsequent playing out at the output. Since the cells (in this non-staggered case) are generated at the same instant, the range of possible arrival times will be the same for each channel. (In the figure, the delay for ATM cells is assumed to range from 0 up to the maximum cell delay variation, tCDV, although in practice there would be a fixed delay component also). Thus any channel out of the group could be used as the reference for the start time of the read clocks in all of the channels without fear of the buffers in any of the channels either underflowing or overflowing.
(a) The TDM channel numbers for the input group would be chosen (possibly fixed by the hardware connections on the TDM bus).
Segmentation in these channels would be started in the usual way by signalling to the microprocessor controlling the input ATM-TDM interface.
(b) One of the channels would be designated as the reference channel and the staggering offset for each of the slave channels in the group would be calculated relative to the reference channel using the channel numbers and a knowledge of the staggering pattern.
(c) The slave channels in the output card would be set up in the normal way except that they would be programmed with a fixed offset for their re-assembly start times relative to the reference channel start time. This could be achieved by inserting a number of dummy fill octets in the smoothing buffers equal to the offset into each of the slave channels and starting the receive clocks for each of them when a pulse is received from the reference channel indicating that it had started re-assembly. Slave channels would discard any cells received before the reference channel had started re-assembling.
(d) The reference channel would then be set up at the receiver. It would wait for the arrival of the first cell and start re-assembly at a time tCDV after the arrival of the first cell in the normal way. Once it started re-assembling, it would send a pulse to each of the slave channels.
With reference to figures 35 to 37, basic chain architectures are shown. Any of the architecture shown are exemplary only to illustrate how the by-pass architecture of the present invention can be provided in a communication system.
In general, the by-pass feature allows for the by-pass of a connected card and / or node, provision of externally controlled ioopback, backplane bus overflow error indicator, resynchronization to the master clock, selectable master clock (e.g. from backplane or local card), lower clock speed (preferably <=80MHz), and significant capacity (preferably 320Mbps). With reference to figure 35, each of cards 1 , 2 and 3 have a transmit (TX) bus and a receive (RX) bus. Empty, idle or cells having user or control information therein flow on the TX and RX busses, when the system is in use.
If, for example, card 2 fails, in accordance with the present invention, by- pass busses A and B can be brought into service (manually or automatically, switched). In bringing busses A and B into service, transmit and receive bus outputs of card 2 are isolated from the system as a whole, thus enabling the system (other than card 2) to operate otherwise normally with the addition of busses A and B. Any particular terminal equipment or networks coupled to card 2 may remain 'down' for a period of time until card 2 is again fully operational.
Alternatively, the card 2 coupled equipment or networks may be otherwise connected to another card (manually or automatically, switched). In this alternative, although card 2 is not operational, terminal equipment or networks usually coupled to card 2 may access the system via other cards.
Busses C and D, likewise, enable card 1 to be by-passed, and in Figure 36, bus C needs only to be implemented to by-pass card 1.
Busses A, B, C and D may be implemented by way of a suitable cable or optical connection, track or other suitable transmission medium. In figure 36, the interface modules may be provided on or coupled to a mother board.
In a similar manner to the open chain of figures 35 and 37, by-pass busses E or F serve to provide an alternate coupling between cards, thus enabling one card to be isolated, if necessary, without substantially hindering performance of the remainder of the system. Cards 1 , 2, 3 and 4 are denoted by broken lines. In this closed implementation, approximately half the amount of by¬ pass busses are required.
The switch to implement by-pass operation in one form may be triggered by use of cells flowing in the system. A 'by-pass' maintenance cell may be generated periodically, and if not passed through the system or if corrupted by the system, may trigger cards immediately downstream of the suspect card to switch to its by-pass buss(es) so that the suspect card is then by-passed. If a card is to be replaced, for example for maintenance, substantially without corruption of cells flowing in the communication system, the operation of a by-pass architecture as noted above can be modified to reduce corruption of cells during the switching operation. This may entail the provision of a switch operation synchronisation circuit, which when armed by command from a local μP, causes the switch to change within the payload period of a synchronisation cell designed particularly to enable switch operation with minimal cell loss or corruption.
As a synchronisation cell passes to one card, that card may be switched to its transmit by-pass bus. The synchronisation cell may continue on the system transmit bus, and return on the system receive bus. When the synchronisation cell is received by another downstream card, switch operation to the receive by¬ pass bus can be made.
Implementation of idle cells in accordance with the characteristics disclosed to various systems, including small business customer switching systems and LAN networks, provides a technology base which can be used far into the future. Cost effectiveness and flexibility may be provided, in part, by integration of control and user data.
- interactive, conversational - time constrained conversational - 0.2 - 2 Mbps "Medical: Mag.
1. A communication system adapted to traffic CBR and / or non-CBR.
2. A communication system as claimed in claim 1 , where the CBR and / or non-CBR is trafficked without substantial degradation to the quality of service.
3. A communication system as claimed in claim 1 , comprising an open or closed architecture.
4. A communication system as claimed in claim 1 , further including means for determining access to the system in accordance with a round robin access.
5. A method of enabling CBR and / or non-CBR services to utilise or operate a communication system, the method comprising the characteristics of: a. group contention resolution, b. priority, and c. bandwidth allocation.
6. A method as claimed in claim 5, wherein the communication system is the system of claim 1.
7. A cell adapted for use in a communication system, the cell including a Req_Pri bit for a priority indication of the cell.
8. A cell as claimed in claim 7, further including an activity bit (A) indicating whether the cell is in an active or idle state.
9. A cell substantially in accordance with a CCITT UNI CELL, the improvement comprising overwriting the GFC field with information indicating activity and / or priority status of the cell.
SUBSTTTUTE SHEET (Rule 26) 10. A communication system adapted to utilise the cell of claim 7, 8 or 9.
11. A method of echo control for use in a communication system, the method comprising providing a degree of control over the fill of cell(s) or the use of partially filled cells for trafficking information within the system.
12. A method of substantially reducing access delay to a communication system, the method comprising staggering between channels which have access to the system.
13. A method as claimed in claim 12, wherein the staggering is provided by forcing a fixed phase difference between different sources.
14. A method of reducing differential delay of a plurality of bit streams placed on at least a first interface and emerging from at least one second interface of a communication system, the method comprising enabling more than one bit stream to be carried within a given cell.
15. A communication system incorporating a backbone, the backbone having a by-pass means enabling, if desired, cells to bypass a particular point or connection to the system.
16. A CBR interface node as herein disclosed.
17. A non-CBR interface node as herein disclosed.
ES2306514T3 (en) 2008-11-01 integrated voice and data over a local area network communications.

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