Source: https://www.eee.hku.hk/people/nwong/
Timestamp: 2019-04-19 19:04:36+00:00

Document:
VLSI model reduction, digital filter design, Sigma-Delta converters, antenna array, semidefinite programming and optimization techniques. Dr. N. Wong received his B.Eng. (first class honor) degree in 1999 and Ph.D. degree in 2003, both in Electrical and Electronic Engineering from The University of Hong Kong. From Jan 2003 to Sep 2003, he was a visiting scholar at the Purdue University, IN, USA, where he investigated VLSI related topics. From 1997 to 1998, he was a product engineer in Motorola Semiconductor Hong Kong Ltd. under an internship program, where he worked on mixed-signal IC design and circuit testing. His research interests include digital filter design with delta operator, filter optimization, Sigma-Delta modulator design and analysis, and the application of semidefinite programming in communication systems and VLSI synthesis. His current research focuses on VLSI model order reduction for computer-aided design, and the corresponding algorithmic development and electrical network synthesizing techniques.
N. Wong and T. S. Ng, “Fast detection of instability in sigma-delta modulators based on unstable embedded limit cycles,” IEEE Trans. Circuits Syst. II, vol. 51, pp. 442-449, Aug 2004.
N. Wong, V. Balakrishnan, and T. S. Ng, “A second-order cone bounding algorithm for robust minimum variance beamforming,” Lecture Notes in Computer Science, Springer-Verlag GmbH, Volume 3355, Pages 223-247, Jan 2005.
N. Wong, V. Balakrishnan, C.-K. Koh, and T. S. Ng, “A Fast Newton/Smith Algorithm for Solving Algebraic Riccati Equations and Its Application in Model Order Reduction,” in Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, vol. 5, 2004, pp. 53-56.
N. Wong and V. Balakrishnan, “Fast Balanced Stochastic Truncation Via A Quadratic Extension of the Alternating Direction Implicit Iteration,” in Proc. Int. Conf. Computer Aided Design 05, 2005, pp. 801-805.
N. Wong and V. Balakrishnan, “Quadratic Alternating Direction Implicit Iteration for the Fast Solution of Algebraic Riccati Equations,” in Proc. Int. Symposium on Intelligent Signal Processing and Communication Systems, 2005, pp.373-376.
N. Wong and C.K. Chu, “A Fast Passivity Test for Descriptor Systems Via Structure-Preserving Transformations of Skew-Hamiltonian/Hamiltonian Matrix Pencils,” in Proc. Design Automation Conference (DAC) 2006, pp. 261-266.
N. Wong and V. Balakrishnan, “Multi-Shift Quadratic Alternating Direction Implicit Iteration for High-Speed Positive-Real Balanced Truncation,” in Proc. Design Automation Conference (DAC) 2006, pp. 257-260.
S. Ma, N. Wong, and T.S. Ng, “Time Domain Equalization for OFDM Systems,” in Proc. IEEE Int. Symp. Circuits and Systems 2006, pp. 3946-3949.
N. Wong, V. Balakrishnan, C.-K. Koh, and T. S. Ng, “Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2062-2075, Oct 2006.
A.Y.H. Ho, C.U. Lei and N. Wong, “A common subexpression sharing approach for multiplierless synthesis of multiple constant multiplications,” AENG Engineering Letters, 2007, 15(1): 149-156.
C.U. Lei, C.M. Cheung and N. Wong, “Efficient 2D linear-phase IIR filter design and application in image filtering,” IAENG International Journal of Applied Mathematics, 2007, 37(1): 56-63.
N. Wong and V. Balakrishnan, “Fast positive-real balanced truncation via quadratic alternating direction implicit iteration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 1725-1731.
Q. Chen and N. Wong, “An efficient stochastic integral equation method for modeling the influence of conductor surface roughness on interconnect ohmic loss,” Proc. Midwest Symp. Circuits and Systems (MWSCAS), 2007, 1417-1420.
Y. Liu and N. Wong, “Passivity-preserving model order reduction of linear time-varying macromodels,” Proc. Intl. Conf. on ASIC (ASICON) (invited paper), 2007.
C.W. Ng, N. Wong and T.S. Ng, “Tri-level bit-stream signal processing circuits and applications,” Proc. Intl. Conf. Signal Processing and Communications Systems (ICSPCS 2007), 2007.
D.C.W. Ng, W.Y.T. Wong , N. Wong, K.W.H. Wan and D.K.K. Kwong, “A low-power high-output-driving CMOS voltage reference with +/-5% trimming accuracy,” Proc. Intl. Conf. Microelectronics (ICM), 2007.
W.K. So, W.T. Cheung, Y. Liu, H.K. Kwan and N. Wong, “Design and optimization of highly linear CMOS low noise amplifiers via geometric programming,” Proc. Intl. Conf. on ASIC (ASICON), 2007.

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