Source: https://patents.google.com/patent/US7730335B2/en
Timestamp: 2019-04-25 13:22:53+00:00

Document:
This application is related to U.S. patent application Ser. No. 10/779,544, which was filed on Feb. 13, 2004 and U.S. patent application Ser. No. 10/865,368, which was filed on Jun. 10, 2004, both of which are hereby incorporated by reference in their entirety.
wherein transistors of said secondary processor are operated at greater than approximately 80% duty cycle.
wherein transistors of said secondary processor are operated at greater than approximately 90% duty cycle.
wherein said secondary processor executes a restricted-feature operating system during said low power mode.
wherein said restricted-feature operating system is executed by said secondary processor during said low power mode.
wherein said full-featured operating system is executed by said primary processor during said high power mode.
a CPU level for data said primary processor or said secondary processor.
wherein said volatile memory level corresponds to data in said primary volatile memory during said high power mode.
wherein said volatile memory level corresponds to data in said secondary volatile memory during said low power mode.
wherein said volatile memory level corresponds to data in said embedded secondary volatile memory during said low power mode.
11. The processing device of claim 3, wherein said full-featured operating system and said restricted-feature operating system share a common data format.
wherein said LP nonvolatile memory includes flash memory or a low power disk drive having a platter with a diameter less than or equal to 1.8″.
wherein said secondary processing means includes switching means for switching and operating at greater than approximately 80% duty cycle.
wherein said secondary processing means includes switching means for switching and operating at greater than approximately 90% duty cycle.
wherein said secondary processing means executes a restricted-feature operating system during said low power mode.
storing a restricted-feature operating system, which is executed by said secondary processing means during said low power mode.
storing a full-featured operating system, which is executed by said primary processing means during said high power mode.
wherein said second cache means communicates with said primary processing means.
wherein said processing device employs a cache hierarchy comprising HP nonvolatile memory level for data in HP nonvolatile storing means, a LP nonvolatile memory level for data in LP nonvolatile storing means, a volatile memory level that corresponds to data in one of said primary volatile storing means and said secondary volatile storing means, a second level for data in second cache means, a first level for data in first cache means, and a CPU level for data in at least one of said primary processing means and said secondary processing means.
wherein said volatile memory level corresponds to data in said primary volatile storing means during said high power mode.
wherein said volatile memory level corresponds to data in said secondary volatile storing means during said low power mode.
wherein said volatile storing memory level corresponds to data in said embedded secondary volatile storing means during said low power mode.
23. The processing device of claim 15, wherein said full-featured operating system and said restricted-feature operating system share a common data format.
wherein said LP nonvolatile storing means includes flash storing means for storing data or a hard disk drive including a platter having a diameter less than or equal to 1.8″.
storing data using a cache hierarchy comprising a high power (HP) nonvolatile memory level for data in a HP nonvolatile memory, a low power (LP) nonvolatile memory level for data in a LP nonvolatile memory, a volatile memory level that corresponds to data in one of the primary volatile memory and the secondary volatile memory, a second level for data in a level two cache, a first level for data in a level one cache, and a CPU level for data in at least one of said primary processor and said secondary processor.
28. The method of claim 27, wherein said primary volatile memory communicates with said primary processor or said secondary processor, wherein said volatile memory level corresponds to data in said primary volatile memory during said high power mode.
wherein said LP nonvolatile memory includes at least one of flash memory or a low power disk drive having a platter with a diameter less than or equal to 1.8″.
wherein said primary graphics processor and said secondary graphics processor are operated respectively in said high power mode and said low power mode based on at least one of space available on said LPDD, reception of a data storing request, and reception of a data retrieving request.
wherein said first process has smaller feature sizes than said second process.
a secondary processor that communicates with said secondary graphics processor and operates during said low power mode.
35. The processing device of claim 32, further comprising primary volatile memory that communicates with said primary graphics processor during said high power mode and with said secondary graphics processor during said low power mode.
38. The processing device of claim 34, further comprising a processing chipset that communicates with said primary processor and said primary graphics processor during said high power mode and with said secondary processor and said secondary graphics processor during said low power mode.
39. The processing device of claim 34, further comprising an I/O chipset that communicates with said secondary processor and said secondary graphics processor during said low power mode.
40. The processing device of claim 32, wherein transistors of said primary graphics processor are operated at less than approximately 20% duty cycle and transistors of said secondary graphics processor are operated at greater than approximately 80% duty cycle.
41. The processing device of claim 32, wherein transistors of said primary graphics processor are operated at less than approximately 10% duty cycle and transistors of said secondary graphics processor are operated at greater than approximately 90% duty cycle.
wherein said primary graphics processing means and said secondary graphics processing means are operated respectively in said high power mode and said low power mode based on at least one of space available on said LPDD, reception of a data storing request, and reception of a data retrieving request.
secondary processing means for processing data, that communicating with said secondary graphics processing means, and operating during said low power mode.
45. The processing device of claim 42, further comprising primary volatile storing means for storing data, communicating with said primary graphics processing means during said high power mode, and communicating with said secondary graphics processing means during said low power mode.
secondary volatile storing means for storing data and communicating with said secondary graphics processing means during said low power mode.
wherein said secondary volatile storing means is embedded in said secondary graphics processing means.
wherein said processing chipset communicates with said secondary graphics processing means and said secondary graphics processing means during said low power mode.
49. The processing device of claim 44, further comprising an I/O chipset that communicates with said secondary processing means and said secondary graphics processing means during said low power mode.
wherein said secondary graphics processing means includes switching means for switching and operating at greater than approximately 80% duty cycle.
wherein said secondary graphics processing means includes switching means for switching and operating at greater than approximately 90% duty cycle.
55. The method of claim 52, further comprising using primary volatile memory that communicates with said primary graphics processor during said high power mode and with said secondary graphics processor during said low power mode.
using secondary volatile memory that communicates with said secondary graphics processor during said low power mode.
using secondary volatile memory that is embedded in said secondary graphics processor during said low power mode.
58. The method of claim 54, further comprising using a processing chipset that communicates with said primary processor and said primary graphics processor during said high power mode and with said secondary processor and said secondary graphics processor during said low power mode.
59. The method of claim 54, further comprising using an I/O chipset that communicates with said secondary processor and said secondary graphics processor during said low power mode.
wherein said second operating system is executed by said secondary processing device during said low power mode.
63. The processing device of claim 62, wherein said first operating system is a full-featured operating system and said second operating system is a restricted-feature operating system.
65. The processing device of claim 63, wherein said full-featured operating system and said restricted-feature operating system share a common data format.
66. The processing device of claim 32, wherein said secondary graphics processor is deactivated in said high power mode.
wherein said LUB is transferred from said LPDD to said HPDD in said high power mode.
68. A processing device as in claim 67, wherein said primary graphics processor is deactivated in said low power mode.
wherein at least one of said secondary processor and said secondary graphics processor is directly coupled to said processing chipset.
70. The processing device of claim 69, further comprising an I/O chipset that communicates with said secondary processor and said secondary graphics processor during said low power mode.
71. The processing device of claim 70, wherein said I/O chipset communicates with said secondary processor and said secondary graphics processor over a peripheral component interconnect (PCI) bus.
wherein transistors of said primary processor are operated at a first duty cycle and transistors of said secondary processor are operated at a second duty cycle that is greater than said first duty cycle.
73. The processing device of claim 1, wherein said transistors of said primary processor are operated at less than approximately 20% duty cycle when in said high power mode and transistors of said secondary processor are operated at greater than approximately 80% duty cycle when in said low power mode.
74. The processing device of claim 69, wherein said processing chipset is distinct from said secondary processor and said secondary graphics processor.
75. The processing device of claim 70, wherein said processing chipset is distinct from said I/O chipset.
"How to increase virtual memory in XP", Mar. 25, 2002, Retrieved from: http://www.computing.net/answers/windows-xp/how-to-increase-virtual-memory-in-xp/20067.html [Online].
Communication from the European Patent Office dated Oct. 11, 2006 with the European Search Report for Application No. 05010993.3-1245; 3 pages.
Communication from the European Patent Office dated Oct. 11, 2006 with the European Search Report for Application No. 05010993.3—1245; 3 pages.
Communication from the European Patent Office dated Oct. 6, 2006 with the partial European Search Report for Application No. 05010992.5-1245; 5 pages.
Communication from the European Patent Office dated Oct. 6, 2006 with the partial European Search Report for Application No. 05010992.5—1245; 5 pages.
Communication from the European Patent Office dated Oct. 9, 2006 with the European Search Report for Application No. 05010994.1-1245; 3 pages.
Communication from the European Patent Office dated Oct. 9, 2006 with the European Search Report for Application No. 05010994.1—1245; 3 pages.
U.S. Appl. No. 10/779,544, filed Feb. 13, 2004; Entitled "Computer WIth Low-Power Secondary Processor and Secondary Display".
U.S. Appl. No. 60/678,249, filed May 2005, Yang.
U.S. Appl. No. 60/799,151, filed May 2005, Sutardja et al.
U.S. Appl. No. 60/820,867, filed Jul. 2006, Sutardja et al.
U.S. Appl. No. 60/822,015, filed Aug. 2006, Sutardja et al.
U.S. Appl. No. 60/823,453, filed Aug. 2006, Sutardja et al.
U.S. Appl. No. 60/825,368, filed Sep. 2006, Sutardja et al.
U.S. Application Entitled "Adaptive Storage System", filed Jun. 10, 2004.

References: Application No. 05010993
 Application No. 05010993
 Application No. 05010992
 Application No. 05010992
 Application No. 05010994
 Application No. 05010994