Source: http://dtsheet.com/doc/93229/ad-5962-9559701mpa
Timestamp: 2019-04-23 18:32:21+00:00

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3 mV or less and distortion in the clamp region is minimized.
This product can be used as a classical op amp or a clamp amplifier where a high and low output voltage are specified.
AD8037’s recover from 2× clamp overdrive within 1.5 ns.
driving as well as buffering flash and high resolution ADCs.
diverse applications which can be designed with input clamps.
in plastic DIP and SOIC; MIL versions are packaged in cerdip.
CLAMPIN is a trademark of Analog Devices, Inc.
See Max Ratings and Theory of Operation sections of data sheet.
Nonlinearity is defined as the voltage delta between the set input clamp voltage (VH or V L) and the voltage at which V OUT starts deviating from VIN (see Figure 73).
Measured at A V = 50.
Measured with respect to the inverting input.
Specific ations subject to change without notice.
The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature.
conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
8-Lead Cerdip: θ JA = 110°C/W.
Connect Substrate to –VS .
Figure 2. Plot of Maximum Power Dissipation vs.
Figure 17. AD8036 Open-Loop Gain and Phase Margin vs.
Figure 61. AD8036/AD8037 Clamp Input Bias Current vs.
of signal and noise peaking.
Applications section. In applications that do not require clamping, Pins 5 and 8 (respectively VL and VH) may be left floating.
wide bandwidth, low parasitic peaking, and fast settling time.
(see Closed-Loop BW plots, Figures 15 and 27).
AD8037 is due to a unique, proprietary design architecture.
VO ≤ 3.5 V p-p).
least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended.
damping resistor ≈4.7 Ω for optimum results.
ground in order to maintain stability.
is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 70. The accompanying graph shows the optimum value for RSERIES vs.
6 pF or less, no RSERIES is necessary.
voltage on VL and ignore +VIN.
for VH = 1.0 V.
versatility of the clamp inputs.
in that A1 is optimized for closed-loop gains of two or greater.
only affects A1’s noninverting input.
+1 and VH = +1 V.
(actual) is typically 18 mV times the amplifier closed-loop gain.
for the connection just described, VOUT should track +VIN perfectly up to +1 V, then should limit at exactly +1 V as +VIN continues to +2 V.
VH, for VH > 1 V, will be faithfully reproduced at VOUT.
VL would need to be set to +0.333 V and –0.333 V, respectively.
all three voltages be within the supply voltage range. For example, if VL is set at –3 V, then VIN should not exceed +3.3 V.
*Amplifier offset is assumed to be zero.
and VL can go above ground as long as VH is kept higher than VL.
applied to Pin 8) and a lower voltage set by VL (the voltage applied to Pin 5).
where the offset voltage can be summed in as one of the inputs.
Since AD8036/AD8037 clamping does not function in the inverting mode, it is not possible to clamp with this configuration.
A/D converter and illustrates some of the considerations for using an AD8037 with offset and clamping.
Where VOFF is the offset voltage that appears at the output.
for optimum performance of the AD8037 at a gain of two.
must be biased at +0.55 V while VL must be biased at –0.55 V.
The analog input range of the AD9002 is from ground to –2 V.
the AD8037 a prime candidate for signal conditioning.
input of the AD9002 (output of AD8037).
pins VH and VL and ground to ensure stable operation.
pulses at the output up to 24 V p-p with 2500 V/µs slew rate.
–12 V to +12 V.
drives VL, the lower level clamping input. The high level clamping input, VH, is left floating and plays no role in this circuit.
the high or low logic levels passing through a linear amplifier.
with high speed edges should be used.
output level to be 10 times the voltage at VL.
functions when they are driven dynamically.
effectively produces an offset as explained above, but with a dynamic level that is equal to –1 times the input.
positive, dynamic voltage in this case). The factor of two is because the noise gain of the amplifier is two.
20 MHz and amplitude ± 1 V, see Figure 80.
gain inverting amplifier and to VL, the lower clamping input.
VH is biased at +0.5 V dc.
noise gain of the circuit is two.
of the input by applying the input to VH instead of VL.
as an amplitude modulator as shown in Figure 81.
the offset voltage by the modulation signal being applied to VL.
these two effects, which produces the lower envelope of an amplitude modulated waveform. See Figure 82.
high and low levels. This is the higher frequency carrier signal.
the amplitude of the upper and lower envelope waveforms.
lower envelope waveforms stay constant, but the spacing between them changes. This alters the ratio of the envelope amplitude to the amplitude of the overall waveform.
AD8037 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic component selection are mandatory.
area near the input pins to reduce stray capacitance.
minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance.
characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end.
serve as a guide for a board layout.

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