Source: https://patents.google.com/patent/US8645688B2/en
Timestamp: 2019-04-22 08:37:17+00:00

Document:
This application is a continuation of U.S. application Ser. No. 12/455,844, filed on Jun. 8, 2009, entitled “SYSTEM AND METHOD FOR EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION” which claims priority to U.S. application Ser. No. 11/096,618, filed on Mar. 31, 2005, entitled “SYSTEM AND METHOD FOR EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION” which issued on Jun. 9, 2009, as U.S. Pat. No. 7,546,457, and claims priority to U.S. application Ser. No. 10/112,169, filed on Mar. 29, 2002, entitled “SYSTEM AND METHOD FOR EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION” which issued on Jun. 27, 2006, as U.S. Pat. No. 7,069,442.
The chipset 240 may contain a pair of registers, “EXISTS” register 270 and “JOINS” register 272. These registers may be used to verify that the ILP and all of the RLPs are responding properly to the SENTER BUS MESSAGE. In one embodiment, chip set 240 may keep track of all operational logical processors in the system by writing a “1” into the corresponding bit of the EXISTS register 270 on any system bus transaction made by that logical processor. In this embodiment, each transaction on system bus 230 must contain an identification field containing the logical processor identifier. In one embodiment, this consists of a physical processor identifier and an indentifier for the hardware execution thread within each physical processor. For example, if a thread executing on processor 222 caused any bus transactions on system bus 230, chipset 240 would see this logical processor identifier within the transaction and write a “1” into the corresponding location 286 within EXISTS register 270. During the secure launch process, when that same thread on processor 222 sends its ACK message on system bus 230, the chipset 240 would also see this and could write a “1” into the corresponding location 288 in the JOINS register 272. (In the FIG. 2 example, each physical processor is shown with only a single thread executing for clarity. In alternate embodiments the physical processors may support multiple threads, and thereby multiple logical processors.) When the contents of the JOINS register 272 matches the contents of the EXISTS register 270, then chipset 240 can set an ALL_JOINED flag 246 indicating that all processors have properly responded to the SENTER BUS MESSAGE.
In another embodiment, EXISTS register 270 and JOINS register 272 may continue to aid security subsequent to the setting of the ALL_JOINED flag 246. During the time subsequent to the setting of the ALL_JOINED flag 246 until the end of trusted or secure operations, chipset 240 may continue to monitor and compare bus cycles against the JOINS register 272. During this period, if chip set 240 ever sees a bus transaction from a logical processor that is not currently identified in JOINS register 272, then chipset 240 may presume that this logical processor has somehow “appeared” late. This would imply that such a logical processor did not participate in the secure launch process, and therefore could represent an attacker (security threat). In such circumstances, chip set 240 may respond appropriately to keep this attacker out of the secured environment. In one embodiment, chipset 240 may force a system reset in such circumstances. In a second embodiment, similar detection of a “late” processor may be achieved by each logical processor asserting a special reserved signal on the system bus on every transaction following the assertion of the ACK bus message. In this embodiment, following the setting of the ALL_JOINED flag 246 if the chipset 240 observes a bus transaction initiated by a processor without the special signal asserted, then chipset 240 may again presume that this logical processor has somehow appeared “late”, and may represent an attacker.
Meanwhile the ILP, in block 724, moves the public key of the chipset and the memory-resident copy of SINIT-AC into its own secure memory for secure execution. The ILP, in block 726, uses the key to validate the secure-memory-resident copy of SINIT-AC, and then executes it. The execution of SINIT-AC may perform tests of the system configuration and the SVMM copy, then registers the SVMM identity, and finally begins the execution of SVMM in block 728. As part of actions performed in block 728, the ILP SINIT code may configure device-access page table 248 and device-access logic 247 of memory and chip set to protect those memory pages used by the memory-resident copy of SVMM 282 from interference by non-processor devices, as shown in block 754.
wherein the initialization includes verification of a secure virtual machine monitor and beginning of secure virtual machine monitor operations.
2. The processor of claim 1, wherein the special bus transactions include a first special bus transaction to be responded to by responding logical processors with a non-maskable internal event.
3. The processor of claim 2, wherein the responding logical processors are to terminate current operations, send an acknowledge special bus transaction, and enter a wait state in response to the first special bus transaction.
4. The processor of claim 2, wherein the bus transaction logic is also to poll a flag to confirm that an other processor has properly responded to the first special bus transaction.
5. The processor of claim 4, wherein the special bus transactions include a second special bus transaction to signal that secure operations are going to be initiated.
6. The processor of claim 1, wherein the special bus transactions are to transfer information to support initialization of the secure system environment.
7. The processor of claim 6, wherein the information includes a key.
9. The method of claim 8, wherein the special bus transactions are to transfer information to support initialization of the secure system environment.
10. The method of claim 9, wherein the information includes a key.
11. The method of claim 8, wherein the special bus transactions include a first special bus transaction to be responded to by responding logical processors with a non-maskable internal event.
12. The method of claim 11, wherein responding logical processors are to terminate current operations, send an acknowledge special bus transactions, and enter a wait state in response to the first special bus message.
13. The method of claim 11, including polling a flag to confirm that an other processor has properly responded to the first special bus transaction.
14. The method of claim 13, wherein the special bus transactions include a second special bus transaction to signal that secure operations are going to be initiated.
a second processor to respond to a first special bus transaction by terminating current operations, sending an acknowledge special bus transaction, and entering a wait state.
16. The system of claim 15, wherein the first processor is also to poll a flag to confirm that the second processor has properly responded to the first special bus transaction.
17. The system of claim 15, wherein special bus transactions also include a second special bus transaction to signal that secure operations are going to be initiated.
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