Source: https://patents.google.com/patent/US8081516B2/en
Timestamp: 2019-04-21 20:33:27+00:00

Document:
With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results from fringing fields that occupy the gaps that separate the neighboring charge storage structures. The fringing electric fields are suppressed, by the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide, from entering the neighboring charge storage structures. In some embodiments, the insulating structures suppress the fringing electric fields from entering a channel region. This suppresses the short channel effects despite the small dimensions of the devices.
The present application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 61/142,324, filed on Jan. 2, 2009; the entire contents of which is incorporated herein by reference.
The present application relates to the field of nonvolatile NAND memory, and particularly to nonvolatile NAND memory having a 60 nm pitch or less.
With 90 nm design rule cells, a NAND nonvolatile memory storing charge on floating gates has the problem of parasitic capacitance between the floating gates of neighboring cells in the NAND nonvolatile memory. A solution to this problem of parasitic capacitance between neighboring floating gates, is the use of air spacers between the floating gates of neighboring cells of the NAND nonvolatile memory. This solution is discussed in, for example, US Patent Application Publication 2008/0283898, which cites Daewoong Kang et al., “Improving the Cell Characteristics Using Low-k Gate Spacer in 1 Gb NAND Flash Memory”, 2006 International Electron Devices Meeting, Technical Digest, December 2006, all of which are incorporated by reference.
NAND nonvolatile memory has advanced with the use of charge trapping material such as silicon nitride, to replace the floating gate. The floating gate is heavily doped polysilicon, a highly conductive equipotential material. In contrast with the floating gate, a charge trapping gate such as silicon nitride is a dielectric, and not a highly conductive equipotential material. Because charge trapping NAND nonvolatile memory does not rely on floating gates to store charge, charge trapping NAND nonvolatile memory does not have parasitic capacitance between neighboring floating gates. Accordingly, charge trapping NAND nonvolatile memory does not need air spacers between neighboring cells of the NAND nonvolatile memory, to address parasitic capacitance between neighboring floating gates.
The paper by Kang et al. discloses a memory cell with an aspect ratio, or ratio of gate height to channel width, of about 1. Because of the relatively wide trench between neighboring memory cells, this paper discloses the necessity of many steps to form an air gap between neighboring memory cells.
Another NAND nonvolatile memory advance is the continued scaling of size. NAND nonvolatile memory at sub-20 nm and sub-30 nm sizes have been successfully fabricated and characterized. Hang-Ting Lue et al., “Scaling Evaluation of BE-SONOS NAND Flash Beyond 20 nm”, 2008 Symposium on VLSI technology, Digest of Papers, June 2008, incorporated by reference. At these sizes and lower sizes, techniques such as double patterning can be applied to manufacture NAND nonvolatile memory. Yi-Shiang Chang et al., “Pattern Decomposition and Process Integration of Self-Aligned Double Patterning for 30 nm Node NAND FLASH Process and Beyond”, Optical Microlithography XXII, Proceedings of the SPIE, Volume 7274, pp. 72743E-1-72743E-8, 2009; Huixiong Dai et al., “Implementing Self-Aligned Double Patterning on Non-Gridded Design Layouts”, Proceedings of the SPIE, Volume 7275, pp. 72751E1-72751E-11, 2009; Andrew J. Hazelton et al., “Double patterning requirements for optical lithography and prospects for optical extension without double patterning”, J. Micro/Nanolith. MEMS MOEMS, Vol. 8, pp. 011003-1-011003-11, 2009; all incorporated by reference.
Analysis results presented herein show that charge-trapping NAND Flash beyond the sub-30 nm node suffer various interference disturbs. Edge fringing field due to bias voltages applied to adjacent word lines is a major factor effecting device performance not only in the initial cell characteristics but also in the programming/erasing efficiency. Analysis results show that, beyond the sub-20 nm node, devices with an oxide spacer between wordlines have more than a 2V VT shift with a word line bias of 7V. In addition, the interference from programmed charge in adjacent devices is less than 200 mV in the sub-30 nm node.
The low-k spacer described herein suppresses the edge fringing field and results in improved performance. In addition, the low-k spacer is also shown to confine the E-field within the bottom tunnel dielectric of the memory cell, which can further improve programming/erasing efficiency. As a result, the memory cells described herein can be implemented for the 20 nm node and below, including for the 15 nm node and below.
An aspect of the technology is an integrated circuit memory device, comprising a semiconductor body, charge storage structures, gates, and insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide.
The charge storage structures are arranged in series on the semiconductor body, and are separated by insulating structures. The charge storage structures include dielectric charge trapping locations beneath the gates. The charge storage structures including a tunnel dielectric structure disposed above the semiconductor body, a charge storage layer disposed above the tunnel dielectric structure, and an insulating layer disposed above the charge storage layer.
The gates are arranged in series and control the charge storage structures beneath the gates. In some embodiments, the gates have an aspect ratio greater than 3, the aspect ratio being equal to a ratio of a height of the gates to a channel width between neighboring gates.
In some embodiments, the gates are positioned sufficiently close together, such that in response to one or more of the gates having a pass gate voltage, the gates having the pass gate voltage have fringing electric fields that occupy most of at least one of the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the pass gate voltage.
The fringing electric fields are suppressed, by the insulating structures occupied by the fringing electric fields, from entering the neighboring charge storage structures. In some embodiments, the insulating structures suppress the fringing electric fields from entering a channel region. This suppresses the short channel effects despite the small dimensions of the devices.
In some embodiments, in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the insulating layer of the charge storage structures beneath the gates having the programming gate voltage, are suppressed by the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the programming gate voltage. In some embodiments, fringing fields adjacent to at least the tunnel dielectric structure portion of the insulating layer are suppressed. In some embodiments, due to this suppression of fringing fields adjacent to at least the tunnel dielectric structure, the tunnel dielectric structure has a lateral voltage variation from the fringing fields of no more than a volt between a center of the tunnel dielectric structure and an edge of the tunnel dielectric structure.
The insulating structures are covered by various structures in various embodiments. In one embodiment, a polymer thin film caps the insulating structures and the gates, and the insulating structures are air. In one embodiment, mushroom-shaped dielectric structures cap the insulating structures and the gates, and the insulating structures are air.
Some embodiments have a controller which applies multiple gate voltage settings to the gates.
Some embodiments have a BE-SONOS structure memory cells. The tunnel dielectric structure disposed above the semiconductor body comprises a first silicon oxide layer adjacent a channel of the semiconductor body and having a thickness of 18 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å or less, and a second silicon oxide layer on the silicon nitride layer having a thickness of 35 Å or less; and the charge storage layer comprises silicon nitride having a thickness of 50 Å or more; and the insulating layer comprises a blocking dielectric layer of silicon oxide.
Another aspect of the technology is an integrated circuit memory device, comprising a semiconductor body, charge storage structures, gates, and insulating structures. The aspect is similar to the prior aspect. However, the gates arranged in series are positioned sufficiently close together, such that in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the insulating layer of the charge storage structures beneath the gates having the programming gate voltage, are suppressed, by the insulating structures that separate neighboring charge storage structures, from entering the charge storage structures beneath the gates with the programming gate voltage. Some embodiments have this described response to the programming gate voltage and the above described response to a pass gate voltage.
wherein the gates are positioned sufficiently close together, such that in response to one or more of the gates having a pass gate voltage, the gates having the pass gate voltage have fringing electric fields that occupy most of at least one of the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the pass gate voltage, wherein the fringing electric fields are suppressed, by the insulating structures occupied by the fringing electric fields, from entering the neighboring charge storage structures.
wherein the gates are positioned sufficiently close together, such that in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the insulating layer of the charge storage structures beneath the gates having the programming gate voltage, are suppressed, by the insulating structures that separate neighboring charge storage structures, from entering the charge storage structures beneath the gates with the programming gate voltage.
suppressing fringing fields of a NAND nonvolatile charge trapping memory cell from interfering with a threshold voltage of neighboring NAND nonvolatile charge trapping memory cells in the NAND nonvolatile charge trapping memory device, with insulating structures separating the NAND nonvolatile charge trapping memory cells in the NAND nonvolatile charge trapping memory device, the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide.
Another aspect of the technology is an integrated circuit device, comprising a plurality of cells arranged in series on a semiconductor body, such that the cells are separated by insulating structures; a plurality of controlling terminals arranged in series controlling the cells; and the insulating structures that have a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide.
In various embodiments, the insulating structures are any of fluorinated silica glass, carbon doped silicon oxide, and spin-on polymer dielectric.
Another embodiment includes a polymer thin film capping the insulating structures and the plurality of gates, such that the insulating structures are air.
Another aspect of the technology is an integrated circuit device, comprising a plurality of cells arranged in series on a semiconductor body, such that the cells are separated by insulating structures; a plurality of controlling terminals with an aspect ratio greater than 3, such that the aspect ratio is equal to a ratio of a height of the plurality of controlling terminals to a width between neighboring controlling terminals, such that the plurality of controlling terminals are arranged in series controlling the cells; and the insulating structures which have a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide.
FIG. 1 illustrates a cross-sectional view of a NAND memory device.
FIG. 2A is a structure of a charge-trapping NAND memory device.
FIG. 2B is the equivalent circuit with a default bias condition.
FIG. 3A shows the various interference modes for selected memory cell Cell_5 of FIG. 2B.
FIG. 3B shows the interference disturb of memory cell 5 for the various interference modes of FIG. 3A.
FIG. 4 shows the interference from bias voltages applied to word lines adjacent memory cell 5.
FIG. 5A shows the suppressed interference from adjacent pass WL's with a low-k spacer between WL's.
FIG. 5B shows an electropotential distribution with suppressed interference from adjacent pass WL's.
FIG. 6A shows the bottom tunnel dielectric E-field distribution for different spacer materials.
FIG. 6B shows the bottom tunnel dielectric E-field under various programmed voltages applied to the selected cell.
FIG. 7A is a cross-sectional view of a first embodiment of a memory array having a low-k spacer between the word lines as described herein.
FIG. 7B is a cross-sectional view of a second embodiment of a memory array having a low-k spacer between the word lines as described herein.
FIG. 8A is a cross-sectional view of a third embodiment of a memory array having a low-k spacer between the word lines as described herein.
FIG. 8B is a cross-sectional view of a fourth embodiment of a memory array having a low-k spacer between the word lines as described herein.
FIG. 9 is a simplified block diagram of an integrated circuit including a memory array implemented using dielectric charge trapping memory cells having low-k spacers as described herein.
FIG. 10 is a simplified diagram of a BE-SONOS cell in the NAND array.
FIG. 11 is a band diagram for a tunneling dielectric layer including band offset technology at low electric fields.
FIG. 12 is a band diagram for a tunneling dielectric layer including band offset technology at high electric fields.
FIG. 13 illustrates the electric fields and tunneling currents during an erase operation for an embodiment of a memory cell.
FIGS. 14A through 14D are conduction band diagrams for the blocking dielectric layer of a single silicon dioxide layer (FIG. 14A), a single aluminum oxide layer (FIG. 14B), a first example stacked silicon dioxide/aluminum oxide layer (FIG. 14C), and a second example stacked silicon dioxide/aluminum oxide layer having a thicker aluminum oxide layer than the first example (FIG. 14D).
An innovative technology to suppress the interference beyond sub-30 nm node charge-trapping NAND Flash is described herein, resulting in high density charge trapping memory cells having improved performance. Analysis results presented herein show that, because the effective oxide thickness (EOT) (>15 nm) of charge trapping memory cells is comparable with the memory cell dimension (F), edge fringing field effect interference caused by voltages applied to adjacent wordlines can be more significant than the interference caused by programmed charge within adjacent cells. The EOT is defined as the thickness of the dielectric layers scaled by the ratio of the dielectric constant of silicon dioxide to the dielectric constant of the material of the layer.
A low-k spacer between wordlines in the array is shown herein to be very effective in suppressing the interference from both the edge fringing field due to bias voltages applied to adjacent wordlines, as well as from programmed charge in adjacent cells. As a result, memory cell NAND arrays with a half pitch of 15 nm and below are shown to have low interference.
As used herein, the term “low-k” refers to a permittivity (k) less than that of silicon dioxide, silicon dioxide having a permittivity of approximately 3.9. Low-k spacers described herein include one or more dielectric materials with a k less than that of silicon dioxide (k<3.9) which fill the space between the word lines, as well a gas-filled void which may substantially or entirely fill the space between the word lines, so that the effective k of the spacer is less than that of silicon dioxide.
Using a low-k spacer as described herein is also shown to also suppress the short channel effect. In addition, programming/erasing efficiency is also improved due to the confined E-field within the bottom tunnel dielectric of the memory cell.
FIG. 1 illustrates a cross-sectional view of a NAND memory device (not to scale) formed on a semiconductor substrate 100. Various embodiments of the NAND device are junction-free or junction based, depending on the presence or absence of junctions in the substrate 100 between neighboring memory cells in a given NAND string of memory cells. The NAND strings include memory cells 101, 102, and 103, separated by gaps that are filled with low-k dielectric structures 111 and 112.
A tunneling dielectric layer 131 comprising for example, silicon dioxide or silicon oxynitride, overlies the channel region of the substrate 100, a dielectric charge storage layer 141 comprises silicon nitride and is on the tunneling dielectric layer 131, a blocking dielectric layer 151 comprises silicon dioxide in this example and is on the charge storage layer 141, and a gate 161 for example comprising p-type or n-type polysilicon is on the blocking dielectric layer 151. Alternative embodiments using a multi-layer blocking layer can be implemented. A higher work function material may be used in addition to or in place of the polysilicon in contact with the blocking layer 151, such as tantalum, titanium, platinum, tantalum nitride, titanium nitride and so on. A variety of high work function materials suitable for use as a gate material are described in U.S. Pat. No. 6,912,163, which is incorporated by reference herein.
The memory cell is programmed and erased by applying appropriate voltages to the gate 161, and substrate 100 of the memory cell to induce an electric field between the gate 161 and substrate 100. A junction based embodiment will also have biased doped regions in the substrate 100. The memory cell can be programmed, for example, by tunneling of electrons into the charge storage layer 141 using one of a number of well-known biasing techniques (for example, Fowler Nordheim (FN) tunneling, Channel Hot Electron (CHE), etc.). The memory cell can be erased, for example, by hole tunneling from the substrate 100 into the charge storage layer 141 or by electron de-trapping from the charge storage layer 141.
In the shown NAND device, the memory cell 102 receives a pass gate voltage at gate 162. Fringing electric fields result, which are electric fields that are not confined within the memory cell 102 with its gate and charge storage structure. The fringing fields fill most of the neighboring dielectric/insulating structures 111 and 112. Because of the choice of low-k material(s) for the insulating structures 111 and 112, the fringing electric fields are suppressed from entering the charge storage structures of neighboring memory devices 101 and 103. In prior, larger dimension lithographic nodes, the fringing fields did not fill the gaps between neighboring charge storage structures in this fashion, because the height of the charge storage structure, and its equivalent oxide thickness, was much smaller, relative to the pitch of the NAND memory cells.
ii) the negative of the surface integral over the surface enclosed by the contour, of the dot product of ii)a) the partial derivative of the magnetic B field with respect to time and ii)b) the surface vector of the incremental surface dS.
Applying Faraday's Law to a cylindrical surface straddling two different materials, the tangential component of the electrical field is continuous across the interface between the two materials.
ii) the volume integral over the enclosed volume of the volume charge density at each incremental volume dv.
Applying Gauss's Law to a cylindrical surface straddling two different materials, the normal component of the electrical flux density D is continuous across the interface between the two materials, excepting surface charge at that interface.
Electric flux density D is equal to the electrical field E multiplied by the permittivity ε, where the permittivity ε is the product of the relative permittivity K and the permittivity of free space ε0. Accordingly, when applying Gauss's Law to a cylindrical surface straddling a low-K spacer and a higher-K word line stack, a particular normal electrical field in the low-K spacer, will correspond to a lower normal electrical field in the higher-K word line stack, scaled down by a factor of the ratio of the relative permittivities of the low-K spacer to the higher-K word line stack.
FIG. 2A is a structure of a charge-trapping NAND charge trapping memory device, for which simulated results are presented herein. In alternative embodiments, other types of array configurations can also be used.
The device 200 includes wordlines 220 acting as gates for the charge-trapping memory cells of the device 200. The wordlines 220 overlie the tunneling dielectric layer 230, a dielectric charge storage layer 232, and blocking dielectric layer 234 of the memory cells of the array. Spacers 240 separate the wordlines 220. The device 200 also includes bit lines 250, separated by shallow trench isolation structures 270.
In the simulated results presented below, the wordlines 220 comprise P+ doped polysilicon, the tunneling dielectric layer 230 comprises silicon dioxide having a thickness of 5 nm, the dielectric charge storage layer 232 comprises silicon nitride having a thickness of 6 nm, the blocking dielectric layer 234 comprises silicon dioxide having a thickness of 6 nm, the shallow trench isolation structures comprise silicon dioxide, and the substrate/junction doping concentrations are 1E18 cm−3 and 5E19 cm−3 respectively, unless otherwise noted. In the simulated results presented below, the half-pitch ranges from 50 to 15 nm. The full pitch is the period of the memory pattern. It will be understood that the materials, thicknesses, doping concentrations, etc. used for the memory device 200 will vary from embodiment to embodiment.
FIG. 2B is the equivalent circuit with a default bias condition for the device 200 of FIG. 2A, along with a read bias arrangement applied to evaluate interference issues of a selected memory cell Cell_5. In FIG. 2B the read bias arrangement comprises 7V applied to wordlines 220 a and 220 c, 0V applied to bit lines 250 a and 250 c, 1V applied to bit line 250 b, and ground applied to the sources of Cell_3, Cell_6, and Cell_9. Alternatively, the voltages for the read bias arrangement can be different.
FIG. 3A is a table of the various interference modes from adjacent programmed cells for selected memory cell Cell_5 of FIG. 2B. The first column of the table is the name of the disturb mode used herein, and the second column lists which of the memory cells of the device 200 are programmed for each disturb mode. For example, in the “WL” disturb mode Cell_4 and Cell_6 are in the programmed state, while Cell_1, Cell_2, Cell_3, Cell_7, Cell_8, and Cell_9 are in the erased state.
In the simulation results below, the dielectric charge trapping layer 232 of each of the cells in the programmed state have an electron density of 2E19 cm−3 (equivalent to a shift in VT of about 4.2 V), while the other cells are in the erased state and have no charge stored in layer 232. Alternatively, the electron density for each of the states can be different.
FIG. 3B shows the simulated change in the threshold voltage VT (interference) of selected Cell_5 of FIG. 2B (initially in the erased state) due to the read bias arrangement for each of the interference modes of the table of FIG. 3A. In the results of FIG. 3B the spacers 240 between the wordlines 220 comprise silicon dioxide with a k of 3.9, and the half-pitch (feature size) is 25 nm. In FIG. 3B the maximum interference is within 200 mV.
The above simulated data prove that threshold voltage interference is negligible, from the programmed charge storage layer of neighboring memory. Even the worst case of the disturb mode “All”, in which all neighboring memory cells are programmed, results in a maximum threshold voltage disturbance of less than 0.2 V.
FIG. 4 is the simulated interference of Cell_5 versus the adjacent pass-gate wordline bias using silicon dioxide spacers 240 between the wordlines 220. As can be seen in FIG. 4, as the half-pitch is reduced below 20 nm the interference from the wordline bias voltages becomes much more severe. As can also be seen, larger voltages on the wordlines 120 also cause larger shifts in VT. Pass-gate voltages of over 5V cause significant threshold voltage interference of neighboring memory cells. At a 25 nm half-pitch, threshold voltage interference is about −0.5 V. At a 15 nm half-pitch, threshold voltage interference is about −1.3 V for a pass-gate voltage of 5V, and about −2.1 V for a pass-gate voltage of 7V. Accordingly, a small half-pitch below 20 nm and a high pass-gate voltage over 5V, result in a pass gate that helps to turn on the neighboring memory cell. With pitch scaling downwards and a fixed EOT, the ratio of EOT/full pitch becomes larger. The impact of fringing field also becomes correspondingly larger, and a severe VT roll-off trend is found in the conventional oxide spacer.
FIG. 5A shows the suppressed interference from adjacent pass WL's with a low-k spacer between WL's. In particular, FIG. 5A is the simulated interference of Cell_5 for air-filled spacers 240 (k of approximately 1). As can be seen in FIG. 5A, compared with FIG. 4 the interference is significantly suppressed. At a 25 nm half-pitch, threshold voltage interference is about −0.2 V. At a 15 nm half-pitch, threshold voltage interference is about −0.3 V for a pass-gate voltage of 5V, and about −0.7 V for a pass-gate voltage of 7V. In contrast with FIG. 4, by using a low-k spacer, the VT roll-off trend is released. Therefore, the minimum spacing between neighboring NAND cells with an acceptable fringing field can be found in a pitch with acceptable interference value. The maximum spacing between neighboring NAND cells at which the low-k spacers become useful to suppress fringing electric fields, can be characterized by comparing these FIGS. 4 and 5A. The maximum spacing occurs at the pitch that unacceptable interference occurs with the oxide spacer but not with the low-k spacer.
FIG. 5B shows electropotential distributions with suppressed interference from adjacent pass WL's using spacers 240 of air (k=1, top figure), in contrast with silicon nitride (k=7, bottom figure). As can be seen in FIG. 5B, with the spacer 240 of air rather than silicon nitride the channel and the charge storage structure of the memory cell Cell_5 has a smaller electrostatic potential. The electropotential distribution with air spacers shows that the charge storage structure is substantially 0V, with some field penetration of about 1 V on the right portion of the channel and the bottom-right portion of the tunnel dielectric structure. In contrast, the electropotential distribution with nitride spacers shows that the charge storage structure is substantially 0V only at the word line and the insulating layer, with field penetration of about 1 V throughout the charge storage layer, the tunnel dielectric structure, and the channel.
FIG. 6A shows the bottom tunnel dielectric E-field distribution for different spacer materials. FIG. 6A shows the electrical field in the dielectric charge storage layer 232 of Cell_5 under +FN programming condition (Vpgm/Vpass=20/10V) for a 25 nm NAND. As can be seen in FIG. 6A, as the k of the spacer is reduced the electric field in the dielectric charge storage layer 232 of Cell_5 increases and also becomes broader in the wordline direction, as the spacer suppresses fringing fields from exiting the charge storage structures. With air spacers, both the upper insulating layer and the bottom tunnel dielectric structure have a fairly laterally uniform voltage of about 14 V. With nitride spacers, fringing fields substantially exit from the charge storage structure into the spacers, such that the bottom tunnel dielectric structure has a laterally substantially varying voltage of about 13 V in the center and about 11V at the edges. FIG. 6B is the simulated electric field dielectric charge storage layer 232 of Cell_5 at the center of the tunnel dielectric structure, under varying +FN programming bias conditions. The low-k spacer increases the center E-field and decreases the variation between the center and the edge, which suggests that the low-k spacer will increase the programming/erasing efficiency. This is because the low-K spacer helps to confine the electric field and thus it has a less degraded electric field at the center of the tunnel dielectric structure.
FIG. 7A is a simplified cross-sectional view of a first embodiment of a memory array having a low-k spacer between the wordlines, the wordlines acting as gates of the charge-trapping memory cells. Following patterning of the wordlines to form gaps therebetween, material 700 with very poor gap filing capability is deposited on the wordlines so that voids consisting of gas that was used in the deposition process remaining between the wordlines, resulting in a mushroom structure as shown in FIG. 7A. An ONO stack is between the gate and the substrate.
FIG. 7B is a simplified cross-sectional view of a second embodiment of a memory array having a low-k spacer between the wordlines. In FIG. 7B the gate material is thicker than that of FIG. 7A, resulting in higher aspect ratio openings between the wordlines. The higher aspect ratio of the opening between the wordlines helps prevent the subsequently formed dielectric 800 from filling the space between the wordlines and results in voids as shown. An ONO stack is between the gate and the substrate. A height/width ratio greater than 10 is difficult to etch. An aspect ratio, or ratio of gate height to channel width, larger than 3, is favorable, because of the relatively narrow trench between neighboring memory cells, making it easier to form an air gap between neighboring memory cells. If the aspect ratio is greater than 3, it is easier to form an air gap, because the trench is harder to fill with low-k material. Accordingly, extra steps in the paper by Kang et al. are unnecessary. For example, the insulating structures (which separate neighboring charge storage structures) do not have nitride wing spacers.
FIG. 8A is a simplified cross-sectional view of a third embodiment of a memory array having a low-k spacer between the wordlines. In FIG. 8A a thin film polymer membrane is formed on the wordlines that does not fill the openings, resulting in the formation of voids as shown. An ONO stack is between the gate and the substrate.
FIG. 8B is a simplified cross-sectional view of a fourth embodiment of a memory array having a low-k spacer between the wordlines. In FIG. 8B the space between the wordlines is filled with one or more materials having a k less than that of silicon dioxide. The spaces can be filled by depositing the low-k material on the wordlines and within the openings, and performing a planarizing process or etch back to expose the top surfaces of the wordlines. Examples of low-k materials that can be used include, for example, FSG (fluorinated silicate glass, k<3.5), Black diamond (Applied Materials, k=2.6˜3.0), SiLK (k=2.6˜2.8), and Coral (k=2.7˜2.9). An ONO stack is between the gate and the substrate.
Additional details of the present invention are described in “A Study of Stored Charge Interference and Fringing Field Effects in Sub-30 nm Charge Trapping NAND Flash” by Hsiao, et al., which is attached hereto and incorporated by reference herein.
The memory cell devices described above were implemented as SONOS type memory cells. Alternatively, the low-k spacers described can be implemented in other types of charge trapping memory cell arrays. For example, the low-k spacers can be implemented in Bandgap Engineered SONOS (BE-SONOS) devices. In one such embodiment, the tunneling layer 230 of the memory cells of FIG. 2A is replaced with a tunneling dielectric structure comprising a bottom dielectric layer of silicon dioxide less than 2 nm thick (such as about 1.3 nm), a middle dielectric layer of silicon nitride less than 2.5 nm thick (such as about 2 nm) on the bottom dielectric layer, and a top dielectric layer of silicon dioxide less than 3.5 nm thick (such as about 2.5 nm) on the middle dielectric layer. Other thicknesses can also be used. BE-SONOS technology has been proven to provide excellent performance, overcoming many of the erase speed, endurance and charge retention issues of prior art SONOS type memory.
For further information on BE-SONOS devices, attached hereto and incorporated by reference herein is U.S. patent application Ser. No. 12/182318 entitled “High-K Capped Blocking Dielectric Bandgap Engineered SONOS and MONOS”, filed on 30 Jul. 2008.
FIG. 9 is a simplified block diagram of an integrated circuit 900 including a memory array 912 implemented using dielectric charge trapping memory cells having low-k spacers as described herein. A word line (or row) and block select decoder 914 is coupled to, and in electrical communication with, a plurality 916 of word lines and string select lines, and arranged along rows in the memory array 912. A bit line (column) decoder and drivers 918 are coupled to and in electrical communication with a plurality of bit lines 920 arranged along columns in the memory array 912 for reading data from, and writing data to, the memory cells in the memory array 912. Addresses are supplied on bus 922 to the word line decoder and drivers 914 and to the bit line decoder 918. Sense amplifiers and data-in structures in block 924, including current sources for the read, program and erase modes, are coupled to the bit line decoder 918 via the bus 926. Data is supplied via the data-in line 928 from input/output ports on the integrated circuit 910, to the data-in structures in block 924. In the illustrated embodiment, other circuitry 930 is included on the integrated circuit 900, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory cell array. Data is supplied via the data-out line 932 from the sense amplifiers in block 924 to input/output ports on the integrated circuit 1000, or to other data destinations internal or external to the integrated circuit 1000.
The array 912 can be a NAND array, an AND array or a NOR array, depending on the particular application.
A controller implemented in this example, using bias arrangement state machine 934, controls the application of bias arrangement supply voltages and current sources 936, such as read, program, erase, erase verify, program verify voltages or currents for the word line and bit lines, and controls the word line/source line operation using an access control process. The controller 934 may be implemented using special purpose logic circuitry as known in the art. In alternative embodiments, the controller 934 comprises a general purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.
FIG. 10 is a simplified diagram of a charge trapping memory cell in the NAND array employing a multilayer blocking dielectric layer and a bandgap engineered dielectric tunneling layer. The memory cell includes a channel 10, a source 11 and a drain 12 adjacent the channel in a semiconductor body. A gate 18 overlies a multilayer stack, including the multilayer blocking dielectric layer, the charge trapping layer and the tunneling layer, of dielectric materials acting as the charge storage structure.
In the embodiment illustrated in FIG. 10, the dielectric tunneling layer comprises a composite of materials, including a first layer 13, referred to as a hole tunneling layer, of silicon dioxide on the surface 10 a of the channel 10 formed for example using in-situ steam generation ISSG with optional nitridation by either a post deposition NO anneal or by addition of NO to the ambient during deposition. The thickness of the first layer 13 of silicon dioxide is less than 20 Å, and preferably 15 Å or less. Representative embodiments are 10 Å or 12 Å thick.
The structure of the dielectric tunneling layer is described in more detail below with reference to FIGS. 11 and 12.
The blocking dielectric layer in this embodiment comprises a stack including a buffer layer 17A and a high-κ capping layer 17B. High-κ herein refers to dielectric constant>7, such as found in materials including Al2O3, HfO2, ZrO2, La2O3, AlSiO, HfSiO and ZrSiO etc.
In a representative embodiment, the first layer 13 can be 13 Å of silicon dioxide; the band offset layer 14 can be 20 Å of silicon nitride; the isolation layer 15 can be 25 Å of silicon dioxide; the charge trapping layer 16 can be 70 Å of silicon nitride; and the blocking dielectric layer 17A,17B can be of silicon oxide between 5 Å and 90 Å, with a capping layer of aluminum oxide between 5 and 90 Å The gate material can be p+ polysilicon (work function about 5.1 eV). For improved retention characteristics, it is preferred that the layer of silicon oxide have a thickness greater than 30 Å.
Also, it is found that the ratio of the thickness of the top layer 17B to the thickness of the bottom layer 17A of the blocking dielectric layer can be less than 2 for the combination of silicon oxide (κ1=3.9) and aluminum oxide (κ2=about 8). In general, the top layer 17B can have a thickness that is less that the ratio of the dielectric constants (8/3.9) times the thickness of the bottom layer 17A. Thus, the blocking dielectric layer as described herein includes a first layer 17A having a dielectric constant κ1 contacting the charge trapping dielectric layer and a second layer 17B contacting another one of the channel surface and the gate, the second layer 17B having a dielectric constant κ2 higher than κ1 of the first layer, and the second layer having thickness less than κ2/κ1 times that of the first layer. For aluminum oxide as a top capping layer, the dielectric constant is ˜8 and the barrier height or conduction band offset is more than 3 eV to obtain the erase saturation VFB<−2V. Since the barrier height of Al2O3 is almost the same as SiO2, the electron barrier height or conduction band offset of aluminum oxide with N+ polysilicon gate is about 3.1 eV.
FIG. 11 is a diagram of the energy levels of the conduction and valence bands of the dielectric tunneling structure including the stack of layers 13-15 of FIG. 10 under a low electric field, showing a “U-shaped” conduction band and an “inverted U-shaped” valence band. From the right side, the bandgap for the semiconductor body is shown in region 30, the valence and conduction bands for the hole tunneling layer are shown in region 31, the bandgap for the offset layer is shown in region 32, the valence and conduction bands for the isolation layer are shown in region 33 and the valence and conduction bands for the charge trapping layer are shown in region 34. Electrons, represented by the circles with the negative sign, trapped within the charge trapping region 34 are unable to tunnel to the conduction band in the channel, because the conduction band of the tunneling dielectric layer in all three regions 31, 32, 33 remains high relative to the energy level of the trap. The likelihood of electron tunneling correlates with the area under the “U-shaped” conduction band in the tunneling dielectric layer and above a horizontal line at the energy level of the trap to the channel. Thus, electron tunneling is very unlikely at low field conditions. Likewise, holes in the valence band of the channel in region 30 are blocked by the full thickness of regions 31, 32 and 33 from tunneling to the charge trapping layer (region 34), and the high hole tunneling barrier height at the channel interface. The likelihood of hole tunneling correlates with the area over the “inverted U-shaped” valence band in the tunneling dielectric layer and below a horizontal line at the energy level of the channel to the charge trapping layer. Thus, hole tunneling is very unlikely at low field conditions. For the representative embodiment, in which the hole tunneling layer comprises silicon dioxide, a hole tunneling barrier height of about 4.5 eV prevents hole tunneling. The valence band in the silicon nitride remains 1.9 eV below that of the valence band in the channel. Therefore, the valence band in all three regions 31, 32, 33 of the tunneling dielectric structure remains significantly below the valence band in the channel region 30. The tunneling layer described herein therefore is characterized by band offset characteristics, include a relatively large hole tunneling barrier height in a thin layer (region 31) at the interface with the semiconductor body, and an increase 37 in valence band energy level at a first location spaced less than 2nm from the channel surface. The band offset characteristics also include a decrease 38 in valence band energy level at a second location spaced from the channel by providing a thin layer (region 33) of relatively high tunneling barrier height material, resulting in the inverted U-shaped valence band shape. Likewise, the conduction band has a U-shape caused by the same selection of materials.
FIG. 12 shows the band diagram for the dielectric tunneling structure under conditions of an electric field of about −12 MV/cm in the tunneling region 31, for the purposes of inducing hole tunneling (in FIG. 12, the O1 layer is about 15 Å thick). Under the electric field the valence band slopes upward from the channel surface. Therefore, at an offset distance from the channel surface the valence band in the tunneling dielectric structure increases in band energy level substantially, and in the illustration rises above the band energy in the valence band in the channel region. Therefore, the hole tunneling probability is increased substantially as the area (shaded in FIG. 12) between the level of the valence band in the channel and above the sloped, inverted U-shaped valence band in the tunneling stack is reduced. The band offset effectively eliminates the blocking function of the offset layer in region 32 and isolation layer in region 33 from the tunneling dielectric during high electric field allowing a large hole tunneling current under relatively small electric fields (e.g. E<14 MV/cm).
FIG. 13 is a schematic illustration of the gate stack for a charge trapping memory cell like that in FIG. 10, showing electric field dynamics during an erase process. The gate stack includes a hole tunneling layer 43, a band offset layer 44, and an isolation layer 45 which in combination act as the dielectric tunneling layer for the device. A charge trapping layer 46 is shown on the tunneling dielectric layer. A blocking dielectric layer consisting of a multilayer structure including a buffer layer 47A and a capping layer 47B separates the charge trapping layer 46 from the gate 48. During an erase process, the electric field is induced by bias voltages VG and VW applied at the gate and channel of the memory cell, and results in an electric field ETUN 50 through the dielectric tunneling layer 43, 44, 45 and an electric field EB 51 through the blocking layer 47A/47B. The magnitude of the electric field ETUN 50 through the dielectric tunneling layer is sufficient to induce hole tunneling current 52 into the trapping layer 46. The magnitude of the electric field EB 51 through the capping layer 47B in the blocking dielectric layer is reduced relative to that through the silicon dioxide in the tunneling dielectric layer because of the higher dielectric constant by an amount that is about 3.9/κ, where 3.9 is the dielectric constant for silicon dioxide and κ is the dielectric constant of the capping layer 47B. Therefore, because of sufficient electron affinity of the gate 48, the relatively lower electric field EB 51 and the thickness of the blocking dielectric layer 47A/47B, electron tunneling current 53 is effectively blocked, allowing large memory windows without erase saturation effects. Memory devices as taught herein are operable with bias voltages across the gate and semiconductor body low enough that a maximum electric field of 14 MV/cm or less occurs in the tunneling dielectric layer during erase, with a corresponding lower electric field in the blocking dielectric layer.
FIGS. 14A through 14D are conduction band diagrams for the blocking dielectric layer of a single silicon dioxide layer (FIG. 14A), a single aluminum oxide layer (FIG. 14B), a first example stacked silicon dioxide/aluminum oxide layer (FIG. 14C), and a second example stacked silicon dioxide/aluminum oxide layer having a thicker aluminum oxide layer than the first example (FIG. 14D). The tunneling probability for electron injection from the gate can be understood from these figures. The magnitude of the electric field within the material is reflected by the slope of the conduction band. Thus, the region corresponding to the silicon dioxide buffer layer labeled O3 in FIGS. 14C and 14D has a greater slope than the region corresponding to the aluminum oxide capping layer. The conduction band offset at the gate interface is reflected by the height of the step in the conduction band. For a bandgap engineered SONOS device as shown in FIG. 14A, the tunneling probability is relatively high, even though the conduction band offset is relatively large because of the high magnitude of the electric field. For an embodiment having an aluminum oxide blocking dielectric layer as represented in FIG. 14B, the tunneling probability is relatively low because of the lower slope on the conduction band caused by the relatively high dielectric constant (e.g. greater than 7), and because the conduction band offset remains relatively high (e.g. greater than 3 eV). FIGS. 14C and 14D suggest that the tunneling probability for gate injection is about the same for multilayer stacks having a silicon dioxide buffer layer and an aluminum oxide top layer, so long as the thickness of the aluminum oxide top layer is larger than a minimum value. Thus, the tunneling probability for the embodiment FIG. 14C having a thinner aluminum oxide layer is about the same as that for the embodiment of FIG. 14D having a thicker aluminum oxide layer.
the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide.
2. The integrated circuit memory device of claim 1, wherein the gates are positioned sufficiently close together, such that in response to one or more of the gates having a pass gate voltage, the gates having the pass gate voltage have fringing electric fields that occupy most of at least one of the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the pass gate voltage, wherein the fringing electric fields are suppressed, by the insulating structures occupied by the fringing electric fields, from entering the neighboring charge storage structures.
wherein the insulating structures between neighboring charge storage structures of the plurality of charge storage structures, are air, and lack wing spacers.
wherein the full pitch of the charge storage structures, causes the fringing electric fields to occupy most of at least one of the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the pass gate voltage.
wherein the insulating structures suppress the fringing electric fields from entering a channel region.
6. The integrated circuit memory device of claim 1, wherein in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the insulating layer of the charge storage structures beneath the gates having the programming gate voltage, are suppressed by the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the programming gate voltage.
7. The integrated circuit memory device of claim 1, wherein in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the tunnel dielectric structure of the charge storage structures beneath the gates having the programming gate voltage, are suppressed by the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the programming gate voltage.
8. The integrated circuit memory device of claim 1, wherein in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the tunnel dielectric structure of the charge storage structures beneath the gates having the programming gate voltage, are suppressed by the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the programming gate voltage, such that the tunnel dielectric structure has a lateral voltage variation from the fringing fields of no more than a volt between a center of the tunnel dielectric structure and an edge of the tunnel dielectric structure.
9. The integrated circuit memory device of claim 1, wherein the insulating structures have a relative dielectric constant with respect to vacuum that is less than relative dielectric constants of materials in the tunnel dielectric structure.
10. The integrated circuit memory device of claim 1, wherein the insulating structures are air.
11. The integrated circuit memory device of claim 1, wherein the insulating structures are any of fluorinated silica glass, carbon doped silicon oxide, and spin-on polymer dielectric.
a polymer thin film capping the insulating structures and the plurality of gates, wherein the insulating structures are air.
a plurality of mushroom-shaped dielectric structures capping the insulating structures and the plurality of gates, wherein the insulating structures are air.
a controller which applies a plurality of gate voltage settings to the plurality of gates.
the insulating layer comprises a blocking dielectric layer of silicon oxide.
forming insulating structures separating the charge storage structures, the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide.
17. The method of claim 16, wherein the gates are positioned sufficiently close together, such that in response to one or more of the gates having a pass gate voltage, the gates having the pass gate voltage have fringing electric fields that occupy most of at least one of the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the pass gate voltage, wherein the fringing electric fields are suppressed, by the insulating structures occupied by the fringing electric fields, from entering the neighboring charge storage structures.
18. The method of claim 16, wherein in response to one or more of the gates having a programming gate voltage, fringing fields adjacent to the tunnel dielectric structure of the charge storage structures beneath the gates having the programming gate voltage, are suppressed by the insulating structures that separate neighboring charge storage structures from the charge storage structures beneath the gates with the programming gate voltage.
suppressing fringing fields of a NAND nonvolatile charge trapping memory cell from interfering with a threshold voltage of neighboring NAND nonvolatile charge trapping memory cells in the NAND nonvolatile charge trapping memory device, with insulating structures separating the NAND nonvolatile charge trapping memory cells in the NAND nonvolatile charge trapping memory device, the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide, the NAND nonvolatile charge trapping memory cell and the neighboring NAND nonvolatile charge trapping memory cells having gates with an aspect ratio greater than 3, the aspect ratio being equal to a ratio of a height of the gates to a channel width between neighboring gates.
21. The integrated circuit memory device of claim 20, wherein the insulating structures are any of fluorinated silica glass, carbon doped silicon oxide, and spin-on polymer dielectric.
23. The integrated circuit device of claim 22, wherein the insulating structures are any of fluorinated silica glass, carbon doped silicon oxide, and spin-on polymer dielectric.
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