Source: https://patents.google.com/patent/US6452427B1/en
Timestamp: 2019-04-24 02:38:32+00:00

Document:
2006-07-26 Assigned to THE GOODYEAR TIRE & RUBBER COMPANY reassignment THE GOODYEAR TIRE & RUBBER COMPANY RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A.
A dual output capacitance interface circuit (100) based on switched capacitor circuits and charge subtraction technique provides both voltage output (104) and frequency output (106). The circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance. Temperature compensation methods are described.
This application is a continuation-in-part of commonly-owned, copending U.S. Provisional Patent Application No. 60/091,909, filed Jul. 7, 1998 by Ko et al.
Attention is directed to commonly-owned, copending PCT Patent Application No. 09/743,432, entitled METHOD OF FABRICATING SILICON CAPACITIVE SENSORS filed on even date herewith.
The invention relates to circuits for interfacing with and deriving usable signals from transducers, more particularly capacitive force transducers such as pressure transducers, more particularly touch mode capacitive pressure sensors (“TMCPS”).
Capacitive pressure sensors typically include a pair of conductive elements, one of which is a fixed substrate another of which is a flexible diaphragm. In a conventional capacitive pressure sensor, as pressure increases a gap between the diaphragm and the underlying substrate decreases, and the capacitance of the sensor increases. The sensor is normally operated in a pressure range wherein the diaphragm is kept from actually contacting the underlying substrate. These sensors normally exhibit nonlinear characteristics. This inherent non-linearity has led to the development of many linearization schemes using complex and costly interface circuits which include analog circuits and amplifiers, segment linearization, microprocessor and ROM matrix linearization, etc.
Another type of capacitive pressure sensor is the touch mode capacitive pressure sensor (“TMCPS”). In touch mode operation, the diaphragm of the capacitive pressure sensor touches the underlying substrate which is covered by a thin insulating layer. As pressure increases, the contact area increases. The major component of output capacitance is the capacitance of the touched area with a thin layer of isolation layer which gives a larger capacitance per unit area compared to the air-gap capacitance in the untouched area. The touch mode device was developed to withstand harsh industrial environment, and with one or two orders of magnitude higher sensitivity than the normal (non-touch) mode operation in the near linear operation range, so that some of the stray capacity effects can be neglected. Advantages of touch mode capacitive pressure sensors include near linear output characteristics, large over-range pressure capability and robust structure that make them capable to withstand harsh industrial field environments. One application of interest for pressure sensors generally, and touch mode capacitive pressure sensors in particular, is in conjunction with an RF transponder inside a pneumatic tire.
Examples of capacitive pressure sensors can be found in U.S. Pat. No. 3,993,939 (November 1976), U.S. Pat. No. 5,528,452 (June 1996), U.S. Pat. No. 5.656,781 (August 1997), and U.S. Pat. No. 5,706,565 (January 1998).
It has been observed that one drawback of the silicon fusion bonded capacitive pressure sensors is that they have large zero-pressure capacitance, which limits applications of some capacitive interface circuits. The large zero-pressure capacitance originates from the large bonding area and the isolation material with a large dielectric constant surrounding the diaphragm. At zero-pressure, since the deflection of the diaphragm is small, the gap distance between diaphragm and the electrode on the bottom electrode is large. Therefore the capacitance of the air-gap capacitor contributes a small part to the overall capacitance at zero-pressure. The zero-pressure capacitance is mainly determined by the bonding area required to ensure the hermetic seal and mechanically support of the diaphragm. In the current design, the measured zero-pressure capacitance of the fabricated sensor is 7.3 pF, of which the bonding area contributes about 80%.
U.S. Pat. No. 4,104,595 (August 1978), incorporated in its entirety by reference herein, discloses a signal translating circuit for variable area capacitive pressure transducer. The circuit translates the capacitance change of a variable area capacitive transducer into a d-c voltage change. The transducer has two electrodes. As a force is applied to a deformable one of two electrodes, there is a change in the effective contact area between the electrodes in accordance with the applied pressure, producing a resulting change in capacitance. The signal translating circuit produces a d-c output signal which varies as a function of the transducer capacitance change.
U.S. Pat. No. 4,392,382 (July 1983), incorporated in its entirety by reference herein, discloses a linearized electronic capacitive pressure transducer. A variable capacitance pressure sensor (CX) and a reference capacitor (CR), and associated circuitry, provide a temperature compensated output signal which has a substantial linear variation as a function of sensed pressure.
U.S. Pat. No. 4,446,447 (May 1984), incorporated in its entirety by reference herein, discloses a circuit for converting pressure variation to frequency variation which includes a reference oscillator and a sensor oscillator coupled to a digital mixer. The reference oscillator includes a reference capacitor and a reference resistor. The sensor oscillator has a variable sensor timing capacitor and a sensor resistor.
U.S. Pat. No. 4,820,971 (November 1989), incorporated in its entirety by reference herein, discloses a precision impedance measurement circuit providing an output voltage (Vout) as a function of a capacitance (Cx) of a condition-sensing capacitor, and also describes the use of a reference capacitor having a capacitance (Co) which is unaffected by the sensed condition is disclosed.
It is an object of the present invention to provide method and apparatus for interfacing with and deriving usable signals from transducers, more particularly capacitive force transducers such as pressure transducers, more particularly touch mode capacitive pressure sensors (“TMCPS”), as defined in one or more of the appended claims and, as such, having the capability of being implemented in a manner to accomplish one or more of the subsidiary objects.
According to the invention, a dual output capacitance interface circuit (100, FIG. 1) provides a voltage output (104) and a frequency output (106), each of which is related to a capacitance value of a condition-sensitive capacitance (Cx), such as a touch-mode capacitive pressure sensor. A capacitance-to-current (C-I) sub-circuit 110 converts capacitance to current. A current-to-frequency (I-F) sub-circuit (112) converts current to frequency signal. A current-to-voltage (I-V) sub-circuit (114) converts current to a DC voltage.
According to an aspect of the invention, the capacitance-to-current (C-I) converter comprises three capacitor controlled current sources controlled by a three-phase non-overlapping clock (116, FIG. 9). The three-phase non-overlapping clock (FIG. 9) may be driven by a clock generator (FIG. 10) comprising a Schmitt trigger.
According to an aspect of the invention, the current-to-frequency (I-F) converter (112, FIG. 5A) comprises a Schmitt trigger.
According to an aspect of the invention, the circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance.
The dual output capacitance interface circuit (100) is based on switched capacitor circuits and charge subtraction techniques for providing the voltage (104) and frequency (106) outputs. The circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance. Temperature compensation methods are described.
Other objects, features and advantages of the invention will become apparent from the description that follows.
Reference will be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings (FIGURES). The drawings are intended to be illustrative, not limiting. Although the invention will be described in the context of these preferred embodiments, it should be understood that it is not intended to limit the spirit and scope of the invention to these particular embodiments.
Certain elements in selected ones of the drawings may be illustrated not-to-scale, for illustrative clarity.
Often, similar elements throughout the drawings may be referred to by similar reference numerals. For example, the element 199 in a FIGURE (or embodiment) may be similar in many respects to the element 299 in another FIGURE (or embodiment).Such a relationship, if any, between similar elements in different FIGURES or embodiments will become apparent throughout the specification, including, if applicable, in the claims and abstract.
In some cases, similar elements may be referred to with similar numbers in a single FIGURE. For example, a plurality of elements 199 may be referred to as 199 a 199 b, 199 c, etc.
The cross-sectional views, if any, presented herein may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a true cross-sectional view, for illustrative clarity.
FIG. 20 is a graph illustrating characteristics of the dual output converter of the present invention.
a three-phase clock generator 116, driven by an oscillator 118 controlled by a capacitor (Cosc), which provides a three-phase non-overlapping clock to control the charging/discharging process of the capacitance-to-current (C-I) converter 110. No reset is necessary to initiate the three-phase clock. The transition of the states is designed to avoid any simultaneous high state of the three phases.
FIGS. 2, 3 and 4 are simplified schematics illustrating the operation and an implementation of the capacitance-to-current (C-I) converter 110 of FIG. 1.
A modified switched-capacitor emulated resistor may be used to implement the capacitor controlled current source, and is shown in FIG. 2. Switches S1 and S2 are controlled by a non-overlapping two-phase clock (not shown). During phase 1, switch S1 is closed and switch S2 is opened. The capacitor, C, is charged to V1 at the end of phase 1. The charge on the capacitor C is CV1 During phase 2, the switch S1 is opened and the switch S2 is closed. The charge on the capacitor C will become Q=CV2 at the end of phase 2. The net charge transferred in one clock cycle is CV1−CV2. If the process continues, the average current flowing between V1 and V2 is (CV1−CV2)ƒ=(V1−V2)ƒC, where ƒ is the cycling clock frequency. The equivalent resistance between V1 and V2 is 1/ƒC. By replacing V2 with a MOSFET transistor. M1, as shown in FIG. 3, the average current flow through the transistor M1 is (V1−VT)ƒC, where VT is the threshold voltage of the MOSFET providing the adequate settling time is allowed. Since transistors M1 and M2 are connected as a current mirror, the current flowing through M2 will be the same as the current flowing through M1 (ignoring a finite output resistance for M2).
where K1=ƒ(Vg−VT), K2=ƒ(Vo−VT), K3=ƒ(Vo−VT)Co, assuming that threshold voltages of the transistors M1, M2 and M3 are the same.
Hence, the current I, flowing through the transistor. M3 is related to (a measure of) the capacitance Cx. The current I is also related to both ƒVg and ƒVoCo, which makes it possible to adjust the current by two external parameters, Vg and VoCo, independently. The VoCo is used to adjust reference or offset current, while Vg is used for gain control of C-I converter 110.
FIGS. 5A, 5B and 6 illustrate the operation and an implementation of the current-to-frequency (I-F) converter 112 of FIG. 1.
FIG. 5A is a simplified schematic illustrating the operation and an implementation of the current-to-frequency (I-F) converter 112 of FIG. 1. An output portion of the C-I converter 110, including the transistors M3 and M4 is shown to the left of a dashed line. The current-to-frequency (I-F) components are shown to the right of the dashed line.
where Vc is the threshold voltage of the Schmitt trigger, which is the difference between VH and VL.
where ki (i=1-4) are the width length ratio of MOSFETs; VDD is power supply; VTn and VTp are the threshold voltage of nMOS and pMOS, respectively.
The two equations Eqn. 4 and Eqn. 6 can be used to determine the high threshold voltage and low threshold voltage of the Schrnitt trigger. On the other hand, these two equations can also be used to design transistors' sizes to get threshold voltages required.
where ki (i=1, 2, . . . , 5) are the width:length ratios of the MOSFET transistors MS1-MS6. In this example: the transistor MS1 has a width:length ratio of 18:2 (6/2 ), the transistor MS2 has a width:length ratio of 18:2 (18/2), the transistor MS3 has a width:length ratio of 18:2 (21/2), the transistor MS4 has a width:length ratio of 18:2 (18/2), the transistor MS5 has a width:length ratio of 18:2 (90/2), and the transistor MS6 has a width:length ratio of 18:2 (36/2).
It can be seen from the equations above that to reduce ΔVH and ΔVL, the k2/k5 should be kept constant and both k2/k4 and k5/k1 should be increased.
Assume that a Schmitt trigger has threshold values of VHi=3.5 v and VLi=1.7 v. The circuit operates at VDD=5 v. Using MOSIS process parameters μnCox/2=26.5, μpCox/2=9.6, VTn=0.7412, VTp=−0.9002 [4.7] and equations Eqn. 4-Eqn. 8, the Schmitt trigger is designed. The sizes of transistors (W/L) are marked in FIG. 6. The calculated (from equation 4.4-4.8), Pspice simulated and measured threshold voltages are listed in the following table (TABLE 1).
FIG. 7 is a state diagram, FIG. 8 is a true value table and FIG. 9 is a schematic of an implementation of the three-phase clock generator 116 of FIG. 1. FIG. 10 is a schematic of a Schmitt oscillator (input clock generator) for providing a high duty cycle pulse for the three-phase clock generator of FIG. 9. FIG. 11 is a timing diagram for the three-phase, non-overlapping clock generator of FIG. 9 and the Schmitt oscillator of FIG. 10.
The “don't care” phases are added in the true value table as shown in FIG. 8.
Two three-phase non-overlapping clock 116 can be constructed according to equations set forth above. An embodiment of a physical implementation (realization) for the clock is shown in FIG. 9. A high duty cycle clock is used as an input clock of the three-phase clock. Two edge-trigged D flip-flops are used to control the transition timing. Since the transition of D flip-flops occurs at the rising edge of the input clock, there will be no undesirable spike to cause erroneous turn-on of switches. The low period of input clock pulls all the outputs low, which produces the non-overlapping period between adjacent phases. Since the clock generator has “anti-lock” property, no reset is necessary to initiate the clock.
FIG. 10 illustrates a Schmitt oscillator (clock generator) for providing a high duty cycle pulse for the three-phase clock generator of FIG. 9. The low period will be used to produce the non-overlapping period. The high period is converted to the high period of each phase of the three-phase clock by the sequence desired. The charging and discharging of the capacitor Cosc is achieved by a non-symmetric inverter whose pMOS has a lower driving capacity than that of nMOS, so that Cosc can be charged slowly up to the high threshold voltage of the Schmitt trigger to provide a long positive period of the pulse. FIG. 11 illustrates the schematic timing diagram of the Schmitt trigger input clock generator of FIG. 10 and the three-phase non-overlapping clock generator of FIG. 9. The ratio of (W/L)p/(W/L)n is 3/10. which will give the nMOS about 10 times driving power than the pMOS considering μn≈3μp. Therefore, the duty cycle of the clock is 90.9%.
The time, t, is the time required for the gate voltage started at Vi to drop to V. It can be observed that R has to be made small and k′ be large in order to reduce the discharging time, t.
Other techniques to reduce ΔV can be developed so that the clock frequency can be increased.
In the equation Eqn. 19, Vc is the threshold voltage of the Schmitt trigger and cannot be adjusted due to circuit configuration. However, the resolution of the converter, ΔC, can be designed by choosing the ratio of Cst/ƒVg under the condition that ΔF is greater than 1 Hz which is determined by the external measurement instrument. FIG. 12 shows that the resolution of the C-F converter (110/112) can be 0.01 pF when the parameters of the circuit listed are chosen.
Temperature characteristics of the C-F converter 110/112 are discussed in this section in order to understand the temperature drift of the circuit. The temperature sensitivity of all three sub-circuits, capacitance-to-current converter 110, current-to-frequency converter 112 and clock generator 116, contribute to the temperature error of the C-F converter 110/112.
in which “−” is used for an nMOS and “+” for a pMOS.
The parameter ΦF always decreases in absolute value when the temperature increases. The term Ego is dominant. As a result, for an nMOS, ΦF is positive and its dΦF/dT is negative. Since the nMOS is usually in the enhancement mode, its threshold voltage decreases in absolute value. On the other hand, for a pMOS, ΦF is negative and dΦF/dT is positive. The threshold voltage thus decreases in absolute value as well.
with “+” for a nMOS and “−” for a pMOS.
can be estimated as 2 mv/K.
The temperature error of the current is proportional to the temperature drift of the threshold voltage and clock frequency.
The current-to-frequency converter and the clock generator are realized by the Schmitt trigger circuits. The temperature characteristics of the two sub-circuits are determined by the temperature dependency of the Schmitt trigger.
The temperature error of the Schmnitt trigger is proportional to the error of the threshold voltages of both pMOS and nMOS. The temperature drift can be determined as −1.525 mv/K according to equation Eqn. 24, where k1/k3=6/21 and k4/k6=18/36. FIG. 13 shows a Pspice simulation result of the temperature characteristics of the threshold voltage of the Schmitt trigger circuit used in the converter.
As discussed before, both the threshold voltage of a nMOS and the threshold voltage of a Schmitt trigger have negative temperature coefficients. It can be noticed from equation Eqn. 26 that the ∂VT/∂T and ∂Vc/∂T have opposite signs with ∂ƒ/∂T. Therefore, the temperature error of the C/F converter circuit can be compensated if the clock frequency has an appropriate negative temperature coefficient. A temperature compensation method based on the temperature controlled saturation current of pMOS transistors is discussed in the following section.
For low doping levels, the value of nμ is about 1.5. The channel of a MOSFET has an average doping level that is at least the doping level of bulk (i.e. strong inversion condition). Therefore, the bulk doping level can be used to estimate the value of nμ. The result usually is close to 1.5.
The two terms have different signs and can be compensating each other. It can be shown, theoretically and experimentally, that unique (and distinct) gate voltage exists for a given MOSFET that the drain current has a zero temperature coefficient.
For a pMOS made by MOSIS, the VT is −0.9 v, using nμ=1.5, the zero temperature coefficient VGS can be estimated as −1.7 v at 300 K. FIGS. 14A and 14B show the drain current of a pMOS simulated by Pspice. Using VGS=−5 v in (a), the drain current changes from 161.055 μA to 106.663 μA in the temperature range between 0 to 100° C. The maximum error is 33.77%. Using VGS=−1.8115 v in (b), the transistor keeps the drain current of 11.779 μA at 0° C. and 100° C. The minimum drain current is 11.657 μA at 45° C. The maximum error is 1.035% with respect to the drain current at 0 ° C.
The simulated results were used to design the circuit of the capacitance-to-frequency/voltage converter.
The current obtained from the capacitance-to-current (C-I) converter 110 can also be used to provide DC voltage signal output 104. A combination of the capacitance-to-current (C-I) converter 110 and current-to-voltage (I-V) converter 114 constitute a capacitance-to-voltage converter “110/114”.
where the equivalent resistance R=rI2gm3rI3.
Thus, the sensitivity of the converter can be adjusted either by voltage Vg or capacitor Cƒ.
FIG. 20 is a graph illustrating the frequency and voltage outputs of the dual output converter 100. Each of the C-F and C-V converters 110/112 and 110/114, respectively, are adjusted to have the best linear characteristics in the test range. The C/V converter is first adjusted by varying Vo to get the offset voltage greater than 1.5 v. The span of the voltage output can be adjusted by changing the sensitivity of the circuit, normally by shunting the feedback capacitor, Cƒ. The frequency output can be adjusted by varying capacitor Cst, as discussed hereinabove. As illustrated in FIG. 20, the sensitivity of the C/V converter is 0.63 v/pF with non-linearity ±0.38% and the sensitivity of the C/F converter is 729 Hz/pF with non-linearity of ±0.61%. The sensitivity of the C/V converter is lower than the designed value because of large stray capacitance of Cƒ.
A dual output capacitance interface circuit (100) based on switched capacitor circuits and charge subtraction technique provides both voltage output (104) and frequency output (106). The circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance. A sensitivity of 350 Hz/pF has been achieved in the 10 pF measurement range with non-linearity less that ±0.6%. A higher capacitance-to-frequency (C-F) sensitivity can be obtained for a smaller capacitance measurement range. A voltage sensitivity of 3-4 v/pF can be achieved. In the temperature range of 25° C.-95° C., the offset temperature drift of the C-V converter is less than 5%. The sensitivity drift is less than 3.5%. The offset temperature drift of the C-F converter is about −16% and the sensitivity drift is also −16% in the temperature range of 25° C.-95° C.
A temperature compensation method is based on the fact that a MOSFET has a bias voltage VGS which can give the saturation current with a zero-temperature-coefficient (ZTC). Using this principle, a temperature compensated clock generator is utilized. The temperature characteristics of the clock frequency, which is related to the output frequency of the C-F converter, can be used to compensate the overall temperature error of the converter. In the temperature range from 25° C. to 95° C., the temperature coefficient of sensitivity, after temperature compensation, is 37 ppm/° C., and the temperature coefficient of offset is 86 ppm/° C. The extra current source results in a clock frequency with a positive temperature coefficient. Since the C-F converter has negative temperature coefficient and the output frequency is proportional to the clock frequency, the temperature error can be compensated. Measured results shows that after the compensation, the temperature drift, when the input capacitor is fixed as 6.6 pF, is ±0.3% and the sensitivity drift is ±0.8%. An alternative temperature compensation method is to use an external MOS current source and a thermistor with a positive temperature coefficient.
Although the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only preferred embodiments have been shown and described, and that all changes and modifications that come within the spirit of the invention are desired to be protected. Undoubtedly, many other “variations” on the “themes” set forth hereinabove will occur to one having ordinary skill in the art to which the present invention most nearly pertains, and such variations are intended to be within the scope of the invention, as disclosed herein.
a current-to-frequency converter that is used to convert the current signal from the capacitance-to-current converter to a frequency output signal, wherein the current-to-frequency converter comprises a Schmitt trigger having an input connected to the output of an oscillator comprised of current mirrors that are switched by an output of the Schmitt trigger, to alternately charge and discharge a fixed capacitor using a mirrored current that is proportional to the current signal from the capacitance-to-current converter, thereby producing a Schmitt trigger output that provides a symmetric square wave output signal with a frequency determined by the condition-sensitive capacitance.
a current-to-frequency converter that is used to convert the current signal from the capacitance-to-current converter to a frequency output signal.
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References: Application No. 60
 Application No. 09
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