Source: http://cdc.ioc.ee/dt.html
Timestamp: 2019-04-19 18:52:51+00:00

Document:
Margus Kruus, TTÜ arvutitehn. inst. dir., dots.
Jaan Raik, TTÜ arvutitehn. inst. van.-tead.
Aleksandr Sudnitsõn, TTÜ arvutitehn. inst. dots.
S. Devadze, R. Gorjachev, A. Jutman, E. Orasson, V. Rosin, R. Ubar. E-learning tools for digital test. In Distance Learning - Educational Environment of the XXI Century, pp. 336-342. Minsk, 2003.
P. Ellervee, J. Raik, V. Tihomirov. Fault emulation on FPGA: a feasibility study. In Proc. of 21st IEEE NORCHIP Conf., 2003 (Riga, Nov. 2003), pp. 92-95. 2003.
E. Fomina, A. Keevallik, M. Kruus, A. Sudnitson. A decomposition procedure for register-transfer level power management. In Proc. of Int. Conf. on Computer Systems and Technologies, CompSysTech 2003 (Sofia, June 2003), v. 1, pp. 21-26. 2003.
E. Fomina, A. Sudnitson. Synthesis of finite state machines networks guided by information relationships. In Proc. of Int. Conf. on the Experience of Designing and Application of CAD Systems in Microelectronics, CADSM 2003 (Slavske, Feb. 2003). 2003.
E. Gramatova, M. Hristov, W. Kuzmicz, V. Lantsov, M. Lobur, V. Nelayev, V. Stepanets, R. Ubar, H.-D. Wuttke. Results of international cooperation for development and exchange of Web-based educational materials. In Distance Learning - Educational Environment of the XXI Century, pp. 17-23. Minsk, 2003.
V. Hahanov, R. Ubar. First East-West Design and Test Conference. IEEE Design & Test of Computers, v. 20, n. 6, p. 103, 2003.
A. Jutman. On SSBDD model size and complexity. In Proc. of 4th Electronic Circuits and Systems Conf. (Bratislava, Sept. 2003), pp. 17-22. 2003.
A. Jutman, A. Sudnitson, R. Ubar, Digital design learning system based on Java applets. In Proc. of 4th Ann. Conf. of LTSN Subject Centre for Information and Computer Sciences (Galway, Aug. 2003), pp. 183-187. 2003.
A. Jutman, A. Sudnitsõn, R. Ubar. Web-based applet for teaching boundary scan standard IEEE 1149.1. In Proc. of 10th Int. conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2003 (Lodz, June 2003), pp. 584-589. 2003.
A. Jutman, A. Sudnitson, R. Ubar. Web-based training system for teaching principles of boundary scan technique. In Proc. of 14th EAEEIE Ann. Conf. on Education in Electrical and Information Engineering, EAEEIE 2003 (Gdansk, June 2003), 4 pp. 2003.
A. Jutman, A. Sudnitsõn, R. Ubar, D. Wuttke. Java applets support for an asynchronous-mode learning of digital design and test. In Proc. of 4th Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2003 (Marrakech, July 2003), pp. 397-401. IEEE, 2003.
M. Kruus, A. Sudnitson. Virtual European Department of Computing project: problems and perspectives. In Proc. of 30th Int. Conf. on Information Technologies in Science, Education, Telecommunication, Business, IT+SE 2003 (Yalta-Gurzuf, May 2003), pp. 280-283. 2003.
J. Raik, T. Nõmmeots, R. Ubar. New method of testability calculation to guide RT-level test generation. In Proc. of 4th IEEE Latin-American Test Workshop, LATW 2003 (Natal, Feb. 2003), pp. 46-51. 2003.
J. Raik, R. Raidma, R. Ubar. Explorations in low area overhead DfT techniques for sequential BIST. In Proc. of 21st IEEE Conf. NORCHIP 2003 (Riga, Nov. 2003), pp. 220-223. 2003.
A. Schneider, K.-H. Diener, G. Elst, R. Ubar, E. Ivask, J. Raik. Integration of digital test tools to the Internet-based environment MOSCITO. In Proc. of 7th World Multiconf. on Systemics, Cybernetics and Informatics, SCI 2003 (Orlando, July 2003), pp. 136-141. IIIS, 2003.
A. Sudnitson, A. Jamshanov. A FSM decomposition method for mixed synchronous / asynchronous implementation. In Proc. of 17th Int. Conf. on Systems for Automation of Engineering and Research, SAER 2003 (Varna, Sept. 2003). 2003.
R. Ubar. Decision diagrams and digital test. In Proc. of 6th Int. Wksh. on Electronics, Control, Measurement and Signals (Liberec, June 2003), pp. 266-273. 2003.
R. Ubar. E-learning tools for the field of electronics design and test. In Proc. of 4th Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2003 (Marrakech, July 2003), pp. 285-290. 2003.
R. Ubar. Mapping faults in hierarchical testing of digital systems. In Proc. of Int. Conf. on Computer, Communication and Control Technologies, CCCT '03 (Orlando, July/Aug. 2003), pp. 14-19. IIIS, 2003.
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. Test time minimization for hybrid BIST with test pattern broadcasting. In Proc. of 21st IEEE NORCHIP Conf., 2003 (Riga, Nov. 2003), pp. 112-116. 2003.
R. Ubar, E. Orasson. E-learning tool and exercises for teaching digital test. In Proc. of 2nd IEEE Conf. on Signals, Systems, Decision and Information Technology (Sousse, March 2003), CIT-6, pp. 1-6. 2003.
R. Ubar, J. Raik, B. Klüver. Algorithms for hierarchical fault simulation in digital systems. In Proc. of 10th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2003 (Lodz, June 2003), pp. 530-535. 2003.
M. Brik, E. Ivask, J. Raik, R. Ubar. On using genetic algorithm for test generation. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 233-236. Tallinn Univ. of Techn., 2004.
P. Ellervee, J. Raik, V. Tihhomirov. Environment for fault simulation acceleration on FPGA. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 217-220. Tallinn Univ. of Techn., 2004.
E. Fomina, A. Sudnitson. Information relationships for decomposition of finite state machine. In Proc. of 2nd IEEE East-West Design and Test Wksh., EWDTW 2004 (Alushta, Sept. 2004), pp. 41-47. 2004.
E. Fomina, A. Sudnitson, R. Vasilyev. FSM's network encoding guided by information relationship measure. In Proc. of 6th Int. Wksh. on Boolean Problems (Freiberg, Sept. 2004), pp. 55-62. 2004.
E. Fomina, A. Sudnitsyn, R. Vasilyev. Optimization of FSMs network by new encoding strategy. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 119-122. Tallinn Univ. of Techn., 2004.
E. Fomina, P. Ellervee, M. Kruus, A. Sudnitson, K. Tammemae. Digital synthesis tools for education and research. In Proc. of 18th Int. Conf. on Systems for Automation of Engineering and Research, SAER 2004 (Varna, Sept. 2004), pp. 160-164. 2004.
E. Ivask, P. Ellervee. VHDL front-end for high-level synthesis tool xTractor. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 111-114. Tallinn Univ. of Techn., 2004.
E. Ivask, A. Jutman, E. Orasson, J. Raik, R. Ubar, H.-D. Wuttke. Research Environment for Teaching Digital Test. In Proc. of Int. Conf. IWK (Ilmenau, Sept. 2004), pp. 468-473. 2004.
A. Jutman, E. Gramatova, T. Pikula, R. Ubar. E-learning tools for teaching self-test of digital electronics. In Proc. of 15th EAEEIE Ann. Conf. on Innovation in Education for Electrical and Information Engineering (Sofia, May 2004), pp. 267-272. 2004.
A. Jutman, A. Peder, J. Raik, M. Tombak, R. Ubar. Structurally synthesized binary decision diagrams. In Proc. of 6th Int. Wksh. on Boolean Problems (Freiberg, Sept. 2004), pp. 271-278. 2004.
A. Jutman, A. Sudnitson, R. Ubar, H.-D. Wuttke. Asynchronous e-learning resources for hardware design issues. In Proc. of Int. Conf. on Computer Systems and Technologies, CompSysTech 2004 (Ruse, June 2004), v. IV, pp. 11.1-11.6, 2004.
A. Jutman, R. Ubar, H.-D. Wuttke. Overview of e-learning environment for Web-based study of testing and diagnostics of digital systems. In Pre-Proc. of 5th European Wksh. on Microelectronics Education, EWME 2004 (Lausanne, Apr. 2004), pp. 173-176. 2004.
A. Jutman, R. Ubar, H.-D. Wuttke. Overview of e-learning environment for Web-based study of testing and diagnostics of digital systems. In A. M., Ionescu, M. Declercq, M. Kayal, Y. Leblebici, eds., Proc. of 5th European Wksh. on Microelectronics Education, EWME 2004 (Lausanne, Apr. 2004), pp. 253-258. Kluwer Acad. Publ., 2004.
N. Mazurova, J. Smahtina, R. Ubar. Hybrid functional BIST for digital systems. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 205-208. TTU, 2004.
J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar. Fast fault emulation for synchronous sequential circuits. In Proc. of 2nd East-West Design and Test Wksh., EWDTW 2004 (Alushta, Sept. 2004), pp. 35-40. 2004.
J. Raik, A. Krivenko, R. Ubar. Comparative analysis of sequential test generation approaches. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 225-228. Tallinn Univ. of Techn., 2004.
J. Raik, E. Orasson, R. Ubar. Sequential circuits BIST with status BIT control. In Proc. of 11th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2004 (Szczecin, June 2004), pp. 507-510. 2004.
J. Raik, R. Ubar. Enhancing hierarchical ATPG with a functional fault model for multiplexers. In Proc. of 7th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2004 (Stara Lesna, Apr. 2004), pp. 219-222. 2004.
J. Raik, R. Ubar. Targeting conditional operations in sequential test pattern generation. In Proc. of 9th IEEE European Test Symp., ETS 2004 (Ajaccio, May 2004), pp. 17-18. 2004.
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, R. Ubar. Evolutionary approach to the functional test generation for digital circuits. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 229-232. Tallinn Univ. of Techn., 2004.
R. Ubar. Diagnostic modelling of digital systems with decision diagrams. In Proc. of Tomsk State University, v. 1, n. 9, pp. 174-179, 2004.
R. Ubar, M. Aarna, M. Brik, J. Raik. High-level fault modeling in digital systems. In Proc. of Int. Conf. IWK (Ilmenau, Sept. 2004), pp. 486-491. 2004.
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. An iterative approach to test time minimization for parallel hybrid BIST architecture. In Proc. of 5th IEEE Latin-American Test Wksh., LATW 2004, Digest of Papers (Cartagena, March 2004), pp. 98-103. 2004.
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. An iterative approach to test time minimization for parallel hybrid BIST architectures. In Proc. of System-on-Chip Conf. 2004 (Båstad, Apr. 2004). 2004.
R. Ubar, N. Mazurova, J. Smahtina, E. Orasson, J. Raik. HyFBIST: hybrid functional built-in self-test in microprogrammed data-paths of digital systems. In Proc. of 11th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2004 (Szczecin, June 2004), pp. 497-502. 2004.
R. Ubar, H.-D. Wuttke. Research and training scenarios for design and test of SOC. In Proc. of World Congress on Engineering and Technology Education (Guaruja/Santos, March 2004), pp. 320-324. 2004.
V. Vislogubov, A. Jutman, H. Kruus, E. Orasson, J. Raik, R. Ubar. Diagnostic software with WEB interface for teaching purposes. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 255-258. Tallinn Univ. of Techn., 2004.
M. Balas, M. Fisherova, E. Gramatova, A. Jutman, Z. Kotasek, O. Novak, T. Pikula, J. Raik, J. Strnadel, R. Ubar, J. Zahradka. Testing tools for training and education. In Proc. of 12th Int. Conf. Mixed Design of Integrated Circuits and Systems, MIXDES 2005 (Kraków, June 2005), pp. 671-676, 2005.
T. Bengtsson, A. Jutman, S. Kumar, R. Ubar. Delay testing of asynchronous NOC interconnects. In Proc. of 12th Int. Conf. Mixed Design of Integrated Circuits and Systems, MIXDES 2005 (Kraków, June 2005), pp. 419-424, 2005.
M. Brik, E. Fomina, R. Ubar. A proposal for optimisation of low-powered FSM testing. In Proc. of 3rd East-West Design & Test Wksh., EWDTW 2005 (Odessa, Sept. 2005), pp. 15-20, 2005.
E. Gramatová, R. Ubar, W.Pleskacz, M. Fischerová. Defects, faults, fault models. In O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems, ch. 2, pp. 26-96. Czech Techn. Univ. Publ. House, 2005.
E. Fomina, M. Brik, R. Vasilyev, A. Sudnitsyn. A new approach to state encoding of low power FSM. In Proc. of 3rd East-West Design & Test Wksh., EWDTW 2005 (Odessa, Sept. 2005), pp. 21-26, 2005.
E. Fomina, A. Sudnitson. Extended finite-state machine decomposition for low power. In Proc. of 19th Int. Conf. on Systems for Automation of Engineering and Research, SAER 2005 (Varna, Sept. 2005), pp. 126-131. 2005.
G. Jervan, Z. Peng, R. Ubar, O. Korelina. An improved estimation technique for hybrid BIST test set generation. In Proc. of 8th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2005 (Sopron, Apr. 2005), pp. 182-185. 2005.
A. Jutman. Efficient at-speed interconnect BIST and diagnosis framework. In Informal Digest of Papers of 10th IEEE European Test Symp., ETS 2005 (Tallinn, May 2005), pp. 257-258. Tallinn Univ. of Techn., 2005.
A. Jutman. At-speed BIST for board-level interconnect. In Proc. of IEEE European Board Test Wksh., EBTW 2005 (Tallinn, May 2005). 2005.
A. Jutman, M. Kruus, A. Sudnitson, R. Ubar, H.-D. Wuttke. Web-based software package for e-learning and research training in digital system design. In Proc. of 32nd Int. Conf. on Information Technologies in Science, Education, Telecommunication, Business, IT+SE 2005 (Gurzuf, May? 2005), pp. 306-308. 2005.
A. Jutman, V. Rosin, A. Sudnitson, R. Ubar, H.-D. Wuttke. A system for teaching basic and advanced topics of IEEE 1149.1 boundary scan standard. In Proc. of 16th EAEEIE Ann. Conf. on Innovation in Education for Electrical and Information Engineering (Lappeenranta, June 2005). 2005.
A. Jutman, R. Ubar, J. Raik. Generic interconnect BIST for network-on-chip. In Proc. of 8th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2005 (Sopron, Apr. 2005), pp. 224-227. 2005.
A. Jutman, R. Ubar, J. Raik. New built-in self-test scheme for SoC interconnect. In Proc. of 9th World Multi-Conf. on Systemics, Cybernetics and Informatics, SCI 2005 (Orlando, FL, July 2005), v. 4, pp. 19-24. IIIS, 2005.
A. Jutman, R. Ubar, V. Rosin. A software system for IEEE 1149.1 boundary scan design, simulation and demonstration. In Proc. of IEEE European Board Test Wksh., EBTW 2005 (Tallinn, May 2005). 2005.
A. Yu. Matrosova, A. G. Pleshkov, R. R. Ubar. Test generation for combinational circuits by orthogonal disjunctive normal forms and SSBDDs. Avtomatika i Telemekhanika, v. 2005, n. 2, pp. 158-174. 2005.
O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems. 402 pp. Czech Techn. Univ. Publ. House, 2005.
O. Novák, E. Gramatová, R. Ubar. IST project REASON - Handbook of testing electronic systems. In Proc. of 5th European Dependable Computing Conf., EDCC-5 (Budapest, Apr. 2005), pp. 15-18. IEEE, 2005.
J. Raik, R. Ubar, J. Sudbrock, W. Kuzmicz, W. Pleskacz. Deterministic defect-oriented test generation for digital circuits. In Proc. of 6th IEEE Latin-American Test Wksh., LATW 2005 (Salvador de Bahia, March/Apr. 2005), pp. 325-330. 2005.
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, R. Ubar, J. Raik. Evolutionary approach to test generation for functional BIST. In Informal Digest of Papers of 10th IEEE European Test Symp., ETS 2005 (Tallinn, May 2005), pp. 151-155. Tallinn Univ. of Techn., 2005.
R. Ubar. Decision diagrams and digital test (invited paper). In Proc. of 41th Int. Conf. on Microelectronics, Devices and Materials, MIDEM 2005 (Ribno at Bled, Sept. 2005), pp. 15-26. 2005.
R. Ubar. Digitaalsüsteemide diagnostika I: Diagnostiline modelleerimine. 148 lk. TTÜ Kirjastus, 2005.
R. Ubar. Introduction. In O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems, ch. 1, pp. 18-23. Czech Techn. Univ. Publ. House, 2005.
R. Ubar, E. Gramatová, M. Fischerová. Test generation techniques and algorithms. In O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems, ch. 3, pp. 99-173. Czech Techn. Univ. Publ. House, 2005.
T. Bengtsson, A. Jutman, S. Kumar, R. Ubar. Analysis of a test method for delay faults in NoC interconnects. In Proc. of 4th East-West Design and Test Wksh., EWDTW '06 (Sochi, Sept. 2006), pp. 42-46. Kharkov Univ. of Techn., 2006.
S. Devadze, J. Raik, A. Jutman, R. Ubar. Fault simulation with parallel critical path tracing for combinational circuits using structurally synthesized BDDs. In Proc. of IEEE Latin American Test Wksh., LATW 2006 (Buenos Aires, March 2006), pp. 97-102. IEEE, 2006.
P. Ellervee, G. Jervan. How to emulate network-on-chip? In Proc. of 4th East-West Design and Test Wksh., EWDTW '06 (Sochi, Sept. 2006), pp. 282-286. Kharkov Univ. of Techn., 2006.
P. Ellervee, J. Raik, K. Tammemäe, R. Ubar. Environment for FPGA based fault emulation. Proc. of Estonian Acad. Sci.: Engineering, v. 12, n. 2-3, pp. 323-335, 2006.
P. Ellervee, U. Reinsalu, A. Arhipov. Teaching HDL for IT-students. In L.-R. Zheng, J. Nurmi, J. Liu, R.Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 112-115. KTH, 2006.
G. Jervan, A. Arhipov, P. Ellervee. FPGA based emulation environment. In Proc. of 2nd Int. Wksh. on Reconfigurable Communication.Centric Systems-on-Chip, ReCoSoc '06 (Montpellier, July 2006), pp. 146-151. Univ. Montpellier II, 2006.
G. Jervan, R. Ubar, Z. Peng. Hybrid BIST methodology for testing core-based systems. Proc. of Estonian Acad. Sci.: Engineering, v. 12, n. 2-3, pp. 300-322, 2006.
A. Jutman, W. Pleskacz, N. Boiko, R. Ubar. DefSim-based exercises for studying defects in CMOS gates. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. ?-?. Kungl. Tekn. Högskolan, 2006.
A. Jutman, A. Tsertov, R. Ubar. A tool for teaching pseudo-random TPG principles. In Proc. of 17th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering (Craiova, June 2006), pp. 182-187. Editura Universitaria Craiova, 2006.
A. Jutman, R. Ubar, V. Rosin, S. Devadze. Trainer 1149.1: a boundary-scan simulator. In Proc. of 5th IEEE Int. Board Test Wksh., BTW 2006 (Fort Collins, CO, Sept. 2006), ? pp. 2006.
M. Kruus, P. Ellervee. Four years of system-on-chip curricula: Experiences at Tallinn University of Technology. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 88-91. Kungl. Tekn. Högskolan, 2006.
W. Pleskacz, T. Borejko, A. Walkanis, V. Stopjakova, A. Jutman, Artur, R. Ubar. DefSim: CMOS defects on chip for research and education. In Proc. of 7th IEEE Latin-American Test Wksh., LATW 2006 (Buenos Aires, March 2006), pp. 74-79. IEEE, 2006.
T. Robal, M. Aarna, M. Brik. e-learning of digital logic: Using e-environments in teaching digital logic. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 120-123. Kungl. Tekn. Högskolan, 2006.
A. Smrikarov, S. Smrikarova, M. Kruus, A. Sudnitson. European thematic network for doctoral education in computing. In Proc. of 33rd Int. Conf. on Information Technologies in Science, Education, Telecommunication, Business, IT+SE 2006 (Gurzuf, May 2006), pp. 339-340. 2006.
A. Sudnitson, S. Devadze. Computer aided design support of FSM multiplicative decomposition. In Proc. of 4th East-West Design and Test Wksh., EWDTW '06 (Sochi, Sept. 2006), pp. 241-246. Kharkov Univ. of Techn., 2006.
A. Sudnitson, M. Kruus. E-learning tools for teaching the decomposition based digital synthesis. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 63-66. Kungl. Tekn. Högskolan, 2006.
R. Ubar, A. Jutman, M. Kruus, H.-D. Wuttke. Applets for learning digital design and test. In Proc. of 1st Int. Conf. on Interactive Mobile and Computer Aided Learning, IMCL 2006 (Amman, Apr. 2006), pp. 1-6?. Univ. Kassel, 2006.
R. Ubar, M. Kruus. Success story of the Computer Engineering Department at the Tallinn University of Technology in EU projects. The Parliament Magazine: European Politics and Policy, n. 234, pp. 33, 2006.
R. Ubar, J. Raik, A. Jutman, P. Ellervee. Digital electronics design and test at Computer Engineering Department of Tallinn University of Technology. The House Magazine: The Parlamentary Weekly, v. 32, n. 1198, p. 42, 2006.
H.-D. Wuttke, A. Sudnitson, K. Henke. E-learning tools for teaching the design and validation of finite state machines. In E-Learning and the Knowledge Society, pp. 327-341. Communication and Cognition, Gent, 2006.
P. Ellervee, A. Arhipov, U. Reinsalu. Using emulation for system model analysis. In Wksh. Digest of DATE 2007 Wksh. on Diagnostic Services in Network-on-Chips: Test, Debug and On-Line Monitoring (Nice, Apr. 2007), pp. 280-282. 2007.
P. Ellervee, U. Reinsalu, A. Arhipov. Translating behavioral VHDL for emulation. In Proc. of 25th IEEE NorChip Conf. 2007 (Aalborg, Nov. 2007), pp. ?-?. IEEE, 2007.
G. Guglielmo, F. Fummi, M. Jenihhin, G. Pravadelli, J. Raik, R. Ubar. On the combined use of HLDDs and EFSMs for functional ATPG. In Proc. of 5th IEEE East-West Design and Test Symp., EWDTS 2007 (Yerevan, Sept. 2007), pp. 503-509. IEEE, 2007.
M. Jenihhin, J. Raik, A. Chepurov, R. Ubar. Assertion checking with PSL and high-level decision diagrams. In Proc. of 8th IEEE Wksh. on RTL and High Level Testing, WRTLT '07 (Beijing, Oct. 2007), pp. ?-?. IEEE, 2007.
A. Mellik, J. Raik. Comparative mixed-signal test method and toolset. In Proc. of IEEE Int. Wksh. on Open Source Test Technology Tools, IOST3 2007 (Berkeley, CA, May 2007), ? pp. 2007.
J. Raik, V. Govind, R. Ubar. An external diagnosis method for network-on-a-chip. In Wksh. Digest of DATE 2007 Wksh. on Diagnostic Services in Network-on-Chips: Test, Debug and On-Line Monitoring (Nice, Apr. 2007), pp. ?-?. 2007.
J. Raik, R. Ubar, M. Jenihhin, A. Chepurov. PSL assertion checking with temporally extended high-level decision diagrams. In Proc. of 9th IEEE Latin-American Test Wksh. (Puebla, Feb. 2008), IEEE, to appear.
J. Raik, R. Ubar, A. Jutman, I. Aleksejev. A scalable test set compaction method for sequential circuits. In Proc. of 9th IEEE Latin-American Test Wksh. (Puebla, Feb. 2008), IEEE, to appear.
J. Raik, R. Ubar, T. Viilukas, M. Jenihhin. Mixed hierarchical-functional fault models for targeting sequential cores. J. of Systems Architecture, to appear.
A. Sudnitson, S. Devadze. Web-based computer aided design support of finite state machine additive decomposition for low power. In Proc. of 5th IEEE East-West Design and Test Symp., EWDTS 2007 (Yerevan, Sept. 2007), pp. 494-498. IEEE, 2007.
M. Tagel, G. Jervan. Deterministic traffic generator for NoC simulator. In Wksh. Digest of DATE 2007 Wksh. on Diagnostic Services in Network-on-Chips: Test, Debug and On-Line Monitoring (Nice, Apr. 2007), pp. 288-290. 2007.
R. Ubar, S. Devadze, M. Jenihhin, J. Raik, G. Jervan, P. Ellervee. Hierarchical calculation of malicious faults for evaluating the fault-tolerance. In Proc. of 4th IEEE Int. Symp. on Electronic Design, Test and Applications, DELTA '08 (Hongkong, Jan. 2008), IEEE, to appear.
R. Ubar, S. Devadze, J. Raik, A. Jutman. Parallel fault backtracing for calculation of fault coverage. In Proc. of Int. Conf. on Microelectronics, Devices and Materials and Wksh. on Electronic Testing, MIDEM '07 (Bled, Sept. 2007), pp. 165-170. MIDEM, 2007.
R. Ubar, S. Devadze, J. Raik, A. Jutman. Parallel Fault Backtracing for Calculation of Fault Coverage. In Proc. of 13th Asia and South Pacific Design Automation Conf., ASP-DAC 2008 (Seoul, Jan. 2008), IEEE, to appear.
R. Ubar, T. Evartson, H. Lensen, M. Aarna. Hierarchical fault diagnosis in embedded digital systems with multi-level decision diagrams. In Proc. of 5th Int. Conf. on Industrial Automation (Montréal, July 2007), pp. 1-6. 2007.
R. Ubar, G. Jervan, J. Raik, M. Jenihhin, P. Ellervee. Dependability evaluation in fault-tolerant systems with high-level decision diagrams. In Proc. of 52nd Int. Scientific Coll., IWK 2007 (Ilmenau, Sept. 2007), v. 2, pp. 147-152. Universitätsverlag Ilmenau, 2007.
R. Ubar, A. Jutman, S. Devadze, H.-D. Wuttke. Bringing research issues into lab scenarios on the example of SoC testing. In Proc. of 2007 Int. Conf. on Engineering Education, ICEE 2007 (Coimbra, Sept. 2007), pp. ?-?. 2007.
R. Ubar, S. Kostin, J. Raik. Built-in self diagnosis with multiple signature analyzers in digital systems. In Proc. of 9th IEEE Latin-American Test Wksh., LATW 2008 (Puebla, Feb. 2008), IEEE, to appear.
R. Ubar, S. Kostin, J. Raik. Embedded diagnosis in digital systems. In Proc. of 26th Int. Conf. on Microelectronics, MIEL 2008 (Nis, May 2008), IEEE, to appear.
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