Source: https://www.intel.com/content/www/us/en/programmable/documentation/nik1412640107351.html
Timestamp: 2019-04-19 21:14:41+00:00

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The Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices require a specific power-up and power-down sequence. This document describes several power management options and discusses proper I/O management during device power-up and power-down. Design your power supply solution to properly control the complete power sequence.
The requirements in this document must be followed to prevent unnecessary current draw to the FPGA device. Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The tables below also show what the unpowered pins can tolerate during power-up and power-down sequences.
Table 2. Pin Tolerance – Power-Up/Power-Down'√' is Acceptable; '-' is Not Applicable.
1 The maximum current allowed through any LVDS I/O bank pin when the device is unpowered or during power up/down conditions = 10 mA (refer to "LVDS I/O Pin Guidance for Unpowered FPGA Pins").
2 This applies to Intel® Stratix® 10 L-tile/H-tile only (refer to "Transceiver Pin Guidance for Unpowered FPGA Transceiver Pins").
The power rails in Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices are each divided into three groups. Refer to the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines , Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines , Intel® Stratix® 10 Device Family Pin Connection Guidelines , and the Intel® Stratix® 10 Power Management User Guide for additional details.
The diagram below illustrates the voltage groups of the Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices and their required power-up sequence.
For Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rail VCCPT. Exception: E-tile devices must maintain voltage rail groupings for power-up sequencing as stated in the table above. VCCCLK_GXE must power up before VCCIO_SDM.
All power rails must ramp up monotonically. The power-up sequence should meet either the standard or the fast Power On Reset (POR) delay time. The POR delay time depends on the POR delay setting you use.
4 PCIe* hard IP to initialize after POR trip.
Intel's FPGAs need to follow certain requirements during a power-down sequence. The power-down sequence can be a controlled power-down event via an on/off switch or an uncontrolled event as with a power supply collapse. In either case, you must follow a specific power-down sequence. Below are three power-down sequence specifications. They are either Recommended Power-Down Ramp, Required Power-Down Ramp, or Required Voltage Differential. To comply with Intel® ’s FPGA Power-Down requirements, the Recommended option is best.
Note: If you cannot follow the Recommended specification, you must follow the Required specification. The Required specification includes both the Power-Down Ramp and the Voltage Differential specifications.
For Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices, you can combine and ramp down Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as the Group 2 power rails.
For supplies powered down with no active discharge, voltage reduction to GND slows down as supply approaches 0 V. In this case, the 100 ms power requirement is relaxed.
Using a programmable power management controller provides a full-featured option to implement the power sequencing requirements.
These controllers provide the necessary power-up/down sequence control functions. These controllers can dynamically monitor and scale the regulator's output voltage, and supervise fault conditions such as over voltage or under voltage. To program the power management controller, typically a PMBus or I2C interface is used to connect to an intelligent host such as the system's microprocessor.
PPMC can be an optimal solution for systems in which up-time and fault tolerance are critical features and voltage monitoring and fault reporting are essential system requirements.
Differential sense line inputs to remotely monitor the load voltage.
Digital-to-Analog Converter (DAC) outputs to trim the regular output voltages. The DAC outputs drive the regulator's feedback input (fb) and control the regulator's output voltage.
Enable Outputs (EN1, EN2, ...ENn) that drive the voltage regulator's Enable Inputs (en). The regulator's enable inputs control the desired power-up/down sequence.
Typically, PPMC devices have multiple channels so that a single controller can sequence multiple regulators. If more channels are required than what is offered by a single device, then multiple devices can be cascaded. A separate host interface (PMBus or I2C) is used to connect the system processor and the PPMC to manage the controller software and programming.
Consult your power module vendor for more information about PPMC.
If only a simple power-up/power-down sequencing is required to follow the Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices power sequencing considerations, a low-cost multiple supply sequencer IC can be used.
These devices offer multiple sequenced output enables that are controlled by a dedicated input. When the input is switched on, the Output Enables (EN1/ EN2 /EN3) turn on in successive order after a programmed time delay. This time delay between the output enables can be adjusted.
Consult your power module vendor for more information about multiple supply sequencer ICs.
A discrete sequencer design is a low-cost option in which the charging and discharging voltage of a simple resistor-capacitor (RC) network and preset reference voltage levels are used.
The RC ramp-up/down voltage is compared with preset reference voltage levels to generate a series of sequenced power enable outputs to control the voltage regulators.
The power-on event triggers the capacitor charging. As the capacitor voltage rises above each of the preset reference voltage levels, the power enable outputs are sequentially turned on. Similarly, for the power-down event, the discharging of the capacitor causes the power enable outputs to turn off in the reverse sequential order.
The example design for the simple low-cost power-up/down sequencer uses a quad comparator IC (U1) and discrete resistors and capacitors (Recommended Version).
A system standby voltage VCC_stby is always present to power the comparator U1A. A reference voltage Vref is generated from VCC_stby through resistor dividers R3 and R4. Vref is the reference voltage for the inverting input of comparator U1A. A more accurate Vref can be generated using a precision trimmed zener diode in place of resistor R4. The resistor ladder network consists of resistors R7, R8, R9, and R10. This ladder network further divides the reference voltages V3, V2, and V1. Comparator (U1B, U1C, and U1D) outputs drive the associated regulator enables (En_reg3, En_Reg2, En_Reg1). These outputs turn On/Off the voltage regulators (not shown). Switch S1 is the system power On/Off switch.
Initially, the power sequencer circuit is not operational because the power switch S1 is open. As a result, all regulator enables (En_Reg1, En_Reg2, and En_Reg3) are low. As the regulator enables drive the voltage regulators, all voltage regulators are turned off.
When switch S1 is closed, the system turns on and the voltage VCC charges the capacitor C1 to voltage level Vin.
C1 is charged through resistor R1. Voltage level Vin depends on the values of R1 and R2 which form voltage divider and Vin = (R2/(R1+R2))*VCC. R1 and R2 are selected such that the value of Vin is slightly higher than comparator U1A's reference voltage Vref.
When the value of Vin rises above Vref, comparator U1A's output goes high and capacitor C4 starts charging through resistor R5.
Resistors R5 and R6 set the ramp voltage Vramp. Resistor R5 and capacitor C4 define the time constant for the ramp rate of Vramp. Vramp is the input voltage to the non-inverting inputs of comparators U1B, U1C, and U1D. As Vramp rises above the voltage references (V1, V2, and V3), it sequentially trips comparators U1D, U1C, and U1B, turning on regulator enables En_Reg1, En_Reg2, and En_Reg3.
The order of the power-down sequence is reverse of the power-up sequence.
When switch S1 is opened, the system starts shutting down. Capacitor C1 starts discharging through R2. R2 and C1 set the decay rate of Vin during the power-down cycle.
When Vin falls below Vref, comparator U1A's output turns off. This discharges Vramp through the parallel combination of R5 and R6.
As Vramp discharges below V3, V2, and V1, the comparators U1B, U1C and U1D sequentially turn off their regulator enables.
This example circuit can be easily expanded to support more regulator enable (reg_en) outputs.
To expand the circuit, add more comparators and extend the resistor ladder network to generate additional reference voltage comparison points (for example, V4, V5, etc). Also, increase the Vramp charging/discharging rate to allow more time between the additional regulator enables. This time delay is controlled by the time constant determined by R5, R6, and C4.
The following figure shows a conceptual implementation for managing uncontrolled power loss events.
The Power Management Circuit (in the above diagram) is powered directly from the VIN high-side DC input voltage, but can operate down to 5 V. You may need CHOLD to maintain sufficient charge to keep the Power Management Circuitry operational during loss of power events. CDECAP Group 1-3 represents the total decoupling capacitance associated with each power rail grouping. RDISCHARGE 2-3 and its associated power FETs enable fast discharging of each power group voltage to 0 V when you initiate a shutdown sequence. The fast discharging circuit speeds up the power-down cycle of each rail (as the natural RC discharge decay is very slow) and can also define the order in which the rails discharge by trimming RDISCHARGE. Without the fast discharge circuit, the shutdown time can be very long, requiring a larger capacitance for CHOLD.
While the system is running, the high-side DC input is maintained at VIN +/-10% tolerance. The power loss detection circuit continuously monitors the DC input for a loss of power event. This detection circuit can be a simple comparator with a reference voltage set to a threshold slightly below the -10% threshold, or it can be an Analog-to-Digital Converter (ADC) employing multiple successive samplings to discriminate against false power interruptions.
When a valid loss of power event occurs, the detection circuit generates a reset to the system. The reset signal pulls the FPGAs’ NCONFIG signal low to reduce the device’s operational current to just its static quiescent value. Concurrently, the Power Management Circuit is triggered to initiate a shutdown sequence. This reduces the value of CHOLD needed to support the Power Management Circuitry during the shutdown process.
Consider an FPGA system that has total quiescent current of 25 A when the system is under reset (FPGA leakage and total system standby current), and the hold time of the capacitor needs to be 1 ms as the voltage drops from 10 V to 5 V. Also, assume that the voltage rail is 0.9 V.
Determine the CHOLD capacitance required for the Power Management Controller to maintain operation so that you can complete a proper power-down sequence.
Some sequencers on the market may simultaneously bring all voltage rails down instead of powering the voltage rails down sequentially.
Take care when selecting a design for controlling the sequence during a fault condition. Non-sequential power-down controllers can violate the power-down specification of the Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices. External active discharge and trimming RDISCHARGE can alleviate this problem (refer to the "Fault Tolerant Block Diagram (Required Version)" in Managing Uncontrolled Loss of Power Events ).
There are voltage regulators on the market that clamp the output to GND in the event of a fault condition. This type of control can be disabled. Group 2 can be clamped only if it is clamped with the same control signal as Group 3. Otherwise, make sure that regulators in Group 1 and Group 2 do not have this option enabled.
Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 device LVDS I/O pins do not support ‘Hot-Socketing;’ these LVDS I/O pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per I/O bank. The voltage level must not exceed 1.89 V.
A series resistor can be used to help limit current if necessary. The worst case assumption is that VCCIO is ~0 V. If diode D2 is biased by 1.8 V, impedance into VCCIO is extremely low (refer to the figure below).
Fully configure the transceiver block before driving or having any activity on the Intel® Cyclone® 10 GX and Intel® Arria® 10 device transceiver pins.
Intel® Stratix® 10 device transceiver pins do not support ‘Hot-Socketing’ although these transceiver pins can tolerate 1.0 Vp-p during power-up or power-down. This applies to L-tile and H-tile devices only.
Added E-tile voltage rails and power-up exception to Power-Up Sequence Requirements .
Changed Original Text: For Intel® Cyclone® 10 GX and Intel® Arria® 10 devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rails VCCIO, VCCPGM, and VCCIO_HPS. to Updated Text: For Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rail VCCPT.
Changed 1.1 Vp-p references to 1.0 Vp-p.
Deleted the note: To satisfy the power-up requirements, program the FPGA device immediately after the power-up sequence completes.
Added links to References and moved it to the beginning.
Added "Sequential vs Simultaneous Power-Down."
Added "Voltage Regulators with Clamping Capability."
Added "Driving Unpowered FPGA Pins" - "LVDS I/O Pin Guidance for Unpowered FPGA" and "Transceiver Pin Guidance for Unpowered FPGA."
Added POR Delay specifications for Intel® Cyclone® 10 GX and Intel® Arria® 10.
Added the following description for power-down sequence for Intel® Arria® 10 and Intel® Stratix® 10 devices "For Arria 10 and Stratix 10 devices, when the Group 3 power rails are 1.8V and share the same voltage regulator, then the Group 3 power rails can be combined with Group 2 power rails. In this case, Group 2 and Group 3 power rails can ramp down together." Updated the diagrams accordingly.
Added the following note in "Hot-Plug Challenges" topic: "There are hot socket circuits in every 6-pack to monitor VCC, VCCT and VCCR power level. If any of those power supplies are not at operational level, all PMA outputs and inputs are gated low."
In the section "Hot Swap Controller and Regulator" updated the description to "When the line card is fully engaged, the card present indicator informs the host that a new card has been successfully inserted. The CONF_DONE signal should then be routed back to the master and sampled as an enable to the signals that are driven. This ensures that configuration is done, the device is stable, and that the master can drive the I/O to the newly powered up slave device without fear of damaging the part. The host system drives the line card's I/O pins and configures it for normal operation."
In the "Hot-Plug Example" section added 2 new diagrams for "Hot-Plug Example using Staggered Pin Length Connectors."
In topic "Power Sequence for Arria 10 and Stratix 10 Devices" for figure "Power-Down Sequence for Arria 10 Devices for combined Group2 and Group3 powers" edited the description to "During the power-up/down sequence, the device output pins are tri-stated. Intel recommends that the input pins should not be driven during this time to ensure long term reliability of the device."
Added new figures for "Power-Down Sequence for Arria 10 Devices", "Power-Down Sequence for Stratix 10 Devices" and "Power-Down Sequence for Arria 10 Devices for combined Group2 and Group3 powers".
Added the "Power-Up Sequence Considerations for Stratix 10 Devices".
Added a new section for "Managing Uncontrolled Loss of Power Events".
Added a new figure for "Power-Up Sequence for Stratix 10 Devices".
Clarified information in the "Power-Up Sequence for Arria 10 Devices" section.
2013.09.06 Initial release to MOLSON.

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