Source: https://patents.google.com/patent/US7426140B2/en
Timestamp: 2019-04-19 22:46:31+00:00

Document:
This application is a continuation of U.S. patent application Ser. No. 11/324,581, filed Jan. 3, 2006, now U.S. Pat. No. 7,315,474 which is based upon, and claims priority under 35 U.S.C. §119(e) of: provisional U.S. Patent Application No. 60/640,229, filed on Jan. 3, 2005; provisional U.S. Patent Application No. 60/647,012, filed on Jan. 27, 2005; provisional U.S. Patent Application No. 60/689,231, filed on Jun. 10, 2005; and provisional U.S. patent application No. 60/689,314, filed on Jun. 10, 2005; the entire contents of each of which are incorporated herein by reference.
As used herein, the phrase “small hole tunneling barrier height” refers generally to values which are less than or equal to the approximate hole tunneling barrier height of silicon dioxide. In particular, a small hole tunneling barrier height is preferably less than or equal to about 4.5 eV. More preferably, a small hole tunneling barrier height is less than or equal to about 1.9 eV.
FIGS. 5 c and 5 d illustrate another set of band diagrams in one example. For a better band offset condition in one example, the thickness of N1 may be larger than that of O1. The band diagram of valence band is plotted at the same electrical field E01=14 MV/cm. The tunneling probability according to WKB approximation is correlated to the shadow area. In this example, for N1=O1 in thickness, the band offset does not completely screen out the barrier of O2. On the other hand, for N1>O1, the band offset can more easily screen out O1. Therefore, for N1>O1 in thickness, the hole tunneling current may be larger under the same electrical field in O1.
As noted above, a tunnel dielectric layer may include two or more layers, including one layer that may provide a small hole-tunneling-barrier height. In one example, the layer providing a small hole-tunneling-barrier height may contain silicon nitride. The layer may be sandwiched between two silicon oxide layers, thereby forming an O/N/O tunnel dielectric if silicon nitride is used as the intermediate layer. In certain preferred embodiments of the present invention, each layer in a tunnel dielectric structure is up to about 4 nm thick. In some preferred embodiments, each of the layers in the tunnel dielectric structure can have a thickness of about 1 nm to 3 nm. In one exemplary device, a tri-layer structure may have a bottom layer, such as a silicon oxide layer, of about 10 Å to 30 Å, an intermediate layer, such as a silicon nitride layer, of about 10 Å to 30 Å, and a top layer, such as another silicon oxide layer, of about 10 Å to 30 Å. In one particular example, an O/N/O tri-layer structure having a 15 Å bottom silicon oxide layer, a 20 Å intermediate silicon nitride layer, and an 18 Å top silicon oxide layer may be used.
An exemplary device in accordance with an embodiment of the present invention having a high work function gate material may also be fabricated by 0.12 μm NROM/NBit technologies. Table 2 shows the device structure and parameters in one example. The proposed tunnel dielectric with an ultra-thin O/N/O may alter the hole tunneling current. A thicker (7 nm) N2 layer may serve as a charge-trapping layer and an O3 (9 nm) layer may serve as the blocking layer in one example. Both N2 and O3 may be fabricated using NROM/NBit technologies.
In accordance with certain embodiments of memory cells of the present invention having high work function gate materials, wherein the high work function gate suppresses gate electron injection, the threshold voltage of the device in an erased or reset state can be much lower, and even negative, depending upon erase time. The threshold voltage values of a memory device in accordance with one embodiment of the present invention wherein the gate is comprised of platinum and the tunnel dielectric layer comprises a 15/20/18 angstrom ONO structure are shown in FIG. 7 b. As shown in FIG. 7 b, at a similar gate voltage (−18 V) during a−FN erase operation, the flat band voltage (which correlates with threshold voltage) of the device can be set below −3V. The corresponding capacitance versus gate voltage values for the device are shown in FIG. 7 c.
FIGS. 14 a and 14 b illustrate possible electrical RESET schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. Before performing further P/E cycles, all the devices may first undergo an electrical “RESET”. A RESET process may ensure the Vt uniformity of memory cells in the same array and raise the device Vt to the convergent erased state. For example, applying Vg=−15 V for 1 sec, as shown in FIG. 14 a, may have the effect of injecting some charge into a charge trapping layer of silicon nitride to reach a dynamic balancing condition. With the RESET, even memory cells that are non-uniformly charged due, for example, to the plasma charging effect during their fabrication processes may have their Vt converged. An alternative way for creating a self-converging bias condition is to provide bias for both gate and substrate voltages. For example, referring to FIG. 14 b, Vg=−8 V and P-well=+7 V may be applied.
FIGS. 16 a and 16 b illustrate reading schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. In one example, reverse read is used to read the device to perform a 2 bits/cell operation. Referring to FIG. 16 a, for reading Bit-1, BLN-1 is applied with a suitable read voltage, such as 1.6 V. Referring to FIG. 16 b, for reading bit-2, BLN is applied with a suitable read voltage, such as 1.6V. In one example, the reading voltage may be in the range of about 1 to 2 V. The word lines and the P-well may be 13 kept grounded. However, other modified read schemes, such as a raised-Vs reverse read method can be performed. For example, a raised-Vs reverse read method may use Vd/Vs=1.8/0.2 V for reading Bit-2, and Vd/Vs=0.2/1.8 for reading Bit-1.
FIG. 25 illustrates an example of operating a memory array. Programming may include channel +FN injection of electrons into an SONONOS nitride trapping layer. Some examples may include applying Vg=about +18 V to the selected WLN−1, and applying VG=about +10 V to other WLs, as well as the BLT. The SLT can be turned off to avoid channel hot electron injection in cell B. In this example, because all the transistors in the NAND string are turned-on, the inversion layer passes through the strings. Furthermore, because BL1 is grounded, the inversion layer in BL1 has zero potential. On the other hand, other BLs are raised to a high potential, such as a voltage of about +7 V, so that the inversion layer of other BLs are higher.
In some examples, a split-gate design, such as a split-gate SONONOS-NAND design, may be used to achieve a more aggressive down-scaling of a memory array. FIG. 31 illustrates an example of using such design. Referring to FIG. 31, the spaces (Ls) between each word line, or between two neighboring memory devices sharing the same bit line, may be reduced. In one example, Ls may be shrunk to about or less than 30 nm. As illustrated, the memory devices using a split-gate design along the same bit line may share only one source region and one drain region. In other words, a split-gate SONONOS-NAND array may use no diffusion regions or junctions, such as N+-doped regions, for some of the memory devices. In one example, the design may also reduce or eliminate the need for shallow junctions and neighboring “pockets”, which in some examples may involve a more complicated manufacturing process. Furthermore, in some examples, the design is less affected by short-channel effects, because the channel length has been increased, such as increased to Lg=2F−Ls in one example.
In one example, the space Ls between neighboring memory devices along the same bit line may be in the range of about 15 nm to about 30 nm. As noted above, the effective channel length may be enlarged to 2F−Ls in this example. In one example, if F is about 30 nm and Ls is about 15 nm, Leff is about 45 nm. For the operation of those exemplary memory devices, the gate voltage may be reduced to below 15 V. In addition, the inter-polysilicon voltage drop between word lines may be designed to be no larger than 7V to avoid breakdown of the spacers in the Ls spaces. In one example, this may be achieved by having an electric field of less than 5 MV/cm between neighboring word lines.
FIG. 33 is a graph of change in threshold voltage of a MOSFET having an ultra-thin multi layer gate dielectric (O1/N1/O2=15/20/18 Angstroms) versus an number of shots of program disturb bias pulses or erase disturb bias pulses showing negligible charge trapping in the ONO gate dielectric regardless of the injection mode CHE, +FN, −FN in an exemplary device with a tunneling dielectric.
FIG. 34 is a graph of change in gate voltage versus time under constant current stress in an ultra-thin ONO (O1/N1/O2=15/20/18) dielectric capacitor, demonstrating small charge trapping under negative gate current stress and indicating excellent stress tolerance. The small trapping efficiency may be due to that the capture mean free path is much longer than the nitride thickness of about 20 Angstroms. This suggests that the N1 layer less than 20 Angstroms is desirable. In addition, no interfacial traps between O1/N1 and N 1/O2 are introduced during processing in preferred embodiments.
FIG. 38 is a graph of flat band voltage versus time for +FN programming characteristics at VG equal to +19, +20 and +21 volts, for an exemplary device having a P+-poly gate and an ONONO=15/20/18/70/90 Angstroms. As illustrated in FIG. 38, a large memory window (as much as about 7 V in this graph) can be obtained within 10 msec and a 3 V memory window can be achieved in less than 200 μsec.
wherein the semiconductor body includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, the multiple-gate channel region having one of n-type and p-type conductivity.
2. The device of claim 1, including dielectric charge trapping locations beneath all the gates in the series.
3. The device of claim 1, wherein the series of gates includes more than two gates, and the charge storage structure includes dielectric charge trapping locations beneath more than two gates in the series of gates having more than two gates.
4. The device of claim 1, wherein the insulating members isolating the gates in the series have thicknesses less than 30 nm between adjacent gates.
wherein the tunnel dielectric structure is adapted for Fowler Nordheim FN hole tunneling to the charge trapping layer to lower the threshold voltage by at least 2 volts in less than 100 msec.
6. The device of claim 5, wherein the tunnel dielectric structure is adapted for Fowler Nordheim FN hole tunneling to the charge trapping layer to lower the threshold voltage from the target threshold voltage by about 2 Volts in about 50 msec or less.
7. The device of claim 5, wherein the tunnel dielectric structure is adapted for Fowler Nordheim FN hole tunneling to the charge trapping layer to lower the threshold voltage from the target threshold voltage by about 6 Volts in about 100 msec or less.
8. The device of claim 1, wherein the gates in the plurality of gates comprise a material having a word function greater than n-type polysilicon.
9. The device of claim 1, wherein the gates in the plurality of gates comprise p-type silicon.
10. The device of claim 1, wherein the gates in the plurality of gates comprise platinum.
11. The device of claim 5, wherein the bottom dielectric layer has a thickness less than that of the middle dielectric layer.
12. The device of claim 5, wherein the middle dielectric layer has a thickness such that an electric field applied during FN hole tunneling is sufficient to substantially eliminate the hole tunneling barrier of the middle dielectric layer and the top dielectric layer of the tunnel dielectric structure.
13. The device of claim 5, wherein the bottom dielectric layer comprises silicon dioxide, the middle dielectric layer comprises silicon nitride, the top dielectric layer comprises silicon dioxide, the charge storage layer comprises silicon nitride and the insulating layer comprises silicon dioxide.
14. The device of claim 13, wherein the gate comprises p-type silicon.
the insulating layer comprising a blocking dielectric layer on the charge trapping layer having a hole tunneling barrier height greater than that of the dielectric charge trapping layer, and having a thickness greater than 5 nm.
16. The device of claim 1, wherein the thickness of the bottom dielectric layer is less than or equal to 18 Angstroms.
17. The device of claim 1, wherein the thickness of the bottom dielectric layer is less than or equal to 15 Angstroms.
18. The device of claim 1, wherein the thickness of the middle dielectric layer is greater than the thickness of the bottom dielectric layer.
19. The device of claim 15, wherein the dielectric charge trapping layer thickness is between about 50 Angstroms and about 100 Angstroms.
20. The device of claim 15, wherein the blocking dielectric layer has a thickness between about 50 Angstroms and about 120 Angstroms.
21. The device of claim 1, wherein the bottom dielectric layer comprises silicon dioxide, the middle dielectric layer comprises silicon nitride, and the top dielectric layer comprises silicon dioxide.
22. The device of claim 15, wherein the dielectric charge trapping layer comprises silicon nitride and the blocking dielectric layer comprises silicon dioxide.
23. The device of claim 15, wherein the gates in the plurality of gates comprise p-type silicon.
24. The device of claim 15, wherein the gates in the plurality of gates comprise platinum.
25. The device of claim 15, including bias structures arranged to apply a negative voltage of about 20 Volts or less, across a gate in the plurality of gates and the channel to induce FN hole tunneling sufficient to decrease a threshold voltage by at least 2 Volts in less than 100 msec.
26. The device of claim 15, including bias structures arranged to apply a negative voltage of about 20 Volts or less, across a gate in the plurality of gates and the channel to induce FN hole tunneling sufficient to decrease a threshold voltage by at least 2 Volts in less than 10 msec.
a blocking silicon oxide layer on the silicon nitride charge trapping layer and having a thickness of 50 Angstroms or greater.
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