Source: https://patents.google.com/patent/US8972472B2/en
Timestamp: 2019-04-23 12:23:14+00:00

Document:
A system and method for unbiased rounding away from, or toward, zero by truncating N bits from a M bit input number to provide a M−N bit number, and adding the equivalent value of ‘½’ to the M−N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½. The method for rounding away from zero may include outputting a (M−N) bit truncated number if the M-bit input number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical operation on the most significant bit of the sequence of truncated bits and (b) the (M−N) bit truncated number.
This application is a National Phase Application of PCT International Application No. PCT/IL2008/001240, entitled “APPARATUS AND METHODS FOR HARDWARE-EFFICIENT UNBIASED ROUNDING”, International Filing Date Sep. 17, 2008, published on Oct. 1, 2009 as International Publication No. WO 2009/118720, which in turn claims priority from US Provisional Application No. 61/064,760, filed Mar. 25, 2008 and entitled “Hardware Efficient Implementation of Rounding in Fixed-Point Arithmetic” and US Provisional Application No. 61/071,404, filed Apr. 28, 2008 and entitled “Apparatus and Methods for Hardware-Efficient Unbiased Rounding”, all of which are incorporated herein by reference in their entirety.
Other co-pending applications include: U.S. Provisional Application No. 60/960,207, filed Sep. 20, 2007 and entitled “Systems and Methods for Coupling Detection in Flash Memory”, U.S. Provisional Application No. 61/071,467, filed Apr. 30, 2008 and entitled “Improved Systems and Methods for Determining Logical Values of Coupled Flash Memory Cells”, U.S. Provisional Application No. 60/960,943, filed Oct. 22, 2007 and entitled “Systems and methods to reduce errors in Solid State Disks and Large Flash Devices” and U.S. Provisional Application No. 61/071,469, filed Apr. 30, 2008 and entitled “Systems and Methods for Averaging Error Rates in Non-Volatile Devices and Storage Systems”, U.S. Provisional Application No. 60/996,027, filed Oct. 25, 2007 and entitled “Systems and Methods for Coping with Variable Bit Error Rates in Flash Devices”, U.S. Provisional Application No. 61/071,466, filed Apr. 30, 2008 and entitled “Systems and Methods for Multiple Coding Rates in Flash Devices”, U.S. Provisional Application No. 61/006,120, filed Dec. 19, 2007 and entitled “Systems and Methods for Coping with Multi Stage Decoding in Flash Devices”, U.S. Provisional Application No. 61/071,464, filed Apr. 30, 2008 and entitled “A Decoder Operative to Effect A Plurality of Decoding Stages Upon Flash Memory Data and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/006,385, filed Jan. 10, 2008 and entitled “A System for Error Correction Encoder and Decoder Using the Lee Metric and Adapted to Work on Multi-Level Physical Media”, US Provisional Application No. 61/064,995, filed Apr. 8, 2008 and entitled “Systems and Methods for Error Correction and Decoding on Multi-Level Physical Media”, U.S. Provisional Application No. 60/996,948, filed Dec. 12, 2007 and entitled “Low Power BCH/RS Decoding: a Low Power Chien-Search Implementation”, U.S. Provisional Application No. 61/071,487, filed May 1, 2008 and entitled “Chien-Search System Employing a Clock-Gating Scheme to Save Power for Error Correction Decoder and other Applications”, U.S. Provisional Application No. 61/071,468, filed Apr. 30, 2008 and entitled “A Low Power Chien-Search Based BCH/RS Recoding System for Flash Memory, Mobile Communications Devices and Other Applications”, U.S. Provisional Application No. 60/996,782, filed Dec. 5, 2007 and entitled “Systems and Methods for Using a Training Sequence in Flash Memory”, U.S. Provisional Application No. 61/064,853, filed Mar. 31, 2008 and entitled “Flash Memory Device with Physical Cell Value Deterioration Accommodation and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/129,608, filed Jul. 8, 2008 and entitled “A Method for Acquiring and Tracking Detection Thresholds in Flash Devices”, U.S. Provisional Application No. 61/006,806, filed Jan. 31, 2008 and entitled “Systems and Methods for using a Erasure Coding in Flash memory”, U.S. Provisional Application No. 61/071,486, filed May 1, 2008 and entitled “Systems and Methods for Handling Immediate Data Errors in Flash Memory”, U.S. Provisional Application No. 61/006,078, filed Dec. 18, 2007 and entitled “Systems and Methods for Multi Rate Coding in Multi Level Flash Devices”, U.S. Provisional Application No. 61/064,923, filed Apr. 30, 2008 and entitled “Apparatus For Coding At A Plurality Of Rates In Multi-Level Flash Memory Systems, And Methods Useful In Conjunction Therewith”, U.S. Provisional Application No. 61/006,805, filed Jan. 31, 2008 and entitled “A Method for Extending the Life of Flash Devices”, U.S. Provisional Application No. 61/071,465, filed Apr. 30, 2008 and entitled “Systems and Methods for Temporarily Retiring Memory Portions”, U.S. Provisional Application No. 61/136,234, filed Aug. 20, 2008 and entitled “A Method Of Reprogramming A Non-Volatile Memory Device Without Performing An Erase Operation”, U.S. Provisional Application No. 61/129,414, filed Jun. 25, 2008 and entitled “Improved Programming Speed in Flash Devices Using Adaptive Programming”, and several other co-pending patent applications being filed concurrently (same day).
The present invention relates generally to bit reduction and more particularly to rounding.
Two's complement arithmetic is known.
Clipping, according to Wikipedia, “is a form of distortion that limits a signal once it exceeds a threshold. Clipping may occur when a signal is recorded by a sensor that has constraints on the range of data it can measure, it can occur when a signal is digitized, or it can occur any other time an analog or digital signal is transformed. Clipping may be described as hard, in cases where the signal is strictly limited at the threshold, producing a flat cutoff; or it may be described as soft, in cases where the clipped signal continues to follow the original at a reduced gain. Hard clipping results in many high frequency harmonics; soft clipping results in fewer higher order harmonics and intermodulation distortion components.
“In digital signal processing, clipping occurs when the signal is restricted by the range of a chosen representation. For example in a system using 16-bit signed integers, 32767 is the largest positive value that can be represented, and if during processing the amplitude of the signal is doubled, sample values of 32000 should become 64000, but instead they are truncated to the maximum, 32767. Clipping is preferable to the alternative in digital systems—wrapping—which occurs if the digital hardware is allowed to “overflow”, ignoring the most significant bits of the magnitude, and sometimes even the sign of the sample value, resulting in gross distortion of the signal.
“The incidence of clipping may be greatly reduced by using floating point numbers instead of integers. However, floating point numbers are usually less efficient to use, sometimes result in a loss of precision, and they can still clip if a number is extremely large or small.
Rounding, according to Wikipedia, is “the process of reducing the number of significant digits in a number. The result of rounding is a “shorter” number having fewer non-zero digits yet similar in magnitude. The result is less precise but easier to use. For example: 73 rounded to the nearest ten is 70, because 73 is closer to 70 than to 80. Rounding can be analyzed as a form of quantization. There are many different rules that can be followed when rounding. Some of the more popular are described below.
“Common method: This method is commonly used in mathematical applications, for example in accounting. It is the one generally taught in elementary mathematics classes. This method is also known as Symmetric Arithmetic Rounding or Round-Half-Up (Symmetric Implementation): Decide which is the last digit to keep. Increase it by 1 if the next digit is 5 or more (this is called rounding up). Leave it the same if the next digit is 4 or less (this is called rounding down). Examples: 3.044 rounded to hundredths is 3.04 (because the next digit, 4, is less than 5). 3.045 rounded to hundredths is 3.05 (because the next digit, 5, is 5 or more). 3.0447 rounded to hundredths is 3.04 (because the next digit, 4, is less than 5). For negative numbers the absolute value is rounded. Examples: −2.1349 rounded to hundredths is −2.13. −2.1350 rounded to hundredths is −2.14.
“Round-to-even method: This method is also known as unbiased rounding, convergent rounding, statistician's rounding, Dutch rounding or bankers' rounding. It is identical to the common method of rounding except when the digit(s) following the rounding digit starts with a five and has no non-zero digits after it. The new algorithm is: Decide which is the last digit to keep. Increase it by 1 if the next digit is 6 or more, or a 5 followed by one or more non-zero digits. Leave it the same if the next digit is 4 or less. Otherwise, if all that follows the last digit is a 5 and possibly trailing zeroes; then change the last digit to the nearest even digit. That is, increase the rounded digit if it is currently odd; leave it if it is already even.
“With all rounding schemes there are two possible outcomes: increasing the rounding digit by one or leaving it alone. With traditional rounding, if the number has a value less than the half-way mark between the possible outcomes, it is rounded down; if the number has a value exactly half-way or greater than half-way between the possible outcomes, it is rounded up. The round-to-even method is the same except that numbers exactly half-way between the possible outcomes are sometimes rounded up—sometimes down.
“Although it is customary to round the number 4.5 up to 5, in fact 4.5 is no nearer to 5 than it is to 4 (it is 0.5 away from both). When dealing with large sets of scientific or statistical data, where trends are important, traditional rounding on average biases the data upwards slightly. Over a large set of data, or when many subsequent rounding operations are performed as in digital signal processing, the round-to-even rule tends to reduce the total rounding error, with (on average) an equal portion of numbers rounding up as rounding down. This generally reduces the upwards skewing of the result.
“Round-to-even is used rather than round-to-odd as the latter rule would prevent rounding to a result of zero. Examples: 3.016 rounded to hundredths is 3.02 (because the next digit (6) is 6 or more). 3.013 rounded to hundredths is 3.01 (because the next digit (3) is 4 or less). 3.015 rounded to hundredths is 3.02 (because the next digit is 5, and the hundredths digit (1) is odd). 3.045 rounded to hundredths is 3.04 (because the next digit is 5, and the hundredths digit (4) is even). 3.04501 rounded to hundredths is 3.05 (because the next digit is 5, but it is followed by non-zero digits) . . . .
“Other methods of rounding exist, but use is mostly restricted to computers and calculators, statistics and science. In computers and calculators, these methods are used for one of two reasons: speed of computation or usefulness in certain computer algorithms. In statistics and science, the primary use of alternate rounding schemes is to reduce bias, rounding error and drift—these are similar to round-to-even rounding. They make a statistical or scientific calculation more accurate.
“Other methods of rounding include “round towards zero” (also known as truncation) and “round away from zero”. These introduce more round-off error and therefore are rarely used in statistics and science; they are still used in computer algorithms because they are slightly easier and faster to compute. Two specialized methods used in mathematics and computer science are the floor (always round down to the nearest integer) and ceiling (always round up to the nearest integer).
“Stochastic rounding is a method that rounds to the nearest integer, but when the two integers are equidistant (e.g., 3.5), then it is rounded up with probability 0.5 and down with probability 0.5. This reduces any drift, but adds randomness to the process. Thus, if you perform a calculation with stochastic rounding twice, you may not end up with the same answer. The motivation is similar to statistician's rounding . . . .
Described herein is an unbiased rounding “away from zero” system comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M−N bit number, and apparatus for adding the equivalent value of ½’ to the M−N bit number unless the input number is negative and the N truncated bits represent exactly ½, all constructed and operative in accordance with certain embodiments of the present invention.
Also described herein is an unbiased rounding “toward zero” system comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M−N bit number, and apparatus for adding the equivalent value of ½’ to the M−N bit number unless the input number is positive and the N truncated bits represent exactly ½, all constructed and operative in accordance with certain embodiments of the present invention.
a. The gate count of the apparatus which may be employed to implement certain embodiments of the invention is less than the gate count of conventional apparatus described herein for rounding two's complement represented signed numbers toward or away from zero, thereby to provide compact, low power apparatus.
b. The apparatus which may be employed to implement certain embodiments of the invention allows clipping to follow rounding as is demanded in many applications, using any other apparatus.
There is thus provided, in accordance with at least one embodiment of the present invention, a method for rounding two's complement represented signed numbers away from zero, the method comprising providing an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number, truncating N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; if the M-bit two's complement represented signed number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, outputting the (M−N) bit truncated number; and otherwise, computing and outputting a sum of the most significant of the sequence of truncated bits and the (M−N) bit truncated number.
Also provided, in accordance with at least one embodiment of the present invention, is a method for rounding two's complement represented signed numbers toward zero, the method comprising providing an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number, truncating N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits, if the M-bit two's complement represented signed number is positive and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, outputting the (M−N) bit truncated number; and otherwise, computing and outputting a sum of the most significant of the sequence of truncated bits and the (M−N) bit truncated number.
Further in accordance with at least one embodiment of the present invention, the method also comprises providing special treatment for a largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’, to prevent the largest positive number from wrapping around zero and rounding to a lowest negative number.
Additionally provided, in accordance with at least one embodiment of the present invention, is a system for rounding two's complement represented signed numbers away from zero, the system comprising a receiver operative to receive an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number, a truncator operative to truncate N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; and a selector operative, if the M-bit two's complement represented signed number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, to output the (M−N) bit truncated number; and otherwise, to compute and to output a sum of the most significant of the sequence of truncated bits and the (M−N) bit truncated number.
Further provided, in accordance with at least one embodiment of the present invention, is a system for rounding two's complement represented signed numbers toward zero, the system comprising a receiver operative to receive an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; a truncator operative to truncate N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; and a selector operative, if the M-bit two's complement represented signed number is positive and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, to output the (M−N) bit truncated number; and otherwise, to compute and to output a sum of the most significant of the sequence of truncated bits and the (M−N) bit truncated number.
Still further provided, in accordance with at least one embodiment of the present invention, is a 2's complement arithmetic based hardware device including a system for rounding as described above.
Additionally provided, in accordance with at least one embodiment of the present invention, is a digital signal processing system including a 2's complement arithmetic based hardware device as described above.
Further in accordance with at least one embodiment of the present invention, the system also comprises a clipper providing special treatment for a largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’, to prevent the largest positive number from wrapping around zero and rounding toward a lowest negative number.
Any suitable processor, display and input means may be used to process, display, store and accept information, including computer programs, in accordance with some or all of the teachings of the present invention, such as but not limited to a conventional personal computer processor, workstation or other programmable device or computer or electronic computing device, either general-purpose or specifically constructed, for processing; a display screen and/or printer and/or speaker for displaying; machine-readable memory such as optical disks, CDROMs, magnetic-optical discs or other discs; RAMs, ROMs, EPROMs, EEPROMs, magnetic or optical or other cards, for storing, and keyboard or mouse for accepting. The term “process” as used above is intended to include any type of computation or manipulation or transformation of data represented as physical, e.g. electronic, phenomena which may occur or reside e.g. within registers and/or memories of a computer.
The apparatus of the present invention may include, according to certain embodiments of the invention, machine readable memory containing or otherwise storing a program of instructions which, when executed by the machine, implements some or all of the apparatus, methods, features and functionalities of the invention shown and described herein. Alternatively or in addition, the apparatus of the present invention may include, according to certain embodiments of the invention, a program as above which may be written in any conventional programming language, and optionally a machine for executing the program such as but not limited to a general purpose computer which may optionally be configured or activated in accordance with the teachings of the present invention.
A description of embodiments referred to above, and other embodiments, will follow.
Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions, utilizing terms such as, “processing”, “computing”, “estimating”, “selecting”, “ranking”, “grading”, “calculating”, “determining”, “generating”, “reassessing”, “classifying”, “generating”, “producing”, “stereo-matching”, “registering”, “detecting”, “associating”, “superimposing”, “obtaining” or the like, refer to the action and/or processes of a computer or computing system, or processor or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories, into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices.
FIG. 9 is a logical diagram of circuitry for rounding toward zero, constructed and operative in accordance with certain embodiments of the present invention and providing efficient unbiased signed rounding with wrap around.
In fixed-point arithmetic it is often desired to reduce the number of bits which represent a number. In order to prevent bias and minimize rounding error, caused by the bits' number reduction, a rounding operation may be performed. Other common bit reduction methods are floor, ceiling and fix (rounding towards zero). The table of FIG. 1 presents some numerical examples of rounding away from and toward zero as opposed to floor and ceiling operations.
Representation of quantities as signed numbers in 2's complement representation, as illustrated in FIG. 2, is known. The smallest number that can be represented by M bits is −2M−1 and the largest number is 2M−1−1.
The rounding operation is defined as setting to the nearest integer. When the input lies exactly in the middle between two integers, the rounding is away from zero, for both positive and negative numbers.
In hardware, conventionally, rounding of N bits off an M bit positive number is performed by adding the equivalent value of ½’ and then truncating N bits from the results. For truncation of N bits, the equivalent value of ½’ is ‘1’ followed by N−1 zeroes. Rounding N bits off an M bit negative number is performed by computing the absolute value, rounding it, and then computing back the negative number from the rounding result.
These conventional rounding operations require the following hardware: An M bit adder for the addition of the equivalent value of ½’; M inverters, M 2→1 multiplexers, an M bit adder and a 1 bit comparator for the absolute value computation of the input; and M−N inverters, M−N 2→1 multiplexers, and an M−N bit adder for deriving the output with correct sign.
Step 310: Truncate N bits from an original M bit input number thereby to provide M−N bits.
Step 320: Determine whether the input number is negative (the MSB bit is ‘1’) and the N truncated bits represent exactly ½ (i.e. ‘1’ followed by N−1 replicas of 0’). If so, terminate, to keep the rounding operation unbiased.
Step 330: Otherwise, add the equivalent value of ½’ to the M−N bits to implement the rounding.
An example hardware implementation of the method of FIG. 3 is shown in FIG. 5. It is appreciated that the table of FIG. 4 is a Truth table for the input to the adder in FIG. 5. The hardware included in the apparatus of FIG. 5 includes an (N−1)-input NOR gate, a 2-input NAND gate, a 2-input AND gate, and an (M−N) bit adder.
Both in conventional rounding and in the rounding apparatus of FIG. 5, the largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’ may be regarded as an exception. For this number, rounding of N bits results with ‘1’, followed by M−N−1 replicas of ‘0’. However, this number is the lowest negative number. Thus, absent special treatment, rounding the highest positive number may result in the lowest negative number due to a process of wrapping around the zero. This exception may be identified and handled e.g. as shown in FIG. 6. The apparatus of FIG. 6 is similar to the apparatus of FIG. 5, however, clipping apparatus, which may be conventional, is added.
A method for rounding “toward zero”, provided according to certain embodiments of the present invention, is now described with reference to FIG. 7. Rounding “toward zero” is typically defined as setting to the nearest integer, and when the input lies exactly in the middle between two integers, the rounding is toward zero, for both positive and negative numbers.
Step 710: Truncate N bits from an original M-bit input number thereby to provide M−N bits.
Step 720: Determine whether the input number is positive (the MSB bit is ‘1’) and the N truncated bits represent exactly ½ (i.e. ‘1’ followed by N−1 replicas of ‘0’). If so, terminate, to keep the rounding operation unbiased.
Step 730: Otherwise, add the equivalent value of ½’ to the M−N bits to implement the rounding.
The decision when to add the equivalent value of ½’ is summarized in the table of FIG. 8.
An example hardware implementation of the method of FIG. 7 is shown in FIG. 9. It is appreciated that the table of FIG. 8 is a Truth table for the input to the adder in FIG. 9. The hardware included in the apparatus of FIG. 9 includes an (N−1) input NOR gate, a 2 input NAND gate, a 2-input AND gate, and an (M−N) bit adder.
Both in conventional rounding and in the rounding toward apparatus of FIG. 9, the largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’ may be regarded as an exception. For this number, rounding of N bits results with ‘1’, followed by M−N−1 replicas of ‘0’. However, this number is the lowest negative number. Thus, absent special treatment, rounding the highest positive number may result in the lowest negative number due to a process of wrapping around the zero. This exception, for rounding toward, may be identified and handled by adding conventional clipping apparatus, analogously to the apparatus described above with reference to FIG. 6, for rounding away.
Comparing the rounding away and rounding toward embodiments described herein, it is typically the case that when it is desired to round a signed number “away from” zero, the ‘N−1’th bit is added, except if the number is negative (MSB=1) and the [N−1:0] bits are “100 . . . 000” (equivalent ½). In contrast, when it is desired to round a signed number “toward” zero, the ‘N−1’th bit is added except if the number is positive (MSB=0) and the [N−1:0] bits are “100 . . . 000” (equivalent ½). There are many applications of the techniques and apparatus shown and described herein in a wide variety of hardware devices that perform computations in 2's complement representation and have occasion to perform rounding, such as but not limited to DSP (Digital Signal Processing) applications e.g. in communication devices (both wired and wireless communication devices), networking, coding, processors, storage devices, or digital TV set—top boxes. It is appreciated that typically, the lower the gate count for implementing rounding operations, the higher the resulting efficiency of the apparatus.
It is appreciated that the particular hardware implementations shown and described herein are not intended to be limiting and any De-Morgan or other logical equivalent of the apparatus specifically shown and described herein is also within the scope of the present invention.
It is appreciated that software components of the present invention including programs and data may, if desired, be implemented in ROM (read only memory) form including CD-ROMs, EPROMs and EEPROMs, or may be stored in any other suitable computer-readable medium such as but not limited to disks of various kinds, cards of various kinds and RAMs. Components described herein as software may, alternatively, be implemented wholly or partly in hardware, if desired, using conventional techniques.
Included in the scope of the present invention, inter alia, are electromagnetic signals carrying computer-readable instructions for performing any or all of the steps of any of the methods shown and described herein, in any suitable order; machine-readable instructions for performing any or all of the steps of any of the methods shown and described herein, in any suitable order; program storage devices readable by machine, tangibly embodying a program of instructions executable by the machine to perform any or all of the steps of any of the methods shown and described herein, in any suitable order; a computer program product comprising a computer useable medium having computer readable program code having embodied therein, and/or including computer readable program code for performing, any or all of the steps of any of the methods shown and described herein, in any suitable order; any technical effects brought about by any or all of the steps of any of the methods shown and described herein, when performed in any suitable order; any suitable apparatus or device or combination of such, programmed to perform, alone or in combination, any or all of the steps of any of the methods shown and described herein, in any suitable order; information storage devices or physical records, such as disks or hard drives, causing a computer or other device to be configured so as to carry out any or all of the steps of any of the methods shown and described herein, in any suitable order; a program pre-stored e.g. in memory or on an information network such as the Internet, before or after being downloaded, which embodies any or all of the steps of any of the methods shown and described herein, in any suitable order, and the method of uploading or downloading such, and a system including server/s and/or client's for using such; and hardware which performs any or all of the steps of any of the methods shown and described herein, in any suitable order, either alone or in conjunction with software.
Certain operations are described herein as occurring in the microcontroller internal to a flash memory device. Such description is intended to include operations which may be performed by hardware which may be associated with the microcontroller such as peripheral hardware on a chip on which the microcontroller may reside. It is also appreciated that some or all of these operations, in any embodiment, may alternatively be performed by the external, host-flash memory device interface controller including operations which may be performed by hardware which may be associated with the interface controller such as peripheral hardware on a chip on which the interface controller may reside. Finally it is appreciated that the internal and external controllers may each physically reside on a single hardware device, or alternatively on several operatively associated hardware devices.
Any data described as being stored at a specific location in memory may alternatively be stored elsewhere, in conjunction with an indication of the location in memory with which the data is associated. For example, instead of storing page- or erase-sector-specific information within a specific page or erase sector, the same may be stored within the flash memory device's internal microcontroller or within a microcontroller interfacing between the flash memory device and the host, and an indication may be stored of the specific page or erase sector associated with the cells.
It is appreciated that the teachings of the present invention can, for example, be implemented by suitably modifying, or interfacing externally with, flash controlling apparatus. The flash controlling apparatus controls a flash memory array and may comprise either a controller external to the flash array or a microcontroller on-board the flash array or otherwise incorporated therewithin. Examples of flash memory arrays include Samsung's K9XXG08UXM series, Hynix's HY27UK08BGFM Series, Micron's MT29F64G08TAAWP or other arrays such as but not limited to NOR or phase change memory. Examples of controllers which are external to the flash array they control include STMicroelectrocincs's ST7265× microcontroller family, STMicroelectrocincs's ST72681 microcontroller, and SMSC's USB97C242, Traspan Technologies' TS-4811, Chipsbank CBM2090/CBM1190. Example of commercial IP software for Flash file systems are: Denali's Spectra™ NAND Flash File System, Aarsan's NAND Flash Controller IP Core and Arasan's NAND Flash File System. It is appreciated that the flash controller apparatus need not be NAND-type and can alternatively, for example, be NOR-type or phase change memory-type.
Flash controlling apparatus, whether external or internal to the controlled flash array, typically includes the following components: a Memory Management/File system, a NAND interface (or other flash memory array interface), a Host Interface (USB, SD or other), error correction circuitry (ECC) typically comprising an Encoder and matching decoder, and a control system managing all of the above.
The present invention may for example interface with or modify, as per any of the embodiments described herein, one, some or all of the above components and particularly with the ECC component.
Features of the present invention which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, features of the invention, including method steps, which are described for brevity in the context of a single embodiment or in a certain order may be provided separately or in any suitable subcombination or in a different order. “e.g.” is used herein in the sense of a specific example which is not intended to be limiting.
1. A method for rounding two's complement represented signed numbers away from zero, the method comprising: providing an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; truncating N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; if the M-bit two's complement represented signed number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, outputting the (M−N) bit truncated number; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical operation on the most significant bit of the sequence of truncated bits and (b) the (M−N) bit truncated number; rounding two's complement represented signed numbers away from zero by a circuit that essentially consists of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate, an inverter; wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate; wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.
2. The method according to claim 1 and also comprising providing special treatment for a largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’, to prevent said largest positive number from wrapping around zero and rounding toward a lowest negative number.
3. The method according to claim 2 comprising checking if the M-bit two's compliment represented signed number is the largest positive number by the (M−N) input NAND gate.
4. A method for rounding two's complement represented signed numbers toward zero, the method comprising: providing an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; truncating N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; if the M-bit two's complement represented signed number is positive and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, outputting the (M−N) bit truncated number; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical function on the most significant bit of said sequence of truncated bits and (b) the (M−N) bit truncated number; rounding two's complement represented signed numbers towards zero by a circuit that essentially consists of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate, an inverter; wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate; wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.
5. A method according to claim 4 and also comprising providing special treatment for a largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’, to prevent said largest positive number from wrapping around zero and rounding toward a lowest negative number.
6. A system for rounding two's complement represented signed numbers away from zero, the system comprising: a receiver operative to receive an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; a truncator operative to truncate N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; a clipped and a selector operative, if the M-bit two's complement represented signed number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, to output said (M−N) bit truncated number; and otherwise, to compute and to output a sum of (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical function on the most significant bit of said sequence of truncated bits and (b) the (M−N) bit truncated number; wherein the clipper and the selector essentially consist of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate, an inverter; wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate; wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.
7. The system according to claim 6 wherein selector is arranged to check if the M-bit two's compliment represented signed number is a largest positive number by a (M−N) input NAND gate arranged to receive an inverted most significant bit of the M-bit two's compliment represented signed number and to receive non-inverted second till (M−N−1)'th significant bits of the M-bit two's compliment represented signed number.
8. A system according to claim 6 wherein the clipper is arranged to providing special treatment for a largest positive number, represented by a ‘0’, followed by M−1replicas of ‘1’, to prevent said largest positive number from wrapping around zero and rounding toward a lowest negative number.
9. A system for rounding two's complement represented signed numbers toward zero, the system comprising: a receiver operative to receive an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; a truncator operative to truncate N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; a clipper and a selector operative, if the M-bit two's complement represented signed number is positive and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, to output said (M−N) bit truncated number; and otherwise, to compute and to output a (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical function on the most significant bit of said sequence of truncated bits and (b) the (M−N) bit truncated number; wherein the clipper and the selector essentially consist of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate an inverter wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate; wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.
10. A system according to claim 9 wherein the clipper provides special treatment for a largest positive number, represented by a ‘0’, followed by M−1 replicas of ‘1’, to prevent said largest positive number from wrapping around zero and rounding toward a lowest negative number.
11. A 2's complement arithmetic based hardware device including a system for rounding, wherein the system for rounding comprises a receiver operative to receive an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; a truncator operative to truncate N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; a clipped and a selector operative, if the M-bit two's complement represented signed number is negative and the sequence of N truncated bits comprises a most significant bit of 1 followed by zeros, to output said (M−N) bit truncated number; and otherwise, to compute and to output a sum of (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical function on the most significant bit of said sequence of truncated bits and (b) the (M−N) bit truncated number; wherein the clipper and the selector essentially consist of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate, an inverter; wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.
12. A 2's complement arithmetic based hardware device including a system for rounding that comprises a receiver operative to receive an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; a truncator operative to truncate N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; a clipper and a selector operative, if the M-bit two's complement represented signed number is positive and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros, to output said (M−N) bit truncated number; and otherwise, to compute and to output a (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical function on the most significant bit of said sequence of truncated bits and (b) the (M−N) bit truncated number; wherein the clipper and the selector essentially consist of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate, an inverter; wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate: wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.
13. A digital signal processing system including a 2's complement arithmetic based hardware device according to claim 11.
14. A digital signal processing system including a 2's complement arithmetic based hardware device according to claim 12.
International Search Report for International Application No. PCT/IL08/01240 mailed Mar. 23, 2009.

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