Source: https://pubs.rsc.org/en/content/articlehtml/2015/nr/c5nr01052g?page=search
Timestamp: 2019-04-26 11:43:29+00:00

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Just when the interest of the transistor community in graphene began to subside,4,5 a paper on the fabrication of single-layer MoS2 FETs6 gave new momentum to the research on 2D materials. Over a surprisingly short period of time, entire classes of new 2D materials have been discovered. A steadily increasing number of groups worldwide are now working intensively on 2D FETs, chipmakers pay attention to the progress in the field, and since 2011 the ITRS (International Technology Roadmap for Semiconductors), the strategic planning document of the semiconductor industry, has mentioned 2D materials beyond graphene as candidates for future electronics.7 Nevertheless, the prospects of the 2D materials in electronics are controversially debated. While part of the community is very optimistic, another fraction believes that 2D transistors are of academic interest only and are useful for niche applications at best.
The present paper focuses on the properties and physics of 2D materials and 2D FETs and is organized as follows. Section 2 reviews important trends in semiconductor electronics and introduces the figures of merit we later use to assess the performance of transistors. Section 3 presents an overview of the different classes of 2D materials. In section 4 we compose a wish list of properties desirable for FET channel materials and examine to what extent the 2D materials meet the requirements of our list. To keep the discussion manageable, neither the entries of the wish list nor the set of transistor figures of merit are intended to be exhaustive. Instead, we limit the discussion to a selected set of material parameters as entries for the wish list and a few key transistor figures of merit. Section 5 provides a discussion of the current status, prospects, and problems of 2D transistors, and finally section 6 concludes the paper.
The overall semiconductor chip market has an annual volume of about $300 billion and can, as shown in Fig. 1, broadly be divided into the two main domains More Moore and More Than Moore.
It is important to recognize that, to follow Moore's Law, increasing circuit complexity by scaling alone is not sufficient. Instead, the electrical performance of the scaled MOSFETs must be improved as well. In particular, transistor switching speed should increase exponentially and the energy needed for a single switching event should decrease exponentially. Only if these “triple dividends of MOSFET scaling”15 – smaller, faster, more power-efficient – can be achieved in concert, Moore's Law will survive.
More Than Moore is not primarily focused on increasing circuit complexity but rather on enhancing the functionality of ICs and electronic systems by combining digital electronics with components such as analog/RF (radio frequency) and high-voltage circuitry, sensors, actuators, etc. In the More Than Moore domain, traditionally the material basis has been much broader compared to More Moore and, apart from Si, a variety of alternative semiconductors is used to complement Si.
More Than Moore covers a wide and heterogeneous field, see Fig. 1. Here we focus solely on RF electronics where at present, in addition to Si, the compound semiconductors based on GaAs, InP, and GaN are very popular. It should be noted that in RF electronics only n-channel FETs are used since in most materials electrons are faster than holes. A major trend in RF electronics is the striving for higher transistor operating frequencies and for extending transistor operation into the THz range. The evolution of the frequency performance of RF FETs in terms of the characteristic frequencies fT (cutoff frequency) and fmax (maximum frequency of oscillation) is shown in Fig. 3.
Fig. 3 Evolution of the cutoff frequency fT and maximum frequency of oscillation fmax of RF FETs. Shown are the record fT and fmax values reported at a certain time. MESFET: metal-semiconductor FET; HEMT: high electron mobility transistor; pHEMT: pseudomorphic HEMT; mHEMT: metamorphic HEMT. Data are taken from ref. 20–39.
As can be seen, the current record fmax of RF FETs is slightly above 1 THz, which means that FETs capable of THz amplification with reasonable power gain are still missing. On the other hand, the frequency range around and above 1 THz is attractive for applications in a variety of fields, such as security, medicine, and ultra-high-speed communications, to name just a few.40,41 Therefore, RF device engineers are looking for alternative FET channel materials offering improved mobility and closely follow the research on 2D materials.
A FET consists of a channel region connecting two reservoirs of mobile charges called source and drain. The third electrode (gate) is separated from the channel by a thin barrier. The applied gate–source voltage VGS controls the conductivity of the channel and the applied drain–source voltage VDS drives a drain current ID through the transistor. Fig. 4 shows a generic FET, together with the structures of Si MOSFETs, III–V HEMTs, and 2D MOSFETs. FETs are devices with the ability (i) to switch and (ii) to amplify signals and provide gain. For digital electronics, i.e., More Moore, switching is relevant while amplifying signals is important for RF applications.
In digital logic, the FET is supposed to switch between on and off. In the on-state, see Fig. 4(a), the channel has a low resistance and a large on-current Ion can flow through it. As per definition, Ion is the transistor current for the bias condition VGS = VDS = VDD. In the off-state, see Fig. 4(b), on the other hand, the FET should block the current, the channel resistance should be high, and only a very small off-current Ioff is allowed to flow. The off-current is defined as the current flowing under the condition VGS = 0 and VDS = VDD. The gate voltage at which the transistor is just at the verge of switching on is the threshold voltage VTh. The transfer characteristics of a MOSFET shown in Fig. 5 indicate that in the subthreshold region (VGS < VTh) the drain current depends exponentially on VGS, followed by a transition region around VTh and finally by the superthreshold region where the drain current is essentially linearly dependent on VGS. As we have shown in Fig. 2, the supply voltage VDD of logic circuits has been decreased continuously over the years and a further reduction is required for the future. This means that logic transistors must switch from off to on within a very limited range of VGS.
Fig. 5 Transfer characteristics of an n-channel FET showing the drain current ID as a function of the gate-source voltage VGS together with the on and off operating points for CMOS logic. Note that the scale of the left current axis is logarithmic and that of the right current axis is linear.
A further FOM (figure of merit) related to switching is the on–off ratio Ion/Ioff. For FETs to be used in digital logic, on–off ratios in the range of ≈104–5 × 107 are required.7 As a basic rule, Ioff should be as low as possible and both Ion and the on–off ratio should be as high as possible. A low Ioff is needed for a low static power consumption of logic circuits while a high Ion is relevant for a high transistor switching speed.
When operated as an amplifier, on the other hand, the FET does not necessarily need to switch off. Instead, in most RF amplifier configurations the FET is permanently operated in the on-state and small signals applied to its input, i.e., the gate, appear amplified at the output. The extent to which the input signal is amplified is called gain. The small-signal current gain, for example, is defined as the RF output current of the transistor divided by the RF input current. Gains are frequency dependent and decrease with increasing frequency. Two important FOMs of RF transistors are the characteristic frequencies fT and fmax. The cutoff frequency fT is the frequency at which the small-signal current gain h21 of the transistor has dropped to unity (i.e., 0 dB) and the maximum frequency of oscillation fmax is the frequency where the unilateral power gain U becomes unity. It should be noted that for most RF applications, power gain and fmax are more important than current gain and fT. Moreover, as a rule of thumb, the operating frequency should be lower than 20% of the used transistors’ fmax to guarantee sufficient power gain. Fig. 6 shows the small-signal current and power gains of an RF FET as a function of frequency, together with fT and fmax.
Fig. 6 Small-signal current gain h21 and unilateral power gain U of a RF FET as a function of frequency, after ref. 43 and 44. The characteristic frequencies fT and fmax are obtained by extrapolating the measured h21 and U with the characteristic slope of −20 dB per dec.
where gm is the transconductance (i.e., the slope of the transfer characteristics, see Fig. 5, at the dc operating point) and gd is the drain conductance (i.e., the slope of the ID–VDS output characteristics). A transistor with low intrinsic gain, e.g., caused by a large drain conductance, will always suffer from a low power gain.
where PSi and PSo are the signal powers at the input and output, and PNi and PNo are the noise powers at the input and output, respectively. Under optimum matching and bias conditions, the noise figure reaches a minimum called minimum noise figure NFmin. It is the relevant FOM to characterize the noise performance of RF transistors. For a good RF FET the characteristic frequencies fT and fmax should be high and the minimum noise figure NFmin should be low.
Inspired by the successful preparation of graphene, researchers have intensively examined options to obtain stable 2D materials beyond graphene. These efforts include real-world experiments where 2D materials have been prepared and analyzed, as well as computational experiments where the thermodynamic stability and the band structure of existing and hypothetical 2D materials have been computed. For the latter, particularly the Atlas of 2D Materials reporting the properties of more than 140 different 2D materials45 is worth mentioning.
Recent experimental and theoretical efforts have shown that a variety of 2D materials beyond graphene does or should exist and that their electronic properties span the full range from metallic to insulating. Of particular interest for FET channels are the semiconducting and, to a lesser extent, the gapless semi-metallic 2D materials. Fig. 7 shows schematically the relevant parts of the band structure of different classes of these 2D materials.
Fig. 7 Schematic band structure of 2D materials relevant for transistors. BLG: bilayer graphene; GNR: graphene nanoribbon; TMD: transition metal dichalcogenide; SMC: semimetal chalcogenide.
Compared to graphene, much less is known on the other X-enes. As of the end of 2014, the Web of Science database listed almost 91 000 entries under the search term graphene compared to 654 entries for silicene, 133 for germanene, 81 for phosphorene, and 8 for stanene.50 As shown in Fig. 7, graphene, silicene, germanene, and stanene are gapless and have cone-shaped conduction and valence bands. The cones are frequently called Dirac cones and, correspondingly, graphene, silicene, germanene, and stanene are designated as Dirac materials. Phosphorene, on the other hand, is a semiconductor with a sizeable gap.
The crystallographic structure of the X-anes is closely related to that of the X-enes. They also possess a hexagonal lattice of carbon (graphane), silicon (silicane), germanium (germanane), or tin (stanane) atoms. However, their lattice atoms are additionally out of plane bonded to hydrogen atoms – this is frequently called hydrogenated. Graphane was predicted to exist in 200751 and was produced experimentally shortly afterwards.52 Recently, germanane could also be realized experimentally.53 Most relevant for electronic applications is the fact that graphane, silicane, and germanane possess sizeable bandgaps.
By first-principles calculations, the phonon properties and band structures of entire classes of 2D IV–IV and III–V compounds and of many other 2D materials have been investigated. It has been shown that a large body of these 2D materials with both hexagonal and tetragonal lattice structures should be stable and show bandgaps between 0.2 and 5 eV.45,63,64 Although it is uncertain whether all these 2D materials can be synthesized, at least part of them may become available for experiments in the future.
To fabricate 2D transistors, first the 2D starting material must be produced, preferably in the form of large-area sheets with uniform thickness and high crystallographic quality. Layered van der Waals materials, where the stacked layers are bound by weak van der Waals forces, can be exfoliated. Mechanical exfoliation is widely used to produce graphene,1 TMDs,6 and phosphorene48 layers. While this approach is simple and does not require expensive equipment, it is time consuming and provides flakes of limited size only. Liquid exfoliation as a second exfoliation method delivers 2D flakes dispersed in a liquid.65 This method is very effective, but the dispersed flakes are small, which makes transistor and circuit processing challenging.
To assess the potential of novel materials for FET channels it is not sufficient to consider only one single material property such as the carrier mobility. Instead, a set of properties should be examined to get a realistic impression on the suitability of the new material for transistors. Therefore, in the following we compose a (certainly not complete) wish list for the material properties of a FET channel, particularly for use in digital logic and RF FETs, and examine the extent to which the 2D materials meet our wishes. In the discussion it should always be kept in mind that research on most of the 2D materials has just begun and is in an embryonic stage compared to the conventional 3D bulk semiconductors such as Si, Ge, and the III–V compounds. This leads to the situation that, while our wish list itself is well established and relies on the experiences of decades of transistor research, the available data for the relevant properties of the 2D materials are rather fragmentary.
Since RF FETs can permanently be operated in the on-state and do not need to switch off, one might conclude that here a gap is not needed. Unfortunately, the situation is more complex. It has been discussed in detail that to achieve a high power gain and high fmax, the FET needs to show a sufficiently good saturation of the drain current and for that, in turn, a gap is needed.3 Current gain and fT, on the other hand, are less affected by a missing or weak current saturation. Thus, transistors with gapless channels can provide high current gain and fT but suffer from poor power gain and fmax. It is not exactly known how wide the gap of the channel of a good RF FET should be. Most likely, the requirements are less stringent than for logic FETs. The fastest and least noisy RF FETs are InP HEMTs32 and GaAs mHEMTs75,76 having InxGa1−xAs channels with high In contents x ranging from 0.7 (EG ≈ 0.65 eV) to 1 (i.e., InAs, EG = 0.35 eV). Experiments with InSb channel HEMTs (EG InSb = 0.17 eV), on the other hand, revealed that these transistors, despite being fast, show lower fT and fmax compared to InP HEMTs and GaAs mHEMTs with a similar gate length.77,78 This suggests that the 0.17 eV gap of InSb might already be too narrow for ultra-high-performance RF FETs.
4.1.2 Entry #2: carrier transport and effective mass. Logic and RF FETs should be fast, i.e., they should react quickly on variations of their input signals, and show a large on-state current. For this, fast carriers are needed. Measures for the speed of carrier transport are the mobility μ, the peak velocity vpeak, and the saturation velocity vsat. When a low electric field E acts on a carrier, its drift velocity v is given by v = μ × E. The mobility is inversely proportional to the carrier effective mass meff and a light meff is a precondition for a high μ. Under high-field conditions, the carrier velocity no longer follows the field linearly. The high-field velocity for holes shows a soft saturation and approaches vsat at high fields. For electrons, the situation is more diverse. In some semiconductors (e.g., GaAs), the electron velocity shows a pronounced peak (vpeak) at a certain field, then decreases at higher fields, and eventually approaches the saturation velocity. In other semiconductors, e.g., Si, soft saturation without a velocity peak occurs. Fig. 8 shows exemplarily the v–E (velocity–electric field) characteristics for electrons and holes in Si and GaAs. The channel material of a fast FET should show a high mobility (and thus a light meff), preferably combined with a high vpeak and/or vsat.
Fig. 8 Velocity-field characteristics for electrons and holes in Si and GaAs. Note the peak of the electron velocity in GaAs and the soft saturation of the other v–E characteristics.
For logic FETs, a high mobility and a high saturation velocity are always desirable. It should be mentioned, however, that Si MOSFETs show surprisingly good switching characteristics in spite of the rather moderate μ (200–500 cm2 V−1 s−1) and vsat (107 cm s−1). The InxGa1−xAs channels of the best RF FETs, i.e., InP HEMTs and GaAs mHEMTs, show mobilities of 10 000–15 000 cm2 V−1 s−1 and peak velocities of 3–4 × 107 cm s−1, and alternative channel materials that are to compete with InxGa1−xAs for high-performance RF FETs should show at least similar transport characteristics, combined with an appropriate bandgap. Reasonably good RF performance, however, can be achieved already with lower mobility channels, e.g., Si channels of RF Si MOSFETs, provided the contact resistance (see entry #4) is low and the scale length (entry #5) is short.
4.1.3 Entry #3: heat transport. If a voltage is applied to a FET and a current is flowing through its channel, electrical energy is converted into heat and this heat must be removed to avoid unacceptable self-heating. To accomplish an effective heat removal, the channel material should show a high thermal conductivity κ.
The thermal conductivity of the channel material, however, does not tell the whole story of heat transport, in particular if the transistor is located on a substrate different from the channel material. 2D FETs, such as graphene or TMD FETs (see Fig. 4e showing a MoS2 MOSFET), are frequently realized on the surface of oxidized Si wafers. Here, the heat generated in the channel first has to cross the channel–SiO2 interface acting as a thermal boundary resistance RTB, move through the SiO2 layer, and then cross the SiO2–substrate interface forming a second RTB before it can spread across the Si substrate.79 To limit self-heating, the thermal conductivity of the FET channel material and of all materials underneath should be high and the thermal boundary resistances of all interfaces between the channel and the back side of the chip should be low.
4.1.4 Entry #4: contact resistance. In a FET, the gate–source voltage controls the channel conductivity and thus the drain current ID. A closer inspection shows that not the gate–source voltage applied between the gate and source terminals, but rather the intrinsic gate–source voltage VGS-int, i.e., the potential difference between the gate and the source-sided end of the channel, is controlling the current. Carriers coming from the source terminal first cross the metal–semiconductor interface which hinders the carrier flow and acts as a resistance called source contact resistance Rco-S. Next, the carriers flow through an ungated semiconductor region until they reach the channel underneath the gate. This ungated region represents the source series resistance Rser-S. The overall parasitic resistance at the source side, RS, is the sum Rco-S + Rser-S. The same situation occurs at the drain side of the FET leading to the parasitic drain resistance RD.
The parasitic source and drain resistances RS and RD, and thus the contact resistance Rco, deteriorate transistor performance. Therefore, the Rco should be as low as possible.
The contact resistance is proportional to the inverse of the contact width, i.e., Rco ∝ 1/W. To compare the contact resistances obtained from structures with different contact widths, Rco is commonly normalized with respect to the contact width and is given in units of Ω mm.
where a is a constant, short-channel effects, most notably the undesirable degradation of the subthreshold behavior and the increase of the off-current, are sufficiently suppressed. Therefore, a short scale length and thus a combination of a thin channel region and a thin barrier are always desirable.
where veff is the effective carrier velocity in the channel, which is related to μ, vpeak, and vsat. While a light meff is beneficial for a high veff, the opposite is the case for ΔQch/ΔVGS. Thus, a light meff is preferable only as long as its positive effect on veff overcompensates its deteriorating influence on ΔQch/ΔVGS.
Table 1 summarizes our discussion on the wish list for the properties of FET channel materials.
Good carrier transport properties, most notably a high mobility, are important for a high on-current and a high fT, while bandgap and scale length are most relevant for the off-current and, to a certain extent, for drain current saturation and fmax.
Large-area graphene is gapless and the same holds for silicene and germanene.45 There are, however, options to open a gap in these materials. For graphene, the first approach is to form narrow GNRs by either chemical synthesis91,92 or lithographic patterning.93,94 Chemically synthesized GNRs with atomically precise edges have been reported while patterned GNRs typically show non-ideal edges that degrade carrier transport. Fig. 9 compiles theoretical bandgap data (calculated by the GW method) together with experimental bandgap data for GNRs and shows the general trend of an increasing gap for decreasing width. As can be seen, narrow ribbons having a width of 10 nm or less are needed to achieve the 0.4 eV gap required for digital logic.
Fig. 9 Bandgap of GNRs vs. ribbon width. Shown are theoretical data obtained by the GW method for ac (armchair) GNRs of the 3p, 3p + 1, and 3p + 2 families (full triangles and lines, p is an integer) and for zz (zigzag) GNRs from ref. 87, together with measured results for chemically synthesized89,90,95 and lithographically patterned93,94 GNRs.
The second option to open a gap in graphene is by applying a perpendicular electric field to BLG, i.e., two graphene layers, one located directly on top of the other.96,97 As shown in Fig. 7, the conduction and valence bands of biased BLG are not parabolic as for most other semiconductors, but Mexican-hat-shaped.96 For FET-relevant BLG structures, realistically gaps up to 130 meV can be expected.97 This might be helpful for RF FETs but is not sufficient for digital logic FETs.
Recent calculations have predicted a gap opening in silicene and germanene nanoribbons98 as well as in single-layer silicene and germanene when a vertical electric field is applied.99 For a given field, however, the gap in silicene and germanene is smaller than that in biased BLG. Thus, regarding the bandgap, large-area silicene and germanene are not suited for logic FETs and their potential for RF FETs is unclear.
The bandgaps of the 2D materials (except Dirac materials, nanoribbons, BLG, and biased silicene and germanene) are summarized in Fig. 10. To guarantee consistency, all gaps shown are calculated by DFT. True semiconductors (EG = 0.5–2 eV) are phosphorene, germanane, fluorosilicene, the Mo- and W-based TMDs, as well as HfS2, ZrS2, and TiS2, GaSe, InSe, and several MX-enes. Graphane, silicane, fluorographene, GaS, InS, and SiC can be considered as wide bandgap semiconductors while BN is an insulator. For comparison, bandgap data for conventional 3D semiconductors widely used for FET channels are also shown in Fig. 10.
Fig. 10 Bandgap of semiconducting and insulating 2D materials calculated by DFT (data taken from ref. 45 unless otherwise stated). The letters indicate the material class. (a) Semiconducting X-enes (phosphorene,100 note that graphene, silicene, and germanene are gapless). (b) X-anes (from top to bottom graphane, silicane, germanane). (c) Fluoro-X-enes (fluorographene, fluorosilicene, note that fluorogermanene is gapless). (d) Mo-based TMDs (MoS2, MoSe2, MoTe2). (e) W-based TMDs (WS2, WSe2, WTe2). (f) Further disulfides (HfS2, ZrS2, TiS2). (g) SMCs (GaS, InS, GaSe, InSe). (h) MX-enes62,101 (top: Sc2CO2, middle: Hf2CO2, Sc2CF2, Ti2CO2 (all 1 eV), bottom: Zr2CO2). (i) BN, SiC. Also shown are the gaps of conventional 3D semiconductors labeled as material class k (GaN, GaAs, Si, In0.53Ga0.47As, Ge, InAs).
In summary we state that in terms of bandgap many 2D materials fulfill the requirements of our wish list and therefore are suitable for FET channels.
It is well established that the carrier mobility of semiconductors tends to decrease with increasing bandgap. From Fig. 11 showing this trend for the electron mobility μn, we see that for the III–V compounds (black full circles), the electron mobility reduces from 77 000 cm2 V−1 s−1 for the narrow-bandgap InSb to 3000 cm2 V−1 s−1 for the wider-bandgap Ga0.51In0.49P (EG = 1.85 eV). Si (EG = 1.12 eV) and Ge (EG = 0.66 eV) follow this tendency although for these materials the electron mobility is lower than that of the III–V compounds with a comparable gap. Also graphene cannot escape from this mobility-bandgap trend. Suspended gapless graphene shows very high electron mobilities of up to 200 000 cm2 V−1 s−1. The electron mobility in gapless graphene on insulating substrates is lower, but still impressively high as shown in Table 2. The gap opening in GNRs and biased BLG results, however, in a dramatic mobility reduction.
Fig. 11 Room-temperature electron mobility vs. bandgap for different materials. The data for the conventional 3D bulk semiconductors taken from the compilation in ref. 44 relate to undoped material. III–V materials (black solid circles), from left to right InSb, InAs, In0.53Ga0.47As, InP, GaAs, In0.52Al0.48As, Al0.3Ga0.7As, Ga0.51In0.49P. Experimental data for graphene and simulated mobilities for GNRs and BLG taken from the compilation in ref. 3. Calculated mobilities for silicene and germanene taken from ref. 104–106. Simulated MoS2 mobilities taken from ref. 104, 107 and 108, experimental MoS2 data taken exemplarily from ref. 6 and 109–112, and those for WS2, MoSe2 and WSe2 from ref. 113, 114, 124 and 125.
Velocity-field characteristics for gapless graphene have been simulated and measured, and for BLG, GNRs, silicene, and MoS2 high-field transport data have been simulated. The reported v–E characteristics of 2D materials show a soft saturation with a slight decline of the velocity at high fields. Table 3 summarizes the available saturation and peak velocity data for 2D materials. These high-field transport data can be compared with the v–E characteristics for Si and GaAs in Fig. 8.
It should be mentioned that for future generations of Si-based logic ICs, ultra-thin-body SOI MOSFETs and possibly Si nanowire MOSFETs with ultra-small body cross-section will be needed and that in these structures, the mobility is degraded and much smaller compared to bulk Si. For example, in sub-5 nm diameter Si nanowire MOS structures, the electron mobility at low perpendicular effective fields can be below 100 cm2 V−1 s−1 and drop further at higher effective fields down to a few tens of cm2 V−1 s−1.133,134 Thus, several 2D semiconductors can be considered as a viable alternative.
If carrier transport data for a new material are not available, an examination of the material's band structure and carrier effective mass can be helpful. Although the effective mass is not the only quantity influencing the mobility, a light effective mass is always an indication for a high mobility. In Fig. 12 the electron effective mass of 2D materials and of conventional semiconductors is plotted as a function of the bandgap.
Fig. 12 Electron effective mass of 2D and conventional 3D semiconductors vs. bandgap. III–V compounds (black solid circles), from left to right InSb, InAs, In0.53Ga0.47As, InP, GaAs, Al0.3Ga0.7As. Data for TMDs and graphane from ref. 45, for germanane from ref. 53, for GNRs from ref. 135, and for phosphorene from ref. 136 and 137. The numbers at the GNR data points indicate the ribbon width according to the width–gap relationship from ref. 87.
For conventional semiconductors (Si, Ge, III–V compounds) the hole mobility μp is always lower than the electron mobility. This is particularly true for the III–V compounds with very high electron mobility. The ratio μp/μn is around 0.5 for Ge, 0.3 for Si, 0.05 for GaAs, and approaches 0.01 for the narrow bandgap compounds InAs and InSb. For the Mo- and W-based TMDs45 and for germanane,53 as well as for phosphorene for transport in the armchair direction,100,136,137meff-n/meff-p ratios (meff-n and meff-p are the electron and hole effective masses) of 0.8–1 have been calculated and band structure calculations for BLG and GNRs also reveal a high degree of symmetry of the top of the valence band and the bottom of the conduction band. This suggests μp/μn ratios close to unity for these materials. For CMOS logic, μn ≈ μp is highly desirable since under these conditions a symmetric design of n- and p-channel MOSFETs is possible.
When comparing the electron mobilities of the 2D materials in Fig. 11 with those of the conventional 3D semiconductors it seems that the semiconducting 2D materials show rather moderate mobilities and, with the exception of germanene, do not compete well. This leads us to the conclusion that the 2D materials cannot compete with the high-mobility III–V compounds and will not be suitable for ultra-fast high-performance transistors. On the other hand, their mobilities are appropriate for many other applications where high speed is not of primary importance. The calculated electron mobility of more than 18 000 cm2 V−1 s−1 for germanane,106 on the other hand, is very promising. However, this result needs to be confirmed by experiments and to be reproduced by calculations of other groups.
Table 4 summarizes the currently available data for the thermal conductivity of 2D materials in comparison with that of 3D bulk materials. The thermal conductivity of suspended graphene exceeds that of metals (e.g., κCu = 400 W m−1 K−1) and the maximum reported record value from ref. 138 is even above that of bulk graphite. The thermal conductivity of graphene on SiO2 is still high but lower compared to suspended graphene due to interface interactions. GNRs as well as the Mo- and W-based TMDs show lower thermal conductivities.
Table 5 shows the thermal boundary resistance RTB of graphene/SiO2, graphene/SiC, and graphene/BN junctions and for comparison that of silicon on SiO2 as used in modern SOI structures. Unfortunately, information on the thermal boundary resistance for the 2D materials beyond graphene is not yet available. The measured RTB of single-layer graphene on SiO2 145,146 is more than a factor of 10 larger than that calculated for Si on SiO2.147,148 This factor of 10, however, is less critical than it seems on first sight. Usually the thermal resistance encountered by the heat flow from the chip surface (where the devices are located and the heat is generated) to the heat sink at the back side of the chip is much larger than the thermal boundary resistance the heat has to surmount when flowing from the 2D channel to the underlying substrate. To illustrate this issue, let us consider a graphene device layer located on a Si wafer (thickness tSi = 360 μm) covered with SiO2 (thickness tSiO2 = 90 nm) and assume the simplified case of a homogeneous heat flow from the graphene layer downward to the bottom of the substrate. The heat generated in the graphene layer first crosses the graphene/SiO2 interface having a thermal boundary resistance RTB1, flows through the SiO2 layer with a thermal resistance Rth-ox, then crosses the SiO2/Si interface (RTB2), and finally flows through the Si substrate (Rth-Si).
where A is the area of the device layer. Using the data from Tables 4 and 5, one obtains RTB1 = 10−8 m2 K W−1, Rth-ox = 6 × 10−8 m2 K W−1, RTB2 = 10−9 m2 K W−1, and Rth-Si = 2.8 × 10−6 m2 K W−1, which clearly shows the dominating role of the substrate for heat removal.
Reliable targets for the thermal conductivity and the thermal boundary resistance of FET channel materials have not yet been established. It is certainly fair, however, to state that both κ and RTB of the 2D materials should not fall far behind those of Si and the III–V compounds.
The first contact experiments for 2D materials have been focused on graphene and revealed that achieving low-resistance contacts is challenging. In late 2010, the best metal–graphene contact resistances have been in the range 0.5–10 Ω mm,154i.e., orders of magnitude higher than for contacts to Si and III–V compounds. Therefore, a lot of effort has been invested in reducing the metal–graphene contact resistance that finally led to significant improvements. Today, metal–graphene contact resistances as low as 0.01–0.2 Ω mm have been achieved. This already comes close to the resistance of state-of-the-art metal contacts on Si and III–V semiconductors.
Meanwhile, data for metal–TMD and metal–phosphorene contacts have been reported as well. Here, however, the contact resistance is still too high and typically exceeds 0.5 Ω mm. Table 6 summarizes the state-of-the-art metal contacts on 2D materials and on conventional semiconductors.
From the ITRS one can get an impression about the contact requirements related to logic MOSFETs. During the entire horizon of the 2013 ITRS edition, the maximum allowed parasitic resistance (which includes both the contact resistance itself and the semiconductor series resistance, see eqn (4)) is around 0.065 Ω mm. Thus, the contact resistance must be significantly below 0.065 Ω mm. As Table 6 indicates, so far only graphene has fulfilled this requirement. Given the successful reduction of Rco for metal–graphene contacts by more than an order of magnitude within a few years, we expect sizeable improvements for TMD and phosphorene contacts in the near future as well.
Table 7 shows the scale length λ of GNR, MoS2, and Si MOSFETs as well as of InP HEMTs and GaAs mHEMTs obtained using eqn (8). The results indicate that, in terms of scale length and thus regarding the suppression of short-channel effects and scaling limits, the FETs with 2D channels behave much better than those with conventional channel materials.
In the following, the status of research on 2D transistors is reviewed by presenting experimental transistor data collected from the literature. In addition, transistor performance trends are discussed on the basis of theoretical considerations.
5.1.1 Graphene FETs. Recently, several comprehensive review papers on the state-of-the-art graphene FETs have been published.3,102,170,171 Therefore, we only summarize the main messages of these papers and refer the reader to ref. 3, 102, 170 and 171 for more details.
5.1.2 Graphene MOSFETs for digital logic. MOSFETs with gapless large-area graphene channels do not switch off and show on–off ratios of only 2–10. Thus, large-area graphene is not a suitable channel material for logic MOSFETs. Back-gate GNR MOSFETs with on–off ratios of 104 to >106 have been successfully fabricated.91,172,173 Due to the thick back-gate dielectrics, however, these transistors need unacceptably large gate voltage swings of 3–20 V for switching. As we have shown in Fig. 2, the supply voltage for logic circuits (and thus the maximum available gate voltage swing) is currently below 1 V and is required to decrease further in the future. Therefore, top-gate GNR MOSFETs with very thin gate dielectrics are needed to achieve good switching behavior with a sub-1 V gate voltage swing. Moreover, as has been shown in Fig. 11, the gap opening in GNRs is accompanied by a dramatic mobility reduction. For these reasons, in the short to medium term the application of GNR MOSFETs in digital logic is rather unlikely. Things may change at 5 nm and below gate length levels when direct source–drain tunneling becomes an issue.
To circumvent the problems of gapless large-area graphene, vertical non-FET transistor concepts that do not require a gap for switch-off have been elaborated. These concepts rely either on graphene–Si Schottky barriers as described in ref. 174, where on–off ratios of up to 105 have been demonstrated, on tunneling through an insulator between two graphene layers,175 or on using graphene as the base of a hot electron transistor.176 These devices represent interesting options to exploit gapless graphene in logic transistors and can in general be realized also using 2D materials beyond graphene. It is difficult, however, to assess their true potential for future logic at the moment.
5.1.3 Graphene MOSFETs for RF. So far, only experimental graphene RF FETs with gapless channels have been reported. Soon after the demonstration of the first graphene MOSFET with a gapless channel,177 the RF capabilities of such transistors have been investigated,178 and meanwhile many groups have realized RF MOSFETs with gapless graphene channels. Table 8 summarizes the best reported cutoff frequencies fT and maximum frequencies fmax of such graphene MOSFETs, together with the fT − fmax performance of competing RF FET types. More details can be found in the fTvs. L and fmaxvs. L plots of ref. 3.
In terms of fT, graphene MOSFETs perform competitively. They outperform Si MOSFETs with comparable size and compete well with InP HEMTs and GaAs mHEMTs (which are the fastest RF FETs of all) down to gate lengths of about 60 nm.3 Regarding the more important FOM fmax, however, the picture looks less promising for graphene MOSFETs. While the record fmax of InP HEMTs and GaAs mHEMTs exceeds 1 THz and Si MOSFETs with an fmax of 420 GHz have been reported, the best graphene RF FETs show an fmax of about 100 GHz only.182 It has been discussed in detail that the main reason for this poor fmax performance is the missing gap in large-area graphene.3 Thus, no matter how carefully the design of large-area graphene FETs is optimized, these transistors will never compete well with III–V HEMTs and Si MOSFETs in terms of power gain and fmax.
When comparing experimental fT and fmax data of graphene MOSFETs with that of other RF FETs, one should take a closer look at the applied de-embedding procedure. De-embedding is a common practice in RF electronics to eliminate the effect of the parasitics of the measurement environment from the measured RF data. Usually all parasitics down to the large pads (needed for the RF probes) are de-embedded while the metal lines from the pads to the transistor are not de-embedded. In the RF characterization of graphene MOSFETs, however, frequently these metal lines are de-embedded as well. This full de-embedding procedure provides the RF parameters of the intrinsic device which are difficult to compare with those obtained by the common pad de-embedding approach and leads to a very optimistic picture of the transistor's RF performance. This issue has nicely been discussed in ref. 187 and its relevance becomes evident from Table 9 comparing the fT and fmax data of a 260 nm gate graphene MOSFET obtained by different de-embedding procedures.
where T0 is the ambient temperature during measurement. It should be noted sometimes that other expressions such as MN = TN-min/(f × L) or NFmin/(f × L) are used as noise-related FOM.188,190 These figures, however, may be misleading since they result in noticeably different numbers of MN for one and the same transistor at different frequencies. Table 10 shows MN after eqn (12) for graphene MOSFETs and competing state-of-the-art RF FETs based on noise figures consistently measured at a frequency of 8 GHz. The choice of this frequency is a compromise since it marks the upper bound up to which experimental noise data for graphene MOSFETs are available at present and the lower bound of published experimental noise data for III–V HEMTs which are usually characterized at much higher frequencies.
a De-embedded. b As measured.
As Table 10 shows, the noise performance of graphene transistors significantly lags behind that of InP and GaAs HEMTs, but their MN is close to that of RF Si MOSFETs.
While so far experimental RF data for GNR MOSFETs have not been reported, their fT performance has been studied using simulations. An overview of recent simulation activities for graphene RF MOSFETs with both gapless large-area and GNR channels can be found in ref. 199. Taking carrier scattering into account, a cutoff frequency of 5 THz has been simulated for a 10 nm gate transistor with a 10 nm wide GNR channel.200 Without experimental results for RF GNR MOSFETs it is hard to judge this result, particularly since, in simulations, usually idealized device structures and conditions are assumed. Although fmax simulations for GNR MOSFETs are still missing, we expect that due to the gap opening in narrow GNRs a notable improvement of fmax compared to gapless graphene MOSFETs should be possible. On the other hand, achieving an fmax performance of GNR MOSFETs better than that of InP HEMTs and GaAs mHEMTs is rather unlikely owing to the much lower mobility of GNR channels.
An interesting direction in 2D transistor research that concerns transistors with gapless graphene and TMD channels and that recently has attracted considerable interest is the development of MOSFETs on flexible substrates. Graphene and the 2D materials beyond graphene are bendable and can easily be transferred to flexible substrates without seriously affecting the carrier mobility. For example, electron and hole mobilities of 8000 cm2 V−1 s−1 and 6000 cm2 V−1 s−1, respectively, have been reported for CVD-grown graphene transferred to polyimide.201 This is orders of magnitude more than the mobility of organic semiconductors which are commonly used for flexible electronics. Although flexible graphene transistors suffer from the missing switch-off as do their counterparts on rigid substrates, they show promise for flexible RF electronics. Fig. 13 summarizes the state-of-the-art RF performance of flexible 2D transistors. Particularly remarkable are the results for a 260 nm gate flexible graphene MOSFET showing an fT of 198 GHz and an fmax of 28 GHz.187 For comparison, the fastest competing organic transistor reported so far is a 2 μm gate pentacene-channel MOSFET showing an fT of 27.7 MHz.202 Even when the relatively long gate is taken into consideration, this transistor behaves much worse compared to flexible 2D FETs.
Fig. 13 RF performance of 2D MOSFETs on flexible and rigid substrates. (a) Cutoff frequency fTvs. gate length. (b) Maximum frequency of oscillation fmaxvs. gate length. The respective record fT and fmax data are shown by large symbols. The numbers next to the record data points are the frequency (fT or fmax) and the gate length of the transistor. Data taken from ref. 179, 182, 187, 201, 205 and 206 for MOSFETs with graphene, from ref. 163 and 207 with MoS2, and from ref. 208 with phosphorene channels.
Thus, the 2D materials are very promising for flexible electronics. Graphene is particularly interesting for flexible RF electronics while phosphorene and the TMDs are useful for both flexible digital and RF applications due to their semiconducting nature.
5.1.4 Phosphorene and silicene MOSFETs. In 2014, the first experimental phosphorene MOSFETs were reported.48,100,208 The channels of these transistors obtained by exfoliating few-layer phosphorene flakes (several nm thick) from black phosphorus crystals show p-type conductivity and hole mobilities ranging from 286 cm2 V−1 s−1 (ref. 100) to almost 1000 cm2 V−1 s−1.48 As can be expected from the reasonably wide gap of phosphorene, high on–off ratios of up to 105 have been reported.100 Particularly interesting are a 300 nm RF phosphorene MOSFET showing an fT of 12 GHz and an fmax of 20 GHz, see Fig. 13,208 and the first flexible phosphorene MOSFET circuits.209 Phosphorene transistors have (even for 2D transistor standards) a short history. Nevertheless, remarkable results have been obtained in such a short period of time and further progress in phosphorene transistor processing and performance is expected in the near future. More work is needed, however in order to assess the true potential of these transistors.
In 2015, the first silicene MOSFET was demonstrated.70 This back-gate device shows an on–off ratio of around 10 only due to the gapless silicene channel.
The current–voltage characteristics of graphane n- and p-channel MOSFETs have been simulated and, assuming ballistic carrier transport, on–off ratios of 105–106 have been obtained for a gate voltage swing of 0.8 V.210 Due to the fact that in graphane (in contrast to other bulk and 2D semiconductors) the electron effective mass is heavier than the hole effective mass, a higher on-current has been predicted for the p-channel MOSFET. Recently the first experimental graphane-like MOSFET has been reported.211 For this back-gate transistor with a hydrogenated graphene channel having a hydrogen coverage of 25% (compared to 100% for true graphane) and a gap of 4 eV, an on–off ratio of 3 × 106 has been measured for a gate voltage swing of more than 40 V.
Since MoS2 is bendable,214 it is attractive for flexible electronics. Indeed, MoS2 MOSFETs on flexible substrates have been demonstrated.207,215 Due to their relatively low channel mobility, MoS2 MOSFETs show worse fT performance compared to graphene MOSFETs, see Fig. 13(a). They have, however, the big advantage of a semiconducting channel with a sufficiently wide gap leading to excellent switch-off as well as good drain current saturation and thus reasonable power gain and fmax. The current record RF performance for MoS2 MOSFETs is defined by a 68 nm gate transistor on a rigid SiO2/Si substrate showing an fT of 42 GHz and an fmax of 50 GHz and its counterpart on a flexible substrate with fT = 13.5 GHz and fmax = 10.5 GHz.207 Thus, MoS2 MOSFETs are very promising for flexible digital and RF applications.
While experimental work on TMD transistors has so far focused on MoS2 MOSFETs, recently the first single- and/or multi-layer WSe2,216 WS2,217 MoSe2,218 and MoTe2 219 MOSFETs have been demonstrated.
As we have seen in Fig. 2, logic MOSFETs with gate lengths around 5 nm will be needed in 2028. This target was the motivation for numerous theoretical studies on the behavior of 5 nm gate MOSFETs.18,19,223 It has been shown that in such short channels direct source–drain tunneling becomes a serious issue, and that particularly high-mobility (and thus low-effective-mass) channels will suffer from unacceptably large tunneling currents. This suggests that channel materials with heavier carrier effective mass such as the TMDs would be a viable option. While the tunneling currents in 5 nm TMD channels have been analyzed by simulations,224 a study comparing the tunneling tendency of 5 nm Si and III–V channels with that of TMD channels is still missing. In the following we provide such a comparison for n-channel MOSFETs employing a simple first-order approximation.
where c is a constant and M is the number of propagating modes (4 for the Si and Ge NWs and 1 for the III–V NWs19). As can be seen from Fig. 14(a), our simple approach reproduces the tunneling currents and the order of the materials from ref. 19 properly. This shows that the transmission coefficient according to eqn (14) is a reasonable measure to assess and compare the source-to-drain tunneling tendency in different materials.
Fig. 14 Tunneling behavior of 5 nm wide source–drain barriers. (a) Tunneling currents of 5 nm n-channel NW MOSFETs vs. electron tunneling effective mass of the barrier material from ref. 19 (blue curve) and calculated using eqn (14) and (15) with c = 10.4 μA. (b) Transmission coefficient through a 5 nm wide barrier vs. the electron effective mass of the barrier. Symbols indicate the calculated coefficients for 6 nm diameter NWs (black squares, from left to right InSb, InAs, GaAs, Ge, Si), 3.8 nm diameter strained Si NWs (red circles), W-based TMDs (blue circles, from left to right WS2, WSe2, WTe2), Mo-based TMDs (green circles, from left to right MoS2, MoSe2, MoTe2), and GNRs (olive stars, width from left to right 5, 3, 1.48, 1.11, and 0.74 nm).
Fig. 14(b) shows the transmission coefficient through a 5 nm wide barrier as a function of the carrier effective mass of the channel material. The transmission coefficients have been calculated using eqn (14) and assuming the potential profile from ref. 19. Indicated by symbols are the transmission coefficients for selected 2D materials, 6 nm diameter Si, Ge, and III–V NWs using the effective masses from ref. 19, and different GNRs. As can be seen, the TMDs and the narrowest GNRs clearly outperform the III–V NWs in terms of tunneling. It should be noted that in narrow Si NWs the carrier effective mass can be tuned over a wide range by properly choosing the wire direction and strain.223 Therefore, in Fig. 14(b) the transmission coefficients for two compressively strained Si NWs with 3.8 nm diameter are included. NW (i) is <110> oriented and experiences −3 GPa strain leading to an electron effective mass of 0.581 × m0 and NW (ii) is <100> oriented, strained by −2 GPa, and shows an electron effective mass of 0.948 × m0.223 As can be seen, both NWs perform highly competitively in terms of tunneling. Thus, apart from TMDs and narrow GNRs, Si NWs are a possible option for the channels of beyond-roadmap MOSFETs. This leads us to the conclusion that Si remains a strong contender even at the end of and beyond the ITRS horizon.
Based on the results of our previous study, Fig. 15 shows a possible scenario for the choice of MOSFET channel materials. As discussed above and shown in Fig. 14(b), particularly the Mo-based TMDs, well-designed strained Si NWs, and narrow GNRs may become attractive beyond the horizon of the 2013 ITRS edition due to their reasonably heavy carrier effective mass.
Fig. 15 Possible scenario for the selection of the channel materials for logic MOSFETs. sSi means strained Si, μ is the carrier mobility, meff is the carrier effective mass, and 2Ds means semiconducting 2D materials.
Recently transistors with multiple 2D materials in different device parts have been demonstrated.164,226–228 The general idea of all-2D MOSFETs is to use a suitable 2D material, e.g., MoS2 or WS2, for the channel, boron nitride as a gate dielectric, and gapless graphene for the contacts.
Research on 2D materials for electronic applications is a new field as can be seen from the fact that the first graphene, MoS2, and phosphorene MOSFETs have been reported in 2007, 2011, and 2014, respectively. Given this short history, the achievements made so far are remarkable and further progress is expected. On the other hand, it is extremely difficult to assess the real potential of the 2D materials in electronics. Table 11 lists, based on our current state of knowledge and provided that high-quality 2D layers can be realized in an industrial environment, our expectations on future applications of several 2D materials for MOSFET channels.
a The high mobility of germanene is yet to be confirmed. hp: high performance; mp: medium performance; flex: flexible. A question mark indicates that the advantages, drawbacks, and potential applications are not clear yet.
Due to their zero gap, the gapless X-enes are not suitable for logic and high-performance RF FETs. The bendability and high mobility make graphene, however, a candidate for flexible medium-performance RF FETs. The semiconducting 2D materials with the exception of germanane suffer from low mobilities and therefore show only a little promise for high-performance logic (as long as source–drain tunneling is not an issue) and RF transistors, while they may find applications in flexible medium-performance logic and RF circuits. Due to their thinness (resulting in short scale lengths) and relatively heavy carrier effective mass (leading to suppressed source–drain tunneling) they may become an option for sub-5 nm logic FETs. It should be recognized, however, that multiple-gate Si NW transistors will be strong competitors in this field. In case germanane actually shows such a high mobility as predicted in ref. 53, it could become a very interesting material for high-performance logic and RF FETs.
We note that the fascinating variety of 2D materials is both a blessing and a curse – a blessing for researchers for whom the 2D materials are a new and wide field for exciting science, and a curse since the available funding for research spreads across many materials. Thus, sooner or later funding and research activities need to be focused on a limited number of promising 2D materials.
In conclusion we believe that research on 2D materials is just at the beginning and will stay a very exciting field. We are convinced that eventually certain 2D materials will find their applications in electronics, particularly since they can be used not only in transistors but also for other purposes, such as transparent electrodes, sensors, touch screen displays, etc., which are possibly closer to industrial fabrication than 2D transistors.
This work was supported by the Excellence Research and the Intra-Faculty Research Grants of Technische Universität Ilmenau, Germany, and by DFG under contract numbers SCHW 729/16-1 and PE 624/11-1. The authors would like to thank A. Alsioufy and M. Lootze for processing MoS2 and WS2 devices as well as F. Bechstedt, T. Heine and A. MacDonald for fruitful discussions and D. Akinwande for providing experimental results prior to its publication.
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