Source: https://patents.google.com/patent/US9164937B2/en
Timestamp: 2019-04-25 04:16:15+00:00

Document:
A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
This application is a continuation of U.S. patent application Ser. No. 13/612,490, filed Sep. 12, 2012, and issued as U.S. Pat. No. 8,694,735 on Apr. 8, 2014, which is a continuation of U.S. patent application Ser. No. 12/840,007, filed Jul. 20, 2010, and issued as U.S. Pat. No. 8,291,173 on Oct. 16, 2012, which is a continuation of U.S. patent application Ser. No. 10/773,583, filed Feb. 5, 2004, and issued as U.S. Pat. No. 7,788,451 on Aug. 31, 2010. These applications and patents are incorporated herein by reference, in their entirety, for any purpose.
The present invention relates to memory systems, and more particularly, to memory modules having a data bypass for preventing data collision on a bi-direction data bus.
Although computer systems using memory hubs may provide superior performance, they may often rail to operate at optimum efficiency for a variety of reasons. One such reason is the issue of managing data collision between data flowing to and from the memory controller through the memory hubs. In conventional memory controllers, one approach taken to avoid data collision is to delay the execution of one memory command until the completion of another memory command. For example, with a conventional memory controller, a write command issued after a read command is not allowed to begin until the read command is nearly completed in order to avoid the read (i.e., inbound) data colliding with the write (i.e., outbound) data on the memory bus. However, forcing the write command to wait effectively reduces bandwidth, which is inconsistent with what is typically desired in a memory system.
One aspect of the present invention is directed to a memory hub having a data bypass circuit. The memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces. The memory hub further includes a write bypass circuit coupled to the data path for coupling write data on the data path and temporarily storing the write data to allow read data to be transferred through the data path while the write data is temporarily stored. In another aspect of the invention, a method for writing data to a memory location in a memory system coupled to a memory bus is provided. The method includes accessing read data in the memory system, providing write data to the memory system on the memory bus, and coupling the write data to a register for temporary storage of the write data. While the data is temporarily stored, the read data is coupled from the memory bus and provided for reading. The write data is recoup led to the memory bus and written to the memory location.
FIG. 1 is a block diagram of a computer system having memory modules in a memory hub architecture in which embodiments of the present invention can be implemented.
FIG. 2 is a partial block diagram of a memory hub according to an embodiment of the present invention for use with the memory modules of FIG. 1.
FIG. 3 is a block diagram of a data bypass circuit for the memory hub of FIG. 2 according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating the operation of the data bypass circuit of FIG. 3 for a computer system having the memory hub architecture of FIG. 1 and the memory hub of FIG. 2.
Embodiments of the present invention are directed to a memory hub having bypass circuitry that provides data bypass for a bi-directional data bus in a hub-based memory sub-system. Certain details are set forth below to provide a sufficient understanding of various embodiments of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention.
FIG. 1 illustrates a computer system 100 according to one embodiment of the present invention. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to cache memory 108. Typically, the cache memory 108 is provided by a static random access memory (“SRAM”). The processor bus 106 is also coupled to a system controller 110, which is sometimes referred to as a bus bridge.
The system controller 110 serves as a communications path to the processor 104 for a variety of other components. For example, as shown in FIG. 1, the system Controller 110 includes a graphics port that is typically coupled to a graphics controller 112. The graphics controller is typically coupled to a video terminal 114, such as a video display. The system controller 110 is also coupled to one or more input devices 118, such as a keyboard or a mouse, to allow an operator to interface with the computer system 100. Typically, the computer system 100 also includes one or more output devices 120, such as a printer, coupled to the processor 104 through the system controller 110. One or more data storage devices 124 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).
The system controller 110 includes a memory hub controller 128 that is coupled to memory hubs 140 of several memory modules 130 a, 130 b, 130 c, . . . 130 n. The memory modules 130 serve as system memory for the computer system 100, and are preferably coupled to the memory hub controller 128 through a high-speed bi-directional memory controller/hub interface 134. The memory modules 130 are shown coupled to the memory hub controller 128 in a point-to-point arrangement in which the memory controller/hub interface 134 is coupled through the memory hubs 140 of the memory modules 130. That is, the memory controller/hub interface 134 is a bi-directional bus that couples the memory hubs 140 in series. Thus, information on the memory controller/hub interface 134 must travel through the memory hubs 140 of “upstream” memory modules 130 to reach a “downstream” destination. For example, with specific reference to FIG. 1, information transmitted from the memory huh controller 128 to the memory hub 140 of the memory module 130 c will pass through the memory hubs 140 of the memory modules 130 a and 130 b.
It will be appreciated, however, that topologies other than the point-to-point arrangement of FIG. 1 may also be used. For example, a coupling arrangement may be used in which a separate high-speed link (not shown) is used to couple each of the memory modules 130 to the memory hub controller 128. A switching topology may also be used in which the memory hub controller 128 is selectively coupled to each of the memory modules 130 through a switch (not shown). Other topologies that may be used will be apparent to one skilled in the art. Additionally, the memory controller/hub interface 134 coupling the memory modules to the memory hub controller may be an electrical or optical communication path. However, other types of communications paths can be used for the memory controller/hub interface 134 as well. In the event the memory controller/hub interface 134 is implemented as an optical communication path, the optical communication path may be in the form of one or more optical fibers. In such case, the memory hub controller 128 and the memory modules will include an optical input/output port or separate input and output ports coupled to the optical communication path, as well known in the art.
The memory hubs 140 control access to memory devices 148 of the respective memory module 130. In FIG. 1, the memory devices are illustrated as synchronous dynamic random access memory (“SDRAM”) devices. However, memory devices other than SDRAM devices may also be used. As also shown in FIG. 1, the memory hub is coupled to four sets of memory devices 148 through a respective memory bus 150. Each of the sets includes four memory devices 148 for a total of 20 memory devices 148 for each memory module 130. The memory busses 150 normally include a control bus, an address bus, and a data bus, as known in the art. However, it will be appreciated by those ordinarily skilled in the art that other bus systems, such as a bus system using a shared command/address bus, may also be used without departing from the scope of the present invention. It will be further appreciated that the arrangement of the memory devices 148, and the number of memory devices 148 can be modified without departing from the scope of the present invention.
FIG. 2 illustrates a portion of the memory hub 140 according to an embodiment of the present invention. The memory huh 140 includes a local hub circuit 214 coupled to the memory controller/hub interface 134 (FIG. 1). The local hub circuit 214 is further coupled to memory devices 148 through the memory bus 150. The local hub circuit 214 includes control logic for processing memory commands issued from the memory controller 128 and for accessing the memory devices 148 over the memory bus 150 to provide the corresponding data when the memory command is directed to the respective memory module 130. The design and operation of such control logic is well known by those ordinarily skilled in the art, and consequently, a more detailed description has been omitted from herein in the interest of brevity. The memory hub 140 further includes a data bypass circuit 286 coupled to the local huh circuit 214. As will be explained in more detail below, the data bypass circuit 286 is used to temporarily capture data passing to a distant memory hub, which allows data returning from another distant memory hub to pass through the memory hub 140 before the captured data continues onto the distant memory hub. Thus, the data bypass circuit 286 provides a data bypass mechanism that can be used to avoid data collisions on the bi-directional memory controller/hub interface 134 to which the memory hub 140 is coupled.
As previously discussed, one approach taken by conventional memory sub-systems to avoid data collision is to delay the execution of one memory command until the completion of another memory command. For example, in typical memory systems a write command issued after a read command would not have been allowed to start until near the completion of the read command in order to is the read (i.e., inbound) data colliding with the write (i.e., outbound) data on the memory controller/hub interface 134. In contrast, by employing the memory hub 140 having the data bypass circuit 286, write commands issued after a read command can be sequenced earlier than compared with conventional memory systems, and consequently, memory commands scheduled after the earlier scheduled write command can be executed sooner as well.
FIG. 3 illustrates a data bypass circuit 300 according to an embodiment of the present invention. The data bypass circuit 300 can be substituted for the data bypass circuit 286 (FIG. 2) and can be implemented using conventional designs and circuits well known to those ordinarily skilled in the art. The data bypass circuit 300 includes an input buffer 302 that receives input write data WR-DATA_IN and provides the same to a bypass register/FIFO 304 and a first input of to multiplexer 306. An output of the bypass register/FIFO 304 is coupled to a second input of the multiplexer 306. Selection of which of the two inputs to couple to the output of the multiplexer 306 is made by an enable signal EN generated by a bypass select logic 308. The EN signal is also provided to an input/output buffer 310 as an output enable signal activating or deactivating the input/output buffer 310. The bypass select logic 308 generates the appropriate EN signal in response to an activation signal BYPASS_EN provided by the memory hub controller 128 (FIG. 1). Alternatively, the BYPASS_EN signal may be provided from other memory hubs (not shown) that are part of the same memory system. The circuitry of the data bypass circuit is conventional, and it will be appreciated that the circuits of the data bypass circuit 300 can be implemented using conventional designs and circuitry well known in the art.
In operation, WR_DATA_IN received by the data bypass circuit 300 is driven through the input buffer 302 and is provided to the first input of the multiplexer 306. The WR_DATA_IN is also saved in the bypass register/FIFO 304. In response to an inactive BYPASS_EN signal, an active EN signal is generated by the bypass select logic 308. The active EN signal enables output by the input/output buffer 310 and couples the output of the input buffer 302 to the input of the input/output buffer 310 through the multiplexer 306. As a result, the WR_DATA_IN is provided directly to the input of the input/output buffer 310 and the WR_DATA_IN is provided through the data bypass circuit 300 without any bypass. However, in response to an active BYPASS_EN signal, the bypass select logic 308 generates an inactive EN signal, disabling the output function of the input/output buffer 310 and placing its output in a high-impedance state. Additionally, the inactive EN signal couples the input of the input/output buffer 310 to the output of the bypass register/FIFO 304. In this manner, the WR_DATA_IN is received by the data bypass circuit 300, stored by the bypass register/FIFO 304, and applied to the input of the input/output buffer 310. However, due to the inactive state of the EN signal, the WR_DATA_IN is not provided as output data WR_DATA_OUT by the input/output buffer 310. As a result, the WR_DATA_IN is held in a bypass state until the BYPASS_EN signal becomes inactive, at which time, the EN signal become active again, enabling the input/output buffer 310 to provide the WR_DATA as WR_DATA data. The multiplexer 306 is also switched back to coupling the output of the input buffer 302 directly to the input of the input/output buffer 310 to allow WR_DATA_IN to pass through the data bypass circuit unhindered.
Operation of the data bypass circuit 286 will be described with reference to FIG. 4. FIG. 4 is similar to FIG. 1, except that FIG. 4 has been simplified. In particular, many of the functional blocks of FIG. 1 have been omitted, with only the memory modules 130 a-130 c being shown, and represented by memory hubs 140 a-140 c. Only one memory device 148 a-148 c is shown to be coupled to a respective memory hub 140 a-140 c through a respective memory bus 150 a-150 c. As with FIG. 1, the memory hubs 140 a-140 c are coupled by a high-speed bi-directional memory controller/hub interface 134 to a memory hub controller 128.
In FIG. 4, it is assumed that the memory hub controller 128 has just issued read and write commands, with the read command sequenced prior to the write command. The read command is directed to the memory module 130 b and the write command is directed to the memory module 130 c. That is, the memory module to which data will be written is further downstream than the memory module from which data is read. In response to the read command, the memory hub 140 b begins retrieving the read data (RD) from the memory device 148 b, as indicated in FIG. 4 by the “(1)”. With the read command issued, the write command is then initiated, and the write data (WD) is provided onto the memory controller/hub interface 134, However, since the memory hub controller 128 is expecting the RD to be returned from the memory module 130 b, the memory hub 140 a is directed to capture the WD in its data bypass circuit 286 a. As a result, the data bypass circuit 286 a captures the WD to clear the memory controller/hub interface 134, as indicated in FIG. 4 by the “(2)”, for the RD to be returned to the memory hub controller 128. When the memory hub 140 b has retrieved the RD from the memory device 148 b, the RD is then provided to the memory hub controller 128 through the memory controller/hub interface 134, as indicated in FIG. 4 by the “(3)” to complete the read request. Upon the RD passing through the memory hub 140 a on its way to the memory hub controller 128, the memory hub 140 a releases the WD from the data bypass circuit 286 a to continue its way to the memory hub 140 c. The WD is provided to the memory hub 140 c through the high-speed link, which is now clear between the memory hub 140 a and 140 c. Upon reaching the memory hub 140 c, the WD is written in the memory device 148 c, as shown in FIG. 4 by the “(4)”.
In an embodiment of the present invention, coordination of the data flow of the RD and WD on the memory controller/hub interface 134 and through the data bypass circuits 286 is under the control of the memory hub controller 128. For example, in the previous example the memory hub controller ensures that any WO flowing in the opposite direction of the RD is out of the way when retrieving RD from the memory module 130 b. It will be appreciated, however, that in alternative embodiments data flow through the memory controller/hub interface 134 and the data bypass circuits 286 can be managed differently, such as the memory hub controller 128 sharing coordination of the data flow with the memory hubs 140.
In the previous example, the RD is returned to the memory hub controller 128 as in a conventional memory system. That is, the RD transmitted by the memory devices 148 is provided to the memory controller without any significant delay. However, by employing the previously described data bypass mechanism, write commands can be scheduled earlier than with conventional memory systems. A write command issued after a read command would not have been allowed to start until near the completion of the read command in typical memory systems. In contrast, embodiments of the present invention allow a subsequently issued write command to be scheduled earlier, thus, reducing the time gap between read and write commands. As a result, commands scheduled behind an earlier scheduled write command have an overall reduced latency.
a plurality of memory modules coupled to the controller by a bi-directional data bus, and each memory module of the plurality of memory modules coupled to a respective other memory module of the plurality of memory modules by the bi-directional data bus, wherein each memory module of the plurality of memory modules is configured to process memory commands issued from the controller, wherein a first memory module of the plurality of memory modules includes bypass circuitry configured to capture write data associated with a write command passing to a third memory module of the plurality of memory modules, and wherein the first memory module is further configured to allow read data associated with a read command to return from a second memory module of the plurality of memory modules before allowing the captured write data to continue on to the third memory module, and wherein the bypass circuit is further configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between first and second data bus interfaces of the memory module of the plurality of memory modules.
2. The system of claim 1, wherein the controller is configured to issue the write command associated with the write data after issuing the read command associated with the read data and prior to the controller receiving the read data.
3. The system of claim 2, wherein the controller is further configured to provide the write data on an interface coupled to the first memory module after issuing the read command and before receiving the read data.
4. The system of claim 1, further comprising a processor coupled to the controller.
5. The system of claim 1, wherein each memory module of the plurality of memory modules comprises a respective plurality of memory devices.
6. The system of claim 1, wherein the plurality of memory modules are coupled in series.
7. The system of claim 1, wherein each memory module of the plurality of memory modules is coupled to a respective other memory module of the plurality of memory modules through a respective bi-directional interface.
8. The system of claim 1, wherein the first memory module is further downstream than the second memory module relative to the controller and the second memory module is further downstream than the third memory module relative to the controller.
9. The system of claim 1, wherein the plurality of memory modules are configured in a point-to-point arrangement.
bypass select logic coupled to the multiplexer and the write data output buffer, wherein the bypass select logic is configured to provide the control signal and the enable signal based on the read data being transferred over the bi-directional data bus between the first and second data bus interfaces in the first direction.
11. The system of claim 10, wherein the memory module of the plurality of memory modules further includes control logic configured to control the bypass circuit responsive to a bypass signal.
12. The system of claim 11, wherein the control logic receives bypass commands from the memory controller.
13. The system of claim 10, wherein the bypass circuit is configured to store the write data in a register while read data is transferred over the bi-directional data bus between the first and second data bus interfaces in the first direction.
14. The system of claim 10, wherein the bypass circuit is configured to couple an output of an input buffer to an input of an output buffer to restore write data to the data bidirectional bus in the second direction when the read data has finished transmitting.
a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bi-directional data bus, while read data is transferred overwrite data to the data bus in the second direction when the read data has finished transmitting, wherein the bypass circuit is configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between the first and second data bus interfaces.
a first memory module coupled to the controller by a bi-directional data bus and configured to receive the write data and to store the write data, the first memory module coupled to a second memory module by the bi-directional data bus and configured to receive read data associated with a read command from the second memory module, the first memory module configured to provide the read data to the controller and to provide the write data to the second memory responsive to providing the read data to the controller, wherein the first memory controller includes a bypass circuit configured to store write data from the bi-directional data bus while read data is transferred over the data bus between first and second data bus interfaces of the first memory in a first direction and restore write data to the data bus in a second direction when the read data has finished transmitting, wherein the bypass circuit is configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between the first and second data bus interfaces.
17. The system of claim 16, wherein the memory controller is configured to provide the write command after the read command and before receiving the read data.
18. The system of claim 16, wherein the first memory is configured to store the write data in a data bypass circuit.
19. The system of claim 18, wherein the memory controller is configured to cause the first memory to store the write data in the bypass circuit using a bypass enable control signal.
20. The system of claim 16, wherein the read command is associated with the second memory and the write command is associated with a third memory.
"Flash Erasable Programmable Read-Only Memory", "Free On-Line Dictionary of Computing", online May 17, 2004 [http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?flaxh+memory].
"Hyper Transport I/O Link Specification v 1.10", Hyper Transport Consortium, 2003, 1,28-43,80-82.
"HyperTransport I/O Link Specification", HyperTransport Technology Consortium, 2001, pp. 46-49.
"International Search Report and Written Opinion", International Application No. PCT/US2005/02410; International Filing Date Jan. 25, 2005.
"Micron 1Gb: x4, x8, x16 DDR SDRAM", Micron Technology, Inc, Jul. 2003.
"Offical Notice of Rejection", Japanese Patent Application No. 2006-0552148; mailed Mar. 23, 2010.
"Office Action of the IPO", Taiwan Patent Application No. 094104058; issued Mar. 4, 2009.
"Office Action of the IPO", Taiwan Patent Application No. 094104058; May 30, 2008.
"Response to Office Action of the IPO", Taiwan Patent Application No. 094104058; filed May 2009.
"Response to Taiwan Office Action", Taiwan Patent Application No. 094104058; filed Nov. 2008.
"Second Office Action of the People's Republic of China", Patent Application Filing No. 200580010700.8; dated Apr. 17, 2009.
"Supplemental European Search Report", Application No. 05712043.8; mailed Oct. 29, 2009.
EP Office Action for Appl No. 05712043.8 dated Sep. 27, 2013.
Extended search report received for EP 12 194 174.4 dated Feb. 8, 2013.
First Office action dated Jun. 27, 2012 for EP application No. 05 712 043.8.
First Office Action issued Jun. 29, 2012 for European application No. 05 760 644.4.
First Office Action of the People's Republic of China, Patent Application Filing No. 200580010700.8; dated Jan. 20, 2009.
Micron Technology, Inc., "Synohroncus DRAM Module 512MB/1GB (x72, ECC) 168-PIN Registered FBGA SDRAM DIMM", Micron Technology, Inc., 2002, pp. 1-23.
Rambus, Inc., "Direct RambusTM Technology Disclosure", Rambus, Inc, Oct. 1997, 1-16.
Second Office action dated Jan. 22, 2013 for EP application No. 05 712 043.8.
Shanley, T et al., "PCI System Architecture", Third Edition, Mindshare, Inc., 1995, Jul. 1996, 24-25.

References: Application No. 2006
 Application No. 094104058
 Application No. 094104058
 Application No. 094104058
 Application No. 094104058
 Application No. 05712043
 application No. 05
 application No. 05
 application No. 05