Source: https://wiki.analog.com/resources/quick-start/ad5791
Timestamp: 2019-04-20 18:10:37+00:00

Document:
This version (16 Apr 2013 17:08) was approved by EstiS, clon.The Previously approved version (12 Feb 2013 16:56) is available.
INV Inverting input connection for external amplifier.
VREFPS Positive reference sense voltage input. Connect a voltage in the range of 5 V to VDD - 2.5 V.
VREFPF Positive reference force voltage input. Connect a voltage in the range of 5 V to VDD - 2.5 V.
VDD Positive analog supply connection. Connect a voltage in the range of 7.5 V to 16.5 V. VDD must be decoupled to AGND.
Active low reset. Asserting this pin returns the DAC to its power-on status.
Active low input. Asserting this pin sets the DAC register to a user defined value and updates the DAC output.
Active low load DAC logic input. This is used to update the DAC register and, consequently, the analog output.
VCC Digital supply. Connect a voltage in the range of 2.7 V to 5.5 V. VCC must be decoupled to DGND.
IOVCC Digital interface supply. Voltage range is from 1.71 V to 5.5 V.
SCLK Serial clock input. Data can be transferred at clock rates of up to 35 MHz.
Active low digital interface synchronization input. This is the frame synchronization signal for the input data.
DGND Ground reference for digital circuitry.
VREFNF Negative reference force voltage input. Connect a voltage in the range of VSS + 2.5 V to 0 V.
VREFNS Negative reference sense voltage input. Connect a voltage in the range of VSS + 2.5 V to 0 V.
VSS Negative analog supply connection. Connect a voltage in the range of -16.5 V to -2.5 V. VSS must be decoupled to AGND.
AGND Ground reference for analog circuitry.
RFB Feedback connection for external amplifier.
X1 X1	 0	 DAC in reset mode. The device cannot be programmed.
X1 X1	 ⇑2	 DAC is returned to its power-on state. All registers are set to their default values.
0 0	 1	 DAC register loaded with the clearcode register value and output set accordingly.
0 1	 1	 Output set according to the DAC register value.
1 0 1 DAC register loaded with the clearcode register value and output set accordingly.
⇓3 1	 1	 Output set according to the DAC register value.
⇓3 0	 1	 Output remains at the clearcode register value.
⇑2 1	 1	 Output remains set according to the DAC register value.
⇑2 0	 1	 Output remains at the clearcode register value.
1 ⇓3	 1	 DAC register loaded with the clearcode register value and output set accordingly.
0 ⇓3	 1	 DAC register loaded with the clearcode register value and output set accordingly.
1 ⇑2	 1	 Output remains at the clearcode register value.
0 ⇑2	 1	 Output set according to the DAC register value.
1 X is don't care.
2 ⇑ is rising edge.
3 ⇓ is falling edge.
1 X = don't care.
RBUF Output amplifier configuration control.
0 Internal amplifier powered up.
1 (default) Internal amplifier powered down.
OPGND Output ground clamp control.
0 DAC output clamp to ground removed and DAC placed in normal mode.
1 (default) DAC output clamped to ground and DAC placed in tristate mode.
0 DAC in normal operating mode.
1 (default) DAC in tristate mode.
BIN/2sC DAC register coding selection.
0 (default) DAC register uses twos complement coding.
1 DAC register uses offset binary coding.
SDODIS SDO pin enable/disable control.
0 (default) SDO pin enabled.
1 SDO pin disabled (tristate).
LIN COMP Linearity error compensation for varying reference input spans. Note that the reference input span options for the AD5781 are: up to 10 V (0000) and 20 V (1100). See the AD5781 data sheet for additional details.
0000 (default) Reference input span up to 10 V.
1001 Reference input span between 10 V and 12 V.
1010 Reference input span between 12 V and 16 V.
1011 Reference input span between 16 V and 19 V.
1100 Reference input span between 19 V and 20 V.
0 AD5781/AD5791 addressed for a write operation.
1 AD5781/AD5791 addressed for a read operation.
LDAC1 Setting this bit to 1 updates the DAC register and, consequently, the DAC output.
CLR2 Setting this bit to 1 sets the DAC register to a user defined value and updates the DAC output.
RESET Setting this bit to 1 returns the AD5781/AD5791 to its power-on state.
1 The LDAC function has no effect when the pin is low. Refer to Table 2 in the Hardware Control Pins Truth Table section for additional details.
2 The CLR function has no effect when the pin is low. Refer to Table 2 in the Hardware Control Pins Truth Table section for additional details.
VREFN is the negative voltage applied at the VREFNx input pin.
VREFP is the positive voltage applied at the VREFPx input pin.
D is the 18-bit (AD5781) or 20-bit (AD5791) code programmed to the DAC.
Because this initialization is a write to the part, set the R/ bit to a Logic 0.
Keep the default mode for LIN COMP, SDODIS, and RBUF.
To write in binary coding, select BIN/2sC = 1.
Set DACTRI = 0 and OPGND = 0 to place the DAC in normal operating mode and remove the DAC output clamp to ground, respectively.
Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/ bit, three register address bits, 20 data bits).
See Table 6 and Figure 6.
To write in offset binary coding, set BIN/2sC = 1.
The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading back from it.
Set R/ = 0 to select the write option from the read/write bit.
Set C[2:0] = 001 for the correspondent register address.
Set D[19:0], the data bits, for a midscale code.
where X = don't care.
See Table 7 and Figure 7.
To define the value at which the DAC output is set when the pin or CLR bit in the software control register is asserted, write the desired code to the clearcode register.
Set the CLR bit to a Logic 1 to set the DAC register to a user defined value and update the DAC output.
The user should see the DAC output value change to full-scale code.
To confirm the clearcode value written to the part, read the data from the clearcode register (full scale for this example).
Note that this action is a read function. Therefore, set the R/ bit = 1.
D19 to D0, the data bits, are don't care bits because the intention is to read from the part, and not to write to the part.

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