Source: https://www.associazione-sie.it/index.php?option=com_content&view=article&id=59&Itemid=158
Timestamp: 2019-04-22 04:54:07+00:00

Document:
Collaborations: Università di Pavia, Università di Pisa, Università di Bologna, Università di Trento, Università di Trieste, Fermilab (Chicago), Istituto Pluridisciplinare Hubert Curien (IPHC) (Strasburgo).
Collaborations: University of Heidelberg, Mannheim, Germany; Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany; Politecnico di Milano, Dipartimento di Elettronica e Informazione, Milano, Italy; Max-Planck-Institut für extraterrestrische Physik, Garching, Germany and MPI Halbleiterlabor, München, Germany; Università degli Studi di Pavia, Dipartimento di Elettronica, Pavia, Italy.
Vertical integration technology is going to play an important role in the design of advanced silicon pixel sensors in future high energy physics experiments at particle accelerators. These sensors, along with the readout electronics, will be required to have a small pixel pitch, a high degree of radiation tolerance, a large signal-to-noise ratio, a low mass to minimize particle scattering, a low power dissipation and the capability of handling very high data rates. Three dimensional circuit manufacturing involves the independent fabrication of two or more planar circuits on different wafer, which are subsequently bonded together after precise alignment and thinning.
Two main research lines and technological solutions are being followed to exploit 3D vertical integration. The first one can be seen as the development of the classical CMOS MAPS concept of signal charge generation and collection by diffusion in an undepleted silicon region. In these case, vertical integration of two CMOS layers makes it possible to separate the analog front-end electronics from the digital readout section, with great advantages in terms of pixel size, functionalities and performance. The second research line explores the possibility of using 3D integration to interconnect layers fabricated in different technologies, i.e. to connect a sensor built in a fully-depleted high resistivity silicon substrate to readout electronics fabricated in a deep submicron CMOS process. This can provide a large benefit in terms of radiation hardness and signal-to-noise ratio.
The SuperB factory is an Italian e+ e- accelerator project that plans to reach a luminosity higher than 1036 cm-2s-1 by means of a very small beam size and with moderate beam currents. A Silicon Vertex Tracker (SVT) with six layers of microstrip silicon sensors is foreseen in the present design. The very different features of inner (Layer 0-3) and outer layers (4-5) of the SVT set divergent requirements to the readout chips. The SuperB SVT readout chip for inner layers is a 128-channel mixed-signal integrated circuit in a 130 nm CMOS technology and is being designed to comply with the following constraints: hit efficiency >95% at the design luminosity on most of the SVT, S/N of 20 across the whole SVT after irradiation, 30 ns time stamp resolution, radiation tolerance to >3 Mrad/year and ~1013 neq/cm2/year. Each channel consists of a charge-sensitive preamplifier, a second order unipolar semi-Gaussian shaper with selectable peaking time (from 25 ns to 200 ns) and a hit discriminator. A polarity selection signal allows the chip to operate with signals delivered both from n- and p-sides of the SVT double-sided strip detector. A symmetric baseline restorer (BLR) may be included to achieve baseline shift suppression. When a hit is detected, a 3-4 bit analog-to-digital conversion will be performed by means of a Time-Over-Threshold (TOT) detection. This will serve for calibration and monitoring purposes and for dE/dx measurements. The hit information will be buffered until a trigger is received; together with the hit time stamp, it will be then transferred to an output interface, where data are serialized and transmitted off chip on output LVDS lines. An n-bit data output word (about 16 bit for time stamp, microstrip number and signal amplitude) will be generated for each hit on a strip. A programming interface accepts commands and data from a serial input bus and programmable registers are used to hold inputs values for DACs that provide currents and voltages required for the analog section. The digital readout will exploit the architecture that was originally devised for high-rate, high-efficiency readout of a large CMOS pixel sensor matrix. The power dissipation will be about 4 mW/channel including both analog and digital section. The readout chip has to be capable of operating with the required efficiency with a remarkably high background hit frequency, in the order of 2 MHit/s/strip. The submission of a prototype including 64 analog channels and a reduced-scale version of the readout architecture is foreseen for the end of 2012. The submission of the full-scale, 128-channels prototype with full functionality of the final production chip is scheduled in late 2013.
An ultra high speed focal plane detector system is being developed for the new European XFEL (X-ray Free Electron Laser) in Hamburg. The instrument will be able to record X-ray images with a maximum frame rate of 4.5 MHz and to achieve a high dynamic range. This will allow coping with the very demanding pulse time structure of XFEL. The machine will provide macro-bunches with a repetition rate of 10 Hz. Every macro-bunch is composed of ~2700 X-ray pulses with a temporal distance of 220 ns. The device under development will be able to acquire images every 220 ns obtaining a frame rate of 4.5 MHz and high dynamic range at the same time. The number of stored frames per macro-bunch will be up to 640 with the possibility to discard bad frames thanks to an external trigger. The system is based on a novel DEPFET Sensor with integrated Signal Compression (DSSC) designed so as to combine high energy resolution at low signal charge with high dynamic range: special care has been taken in order to achieve single photon resolution also in the energy range 0.5-4 keV. This has been motivated by the desire to be able to be sensitive to single low energy photons and at the same time to measure at other positions of the detector signals corresponding to up to 104 photons of 1keV per pixel. The hexagonal pixels of the DEPFET based sensor will be read out by bump-bonded pixel readout ASICs designed in 130 nm CMOS technology. Each ASIC will have 64x64 pixel channels of 236x204 um2 area, each one containing a low noise (<50 e-) amplification of the DEPFET signal, an 8bit single slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of >512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to <100 mW per ASIC. In the framework of the DSSC chip development an high-linearity, low dispersion injection circuit to be used for pixel-level calibration of detector readout electronics has been designed. The circuit provides a very useful means for precise analog test of the pixel cell units already at the chip level, when no sensor is connected. Moreover, it provides a simple means for calibration of readout electronics once the detector has been connected to the chip. Since in an earlier phase of the DSSC chip development two options for the detector readout have been investigated, two injection circuit architectures have been designed: one for a charge sensitive amplification and the other for a transresistance readout architecture.
· Development of a low-power pH sensor, based on smart textiles, to be used as a sweat pH wearable sensor for fitness and wellness applications or as an environmental monitor.
· Real-time body motion tracking using a Zigbee based body sensors network of inertial modules.
· Study and characterization of a system-on-chip for biopotential measurements.
· Development of a Li-ion battery wireless recharge system for wearable medical devices.
1) V. Re, “3D vertical integration technologies for advanced semiconductor radiation sensors and readout electronics", proceedings of the 4th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 28-29 June 2011, pp. 33-36.
2) Traversi G, Gaioni L, Manghisoni M, Ratti L, Re V, “2D and 3D CMOS MAPS with high performance pixel-level signal processing”, Nucl. Instrum. Methods, vol. 628, p. 212-215, doi: 10.1016/j.nima.2010.06.320.
3) G. TRAVERSI, L. GAIONI, M. MANGHISONI, L. RATTI, V. RE , “A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0”, JOURNAL OF INSTRUMENTATION, doi: 10.1088/1748-0221/6/01/C01010.
4) L. Ratti, L. Gaioni, M. Manghisoni, V. Re, G. Traversi, “Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging”, Nucl. Instrum. Methods, vol. 652, p. 630-633, doi: 10.1016/j.nima.2010.09.084.
6) Manazza, L. Gaioni, M. Manghisoni, L. Ratti, V. Re, G. Traversi, S. Zucca: “Vertical integration approach to the readout of pixel detectors for vertexing applications”, 2011 IEEE Nuclear Science Symposium Conference Record, Valencia (Spain), October 23 – 29, 2011, pp. 641-647.
7) M. Manghisoni, L. Gaioni, L. Ratti, V. Re, G. Traversi: “Analog design criteria for high granularity detector readout in the 65 nm CMOS technology”, 2011 IEEE Nuclear Science Symposium Conference Record, Valencia (Spain), October 23 – 29, 2011, pp. 1961-1965.
10) V. Re, M. Manghisoni, G. Traversi, et al, “The SuperB silicon vertex tracker”, Nucl. Instrum. Methods, vol. 636, p. S168–S172, doi: 10.1016/j.nima.2010.04.104.

References: V. 
 V. 
 V. 
 V. 
 V. 
 V.