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Khalid H. Abed and R. E. Siferd, ``CMOS VLSI Implementation of a Low-Power Logarithmic Converter,” IEEE Transactions on Computers, vol. 52, no. 11, pp. 1421-1433, Nov. 2003.
Khalid H. Abed and R. E. Siferd, ``VLSI Implementation of a Low-Power Antilogarithmic Converter,” IEEE Transactions on Computers, vol. 52, no. 9, pp. 1221-1228, Sept. 2003.
Khalid H. Abed and R. E. Siferd, ``CMOS VLSI Implementation of 16-bit Logarithm and Anti-logarithm Converters,” Proceedings of the 43rd IEEE Midwest Circuits and Systems, 2000, vol. 2, pp. 776-779, Aug. 2000.
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F. Albu, Jiri Kadlec, Nick Coleman and Anthony Fagan, ``The Gauss-Seidel Fast Affine Projection Algorithm,” Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '02), pp. 109-114, San Diego, 16-18 Oct. 2002.
F. Albu, C. Paleologu and S. Ciochina, ``Analysis of LNS Implementation of the QRD-LSL Algorithms,” Proceedings of the International Symposium on Communications Systems, Networks and Digital Signal Processing (CSNDSP'02), pp. 364-367, Staffordshire, UK, 15-17 July 2002.
F. Albu, J. Kadlec, A. Fagan, A. Hermanek and N. Coleman, ``Analysis of the LNS Implementation of the Fast Affine Projection Algorithms,” Proceedings of ISSC 2002, pp. 251-255, Cork, Ireland, June 2002.
F. Albu, Jiri Kadlec, Nick Coleman and Anthony Fagan, ``Pipelined Implementations of the A Priori Error-Feedback LSL Algorithm Using Logarithmic Number System,” Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 2002, vol. 3, pp. 2681-2684, Orlando, Florida, 13-17 May 2002.
Felix Albu, Jiri Kadlec and J. Nick Coleman Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic, Research Report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.
Felix Albu, Jiri Kadlec and J. N. Coleman, ``Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic,” 5th WSES Multiconference on Circuits, Systems, Communications & Computers (CSCC 2001), pp. 517-521, Rethymno, Greece, 2001.
Felix Albu, Jiri Kadlec, R. Matousek, A. Hermanek and J. Nick Coleman, A Comparison of FPGA Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic, Research Report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.
M. H. Andoyer, ``Tables Fondamentales pour les Logarithmes d'Addition et de Soustraction,” Bulletin Astronomique, vol. 2, pp. 5-32, 1922.
Mark G. Arnold, and Sylvain Collange, ``The Denormal Logarithmic Number System", 24th International Conference on Application Specific Systems, Architectures and Processors, Washington, DC, June 2013.
M.G. Arnold, ``Improved DNA-sticker Arithmetic: Tube-encoded-carry, Logarithmic Number System and Monte-Carlo methods," Natural Computing, Vol. 12, no. 2, pp. 235-246, 2013.
M.G. Arnold, ``An Improved DNA-Sticker Addition Algorithm and Its Application to Logarithmic Arithmetic," 17th International Conference on DNA Computing, Pasadena, LNCS, vol. 6937, pp. 34-48, Sept. 2011.
M. Arnold, S. Collange, D. Defour, ``Implementing LNS Using Filtering Units of GPUs," Proceedings of the IEEE International Conference on Acoustics, Speech, Signal Processing, pp. 1542-1545, Dallas, Texas, 14 March 2010.
Mark G. Arnold and Sylvain Collange, ``A Dual-Purpose Real/Complex Logarithmic Number System ALU,” IEEE Symposium on Computer Arithmetic, pp. 15-24, Portland, Oregon, 8 June 2009.
Mark G. Arnold and Panos Vouzis, ``A Serial Logarithmic Number System ALU,” EuroMicro Digital System Design DSD, pp. 151-156, Lubeck, Germany, 29 Aug. 2007.
Mark G. Arnold, ``A RISC Processor with Redundant LNS Instructions,” EuroMicro Digital System Design DSD, pp. 475-482, Dubrovnik, Croatia,1 Sept. 2006.
Mark G. Arnold, ``Approximating Trigonometric Functions with the Laws of Sines and Cosines Using the Logarithmic Number System,” EuroMicro Symposium on Digital Systems Design, pp. 48-53, Porto, Portugal, Aug. 30 - Sept. 3 2005.
Mark G. Arnold and P. Leong, ``Logarithmic Arithmetic for N-body Simulation,” Proceedings of the Work- in-Progress Session of 31st EuroMicro Conference, Porto, Portugal, pp. 24-25, Porto, Portugal, Sept. 3 2005.
M. Arnold and J. Ruan, ``Bipartite Implementation of the Residue Logarithmic Number System,” International Symposium on Optical Science and Technology SPIE Annual Meeting, pp. 196-205. San Diego, Aug. 2005.
Mark G. Arnold, ``The Residue Logarithmic Number System: Theory and Implementation,” 17th International Symposium on Computer Arithmetic, pp. 196-205, Cape Cod, MA, 27-29 June 2005.
Mark G. Arnold, ``LPVIP: A Low-power ROM-Less ALU for Low-Precision LNS,” 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS 3254, pp. 675-684, Santorini, Greece, 15-17 Sept. 2004.
Mark G. Arnold, ``Redundant Logarithmic Arithmetic for MPEG Decoding,” International Symposium on Optical Science SPIE Annual Meeting 2004, Denver, Colorado, 2-6 Aug. 2004.
M. G. Arnold, “Geometric-Mean Interpolation for Logarithmic Number Systems,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), vol. 2, pp. 433-436, Vancouver, Canada, 23-26 May 2004.
M. Arnold, T. Bailey, J. Cowles and C. Walter, ``Fast Fourier Transform Using the Complex Logarithmic Number System,” Journal of VLSI Signal Processing, vol. 33, no. 3, pp. 325-335, 2003.
M. G. Arnold, J. Garcia and M. Schulte, ``The Interval Logarithmic Number System,” 16th IEEE International Symposium on Computer Arithmetic(ARITH-16'03), pp. 253-261, Santiago de Compostela, Spain, 15-18 June 2003.
Mark Arnold, ``Asymmetric and Compressed Logarithmic Number Systems for a Multimedia Coprocessor,” Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers, pp. 1426-1430, Pacific Grove CA, 9-12 Nov. 2003.
Mark Arnold, ``A VLIW Architecture for Logarithmic Arithmetic,” Proceedings of the EuroMicro Digital System Design (DSD'03), pp. 294-302, Antalya, Turkey, 1-6 Sept. 2003.
Mark G. Arnold, ``Iterative Methods for Logarithmic Subtraction,” The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), pp. 315-325, Hague, Netherlands, 24-26 June 2003.
Mark G. Arnold, ``Avoiding Oddification to Simplify MPEG-1 Decoding with LNS,” IEEE International Workshop on Multimedia Signal Processing, St. Thomas, Virgin Islands, Dec. 2002.
M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Error Analysis of the Kmetz/Maenner Algorithm,” Journal of VLSI Signal Processing, vol. 33, pp. 37-53, Oct. 2002.
Mark G. Arnold, ``LNS for Low-Power MPEG Decoding,” Proceedings of SPIE Advanced Signal Processing, Architectures and Implementations XII, vol. 4791, pp. 369-380, Seattle, Washington, 9-1 July 2002.
Mark G. Arnold, ``Reduced Power Consumption for MPEG Decoding with LNS,” The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), pp. 65-75, San Jose, CA, 17-19 July 2002.
Mark G. Arnold, Logarithmic Number Systems for MPEG and Multimedia Applications, PhD thesis, University of Manchester Institute of Science and Technology, 2002.
Mark G. Arnold, ``An Improved Cotransformation for Logarithmic Subtraction,” Proceedings of the International Symposium on Circuits and Systems (ISCAS'02), pp. 752-755, Scottsdale, Arizona, 26-29 May 2002.
Mark G. Arnold, ``Slide Rules for the 21st Century: Logarithmic Arithmetic as a High-speed, Low-cost, Low-power Alternative to Fixed Point Arithmetic,” Second Online Symposium for Electronics Engineers, 2001.
Mark G. Arnold, Thomas A. Bailey, John R. Cowles and Colin Walter, ``Analysis of Complex LNS FFTs,” Francky Catthoor and Marc Moonen, editors, Proceedings of Signal Processing Systems SIPS 2001: Design and Implementation, pp. 58-69, Antwerp, Belgium, 26-28 Sept. 2001. IEEE Press.
Mark G. Arnold, ``Design of a Faithful LNS Interpolator,” Proceedings of the EuroMicro Digital System Design (DSD'01), pp. 336-345, Warsaw, Poland, 4-6 Sept. 2001.
Mark G. Arnold and Mark D. Winkel, ``A Single-Multiplier Quadratic Interpolator for LNS Arithmetic,” Proceedings of the 2001 International Conference on Computer Design (ICCD'01), pp. 178-183, Austin, Texas, 23-26 Sept. 2001.
M. Arnold and M. Winkel, ``Reconfiguring an FPGA-based RISC for LNS Arithmetic,” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, Proceedings of SPIE, vol. 4525, pp. 88-98, Denver, 21-22 Aug. 2001.
Mark G. Arnold and C. Walter, ``Unrestricted Faithful Rounding is Good Enough for Some LNS Applications,” Proceedings of the 15th International Symposium on Computer Arithmetic, pp. 237-246, Vail, Colorado, 11-13 June 2001.
Mark G. Arnold, ``A Pipelined LNS ALU,” IEEE Workshop on VLSI, Orlando, Florida, 19-20 April 2001.
Mark Arnold, Colin Walter and Freddy Engineer, ``Verilog Transcendental Functions for Numerical Testbenches,” Proceedings of the 10th International HDL Conference, Santa Clara, California, 1 March 2001.
M. G. Arnold, F. N. Engineer and M. D. Winkel, ``AWE: The ARM Workalike Experiment,” WESTCON, San Jose, California, 21 Oct. 1999. www.cs.uwyo.edu/~marnold/awe.html.
M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems,” IEEE Transactions on Computers, vol. 47, no. 7, pp. 777-786, July 1998.
M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems,” Proceedings of the 13th IEEE Symposium on Computer Arithmetic(ARITH-13), pp. 190-197, Asilomar, California, 6-9 July 1997.
M. G. Arnold, T. A. Bailey, J. J. Cupal and M. D. Winkel, ``On the Cost Effectiveness of Logarithmic Arithmetic for Back-Propagation Training on SIMD Processors,” Proceedings of the 1997 International Conference on Neural Networks, vol. 2, pp. 933-936, Houston, Texas, 9-12 June 1997.
M. G. Arnold, Method and Apparatus for Fast Logarithmic Addition and Subtraction, United States Patent 5,337,266, 9 Aug. 1994.
M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Applying Features of IEEE 754 to Sign/Logarithm Arithmetic,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 1040-1050, Aug. 1992.
M. Arnold, T. Bailey and J. Cowles, ``Comments on `An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System’,” IEEE Transactions on Computers, vol. 41, no. 6, pp. 786-788, June 1992.
M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Initializing RAM-based Logarithmic Processors,” Journal of VLSI Signal Processing, vol. 4, no. 2-3, pp. 243-252, May 1992.
M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Implementing Back-Propagation Neural Nets with Logarithmic Arithmetic,” Proceedings of the International AMSE Conference Neural Networks, vol. 1, pp. 75-86, San Diego, California, May 1991.
M. G. Arnold, T. A. Bailey, J. R. Cowles and J. J. Cupal, ``Redundant Logarithmic Arithmetic,” IEEE Transactions on Computers, vol. 39, no. 8, pp. 1077-1086, Aug. 1990.
M. Arnold, T. Bailey, J. Cowles and J. Cupal. ``Redundant Logarithmic Number Systems,” Proceedings of the 9th Symposium on Computer Arithmetic, pp. 144-157, Santa Monica, CA, 6-8 Sept. 1989.
M. G. Arnold, T. A. Bailey and J. R. Cowles, ``Improved Accuracy for Logarithmic Addition in DSP Applications,” Proceedings of the IEEE International Conference on Acoustics, Speech, Signal Processing, vol. 3, pp. 1714-1717, 1988.
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L. G. Bleris, P. D. Vouzis, J. G. Garcia, M. G. Arnold and M. V. Kothare, ``Pathways for Optimization-Based Drug Delivery,” Control Engineering Practice Journal, Special Issue for ADCHEM Symposium, vol. 15, no. 10, pp 1280-1291, Oct. 2007.
L. Bleris, J. G. Garcia and M. G. Arnold and M. V. Kothare, ``Model Predictive Hydrodynamic Regulation of Microflows,” Journal of Micromechanics and Microengineering, vol. 16, pp. 1792-1799, July 2006.
L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``A Co-Processor FPGA Platform for the Implementation of Real-Time Model Predictive Control,” American Control Conference (ACC-06), Minneapolis, Minnesota, 14 June 2006.
L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``Pathways for Optimization-Based Drug Delivery Systems and Devices,” International Symposium on Advanced Control of Chemical Processes (ADCHEM-06), Gramado, Brazil, 2 April 2006.
L. Bleris, J. G. Garcia and M. G. Arnold and M. V. Kothare, ``Towards Embedded Model Predictive Control for System-on-a-Chip Applications,” Journal of Process Control, vol. 16, no. 3, pp. 255-264, March 2006.
Leonidas Bleris, Mayuresh V. Kothare, Jesus Garcia and Mark G. Arnold, ``Embedded Model Predictive Control for System-On-a-Chip Applications,” Proceedings of the 7th International Symposium on Dynamics and Control of Process Systems, Boston, July 2004.
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