Source: https://www.scribd.com/document/127801645/MKW22D512V-Data-Sheet-Rev0
Timestamp: 2019-04-26 06:38:29+00:00

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The MKW22D512 device consists of two separate ICs: a 2.4 GHz transceiver and a microcontroller. The MCU is done in the 90 nm thin film storage (TFS) process, is built from the Kinetis platform and is part of the Kinetis portfolio. The transceiver is built using a 180 nm process. The primary target for the MKW22D512V portfolio is to meet the higher performance requirements of ZigBee Pro and ZigBee IP based applications, especially Smart Energy and Commercial Building Automation. This product is a cost-effective solution that matches or exceeds competitive solutions. The following content describes the MKW22D512V. The MKW22D512V portfolio consist of a system on chip for the IEEE® 802.15.4 standard that incorporates a complete, low power, 2.4 GHz 802.15.4 compliant radio frequency transceiver and a Kinetis family low power, mixed-signal ARM® eCortex™- M4 MCU, with a functional set of MCU peripherals integrated into a single package.
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2012. All rights reserved.
This section provides a simplified block diagram and highlights MKW22D512V features.
Figure 1 shows a simplified block diagram of the MKW22D512V, which is an IEEE®802.15.4 standard compatible transceiver.
1 Joint Test Action Group (JTAG) – IEEE 1149. store data. 0 Freescale Semiconductor 5 .7 compact JTAG (cJTAG) – Trace port interface unit (TPIU) – Flash patch and breakpoint (FPB) – Data watchpoint and trace (DWT) – Instrumentation trace macrocell (ITM) – Enhanced Trace Macrocell (ETM) System and power management — Software and hardware watchdog with external monitor pin — DMA controller with 16 channels — Low-leakage wake-up unit (LLWU) — Power management controller with 10 different power modes — Non-maskable interrupt (NMI) — 128-bit unique identification (ID) number per chip Clocks — Multi-purpose clock generator – PLL and FLL operation – Internal reference clocks (32 kHz or 2 MHz) — Three separate crystal oscillators – 3 MHz to 32 MHz crystal oscillator for MCU – 32 kHz to 40 kHz crystal oscillator for MCU or RTC – 32 MHz crystal oscillator for Radio — Internal 1 kHz low power oscillator — DC to 50 MHz external square wave input clock Memories and Memory Interfaces — FlexMemory consisting of FlexNVM (non-volatile flash memory that can execute program code.• • • • Core features — Next generation 32-bit ARM Cortex-M4 core — Supports DSP instructions — Nested vectored interrupt controller (NVIC) — Asynchronous wake-up interrupt controller (AWIC) — Debug and trace capability – 2-pin serial wire debug (SWD) – IEEE 1149. and also accelerates flash programming) — Flash security and protection features — Serial flash programming interface (EzPort) MKW22D512V Product Electrical Specification. Rev. or backup EEPROM data) or FlexRAM (RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage.
The radio receiver path is based upon a near zero IF (NZIF) architecture incorporating front end amplification.5 kbps — Modulation: OQPSK Receiver sensitivity: –102 dBm. This provides a highly accurate clock source based on the transceiver reference oscillator. typical (@1% PER for 20 byte payload packet) Differential bidirectional RF input/output port with integrated transmit/receive switch Programmable output power from –30 dBm to +10 dBm. demodulated and digitally processed. then the frequency will be 4 MHz (32 MHz/8). These signals designated ANT_A.2 RF interface and usage The MKW22D512V RF output ports are bidirectional (diplexed between receive/transmit modes) and differential enabling interfaces with numerous off-chip devices such as a balun.2.The CLK_OUT pin will be enabled upon POR. The clock is programmable over a wide range of frequencies divided down from the reference 32 MHz (see Table 3). In addition. and TX_SWITCH when enabled are switched via an internal hardware state machine.1 Transceiver functions Receive path The receive path has the functionality to operate in run state or operate in a low power run state (LPRS) that can be considered as a partial power down mode. These ports provide control features for peripheral devices such as: • Antenna diversity modules • External PAs • External LNAs • T/R switched 3. If this pin is low upon POR. 3.• • • — Data rate: 250 kbps — Symbol rate: 62. 0 Freescale Semiconductor 7 .3 3.3. this device provides an interface to directly connect between a single-ended antenna with MKW22D512V RF ports. ANT_B. MKW22D512V provides four output driver ports that can have both drive strength and slew rate configured to control external peripheral devices. If this pin is high upon POR (upon POR GPIO5 has a pullup resistor) then the frequency will be 32. The RF front end (FE) input port is differential that shares the same off chip matching network with the transmit path.1 Clock output feature The CLK_OUT digital output can be enabled to drive the system clock to the MCU. The frequency CLK_OUT will be determined by the state of the GPIO5/BOPT pin. MKW22D512V Product Electrical Specification. 3.78689 kHz (32 MHz/976). RX_SWITCH. When using a balun. Rev. one(1) mixed signal down conversion to IF that is programmably filtered.
3. 3.4 signal transmitting at the frequency band that an 802.1 CCA mode 1 CCA mode 1 has two functions: • To estimate the energy in the received baseband signal. • CCA mode 3 is asserted if either CCA mode 1 or CCA mode 2 is asserted. Whether the detected energy is strong or not is not important for CCA mode 2.4 standard is implemented using a logical combination of CCA mode 1 and CCA mode 2.4 transmitter intends to transmit.15.3 CCA mode 3 CCA mode 3 as defined by 802. and link quality indicator (LQI) MKW22D512V supports three clear channel assessment (CCA) modes of operation to include energy detection (ED) and link quality indicator (LQI). 3.3.This energy is estimated based on receiver signal strength indicator (RSSI). the modulated buffered signal is then routed to a multi-stage amplifier for transmission. coarse and fine tuning is executed within the Frac-N PLL to engage signal lock. 0 8 Freescale Semiconductor . CCA mode 3 operates in one of two operating modes: • CCA mode 3 is asserted if both CCA mode 1 and CCA mode 2 are asserted.2 CCA mode 2 CCA mode 2 detects whether there is any 802.15.3. 3.15. From the definition of CCA mode 2 in the 802.3.3. After signal lock is established.2 Transmit path MKW22D512V transmits OQPSK modulation having power and channel selection adjustment per user application. • To determine whether the energy is greater than a threshold. 3. Rev. This mode setting is available through a programmable register. Functionality for each of these modes is provided in the sections that follow.3.3. the requirement is to detect an 802. The differential signals at the output of the PA (RFOUTP. RFOUTN) are converted as single ended (SE) signals with off chip components as required.3. MKW22D512V Product Electrical Specification.15. The estimate of the energy can also be used as the Link Quality metric.3. MKW22D512V warms up from Idle to Receive mode where RSSI (Receiver Signal Strength Indicator) averaging takes place right after 170µs of receiver warm-up. energy detection (ED).4 standard.15. After the channel of operation is determined.4 complied signal. Specifically.3 Clear channel assessment (CCA). In CCA Mode 1.
15. The magnitude from this measurement is calculated from the digital RSSI value that is averaged over an 128 s duration. including reserved types Supports all valid 802.4 Packet processor The MKW22D512V packet processor performs sophisticated hardware filtering of the incoming received packet.4 frame lengths Enables auto-Tx acknowledge frames (no MCU intervention) by parsing of frame control field and sequence number Supports all source and destination address modes.and rules-checking Allows frame type-specific filtering (e. Supports Dual PAN mode.3. This setting is executed through a register bit where the final LQI value is available 64 s after preamble is detected.g. LQI computations for MKW22D512V are based on either digital RSSI or correlator peak values.and MAC-compliant. 3. and if the device is a PAN coordinator. 3.or rules-checking. whether a message is pending for the sending device. RSSI measurement is done during normal packet reception. is based on receiver signal strength indicator (RSSI) or correlator output for the 802.3. 3. whether the packet is addressed to this device. allowing the device to exist on 2 PAN’s simultaneously Supports 2 IEEE addresses for the device MKW22D512V Product Electrical Specification. to receive all packets regardless of address.5 Link quality indicator (LQI) Link quality indicator (LQI). and also PAN ID compression Supports broadcast address for PAN ID and short address mode Supports “promiscuous” mode. The packet processor greatly reduces the packet filtering burden on software. If a continuous update of LQI based on RSSI throughout the packet is desired. energy detect (ED) is an average value of signal strength.1 • • • • • • • • • • • • • • • • Features Aggressive packet filtering to enable long.3.3.4. 0 Freescale Semiconductor 9 . to determine whether the packet is both PHY. it can be read in a separate 8-bit register by enabling continuous update in a register bit.15..4 Energy detection (ED) Energy detection (ED) is based on receiver signal strength indicator (RSSI) and correlator output for the 802. uninterrupted MCU sleep periods Fully compliant with both 2003 and 2006 versions of the 802. In this mode. allowing software to tend to higher-layer tasks with a lower latency and smaller software footprint.15.4 wireless standard Supports all frame types.4 standard.3.3.3.4 standard. Rev. reject all but beacon frames) Supports SLOTTED and non-SLOTTED modes Includes special filtering rules for PAN coordinator devices Enables minimum-turnaround Tx-acknowledge frames for data-polling requests by automatically determining message-pending status Assists MCU in locating pending messages in its indirect queue for data-polling end devices Makes available to MCU detailed status of frames that fail address.15.
These parameters are described in Table 2. Hardware support for Dual PAN operation consists of two (2) sets of PAN and IEEE addresses for the device. MKW22D512V represents a high-performance SoC that includes hardware support for a device to reside in two networks simultaneously.4 packets Same buffer serves both TX and RX sequences The entire Packet Buffer can be uploaded or downloaded in a single SPI burst. but will not inhibit TX content loading of the packet buffer via the SPI. two (2) sets of network parameters are maintained. software stores the contents of the packet buffer starting with the frame length byte at packet buffer address 0. Entire packet buffer can be accessed in hibernate mode Under-run error interrupt supported 3. There are control bits to configure and enable Dual PAN mode and read only bits to monitor status in Dual PAN mode.15. For receive packets.1 • • • • • • • Features 128 byte buffer stores maximum length 802. Usage of the packet buffer for RX and TX sequences is on a time-shared basis. 3.4 packet contents for both TX and RX sequences. PAN0 and PAN1. This facilitates DMA transfer through the SPI. Automatic address auto-incrementing for burst accesses Single-byte access mode supported. This will block RX packet overwriting. a programmable timer to automatically switch PANs (including on-the-fly channel changing) without software intervention.15. For TX sequences. two (2) different channels (one for each PAN). For the purpose of defining PAN in the content of Dual PAN mode. both networks.• Supports active promiscuous mode 3. A device can be configured to be a PAN coordinator on either network. the device alternates between the two (2) PANs under hardware or software control. followed by the packet contents at the subsequent packet buffer addresses.4 and ZigBee applications allowed a device to associate to one and only one PAN (Personal Area Network) at any given time. Software can inhibit receive-packet overwriting of the packet buffer contents by setting the PB_PROTECT bit. 0 10 Freescale Semiconductor . receive packet data will overwrite the contents of the packet buffer. Software will read this register to determine the number of bytes of packet buffer to read.5. radio transceivers designed for 802.3. an LQI byte is stored at the byte immediately following the last byte of the packet (frame length +1).4 Dual PAN ID In the past. In optional Dual PAN mode. external to the packet buffer. MKW22D512V Product Electrical Specification. PAN0 and PAN1 will be used to refer to the two (2) PANs where each parameter set uniquely identifies a PAN for Dual PAN mode.15. Rev. or neither.5 Packet buffering The packet buffer is a 128-byte random access memory (RAM) dedicated to the storage of 802.3. For RX sequences the incoming packet’s frame length is stored in a register.
Rev. or CCA/ED operation. software will program both parameter sets to configure the hardware for operation on two (2) networks. 0 Freescale Semiconductor 11 . PHY_FRAC1) MacPANID1 (16-bit register) MacShortAddrs1 (16-bit register) MacLongAddrs1 (64-bit registers) PANCORDNTR1 (1-bit register) During device initialization if Dual PAN mode is used.Table 2. RX. PHY_FRAC0) MacPANID0 (16-bit register) MacShortAddrs0 (16-bit register) MacLongAddrs0 (64-bit registers) PANCORDNTR0 (1-bit register) PAN1 Channel1 (PHY_INT1. programmable power modes available are: • Receiver modes of operation: — RX preamble search — RX Preamble search sniff — X FAD Preamble search — RX packet decoding • The RF section of the radio only powered-up as required to do a TX.2 Power management The MKW22D512V power management is controlled through programming the modes of operation.1 Modes of operation The transceiver modes of operation include: • Idle mode • Doze mode • Low power (LP) / hibernate mode • Reset / powerdown mode • Run mode 4. 4. 4 System and power management The MKW22D512V is a low power device that also supports extensive system control and power management modes to maximize battery life and provide system protection. MKW22D512V Product Electrical Specification. For the receiver. Different modes allow for different levels of power-down and RUN operation. PAN0 and PAN1 descriptions PAN0 Channel0 (PHY_INT0.
5 Radio Peripherals The MKW22D512V provides a set of I/O pins useful for suppling a system clock to the MCU. There will also be one (1) bit available to adjust the CLK_OUT I/O pad drive strength. The transceiver CLK_OUT pin is internally connected to the MCU EXTAL pin so that no external connection is needed to drive the MCU clock. SCLK. to be serialized and shifted out to external hardware for further processing. 0 12 Freescale Semiconductor . CLK_OUT table CLK_OUT_DIV [2:0] 0 1 2 3 4 5 6 7 CLK_OUT frequency 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 62. • Aggressive clock gating in the XTAL domain to minimize dynamic current consumption based on the power mode selected.5 kHz 32. 5.2 Bit streaming mode (BSM) Another peripheral option is bit streaming mode that when activated allows all 802. A simple development system can be crafted to consume the BSM outputs and generate packet trace data for MKW22D512V Product Electrical Specification. 5.786 kHz DEFAULT if GPIO5/BOPT=1 DEFAULT if GPIO5/BOPT=0 Comments There is an enable and disable bit for CLK_OUT. the clock output will optionally continue to run for 128 clock cycles after disablement. Rev. controlling external RF modules/circuitry. • Built in synchronization at all clock domain crossings. received or transmitted. SDM_CK). In addition.1 Clock output (CLK_OUT) MKW22D512V integrates a programmable clock to source numerous frequencies for connection with various MCUs.15. When disabling. Package pin 39 can be used to provide this clock source as required allowing the user to make adjustments per their application requirement. there is a special option for streaming the digital packet data for external monitoring (BSM). Additional functionality this feature supports is: • 3 clock domains (XTAL.4 packet data. Care must be taken that the clock output signal does not “talk” or interfere with the reference oscillator or the radio. and GPIO. • XTAL domain can be completely gated off (hibernate mode) • SPI communication allowed in hibernate • Single-clock domain in scan mode Table 3.
BSM_DATA and BSM_FRAME are synchronous to BSM_CLK.15. Signaling is provided on BSM_FRAME to indicate start-of-packet and end-of-packet and to discriminate between TX and RX packet types. capability. Pin configuration will be executed by software to adjust input/output direction and drive strength. BSM uses a simple synchronous 3-wire interface consisting of BSM_CLK.4 bit rate (250 kHz). BSM requires no software support while the mode is engaged. 0 Freescale Semiconductor 13 . there will be specific settings required per use case. which depending on the battery can vary from 1.3 General-purpose input output (GPIO) MKW22D512V embedded transceiver supports up to 8 GPIO pins where all I/O pins will have the same supply voltage. Aside from controlling this bit. so that the pins are available for general-purpose use when BSM is disabled. 5. BSM_DATA.4 traffic appearing on a network within the range of the MKW22D512V device allowing for PAN-level monitoring and debugging. BSM_DATA and BSM_ FRAME are shifted out on the falling BSM_CLK and intended to be captured on rising BSM_CLK. and BSM_ FRAME outputs. When a die pin is configured as a general-purpose input or for peripheral use.6 V. software (see Table 4) can enable a pull-up or pull-down device. Packet data is shifted out serially at the 802.8 V up to 3. BSM when engaged will not measurably increase current consumption because the hardware (including the external I/O) operates at the 250 kHz rate. A single shift register control bit activates or deactivates BSM.all 802. it is merely a monitoring tool. BSM outputs are multiplexed with GPIO. Immediately after reset. BSM does not interfere with packet processing or transmit data handling in any way. Rev. all pins are configured as high-impedance general-purpose inputs with “internal pull-up or pull-down devices enabled”. When a die pin is configured as a general-purpose output or for peripheral use.15. Features for these pins include: • Programmable output drive strength • Programmable output slew rate • Hi-Z mode • Programmable as outputs or inputs (default) • Pins shared with BSM mode outputs MKW22D512V Product Electrical Specification. Not all 8 are available on the MKW22D512V.
5 V from the rail reference VOH or VOL. Most SPI access types require only a single-byte control word. except Reset. Rev. The SPI interface is asynchronous to the rest of the IC. the output voltage will not deviate more than 0. Write and read access to the Packet buffer can also be single-byte. The SPI is a slave-only interface. reducing SPI access latency to a minimum. No relationship between R_SCLK and MKW22D512V’s internal oscillator is assumed. and IC-to-SPI (register reads). — — 10 6 6 24 24 11 11 50 50 mA mA nA ns ns ns ns ns ns ns ns — — — 2 2 6 6 — — — — No slew. 0 14 Freescale Semiconductor . slew Propagation delay. Write and read access to both direct and indirect registers is supported. The SPI is capable of operation in all power modes. the contents of the IRQSTS1 register (MKW22D512V’s highest-priority status register) are MKW22D512V Product Electrical Specification. slew 1 2 3 4 5 6 7 Rise and fall time Rise and fall time Rise and fall time Full drive6 Partial drive7 Full drive Partial drive For this drive condition. partial drive Propagation delay5. The SPI design features a compact. and transfer length can be single-byte. full drive Slew. Partial drive values provided are in reference to a 15 pF load. R_SCLK and R_MOSI. the output voltage will not deviate more than 0. partial drive Slew. And no relationship between R_SCLK and the CLK_OUT pin is assumed.Table 4.1 Serial peripheral interface (SPI) MKW22D512V’s SPI interface allows an MCU to communicate with MKW22D512V’s register set and packet buffer. single-byte control word. the MCU must drive R_SSEL_B. no slew Propagation delay. no slew Propagation delay. Source or sink Source or sink Off state Rise and fall time 4 Units Typ. 10 2 — 4 4 12 12 — — — — Max. with the address embedded in the control word. For this drive condition. All synchronization of the SPI interface to the IC takes place inside the SPI module. During control word transfer (the first byte of any SPI access). full drive No slew. 5.3. or bursts of unlimited length. especially during the register-initialization phase of the IC. or a burst mode of unlimited length. Pin configuration summary Tolerance Pin function configuration I/O buffer full drive mode1 I/O buffer partial drive mode2 I/O buffer high impedance3 Details Min. Rise and fall time values in reference to 20% and 80% Propagation Delay measured from/to 50% voltage point.5 V from the rail reference VOH or VOL. Full drive values provided are in reference to a 75 pF load. SPI synchronization takes place in both directions: SPI-to-IC (register writes). Operation in hibernate mode allows most MKW22D512V registers and the complete packet buffer to be accessed in the lowest-power operating state enabling minimal power consumption. Leakage current applies for the full range of possible input voltage conditions.
Rev. the FAD block will select the first antenna on which the received signal has a correlation factor above a predefined progammable threshold. The period ta is required to allow for the external module control circuitry to turn on/off to select the antenna.2 Antenna diversity To improve the reliability of RF connectivity to long range applications. and 47) by direct register antenna selection. Automatic address auto-incrementing for burst accesses The entire packet buffer can be uploaded or downloaded in a single SPI burst. 0 Freescale Semiconductor 15 . enabling multi-slave configurations 5. can be accessed in hibernate mode Built-in synchronization inside the SPI module to/from the rest of the IC. R_MISO can be tristated when SPI inactive. 45. so that the MCU gets access to IRQSTS1. and most registers. Operationally. 46. ta = 8 s. FAD’s operation covers less than four s0 symbols before the antenna that is selected allowing the symbol demodulator to detect at least four s0 symbols before declaring “Preamble Detect”. 6 MKW22D512V operating modes The radio has these 6 operating modes: • Reset / power down • Low power (LP) / hibernate • Dz o e MKW22D512V Product Electrical Specification. then antenna monitoring is switched to the second antenna. supported by all MCUs SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses). the antenna diversity feature is supported without using the MCU through use of four dedicated control pins (package pins 44. The first antenna is monitored for a period equal to 1 symbol. ts + ta = 24 s that will allow enough time to test both antennas within the first 4 preamble symbols. on every SPI access. The digital regulator supplies bias to analog switches that can be programmed to sink and source current or operate in a high impedance mode. with the minimum possible latency. 5.always shifted out. tfad = 3 x ta + 2 x ts = 56 s. when enabled. FAD will continue to switch between the two antennas until one is found that has a sufficiently strong detected signal. will allow the choice of selection between two antennas during the preamble phase.1. By continually monitoring the received signal. Write and read access to all Coconino registers (direct and indirect) Write and read access to packet buffer SPI accesses can be single-byte or burst. The FAD accomplishes the antenna selection by sequentially switching between the two antennas testing for the presence of a suitably strong signals/symbols where the first antenna to reach this condition is then selected for the reception of the packet.3. SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses). Fast antenna diversity (FAD) mode supports this radio feature and. ts = 16 s.1 • • • • • • • • • • • Features 4-wire industry standard interface. thus tfad < 4 x ts < 64 s.3. Entire packet buffer.
Crystal reference oscillator on. Crystal reference oscillator on with CLK_OUT output available.• • • (low power with reference oscillator active) Idle Receive Transmit Table 5. Radio mode definitions and transition times Table 5 lists and describes these modes.7 V. Rev. Mode Definition Current consumption1 < 30 nA < 1 A 600 A (no clockout) 700 A (no clockout) 15 mA 2 15 mA 3 Transition time to or from idle TBD TBD TBD TBD TBD TBD Reset / All IC functions off. Crystal reference oscillator on. MCU power modes MKW22D512V Product Electrical Specification. Transmitter on. 0 16 Freescale Semiconductor .) hibernate Doze Idle Receive Transmit 1 2 Crystal reference oscillator on but CLK_OUT output available only if selected. (SPI is functional. Receiver on. nominal process @ 25C Signal sensitivity = –102 dBm 3 RF output = 0 dBm The MCU has these radio modes: Table 6. RST asserted. leakage only. powerdown Low power / Crystal reference oscillator off. Conditions: VBAT and VBAT_2 = 2.
0 Freescale Semiconductor 17 . Rev.MKW22D512V Product Electrical Specification.
(no CLOCKOUT) 600 A. 0 18 Freescale Semiconductor .Table 7. Power Modes MCU Mode Stop Stop VLLS1 VLLS0 Run2 Run3 1 Radio Mode Idle Doze Low power / Hibernate Reset / Powerdown Transmit Receive MCU typical current consumption 320 A 320 A 0. typ.6 A <250 nA 12 mA 12 mA Radio typical current consumption 700 A. 32 MHz operation 3 32 MHz operation 2 Table 7 describes alignment of radio and MCU power modes versus current consumption for typical conditions: VBAT / VDD = + 2. typ.7V @ T=25OC MKW22D512V Product Electrical Specification. (no CLOCKOUT) <1 A1 <30 nA 15 mA 15 mA Value does not include SPI activity. Rev.
15.8 2. 0 Freescale Semiconductor 19 .360 –40 0 70% VDDINT — — Typ 2. –55 — Max. Rev. Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.3 Symbol MSL 1 Moisture handling ratings Description Moisture sensitivitiy level Min. 3 Unit — Nots 1 Determined according to IPC/JEDEC Standard J-STD-020.1 MKW22D512V electrical characteristics Recommended operating conditions Table 8. Determined according to IPC/JEDEC Standard J-STD-020.0 10 Unit Vdc GHz C V V MHz dBm 32 MHz only 7. MKW22D512V Product Electrical Specification. 7.7 — 25 — — — — Max 3. — Max.6 2. High Temperature Storage Life. lead-free Min.2 Symbol TSTG TSDR 1 2 Thermal handling ratings Description Storage temperature Solder temperature. 150 260 Unit C C Nots 1 2 Determined according to JEDEC Standard JESD22-A103. VDDINT fin TA VIL VIH fSPI Pmax fref Min 1. Recommended operating conditions Characteristic Power Supply Voltage (VBATT = VDDINT) Input Frequency Ambient Temperature Range Logic Input Voltage Low Logic Input Voltage High SPI Clock Rate RF Input Power Crystal Reference Oscillator Frequency (40 ppm over operating conditions to meet the 802. Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.7 7.4 Standard.480 105 30% VDDINT VDDINT 16.) Symbol VBATT.
8 155 Unit V mA V V mA V V V V V VUSB_DP USB_DP input voltage VUSB_DM USB_DM input voltage VREGIN USB regulator input VBAT 1 RTC battery supply voltage Analog pins are defined as pins that do not have an associated general purpose I/O port function.3 –0. –2000 –500 –100 Max.63 6 3.8 Max. 0 20 Freescale Semiconductor . 3. Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. MKW22D512V Product Electrical Specification. Rev. EXTAL. 2000 500 100 Unit V V mA Nots 1 2 Determined according to JEDEC Standard JESD22-A103.3 –0. High Temperature Storage Life. and XTAL) Analog1. 7. Determined according to IPC/JEDEC Standard J-STD-020.3 –25 VDD – 0.5 Symbol VDD IDD VDIO VAIO ID VDDA Voltage and current ratings Description Digital supply voltage Digital supply current Digital input voltage (except RESET. –0. and XTAL input voltage Maximum current single pin limit (applies to all port pins) Analog supply voltage Min.3 –0. charged-device model Latch-up current at ambient temperature of 105C Min.3 VDD + 0. human body model Electrostatic discharge voltage.3 –0. RESET.7.3 3.63 3.3 — –0.4 Symbol VHBM VCDM ILAT 1 2 ESD handling ratings Description Electrostatic discharge voltage.3 –0. EXTAL.3 25 VDD + 0.
Go to http://www.7. Rev.1 EMC radiated emissions operating behaviors 7.” 7. Perform a keyword search for “EMC design.5. 2.freescale. 0 Freescale Semiconductor 21 .2 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1.3 Capacitance attributes MKW22D512V Product Electrical Specification.5.5.com.
3 to (VDDINT + 0.3) +10 2000 200 750 No damage / latch up to 4000 Vdc No soft failure / reset to 1000 PESD Power Electro-Static Discharge / Indirect Contact No damage / latch up to 6000 Vdc No soft failure / reset to 1000 No damage / latch up to 5 Langer IC / EFT / P201 EFT (Electro Magnetic Fast Transient) No soft failure / reset to 5 No damage / latch up to 300 No soft failure / reset to 150 Junction Temperature Storage Temperature Range TJ Tstg +150 –65 to +165 C C Vdc Unit Vdc Vdc dBm Vdc Vdc Vdc Power Electro-Static Discharge / Direct Contact EMC2 Langer IC / EFT / P201 Vdc NOTE Maximum ratings are those values beyond which damage to the device may occur. VBAT2 Vin Pmax HBM MM CDM Rating level –0.6 –0.8 8.1 MCU Electrical characteristics Maximum ratings Table 9. Maximum ratings Requirement Power Supply Voltage Digital Input Voltage RF Input Power Human Body Model ESD1 Machine Model Charged Device Model Description Symbol VBAT. Rev. Functional operation should be restricted to the limits in the electrical characteristics or recommended operating conditions tables. 1 2 Electrostatic discharge on all device pads meet this requirement Electromagnetic compatibility for this product is low stress rating level MKW22D512V Product Electrical Specification. 0 22 Freescale Semiconductor .3 to 3.
Rev. as shown in the following figure. and — are configured for high drive strength (PORTx_PCRn[DSE]=1) • input pins — have their passive filter disabled (PORTx_PCRn[PFE]=0) MKW22D512V Product Electrical Specification.1 General AC electrical characteristics Unless otherwise specified. — are configured for fast slew rate (PORTx_PCRn[SRE]=0). 0 Freescale Semiconductor 23 .2 8. Input signal measurement reference All digital I/O switching characteristics assume: • output pins — have CL=30pF loads. propagation delays are measured from the 50% to the 50% point.2. and rise and fall times are measured at the 20% and 80% points.8. Figure 2.
MKW22D512V Product Electrical Specification.3V) is observed. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|.1 1 Nonswitching electrical specifications Voltage and current operating requirements 1.2.2. 0 24 Freescale Semiconductor .3V) and VIN is less than VAIO_MAX(=VDD+0. then there is no need to provide current limiting resistors at the pads. Select the larger of these two calculated resistances. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. Rev.2 8. All analog pins are internally clamped to VSS and VDD through ESD protection diodes.2. If VIN is greater than VAIO_MIN (=VSS-0. If these limits cannot be observed then a current limiting resistor is required.8.
3.1V MKW22D512V Product Electrical Specification. 0 Freescale Semiconductor 25 . Rising thresholds are falling threshold + hysteresis voltage. VBAT power operating requirements 8. Rev.8.3 LVD and POR operating requirements 1.
oltage and current operating behaviors 8. Rev. 0 26 Freescale Semiconductor .3.2 Power mode transition operating behaviors All specifications except tPOR. and VLLSx to RUN recovery times in the following table assume this clock configuration: • • • CPU and system clocks = 50 MHz Bus clock = 50 MHz Flash clock = 25 MHz MKW22D512V Product Electrical Specification.
MKW22D512V Product Electrical Specification. 0 Freescale Semiconductor 27 . Rev.
3.3 PPower consumption operating behaviors MKW22D512V Product Electrical Specification.8. 0 28 Freescale Semiconductor . Rev.
0 Freescale Semiconductor 29 . Rev.MKW22D512V Product Electrical Specification.
1 Switching specification Device clock specifications 1. MKW22D512V Product Electrical Specification. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module.4. 0 30 Freescale Semiconductor . Rev.4 8.8.
CMT.4.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO. 0 Freescale Semiconductor 31 . and I2C signals.8. Rev. UART. MKW22D512V Product Electrical Specification.
5. Rev.1 Core modules JTAG electricals Figure 3. 0 32 Freescale Semiconductor . Test clock input timing MKW22D512V Product Electrical Specification.8.5 8.
Figure 4. Test access port timing MKW22D512V Product Electrical Specification. Boundary scan (JTAG) timing Figure 5. 0 Freescale Semiconductor 33 . Rev.
TRST timing MKW22D512V Product Electrical Specification.Figure 6. Rev. 0 34 Freescale Semiconductor .
Rev.8.6 Clock modules MKW22D512V Product Electrical Specification. 0 Freescale Semiconductor 35 .
Rev.MKW22D512V Product Electrical Specification. 0 36 Freescale Semiconductor .
Rev.1 Oscillator electrical specifications MKW22D512V Product Electrical Specification.8.6. 0 Freescale Semiconductor 37 .
1.1 Oscillator frequency specification MKW22D512V Product Electrical Specification.6. 0 38 Freescale Semiconductor .8. Rev.
7.8.1 8.6.1. Rev.6.2 8.2. MKW22D512V Product Electrical Specification.1 Memories and memory interfaces Flash electrical specifications Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.7.2 32 kHz oscillator frequency specifications 8.1 32 kHz oscillator electrical characteristics 32 kHz oscillator DC electrical specifications 8.7 8.2. 0 Freescale Semiconductor 39 .6.
NVM program/erase timing specifications 8. 0 40 Freescale Semiconductor .7.1.2 Flash timing specifications — commands MKW22D512V Product Electrical Specification. Rev.
8. Rev.3 MKW22D512V Product Electrical Specification. 0 Freescale Semiconductor 41 .7.1.
1.Flash high voltage current behaviors 8.7. MKW22D512V Product Electrical Specification. the EEPROM data set size can be set to any of several non-zero values.4 NVM reliability specifications 8.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash.1. Rev.7. 0 42 Freescale Semiconductor .
Writes_subsystem = EEPROM . entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. 2 Å~ EEESPLIT Å~ EEESIZE EEESPLIT Å~ EEESIZE x Write_efficiency x nnvmcycd where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART.25 for 8-bit writes to FlexRAM — 0.000 cycles) MKW22D512V Product Electrical Specification. While different partitions of the FlexNVM are available. Rev.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycd — data flash cycling endurance (the following graph assumes 10. the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. 0 Freescale Semiconductor 43 . The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem.The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. entered with the Program Partition command • Write_efficiency — 0.
Figure 7. 0 44 Freescale Semiconductor . EEPROM backup writes to FlexRAM 8.2 EzPort switching specifications MKW22D512V Product Electrical Specification.7. Rev.
0 Freescale Semiconductor 45 . MKW22D512V Product Electrical Specification.8.1 Analog ADC electrical specifications The 16-bit accuracy specifications are achievable on the differential pins ADCx_DP0. Rev. ExPort timing diagram 8.Figure 8. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. ADCx_DM0.8 8.
0 46 Freescale Semiconductor .MKW22D512V Product Electrical Specification. Rev.
ADC input impedance equivalency diagram MKW22D512V Product Electrical Specification.Figure 9. 0 Freescale Semiconductor 47 . Rev.
1 16-bit ADC electrical characteristics MKW22D512V Product Electrical Specification.8.8. Rev.1. 0 48 Freescale Semiconductor .
MKW22D512V Product Electrical Specification. Rev. 0 Freescale Semiconductor 49 .
Rev. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode MKW22D512V Product Electrical Specification. Typical ENOB vs. 0 50 Freescale Semiconductor . ADC_CLK for 16-bit differential mode Figure 11.Figure 10.
2 CMP and 6-bit DAC electrical specifications MKW22D512V Product Electrical Specification.8. Rev. 0 Freescale Semiconductor 51 .8.
8.4.8.4 8. temperature 8. 0 56 Freescale Semiconductor . Offset at half scale vs.Figure 15.1 Voltage reference electrical specifications VREF full-range operating requirements MKW22D512V Product Electrical Specification. Rev.
8.8.4. visit http://www.8.2 VREF full-range operating behaviors 8.1 Communication interfaces USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum.9. Rev.4 VREF limited-range operating behaviors 8.9 8. For the most up-to-date standards.4.org.usb.3 VREF limited-range operating requirements 8.4. 0 Freescale Semiconductor 57 . MKW22D512V Product Electrical Specification.8.
8.3 VREG electrical specifications MKW22D512V Product Electrical Specification.2 USB DCD electrical specifications 8. 0 58 Freescale Semiconductor .9. Rev.9.
4 DSPI switching specifications (limited voltate range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.8. 0 Freescale Semiconductor 59 . The tables below provide DSPI timing characteristics for classic SPI timing modes. Rev. Many of the transfer attributes are programmable.9. Master mode Figure 16. DSPI classic SPI timing — master mode MKW22D512V Product Electrical Specification.
MKW22D512V Product Electrical Specification. 0 60 Freescale Semiconductor . The tables below provides DSPI timing characteristics for classic SPI timing modes. Rev. DSPI classic SPI timing — slave mode 8.Slave mode Figure 17. Many of the transfer attributes are programmable.9.5 DSPI switching specification (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
Rev. DSPI classic SPI timing — master mode Slave mode DSPI timing (full voltage range) MKW22D512V Product Electrical Specification. 0 Freescale Semiconductor 61 .Master mode DSPI timing (full voltage range) Figure 18.
6 Normal Run. DSPI classic SPI timing — slave mode 8. Rev. Wait and Stop mode performance over the fulloperating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run. 0 62 Freescale Semiconductor . MKW22D512V Product Electrical Specification. Wait and Stop modes.9.Figure 19.
I2S/SAI master mode timing Figure 20. 0 Freescale Semiconductor 63 . I2S/SAI timing — master modes MKW22D512V Product Electrical Specification. Rev.
and VLPS modes.7 VLPR. I2S/SAI timing — slave modes 8. VLPW. VLPW. MKW22D512V Product Electrical Specification. and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR.9.I2S/SAI slave mode timing Figure 21. Rev. 0 64 Freescale Semiconductor .
0 Freescale Semiconductor 65 . VLPW. Rev.I2S/SAI master mode timing in VLPR. I2S/SAI timing — master modes I2S/SAI slave mode timing in VLPR. VLPW. and VLPS modes (full voltage range) Figure 22. and VLPS modes (full voltage range) MKW22D512V Product Electrical Specification.
unless otherwise noted) Characteristic Power Supply Current (VBATT + VDDINT) Reset / power down1 Hibernate1 Doze (No CLK_OUT) Idle (No CLK_OUT) Transmit mode (0 dBm nominal output power) Receive mode Input current (VIN = 0 V or VDDINT) (All digital inputs) Symbol Min Typ Max Unit Ileakage ICCH ICCD ICCI ICCT ICCR IIN — — — — — — — <30 <1 600 700 15 15 — — — — — 18 18 1 nA µA µA µA mA mA µA MKW22D512V Product Electrical Specification. I2S/SAI timing — slave modes 9 9. TA=25°C.1 Transceiver electrical characteristics DC electrical characteristics Table 10. Rev. 0 66 Freescale Semiconductor .Figure 23. VDDINT = 2. DC electrical characteristics (VBATT.7 V.
Rev.7 V. VDDINT = 2. TA=25°C. DC electrical characteristics (VBATT. MKW22D512V Product Electrical Specification.Table 10. 0 Freescale Semiconductor 67 . all GPIO and other digital IO must be handled properly. unless otherwise noted) Characteristic Input low voltage (all digital inputs) Input high voltage (all digital inputs) Output high voltage (IOH = -1 mA) (all digital outputs) Output low voltage (IOL = 1 mA) (all digital outputs) 1 Symbol VIL VIH VOH VOL Min 0 70% VDDINT 80% VDDINT 0 Typ — — — — Max 30% VDDINT VDDINT VDDINT 20% VDDINT Unit V V V V To attain specified low power current.
Relative limit from –40C to +105C Nominal output power Maximum output power Error vector magnitude Output power control range3 Over the air data rate 2nd harmonic 4 Symbol Min –30 –20 Typ — — 0 10 8 40 250 <-50 <-50 Max — — 0.5 — EVM — — — — — 3rd harmonic 4 1 2 [f-fc] > 3. Receiver AC electrical characteristics (VBATT.7 V.5 MHz. absolute limit from –40C to +105C Power Spectral Density2. VDDINT=2. MKW22D512V Product Electrical Specification.2 AC electrical characteristics Table 11. 0 68 Freescale Semiconductor . average spectral power is measured in 100 kHz resolution BW. It does not degrade more than 2 dB across temperature and an additional 1 dB across all processes.5 — 13 — — <-40 <-40 Unit dBm dB dBm dBm % dB kbps dBm dBm Pout –0. TA=25°C. Transmitter AC electrical characteristics (VBATT. For the relative limit. unless otherwise noted) Characteristic Symbol SENSper SENSper SENSmax Min — — — — — — — — — 80 Typ –99 –102 +10 38 34 47 47 55 — — — — — — — — 200 — Max –97 Unit dBm dBm dBm dB dB dB dB dB kHz ppm Sensitivity for 1% packet error rate (PER) (–40 to +105 °C) Sensitivity for 1% packet error rate (PER) (+25 °C) Saturation (maximum input level) Channel rejection for dual port mode (1% PER and desired signal –82 dBm) +5 MHz (adjacent channel) –5 MHz (adjacent channel) +10 MHz (alternate channel) –10 MHz (alternate channel) >= 15 MHz Frequency error tolerance Symbol rate error tolerance Table 12.7 V. 4 Measured with output power set to nominal (0 dBm) and temperature @ 25°C. the reference level is the highest reference power measured within  1 MHz of the carrier frequency 3 Measurement is at the package pin on the output of the Tx/Rx switch.9. If trap filter is needed must meet reference board size requirements. fref=32 MHz. fref=32 MHz. unless otherwise noted) Characteristic Power spectral density1. VDDINT=2. Power adjustment will span nominally from –30 dBm to +10 dBm in 21 steps @ 2 dBm / step. TA=25 °C. Rev.
0 Freescale Semiconductor 69 .55 ns (for SPI reads) tCKL (Minimum R_SCLK low time): 31.9. These constraints apply to the Master SPI (R_MOSI).25 ns tASC (After SCK delay): 31. SPI timing: R_SCLK to R_MOSI and R_MISO tDSU (data-to-SCK setup): 10 ns tDH (SCK-to-data hold): 10 ns MKW22D512V Product Electrical Specification. 55. and are guaranteed by the radio SPI (R_MISO).25 ns (for SPI writes).2.55 ns (for SPI reads) NOTE The SPI master device deasserts R_SSEL_B only on byte boundaries.25 ns tDT (Minimum CS idle time): 62.25 ns (for SPI writes). Rev. 9.1 SPI timing: R_SSEL_B to R_SCLK The following diagram describes timing constraints that must be guaranteed by the system designer. R_SCLK R_MOSI R_MISO tDSU tDH Figure 25.2.2 SPI timing: R_SCLK to R_MOSI and R_MISO The following diagram describes timing constraints that must be guaranteed by the system designer. R_SSEL_B R_SCLK tCSC tCKH tCKL tASC tDT Figure 24. SPI timing: R_SSEL_B to R_SCLK tCSC (CS-to-SCK delay): 31. and only after guaranteeing the tASC constraint shown above. 55.5 ns tCKH (Minimum R_SCLK high time): 31.
360 GHz 2.480 GHz PAO Pins for external T/R switch configuration.2 Crystal requirements The suggested crystal specification for the MKW22D512V is shown in Table 14. Table 14.420 GHz 2.Table 13.420 GHz 2. TX mode 2. RX mode 2.420 GHz 2. TX mode 2. The MKW22D512V transceiver provides on board crystal trim capacitors to assist in meeting this performance.4 Standard requires that frequency tolerance be kept within ±40 ppm accuracy. RF port impedance Characteristic RFIN Pins for internal T/R switch configuration.1 Crystal oscillator design considerations The IEEE ® 802. 10. A number of the stated parameters are related to desired package. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance.360 GHz 2. while the bulk of the crystal load capacitance is external. 10.15.360 GHz 2.480 GHz RFIN Pins for internal or external T/R switch configuration.480 GHz Symbol Typ TBD Zin  Unit TBD Zin  TBD Zin  10 Crystal oscillator reference frequency This section provides application specific information regarding crystal oscillator reference design and recommended crystal usage. Rev. desired temperature range and use of crystal capacitive load trimming. MKW22D512V crystal specifications Parameter Frequency Frequency tolerance (cut tolerance) Frequency stability (temperature) Aging1 Equivalent series resistance Load capacitance Value 32 10 25 2 60 5–9 Unit MHz ppm ppm ppm  pF at 25°C Over desired temperature range max max Condition MKW22D512V Product Electrical Specification. 0 70 Freescale Semiconductor .
MKW22D512V crystal specifications (continued) Parameter Shunt capacitance Mode of oscillation 1 Value <2 Unit pF max fundamental Condition A wider aging tolerance may be acceptable if application uses trimming at production final test.Table 14. Rev. 0 Freescale Semiconductor 71 . MKW22D512V Product Electrical Specification.
Rev. 0 72 Freescale Semiconductor . MKW22D512V pin assignments (Sheet 1 of 4) Typical feature RADIO RADIO RADIO SPI0 MKW22D MKW21D 512V xxxV (USB) 1 2 3 4 1 2 3 4 Pin Name EXTAL _32M GPIO1 GPIO2 Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EXTAL _32M GPIO1 GPIO2 — — — — — — — PTC4/ LLWU_ P8 PTC5/ LLWU_ P9 — — — SPI0_ PCS0 SPI0_ SCK SPI0_ SOUT SPI0_ SIN SPI0_ SCK SPI0_ SOUT SPI0_ SIN SPI0_ PCS1 SPI0_ PCS2 — — — UART1 _TX LPTMR 0_ALT2 PDB0_ EXTRG USB_ SOF_ OUT UART2 _CTS_ b UART2 _RX UART2 _TX UART0 _RTS_ b UART0 _CTS_ b/ UART0 _COL_ b UART0 _RX UART0 _TX — — — FTM0_ CH3 I2S0_ RXD0 I2S0_ RX_ BCLK I2S0_ RX_FS — — — — — — — — CMP1_ OUT CMP0_ OUT I2S0_ MCLK — — — — — PTC4/ DISABL LLWU_ ED P8 PTC5/ DISABL LLWU_ ED P9 SPI0 5 5 — — — SPI0 6 6 PTC6/ CMP0_ CMP0_ PTC6/ LLWU_ IN0 IN0 LLWU_ P10 P10 PTC7 CMP0_ CMP0_ IN1 IN1 ADC0_ SE5b ADC0_ SE5b — PTC7 — — SPI0 7 7 — — I2C 8 8 PTD1 PTD1 — — — I2C 9 9 PTD2/ DISABL LLWU_ ED P13 PTD3 DISABL ED PTD2/ LLWU_ P13 PTD3 I2C_ SDA I2C_ SCL FTM0_ CH4 FTM0_ CH5 — — GPIO4 _BSM_ DATA GPIO5 _BSM_ CLK GPIO_ BSM_ FRAME — 10 10 — — — UART0 11 11 PTD4/ mADC0 mADC0 PTD4/ LLWU_ _SE21 _SE21 LLWU_ P14 P14 PTD5 ADC0_ SE6b ADC0_ SE6b PTD5 — EWM_ IN EWM_ OUT_b UART0 12 12 — UART0 13 13 PTD6/ LLWU_ P15 PTD7 ADC0_ SE7b ADC0_ SE7b PTD6/ LLWU_ P15 PTD7 SPI0_ PCS3 CMT_ IRO FTM0_ CH6 FTM0_ CH7 — FTM0_ FLT0 FTM0_ FLT1 — UART0 14 14 mADC0 mADC0 _SE22 _SE22 — — MKW22D512V Product Electrical Specification.11 Pin assignments Table 15.
Table 15.U ART1. 0 Freescale Semiconductor 73 .I2C MKW22D MKW21D 512V xxxV (USB) 15 15 Pin Name PTE0 Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 mADC0 mADC0 _SE10 _SE10 PTE0 SPI1_ PCS1 UART1 _TX — mTRAC E_ CLKOU T mTRAC E_D3 mTRAC E_D2 mTRAC E_D1 mTRAC E_D0 — — — — I2C1_ SDA RTC_ CLKOU T SPI1_ SIN — TRACE. 18 18 — — SPI1_ SOUT — TRACE. 16 16 PTE1/ mADC0 mADC0 PTE1/ LLWU_ _SE11 _SE11 LLWU_ P0 P0 PTE2/ mADC0 mADC0 PTE2/ LLWU_ _DP1 _DP1 LLWU_ P1 P1 PTE3 mADC0 mADC0 _DM1 _DM1 PTE3 SPI1_ SOUT SPI1_ SCK SPI1_ SIN SPI1_ PCS0 — SPI0_ PCS0 SPI0_ SCK SPI0_ SOUT SPI0_ SIN — — — — — — UART1 _RX UART1 _CTS_ b UART1 _RTS_ b UART3 _TX — — I2C1_ SCL — TRACE. 17 17 — TRACE. Rev. MKW22D512V pin assignments (Sheet 2 of 4) Typical feature TRACE. 19 19 PTE4/ DISABL LLWU_ ED P2 VDD_ MCU PTE16 PTE17 PTE18 VDD_ MCU ADC0_ SE4a ADC0_ SE5a ADC0_ SE6a ADC0_ SE7a USB0_ DP USB0_ DM VDD_ MCU ADC0_ SE4a ADC0_ SE5a ADC0_ SE6a ADC0_ SE7a USB0_ DP USB0_ DM PTE4/ LLWU_ P2 — PTE16 PTE17 PTE18 — — — — — — 20 — — — 20 21 22 23 — — FTM0_ FLT3 LPTMR 0_ALT3 — — — — — UART2 FTM_ _TX CLKIN0 UART2 FTM_ _RX CLKIN1 UART2 _CTS_ b UART2 _RTS_ b — — — — — — I2C0_ SDA I2C0_ SCL — — — — — — — — 24 PTE19 PTE19 — — — USB USB USB USB Analog Power Analog Power 21 22 23 24 25 26 — — — — 25 26 USB0_ DP USB0_ DM — — — — — — — — — — — — — — — — — — — — — — — — VOUT3 VOUT3 VOUT3 3 3 3 VREGI N VDDA VREGI N VDDA VREGI N VDDA VREFH VREFH VREFH MKW22D512V Product Electrical Specification.
Timer 34 34 PTA1 — PTA1 FTM0_ CH6 FTM0_ CH7 — — — JTAG_ TDI JTAG_ TDO/ TRACE _SWO 35 35 PTA2 — PTA2 — — — JTAG. 32KHz OSC JTAG. Timer 36 36 PTA3 — PTA3 UART0 _RTS_ b — FTM0_ CH0 — — — JTAG_ TMS/ SWD_ DIO NMI_b NMI 37 37 PTA4/ LLWU_ P3 VDD_ MCU PTA18 — PTA4/ LLWU_ P3 — PTA18 FTM0_ CH1 — — — — — MCU XTAL 38 39 38 39 VDD_ MCU EXTAL 0 — — — — — — — — — FTM0_ FTM_ FLT2 CLKIN0 MKW22D512V Product Electrical Specification. 0 74 Freescale Semiconductor . 32KHz OSC VBAT. Timer JTAG. MKW22D512V pin assignments (Sheet 3 of 4) Typical feature Analog Power Analog Power Tamper MKW22D MKW21D 512V xxxV (USB) 27 28 29 27 28 29 Pin Name VREFL VSSA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 VREFL VSSA VREFL VSSA — — — — — — — — — — — — — — — — — — — — — TAMPE TAMPE TAMPE R0/ R0/ R0/ RTC_ RTC_ RTC_ WAKE WAKE WAKE UP_B UP_B UP_B XTAL32 XTAL32 XTAL32 VBAT.Table 15. Timer 30 30 — — — — — — — 31 31 EXTAL 32 VBAT_ MCU PTA0 EXTAL 32 VBAT_ MCU JTAG_ TCLK/ SWD_ CLK/ EZP_ CLK JTAG_ TDI/ EZP_DI JTAG_ TDO/ TRACE _SWO/ EZP_ DO JTAG_ TMS/ SWD_ DIO NMI_b/ EZP_ CS_b VDD_ MCU EXTAL 0 EXTAL 32 VBAT_ MCU — — — — — — — — 32 32 — — — — — — — 33 33 PTA0 UART0 _CTS_ b/ UART0 _COL_ b UART0 _RX UART0 _TX FTM0_ CH5 — — — JTAG_ TCLK/ SWD_ CLK JTAG. 32KHz OSC VBAT. Rev.
Table 15. Rev. 0 Freescale Semiconductor 75 . MKW22D512V pin assignments (Sheet 4 of 4) Typical feature MCU XTAL RESET RADIO RADIO RADIO RADIO RADIO MKW22D MKW21D 512V xxxV (USB) 40 41 42 43 44 45 46 40 41 42 43 44 45 46 Pin Name PTA19 Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 XTAL0 XTAL0 PTA19 — — — — — — — — — — — — — FTM1_ FTM_ FLT0 CLKIN1 — — — — — — — — — — — — — — — — — — — LPTMR 0_ALT1 — — — — — — — — — — — — — RESET RESET RESET _b _b _b VBAT2 _RF VDD_ REGD ANT_A ANT_B RX_ SWITC H TX_ SWITC H GND_ PA RF_ OUTP RF_ OUTN GND_ PA VDD_ PA VBAT3 _RF VDD_ REGD ANT_A ANT_B RX_ SWITC H TX_ SWITC H GND_ PA RF_ OUTP RF_ OUTN GND_ PA VDD_ PA — — — — — RADIO 47 47 — — — — — — — — RADIO RADIO RADIO RADIO RADIO RADIO RADIO RADIO RADIO 48 49 50 51 52 53 54 55 56 48 49 50 51 52 53 54 55 56 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VDD_IF VDD_IF VDD_ RF VBAT_ RF XTAL_ 32M VDD_ RF VBAT_ RF XTAL_ 32M MKW22D512V Product Electrical Specification.
12 Packaging information TX_SWITCH RX_SWITCH XTAL_32M VBAT_RF EXTAL_32M GPIO1 GPIO2 PTC4/LLWU_P8 PTC5/LLWU_P9 PTC6/LLWU_P10 PTC7 PTD1 PTD2/LLWU_P13 PTD3 PTD4/LLWU_P14 PTD5 PTD6/LLWU_P15 PTD7 1 2 3 4 5 6 7 8 9 10 11 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 VDD_REGD RF_OUTN VDD_PA GND_PA RF_OUTP GND_PA VDD_RF VDD_IF ANT_B ANT_A VBAT2_RF RESET_b PTA19/XTAL PTA18/EXTAL/RCLK_OUT VDD_MCU PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTAO VBAT_MCU EXTAL32 XTAL32 TAMPER0/RTC_WAKEUP_B MKW22D512V (USB) 35 34 33 32 31 30 12 13 14 15 16 17 18 19 20 21 22 23 VOUT_33 24 25 26 27 29 28 PTE1/LLWU_P0 PTE4/LLWU_P2 VDD_MCU VREFH PTE2/LLWU_P1 VREFL PTE0 USB0_DM USB0_DP VREGIN MKW22D512V Product Electrical Specification. Rev. 0 76 Freescale Semiconductor VDDA VSSA PTE3 .
Rev.TX_SWITCH RX_SWITCH XTAL_32M VBAT_RF EXTAL_32M GPIO1 GPIO2 PTC4/LLWU_P8 PTC5/LLWU_P9 PTC6/LLWU_P10 PTC7 PTD1 PTD2/LLWU_P13 PTD3 PTD4/LLWU_P14 PTD5 PTD6/LLWU_P15 PTD7 1 2 3 4 5 6 7 8 9 10 11 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 VDD_REGD RF_OUTN GND_PA RF_OUTP GND_PA VDD_RF VDD_IF VDD_PA ANT_B ANT_A VBAT2_RF RESET_b PTA19/XTAL PTA18/EXTAL/RCLK_OUT VDD_MCU PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTAO VBAT_MCU EXTAL32 XTAL32 TAMPER0/RTC_WAKEUP_B MKW21D512V MKW21D256V 35 34 33 32 31 30 12 13 14 15 16 17 18 19 20 21 22 23 PTE18 24 25 26 27 29 28 PTE1/LLWU_P0 PTE4/LLWU_P2 VDD_MCU VREFH PTE2/LLWU_P1 VREFL PTE0 PTE17 PTE16 MKW22D512V Product Electrical Specification. 0 Freescale Semiconductor 77 PTE19 VDDA VSSA PTE3 .

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