Source: http://dtsheet.com/doc/747374/fujitsu-mb90v800
Timestamp: 2019-04-25 19:51:01+00:00

Document:
controller of 48 segment four common is built into.
enrichment of bit processing. In addition, long word processing is now available by introducing a 32-bit accumulator.
* : F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.
oscillation of 6.25 MHz, 6.25 MHz to 25 MHz).
• The priority level can be set to programmable.
• 8-bit resolution or 10-bit resolution can be set.
Upon detecting a valid edge of the signal input from the external input pin, the count value of the 16-bit freerun timer is loaded into the input capture data register and an interrupt request can be output.
The event count function is optional. The event count function is optional.
Three channels are built in.
Two channels are built in.
I2C Interface. 1 channel is built-in.
The 8-bit resolution or 10-bit resolution can be set.
Conversion time : 5.9 µs (When machine clock 16.8 MHz works).
Asynchronous/synchronous transmit (with start/stop bits) are supported.
It is a terminal which connects the oscillator.
It is 32 kHz oscillation pin.
Input pin for selecting operation mode.
Serial data output pin of serial I/O channel 3.
Serial clock I/O pin of serial I/O channel 3.
* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.
Serial data input pin of serial I/O channel 3.
It is effective when permitting the power output.
Output terminal for the Output Compares.
It is a output terminal for LED (IOL = 15 mA).
External clock input pin of reload timer channel 2.
PPG timer (ch0) output pin.
PPG (ch1) timer output pin.
Serial data input pin of UART channel 0.
Serial clock input/output pin of UART channel 0.
Serial data output pin of UART channel 0.
Serial data input pin of UART channel 1.
" enabled "(set by ADER).
Analog input pin channel 8 of A/D converter.
Functions as an external interrupt ch3 input pin.
Analog input pin channel 9 of A/D converter.
Serial clock input/output pin of UART channel 1.
Analog input pin channel 10 of A/D converter.
Serial data output pin of serial I/O channel 1.
Analog input pin channel 11 of A/D converter.
Serial data input pin of serial I/O channel 2.
Data input/output pin of I2C Interface.
running, the port must be set for input use.
LCD drive power Reference power terminals of LCD controller/driver.
A/D converter exclusive power supply input pin.
A/D converter-exclusive GND power supply pin.
These are power supply input pins.
Clock input/output pin of I2C Interface.
Serial data output pin of serial I/O channel 2.
Serial clock input pin of serial I/O channel 2.
Reference power terminals of LCD controller/driver.
resource share one output buffer.
resource share one input buffer.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• If the AVCC power supply is turned on before the VCC voltage.
VCC and the digital power supply).
using CMOSICs, take great care to prevent the occurrence of latchup.
is recommended at 0.1 µF across VCC and VSS.
cannot be guaranteed. Performance of this operation, however, cannot be guaranteed.
X0A = VSS and X1A = OPEN.
Ensure that you must write to FLASH at the operating voltage VCC = 3.13 V to 3.6 V.
Ensure that you must normal write to FLASH at the operating voltage VCC = 3.0 V to 3.6 V.
• Built-in ROM is not exist.
• The device has 28 KB built-in RAM.
* : ROM is not built into V products.
I must think ROM decipherment region on the tool side.
• The ROM mirror function is for using the C compiler small model.
32 K bytes, all data in the ROM area cannot be shown in mirror image in bank 00.
without declaring the far addressing with the pointer.
0 Initial Value is “0”.
1 Initial Value is “1”.
X Initial Value is Indeterminate.
: Available El2OS function is provided.
: Available when a cause of interrupt sharing a same ICR is not used.
masked during IIOS start, masking one of the interrupt requests is recommended when using IIOS.
cleared by an IIOS interrupt clear signal.
in bit by the port direction register (DDR).
port9 when the subclock is not used) are input/output port.
When reading : Read the corresponding pin level.
When writing : Write into the latch for the input/output.
When reading : Read the value of the data register latch.
When writing : Write into the corresponding pin.
1 : Output mode This bit becomes “0” after a reset.
and finally change to the output when changing the input pin to the output pin is made.
Control each pin of Port 6 as follows.
1 : Analog input mode.This bit becomes “1” after a reset.
Variable baud rate can be set by an external clock.
Master/slave type communication function (at multiprocessor mode) : The communication between one (master) to n (slave) can be operating.
on the I2C bus. MB90800 series have 1 channel of the built-in I2C interface.
It has the features of I2C interface below.
• The forwarding rate can be supported to 100 Kbps.
in data transfer called LSB first and MSB sirst.
• Internal shift clock mode : Transfer data in sync with the internal clock.
operating the general-use port sharing an external pin (SCK) .
A/D converter converts an analog input voltage into digital value. The feature of A/D converter is shown as follows.
• 8-bit resolution or 10-bit resolution can be select.
• 12 channel program-selectable analog inputs.
Continuous conversion mode : Selected channel converted continuously.
• EI OS can be activated by outputting the interrupt request when the A/D conversion completes.
buffer, a 16-bit compare register with a duty setting buffer, and the pin control unit.
The PPG timer can output pulses synchronized to the software trigger.
The period and duty of the output pulse can be changed freely by updating two 16-bit register values.
Can also be used as a D/A converter by an external circuit.
By detecting an edge of the trigger input, a single pulse can be output.
The counter operation clock comes from eight kinds optional. There are eight kinds of internal clocks.
The counter is initialized to " FFFFH " at a reset or counter borrow.
interrupt input terminal, and outputs the interrupt request.
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare and two input capture modules.
widths and external clock frequencies to be measured.
The 16-bit free-run timer consists of a 16-bit up-down counter and control status register.
Counter value of 16-bit free-run timer is available as base timer for input capture and output compare.
• Clock for the counter operation can be selected from eight types.
• The counter overflow interruption can be generated.
compare clear register in the output compare.
value matches a value set in one of the 16-bit compare registers of this module.
controlled by using two compare registers.
• An interrupt can be set by a comparing match.
This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.
• It can generate an interrupt when it detects the valid edge of the external input.
the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.
be used as the clock source of the watchdog timer by setting so.
the CPU when the counter is not cleared for a preset period of time.
: The machine clock is switched from main/sub clock to PLL clock.
: The machine clock is switched from sub clock to main clock.
the control of the clock.
set division clock. Selectable from 32/64/128/256 division of the oscillation clock.
The timer clock output circuit is inactive in reset or stop mode. Normally, it is active in run, sleep, or pseudotimer mode.
Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output.
For detail of the timebase timer’s clear condition, see the section of timebase timer in Hardware Manual.
among the settings of the register.
Note : Do not access to this register in the middle of the operation of the address 008000H to 00FFFFH.
• Setting of Interrupt level at correspondent peripheral circuit.
Note : Do not access using the read modify write instruction because it causes a malfunction.
• Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be connected.
• Contains 24-byte display data memory (display RAM).
• For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).
• The LCD can directly be driven.
The Absolute Maximum Ratings is based on VSS = AVSS = 0.0 V.
*1 : AVCC should not be exceeding VCC at power-on etc.
*2 : VI, VO, should not exceed Vcc + 0.3 V.
*3 : A peak value of an applicable one pin is specified as a maximum output current.
*4 : An average current value of an applicable one pin within 100 ms is specified as an average output current.
*5 : An average current value of all pins within 100 ms is specified as an average total output current.
The Recommended Operating Conditions is based on VSS = AVSS = 0.0 V.
The DC Characteristics is based on VSS = AVSS = 0.0 V.
LCRR (LCDC range register) .
The Clock timing is based on VSS = AVSS = 0.0 V.
in “Base oscillator frequency vs. Internal operating clock frequency”.
The Reset input timing is based on VSS = AVSS = 0.0 V.
on a FAR/ceramic oscillator, and 0 milliseconds on an external clock.
The Power-on reset is based on VSS = AVSS = 0.0 V.
Notes : • VCC should be set under 0.2 V before power-on rising up.
• These value are for power-on reset.
is executing, power-on prosedure must be obeyed by these value.
1mV/s or less, use of PLL clock is allowed during operation.
The Serial I/O is based on VSS = AVSS = 0.0 V.
Notes : • AC rating in CLK synchronous mode.
• C L is a load capacitance value on pins for testing.
• tCP is machine cycle frequency (ns) .
The Timer input timing is based on VSS = AVSS = 0.0 V.
The Timer output timing is based on VSS = AVSS = 0.0 V.
The Trigger Input Timing is based on VSS = AVSS = 0.0 V.
The I2C trriger is based on AVSS = VSS = 0.0 V.
*2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
The Electrical characteristics for the A/D converter is based on VSS = AVSS = 0.0 V.
*1 : At operating, main clock 25 MHz.
Note : The values are reference values.
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• As | AVCC | becomes smaller, values of relative errors grow larger.
Analog variation that is recognized by an A/D converter.
The 10-bit can resolve analog voltage into 210 = 1024.
offset error, gain error, non-linearity error and noise.
(11 1111 1110↔11 1111 1111) and actual conversion characteristics.
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
VNT: A voltage at which digital output transitions from (N-1) to N.
VOT : Voltage at which digital output transits from 000H to 001H.
VFST : Voltage at which digital output transits from 3FEH to 3FFH.
measuremunts into normalized value at + 85 °C).
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
FUJITSU MICROELECTRONICS ASIA PTE LTD.

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