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Timestamp: 2019-04-26 02:37:14+00:00

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i EQ1=2R ×I UNIT+(c EQ1×2R)×Polarity(Dataj-1)×I UNIT; where Polarity(Dataj-1) is 1 if Dataj-1=1 and −1 if Dataj-1=0.
⁢ i OL = i SIG + i EQ ; where i EQ = 2 R × K × I UNIT + ( c EQ ⁢ ⁢ 1 × 2 R ) × Polarity ⁡ ( Data j - 1 ) × I UNIT + ( c EQ ⁢ ⁢ 2 × 2 R ) × Polarity ⁡ ( Data j - 2 ) × I UNIT + … ⁡ ( c EQK × 2 R ) × Polarity ⁡ ( Data j - K ) × I UNIT .
Allan, Graham, "DDR SDRAM/SGRAM: An Interpretation of the JEDEC Standard," MOSAID Technologies Inc., Sep. 25, 1998. 73 pages.
Armstrong, David H., "Pitfalls in Testing Digital Devices," IEEE 1987 Custom Integrated Circuits Conference, pp. 573-578. 7 pages.
Biber, Alice I., "The Design of an Application Specific Interface Driver for a High Capactive Load," Masters Thesis at the Massachusetts Inst. Of Technology, Dec. 1989. 68 pages.
Brief Communication with Preliminary Opinion Examining Division dated Sep. 21, 2010 for EP Application No. 07121085.0-2212. 2 pages.
Cox et al., "VLSI Performance Compensation for Off-Chip Drivers and Clock Generation," IEEE 1989 Custom Integrated Circuits Conference, pp. 14.3.1-14.3.4. 12 pages.
Dally et al., "Digital Systems Engineering," 1998, pp. 361-366. 21 pages.
Douseki et al., "BiCMOS Circuit Technology for a High-Speed SRAM," IEEE Journal of Solid State Circuits, vol. 23, No. 1, Feb. 1988, pp. 68-73. 8 pages.
EP Communication with mail date of Dec. 14, 2010 for EP Application No. 10180625.5 re Extended European Search report. 5 pages.
EP Extended Search Report dated Feb. 8, 2011 re EP Application No. 10179814.8. 5 pages.
EP Office Action with mail date of Mar. 19, 2010 re EP Patent Application No. 00 975 263.5 re Commencement of Proceedings before the Board of Appeal. 1 Page.
EP Office Communication dated Dec. 1, 2010 re EP Application No. 05025388.9 in the Decision to refuse a EP Application. 9 Pages.
EP Office Communication with mail date of Sep. 24, 2010, re EP Patent Application No. 07121085.0-2212. 1 page.
EP Provision of the Minutes of the Oral Proceedings before the Opposition Division with mail date of Dec. 30, 2009 re EP Application 00 975 263.5 with opponent Micron Europe Ltd. Includes the Interlocutory Decision in Opposition Proceedings and Documents for the Maintenance of the Patent as Amended, listed under Annex to the Minutes. 59 pages.
EP Response dated Jul. 5, 2011 to the European Search Opinion dated Feb. 8, 2011 and to the Official Communication dated Mar. 14, 2011re EP Application No. 10179814.8. 6 Pages.
EP Response dated Jun. 15, 2011 to the European Search Opinion dated Dec. 2011 and to the Official Communication dated Jan. 17, 2011 re EP Application No. 10180625.5. 17 Pages.
EP Response to the Official Communication of Mar. 8, 2010 (summons to attend oral proceedings), dated Aug. 27, 2010, Includes Summons to Attend Oral Proceedings, New claims 1-18 (with highlighted amendments), and New claims 1-18 (clear copy), in EP Application No. 07121085.0-2212. 12 pages.
EP Response to the Official Communication of Sep. 21, 2010, dated Sep. 22, 2010 in EP Application No. 07121085.0-2212 (Includes Clear and Highlighted Amendments). 12 pages.
EP Response to the Summons to Attend Oral Proceedings, Official Communication of Mar. 9, 2010, dated Aug. 27, 2010, Includes Summons to Attend Oral Proceedings, New claims 1-10 (with highlighted amendments), and New claims 1-10 (clear copy), in EP Application No. 05025388.9-2212. 19 pages.
Gabara et al., "Digitally Adjustable Resistors in CMOS for High-Performance Applications," IEEE Journal of Solid-State Circuits, vol. 27, No. 8, Aug. 1992. 10 pages.
Gillingham et al., "SLDRAM: High Performance Open-Standard Memory," IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc., Los Alamitos, California. 11 pages.
Gillingham, Peter, "SLDRAM Architectural and Functional Overview," SLDRAM Consortium, Aug. 29, 1997, pp. 1-14. 14 pages.
IBM Application Note, "DDR SDRAM Module Serial Presence Detect Definitions," Oct. 1999, pp. 1-34. 34 pages.
IBM Corporation, "184 Pin DIMM Updates/Ramifications for Unbuffered and Registered DDR DIMMs," 2000. 14 pages.
IBM Corporation, "Driver with Noise-Dependent Switching Speed Control," IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, IBM Corporation, pp. 1243-1244. 16 pages.
IBM, Micron Technology and Reliance Computer Corporation, "DDR SDRAM Registered DIMM," Design Specification, Revision 0.6, Nov. 1999. 62 pages.
Intel Corporation, "Intel 430TX PCISET: 82439TX System Controller (MTXC)," Preliminary, Order No. 290559-001, Feb. 1997. 84 pages.
Intel, "440BX AGPset: 82443BX Host/Bridge/Controller Datasheet," Apr. 1998. 158 pages.
Johnson, Curtis D. et al., "Highly Accurate Resistance Deviation to Frequency Converter with Programmable Sensitivity and Resolution," IEEE vol. IM-35, No. 2, Jun. 1986, 4 pages.
Knight et al., "Self-Terminating Low-Voltage Swing CMOS Output Driver," IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1988. 8 pages.
Leung, Kam, "Controlled Slew Rate output Buffer," IEEE 1988 Custom Integrated Circuits Conference, 1988, pp. 5.5.1-5.5.4. 4 pages.
Mathews et al., "Power Supply Voltages for Future VLSI," IEEE 1986 Custom Integrated Circuits Conference, pp. 149-152. 4 pages.
Minutes of Meeting No. 33 JC-16 Committee on Voltage Level and Interface, Mar. 2, 1999, Las Vegas, Nevada. 12 pages.
Nakase et al., "Source-Synchronization and Timing Vernier Techniques for 1.2 GB/s SLDRAM Interface," IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 494-501. 8 pages.
Notice of Opposition to a European Patent No. 1151387, filed by Micron Europe Ltd., on Jun. 19, 2008, 33 pages.
Official Communication dated May 17, 2010 re statement of grounds of appeal filed by Micron on May 10, 2010 re EP Application No. 00975263.5, Appeal No. T0555/10-3501. 15 Pages.
Oshima et al., "High-Speed Memory Architecture for Multimedia Applications," IEEE, Circuits & Devices, Jan. 1997, pp. 8-13. 7 pages.
Paris et al., "WP 24.3: A 800 Mb/s 72 Mb SLDRAM with Digitally-Calibrated DLL," ISSCC, 0-7803-5129-0/99, Slide Supplement, IEEE, 1999. 10 pages.
Poulton, John, "Signaling in High Performance Memory Systems," IEEE Solid State Circuits Conference, slides 1-59, Feb. 1999. 30 pages.
Preliminary publication of JEDEC Semiconductor Memory Standards, JEDEC 64 MEG: x4, x8, x16 DDR SDRAM, JEDEC, Aug. 1999. 73 pages.
Rambus Inc., "16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM-Advance Information," Rambus Inc. Data Sheet, Jul. 1996. 61 pages.
Rambus Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM-Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996. 30 pages.
Rambus Inc., "RDRAM Annotated Specification 4.1-2," Apr. 29, 1997. 366 Pages.
Raver, Norman, "Open-Loop Gain Limitations for Push-Pull Off-Chip Drivers," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 145-150. 7 pages.
Reynolds, C.B., "Analysis and Guidelines for High-Speed VLSI System Interconnections," IEEE 1988 Custom Integrated Circuits Conference, pp. 23.5.1-23.5.4. 4 pages.
Rhoden, DESI Advanced Memory International, Inc., Platform99, Standard DRAM Futures and DDR Infrastructures, Jul. 21 & 22, 1999. 48 pages.
Rhoden, DESI, Platform99 Standard DRAM Futures and DDR Infrastructures, Advanced Memory International, Inc., Jul. 21 and 22, 1999. 49 pages.
Sasaki et al., "A Modified Wheatstone Bridge for High-Precision Automated Resistance Measurement," IEEE Trans. on Instr. and Measurement, vol. 26, No. 2, Dec. 1987, pp. 947-949. 5 pages.
Sasaki et al., "Automated Measurement System for 1-.OMEGA. Standard Resistors Using a Modified Wheatstone Bridge," IEEE Trans. On Instr. And Measurement, vol. 40, No. 2, Apr. 1991, pp. 274-277. 4 pages.
Senbon, Tasuku et al., "Instrumentation Systems: Fundamentals and Applications, Chapter 3: Detection and Conversion of Industrial Variables," 1991, 77 pages.
SLDRAM Inc., "SLD4M18DR400 4 MEG×18 SLDRAM: 400 Mb/s/pin SLDRAM 4 M×18 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," Jul. 9, 1998. 69 pages.
Song et al., "NRZ Timing Recovery Technique for Band-Limited Channels," IEEE Journa of Solid-State Circuits, vol. 32, No. 4, Apr. 1997, pp. 514-520. 7 pages.
Submission to EPO dated Aug. 26, 2010 in Patent Application No. 00975263.2-2212. (Includes both highlighted and the Main Request as well as Auxiliary Requests I-IV, Annexes 1-3, and Excerpts from Betty Prince's "High Performance Memories," John Wiley & Sons, 1996, p. 11). 82 pages.
Summons to Attend Oral Proceedings with mail date of Mar. 8, 2010 re EP Patent Appln. No. 07121085.0. 4 Pages.
Ware, Frederick A., "Direct RDRAM 256/288-Mbit (512K×16/18×32s) Data Sheet," Preliminary Information, Rambus Inc., Document DL0060 Version 0.90, 1999, pp. 1-66. 66 pages.
Widmer et al., "Single-Chip 4×500-MBd CMOS Transceiver," IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2004-2014. 11 pages.

References: Application No. 07121085
 Application No. 10180625
 Application No. 10179814
 Application No. 00
 Application No. 05025388
 Application No. 07121085
 Application No. 10179814
 Application No. 10180625
 Application No. 07121085
 Application No. 07121085
 Application No. 05025388
 Application No. 00975263
 Application No. 00975263