Source: http://rsim.cs.illinois.edu/consistency/
Timestamp: 2019-04-18 20:57:14+00:00

Document:
A memory consistency model for a shared-memory multiprocessor defines the order in which memory operations will appear to execute to a programmer, or in other words, the values a read may return [IEEE Computer tutorial].
Traditionally, memory consistency models have involved a significant tradeoff between performance (for the hardware and compiler) and programmability. My dissertation research (under Prof. Mark Hill at the University of Wisconsin-Madison) alleviates this tradeoff by showing how systems can use performance-enhancing techniques such as write buffers and out-of-order memory operations, but still allow programmers to reason with the simple model of sequential consistency.
As part of the RSIM project, I explored speculation techniques to narrow the hardware performance gap between sequential consistency (the simplest model) and relaxed memory consistency models [ASPLOS'96, SPAA'97, Proc. of the IEEE'99].
With the Rice Treadmarks group, I also worked on consistency models for software distributed shared-memory systems [HPCA'96].
I co-developed the Java memory model (adopted for Java 5.0 in 2005) and the default C++ memory model (currently in the process of standardization). Both are based on the foundation of data-race-free models proposed in my PhD thesis.
Foundations of the C++ Concurrency Memory Model, Hans-J. Boehm and Sarita V. Adve, to appear in the Proceedings of the Conference on Programming Language Design and Implementation (PLDI), June 2008.
The Java Memory Model, Jeremy Manson, William Pugh, Sarita V. Adve, Proceedings of the 32nd Symposium on Principles of Programming Languages (POPL) Jan. 2005.
Recent Advances in Memory Consistency Models for Hardware Shared-Memory Systems, , S. V. Adve, V. S. Pai, and P. Ranganathan, Proceedings of the IEEE, special issue on distributed shared-memory, vol. 87, no. 3, March 1999, 445-455.
A Retrospective on "Weak Ordering -- A New Definition", S. V. Adve and M. D. Hill, 25 Years of the International Symposia on Computer Architecture - Selected Papers (Gurindar S. Sohi, editor), ACM Press, 1998.
Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors, P. Ranganathan, K. Gharachorloo, S. V. Adve, and L. A. Barroso, Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems,October 1998, 307-318.
Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models , Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve, Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures, June 1997, 199-210.
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems, Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, and Sarita V. Adve, Proceedings of the 24th International Symposium on Computer Architecture, June 1997, 144-156.
Shared Memory Consistency Models: A Tutorial, S.V. Adve and K. Gharachorloo, Rice University ECE Technical Report 9512 and Western Research Laboratory Research Report 95/7, September 1995. A version of this paper appears in IEEE Computer, December 1996, 66-76.
An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, and Tracy Harton, Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), October 1996, 12-23.
A Comparison of Entry Consistency and Lazy Release Consistency Implementations, S.V. Adve, A.L. Cox, S. Dwarkadas, R. Rajamony, and W. Zwaenepoel, Proceedings of the 2nd International Symposium on High Performance Computer Architecture, February 1996, 26-37.
Replacing Locks by Higher-Level Primitives, S.V. Adve, A.L. Cox, S. Dwarkadas, and W. Zwaenepoel, Technical Report #TR94-237, Department of Computer Science, Rice University, 1994. Presented at the Fourth Workshop on Scalable Shared-Memory Multiprocessors, Chicago, May 1994.
Designing Memory Consistency Models for Shared-Memory Multiprocessors, S. V. Adve, Ph.D. Thesis, Available as Computer Sciences Technical Report #1198, University of Wisconsin, Madison, December 1993.
Specifying System Requirements for Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Technical Report #CSL-TR-93-594, Stanford University, December 1993. Also available as Computer Sciences Technical Report #1199, University of Wisconsin, Madison, December 1993.
Sufficient System Requirements for Supporting the PLpc Memory Model, S.V. Adve, K. Gharachorloo, A. Gupta, J.L. Hennessy, and M.D. Hill, Computer Sciences Technical Report #1200, University of Wisconsin, Madison, December 1993. Also available as Technical Report #CSL-TR-93-595, Stanford University, December 1993.
A Unified Formalization of Four Shared-Memory Models, S.V. Adve and M.D. Hill, IEEE Transactions on Parallel and Distributed Systems 4, 6 (June 1993), 613-624.
Sufficient Conditions for Implementing the Data-Race-Free-1 Memory Model, S.V. Adve and M.D. Hill, Computer Sciences Technical Report #1107, University of Wisconsin, Madison, September 1992.
Programming for Different Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Journal of Parallel and Distributed Computing, August 1992, 399-407.
Detecting Data Races on Weak Memory Systems, S.V. Adve, M.D. Hill, B.P. Miller, and R.H.B. Netzer, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 234-243.
Weak Ordering - A New Definition, S.V. Adve and M.D. Hill, Proceedings of the 17th Annual International Symposium on Computer Architecture, May 1990, 2-14.
Implementing Sequential Consistency in Cache-Based Systems, S.V. Adve and M.D. Hill, Proceedings of the 1990 International Conference on Parallel Processing, August 1990, I47-I50.

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