Source: https://patents.google.com/patent/US8193567B2/en
Timestamp: 2019-04-24 16:10:08+00:00

Document:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
This application is a division of and claims the benefit of priority to U.S. application Ser. No. 11/238,444, filed on Sep. 28, 2005, now U.S. Pat. No. 7,479,421 the disclosure of which is incorporated herein by reference in its entirety for all purposes.
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to methods of integrating non-planar transistors with variable channel widths into a bulk semiconductor CMOS process.
For decades, planar transistors have been fabricated on bulk semiconductor substrates. Transistor 100, as shown in FIG. 1A, is such a planar device. An active region, having opposite sidewalls 106 and 107, and a top surface 108, is formed between isolation regions 110 on bulk semiconductor substrate 101. The isolation regions 110 substantially cover the opposite sidewalls 106 and 107. The top semiconductor surface 108 is apportioned into, a source region 116, a drain region 117, and a channel region covered by a gate insulator 112 and a gate electrode 113. In the planar transistor design, the device is typically controlled or gated via the capacitive coupling between the top semiconductor surface 108 and the gate electrode 113. Because the channel is gated by a single gate electrode-semiconductor interface, the planar transistor is frequently called a single-gate device.
More recently, non-planar transistors have been under development to address the short channel effect (SCE) afflicting planar nano-scale transistors. A non-planar transistor is a transistor where the semiconductor channel is non-planar and the gate electrode couples to the channel through more than one surface plane, typically through sidewall portions formed by the non-planarity. Transistor 150, as shown in FIG. 1B, is such a non-planar device. An active semiconductor region, having opposite sidewalls 106 and 107, and a top surface 108, is formed over a substrate comprised of an isolation region 103 on a carrier 102. The top surface 108 and the opposite sidewalls 106 and 107 are apportioned into a source region 116, and a drain region 117, and a channel region covered by a gate insulator 112 and a gate electrode 113. In this transistor design, the device can be gated by the opposite sidewalls 106 and 107, as well as the top surface 108 of the device, reducing the SCE. Because the channel is gated by multiple gate electrode-semiconductor interfaces, the non-planar transistor is frequently called a multi-gate device.
Non-planar, or multi-gate, devices have been typically been formed upon substrates comprising an insulating layer, commonly called semiconductor-on-insulator (SOI). While there are many advantages to non-planar devices formed on SOI, there are also many disadvantages. For example, the channel width of a non-planar transistor on SOI is limited by the final thickness of the active silicon layer formed on the insulator layer of the SOI substrate. Thus, circuit designers are limited to a fundamental width and multiples of that width for all transistors of a circuit formed on the substrate. As shown in FIG. 1C, multiple non-planar bodies, each having a source 116 and drain 117 region are coupled by a common gate electrode 113 through a gate insulator 112 in an electrically parallel fashion to form device 175. Device 175 limits circuit design flexibility because the current carrying width must be incremented discretely, not continuously. Also, because of lithographic pitch limitations, non-planar transistors like device 175 shown in FIG. 1C incur a layout penalty relative to traditional planar transistors. Another disadvantage of devices formed on SOI is the commonly known “floating body” effect due to the buried insulator layer, which results in the loss of a ground plane for the transistors. Furthermore, non-planar transistors formed on SOI substrates suffer from poorer thermal conductivity and a higher overall cost than devices formed on bulk substrates.
FIGS. 1A, 1B and 1C are illustrations of a perspective view of a conventional planar, single-gate transistor on a bulk semiconductor substrate and a conventional non-planar, multi-gate transistor on an SOI substrate, respectively.
FIG. 2 is an illustration of a perspective view of a circuit device having a planar transistor and non-planar transistors in accordance with an embodiment of the present invention.
FIGS. 3A-3G are illustrations of perspective views of a method of fabricating a device with both planar and non-planar transistors in accordance with an embodiment of the present invention.
A novel CMOS device structure and its method of fabrication are described. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes, etc. in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.
In accordance with an embodiment of the present invention, as illustrated in FIG. 2, three transistors, a planar device 10, a non-planar device 20 having a first channel width and a non-planar device 30 having a second channel width are formed on a single “bulk semiconductor” substrate 201. Transistors 10, 20, and 30 are each coupled to the semiconductor substrate (preventing the floating-body effect) and both planar and non-planar transistor designs have a channel width that can be independently defined to be any value (rather than merely discrete values). By utilizing a method enabling the non-planar transistors 20 and 30 to have various sidewall heights, various channel widths can be specified and the performance requirements of individual portions of a single device can be individually satisfied with any combination of planar transistors (having baseline SCE) and non-planar transistors (having reduced SCE). In a specific embodiment of the present invention, a microprocessor core, comprising a logic region 280, is made up of planar transistors, while a microprocessor cache 281, comprising memory, such as SRAM, is made up of non-planar transistors. In another particular embodiment of the present invention, a portion of a circuit, such as a driver, requiring a large total current is made up of planar transistors having a larger current carrying channel width than the non-planar transistors used in other portions of the circuit.
Embodiments of the non-planar transistor of the present invention include, but are not limited to, dual-gate, FinFET, tri-gate, pi-gate or omega-gate designs. In some embodiments, all non-planar transistors are a “tri-gate” design having a top gate, while in other embodiments all non-planar transistors are a “dual-gate” design having only sidewall gates.
Substrate 201 is comprised of a “bulk semiconductor”, such as, but not limited to, a monocrystalline silicon substrate or a gallium arsenide substrate. In a further embodiment of the present invention the substrate 201 is a bulk silicon semiconductor having a doped epitaxial silicon layer with either p-type or n-type conductivity at an impurity concentration level between 1×1016-1×1019 atoms/cm3. In another embodiment of the present invention, the substrate 201 is a bulk silicon semiconductor substrate having an undoped, or intrinsic epitaxial silicon layer. In a “bulk semiconductor” substrate, unlike a silicon-on-insulator (SOI) substrate, there is no “buried” insulating layer between semiconductor portion used to fabricate the active devices and the semiconductor portion used for handling.
Transistors 10, 20 and 30, as shown in FIG. 2, are comprised of active regions 204, 224 and 244 on the bulk semiconductor substrate. The distance between the isolation regions 210 defines an individual transistor active area width. The active regions 204, 224, 244 have top surfaces, 218, 238, 258 and bottom planes 208, 228, 248, respectively. The bottom planes 208, 228 and 248 are defined to be substantially level with the bottom surface of isolation regions 210, as shown in FIG. 2. For simplicity, semiconductor active regions of FIG. 2 are referred to as “on” the substrate, wherein the substrate is the semiconductor portion below the reference planes 208, 228, and 248. However, the active regions could also be considered “in” the substrate if a different reference plane is chosen. The portion of the active region sidewalls exposed to the gate insulator and control gate electrode is referred as the “gate-coupled sidewall.” As shown in FIG. 2, the isolation regions 210 substantially cover the sidewalls 206 and 207 of the active region 204 of transistor 10. Therefore, the planar, single-gate transistor 10 does not have gate-coupled sidewalls because the distance between the top surface 218 and the bottom plane 208 is roughly equal to the thickness of the bordering isolation regions 210. As such, the active region of transistor 10 has primarily only the top surface 218 coupled to the control gate 213 and the channel width is equal to the width of the top surface 218. For non-planar device 20 however, the portion of the pair sidewalls 226 and 227 extending above the top surface of the adjacent isolation regions 210 is “gate-coupled” and this portion contributes to the total channel width of device 20. As shown in FIG. 2, the “gate-coupled sidewall” height of transistor 20 is equal to the distance between the top surface 238 and the bottom plane 228 minus the thickness of the adjacent isolation regions 210. In an embodiment of the present invention, the height of the gate-coupled sidewalls is substantially equal to the width of the active area top surface 258, as shown in transistor 30 of FIG. 2. In another embodiment of the present invention, the gate-coupled sidewall height of the non-planar transistors is between half the active area width and twice the active area width. In a particular embodiment of the present invention, the non-planar transistors have an active area width and gate-coupled sidewall height less than 30 nanometers, and more particularly, less than 20 nanometers.
The current carrying width of a non-planar transistor in accordance with an embodiment of the present invention can be continuously and individually set to virtually any desired value by varying the height of the gate-coupled sidewall. As pictured in FIG. 2, sidewalls 226 and 227 of transistor 20 have a first gate-coupled sidewall height and sidewalls 246 and 247 of transistor 30 have a second, different gate-coupled sidewall height. Therefore, transistor 20 has a first current carrying channel width and transistor 30 has a second, different, current carrying channel width. Because the current carrying channel width of a non-planar transistor increases as the gate-coupled sidewall height increases, in the embodiment shown in FIG. 2, transistor 20 has a greater channel width than transistor 30. Thus, embodiments of the present invention have non-planar transistors with continuously variable channel widths and thereby provide circuit design flexibility previously unavailable to non-planar transistors.
In embodiments of the present invention no layout efficiency penalty is incurred for non-planar transistors having a channel width greater than a minimum width. Layout efficiency is a ratio of the absolute current carrying width of a non-planar device layout over that of the typical planar device occupying the same layout width. In embodiments of the present invention, the gate-coupled sidewall height of a single non-planar transistor is scaled to provide a desired total current carrying width. Thus, scaling the current carrying width does not rely on incrementing the number of parallel non-planar devices having a discrete channel width. Because the channel width increases with sidewall height rather than top surface area, no additional layout width is required to increase the channel width of a non-planar transistor fabricated in accordance with particular embodiments of the present invention. As such, these particular embodiments improve the packing density of the devices and can have layout efficiencies greater than unity.
As shown in FIG. 2, transistors 10, 20, and 30 have a gate insulator layer 212. In the depicted non-planar embodiments, gate insulator 212 surrounds the active regions, in contact with the exposed semiconductor surfaces. In such embodiments, gate dielectric layer 212 is in contact with the sidewalls as well as the top surfaces of the active regions of transistors 20 and 30, as shown in FIG. 2. In other embodiments, such as in particular FinFET or dual-gate designs, the gate dielectric layer is only in contact with the sidewalls of the active regions, and not the top surfaces 238 and 258 of the non-planar devices. In planar transistor embodiments, such as transistor 10 in FIG. 2, the gate insulator is formed only on the top surface 218. Gate insulator 212 can be of any commonly known dielectric material compatible with the semiconductor surface and the gate electrode 213. In an embodiment of the present invention, the gate dielectric layer is a silicon dioxide (SiO2), silicon oxynitride (SiOxNy) or a silicon nitride (Si3N4) dielectric layer. In one particular embodiment of the present invention, the gate dielectric layer 212 is a silicon oxynitride film formed to a thickness of between 5-20 Å. In another embodiment of the present invention, gate dielectric layer 212 is a high K gate dielectric layer, such as a metal oxide dielectric, such as but not limited to tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, and aluminum oxide. Gate dielectric layer 212 can be other types of high K dielectric, such as, but not limited to, lead zirconium titanate (PZT).
The transistors 10, 20, and 30 have a gate electrode 213, as shown in FIG. 2. In certain embodiments, gate electrode 213 is in contact with gate dielectric layer 212 formed on sidewalls of each of the non-planar transistors 20 and 30. In planar embodiments, such as transistor 10, the gate electrode 213 is in contact with the gate dielectric layer over the top surface 218. Gate electrode 213 has a pair of laterally opposite sidewalls separated by a distance, defining the gate length (Lg) of transistor 10, 20, and 30. In an embodiment of the present invention, Lg of planar transistor 10 and non-planar transistors 20 and 30 are between about 20 nm and about 30 nm. Gate electrode 213 has an effective width equal to the current carrying width of the semiconductor channel controlled by gate electrode 213. In an embodiment of the present invention, effective current carrying width of a non-planar device is greater than the effective width of the planar device. In a particular embodiment, as shown in FIG. 2, the gate-coupled sidewall height of each the sidewalls 226 and 227 is greater than the width of the top surface 218. In this manner, the effective gate electrode width of transistor 20 is greater than the effective gate electrode width of transistor 10. In another embodiment, the effective width of the gate electrode of transistor 10 is greater than that of transistor 20. In still another embodiment of the present invention, the gate electrode physically connects, or is continuous between, a planar device and a non-planar device, multiple planar devices, or multiple non-planar devices.
Gate electrode 213 of FIG. 2 can be formed of any suitable gate electrode material having the appropriate work function. In an embodiment of the present invention, the gate electrode is comprised of polycrystalline silicon. In another embodiment, the gate electrode is comprised of a metal, such as tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, or cobalt silicide. It should also be appreciated that the gate electrode 213 need not necessarily be a single material, but rather can also be a composite stack of thin films such as a metal/polycrystalline silicon electrode.
Transistors 10, 20 and 30, as shown in FIG. 2, each have source regions 216 and drain regions 217. Source regions 216 and drain regions 217 are formed in the active regions on opposite sides of gate electrode 213. The source region 216 and the drain region 217 are formed of the same conductivity type, such as n-type or p-type conductivity, depending on the transistor being an nMOS device or a pMOS device. In an embodiment of the present invention, source region 216 and drain region 217 have a doping concentration of 1×1019-1×1021 atoms/cm3. Source region 216 and drain region 217 can be formed of uniform concentration or can include subregions of different concentrations or doping profiles such as tip regions (e.g., source/drain extensions).
As shown in FIG. 2, transistors 10, 20, and 30 each have a channel region below the gate electrode 213 in the active area located between source regions 216 and drain regions 217. The channel regions of transistors 10, 20, and 30 can be independently doped to an impurity level appropriate for the particular device geometry, gate stack, and performance requirements. When the channel region is doped, it is typically doped to the opposite conductivity type of the source region 216 and the drain region 217. For example, the nMOS device 205 has source and drain regions which are n-type conductivity while the channel region is doped to p-type conductivity. In certain embodiments of the present invention, the channel regions of the non-planar devices 20 and 30 are intrinsic or undoped while the channel region of the planar devices is doped. In an embodiment of the present invention, the channel regions of transistors 10, 20 30 are all doped. When a channel region is doped, it can be doped to a conductivity level of 1×1016-1×1019 atoms/cm3.
A method of fabricating a CMOS device on a bulk substrate in accordance with an embodiment of the present invention as shown in FIG. 2 is illustrated in FIGS. 3A-3G. In a particular embodiment, the fabrication begins with a “bulk” silicon monocrystalline substrate 201. In certain embodiments of the present invention, the substrate 201 is a silicon semiconductor having a doped epitaxial region with either p-type or n-type conductivity with an impurity concentration level of 1×1016-1×1019 atoms/cm3. In another embodiment of the present invention the substrate 201 is a silicon semiconductor having an undoped, or intrinsic epitaxial silicon region. In other embodiments, the bulk substrate 201 is any other well-known semiconductor material, such as gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), gallium phosphide (GaP), indium phosphide (InP), or carbon nanotubes (CNT).
A mask is used to define the active regions of the transistors. The mask can be any well-known material suitable for defining the semiconductor substrate. As shown in FIG. 3A, in an embodiment of the present invention, mask 310 is formed of a dielectric material that has been lithographically defined and etched. In another embodiment, mask 310 is itself a photo-definable material. In a particular embodiment, as shown in FIG. 3A, masking layer 310 can be a composite stack of materials, such as an oxide/nitride stack. If masking layer 310 is a dielectric material, commonly known techniques, such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or even spin on processes may be used to deposit the mask material while commonly known lithography and etching process may be used to define the mask. In an embodiment of the present invention, the minimum lithographic dimension is used to define the width of the mask 310. In another embodiment, the minimum width of the mask 310 is sub-lithographic, formed by commonly known techniques such as dry develop, oxidation/strip, or spacer-based processes. In a particular embodiment of the present invention, the width of mask 310 is less than 30 nanometers, and more particularly, less than 20 nanometers.
As shown in FIG. 3B, once masking layer 310 has been defined, a portion of the semiconductor on bulk substrate 201 is etched using commonly known methods to form recesses or trenches 320 on the substrate in alignment with mask 310. The isolation etch defining the active regions has sufficient depth to isolate individual devices from one another and form a gate-coupled sidewall of adequate height to achieve the maximum desired channel width of the non-planar transistors. In a particular embodiment of the present invention, trenches 320 are etched to a depth equal to the maximum desired non-planar transistor channel width plus about 100 Å to about 500 Å to accommodate a dielectric isolation region. In still another embodiment, the trenches 320 are etched to a depth of approximately 1500 Å to 3000 Å.
As shown in Figure FIG. 3C, the trenches 320 are then filled with a dielectric to form shallow trench isolation (STI) regions 210 on substrate 201. In an embodiment of the present invention, a liner of oxide or nitride on the bottom and sidewalls of the trenches 320 is formed by commonly known methods, such as thermal oxidation or nitridation. Next, the trenches 320 are filled by blanket depositing an oxide over the liner by, for example, a high-density plasma (HDP) chemical vapor deposition process. The deposition process will also form dielectric on the top surfaces of the mask 310. The fill dielectric layer can then be removed from the top of mask 310 by chemical, mechanical, or electrochemical, polishing techniques. The polishing is continued until the mask 310 is revealed, forming isolation regions 210, as shown in FIG. 3C. In a particular embodiment of the present invention, commonly known methods are used to selectively remove the mask 310. In another embodiment, as shown in FIG. 3C, a portion of mask 310 is retained.
If desired, wells can then be selectively formed for pMOS and nMOS transistors. Wells can be formed using any commonly known technique to dope the active regions to a desired impurity concentration. In embodiments of the present invention, active regions 204, 224, and 244 are selectively doped to p-type or n-type conductivity with a concentration level of about 1×1016-1×1019 atoms/cm3 using commonly known masking and ion implantation techniques. In a particular embodiment, the well regions extend into the semiconductor about 500 Å deeper than the bottom planes 208, 228 and 248 of the active regions, shown in FIG. 3C. In embodiments of the present invention, after the selective well implant and mask strip, a commonly known clean, such as HF, removes either the mask 310 or native oxides from the active region top surfaces 218, 238 and 258. In a further embodiment of the present invention, commonly known techniques are then used to either grow or deposit a sacrificial oxide over the top surfaces 218, 238 and 258.
The isolation regions can then be selectively protected with a masking material to allow selective definition of the non-planar devices. In an embodiment, as shown in FIG. 3D, mask 330 is formed in a manner similar to that described above with reference to FIG. 3A. Mask 330 can be either a photo-definable material or a commonly known “hard” mask material that was patterned with common lithography and etch techniques. In the embodiment depicted in FIG. 3D, mask 330 is a photo-definable material, a photo resist. As shown in FIG. 3D, mask 330 is used to protect isolation regions 210 bordering the active region 204 of planar device 10 and active region 224. If desired, additional mask layers may be utilized to selectively protect various other isolation regions.
Next, the isolation regions not protected by a mask are etched back, or recessed, to expose the sidewalls of the active area of the non-planar transistors. As shown in FIG. 3E, isolation regions 210 not protected by mask 330 are etched back without significantly etching the semiconductor active area 224, exposing at least a portion of semiconductor sidewalls 226 and 227. In embodiments where semiconductor active areas are silicon, isolation regions 210 can be recessed with an etchant comprising a fluorine ion, such as HF. In some embodiments, isolation regions 210 are recessed using a commonly known anisotropic etch, such as a plasma or RIE process using an etchant gas such as, but not limited to, C2F6. In a further embodiment, an anisotropic etch can be followed by an isotropic etch, such as a commonly known dry process using a gas such as NF3, or a commonly known wet process such as HF, to completely remove the isolation dielectric from at least a portion of the semiconductor active region sidewalls. In some embodiments, only a portion of the unprotected isolation regions is removed during the recess etch. In a particular embodiment (not pictured), the recess etch is selective to the isolation liner material over the isolation fill material, such that the isolation recess etch is deeper along the liner region immediately adjacent to the active region than in the isolation fill region. In this manner, the width of the recess etch can then be very tightly controlled by the width of the liner, enabling a high transistor packing density.
The isolation regions are selectively recessed by an amount which, when added to a subsequent amount of unselective, or blanket recess etching, achieves the desired final gate-coupled sidewall height for the designed non-planar transistor channel width. A transistor's final gate-coupled sidewall height is determined by the cumulative amount, or depth, the adjacent isolation region is recessed. The isolation recess depth is limited by the demands of device isolation and moderate aspect ratios. For example, subsequent processing can result in inadvertent spacer artifacts if the isolation recess produces aspects ratios that are too aggressive. In a particular embodiment of the present invention, a portion of the isolation region is recessed so that the final isolation thickness is about 200 Å to about 300 Å. In other embodiments, the final isolation thickness is significantly more than about 300 Å. In an embodiment of the present invention, isolation regions 210 are recessed by approximately the same amount as the width dimension of the top surface 238 of the semiconductor active region 224. In other embodiments, the isolation regions 210 are recessed by a significantly larger amount than the width dimension of the top surface 238.
In an embodiment of the present invention, as shown in FIG. 3F, the mask 330 is then removed by commonly known means and a second mask 340 is formed in a fashion similar as that previously discussed in reference to FIG. 3D. Mask 340 protects the active region 224 while the isolation regions 210 surrounding active region 244 are recessed as described above in reference to FIG. 3E. In this embodiment, a different sidewall height can be achieved for 244 than that of 224, thereby forming a non-planar transistor 30 having a different channel width than non-planar transistor 20. It should be appreciated that the process of selectively masking a portion of the isolation regions and recess etching the isolation regions by a specific amount can be repeated a number of times and in a number of ways to achieve a menu of gate-coupled sidewall heights, corresponding to a menu of non-planar transistor channel widths, in accordance with the present invention.
Once the selective isolation recess etches are completed, all isolation masks are removed with commonly known techniques. If desired, a final clean, such as HF, may then be performed on all active regions, further recessing all isolation regions. In a particular embodiment of the present invention, additional sacrificial oxidation and blanket oxide etches or cleans are performed to both improve the semiconductor surface quality and further tailor the shape of the active regions through corner rounding, feature shrinking, etc.
A gate dielectric can then be formed over the active regions in a manner dependent on the type of non-planar device (dual-gate, tri-gate, etc.). In a tri-gate embodiment of the present invention, as shown in FIG. 3G, a gate dielectric layer 212 is formed on the top surface of each of the active regions 204, 224 and 224, as well as on, or adjacent to, the exposed sidewalls 226, 227 and 246, 247 of the non-planar devices. In certain embodiments, such as dual-gate embodiments, the gate dielectric is not formed on the top surfaces of the non-planar active regions. The gate dielectric can be a deposited dielectric or a grown dielectric. In an embodiment of the present invention, the gate dielectric layer 212 is a silicon dioxide dielectric film grown with a dry/wet oxidation process. In an embodiment of the present invention, the gate dielectric film 212 is a deposited high dielectric constant (high-K) metal oxide dielectric, such as tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, or another high-K dielectric, such as barium strontium titanate (BST). A high-K film can be formed by well-known techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
A gate electrode is then formed over each active region. In an embodiment of the present invention, the gate electrode 213, as shown in FIG. 3G, is formed on the gate dielectric layer 212 over the top surfaces 218, 238, 258 and is formed on or adjacent to the gate dielectric 212 along the sidewalls 226, 227 and 246, 247. The gate electrode can be formed to a thickness between 200-3000 Å. In particular embodiments, the thickness of the gate electrode material is constrained by the depth of the isolation region recess etch because the gate electrode material will tend to form a conductive spacer along the topography generated by the recess etch. For such embodiments, over-etching of the gate electrode material can prevent such spacer artifacts if the isolation recess depth is less than the thickness of the gate electrode material. In an embodiment, the gate electrode has a thickness of at least three times the gate-coupled sidewall height (previously defined as the exposed portion of the active area sidewall). In an embodiment of the present invention, the gate electrode is comprised of polycrystalline silicon. In some embodiments of the present invention, the gate material is metal such as, but not limited to, tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, or cobalt silicide. In still other embodiments, the electrode is formed from a composite of poly-silicon and metal. In an embodiment of the present invention, gate electrode 213 is formed by well-known techniques, such as blanket depositing a gate electrode material over the substrate and then patterning the gate electrode material. In other embodiments of the present invention, the gate electrode is formed using “replacement gate” methods. In such embodiments, the gate electrode utilizes a fill and polish technique similar to those commonly employed in damascene metallization technology, whereby the recessed isolation regions may be completely filled with gate electrode material.
In an embodiment of the present invention, source regions 216 and drain regions 217 for transistors 10, 20, and 30 are formed in the active regions on opposite sides of gate electrode 213, as shown in FIG. 3G. For a pMOS transistor, the active region is doped to p-type conductivity and to a concentration of 1×1019-1×1021 atoms/cm3. For an nMOS transistor, the active is doped with n-type conductivity ions to a concentration of 1×1019-1×1021 atoms/cm3. At this point the CMOS transistor of the present invention is substantially complete and only device interconnection remains.
Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as particularly graceful implementations of the claimed invention.
a third pair of source/drain regions on opposite sides of the third gate electrode.
2. The microprocessor of claim 1, wherein a top surface of the third active region is coplanar with both the first second active regions.
3. The microprocessor of claim 1, wherein the planar transistor has a larger current carrying channel width than at least one of the first and second non-planar transistors.
4. The microprocessor of claim 1, wherein the channel regions of the first and second non-planar transistors are undoped and wherein the channel region of the planar transistor is doped.
KR101263648B1 (en) * 2007-08-31 2013-05-21 삼성전자주식회사 Fin field effect transistor and its production method.
Auth, Christopher P., et al., "Vertical, Fully-Depleted, Surrounding Gate MOSFETs on sub-0.1 mum Thick Silicon Pillars," 54th Annual Device Research Conference Digest, 1996, 4 pgs.
Auth, Christopher P., et al., "Vertical, Fully-Depleted, Surrounding Gate MOSFETs on sub-0.1 μm Thick Silicon Pillars," 54th Annual Device Research Conference Digest, 1996, 4 pgs.
Buchanan, D. A., et al., "Fabrication of Midgap Metal Gates Compatible With Ultrathin Dielectrics," Applied Physics Letters, vol. 73.12, Sep. 21, 1998, 3 pgs.
Burenkov, A., et al., "Corner Effect in Double and Triple Gate FinFETs," IEEE, 2003, 4 pgs.
Chang, L., et al., "CMOS Circuit Performance Enhancement by Surface Orientation Optimization," IEEE Transactions on Electron Devices, vol. 51, No. 10, Oct. 2004, 7 pgs.
Chang, S. T., et al., "3-D Simulation of Strained Si/SiGe Heterojunction FinFETs," Semiconductor Device Research Symposium, Dec. 2003, 2 pgs.
Chau, et al., "Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-gate (Invited Paper)", Components Research, Logic Technology Development, Intel Corporation, Hillsboro, OR, 2 pages, filed Sep. 21, 2011.
Chau, Robert, "Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors," Components Research, Intel Corporation, 2004, 3 pgs.
Choi, et al., "A Spacer Patterning Technology for Nanoscale CMOS," IEEE, (49)3, Mar. 2002, 6 pgs.
Choi, et al., "Sub-20nm CMOS FinFET Technologies," IEEE, IEDM, 2001, 4 pgs.
Final Office Action for U.S. Appl. No. 11/648,521 mailed Jan. 8, 2010, 11 pgs.
Final Office Action from U.S. Appl. No. 11/080,765 mailed Nov. 13, 2007, 13 pgs.
Final Office Action from U.S. Appl. No. 11/154,138 mailed Dec. 8, 2009, 11 pgs.
Final Office Action from U.S. Appl. No. 11/158,661 mailed Jan. 15, 2008, 25 pgs.
Final Office Action from U.S. Appl. No. 11/240,487 mailed Sep. 21, 2009, 22 pgs.
Final Office Action from U.S. Appl. No. 11/322,795 mailed Jan. 13, 2010, 12 pgs.
Final Office Action from U.S. Appl. No. 11/828,290, mailed Feb. 17, 2010 18 pgs.
Final Office Action from U.S. Appl. No. 12/025,665 mailed Jun. 10, 2009, 9 pgs.
International Preliminary Report on Patentability from PCT Application No. PCT/US2006/024516 mailed Jan. 10, 2008, 11 pgs.
International Preliminary Report on Patentability from PCT/US/2006/037634, mailed Apr. 10, 2008, 12 pgs.
International Preliminary Report on Patentability from PCT/US2005/010505 mailed Oct. 12, 2006, 16 pgs.
International Search Report & Written Opinion from PCT/US2004/032442 mailed on Jun. 16, 2005, 12 pgs.
International Search Report & Written Opinion from PCT/US2005/000947 mailed on May 3, 2005, 14 pgs.
International Search Report & Written Opinion from PCT/US2005/033439 mailed on Jan. 31, 2006, 7 pgs.
International Search Report & Written Opinion from PCT/US2005/035380 mailed on Feb. 13, 2006, 14 pgs.
International Search Report & Written Opinion from PCT/US2005/037169 mailed on Feb. 23, 2006, 11 pgs.
International Search Report & Written Opinion from PCT/US2006/000378 mailed on May 24, 2006, 11 pgs.
International Search Report & Written Opinion from PCT/US2006/024516 mailed on Jan. 10, 2007, 18 pgs.
International Search Report & Written Opinion from PCT/US2006/025751 mailed on Dec. 6, 2006, 14 pgs.
International Search Report & Written Opinion from PCT/US2006/037634 mailed on May 31, 2007, 21 pgs.
International Search Report & Written Opinion from PCT/US2006/037643 mailed on Jan. 24, 2007, 14 pgs.
International Search Report and Written Opinion from PCT/US2004/032442 mailed Jun. 16, 2005, 22 pgs.
International Search Report and Written Opinion from PCT/US2005/010505 mailed Aug. 26, 2005, 24 pgs.
International Search Report and Written Opinion from PCT/US2005/010505 mailed on Aug. 26, 2005, 24 pgs.
International Search Report and Written Opinion from PCT/US2005/020339 mailed on Oct. 4, 2005, 12 pgs.
International Search Report from PCT Application No. PCT/US2003/40320 mailed Jun. 2, 2004, 6 pgs.
International Search Report from PCT/US03/26242 mailed on Jan. 26, 2004, 8 pgs.
International Search Report from PCT/US03/39727 mailed on Apr. 27, 2004, 6 pgs.
International Search Report from PCT/US03/40320 mailed Jun. 2, 2004, 6 pgs.
International Search report from PCT/US2003/39727 mailed Apr. 27, 2004, 6 pgs.
IPO Search Report for Application No. 094136197, date mailed Sep. 19, 2008, 1 pg.
Lide, David R., "Properties of Semiconductors", CRC Handbook of Chemistry and Physics, Internet version 2007, (87th edition), David R. Lide-Editor; Taylor and Francis., pp. 12-77-12-89.
Lide, David R., "Properties of Semiconductors", CRC Handbook of Chemistry and Physics, Internet version 2007, (87th edition), David R. Lide—Editor; Taylor and Francis., pp. 12-77-12-89.
Non-Final Office Action for U.S. Appl. No. 11/240,440 Mailed May 12, 2010, 8 Pages.
Non-Final Office Action from U.S. Appl. No. 11/322,795 mailed Jul. 28, 2009, 18 pgs.
Non-Final Office Action from U.S. Appl. No. 11/855,823, mailed Jul. 23, 2009, 31 pgs.
Notice of Preliminary Rejection from Korean Patent Application No. 10-2007-7030988 incl. translation, Sep. 14, 2009, 11 pgs.
Office Action for Application No. 200680023301.X dated May 23, 2011, 11 pages.
Office Action for European Application No. 03817697.0 mailed Nov. 22, 2010, 4 pgs.
Office Action for German Patent Application No. 11 2006 003 576.2-33 mailed Nov. 11, 2008, 6 pgs.
Office Action for German Patent Application No. 112006001735.7 with translation mailed Oct. 20, 2009, 6 pgs.
Office Action for Japanese Application No. 2006-549560 mailed Aug. 31, 2010, 7 pgs.
Office Action for Korean Application No. 10-2008-7007431 mailed on Dec. 30, 2010, 6 pgs.
Office Action for U.S. Appl. No. 11/064,996 mailed Jun. 27, 2008, 12 pages.
Office Action for U.S. Appl. No. 11/064,996 mailed Mar. 13, 2007, 19 pages.
Office Action for U.S. Appl. No. 11/064,996 mailed Mar. 14, 2008, 13 pages.
Office Action for U.S. Appl. No. 11/064,996 mailed Sep. 4, 2007, 11 pages.
Office Action for U.S. Appl. No. 11/648,521 mailed Aug. 5, 2009, 12 pgs.
Office Action for U.S. Appl. No. 11/648,521 mailed Jan. 4, 2011, 14 pgs.
Office Action for U.S. Appl. No. 12/343,400 mailed Dec. 30, 2009, 12 pages.
Office Action from Chinese Patent Application No. 200680023301.X mailed Jun. 26, 2009, 11 pgs.
Office Action from European Patent Application No. 03817699.6 mailed Aug. 29, 2007, 3 pgs.
Office Action from European Patent Application No. 05711376.3 mailed Jan. 11, 2010, 5 pgs.
Office Action from European Patent Application No. 06815547.2, mailed Sep. 9, 2008, 3 pgs.
Office Action from Korean Patent Application No. 10-2007-7030988 mailed Mar. 12, 2010, 3 pgs.
Office Action from Taiwan Patent Application No. 95122087 mailed Dec. 16, 2008, 14 pgs.
Office Action from Taiwan Patent Application No. 95122087 mailed Jun. 20, 2008, 8 pgs.
Office Action from Taiwan Patent Application No. 95123858, dated Oct. 9, 2008, 9 pgs.
Office Action from Taiwan Patent Application No. 95123858-translation, mailed Mar. 3, 2009, 10 pgs.
Office Action from Taiwan Patent Application No. 95123858—translation, mailed Mar. 3, 2009, 10 pgs.
Office Action from Taiwan Patent Application No. 95135820 mailed Oct. 22, 2009, 3 pgs.
Office Action from Taiwan Patent Application No. 95135820 mailed on Jan. 9, 2009, 14 pgs.
Office Action from Taiwanese Patent Application No. 95134963 issued Jun. 1, 2009; incl. translation, 15 pgs.
Office Action from U.S. Appl. No. 10/227,068 mailed Dec. 18, 2006, 25 pgs.
Office Action from U.S. Appl. No. 10/703,316 mailed Dec. 15, 2006, 22 pgs.
Office Action from U.S. Appl. No. 10/973,228 mailed Feb. 2, 2010, 8 pgs.
Office Action from U.S. Appl. No. 11/080,765 mailed May 2, 2007, 47 pgs.
Office Action from U.S. Appl. No. 11/234,014 mailed Jan. 23, 2008, 9 pgs.
Office Action from U.S. Appl. No. 11/240,440 mailed May 12, 2010, 8 pgs.
Office Action from U.S. Appl. No. 11/240,487 mailed Dec. 11, 2009, 9 pgs.
Office Action from U.S. Appl. No. 11/240,487 mailed Mar. 17, 2009, 13 pgs.
Office Action from U.S. Appl. No. 11/322,795 mailed Mar. 4, 2009, 12 pgs.
Office Action from U.S. Appl. No. 11/855,823 mailed Mar. 15, 2010, 31 pgs.
Office Action from U.S. Appl. No. 11/855,823, mailed Dec. 30, 2008, 18 pgs.
Office Action from U.S. Appl. No. 12/025,665 mailed on Nov. 12, 2008, 7 pgs.
Office Action from U.S. Appl. No. 12/114,227 mailed Mar. 30, 2010, 10 pgs.
Second Office Action for Chinese Patent Application No. 200680021817.0 mailed Dec. 11, 2009, 10 pgs.
Third Office Action for Chinese Patent Application No. 200580032314.9 mailed Jan. 29, 2010, 13 pgs.
Written Opinion from Singapore Patent Application No. 200507013-1 issued May 18, 2007, 4 pgs.
Written Opinion from Singapore Patent Application No. 200604766-6 mailed Apr. 4, 2008, 4 pgs.

References: Application No. 094136197
 Application No. 10
 Application No. 200680023301
 Application No. 03817697
 Application No. 11
 Application No. 112006001735
 Application No. 2006
 Application No. 10
 Application No. 200680023301
 Application No. 03817699
 Application No. 05711376
 Application No. 06815547
 Application No. 10
 Application No. 95122087
 Application No. 95122087
 Application No. 95123858
 Application No. 95123858
 Application No. 95123858
 Application No. 95135820
 Application No. 95135820
 Application No. 95134963
 Application No. 200680021817
 Application No. 200580032314
 Application No. 200507013
 Application No. 200604766