Source: http://www.chiplist.com/ChipList1/chiplist.long.html
Timestamp: 2019-04-22 13:19:22+00:00

Document:
Since there are a lot of questions about the differences between the various chips used in the IBM PC, IBM PC/XT, IBM PC/AT, IBM PS/2 and compatibles, this list, containing their CPUs and NPXs, has been compiled for the benefit of the Net community. I hope it can answer some questions.
This list is the result of collecting many snippets of information from the Web, USENET News and data books. Furthermore, various contributors and others have helped to make this list to what it is today. Thank you all.
Date: often the week number and the year of manufacturing.
speed: 10, 15, 20, 40, 60, 70, 80, 100, 120, 150 ns.
Orientation: indicated by a hole or a dot; from this indication the pin numbering starts contra clock-wise with number 1.
For microprocessors at boot the chip mask revision number is often left in one of the control registers.
UMC: "UMC UMC UMC "
CERDIP (CERamic Dual In-line Package).
PQFP (Plastic Quad Flat Package): surface mounted.
SQFP (Shrink Quad Flat Package): surface mounted, thermally enhanced.
MQFP (Metal Quad Flat Package).
CPGA (Ceramic Pin Grid Array).
PPGA (Plastic Pin Grid Array).
SEC module (Single Edge Contact): consists of a PCB containing the processor chip and the level 2 cache chips.
ZIF sockets (Zero Insertion Force) have a handle to fasten and loosen the chip to and from its socket.
The BGA system consists of balls on the chip package that fit into grips on the socket.
BallNest provides a four-fingered "nest" for each ball termination of the device to be socketed. On top of the BGA device a socket lid must be placed to hold it down. The BallLock system grips the balls of the BGA device, eliminating the need for a lid. A ZIF (Zero Insertion Force) version of the BGA socket is being worked on.
411000 1 M x 1 (1987, 1988).
SIMM (Single In-line Memory Module) (Wang): contains a complete RAM bank. Mac SIMMs are only 8 bits wide; they don't contain a parity bit. However, there are Personal Computers around in which parity checking can be disabled, that can operate with 8 bit SIMMs.
If the correct refresh is supplied, SIMMs with a different number of chips and different speed can be used together.
SIP (Single In-line Package): contains a complete RAM bank.
The orientation of SIMMs and SIPs is indicated by a hole. Starting from this indication the numbering of the pins starts with number 1. Apart from the pins there is no difference at all between SIMMs and SIPs.
The normal SIMMs and SIPs have 30 pads/pins. There are also 36 pin SIMMs and SIPs. The extra pins are used for speed detection by the motherboard.
There are also 72 pin SIMMs. These are 32 bits and 4 parity bits wide. 4 pins are assigned for speed detection. They are mostly used in 486 class and higher Personal Computers.
Capacity: 1, 2, 4, 8, 16, 32 Mbytes.
DIMM (Dual In-line Memory Module): 64 bit memory module.
They have 168 pads. They can only be found in the newer Pentium class Personal Computers.
Memory banks, consisting of 1, 2, or 4 sockets, should always be filled completely. The number of sockets in a bank depends on the width of the memory module and the width of the processor's address bus. For example, a bank in a 486 class motherboard (32 bit address bus) might need four 8 bit SIMMs, or a single 32 bit SIMM.
EDO RAM (Extended Data Output): faster access method.
This can only be found in the newer Pentium class Personal Computers.
SDRAM (Synchronous DRAM): clock synchronized with the processor busses.
RTL (Resistor-Transistor Logic): SSI (Small Scale Integration).
TTL (Transistor-Transistor Logic) (Texas Instruments, 1965): bipolar, SSI, MSI (Medium Scale Integration), LSI (Large Scale Integration).
7400 series: 0 - 70 C.
5400 series: -55 - 125 C (military).
54ALS00, 74ALS00: Advanced Low power Schottky.
I2L (Integrated Injection Logic) (1972): bipolar, LSI, VLSI (Very Large Scale Integration).
Propagation time: 20 - 50 ns.
ECL (Emitter Coupled Logic, Current Mode Logic): bipolar.
Propagation time: 0.5 - 2 ns.
Dissipation: 3 - 10 times higher than TTL.
MOS (Metal Oxide Semiconductor): FET (Field-Effect Transistors).
PMOS (Positive-channel MOS): LSI, VLSI.
NMOS (Negative-channel MOS): LSI, VLSI.
HMOS (High performance n-channel MOS): LSI, VLSI.
CMOS (Complementary MOS): LSI, ULSI (Ultra Large Scale Integration).
Better current management combining n- and p-channels.
Developed by military for radiation hardness in space and tactical/strategic nuclear warfare environments.
For a long time 0.6 micron geometries were thought to be a limit imposed by the electron microscopes used for mask alignment, but then the X-ray lithography was invented.
Now, the EUV LLC (EUV Limited Liability Company), consisting of Intel, AMD, and Motorola, and the VNL (Virtual National Laboratory), are working on an advanced lithography research project EUV (Extreme Ultra Violet), which will allow industries to etch circuit lines smaller than 0.1 micron widths. The EUV technology uses mirrors instead of lenses for the mask light exposure.
In September 1997 IBM started manufacturing chips with copper metal layers instead of aluminium. Copper is a better conductor, and allows for circuit lines smaller than 0.1 micron widths. Corrosion of the silicium by the copper is avoided by using a fusion barrier sealer in between.
JEDEC was first known for their DIP definitions for memory chips.
JEDEC has suggested a new standard of 3.3 V for all electronic components, including CPUs. CPUs operating at 3.3 V consume less than 50 % of the power of their 5 V equivalents. Intel currently uses a manufacturing process with a resolution of 0.8 micron, but is starting production with a 0.6 micron process. This produces chips that can only operate reliably at 3.3 V, which means that all its future CPUs are likely to operate only at this lower voltage.
In July 1997 Intel acquired Chips & Technologies.
European Centre: +44 (0) 1793-432509.
Intel European Centre: +44 (0) 1793-431155.
In 1996 AMD acquired NexGen.
Chips & Technologies has dropped its development of X86 clones.
Acquired by Intel in July 1997.
Acquired by National Semiconductor in July 1997.
Cyrix fax-bak service: 1-800-46-CYRIX (1-800-462-9749).
12 bit address bus (multiplexed).
Separate address space for instructions and data.
Package: 16 pin ceramic DIP (Dual In-line Package).
Package: 24 pin ceramic DIP (Dual In-line Package).
14 bit address bus (multiplexed).
Package: 18 pin ceramic DIP (Dual In-line Package).
Intel i8008 CPU with stack.
Intel i8080 CPU: 2 MHz, 6 micron PMOS.
Intel i8080A-2 CPU: 2.67 MHz, NMOS.
Intel i8080A-1 CPU: 3.125 MHz, NMOS.
Intel iM8080A CPU: military (-55 - 125 C).
Package: 40 pin CERDIP (CERamic Dual In-line Package).
Intel i8080 CPU: 1973, PMOS, 4500 transistors.
Intel i8080A CPU: 1976, NMOS, 4000 transistors.
Intel i8080 CPU upward instruction compatible.
Not Intel i8080 CPU pin compatible.
Extra interrupt lines, including NMI (Non-Maskable Interrupt).
Data and address bus are multiplexed.
Intel i8085A CPU: 3 MHz, NMOS.
Intel iM8085A CPU: military (-55 - 125 C), NMOS.
Intel i8085AH-2 CPU: 5 MHz, HMOS.
Intel i8085AH-1 CPU: 6 MHz, HMOS.
Intel iM8085AH CPU: military (-55 - 125 C), HMOS.
1 Mbyte address space, 64 kbyte per segment.
Technology: 3.0 micron, later 2.0 micron.
16 bit internal data bus.
16 bit external data bus.
Intel i8086A CPU: 4 MHz, NMOS.
Intel i8086AH CPU: 5 MHz, HMOS.
Intel i8086AH-2 CPU: 8 MHz, HMOS.
Intel i8086AH-1 CPU: 10 MHz, HMOS.
Intel i80C86A CPU: 5 MHz, CMOS.
Intel i80C86A-2 CPU: 8 MHz, CMOS.
Intel i80C86A-1 CPU: 10 MHz, CMOS.
Intel iM80C86A CPU: military (-55 - 125 C).
Used in IBM PC clones, IBM PC/XT clones.
8 bit external data bus (can co-operate with all Intel i8085 CPU periphery chips).
Intel i80C88A CPU: 5 MHz, CMOS.
Intel i80C88A-2 CPU: 8 MHz, CMOS.
Intel i80C88A-1 CPU: 10 MHz, CMOS.
Used in IBM PC (Personal Computer), IBM PC/XT (eXtended Technology).
Intel i8086 CPU instruction/pin compatible.
AMD Am8086-1 CPU: 10 MHz, HMOS.
AMD Am80C86 CPU: 5 MHz, CMOS.
AMD Am80C86-2 CPU: 8 MHz, CMOS.
AMD Am80C86-1 CPU: 10 MHz, CMOS.
Intel i8088 CPU instruction/pin compatible.
AMD Am8088 CPU: 5 MHz, HMOS.
AMD Am8088-2 CPU: 8 MHz, HMOS.
AMD Am8088-1 CPU: 10 MHz, HMOS.
Harris HS80C86/883 CPU: 5 MHz, CMOS.
Harris HS80C86-2/883 CPU: 8 MHz, CMOS.
Harris HS80C86-1/883 CPU: 10 MHz, CMOS.
Harris HSMD80C86 CPU: military (-55 - 125 C), CMOS.
Harris HS80C88/883 CPU: 5 MHz, CMOS.
Harris HS80C88-2/883 CPU: 8 MHz, CMOS.
Harris HS80C88-1/883 CPU: 10 MHz, CMOS.
Siemens SAB8086-2P CPU: 8 MHz.
Siemens SAB8086-1P CPU: 10 MHz.
Siemens SAB8088-I-P CPU: 16 MHz.
Contemporary 16 bit CPUs to 8086/8088 were Zilog Z8000 CPU, Fairchild 9445 CPU, Texas Instruments TI9900 CPU and Mil-Std 1750A CPU. Last is reason DOD (Department Of Defence) contractors were not interested in 8086/8088. Mil-Std 1750A CPU was specified in all contracts of 1979 - 1984 period.
Texas Instruments TI9900 CPU was probably the best of the lot, but Texas Instruments considered it a closed architecture, so no-one used it.
extra instructions: all of the Intel i80286 CPU real mode instructions.
The Intel i80C188 CPU has no NPX interface.
Intel i80186 CPU: 6 MHz, NMOS.
Intel i80186 CPU: 8 MHz, NMOS.
Intel i80186 CPU: 10 MHz, NMOS.
Intel i80C186 CPU: 10 MHz, CMOS.
Intel i80C186-12 CPU: 12.5 MHz, CMOS.
Intel i80C186-16 CPU: 16 MHz, CMOS.
Intel iM80C186 CPU: military (-55 - 125 C), 10 MHz, CMOS.
Intel iM80C186-12 CPU: military (-55 - 125 C), 12.5 MHz, CMOS.
Intel i80C186XL20 CPU: 20 MHz, CMOS.
Intel i80C186EA20 CPU: 20 MHz, CMOS.
Intel i80C186EB-16 CPU: 16 MHz, CMOS.
Intel i80C186EC-16 CPU: 16 MHz, CMOS.
Intel i80188 CPU: 6 MHz, NMOS.
Intel i80188 CPU: 8 MHz, NMOS.
Intel i80C188 CPU: 10 MHz, CMOS.
Intel i80C188-12 CPU: 12.5 MHz, CMOS.
Intel i80C188-16 CPU: 16 MHz, CMOS.
Intel i80C188XL20 CPU: 20 MHz, CMOS.
Intel i80C188EA20 CPU: 20 MHz, CMOS.
Intel i80C188EB-16 CPU: 16 MHz, CMOS.
Intel i80C188EC-16 CPU: 16 MHz, CMOS.
Intel i80186/i80188 CPU upward instruction compatible.
Intel i80186 CPU bus interface.
16 MHz: 3.3 V, 1995.
AMD Embedded Processors E86 Family.
Intel i80188 CPU bus interface.
Intel i80286 CPU style bus interface.
Intel i80186 CPU / Intel i80188 CPU upward instruction compatible.
fewer CPI (Cycles Per Instruction).
Intel i8086 CPU pin compatible.
80 pin PFP (QFP (Quad Flat Package)).
speeds up to 16 MHz.
Intel i8088 CPU pin compatible.
Intel i80186 CPU instruction/pin compatible.
Siemens SAB80186-N CPU: 8 MHz.
Siemens SAB80186-1 CPU: 10 MHz.
Siemens SAB80186-16 CPU: 16 MHz.
Intel i80188 CPU instruction/pin compatible.
Siemens SAB80188-N CPU: 8 MHz.
Siemens SAB80188-1N CPU: 10 MHz.
Real mode: Intel i8086/i8088 CPU mode.
8 MHz: PLCC (Plastic Leaded Chip Carrier).
10 MHz: PLCC (Plastic Leaded Chip Carrier).
12 MHz: PLCC (Plastic Leaded Chip Carrier).
16 MHz: PLCC (Plastic Leaded Chip Carrier).
Package: 68 pin CERDIP (CERamic Dual In-line Package).
Used in IBM PC/AT (Advanced Technology).
Intel i80286 CPU instruction/pin compatible.
AMD Am80286 CPU: 8 MHz, HMOS.
AMD Am80286 CPU: 10 MHz, HMOS.
AMD Am80286 CPU: 12 MHz, HMOS.
AMD Am80286 CPU: 16 MHz, HMOS.
AMD Am80C286 CPU: 10 MHz, CMOS.
AMD Am80C286 CPU: 12 MHz, CMOS.
AMD Am80C286 CPU: 16 MHz, CMOS.
AMD Am80C286 CPU: 20 MHz, CMOS.
AMD Am80EC286 CPU: low power version of the AMD Am80C286 CPU.
Siemens SAB80286 CPU: 8 MHz.
Siemens SAB80286-1-N CPU: 10 MHz.
Siemens SAB80286-12-N CPU: 12 MHz.
Siemens SAB80286-16 CPU: 16 MHz.
Virtual 8086 mode (V86 mode): parallel simulation of more virtual Intel i8086/i8088 CPUs.
POPAD bug: EAX register is trashed when there is a memory access instruction directly after the POPAD instruction.
32 bit internal data bus.
32 bit external data bus (DX: Double-word eXternal).
12 MHz: first 16 MHz CPUs had clock speed troubles and were released as 12 MHz items.
16 MHz: early Intel i80386 CPUs had a bug in the 32 bit MUL instruction (MUL bug); it is fixed in the double-sigma step level, no longer available.
20 MHz: no longer available.
33 MHz: 2000 mW, iCOMP 68.
Package: 132 pin PGA (Pin Grid Array).
ID: AH=0x03 (Intel i80386 CPU).
step level Ex, Fx: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).
16 bit external data bus (SX: Single-word eXternal).
Package: 100 pin QFP (Quad Flat Package).
step level C, D, E: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).
Low power version of the Intel i80386SX CPU: SMM (System Management Mode).
Extra pins assigned for power management.
ISA-bus driver (Industry Standard Architecture).
Intel i80386SX CPU upward pin compatible.
Other package: 196 pin surface mounted QFP (Quad Flat Package) (KC80386SLB1A, ISA SX621).
step level B1: DH = 0x43 (model ID, family ID), DL = 0x11 (revision).
Intel i80386 CPU with FPU (Floating Point Unit) (same implementation as Intel i80486DX CPU).
The Intel RapidCAD CPU consists of a set of 2 chips. The Intel RapidCAD-1 (132 pin PGA) contains the Intel i80386 CPU with FPU. The Intel RapidCAD-2 (68 pin PGA) fits in the Intel i80387DX NPX socket and contains a PLA for the FERR signal generation.
Intel i80386DX CPU / Intel i80387DX NPX pin compatible.
33 MHz: 2.6 W typical, 3500 mW max.
Technology: 0.8 micron CHMOS IV.
step level B: DH = 0x03 (family ID), DL = 0x41 (model ID, revision).
Embedded version of Intel i80386SX CPU.
Intel i80386SX CPU pin compatible.
Intel i80386 CPU instruction set, 32 bit protected mode only, no real mode, no V86 mode, no 286 mode.
No MMU (Memory Management Unit).
88 pin PGA (Pin Grid Array).
step level B: DH = 0x33 (model ID, family ID), DL = 0x08 (revision).
16 MHz: 5 V, 0-16 MHz, 1993.
20 MHz: 5 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.
military (-55 - 125 C).
ID: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).
12 MHz: 3 V, 0-12 MHz, 1993.
20 MHz: 3.3 V, 0-20 MHz, 1993.
ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).
16 MHz: 3 V, 0-16 MHz, 1994.
20 MHz: 3.3 V, 0-20 MHz, 1994.
25 MHz: 5 V, 0-25 MHz, 1994.
Intel i80386 CPU instruction compatible.
Same core and microcode as Intel i80386 CPU.
Intel i80386DX CPU instruction/pin compatible.
Intel i80386DX IV CPU microcode.
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).
Low power version of AMD Am386DX CPU.
Intel i80386DX CPU upward pin compatible.
Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version of AMD Am386DX CPU.
25 MHz: 2-25 MHz, no longer available.
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).
Low power version of AMD Am386SX CPU.
Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version of AMD Am386SX CPU.
Embedded static version of the AMD Am386DX CPU.
Embedded static version of the AMD Am386SX CPU.
Some instructions are executed faster than when executed by the Intel i80386 CPU.
To be enabled via software.
Intel i80386SX CPU upward pin compatible (100 pin MQFP (Metal Quad Flat Package)).
ID: step level A: DH = 0xA3 (model ID, family ID), DL = 0xXX (revision).
Intel i80386 CPU instruction compatible, including undocumented LOADALL386 instruction.
Co-operation with an appropriate NPX causes communication problems, which causes the over-all performance to drop below that of an Intel i80386DX CPU with NPX.
Intel i80386DX CPU pin compatible.
32 bit external data bus.
Not Intel i80386DX CPU pin compatible.
Package: 144 pin PGA (Pin Grid Array).
Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386 CPU bus interface.
Intel i80386 CPU core, enhanced by IBM.
16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).
Clock doubled version of the IBM 486DLC CPU.
Not Intel i80386SX CPU pin compatible.
20 MHz: 3.3 V, 1.0 W.
25 MHz: 3.3 V, 1.3 W.
ID: step level A: DH = 0xA4 (model ID, family ID), DL = 0xXX (revision).
Clock doubled version of the IBM 486SLC CPU.
16 kbyte cache: 4-way set-associative, write-through, 16 byte line size.
Intel i80386SX CPU pin compatible (100 pin MQFP (Metal Quad Flat Package)).
25/50 MHz: 1993, 2.3 W.
step level Bx: DH = 0xA4 (model ID, family ID), DL = 0x2X (revision).
Intel i80486 CPU core and microcode, no FPU.
Power management: SMM (System Management Mode).
Intel i80386DX CPU upward pin compatible / AMD Am386DXL/Am386DXLV CPU pin compatible (132 pin MQFP (Metal Quad Flat Package)).
Clock doubled version of the IBM 486BLX CPU.
Clock tripled version of the IBM 486BLX CPU.
ID: step level A: DH = 0x84 (model ID, family ID), DL = 0xXX (revision).
Own core (clean room): not 100% compatible.
First generation 40 MHz CPUs had a bug: using a NPX (Cyrix Fasmath EMC87 NPX, Cyrix FasMath Cx83D87 NPX (until November 1991), IIT IIT-3C87 NPX) caused crashes. These are caused by synchronisation errors in FSAVE and FSTOR instructions. Later, improved CPUs have an AB prefix printed in the lower right corner. The Cyrix FasMath Cx387+ NPX (European name for Cyrix FasMath Cx83D87 NPX from November 1991) causes no trouble when co-operating with a bad Cyrix Cx486DLC CPU.
maximum of 4 non-cachable areas.
85% with support of cache by motherboard (Cache Coherency Support).
Contains a fast extra 16x16 bit multiplier.
DH = 0x04 (family ID), DL = 0x2X (revision).
Low power (SMM: System Management Mode) version of Cyrix Cx486SLC CPU.
Low power (SMM: System Management Mode), low voltage (3.3 V) version of Cyrix Cx486SLC CPU.
Differences in execution time of various instructions, average CPI (Cycles Per Instruction) about equal.
Clock doubled version of the Cyrix Cx486DLC CPU.
The chip is placed over the surface mounted 80386SX CPU. The original CPU is disabled by using the FLOAT pin. Older 16 MHz 80386SX CPUs can not be upgraded (Cyrix can supply a compatibility test program).
Clock doubled version of the Cyrix Cx486DRx CPU.
early Compaq Deskpro 386/16 MHz systems with 287 NPX (NPX to be removed).
Clock doubled version of the Cyrix Cx486SRx CPU.
In fact a Cyrix Cx486DLC CPU with some additional hardware on a little PCB that fits in a PGA (Pin Grid Array).
Clock doubled version of the Cyrix Cx486DRu CPU.
Clock doubled version of the Cyrix Cx486SRu CPU.
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
Intel i80386DX CPU bus interface.
8 kbyte cache: write-through, 2-way set-associative, 1024 sets, 4 bytes per line.
Package: ceramic PGA (Pin Grid Array).
Low power (3.3 V) version of the Texas Instruments TI486SXL-S-GA CPU.
Clock doubled version of the Texas Instruments TI486SXL-S-GA CPU.
Clock doubled, low power (3.3 V) version of the Texas Instruments TI486SXL-S-GA CPU.
Intel i80386SX CPU bus interface.
Package: QFP (Quad Flat Package).
Low power (3.3 V) version of the Texas Instruments TI486SXLC-PAF CPU.
Clock doubled version of the Texas Instruments TI486SXLC-PAF CPU.
Clock doubled, low power (3.3 V) version of the Texas Instruments TI486SXLC-PAF CPU.
Rio Grande series: Potomac series follow-up.
Intel i80386 CPU upward instruction compatible.
8 kbyte unified cache: write-through, 4-way set-associative, 128 sets, 16 bytes per cache line, 4 write buffers, only invalidation of a complete cache line, 96 % hit rate.
branch taken / not taken prediction (BTB: Branch Target Buffer).
every next access: 1 clock cycle.
Build-in FPU (Floating Point Unit).
25 MHz: 2600 mW, 1 micron CHMOS IV, iCOMP 122, no longer available.
33 MHz: 3500 mW, 1 micron CHMOS IV.
50 MHz: June 1991, 3875 mW, 0.8 micron CHMOS V.
Intel i80486DX2 CPU (ODPR), Intel OverDrive CPU (ODP: Intel i80486DX2 CPU), Intel i80486DX4 CPU (ODPR), Intel OverDrive CPU (ODP: Intel i80486DX4 CPU), Intel OverDrive CPU (ODPR: Intel Pentium CPU with Intel i80486DX CPU bus interface), Intel OverDrive CPU (ODP: Intel Pentium CPU).
Package: 168 pin PGA (Pin Grid Array).
No longer available from second quarter 1995.
step level D0: DH = 0x04 (family ID), DL = 0x04 (model ID, revision).
step level aB0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x15 (model ID, revision).
Not Intel i80486DX CPU pin compatible.
196 pin PQFP (Plastic Quad Flat Package).
From June 1993 replaced by Intel i80486DX-S CPU.
ID: step level A: DH = 0x04 (family ID), DL = 0x40 (model ID, revision).
currently FPU not implemented (resulting in a smaller chip, plastic package).
One extra pin assigned to allow an Intel i80487SX NPX to disable this CPU.
Not Intel i80486DX CPU upward pin compatible.
16 MHz: 1991, no longer available.
20 MHz: 1991, iCOMP 78, no longer available.
25 MHz: 1991, iCOMP 100 (per definition).
Intel OverDrive CPU (ODP: Intel Pentium CPU).
208 pin PQFP (Plastic Quad Flat Package).
25 MHz: iCOMP 100 (by define).
step level aB0, aC0: DH = 0x04 (family ID), DL = 0x2B (model ID, revision).
Clock doubled version of the Intel i80486DX CPU.
Intel i80486DX CPU pin compatible.
20/40 MHz: SQFP (Shrink Quad Flat Package).
No longer available from fourth quarter 1995.
step level A (write-back): DH = 0x04 (family ID), DL = 0x36 (model ID, write-through), DL = 0x7X (model ID, write-back).
Clock tripled version of the Intel i80486DX CPU.
Selection of doubling/tripling by a pin on the chip (CLKMUL: 0, 1). Connecting this pin with the BREQ pin makes the core running at 2.5 times the external speed (not implemented yet).
Intel i80486DX CPU upward pin compatible.
5 V external, 3.3 V internal: if the motherboard does not provide the 3.3 V power to the CPU, the CPU can be installed using a special socket wired to the 3.3 V output of your PSU (Power Supply Unit); in either case another PSU providing the 3.3 V is needed.
25/75 MHz max (A80486DX475): 3.3 V, March 1994, iCOMP 319.
33/100 MHz max (A80486DX4100): 51 SPECint92, 27 SPECfp92, 3.3 V, March 1994, iCOMP 435.
Production cancelled for a few months from September 1994 in favor of Intel Pentium CPUs.
Power consumption: 4 W typical.
SL Enhanced Intel i80486DX CPU pin compatible.
Extra integer multiplier: 5 cycle 16 x 16 multiply.
208 pin SQFP (Shrink Quad Flat Package).
Technology: 4-layer metal, 0.6 micron biCMOS/CHMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x8X (model ID, revision).
CPUID: step level A: family=0x4, model=0x8.
From October 1994 (Intel i80486DX4WB CPU): write-back cache.
Clock doubled version of the Intel i80486SX CPU.
25/50 MHz: March 1994, iCOMP 180.
ID: step level aC0: DH = 0x04 (family ID), DL = 0x5B (model ID, revision).
Originally same core and microcode as Intel i80486 CPUs; currently an own implementation. In between there were CPUs with recompiled 486 microcode.
Intel i80486 CPU instruction compatible.
All current Enhanced AMD processors support the CPUID instruction.
Intel i80486DX CPU instruction/pin compatible.
33 MHz: 8-33 MHz, 1993.
40 MHz: 8-40 MHz, 1993.
DH = 0x04 (family ID), DL = 0x12 (model ID, revision).
Low power version of the AMD Am486DX CPU.
ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).
Low power (SMM: System Management Mode), low voltage (3.0 V) version of the AMD Am486DX CPU.
33 MHz: 0-33 MHz, 1993.
Clock doubled version of the AMD Am486DX CPU.
From November 1994: 3.3 V.
40/80 MHz: September 1994, heatsink required.
Some 3.3 V, 66, 80 MHz items are DX4 parts that failed Q.C. at 100 MHz (Malaysia, fab number 25253).
ID: DH = 0x04 (family ID), DL = 0x3X (model ID, revision).
Clock doubled version of the AMD Am486DXL CPU.
Low power (SMM: System Management Mode).
ID: DH = 0x04 (family ID), DL = 0x32 (model ID, revision).
Clock tripled version of the AMD Am486DX CPU.
Intel i80486DX4 CPU pin compatible.
Selection of doubling/tripling by a pin on the chip.
33/100 MHz: 3.3 V, September 1994, heatsink + fan required.
Technology: 3-layer metal, 0.5 micron CMOS.
DH = 0x04 (family ID), DL = 0x32 (model ID, revision).
B: write-back cache, T: write-through cache.
Intel i80486SX CPU instruction/pin compatible.
Low power (SMM: System Management Mode), low voltage (3.0 V) version of the AMD Am486SX CPU.
Clock doubled version of the AMD Am486SX CPU.
Embedded static version of the AMD Am486SX CPU.
Embedded static version of the AMD Am486DX4 CPU.
SL Enhanced Intel i80486DX2 CPU (P24D) pin compatible.
16 kbyte cache: write-through / write-back.
33/133 MHz (AMD Am5x86-P75, AMD 486X5-133): November 1995.
W: case temperature 55 C, Y: 75 C, Z: 85 C.
33/66 MHz: Cyrix FasCache Cx486DX2-V-66 CPU.
40/80 MHz: Cyrix FasCache Cx486DX2-V-80 CPU.
ID: DH = 0xA4 (family ID), DL = 0x80 (model ID, revision).
IBM265x86-3V3100GB: 33/100 MHz, package: PGA (Pin Grid Array). IBM265x86-3V3100QB: 33/100 MHz, package: PQFP (Plastic Quad Flat Package).
Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point Unit).
Can piggy-back a Cyrix Cx487S NPX.
Intel i80486SX CPU upward pin compatible.
ID: DH = 0x00 (family ID), DL = 0x05 (model ID).
Low Power: SMM (System Management Mode).
Low power (SMM: System Management Mode) version of the Cyrix FasCache Cx486S CPU. Static core.
Low voltage (3.3 V) version of the Cyrix FasCache 486S CPU.
Clock doubled version of the Cyrix FasCache 486S CPU.
Low power (SMM: System Management Mode) version of the Cyrix FasCache Cx486S2 CPU.
Low voltage (3.3 V) version of the Cyrix FasCache Cx486S2 CPU.
Cyrix FasCache Cx486DX/Cx486DX2 CPU FP bug: when a register load instruction is followed by an instruction that clears the FP status register (FCLEX), and the memory location being referenced is not in the CPU's internal cache, the external memory bus cycle is aborted by the FCLEX instruction and the register is not loaded properly.
Since this code sequence is very unlikely to occur in any software, the bug will probably not be fixed at all.
Intel i80486DX CPU instruction compatible, FPU (Floating Point Unit).
8 kbyte cache: write-through / write-back.
ID: DH = 0x00 (family ID), DL = 0x06 (model ID).
Low voltage (3.3 V) version of the Cyrix FasCache Cx486DX CPU.
Clock doubled Cyrix FasCache Cx486DX CPU.
ID: DH = 0x00 (family ID), DL = 0x07 (model ID).
Low voltage (3.3V) version of the Cyrix FasCache Cx486DX2 CPU.
Low voltage (4 V) version of the Cyrix FasCache Cx486DX2 CPU.
33/66 MHz (announced: fourth quarter 1994).
40/80 MHz (announced: fourth quarter 1994).
Technology: IBM 0.65 micron CMOS.
ID: DH = 0x04 (family ID), DL = 0x80 (model ID, revision).
Clock tripled Cyrix FasCache Cx486DX CPU.
Intel i80486DX4 P24C CPU pin compatible.
3 V core, 5 V tolerant I/O.
Dual SMM support: Cyrix SMM / SL compatible SMM.
208 pin QFP (Quad Flat Package).
DIR0 register: 0x1B (CLOCKMUL=0), 0x1F (CLOCKMUL=1).
Cyrix 586 CPU with Intel i80486DX4 P24D CPU bus interface.
64 bit internal data bus, 32 bit external data bus.
16 kbyte unified cache: write-back/write-through, 4-way set-associative, 4 sets of 256 lines, 16 bytes per line.
Superpipelined superscalar: data forwarding, branch prediction, BTB (Branch Target Buffer), decoupled load/store unit.
MMU (Memory Management Unit): 32-entry TLB (Translation Look-aside Buffer).
SMM (System Management Mode): stop-clock, FPU auto-idle, hardware suspend, static core.
33/100 or 50/100 MHz: 3.5 W.
3.45 V core, 5 V tolerant I/O.
Technology: 0.65 micron CMOS (IBM).
Low power (3.3 V) version of the Texas Instruments TI486SXL-GA CPU.
Clock doubled version of the Texas Instruments TI486SXL-GA CPU.
Clock doubled, low power (3.3 V) version of the Texas Instruments TI486SXL-GA CPU.
Intel and Cyrix pin compatible.
Cyrix FasCache Cx486DX4 CPU with Texas Instruments TI486DX2 CPU pin layout.
33/100 MHz (announced December 1995).
The UMC 486 CPU does violate some of Intel's patents and will therefore not be sold in the USA.
Some 3.3 V U5 CPUs are sold as 3 V parts.
Intel i80486SX CPU instruction/pin compatible, no FPU (Floating Point Unit).
33 MHz: 2.25 W, August 1994.
ID: step level A: DH = 0x04 (family ID), DL = 0x23 (model ID, revision).
Intel i80486DX CPU pin compatible UMC U5S CPU.
ID: DH = 0x04 (family ID), DL = 0x1X (model ID, revision).
UMC U5S CPU with 208 pin QFP (Quad Flat Package) package.
33 MHz (UMC U5SF-SUPER33 CPU).
3.3 V version of the UMC U5S CPU.
25 MHz (UMC U5SLV-SUPER25 CPU).
33 MHz (UMC U5SLV-SUPER33 CPU): 0.76 W, August 1994.
Package: 196 pin PGA (Pin Grid Array).
UMC U5SLV CPU with 208 pin LQFP package.
25 MHz (UMC U5FLV-SUPER25 CPU).
33 MHz (UMC U5FLV-SUPER33 CPU).
LV: 3.3 V, _: 5 V.
Many 486 CPU motherboards contain an Intel OverDrive socket in which a more powerful CPU can be placed (ODP: OverDrive Processor), this being an Intel i80486DX2 CPU, an Intel i80486DX4 CPU, or an Intel Pentium CPU. It is possible to remove the old CPU while upgrading. All output pins of the original CPU are put in 3-state and the power consumption is reduced when the UP# pin (Upgrade Present) is activated.
An Intel OverDrive CPU will be made available that will fit in the original PGA (Pin Grid Array) (ODPR: OverDrive Processor Replacement), so motherboards without an Intel OverDrive socket can be upgraded too.
At this moment it is still unsure if all motherboards with an Intel OverDrive socket can indeed be upgraded to an Intel Pentium CPU. The Intel Pentium P24T CPU (ODP), the Intel Pentium CPU upgrade for the blue 238 pin PGA OverDrive socket (Socket 2: 5 V), appears to produce too much heat for most thermally not compliant systems. It is not even sure if there will ever be an Intel Pentium CPU upgrade for those motherboards at all (see Intel OverDrive Processor Upgradability Guide). For the newer motherboards with a white 237 pin PGA OverDrive socket (Socket 3: 3.3 V, 5 V), that do satisfy the heat specifications, there will be an Intel Pentium CPU at 3.3 V with a ventilator on the IC. There are also black 168 pin OverDrive sockets (standard 486 socket) around; these can contain an Intel i80486DX2 ODP CPU or an Intel i80486DX4 ODP CPU. For the black 169 pin OverDrive sockets (Socket 1: 5 V) of 486SX systems, an Intel i80487SX CPU, an Intel i80486DX2 ODP CPU, or an Intel i80486DX4 ODP CPU is available. For the 235 pin Overdrive socket (Socket 6: 3 V) of 486DX4 systems, the same Intel Pentium CPU at 3.3 V that could be used with Socket 3, can be used here as well.
SL Enhanced from June 1993.
No longer available from April 1996.
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID, revision).
Package: 169 pin PGA (Pin Grid Array) (487SX).
3.3 V core (voltage regulator), 5 V I/O.
25/75 MHz max (DX4ODPR75): October 1994, iCOMP 319.
33/100 MHz max (DX4ODPR100): October 1994, iCOMP 435.
No longer available from fall 1996.
ID: step level A: DH = 0x14 (family ID), DL = 0x80 (model ID, revision).
ID: DH = 0x15 (model ID, family ID), DL = 0x31 (revision).
32 kbyte cache: 16 kbyte code, 16 kbyte data.
25/63 MHz (PODP5V63): for 25 MHz external bus systems, January 1994, 235 pin PGA (Pin Grid Array), iCOMP 443.
33/83 MHz (PODP5V83): for 33 MHz external bus systems, October 1995, 237/238 pin PGA (Pin Grid Array), iCOMP 581, no longer available from March 1998.
ID: DH = 0x15 (model ID, family ID), DL = 0x2X (revision).
step level C0 (33/83 MHz, SU014): 1532.
64 bit external data bus (MMU (Memory Management Unit, including cache) - memory).
Package: 296 pin PGA (Pin Grid Array).
In October 1994 Dr. Thomas R. Nicely, Professor of Mathematics at the Lynchburg College, Lynchburg, Virginia (nicely@acavax.lynchburg.edu), reported a bug present in the FPU of all Intel Pentium CPUs. The double precision part of the mantissa is not computed correctly when dividing in some areas of the mantissa space of the divisor. The bug is fixed in Intel Pentium CPUs produced after November 1994.
60 MHz (Intel Pentium 510\60 CPU): 5 V, March 1993, 17-13 W, iCOMP 510.
66 MHz (Intel Pentium 567\66 CPU): 5 V, 16-13 W, iCOMP 567, 64.5 SPECint92, 56.9 SPECfp92 (First 66 MHz CPUs had heat troubles and were released as 60 MHz items).
Package: 273 pin PGA (Pin Grid Array) (Socket 4: 273 pins, 5 V).
Die size: 18 x 16 mm.
step level D1: DH = 0x05 (family ID), DL = 0x17 (model ID, revision).
step level Bx: family=0x5, model=1.
Model 1, revision 7: FDIV bug fixed.
50/75 MHz (Intel Pentium 610\75 CPU) (notebooks, P54T): 3.3 V, August 1994, package: 320 pin TCP, iCOMP 610.
60/90 MHz (Intel Pentium 735\90 CPU): 3.3 V, March 1994, iCOMP 735.
66/100 MHz (Intel Pentium 815\100 CPU): 3.3 V, March 1994, iCOMP 815.
Package: 296 pin PGA (Pin Grid Array) (Socket 5: 320 pins, 3.3 V).
Technology: 4-layer metal, 0.6 micron biCMOS.
60/120 MHz (Intel Pentium 1000\120 CPU, Intel Pentium P54CQS CPU): no multi-processor features, 3.3 V, March 1995, iCOMP 1000, step level C2.
Package: 296 pin PGA (Pin Grid Array) (Socket 5).
66/133 MHz (Intel Pentium 1110\133 CPU): package: 296 pin PGA (Pin Grid Array) (Socket 5), iCOMP 1110.
60/150 MHz: 3.3 V, iCOMP 1195.
66/166 MHz: 3.3 V, iCOMP 1340.
Package: 296 pin PGA (Pin Grid Array) (Socket 7: 321 pins, 3.3 V, maximum 5 A, maximum 17 W).
P54LM, 2.9 V, step level Ax: DH = 0x05 (family ID), DL = 0x25 (model ID, revision).
CPUID: family = 0x5, model = 0x2.
Pentium OverDrive processor for Intel Pentium P54C CPU.
ID: DH = 0x25 (model ID, family ID), DL = 0x2X (revision).
Pentium OverDrive processor for Intel Pentium P5 CPU.
60/120 and 66/133 MHz (P5T, PODP5V120/133): for 60 and 66 MHz systems, iCOMP 877/978.
Package: 273 pin PGA (Pin Grid Array) (Socket 4).
Pentium P54CT(A) OverDrive processor for Intel Pentium P54C CPU.
50/125 MHz (PODP3V125): for 50/75 MHz systems, iCOMP 1070.
60/150 MHz (PODP3V150): for 60/90 MHz systems, iCOMP 1176.
66/166 MHz (PODP3V166): for 66/100 MHz systems, iCOMP 1308.
Voltages: 3.3 V: 3.135 - 3.600 V.
Package: 320 pin PGA (Pin Grid Array) (Socket 5/7).
3 integer pipelines, FP pipeline.
Cache: 16 kbyte instruction with predecode unit, 8 kbyte data (Harvard architecture), MESI architecture.
Package: 296 pin SPGA (Pin Grid Array) (Socket 7).
0.35 micron CMOS (first quarter 1996).
AMD K5-PR75 CPU (SSA, model 0): 50/75 MHz, March 1996, die size: 177 mm2.
AMD K5-PR90 CPU (SSA, model 0): 60/90 MHz.
AMD K5-PR100 CPU (SSA, model 0): 66/100 MHz.
AMD K5-PR120 CPU (5k86, model 1): 60/90 MHz.
AMD K5-PR133 CPU (5k86, model 1): 66/100 MHz.
AMD K5-PR150 CPU (5k86, model 2): 60/105 MHz.
AMD K5-PR166 CPU (5k86, model 2): 66/116 MHz, March 1997.
AMD K5-PR166 CPU (5k86, model 3): 66/133 MHz, August 1998 / never released, 3.52 V core.
No longer manufactured from mid 1997.
The multiplier can not be changed.
Pre-release AMD 5k86 K5 CPU: more internal wait states, incomplete BTB (Branch Target Buffer).
Features: VME, I/O Breakpoints, TSC (Time Stamp Counter), Machine Check.
16 kbyte unified cache: write-back, 4-way set-associative.
3.3 V, 5 V I/O.
100 MHz (announced: third quarter 1995).
Not available anymore due to compatibility problems.
Branch prediction, branch target cache.
FPU: 4 64 bit write buffers.
Technology: 0.5 micron CMOS (IBM, SGS-Thomson).
Primary cache: 16 kbyte unified, write-back, 4-way set-associative.
50/100, 33/100 (Cyrix Cx5x86-100GP/QP CPU): 3.45 V, July 1995.
40/120 (Cyrix Cx5x86-120GP/QP CPU): 3.45 V.
The multiplier can be 2 or 3.
In general practice, even faster than Intel's Pentium Pro CPUs (Cyrix optimized for 16 bit code, Intel optimized the Pentium and Pentium Pro CPUs for 32 bit code).
208 pin QFP (Quad Flat Package) (QP).
Intel Pentium CPU instruction compatible, n� FPU (Fl��ting P�in Unit).
RISC (Reduced Instruction Set Computer): RISC86: interpreting (hardware) Intel Pentium CPU instruction set.
Runs internally at 4 V; Compatibility with 5 V motherboard provided through the bus interface chip.
16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture).
External level 2 cache controller for 256 kbyte or 1 Mbyte.
NexGen NxPCI PCI Bus interface: October 1995.
NexGen Nx586 CPU: 4 V, 9 W, 3.5E6 transistors, die size: 118 mm2, 0.5 micron CMOS.
NexGen Nx587 NPX: 4 V, 1.1 W, 0.7E6 transistors, 0.5 micron CMOS.
NexGen NxVL Vesa Local Bus interface: 5 V, 1.0 W, 0.5 micron CMOS.
70 MHz (PR75): September 1994.
Upward compatible with all previous iapx CPUs (RISC core with X86 translation).
Superpipelined superscalar: 3-issue, 12-stage, instruction pool, fetch/decode unit, dispatch/execution unit (2 AGU (Address Generation Unit): 1 load, 1 store, 1 JEU (Jump Execution Unit), 2 IEU (Integer Execution Unit), 1 FEU (Floating Execution Unit)), retire unit.
Multi-branch prediction, data flow analysis, speculative execution.
Level 1 cache: 8 kbyte instruction, 8 kbyte data (Harvard architecture).
Level 2 cache: 256/512 kbyte or 1 Mbyte, MESI architecture, custom SRAM.
4 Gbyte cachable main memory.
2 or 4 Intel Pentium Pro CPUs can co-operate in a SMP (Symmetric Multi-Processor) environment.
The speed-up of a 2-CPU configuration is excellent. The speed-up of a 4-CPU configuration is relatively poor, probably due to too small caches causing too many cache flushes.
66/133 MHz (engineering sample): 256 kbyte level 2 cache, 2.9 V, 3.1 V, 14 W.
60/150 MHz: 256 kbyte level 2 cache, 3.1 V, November 1995, 23.0 W.
Technology: 0.6 micron biCMOS, precharged domino logic.
66/166 MHz: 512 kbyte level 2 cache, November 1995, 27.5 W.
60/180 MHz: 256 kbyte level 2 cache, November 1995, 24.8 W.
66/200 MHz: 256 kbyte level 2 cache, 3.3/3.5 V, November 1995, 27.3 W.
66/200 MHz: 512 kbyte level 2 cache, November 1995, 32.6 W, 0.35 micron technology.
Package: 387 pin CPGA (Ceramic Pin Grid Array) (Socket 8).
This package contains two dies: the processor and the level 2 cache (dual-cavity package), interconnected by the DIB (Dual Independent Bus).
ID: DH = 0x06 (model ID, family ID), DL = 0xXX (revision).
Pentium Pro and Pentium II processors contain a bug in the FPU (Floating Point Unit) (Dan-0411). The conversion of certain large negative numbers into integers sometimes fails to detect an overflow. Software work-arounds are available.
66/200 MHz: 1 Mbyte level 2 cache, 3.3 V, August 1997, 43 W.
66/200 MHz: 1 Mbyte level 2 cache, 3.2 V (VID (Voltage Identification) to be ignored), August 1997, 40 W.
3.5 V: 3.325 - 3.675 V.
The multiplier can be 2.5, 3, 3.5, or 4.
Intel Pentium Pro P6 CPU without level 2 cache.
Pentium II OverDrive processor for Pentium Pro.
Pentium II Deschutes P6 Microarchitecture Core.
Dynamic Execution: multiple branch prediction, dataflow analysis, speculative execution.
Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture), non-blocking.
Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM.
The level 2 cache runs at the same speed as the processor core, like at the Pentium Pro.
66/333 MHz: for 150 (60/300 MHz), 166, 180 (60/300 MHz) en 200 MHz (dual) Pentium Pro systems, August 1998, 23.8 W (60/300 MHz), 26.3 W (66/333 MHz).
2.5 V core, 3.3 V I/O.
3.3 V: 3.135 - 3.465 V.
Package: 387 pin PGA (Pin Grid Array) (Socket 8).
Technology: 5 layer metal, 0.25 micron CMOS.
ID: DH = 0x16 (model ID, family ID), DL = 0xXX (revision).
IBM 266x86-2V2100GB CPU: 50/100 MHz.
IBM 266x86-2V2110GB CPU: 55/110 MHz.
IBM 266x86-2V2120GB CPU: 60/120 MHz.
IBM 266x86-2V2133GB CPU: 66/133 MHz.
CPUID: family=0x5, model=0x3, step level=0.
IBM 6x86-P120+ CPU (IBM 266x86-2V2P120GE CPU): 50/100 MHz, 3.3 V core, 5 V tolerant I/O.
IBM 6x86-P133+ CPU (IBM 266x86-2V2P133GE CPU): 55/110 MHz, 3.3 V core, 5 V tolerant I/O.
IBM 6x86-P150+ CPU (IBM 266x86-2V2P150GE CPU): 60/120 MHz, 3.3 V core, 5 V tolerant I/O.
IBM 6x86-P150+ CPU (IBM 266x86-2V7P150GE CPU): 60/120 MHz, 3.5 V core, 5 V tolerant I/O.
IBM 6x86-P166+ CPU (IBM 266x86-2V2P166GE CPU): 66/133 MHz, 3.3 V core, 5 V tolerant I/O.
IBM 6x86-P166+ CPU (IBM 266x86-2V7P166GE CPU): 66/133 MHz, 3.5 V core, 5 V tolerant I/O.
IBM 6x86-P200+ CPU (IBM 266x86-2V7P200GE CPU): 75/150 MHz, 3.5 V core, 5 V tolerant I/O.
Package: 296 pin SPGA (Pin Grid Array) (P54C socket compatible).
DIR0 register: 0x31, DIR1 register: 0x1X / 0x2X.
Low power version (25 % reduction) of the IBM 6x86 CPU.
2.8 V core, 3.3 V I/O, 5 V tolerant I/O.
IBM 6x86L-P120+ CPU: 50/100 MHz.
IBM 6x86L-P133+ CPU: 55/100 MHz.
IBM 6x86L-P150+ CPU (IBM 266x86L-2VAP150GB CPU): 60/120 MHz.
IBM 6x86L-P166+ CPU (IBM 266x86L-2VAP150GB CPU): 66/133 MHz.
IBM 6x86L-P200+ CPU (IBM 266x86L-2VAP150GB CPU): 75/150 MHz, technology: 5-layer metal, 0.44 micron IBM CMOS.
This CPU uses two power supplies: one supply (2.8 V) is for the core, and the other (3.3 V) is for the I/O interface.
Package: 296 pin SPGA (Pin Grid Array) (Socket 7 compatible).
DIR0 register: 0x31, DIR1 register: 0x2X.
Pentium Pro class CPU (RISC core with X86 translation). However, due to the slow FPU, the performance of floating point intensive applications like the game Quake is low.
Due to the first chips' sensitivity for reflections on the busses, Microsoft decided to turn off the primary cache for Window NT 4.0 for pre revision 2.7 chips. Registered Windows NT 4.0 users can obtain a processor replacement from Cyrix, or download a patch.
Superpipelined superscalar: 2-issue, 7-stage, 2 integer units, FPU (Floating Point Unit).
Features: register renaming, out-of-order execution, data dependancy removal, multi-branch prediction, speculative execution.
TLB (Translation Look-aside Buffer): 128-entry L1, 8-entry victim.
BTB (Branch Target Buffer): 256-entry, 4-way set-associative, 512-entry branch history table.
16 kbyte unified cache: write-back/write-through, 4-way set-associative, dual-ported, MESI architecture.
Pipelined burst-mode reads and writes.
256 byte instruction cache: fully-associative.
Multiprocessing support: SLiC/MP, OpenPIC interrupt architecture.
Cyrix 6x86 CPU: 3.3 V (C016) or 3.52 V (C028) core, or voltage switching supporting both, 5 V tolerant I/O, from revision 2.7 less power consumption.
40/80 MHz (Cyrix 6x86-PR90+ CPU): 3.3 V.
50/100 MHz (Cyrix 6x86-P120+GP CPU): 3.3 V.
55/110 MHz (Cyrix 6x86-P133+GP CPU): 3.3 V.
60/120 MHz (Cyrix 6x86-P150+GP CPU): 3.3 or 3.52 V.
66/133 MHz (Cyrix 6x86-P166+GP CPU): 3.3 or 3.52 V.
75/150 MHz (Cyrix 6x86-PR200+ CPU): 3.52 V.
Cyrix 6x86L CPU (low power): 2.8 V core, 3.3 V I/O.
50/100 MHz (Cyrix 6x86L-PR120+ CPU).
55/110 MHz (Cyrix 6x86L-PR133+ CPU).
60/120 MHz (Cyrix 6x86L-PR150+ CPU).
66/133 MHz (Cyrix 6x86L-PR166+ CPU).
75/150 MHz (Cyrix 6x86L-PR200+ CPU): technology: 0.44 micron CMOS.
296 pin CPGA (Ceramic Pin Grid Array) (Socket 7).
Pentium Pro class CPU (RISC core with X86 translation).
Cache: 16 kbyte instruction, 32 kbyte data (Harvard architecture).
Technology: 5-layer metal, 0.35 micron IBM CMOS.
In 1994 Intel started the NSP initiative (Native Signal Processing), but that project failed due to software problems. In 1995 the MMX project was started.
MMX (Matrix Math eXtensions, Multi-Media eXtensions): 57 SIMD instructions (Single-Instruction, Multiple-Data) for audio, video, and communication. Multi-media code of applications need to be rewritten and recompiled to take advantage of the MMX instruction set.
The MMX technology has been licenced to AMD and Cyrix.
The KNI technology (Katmai New Instructions, "MMX2"), adding another 70 instructions for 3D applications, will be available at the first quarter of 1999.
4 to 10 times faster than MMX processors, prices around $50.
66/266 MHz (announced: end 1997).
2.8 V, 3.3 V I/O.
Both Intel MMX processors and the Cyrix 6x86MX CPU use the FPU for the MMX implementation, resulting in tens of stall cycles while switching between integer, FPU, and MMX code.
EMBMOD166: 66/166 MHz Pentium/MMX with 82430HX PCIset, announced: first quarter 1998.
Runs MMX aware multi-media applications about 60 % faster than ordinary Intel Pentium CPU.
Package: 296 pin PPGA (Plastic Pin Grid Array) (Socket 7).
Technology: 4-layer metal, 0.35 micron CMOS.
2.45 V, 3.3 V I/O.
66/166 MHz: January 1998, 2.9 W.
66/200 MHz: September 1997, 3.4 W.
66/233 MHz: September 1997, 3.9 W.
66/266 MHz: 2.0 V, January 1998, 5.3 W.
1.8 V, 2.5 V I/O (Voltage Reduction Technology).
320 pin TCP (Tape Carrier Packaging).
Pentium/MMX P54CTB OverDrive processor for Intel Pentium CPUs.
2.8 V core (voltage regulator), 3.3 V I/O.
50/125 MHz: for 75, 100 MHz systems.
60/150 MHz: for 90, 120 MHz systems.
66/166 MHz (BPODPMT66X166): for 75 (to 50/125), 90 (to 60/150), 100, 133 MHz systems.
60/180 MHz (BPODPMT66X180): for 75 (to 50/150), 90, 120, 150 MHz systems, August 1997.
66/200 MHz (BPODPMT66X200): for 100, 133, 166 MHz Socket 7 systems, August 1997.
Voltages: 3.3 V: 3.135 - 3.6 V.
Pentium Pro class CPU with MMX technology.
512 Mbyte cachable main memory.
SMP (Symmetric Multi-Processor) support for 2 CPUs through GTL+ bus.
66/200 MHz. 66/233 MHz: April 1997, 34.8 W, iCOMP 2.0 267, SPECint95 9.38, SPECfp95 7.4, Intel Media Benchmark 364.13, no longer available from September 1998.
66/266 MHz: April 1997, 38.2 W, iCOMP 2.0 303, SPECint95 10.7, SPECfp95 8.17, Intel Media Benchmark 412.31, no longer available from October 1998.
66/300 MHz: ECC (Error Correcting Code), 43.0 W, iCOMP 2.0 332, SPECint95 11.9, SPECfp95 8.82, Intel Media Benchmark 459.08.
2.8 V core, 3.3 V I/O.
From July 1997 the secondary cache is supplied with ECC (Error Correcting Code).
Package: 242 pin SEC module (Single Edge Contact) (Slot 1).
The SEC module consists of a PCB containing the processor chip and the level 2 cache chips. Compared to the Intel Pentium Pro P6 CPU that combines the processor die and level 2 cache die in a single package (dual-cavity package), the DIB (Dual Independent Bus) is clocked at only half the speed.
The clock multiplier can be 3.5, 4, 4.5, 5.
Technology: 4 layer metal, 0.35 micron CMOS.
Pentium Pro and Pentium II processors contain a bug in the FPU (Floating Point Unit) (Dan-0411). The conversion of certain large negative numbers into integers sometimes failsi to detect an overflow. Software work-arounds are available.
4 Gbyte cachable main memory (512 Mbyte by step level dA0, 333 MHz version).
SMP (Symmetric Multi-Processor) support for 2 CPUs (Nightshade architecture).
66/333 MHz: January 1998, 23.6 W, iCOMP 2.0 366, SPECint95 13.0, SPECfp95 9.55, Intel Media Benchmark 498.79.
2.0 V core, 3.3 V I/O.
100/350 MHz: April 1998, 24.5 W, iCOMP 2.0 386, SPECint95 13.9, SPECfp95 11.20, Intel Media Benchmark 534.61.
100/400 MHz: April 1998, 27.9 W, iCOMP 2.0 440, SPECint95 15.8, SPECfp95 12.40, Intel Media Benchmark 601.10.
step level dA1: family ID 6, model ID 5, revision 1.
On-die thermocouple for temperature monitoring.
Low-end Intel Pentium II CPU for Basic PC.
66/266 MHz: April 1998, 16.7 W, iCOMP 2.0 213, Business Winstone 98 14.7, Intel Media Benchmark 305.36, 3D Winbench 98 437, no longer available from October 1998.
Voltages: 2.0 V: 1.9 - 2.1 V.
Package: SEPP (Single Edge Processor Package) (Slot 1).
On-chip level 2 cache: 128 kbyte, 4-way set-associative, non-blocking, BSRAM.
66/300A MHz: August 1998, integrated L2 cache.
66/333 MHz: August 1998, integrated L2 cache.
66/366 MHz: announced: first quarter 1999.
100/400 MHz: announced: second quarter 1999.
66/233 MHz: April 1998, 1.7 V core, 10.6 W.
66/266 MHz: April 1998, 1.7 V core, 12.1 W.
66/300 MHz: September 1998, 1.6 V core, 9.0 W, 7.8 W TDP core (Thermal Design Power), also available as Mobile Module with AGP support.
66/333 MHz (announced: first quarter 1999).
66/366 MHz (announced: first quarter 1999).
Voltages: 1.7 V: 1.58 - 1.82 V.
PSE36 addressing mode (part of Intel's Extended Server Memory Architecture): up to 64 Gbyte of addressable main memory.
Level 2 cache: 512 kbyte or 1/2 Mbyte, 4-way set-associative, non-blocking, BSRAM.
The level 2 cache runs at the same speed as the processor core, like at the Intel Pentium Pro CPU.
Multi-processor support (4-CPU with 450NX chipset, 8-CPU (announced: fourth quarter 1998): Saber architecture, Corollary Profusion chipset).
At the introduction, a bug in 4-CPU 450NX chipset based systems was discovered, which delayed the introduction of these systems.
100/400 MHz: 512 kbyte or 1 Mbyte L2 cache, 2-way SMP, June 1998, 30.8 W.
100/450 MHz: 512 kbyte or 1 Mbyte L2 cache, 2-way SMP, October 1998, 34.5 W, 38.1 W.
100/450 MHz (announced: first quarter 1999): 2 Mbyte L2 cache, 4-way SMP.
100/450 MHz (announced: second quarter 1999): 8-way SMP.
2.0 V, 3.3 V I/O.
Package: 330 pin SEC module (Single Edge Contact) (Slot 2).
Intel Pentium II CPU with KNI instruction set (Katmai New Instructions).
100/450 MHz (announced: first quarter 1999): 512 kbyte L2 cache.
100/500 MHz (announced: first quarter 1999): 512 kbyte L2 cache.
133/533 MHz (announced: second quarter 1999): 512 kbyte L2 cache.
Technology: 5 layer metal, 0.25 micron CMOS, later 0.18 micron (second half 1999).
Plans for mobile version canceled in May 1998.
Mobile Celeron for low-cost notebooks (announced: first quarter 1999), 366 and 400 MHz (announced: end 1999).
Dixon: mobile Mendocino with 256 kbyte on-chip level 2 cache for low-cost notebooks, 266 MHz (PE, Performnce Enhanced, announced: fourth quarter 1998), 300 MHz (PE, Performnce Enhanced, announced: first quarter 1999), 333 MHz (announced: first half 1999), 366 MHz (announced: end 1999).
Dual-processor modules for Slot 2 systems (DP Ready, Camino chipset).
Willamette: successor Intel Pentium II CPU series, 600 MHz (announced: end 1999), 0.18 micron, later 0.13 micron.
Coppermine: mobile version of Willamette, 100/450 and 100/500 MHz, on-die level 2 cache, AC/DC powering (Geyserville technology), 0.18 micron technology, announced: end 1999.
Tanner: Xeon with KNI, 100/500 MHz (announced: first quarter 1999), multi-processor support (4-CPU: Lion32 architecture), Slot 2 and Slot M, technology: 0.25 micron.
Cascades: Xeon with KNI, 700 MHz (announced: second half 1999), on-die level 2 cache, technology: 0.18 micron.
P7, Merced: 64 bit architecture (IA-64), EPIC (Explicit Parallel Instruction Computing, narrow VLIW (Very Long Instruction Word)), multi-processor support (4-CPU with 460GX chipset: Lion64 architecture), 600 MHz, 133 MHz external bus, Slot M (64/128 bits), announced: mid 2000, 14E6 transistors, die size: 300 mm2, technology: 0.18 micron, 800 MHz, copper.
McKinley: successor Merced, 0.13 micron.
Intel will introduce copper chips only in 2001, together with the 0.13 micron technology.
Based on the NexGen Nx686 CPU design.
Intel Pentium/MMX P54C CPU pin compatible.
Optimized for 16 bit code.
Superscalar: 6-stage, 7 execution units: load, store, 2 integer, FPU, branch, MMX.
Features: X86 to RISC86 instruction translation, instruction predecoding, out-of-order execution, speculative execution, central Instruction Control Unit.
Branch prediction: 8192-entry branche history table, 16-entry BTB (Branch Target Buffer), 16-entry return address stack.
32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Instruction cache: 2-way set-associative, 32 bytes per line, single cycle access.
Data cache: write-back, 2-way set-associative, 32 bytes per line, simultanious load and store in single cycle, MESI architecture.
66/166 MHz (PR166): 2.9 V core, 3.3 V I/O, April 1997. 60/180 MHz: 2.9 V. 66/200 MHz (PR200): 2.9 V core, 3.3 V I/O, April 1997. 66/233 MHz (PR233): 3.3/3.2 V core, 3.3 V I/O, April 1997.
Technology: 5-layer metal, 0.35 micron C4 CMOS.
8.8E6 transistors, from which 3E6 for the cache.
2.2 V core, 3.3 V I/O.
Technology: 0.25 micron PGA (Pin Grid Array) (Socket 7).
100/350 MHz (announced: third quarter 1998).
100/400 MHz (announced: fourth quarter 1998).
Package: 321 pin PGA (Pin Grid Array) (Socket 7+).
3DNow! technology: 3D multi-media instruction set (21 instructions).
100/350 MHz: September 1998, Socket 7+.
100/400 MHz (announced: fourth quarter 1998): Socket 7+.
100/450 MHz (announced: first quarter 1999): Socket 7+.
Package: 321 pin PGA (Ceramic Pin Grid Array) (Socket 7).
Model 9: 256 kbyte level 2 cache.
100/350 MHz (announced: fourth quarter 1998).
K6-3 (Sharptooth): K6-2 with 256 kbyte on-chip level 2 cache, 450 MHz (announced: first quarter 1999).
K7: announced: begin 1999, Slot A (Intel Slot 1 compatible) or EV6 (DEC Alpha CPU compatible).
Copper technology: announced: end 1999, new fab in Dresden, Germany.
1 GHz K7 in 2000.
Superscalar: register renaming, out-of-order execution, speculative execution.
Branch prediction: 512-entry branch target cache, 4-way set-associative, 1024-entry branch history cache.
TLB (Translation Look-aside Buffer): 16-entry L1, direct mapped, dual-ported, 384-entry L2, direct mapped, dual-ported.
Optimized for 32 bit code.
64 kbyte unified cache: 4-way set-associative, 32 bytes per line.
256 byte instruction line cache: 8-entry, fully-associative, 32 bytes per line.
66/133 MHz (Cyrix 6x86MX-PR166+ CPU), May 1997.
66/166 MHz (Cyrix 6x86MX-PR200+ CPU).
75/188 MHz ()Cyrix 6x86MX-PR233+ CPU.
The multiplier can be 2, 2.5, 3, or 3.5.
Dual voltage: 2.8 V core, 3.3 V I/O.
83/208 MHz (Cyrix 6x86MX-PR266 CPU): March 1998, 2.9 V core, 3.3 V I/O.
75/225 MHz (Cyrix 6x86MX-PR300 CPU): April 1998, 0.25 micron IBM CMOS.
100/250 MHz (Cyrix 6x86MX-PR333 CPU): announced: third quarter 1998.
Package: 296 pin PGA (Pin Grid Array) (P54C socket compatible).
Technology: 5-layer metal, 0.35 micron CMOS (IBM and SGS-Thomson).
Cayenne: announced: 1998, own 3D multi-media instruction set.
Intel Pentium/MMX P55C CPU compatible.
Cache: 32 kbyte data, 32 kbyte instruction.
50/150 MHz: 3.3 V, never produced.
Package: 296 pin PGA (Pin Grid Array) (Socket 7).
Package: 296 pin PGA (Pin Grid Array) (Socket 7+).
WinChip C6+ with 3DNow! technology.
66/266 MHz (announced: second half 1998).
100/300 MHz (announced: second half 1998).
100/300 MHz (announced: fourth quarter 1998).
The Cyrix MediaGX CPU together with the MediaGX Cx5510 companion chip implements a complete PC system including 64 bit FPM / EDO DRAM controller (maximum 128 Mbyte in 4 banks), ISA and PCI bus, video and audio.
Primary cache: 16 kbyte unified, write-back, 4-way set-associative, 1024 lines of 16 bytes.
to be connected to TFT (Thin Film Transistor) flat panel or RAMDAC (RAM Digital to Analog Converter)).
upgradable to hardware wave table.
private link to Cx5510 for monitoring system activity.
MediaGX Cx5510 chip: 208 pin MQFP (Metal Quad Flat Package).
60/120 MHz (Cyrix Cx5gx86-120 CPU).
66/133 MHz (Cyrix Cx5gx86-133 CPU): February 1997.
66/150 MHz (Cyrix Cx5gx86-150 CPU).
66/166 MHz (Cyrix Cx5gx86-166 CPU): June 1997.
60/180 MHz (Cyrix Cx5gx86-180 CPU): June 1997.
MediaGX Cx5510 chip: 3-layer metal, 0.6 micron CMOS, 3.3 V.
Used in Compaq Pressario 2000.
RISC (Reduced Instruction Set Computer).
1.7E6 transistors, die size: 234 mm2.
300 MHz: 3.3 V, June 1994.
Used in DEC Alpha AXP.
533 MHz: March 1997, SPECint95 14.3, SPECfp95 17.0.
266 MHz: September 1994, 9.3E6 transitors, die size: 314 mm2.
300 MHz: September 1994, 9.3E6 transitors, die size: 314 mm2.
500 MHz: 16 kbyte level 1 cache, 96 kbyte level 2 cache, 9.6E6 transistors.
Manufactured by DEC, Mitsubishi, and Samsung.
1 GHz (announced: 2000): 0.18 micron CMOS.
8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture): both direct mapped.
MIPS R4000MC / R4000SC CPU: secondary external cache controller (128 bit bus).
LSI Logic LR4000PC CPU: 50 MHz, 0.7 micron CMOS.
LSI Logic LR4000SC CPU: internal / external clock rate selectable 1/2, 1/3, 1/4, 100 MHz maximum.
Also available from NEC, IDT and Toshiba.
16 kbyte instruction cache, 8 kbyte data cache (Harvard architecture): both direct mapped.
80 MHz: 3.3 V (also available from NEC).
16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture): both direct mapped.
MIPS R4400MC / R4400SC CPU: secondary external cache controller (128 bit bus).
200 MHz: 3.3 V, May 1994.
16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture): both 2-way set-associative.
100 MHz: 5 V (also available from IDT).
100 MHz: 3.3 V (also available from Toshiba).
In June 1998 the PowerPC consortium fell apart. Motorola bought the IBM part of the Sommerset PowerPC development center in Austin, Texas.
64 bit external data bus.
50 MHz: 3.6 V, April 1993.
66 MHz: 3.6 V, April 1993, 9 W.
80 MHz: 3.6 V, fourth quarter 1994, 85 SPECint92, 105 SPECfp92, 8 W, used in Apple Power Macintosh and IBM RS/6000.
100 MHz: November 1994, 4 W, IBM 0.5 micron CMOS.
135 MHz (announced: fourth quarter 1994).
POWER (Performance Optimization With Enhanced RISC).
For advanced consumer electronics, handheld computers.
66 MHz: 3.3 V, October 1993.
80 MHz: October 1993, 75 SPECint92, 85 SPECfp92.
Troubles running SoftPC; probably a 603+ will be developed by Apple.
100 MHz: October 1995, 1.2 W.
For high performance desktop computers, workstations.
75 MHz: 3.3 V, December 1994.
100 MHz: 3.3 V, December 1994.
120 MHz: 3.3 V, SPECint92 180, SPECfp92 180.
133 MHz: 3.3 V, SPECint92 200.
ceramic BGA (Ball Grid Array).
Die size: 13 x 15 mm.
Intel ODP CPU pin compatible.
Units: 2 integer, 2 floating point, 2 branch, jump.
POWER2 (Performance Optimization With Enhanced RISC 2).
71.5 MHz: 126 SPECint92, 260 SPECfp92.
Multi-chip CPU: core, cache, controller.
POWER3 (Performance Optimization With Enhanced RISC 3).
Technology: IBM 7S copper CMOS.
300 MHz: 32 kbyte data cache, 32 kbyte instruction cache, 2.7 V, March 1998, 7.3 W, SPECint92 13.2, SPECfp92 8.5, 6.35E6 transistors, IBM 0.25 micron 6S CMOS.
400 MHz (demo IBM): technology: IBM C7 CMOS.
480 MHz (demo IBM): technology: IBM 7S copper CMOS.
500 MHz (announced): IBM copper CMOS.
333 MHz (announced: September 1998). 366 MHz (announced: September 1998). 400 MHz (announced: September 1998).
Technology: 0.18 micron copper CMOS.
Texas Instruments SuperSPARC CPU (Viking).
Texas Instruments SuperSPARC II CPU (announced).
Texas Instruments UltraSPARC CPU (announced).
Sparc Ultra: 250 MHz, end 1995.
Sparc Ultra II: 336 MHz, March 1998.
Sparc Ultra III (announced: 1999): 600 MHz, technology: TI 0.18 micron CMOS.
HP invested over $1,000,000,000 in this CPU and agreed with Intel to co-operate in the development of a new 64 bit RISC CPU using this architecture.
HP PA-8000 CPU: 180 MHz.
HP PA-8200 CPU: 240 MHz, March 1998.
HP PA-8500 CPU: announced: end 1998.
In this section the Motorola CPU series, used in the Apple Macintosh personal computers and the Commodore Amiga home computers are described.
Hitachi 6802W CPU: Motorola MC6802 CPU.
Optimized for high level languages.
Motorola MC6809E CPU: external clock input for external sync.
Used in Atari ST, Commodore Amiga, Apple Lisa, Macintosh.
Motorola MC68000 CPU instruction compatible.
Same core as Motorola MC68000 CPU.
2 serial management controllers to support GCI and IDL.
Motorola MC68000 CPU upward instruction compatible: more instructions, more instructions with restart capabilities after interrupts.
Motorola MC68000 CPU pin compatible.
Embedded version of Motorola MC68010 CPU.
145 pin PGA (Pin Grid Array).
Motorola MC6800 CPU / Motorola MC68010 CPU upward instruction compatible.
MMU (Memory Management Unit): Motorola MC68851 Paged MMU, 16 byte burst mode.
or faster Motorola MC68882 NPX.
Used in Amiga, Apple Macintosh, Sun3, Atari TT030, Atari Falcon 030.
256 byte instruction cache, 256 byte data cache (Harvard architecture).
MMU (Memory Management Unit), 16 byte burst mode.
Used in Amiga 3000 and 4000, Sun3, NeXT, Atari TT030, Atari Falcon 030, Apple Macintosh and PowerBook.
MMU (Memory Management Unit), FPU (Floating Point Unit), pipelined, clock doubled.
4 kbyte instruction cache, 4 kbyte data cache (Harvard Architecture).
Used in Amiga 4000, Apple Macintosh, NeXT.
Motorola MC68040 CPU without MMU (Memory Management Unit) and FPU (Floating Point Unit).
Used in Apple Macintosh, QXL.
Low power version (3.3 V) of the Motorola MC68040 CPU, no FPU (Floating Point Unit).
Used in DraCo, Apple Powerbook.
Enhanced FPU (Floating Point Unit).
Used in DraCo, Amiga accelerator boards.
NPX for Intel i8086 CPU, Intel i8088 CPU, Intel i80186 CPU, Intel i80188 CPU.
10 MHz (8087-1): 2400 mW.
NPX for Intel i80286 CPU, Intel i80386 CPU.
Intel i80287-fast10: 10 MHz, asynchronous.
Intel i80287 NPX instruction/pin compatible.
44 pin PLCC (Plastic Leaded Chip Carrier).
AMD Am80C287 NPX with power management.
NPX for Intel i80C186 CPU.
Intel i80387 NPX instruction compatible.
12.5 MHz: 1989, CMOS, 675 mW.
16 MHz: 1989, CMOS, 780 mW.
Intel i80287 NPX pin compatible.
12.5 MHz: 1990, 675 mW.
44 pin PLCC (Plastic Leaded Chip Carrier) (Intel i80287XLT NPX).
Cyrix FasMath Cx387+ NPX core/microcode (from November 1991).
44 pin PLCC (Plastic Leaded Chip Carrier) (Intel i80287XLT NPX pin compatible).
IIT IIT-3C87 NPX instruction compatible.
IIT IIT-2C87-10F NPX: 10 MHz, asynchronous.
IIT IIT-2C87-12F NPX: 12 Mhz, asynchronous.
20 MHz, 1989, 500 mW.
IIT IIT-2C87-20F NPX: 20 MHz, asynchronous.
NPX for Intel i80386/i80386DX CPU.
Package: 68 pin, 2 row ceramic PGA (Pin Grid Array).
Technology: 1.5 micron CHMOS III.
Package: 68 pin, 2 row PGA (Pin Grid Array).
NPX for Intel i80386SX CPU.
Package: 68 pin PLCC (Plastic Leaded Chip Carrier).
NPX for Intel i80386SL CPU.
Intel i80387DX NPX instruction/pin compatible.
Intel i80387SX NPX instruction/pin compatible.
Computations are executed faster than by Intel i80387DX NPX.
Later versions (from November 1991) correctly co-operate with first generation Cyrix Cx486DLC CPUs, which were having synchronization problems, when co-operating with a NPX.
European name for Cyrix FasMath Cx83D87 NPX from November 1991.
Also know as Cyrix AutoMath.
Computations are executed faster than by Intel i80387SX NPX.
NPX for Intel i80386 CPU.
Not fully Intel i80387 NPX instruction compatible.
Intel i80387DX NPX pin compatible.
Intel i80387SX NPX pin compatible.
Clock doubled version of the IIT IIT-3C87 NPX.
NPX for Intel i80386DX CPU.
Not Intel i80387 NPX instruction compatible.
In fact a small PCB with three chips mounted on it.
Not Intel i80387DX NPX pin compatible.
NPX for Intel i80386DX CPU, Intel i80486 CPU.
Package: 121 pin, 3 row PGA (Pin Grid Array) (EMC (Extended Math Coprocessor) socket).
Can be used together with Intel i80387DX NPX. If the motherboard has no apart PGA (Pin Grid Array) for the Abacus, two NPXs can be used simultaniously by installing an extra PCB, containing two PGAs, on the original PGA.
NPX for Cyrix Cx486DLC CPU.
Clock doubled versions of IIT-4C87DLC NPX.
NPX for Intel i80486SX CPU.
In fact an Intel i80486DX CPU with different pin layout (in Intel i80487SX NPX socket) and one extra pin assigned to disable the Intel i80486SX CPU. The Intel i80486SX CPU can be removed.
Package: 169 pin PGA (Pin Grid Array).
step level B0: DH = 0x04 (family ID), DL = 0x21 (model ID, revision).
In fact an Intel i80486DX CPU with Intel i80486SX CPU pin layout (in Intel i80486SX CPU socket).
NPX for Cyrix FasCache Cx486D CPU.
NPX for Intel i80486 CPU.
Package: 142 pin, 3 row PGA (Pin Grid Array).

References: V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V.

 V. 
 V.