Source: http://www.eng.auburn.edu/~jaeger/pubs.html
Timestamp: 2019-04-19 23:24:42+00:00

Document:
2005 InterPack Best Paper of Conference: M. K. Rahim, J. C. Suhling, R. C. Jaeger, and P. Lall, "Evolution of die stress and delamination during thermal cycling of flip chip assemblies," Proceedings of InterPack 2005 (IPACK2005-73348), pp. 1-16, July 2005.
1999 IMAPS Best Paper of Conference: Y. Zou, R. W. Johnson, J. C. Suhling, R. C. Jaeger, J. Harris, C. Kromis, I. Ahmad, D. Tucker and Z. Fathi, "Comparison of die level stresses in chip-on-board packages processed with convection and variable frequency microwave encapsulant curing," Proceedings of the IMAPS International Conference on High Density Packaging and MCMs, pp. 77-86, April 1999.
1992 SEMITHERM Best Paper: A. Goyal, R. C. Jaeger, S. H. Bhavnani, C. D. Ellis, N. K. Phadke, M. Azimi-Rashti and J. S. Goodling, "Re-entrant cavity heat sink fabricated by anisotropic etching and silicon direct wafer bonding," 1992 IEEE SEMITHERM Proceedings, pp. 25-29, February 1992.
1986 ISHM Symposium: R. W. Johnson, M. B. Cornelius, J. L. Davidson, and R. C. Jaeger, "Planar hybrid interconnection technology," Proceedings of the 1986 ISHM International Symposium on Microelectronics, pp.758-765, October 1986, selected as one of the top five papers of the Symposium.
R. W. Johnson, J. L. Davidson, R. C. Jaeger and D. V. Kerns, "Silicon hybrid wafer-scale package technology," IEEE JSSC, Special Issue on Logic and Memory, vol. SC-21, no. 5, pp. 845-851, October 1986.
R. W. Johnson, R. C. Jaeger, J. L. Davidson, and D. V. Kerns, Jr., "Hybrid silicon wafer-scale packaging technology," IEEE International Solid-State Circuits Conference Digest, pp. 66-167, February 1986.
R. W. Johnson, M. B. Cornelius, J. L. Davidson, and R. C. Jaeger, "Planar hybrid interconnection technology," Proceedings of the 1986 ISHM International Symposium on Microelectronics, pp.758-765, October 1986. Selected as one of top five papers of the symposium.
R. C. Jaeger, R. W. Johnson and J. L. Davidson, "Silicon-based hybrid wafer-scale packaging," IFIP Workshop on Wafer-Scale Integration, Paper K1, March 1986.
R. W. Johnson, M. Cornelius, J. L. Davidson, and R. C. Jaeger, "Planar hybrid interconnect technology," International Journal for Hybrid Microelectronics, vol. 10, no. 1, pp. 28-35, 1st Quarter 1987.
W. C. Dillard, J. L. Davidson and R. C. Jaeger, "A high density anodized aluminum microstrip structure for high speed interconnections," Proceedings of the 1988 SPIE Conference, pp. 262-267, January 1988.
R. W. Johnson, T. L. Phillips, R. C. Jaeger, S. F. Hahn and D. C. Burdeaux, "Thin film silicon multichip technology," Proceedings of the Electronic Components Conference, vol. 871, pp. 267-275, May 1988.
R. W. Johnson, R. C. Jaeger and T. N. Blalock, "Wafer-scale multichip packaging technology," Wafer Scale Integration, Chapter 10, Kluwer Publishing Company, 1989.
R. W. Johnson, T. L. Phillips, R. C. Jaeger, S. F. Hahn and D. C. Burdeaux, "Multichip thin film technology on silicon," IEEE Trans. Components Hybrids and Manufacturing Technology," vol. 12, no. 2, pp. 185-194, June 1989.
C. L. Chen, R. W. Johnson, R. C. Jaeger, M. B. Cornelius and W. A. Foster, "Packaging technology for a low temperature astrometric sensor array," IEEE Trans. Components Hybrids and Manufacturing Technology, vol. 13, no. 4, pp. 1083-1089, December 1990.
R. E. Beaty, J. C. Suhling, C. A. Moody, D. A. Bittle, R. W. Johnson, R. D. Butler and R. C. Jaeger, "Calibration considerations for piezoresistive-based stress sensors," Proceedings of the Electronic Components and Technology Conference, pp. 797-806, May 1990.
D. A. Bittle, J. C. Suhling, R. E. Beaty, R. C. Jaeger and R. W. Johnson, "Structural analysis of electronic packages using test chips with integral piezoresistive stress sensors," 1990 ASME Winter Annual Meeting, paper 90-WA/EEP-12.
R. E. Beaty, R. W. Johnson, J. C. Suhling, D. A. Bittle, J. C. Pope and R. C. Jaeger, "Stress measurement in electronic packaging using silicon piezoresistive sensors," SRC TECHCON Digest, pp. 413-416, October 1990.
D. A. Bittle, J. C. Suhling, R. E. Beaty, R. C. Jaeger and R. W. Johnson, "Piezoresistive stress sensors for structural analysis of electronic packages," Journal of Electronic Packaging, pp. 203-215, September 1991.
J. C. Suhling, R. E. Beaty, R. C. Jaeger and R. W. Johnson, "Piezoresistive sensors for measurement of thermally-induced stresses in microelectronics," Proceedings of the 1991 Spring Conference of the Society for Experimental Mechanics, pp. 683-694, Milwaukee, WI, June 10-13, 1991.
J. C. Suhling, M. T. Carey, R. W. Johnson and R. C. Jaeger, "Stress measurement in microelectronic packages subjected to high temperatures," in Manufacturing Processes and Materials Challenges in Microelectronic Packaging, 1991 ASME Winter Annual Meeting, AMD-Vol. 131/EEP-Vol. 1, pp. 143-152, December 1991.
R. C. Jaeger, J. C. Suhling and R. Ramani, "Errors associated with the design and calibration of piezoresistive stress sensors in (100) silicon," Proceedings of the ASME/JSME Joint Conference on Electronic Packaging, vol. EEP-1-1, pp. 447-456, April 9-12, 1992.
Y. L. Kang, J. C. Suhling, and R. C. Jaeger, "Piezoresistive stress sensors on (110) silicon wafers," Proceedings of the VII Annual International Congress on Experimental Mechanics, pp. 705-712, June 1992.
R. E. Beaty, R. C. Jaeger, J. C. Suhling, R. W. Johnson, and R. D. Butler, "Piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixture," IEEE Trans. Components, Hybrids and Manufacturing Technology, vol. 15, no. 5, pp. 904-914, October 1992.
Y. L. Kang, J. C. Suhling and R. C. Jaeger, "Piezoresistive stress sensors on alternative crystal planes," 1992 ASME Winter Annual Meeting, Vol. 92-WA, paper EEP-17, pp. 1-10, December 1992.
J. C. Suhling, R. C. Jaeger, Y-L. Kang and R. A. Cordes, "A new wafer-level calibration procedure for piezoresistive stress sensors," Proceedings of the 1993 SEM Spring Conference on Experimental Mechanics, pp. 977-987, June 1993.
R. C. Jaeger, J. C. Suhling, M. T. Carey and R. W. Johnson, "A piezoresistive sensor chip for measurement of stress in electronic packaging," Proceedings of the 1993 Electronic Components and Technology Conference, pp. 686-692, June 1993.
R. C. Jaeger, J. C. Suhling and R. Ramani, "Thermally induced errors in the calibration and application of silicon piezoresistive stress sensors," Advances in Electronic Packaging 1993, ASME vol. EEP 4-1, pp. 457-470, September 1993.
R. C. Jaeger, J. C. Suhling, M. T. Carey and R. W. Johnson, "Off-axis sensor rosettes for measurement of the piezoresistive coefficients of silicon," IEEE Trans. Components, Packaging and Manufacturing Technology, vol. 16, no. 8, pp. 925-931, December 1993.
R. C. Jaeger, J. C. Suhling and R. Ramani, "Errors associated with the design, calibration and application of piezoresistive stress sensors in (100) silicon," IEEE Trans. Components, Hybrids and Manufacturing Technology, vol. 17, no. 1, pp. 97-107, February 1994.
J. C. Suhling, R. C. Jaeger and Y-L. Kang, "Silicon and silicon carbide stress sensors for application to electronic packaging," Proceedings of the1994 SEM Spring Conference on Experimental Mechanics, June 6-8, 1994.
R. C. Jaeger, J. C. Suhling, R. Ramani and A. Anderson, "A (100) silicon stress test chip with optimized piezoresistive sensor rosettes," Proceedings of the 1994 Electronic Components and Technology Conference (ECTC). pp. 741-749, May 1994.
J. C. Suhling, R. A. Cordes, Y. L. Kang and R. C. Jaeger, "Wafer-level calibration of stress sensing test chips," Proceedings of the 1994 Electronic Components and Technology Conference (ECTC), pp. 1058-1070, May 1994.
J. C. Suhling, R. C. Jaeger and A. Anderson "Optimized stress sensors for application to electronic packaging," Proceedings of the International Conference on Advances in Engineering Measurements, pp. 9-15, August 30, 1994, Edinburgh, Scotland.
J. C. Suhling, R. C. Jaeger and R. Ramani, "Stress measurements using 0-90 piezoresistive rosettes on (111) silicon," 1994 ASME winter Annual Meeting, vol. AMD-195, pp. 65-73, November 1994.
R. C. Jaeger, R. Ramanathan, and J. C. Suhling, "Effects of stress-induced mismatches on CMOS analog circuits," Proceeings of the 1995 International VLSI TSA Symposium, Taipei, Taiwan, May 1995, pp. 354-360.
R. C. Jaeger, R. Ramanathan, J. C. Suhling and Y. Kang, "CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETS)," Digest of Technical Papers of the 1995 International Symposium on VLSI Circuits, June 1995, pp. 43-44.
J. C. Suhling, R. A. Cordes, Y. Kang and R. C. Jaeger, "Optimal temperature compensated piezoresistive stress sensor rosettes,"Proceedings of the Symposium on Applications of Experimental Mechanics to Electronic Packaging, EEP-Vol. 12, AMD-Vol.-214, pp. 109-116, ASME IMECE, November, 1995.
R. A. Cordes, J. C. Suhling, Y. Kang, R. C. Jaeger and R. Ramanathan, "Application of a wafer-level calibration technique for stress sensing test chips," Proceedings of the Symposium on Applications of Experimental Mechanics to Electronic Packaging, EEP-Vol. 12, AMD-Vol.-214, pp. 79-94, ASME IMECE, November, 1995.
J. C. Suhling, R. C. Jaeger and S. T. Lin, "Piezoresistive sensors for measurement of packaging induced die stress," Proceedings of the VIIIth International Congress on Experimental Mechanics.
B. M. Wilamowski, J. C. Suhling, R. C. Jaeger, and S. T. Lin, "Design of Optimized (111) Stress Test Chips," 1996 ASME International Congress and Exhibition, November 17-22, 1996.
Y. Zou, S. T. Lin, J. C. Suhling and R. C. Jaeger, "Measurement of plastic packaging induced die stress," 1996 ASME International Congress and Exhibition, November 17-22, 1996.
J. C. Suhling, S. T. Lin, R. J. Moral, R. W. Johnson and R. C. Jaeger, "Measurement of die stress in advanced electronic packaging for space and terrestrial applications," Proceedings of the Space Technology and Applications International Forum, pp. 819-824, January 26-30, 1997, Albuquerque, NM.
J. C. Suhling, R. C. Jaeger, S. T. Lin, R. J. Moral and Y. Zou, "Measurement of the complete stress state in plastic encapsulated packages," Proceedings of the 1997 InterPACK Conference, ASME EEP-Vol. 19-2, pp. 1741-1750, June 15-19, 1997.
J. C. Suhling, R. C. Jaeger, S. T. Lin, A. K. M. Mian, Y. Zou and B. M. Wilamowski, "Design and calibration of optimized (111) silicon stress sensing test chips," Proceedings of the 1997 InterPACK Conference, ASME EEP-Vol. 19-2, pp. 1723-1729, June 15-19, 1997.
R. C. Jaeger, A. T. Bradley, J. C. Suhling and Y. Zou, "FET mobility degradation and device mismatch due to packaging induced die stress," Proceedings of the 23rd European Spolid-State Circuits Conference (ESSCIRC), pp. 272-275, September 1997.
R. C. Jaeger and J. C. Suhling, "Advances in Stress Test Chips," Proceedings of the 1997 ASME International Congress and Exhibition, November 1997.
Y. Zou, S. T. Lin, J. C. Suhling, R. C. Jaeger, L. Nguyen and S. A. Gee, "Characterization of plastic packages using (100) and (111) silicon stress test chips," Proeedings of the 1997 ASME International Congress and Exhibition, ASME vol. EEP-22, pp. 15-21, November 1997.
Y. Zou, J. C. Suhling, R. C. Jaeger and H. Ali, "Comparison of stresses within delaminated and non-delaminated plastic packages," Proceedings of the 1997 ASME International Congress and Exhibition, November 1997.
Y. Kang, J. C. Suhling, R. C. Jaeger, and A. Mian, "Hydrostatic response of piezoresistive stress sensors," Proceedings of the 1997 ASMEInternational Congress and Exhibition, November 1997.
A. Mian, J. C. Suhling, R. C. Jaeger and B. M. Wilamowski, "Evaluation of die stress using van der Pauw sensors," Proceedings of the 1997 ASME International Congress and Exhibition, EEP vol. 22, pp. 59-67, November 1997.
C-H. Cho, R. C. Jaeger, J. C. Suhling, "Evaluation of the temperature dependence of the combined piezoresistive coefficients of (111) silicon using chip-on-beam and hydrostatic calibration," Journal of the Korean Physical Society, vol. 52, no. 3, pp. 612-620, March 2008.
C-H. Cho, R. C. Jaeger, J. C. Suhling, Y. Kang and A. Mian, "Characterization of the temperature dependence of the pressure coefficients of n- and p-type silicon using hydrostatic testing," IEEE Sensors Journal, vol. 8, no. 4, pp. 392-400, April 2008.
C-H. Cho, R. C. Jaeger, and J. C. Suhling, "The effect of transverse sensitivity on measurement of the piezoresistive coefficients of silicon," Japanese Journal of Applied Physics, vol. 47, no. 5, pp. 3647-3656, May 2008.
C-H. Cho, R. C. Jaeger, J. C. Suhling, "Characterization of the temperature dependence of the piezoresistive coefficients of silicon from -150 oC to +125 oC," IEEE Sensors Journal, vol. 8, no. 8, pp. 1455-1468, August 2008.
J. C. Roberts, M. Motalab, S. Hussain, J. C. Suhling, R. C. Jaeger, and P. Lall, "Characterization of compressive die stresses in CBGA microprocessor packages due to component assembly and heat sink clamping," ASME Journal of Electronic Packaging, vol. 134, no. 3, pp. 031005-1-031005-17, September 2012.
Y. Chen, R. C. Jaeger and J. C. Suhling, "CMOS sensor arrays for high resolution die stress mapping in packaged integrated circuits,"IEEE Sensors Journal, vol. 13. No. 6, pp. 2066-2076, June 2013.
R. C. Jaeger, M. Motalab, S. Hussain and J. C. Suhling, "Four-wire bridge measurements of silicon van der Pauw stress sensors," Journal of Electronic Packaging, vol. 136, pp. 041014-1-041014-10, December 2014.
R. C. Jaeger, J. S. Goodling, N. V. Williamson, C. D. Ellis, R. M. O'Barr, R. W. Johnson and T. D. Slagh, "Test section design for evaluation of cooling of silicon wafer-scale packaging," Proceedings of the International Electronics Packaging Society Conference," pp. 944-953, November 1987.
J. S. Goodling, R. C. Jaeger, N. V. Williamson, C. D. Ellis and T. D. Slagh, "Wafer scale cooling using jet impingement boiling heat transfer," ASME Winter Annual Meeting, paper 87-WA/EEP-3, Boston, MA, December 13-18, 1987.
J. S. Goodling, R. W. Knight and R. C. Jaeger, "Cooling tomorrow's computer systems," Computers in Mechanical Engineering, pp. 16-22, May 1988.
R. C. Jaeger, J. S. Goodling, M. E. Baginski, C. D. Ellis, N. V. Williamson, and R. M. O'Barr, "High heat flux cooling for silicon-on-silicon packaging," IEEE SEMITHERM V Proceedings, pp. 104-111, February 1989.
R. C. Jaeger, J. S. Goodling, M. E. Baginski, C. D. Ellis, N. V. Williamson, and R. M. O'Barr, "High heat flux cooling for silicon hybrid multichip packaging," IEEE Trans. Components Hybrids and Manufacturing Technology, vol. 12, no. 4, pp. 772-779, December 1989.
M. Azimi-Rhasti, R. C. Jaeger, M. E. Baginski and J. S. Goodling, "Liquid freon immersion cooling for microelectronic applications," Proceedings of the National Electronics Packaging Conference, pp. 1643-1649, February 1990.
S. H. Bhavnani, C-P. Tsai and R. C. Jaeger, "Pool boiling characteristics of enhanced hybrid silicon surfaces," Proceedings of Heat Transfer in 'Electronic Equipment 1991, HTD-Vol. 171, pp. 19-27, July 1991.
M. Azimi-Rashti, C. D. Ellis, R. C. Jaeger, S. H. Bhavnani and J. S. Goodling, "A microelectronic structure for basic heat transfer studies," IEEE Transducers '91 Digest of Technical Papers, pp. 639-642.
N. K. Phadke, S. H. Bhavnani, A. Goyal, R. C. Jaeger and J. S. Goodling, "Re-entrant cavity surface enhancements for immersion cooling of silicon multichip packages," Proceedings of the Third IEEE/ASME Intersociety Conference on Thermal Phenomena in Electronic Systems, pp. 59-65, February 1992.
N. K. Phadke, S. H. Bhavnani, R. C. Jaeger, J. S. Goodling, C. D. Ellis and S. Bhutani, "Enhanced surfaces for cooling high flux microelectronic components," Proceedings of the ASME/JSME Joint Conference on Electronic Packaging, pp. 253-261, April 9-12, 1992.
R. W. Knight, D. J. Hall, J. S. Goodling and R. C. Jaeger, "Heat sink optimization with applications to microchannels," IEEE Trans. Components, Hybrids and Manufacturing Technology, vol. 15, no. 5, pp. 832-842, October 1992.
N. K. Phadke, S. H. Bhavnani, A. Goyal, R. C. Jaeger and J. S. Goodling, "Re-entrant cavity surface enhancements for immersion cooling of silicon multichip packages," IEEE Trans. Components, Hybrids and Manufacturing Technology, vol. 15, no. 5, pp. 815-822, October 1992.
A. Goyal, S. H. Bhavnani, R. C. Jaeger, C. D. Ellis, J. S. Goodling and M. Azimi-Rashti, "Formation of silicon re-entrant cavity heat sinks using anisotropic etching and direct wafer bonding," IEEE Electron Device Letters, vol EDL-14, no. 1, pp. 29-32, January 1993.
M. Azimi and R. C. Jaeger, "A microelectronic test structure and numerical algorithm for characterization of liquid immersion cooling," IEEE Trans. Components, Hybrids and Manufacturing Technology, vol. 16, no. 3, pp. 253-265, May 1993.
S. H. Bhavnani, C-P. Tsai, R. C. Jaeger and D. L. Eison, "An integral heat sink for cooling microelectronic components," ASME Journal of Electronic Packaging, vol. 115, pp. 284-291, September 1993.
R. C. Jaeger and M. Azimi, "A microelectronic test structure and numerical algorithm for characterization of liquid immersion cooling with application to optimum multichip module substrate thickness," Advances in Electronic Packaging 1993, ASME vol. EEP 4-2, pp. 859-870, September 1993.
S. Hingnorani, C. J. Fahrner, D. W. Mackowski, J. S. Goodling and R. C. Jaeger, "Optimal sizing of planar thermal spreaders," ASME Journal of Heat Transfer, pp. 296-301, May 1994.
S. H. Bhavnani, R. C. Jaeger, N. K. Phadke, J. S. Goodling and S. Bhutani, "Immersion cooling of microelectronics using direct-bonded heat sinks," ASME Journal of Electronic Packaging, accepted for publication.
S. E. Balch, S. H. Bhavnani, R. C. Jaeger, and S. Bhutani, "Pool boiling interactions between multiple heat sources in an array of silicon chips," Proceedings of IEEE I-THERM IV, pp. 9-15, May 1994.
R. M. Nowell, S. H. Bhavnani and R. C. Jaeger, "Effect of channel width on pool boiling from a microconfigured heat sink," Proceedings of IEEE I-THERM IV, pp. 163-168, May 1994.
M. Azimi-Rashti, and R. C. Jaeger, "Substrate thickness optimization for liquid immersion cooled silicon multichip modules," IEEE Trans. Components, Packaging and Manufacturing Technology - Part B: Advanced Packaging, vol. 18 no. 1, pp. 144-149, February 1995.
R. M. Nowell, S. H. Bhavnani and R. C. Jaeger, "Effect of channel width on pool boiling from a microconfigured heat sink," IEEE Trans. Components, Packaging and Manufacturing Technology - Part A, vol. 18, no. 3, pp. 534-539, September 1995.
S. K. Hingorani, J. S. Goodling, R. W. Knight and R., C. Jaeger, "Experimental investigation of jet impingement heat transfer," 1996 IEEE/ASME ITHERM, May 28, 1996, Orlando , FL.
Nitesh D. Nimkar, Sushil H. Bhavnani and Richard C. Jaeger, "Benchmark heat transfer data for microstructured surfaces for immersion-cooled microelectronics," IEEE Trans. Components and Packaging Technologies, vol. 29, no. 1, pp. 89-97, March 2006.
R. C. Jaeger and F. H. Gaensslen, "MOS devices and switching behavior," in Low Temperature Electronics, R. K. Kirschman, Editor, IEEE PRESS, New York: 1986.
F. H. Gaensslen and R. C. Jaeger, "Foreword," Special Issue on Low Temperature Semiconductor Electronics, IEEE Trans. Electron Devices, vol. ED-34, no. 1, pp. 1-3, January 1987.
F. H. Gaensslen and R. C. Jaeger, "Foreword," Second Special Issue on Low Temperature Semiconductor Electronics, IEEE Trans. Electron Devices, vol. ED-36, no. 8, pp. 1401-1403, August 1989.
R. J. Krane, R. C. Jaeger, F. H. Gaensslen and A. Bar-Cohen, "MOS electronics and thermal control design for low temperature computer systems," in Advances in Thermal Modeling of Electronic Components & Systems - Vol. II, Hemisphere Press, 1989.
F. H. Gaensslen and R. C. Jaeger, "Low temperature threshold behavior of depletion-mode devices - Characterization and simulation," IEEE IEDM Digest 24.3, pp. 520-524, December 1977.
F. H. Gaensslen and R. C. Jaeger, "Temperature dependent threshold behavior of depletion-mode MOSFETS - Characterization and simulation," Solid-State Electronics, vol. 22, no. 4, pp. 423-430, April 1979, Reprinted in Low Temperature Electronics, IEEE PRESS, New York: 1986.
R. C. Jaeger and F. H. Gaensslen, "Simple analytical models for the temperature dependent threshold behavior of depletion-mode devices," IEEE JSSC Joint Special Issue on VLSI, vol. SC-14, no. 4, pp. 423-430, April 1979, and IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 501-508, April 1979.
F. H. Gaensslen and R. C. Jaeger, "Behavior of electrically small depletion-mode MOSFET's at low temperature," Solid-State Electronics, vol. 24, pp. 215-220, March 1981.
R. C. Jaeger, F. H. Gaensslen and S. E. Diehl, "Efficient simulation of MOS capacitance for a wide range of temperatures, impurity distributions and surface state densities," IEEE ISSCC Digest, pp. 14-15, 280, February 1982.
R. C. Jaeger and F. H. Gaensslen, "Simulation of impurity freezeout through numerical solution of Poisson's equation with application to MOS device behavior," IEEE Trans. Electron Devices, vol. ED-27, no. 5, pp. 914-920, May 1980.
J. G. Dooley and R. C. Jaeger, "Temperature dependence of latch-up in CMOS circuits," IEEE Electron Device Letters, vol. EDL-5, no. 2, pp. 41-43, February 1984. Reprinted in Low Temperature Electronics, IEEE PRESS, New York: 1986.
F. H. Gaensslen and R. C. Jaeger, "Anomalous MOS capacitance behavior in depletion-mode structures," IEEE Trans. Electron Devices, vol. ED-31, no. 12, pp. 1916-1918, December 1984.
R. M. Fox, P. L. Heedley and R. C. Jaeger, "Design and performance of analog MOS circuits for low temperature operation," Digest of the 1984 IEEE International Symposium on Circuits and Systems, pp.1219-1222, May 1984. R. M. Fox and R. C. Jaeger, "Analysis and design of CMOS analog circuits for operation at liquid nitrogen temperature," IEEE UGIM '85 Proceedings, pp. 117-121, June 1985.
W. C. Dillard and R. C. Jaeger, "The temperature dependence of hybrid-pi circuit parameters," IEEE UGIM '85 Proceedings, pp. 22-128, June 1985.
R. M. Fox and R. C. Jaeger, "MOS models and amplifier design for low temperature operation," IEEE 1986 International Symposium on Circuits and Systems Proceedings, pp. 1154-1156, May 1986.
M. Chrzanowska-Jeske and R. C. Jaeger, "Modeling of temperature dependent transport parameters for low temperature bipolar transistor simulation," Proceedings of the 172nd Electrochemical Society Meeting, vol. 88-9, pp. 185-199, Honolulu, Hawaii, October 1987.
R. M. Fox and R. C. Jaeger, "MOSFET behavior and circuit considerations for analog applications at 77K," IEEE Trans. Electron Devices, Special Issue on Low Temperature Semiconductor Electronics, vol. ED-34, no. 1, pp. 114-123, January 1987.
M. Chrzanowska-Jeske and R. C. Jaeger, "Temperature range extension and boundary condition modifications for the MOSCAP simulation program," IEEE Trans. Electron Devices, Special Issue on Low Temperature Semiconductor Electronics, vol. ED-34, no. 1, pp. 142-143, January 1987.
W. C. Dillard and R. C. Jaeger, "The temperature dependence of the amplification factor of bipolar junction transistors," IEEE Trans. Electron Devices, Special Issue on Low Temperature Semiconductor Electronics, vol. ED- 34, no. 1, pp. 139-142, January 1987.
M. Chrzanowska-Jeske and R. C. Jaeger, "BILOW - Simulation of low temperature bipolar device behavior," IEEE Trans. Electron Devices, Special Issue on Low Temperature Semiconductor Electronics, vol. ED-36, no. 8, pp. 1475-1488, August 1989.
P. L. Heedley and R. C. Jaeger, "An analytical model for BiCMOS logic transient response allowing for parameter variations," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 13.4.1-13.4.4, April 1989.
M. Chrzanowska-Jeske and R. C. Jaeger, "Steady-state bipolar transistor simulator for the 77K - 300K temperature range," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 9.2.1-9.2.4, April 1989.
M. Chrzanowska-Jeske and R. C. Jaeger, "A numerical study of the temperature dependence of silicon bipolar transistor fT (77K-300K)," Proceedings of the 1989 Low Temperature Workshop, pp. 33-37, Burlington, VT, August 1989.
K. B. Hong and R. C. Jaeger, "Experimental survey of semiconductor power device operation at low temperature," Proceedings of the 1989 Low Temperature Workshop, pp. 99-103, Burlington, VT, August 1989.
P. L. Heedley and R. C. Jaeger, "Characterization and modeling of BICMOS logic for low temperature operation," Proceedings of the 1989 Low Temperature Workshop, pp. 1-4, Burlington, VT, August 1989.
R. C. Jaeger and T. N. Blalock, "Quasi-Static RAM Design for High Performance Operation at Liquid Nitrogen Temperature," Cryogenics, vol. 30, no. 12, pp. 1030-1035, December 1990.
T. N. Blalock and R. C. Jaeger, "An experimental 2T cell RAM with 7 ns access time at low temperature," Proceedings of the 1990 International Symposium on VLSI Circuits, pp. 13-14, June 7, 1990, Honolulu, Hawaii.
T. N. Blalock and R. C. Jaeger, "Quasi-Static RAM Design for High Performance Operation at Liquid Nitrogen Temperature," Proceedings of the International Conference on Low Temperature Electronics, April 1990.
T. N. Blalock and R. C. Jaeger, "Optimization of CMOS low temperature quasi-static RAM based on non-destructive readout dynamic cell structures," Proceedings of the1991 ECS Symposium on Low Temperature Electronic Device Operation, pp. 178-185.
C-L. Chen and R. C. Jaeger, "Anomalous retention time behavior in dynamic memory cells at low temperature," 1991 ECS Symposium on Low Temperature Electronic Device Operation, presentation only.
D. M. Richey, R. E. Beaty and R. C. Jaeger, "Observations on low temperature NPN bipolar transistor simulations using BILOW," Proceedings of the 1991 ECS Symposium on Low Temperature Electronic Device Operation, pp. 75-81.
K-B. Hong and R. C. Jaeger, "Power MOSFET modeling and application at liquid nitrogen temperature," Proceedings of the1991 ECS Symposium on Low Temperature Electronic Device Operation, pp. 238-245.
J. D. Cressler, D. M. Richey, R. C. Jaeger, E. F. Crabbe, J. H. Comfort, and J. M. C. Stork, "High-injection barrier effects in SiGe NBTs operating at cryogenic temperatures," Journal de Physique IV, vol. 4, pp. C6-117-122, June 1994.
D. M. Richey, J. D. Cressler and R. C. Jaeger, "Numerical simulation of SiGe HBT's at cryogenic temperatures," Supplement au Journal de Physique III, vol. 4, pp. C6-127-132, June 1994. D. M. Richey, A. J. Joseph, J. D. Cressler and R. C. Jaeger, "Evidence for non-equilibrium base transport in Si and SiGe bipolar transistors at cryogenic temperatures," Solid-State Electronics.
D. M. Richey, J. D. Cressler and R. C. Jaeger, "Numerical simulation of SiGe HBT's at cryogenic temperatures," Proceedings of the International Conference on Low Temperature Electronics, Grenoble, France, June 1994.
J. D. Cressler, D. M. Richey, R. C. Jaeger, E. F. Crabbe, J. H. Comfort and J. M. C. Stork, "High injection barrier effects in SiGe HBT's operating at cryogenic temperatures," Proceedings of the International Conference on Low Temperature Electronics, Grenoble, France, June 1994.
D. M. Richey, J. D. Cressler and R. C. Jaeger, "Low temperature simulation of SiGe HBTs using SCORPIO," 1995 ECS Symposium on Low Temperature Electronics.
D. M. Richey, A. J. Joseph, J. D.Cressler and R. C. Jaeger, "Non-equilibrium base transport in Si and SiGe bipolar transistors at cryogenic temperatures," Proceedings of the 1995 IEEE Bipolar /BICMOS Circuits and Technology Meeting, pp.35-38, October 1995.
A. J. Joseph, J. D. Cressler, R. C. Jaeger, D. M. Richey and D. L. Harame, "Neutral base recombination in advanced SiGe HBTs and its impact on the temperature characteristics of precision analog circuits," Digest of the 1995 IEEE International Electron Devices Meeting, pp. 755-758, December 1995.
M. S. Latham, J. D. Cressler, A. J. Joseph and R. C. Jaeger, "The impact of Ge grading on the bias and temperature characteristics of SiGe HBT precision voltage references," Proceedings of the Second European Workshop on Low Temperature Electronics International (WOLTE2), Leuven, Belgium, June 1996.
A. J. Joseph, J. D. Cressler, D. M. Richey, R. C. Jaeger and D. L. Harame, "Neutral base recombination and its influence on the temperature dependence of Early voltage and current gain - Early voltage product in UHV/CVD SiGE heterojunction bipolar transistors," IEEE Trans. on Electron Devices, vol. 44, no. 3, pp. 401-413, March 1997.
Y. Yao, F. F. Dai, R. C. Jaeger and J. D. Cressler, "A 12-bit cryogenic and radiation tolerant digital-to-analog converter for aerospace extreme environment applications," IEEE Trans. Industrial Electronics, vol. 55, no. 7, pp. 2810-2819, July 2008.
R. C. Jaeger and G. A. Hellwarth, "Dynamic zero-correction method suppresses offset error in op-amps," Electronics, pp. 109-110, December 4, 1972.
R. C. Jaeger and G. A. Hellwarth, "A differential zero-correction amplifier," IEEE JSSC, vol. SC-8, pp. 235-236, June 1973.
R. C. Jaeger and G. A. Hellwarth, "Cascode differential pairs," Electronic Design, March 15, 1973.
R. C. Jaeger and G. A. Hellwarth, "Differential cascode amplifier offers unique advantages," EDN, pp. 78-80, June 5, 1974.
R. C. Jaeger, "Common-mode rejection ratio analysis using the adjoint network," IEEE Trans. Circuits and Systems, vol. CAS-21, pp. 155-156, January 1974.
R. C. Jaeger, "A high output resistance current source," IEEE JSSC, vol. SC-9, pp. 192-194, August 1974.
R. C. Jaeger and G. A. Hellwarth, "On the performance of the differential cascode amplifier," IEEE JSSC, vol. SC-8, pp. 169-174, April 1973. "Correction to 'On the performance ...'," IEEE JSSC, vol. SC-10, pp. 252, August 1975.
R. C. Jaeger, "Comments on 'An optimized output stage for MOS integrated circuits'," IEEE JSSC, vol. SC-10, pp. 185-186, June 1975.
R. C. Jaeger, "Common-mode rejection limitations of differential amplifiers," IEEE JSSC, vol. SC-11, pp. 411-417, June 1976.
R. C. Jaeger, "Unifying the concepts of offset voltage and common-mode rejection ratio," IEEE JSSC, vol. SC-11, pp. 557-561, August 1976.
R. C. Jaeger, S. W. Director and A. J. Brodersen, "Computer-aided characterization of differential amplifiers," IEEE JSSC, vol. SC-12, pp. 83- 86, February 1977.
R. C. Jaeger, "CMRR performance limits of analog multiplexers using normal-mode filters," IEEE Trans. Instrumentation and Measurement, vol. IM-30, pp. 129-132, June 1981.
R. C. Jaeger, "Analog data acquisition technology - Part I: Digital-to-analog converters," IEEE MICRO, pp. 20-37, May 1982.
R. C. Jaeger, "Analog data acquisition technology - Part II: Analog-to-digital converters," IEEE MICRO, pp. 46-57, August 1982.
R. C. Jaeger, "Analog data acquisition technology - Part III: Sample-and-holds, instrumentation amplifiers, and analog multiplexers," IEEE MICRO, pp. 20-34, November 1982.
R. C. Jaeger, "Analog data acquisition technology - Part IV: System design, analysis and performance," IEEE MICRO, pp. 52-61, February 1983.
R. C. Jaeger, R. M. Fox and S. E. Diehl, "Analytical expressions for the critical charge in CMOS static RAM cells," IEEE Trans. Nuclear Science, vol. NS-30, pp. 4616-4619, December 1983.
R. C. Jaeger, R. M. Fox and S. E. Diehl, "Analytical expressions for the critical charge in CMOS static RAMs," 1983 IEEE NSRE Conference, July 1983.
R. C. Jaeger and R. M. Fox, "Phase plane analysis of the upset characteristics of CMOS RAM cells," IEEE UGIM '85 Proceedings, pp. 183-187, June 1985.
Y. J. Hsu, V. P. Nelson and R. C. Jaeger, "A gate array design of a shuffle/exchange network switching element," IEEE UGIM '85 Proceedings, pp. 158-164, June 1985.
Y. J. Hsu, V. P. Nelson and R. C. Jaeger, "A random self-test structure for LSI/VLSI chips," IEEE UGIM '87 Proceedings, pp. 100-105, June 1987.
T. N. Blalock and R. C. Jaeger, "A high speed clamped-bit-line current-mode sense amplifier," IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 542-548, April 1991.
T. N. Blalock and R. C. Jaeger, "A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs," Proceedings of the 1991 International Symposium on VLSI Circuits, pp. 61-62, May 1991.
T. N. Blalock and R. C. Jaeger, "High speed clamped-bit-line sensing 1T dynamic RAMs," Proceedings of the 1991 International Symposium on VLSI Technology, Systems and Applications, pp. 82-86, Taipei, Taiwan, May 1991.
T. N. Blalock and R. C. Jaeger, "A high speed sensing scheme for 1T dynamic RAMs utilizing the clamped-bit-line sense amplifier," IEEE Journal of Solid-State Circuits, vol. SC-27, no. 4, pp. 618-625, April 1992.
M. Tomana, R. W. Johnson, R. C. Jaeger and W. C. Dillard, "A hybrid silicon carbide differential amplifier for 350C operation," IEEE Trans. Components, Hybrids and Manufacturing Technology, vol. 16, no. 5, pp. 536-542, August 1993.
M. Tomana, R. W. Johnson, R. C. Jaeger and John Palmour, "A SiC hybrid differential amplifier for 350C operation," Proceedings of the 1992 Electronic Components and Technology Conference, pp. 157-161.
W. C. Dillard, J. B. Cassady, R. C. Jaeger, R. W. Johnson and D. C. Sheridan, "A hybrid 4-H silicon carbide operational amplifier,"Third International High Temperature Electronics Conference - "HiTEC 1996".
B. M. Wilamowski and R. C. Jaeger, "Implementation of RBF type networks by MLP networks," Proceedings of the IEEE International Conference on Neural Networks, pp. 1670-1675, June 1996.
B. M. Wilamowski, R. C. Jaeger, M. Padgett and L. J. Myers, "CMOS implementation of a pulse-coupled neuron cell," Proceedings of the IEEE Internatinal Conference on Neural Networks, pp. 986-990, June 1996.
B. M. Wilamowski, M. L. Padgett and R. C. Jaeger, "Pulse-coupled neurons for image filtering," Proceedings of the World Congress of Neural Networks, pp. 851-854, September 15-20, 1996.
B. M. Wilamowski and R. C. Jaeger, "Neuro-fuzzy architecture for CMOS implementation," accepted for publication by the IEEE Transactions on Industrial Electronics.
L. S. J. Chimakurthy, Malinky Ghosh, Foster F. Dai and Richard C. Jaeger, "A novel DDS using nonlinear ROM addressing with improved compression ratio and quantization noise," IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 53, no. 2, pp. 274-283, February 2006.
Weining Ni, Foster F. Dai, Shi Yin and Richard C. Jaeger, "A direct digital frequency synthesizer with fourth-order phase domain ΔΣ interpolator and 12-bit current-steering DAC," IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 839-850, April 2006.
V. Kakani, F. F. Dai and R. C. Jaeger, "A 5-GHz low-power series-coupled BiCMOS quadrature VCO with wide tuning range," IEEE Microwave and Wireless Components Letters, vol. 17, no. 6, pp. 457-459, June 2007.
X. Yu, F. F. Dai, J. D. Irwin and R. C. Jaeger, "A 9-bit quadrature direct digital synthesizer implemented in 0.18-um SiGe BiCMOS technology," IEEE Trans. on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1257-1266, May 2008.
X. Yu, F. F. Dai, J. D. Irwin and R. C. Jaeger, "A 12 GHz 1.9 W direct digital synthesizer MMIC implemented in 0.18 um SiGe BiCMOS technology," IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1384-1393, June 2008.
D. Yang, F. F. Dai, W. Ni, Y. Shi and R. C. Jaeger, "Delta-sigma modulation for direct digital frequency synthesis," IEEE Transactions on VLSI Systems, vol. 17, no. 6, pp. 793-802, 2009.
X. Geng, X. Yu, F. F. Dai, J. D. Irwin and R. C. Jaeger, "An 11-bit 8.6 GHz direct digital synthesizer MMIC with 10-bit segmented sine-weighted DAC," IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 300-313, February 2010.
J. Yu, F. F. Dai, and R. C. Jaeger, "A 12-bit vernier ring time-to-digital converter in 0.13 um CMOS technology," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 830-842, April 2010.
X. Geng, F. F. Dai, J. D. Irwin and R. C. Jaeger, "24-bit 5.0 GHz direct digital synthesizer RFIC with direct digital modulations in 0.13 um SiGe BiCMOS technology," IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 944-954, April 2010.
D. Ma, F. F. Dai, R. C. Jaeger and J. D. Irwin, "An X- and Ku-Band Recursive Receiver MMIC with Gain-Reuse," IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 562-571, March 2011.
R. C. Jaeger and A. J. Brodersen, "Low frequency noise sources in bipolar junction transistors," IEEE Trans. Electron Devices, vol. ED-17, pp.128-134, February 1970.
A. J. Brodersen, R. C. Jaeger and E. R. Chenette, "Noise in integrated circuit transistors," IEEE JSSC, vol. SC-5, pp. 63-66, April 1970.
R. C. Jaeger, "An evaluation of injection modeling," IEEE ISSCC Digest THAM 9.3, February 1976.
R. C. Jaeger, "An evaluation of injection modeling," Solid-State Electronics, vol. 19, pp. 639-643, July, 1976. Reprinted in Integrated Injection Logic, IEEE PRESS, New York: 1980.
R. C. Jaeger and A. J. Brodersen, "Self consistent bipolar transistor models for computer simulation," Solid-State Electronics, vol. 21, no. 10, pp. 1269-1272, October 1978.
B. M. Wilamowski and R. C. Jaeger, "The lateral punch-through transistor," IEEE Electron Device Letters, EDL-3, no. 10, pp. 277-280, October 1982.
R. C. Jaeger, F. H. Gaensslen and S. E. Diehl, "An efficient numerical algorithm for simulation of MOS capacitance," IEEE Trans. Computer-Aided Design, vol. CAD-2, no. 2, pp. 111-116, April 1983.
W. C. Yeh, R. C. Jaeger and K. B. Cook, "A new CMOS structure," IEEE Electron Device Letters, vol. EDL-4, no. 6, pp. 196-198, June 1983.
B. M. Wilamowski, J. N. Fordemwalt and R. C. Jaeger, "Buried-channel MOS transistor with punch-through," Solid-State Electronics, vol. 27, no. 8/9, pp. 811-815, August/September 1984.
R. C. Jaeger, K. Daneshvar, R. M. Fox, and W. C. Dillard, "Direct measurement of the available voltage gain of Bipolar and MOS transistors," IEEE Electron Device Letters, vol. EDL-6, pp. 219-220, May 1985. L. E. Fosdick, J. L. Anderson, T. A. Baginski, and R. C. Jaeger, "Amperometric response of microlithographically fabricated microelectrode array flow sensors in a thin-layer channel," Analytical Chemistry, vol. 58, no. 13, pp. 2750-2756, November 1986.
R. C. Jaeger, "Automated MOS impurity profile design," Digest of the 1984 IEEE Custom Integrated Circuits Conference, pp. 329-334, May 1984.
R. C. Jaeger, "Computer-aided design of one-dimensional MOSFET impurity profiles," IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, pp. 198-203, January 1986.
J. Bromstead, B. Weir, R. C. Jaeger, R. W. Johnson and E. D. Baumann, "Performance of semiconductor power devices at high temperature," Proceedings of the 1st International Conference on High Temperature Electronics, pp. 27-35, Albuquerque, NM, June 16-20, 1991.
J. A. Babcock, J. D. Cressler, L. S. Vempati, S. D. Clark, R. C. Jaeger and D. L. Harame, "Ionizing radiation tolerance and low-frequency noise degradation in UHV/CVD SiGe HBTs," IEEE Electron Device Letters, vol. 16, no. 8, pp. 351-353, August 1995.
J. A. Babcock, J. D. Cressler, L. S. Vempati, R. C. Jaeger and D. L. Harame, "Ionizing radiation tolerance of high-performance SiGe HBT's grown by UHV/CVD," IEEE Trans. Nuclear Science, vol. 42, no. 6, pp. 1558-1566, December 1995.
J. D. Cressler, L. Vempati, J. A. Babcock, R. C. Jaeger and D. L. Harame, "Low-frequency noise characteristics of UHV/CVD epitaxial Si- and SiGe-base bipolar transistors," IEEE Electron Device Letters, vol. 17, no. 1, pp. 13-15, January 1996.
L. S. Vempati, J. D. Cressler, J. A. Babcock, R. C. Jaeger, and D. L. Harame, "Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors," IEEE Journal of Solid-State Ciircuits, vol. 31, no. 10, pp. 1458-1467, October 1996.
J. A. Babcock, J. D. Cressler, S. D. Clark, L. S. Bhamidipati, R. C. Jaeger and D. L. Harame, "Radiation tolerance of high-performance SiGe HBTs grown by UHV/CVD," 1995 IEEE Nuclear and Space Radiation Effects Conference.
L. S. Vempati, J. D. Cressler, R. C. Jaeger and D. L. Hareme, "Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors," Proceedings of the1995 IEEE Bipolar/ BICMOS Circuits and Technology Meeting, pp. 129-132, October 1995.
R. C. Jaeger, Microelectronic Circuit Design, McGraw Hill, New York: 1997 (1150 pages).
R. C. Jaeger, Introduction to Microelectronic Fabrication, Addison-Wesley, Reading, MA: 1987 (230 pages).
R. C. Jaeger, "An LSI/VLSI design course using commercial CMOS gate arrays," 1983 IEEE UGIM Symposium Digest, May 1983.
R. C. Jaeger, Y. Tzeng, K. Daneshvar, T. A. Baginski and J. L. Davidson, "The Alabama Microelectronics Science and Technology Center and the microelectronics program at Auburn University," IEEE UGIM '85 Proceedings, pp. 42-45, June 1985.
R. W. Johnson, J. L. Davidson and R. C. Jaeger, "Microelectronics at Auburn University," Proceedings of the International Electronic Packaging Society Conference," pp. 353-360, October 1985.
R. C. Jaeger, "Microelectronic fabrication," IEEE Potentials, pp. 33-36, May 1987.
R. W. Johnson, D. C. Hopkins and R. C. Jaeger, "The microelectronics program at Auburn University," Proceedings of the 1989 International Symposium on Hybrid Microelectronics, pp. 367-375, October 1989. Selected as the best paper of its session.
R. C. Jaeger, "Development of low temperature CMOS for high performance systems," IEEE International Conference on Computer Design: VLSI in Computers, pp.128-130, October 1986.
F. H. Gaensslen and R. C. Jaeger, "Low temperature MOS microelectronics," Proceedings of the IFIP VLSI-87 International Conference, Vancouver, British Columbia, Canada, August 10-12, 1987.
R. C. Jaeger and F. H. Gaensslen, "Low temperature MOS microelectronics," Proceedings of the 172nd Electrochemical Society Meeting, vol. 88-9, pp. 43-54, Honolulu, Hawaii, October 1987.
R. C. Jaeger and F. H. Gaensslen, "Low temperature semiconductor electronics," IEEE/ASME I-THERM Proceedings, pp. 106-114, May 11-13, 1988.
F. H. Gaensslen and R. C. Jaeger, "Low temperature MOS VLSI," Proceedings of Digitale Speicher, VDE-Verlag, pp. 341-351, September 19-21, 1988, Darmstadt, West Germany.
R. C. Jaeger, "High heat flux cooling for VLSI systems," Proceedings of CCVLSI-89, pp. 225-233, Vancouver, British Columbia, Canada, October 1989.
F. H. Gaensslen and R. C. Jaeger, "Low temperature microelectronics," Proceedings of the International Conference on Solid-State Devices and Materials, pp. 353-356, Sendai, Japan, August 1990.
R. C. Jaeger and F. H. Gaensslen, "Low temperature semiconductor microelectronics," Seventh International Conference on Microelectronics, Minsk, USSR, October 16, 1990, presentation only.
R. C. Jaeger, L. M. Terman, P. W. Verhofstadt and P. K. Chatterjee, "A view of microelectronics in the USSR," IEEE International Solid State Circuits Conference Digest, pp. 222-223, February 1991.
R. C. Jaeger and J. S. Goodling, "Cooling for high heat flux VLSI systems," Proceedings of the 1991 International Symposium on VLSI Technology, Systems and Applications, pp. 99-103, Taipei, Taiwan, May 22-24, 1991.
R. C. Jaeger, "Add digital display for $50," 73 Magazine, pp. 28-30, June 1979.
R. C. Jaeger, "Double duty mag-mount antenna," 73 Magazine, vol. 80-5, pp. 134, May 1980.
R. C. Jaeger, "An improved circuit for interfacing the SB-200/220 amplifiers to solid-state transceivers," Hints & Kinks, QST, pp. 48-49, May, 1989.
R. C. Jaeger, "A multiband groundplane for 80-10 meters," The ARRL Antenna Compendium, Volume 2, pp. 46-49, The American Radio Relay League, Newington, CT: 1989.

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