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In the three dimensional view of a silicon n -channel MOS transistor shown below, d = 20 nm . The transistor is of width 1 mm . The depletion width formed at every p -n junction is 10 nm. The relative permittivity of Si and SiO 2 , respectively, are 11.7 and 3.9, and e0 = 8.9 # 10-12 F/m .
The following information is given: T = 300 K electronic charge = 1.12 & 3.10 & 3.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 31 (A) increases by 60 mV (B) decreases by 60 mV (C) increases by 25 mV (D) decreases by 25 mV 2011 TWO MARKS is lower (C) Reverse breakdown voltage is lower and depletion capacitance is higher (D) Reverse breakdown voltage is higher and depletion capacitance is higher Statements for Linked Answer Question : 3.cm . a possible value for the mobility of electrons in the inversion layer of a silicon n -channel MOSFET is (A) 450 cm2 / V-s (B) 1350 cm2 / V-s (C) 1800 cm2 / V-s (D) 3600 cm2 / V-s Thin gate oxide in a CMOS process in preferably grown using (A) wet oxidation (B) dry oxidation (C) epitaxial oxidation (D) ion implantation 2010 TWO MARKS 2. respectively.1mm Depletion width on the p -side = 1.n junction at room temperature having the following parameters: Doping on the n -side = 1 # 1017 cm .13 : The channel resistance of an N-channel JFET shown in the figure below is 600 W when the full channel thickness (tch ) of 10 μm is available for conduction.i c .13 and 3. thermal voltage = 26 mV and electron mobility = 1350 cm2 / V-s 2. 3.17 Common Data For Q.08 # 10 4 A/m2 (C) 4. which of the following can have a concentration of 4 # 1019 cm .1 (D) V.3 Depletion width on the n -side = 0. S1 : The inversion charge decreases from source to drain S2 : The channel potential increases from source to drain.16 In a uniformly doped BJT.3 ? (A) Silicon atoms (B) Holes (C) Dopant atoms (D) Valence electrons The ratio of the mobility to the diffusion coefficient in a semiconductor has the units (A) V . When the gate to source voltage (VGS ) is 0 V.19 d 2009 n o.s 2009 TWO MARKS 2. the channel is depleted by 1 μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm The silicon sample with unit cross-sectional area shown below is in thermal equilibrium.48 # 102 A/cm2 ONE MARK 2. 3. NB and NC are the emitter.5 mm is (A) 2.18 The magnitude of the electric field at x = 0. ia In an n-type silicon crystal at room temperature.14 Consider a silicon p . The built-in voltage of the gate P+ N junction (Vbi ) is .V1 (C) V.5 mm is (A) 1 kV/cm (B) 5 kV/cm (C) 10 kV/cm (D) 26 kV/cm The magnitude of the electron of the electron drift current density at x = 0.co.32 # 103 A/cm2 (D) 6.1 (B) cm. Which of the following is correct? (A) Only S2 is true (B) Both S1 and S2 are false (C) Both S1 and S2 are true. base and collector doping in atoms/cm3 .22 2.20 2.no A I D 2.14 At room temperature. and S2 is a reason for S1 2.16 # 10 4 A/cm2 (B) 1.21 2.12 The channel resistance when VGS =. but S2 is not a reason for S1 (D) Both S1 and S2 are true.13 O N ww w ONE MARK . Download a sample chapter at www. which one of the following condition is TRUE (A) NE = NB = NC (B) NE >> NB and NB > NC (C) NE = NB and NB < NC (D) NE < NB < NC Compared to a p-n junction with NA = ND = 1014 /cm3 . assume that NE .3 V is (A) 360 W (B) 917 W (C) 1000 W (D) 3000 W The channel resistance when VGS = 0 V is (A) 480 W (B) 600 W (C) 750 W (D) 1000 W 2010 2.1 V . which one of the following statements is TRUE for a p-n junction with NA = ND = 1020 /cm3 ? (A) Reverse breakdown voltage is lower and depletion capacitance is lower (B) Reverse breakdown voltage is higher and depletion capacitance Consider the following two statements about the internal conditions in a n -channel MOSFET operating in the active region.15 2. If the emitter injection efficiency of the BJT is close unity.6 # 10-19 C .0mm GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination.11 : Common Data For Q.in .nodia.
2/Vp o 1 .427 eV (D) goes up by 0. If the width W is doubled (with other geometrical parameters and doping levels remaining the same).cm .80 MV .co. Now.5 # 1010 / cm 3 and the value of kT/q to be 25 mV at 300 K. Which of the following figures represents the expected dependence of gm on VG ? 2.no w oxidation rate ww (A) is independent of current oxide thickness and temperature (B) is independent of current oxide thickness but depends on tem.80 MV .31 2. the fermi level of doped silicon (A) goes down by 0.1.1.1.[1 (2 Vp )] 2. directed from n -region to p -region (C) 1. a very narrow energy barrier is required. Let Vc be .VT ) 2 where K is a constant. The. the electron concentration per cm3 at 300 K will be) (A) ni (B) ni + NA 2 (C) NA .1.28 Consider the following assertions.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 32 Intrinsic carrier concentration = 1. cm .14 F.Vp ) (D) 1 .25 Which of the following is NOT associated with a p .2/Vp (B) 1 e 2 1 . cm .31 eV (B) goes up by 0.2 V and let VP be the initial pinch -off voltage. directed from p -region to n -region (D) 1.i c .70 V (B) is 0. directed from n -region to p -region 2008 ONE MARK 2.(2 .32 perature (C) slows down as the oxide grows (D) is zero as the existing oxide prevents further oxidation The drain current of MOSFET in saturation is given by ID = K (VGS .13 eV (C) goes down by 0.VT ) 2 VGS TWO MARKS 2.VT ) (D) K (VGS .VT ) 2 VDS Id VGS . directed from p -region to n -region (B) 0.85 # 10 .427 eV The cross section of a JFET is shown in the following figure.27 A silicon wafer has 100 nm of oxide on it and is furnace at a d temperature above 1000c C for further oxidation in dry oxygen. Assume the intrinsic carrier concentration of silicon to be 1.34 The electron and hole concentrations in an intrinsic semiconductor are ni per cm3 at 300 K.VDS (B) 2K (VGS . Compared to undopped silicon. S1 : For Zener effect to occur.30 2.1/2Vp 1 . then the ratio between the mutual trans conductances of the initial and the modified JFET is 2.4 # 1010 cm .29 The measured trans conductance gm of an NMOS transistor operating in the linear region is plotted against the gate voltage VG at a constant drain voltage VD .33 O N A I D n o.15 MV .15 MV .82 V (D) Cannot be estimated from the data given The peak electric field in the device is (A) 0.24 Silicon is doped with boron to a concentration of 4 # 1017 atoms cm3 . ia (A) 4 (C) e 1 .26 2.1 Dielectric constant of silicon = 12 2. S2 : For quantum tunneling to occur. The magnitude of the transconductance gm is (A) (C) K (VGS .ni (D) ni NA + In a p n junction diode under reverse biased the magnitude of electric field is maximum at (A) the edge of the depletion region on the p -side (B) the edge of the depletion region on the n -side (C) the p+ n junction GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www.3 Thermal voltage = 26 mV Permittivity of free space = 8.76 V (C) is 0.n junction ? (A) Junction Capacitance (B) Charge Storage Capacitance (C) Depletion Capacitance (D) Channel Length Modulations Which of the following is true? (A) A silicon wafer heavily doped with boron is a p+ substrate (B) A silicon wafer lightly doped with boron is a p+ substrate (C) A silicon wafer heavily doped with arsenic is a p+ substrate (D) A silicon wafer lightly doped with arsenic is a p+ substrate 2. cm . if acceptor impurities are introduced with a concentration of NA per cm3 (where NA >> ni .1/2Vp o 1 .nodia. a very abrupt junction is required.23 The built-in potential of the junction (A) is 0. cm . Which of the following is correct ? (A) Only S2 is true (B) S1 and S2 are both true but S2 is not a reason for S1 (C) S1 and S2 and are both true but S2 is not a reason for S1 (D) Both S1 and S2 are false 2007 ONE MARK 2008 2.2.in and get maximum available discount .
the switch was connected to position 1 at t < 0 and at t = 0 .8 V.-2 (D) P . S . w (C) Recombination current (D) Induced current (A) 4 mm (B) 4.47 (B) vR =+ 5 (D) .5 (C) 0 # vR < 5 2.5 # vR < 0 2.990 (D) 0. Q .c a width a reverse bias of 1.4.3.46 TWO MARKS In the circuit shown below.2 (B) P .V characteristics plot : S1 : The MOS capacitor has as n -type substrate S2 : If positive charges are introduced in the oxide. For 0 < t # ts.2.2 (C) P . Q .40 The majority carriers in an n-type semiconductor have an average drift velocity v in a direction perpendicular to a uniform magnetic field B .1. Download a sample chapter at www. Q .2 V is 2 mm.985 (C) The forward biasing of emitter-base junction (C) 0.45 (C) 8 mm (D) 12 mm The phenomenon known as “Early Effect” in a bipolar transistor refers to a reduction of the effective base-width caused by The DC current gain (b) of a BJT is 50. Match each device in Group I with one of the option in Group II to indicate the bias condition of the device in its normal mode of operation.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 33 (D) the centre of the depletion region on the n -side 2. R .2 (D) P .3. Q . the injected minority carrier in low .13 F/cm respectively.voltage characteristics of Metal/Sio 2 /silicon (MOS) capacitor having an area of 1 # 10 .37 2. S .29.collector junction (A) 0.4.2. The electric field E induced due to Hall effect acts in the direction GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination.143 mm (B) 0. R .2 (B) P .1.1.1. Then which of the following is true? (A) Both S1 and S2 are true (B) S1 is true and S2 is false (C) S1 is false and S2 is true (D) Both S1 and S2 are false 2006 ONE MARK 2.1. Assume that the permittivities (e0 er ) of silicon and Sio2 are 1 # 10 .30 and 2. it is changed to position 2.31 : The figure shows the high-frequency capacitance . Q .2. match each device in Group I with its charactecteristic property in Group II Group-I Group-II (P) BJT (1) Population iniversion (Q) MOS capacitor (2) Pinch-off voltage (R) LASER diode (3) Early effect (S) JFET (4) Flat-band voltage (A) P . 2. 2.2.3.n junction diodes.5 # 10 .44 Under level injection assumption.2.143 mm 2007 2. Q .43 2. R .1.42 2. R . Q . Assume that the diode has zero voltage drop and a storage time ts .12 F/cm and 3. R .2.39 The gate oxide thickness in the MOS capacitor is (A) 50 nm (B) 143 nm (C) 350 nm (D) 1 m m The maximum depletion layer width in silicon is (A) 0. Group .1. S . For a reverse bias of 7.VD characteristics is negative would be (A) VD < 0 (B) 0 # VD < Vp (C) Vp # VD < Vv (D) VD $ Vv The concentration of minority carriers in an extrinsic semiconductor under equilibrium is (A) Directly proportional to doping concentration (B) Inversely proportional to the doping concentration (C) Directly proportional to the intrinsic concentration (D) Inversely proportional to the intrinsic concentration 2.2. R .980 (B) 0.2 V.2 (C) P .36 Group I lists four different semiconductor devices.4. R .9 mm ww 2.I Group-II (P) Zener Diode (1) Forward bias (Q) Solar cell (2) Reverse bias (R) LASER diode (S) Avalanche Photodiode (A) P . Q .995. the base transport factor is (B) The reverse biasing of the base .hole recombination at the base injection efficiency is 0.3.1. A p+ n junction has a built-in potential of 0.4 cm 2 . Assuming that the emitter (A) Electron .857 mm (A) vR =.4 The values of voltage (VD) across a tunnel-diode corresponding to peak and valley currents are Vp.1. S.2 Consider the following statements about the C .38 2. the i d (A) Diffusion current (B) Drift current no depletion layer width will be .V polt will shift to the left. vR is given by (all in Volts) 2. R . The depletion layer o current for an extrinsic semiconductor is essentially the . S . VD respectively. S . the C .995 (D) The early removal of stored base charge during saturation-tocut off switching O N A I D Common Data For Q.nodia.in . The range of tunneldiode voltage for VD which the slope of its I .co.41 (C) 1 mm TWO MARKS (D) 1. S .35 Group I lists four types of p . 2006 2. S .1.
1 V and the device is an active region 2004 2.7 V and the collector-to-base voltage (VCB) is 0.Schottky diode 4. The depletion capacitance of the diode per square meter is (A) 100 mF (B) 10 mF (C) 1 mF (D) 20 mF A MOS capacitor made using p type substrate is in the accumulation (A) an NOMS inverter with enhancement mode transistor as load (B) an NMOS inverter with depletion mode transistor as load (C) a CMOS inverter (D) a BJT inverter 2.in and get maximum available discount .85 # 10 . G .1.n current at 40cC for the same bias is approximately w creased. Tuned circuits H .7 eV (C) 1.co.58 n 2. H . the base-to-emitter voltage (VBE ) is 0.1. the minimum base current (IB) required to drive the transistor in the figure to saturation is 2.3.52 A Silicon PN junction at a temperature of 20c C has a reverse o.2.1 eV (D) 1.59 saturation current of 10 pico .1. er = 11. Another sample B of identical dimension is doped with 1018 atoms/cm 3 phosphorus.1.4. The ratio of electron to hole mobility is 3.2 # 108 atoms/m3 Intrinsic concentration : 1. o S1 : The b of a bipolar transistor reduces if the base width is in. Current controlled attenuator (A) E .2.12 F/m.5 # 10 4 atoms/m 3 The ratio of conductance of the n -type semiconductor to that of the intrinsic semiconductor of same material and ate same temperature is given by (A) 0. then the transistor is operating in the (A) normal active mode (B) saturation mode (C) inverse active mode (D) cutoff mode 2.1 V and the device is in saturation region (C) 1 V and the device is in saturation region (D) . The reserve saturation dia Consider the following statements S1 and S2. (C) Both S1 and S2 are FALSE (C) favorable properties of Silicon .48 (B) B # v (D) opposite to v Find the correct match between Group 1 and Group 2 Group 1 Group 2 E .2 V and b = 50 .type semiconductor has the following data: Hole-electron ratio : 0. H .51 2.57 ONE MARK The impurity commonly used for realizing the base region of a silicon n .dioxide (SiO2) (D) S1 is TRUE and S2 is FALSE (D) lower melting point 2.3.4.4 eV 2.56 For an n -channel MOSFET and its transfer curve shown in the figure.3 eV (B) 0. (B) Both S1 and S2 are TRUE (B) larger bandgap of Silicon in comparison to Germanium. 2.Ameres (pA).3 (C) E .Varactor diode 1. F . F .49 A heavily doped n . (A) 30 pA (B) 40 pA ww S2 : The b of a bipolar transistor increases if the dopoing concen(C) 50 pA (D) 60 pA tration in the base is increased. The dominant charge in the channel is due to the presence of (A) holes (B) electrons (C) positively charged icons (D) negatively charged ions 2. G .4 mode. F .GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 34 (A) v # B (C) along v 2. H .PIN diode 2.54 A Silicon sample A is doped with 1018 atoms/cm 3 of boron.4. The relative permittivity of Silicon. F .3 (B) E .p .60 Given figure is the voltage transfer characteristic of 2005 TWO MARKS O N A I D 2. High frequency switch G . the threshold voltage is 2.00005 (B) 2000 (C) 10000 (D) 20000 2005 ONE MARK (A) 1 V and the device is in active region (B) .nodia.53 2.55 GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www.i c . G . Voltage reference F .n transistor is (A) Gallium (B) Indium (C) Boron (D) Phosphorus If for a silicon npn transistor. G .7 and the permittivity of free space e0 = 8. The primary reason for the widespread use of Silicon in semiconductor Which remarks of the following is correct ? device technology is (A) S1 is FALSE and S2 is TRUE (A) abundance of Silicon on the surface of the Earth.2 V.2 (D) E .61 Assuming VCEsat = 0. H . The ratio of conductivity of the sample A to B is (A) 3 (B) 1 3 (C) 2 (D) 3 3 2 A Silicon PN junction diode under reverse bias has depletion region of width 10 m m.4 Doping concentration : 4.50 The bandgap of Silicon at room temperature is (A) 1.Zener diode 3.2.
If the drain current (ID) is 1 mA for VGS = 2 V. If the junction capacitance (Cj ) is 1 pF for Vbi + VR = 1 V. If the charge of an electron is 1.63 2. biased in the active region.nodia.2.i 2003 TWO MARKS 2. LASER 4. the current density in the silicon.5W mc. ID is (A) 2 mA (B) 3 mA (C) 9 mA (D) 4 mA The longest wavelength that can be absorbed by silicon.3 (B) P .1. the doping concentrations on the p side and n -side are NA = 9 # 1016 /cm 3 respectively.67 eV The intrinsic carrier concentration of silicon sample at 300 K is 1.4 (C) P . Coherent radiation R.12 eV.n junction is reverse biased and the total depletion width is 3 m m. the threshold voltage VT of the MOSFET will (A) remain unchanged (B) decrease (C) n change polarity (D) increase TWO MARKS In an abrupt p . S .n junction.6 # 10 . R .1. R . The threshold voltage (VT ) of the MOSFET is 1 V. Group 1 Group 2 P.4. LED 1.1 m m.4.7 m m (B) 0.77 At 300 K.25 pF (D) 0.6 # 10 .6 # 10 .886 eV (C) 0. Y: reverse (B) X: reverse.5 pF Consider the following statements Sq and S2.1. Y: forward For an n . the minority carrier density is (A) 4.00 # 1020 /m 3 (D) 3.13 m2 /V-s at 300 K. then bandgap of this material is (A) 1.36 eV (B) 1. A I D 2. Q .416 A/cm 2 (B) 0. the collector current density is (the electron charge is 1. Y: reverse (D) X: forward.5 m m.5 # 1015 /cm 3 (D) 5 # 1015 /cm 3 Consider an abrupt p .19 coulomb and the diffusion constant Dn = 35 cm 2 /s.74 An n -type silicon bar 0. Current gain (A) P . Let Vbi be the built-in potential of this junction and VR be the applied reverse bias.25 m m (D) 0.1 Ohm (D) 10 .2.19 Coulomb.channel enhancement type MOSFET.87 m m. Avalanche photo diode 2. is (A) zero (B) -112 A/cm 2 (C) +1120 A/cm 2 (D) -1120 A/cm 2 Match items in Group 1 with items in Group 2.68 2.2 (D) P . R . Q . Spontaneous emission S. Assuming negligible recombination in the base. If after doping. if no electric field is present.67 2.73 d co ia.5 /m 3 Choose proper substitutes for X and Y to make the following statement correct Tunnel diode and Avalanche photo diode are operated in X bias ad Y bias respectively (A) X: reverse.1 cm long and 100 mm2 i cross-sectional area has a majority carrier concentration of 5 # 1020 /m 2 and the carrier mobility is 0.72 2. Cj will be (A) 4 pF (B) 2 pF (C) 0. S .50 # 1011/m 3 (B) 3. the donor impurity concentration (ND) in the sample is (A) 2 # 1016 /cm 3 (B) 1 # 1016 /cm 3 (C) 2. The depletion width on the p -side is (A) 2.76 The electron concentration in a sample of uniformly doped n -type silicon at 300 K varies linearly from 1017 /cm 3 at x = 0 to 6 # 1016 / cm 3 at x = 2mm .19 2. if the source is connected at a higher potential than that of the bulk (i.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 35 Coulomb) (A) 800 A/cm 2 (C) 200 A/cm 2 2003 2.3 2.n junction.3 m m (C) 2. Q .706 eV The neutral base width of a bipolar transistor. Tunnel diode 3. for a diode current of 1 mA. Y: forward (C) X: forward.e. If electronic charge is 1.75 2. then for VGS = 3 V.70 n -type silicon is obtained by doping silicon with (A) Germanium (B) Aluminium (C) Boron (D) Phosphorus The Bandgap of silicon at 300 K is (A) 1.75 m m The resistivity of a uniformly doped n -type silicon sample is 0.69 (B) 8 A/cm 2 (D) 2 A/cm 2 ONE MARK (A) 56 m A (C) 60 mA 2004 2. The maximum electron concentration and the diffusion constant in the base are 1014 / cm 3 and Dn = 25 cm 2 / sec respectively.64 2. is 0. Which Marks of the following is correct ? (A) S1 is FALSE and S2 is TRUE (B) Both S1 and S2 are TRUE (C) Both S1 and S2 are FALSE (D) S1 is TRUE and S2 is FALSE 2. then for Vbi + VR = 4 V. S .5 # 10 . is 1. ww S1 : The threshold voltage (VT ) of MOS capacitor decreases with increase in gate oxide thickness. S .4 Ohm 2. VSB > 0 ).66 The drain of an n-channel MOSFET is shorted to the gate so that VGS = VDS .854 eV (D) 0.10 eV (C) 0. Download a sample chapter at www.71 2.3. most suitably.65 O N no w. .80 eV (D) 0. Heavy doping Q.4.2. R .19 coulomb. S2 : The threshold voltage (VT ) of a MOS capacitor decreases with increase in substrate doping concentration. a certain germanium diode GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination. the number of majority carriers is 5 # 1020 /m 3 .co.3 Q . If the longest wavelength that can be absorbed by another material is 0.62 (B) 140 mA (D) 3 mA 2.00 # 10 . The p .5 # 1016 /m 3 . Assume a situation that electrons are supplied to keep this concentration gradient constant with time.1. then the resistance of the bar is (A) 106 Ohm (B) 10 4 Ohm (C) 10 . If the electron mobility (mn) is 1250 cm 2 /V-sec and the charge of an electron is 1.333 # 10 4 /m 3 (C) 5.in . which has the bandgap of 1.
Neglecting the channel width modulation effect and assuming that the MOSFET is operating at saturation.no A I D 2. When doped with a p -type material. The value of its Cm (in pF) is approximately (VT = 26 mV) (A) (B) 30 in 15 .R .P .626 # 10 .82 In the figure.S .91 If the transistor in the figure is in saturation. then the order in which they are carried out in a standard n -well CMOS fabrication process.80 2.25 (B) 0.5 mA (D) 4. The composite FET is then characterized by the parameters g g (B) m and rd (A) m and 2rd 2 2 2 2.bde IB is greater than or equal to bdc IB is less than or equal to bdc IB 2.75 (D) 1.nodia.0 mA If P is Passivation.5 mA (B) 2. silicon diode is carrying a constant current of 1 mA. Under the conditions state above.3 pF ) has a unity-gain cutoff frequency fT of 400 MHz at a dc bias current Ic = 1 mA . respectively. VD becomes approximately equal to 2.98 eV (C) 1.85 A particular green LED emits light of wavelength 5490 Ac. Q is n -well implant.89 The electron and hole concentrations in a intrinsic semiconductor are ni and pi respectively.84 ONE MARK MOSFET can be used as a (A) current controlled capacitor (C) current controlled inductor (B) voltage controlled capacitor (D) voltage controlled inductor 2.81 The action of JFET in its equivalent circuit can best be represented as a (A) Current controlled current source (B) Current controlled voltage source (C) Voltage controlled voltage source (D) Voltage controlled current source 2002 2.87 2. whereas a certain silicon diode requires a forward bias of 0. if the plot is of (A) log I vs log V (B) log I vs V (C) I vs log V (D) I vs V A long specimen of p -type semiconductor material (A) is positively charged (B) is electrically neutral (C) has an electric field directed along its length (D) acts as a dipole Two identical FETs.83 (B) 660 mV (D) 700 mV 2.90 O N ONE MARK ww w . each characterized by the parameters gm and rd are connected in parallel. these change to n and p .2 V is (A) 0. Then (A) n + p = ni + pi (B) n + ni = p + pi (C) npi = ni p (D) np = ni pi The fT of a BJT is related to its gm. working in saturation is 900 mV. the drain current is observed to be 1 mA.17 eV (D) 0.26 eV (B) 1.R .74 eV When the gate-to-source voltage (VGs) of a MOSFET with threshold voltage of 400 mV.86 The effective channel length of MOSFET in saturation decreases with increase in (A) gate voltage (B) drain voltage (C) source voltage (D) body voltage 1999 ONE MARK 2.1435 V. then The static characteristic of an adequately forward biased p -n junction is a straight line. VD is found to be 700 mV.co.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 36 requires a forward bias of 0. If the temperature rises to 40cC.P (C) R . o (D) 96 a.Q .93 GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www. the drain current for an applied VGS of 1400 mV is (A) 0.5 (C) 0.S .P 2. When the temperature of the diode is 20cC. The energy bandgap of the semiconductor material used there is (Plank’s constant = 6.92 (A) (B) (C) (D) IC IC IC IC is always equal to bdc IB is always equal to .0 mA (C) 3.s ) (A) 2.88 An n -channel JEFT has IDSS = 2 mA and Vp =. C p and C m as follows (A) fT = Cp + Cm gm gm (C) fT = Cp + Cm 2p (C p + C m) gm gm (D) fT = 2p (C p + C m) (B) fT = (A) 740 mV (C) 680 mV 2. is (A) P . Its transconductance gm (in milliohm) for an applied gate-to-source voltage VGS of .in and get maximum available discount . R is metallization and S is source/drain diffusion.c (C) 50 1998 ONE MARK 2.34 J .Q .0 di An npn transistor (with C = 0.4 V .78 2001 2.79 The early effect in a bipolar junction transistor is caused by (A) fast turn-on (B) fast turn-off (C) large collector-base reverse bias (D) large emitter-base forward bias 1999 TWO MARKS 2.718 V.R . the closest approximation of the ratio of reverse saturation current in germanium diode to that in silicon diode is (A) 1 (B) 5 3 (C) 4 # 10 (D) 8 # 103 2.S (B) Q .Q (D) S .
5 # 1010 /cm3 1996 ONE MARK 2.94 (D) 2gm and 2rd 2.5 # 1015 /cm3. For n -type silicon doped to 2. 200 MHz (D) 201 MHz.nodia. i.in .25 # 1015 atoms/cm3 . The dose and type of the implant (assumed to be a sheet charge at the interface) required to shift the threshold voltage to .100 2.99 2.1 V 1996 TWO MARKS O N A I D 2.854 # 10-14 F/cm.0 V (D) 2.e. left floating . strong inversion occurs when (A) surface potential is equal to Fermi potential (B) surface potential is zero (C) surface potential is negative and equal to Fermi potential in magnitude (D) surface potential is positive and equal to twice the Fermi potential The intrinsic carrier density at 300 K is 1.102 (A) doubles (C) increases by about 20 mV (B) halves (D) decreases by about 20 mV q The units of are kT (A) V (C) J 1997 (B) V (D) J/K ONE MARK 2. q = 1.95 For a MOS capacitor fabricated on a p -type semiconductor.n w (C) the most positive potential available in the circuit ww (D) the most negative potential available in the circuit If a transistor is operating with both of its junctions forward biased.08 # 1012 /cm2 . but with the collector base forward bias greater than the emitter base forward bias.08 # 1012 /cm2 .4 # 1011 /cm2 . then it is operating in the (A) forward active mode (B) reverse saturation mode (C) reverse active mode (D) forward saturation mode The common-emitter short-circuit current gain b of a transistor (A) is a monotonically increasing function of the collector current IC (B) is a monotonically decreasing function of IC (C) increase with IC .1 V (B) 0 V (C) 1. the new threshold voltage should be (A) .5 # 1010 /cm3 . if the gate is changed to p+ poly-silicon. p = 1. p-type (D) 5. p = 2.103 -1 An npn transistor has a beta cut-off frequency fb of 1 MHz and common emitter short circuit low-frequency current gain bo of 200 it unity gain frequency fT and the alpha cut-off frequency fa respectively are (A) 200 MHz. the equilibrium electron and hole densities are (A) n = 1.97 The p -type substrate in a conventional pn -junction isolated integrated circuit should be connected to n o.i c (A) nowhere.4 # 1011 /cm2 . n-type (C) 5. n-type 2.0 # 1015 /cm3 (D) n = 1.25 # 1015 /cm3.co. e0 = 8. Download a sample chapter at www.9. p-type (B) 1. ia d o (B) a DC ground potential . p = 1. [er (SiO 2) = 3. for low IC . Now.5 # 1010 /cm3 (B) n = 1.25 # 1015 /cm3 (C) n = 2. if the emitter current is doubled the voltage across its base-emitter junction GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination.5 # 1010 /cm3.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 37 (C) 2gm and rd 2 2. reaches a maximum and then decreases with further increase in IC (D) is not a function of IC A n -channel silicon (Eg = 1.1 eV) MOSFET was fabricated using n + poly-silicon gate and the threshold voltage was found to be 1 V. p = 1. 200 MHz A silicon n MOSFET has a threshold voltage of 1 V and oxide thickness of Ao . 199 MHz (C) 199 MHz.1 V are (A) 1.5 # 1010 /cm3. 201 MHz (B) 200 MHz. other things remaining the same.98 2.6 # 10-19 C] The region under the gate is ion implanted for threshold voltage tailoring.0. in silicon.96 2.101 In a bipolar transistor at room temperature.
VTn) 2 L6 2 Since.1) 2 dVB = 1 & 2 (4 .V SD @ = 2 L (VGS .VTn and for N -MOS & VD = Vin . VB = 2V VTN = 1V So.Vin .5 # 10 W & 48 . Therefore. allowing electrons and holes to flow across the space charge region (Injection) when holes flow from the p region across the space charge region into the n region.36 .VTp) VSD .Vin) . VD = 5 V Therefore. So for the NMOS o So.9 # 10-12 = 10 cm = 20 # 10 # 1 # 10 # 1 # 10-9 So total no.(5 .1hdVB 2 2 dID 2 (VSG . m C 2 Since. 2 or.(5 .VD) .VTp h = VSD 2 ^5 .875 V p 0 = i = 1019 = 10 per cm3 n 0 10 2.VTp) VSD .Vin) 2 = (Vin . I1 = p OX bW l82VSD ^VSG . Given.V SD & ] 2 L Solving it we get. In a MOSFET operating in the saturation region. the channel length modulation effect causes a decrease in output resistance.(6 .7 Option (B) is correct. Option (A) is correct. Option (D) is correct.VD) .1h = 5 .5 kW & 6Vin = 11 Option (D) is correct. mn = mp COX bW l = COX bW l = COX bW l L M1 L M2 L Given that M1 is in linear region. Source body junction capacitance. In IC technology.833 V or Vin < 1. = 1 mm 2 # 1 mm Co = dWeox e0 (medium Sio 2 ) tox = 10-8 cm2 # 10-4 cm -9 -6 -12 3 3. V = Area # depth Gate source overlap capacitance.5 2.VTp h . n 0 p 0 = n i2 6 2 20 n So for M2 to be in saturation Vin < 1.1h So.1) 2 3 = 12.co.c i d VGS = Vin .6 VD = 2 volt & VG = 2 volt VS = 0 (Ground) For I1 = 0 .VTN in .V SD B 2 L m C 2 0 = p OX bW l [2VSD ^VSG .Vin) (6 .VD Vin = VD + 3 2 2.2 2.9 # 8.nodia. dry oxidation as compared to wet oxidation produces superior quality oxide with a lower growth rate Option (D) is correct. 2 So it can’t be in cutoff region.VD) 2 = (Vin . I 2 = I1 = 0 Where I1 is drain current in M1 and I2 is drain current in M2 .VTN h ww w Case 2 : M2 must be in saturation region. Case 1 : M2 is in cut off So. we obtain & 2 (5 . Vin = 5 + 3 = 4 V 2 and VDS = 2 > VGS .C. & 2 ^VSG .VD) 2 = (Vin . Volume of given device. Which is approximately equal to zero. Voltage) & 2 (VSG . So. The potential barrier of the pn junction is lowered when a forward bias voltage is applied. So.1h 1 Substituting VD = VDS = VGS .1 Option (A) is correct.0 . drift and recombination processes. of holes is.2Vin + 1 = 12.8 Option (B) is correct.0 = 4 . VGS = 2 > VTN So. I1 = I 2 Differentiating both side with respect to ID mp COX W mn COX W 1 = kN 2 ^VB .VTp h . we have Drain voltage 2.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 38 SOLUTIONS 2.1h & 2 (4 . Given the circuit as below : Cs = Aer e0 d O N A I D GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www.1) (5 .Vin . Option (A) is correct.V SD = (VGS .0 = 4 V and VGS > VTn rent is no . they become excess minority carrier holes and are subject to diffuse.1) 2 dID 2kN ^VB . drain cura.in and get maximum available discount . we assume that M2 is either in cutoff or saturation. ID = kN ^VB .Vin) (5 . the MOSFET is in the saturation region.8Vin =.VTn) 2 Hence. = 0.1 = 2 # 40 # 10-6 # ^2 .833 V For the semiconductor. VBQ = 2 volt (at D.3 2.69 # 10-15 F p = p 0 # V = 10 # 10-12 = 10-11 2. ID = kN ^VGS .4 Since all the parameters of PMOS and NMOS are equal. & Vin = 11 = 1.
Dry oxidation is used to achieve high quality oxide growth.co. Channel resistance is r L where b = a c1 rl = # W#b Pinch off voltage.(2) Option (C) is correct.3 mm = 3. qN Vj = D d2 2e qN qND or 1 = D (1 # 10-6) 2 & = 1012 2e 2e Now from equation (2).4 # 10 ) 2. Option (A) is correct.23 2.760 = 26 # 10-3 ln e 1 # 10 # 1 10 o 2 (1. Sample is in thermal equilibrium so. Thus for 10c C increase.15 A = (0.nodia. At VGS = 0 V .6 # 10-19 # 10 # 1013 4 2 # 10 A/cm n o. For every 1c C increase in temperature.(1) VGS od n .3 in n type silicon at room temperature.21 2. Thus The built-in potential is since 2b = 8 mm b = 4 mm rL a = 600 5 = 750 W rl = #4 Wa # b 2.2 mm) = 0. 2. Full channel resistance is r L r # = 600 W W#a If VGS is applied. Only dopant atoms can have concentration of 4 # 1019 cm ..in . Breakdown voltage VB \ 1 NA ND So. The peak electric field in device is directed from p to n and is from p to n E =. a large positive gate voltage is to be applied. Option (B) is correct. Therefore.2 mm + 0.16 = 7 # 10-15 F 2. NE >> NB Option (C) is correct. electric field 1 = 10 kV/cm 1 mm Option (A) is correct.68 mm2 d = 10 nm (depletion width of all junction) -12 -12 # 8.68 # 10 # 11.17 2. So. Mobility mn < 1350 cm2 /Vs for n -channel MOSFET GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia Option (B) is correct.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 39 2.1 -6 WP 1 # 10 D Vbi = VT 1nc NA N n i2 m 17 16 # 10 = 0. breakdown voltage decreases as concentration increases Depletion capacitance 1/2 ees NA ND C =' 1 2 (Vbi + VR) (NA + ND) Thus C \ NA ND Depletion capacitance increases as concentration increases 2.9 Option (C) is correct.19 Option (C) is correct.2 mm) # 1 mm + 2 (0.18 2.. In a highly doped PN junction.20 A I D 2. At room temperature mobility of electrons for Si sample is given mn = 1350 cm2 /Vs . Option (B) is correct.14 Option (A) is correct.16 ww . For an n -channel MOSFET to create an inversion layer of electrons. Option (B) is correct.9 # 10 Cs = 0.25 l rL rL a 5 = rl = # b = 600 # 3. forward bias voltage across diode decreases by 2. Drift current Id = qnmn E It depends upon Electric field E and carrier concentration n Option (B) is correct.26 = 917 W Wa W#b 2.10 2. ia = 2.26 mm b = 5 b1 . .22 Option (D) is correct. Electron drift current density E = Jd = ND mn eE = 1016 # 1350 # 1.eND xn es from n to p = eND xn es GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination. sec 2 Unit of diffusion current Dn is = cm sec 2 2 m Thus unit of n is = cm / cm = 1 = V-1 V $ sec sec V Dn 2. induced electric field increases and mobility decreases. 2 Unit of mobility mn is = cm V. there us 25 mV decreases. the conduction and valence bands on opposite sides of the junction are sufficiently close during reverse bias that electron may tunnel directly from the valence band on the p -side into the conduction band on n -side.5 mV.11 Option (D) is correct.3 V .i c .24 2.25 V At VGS =. qN Vp = D a2 2e If depletion on each side is d = 1 μm at VGS = 0 . Zener diode operates in reverse breakdown region.2 mm + 0.2 mm # 0. we have Vp = 1012 # (5 # 10-6) 2 or Vp =. Reverse bias breakdown or Zener effect occurs in highly doped PN junction through tunneling mechanism. We know that or NA WP = ND WN 17 -6 # 10 = 1 # 1016 NA = ND WN = 1 # 10 # 0. Emitter injection efficiency is given as 1 g = 1 + NB NE To achieve g = 1.12 O N . Download a sample chapter at www... Vp m w 2. Both S1 and S2 are true and S2 is a reason for S1.13 Option (C) is correct.7 9 10 # 10 Option (B) is correct.
In JFET the gate to source voltage that must be applied to achieve E2 .VT ) diffusion current. Option (B) is correct. w Therefore 2 BJT : Early effect Pinch off voltage VP = eW ND es MOS capacitor : Flat-band voltage Let VP = VP1 LASER diode : Population inversion 2 2 W V W P1 1 Now = 2= JFET : Pinch-off voltage VP2 W2 (2W) 2 2. At low voltage when there is no depletion region and capacitance is decide by SiO2 thickness only.VT ) 2 = 2K (VGS . The electric field has the maximum value at the junction of p+ n .5 # 10 . Option (D) is correct.995 b2 Option (A) is correct.37 Option (A) is correct. This effect si known as base modulation as early effect.36 O N A I D 2.32 2. Thus Zener diode : Reverse Bias Solar Cell : Forward Bias Laser Diode : Forward Bias Avalanche Photo diode : Reverse Bias 2.6 # 10 # 1 #-10 14 8.2/VP1 Current Gain = Base Transport Factor # Emitter injection Effigm1 Dividing =f p gm2 1 . A Option (C) is correct. NA = 4 # 10 In LASER population inversion occurs on the condition when ni = 1.985 51 # 0.8 + 1.(.8 + 7.nodia. Oxidation rate is zero because the existing oxide prevent the further oxidation. Silicon wafer heavily doped with boron is a p+ substrate. 1. Option (C) is correct.2) 2 = Kn =1 = Kn . C = e0 er1 A D GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www. Channel length modulation is not associated with a p .2 2 0 .in In MOS capacitor.31 Option (C) is correct.35 2.n junction.VGS E Vp From above two equation we get For first condition gm1 W = 0. a di applied to create flat ban condition in which there is no space charge o boron. Option (A) is correct.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 40 MV/cm 2. It is being associated with MOSFET in which effective channel length decreases. a non equilibrium condition. gm = 2ID = 2 K (VGS .38 Option (B) is correct.type semiconductors.e. Trivalent impurities are used for making p . w Option (C) is correct. neutral base width) > A change in neutral base width will change the collector current. i.2) b 2 gm2 = Kn =1 = K2 . producing the phenomenon called channel length modulation.1 = 50 = 50 a= VP2 G 4VP1 E b + 1 50 + 1 51 1 .8 + 1. Option (D) is correct.30 2. or 4VP1 = VP2 W = K V + VR Initial transconductance Now 2m = K 0.(. As per mass action law np = ni2 If acceptor impurities are introduces p = NA 2.85 # 10 # 12 -19 17 -5 Thus = 0.28 2.1 . reduction in base width will causes the gradient in minority carrier As VD = constant concentration to increase.25 # 1 # 10 = 1.15 2.26 2.Vbi .29 2.34 or nNA = ni2 2 n = ni NA Option (D) is correct.VT ) 2VGS 2VGS Option (C) is correct.in and get maximum available discount . So. Zener diode and Avalanche diode works in the reverse bias and laser diode works in forward bias.1 G E VP1 VP1 or W2 = 4 m m For second condition 2.E1 = kT ln NA ni pinch off voltage is described as pinch off voltage and is also called 17 as turn voltage or threshold voltage. 0 .27 2. In solar cell diode works in forward bias but photo current is in reverse direction. which in turn causes an increased in the Thus Which is straight line.co.E1 = 25 # 10-3 e ln 4 # 10 10 = 0. Option (B) is correct. the B-C space charge region width increases which xB (i.5 # 1010 concentration of electrons in one energy state is greater than that in 17 E2 .1/ (2VP1) ciency Hence VP = VP1 a = b1 # b2 2. w. gm \ (VGS . flat band voltage is the gate voltage that must be o c Hence fermi level goes down by 0.e.33 Option (A) is correct. In BJT as the B-C reverse bias voltage increases.2 gm = Kn .39 or 50 b1 = a = = 0. n region in semiconductor under oxide.427 eV lower energy state.427 eV as silicon is doped with .2 = 8 = 2 2m 0.
Hence S2 is true.51 EgT = Eg0 . a depletion region will be formed as shown in fig an total capacitance is 1 pF.4 T At T = 300 K.6 # 10 .40 Option (B) is correct.3. Diffusion current.52 2. The reverse saturation current doubles for every 10cC rise in temperature as follows : I0 (T) = I 01 # 2(T . This effect si known as base modulation as early effect.i (D) is correct.47 When applied voltage is 0 volts.co. Option (A) is correct. Eg300 = 1.53 GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination. which in turn causes an increases in the diffusion current. The varacter diode is used in tuned circuit as it can provide frequently stability. no d We have mn . Option (B) is correct.e. PIN diode is used as a current controlled attenuator. the B-C space charge region width increases which xB (i. si = ni q (mn + mp) Option (C) is correct.12 # 10 . Option (B) is correct.42 Option (C) is correct.21 eV At any temperature 2. then to equalize sn = nqmn the effect the applied voltage V must be reduced. But in storage time 0 < t < ts diode retain its resistance of forward biased. Option (B) is correct. Zener diode is used in regulated voltage supply or fixed voltage reference.4 # 300 = 1. ni2 Since ni is constant 2.4 substrate but from C-V characteristics.12 C2 7 6 # 10 = 0.V Conductance of intrinsic semiconductor plot moves to the left. C reduces if V is increased.49 Option o. For t < 0 diode forward biased and VR = 5 .v # B E = B#v 2.5 # 10 4 (1 + 0.41 E =.50 O N A I D Option (B) is correct. Thus CT = 1 pF or CT = C1 C2 = 1 pF C1 + C2 1 = 1 + 1 or CT C1 C2 Substituting values of CT and C1 we get C2 = 7 pF 6 10 . that must be remembered. A 2.46 reduction in base width will causes the gradient in minority carrier concentration to increases.1 eV This is standard value. neutral base width) > A change in neutral base width will change the collector current. sn = nqmn 2.4 cm Now D2 = e0 er2 A = 1 # 7 .nodia.45 Option (A) is correct. Thus depletion region must be formed.5 V Option (B) is correct. c Depletion region will not be formed if the MOS capacitor has n type . since the drift current is negligible for minority carrier. For n -type p is minority carrier concentration np = np = Constant p \ 1 n Thus p is inversely proportional to n .43 Option (A) is correct.857 m m 2.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia -13 -4 # 10 = 50 nm D = e0 er1 A = 3. Hence S1 is false ww Conductance of n type semiconductor w If positive charges is introduced in the oxide layer. mP ia = 0.21 . Schottkey diode has metal-semiconductor function so it has fast switching action so it is used as high frequency switch Varactor diode : Tuned circuits PIN Diode : Current controlled attenuator Zener diode : Voltage reference Schottky diode : High frequency switch mp mn h Option (C) is correct. In BJT as the B-C reverse bias voltage increases. nmn sn = n Ratio is = For the case of negative slope it is the negative resistance region s n ( m + m ) n 1 + ^ i i n p i 8 4 4 .4 = 6 # 10 .48 2. Download a sample chapter at www. For silicon at 0 K. or 2. The construction of given capacitor is shown in fig below 2. Silicon is abundant on the surface of earth in the from of SiO2 .3. According to Hall effect the direction of electric field is same as that of direction of force exerted. Eg0 = 1. Thus the C . n 2.44 Option (A) is correct.in . Thus for 0 < t < ts it will be ON and VR =. I0 = 40 pA 1 2.T )/10 Thus at 40c C.5 # 10 C 7 # 10 12 Page 41 or 2. At t = 0 diode abruptly changes to reverse biased and current across resistor must be 0. there will be no depletion region and we get C1 = 7 pF When applied voltage is V .4) 2. 2 10 # = = 2 # 10 1.6 # 10 .
87 Option (C) is correct.VT ) 2 2 IDS = (VGS2 . Option (A) is correct.6 # 10 .4 JC = qDn dn = 1. recombination of carrier in base region increases and a decreases & hence b decreases.in and get maximum available discount .60 2.8m = 56 mA b 50 2.2 = 2.7 = 10. In accumulation mode for NMOS having p -substrate.71 Option (A) is correct.416 eV 0. If doping in base region increases.VCE = 0 IC = VCC . Option (A) is correct.4 # 300 = 1. 2 (Vbi + VR)( NA + ND) E 1 Cj \ (Vbi + VR) C j2 (Vbi + VR) 1 1 =1 = = (Vbi + VR) 2 4 2 C j1 C Cj2 = j1 = 1 = 0.64 For n type semiconductor n = ND Option (D) is correct.58 2. when positive voltage is applied at the gate.1) = 4 ID1 (2 . We know that Wp NA = Wn ND 3 m # 1016 = 0.type surface beneath the gate. Hence S1 is false.1 Eg1 l2 0." b .4 T At T = 300 K.6 # 10 .67 d or n o. Here emitter base junction is forward biased and base collector junction is reversed biased. an inversion of electrons is formed and this in effect forms and n . C = e0 er A d C = e0 er = 8.1 = 2 V and VDS = 5 .62 Option (B) is correct.5 # 1250 or 2.channel. From the graph it can be easily seen that Vth = 1 V Now VGS = 3 . Option (C) is correct.19 C Dn = 25 1014 dn = dx 0. Option (C) is correct.co. When VGS is made sufficiently large.i c .GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 42 sp = pqmp sp m = p =1 sn mn 3 2.Vth Thus MOSFET is in saturation region.35 m F d A 10 # 10-6 or 2. 2.6 # 10 . Hence S2 is false.VT ) 2 Substituting the values we have 2 ID2 = (3 . Thus S1 is true and S2 is false.5 # 10 . For silicon at 0 K Eg0 = 1.0.3.1 eV This is standard value. GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www. If the base width increases.61 O N .70 2.21 eV At any temperature EgT = Eg0 .5 pF 2 2 1 2 Option (B) is correct.3 m m Wp = Wn # ND = NA 9 # 1016 Option (B) is correct. We know that eeS NA ND Cj = .66 2. Thus VT increases if we increase substrate doping concentration. We know that ID = K (VGS . Applying KVL we get or Now VCC . 2. We have Thus b = a 1-a 2.65 Option (B) is correct.VCE = 3 . Option (D) is correct.57 2.56 Option (C) is correct. Trivalent impurities are used for making p type semiconductor.68 Eg \ 1 l Eg2 = l1 = 1.no A I D 2. that must be remembered. this will induce negative charge near p .63 2.19 # 0.VT ) Thus IDI (VGS1 . Option (D) is correct. ia Option (A) is correct.3.69 Option (B) is correct.55 Thus Now or 2.19 # 25 # 2 # 1018 = 8 A/cm 2 dx Option (D) is correct. Increase in substrate doping concentration require more gate voltage because initially induce charges will get combine in substrate.5 # 10 q = 1. Conductivity s = nqun or resistivity r = 1 = 1 s nqmn Thus n = 1 qrmn 16 1 = = 10 /cm 3 1. Boron is trivalent.8 mA RC 1k IB = IC = 2.6 # 10 .21 .87 Eg2 = 1. Thus or 2. recombination of carrier in base increases and a decreases thereby decreasing b .IC RC .1 # 1. Thus VT increases if we increases gate oxide thickness. Thus transistor is operating in normal active region.1 = 4 V Since VDS > VGS $ VDS > VGS . Concentration gradient 1014 dn = = 2 # 1018 -4 dx 0.6 # 10 . Eg300 = 1.12 = 1. Option (C) is correct.nodia.59 w a -" b ww a . Pentavalent make n -type semiconductor and phosphorous is pentavalent.85 # 10-12 # 11.1) 2 ID2 = 4IDI = 4 mA 2.54 (n = p) 2. Increase in gate oxide thickness makes difficult to induce charges in channel.
1 region of this junction.77 2.2. The reverse bias We know that I = Io `e h V . We that rl R = .26 eV l (mm) 5490 # 10-4 mm 2.78 Option (C) is correct.1 or 4 10 = eV = e 2 #026 = # collector-base junction and thus increases the width of the depletion .2IDSS 1 .nodia.3 # 10-12 = 15 # 10-12 15 pF or ID2 = (1. form a parallel plate capacitor. We know that ID = K (VGS .5 mV per degree centigrade dT Here Thus Therefore.19 # 35 # (. E = 0 and we get So. The resulting reverse bias voltage between source V and body will have an effect on device function.5 # 1016 = 4.20 = 20cC 3 VD =. .2) g = m = Alternatively -4 VP b VP l (.87 Option (B) is correct.50 = 650 mV Option (D) is correct.3 # 10-12 .1j will widen the depletion region resulting the reduction in channel where h = 1 for germanium and h = 2 silicon. c 2.6 # 10 .718 At a given value of vBE . Option (D) is correct.88 Option (D) is correct.1 e hV .2 # 1020 2.62 J Eg = hc = 6.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 43 2. Jn = qDn dn dx = 1. Condition for saturation is IC < bIB Option (B) is correct.VGS m VP 2.VT ) 2 n i o.4 .84 Dsi hVT DGe T n Ge Dsi si si T -3 DGe T -3 1.9 .79 = 10-3 # 1 = 0. large current gain. cutoff condition.24 eV = = 2. At constant current the rate of change of voltage with respect to temperature is dV =. IS -34 8 increases and that iC increases proportionally.5 # 1011 = 1. -19 Eg (J) 3 . In the avalanche photo diode due to the avalanche effect there is IDS = K (VGS . increasing the reverse-bias voltage on the Io hV . This in turn results in a decrease in the Option (A) is correct. Avalanche photo diode is used in reverse bias.0 Now 16 17 =.26 eV e 1.2 # 2 # 10-3 1 .12 Option (B) is correct.T1 = 40 .83 Jn = nqme E + Dn q dn dx Since no electric field is present.3 # 10-12 + C m) = 2p # 26 # 400 C m 15. As per question length.6 # 10 .74 From above equation it is clear that the action of a JFET is voltage controlled current source.(. a i Tunnel diode has very large doping.3 # 10-12 + C m) 1 = 15. V 0.1 # 10 .626 # 10 # 10 l 54900 # 10 2.5 # 10 # 120 n 5 # 10 Option (C) is correct.85 Option (D) is correct. It is used in forward bias.4 . Download a sample chapter at www. Since IS is inversely proportional to W .13 # 100 # 10 .no LASER diode are used for coherent radiation.75 1 0. V V Io `e e .VT ) 2 Substituting the values we have 2 2 Option (A) is correct.4) 2 ID2 = 4IDI = 4 mA GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia GATE GUIDEs and CLOUDs are subjectwise books exclusive for GATE EC Examination.co. LED works on the principal of spontaneous emission.1435 Io e 26 # 10 . d In MOSFET the body (substrate) is connected to power supply in .VT ) Thus ID1 (VGS1 .4) = 4 ID1 (0.10 dx 2 # 10 .0.76 Option (D) is correct.19 # 0. We have Now or or or gm = IC = 1 26 VT gm fT = 2p (C p + C m) 1/26 400 = 2p (0. Tunnel diode shows the negative characteristics in forward bias.80 By Mass action law np = p = 2. The metal area of the gate in conjunction with the insulating dielectric oxide layer and semiconductor channel. This is early effect.well implant (B) Source drain diffusion (C) Metalization (D) Passivation Option (D) is correct.24 Eg = 1. Option (A) is correct. 3 T = T2 . dn = 6 # 10 . 62 10 # For an n -channel JEFT trans-conductance is In eV Eg (eV) = = = 2.1j = Io `e hV .0.86 Option (C) is correct.2.6 # 10-19 .VGS = .3 # 10-12 (0.1120 A/cm 2 2.2 = 20 nqmn A 5 # 10 # 1. w such a way to maintain the body (substrate) to channel junction in w w Option (C) is correct.4)G D1 T si O N A I D 2.in . r = 1 and a = nqun A s Option (B) is correct. 2. 3 # 10 = 3.VT ) 2 ID2 = (VGS2 . It is voltage controlled capacitor because in active region the current voltage relationship is given by 2. For a JFET in active region we have 2 IDS = IDSS c1 .81 2.72 ni2 ni2 16 .0.73 2.5 mho 2 2.82 From above relation we have R = = 106 W 2.5 # 20 = 50 mV VD = 700 . In n -well CMOS fabrication following are the steps : (A) n .2 # 1020) =. effective base width W .1 3 # 10 .1j 2.
94 Now if emitter current is double i.type is always electrical neutral. For a n -channel mosfet thresholds voltage is given by VTN = VGS .60) m volt = (VBE ) 1 + 15 m volt Thus if emitter current is doubled the base emitter junction voltage is increased by 15 mV. A I D 2. We have ni = 1. b also increases until we reach (IC ) saturation. For any semiconductor (Intrinsic or extrinsic) the product n p remains constant at a given temperature so here np = ni pi Option (D) is correct.0 # 105w n 2. A specimen of p . O N no w. Option (D) is correct. Option (B) is correct.e. 2.co.90 Option (C) is correct. Option (A) is correct. Thus unit of e/kT is e/eV = V-1 . 2.103 d co ia. fT = gm 2p (C p + C m) for p -channel [ p+ polysilicon used in gate] VTP = VSD (sat) . Further increases in IC (since transistor is in saturation mode know) will increases IB and b decreases.type or n . 2.ln b IE 2 lE = kT ln b 2IE 1 l IE 1 IE 1 BE BE BE 2. (So connect p to negative potential in the circuit) Option (B) is correct.VDS (sat) + VGS so threshold voltage will be same.in = 106 # (200 + 1) = 201 MHz Option (A) is correct.5 # 10 /cm Nd = 2. Option (C) is correct. The unit of q is e and unit of kT is eV. For a Forward Bias p -n junction. For normal active mode we have b = IC IB For small values of IC .1) or or I + 1 = eV/kT I0 kT log b I + 1l = V I0 /kT >> 1 So if we plot log I vs V we get a straight line. current equation I = I 0 (eV/kT .25 # 1015 atoms/cm3 For n type doping we have electron concentration n .102 2.nodia.101 2.89 Page 44 Option (D) is correct. Option (C) is correct.25 # 1015 atom/cm3 For a given temperature np = n i2 Hole concentration 2 i 10 2 10 3 2.GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia 2.5 # 10 ) w3 p =n = /cm = 1. 2. if we increases IC .25 # 1015 2. so that p n junction should be kept in reverse bias.95 2.VGS so VTP =.(VBE ) 1 = kT .97 Option (D) is correct.Nd = 2.99 Option (C) is correct.in and get maximum available discount .93 2. Unity gain frequency is given by fT = fB # b = 106 # 200 = 200 MHz a -cutoff frequency is given by f fb fa = b = = fb (b + 1) 1-a b 1b+1 2. In p n -junction isolated circuit we should have high impedance.92 or Option (B) is correct. Emitter current is given by or or Now IE = I 0 (eV /kT .100 Option (C) is correct. IE 2 = 2IE 1 (VBE ) 2 = (VBE ) 1 + (25 # 0.91 Option (B) is correct.VDS (sat) GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes) Purchase Online from our portal www. 2.98 If both junction are forward biased and collector base junction is more forward biased then IC will be flowing out wards (opposite direction to normal mode) the collector and it will be in reverse saturation mode. .96 (1.1) IE = I 0 eV /kT eV VBE = kT ln b IE l I0 (VBE ) 1 = kT ln b IE 1 l I0 (VBE ) 2 = kT ln b IE 2 l I0 (VBE ) 2 .

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