Source: https://patents.google.com/patent/US9235258B2/en
Timestamp: 2019-04-19 18:05:06+00:00

Document:
This application is continuation of U.S. patent application Ser. No. 12/706,631, filed on Feb. 16, 2010, now U.S. Pat. No. 8,707,062, issued on Apr. 22, 2014, which is a continuation of U.S. patent application Ser. No. 11/323,254, filed on Dec. 30, 2005, now U.S. Pat. No. 7,664,970, issued on Feb. 16, 2010, all of which are hereby incorporated by reference in their entirety into this application.
This application is related to U.S. application Ser. No. 10/931,565 filed Aug. 31, 2004, now U.S. Pat. No. 7,363,523, issued on Apr. 22, 2008, by inventors Kurts et al., assigned to Intel Corporation; U.S. application Ser. No. 10/934,034 filed Sep. 3, 2004, now U.S. Pat. No. 7,451,333, issued on Nov. 11, 2008, by inventors Naveh et al. assigned to Intel Corporation; U.S. application Ser. No. 11/024,538 filed Dec. 28, 2004, now abandoned, by inventors Naveh et al. assigned to Intel Corporation; U.S. application Ser. No. 10/899,674 filed Jul. 27, 2004, now U.S. Pat. No. 7,966,511, issued on Jun. 21, 2011, by inventors Naveh et al. assigned to Intel Corporation; and to concurrently filed patent application entitled “Method and System for Optimizing Latency of Dynamic Memory Sizing” by inventor Jahagirdar, assigned to Intel Corporation Ser. No. 11/323,259.
FIGS. 2A and 2B are block diagrams of an exemplary system that may be utilized to implement the zero voltage power management state approach, according to one embodiment of the present invention.
FIGS. 2A and 2B are block diagrams of an exemplary system 200 that may implement the zero voltage power management state transition approach of one or more embodiments. It should be noted that FIG. 2 is divided into 2A and 2B. The system 200 may be a notebook or laptop computer system, or may be any different type of mobile electronic system such as a mobile device, personal digital assistant, wireless telephone/handset or may even be a non-mobile system such as a desktop or enterprise computing system. Other types of electronic systems are also within the scope of various embodiments.
Also, in one embodiment, voltage from the I/O control hub 225 (V.sub.I/O 349) may be provided to the processor 205 in order to provide sufficient power to the dedicated cache memory 340 such that it can store the critical state variables associated with the processor 205 while the rest of the processor 205 is powered down by the reduction of the operating voltage 240 down to a zero state.
For other types of architectures and/or for processors that support different power management and/or normal operational states, the power management state control logic 242 may control transitions between two or more different power management and/or normal operational states using one or more signals that may be similar to or different from the signals shown in FIG. 2B.
It should be appreciated that, in one embodiment, the processor 205 of FIG. 2A may transition between various known C-states. The normal operational state or active mode for the processor 205 is the C0 state in which the processor actively processes instructions. In the C0 state, the processor 205 is in a high-frequency mode (HFM) in which the voltage/frequency setting may be provided by the maximum voltage/frequency pair.
In the system 200 of FIGS. 2A and 2B, a transition into the C4 state or into a zero voltage sleep state may be undertaken in response to ACPI software 250 detecting that there are no pending processor interrupts, for example. ACPI software may do this by causing the ICH 225 to assert one or more power management-related signals such as the exemplary Deeper Stop (DPRSTP#) signal and the exemplary DPSLP# signal. The Deeper Stop (DPRSTP#) signal is provided directly from the chipset to the processor and causes clock/power management logic 350 on the processor to initiate a low frequency mode (LFM). For the low frequency mode, the processor may transition to the minimum or another low operating frequency, for example.
More particularly, in one embodiment, in the zero voltage processor sleep state, (which may be referred to as a C6 state in accordance with ACPI standards), the critical state of the CPU 205 is saved in dedicated sleep state SRAM cache 340, which may be powered off the I/O power supply (V.sub.I/O) 349, while the core operating voltage 240 for the CPU 205 is taken down to approximately 0 Volts. At this point, the CPU 205 is almost completely powered off and consumes very little power.
It will be appreciated that the system 200 and/or other systems of various embodiments may include other components or elements not shown in FIGS. 2A and 2B and/or not all of the elements shown in FIGS. 2A and 2B may be present in systems of all embodiments.
In one example, the size of the SRAM 340 may be 8 KB per CPU core and may be 32 bits wide and may be clocked by the clock/power management logic 350. As previously discussed, the dedicated sleep state SRAM cache 340 may be powered by I/O voltage (V.sub.I/O 349) such that its contents are retained when the operating voltage for the CPU 205 is shut off.
Looking particularly at FIG. 4, an illustration of entry into the zero voltage processor sleep state is provided. As shown in FIG. 4, each core independently performs a state save when the zero voltage processor sleep state is initiated. Particularly, looking at CPU core #0 320, the first CPU core #0 is active (circle 402) and then a command for a zero voltage sleep state is initiated (e.g. via a sleep or MWAIT instruction) (circle 404). Responsive to this, the state of CPU core 320 is saved at circle 406 to dedicated cache memory 340. This includes the dedicated state 325 and the shared state 324. CPU core 320 then goes into a first sleep state 408 (e.g. CC6) in which it waits for the other core to get into the CC6 tate as well, before the whole package can transition into the overall package sleep state (e.g. C6).
the cache memory, wherein the cache memory is to be powered when the first and second processor cores are to be powered off, and the saved state of the first processor core and the saved state of the second processor core are to be restored when the first processor core and the second processor core transition to a mode in which the first processor core and the second processor core are to be powered on, respectively.
3. The processor of claim 1, wherein the first processor core is to enter the mode in which the first processor core is to be powered off in response to execution of an instruction by the first processor core.
4. The processor of claim 3, wherein the second processor core is to enter the mode in which the second processor core is to be powered off in response to execution of an instruction by the second processor core.
7. The processor of claim 1, wherein the first processor core is to transition to the mode in which the first processor core is to be powered on in response to a signal from a power management controller.
8. The processor of claim 7, wherein the second processor core is to transition to the mode in which the second processor core is to be powered on in response to a signal from the power management controller.
11. The processor of claim 1, wherein the cache memory comprises a static random access memory.
12. The processor of claim 1, further comprising a power management unit to control transition of the first processor core between a first operating point and a second operating point.
a voltage regulator coupled to the processor to provide an operational voltage to the processor, wherein the voltage regulator is adapted to reduce the operational voltage applied to the processor to approximately zero volts during a transition to a zero voltage power management state for the processor, and the dedicated cache memory is adapted to receive first state variables associated with the first core when the first core is to enter a first sleep state and second state variables associated with the second core when the second core is to enter the first sleep state, the processor to thereafter transition into a package sleep state comprising the zero voltage power management state, wherein the dedicated cache memory is coupled to a power source of a controller coupled to the processor that remains powered while the operational voltage applied to the processor is reduced to approximately zero volts.
14. The system of claim 13, wherein the dedicated cache memory comprises a synchronous random access memory (SRAM) internal to a package of the processor.
15. The system of claim 13, wherein the controller comprises an input/output controller.
restoring the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered on.
17. The non-transitory machine-readable medium of claim 16, wherein entering the mode in which the first processor core is powered off is in response to execution of an instruction by the first processor core, and wherein entering the mode in which the second processor core is powered off is in response to execution of an instruction by the second processor core.
18. The non-transitory machine-readable medium of claim 16, wherein restoring the saved state of the first processor core occurs when the first processor core is reset.
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