Source: https://studyres.com/doc/43174/?page=58
Timestamp: 2019-04-21 12:19:49+00:00

Document:
interface standards running at clock speeds of up to 50 MHz.
Fax: 781.461.3113 ©2008-2012 Analog Devices, Inc. All rights reserved.
Allow ±500 mV for external RSENSE voltage drop.
±500 mV for internal RSENSE voltage drop.
includes ±500 mV for external RSENSE voltage drop.
Uncalibrated, use c register to calibrate, measured at midscale.
Standard deviation = 23 μV/°C.
Uncalibrated, use m register to calibrate.
Standard deviation = 3 ppm/°C.
Positive and negative dc short-circuit current.
±25 mA range, positive and negative dc shortcircuit current.
EXTFORCE1 range, ±1 A load current change.
EXTFORCE2 range, ±0.5 A load current change.
(10 mΩ ESR), autocompensation mode.
Measured at 1 kHz, at output of FORCE.
gain = 20, or with VREF = 2.5 V and MI gain = 5.
Set using internal sense resistor.
RSENSE × MI gain), unless otherwise noted.
Maximum voltage across RSENSE, MI gain = 20.
Maximum voltage across RSENSE, MI gain = 10.
Measure current block alone (internal node).
At 0 A, MI gain = 20, MEASOUT gain = 1.
Standard deviation = 13 ppm/°C.
At 0 A, MI gain = 10, MEASOUT gain = 1.
At 0 A, MI gain = 20, MEASOUT gain = 0.2.
At 0 A, MI gain = 10, MEASOUT gain = 0.2.
Standard deviation = 15 ppm/°C.
Internal current ranges, all gain settings.
External current ranges, excluding RSENSE.
Standard deviation = 5 ppm/°C.
MI gain = 20 and 10.
Nominal supply (±16.5 V, 0x8000 offset DAC).
Low supply (−25 V/+8 V, 0xD4EB offset DAC).
High supply (−5 V/+28 V, 0xD1D offset DAC).
MEASOUT @ 1 kHz, inputs grounded.
MEASOUT Gain 1 and MEASOUT Gain 0.2.
Standard deviation = 2 ppm/°C.
Standard deviation = 12 µV/°C.
@ 1 kHz, at MEASOUT, inputs grounded.
PD = 1, SW-INH = 0 (power up and tristate).
TJ = 25°C to 70°C.
SYS_SENSE high-Z, force amplifier inhibited.
AVDD = 16.5 V, AVSS = −16.5 V.
SYS_FORCE high-Z, force amplifier inhibited.
1 V separation from AGND/0 A.
Time for CLALM to flag.
Fastest slew rate, controlled via serial interface.
Slowest slew rate, controlled via serial interface.
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load.
1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load.
3 V step, CDUT = 2.2 µF, full dc load.
8 V step, CDUT = 2.2 µF, full dc load.
3 V step, CDUT = 10 µF, full dc load.
8 V step, CDUT = 10 µF, full dc load.
3 V step, CDUT = 20 µF, full dc load.
8 V step, CDUT = 20 µF, full dc load.
Of programmed value (≥1 V).
To within 10 mV of programmed value.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
10 mV of final value.
To within 100 mV of programmed value.
3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load.
lower ranges (except EXTFORCE1 to EXTFORCE2).
CDUT = 100 μF, changing between all ranges.
1 V change to 1 LSB.
Per input; typically ±30 nA.
With respect to the measured voltage.
Of programmed current range, uncalibrated.
MEASOUT gain = 1, VREF = 2.5 V.
MEASOUT gain = 0.2, VREF = 2.5 V.
If it moves 100 mV away from input level.
Relative to a temperature change.
SDO, CPOL, CPOH, GPO, CPO.
IOL = 500 µA, CL = 50 pF, RPULLUP = 1 kΩ.
|AVDD – AVSS| < 33 V.
here are consumed by the load.
When enabled, excluding load conditions.
When enabled, excluding load condition.
Guaranteed by design and characterization, not subject to production test.
Programmable clamps must be enabled if taking advantage of reduced headroom/footroom.
Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins.
−30 dB at 100 kHz.
−25 dB at 100 kHz.
−60 dB at 100 kHz.
−62 dB at 100 kHz.
−20 dB at 100 kHz.
−65 dB at 100 kHz.
−46 dB at 100 kHz.
−36 dB at 100 kHz.
maximum specifications, unless otherwise noted).
Guaranteed by design and characterization, not production tested.
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
See Figure 4 and Figure 5.
This is measured with the load circuit shown in Figure 2.
This is measured with the load circuit shown in Figure 3.
Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2.
shorted to AVSS voltage at any time because this can cause damage to the device.
1. NC = NO CONNECT.
Comparator High Output (CPOH) or Window Comparator Output (CPO).
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
Clock Input, Active Falling Edge.
this input to drive the ramp circuitry. Tie RCLK low if it is unused.
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
LOAD input (see the system control register, Address 0x1).
Accurate Ground Reference for Applied Voltage Reference.
Reference Input for DAC Channels, Input Range 2 V to 5 V.
Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
Slave Input When Ganging Multiple DPS Devices.
Master Output When Ganging Multiple DPS Devices.
Output Force Pin for Internal Current Ranges.
Low Side Measure Current Line for External High Current Ranges.
Input High Measure Line for External High Current Range 1.
Input High Measure Line for External High Current Range 2.
High Current Positive Analog Supply Voltage, for EXTFORCE1 Range.
Output Force. This pin is used for high Current Range 1, up to a maximum of ±1.2 A.
High Current Negative Analog Supply Voltage, for EXTFORCE1 Range.
High Current Negative Analog Supply Voltage, for EXTFORCE2 Range.
Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA.
High Current Positive Analog Supply Voltage, for EXTFORCE2 Range.
Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT.
The exposed pad is internally connected to AVSS.
Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A.
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE2 Range.
to this input to drive the ramp circuitry. Tie RCLK low if it is unused.
Reference Input for DAC Channels, Input Range is 2 V to 5 V.
the ideal voltage at full scale.
the ideal voltage at zero scale.
for offset error and gain error and is expressed in millivolts (mV).
full-scale voltage range per volt (%FSVR/V).
fully and limit the clamped voltage or current.
expressed in volts per microsecond (V/μs).
DNL of ±1 LSB maximum ensures monotonicity.
modulation is the ACPSRR. It is expressed in decibels (dB).
the circuit connected to that pin is in high impedance state.
required to operate the device are available on chip.
current or voltage is available on the MEASOUT pin.
across the selected sense resistor with full-scale current flowing.
[V(FIN DAC) − threshold − VBE].
decoupling when making low current measurements.
maintain a force/sense connection when a DUT is not in place.
when in high current ranges.
SW-INH bit in the DPS Register 1, Address 0x2).
DUTGND is the ground level of the DUT.
AD5560 devices for currents in excess of ±1.2 A.
when driving DUT capacitances of up to 160 μF.
or HW_INH can be chosen as a LOAD function.
the necessary reference voltage to generate the required dc levels.
amplifier becoming disconnected from each other.
Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs.
when making low current measurements.
(Address 0x7) details the addressing and location of the diodes.
temperature at different points across the die.
up the charging time of the load capacitance. CLEN is active high.
chosen as a LOAD function.
window set by the CPL and CPH DAC levels (see Table 24).
protection per stage as noted in the Specifications section.
condition (for all current ranges).
minimize errors from cable insulation leakage.
away from the 0 A level.
read back via the SPI interface.
programmed clamp limit + 10% of full-scale current.
open-drain KELALM pin when the guard output is shorted.
The delay in the alarm flag is 200 μs.
DPS Register 2, Table 19).
to 160 μF using one of the modes previously listed.
inputs of each slave force amplifier (via the SLAVE_IN pin ).
specified current ranges with large or small voltage swings.
across RSENSE is ±0.64 V (gain of 20) or ±0.7 V (gain of 10).
is ±500 mV when full-scale current is flowing through it.
ranges. Selection of CCx should be at ≤5% tolerance.
whereby multiple devices are ganged together for higher currents.
discussed in the following two sections.
EXTFORCE1 path results in a 3.5 V/4.8 A DPS.
removing devices should be the reverse of Step 1 through Step 5.
ensure that the slave devices are in high-Z mode while configuring them into the required range and gang setting.
can be brought back into the gang if needed.
Choose the master device and force 0 V output, corresponding to zero current.
high-Z mode via SW-INH or HW_INH until ready to gang).
Select to gang in either current or voltage mode.
devices copy either voltage or current as programmed.
the DPS Register 2 in Table 19 for addressing details.
There are three types of temperature sensors in the AD5560.
4.7 mV/°C. This sensor is active during power-down mode.
25°C and output scaling factor.
stage that it senses is determined by the active stage.
voltage levels (see Table 23) also available on MEASOUT.
This set of sensors is not active in power-down mode.
x, y are (high, NPN) and (low, PNP).
diagnostic register section in Table 23.
to reenable the force amplifier.
See also the Thermal Considerations section.
with an ADC with a smaller input range.
the output range on MEASOUT scales accordingly.
The MEASOUT line can be tristated via the serial interface.
headroom and footroom for the required force voltage range.
amplifier block to center the current ranges at about 0 A.
DAC setting (see Table 15 and Figure 56).
AVDD/AVSS Power Supply Rails section for more information.
VREF = 5 V, unless otherwise noted.
The offset DAC setting has no effect on the output voltage range.
Subset of the possible ADCs, ADC drivers, and multiplexers suitable for use with the AD5560. Visit http://www.analog.com for more options.
Do not allow the MEASOUT output range to exceed the AIN range of the ADC.
1. att: ATTENUATION FOR EXTERNAL MEASOUT × 0.20 FOR OUTPUT VOLTAGE RANGE 0V TO 5.125V (WITH OVERRANGE) (VREF = 5V).
mode, autocompensation mode, and manual compensation mode.
is for an optimum tradeoff between ac response and stability.
Table 12 and Table 13.
Figure 57 shows more details of the force amplifier block.
is a conservative 90° of phase margin.
various load conditions that a DPS is presented with.
whole circuit (particularly the measure current).
from 0 pF to 160 μF, all four CCx capacitors are required.
how many capacitors are missing.
CC0 is switched on at all times. CC3, CC2, and CC1 can be connected in addition to CC0 to slow down the force amplifier loop.
low current ranges but not so for the highest current ranges.
ranges but are of lesser benefit in higher current ranges.
is a pole at 1/( RSENSE × [CFx + CR]) and a zero at 1/[ RSENSE × CFx].
this should be added to the 1 Ω to calculate the pole frequency.
a current (RSENSE × CFx).
are both a large CR and large RC.
instead allow the zero to be 2× to 3× the frequency of the pole.
this complexity by using a high quality capacitor with low ESR.
10× larger before making a large DAC step.
ESR of that load capacitance) as inputs.
guide. However, do not underestimate this ESR).
a. CC0 is the suggested 100 pF.
corresponding CFx pin to one that is.
capacitor that is smaller than CR.
current range using RS = 0.5 V/IRANGE.
selected CFx capacitor is large compared to 2.2 μF.
where RC takes its value from the assumptions in Step 2.
of 6 × FP on a logarithmic scale.
frequency of 2 × FZ.
to this ideal frequency of 2 × FZ on a logarithmic scale.
impedance at that particular frequency.
resistor-string architecture guarantees DAC monotonicity.
off before being fed to the output amplifier.
to enable offset and gain errors to be calibrated out.
it is likely that the autocompensation algorithm is nonoptimal.
capacitor does not exist normally is a safer simplifying assumption.
fed to the output amplifier.
enable offset and gain errors to be calibrated out.
RSENSE is the sense resistor.
MI_AMP_GAIN is the gain of the MI amp (either 10 or 20).
The offset DAC does not affect the OSD DAC output range.
AGND lines before the alarm circuit flags an error.
function for this 16-bit DAC is shown in Equation 1.
DAC code shown for 16-bit force DAC.
registers that allow the user to digitally trim offset and gain.
internal m and c registers, which hold the correction factors.
x2 is the data-word loaded to the resistor string DAC.
x1 is the 16-bit data-word written to the DAC input register.
m is the code in the gain register (default code = 216 – 1).
n is the DAC resolution (n = 16).
c is the code in the offset register (default code = 215).
voltage range: x1, m, and c.
the m (gain) and c (offset) registers.
because the output amplifiers are limited by available footroom.
the device (clamp, comparator, and force DACs).
and gain registers are 16 bit.
and comparator inputs and the current ranges.
Using a 5 V reference and setting the m (gain) register to onefourth scale or 0x4000 gives an output voltage span of 6.25 V.
achieve 16-bit resolution in this 6.25 V range.
The measure current amplifier has two gain settings, 10 and 20.
minimum voltage level, as well as headroom/footroom.
VDUTGND is the voltage range anticipated at DUTGND.
RCABLE is the cable/path resistance.
ILOAD is the maximum load current.
and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V.
with sufficient current to slew.
drop should also be factored into the supply rail calculation.
stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W.
specified for performance up to 90°C junction temperature (TJ).
tin finish. The exposed paddle is connected internally to AVSS.
quoted maximum force may cause permanent lead bending.
method is using the ramp feature and an external clock.
0.4375 V/µs, 0.35V µs, and 0.313 V/µs.
user supplies a clock, RCLK, to control the timing.
for a step of 10 mV with CDUT in the lowest range of <0.2 µF.
here; therefore, there is a calibration delay of 1.2 µs.
For slower ramp rates, an even slower RCLK can be used.
833 kHz clock using a 2032 LSB step size and divider = 1).
833 kHz clock using a 16 LSB step size and divider = 255).
It reaches the end code.
An interrupt ramp is received from the user.
the user to service the activated alarm.
be written to the device while ramping because they are ignored.
to, that is, on the falling edge of SYNC.
is all registers except the DAC registers.
to SCLK. The first falling edge of SYNC starts the write cycle.
in 24 bits of data before SYNC is taken high again.
The SDO output in the AD5560 is a weak/slow output driver.
time while the calculations are completed.
DAC outputs update immediately after BUSY goes high.
low level is detected on the RESET pin.
control register, Address 0x1, Bits[8:7]).
of these pins is a CLEN or HW_INH function).
ignored until it goes low again.
the CLEN and HW_INH pins in their normal function.
can still be synchronized by simply tying BUSY pins together).
some read-only registers (Address 0x43 and Address 0x44).
DAC x2 registers are not available for readback.
NOP command; performs no operation.
bits. This allows for use of asymmetrical supplies or for use of a smaller input range ADC.
MEASOUT scales accordingly (see Table 9).
0, the input of the force amplifier is connected to the output of the force DAC.
the user to bring only one line back to the controller per DPS device.
powers this block down (default).
the active LOAD pin is brought low (or in the case of LOAD 3, until BUSY goes high).
Default operation, CLEN and HW_INH function normally.
The CLEN pin is a LOAD input.
The HW_INH pin is a LOAD input.
goes high. No LOAD hardware pin. CLEN and HW_INH function normally.
Current range addressing. These bits allow selection of the required current range.
comparing DUT current or voltage; by default, the comparators are high-Z on power-on.
reduced. For details on diagnostic functions, see Address 0x7, the diagnostic register.
Connect MEASOUT to DUTGND SENSE.
Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7).
Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7).
Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp.
the decoupling capacitor to help speed up low current testing.
apparent when in high current ranges.
SYS_DUTGND pin in the SYS_DUTGND function.
bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions.
optimize the compensation used. Do not overestimate CDUT because this can cause oscillations.
Underestimating CDUT gives suboptimal but stable performance.
optimize the compensation used. Do not underestimate ESR because this can cause oscillations.
Overestimating ESR gives suboptimal but stable performance.
extremely slow response. The default operation on power-on or reset is SAFEMODE.
SAFEMODE settings are always gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set this bit high to enable autocompensation.
settings are gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set the value of RZ to add a zero at the following frequencies. This calculation assumes that CC0 = 100 pF.
creating a pole at one of the following frequencies.
voltage loop is equal to gmx/CC0. The following values assume CC0 = 100 pF.
These bits determine which feedforward capacitor CFx is switched in.
This item corresponds to a SAFEMODE setting (SAFEMODE is the power-on default setting).
leave low for an unlatched alarm pin (default).
Set this bit high to disable the open-drain TMPALM alarm pin; leave low to leave enabled (default).
pin; leave low for an unlatched alarm pin (default).
to have all or selected information flagged to the alarm pin.
Set this bit high to disable the DUTALM alarm function flagging the open-drain KELALM pin.
output; leave low for an unlatched alarm pin (default).
Set this bit high to disable the open drain CLALM alarm pin; leave low to leave enabled (default).
all or any information flagged to the KELALM alarm pin.
addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT.
VMID code is the midscale voltage of the DACs; the offset DAC has a direct effect on this voltage level.
VMIN code is the zero-scale voltage of the DACs; again the offset DAC has a direct effect.
diode is available on the GPO pin; the D− is on the AGND.
the force amplifier PNP devices (output devices for sinking current).
each parallel stage. The enabled stage depends also on which current range is selected.
x1 DAC register; D15 to D0, MSB first.
m register; D15 to D0, MSB first.
c register; D15 to D0, MSB first.
D15 to D0; the low clamp level can only be negative; the MSB is always 0 to ensure this.
D15 to D0; the high clamp level can only be positive; the MSB is always 1 to ensure this.
D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range.
0000 0000 D6 to D0.
16 LSB = 6.1 mV.
111 1111 = 2032 LSBs (775 mV) step.
0000 0000 D7 to D0.
D7:D0 set the RCLK divider.
Latched clamp alarm; if low, indicates that an alarm event has occurred.
Unlatched clamp alarm; if low, indicates that an alarm event is still present.
LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred.
Unlatched guard alarm; if low, indicates that an alarm event is still present.
Comparator output low condition as per the comparator output pin.
Comparator output high condition as per the comparator output pin.
the comparator outputs. Reading this register also automatically clears any latched alarm pins or bits.
available on the SDO pin during the next SPI operation.
status and the comparator output result.
and clear alarm register (see Table 25)).
function in the power-on event.
full scale and to c at zero scale.
X = don’t care; the switch is unaffected by the particular bit condition.
Power-down mode; used for low power consumption.
Force amplifier outputs tristate, low leakage mode; feedback made around amplifier.
Master: MASTER_OUT = internally connects to active EXTFORCE1/EXTFORCE2/25 mA output.
Master: MASTER_OUT = master MI.
Slave FV: EXTFORCE1/EXTFORCE2/25 mA connected internally to close the FVAMP loop.
internal pull-up resistors between the supplies (see Figure 59).
should take into account the current carrying requirements.
allow for this extra voltage drop.
internal sense resistors up to 25 mA maximum).
the AD5560 device for the EXTFORCE1 range (up to ±1.2 A).
by ensuring that the supplies are at the lowest voltages.
ground plane before the positive or negative supplies are applied.
as the HCAVDDx and HCAVSSx supplies, as indicated in Table 3.
indicated by the absolute maximum ratings (see Table 3).
to different power rails as required by the set voltage range.
the forced voltage, irrespective of the current range being used.
Subset of the possible references suitable for use with the AD5560. See www.analog.com/references for more options.
point should be established as close as possible to the device.
connected to the negative supply AVSS.
All numbers are simulated and assume a JEDEC 4-layer test board.
θJA is the thermal resistance from hottest junction to ambient air.
θJC (Uniform) is the thermal resistance from junction to the package top, assuming total power is uniformly distributed.
θJCP is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM).
Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.5 mm thick, with thermal conductivity of 2.56 W/m/k.
Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.4 mm thick, with thermal conductivity of 3.57 W/m/k.
dependent on where the case temperature is measured.
for the flip chip BGA.

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