Source: https://patents.google.com/patent/US8185734B2/en
Timestamp: 2019-04-21 02:52:33+00:00

Document:
This application is a continuation of, and claims the priority of, application Ser. No. 11/096,618, filed Mar. 31, 2005, entitled “System and Method for Execution of a Secured Environment Initialization Instruction,” which is a continuation of, and claims the priority of, application Ser. No. 10/112,169, filed on 29 Mar. 2002, entitled “SYSTEM AND METHOD FOR EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION,” which issued on Jun. 27, 2006 as U.S. Pat. No. 7,069,442.
Chipset 240 may support standard I/O operations on I/O busses such as peripheral component interconnect (PCI), accelerated graphics port (AGP), universal serial bus (USB), low pin count (LPC) bus, or any other kind of I/O bus (not shown). An interface 290 may be used to connect chipset 240 with token 276, containing one or more platform configuration registers (PCR) 278, 279. In one embodiment, interface 290 may be the LPC bus (Low Pin Count (LPC) Interface Specification, Intel Corporation, rev. 1.0, 29 Dec. 1997) modified with the addition of certain security enhancements. One example of such a security enhancement would be a locality confirming message, utilizing a previously-reserved message header and address information targeting a platform configuration register (PCR) 278 within token 276. In one embodiment, token 276 may contain special security features, and in one embodiment may include the trusted platform module (TPM) 281 disclosed in the Trusted Computing Platform Alliance (TCPA) Main Specification, version 1.1a, 1 Dec. 2001, issued by the TCPA (available at the time of filing of the present application at wwwDOTtrustedpcDOTcom).
begin execution of the secure initialization software in the secure memory.
2. The processor of claim 1, wherein the logic is to copy the secure initialization software into the secure memory for validation.
3. The processor of claim 1, wherein the logic is to begin execution of the secure initialization software by transferring control to the secure initialization software.
4. The processor of claim 1, wherein the logic is also to provide a location at which the other processor is to begin execution in the secure environment.
executing, by the first processor, the secure initialization software in the secure memory in response to the secure environment initialization instruction.
6. The method of claim 5, further comprising validating the secure initialization software in the secure memory in response to the secure environment initialization instruction.
7. The method of claim 6, wherein validating the secure initialization software in the secure memory in response to the secure environment initialization instruction includes using a digital signature of the secure initialization software.
8. The method of claim 7, wherein the digital signature of the secure initialization software is produced by a hash of the secure initialization software.
9. The method of claim 8, wherein the digital signature of the secure initialization software is produced by a hash of the secure initialization software.
10. The method of claim 5, further comprising executing, after execution of the secure initialization software, a secure virtual machine monitor.
11. The method of claim 5, further comprising providing a location at which the second processor is to begin execution in the secure environment.
wherein the first processor is also to confirm that the second processor has entered a wait state before copying the secure initialization software into the secure memory.
13. The system of claim 12, further comprising a secure virtual machine monitor to be executed after execution of the secure initialization software.
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