Source: https://www.ee.iitb.ac.in/wiki/faculty/udayan
Timestamp: 2019-04-23 20:58:51+00:00

Document:
Intel Ph.D. Fellowship awarded to Sandip Lashkare for the proposal titled “Spiking Neural Network Architecture Hardware Design with Nanoscale Synapse for Supervised and Unsupervised Learning” in 2018.
A. Shukla, U. Ganguly, " An On-chip Trainable and Clock-less Spiking Neural Network with 1R Memristive Synapses,” IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) 2018 link.
V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “Punch-through Diode based Bipolar RRAM Selector by Si Epitaxy”, IEEE Electron Devices Letters, v. 33 , pp. 1396, 2012 link.
U. Ganguly, T. Guarini, D. Wellekens, L. Date, Y. Cho, A. Rothschild, J. Swenberg, “Impact of Top-Surface Tunnel Oxide Nitridation on Flash Memory Performance and Reliability,” IEEE Electron Device Letters , v.31, pp.123-125, 2010 link.
C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Study of Endurance Induced Degradation Mechanism in SANOS Memories under NAND (FN/FN) Operation’, IEEE Transactions on Electron Devices link.
C. Sandhya, A. B. Oak, A.S. Joshi, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Impact of SiN Composition Variation on SANOS Memory Performance and Reliability under NAND (FN/FN) Operation’, IEEE Transactions on Electron Devices. v. 56, pp. 3123-3132, 2009.
C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation” IEEE Electron Device Letters v.30, No.2 pp. 171-173, 2009.
U. Ganguly, T.-H. Hou, E. C. Kan, ‘Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal based Nanotube/Nanowire Memories’, IEEE Trans. Nanotechnology, 6, 22, 2007.
T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Fermi-Level Pinning in Nanocrystal Memories’, IEEE Electron Device Letters, 28, 103, 2007.
T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Programmable Molecular Orbital States of C60 from Integrated Circuits,’ Applied Physics Letters, 89, 253113, 2006.
U. Ganguly, V. Narayanan, C. Lee, T.-H. Hou, E. C. Kan, ‘Three dimensional analytical modeling of nanocrystal memory electrostatics’, Journal of Applied Physics, 99, 114516 2006.
T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3103, 2006.
T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3095, 2006.
U. Ganguly, E.C. Kan, Y. Zhang, ‘Carbon nanotube FET memory with charge storage in metal nanocrystal’, Applied Physics Letters, 87, 043108 (2005).
C. Lee, U. Ganguly, V. Narayanan, T.-H Hou, and E. C. Kan, ‘Asymmetric Electric Field Enhancement in Nanocrystal Memories’, IEEE Electron Device Letters, 26, 879, 2005.
J. Guo, E. C. Kan, U. Ganguly, Y. Zhang, ‘High Sensitivity and Non-Linearity of Carbon-Nanotube-Based Charge Sensors’, Journal of Applied Physics, 99, 084301 2006.
U. Ganguly, J. P. Krusius, “Fabrication of Ultra-Planar Aluminum Mirror Array by Novel Encapsulation CMP for Micro-optics and MEMS applications” Journal of Electrochemical Society, 151, H232, 2004.
U. Ganguly, J. P. Krusius, “Novel compensation CMP for low dishing and high global planarity for ultra-planar die applications in micro-optics and MEMS”, Thin Solid Films, 460,306, 2004.
Piyush Bhatt, Amit Kumar Singh, Monika Gupta, B.Umapathi, HS Jatana and U.Ganguly “Technology development of CMOS compatible high gain BJT to enable 180nm BiCMOS technology” International Workshop on The Physics of Semiconductor Devices (IWPSD 2017).
P. Kumbhare, S. Chouhan, U. Ganguly, “PrMnO3-Based Scaled (<300 nm) Nonlinear RRAM Device for Selector-less Array Application”, International Workshop on the Physics of Semiconductor Devices (IWPSD) 2017.
S. Sadana, A. Singh, D. Sehgal, B. Umapathi, H.S. Jatana, U. Ganguly “One Time Programmable (OTP) Memory based on MIM dielectric breakdown for 180nm CMOS” International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017.
B. Das, J. Schulze, U. Ganguly, “Effect of Delta-p Doping and i-region Length Scaling on Ion/Ioff in Si NIPIN Diode for Selector Application”, International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017.
S. Prasad, A. Biswas, A. Shukla, U Ganguly, “A Highly Efficient Performance and Robustness Evaluation Method for a SNN based Recognition Algorithm” International Conference on Artificial Neural Networks (ICANN) 2017 (accepted).
A. Biswas, S. Prasad, A. Shukla, U Ganguly, “SNN Model for Highly Energy and Area Efficient On-Chip Classification” International Conference on Artificial Neural Networks (ICANN) 2017 (accepted).
R. Mandapati, A. Borkar, S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, and U.Ganguly, “On Pairing Bipolar RRAM memory element with novel punchthrough diode based selector: Compact modeling to array performance” 5th IEEE International Nanoelectronics Conference, IEEE INEC 2013 link.
R. Nori, N. R. C. Raju, N. Thomas, N. Panwar, P. Kumbhare, G. Rao, V. S. S. Srinivasan, N. Venkataramani, U. Ganguly, “Conducting Oxide Electrode to Mitigate Mechanical Instability (Bubble Formation) during Operation of La1-xSrxMnO3 (LSMO) Based RRAM” MRS Fall A12.40, Boston, 2012 link.
S. Chopra, P. Bafna, P. Karkare, S. Srinivasan, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly, “A Two Terminal Vertical Selector Device for Bipolar RRAM”, Pacific Rim Meeting on Electrochemical and Solid State Science (PRiME), Honolulu, Hawaii, USA, October 7-12 2012 link.
P. Paramahans, P. Ray, S. Mane, P. Nyaupane, U. Ganguly, S. Lodha, “Ohmic contacts to n-type Germanium using a thin ZnO interfacial layer” in MRS Spring Meeting, San Francisco 2012.
U. Ganguly, Y. Yokota, J. Tang, S. Sun, M. Rogers, M. Jin , K. Thadani, H. Hamana, G. Leung, B. Chandrasekaran, S. Thirupapuliyur, C. Olsen, V. Nguyen, S. Srinivasan, “Scalability Enhancement of FG NAND by FG Shape Modification” International Memory Workshop, Seoul 2010.
A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, ‘Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation’, International Electron Devices Meeting (IEDM) 2007.
U. Ganguly, T.-H. Hou and E. C. Kan, ‘Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2006.
U. Ganguly, T.-H. Hou and E. C. Kan, ‘Quantum Transport and Trap Effects in Tunneling Rate Measurements of Metal Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.
U. Ganguly, C. Lee and E. C. Kan, ‘Retention characteristics for nonvolatile memory based on metal nanocrystals and carbon nanotube FET with CVD SiO2 and ALD HfO2 tunneling dielectrics’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.
C. Lee, U. Ganguly and E. C. Kan, ‘Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array Beyond 90nm CMOS Technology’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004.
U. Ganguly, C. Lee and E. C. Kan, ‘Interface and oxide contamination monitoring in integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks’, (MRS) Material Research Symposium, Boston, MA, Dec. 2003.
U. Ganguly, S. Deshmukh, B. Rajendran, “An ambipolar two terminal selection device” 2134/MUM/2013.
S. Lodha, U. Ganguly, V. Pavan Kishore, “Method of forming low resistance metal contacts simultaneously on n and p-type semiconductors”, 532/MUM/2013.
Invited talk “Non-volatile memory Engineering- Capabilities and Future Directions at IIT Bombay”, India Research Network Meeting, Organized by Samsung India Software Operations, Bangalore, May 2012.
Abhishek Khanna (2016) - continued as research staff for a year, the joined Ph. D. program at U. Notre Dame.
Shankar Prasad (2017) - Digital IC Design Engineer at Marvell Semiconductors.
• Simulation of number and position fluctations metal nanocrystal impact on memory scalability.
Udayan Ganguly received the B.Tech. degree in Metallurgical Engineering from the IIT Madras, in 2000 and the M.S. and Ph.D. degrees in Materials Science and Engineering at Cornell University, Ithaca, NY, in 2005 and 2006 respectively. In 2006, Udayan joined Applied Materials to serve as the technical lead for Flash Memory Applications Development at Applied Materials’ Front End Product Division, Sunnyvale, CA. He has joined Dept. of Electrical Engineering in 2010. He has authored/ co-authored 45+ journal, 75+ conference and 25+ patents (applied/granted). His research interests are in semiconductor device physics and processing technologies for advanced memory, computing, and neuromorphic systems. He likes to experiment with teaching/learning methods like "Think-Pair-Share". He has contributed to the TIFAC National Vision for ICT 2035. He works to augment national semiconductor manufacturing capability at Semi-Conductor Labs, Chandigarh, for which he has won the Dr. PK Patwardhan Technology Development Award 2018.
Professional maintenance and tracking in a critical need for Indian Govt. institutions. We have established an online campus maintenance tracking system that was initiated in 2012 at the lab level, demonstrated at various levels including institute wide AC maintenance till 2015 in a voluntary mode. This shows the commitment of campus service groups to improve services. From 2015 it is now officially constituted / recognized as part of the IITB administration.
I presently have an opening for Sr. Circuit Design & Test Engineer (Analog Digital).
I request interested M.Tech and Ph.D. students to contact me after they have secured admission at IIT Bombay.
I presently do not need project staff.
I accept interns through two standard processes only given below.
A related talk by Prof. Sridhar Iyer ET @ IITB on Why should IIT give you a Ph.D.?
DD MTP Evaluation procedure based on the above guidelines is present.
Department of Electrical Engineering: Vision The first vision document for the Department of Electrical Engineering, IIT Bombay - where I was proud to serve as the Committee Chair.
Here is the EE Department Video which I had the previlege of developing with Kumar Appaiah, Himanshu Bahirat, and Sudesh Balan’s Team - in addition to persons on the video Anupama Kowli, Debasattam Pal, Rajesh Zele, Sharayu Moharir and Saurabh Lodha.

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