Source: https://www.nature.com/articles/s41586-018-0129-8?error=cookies_not_supported&code=90ee3213-5f39-4143-a33a-60f94365e102
Timestamp: 2019-04-19 05:11:10+00:00

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The junctions formed at the contact between metallic electrodes and semiconductor materials are crucial components of electronic and optoelectronic devices1. Metal–semiconductor junctions are characterized by an energy barrier known as the Schottky barrier, whose height can, in the ideal case, be predicted by the Schottky–Mott rule2,3,4 on the basis of the relative alignment of energy levels. Such ideal physics has rarely been experimentally realized, however, because of the inevitable chemical disorder and Fermi-level pinning at typical metal–semiconductor interfaces2,5,6,7,8,9,10,11,12. Here we report the creation of van der Waals metal–semiconductor junctions in which atomically flat metal thin films are laminated onto two-dimensional semiconductors without direct chemical bonding, creating an interface that is essentially free from chemical disorder and Fermi-level pinning. The Schottky barrier height, which approaches the Schottky–Mott limit, is dictated by the work function of the metal and is thus highly tunable. By transferring metal films (silver or platinum) with a work function that matches the conduction band or valence band edges of molybdenum sulfide, we achieve transistors with a two-terminal electron mobility at room temperature of 260 centimetres squared per volt per second and a hole mobility of 175 centimetres squared per volt per second. Furthermore, by using asymmetric contact pairs with different work functions, we demonstrate a silver/molybdenum sulfide/platinum photodiode with an open-circuit voltage of 1.02 volts. Our study not only experimentally validates the fundamental limit of ideal metal–semiconductor junctions but also defines a highly efficient and damage-free strategy for metal integration that could be used in high-performance electronics and optoelectronics.
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X.D. acknowledges support by the Office of Naval Research through grant number N00014-15-1-2368. Y.H. acknowledges support by the National Science Foundation EFRI-1433541. I.S. thanks the Deanship of Scientific Research at King Saud University for its funding of this research through grant number PEJP-17-01. L.L. acknowledges support by the National Key Research and Development Program of China number 2016YFB0401103. We acknowledge the Electron Imaging Center at UCLA for TEM technical support and the Nanoelectronics Research Facility at UCLA for device fabrication technical support.
X.D. and Y.H. conceived the research. X.D. and Y.L. designed the experiments. Y.L. performed the experiments and data analysis. J.G., S.L. and M.D. contributed to the device fabrication. E.Z. contributed to cross-sectional TEM characterization. L.L., I.S. and V.G. contributed to discussions and data analysis. X.D. and Y.L. co-wrote the manuscript. All authors discussed the results and commented on the manuscript.
Correspondence to Yu Huang or Xiangfeng Duan.
Extended Data Fig. 1 Optical images, photographs and characterization of the transfer process of the metal electrodes.
a–d, Optical images of Au electrodes deposited on a SiO2 substrate (a), physically released using 1-μm-thick PMMA (b), attached to a PDMS (with PMMA) substrate (c) and transferred onto the target substrate (d). Scale bars, 200 μm in a–d. e–h, The corresponding photographs of Au electrodes deposited on a SiO2 substrate (e), physically released using 1-μm-thick PMMA (f), attached on a PDMS (with PMMA) substrate (g), and transferred onto the target substrate (h). i, Atomic force microscopy image of the bottom side of the transferred electrodes, with a root-mean-square surface roughness of 0.26 nm.
Extended Data Fig. 2 Substrate doping effect on MoS2.
a, Optical image of a seven-layer MoS2 flake on a SiO2 substrate contacted with transferred Pt electrodes. Inset, the optical image of MoS2 on SiO2 before the metal contact. Scale bar, 20 μm. b, Ids–Vgs transfer curve of MoS2 transistor on a SiO2 substrate under various bias voltages of 10 mV (black), 100 mV (red), 500 mV (blue) and 1 V (cyan), demonstrating n-type behaviour, suggesting the involvement of defect states within the SiO2–MoS2 interface. c, Optical image of a MoS2 flake approximately 15 layers thick on a PMMA substrate, contacted with transferred Pt electrodes. Inset, the optical image of MoS2 on PMMA before the metal contact. Scale bar, 20 μm. d, Ids–Vgs transfer curve of MoS2 transistor encapsulated in PMMA under various bias voltages of 10 mV (black), 100 mV (red), 500 mV (blue) and 1 V (cyan), demonstrating p-type behaviour, suggesting that the use of a PMMA substrate is essential for preventing substrate pinning effects and retaining the intrinsic properties of MoS2 flakes. All measurements were conducted at room temperature in probe stations.
Extended Data Fig. 3 Highest-hole-mobility device using transferred Pt as the contact electrodes.
a, Optical image of a MoS2 flake on a PMMA/SiO2 substrate. b, Optical image of the MoS2 flake after being contacted by transferred Pt electrodes. The channel length is 13.5 μm and the effective channel width is 8.37 μm. Scale bar in a, b, 10 μm. c, Ids–Vds output curve of the MoS2 transistor under various gate voltages from −60 V to 60 V. d, e, Linear (d) and semi-logarithmic (e) plot of the Ids–Vgs transfer curve of the MoS2 transistor under various bias voltages: 10 mV (black), 100 mV (red), 500 mV (blue) and 1 V (cyan). The purple line is the gate leakage current (Ig), which is an order of magnitude smaller (limited by equipment) than Ids and will not affect the overall carrier transport. Under large gate voltage, the channel majority carrier is inverted to electrons and the carrier concentration is increased exponentially, greatly reducing the electron Schottky barrier width. As a result, the electrons can tunnel through the thin Schottky barrier from the source side, which accounts for the observed ambipolar behaviour. f, The extracted two-terminal field-effect hole mobility using various bias voltages: 10 mV (black), 100 mV (red), 500 mV (blue), 1V (cyan). The width/length ratio is 0.62. The gate dielectric is composed of 300-nm-thick SiO2 and 170-nm-thick PMMA and is calculated to be 6.2 nF cm−2. The highest extracted hole mobility is 175 cm2 V−1 s−1. All measurements were conducted at room temperature in probe stations.
Extended Data Fig. 4 Flat-band Schottky barrier extraction.
a, b, Ids–Vgs transfer curves of a MoS2 transistor using transferred Ag electrodes under various temperatures, with the bias voltage fixed at 100 mV. c, The extracted n-type Schottky barrier height at various gate voltages, where the flat-band electron Schottky barrier is measured to be 20 mV. The flat-band voltage and corresponding Schottky barrier are shown by the dashed lines. d, e, Ids–Vgs transfer curves of a MoS2 transistor using transferred Pt electrodes under various temperatures, with the bias voltage fixed at 100 mV. f, The extracted p-type Schottky barrier height at various gate voltages, where the flat-band hole Schottky barrier is measured to be 67 mV. The flat-band voltage and corresponding Schottky barrier are shown by the dashed lines. Tran, transferred.
Extended Data Fig. 5 Highest-electron-mobility device using transferred Ag as the contact electrodes.
a, Optical image of a MoS2 flake on a PMMA/SiO2 substrate. b, Optical image of the MoS2 flake after being contacted by transferred Ag electrodes. The channel length here is 10 μm and the effective channel width is 5.36 μm. Scale bar in a, b, 10 μm. c, Ids–Vds output curve of the MoS2 transistor under various gate voltages from −60 V to 60 V. d, e, Linear (d) and semi-logarithmic (e) plot of Ids–Vgs transfer curve of the MoS2 transistor under various bias voltages: 10 mV (black), 100 mV (red), 500 mV (blue) and 1 V (cyan). The purple line is the gate leakage current (Ig), which is an order of magnitude smaller than Ids (limited by equipment) and will not affect the overall carrier transport. Under large gate voltage, the channel majority carrier is inverted to holes and the carrier concentration is increased exponentially, greatly reducing the hole Schottky barrier width. As a result, the holes can tunnel through the thin Schottky barrier from the drain side, which accounts for the observed ambipolar behaviour. f, The extracted two-terminal field-effect electron mobility using various bias voltages: 10 mV (black), 100 mV (red), 500 mV (blue) and 1 V (cyan). The width/length ratio is 0.54. The gate dielectric is composed of 300-nm-thick SiO2 and 170-nm-thick PMMA and is calculated to be 6.2 nF cm−2. The highest extracted electron mobility is 260 cm2 V−1 s−1. All measurements are conducted at room temperature in probe stations.
Extended Data Fig. 6 Highest n-type current density using transferred Ag and p-type current density using transferred Pt as the contact electrodes.
a–c, Optical image of initial thin BN flake (a), after MoS2 has been dry-transferred onto BN using an alignment transfer technique (b), and the final device with transferred Ag electrodes (c). The channel length is about 160 nm and the channel width is about 6 μm. The gate dielectric is composed of approximately 5-nm-thick BN flake and 90-nm-thick SiO2 (rather than the 300-nm-thick SiO2 and 170-nm-thick PMMA dielectric used previously) for larger gate capacitance and stronger gate coupling to ensure the highest driving current. d, e, Ids–Vds output curves of the fabricated MoS2 transistor under various gate voltages from −40 V to 40 V. The highest current density is measured to be 0.66 mA μm−1. f, Ids–Vgs transfer curve of the fabricated MoS2 transistor under various bias voltages. With increasing bias voltage, the OFF current of the device increases owing to the short channel effect. g–i, Optical image of initial thin BN flake (g), after MoS2 has been dry-transferred onto BN using an alignment transfer technique (h), and the final device with transferred Pt electrodes (i). The channel length is ~140 nm, the channel width is about 6 μm and the gate dielectric is composed of approximately10-nm-thick BN flake and 90-nm-thick SiO2. j, k, Ids–Vds output curve of the fabricated MoS2 transistor under various gate voltages from 0 V to −40 V. The highest current density is measured to be 0.21 mA μm−1. Scale bar in a–c and g–i, 10 μm. All measurements were conducted at room temperature in probe stations.
Extended Data Fig. 7 Photoresponse of a monolayer MoS2 device with transferred Ag and Pt asymmetric electrodes.
a, Optical image of monolayer MoS2 mechanically exfoliated on a 170 nm PMMA/300 nm SiO2 substrate. b, Optical image of the device after Ag and Pt asymmetric electrodes are transferred on top of monolayer MoS2. Scale bar in a, b, 10 μm. c, Semi-logarithmic plot of Ids–Vds output curve under various gate voltages (−60 V to 60 V, 10 V step) under dark conditions. The Pt is biased and the Ag is grounded. d, Semi-logarithmic plot of Ids–Vds output curve under various gate voltages (−60 V to 60 V, 10 V step) under laser illumination. e, The Ids–Vds output curve under dark and laser illumination, under gate −50 V. The highest open-circuit voltage of 1.02 V is observed in monolayer devices.
Extended Data Fig. 8 Photoresponse of a multilayer MoS2 device with deposited Ag and Pt asymmetric electrodes.
a, Optical image of the device. Scale bar, 5 μm. b, Semi-logarithmic plot of Ids–Vds output curve under various gate voltages (−60 V to 60 V, 10 V step) under dark conditions. The Pt is biased and the Ag is grounded. c, Semi-logarithmic plot of Ids–Vds output curve under various gate voltage (−60 V to 60 V, 10 V step) under laser illumination. d, Ids–Vds output curve under dark conditions and laser illumination, under a gate voltage of 10 V. The highest open-circuit voltage of about 0.3 V is observed.

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