Source: https://es.scribd.com/document/247856184/1724003
Timestamp: 2019-04-23 00:02:37+00:00

Document:
1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.
A voltage below the threshold VFBbm activates the burst-mode operation. The internal set default value of the cycle-by-cycle current limit can be reduced by connecting to ground an CONT external resistor.. 2 5 VDD Supply voltage of the control section. Pin description Pin n. 2. A voltage below the threshold VBRth shuts down (not latch) the device and lowers the power consumption. It can be connected to GND (pins 1-2) or left not connected. It can be connected to ground when not used.Pin settings 3 VIPER27 Pin settings Figure 3. FB Control input for duty cycle control. Pins connected to the metal frame to facilitate heat dissipation. - 4 N. Note: Connection diagram (top view) The copper area for heat dissipation has to be designed under the DRAIN pins. Table 3. BR Brownout protection input with hysteresis. Device operation restarts as the voltage exceeds the threshold VBRth + VBRhyst.2 GND This pin represents the device ground and the source of the power section.. The built-in high voltage switched start-up bias 13.. The following functions can be selected: 1. current limit set point adjustment.16 DRAIN current is drawn from this pin too.. A level close to the threshold VFBlin means that we are approaching the cycle-by-cycle over-current set point. This function is strobed and digitally filtered for high noise immunity. High voltage drain pin. Internal current generator provides bias current for loop regulation. 3 4 5 7. Name SO16N 1 1. output voltage monitoring. This pin also provides the charging current of the external capacitor during start-up time.A.8 4/31 Function DIP7 6 7 8 Control pin. Doc ID 15133 Rev 5 . A voltage exceeding VOVP threshold (see Table 8 on page 7) shuts the IC down reducing the device consumption. Not available for user.
5 V VBR Brown-out input pin voltage (with IBR = 0.VIPER27 Electrical data 4 Electrical data 4.2 Max W Power dissipation at TA < 60 °C (SO16N) 1.5 A 3 A IDRAIN Pulse drain current (limited by TJ = 150 °C) VCONT Control input pin voltage (with ICONT = 1 mA) -0.5 Operating junction temperature range -40 150 °C Storage temperature -55 150 °C Thermal data Table 5. Absolute maximum ratings Value Symbol Parameter Unit Min VDRAIN Drain-to-source (ground) voltage 800 V EAV Repetitive avalanche energy (limited by TJ = 150 °C) 5 mJ IAR Repetitive avalanche current (limited by TJ = 150 °C) 1. Thermal data Max value Symbol Parameter Unit SO16N DIP7 RthJP Thermal resistance junction pin (Dissipated power = 1 W) 25 35 °C/W RthJA Thermal resistance junction ambient (Dissipated power = 1 W) 60 100 °C/W RthJA Thermal resistance junction ambient (1) (Dissipated power = 1 W) 50 80 °C/W 1. When mounted on a standard single side FR4 board with 100 mm2 (0.1 Maximum ratings Table 4.5 mA) -0.3 Self limited V VDD Supply voltage (IDD = 25 mA) -0.3 Self limited V IDD Input current 25 mA Power dissipation at TA < 40 °C (DIP-7) 1 PTOT TJ TSTG 4.3 Self limited V VFB Feed-back voltage -0.3 5.155 sq in) of Cu (35 µm thick) Doc ID 15133 Rev 5 5/31 .
VFB = 3 V.5 V 4 4. VFB = GND Current VDD = 7 V a.5 8 8. with protection tripping IDD_OFF Operating supply current with VDD < VDD_OFF VDRAIN = 120 V. VBR = GND. VBR = GND.5 mA V V 13 14 15 V 7. TJ = 125 °C 14 Ω IOFF RDS(on) COSS Table 7. VBR = GND. VBR = GND. VDD = 10 V 0. VFB = GND 60 μA IDRAIN = 0. 6/31 Doc ID 15133 Rev 5 .5 mA VDRAIN = 120 V. -0.4 -0.6 -0. FSW = 60 kHz 2. VFB = 3 V. not switching IDD1 Operating supply current. Symbol Drain-source on state resistance Effective (energy related) output capacitance Test condition Min Typ Max Unit 800 VDRAIN = 0 to 640 V V 40 pF Supply section Parameter Test condition Min Typ Max Unit Voltage VDRAIN_START Drain-source start voltage IDDch VDD VDDclamp Start up charging current VDRAIN = 120 V.4 A. Adjust VDD above VDDon start-up threshold before settings to 14 V. VBR = GND. unless otherwise specified) Table 6. switching IDD_FAULT Operating supply current.5 VDD clamp voltage IDD = 20 mA 23.3 VIPER27 Electrical characteristics (TJ = -25 to 125 °C. Power section Symbol Parameter VBVDSS Break-down voltage IDRAIN = 1 mA.Electrical data 4.5 5 V VFB = GND.5 mA 400 μA 270 μA VDDon VDD start up threshold VDDoff VDD under voltage shutdown threshold VDD(RESTART) VDD restart voltage threshold VDRAIN = 120 V. FSW = 0 kHz. VFB = GND IDD0 Operating supply current. VDD = 4 V 60 80 100 V -2 -3 -4 mA VDRAIN = 120 V. VBR = GND. VDD = 4 V after fault.9 mA VDRAIN = 120 V.5 23. FSW = 115 kHz 3. VFB = GND. TJ = 25 °C 7 Ω IDRAIN = 0.4 A. VBR = GND.8 Operating voltage range After turn-on 8. VFB = GND TJ = 25 °C OFF state drain current VDRAIN = max rating. VFB = GND. VDD = 14 V(a).
VFB = 1 V VIPER27L FOSC VIPER27H FD 60 66 kHz 103 115 127 kHz VIPER27L ±4 kHz VIPER27H ±8 kHz 250 Hz Modulation depth FM Modulation frequency DMAX Maximum duty cycle Over current protection IDMAX 54 70 80 % (2nd OCP) Second over current threshold 1 A Overvoltage protection VOVP TSTROBE Overvoltage protection threshold 2. ICONT = -10 µA TJ = 25 °C 0.3 V ΔVFB / ΔID 14 21 kΩ 2 6 V/A CONT pin ICONT = -100 µA VCONT_l Low level clamp voltage 0.6 V VFBbmhys Burst mode hysteresis Voltage rising 100 mV -150 -200 -280 μA -3 μA IFB RFB(DYN) HFB VFB = 0.74 8.5 V Current limitation IDlim Max drain current limitation tSS Soft-start time TON_MIN td tLEB ID_BM VFB = 4 V.2 3.2 Doc ID 15133 Rev 5 3.7 Overvoltage protection strobe time 3 2.8 5.66 0.8 V Dynamic resistance VFB < 3.5 Minimum turn ON time 220 400 A ms 480 ns Propagation delay 100 ns Leading edge blanking 300 ns 160 mA Peak drain current during burst mode VFB = 0.3 V us 7/31 .7 0.VIPER27 Table 8. Electrical data Controller section Symbol Parameter Test condition Min Typ Max Unit Feed-back pin VFBolp Over load shutdown threshold 4.3 V < VFB < 4.3 V Feed-back sourced current 3.5 3.6 V Oscillator section VDD = operating voltage range.2 V VFBlin Linear dynamics upper limit 3.7 V VFBbm Burst mode threshold Voltage falling 0.5 4.
VIPER27 Controller section (continued) Symbol Parameter Test condition Min Typ Max Unit Brown out protection VBRth Brown out threshold Voltage falling 0.49 V VBRhyst Voltage hysteresis above VBRth Voltage rising 50 mV IBRhyst Current hysteresis VBRclamp VDIS Clamp voltage 7 IBR = 250 µA Brown out disable voltage 12 3 50 μA V 150 mV Thermal shutdown TSD THYST 8/31 Thermal shutdown temperature 150 Thermal shutdown hysteresis Doc ID 15133 Rev 5 160 °C 30 °C .Electrical data Table 8.41 0.45 0.
Brown out threshold test circuit VBR GND DRAIN VBRth+VBRhyst VBRth VDD DRAIN VDIS IBR Time IDRAIN Time 10 kΩ CONT IBRhyst IBRhyst BR FB 14 V 30 V 2V Time Figure 6. OVP threshold test circuit VCONT 14 V GND DRAIN VDD DRAIN CONT FB VOVP 10 kΩ VDRAIN BR Time 30 V 2V Time Note: Adjust VDD above VDDon start-up threshold before settings to 14 V Doc ID 15133 Rev 5 9/31 .VIPER27 Electrical data Figure 4. Minimum turn-on time test circuit VDRAIN 14 V GND DRAIN VDD DRAIN 90 % TONmin 50 Ω CONT 10 % IDRAIN BR FB 30 V 3.5 V Time IDLIM Time Figure 5.
Brown out threshold vs TJ 10/31 Switching frequency vs TJ Figure 12.Typical electrical characteristics 5 VIPER27 Typical electrical characteristics Figure 7. Drain start voltage vs TJ Figure 10. Current limit vs TJ Figure 8. Figure 9. Brown out hysteresis vs TJ Doc ID 15133 Rev 5 . HFB vs TJ Figure 11.
VIPER27 Typical electrical characteristics Figure 13. Power MOSFET on-resistance Figure 18. Power MOSFET break down vs TJ voltage vs TJ Doc ID 15133 Rev 5 11/31 . Brown out hysteresis current Figure 14. Operating supply current (switching) vs TJ Figure 16. Operating supply current vs TJ (no switching) vs TJ Figure 15. current limit vs RLIM Figure 17.
Typical electrical characteristics VIPER27 Figure 19.THYST Normal operation 12/31 Shut down after over temperature Doc ID 15133 Rev 5 Normal operation time . Thermal shutdown VDD VDDon VDDoff VDD(RESTART) time IDRAIN time TJ TSD TSD .
VIPER27 6 Typical circuit Typical circuit Figure 20. Min-features flyback application D3 AC IN R1 C2 BR Vout C1 C5 AC IN D1 GND D2 R2 R3 VVcc DD OPTO DRAIN R5 BR CONTROL C3 R4 CONT FB C6 GND SOURCE U2 C4 R6 Figure 21. Full-features flyback application D3 Rh AC IN BR C2 Vout R1 C1 C5 Rl AC IN D1 GND Daux Rov p D2 R2 R3 VVcc DD DRAIN OPTO R5 BR CONTROL C3 R4 CONT FB C6 GND SOURCE U2 Rlim C4 Doc ID 15133 Rev 5 R6 13/31 .
the current limit circuit with adjustable set point. 80 VDC typically. the PWM logic. the burst mode management. The power section has a BVDSS of 800 V min. The current limit set-point is set by the CONT pin. in order to have a slow duty cycle during the restart phase. All the fault protections are built in auto restart mode with very low repetition rate to prevent IC's over heating. 7. the second over current circuit. The burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment. and a typical RDS(on) of 7 Ω at 25 °C. the IDDch current (3 mA typical value) is delivered to the capacitor on the VDD pin.Operation descriptions 7 VIPER27 Operation descriptions VIPER27 is a high-performance low-voltage PWM controller chip with an 800 V. The integrated SenseFET structure allows a virtually loss-less current sensing.6 mA. which guarantees safe operation within the specified energy rating as well as high dv/dt capability. the brown-out circuit.2 High voltage startup generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VDRAIN_START threshold. the start up circuits with soft-start feature. The controller includes: the oscillator with jittering feature. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common mode EMI. In case of auto restart mode after a fault event. the UVLO circuit. the IDDch current is reduced to 0. the auto-restart circuit and the thermal protection circuit. 14/31 Doc ID 15133 Rev 5 . avalanche rugged Power section. 7. When the HV current generator is ON.1 Power section and gate driver The power section is implemented with an avalanche ruggedness N-channel MOSFET.
UP NORMAL MODE Doc ID 15133 Rev 5 BURST MODE NORMAL MODE 15/31 . CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than VDDoff threshold. the VDD voltage begins to grow due to the IDDch current (see Table 7 on page 6) coming from the internal high voltage start up circuit. If the VDD voltage reaches VDDon threshold (see Table 7 on page 6) the power MOSFET starts switching and the HV current generator is turned OFF. CVDD. The following formula can be used for the VDD capacitor calculation: Equation 1 I DDch × tSSaux C VDD = ---------------------------------------V DDon – V DDoff The tSSaux is the time needed for the steady state of the auxiliary voltage. See Figure 23 on page 16.3 Operation descriptions Power-up and soft-start up If the input voltage rises up till the device start threshold. etc. This time is estimated by applicator according to the output stage configurations (transformer. a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding.). In fact. VDRAIN_START. The soft-start time lasts 8.VIPER27 7. until when the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. In this way the stress on the secondary diode is considerably reduced.5 ms and the feature is implemented for every attempt of start up converter or after a fault. the drain current limitation is progressively increased to the maximum value. The IC is powered by the energy stored in the capacitor on the VDD pin. It also helps to prevent transformer saturation. Figure 22. output capacitances. During the converter start up time. IDD current during start-up and burst mode VDD VDDon VDDoff t VFB VFBolp VFBlin VFBbmhys VFBbm t VDRAIN t IDD IDD1 IDD0 t IDDch (-3 mA) START.
Timing diagram: normal power-up and power-down sequences VIN VIN < VDRAIN_START HV startup is no more activated VDRAIN_START VDD regulation is lost here time VDDon VDDoff VDD(RESTART) VDRAIN time IDD time IDDch (3mA) Normal operation Power-on time Power-off Figure 24. Soft-start: timing diagram IDRAIN IDlim t VFB VFBolp VFBlin t VOUT t tSS 16/31 ( SOFT START.Operation descriptions VIPER27 Figure 23.UP ) DELAY (OLP) Doc ID 15133 Rev 5 STEADY STATE .
5(67$57. Later. the energy transfers to the IC interrupted and consequently the VDD voltages decreases.
W 7UHS W W )$$ )$$CH  M! 6&" W 6&"OLP 6&"LIN W 7. so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes.6 Oscillator The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz version) at 250 Hz (typical) rate. 7UHS 6$2!). Doc ID 15133 Rev 5 17/31 .
that the designer can adjust according the electrical specification.7 VIPER27 Current mode conversion with adjustable current limit set point The device is a current mode converter: the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. four consecutive times. The sampled signal. through the turn ratio N AUX -------------N SEC The CONT pin has to be connected to the auxiliary winding through the diode DOVP and the resistors ROVP and RLIM as shows the Figure 27 on page 20 When. Referring to the Figure 21. by the RLIM resistor connected to the CONT see Figure 16 on page 11.8 Overvoltage protection (OVP) The VIPER27 has integrated the logic for the monitor of the output voltage using as input signal the voltage VCONT during the OFF time of the power MOSFET. during the OFF time. This voltage is compared with the one on the feed-back pin through a voltage divider on cycle by cycle basis. see Table 8 on page 7 and the Figure 26 on page 19. the reference voltage VOVP (see Table 8 on page 7) the overvoltage protection will stop the power MOSFET and the converter enters the auto-restart mode. IDlim. if higher than VOVP. This is the time when the voltage from the auxiliary winding tracks the output voltage.e. The VIPER27 has a default current limit value. the resistors divider ratio kOVP will be given by: Equation 2 V OVP k OVP = -------------------------------------------------------------------------------------------------N AUX -------------.Operation descriptions 7. In order to bypass the noise immediately after the turn off of the power MOSFET. The CONT pin has a minimum current sunk needed to activate the IDlim adjustment: without RLIM or with high RLIM (i. the voltage VCONT exceeds. The same counter is reset every time the signal OVP is not triggered in one oscillator cycle. 100 kΩ) the current limit is fixed to the default value (see IDlim. trigger the internal OVP digital signal and increments the internal counter. Table 8 on page 7). the voltage VCONT is sampled inside a short window after the time TSTROBE. 7.⋅ ( V OUTOVP + V DSEC ) – V DAUX N SEC Equation 3 R LIM k OVP = --------------------------------R LIM + R OVP 18/31 Doc ID 15133 Rev 5 .
Figure 26. fixed RLIM. the ROVP can be calculating by: Equation 4 1 – k OVP R OVP = R LIM × ----------------------k OVP The resistor values will be such that the current sourced and sunk by the CONT pin be within the rated capability of the internal clamp. according to the desired IDlim. OVP timing diagram VDS t VAUX 0 VCONT t V OVP t 2 µs STROBE 0.5 µs t OVP t COUNTER RESET COUNTER STATUS t 0 0 0 0 →1 1 →2 2 →0 0 0 →1 1 →2 2 →3 FAULT 3 →4 t NORMAL OPERATION TEMPORARY DISTURBANCE Doc ID 15133 Rev 5 FEEDBACK LOOP FAILURE t 19/31 .VIPER27 Operation descriptions Where: ● VOVP is the OVP threshold (see Table 8 on page 7) ● VOUT OVP is the converter output voltage value to activate the OVP set by designer ● NAUX is the auxiliary winding turns ● NSEC is the secondary winding turns ● VDSEC is the secondary diode forward voltage ● VDAUX is the auxiliary diode forward voltage ● ROVP together RLIM make the output voltage divider Than.
seeFigure 2 on page 3.10 Feed-back and overload protection (OLP) The VIPER27 is a current mode converter: the feedback pin controls the PWM operation. RLIM has to be fixed before of ROVP 7. See Figure 2 on page 3. CONT pin configuration R OV P CONT SOFT START OCP BLOCK - Daux + Auxiliary winding OVP LOGIC R LIM OCP to GATE driver From RSENSE OVP Table 9. With the feedback pin voltage between VFBbm and VFBlin. lists the external components needed to activate one or plus of the CONT pin functions. This voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis.Operation descriptions 7. through the CONT pin. 20/31 Doc ID 15133 Rev 5 . Figure 27. The drain current is always limited to IDlim value.9 VIPER27 About CONT pin Referring to the Figure 27. Current limit set point 2. Figure 28 on page 22 and Figure 29 show the internal current mode structure. the PWM comparator is disabled and the drain current is limited to IDlim by the OCP comparator. the PWM logic orders the switch off of the power MOSFET. In case of overload the feedback pin increases in reaction to this event and when it goes higher than VFBlin. When these two voltages are equal. CONT pin configurations Function / component RLIM (1) ROVP DAUX IDlim reduction See Figure 16 No No OVP ≥ 80 kΩ See Equation 4 Yes IDlim reduction + OVP See Figure 16 See Equation 4 Yes 1. Over voltage protection on the converter output voltage The Table 9 on page 20 referring to the Figure 27. controls the burst mode and actives the overload protection. the below features can be implemented: 1. (see Table 8 on page 7) the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator.
two poles (fPFB. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. the capacitor connected to FB pin (CFB) is part of the compensation circuit as well as it needs to activate the over load protection (see equation 5). the appropriate feedback network has to be selected according to the output load. When the value of the CFB capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay. During the first start up phase of the converter. the output capacitor could not be at its nominal value and the controller interprets this situation as an over load condition. an alternative compensation network can be used and it is showed in Figure 29 on page 22. The Figure 28 on page 22 and Figure 29 show the two different feedback networks. the converter is turned off and the start up phase is activated with reduced value of IDDch to 0. More the network feedback fixes the compensation loop stability. The time from the over load detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp) can be set by CFB value (see Figure 28 on page 22 and Figure 29). The mathematical expressions of these poles and zero frequency. during which the feedback voltage is fixed at VFBlin. see Table 7 on page 6. tSS. the OLP delay helps to avoid an incorrect device shut down during the start up phase. tSS. The output transient time depends from the value of the output capacitor and from the load.6 mA. Using this alternative compensation network.VIPER27 Operation descriptions When the feedback pin voltage reaches the threshold VFBlin an internal current generator starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the VFBolp threshold. To avoid this event. the OLP delay time must be long enough to by-pass the initial output voltage transient and check the over load condition only when the output voltage is in steady state. using the formula: Equation 5 V FBolp – V FBlin T OLP – delay = C FB × ---------------------------------------3μA In the Figure 28. after the soft-start up time. the output voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches off the converter itself. fPFB1) and one zero (fZFB) are introduced by the capacitors CFB and CFB1 and the resistor RFB1. After the start up time. In this case. This pole is usually used to compensate the high frequency zero due to the ESR (equivalent series resistor) of the output capacitance of the fly-back converter. considering the scheme in Figure 29 are reported by the equations below: Equation 6 fZFB = 1 2 ⋅ π ⋅ CFB1 ⋅ RFB1 Doc ID 15133 Rev 5 21/31 . Owing to the above considerations.
the designer can satisfy.8V 22/31 Doc ID 15133 Rev 5 - To disable logic . Using the alternative compensation network. The Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered instead of CFB. FB pin configuration From sense FET PWM To PWM Logic + PWM CONTROL - Cfb BURST BURST-MODE LOGIC BURST-MODE REFERENCES OLP comparator To disable logic + - 4.Operation descriptions VIPER27 Equation 7 fPFB = RFB(DYN) + RFB1 2 ⋅ π ⋅ CFB ⋅ RFB(DYN) ⋅ RFB1 ( ) 1 2 ⋅ π ⋅ CFB1 ⋅ RFB1 + RFB(DYN) ) Equation 8 fPFB1 = ( The RFB(DYN) is the dynamic resistance seen by the FB pin. The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. the loop stability and the enough OLP delay time alike.8V Figure 29. FB pin configuration From sense FET PWM To PWM Logic + PWM CONTROL - Rfb1 Cfb BURST Cfb1 BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4. in all case. Figure 28.
and disables the PWM if the voltage applied at the BR pin is below this internal reference.11 Operation descriptions Burst-mode operation at no load or very light load When the load decrease the feedback loop reacts lowering the feedback pin voltage. The switching operation is restarted as the voltage on the pin is above the reference plus the before said voltage hysteresis. Doc ID 15133 Rev 5 23/31 . IBRhyst. the power MOSFET is not more allowed to be switched on. reported on Table 8. VFBbm t IDRAIN Normal -mode 7. the feedback pin voltage increases and exceeding the level. VFBbm + VFBbmhys. see Table 8 on page 7. the VDD voltage continuously oscillates between the VDDon and the UVLO thresholds. see Table 8 on page 7. up to some hundred of hertz. the power MOSFET starts switching again. The power delivered to output during switching periods exceeds the load power demands. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency. The burst mode thresholds are reported on Table 8 and Figure 30 shows this behavior. the excess of power is balanced from not switching period where no power is processed.VIPER27 7. VINoff. After the MOSFET stops. See Figure 5 on page 9. If it falls down the burst mode threshold. The Brown-out comparator is internally referenced to VBRth threshold. as shown in the timing diagram of Figure 31 on page 24. as a result of the feedback reaction to the energy delivery stop. VINon. Thanks to the IBRhyst. Under this condition the power MOSFET is turned off. these two thresholds can be set separately. The designer has to set the rectified input voltage above which the power MOSFET starts switching after brown out event. light load management VFB 100 50 mV hyster. VFBbm. Figure 30. ID_BM. Until the Brown out condition is present. and the rectified input voltage below which the power MOSFET is switched off. The Brown-out comparator is provided also with a current hysteresis.12 Burst-mode Normal -mode t Brown-out protection Brown-out protection is a not-latched shutdown function activated when a condition of mains under voltage is detected. Burst mode timing diagram. A voltage hysteresis is present to improve the noise immunity. Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching. this device working mode is the burst mode. During the burst-mode the drain current peak is clamped to the level. minimizing all frequency related losses.
which might alter the OFF threshold when the converter operates or gives origin to undesired switch-off of the device during ESD tests. In order to enable the brown-out function the BR pin voltage has to be higher than the maximum of VDIS threshold (150 mV. the following relationships can be established for the calculation of the resistors RH and RL: Equation 9 RL = − VBRhyst IBRhyst + VINon − VINoff − VBRhyst VINoff − VBRth × VBRth IBRhyst Equation 10 RH = VINon − V INoff − V BRhyst I BRhyst × RL + RL V BRhyst I BRhyst For a proper operation of this function. If the brown-out function is not used the BR pin has to be connected to GND.Operation descriptions VIPER27 Figure 31. It is possible to bypass the pin to ground with a small film capacitor (e. 24/31 Doc ID 15133 Rev 5 . Brown-out protection: BR external setting and timing diagram VIN VINon VINoff VBR t VBRth VDD Vcc VIN t VDIS Rh Vin_OK + - t IBR AC_OK Disable IBRhyst BR + VDDon - VBRth VDD Vin_OK t VDDoff IBRhyst Rl t VDRAIN t VOUT t Fixed the VINon and the VINoff levels.g. ensuring that the voltage is lower than the minimum of VDIS threshold (50 mV. 1-10 nF) to prevent any malfunctioning of this kind. with reference to Figure 31. thus it is prone to pick up noise. The BR pin is a high impedance input connected to high value resistors. see Table 8). VIN on must be less than the peak voltage at minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. see Table 8).
with very low stress on the power circuit. Such as anomalous condition is invoked when the drain current exceed the threshold IDMAX. VDD(RESTART). which clears the latch.g. To distinguish a real malfunction from a disturbance (e. short circuit on the secondary winding or a hard-saturation of fly-back transformer.13 Operation descriptions 2nd level over current protection and hiccup mode The VIPER27 is protected against short circuit of the secondary rectifier. Hiccup-mode OCP: timing diagram VDD Vcc Secondary diode is shorted here VDDon VDD off VDD (RESTART) t IDRAIN IDMAX t VDRAIN t Doc ID 15133 Rev 5 25/31 . While it is disabled. This behavioral results in a low-frequency intermittent operation (Hiccup-mode operation). otherwise if the IDMAX threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power MOSFET is turned OFF. induced during ESD tests) a “warning state” is entered after the first signal trip. The shutdown condition is latched as long as the device is supplied. see Table 8 on page 7. See the timing diagram of Figure 32. until VDD voltage goes below its restart voltage. The start up HV current generator is still off. After this condition the VDD capacitor is charged again by 600 µA current. and the converter switching restarts if the VDDon occurs. hence the voltage on the VDD capacitor decays till the VDD under voltage threshold (VDDoff). If in the subsequent switching cycle the signal is not tripped. Figure 32. no energy is transferred from the auxiliary winding. If the fault condition is not removed the device enters in auto-restart mode.VIPER27 7. a temporary disturbance is assumed and the protection logic will be reset in its idle state.
Typ.com. Table 10. A 5.62 7.35 7.52 1.81 2.92 2.14 1.46 0.548 Doc ID 15133 Rev 5 .54 eA 7.60 O 26/31 Max.33 A1 0. grade definitions and product status are available at: www.36 0.27 10. ECOPACK® specifications.40 0.50 N1 0.20 0. 0.95 b 0.508 0.30 3.26 E1 6.Package mechanical data 8 VIPER27 Package mechanical data In order to meet environmental requirements. ECOPACK® is an ST trademark.25 0.st.36 D 9. ST offers these devices in different grades of ECOPACK® packages.92 3. depending on their level of environmental compliance.56 b2 1.62 eB L 10.16 E 7.92 M N 3.87 8.60 0. DIP-7 mechanical data mm Dim. Min.02 9.11 e 2.30 4.38 A2 2.10 6.78 c 0.
Package dimensions Doc ID 15133 Rev 5 27/31 .VIPER27 Package mechanical data Figure 33.
VIPER27 SO16 narrow mechanical data mm Dim.9 10 E 5.8 3.1 A2 1.25 D 9. Min.8 9.17 0. 0. A 1.31 0.5 L 0.4 1.8 6 6.27 k 0 8 ccc 28/31 Max. Typ.2 E1 3.25 0.25 1.9 4 e 0.1 Doc ID 15133 Rev 5 .51 c 0.25 b 0.Package mechanical data Table 11.27 h 0.75 A1 0.
SO16 narrow mechanical data Doc ID 15133 Rev 5 29/31 .VIPER27 Package mechanical data Figure 34.
16-Jun-2010 4 Updated Figure 3 on page 4 and Table 3 on page 4. 22-Oct-2009 3 Updated Table 5 on page 5. Doc ID 15133 Rev 5 . Figure 12 and Figure 13.Revision history 9 VIPER27 Revision history Table 12. 30-Jul-2010 5 Updated Figure 11. 30/31 Document revision history Date Revision Changes 16-Jan-2009 1 Initial release 20-Jul-2009 2 Added SO16 narrow package.
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