Source: http://dtsheet.com/doc/845864/silabs-si860x
Timestamp: 2019-04-22 10:36:06+00:00

Document:
temperature and age versus opto couplers or other digital isolators.
isolation channels to support additional system signals, such as interrupts or resets.
unpowered device is inserted into a powered system.
*Note: All voltages are relative to respective ground.
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
1. All voltages are relative to respective ground.
2. VIL < 0.410 V, VIH > 0.540 V.
minimum difference between the output logic low level of the driving device and the input logic threshold.
4. Side A measured at 0.6 V.
combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET.
the same supply voltages, load, and ambient temperature.
*Note: Start-up time is the time period from the application of power to valid data at the output.
Figure 2 depicts the timing test diagram.
The Si860x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
The Si860x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 Vpeak for basic insulation working voltage.
The Si860x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6.Ordering Guide" on page 26.
and SOIC-16 packages and 7.6 mm minimum for the WB SOIC-16 package.
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures 3, 4, and 5.
50% duty cycle square wave.
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Figure 7 for more details.
maximum of 5.0 kVRMS, support I2C clock stretching, and operate to a maximum I2C bus speed of 1.7 Mbps.
typically added to one side of the isolator to avoid this condition (the “A” side for the Si8600/02/05/06).
The following examples illustrate typical circuit configurations using the Si8600/02/05/06.
isolator VIL to prevent the latch condition.
Table 13 lists the I2C isolator design constraints.
less than the bus input low.
too close to the input low logic level.
∆VSDA1, ∆VSCL1 = 50 mV minimum These track over temperature.
Bus VIL 0.3 x VDD = 1.0 V minimum for bus input low voltage.
tracking, but worst case is cold temperature.
The first step in applying an I2C isolator is to choose which side of the bus will be connected to the isolator A side.
isolators are normally used with a pull up of 0.5 mA to 3 mA.
an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V.
level is 0.41 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue.
4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV.
Figures 9 through 14 illustrate typical circuit configurations using the Si8600, Si8602, Si8605, and Si8606.
power supply (VDD) is not present.
this, the outputs follow the states of inputs.
AVDDUVLO+. Side B operates the same as Side A with respect to its BVDD supply.
effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
Table 14 details powered and unpowered operation of the Si86xx’s non-I2C digital channels.
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 3.0 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
channels have pull-downs on inputs/outputs.
7. For I2C channels, the outputs for a given side go to Hi-Z when power is lost on the opposite side.
before starting any design that uses a digital isolator.
may also include resistors (50–300  ) in series with the inputs and outputs if the system is excessively noisy.
page 20 and "6.Ordering Guide" on page 26 for more information.
to Tables 2, 3, 4, and 5 for actual specification limits.
Side A power supply terminal; connect to a source of 3.0 to 5.5 V.
Side A data (open drain) input or output.
Side A clock input or output.
Open drain I/O for Si8600. Standard CMOS input for Si8602.
Side B clock input or output.
Open drain I/O for Si8600. Push-pull output for Si8602.
Side B data (open drain) input or output.
Side B power supply terminal; connect to a source of 3.0 to 5.5 V.
Side A data open drain input or output.
Side B data open drain input or output.
Side A power supply terminal. Connect to a source of 3.0 to 5.5 V.
Side B power supply terminal. Connect to a source of 3.0 to 5.5 V.
Standard CMOS digital input for Si8605.
Side B digital push-pull output (non I2C).
Side A standard CMOS digital input (non I2C).
Standard CMOS digital input for Si8606.
Open drain I/O for Si8605/06.
classifications and peak solder temperature.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-8 packages.
2. All devices >1 kVRMS are AEC-Q100 qualified.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
lists the values for the dimensions shown in the illustration.
for Density Level B (Median Land Protrusion).
fabrication tolerance of 0.05 mm is assumed.
Density Level B (Median Land Protrusion).
values for the dimensions shown in the illustration.
year and workweek of the mold date.
year and work week of the mold date.
Si8601 replaced by Si8602 throughout.
Added chip graphics on page 1.
Moved Table 12 to page 13.
Characteristics for Si86xxxx*,” on page 11.
Moved “3. Typical Application Overview” to page 15.
Updated "5.Pin Descriptions" on page 23.
Updated "6.Ordering Guide" on page 26.
Moved Tables 1 and 2 to page 4.
Moved Table 13 to page 16.
Moved Table 14 to page 20.
Updated Figures 11 and 12.
Updated "4.4.1.Supply Bypass" on page 21.
Updated Table 12 on page 13.

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