Source: https://www2.eecs.berkeley.edu/Faculty/Homepages/elad.html
Timestamp: 2019-04-26 11:54:22+00:00

Document:
Elad Alon joined the University of California at Berkeley in Jan. 2007, where he is now a Professor of Electrical Engineering and Computer Sciences as well as a co-director of the Berkeley Wireless Research Center (BWRC). He has held founding, consulting, or visiting positions at Locix, Lion Semiconductor, Cadence, Xilinx, Sun Labs, Intel, AMD, Rambus, Hewlett Packard, and IBM Research, where he worked on digital, analog, and mixed-signal integrated circuits for computing, high-speed communications, and test and measurement. Dr. Alon received the IBM Faculty Award in 2008, the 2009 Hellman Family Faculty Fund Award, the 2010 and 2017 UC Berkeley Electrical Engineering Outstanding Teaching Award, the 2010 ISSCC Jack Raper Award for Outstanding Technology Directions Paper, the 2011 Symposium on VLSI Circuits Best Student Paper Award, the 2012 and 2013 Custom Integrated Circuits Conference Best Student Paper Award, the 2015 Custom Integrated Circuits Conference Best Invited Paper Award, and the IEEE Symposium on VLSI Circuits Most Frequently Cited Paper Award for 2010-2016. His research focuses on energy-efficient integrated systems, including the circuit, device, communications, and optimization techniques used to design them.
Y. Duan and E. Alon, "A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB," Journal of Solid State Circuits, vol. 49, no. 8, pp. 1725-1738, July 2014.
Y. Duan and E. Alon, "A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB," in Custom Integrated Circuits Conference, IEEE, 2013, pp. 1-4.
M. Tabesh, J. Chen, C. Marcu, L. Kong, S. Kang, A. Niknejad, and E. Alon, "A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver," IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 3018-3032, Dec. 2011.
M. Tabesh, J. Chen, C. Marcu, L. Kong, S. Kang, E. Alon, and A. Niknejad, "A 65nm CMOS 4-Element Sub-34mW/Element 60GHz Phased-Array Transceiver," in International Solid-State Circuits Conference, 2011.
H. Kam, T. King Liu, V. Stojanovic, D. Markovic, and E. Alon, "Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic," Electron Devices, IEEE Transactions on, vol. 58, no. 1, pp. 236 -250, Jan. 2011.
M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. K. Liu, D. Markovic, E. Alon, and V. Stojanovic, "Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications," Solid-State Circuits, IEEE Journal of, vol. 46, no. 1, pp. 308 -320, Jan. 2011.
J. Crossley, E. Naviasky, and E. Alon, "An energy-efficient ring-oscillator digital PLL," in Custom Integrated Circuits Conference (CICC), 2010 IEEE, 2010, pp. 1 -4.
D. Chowdhury, L. Ye, E. Alon, and A. Niknejad, "A 2.4GHz mixed-signal polar power amplifier with low-power integrated filtering in 65nm CMOS," in Custom Integrated Circuits Conference (CICC), 2010 IEEE, 2010, pp. 1 -4.
C. Marcu, D. Chowdhury, C. Thakkar, J. Park, L. Kong, M. Tabesh, Y. Wang, B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, E. Alon, and A. Niknejad, "A 90nm CMOS Low-Power 60GHz Transceiver With Integrated Baseband Circuitry," IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3434-3447, Dec. 2009.
H. Kam, V. Pott, R. Nathanael, J. Jeon, E. Alon, and T. King Liu, "Design and reliability of a micro-relay technology for zero-standby-power digital logic applications," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1 -4.
F. Chen, H. Kam, D. Markovic, T. King Liu, V. Stojanovic, and E. Alon, "Integrated Circuit Design with NEM Relays," in IEEE/ACM International Conference on Computer-Aided Design, 2008.
E. Alon and M. Horowitz, "Integrated Regulation for Energy-Efficient Digital Circuits," IEEE J. Solid State Circuits, vol. 43, no. 8, pp. 1795-1807, Aug. 2008.
E. Alon, V. Stojanovic, and M. A. Horowitz, "Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 820-828, April 2005.
K. Chang, S. Pamarti, K. Kaviani, E. Alon, X. Shi, T. J. Chin, J. Shen, G. Yip, C. Madden, R. Schmitt, C. Yuan, F. Assaderaghi, and M. Horowitz, "Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor," in 52nd IEEE Intl. Solid-State Circuits Conf. (ISSCC 2005) Digest of Technical Papers, L. C. Fujino, Ed., Vol. 48, Piscataway, NJ: IEEE Press, 2005, pp. 526-527, 615.

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