Source: https://www.scribd.com/document/352154023/adc128s022
Timestamp: 2019-04-23 22:25:04+00:00

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up to eight input signals at inputs IN0 through IN7.
• Medical Instruments 3-V supply and 0.25 µW using a 5-V supply.
temperature range of −40°C to +105°C is ensured.
ti. This voltage is also used as the reference voltage. Supply IN0 to IN7 4-11 Analog I/O Analog inputs. Digital data output.7-V to +5. This clock directly controls the conversion and readout processes. Power DGND 12 The ground return for the digital supply and signals. On the falling edge of CS. ADC128S022 www. The output samples are clocked out of this pin on the falling edges of DOUT 15 Digital I/O the SCLK pin. and Power VD 13 bypassed to GND with a 0. Supply Positive digital supply pin. Digital data input. These signals can range from 0 V to VREF. Chip select.25-V source and bypassed to GND with 1-µF Supply and 0.7-V to VA supply. Copyright © 2005–2015.1-µF monolithic ceramic capacitor located within 1 cm of the Supply power pin. This pin should be connected to a +2.1-µF monolithic ceramic capacitors located within 1 cm of the power pin. Conversions continue CS 1 Digital I/O as long as CS is held low. Digital clock input.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View CS 1 16 SCLK VA 2 15 DOUT AGND 3 14 DIN IN0 4 13 VD ADC128S022 IN1 5 12 DGND IN2 6 11 IN7 IN3 7 10 IN6 IN4 8 9 IN5 Pin Functions PIN TYPE DESCRIPTION NAME NO.8 MHz SCLK 16 Digital I/O to 3. The specified performance range of frequencies for this input is 0. This pin Power VA 2 should be connected to a quiet +2. a conversion process begins. Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC128S022 . Positive analog supply pin. Power AGND 3 The ground return for the analog supply and signals. The ADC128S022's Control Register is loaded through this pin on rising DIN 14 Digital I/O edges of the SCLK pin.2 MHz.
5 V Digital supply voltage VD –0.25 V VD supply voltage 2. θJA is 96°C/W.ti.5 V Voltage on any pin to GND –0. so PDMAX = 1. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. unless otherwise specified. These are stress ratings only. when input or output pins are driven beyond the power supply voltages.3 VA + 0. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.ti.7 VA V Digital input voltage 0 VA V Analog input voltage 0 VA V Clock frequency 50 1600 kHz (1) All voltages are measured with respect to GND = 0V.com and SNOA549 (3) If Military/Aerospace specified devices are required.3 Recommended Operating Conditions (1) See . Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.1 Absolute Maximum Ratings (1) (2) (3) See . MIN MAX UNIT Analog supply voltage VA –0.2 ESD Ratings VALUE UNIT Electrostatic Human body model (HBM).g. (2) For soldering specifications see product folder at www. The values for maximum power dissipation listed above will be reached only when the ADC128S022 is operated in a severe fault condition (e.3 6.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. Note that the power consumption of this device under normal operation is a maximum of 12 mW. the current at that pin should be limited to 10 mA. and the ambient temperature (TA). 4 Submit Documentation Feedback Copyright © 2005–2015.com 6 Specifications 6.3 V Input current at any pin (4) ±10 mA Package input current (4) ±20 mA Power dissipation at TA = 25°C See (5) Junction temperature 150 °C Storage temperature. which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. per ANSI/ESDA/JEDEC JS-001 (1) (2) ±2500 V(ESD) V discharge Machine Model (3) ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Obviously.5-kΩ resistor. In the 16-pin TSSOP. please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.3 6. (5) The absolute maximum junction temperature (TJmax) for this device is 150°C. the junction-to-ambient thermal resistance (θJA). (2) Human body model is 100-pF capacitor discharged through a 1.7 5. Texas Instruments Incorporated Product Folder Links: ADC128S022 . MIN NOM MAX UNIT Operating temperature –40 TA 105 °C VA supply voltage 2.200 mW at 25°C and 625 mW at the maximum operating ambient temperature of 105°C. (3) Machine model is 220 pF discharged through ZERO ohms 6. VIN < AGND or VIN > VA or VD). (4) When the input voltage at any pin exceeds the power supplies (that is. such conditions should always be avoided. or the power supply polarity is reversed). 6. and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The maximum allowable power dissipation is dictated by TJmax.3 to VA + 0.
75 91 dB fIN = 39.05 ±1.02 dBFS VA = VD = 3 V.3 11.8 MHz to 3. −0. 70 73 dB fIN = 39.9 kHz.3 0. Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC128S022 .9 kHz.9 kHz.3 ±1 LSB INL method) VA = VD = 5 V ±0. −0.ti. 70.5 LSB FSEM Full scale error match VA = VD = 5 V ±0.3 11.2 ±1.7 −0. −0.5 ±2 LSB FSE Full scale error VA = VD = 5 V 0.9 kHz.3 LSB VOFF Offset error VA = VD = 5 V 1.9 kHz. 70 73 dB fIN = 39.5 LSB OEM Offset error match VA = VD = 5 V ±0.5 LSB DYNAMIC CONVERTER CHARACTERISTICS VA = VD = 3 V 8 MHz FPBW Full power bandwidth (−3 dB) VA = VD = 5 V 11 MHz VA = VD = 3 V.9 kHz 11.02 dBFS THD Total harmonic distortion VA = VD = 5 V.7 −0.9 kHz. fIN = 39.02 dBFS SFDR Spurious-free dynamic range VA = VD = 5 V. 6.9 kHz.8 73 dB fIN = 39. SPRA953. −0. (1) PARAMETER TEST CONDITIONS MIN TYP MAX (2) UNIT STATIC CONVERTER CHARACTERISTICS Resolution with no missing codes 12 Bits Integral non-linearity (end-point VA = VD = 3 V ±0.02 dBFS SINAD Signal-to-noise plus distortion ratio VA = VD = 5 V. −90 −74 dB fIN = 39. −0.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 6.5 1 LSB VA = VD = 5 V −0. Copyright © 2005–2015.5 LSB VA = VD = 3 V 0.2 ±2.4 ±1 LSB 0.9 kHz. unless otherwise noted.05 ±1.3 LSB VA = VD = 3 V 0.8 73 dB fIN = 39.2 ±1. test.4 Thermal Information ADC128S022 THERMAL METRIC (1) PW (TSSOP) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 110 °C/W RθJC(top) Junction-to-case (top) thermal resistance 42 °C/W RθJB Junction-to-board thermal resistance 56 °C/W ψJT Junction-to-top characterization parameter 5 °C/W ψJB Junction-to-board characterization parameter 55 °C/W (1) For more information about traditional and new thermal metrics.02 dBFS VA = VD = 3 V. −0. fSCLK = 0. fSAMPLE = 50 ksps to 200 ksps.9 kHz.8 ±2.3 LSB VA = VD = 3 V ±0.5 Electrical Characteristics The following specifications apply for AGND = DGND = 0 V.9 LSB VA = VD = 3 V −0.8 Bits ENOB Effective number of bits VA = VD = 5 V. 70. −0. −0.3 ±2 LSB VA = VD = 3 V ±0. (2) Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). fIN = 39. Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. or statistical analysis.02 dBFS 11.2 LSB DNL Differential non-linearity 0.8 Bits (1) Data sheet minimum and maximum specification limits are specified by design. CL = 50 pF. see the Semiconductor and IC Package Thermal Metrics application report. ADC128S022 www. 75 91 dB fIN = 39.02 dBFS SNR Signal-to-noise ratio VA = VD = 5 V.02 dBFS VA = VD = 3 V. −0.02 dBFS VA = VD = 3 V. −89 −74 dB fIN = 39.2 MHz.
Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.5 kHz ANALOG INPUT CHARACTERISTICS VIN Rail-to-rail input 0 VA V IDCL DC leakage current ±1 µA Track mode 33 pF CINA Input capacitance Hold mode 3 pF DIGITAL INPUT CHARACTERISTICS VA = VD = 2.8 V IIN Input current VIN = 0 V or VD ±0.41 1. fb = 20. fSCLK = 0. fb = 20. −88 dB fa = 19.6 V 2.5 kHz. fIN = 20 kHz.5 kHz IMD VA = VD = 3 V. second fa = 19.7 V to 3.5 kHz order terms VA = VD = 5 V. unless otherwise noted.75 V to 5.75 V to 5.5 2.1 mA Total supply current fSAMPLE = 200 ksps.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www.7 V to 5. fb = 20.7 V to 5.(1) PARAMETER TEST CONDITIONS MIN TYP MAX (2) UNIT VA = VD = 3 V. 0. third order fa = 19.7 V to 5. VD Analog and digital supply voltages VA ≥ VD 2.25 V 0.6 V.2 MHz.5 kHz terms VA = VD = 5 V. fIN = 39.25 V 2.06 µW Shutdown mode (CS high) VA = VD = 5 V. fSAMPLE = 200 ksps. fSCLK = 0 ksps 0.2 3. fSAMPLE = 50 ksps to 200 ksps.25 V ISINK = 200 µA to 1 mA.5 kHz. fSCLK = 0 ksps 0.7 5. fSAMPLE = 200 ksps. −97 dB Intermodulation distortion.01 ±1 µA CIND Digital input capacitance 2 4 pF DIGITAL OUTPUT CHARACTERISTICS ISOURCE = 200 µA.5 kHz. fIN = 20 kHz 81 dB ISO Channel-to-channel isolation VA = VD = 5 V. fSCLK = 0 ksps 50 nA VA = VD = 3 V. −0.25 µW 6 Submit Documentation Feedback Copyright © 2005–2015.25 V. fIN = 39.4 V VA = VD = 2.25 V ±1 µA COUT Hi-impedance output capacitance (1) 2 4 pF Output coding Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA.6 V. VOH Output high voltage VD − 0.5 kHz. fIN = 39.5 V VA = VD = 2.com Electrical Characteristics (continued) The following specifications apply for AGND = DGND = 0 V. −94 dB fa = 19. 1. −88 dB Intermodulation distortion.9 kHz VA = VD = +2.5 mW kHz Power consumption VA = VD = 3 V. Total supply current 20 nA fSCLK = 0 ksps Shutdown mode (CS high) VA = VD = 4.4 V VIL Input low voltage VA = VD = 2. fIN = 39. Texas Instruments Incorporated Product Folder Links: ADC128S022 .02 dBFS 80 dB VA = VD = 3 V.25 V.25 V IOZH.7 V to 5.25 V VA = VD = +2.7 V to +3.5 11.75 V to +5.ti. CL = 50 pF.9 kHz Normal mode ( CS low) VA = VD = +4.3 mW Power consumption kHz Normal mode ( CS low) VA = VD = 5 V.1 V VIH Input high voltage VA = VD = 4.9 PC 7.7 V to +3.3 mA IA + ID fSAMPLE = 200 ksps.8 MHz to 3. IOZL Hi-impedance output leakage current VA = VD = 2. fb = 20. VOL Output low voltage 0.9 1.
25 V 13 SCLK cycles 40% 30% DC SCLK duty cycle VA = VD = 2.7 V to 5.4 × tSCLK ns tCL SCLK low time 0.25 V 4 ns 6.8 MHz fSCLK Maximum clock frequency VA = VD = 2. CL = 50 pF.25 V 70% 60% tACQ Acquisition (track) time VA = VD = 2. Power Down Power Up Power Up Track Hold Track Hold CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 SCLK Control register DIN ADD2 ADD1 ADD0 ADD2 ADD1 ADD0 DOUT FOUR ZEROS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FOUR ZEROS DB11 DB10 DB9 Figure 1. and CL = 50 pF.7 V to 5. fSAMPLE = 50 ksps to 200 ksps. or statistical analysis.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 Electrical Characteristics (continued) The following specifications apply for AGND = DGND = 0 V. ADC128S022 www.7 V to 5.25 V 0.9 20 ns (1) Data sheet min/max specification limits are specified by design.2 MHz 50 ksps fS Sample rate continuous mode VA = VD = 2. Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.25 V. Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC128S022 . PARAMETER TEST CONDITIONS MIN NOM MAX (1) UNIT tCSH CS hold time after SCLK rising edge 10 0 ns tCSS CS set-up time prior to SCLK rising edge 10 4.ti.7 V to 5.25 V 1000 200 ksps tCONVERT Conversion (hold) time VA = VD = 2.7 V to 5. fSCLK = 0.2 MHz.7 V to 5.8 MHz to 3.7 V to 5. unless otherwise noted.6 Timing Specifications The following specifications apply for VA = VD = 2. ADC128S022 Operational Timing Diagram Copyright © 2005–2015. test. fSCLK = 0.2 MHz.25 V 16 3.7 V to 5.25 V tAD Aperture delay VA = VD = 2.5 ns tEN CS falling edge to DOUT enabled 5 30 ns tDACC DOUT access time after SCLK falling edge 17 27 ns tDHLD DOUT hold time after SCLK falling edge 4 ns tDS DIN set-up time prior to SCLK rising edge 10 3 ns tDH DIN hold time after SCLK rising edge 10 3 ns tCH SCLK high time 0. AGND = DGND = 0 V.8 MHz to 3.7 V to 5.4 × tSCLK ns DOUT falling 2.4 20 ns tDIS CS rising Edge to DOUT high-impedance DOUT rising 0.25 V 3 SCLK cycles Acquisition time + conversion time Throughput time 16 SCLK cycles VA = VD = 2. fSAMPLE = 50 ksps to 200 ksps.(1) PARAMETER TEST CONDITIONS MIN TYP MAX (2) UNIT AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum clock frequency VA = VD = 2.
SCLK and CS Timing Parameters 8 Submit Documentation Feedback Copyright © 2005–2015.com CS tACQ tCONVERT tCH SCLK 1 2 3 4 5 6 7 8 16 tEN tCL tDACC tDHLD tDIS DOUT FOUR ZEROS DB11 DB10 DB9 DB8 DB1 DB0 tDH tDS DIN DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 2. Texas Instruments Incorporated Product Folder Links: ADC128S022 .ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. ADC128S022 Serial Timing Diagram SCLK tCSS CS tCSH CS Figure 3.ti.
2 MHz.ti. fSAMPLE = 200 ksps. ADC128S022 www.7 Typical Characteristics TA = 25°C. fSCLK = 3. INL vs Supply Copyright © 2005–2015. Figure 4. fIN = 39. INL Figure 8. INL Figure 7. DNL Figure 5.9 kHz unless otherwise stated. Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADC128S022 .com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 6. DNL vs Supply Figure 9. DNL Figure 6.
2 MHz. SNR vs Supply Figure 11. fSAMPLE = 200 ksps. Texas Instruments Incorporated Product Folder Links: ADC128S022 .ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. fIN = 39.ti. DNL vs SCLK Duty Cycle 10 Submit Documentation Feedback Copyright © 2005–2015.com Typical Characteristics (continued) TA = 25°C. Figure 10. THD vs Supply Figure 12. fSCLK = 3. DNL vs VD With VA = 5 V Figure 14. ENOB vs Supply Figure 13. INL vs VD With VA = 5 V Figure 15.9 kHz unless otherwise stated.
9 kHz unless otherwise stated. ADC128S022 www. THD vs SCLK Duty Cycle Figure 19. fIN = 39. INL vs SCLK Duty Cycle Figure 17.ti.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 Typical Characteristics (continued) TA = 25°C. fSAMPLE = 200 ksps. ENOB vs SCLK Duty Cycle Figure 20.2 MHz. fSCLK = 3. SNR vs SCLK Duty Cycle Figure 18. INL vs SCLK Copyright © 2005–2015. DNL vs SCLK Figure 21. Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC128S022 . Figure 16.
com Typical Characteristics (continued) TA = 25°C.9 kHz unless otherwise stated. fSCLK = 3. DNL vs Temperature Figure 26. INL vs Temperature Figure 27. Texas Instruments Incorporated Product Folder Links: ADC128S022 .2 MHz. SNR vs Temperature 12 Submit Documentation Feedback Copyright © 2005–2015. THD vs SCLK Figure 24. SNR vs SCLK Figure 23. fSAMPLE = 200 ksps.ti. fIN = 39. Figure 22. ENOB vs SCLK Figure 25.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www.
Power Consumption vs SCLK Copyright © 2005–2015. fIN = 39. fSAMPLE = 200 ksps. ENOB vs Input Frequency Figure 33.2 MHz. SNR vs Input Frequency Figure 31.ti.9 kHz unless otherwise stated.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 Typical Characteristics (continued) TA = 25°C. THD vs Input Frequency Figure 32. Figure 28. Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: ADC128S022 . fSCLK = 3. ADC128S022 www. THD vs Temperature Figure 29. ENOB vs Temperature Figure 30.
The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. The ADC128S022 is in this state for the last thirteen SCLK cycles after CS is brought low. C AGND VA /2 Figure 34.1 Overview The ADC128S022 is a successive-approximation analog-to-digital converter designed around a charge- redistribution digital-to-analog converter. and SW2 balances the comparator inputs. maintaining the sampled voltage.ti. ADC128S022 in Track Mode IN0 CHARGE REDISTRIBUTION DAC MUX SAMPLING CAPACITOR IN7 SW1 + CONTROL LOGIC SW2 - AGND VA /2 Figure 35. The ADC128S022 is in this state for the first three SCLK cycles after CS is brought low. Figure 35 shows the ADC128S022 in hold mode: switch SW1 connects the sampling capacitor to ground. In Figure 34. the ADC128S022 is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer. ADC128S022 in Hold Mode 14 Submit Documentation Feedback Copyright © 2005–2015. Texas Instruments Incorporated Product Folder Links: ADC128S022 .com 7 Detailed Description 7. IN0 CHARGE REDISTRIBUTION DAC MUX SAMPLING CAPACITOR SW1 + CONTRO IN7 L LOGI SW2 . the digital word supplied to the DAC is the digital representation of the analog input voltage. When the comparator is balanced. Simplified schematics of the ADC128S022 in both track and hold operation are shown in Figure 34 and Figure 35 respectively.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. and switch SW2 unbalances the comparator.
Data to be written to the ADC128S022's Control Register is placed on DIN. Each frame must contain an integer multiple of 16 rising SCLK edges. SCLK is internally gated off when CS is brought high. and Table 3. chip select. The LSB width for the ADC128S022 is VA / 4096.3 Feature Description 7. the serial data input pin.2 ADC128S022 Transfer Function The output format of the ADC128S022 is straight binary. Other code transitions occur at steps of one LSB. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out. Similarly. If there is more than one conversion in a frame (continuous conversion mode).2 Functional Block Diagram IN0 . Under this condition. MSB first. In Figure 1. DOUT is the serial data output pin. MUX T/H APPROXIMATION . Table 2. where a conversion result is sent as a serial data stream. see Figure 3 for set-up and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. New data is written to DIN with each conversion. While a conversion is in progress. Code transitions occur midway between successive integer LSB values. initiates conversions and frames the serial data transfers. SCLK falling edges 1 through 4 clock out leading zeros while falling edges 5 through 16 clock out the conversion result. CS goes low with SCLK high and the ADC enters track mode on the first falling edge of SCLK. The ADC128S022 enters track mode under three different conditions.3. MSB first. 7. In the second condition. the address of the next input for conversion is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. the ADC is in the track mode.3. The ADC's DOUT pin is in a high impedance state when CS is high and is active when CS is low. CS. SCLK (serial clock) controls both the conversion process and the timing of serial data. the ADC automatically enters track mode and the falling edge of CS is seen as the first falling edge of SCLK. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. In the third condition. Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: ADC128S022 . While there is no timing restriction with respect to the rising edges of CS and SCLK. ADC128S022 www. acquiring the input voltage.ti.1 Serial Interface An operational timing diagram and a serial interface timing diagram for the ADC128S022 are shown in the Specifications section. CS goes low with SCLK low. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB. CS acts as an output enable. Copyright © 2005–2015. The ideal transfer characteristic is shown in Figure 36. ADC AGND IN7 AGND VD SCLK ADC128S022 CS CONTROL LOGIC DIN DOUT DGND 7. The first conversion result after power up will be that of IN0. the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK. See Table 1. 12-BIT VA SUCCESSIVE . During the first 3 cycles of SCLK. There is no need to incorporate a power-up delay or dummy conversion as the ADC128S022 is able to acquire the input signal to full resolution in the first conversion immediately following power up. Thus.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 7. CS and SCLK go low simultaneously and the ADC enters track mode. or a voltage of VA / 8192. "N" is an integer value.
4 Device Functional Modes The ADC128S022 is fully powered-up whenever CS is low and fully powered-down whenever CS is high.110 ADC CODE 111.000 | | 1LSB = VA/4096 011. Resistor R1 is the ON-resistance of the multiplexer and track / hold switch and is typically 500 Ω.1.com Feature Description (continued) 111.5LSB ANALOG INPUT Figure 36..ti. The operating range for the analog inputs is 0 V to VA. Equivalent Input Circuit 7.010 000.. The digital output (DOUT) operating range is controlled by VD. The capacitor C1 in Figure 37 has a typical value of 3 pF and is mainly the package pin capacitance.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www..3 V to VA. 7. Going beyond this range will cause the ESD diodes to conduct and result in erratic operation.111 111. The output high voltage is VD – 0. Texas Instruments Incorporated Product Folder Links: ADC128S022 .. and DIN) have an operating range of –0..4 Digital Inputs and Outputs The digital inputs of the ADC128S022 (SCLK. 16 Submit Documentation Feedback Copyright © 2005–2015.Switch Closed Figure 37. Diodes D1 and D2 provide ESD protection for the analog inputs...111 000. Capacitor C2 is the ADC128S022 sampling capacitor.4 V (maximum).3.3 Analog Inputs An equivalent circuit for one of the input channels of the ADC128S022 is shown in Figure 37..001 | 000. This is especially important when using the ADC128S022 to sample dynamic signals. They are not prone to latch-up and may be asserted before the digital supply (VD) without any risk.5V (minimum) while the output low voltage is 0.000 0V 0.3. CS. the ADC128S022 automatically enters power-down mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent conversion (see Figure 1). Also important when sampling dynamic signals is a bandpass or lowpass filter which reduces harmonics and noise in the input.Switch Open Track Phase .. These filters are often referred to as anti-aliasing filters.. and is typically 30 pF.5LSB +VA .... If operating in continuous conversion mode. with one exception. Ideal Transfer Characteristic 7. The ADC128S022 will deliver best performance when driven by a low-impedance source (less than 100 Ω).. VA D1 C2 R1 30 pF VIN C1 3 pF D2 Conversion Phase .
This means spending more time in power-down mode and less time in normal mode. Each conversion requires 16 SCLK cycles and the ADC128S022 will perform conversions continuously as long as CS is held low. The Power Consumption vs SCLK curve in the Typical Characteristics section shows the typical power consumption of the ADC128S022. the user can achieve very low sample rates while still using an SCLK frequency within the electrical specifications. 6. 3 ADD0 Table 3. tN tS PC = x PN + x PS tN + t S tN + t S (1) 7. and add the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Equation 1. Continuous mode offers maximum throughput. Control Register Bit Descriptions BIT #: SYMBOL: DESCRIPTION 7. Input Channel Selection ADD2 ADD1 ADD0 INPUT CHANNEL 0 0 0 IN0 (Default) 0 0 1 IN1 0 1 0 IN2 0 1 1 IN3 1 0 0 IN4 1 0 1 IN5 1 1 0 IN6 1 1 1 IN7 Copyright © 2005–2015. simply multiply the fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN).5 Register Maps Table 1. By using this technique. 2. In burst mode. To calculate the power consumption (PC). The mapping between codes and channels is shown in Table 3. Control Register Bits Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Table 2. ADC128S022 www. The values of these bits do not affect the device. the ADC128S022 can perform multiple conversions back to back.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 Device Functional Modes (continued) In continuous conversion mode. Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: ADC128S022 .ti. 1. 0 DONTC Don't care. the user may trade off throughput for power consumption by performing fewer conversions per unit time. 5 ADD2 These three bits determine which input channel will be sampled and converted at the next 4 ADD1 conversion cycle.
the ADC128S022 is suitable for monitoring AC waveforms as well as DC inputs. BW = 10 kHz. The ADC128S022 uses the analog supply (VA) as its reference voltage. 18 Submit Documentation Feedback Copyright © 2005–2015. the ADC128S022 can operate at sampling rates up to 200 kSPS.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification. Because the ADC128S022 integrates an 8 to 1 MUX on the front end.3-V supply. In addition to having 8 input channels. the ADC128S022 is typically run in burst fashion where a voltage is sampled for several times and then the ADC128S022 can be powered down. Typical Application Circuit 8. TI’s customers are responsible for determining suitability of components for their purposes.1uF 1uF High Impedance V VD VDD + 100 100 Source A GPIOa LMV612 IN7 SCLK 100 33n CS GPIOb 100 MCU IN3 ADC128S022 DOUT GPIOc Schottky 100 Diode DIN GPIOd (optional) Low 100 GND Impedance IN0 Source AGN DGN 33n D D Figure 38.1 Design Requirements A positive supply only data acquisition system capable of digitizing signals ranging 0 to 5 V. This follows from the fact that VA is also a reference potential for the ADC. 8. and TI does not warrant its accuracy or completeness.2. Customers should validate and test their design implementation to confirm system functionality. it is also possible to use a precision reference as a power supply. The analog supply is bypassed with a capacitor network located close to the ADC128S022. and a throughput of 125 kSPS.ti. The ADC128S022 has to interface to an MCU whose supply is set at 3.2. so it is very important that VA be kept as clean as possible. Due to the high bandwidth and sampling rate. 5V 3. The requirement of interfacing to the MCU which is powered by 3. As a result.1 Application Information The ADC128S022 is a successive-approximation analog-to-digital converter designed around a charge- redistribution digital-to-analog converter. This is a common technique for applications that are power limited.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. A typical application is shown in Figure 38.1uF 0. the device is typically used in applications where multiple voltages need to be monitored. 8. forces the choice of 3. Texas Instruments Incorporated Product Folder Links: ADC128S022 .2 Typical Application The following sections outline the design principles of data acquisition system based on the ADC128S022.3-V as a VD supply. Due to the low power requirements of the ADC128S022.3V 1uF 0. analog supply.2 Detailed Design Procedure The signal range requirement forces the design to use 5-V analog supply at VA. 8. The following example shows a common configuration for monitoring AC inputs.3 V.
but it also absorbs the charge kick-back from the ADC. especially when the master MCU is capable of producing fast rising edges on the digital bus signals. Typical Performance Copyright © 2005–2015. 8. This also benefits the overall performance of the ADC.3 Application Curve Figure 39. further consideration could be given to the SPI interface. the Nyquist criterion has to be met by Equation 4: Fs BW signal £ 2 (4) Therefore it is necessary to place anti-aliasing filters at all inputs of the ADC. These filters may be single-pole lowpass filters whose pole location has to satisfy.2. The maximum sampling rate of the ADC128S022 when all channels are enabled is. ADC128S022 www. assuming all channels sampled in sequence of Equation 5 and Equation 6: 1 FSCLK £ p ´ R ´ C 16 ´ 8 (5) 128 R´C ³ p ´ FSCLK (6) With Fsclk = 16 MHz. The ESD diodes are not intended as input signal clamps. In the same vain. Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: ADC128S022 . and thus improve the overall noise performance of the system. Take care when the signal source is capable of producing voltages beyond VA. In such instances the internal ESD diodes may start conducting. The VA and VD sources are already separated in this example.ti.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 Typical Application (continued) Sampling is in fact a modulation process which may result in aliasing of the input signal. if the input signal is not adequately band limited. To provide the desired clamping action use Schottky diodes as shown in Figure 38. Inserting small resistances in the digital signal path may help in reducing the ground bounce. as the potentially noisy VD supply does not contaminate the VA. The capacitor at the INx input of the device provides not only the filtering of the input signal. Single channel can be sampled at the maximum rate of Equation 3: FSCLK Fs _ sin gle = 16 (3) In order to avoid the aliasing. a good choice for the single-pole filter is: • R = 100 • C = 33 nF This reduces the input BWsignal = 48 kHz. Fs is calculated by Equation 2: FSCLK Fs = 16 ´ 8 (2) Note that faster sampling rates can be achieved when fewer channels are sampled. due to the design requirements. The kick-back is the result of the internal switches opening at the end of the acquisition period.
Load discharge currents will cause ground bounce noise in the substrate that will degrade noise performance if that current is large enough.ti. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. power management. 9. the digital supply (VD) cannot exceed the analog supply (VA) by more than 300 mV. Similarly. not even on a transient basis. Furthermore. The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies from each other or use separate supplies for them. which is resistive. The two supply pins share ESD resources. causing greater performance degradation than would noise on the digital supply alone. located as close to the ADC output pin as practical. 9.com 9 Power Supply Recommendations There are three major power supply concerns with this product: power supply sequencing. If these variations are large enough. VD. Therefore. If the load capacitance is greater than 50 pF. 20 Submit Documentation Feedback Copyright © 2005–2015.2 Power Supply Noise Considerations The charging of any output load capacitance requires current from the digital supply. verify the signal integrity once the series resistor has been added. This will limit the charge and discharge current of the output capacitance and improve noise performance. discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate. use a 100-Ω series resistor at the ADC output. the more current flows through the die substrate and the greater the noise coupled into the analog channel.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. To avoid turning on the ESD diodes. The larger the output capacitance. Texas Instruments Incorporated Product Folder Links: ADC128S022 . To keep noise out of the digital supply. Because the series resistor and the load capacitor form a low-frequency pole.1 Power Supply Sequence The ADC128S022 is a dual-supply device. and the effect of digital supply noise on the analog supply. if the analog and digital supplies are tied directly together. they could degrade SNR and SINAD performance of the ADC. VA must ramp up before or concurrently with VD. so take care to ensure that the power is applied in the correct sequence. keep the output load capacitance as small as practical. the noise on the digital supply will be coupled directly into the analog supply.
all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the analog ground plane at a single. Any external component (for example. All analog circuitry (input amplifiers. a filter capacitor) connected between the input pins and ground of the converter or to the reference input pin and ground should be connected to a very clean point in the ground plane. Layout Schematic Copyright © 2005–2015. In addition. However. TI recommends the use of a single. Digital circuits create substantial supply and ground current transients.ti. quiet point. uniform ground plane and the use of split power planes.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 10 Layout 10. The power planes should be located within the same board layer. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. ADC128S022 www. the clock line should also be treated as a transmission line and be properly terminated. It is important to keep clock lines as short as possible and isolated from ALL other lines. reference components. avoid crossing analog and digital lines altogether. To avoid performance degradation of the ADC128S022 due to supply noise.1 Layout Guidelines Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. do not use the same supply for the ADC128S022 that is used for digital logic.2 Layout Example ANALOG SUPPLY RAIL CS SCLK VA DOUT toMCU AGND DIN IN0 VD “DIGITAL” SUPPLY RAIL IN1 DGND IN2 IN7 IN3 IN6 to analog IN4 IN5 signal sources VIA to GROUND PLANE GROUND PLANE Figure 40. Furthermore. including other digital lines. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. to maximize accuracy in high resolution systems. analog and digital lines should cross each other at 90° to avoid crosstalk. Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: ADC128S022 . 10. and so forth) should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital power plane. filters. The logic noise generated could have significant impact upon system noise performance. Generally.
or the harmonics included in THD.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. EFFECTIVE NUMBER OF BITS (ENOB.5 LSB – VREF+ (7) where Vmax is the voltage at which the transition to the maximum code occurs.1. The deviation of any given code from this straight line is measured from the center of that code value.1. The ADC128S022 is ensured not to have any missing codes. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period.5 LSB).e. LSB or percent of full scale range... It is defined as the ratio of the power in both the second and the third order intermodulation products to the power in one of the original frequencies.1. ENOB is defined as (SINAD . GAIN ERROR is the deviation of the last code transition (111. of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency..1.76) / 6.5 LSB). after adjusting for offset error.1 Device Nomenclature 11. During this time. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to an individual ADC input at the same time..1 Device Support 11. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition).ti. FSE can be expressed in Volts. Third order products are (2fa ± fb ) and (fa ± 2fb). DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. MISSING CODES are those output codes that will never appear at the ADC outputs.001) from the ideal (i.ADC128S022 SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 www. IMD is usually expressed in dB.c. APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion. CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another channel CROSSTALK is the coupling of energy from one channel into another channel.. Second order products are fa ± fb. GND + 0. or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. where fa and fb are the two sine wave input frequencies. These codes cannot be reached with any input value. OFFSET ERROR is the deviation of the first code transition (000. CONVERSION TIME is the time required. The specification here refers to the SCLK. the hold capacitor is charged by the input voltage. SIGNAL TO NOISE RATIO (SNR) is the ratio. expressed in dB. not including d. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.000) to (000..com 11 Device and Documentation Support 11.. Texas Instruments Incorporated Product Folder Links: ADC128S022 . for the ADC to convert the input voltage to a digital word.111) from the ideal (VREF . after the input voltage is acquired. 22 Submit Documentation Feedback Copyright © 2005–2015. This is similar to Channel-to- Channel Isolation.110) to (111. FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below VREF+ and is defined as: VFSE = Vmax + 1. except for the sign of the data.1..1 Specification Definitions ACQUISITION TIME is the time required for the ADC to acquire the input voltage.
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Addendum-Page 2 .ti.com 10-Sep-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.
95 5.0 12.4 6.6 1.6 8. PACKAGE MATERIALS INFORMATION www.0 Q1 B Pack Materials-Page 1 .ti.0 12.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) ADC128S022CIMTX/NOP TSSOP PW 16 2500 330.
0 367.0 B Pack Materials-Page 2 .com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC128S022CIMTX/NOP TSSOP PW 16 2500 367.ti.0 35. PACKAGE MATERIALS INFORMATION www.
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