Source: https://patents.google.com/patent/EP1653373A2/en
Timestamp: 2019-04-18 20:38:41+00:00

Document:
A bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link. The first interface and the second interface are operable to: a) send information serially through the link in a format different from that of the first bus and the second bus; b) approve an initial exchange between the first bus and the second bus in response to pending transactions having a characteristic signifying a destination across the bridge; c) exchange information between the first bus and the second bus according to a predetermined hierarchy giving the first bus a higher level than the second bus; and d) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus.
The present invention relates to data processing systems, and more particularly, to bridge systems including mechanisms for transferring information between buses.
In accordance with the illustrative embodiments demonstrating features and advantages of the present invention, there is provided a bridge accessible by a host processor for expanding access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is adapted to couple between the first bus and the link. The second interface is adapted to couple between the second bus and the link. The first interface and the second interface operating as a single bridge are operable to (a) send outgoing information serially through the link in a format different from that of the first bus and the second bus without waiting for an incoming acknowledgement over said link before inaugurating a transfer of said information over said link, (b) approve an initial exchange between the first bus and the second bus in response to a pending transaction having a characteristic signifying a destination across the bridge, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus, including memory devices and input/output devices that may be present: (i) using on the first bus substantially the same type of addressing as is used to access devices the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.
In accordance with another aspect of the invention a bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus each are adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is adapted to couple between the first bus and the link. The second interface is adapted to couple between the second bus and the link. The first interface and the second interface are operable to (a) send information serially through the link in a format different from that of the first bus and the second bus, (b) exchange information between the first bus and the second bus according to a predetermined hierarchy giving the first bus a higher level than the second bus, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus, including memory devices and input/output devices that may be present: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus, and (iii) without passing the information through an intervening hierarchical level.
In accordance with another, further aspect of the invention a bridge accessible by a processor can expand access over a first bus to a second bus. The first bus and the second bus each are adapted to separately connect to respective ones of a plurality of bus-compatible devices. The bridge has a link and a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is adapted to couple between the second bus and the link. The first interface and the second interface operate as a single bridge and is operable to transfer information serially through the link in a format different from that of the first bus and the second bus without waiting for an incoming acknowledgment over the link before inaugurating a transfer of the information over the link.
Buses 10 and 12 are shown connecting to a first interface 14 and second interface 16, respectively (also referred to as interfaces 14 and 16). Bus information selected for transmission by interfaces 14 and 16 are loaded into registers 18 and 20, respectively. Incoming bus information that interfaces 14 and 16 select for submission to the buses are taken from registers 22 and 24, respectively. In one embodiment, registers 18-24 are each 16 X 38 FIFO registers, although different types of registers having different dimensions may be used in alternate embodiments.
Each of these five bytes is converted into a 10 bit frame that can carry the information of each byte, as well as information useful for regulating the link. For example, these frames can carry comma markers, idle markers, or flow control signals, in a well-known fashion. A transceiver system working with bytes that were encoded into such 10 bit frames is sold commercially by Hewlett Packard as model number HDMP-1 636 or -1646. Frames produced by encoder 28 are forwarded through transmitter 44 along simplex link 46 to receiver 48, which supplies the serial information to decoder 30. Likewise, encoder 26 forwards serial information through transmitter 38 along simplex link 40 to receiver 42, which supplies the serial information to decoder 32.
ASIC 58 is also shown connected to previously mentioned secondary bus 12. Bus 12 is shown connected to an adapter card 96 to allow the PCI bus 12 to communicate with an IDE device such as a hard drive, backup tape drive, CD-ROM drive, etc. Another adapter card 98 is shown for allowing communications from bus 12 to a universal serial port (USB). A network interface card 100 will allow communications through bus 12 to various networks operating under the Ethernet standard, Token Ring standard, etc. Video adapter card 102 (also referred to as a video means) allows the user to operate another monitor. Add-on card 104 may be one of a variety of cards selected by the user to perform a useful function. While this embodiment shows various functions being implemented by add-on cards, other embodiments may implement one or more of these function on a common circuit board in the dock (e.g., all functions excluding perhaps the IDE adapter card).
ASIC 58 communicates through receiver/transmitter 106, which provides a physical interface through a terminal connector 108 to cable 40, 46. Connector 108 may be a 20 pin connector capable of carrying high speed signals with EMI shielding (for example a low force helix connector of the type offered by Molex Incorporated), although other connector types may used instead. The opposite end of cable 40, 46 connects through a gigabit, terminal connector 110 to physical interface 112, which acts as a receiver/transmitter. Interface 112 is shown connected to previously mentioned first ASIC 56, which is also shown connected to an oscillator 114 to establish a local clock signal. This specific design contemplates using an external transmitter/receiver (external SERDES of lines 27, 29, 31, and 33 of Figure 1), although other embodiments can eliminate these external devices in favor of the internal devices in ASIC's 56 and 58.
Referring to Figure 6, a modified portable computer 126' is again shown with a host processor 128 and primary bus 10. In this embodiment however, portable computer 126' contains previously mentioned ASIC 56. Thus there is no circuitry required (other than perhaps drivers) between ASIC 56 and cable 40,46. In this case, the laptop end of cable 40, 46 has a connector 142 similar to the one on the opposite end of the cable (connector 108 of Figure 5). Connector 143 is designed to mate with connector 141 and support the highspeed link. As before, connectors 141 and 143 can also carry various power management signals, and other signals associated with a docking system.
Next, interface 16 will drive the write data stacked on register 24 into bus 12. If this transaction is a burst, interface 16 will continue to drive data onto bus 1 2 by fetching it from register 24. If however this transaction is a single cycle write, interface 16 will close the transaction on bus 12 and load an acknowledgment into register 20. Since this acknowledgment need not carry data or address information, a unique code may be placed into register 20, so that encoder 28 can appropriately tag this line before parsing it into frames for transmission over link 46. Upon receipt, decoder 30 will produce a unique code that is loaded into register 22 and eventually forwarded to interface 14, which sends an acknowledgment to the device on bus 10 that the write has succeeded.
If the initiator instead sets its control bits during the address cycle to indicate a read request, interface 14 would also accept this cycle, if it has jurisdiction. Interface 14 will also signal the initiator on bus 10 that it is not ready to return data (e.g., a retry signal, which may be the stop signal as defined under the PCI standard). The initiator can still start (but not finish) a data cycle by driving its signaling lines on bus 10 with byte enable information. Using the same technique, the address information, followed by the byte enable information, will be accepted by interface 14 and loaded with tags into register 18. These two lines of information will be then encoded and transmitted serially over link 40. Upon receipt, this information will be loaded into the stack of register 24. Eventually, interface 16 will notice the first item as a read request and drive this address information onto secondary bus 12. A device on bus 12 will respond and perform the appropriate handshaking. Interface 16 will then forward the next item of information from register 24 containing the byte enables, onto bus 12 so the target device can respond with the requested data. This responsive data is loaded by interface 16 into register 20. If pre-fetching is indicated, interface 16 will initiate a number of successive read cycles to accumulate data in register 20 from sequential addresses that may or may not be requested by the initiator.
Eventually the initiator will relinquish control of bus 10. Next, an initiator on bus 12 may send a request for control of bus 1 2 to arbiter 70 (Figure 2). If arbiter 70 grants control, the initiator may make a read or write request by driving an address onto bus 12. Interface 16 will respond if this address does not fall within the jurisdictional range of addresses specified in configuration register 67 (indicating the higher level bus 10 may have jurisdiction). In the same manner as before, but with a reversed flow over links 40, 46, interface 16 may accept address and data cycles and communicate them across link 40, 46. Before being granted bus 10, interface 14 will send a request to an arbiter (not shown) associated with bus 10.
§1. A bridge accessible by a processor for expanding access over a first bus to a second bus, said first bus and said second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, said bridge comprising: a link ; a first interface adapted to couple between said first bus and said link ; and a second interface adapted to couple between said second bus and said link, said first interface and said second interface operating as a single bridge and being operable to transfer information serially through said link in a format different from that of said first bus and said second bus without waiting for an incoming acknowledgment over said link before inaugurating a transfer of said information over said link.
§2. A bridge according to §1 wherein said allowable ones of said buscompatible devices include memory devices and input/output devices, said first interface and said second interface being operable to (a) approve an initial exchange between said first bus and said second bus in response to pending bus transactions having a characteristic signifying a destination across said bridge, and (b) allow said host processor, communicating through said first bus, to individually address different selectable ones of the bus-compatible devices on said second bus, including memory devices and input/output devices that may be present: (i) using on said first bus substantially the same type of addressing as is used to access devices on said first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on said second bus.
§3. A bridge according to §1 wherein said first interface and said second interface are operable to exchange information between said first bus and said second bus according to a predetermined hierarchy giving said first bus a higher level than said second bus.
§4. A bridge according to §1 wherein said first interface and said second interface are operable to (a) exchange information between said first bus and said second bus according to a predetermined hierarchy giving said first bus a higher level than said second bus, and (b) allow said host processor, communicating through said first bus, to individually address different selectable ones of the bus-compatible devices on said second bus, including memory devices and input/output devices that may be present: (i) using on said first bus substantially the same type of addressing as is used to access devices said first bus, (ii) without first employing a second, intervening one of the bus-compatible devices on said second bus, and (iii) without passing the information through an intervening hierarchical level.
§5. A bridge according to §1,2, or 4 wherein said first bus and said second bus each have a plurality of signaling lines for enabling bus-compatible devices to negotiate bus communications, said first interface being operable in response to a pending transaction on said first bus to begin processing said pending transaction and to apply a retry signal to at least one of said signaling lines of said first bus before the pending transaction on said first bus has been transmitted to and acknowledged by said second bus.
§6. A bridge according to §1 wherein less than all of the information on the signaling lines of said first bus is transmitted by said first interface over said link.
§7. A bridge according to §1,2, or 4 wherein said first interface is selectively responsive to those addresses appearing on said first bus that are on a predetermined schedule of addresses corresponding to the bus-compatible devices accessible through said second bus, in order to avoid responding to addresses corresponding to other ones of the bus-compatible devices on said first bus.
§8. A bridge according to §7 comprising: a register for storing said predetermined schedule.
§9. A bridge according to §7 wherein said first interface comprises: a first register for storing said predetermined schedule, said second interface comprising : a second register for storing said predetermined schedule.
§10. A bridge according to §8 wherein said register is operable to establish with respect to said first bus a base address for one or more of the bus-compatible devices on said second bus.
§11. A bridge according to §1,2, or 4 comprising: a register for establishing with respect to said first bus a base address for one or more of the bus-compatible devices on said second bus.
§12. A bridge according to §1,2, or 4 wherein said first interface and said second interface are operable to permit communication between buscompatible devices on said second bus without routing through said first bus.
§13. A bridge according to §12 comprising: an arbiter with authority to grant the second bus and without authority to grant the first bus to either said second interface or one of the buscompatible devices on said second bus.
§14. A bridge according to §1,2, or 4 wherein said first interface and said second interface comprise: a first and a second programmable logic device connected between said link and said first bus and said second bus, respectively.
§15. A bridge according to §1,2, or 4 wherein said first interface and said second interface comprise: a first and a second application-specific integrated circuit connected between said link and said first bus and said second bus, respectively.
§16. A bridge according to §15 wherein said first and said second application-specific integrated circuit are identically structured and each have a control pin for receiving a control signal to establish operation in one of two modes.
§17. A bridge according to §16 wherein said first and said second application-specific integrated circuit each comprise: an arbiter, enabled only in said second application-specific integrated circuit, with authority to grant the second bus and without authority to grant the first bus to either said second interface or one of the bus-compatible devices on said second bus.
§18. A bridge according to §15 wherein said first and said second application-specific integrated circuit each comprise: a plurality of port means coupled to said second interface for providing a plurality of ports for input/output.
§19. A bridge according to §1,2, or 4 wherein said host processor is interrupt-driven, said second interface being operable to transmit through said link to said first interface interrupt signals destined to interrupt the host processor.
§20. A bridge according to §19 wherein said host processor is responsive to error signals, said second interface being operable to transmit through said link to said first interface error signals destined to affect the host processor.
§21. A bridge according to §1,2, or 4 wherein said first bus operates at a predetermined clock speed, said link being operable to propagate data between said first interface and said second interface at a bit transfer rate greater than said predetermined clock speed.
§22. A bridge according to §21 wherein said link comprises: a pair of simplex links for sending information in opposite directions.
§23. A bridge according to §22 wherein said simplex links are driven for differential signal transfers.
§24. A bridge according to §1,2, or 4 wherein said second bus comprises a PCI bus.
§25. A bridge according to §1,2, or 4 wherein said second interface is operable in response to a transaction from said link signifying an initial read request, to fetch and pre-fetch data from a competent one of the buscompatible devices on said second bus for transmission back over said link in order to satisfy pending and anticipated transactions.
§26. A bridge according to §1,2, or 4 wherein said first interface and said second interface are operable to permit at least one of the buscompatible devices on said second bus to address one or more of the buscompatible devices on said first bus using on said second bus substantially the same type of addressing as is used to access devices on said second bus.
characterized in that during a transaction the information provided to the first interface is tagged with data indicative of the transaction type and the information is transferred from the first interface to the second interface without waiting for an incoming acknowledgement from the second interface before inaugurating a transfer of said information over said link.
The bridge according to claim 1 wherein the first interface and the second interface each comprise a register, wherein the information provided to the first interface is loaded into the first register and mirrored to the second register.
A bridge according to claim 1 wherein said allowable ones of said bus-compatible devices (64, 66) include memory devices and input/output devices, said first interface (14) and said second interface (16) being operable to (a) approve an initial exchange between said first bus (10) and said second bus, (12) in response to pending bus transactions having a characteristic signifying a destination across said bridge, and (b) allow communications to be addressed individually through said first bus, to different selectable ones of the bus-compatible devices on said second bus, including memory devices and input/output devices that may be present: (i) using on said first bus substantially the same type of addressing as is used to access devices on said first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on said second bus.
A bridge according to claim 1 wherein said first interface (14) and said second interface (16) are operable to exchange information between said first bus (10) and said second bus (12) according to a predetermined hierarchy giving said first bus a higher level than said second bus.
A bridge according to claim 1 wherein said first interface (14) and said second interface (16) are operable to (a) exchange information between said first bus (10) and said second bus (12) according to a predetermined hierarchy giving said first bus a higher level than said second bus, and (b) allow communications to be addressed individually through said first bus, to different selectable ones of the bus-compatible devices (66) on said second bus, including memory devices and input/output devices that may be present: (i) using on said first bus substantially the same type of addressing as is used to access devices on said first bus, (ii) without first employing a second, intervening one of the bus-compatible devices (66) on said second bus, and (iii) without passing the information through an intervening hierarchical level.
A bridge according to claim 1, 3 or 5 wherein said first bus (10) and said second bus (12) each have a plurality of signalling lines for enabling bus-compatible devices to negotiate bus communications, said first interface (14) being operable in response to a pending transaction on said first bus to begin processing said pending transaction and to apply a retry signal to at least one of said signalling lines of said first bus before the pending transaction on said first bus has been transmitted to and acknowledged by said second bus.
A bridge according to claim 1 wherein less than all of the information on the signalling lines of said first bus (10) is transmitted by said first interface (14) over said link (40, 46).
A bridge according to claim 1, 3 or 5 wherein said first interface (14) is selectively responsive to those addresses appearing on said first bus (10) that are on a predetermined schedule of addresses corresponding to the bus-compatible devices (66) accessible through said second bus (12), in order to avoid responding to addresses corresponding to other ones of the bus-compatible devices (64) on said first bus (10).
A bridge according to claim 9 wherein said register (68) is operable to establish with respect to said first bus (10) a base address for one or more of the bus-compatible devices (66) on said second bus (12).
a register (68) for establishing with respect to said first bus (10) a base address for one or more of the, bus-compatible devices (06) on said second bus (12).
A bridge according to claim 1, 3 or 5 wherein said first interface (14) and said second interface (16) are operable to permit communication between bus-compatible devices (66) on said second bus (12) without routing through said first bus (10).
an arbiter (70) with authority to grant the second bus (12) and without authority to grant the first bus (10) to either said second interface (16) or one of the bus-compatible devices (66) on said second bus (12).
A bridge according to claim 16 wherein said first (56) and said second (58) application-specific integrated circuit are identically structured and each have a control pin (74, 76) for receiving a control signal to establish operation in one of two modes.
an arbiter (70, 72), enabled only in said second (56) application-specific integrated circuit, with authority to grant the second bus (12) and without authority to grant the first bus (10) to either said second, interface, (16) or one of the bus-compatible devices (66) on said second bus (12).
a plurality of port means (80, 82, 84,.86) coupled to said second interface (16) for providing a plurality of ports for input/output.
A bridge according to claim 1, 3 or 5 wherein said second interface (16) is operable to transmit through said link (40, 46) to said first interface (14) interrupt signals destined to interrupt an interrupt-driven host processor.
A bridge according to claim 20 wherein said second interface (16) is operable to transmit through said link (40, 46) to said first interface (14) error signals destined to affect an error responsive host processor.
A bridge according to claim 1, 3 or 5 wherein said first bus (110) operates at a predetermined clock speed, said link (40, 46) being operable to propagate data between said first interface (14) and said second interface (16) at a bit transfer rate greater than said predetermined clock speed.
a pair of complex links (40, 46) for sending information in opposite directions.
A bridge according to claim 23 wherein said simplex links (40, 46) are driven for differential signal transfers.
A bridge according to claim 1, 3 or 5 wherein said second bus (12) 10 comprises a PCI bus.
A bridge according to claim 1, 3 or 5 wherein said second interface (16) is operable in response, to a transaction from said link (40, 46) signifying an initial read request, to fetch and pre-fetch data from a competent one of the bus-compatible devices (66) on said second bus (12) for transmission back over said link in order to satisfy pending and anticipated transactions.
A bridge according to claim 1, 3 or 5 wherein said first interface (14) and said second interface (16) are operable to permit at least one of the bus-compatible devices (66)on said second bus (12) to address one or more of the bus-compatible devices (64) on said first bus (10) using on said second bus substantially the same type of addressing as is used to access devices on said second bus.
A bridge according to claim 1 wherein said first and, second interfaces operate as a single bridge.

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