Source: http://web.eng.gla.ac.uk/groups/devmod/index.php/people/dr-fikru-adamu-lema/
Timestamp: 2019-04-20 06:31:59+00:00

Document:
My main research interest includess, among other things, development of oxide reliability model, and statistical simulation of nano-scale conventional CMOS and non-conventional like silicon on insulator (SOI) and FinFETs. Looking back about 3 decades, the advantages of device miniaturization (mainly cost and performance) outweighs the challenges to fabricate them (for example technological challenges). The end of this successful run of aggressive scaling of CMOS devices is fast approaching its limitation, to a point where it cannot continue in its present form or shape. Based on the current research work in Device Modelling group at University of Glasgow and other research groups, of all the challenges that hinders the progress of of scaling is variability of device parameters. It has severe consequences on device operations and on its reliability. The variability, which we investigate are random discrete dopant, line edge roughness and the metal grain and granularity effects on carrier transport and device performance and advanced circuit functionality.
Time-Dependent Variability: A test-proven modeling approach for systems varification and power consumption minimization.
EU FP7 project: Circuit Stability Under Process Variability and Electro-Thermal-MEchanical Coupling (SUPERTHEME) Research Partners: Fraunhofer IISB, Fraunhofer IIS, University of Glasgow, Gold Standard Simulations Ltd., TU Vienna, AMS, ASML, et al.
In addition to my research activity in the area of Oxide Reliability in nano-scale semiconductor devices, I am working as a Project Coordinator of StatDes. It is a synergy between academic research community (Universities of Glasgow and Edinburgh) and industry (GSS, Wolfson microelectronics, and IBM) with objectives of enabling designers by delivering a better analogue, mixed signal, and Digital electronics designing tools, delivering improved design practice and solutions that will result in a better system on chip (SoC) design and delivering well trained analogue design experts.
My current project is focused on statistical investigation of oxide reliability wear-out mechanisms and performance degradation of nano-scale transistors. In particular, the project gives emphasis to research on instabilities due to bias temperature stress (P/NBTI), hot carrier degradation (HCD) and the investigation of time dependent degradation of dielectric materials breakdown (TDDB), which adversely affects the reliability of CMOS devices. For this purpose, we are developing a 3D-statistical model that applies the principles of Kinetic Monte-Carlo to account the time-evolution of device simulations and the dynamics of trapping and de-trapping mechanisms (transition dynamics). The model will then be integrated into 3D Glasgow Atomistic Simulator to enable as performing a full 3D statistical simulation on different device architectures with various dimensions.
The research program that I am currently involved with is supported by the MORDRED European collaborative project on modelling of the reliability and degradation of next generation nanoelectronic devices, involving the following industrial and academic research partners (IFX, IMEC, KUL-E, KUL-P, GSS, GU, TUT, TUW, UCL).
M. Duan, C. Navarro, B. Cheng, F. Adamu-Lema, X. Wang, V. P. Georgiev, F. Gamiz, C. Miller, S. Amoroso and A. Asenov, "Thorough understanding of retention time of Z2FET memory operation," IEEE Transactions on Electron Devices, Vol. 66, No. 1, pp. 383–388, 2019.
S. Berrada, J. Lee, H. Carrillo-Nunez, C. Medina-Bailon, F. Adamu-Lema, V. Georgiev and A. Asenov, "Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs," 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD): Sept. 2018.
S. Berrada, T. Dutta, H. Carrillo-Nunez, M. Duan, F. Adamu-Lema, J. Lee, V. Georgiev, C. Medina-Bailon and A. Asenov, "NESS: new flexible Nano-Electronic Simulation Software," 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD): Sept. 2018.
H. Carrillo-Nunez, J. Lee, S. Berada, C. Medina-Bailon, F. Adamu-Lema, M. Luisier, A. Asenov and V. Georgiev, "Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study," IEEE Electron Device Letters, Vol. 39, No. 9, pp. 1473–1476, 2018.
J. Lee, O. Badami, H. Carrilo-Nunez, S. Berrada, C. Medina-Bailon, T. Dutta, F. Adamu-Lema, V. P. Georgiev and A. Asenov, "Variability predictions for the next technology generations of n-type SixGe1-x nanowire MOSFETs," Micromachines, Vol. 9, No. 12, p. 643, 2018.
J. Lee, S. Berada, F. Adamu-Lema, N. Nagy, V. Georgiev, T. Sadi, J. Liang, R. Ramos, H. Carrillo-Nunez, D. Kalita, K. Lilenthal, M. Wisliceus, R. Pandey, B. Chen, K. Teo, G. Goncalves, H. Okuno, B. Uhlig, A. Tordi-Sanial, J. Dijon and A. Asenon, "Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electrothermal Simulation Study," IEEE Transactions on Electron Devices, Vol. 65, No. 9, pp. 3384–3892, Sept. 2018.
F. Adamu-Lema, M. Duan, S. Berrada, J. Lee, T. Al-Ameri, V. Georgiev and A. Asenov, "Modelling and Simulation of Advanced Semiconductor Devices," ECS Transaction, Vol. 80, No. 4, pp. 33–42, 2017.
T. Al-Ameri, V. P. Georgiev, T. Sadi, Y. Wang, F. Adamu-Lema, X. Wang, S. M. Amoroso, E. Towie, A. R. Brown and A. Asenov, "Impact of Quantum Confinement on Transport and the Electrostatic Driven Performance of Silicon Nanowire Transistors at the Scaling Limit," Solid State Electronics, Vol. 129, pp. 73–80, Mar. 2017.
T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema and A. Asenov, "Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5 nm CMOS Applications," IEEE Journal of the Electron Devices Society, Vol. 5, No. 6, pp. 466–472, Sept. 2017.
T. Al-Ameri, V. Georgiev, F. Adamu-Lema and A. Asenov, "Position-Dependent Performance in 5 nm Vertically Stacked Lateral Si Nanowires Transistors," International Workshop on Computational Nanotechnolgy: 2017.
T. Al-Ameri, V. Vihar. Georgiev, F. Adamu-Lema and A. Asenov, "Variability-aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors," International Workshop on Computational Nanotechnolgy: 2017.
T. Al-Ameri, V. Georgiev, F. Adamu-Lema and A. Asenov, "Does a Nanowire Transistor Follow the Golden Ratio? A 2D Poisson-Schrödinger/3D Monte Carlo Simulation Study," Simulation of Semiconductor Processes and Devices (SISPAD), 2017 International Conference on: 2017.
M. Duan, F. Adamu-Lema, B. Chen, C. Navaro, X. Wang, F. Gamiz, C. Miller, V. Georgiev and A. Asenov, "2D-TCAD Simulation on Retention Time of Z2FET for DRAM Application," Simulation of Semiconductor Processes and Devices (SISPAD), 2017 International Conference on: 2017.
V. P. Georgiev, M. Mirza, A.-I. Dochioiu, F. Adamu-Lema, S. M. Amoroso, E. Towie, C. Riddet, D. MacLaren, A. Asenov and D. J. Paul, "Experimental and simulation study of silicon nanowire transistors using heavily doped channels," IEEE Transactions on Nanotechnology, Vol. 16, No. 5, pp. 727–735, Feb. 2017.
T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema and A. Asenov, "Influence of Quantum Confinement Effects and Device Electrostatic Driven Performance in Ultra-Scaled SixGe1-Nanowire Transistors," EUROSOI-ULIS 2016 Joint International Conference: Jan. 1, 2016.
T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, T. Sadi, X. Wang, E. Towie, C. Riddet, C. Alexander and A. Asenov, "Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D poisson schrodinger simulation study," International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2016: Sept. 2016.
T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, T. Sadi, E. Towie, C. Riddet and A. Aseov, "Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study," IEEE Nanotechnology Materials and Devices Conference (NMDC): Sept. 2016.
T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, X. Wang and A. Asenov, "Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled SixGe1-x nanowire transistors," Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS): Jan. 25-27, 2016.
V. P. Georgiev, M. Mrza, A.-I. Dochioiu, F. Adamu-Lema, S. M. Amoroso, E. Towie, C. Riddet, D. MacLaren, A. Asenov and D. Paul, "Experimental and simulation study of a high current 1D silicon nanowire transistor using heavily doped channels," IEEE Nanotechnology Materials and Devices Conference (NMDC): Sept. 2016.
T. Al-Ameri, Y. Wang, V. P. Georgiev, F. Adamu-Lema, X. Wang and A. Asenov, "Correlation between Gate Length, Geometry and Electrostatic Driven Performance in Ultra-Scaled Silicon Nanowire Transistors," in Proc. 10th IEEE Nanotechnology Materials and Devices Conference (NMDC), Anchorage AK, Sept. 13-16, 2015, pp. 30–34.
S. M. Amoroso, F. Adamu-Lema, A. R. Brown and A. Asenov, "A Mobility Correction Approach for Overcoming Artifacts in Atomistic Drift-Diffusion Simulation of Nano-MOSFETs," IEEE Trans. Electron Devices, Vol. 62, No. 6, pp. 2056–2060, 2015.
F. Adamu-Lema, S. M. Amoroso, X. Wang, B. Cheng, L. Shifren, R. Aitken, S. Sinha, G. Yeric and A. Asenov, "The Discrepancy Between the Uniform and Variability Aware Atomistic TCAD Simulations of Decananometer Bulk MOSFETs and FinFETs," in Proc. 19th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama Japan, Sept. 8-11, 2014, pp. 285–288.
F. Adamu-Lema, X. Wang, S. M. Amoroso, C. Riddet, B. Cheng, L. Shifren, R. Aitken, S. Sinha, G. Yeric and A. Asenov, "Performance and variability of doped multi-threshold FinFETs for 10nm CMOS," IEEE Transactions on Electron Devices, Vol. 61, No. 10, pp. 3372–3378, Oct. 2014.
A. Asenov, F. Adamu-Lema, X. Wang and S. M. Amoroso, "Problems with the continuous doping TCAD simulations of decananometer CMOS transistors," IEEE Transactions on Electron Devices, Vol. 61, No. 8, pp. 2745–2751, Aug. 2014.
A. Asenov, B. Cheng, F. Adamu-Lema, L. Shifren, S. Sinha, C. Riddet, C. L. Alexander, A. R. Brown, X. Wang and S. M. Amoroso, "Predictive Simulation of Future CMOS Technologies and Their Impact on Circuits," in Proc. IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin China, Oct. 28-31, 2014, pp. 1411–1414.
F. Adamu-Lema, C. M. C. M. Compagnoni, S. M. Amoroso, N. Castellani, S. Markov, L. Gerrer, A. S. A. S. Spinelli, A. L. A. L. Lacaita and A. Asenov, "Accuracy and issues of the spectroscopic analysis of RTN traps in nanoscale MOSFETs," IEEE Trans. Electron Devices, Vol. 60, No. 2, pp. 833–839, Feb. 2013.
S. M. Amoroso, L. Gerrer, S. Markov, F. Adamu-Lema and A. Asenov, "RTN and BTI in Nanoscale MOSFETs: A Comprehensive Statistical Simulation Study," Solid State Electronics, Mar. 2013.
X. Wang, F. Adamu-Lema, B. Cheng and A. Asenov, "Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis," IEEE Trans. Electron Devices, Vol. 60, No. 5, pp. 1547–1554, May 2013.
F. Adamu-Lema, S. M. Amoroso, S. Markov, L. Gerrer and A. Asenov, "A Unified Computational Scheme for 3D Statistical Simulation of Reliability Degradation of Nanoscale MOSFETs," 17th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD): Sept. 5-7, 2012.
S. M. Amoroso, L. Gerrer, S. Markov, F. Adamu-Lema and A. Asenov, "Comprehensive Statistical Comparison of RTN and BTI in Deeply Scaled MOSFETs by means of 3D ‘Atomistic’ Simulation," 42nd European Solid-State Device Research Conference (ESSDERC): Sept. 17-21, 2012.
S. M. Amoroso, F. Adamu-Lema, S. Markov, L. Gerrer and A. Asenov, "3D Dynamic RTN Simulation of a 25nm MOSFET: The Importance of Variability in Reliability Evaluation of Decananometer Devices," 15th International Workshop on Computational Electronics (IWCE): 2012.
L. Gerrer, S. Markov, S. M. Amoroso, F. Adamu-Lema and A. Asenov, "Impact of random dopant fluctuations on trap-assisted tunnelling in nanoscale MOSFETs," Journal of Microelectronics Reliability, July 2012.
S. Markov, L. Gerrer, S. M. Amoroso, F. Adamu-Lema and A. Asenov, "Time Domain Simulation of Statistical Variability and Oxide Degradation Including Trapping/detrapping Dynamics," 17th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD): Sept. 5-7, 2012.
K. Samsudin, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Combined sources of intrinsic parameter fluctuations in sub-25 nm generation UTB-SOI MOSFETs: A statistical simulation study," Solid-State Electronics, Vol. 51, No. 4, pp. 611–616, 2007.
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Transactions on Electron Devices, Vol. 53, No. 12, pp. 3063–3070, 2006.
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy and A. Asenov, "Intrinsic Parameter Fluctuations in Conventional MOSFETs until end of the ITRS," Journal of Physics Conferences Series, Vol. 38, pp. 188–191, 2006.
K. Samsudin, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Intrinsic parameter fluctuations in sub-10nm generation UTB SOI MOSFETs," ser. 7 th European Workshop on ULtimate Integration of Silicon , ULIS 2006, pp. 93–96.
B. Cheng, S. Roy, G. Roy, F. Adamu-Lema and A. Asenov, "Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells," Solid-State Electronics, Vol. 49, No. 5, pp. 740–746, 2005.
L. Yang, J. R. Watling, F. Adamu-Lema and A. Asenov, "Simulations of Sub-100 nm Strained Si MOSFETs with High-k Gate Stacks," Computational Electronics, Vol. 3, pp. 171–176, 2005.
F. Adamu-Lema, S. Roy, A. R. Brown, A. Asenov and G. Roy, "Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit: a statistical study," in Proc. 10th International Workshop on Computational Electronics (IWCE), West Lafayette, IN, USA, Oct. 24-27, 2004, pp. 44–45.
F. Adamu-Lema, G. Roy, A. R. Brown, A. Asenov and S. Roy, "Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit:a statistical study," J. Computational Electronics, Vol. 3, pp. 203–206, 2004.
B. Cheng, S. Roy and F. Adamu-Lema, "Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells," ser. 5th European Workshop on Ultimate Integration of Silicon - ULIS04, pp. 23–26.
L. Yang, J. R. Watling, F. Adamu-Lema, A. Asenov and J. R. Barker, "Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks," in Proc. 2004 International Electron Device Meeting (IEDM), Dec.
A. R. Brown, F. Adamu-Lema and A. Asenov, "Intrinsic parameter fluctuations in nanometer scale thin body SOI devices introduced by interface roughness," in Proc. Sixth International Conference on New Phenomena in Mesoscopic Systems, and Fourth International Conference on Surfaces and Interfaces of Mesoscopic Devices (NPMS-6/SIMD-4), Maui, HI, USA, Nov. 30-Dec. 5, 2003, pp. 32–33.
A. R. Brown, F. Adamu-Lema and A. Asenov, "Intrinsic Parameter Fluctuations in Nanometre Scale Thin-body SOI Devices Introduced by Interface Roughness," Superlattices and Microstructures, Vol. 34, No. 3-6, pp. 283–291, 2003.
A. Asenov, M. Jaraiz, S. Roy, G. Roy, F. Adamu-Lema, A. R. Brown, V. Moroz and R. Gafiteanu, "Integrated atomistic process and device simulation of decananometre MOSFETs," in Proc. Simulation of Semiconductor Processes and Devices, Kobe, Japan, Sept. 4-6, 2002, pp. 87–90.

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