Source: https://patents.google.com/patent/US8707062B2/en
Timestamp: 2019-04-23 21:24:26+00:00

Document:
For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
Also, in one embodiment, voltage from the I/O control hub 225 (VI/O 349) may be provided to the processor 205 in order to provide sufficient power to the dedicated cache memory 340 such that it can store the critical state variables associated with the processor 205 while the rest of the processor 205 is powered down by the reduction of the operating voltage 240 down to a zero state.
Looking particularly at FIG. 4, an illustration of entry into the zero voltage processor sleep state is provided. As shown in FIG. 4, each core independently performs a state save when the zero voltage processor sleep state is initiated. Particularly, looking at CPU core #0 320, the first CPU core #0 is active (circle 402) and then a command for a zero voltage sleep state is initiated (e.g. via a sleep or MWAIT instruction) (circle 404). Responsive to this, the state of CPU core 320 is saved at circle 406 to dedicated cache memory 340. This includes the dedicated state 325 and the shared state 324. CPU core 320 then goes into a first sleep state 408 (e.g. CC6) in which it waits for the other core to get into the CC6 state as well, before the whole package can transition into the overall package sleep state (e.g. C6).
In the same manner, the other CPU core (e.g. CPU core #1 322) likewise commands a sleep instruction (e.g. MWAIT) at circle 414 and its state (e.g. both its shared state 324 and dedicated state 325) is also stored to the dedicated cache memory 340 (circle 418). However, in this case, since this is the last core to go into a sleep state, the shared cache 330 is also shrunk and saved to dedicated cache memory 340 (circle 416). Then at circle 420, the second CPU core 322 likewise enters a sleep state (e.g. CC6).
the second processor core to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.
2. The processor of claim 1, wherein the first processor core is to save the state of the first processor core in the cache memory.
3. The processor of claim 1, wherein the first processor core is to enter the mode in which the first processor core is powered off in response to execution of an instruction by the first processor core.
4. The processor of claim 3, wherein the second processor core is to enter the mode in which the second processor core is powered off in response to execution of an instruction by the second processor core.
5. The processor of claim 1, wherein the first processor core is to restore the saved state of the first processor core when reset.
6. The processor of claim 5, wherein the second processor core is to restore the saved state of the second processor core when reset.
7. The processor of claim 1, wherein the first processor core is to transition to the mode in which the first processor core is powered in response to a signal from a power management controller.
8. The processor of claim 7, wherein the second processor core is to transition to the mode in which the second processor core is powered in response to a signal from the power management controller.
9. The processor of claim 1, wherein the first processor core is to save and restore registers of the first processor core.
10. The processor of claim 1, wherein the first processor core is to save and restore a debug state of the first processor core.
the second processor core to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered, wherein the second processor core is to restore the saved state of the second processor core when reset.
12. The processor of claim 11, wherein the first processor core is to save the state of the first processor core in the cache memory.
13. The processor of claim 11, wherein the first processor core is to transition to the mode in which the first processor core is powered in response to a signal from a power management controller.
14. The processor of claim 13, wherein the second processor core is to transition to the mode in which the second processor core is powered in response to a signal from the power management controller.
15. The processor of claim 11, wherein the first processor core is to save and restore registers of the first processor core.
16. The processor of claim 11, wherein the first processor core is to save and restore a debug state of the first processor core.
restoring the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.
18. The method of claim 17, wherein saving the state of the first processor core includes saving the state of the first processor core in the cache memory.
wherein entering the mode in which the second processor core is powered off is in response to execution of an instruction by the second processor core.
wherein restoring the saved state of the second processor core occurs when the second processor core is reset.
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