Source: http://dtsheet.com/doc/1387888/data-sheet
Timestamp: 2019-04-23 02:00:57+00:00

Document:
in high end broadcast compressors.
readback capability from any point in the algorithm flow.
functions of the two parts are identical.
Fax: 781.461.3113©2004–2010 Analog Devices, Inc. All rights reserved.
Test conditions, unless otherwise noted.
VDD = 2.25 V to 2.75 V. Specifications measured across −40°C to 125°C (case).
SDA is measured with a 3 mA sink current.
Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.
Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ.
The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 37.
master clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.
This pin should be connected to ground.
I2C Filter Enable, Active Low.
Left/Right Clock for Serial or TDM Data Inputs.
Bit Clock for Serial or TDM Data Inputs.
Serial Data Input 2/TDM Input 1.
Serial Data Input 3/TDM Input 0.
Power Connection for Output Pins.
Serial Data Output 0/TDM (16- or 8-Channel) Output 0.
Serial Data Output 4./TDM (8-Channel) Output 1.
Serial Data Output 7/Data Capture Output.
Voltage Level Input to Regulator. Usually 3.3 V or 5 V.
Digital Power Level. Should be tied to VDD.
Drive for External PNP Transistor.
Reference Level for Voltage Regulator.
AD1941 is controlled by an I2C bus.
RAM can be loaded with a custom program after power-up.
serial audio data in MSB first and twos complement format.
AD1941 to be clocked from a variety of different clock speeds.
fS to generate the core’s internal master clock.
driving external DACs or digital analyzers.
The AD1940/AD1941 operate from a single 2.5 V power supply.
writing to Bits 2:0 of the serial input port control register.
Serial Data Input/Output Ports section for further explanation.
clock for the input TDM stream.
described in the Setting Master Clock/PLL Mode section.
Serial Data Input for the SPI Control Port.
SPI read is not active.
Input/Output Ports section for further explanation.
described in the Data Capture Registers section.
gated off between SPI transactions.
beginning of the SPI transaction.
pin should have a 2 kΩ pull-up resistor on it.
connected to this pin should have a 2 kΩ pull-up resistor on it.
bus from improperly affecting the AD1941.
sensed on VSENSE. VSENSE should be tied to VDD.
voltage supply. This is usually 3.3 V or 5 V.
AD1941s to be used on the same I2C bus.
Digital VDD for Core. 2.5 V nominal.
written to the control port until the initialization is complete.
internal 1.15 V reference voltage.
Supply for AD1940/AD1941 PLL. 2.5 V nominal.
2.5 V to 5.0 V.
external PNP transistor is driven from this pin.
this pin must always be at or above the level of ODVDD.
ADI-supplied software, which allows graphical entry and realtime control of all signal processing functions.
processor to allow internal gains up to 24 dB without clipping.
input signal in the signal flow.
range of 1.0 (minus 1 LSB) to –1.0.
0111 1111 1111 1111 1111 1111 1111 = (16.0 – 1 LSB).
gains of up to 24 dB without encountering internal clipping.
outputs are muted by default (see Power-Up Sequence section).
in the core control register.
AD1940/AD1941’s program RAM through the control port.
virtualizers. Contact an ADI sales representative for information about licensing these algorithms.
control, are programmed by writing to the control registers.
on the type of data that is written.
data, such as control port, program, or parameter data.
the core control register), new data loaded, and then restarted.
data written should be MSB first.
(Logic Level 1) or a write (Logic Level 0).
appropriate RAM location or register.
Control Port Read/Write Data Formats section.
diagram of a single SPI read operation is shown in Figure 12.
R/W bit, and subsequent bytes carry the data.
and the part returns to the idle condition.
SCL is held high. Figure 13 shows the timing of an I2C write.
Table 13 shows the timing of a single-word write operation.
Table 14 shows the timing of a burst mode write sequence.
acknowledge pulse to the AD1941.
to a register or memory area with word lengths of two bytes.
address increments after the appropriate number of bytes.
DSP core should be shut down first to avoid clicks/pops.
The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single write mode or burst mode.
program RAM or control registers.
are initialized on power-up from on-board boot ROMs.
parameter, program, and target/slew RAMs.
1023. The parameter RAM is initialized to all 0s on power-up.
0000 1000 0000 0000 0000 0000 0000.
The following sections discuss these two options in more detail.
mechanisms for disabling the core.
Fill the program RAM using burst mode writes.
Fill the parameter RAM using burst mode writes.
register, or simply wait for a given amount of time).
serial output registers, and the serial input registers.
Deassert Bit 9 and Bit 6 of the core control register.
value in one of four modes.
format for the constant time ramping.
safeload registers as described in the Safeload Registers section.
Linear—Value slews to target using a fixed step size.
constant rise and decay when measured in dB.
producing a simple RC type curve for rising and falling.
has no affect on this type.
The result of the equation is normalized to a 5.23 data format.
the fastest and 0xF being the slowest).
the step value is updated.
number of steps equal to 23-bit setting + 6.
Data (16 bits). 2.14 format.
should all be set to 0.
range from 6.1 ms to 1.27 s (–60 dB relative to 0 dB full scale).
difference between the values in the target RAM and slew RAM.
constant dB increasing ramp, and is show in Figure 19.
fs = 48 kHz) of the initiate safe transfer bit being set.
The safeload logic automatically sends only those safeload registers that have been written to since the last safeload operation.
to the RAM and can still hold old or invalid data.
constant time decreasing ramp plot is shown in Figure 21.
signal levels or compressor/limiter activity.
(Bit 14) is set in serial output Control Register 2. These registers are useful when debugging the signal processing flow.
been previously written to the high bits of the target RAM.
selections are shown in Table 23.
capture registers can be seen in Table 32 and Table 33.
click or pop when shutdown is asserted.
assembly language coding in the ADI graphical tools.
occurring during the power-up sequence.
Setting this bit to 1 initializes all data memory locations to 0.
download has occurred to ensure click-free operation.
consumption of the part is cut approximately in half.
have been written since the last safeload event are transferred.
Address 0 corresponds to the first target RAM location.
AD1940/AD1941’s cores. This address offset counter is incremented automatically at the audio frame rate.
Address 0 corresponds to the first parameter RAM location.
length of 192 steps is available, but is not commonly used.
order to extend the data word to the next multiple of eight bits.
Burst mode data transfers can continue beyond the three words that are illustrated here in the same sequential word format. The register/RAM address autoincrements until the data transfer reaches the IC's last address.
Progcount [10:0] = value of program counter where trap occurs (the table of values is generated by the program compiler).
Regsel [1:0] selects one of four registers (see Data Capture Registers section).
serial output and serial input control registers.
modes in which the serial output port will function.
AD1940/AD1941 as either a 50/50 duty cycle clock or as a bitwide pulse.
modes requires the LSB to align with the edge of the LRCLK.
LRCLK_OUT1 and BCLK_OUT1 Clock Ports 8 to 15.
apply to both master and slave modes unless otherwise noted.
Setting this bit to 1 enables dither on the appropriate channels.
following the LSB are set to 0.
Capture Registers section for a full explanation of this mode.
to 1, this is reversed.
This bit sets whether the output port is a clock master or slave.
which time they become clock outputs.
from the internal 73.728 MHz core clock.
This bit sets the type of signal on the LRCLK_OUTx pins.
clock at the beginning of the data frame.
control registers to enable 16-channel TDM on SDATA_OUT0.
in on SDATA_IN2/TDM_IN1 and SDATA_IN3/TDM_IN0.
16-channel TDM input mode, input on TDM_IN1.
register) that follows a falling edge on the LRCLK_IN pin.
be used, and a high pulse should be used when the bit it set to 1.
of the word clock by one BCLK.
rising edge when this bit is set at 1.
these modes are shown in Figure 23, Figure 24, and Figure 25.
Table 37 explains the clock settings for each of these formats.
also cleared during this time.
pins. Reset is synched to the falling edge of the internal MCLK.
to the 16 digital outputs, as shown in Figure 28.
pins should be changed while RESETB is held low.
capacitor should be connected between this pin and ground.
resistor should be connected between VDRIVE and VSUPPLY.
frequencies must be either 32 × fS, 128 × fS, 192 × fS, or 256 × fS.
163 mA (maximum digital current + maximum PLL current).
to the same or higher potential as the VDD pin.
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

References: V. 
 V.

 V. 
 V.

 V.

 V.