Source: http://web-ext.u-aizu.ac.jp/official/researchact/annual-review/2001/hard/cldl_j.html
Timestamp: 2019-04-25 12:00:35+00:00

Document:
In 2001, research themes of the laboratory was On-Chip Learning Artificial Neuron, Logical Timing and Decentralized Control in Massively Parallel Computing Systems and Noise Immunity Asynchronous Protocols with Postponed Handshake.
In the first theme the problem of design floating gate transistors based on-chip learning artificial neural networks were studied. Design methodology of such a structure is created. The methodology could be used for circuit optimization taking into account elements parameter and dimension deviations. Especially important problemis the tolerance to supply voltage deviations, because of possible difference in the voltages in learning and working phases. As a result of investigation the main parts of the structure and their design methodology had been developed. The proposed structure is fully tolerant to any kind of deviations and especially efficient in the environment where supplied voltage varies greatly. The tolerance of the structure was reached using the idea of compensating deviations in one part of the structure by deviations in another part. Such an approach is important because technology process is going to smaller design rules and supply voltage. The possibility of using ??oating gate transistors based step voltage comparator as a way to refresh synapse weight represented as a voltage in dynamic memory is shown.
A special class of threshold functions (Horner's functions) was suggested as test functions for learning of neurons. It was shown that Horner's functions have the complexity close to maximum and have the minimum length of checking sequences that is very important for experiments with neuron learning.
The beta-driven artificial neuron learnable to non-isotonous threshold functions was studied. We suggested the neuron that have synapses capable to form the weight and type (excitatory or inhibitory) of the input during the learning, using only increment and decrement signals. A neuron with such synapses can be learned to an arbitrary threshold function of a certain number of variables.
For such kind of neuron synapse circuits are suggested with one and two memoryelements for storing positiveand negative inputweights. The results of SPICE simulation prove that the problem of teaching neuron to non-isotonous threshold functions has stable solutions.
In the frame of automata theory, we received one rather interesting result. We have proved functional equivalence of bilateral linear cellular automata arrays and cellular arrays with arbitrary unilateral connection graph. The considered problem is building a cellular automaton, such that an array from automata of this type with arbitrary unilateral divalent connection graphcan solve the same problem as a bilateral linear cellular automata array. It is presumed that the complexity of the cellular automaton does not depend on the number of the automata in the array and, maybe, depends in some regular way on the rank of the respective graph vertex.
Third theme is connected with the problem of high noise immunity in distributed channels under high-speed data transmission, especially in wireless communication channel. One of a way to solve this problem is the use of generalized approach to signal processing in noise. The generalized approach is the combination of optimal signal processing algorithms when the amplitude-phase-frequency structure of signal is "a priori" known and unknown. It is expected that the use of asynchronous protocols constructed on the base of the generalized approach to signal processing in noise will allow to increase the noise immunity in distributed channels.
Using the top-down education approach, the undergraduate andg raduate school students are involved in all steps of the research. They learned the real style of design in the environment System-Circuit-Process, understood the importance of creating the design methodology for circuit optimization and prepared themselves to work in time of very fast changes in micro-electronics and computer science.
[rafail-001:2001] R. Lashevsky and Y. Faloutsos, Sato. Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks. Soft Computing, (6):462-469, 2002.
Hardware implementation of artificial neural networks(ANN) based on MOS transistors with floating gate (Neuron MOS) is discussed. Choosing analog approach as a weight storage rather than digital improoves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against Vdd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to devepop their design methodologies.
[marak-001:2001] V. Varshavsky and V. Marakhovsky. Asynchronous Control Logic Design for Counterflow Pipeline Processor. In Proceedings of the 9th International Symposium on Integrated Circuits, Devices and Systems (ISIC-2001), pages 177-181, Singapore, September 2001. IEEE, IEEE Computer Society.
This paper approaches the problem of building an asynchronous control for a stage of the Sproull's Counterflow Pipeline Processor (CFPP) that does not need arbiters. It is shownthat there is no arbitration situations in asynchronous pipeline control circuit with two-track synchronization. An asynchronous control circuit can be built by a synchronous prototype with help of GALA-methodology using the procedure of synchro-stratum designing we suggested earlier.
[marak-002:2001] V. Varshavsky and V. Marakhovsky. A Neuron-MOS Threshold Element with Switching Capacitors. In Volume Editor Bernd Reusch, editor, Lecture Notes in Computer Science 2206, Computational Intelligence Theory and Applications, ed. by Bernard Reusch. Proceedings of the International Conference, 7th Fuzzy Days, pages430-435, Dortmund, Germany, October 2001. University of Dortmund, Springer-Verlag.
In the paper a new approach to building a vMOS threshold element and an artificial neuron on its base is discussed. The implementability of the known vMOS threshold elements is restricted by the sum of input weights. It is shown that by switching the element capacitors in the pre-chargephase it is possible to reduce the implementability restriction to the maximumvalue of the threshold. It essentially expands the set of threshold functions realizable on one element.
[marak-003:2001] V. Varshavsky and V. Marakhovsky. GALA Approach in Design of Asynchronous Control for Counter??ow Pipeline Processor. In International Workshop on Electronic Design, Test, and Applications (DELTA 2002), pages 73-78, New Zealand, January 2002. Massey University, IEEE Computer Society.
[marak-004:2001] V. Varshavsky and V. Marakhovsky. Arbiter-Free Counterflow Pipeline Processor: Designing Asynchronous Control Logic. In M.H.Hamza, editor, Proceedings of the 20th IASTED International Conference on Applyed Informatics, pages 1-6, Innsbruck, Austria, Feb. 2002. IASTED, ACTA Press.
The paper discusses developing asynchronous control logics for Sproull's Counterflow Pipeline Processor (CFPP) without the need for arbiters. As one can see, a synchronous pipeline control circuit with two-track synchronization is free from arbitration situations. One can build an asynchronous control circuit by a synchronous prototype using GALA-methodology and design of synchrostratum which we suggested in our earlier papers.
[rafail-002:2001] R. Lashevsky. Neural-MOS Threshold Gate as aWay to Design On-Chip Learning Neuron Structures. In Vitaliy V. Kluev and Nikos E. Mastorakis, editors, Topics in Applied and Theoretical Mathematics and Computer Science, Proceedings of the 2nd Multiconference, pages 197-201, Cairins, Australia, December 2001. WSEAS, WSEAS Press.
Hardware implementation of artificial neyron networks (ANN) based on MOS-transistors with floating gates (Neuron MOS or v-MOS) is discussed. Compari-son of two type on-chip learning neurons with digital and analog inputs weight storing is provided. The main problem in design the neuron with analog input weight memory is tolerance to deviations of circuit elements parameters and supplied voltage deviation. New neuron circuit that can compensate all kinds of deviations is proposedand investigated. Design methodology of sucha circuit and result of simulation are shown.
[marak-005:2001] V.Varshavsky, A.Yakovlev, V. Marakhovsky, and I Levin. Self-Timing, Self-Checking and Self-Recovery. In Euromicro 4th International Conference on Massively Parallel Computing Systems (MPCS-02), pages 171-172, Ischia, Italy, Apr. 2002. Euromicro, Handouts.
[marak-006:2001] V.Varshavsky, A.Yakovlev, V. Marakhovsky, and I Levin. Self-Timing, Self-Checking and Self-Recovery. In Euromicro 4th International Conference on Massively Parallel Computing Systems (MPCS-02), pages 171-172, Ischia, Italy, Apr. 2002. Euromicro, Handouts.
[tuzlukov-001:2001] Vyacheslav P. Tuzlukov. Signal Detection Theory. Birkhauser Boston, 2001.
[tuzlukov-002:2001] VyacheslavP. Tuzlukov. Signal Processing Noise. CRC Press, 2002.

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