Source: https://patents.google.com/patent/US6911962B1/en
Timestamp: 2019-04-25 16:07:08+00:00

Document:
In a liquid crystal display device of the in-plane switching mode (IPS mode), the potential of data that is output from a data driver is set at values between potentials that are given to common lines. Two levels, i.e., high and low levels, are prepared for the potential to be given to the common lines and the potential is inverted between those levels in every field, whereby the polarity of a voltage between both electrodes of a pixel is inverted. As a result, the potential variation ranges of signals that are output from the data driver and a scan driver can be greatly reduced from those of the conventional case, which contributes to reduction in the power consumption of the drivers. Since the voltage applied to a switching element for controlling each pixel can be reduced, the load of the switching element can also be reduced.
This is a continuation of U.S. application Ser. No. 08/823,238, filed Mar. 24, 1997 now U.S. Pat. No. 5,847,687.
The present invention relates to an active matrix display device. In particular, the invention relates to an active matrix display device which employs a display method of the in-plane switching mode (also called IPS mode). The invention is intended to reduce potential variation of signals (or data) to thereby lower the power consumption, and to reduce voltages applied to the switching elements that are provided for the respective pixels to thereby lower the loads of the switching elements. The invention also relates to a driving method of a capacitive-coupling-type display device such as a liquid crystal display device.
In a capacitive-coupling-type display device such as a liquid crystal display device, it is necessary to invert the polarity of a voltage applied to a pixel capacitor element. This operation is also called alternating. This is because if electric fields in one direction are always applied to an electro-optical material (a material whose optical property such as light transmittance, reflectance, or a refractive index varies depending on the voltage applied thereto) provided between the electrodes of a capacitor element, the material will deteriorate. It is necessary to invert the polarity of the voltage every field (or frame) or every several fields.
Among various inverting methods, there are a field (or frame) inverting scheme in which the polarity is the same over the entire display screen in each field (see FIG. 10A), and a gate line inverting scheme in which the polarity of each row is different from adjacent rows, (see FIG. 10B). The above methods can be applied to the IPS mode.
Conventionally, the polarity inversion is performed such that each pixel is supplied, from a data driver (signal driver), with a signal whose polarity is inverted. FIG. 7 shows a unit pixel of a conventional active matrix liquid crystal display device. A thin-film transistor T as a switching element is controlled by a signal (selection pulses) on a scan line Xn. In a state that a selection pulse is applied to the thin-film transistor T (on-state), a signal on a data line (signal line) Pm is supplied to a liquid crystal pixel element LC and, if necessary, to an auxiliary capacitor C connected in parallel with the pixel element. On the other hand, the potential of a common line (or common electrode) Yn is kept constant. Charge is stored in accordance with a difference between the potential supplied from the data line Pm and that of the common line Yn.
FIG. 8 shows drive signals in a display device in which such unit pixels are arranged in an N-row matrix. In FIG. 8, a clock signal (sync signal) CLK indicates a minimum operation time of the display device. Signals are generated based on the clock signal CLK. As shown in FIG. 8, selection pulses are sequentially applied to scan lines X1, X2, X3, . . . , XN−1, XN. On the other hand, potentials depending on image signals for the respective rows are applied to a data line P1. This example is directed to the field inverting scheme (FIG. 10A). For convenience of comparison, it is assumed that the image information of the fields are always the same; that is, the data of the second field is an inversion of that of the first field with respect to the reference potential (i.e., the potential of the common lines). The same relationship exists between the second and third fields.
FIG. 9 shows an example of data in the case of the gate line inverting scheme (FIG. 10B). The data for each row has opposite polarities between the first and second fields.
As described above, in the conventional active matrix liquid crystal display devices, the driver needs to generate data whose variation range is two times that of a signal required by only image information. That is, although basically it is sufficient to apply a liquid crystal with effective voltages of a 5 V, the necessity of inversion requires a variation range of 10 V, i.e., +5 V to −5 V. This increases drive voltages of the driver, and hence is the greatest obstacle to reduction in power consumption.
There is another problem because of the increase of large potential variations of data, output potential differences (i.e., selection pulse heights) of the scan driver, and power consumption therein. Further, due to large voltages applied to the active matrix circuit, the switching elements (transistors) will possibly be broken or their characteristics will possibly deteriorate.
The present invention has been made in view of the above problems, and an object of the invention is therefore to provide a device configuration and a corresponding driving method which enable necessary polarity inversion while minimizing data variations.
In the in-plane switching (IPS) mode, a display is performed by applying electric fields of which directions are parallel with a substrate surface by means of a single substrate, in contrast to the conventional liquid crystal display devices in which display is performed by applying, between the substrates, electric fields perpendicular to the substrates. Japanese Examined Patent Publication No. Sho. 63-21907 discloses the basic concept of the IPS mode in an active matrix liquid crystal display device using thin-film transistors as switching elements.
Among the inventions made by adapting the above basic concept of the IPS mode are disclosed in Japanese Unexamined Patent Publication Nos. Hei. 7-43744, Hei. 7-43716, Hei. 7-36058, Hei. 6-160878, Hei. 6-202073, Hei. 7-134301, and Hei. 6-214244. Further, Japanese Unexamined Patent Publication No. Hei. 7-72491 is directed to a case where the IPS mode is used in a passive matrix liquid crystal display device. Japanese Unexamined Patent Publication No. Hei. 7-120791 is directed to a case where the IPS mode is employed in an active matrix liquid crystal display device using thin-film diodes as switching elements.
The operation principle of the IPS mode disclosed in the above prior art references will be briefly described below with reference to FIGS. 5 and 6. FIG. 5 shows a unit pixel of an active matrix liquid crystal display device using the IPS mode. As in the case of ordinary active matrix liquid crystal display devices, data lines 11 and scan lines 12 are arranged in matrix form. In addition, common lines (also called opposed electrode lines) 13 are provided.
Conventionally, the common lines 13 are not necessary in the substrate because the opposed substrate has them. However, in the IPS mode in which the opposed substrate has no electrode, wiring lines (i.e., common lines 13) having a function equivalent to that of the above electrode need to be provided on the substrate concerned.
In the conventional IPS mode, the potential of the common lines 13 is kept at a constant value. Where the common lines 13 are formed at the same time as the scan lines 12, the former is patterned so as not intersect the latter, that is, so as to be parallel with the latter. With this structure, the common line 13 may be overlapped with a pixel electrode 14 which is formed at the same time as the data line 11, to form an auxiliary electrode C.
That is, the scan lines 12 and the common lines 13 can be formed at the same time and the data lines 11 and the pixel electrodes 14 can also be formed at the same time. A switching element (thin-film transistor, i.e., TFT) is formed as shown in FIG. 5 with a portion of the scan line 12 used as a control electrode (i.e., gate electrode). The input terminal (source) of the switching element is in contact with the data line 11 and the output terminal (drain) is in contact with one electrode (pixel electrode 14) of the pixel capacitor element. The common line 13 serves as the other electrode of the pixel capacitor element.
In FIG. 6, since the common line 13 is so formed as to be opposed to the pixel electrode 14 as described above, when a potential is given to the pixel electrode 14, electric fields indicated by arrows develop between the pixel electrode 14 and the common line 13. Where a liquid crystal is used as the electro-optical material, in the initial state liquid crystal molecules are so oriented as to form a predetermined angle with expected electric fields (state a in FIG. 6). For example, in the case of a nematic liquid crystal, the predetermined angle is 15°. When electric fields are applied, liquid crystal molecules tend to become parallel with the electric field (state b in FIG. 6). Gradation can be expressed by properly utilizing the inclination of liquid crystal molecules. The description of the operation principle of the IPS mode concludes here.
The IPS mode has a feature of a wider viewing angle than in the conventional liquid crystal display devices because the liquid crystal is oriented parallel with the substrates. However, in the above-described prior art of the IPS mode, no consideration is made of reduction in the load of the data driver; data are generated in the same manner as in the conventional cases.
According to the present invention, with keeping the feature of the IPS mode, it is able to reduce the potential variation range of data while inverting the direction of electric fields applied to liquid crystal molecules. The invention is directed to a configuration in which the common lines and the scan lines are arranged so as not to cross each other and the potential of each common line can be controlled in accordance with a signal supplied to the corresponding scan line. The invention is characterized in that each common line is given a potential VH or VL (VH>VL) during almost all of a period when a selection pulse is not applied to the corresponding scan line, and that each pixel electrode is given a signal potential VD (VL≦VD≦VH) in accordance with image information.
Naturally, a potential other than VH and VL (for instance, a middle value thereof or a value larger than the middle value) may be given to the common lines in a very short period (short enough not to affect an image; for instance, immediately before or after application of a selection pulse).
To avoid affecting an image, the period during which a potential other than VH and VL is applied should be shorter than 20% of one field period, preferably shorter than 5% thereof. That is, the common lines should be kept at the potential VH or VL during 80% or more of one field period, preferably 95% or more thereof.
In the invention, in a case where inversion is performed every field, the potential of each common line in a certain field may be set different from that of immediately preceding and following fields.
Since the potential of each common line needs to be kept constant until another signal is input next via the switching element, it may be changed to another value every time a pulse signal is applied to the corresponding scan line.
The invention can be applied to both of the field inverting scheme and the gate line inverting scheme. In the latter case, the potentials of adjacent common lines may be set always different from each other.
Where the invention is applied to a liquid crystal display device, it is preferred that the potential given to each common line be lower than the threshold voltage of a liquid crystal, to avoid affecting an image.
When the voltage applied to a liquid crystal is increased from 0 V, the major axes of liquid crystal molecules are rotated at a time point when the voltage exceeds a certain value. This voltage value is called the threshold voltage of the liquid crystal.
Therefore, even if the potentials of the common lines vary, disorder in the alignment of the liquid crystal, and resulting influences on an image are prevented by making the absolute values of the potentials given to the common lines smaller than the threshold voltage of the liquid crystal.
FIG. 12A-12C show why it is not effective to apply the invention to the source line inverting scheme.
The operation of a unit pixel according to the present invention will be described below with reference to FIGS. 3A and 3B. A specific electrode/wiring line structure corresponding to FIGS. 3A and 3B is the same as that of the conventional active matrix display device of the IPS mode shown in FIG. 5.
Both FIGS. 3A and 3B show a state that the switching element SD is closed. Therefore, in either case, the scan line Xn is supplied with a potential for rendering the switching element SD in an off-state. Where the switching element SD is a single, n-channel transistor, the necessary and sufficient condition of such a potential VX is VX ≦VL +Vth (Vth is the threshold voltage of the switching element SD) for the reason described later.
In a certain field, a pixel electrode potential Vnm is equal to VD, which corresponds to image information and satisfies a condition VL≦VD ≦VH in any case. It goes without saying that the pixel electrode potential Vnm is determined by a potential Vp of the data lines Pm at a time point when the switching element SD is opened (more precisely, at an instant when it is closed). Therefore, VL<VP<VH.
In FIG. 3A, a potential Vy of the common line Yn is VL. In this state, a potential difference VLC (=Vnm−Vy) applied to the pixel capacitor element LC is VD−VL. Since VD≧VL, the direction of an actual electric field is as indicated by the arrow.
It is assumed that in the next field the potential difference across the pixel capacitor element LC is reversed (FIG. 3B). In this field, the potential VY of the common line Yn is set at VH, and the pixel electrode potential Vnm is set at VH+VL−VD. From the condition VL≦VD≦VH, an inequality VL<VH+VL−VD<VH is satisfied. The potential difference VLC (=Vnm−V Y) applied to the pixel capacitor element LC is equal to VL−VD. Since VD≧VL, the direction of an actual electric field is as indicated by the arrow in FIG. 3B. Thus, the electric field direction can be reversed.
That is, the magnitude of the voltage difference across the pixel capacitor element LC is VH−VL or less. Incidentally, the above relationship is not satisfied in the conventional method because the potential of the common line Yn does not vary, that is, VH=VL=0 and |VLC|>0. The fact that the potential VY of the common electrode Yn varies so as to have the above relationship satisfied is one of the features of the invention.
Next, the potential of the data line Pm will be considered. To obtain the state of FIG. 3B, the potential VP of the data line Pm needs to be set such that VP=Vnm=VH+VL−VD. Since VL≦VH+VL−VD≦VH, the relationship VL≦VP≦VH is satisfied also in this case. That is, when the polarity inversion is performed, the potential VP of the data line Pm satisfies VL≦VP≦VH.
Where the switching element SD is a single, n-channel transistor, to keep an off-state irrespective of the potentials of the data line and the pixel electrode, the potential VX of the scan line (gate line) may be set lower than a potential that is the total of the threshold voltage and the lower one of the potentials of the data line and the pixel electrode. Since the minimum value that can be taken by the potentials of the data line and the pixel electrode is VL, it is sufficient that the potential VX of the scan line be so set as to satisfy VX≦VL+Vth.
On the other hand, to obtain an on-state, the potential VX of the scan line may be set higher than a potential that is the total of the threshold voltage and the higher one of the potentials of the data line and the pixel electrode. Since the maximum value that can be taken by the potentials of the data line and the pixel electrode is VH, it is sufficient that the potential VX of the scan line be so set as to satisfy VX≧VH+Vth.
For example, where the maximum voltage difference applied to the pixel capacitor element LC is 5 V, VL and VH may be set at 0 V and +5 V, respectively, in which case the data line potential VP satisfies 0≦VP≦5 V. In this manner, the voltage difference applied to the pixel capacitor element LC can have any value between −5 V and +5 V. On the other hand, it is sufficient that the scan line potential VX be lower than Vth V in an on-state and higher than (5+Vth) V in an on-state. For example, with assumptions that the threshold voltage Vth is +0.5 V and a margin of 1.5 V is established, the scan line potential VX may be set at 7 V in an on-state and −1 V in an off-state.
As described above, the invention has another feature that even if the variation range of data applied to the data line (and the common line) is greatly reduced from that of the conventional case, the direction of an electric field applied to the liquid crystal capacitor element LC can still be reversed.
For example, it is able to make the potential variation range of data in half. The fact that the variation range of the potential given to the scan line (i.e., the selection pulse height) can be greatly reduced too, which is another feature of the invention. In this manner, the invention can reduce the operation voltages to a large extent.
Although the invention is effective for inverting schemes such as the field inversion and the gate line inversion in which the pixels associated with the same scan line have the same polarity, the abovedescribed advantages cannot be obtained in inverting schemes such as the source line inversion and the dot inversion in which the pixels associated with the same scan line have different polarities.
The source line inverting scheme is characterized in that adjacent pixel electrodes of the same row (i.e., the same scan line) have different polarities. For example, as shown in FIGS. 12A-12C, assume a case where potential differences VLC1 and VLC2 of two adjacent (i.e., left and right) pixels are +5 V and −5 V in the first field (FIG. 12A) and −5 V and +5 V in the second field (FIG. 12B).
Where the switching element SD is an n-channel transistor, the scan line potential is required to be lower than the minimum potential of the data line in an off-state and to be higher than the maximum potential of the data line in an on-state. In the conventional methods (see FIGS. 8 and 9), the potentials of both data lines Pm and Pm+1 varies between −5 V and +5 V, i.e, over a range of 10 V. Therefore, the potential variation range of the scan line should also be 10 V.
To apply the invention to the left-side pixel, in the first field the potential of the common line Yn and the data of the data line Pm may be set at 0 V and +5 V, respectively, and in the second field they may be set at +5 V and 0 V, respectively. As for the right-hand pixel, the data of the data line Pm+l may be set at −5 V in the first field and 0 V in the second field. FIG. 12C summarizes the above.
To effect switching under the above conditions with the assumption that the switching element is an n-channel transistor SD, the potential of the scan line Xn should be lower than −5 V (minimum potential of the data line) in an off-state and should be higher than +5 V (maximum potential of the data line) in an on-state. That is, the variation range of 10 V is still required; the invention is the same as the conventional cases in terms of the potential variation range of the scan line (i.e., the driving ability of the scan driver). The invention provides no advantage in this respect.
However, the potential variation range of each data line is 5 V, which is a half of that of the conventional cases. Thus, the invention cannot substantially reduce the voltages of the entire display circuit, but it is effective in reducing the potential variation range of each data line. Naturally, the effect of the source line inverting is less than that of the field inverting or the gate lane inverting.
Incidentally, in the invention, the common line cannot be formed in parallel with the data line because in such a case a signal on the common line would vary in accordance with the potential of the data line.
FIG. 1 shows a field inverting type driving method according to the invention in an N-row active matrix liquid crystal display device employing the IPS mode. In this embodiment, the same display data as shown in FIG. 8 are used. As shown in FIG. 1, in the first field, selection pulses are sequentially applied to N scan lines X1, X2, X3, . . . , XN-1, XN. At a time point when a pulse is applied to each scan line, the potential of the corresponding one of the common lines Y1, Y2, Y3, . . . , YN−1, YN decreases from the high-level (VH) to the low-level (VL). Thus, the state of FIG. 3A is realized.
Conversely, in the second field, when selection pulses are sequentially applied to the scan lines X1, X2, X3, . . . , XN−1, XN, the potentials of the corresponding common lines Y1, Y2, Y3, . . . , YN−1, YN increase from the low-level to the high-level. This the state of FIG. 3B is realized.
In the third field, the same operation as in the first field is performed. The direction of an electric field applied to each liquid crystal capacitor element in the first field is in inverse to that in the second field. The same relationship holds between the second field and the third field. In this embodiment, the state of FIG. 3A or 3B is established in all rows in a certain field. Thus, the field inverting type driving is performed.
FIG. 2 shows a gate line inverting type driving method according to the invention in an N-row active matrix liquid crystal display device employing the IPS mode. As shown in FIG. 2, in the first field, the potentials of the odd-numbered common lines Y1, Y3, . . . are changed from the high-level to the low-level when selection pulses are applied to the corresponding scan lines. Conversely, the potentials of the even-numbered common lines Y2, Y4, . . . are changed from the low-level to the high-level when selection pulses are applied to the corresponding scan lines.
That is, in the first field, the state of FIG. 3A is established in the odd-numbered rows and the state of FIG. 3B is established in the even-numbered rows. Thus, a gate line inverting state is attained in which the directions of electric fields applied to the liquid crystal capacitor elements LC in adjacent rows are reverse to each other.
The operation in the second field is in converse to that in the first field. The potentials of the odd-numbered common lines Y1, Y3, . . . are changed from the low-level to the high-level while the potentials of the even-numbered common lines Y2, Y4, . . . are changed from the high-level to the low-level. That is, in the second field, the state of FIG. 3B is established in the odd-numbered rows and the state of FIG. 3A is established in the even-numbered rows. The operation in the third field is the same as in the first field.
When attention is paid to a particular row, it is seen that the direction of an electric field applied to the liquid crystal capacitor element LC in the first field is in inverse to that in the second field. In this embodiment, the direction of electric fields applied to the liquid crystal capacitor elements LC of the even-numbered rows is in inverse to that of the odd-numbered rows; that is, the line inverting type driving is performed.
FIG. 4 shows potentials of part of the matrix in a certain field. In FIG. 4, values shown in the matrix represent potentials of the associated pixel electrodes. As for the potentials of the common lines, VL=0 V and VH is +5 V. The scan lines are given a potential of −1 V in an off-state and +7 V in an on-state.
In FIG. 4, the pixels of the fourth row are being subjected to writing. Although the first and second rows display exactly the same image information, the directions of electric fields are in inverse in those rows. For example, with attention paid to the first-row/second column unit pixel and the second-row/second-column unit pixel, in the former unit pixel the potential of the pixel electrode is higher than that of the common line with a potential difference of +4 V, whereas the latter unit pixel has a potential difference of −4 V. A similar relationship holds between other pairs of electrodes. In the fourth row under writing, the potentials of the data lines P1-P4 are so set that the same image information as has been written to the third row is written to the fourth row (the directions of electric fields are in inverse).
Differences between the driving method of the invention and the conventional driving method will be described below with reference FIGS. 11A-11C. FIGS. 11A-11C show waveforms of the potentials of the scan line Xn, the data line Pm, and the common line Yn that are connected to the pixel shown in FIG. 7. It is assumed that the field inverting scheme is employed. This embodiment employs a scheme in which an offset voltage Voff is always superimposed on the voltage that is applied to the pixel. In FIGS. 11A-11C, the potential VX applied to the scan line Xn and the potential VP of the data line Pm are expressed with overlapping on each other, the potential VY of the common line Vn is drawn separately with VC used as a reference potential when it varies over time (FIGS. 11B and 11C), to prevent the drawings from becoming unduly complex.
FIG. 11A shows the conventional driving method. The potential VY of the common line (or common electrode) Yn is kept at the constant value VC. The potential variation due to the image information itself is only Vamp. However, due to the offset voltage Voff, the potential VP of the data line Pm has the maximum variation of 2(Vamp+Voff). Accordingly, the height of selection pulses on the scan line Xn increases.
However, as a matter of fact, useless voltages are applied to the data line Pm. One of those voltages is the offset voltage Voff. The offset voltage Voff need not be supplied via the data line Pm. The potential variation of the data line Pm can be reduced by supplying the offset voltage Voff via the common line Yn. FIG. 11B shows such a case.
What we should pay attention to is the potential difference applied to “the pixel in an off-state” rather than the potential difference between “the data line Pm and the common line Yn.” Therefore, the offset voltage Voff is supplied to the common line Yn in synchronism with the application of a selection pulse to the scan line Xn. In the example of FIG. 11B, the potential of the common line Yn is changed to VC immediately before the application of a selection pulse. The voltage based on only the image information is applied to the data line Pm.
In the above manner, the potential variation of the data line Pm can be reduced to 2Vamp and the selection pulse height can be reduced accordingly. It is apparent that the voltage applied to the pixel in an off-state is almost the same as in the conventional case.
However, even in the driving method of FIG. 11B, a useless voltage is still applied to the data line Pm, which is an inverted output for the alternating. To eliminate the inverting output, in the second field the data is given a bias of Vamp with respect to the data shown in FIG. 11B (also indicated by a broken line in FIG. 11C; this data is based on only the image information). With this measure, the potential variation of the data line Pm is reduced to Vamp.
Since the potential VP of the data line Pm is biased by Vamp in the second field, the potential VY of the common line Yn should also be increased by Vamp in the second field. If this is not the case, the polarity inversion is not effected properly. FIG. 11C is an example in which the potential variation of the data line Pm is decreased according to the above-described concept.
As described above, the potential variation of the data line Pm can be reduced to Vamp and the selection pulse height can be reduced accordingly. It is apparent that the voltage applied to the pixel in a non-selection state is exactly the same as in the case of FIG. 11B and almost the same as in the conventional case of FIG. 11A.
For example, if Voff and Vamp are respectively set at 2 V and 3 V and the selection pulse height is so set as to have a 2-V margin with respect to each of the minimum and maximum values of the potential VP of the data line Pm, the potential variation range of the data line Pm is 10 V and the selection pulse height is 14 V in the conventional driving method of FIG. 11A.
On the other hand, the potential variation range of the data line Pm is 6 V and the selection pulse height is 10 V in the case of FIG. 11B. In the case of FIG. 11C, the potential variation range of the data line Pm and the selection pulse height can be reduced to 3 V and 7 V, respectively.
As described above, the invention can make the potential variation of data in half while enabling the directions of electric fields applied to liquid crystal capacitor elements to be inverted. As a result, the drive voltages of the data driver can be made a half of those in the conventional case, which is effective in reducing the power consumption.
Further, the employment of the invention is advantageous also in the driving circuit of the scan driver and the transistors used in the active matrix circuit.
For example, in an active matrix circuit (see FIG. 7) employing the conventional driving method, if the potential of the electrode of the opposed substrate (or common lines) is set at a constant value, for instance, 0 V, and the variation range of the data for image display is 0 to 5 V, the potential of data that is output from the data driver varies from +5 V to −5 V (variation range: 10 V). That is, the source-drain potential difference of the transistors amounts to 10 V at the maximum.
Further, to keep the transistors in an on-state during selection periods in a reliable manner, the gate electrode potential of the transistors needs to be higher than +5+Vth V.
In the above description of the embodiments, it is assumed that the threshold voltage Vth is +0.5 V and the margin is 1.5 V. Under the same conditions, the potentials to keep an off-state and an on-state should be −6 V and +7 V, respectively. In this case, the maximum source-drain potential difference and the maximum gate-source (or gate-drain) potential difference of the switching transistors amount to 10 V and 12 V, respectively. It is understood that an unduly heavy load as compared to the voltage (5 V) required from image information is imposed on the switching transistors. For this reason, high-breakdown-voltage transistors need to be used in the active matrix circuit.
The scan driver is also required to produce voltages ranging from −6 V to +7 V, i.e., having a potential difference (selection pulse height) of 13 V, which is unduly large. Further, the output potential difference of the data driver is 10 V.
In contrast, according to the invention, even if the same transistors are used to perform the same display as in the above case, the potential variation of data is from 0 V to 5 V (potential difference: 5 V) and the potential of the data line can be kept of the same polarity, as described in the above embodiments. Further, to keep the transistors in an off-state during non-selection periods in a stable manner, the gate electrode potential of the transistors may be set at about −1 V. To keep the transistors in an on-state during selection periods in a reliable manner, the gate electrode potential may be set at about +7 V. That is, the output potential difference (selection pulse height) of the scan driver is 8 V.
That is, according to the invention, the switching transistors of the active matrix circuit have the maximum source-drain potential difference of 5 V and the maximum gate-source (or gate-drain) potential difference of 7 V, for instance. The latter value is much smaller than the potential difference 12 V of the conventional case. Although the 5 V-decrease in potential difference may not appear to provide remarkable effects, it can sufficiently reduce the load of the transistors; that is, it is very effective in increasing the yield of transistors.
Experiments of the present inventors have proved that where a 1,200-Å-thick silicon oxide film is used as the gate insulating film, a very small number of transistors are broken when the gate-source voltage is smaller than 10 V, whereas once the gate-source voltage exceeds 10 V the number of broken transistors increases exponentially with every 1 V-increment. Thus, to make the gate-source voltage smaller than 10 V is very meaningful from the industrial viewpoint.
As described above, the invention enables the driving in which the potential of data varies from 0 V to 5 V, which means that the potential variation range is 5 V and the potential of the data line has a single polarity.
As a result, the invention allows the data driver to produce signals of a single polarity, in contrast to the fact that conventionally the data driver needs to supply polarity-inverting signals to the data lines to effect alternating.
Further, according to the invention, the height of selection pulses that are output from the scan driver is 8 V, which is smaller than the conventional value of 13 V. This means reduction in the load of the scan driver.
Thus, the invention can reduce the power consumption not only in the data driver but also in the scan driver, and can also reduce the load of the transistors used in the active matrix circuit. In particular, as long as the latter item is concerned, even transistors of a little low in quality are allowed to operate with sufficient performance.
The fact that the output voltages of the scan driver and the data driver can be reduced means that the load of the transistors used therein can also be reduced. This is particularly effective in what is called a monolithic active matrix circuit in which the scan driver and the data driver are incorporated in the same substrate as the active matrix circuit in an integral manner. This is because in a monolithic active matrix circuit thin-film transistors are generally used in the scan driver and the data driver as in the active matrix circuit and the thin-film transistors have a weakness of a low breakdown voltage.
Further, the reduction in selection pulse height leads to a reduction in the pixel-side voltage drop that is caused at the time of switching by the existence of a parasitic capacitor of the switching transistor (what is called a feedthrough voltage). This is because this voltage drop is proportional to the selection pulse height.
Although the above embodiments are directed to the case where n-channel transistors (NMOS transistors) are used, it goes without saying that the driving can be performed in the same manner even with p-channel transistors (PMOS transistors). Further, although the above embodiments are directed to the case of in-plane switching (IPS) mode, the present invention is not limited for the IPS device. Exhibiting various advantages when applied to active matrix liquid crystal display devices as described above, the invention is very useful from the industrial viewpoint.
wherein said potential Vp to said data line Pm satisfies a condition VL≦Vp≦VH.
2. A method according to claim 1, wherein said active matrix display device is operated by a field inverting mode.
3. A method according to claim 1, wherein said common line Yn is kept at said potential VH or VL during 80% or more of one field period.
4. A method according to claim 1, wherein said common line Yn is kept at said potential VH or VL during 95% or more of one field period.
5. A method according to claim 1, wherein both of said potentials VH and VL are lower than a threshold voltage of a liquid crystal material included in said active matrix display device.
6. A method according to claim 1, wherein said data line, scan line, common line and pixel electrode are formed over a substrate.
7. A method according to claim 1, wherein said potential Vp to said data line Pm produces signals of a single polarity.
9. A method according to claim 8 wherein said potentials VH, VC, and VL satisfy an inequality, VH>VC>VL.
10. A method according to claim 8, wherein said active matrix display device is operated by a field inverting mode.
11. A method according to claim 8, wherein said common line Yn is kept at said potential VH or VL during 80% or more of one field period.
12. A method according to claim 8, wherein said common line Yn is kept at said potential VH or VL during 95% or more of one field period.
13. A method according to claim 8, wherein both of said potentials VH and VL are lower than a threshold voltage of a liquid crystal material included in said active matrix display device.
14. A method according to claim 8, wherein said data line, scan line, common line and pixel electrode are formed over a substrate.
15. A method according to claim 8, wherein said potential Vp to said data line Pm produces signals of a single polarity.
17. A method according to claim 16, wherein said active matrix display device is operated by a field inverting mode.
18. A method according to claim 16, wherein said common line Yn is kept at said potential (Voffset+Vamp) or −Voffset to be superimposed on said potential Vp during 80% or more of one field period.
19. A method according to claim 16, wherein said common line Yn is kept at said potential (Voffset+Vamp) or −Voffset to be superimposed on said potential VP during 95% or more of one field period.
20. A method according to claim 16, wherein said potential VY for said common line Yn is lower than a threshold voltage of a liquid crystal material included in said active matrix display device.
21. A method according to claim 16, wherein said potential Vp to said data line Pm produces signals of a single polarity.
23. A method according to claim 22, wherein said active matrix display device is operated by a field inverting mode.
24. A method according to claim 22, wherein said common line Yn is kept at said potential VH or VL during 80% or more of one field period.
25. A method according to claim 22, wherein said common line Yn is kept at said potential VH or VL during 95% or more of one field period.
26. A method according to claim 22, wherein both of said potentials VH and VL are lower than a threshold voltage of a liquid crystal material included in said active matrix display device.
27. A method according to claim 22, wherein said potential Vp to said data line Pm produces signals of a single polarity.
29. A method according to claim 28, wherein said potentials VH, VC, and VL satisfy an inequality, VH>VC>VL.
30. A method according to claim 28, wherein said active matrix display device is operated by a field inverting mode.
31. A method according to claim 28, wherein said common line Yn is kept at said potential VH or VL during 80% or more of one field period.
32. A method according to claim 28, wherein said common line Yn is kept at said potential VH or VL during 95% or more of one field period.
33. A method according to claim 28, wherein both of said potentials VH and VL are lower than a threshold voltage of a liquid crystal material included in said active matrix display device.
34. A method according to claim 28, wherein said potential Vp to said data line Pm produces signals of a single polarity.
36. A method according to claim 35, wherein said active matrix display device is operated by a field inverting mode.
37. A method according to claim 35, wherein said common line Yn is kept at said potential VH or VL during 80% or more of one field period.
38. A method according to claim 35, wherein said common line Yn is kept at said potential VH or VL during 95% or more of one field period.
39. A method according to claim 35, wherein said potential VY for said common line Yn is lower than a threshold voltage of a liquid crystal material included in said active matrix display device.
40. A method according to claim 35, wherein said potential Vp to said data line Pm produces signals of a single polarity.

References: V. 
 V. 
 V. 
 V. 
 V.

 V. 
 V. 
 V.

 V. 
 V.

 V. 
 V. 
 V.

 V.