Source: https://www.itiv.kit.edu/english/21_53.php
Timestamp: 2019-04-26 06:43:07+00:00

Document:
Since 2001 Juergen Becker is professor for embedded electronic systems at the Institut fuer Technik der Informationsverarbeitung (ITIV) at the University of Karlsruhe. He gives lectures in digital design (undergraduate), in CAD algorithms for high-level synthesis and VLSI design, hardware/software codesign, as well as in bus interfaces and protocols. His actual research is focused on industrial-driven SoCs with emphasis on adaptive embedded systems, e.g. dynamically reconfigurable hardware architectures. This includes corresponding hardware/software codesign and co-synthesis techniques from high-level specifications, as well as low power SoC optimization. Prof. Becker is co-director of the Embedded Systems and Sensors Engineering (ESS) group at the Computer Science Research Center (FZI).
He is author and co-author of more than 400 scientific papers (+ more than 30 patents), published in peer-reviewed international journals and conferences and active in several technical program and steering committees of international conferences and workshops. Prof. Becker started in October 2004 as Vice President of Universität Karlsruhe (TH) responsible for the area Studies and Teaching, respectively since October 2009 to March 2012 as Chief Higher Education Officer (CHEO) of the KIT.
From 2012 until 2014 he serves as Secretary General of CLUSTER, an association of 12 leading technical universities in Europe. In 2013 Prof. Becker received the Honorary Doctor award (Dr. h. c.) from Technical University Budapest (Hungary).
Automated Assessment of E/E-Architecture Variants Using an Integrated Model- and Simulation-Based Approach.
Bucher, H.; Neubauer, K.; Becker, J.
Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II.
Bucher, H.; Kamm, S.; Becker, J.
Advances in Avionic Platforms : Multi-Core Systems [in press].
Durak, U. D.; Becker, J.; Hartmann, S.; Voros, N. S.
Using simulation techniques within the design of a reconfigurable architecture for fail-operational real-time automotive embedded systems.
Oszwald, F.; Obergfell, P.; Traub, M.; Becker, J.
Becker, J.; Prasanna, V. K.; Weimer, M.; Luk, W.; Aasaraai, K.; Chiou, D.
Dynamic reconfiguration for real-time automotive embedded systems in fail-operational context.
Oszwald, F.; Becker, J.; Obergfell, P.; Traub, M.
Data Reduction and Readout Triggering in Particle Physics Experiments Using Neural Networks on FPGAs [in press].
Baehr, S.; Kempf, F.; Becker, J.
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks [in press].
A Content-Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique [in press].
Harbaum, T.; Balzer, M.; Becker, J.; Weber, M.
Electric Circuit- and Wiring Harness-Aware Behavioral Simulation of Model-Based E/E-Architectures at System Level.
The ARAMiS Project Initiative : Multicore Systems in Safety- and Mixed-Critical Applications.
Becker, J.; Bapp, F. K.
Control Flow Analysis for Embedded Multi-Core Hybrid Systems.
Hoppe, A. W.; Kastensmidt, F. L.; Becker, J.
Foreword to the Special Section on Reconfigurable Computing.
Derrien, S.; Atasu, K.; Cardoso, J. M. P.; Becker, J.
A Timing Synchronizer System for Beam Test Setups Requiring Galvanic Isolation.
Meder, L. D.; Emschermann, D.; Frühauf, J.; Müller, W. F. J.; Becker, J.
A neural network on FPGAs for the z-vertex track trigger in Belle II.
Bähr, S.; Skambraks, S.; Neuhaus, S.; Kiesling, C.; Becker, J.
A versatile small form factor twisted-pair TFC FMC for MTCA AMCs.
Meder, L.; Lebedev, J.; Becker, J.
Ablyazimov, T.; Abuhoza, A.; Adak, R. P.; Adamczyk, M.; Agarwal, K.; Aggarwal, M. M.; Ahammed, Z.; Ahmad, F.; Ahmad, N.; Ahmad, S.; Akindinov, A.; Akishin, P.; Akishina, E.; Akishina, T.; Akishina, V.; Akram, A.; Al-Turany, M.; Alekseev, I.; Becker, K.-H.; Becker, J.; u. a.
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
Harbaum, T.; Schade, C.; Damschen, M.; Tradowsky, C.; Bauer, L.; Henkel, J.; Becker, J.
The NOVA project: maximizing beam time efficiency through synergistic analyses of SRμCT data.
Schmelzle, S.; Heethoff, M.; Heuveline, V.; Lösel, P.; Becker, J.; Beckmann, F.; Schluenzen, F.; Hammel, J. U.; Kopmann, A.; Mexner, W.; others.
Energy efficient scientific computing on FPGAs using OpenCL.
Weller, D.; Oboril, F.; Lukarski, D.; Becker, J.; Tahoori, M.
An Integrated Approach Enabling Cross-Domain Simulation of Model-Based E/E-Architectures.
Bucher, H.; Reichmann, C.; Becker, J.
Providing fault tolerance through invasive computing.
Lari, V.; Weichslgartner, A.; Tanase, A.; Witterauf, M.; Khosravi, F.; Teich, J.; Heißwolf, J.; Friederich, S.; Becker, J.
A signal distribution board for the timing and fast control master of the CBM experiment.
Meder, L.; Dreschmann, M.; Sander, O.; Becker, J.
A V2X Message Evaluation Methodology and Cross-Domain Modelling of Safety Applications in V2X-enabled E/E-Architectures.
Bucher, H.; Buciuman, M.-F.; Klimm, A.; Sander, O.; Becker, J.
Efficient task spawning for shared memory and message passing in many-core architectures.
Zaib, A.; Wild, T.; Herkersdorf, A.; Heisswolf, J.; Becker, J.; Weichslgartner, A.; Teich, J.
A framework for porting the NeuroBayes machine learning algorithm to FPGAs.
Baehr, S.; Sander, O.; Heck, M.; Feindt, M.; Becker, J.
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography.
Birk, M.; Kretzek, E.; Figuli, P.; Weber, M.; Becker, J.; Ruiter, N. V.
An introductory microcontroller programming laboratory course for first-year students.
Nürnberg, T.; Beuth, T.; Becker, J.; Leon, F. P.
SoC design methods and algorithms II.
Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication.
Tutorial 2A: 3D integration - challenges and advantages.
Adaptive Bandwidth Router for 3D Network-on-Chips.
Friederich, S.; Lehmann, N.; Becker, J.
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems.
Tradowsky, C.; Cordero, E.; Orsinger, C.; Vesper, M.; Becker, J.
Power Management Controller for Online Power Saving in Network-on-Chips.
Friederich, S.; Neber, M.; Becker, J.
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment.
Harbaum, T.; Seboui, M.; Balzer, M.; Becker, J.; Weber, M.
Meder, L.; Emschermann, D.; Frühauf, J.; Muller, W. F. J.; Becker, J.
Parallelization of genetic algorithms for sorting permutations by reversals over biological data.
Soncco-Álvarez, J. L.; Almeida, G. M.; Becker, J.; Ayala-Rincón, M.
Online-Analysis of Hits in the Belle-II Pixeldetector for Separation of Slow Pions from Background.
Baehr, S.; Sander, O.; Heck, M.; Pulvermacher, C.; Feindt, M.; Becker, J.
Ultra-Dense, Single-Wavelength DFT-Spread OFDMA PON with Laserless 1.2 Gb/s ONU Ready for Silicon Photonics Integration.
Schindler, P. C.; Agmon, A.; Wolf, S.; Bonk, R.; Meder, L.; Meltsin, M.; Ludwig, A.; Schmogrow, R.; Dreschmann, M.; Meyer, J.; Becker, J.; Nazarathy, M.; Ben-Ezra, S.; Pfeiffer, T.; Freude, W.; Leuthold, J.; Koos, C.
Network Interface with Task Spawning Support for NoC-Based DSM Architectures.
Zaib, A.; Heißwolf, J.; Weichslgartner, A.; Wild, T.; Teich, J.; Becker, J.; Herkersdorf, A.
Weichslgartner, A.; Heisswolf, J.; Zaib, A.; Wild, T.; Herkersdorf, A.; Becker, J.; Teich, J.
A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.
Dreschmann, M.; Heisswolf, J.; Geiger, M.; Haußecker, M.; Becker, J.
Becker, J.; Eguro, K.; Gohringer, D.; Luk, W.; Santambrogio, M. D.; Vaidyanathan, R.; Wilton, S.
Multiplier-free carrier-phase recovery for real-time receivers using processing in polar coordinates.
Baeuerle, B.; Josten, A.; Abrecht, F.; Dornbierer, E.; Boesser, J.; Dreschmann, M.; Becker, J.; Leuthold, J.; Hillerkuss, D.
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip.
Werner, S.; Stiehle, B.; Becker, J.
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.
Figuli, P.; Tradowsky, C.; Martinez, J.; Sidiropoulos, H.; Siozios, K.; Stenschke, H.; Soudris, D.; Becker, J.
A distributed simulation platform using HLA for complex embedded systems design.
Brito, A. V.; Bucher, H.; Oliveira, H.; Costa, L. F. S.; Sander, O.; Melcher, E. U. K.; Becker, J.
Power estimation of an ECDSA core applied in V2X scenarios using heterogeneous distributed simulation.
Bucher, H.; Klimm, A.; Sander, O.; Becker, J.
Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs.
Meder, L.; Schindler, P. C.; Agmon, A.; Meltsin, M.; Bonk, R.; Meyer, J.; Dreschmann, M.; Tolmachev, A.; Hilgendorf, R.; Nazarathy, M.; Ben-Ezra, S.; Pfeiffer, T.; Freude, W.; Leuthold, J.; Koos, C.; Becker, J.
Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors.
Azambuja, J. R.; Kastensmidt, F.; Becker, J.
GPU-based iterative transmission reconstruction in 3D ultrasound computer tomography.
Birk, M.; Dapp, R.; Ruiter, N. V.; Becker, J.
Demonstration of an SOA-assisted open metro-access infrastructure for heterogeneous services.
Schmuck, H.; Bonk, R.; Poehlmann, W.; Haslach, C.; Kuebart, W.; Karnick, D.; Meyer, J.; Fritzsche, D.; Weis, E.; Becker, J.; Freude, W.; Pfeiffer, T.
Real-time Nyquist signaling with dynamic precision and flexible non-integer oversampling.
Schmogrow, R.; Meyer, M.; Schindler, P. C.; Nebendahl, B.; Dreschmann, M.; Meyer, J.; Josten, A.; Hillerkuss, D.; Ben-Ezra, S.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography.
Birk, M.; Zapf, M.; Balzer, M.; Ruiter, N.; Becker, J.
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.
Heisswolf, J.; Zaib, A.; Weichslgartner, A.; Karle, M.; Singh, M.; Wild, T.; Teich, J.; Herkersdorf, A.; Becker, J.
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor.
Tradowsky, C.; Gadeke, T.; Bruckschlogl, T.; Stork, W.; Muller-Glaser, K.-D.; Becker, J.
A Simulation Tool Chain for Investigating Future V2X-based Automotive E/E Architectures.
Roth, C.; Bucher, H.; Brito, A.; Sander, O.; Becker, J.
Towards Dynamic Cache and Bandwidth Invasion.
Tradowsky, C.; Schreiber, M.; Vesper, M.; Domladovec, I.; Braun, M.; Bungartz, H.-J.; Becker, J.
Becker, J.; Bruckschloegl, T.; Oey, O.; Stripf, T.; Goulas, G.; Raptis, N.; Valouxis, C.; Alefragis, P.; Voros, N. S.; Gogos, C.
Ultra-dense, single-wavelength DFT-spread OFDM PON with laserless 1 Gb/s ONU at only 300 MBd per spectral group.
Schindler, P. C.; Agmon, A.; Wolf, S.; Bonk, R.; Meder, L.; Meltsin, M.; Ludwig, A.; Becker, J.; Nazarathy, M.; Ben-Ezra, S.; Pfeiffer, T.; Freude, W.; Leuthold, J.; Koos, C.
Heisswolf, J.; Zaib, A.; Zwinkau, A.; Kobbe, S.; Weichslgartner, A.; Teich, J.; Henkel, J.; Snelting, G.; Herkersdorf, A.; Becker, J.
Embedded Systems Start-Up Under Timing Constraints on Modern FPGAs.
Meyer, J.; Noguera, J.; Hübner, M.; Stewart, R.; Becker, J.
HETA: Hybrid error-detection technique using assertions.
Azambuja, J. R.; Altieri, M.; Becker, J.; Kastensmidt, F. L.
Stripf, T.; Oey, O.; Bruckschloegl, T.; Becker, J.; Rauwerda, G.; Sunesen, K.; Goulas, G.; Alefragis, P.; Voros, N. S.; Derrien, S.; Sentieys, O.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Kritharidis, D.; Mitas, N.; Perschke, T.
Colorless FDMA-PON with flexible bandwidth allocation and colorless, low-speed ONUs.
Schindler, P. C.; Schmogrow, R.; Dreschmann, M.; Meyer, J.; Tomkos, I.; Prat, J.; Krimmel, H.-G.; Pfeiffer, T.; Kourtessis, P.; Ludwig, A.; Karnick, D.; Hillerkuss, D.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
Novel Techniques for Smart Adaptive Multiprocessor SoCs.
Ost, L.; Garibotti, R.; Sassatelli, G.; Marchesan Almeida, G.; Busseuil, R.; Butko, A.; Robert, M.; Becker, J.
Providing multiple hard latency and throughput guarantees for packet switching networks on chip.
Heisswolf, J.; König, R.; Kupper, M.; Becker, J.
Reliable and adaptive network-on-chip architectures for cyber physical systems.
Göhringer, D.; Meder, L.; Oey, O.; Becker, J.
Virtual networks - distributed communication resource management.
Heisswolf, J.; Zaib, A.; Weichslgartner, A.; König, R.; Wild, T.; Teich, J.; Herkersdorf, A.; Becker, J.
JITPR: A framework for supporting fast application’s implementation onto FPGAs.
Sidiropoulos, H.; Siozios, H.; Figuli, P.; Soudris, D.; Hübner, M.; Becker, J.
Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms.
An FPGA-based multi-core approach for pipelining computing stages.
Azarian, A.; Cardoso, J. M. P.; Werner, S.; Becker, J.
Development and evaluation of distributed simulation of embedded systems using ptolemy and HLA.
Brito, A. V.; Negreiros, A. V.; Roth, C.; Sander, O.; Becker, J.
Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation.
Heisswolf, J.; Singh, M.; Kupper, M.; König, R.; Becker, J.
A Platform-Independant Runtime Methodology for Mapping Multiple Applications onto FPGAs through Resource Virtualization.
Sidiropoulos, H.; Figuli, P.; Siozos, K.; Soudris, D.; Becker, J.
Addiguration: Exploring configuration behavior of Spartan-3 devices.
Dreschmann, M.; Sander, O.; Klimm, A.; Roth, C.; Becker, J.
Parallelization and virtualization of genetic algorithms for sorting permutations by reversals.
Soncco-Ãlvarez, J. L.; Almeida, G. M.; Becker, J.; Ayala-Rincon, M.
Goulas, G.; Valouxis, C.; Alefragis, P.; Voros, N. S.; Gogos, C.; Oey, O.; Stripf, T.; Bruckschloegl, T.; Becker, J.; El Moussawi, A.; Naullet, M.; Yuki, T.
A New Approach to Model-Based Development for Audio Signal Processing.
Tradowsky, C.; Figuli, P.; Seidenspinner, E.; Held, F.; Becker, J.
Hardware Supported Adaptive Data Collection for Networks on Chip.
Heisswolf, J.; Weichslgartner, A.; Zaib, A.; Konig, R.; Wild, T.; Herkersdorf, A.; Teich, J.; Becker, J.
Hybrid interconnect design for heterogeneous hardware accelerators.
Pham-Quoc, C.; Heisswolf, J.; Werner, S.; Al-Ars, Z.; Becker, J.; Bertels, K.
LImbiC: An adaptable architecture description language model for developing an application-specific image processor.
Tradowsky, C.; Harbaum, T.; Deyerle, S.; Becker, J.
Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud.
Marchesan Almeida, G.; Bellaver Longhi, O.; Bruckschloegl, T.; Hubner, M.; Hessel, F.; Becker, J.
A novel system on chip for software-defined, high-speed OFDM signal processing.
Meyer, J.; Dreschmann, M.; Karnick, D.; Schindler, P. C.; Freude, W.; Leuthold, J.; Becker, J.
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections.
Zaib, A.; Heisswolf, J.; Weichslgartner, A.; Wild, T.; Teich, J.; Becker, J.; Herkersdorf, A.
Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers.
Heisswolf, J.; Bischof, S.; Ruckauer, M.; Becker, J.
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores.
Figuli, P.; Tradowsky, C.; Gaertner, N.; Becker, J.
Flexible WDM-PON with Nyquist-FDM and 31.25 Gbit/s per Wavelength Channel using Colorless, Low-Speed ONUs.
Schindler, P. C.; Schmogrow, R. M.; Dreschmann, M.; Meyer, J.; Hillerkuss, D.; Tomkos, I.; Prat, J.; Krimmel, H.-.. G.; Pfeiffer, T.; Kourtessis, P.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
Demonstration of SOA-assisted open metro-access infrastructure for heterogeneous services.
Schmuck, H.; Bonk, R.; Haslach, C.; Kuebart, W.; Karnick, D.; Meyer, J.; Poehlmann, W.; Fritzsche, D.; Weis, E.; Becker, J.; Freude, W.; Pfeiffer, T.
Processor Solutions for Smart Mobility.
Becker, J.; Sander, O.; Roth, C.
Adaptive Multiclient Network-on-Chip Memory Core : Hardware Architecture, Software Abstraction Layer, and Application Exploration.
Göhringer, D.; Meder, L.; Werner, S.; Oey, O.; Becker, J.; Hübner, M.
A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware.
Azambuja, J. R.; Pagliarini, S.; Altieri, M.; Kastensmidt, F. L.; Huebner-Glaser, M.; Becker, J.; Foucard, G.; Velazco, R.
Stripf, T.; Oey, O.; Bruckschloegl, T.; Koenig, R.; Becker, J.; Goulas, G.; Alefragis, P.; Voros, N. S.; Potman, J.; Sunesen, K.; Derrien, S.; Sentieys, O.
Goulas, G.; Alefragis, P.; Voros, N. S.; Valouxis, C.; Gogos, C.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Goehringer, D.; Derrien, S.; Menard, D.; Sentieys, O.; Huebner, M.; Stripf, T.; Oey, O.; Becker, J.; Rauwerda, G.; Sunesen, K.; Kritharidis, D.; Mitas, N.
Becker, J.; Stripf, T.; Oey, O.; Huebner, M.; Derrien, S.; Menard, D.; Sentieys, O.; Rauwerda, G.; Sunesen, K.; Kavvadias, N.; Masselos, K.; Goulas, G.; Alefragis, P.; Voros, N. S.; Kritharidis, D.; Mitas, N.; Goehringer, D.
On Designing Self-Aware Reconfigurable Platforms.
Siozios, K.; Sidiropoulos, H.; Diamantopoulos, D.; Figuli, P.; Soudris, D.; Huebner, M.; Becker, J.
Hardware/Software Virtualization for the Reconfigurable Multicore Platform.
Ferger, M.; Kadi, A.; Koedam, M.; Huebner, M.; Sinha, S.; Goossens, K.; Almeida, G.; Azambuja, J. R.; Becker, J.
Determination of On-Chip Temperature Gradients on Reconfigurable Hardware.
Tradowsky, C.; Cordero, E.; Deuser, T.; Huebner, M.; Becker, J.
FPGA based System-on-Chip Solution for Compensation of aging Motor Parameters of two Phase Hybrid Stepper Motors.
Dahm, N.; Hagner, M.; Huebner, M.; Becker, J.
Hardware prototyping of novel invasive multicore architectures.
Becker, J.; Friederich, S.; Heisswolf, J.; Koenig, R.; May, D.
FPGA System-on-Chip Solution for a Field Oriented Hybrid Stepper Motor Control.
Dahm, N.; Huebner, M.; Becker, J.
On Dynamic Run-Time Processor Pipeline Reconfiguration.
Tradowsky, C.; Thoma, F.; Huebner, M.; Becker, J.
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture.
A Scalable NoC Router Design Providing QoS Support using Weighted Round Robin Scheduling.
Heisswolf, J.; Koenig, R.; Becker, J.
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture.
Stripf, T.; Koenig, R.; Becker, J.
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files.
Huebner, M.; Goehringer, D.; Tradowsky, C.; Henkel, J.; Becker, J.
Ultra high speed digital down converter design for Virtex-6 FPGAs.
Meyer, J.; Menzel, S.; Dreschmann, M.; Schmogrow, R.; Hillerkuss, D.; Freude, W.; Leuthold, J.; Becker, J.
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.
Werner, S.; Oey, O.; Goehringer, D.; Huebner, M.; Becker, J.
Towards Design and Integration of a Vehicle-to-X based Adaptive Cruise Control.
Sander, O.; Roth, C.; Glas, B.; Becker, J.
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures.
Lemonnier, F.; Millet, P.; Almeida, G. M.; Hubner, M.; Becker, J.; Pillement, S.; Sentieys, O.; Koedam, M.; Sinha, S.; Goossens, K.; Piguet, C.; Morgan, M.-N.; Lemaire, R.
Stripf, T.; Oey, O.; Bruckschloegl, T.; Koenig, R.; Huebner, M.; Becker, J.; Goulas, G.; Alefragis, P.; Voros, N. S.; Rauwerda, G.; Sunesen, K.; Derrien, S.; Menard, D.; Sentieys, O.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Goehringer, D.; Perschke, T.; Kritharidis, D.; u. a.
Xilinx tools facilitate development of FPGA applications for IEC61508.
Corradi, G.; Girardey, R.; Becker, J.
Fine grain fault tolerance - A key to high reliability for FPGAs in space.
Niknahad, M.; Sander, O.; Becker, J.
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.
Heisswolf, J.; Zaib, A.; Weichslgartner, A.; Koenig, R.; Wild, T.; Teich, J.; Herkersdorf, A.; Becker, J.
Framework for dynamic verification of multi-domain virtual platforms in industrial automation.
Mendoza, F.; Pascal, J.; Nenninger, P.; Becker, J.
On demand dependent deactivation of automotive ECUs.
Schmutzler, C.; Simons, M.; Becker, J.
FPGA controlled DDS based frequency sweep generation of high linearity for FMCW radar systems.
Ayhan, S.; Vu-Duy, V.; Pahl, P.; Scherr, S.; Huebner, M.; Becker, J.; Zwick, T.
Quality metrics for optical signals: Eye diagram, OSNR, Q-factor, EVM and BER.
Freude, W.; Schmogrow, R.; Nebendahl, B.; Winter, M.; Josten, A.; Hillerkuss, D.; Koenig, S.; Meyer, J.; Dreschmann, M.; Huebner, M.; Koos, C.; Becker, J.; Leuthold, J.
Two Dimensional Dynamic Multigrained Reconfigurable Hardware.
REFLECT: Rendering FPGAs to Multi-Core Embedded Computing.
Cardoso, J. M. P.; Diniz, P. C.; Petrov, Z.; Bertels, K.; Hübner, M.; Van Someren, H.; Goncalves, F.; De Coutinho, J. G. F.; Constantinides, G. A.; Olivier, B.; Luk, W.; Becker, J.; Kuzmanov, G.; Thoma, F.; Braun, L.; Kühnle, M.; Nane, R.; Sima, V. M.; Kratky, K.; Alves, J. C.; u. a.
Smart Chips for Smart Surroundings - 4S.
Schueler, E.; Koenig, R.; Becker, J.; Rauwerda, G.; Burgwal, M.; Smit, G.
Multiprocessor System-on-Chip - Hardware Design and Tool Integration.
Huebner, M.; Becker, J. (Hrsg.).
Exploration of Power-Performance Tradeoffs through Parameterization of FPGA-based Multiprocessor Systems.
Goehringer, D.; Obie, J.; Braga, A.; Huebner, M.; Llanos, C.; Becker, J.
Fast Startup for Xilinx FPGAs.
Meyer, J.; Noguera, J.; Stewart, R.; Hübner, M.; Becker, J.
Operating System for Runtime Reconfigurable Multiprocessor Systems.
26 Tbit s-1 line-rate super-channel transmission utilizing all-optical fast Fourier transform processing.
Hillerkuss, D.; Schmogrow, R.; Schellinger, T.; Jordan, M.; Winter, M.; Huber, G.; Vallaitis, T.; Bonk, R.; Kleinow, P.; Frey, F.; Roeger, M.; Koenig, S.; Ludwig, A.; Marculescu, A.; Li, J.; Hoh, M.; Dreschmann, M.; Meyer, J.; Ben Ezra, S.; Becker, J.; u. a.
FPGA-Based Embedded Signal Processing for 3-D Ultrasound Computer Tomography.
Birk, M.; Koehler, S.; Balzer, M.; Huebner, M.; Ruiter, N. V.; Becker, J.
Evaluation of the reconfiguration of the data acquisition system for 3D USCT.
Birk, M.; Hagner, C.; Balzer, M.; Ruiter, N. V.; Hübner, M.; Becker, J.
Real-time OFDM transmitter beyond 100 Gbit/s.
Schmogrow, R. M.; Winter, M.; Hillerkuss, D.; Nebendahl, B.; Ben-Ezra, S.; Meyer, J.; Dreschmann, M.; Huebner, M.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
Reconfiguration Techniques for self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs.
Schuck, C.; Haetzer, B.; Becker, J.
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.
Meyer, J.; Noguera, J.; Huebner, M.; Braun, L.; Sander, O.; Gil, R. M.; Stewart, R.; Becker, J.
HLA-based Simulation Environment for distributed SystemC Simulation.
Roth, C.; Sander, O.; Kuehnle, M.; Becker, J.
Modular Framework for Multi-level Multi-device MPSoC Simulation.
Roth; Sander, O.; Almeida, G.; Ost, L.; Hebert, N.; Sassatelli, G.; Benoit, P.; Torres, L.; Becker, J.
A heterogeneous SoC Architecture with embedded virtual fpga Cores and Runtime core Fusion.
Figuli, P.; Hübner, M.; Girardey, R.; Bapp, F.; Bruckschloegl, T.; Thoma, F.; Henkel, J.; Becker, J.
101.5 Gbit/s Real-Time OFDM Transmitter with 16QAM Modulated Subcarriers.
Schmogrow, R.; Nebendahl, B.; Hillerkuss, D.; Meyer, J.; Dreschmann, M.; Huebner, M.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.; Winter, M.
Run-Time Resource Instantiation for Fault Tolerance in FPGAs.
Pereira, M.; Braun, L.; Huebner, M.; Becker, J.; Carro, L.
Implementation of an ultra-high speed 256-point FFT for Xilinx Virtex-6 devices.
Dreschmann, M.; Meyer, J.; Huebner, M.; Schmogrow, R.; Hillerkuss, D.; Becker, J.; Leuthold, J.; Freude, W.
Flexible and Efficient Co-Simulation of Networked Embedded Devices.
The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip.
Kuehnle, M.; Brito, A.; Roth, C.; Dagas, K.; Becker, J.
Meyer, J.; Noguera, J.; Huebner, M.; Stewart, R.; Becker, J.
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
Huebner, M.; Figuli, P.; Girardey, R.; Soudris, D.; Siozos, K.; Becker, J.
An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels.
Kuehnle, M.; Brito, A. V.; Roth, C.; Kruesselin, M.; Becker, J.
A statistical power estimation methodology embedded in a SystemC code translator.
Kuehnle, M.; Wagner, A.; Becker, J.
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors.
Koenig, R.; Stripf, T.; Heisswolf, J.; Becker, J.
A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.
A study on fine granular fault tolerance methodologies for FPGAs.
Niknahad, M.; Sandery, O.; Becker, J.
QFDR-an integration of Quadded Logic for modern FPGAs to tolerate high radiation effect rates.
FGTMR - Fine Grain Redundancy Method for Reconfigurable Architectures under high Failure Rates.
Using Quadded Logic in nanoPLAs to aggressively increase circuit yield.
Niknahad, M.; Sandery, O.; Carro, L.; Azambuja, J.; Becker, J.; KastenSmidt, F. L.
All-optical real-time OFDM transmitter and receiver.
Freude, W.; Hillerkuss, D.; Schellinger, T.; Schmogrow, R.; Winter, M.; Vallaitis, T.; Bonk, R.; Marculescu, A.; Li, J.; Dreschmann, M.; Meyer, J.; Ben Ezra, S.; Caspi, M.; Nebendahf, B.; Parmigiani, F.; Petropoiu, P.; Resan, B.; Oehler, A.; Weingarten, K.; Becker, J.; u. a.
Approach of an FPGA based adaptive stepper motor control system.
RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.
Goehringer, D.; Werner, S.; Huebner, M.; Becker, J.
Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip.
Goehringer, D.; Oey, O.; Huebner, M.; Becker, J.
Reconfigurable MPSoC versus GPU: Performance, power and energy evaluation.
Göhringer, D.; Birk, M.; Dasse-Tiyo, Y.; Ruiter, N.; Hübner, M.; Becker, J.
New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
Goehringer, D.; Meder, L.; Huebner, M.; Becker, J.
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors.
Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs.
Schuck, C.; Haetzer, B.; Huebner, M.; Becker, J.
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing.
Birk, M.; Guth, A.; Zapf, M.; Balzer, M.; Ruiter, N.; Hübner, M.; Becker, J.
A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker.
Ruemmele-Werner, M.; Perschke, T.; Braun, L.; Huebner, M.; Becker, J.
Power and performance optimization through MPI supported dynamic voltage and frequency scaling.
Thoma, F.; Hübner, M.; Göhringer, D.; Yilmaz, H. Ü.; Becker, J.
3rd Many-core Applications Research Community (MARC) Symposium. (KIT Scientific Reports ; 7598).
Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support.
Goehringer, D.; Huebner, M.; Becker, J.
Real-Time Software-Defined Multiformat Transmitter Generating 64QAM at 28 GBd.
Becker, J.; Dreschmann, M.; Huebner, M.; Meyer, J.; Schmogrow, R.; Hillerkuss, D.; Winter, M.; Nebendahl, B.; Koos, C.; Freude, W.; Leuthold, J.
Car-to-X Simulation Environment for Comprehensive Design Space Exploration Verification and Test.
Becker, J.; Roth, C.; Sander, O.; Huebner, M.
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems.
Kepa, K.; Morgan, F.; Kosciuszkiewicz, K.; Braun, L.; Huebner, M.; Becker, J.
Orthogonal frequency division multiplexing (OFDM) in photonic communications.
Freude, W.; Hillerkuss, D.; Schellinger, T.; Schmogrow, R.; Winter, M.; Vallaitis, T.; Bonk, R.; Marculescu, A.; Dreschmann, M.; Meyer, J.; Ezra, S. B.; Narkiss, N.; Nebendahl, B.; Parmigiani, F.; Petropoulos, P.; Resan, B.; Weingarten, K.; Ellermeyer, T.; Lutz, J.; Becker, J.; u. a.
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration.
Meyer, J.; Huebner, M.; Braun, L.; Sander, O.; Noguera, J.; Stewart, R.; Becker, J.
Performance, Accuracy, Power Consumption and Resource Utilization Analysis for Hardware / Software realized Artificial Neural Networks.
Braga, A.; Goehringer, D.; Llanos, C.; Obie, J.; Huebner, M.; Becker, J.
Semi-Automatic Toolchain for Reconfigurable Multiprocessor Systems-on-Chip: Architecture Development and Application Partitioning.
Becker, J.; Goehringer, D.; Huebner, M.; Benz, M.
CAP-OS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures.
Becker, J.; Huebner, M.; Goehringer, D.; Zeutebouo, E. N.
Fast dynamic and partial reconfiguration Data Path with low Hardware overhead on Xilinx FPGAs.
Becker, J.; Huebner, M.; Goehringer, D.; Noguera, J.
KAHRISMA: A Novel Hypermorphic Reconfigurable- Instruction-Set Multi-grained-Array Architecture.
Becker, J.; Koenig, R.; Stripf, T.; Bauer, L.; Henkel, J.; Shafique, M.; Ahmed, W.
A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.
High Performance Reconfigurable Multi-Processor-Based Computing on FPGAs.
Fast Sequential FPGA Startup based on Partial and Dynamic Reconfiguration.
Becker, J.; Huebner, M.; Meyer, J.; Sander, O.; Braun, L.; Noguera, J.; Stewart, R.
Reliability Analysis and Improvement in Nano Scale Design.
Becker, J.; Huebner, M.; Niknahad, M.
FPGA-based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications.
FPGA-based Embedded Signal Processing for 3D Ultrasound Computer Tomography.
Becker, J.; Birk, M.; Koehler, S.; Balzer, M.; Huebner, M.; Ruiter, N.
Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC.
Becker, J.; Goehringer, D.; Huebner, M.; Hugot-Derville, L.
Scenario extraction for a refined timing-analysis of automotive network topologies.
Becker, J.; Traub, M.; Streichert, T.; Krasovytskyy, O.
A Flexible Integrated Cryptoprocessor for Authentication Protocols based on Hyperelliptic Curve Cryptography.
Becker, J.; Klimm, A.; Haas, M.; Sander, O.
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware.
First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography.
Becker, J.; Huebner, M.; Birk, M.; Hagner, C.; Balzer, M.; Ruiter, N.
ISRC: a runtime system for heterogeneous reconfigurable architectures.
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/Virtex II-Pro FPGAs: A Case Study of Distributed Power Management.
Becker, J.; Schuck, C.; Haetzer, B.
Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors.
Becker, J.; Huebner, M.; Goehringer, D.; Obie, J.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551).
Hübner, M.; Lagadec, L.; Sander, O.
Huebner, M.; Becker, J.; Kuehnle, M.; Thoma, F.
The MORPHEUS Data Communication And Storage Infrastructure.
Kühnle, M.; Hübner, M.; Becker, J. , [u.a.].
Becker, J.; Huebner, M.; Braun, L.; Kepa, K.; Morgan, F.; Kosciuszkiewicz, K.
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing.
A Taxonomy of Reconfigurable Single/Multi-Processor Systems-on-Chip.
Huebner, M.; Becker, J.; Goehringer, D.; Perschke, T.
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture.
Image Processing exploiting new dimensions in reconfigurable multiprocessor systems (Invited Talk).
Goehringer, D.; Perschke, T.; Becker, J.
Multi-Processor-based High Performance Computing utilizing dynamic reconfigurable Hardware (PhD Poster).
Star-wheels network-on-chip featuring a self-adaptive mixed topology and a synergy of a circuit- and a packet-switching communication protocol.
Goehringer, D.; Liu, B.; Huebner, M.; Becker, J.
System concept for an FPGA based real-time capable automotive ECU simulation system.
Becker, J.; Sander, O.; Roth, C.; Stuckert, V.
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Becker, J.; Koenig, R.; Dreschmann, M.; Huebner, M.
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.
Becker, J.; Klimm, A.; Sander, O.
GenerateRCS: A High-Level Design Tool for Generating Reconfigurable Computing Systems.
Becker, J.; Goehringer, D.; Luhmann, J.
Method for improving performance in online routing of reconfigurable nano architectures.
A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing.
Kuehnle, M.; Huebner, M.; Becker, J. , [u.a.].
Dynamic Reconfigurable Mixed-Signal Architecture for Safety Critical Applications.
Girardey, R.; Hübner, M.; Becker, J.
Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.
Göhringer, D.; Liu, B.; Hübner, M.; Becker, J.
Multi-Processor-based High Performance Computing utilizing dynamic reconfigurable Hardware.
Image Processing exploiting new dimensions in reconfigurable multiprocessor systems.
Göhringer, D.; Perschke, T.; Becker, J.
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
Kuehnle, M.; Ries, F.; Huebner, M.; Becker, J. , [u.a.].
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.
Koenig, R.; Stripf, T.; Becker, J.
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.
Standards for Electric/Electronic Components and Architectures.
Becker, J.; Sander, O.; Huebner, M.; Traub, M.; Weber, T.; Luka, J.; Lauer, V.
Data Reallocation by Exploiting FPGA Configuration Mechanisms.
Sander, O.; Braun, L.; Huebner, M.; Becker, J.
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
Kuehnle, M.; Huebner, M.; Becker, J.; Deledda, A.; Mucci, C.; Ries, F.; Coppola, A. M.; Pieralisi, L.; Locatelli, R.; Maruccia, G.; DeMarco, T.; Campi, F.
An Optically Powered Video Camera Link.
Boettger, G.; Dreschmann, M.; Klamouris, C.; Huebner, M.; Rger, M.; Kueng, T.; Becker, J.; Freude, W.; Leuthold, J.
Current Trends on Reconfigurable Computing.
Becker, J.; Huebner, M.; Woods, R.; Long, P.; Esser, R.; Torres, L.
Towards Novel Approaches in Design Automation for FPGA Power Optimization.
Noguera, J.; Esser, R.; Paulsson, K.; Hübner, M.; Becker, J.
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain.
Huebner, M.; Becker, J.; Sander, O.; Traub, M.
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems.
Becker, J.; Huebner, M.; Esser, R.; Herkersdorf, A.; Stechele, W.; Lauer, V.
An Interface for a Decentralized 2d-Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing.
Dynamic Reconfiguration of Nano Architectures using Application Independent Fault Detection.
Niknahad, M.; Schuck, C.; Huebner, M.; Becker, J.
Depth First Traversal Algorithm for Efficient Build-in Self-Test in Nano Fabrics.
A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.
Klimm, A.; Sander, O.; Becker, J.; Subileau, S.
FPGA Based Stepper Motor Control Function Exploiting Run-Time Reconfiguration.
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.
Data path driven waveform-like reconfiguration.
Braun, L.; Paulsson, K.; Kromer, H.; Huebner, M.; Becker, J.
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
Claus, C.; Zhang, B.; Stechele, W.; Braun, L.; Huebner, M.; Becker, J.
New dimensions for multiprocessor architectures: On demand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
Goehringer, D.; Huebner, M.; Perschke, T.; Becker, J.
Thomas, A.; Becker, J. , [u.a.].
SPP1148 booth: Fine grain reconfigurable architectures.
Braun, L.; Schwalb, T.; Graf, P.; Hübner, M.; Becker, J. , [u.a.].
Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.
Morra, C.; Cardoso, J. M. P.; Bispo, J.; Becker, J.
A Web Server Based Edge Detector Implementation in FPGA.
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.
Paulsson, K.; Viereck, U.; Huebner, M.; Becker, J.
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era.
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.
Klimm, A.; Braun, L.; Becker, J.
A framework for dynamic 2D placement on FPGAs.
Schuck, C.; Kuehnle, M.; Huebner, M.; Becker, J.
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.
Huebner, M.; Braun, L.; Goehringer, D.; Becker, J.
Runtime adaptive multi-processor system-on-chip: RAMPSoC.
Goehringer, D.; Huebner, M.; Schatz, V.; Becker, J.
Becker, J.; Huebner, M.; Paulsson, K.; Esser, R.; Noguera, J.
Exploitation of Run-TIme Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems.
Paulsson, K.; Huebner, M.; Bayar, S.; Becker, J.
Dynamic and Partial FPGA Exploitation.
Becker, J.; Huebner, M.; Hettich, G.; Constapel, R.; Eisenmann, J.; Luka, J.
New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur).
Modulares Systemkonzept fur einen FPGA basierten Automotive Gateway = Modular system concept for FPGA-based Automotive Gateway.
Becker, J.; Huebner, M.; Sander, O.; Dreschmann, M.; Luka, J.; Traub, M.; Weber, T.
New tool support and architectures in adaptive reconfigurable computing.
Huebner, M.; Becker, J.; Donlin, A.
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
Braun, L.; Huebner, M.; Becker, J.; Perschke, T.; Schatz, V.; Bach, S.
H. 264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture.
Ganesan, M. K. A.; Singh, S.; May, F.; Becker, J.
On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the AETHER Project.
Paulsson, K.; Huebner, M.; Becker, J.; Philippe, J.-M.; Gamrat, C.
artNoC - A Novel Multi-Functional Router Architecture for Organic Computing.
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs.
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks.
A General Purpose Partially Reconfigurable Processor Simulator (PReProS).
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.
Morra, C.; Cardoso, J. M. P.; Becker, J.
Pionteck, T.; Albrecht, C.; Koch, R.; Maehle, E.; Huebner, M.; Becker, J.
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC.
Optically Powered Video Camera Link.
Boettger, G.; Huebner, M.; Klamouris, C.; Dreschmann, M.; Bett, A. W.; Becker, J.; Freude, W.; Leuthold, J.; Roeger, M.
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.
Huebner, M.; Braun, L.; Becker, J.
A System-on-Chip Audio Decoder - a Project oriented SoC Design for Education.
Kuehnle, M.; Koenig, R.; Thoma, F.; Becker, J.
A Mixed-Signal System-on-Chip Audio Decoder Design for Education.
Koenig, R.; Thomas, A.; Kuehnle, M.; Becker, J.; Crocoll, E.; Siegel, M.
Dynamic and Partial FPGA Self-Reconfiguration Using Real-Time LUT-Based Network-On-Chip Adaptive Topologies for Xilinx FPGAs.
Physical 2D Morphware and Power Reduction Methods for Everyone.
Becker, J.; Huebner, M.; Paulsson, K.
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.
Morra, C.; Sackmann, M.; Shukla, S.; Becker, J.; Hartenstein, R.
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs.
Huebner, M.; Schuck, C.; Becker, J.
Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems.
A high-level target-precise model for designing reconfigurable HW tasks.
Boden, M.; Rulke, S.; Becker, J.
Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration.
Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration manager.
Becker, J.; Benoit, P.; Torres, L.; Sassatelli, G.; Robert, M.; Cambon, G.
Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs.
Paulsson, K.; Huebner, M.; Jung, M.; Becker, J.
QUKU: a two-level reconfigurable architecture.
New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits.
Huebner, M.; Schuck, C.; Kuehnle, M.; Becker, J.
Realization of Real-Time Control Flow Oriented Automotive Applications on a Soft-core Multiprocessor System based on Xilinx Virtex II FPGAs.
Paulsson, K.; Hübner, M.; Zou, H.; Becker, J.
Using Rewriting Logic to Generate Differrent Implementations of Polynomial Approximations in Coarse-Grained Architectures.
Morra, C.; Sackmann, M.; Becker, J.; Hartenstein, R.
Optically Powered Video Camera Network.
Boettger, G.; Huebner, M.; Dreschmann, M.; Klamouris, C.; Paulsson, K.; Kueng, T.; Bett, A. W.; Becker, J.; Freude, W.; Leuthold, J.
Tutorial on Macro Design for Dynamic and Partially Reconfigurable Systems.
Seamless Design Flow for Run-Time Reconfigurable Automotive Systems.
On-Line Optimization of FPGA Power-Dissipation by Exploiting Run-time Adaption of Communication Primitives.
Run-time Reconfigurabilility and other Future Trends.
Exploiting Dynamic and Partial Reconfiguration for FPGAs - Toolflow, Architecture and System Integration.
Optically powered platform with Mb/s transmission over a single fiber.
Klamouris, C.; Boettger, G.; Huebner, M.; Dreschmann, M.; Paulsson, K.; Kueng, T.; Becker, J.; Freude, W.; Leuthold, J.
Dynamically Reconfigurable Hardware: "A promising Way to On-Line Diagnosis, Fault-Tolerance and Reliability.
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.
Becker, J.; Thomas, A.; Scheer, M.
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems.
Ullmann, M.; Jin, W.; Becker, J.
Scalable processor instruction set extension.
Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen.
Ullmann, M.; Becker, J.; Braendle, K.
Real-time configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation.
Huebner, M.; Ullmann, M.; Becker, J.
Paulsson, K.; Huebner, M.; Zou, H.; Becker, J.
Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs.
Huebner, M.; Paulsson, K.; Stitz, M.; Becker, J.
Models and Tools for the Dynamic Reconfiguration of FPGAs.
Donlin, A.; Huebner, M.; Becker, J.
Hardware Enhanced Function Allocation Management in Reconfigurable Systems.
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics.
Huebner, M.; Becker, J.; Paulsson, K.; Thomas, A.
Overview of the 4S Project.
Smit, G. J. M.; Schuler, E.; Becker, J.; Quevremont, J.; Brugger, W.
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.
Hübner, M.; Paulsson, K.; Stitz, M.; Becker, J.
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations.
Morra, C.; Becker, J.; Ayala-Rincon, M.; Hartenstein, R.
Hübner, M.; Becker, J.; Paulsson, K.; Thomas, A.
Multi-grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures.
Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment.
Multi-grained Reconfigurable Harware Architecture with Online-Adaptive Routing Techniques.
Design Of Optimized Reconfigurable HW Tasks Using Operation Graph Signatures.
Boden, M.; Ruelke, S.; Becker, J.
Field Programmable Logic and Application : 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings.
Becker, J.; Vernalde, S.; Platzner, M.
CARUSO - Project Goals and Principal Approach.
Brinkschulte, U.; Becker, J.; Dorfmueller-Ulhaas, H.; Koenig, R.; Uhrig, S.; Ungerer, T.
Brinkschulte, U.; Becker, J.; Dorfmüller-Ulhaas, H.; Koenig, R.; Uhrig, S.; Ungerer, T.
Real-time LUT-based Network Topologies for dynamic and partial FPGA Self-Reconfiguration.
Huebner, M.; Becker, T.; Becker, J.
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.
Ullmann, M.; Huebner, M.; Grimm, B.; Becker, J.
Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.
Huebner, M.; Ullmann, M.; Weissel, F.; Becker, J.
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration.
Ullmann, M.; Grimm, B.; Huebner, M.; Becker, J.
Dynamic Adaptive Routing Techniques In Multigrain Dynamic Reconfigurable Hardware Architectures.
Aufbau- und Strukturkonzepte einer adaptiven multigranularen rekonfigurierbaren Hardwarearchitektur.
Thomas, A.; Becker, J.; Heinkel, U.; Winkelmann, K.; Bormann, J.
Adaptive DMA-based I/O Interfaces for Data Stream Handling in Multi-grained Reconfigurable Hardware Architectures.
Thomas, A.; Zander, T.; Becker, J.
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
Huebner, M.; Ullmann, M.; Braun, L.; Klausmann, A.; Becker, J.
ARCS 2004 - Organic and pervasive computing : workshop proceedings; March 26, 2004, Augsburg.
Brinkschulte, U.; Becker, J.; Fey, D.; Grosspietsch, K.; Hochberger, C.; Maehle, E.; Runkler, T. (Hrsg.).
Field programmable logic and application - 14th international conference (FPL 2004), August 30 - September 1, 2004, Antwerp, Belgium; Proceedings.
ARCS 2004 - Organic and pervasive computing, March 26, 2004, Augsburg; Workshop Proceedings.
Configware and Morphware going Mainstream.
Becker, J.; Hartenstein, R. W.
Configurability for Systems on Silicon: Requirement and Perspective for future VLSI Solutions.
Configurable Systems-on-Chip: Necessity and Perspective for future Microelectronic Solutions.
Real-Time Dynamically Run: Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations.
An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XPP-/Leon-based architecture integration.
Becker, J.; Thomas, A.; Vorbach, M.; Baumgarte, V.
Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations.
Efficient processor instruction set extension by asynchronous reconfigurable datapath integration.
Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC).
Implementing real-time scheduling within a multithreaded Java microcontroller.
Uhrig, S.; Liemke, C.; Pfeffer, M.; Becker, J.; Brinkschulte, U.; Ungerer, T.
Rapid prototyping of FPGA based floating point DSP systems.
Ho, C. H.; Leong, M. P.; Leong, P. H. W.; Becker, J.; Glesner, M.
Configurable systems-on-chip: commercial and academic approaches.
Configurable systems-on-chip: challenges and perspectives for industry and universities.
Dynamically reconfigurable systems-on-chip: a core-based industrial/academic SoC synthesis project.
Becker, J.; Thomas, A.; Vorbach, M.; Ehlers, G.
Ho, C.; Leong, M.; Leong, P.; Becker, J.; Glesner, M.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’02).
Plaks, T.; Athanas, P.; [Hrsg.]; Arabnia, H. R.; Becker, J.; Gokhale, M.; Gorgon, M.; Platzner, M.; [Mitarb.].
Effiziente IP-basierte Abbildungsverfahren für dynamisch rekonfigurierbare Array-Architekturen.
Becker, J.; Pionteck, T.; Glesner, M.
Adaptive Systems-on-Chip: Architectures, Technologies and Applications.
Architectures, Technologies & CAD for Embedded Systems-on-Chip (SoC).
Efficient Mapping of pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
Becker, J.; Pionteck, T.; Liebau, N.; Glesner, M.
Technologies, Architectures, CAD and Applications of Complex Systems-on-Chip (SoC).
Glesner, M.; Becker, J.; Pionteck, T.
Simulation, Prototyping and Reconfigurable Hardware Realization of CDMA RAKE-Receiver Algorithms for Flexible Mobile Transceivers.
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.
Mukherjee, N.; Motgi, J.; Becker, J.; Friebe, A.; Habermann, C.; Glesner, M.
Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture.
Becker, J.; Pionteck, T.; Habermann, C.; Glesner, M.

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