Source: http://www.aece.ro/abstractplus.php?year=2016&number=4&article=7
Timestamp: 2019-04-19 18:48:50+00:00

Document:
Spatiotemporal Data Mining for Distribution Load Expansion, ARANGO, H. G., LAMBERT-TORRES, G., de MORAES, C. H. V., BORGES DA SILVA, L. E.
An Adaptive Sparse Algorithm for Synthesizing Note Specific Atoms by Spectrum Analysis, Applied to Music Signal Separation, AZAMIAN, M., KABIR, E., SEYEDIN, S., MASEHIAN, E.
Research and Implementation of a USB Interfaced Real-Time Power Quality Disturbance Classification System, GOK, M., SEFA, I.
FEM Based Multi-Criterion Design and Implementation of a PM Synchronous Wind Generator by Fully Coupled Co-Simulation, OCAK, C., UYGUN, D., TARIMER, I.
ZAGAN, I. , GAITAN, V. G.
No common words between the references section and the paper title.
A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
 M. Zimmer, D. Broman, C. Shaver, and E. A. Lee, "FlexPRET: A processor platform for mixed-criticality systems," in 20th IEEE Real-Time and Embedded Technology and Applications Symposium - RTAS, pp. 101-110, Apr. 2014.
 E. Dodiu and V. G. Gaitan, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - concept and theory of operation," in IEEE EIT International Conference on Electro-Information Technology, Indianapolis, USA, pp. 1-5, May 2012.
 V. G. Gaitan, N. C. Gaitan, and I. Ungurean, "CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1661-1674, Sept. 2015.
 J. Shawash and D. R. Selviah, "Real-Time Nonlinear Parameter Estimation Using the Levenberg-Marquardt Algorithm on Field Programmable Gate Arrays," IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 170-176, Jan. 2013.
 M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, "FPGA-Based Reconfigurable Control for Fault-Tolerant Back-to-Back Converter Without Redundancy," IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3360-3371, Aug. 2013.
 M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, "Fault-Tolerant Five-Leg Converter Topology With FPGA-Based Reconfigurable Control," IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 2284-2294, Jun. 2013.
 T. T. Phuong, K. Ohishi, Y. Yokokura, and C. Mitsantisuk, "FPGA-Based High-Performance Force Control System With Friction-Free and Noise-Free Force Observation," IEEE Trans. Ind. Electron., vol. 61, no. 2, pp. 994-1008, Feb. 2014.
 N. C. Gaitan, I. Zagan, and V. G. Gaitan, "Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation," International Journal of Advanced Computer Science and Applications - IJACSA, vol. 6, no. 4, 2015.
 A. Metzner and J. Niehaus, "MSparc: Multithreading in Real-Time Architectures," Journal of Universal Computer Science, vol. 6, no. 10, pp. 1034-1051, 2000.
 J. Kreuzinger, R. Marston, Th. Ungerer, U. Brinkschulte and C. Krakowski, "The Komodo project: thread-based event handling supported by a multithreaded Java microcontroller," in 25th EUROMICRO Conference, Milano, vol. 2, pp. 122-128, 1999.
 I. Zagan and V. G. Gaitan, "Schedulability Analysis of nMPRA Processor based on Multithreaded Execution," in 13rt International Conference on Development and Application Systems - DAS, Suceava, Romania, pp. 130-134, May 19-21, 2016.
 E. E Moisuc, A. B. Larionescu, and V. G. Gaitan, "Hardware Event Treating in nMPRA," in 12rt International Conference on Development and Application Systems - DAS, Suceava, Romania, pp. 66-69, 15-17 May, 2014.
 S. Kelinman and J. Eykholt, "Interrupts as threads," ACM SIGOPS Operating Syst. Rev., vol. 29, no. 2, pp. 21-26, Apr. 1995.
Citations for references updated on 2019-04-17 23:15 in 89 seconds.
Website conception, design and maintenance by Eugen COCA. Content updated on 28 Feb 2019. Site engine updated on 28 Feb 2019. This page was generated on the server in 0.059 seconds and loaded in your browser in > seconds.

References: V. 
 V. 
 V. 
 V. 
 V. 
 V.