CELEX: 31981R3744
Language: en
Date: 1981-12-07 00:00:00
Title: Council Regulation (EEC) No 3744/81 of 7 December 1981 concerning Community projects in the field of microelectronic technology

Avis juridique important

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31981R3744

Council Regulation (EEC) No 3744/81 of 7 December 1981 concerning Community projects in the field of microelectronic technology  

Official Journal L 376 , 30/12/1981 P. 0038

+++++( 1 ) OJ NO C 144 , 15 . 6 . 1981 , P . 69 .  ( 2 ) OJ NO C 353 , 31 . 12 . 1980 , P . 4 .  ( 3 ) OJ NO C 231 , 13 . 9 . 1979 , P . 1 .  COUNCIL REGULATION ( EEC ) NO 3744/81 OF 7 DECEMBER 1981 CONCERNING COMMUNITY PROJECTS IN THE FIELD OF MICROELECTRONIC TECHNOLOGY  THE COUNCIL OF THE EUROPEAN COMMUNITIES ,  HAVING REGARD TO THE TREATY ESTABLISHING THE EUROPEAN ECONOMIC COMMUNITY , AND IN PARTICULAR ARTICLE 235 THEREOF ,  HAVING REGARD TO THE PROPOSAL FROM THE COMMISSION ,  HAVING REGARD TO THE OPINION OF THE EUROPEAN PARLIAMENT ( 1 ) ,  HAVING REGARD TO THE OPINION OF THE ECONOMIC AND SOCIAL COMMITTEE ( 2 ) ,  WHEREAS MICROELECTRONIC TECHNOLOGY IS ESSENTIAL TO THE DEVELOPMENT AND COMPETITIVENESS OF COMMUNITY INDUSTRY AS A WHOLE AT A TIME WHEN THE EUROPEAN ECONOMY MUST INCREASINGLY PROVIDE HIGH ADDED VALUE GOODS AND SERVICES ; WHEREAS , HOWEVER , THE SCALE AND NATURE OF THE EFFORT NEEDED TO MATCH THAT OF ITS COMPETITORS BY 1985 REQUIRE A COMMUNITY APPROACH WHICH MUST INCLUDE PUBLIC FINANCIAL SUPPORT FOR COLLABORATIVE RESEARCH AND DEVELOPMENT BY INDUSTRY ; WHEREAS THE COUNCIL RESOLUTION OF 11 SEPTEMBER 1979 ( 3 ) INVITES THE COMMISSION TO EXAMINE THE POSSIBILITIES AND METHODS OF COORDINATING NATIONAL PROJECTS IN THIS SECTOR AND TO SUBMIT TO THE COUNCIL SPECIFIC PROJECTS AT COMMUNITY LEVEL WITH A VIEW TO PROMOTING MICROELECTRONIC TECHNOLOGY ;  WHEREAS THE AID GRANTED SHOULD AIM AT FURTHERING A BALANCED MARKET AND COMPETITION SITUATION IN EUROPE AND TAKE INTO CONSIDERATION THE PRINCIPLES EXPRESSED IN THE FOUR-YEAR PROGRAMMEME FOR THE DEVELOPMENT OF INFORMATICS IN THE COMMUNITY , AND IN PARTICULAR PRINCIPLES OF THE OWNERSHIP OF AND ACCESS TO RESULTS OF SUPPORTED PROJECTS , WITH PARTICULAR STRESS ON THE IMPORTANCE OF AN ADEQUATE DISSEMINATION OF GOODS AND OTHER RESULTS OF SUPPORTED PROJECTS ,  HAS ADOPTED THIS REGULATION :  ARTICLE 1  IN ORDER TO ATTAIN THE COMMUNITY OBJECTIVES CONCERNING MICROELECTRONIC TECHNOLOGY , COORDINATION AT COMMUNITY LEVEL OF THE ACTIVITIES UNDERTAKEN IN THE MEMBER STATES IN THIS DOMAIN AND IMPLEMENTATION OF JOINT PROJECTS TO SUPPLEMENT AND REINFORCE THESE ACTIVITIES SHALL BE CARRIED OUT UNDER THE CONDITIONS SET OUT IN THIS REGULATION .  FOR THE PURPOSES OF GRANTING NATIONAL FINANCIAL SUPPORT TO PROJECTS IN THE FIELDS DEFINED IN ARTICLE 3 , THE MEMBER STATES WILL IN PARTICULAR ENCOURAGE PROJECTS THE EXECUTION OF WHICH REQUIRES MAJOR PARTICIPATION ON THE PART OF ORGANIZATIONS FROM TWO OR MORE COMMUNITY COUNTRIES , OTHER CONDITIONS BEING EQUAL .  TITLE I  INFORMATION AND CONSULTATION  ARTICLE 2  A SYSTEM FOR INFORMATION AND CONSULTATION CONCERNING INITIATIVES AIMED AT PROMOTING THE DIFFUSION AND THE DEVELOPMENT OF MICROELECTRONIC TECHNOLOGY AND ITS APPLICATIONS IS HEREBY ESTABLISHED BETWEEN THE MEMBER STATES AND THE COMMISSION .  ARTICLE 3  1 . IN ORDER TO ENSURE THAT THE CONSULTATIONS PROVIDED FOR IN THIS REGULATION ARE EFFECTIVE , MEMBER STATES SHALL , INDEPENDENTLY OF THEIR OBLIGATIONS UNDER THE RULES OF COMPETITION , SUPPLY THE COMMISSION WITHOUT DELAY ON THEIR OWN INITIATIVE , OR AT THE COMMISSION'S REQUEST , WITH ALL UP-TO-DATE RELEVANT ADVANCE INFORMATION OF A SCIENTIFIC , ECONOMIC AND FINANCIAL NATURE CONCERNING ANY ACTIVITIES UNDER THEIR AUTHORITY , BOTH IN PROGRESS ON THE DATE THIS REGULATION ENTERS INTO FORCE AND CONTEMPLATED AFTER THAT DATE , AIMED AT :  ( A ) THE PROMOTION OF APPLIED INDUSTRIAL RESEARCH AND DEVELOPMENT ON EQUIPMENT , PROCESSES , INSTRUMENTS AND TECHNIQUES , BOTH HARDWARE AND SOFTWARE , FOR USE IN THE DESIGN , INDUSTRIAL MANUFACTURE AND TESTING OF ADVANCED INTEGRATED CIRCUITS ;  ( B ) THE DISSEMINATION OF BASIC KNOWLEDGE AND THE TRAINING AND EDUCATION OF MANAGEMENT AND STAFF SPECIALIZING IN THE DESIGN , UTILIZATION AND TESTING OF ADVANCED INTEGRATED CIRCUITS ;  ( C ) THE ENCOURAGEMENT OF THE ESTABLISHMENT WITHIN THE COMMUNITY OF AN INDUSTRY CAPABLE OF DESIGNING AND PRODUCING THE EQUIPMENT , MATERIALS AND TECHNIQUES USED IN THE MANUFACTURE OF ADVANCED INTEGRATED CIRCUITS .  THEY SHALL ALSO SUPPLY THE COMMISSION WITH AN APPRAISAL OF THE RESULT OF ALL THESE ACTIVITIES .  CONFIDENTIAL COMPANY INFORMATION CONCERNING SPECIFIC POINTS SHALL NOT BE COVERED BY THIS ARTICLE .  2 . THE COMMISSION WILL ENSURE THAT THE INFORMATION CONCERNING THE ACTIVITIES REFERRED TO IN PARAGRAPH 1 ABOVE IS COMMUNICATED TO THE MEMBER STATES .  3 . THE LEVEL OF DETAIL OF INFORMATION TO BE MADE AVAILABLE TO THE COMMISSION CONFIDENTIALLY , TO GOVERNMENT AGENCIES OF THE MEMBER STATES , OR TO THE PUBLIC , AS WELL AS PROCEDURES AND MEASURES FOR MAKING THAT INFORMATION AVAILABLE , SHALL BE SPECIFIED ACCORDING TO THE PROCEDURE LAID DOWN IN ARTICLE 8 .  TITLE II  JOINT PROJECTS  ARTICLE 4  1 . THE FOLLOWING KEY RESEARCH AND DEVELOPMENT PROJECTS , COMING DIRECTLY WITHIN SECTORS DEFINED IN ARTICLE 3 AND REGARDED AS HAVING HIGHEST PRIORITY , SHALL BENEFIT FROM COMMUNITY SUPPORT UNDER THE TERMS LAID DOWN IN ARTICLE 5 .  ( I ) STEP AND REPEAT ON WAFER ,  ( II ) ELECTRON BEAM FOR DIRECT-WRITING ON WAFER ,  ( III ) PLASMA ETCHING AND DEPOSITION ,  ( IV ) TEST EQUIPMENT ,  ( V ) COMPUTER AIDED DESIGN ( CAD ) FOR VERY LARGE SCALE INTEGRATION CIRCUITRY ( VLSI ) IN THE DOMAINS OF :  1 . ARCHITECTURE ;  2 . LANGUAGE AND DATA STRUCTURE ;  3 . TESTING ;  4 . DEVICE MODELLING .  2 . THE TECHNICAL SPECIFICATIONS FOR THE PROJECTS SPECIFIED IN PARAGRAPH 1 ABOVE ARE SET OUT IN THE ANNEX .  3 . THE COMMISSION SHALL UPDATE THE TECHNICAL SPECIFICATIONS AS MAY BE REQUIRED IN ACCORDANCE WITH THE PROCEDURE LAID DOWN IN ARTICLE 8 .  4 . FROM THE BEGINNING OF THE SECOND YEAR AFTER THE ENTRY INTO FORCE OF THIS REGULATION THE LIST REPRODUCED IN PARAGRAPH 1 MAY BE REVISED IN ACCORDANCE WITH THE PROCEDURE LAID DOWN IN ARTICLE 8 WITHIN THE LIMITS OF THE RESOURCES AVAILABLE . THE COMMISSION MAY ALSO SUBMIT TO THE COUNCIL A PROPOSAL FOR THE REVISION OF THE REGULATION IF THAT IS NECESSARY .  TITLE III  FINANCING PROCEDURES  ARTICLE 5  1 . THE EUROPEAN COMMUNITIES SHALL PROVIDE FINANCIAL SUPPORT TO THE PROJECTS SPECIFIED IN ARTICLE 4 IN THE FORM OF SUBSIDIES NORMALLY COVERING 30 % OF THE COSTS OF THEIR EXECUTION , BUT POSSIBLY AS MUCH AS 50 % ON THE BASIS OF A DECISION TAKEN IN ACCORDANCE WITH THE PROCEDURE LAID DOWN IN ARTICLE 8 .  2 . THE COMMITMENT APPROPRIATIONS FOR THE FINANCIAL SUPPORT REFERRED TO IN PARAGRAPH 1 ABOVE ARE 40 MILLION ECU . THIS AMOUNT WILL BE INCLUDED IN THE BUDGET OF THE EUROPEAN COMMUNITIES FOR 1982 .  3 . PROJECTS ELIGIBLE FOR AID SHALL MEET THE FOLLOWING CONDITIONS :  - THEIR PURPOSE MUST BE IN LINE WITH THE TECHNICAL SPECIFICATIONS SET OUT IN THE ANNEX ,  - THE PROJECTS MUST BE CARRIED OUT WITHIN THE COMMUNITY .  FURTHERMORE :  ( A ) FOR PROJECTS FALLING UNDER I TO IV OF ARTICLE 4 ( 1 ) :  - THE APPLICANTS MUST BE MANUFACTURERS OR INDUSTRIAL USERS ESTABLISHED IN THE COMMUNITY ,  - A SUFFICIENT NUMBER OF SUFFICIENTLY QUALIFIED INDUSTRIAL USERS NOT ALL ESTABLISHED IN THE SAME MEMBER STATE AND NOT HAVING FINANCIAL LINKS WITH THE MANUFACTURER OR MANUFACTURERS TAKING PART IN THE SAME PROJECT MUST HAVE PROVIDED EVIDENCE OF THEIR INTEREST IN PARTICIPATING IN THE PROJECT AND IN CONTRIBUTING THEIR OWN RESOURCES THERETO . THIS NUMBER SHALL BE DECIDED BY THE COMMISSION , FOR EACH PROJECT , IN ACCORDANCE WITH THE PROCEDURE LAID DOWN IN ARTICLE 8 ;  ( B ) FOR PROJECTS FALLING UNDER V OF ARTICLE 4 ( 1 ) :  - THE APPLICANTS MUST BE UNIVERSITIES , RESEARCH CENTRES OR FIRMS ESTABLISHED IN THE COMMUNITY ,  - A SUFFICIENT NUMBER OF SUFFICIENTLY QUALIFIED USER FIRMS NOT ALL ESTABLISHED IN THE SAME MEMBER STATE AND NOT HAVING FINANCIAL LINKS WITH EACH OTHER MUST HAVE PROVIDED EVIDENCE OF THEIR INTEREST IN PARTICIPATING IN THE PROJECT AND IN CONTRIBUTING THEIR OWN RESOURCES THERETO . THIS NUMBER SHALL BE DECIDED BY THE COMMISSION , FOR EACH PROJECT , IN ACCORDANCE WITH THE PROCEDURE LAID DOWN IN ARTICLE 8 .  IN APPLYING CRITERIA ( A ) AND ( B ) ABOVE , IN CASES WHERE RESOURCES DO NOT PERMIT TWO OR MORE OTHERWISE ELIGIBLE PROJECTS OF THE SAME NATURE TO BE SUPPORTED , PRIORITY SHALL BE GIVEN , ALL OTHER CONDITIONS BEING EQUAL , TO THE PROJECT INVOLVING ORGANIZATIONS FROM THE LARGEST NUMBER OF MEMBER STATES .  4 . ONCE THE ELIGIBILITY OF THE PROJECT HAS BEEN ESTABLISHED UNDER THE TERMS OF PARAGRAPH 3 ( A ) OR ( B ) ABOVE , ALL SUITABLY QUALIFIED FIRMS ESTABLISHED IN THE COMMUNITY MAY TAKE PART IN THE PROJECT AND APPLY FOR THE RELEVANT FINANCIAL SUPPORT IRRESPECTIVE OF THEIR POSSIBLE FINANCIAL LINKS WITH OTHER PARTICIPANTS IN THE SAME PROJECT .  5 . APPLICATIONS SHALL BE ADDRESSED TO THE COMMISSION BY THOSE CONCERNED IN RESPONSE TO CALLS FOR PROPOSALS PUBLISHED IN THE OFFICIAL JOURNAL OF THE EUROPEAN COMMUNITIES . THESE APPLICATIONS SHALL SHOW EVIDENCE THAT THEY ARE JUSTIFIED UNDER THE TERMS OF PARAGRAPH 3 ABOVE AND SHALL PROVIDE ANY OTHER RELEVANT INFORMATION . THE COMMISSION MAY REQUEST ANY OTHER DOCUMENTS AND ADDITIONAL INFORMATION REQUIRED FOR APPRAISAL OF THE APPLICATION .  6 . THE COMMISSION SHALL ACT ON APPLICATIONS SUBMITTED TO IT WITHIN FOUR MONTHS .  7 . WITHOUT PREJUDICE TO THE POWERS OF THE COURT OF AUDITORS PURSUANT TO ARTICLE 206A ( 3 ) OF THE TREATY , THE COMMISSION MAY CARRY OUT INVESTIGATIONS ON THE SPOT OR INQUIRIES INTO THE OPERATIONS FINANCED , ACCORDING TO THE CONDITIONS SPECIFIED IN THE CONTRACTS REGULATING THE FINANCING OF THE PROJECTS .  TITLE IV  GENERAL PROVISIONS  ARTICLE 6  1 . A CONSULTATIVE COMMITTEE , HEREINAFTER CALLED " THE COMMITTEE " , IS HEREBY SET UP FOR PROJECTS PROMOTING MICROELECTRONIC TECHNOLOGY . IT SHALL CONSIST OF REPRESENTATIVES OF THE MEMBER STATES , WHO MAY BE ASSISTED BY EXPERTS OR ADVISERS DEPENDING ON THE NATURE OF THE PROJECTS UNDER CONSIDERATION , WITH A COMMISSION REPRESENTATIVE AS CHAIRMAN .  2 . THE PROCEEDINGS OF THE COMMITTEE SHALL BE CONFIDENTIAL .  3 . THE COMMITTEE SHALL ADOPT ITS OWN RULES OF PROCEDURE .  4 . SECRETARIAL SERVICES FOR THE COMMITTEE SHALL BE PROVIDED BY THE COMMISSION .  ARTICLE 7  THE COMMISSION MAY CONSULT THE COMMITTEE ON ANY MATTER FALLING WITHIN THE SCOPE OF THIS REGULATION AND MUST IN PARTICULAR CONSULT IT ON :  - THE LEVEL OF DETAIL OF THE INFORMATION CONCERNING NATIONAL ACTIVITIES TO BE SUPPLIED CONFIDENTIALLY TO THE COMMISSION IN ACCORDANCE WITH ARTICLE 3 ,  - THE LEVEL OF DETAIL OF THE INFORMATION TO BE PUBLISHED OR NOTIFIED TO THE GOVERNMENT AGENCIES OF MEMBER STATES ,  - THE PROCEDURES FOR MAKING THE INFORMATION COLLECTED AVAILABLE TO THE MEMBER STATES ,  - THE UPDATING OF THE TECHNICAL SPECIFICATIONS FOR PROJECTS POTENTIALLY ELIGIBLE FOR FINANCIAL SUPPORT ,  - THE MINIMUM NUMBER OF FIRMS REQUIRED TO MAKE A PROJECT ELIGIBLE FOR FINANCIAL SUPPORT ,  - THE APPRAISAL OF APPLICATIONS AND THE GRANTING OF FINANCIAL SUPPORT .  ARTICLE 8  1 . WHERE THE PROCEDURE LAID DOWN IN THIS ARTICLE IS TO BE FOLLOWED , THE MATTER SHALL BE REFERRED TO THE COMMITTEE BY ITS CHAIRMAN , EITHER ON HIS OWN INITIATIVE OR AT THE REQUEST OF THE REPRESENTATIVE OF A MEMBER STATE .  2 . THE COMMISSION REPRESENTATIVE SHALL SUBMIT A DRAFT OF THE MEASURES TO BE TAKEN . THE COMMITTEE SHALL GIVE ITS OPINION ON THE DRAFT DECISION WITHIN TWO MONTHS . ITS DECISIONS SHALL BE TAKEN BY A MAJORITY OF 45 VOTES . WITHIN THE COMMITTEE THE VOTES OF THE MEMBER STATES SHALL BE WEIGHTED IN ACCORDANCE WITH ARTICLE 148 ( 2 ) OF THE TREATY . THE CHAIRMAN SHALL NOT VOTE .  3 . THE COMMISSION SHALL ADOPT THE DRAFT WHERE IT IS IN ACCORDANCE WITH THE OPINION OF THE COMMITTEE . WHERE THE DRAFT DECISION IS NOT IN ACCORDANCE WITH THAT OPINION OR WHERE NO SUCH OPINION IS ISSUED , THE COMMISSION SHALL WITHOUT DELAY MAKE A PROPOSAL TO THE COUNCIL IN THE FORM OF A DRAFT DECISION . THE COUNCIL SHALL ACT BY A QUALIFIED MAJORITY .  ARTICLE 9  EACH YEAR THE COMMISSION SHALL FORWARD TO THE EUROPEAN PARLIAMENT AND TO THE COUNCIL A REPORT ON THE DEVELOPMENT OF THE ACTIVITIES IN THE COMMUNITY FALLING WITHIN THE SCOPE OF THIS REGULATION .  ARTICLE 10  THIS REGULATION SHALL ENTER INTO FORCE ON 1 JANUARY 1982 .  IT SHALL APPLY UNTIL 31 DECEMBER 1985 .  THIS REGULATION SHALL BE BINDING IN ITS ENTIRETY AND DIRECTLY APPLICABLE IN ALL MEMBER STATES .  DONE AT BRUSSELS , 7 DECEMBER 1981  FOR THE COUNCIL  THE PRESIDENT  CARRINGTON  ANNEX  OUTLINE TECHNICAL SPECIFICATION OF PROJECTS AND ACTIVITIES FOR WHICH FINANCIAL SUPPORT IS BEING PROPOSED UNDER THE TERMS OF THE REGULATION  I . STEP AND REPEAT ON WAFER  DIRECT OPTICAL STEPPING TECHNOLOGY  DIRECT OPTICAL STEPPING MACHINES SHOULD BE AVAILABLE IN PRODUCTION WITH THE CHARACTERISTICS LISTED BELOW BY THE END OF 1982 :  - WAFER SIZE : UP TO SIX INCHES ,  - DIE SIZE : 1 CM2 ,  - MINIMUM LINE WIDTHS : 1.25 UM ON THE WAFER ( 1.1 UM ON THE RESIST ) ,  - AUTOMATIC REGISTRATION : 0.1 UM ,  - THROUGHPUT 50 BY FOUR-INCH WAFERS PER HOUR AT 1 CM2 FIELD WITH INSERTION OF FIVE TEST PATTERNS AND AUTO-REGISTRATION AT EACH CHIP ; ADDITION OF A RETICLE MAGAZINE .  INDIVIDUAL TIMES SHOULD BE GIVEN IN THE DESCRIPTION OF THE EQUIPMENT INCLUDING THE TIME TO INSERT TEST PATTERNS . REGISTRATION SHOULD BE PROGRAMMEMABLE ( PER INDIVIDUAL EXPOSURE - PER BLOCK - PER WAFER ) . MINIMUM ALLOWABLE SIZE OF ALIGNMENT MARKS SHOULD BE GIVEN .  IT IS CONSIDERED DESIRABLE THAT MACHINES COULD BE SUPPLIED IN 1983 WITH AN IMPROVED THROUGHPUT OF 50 BY SIX-INCH WAFERS PER HOUR AND IMPROVED RESOLUTION OF 1.0 UM MINIMUM LINE WIDTH ON WAFER .  II . ELECTRON BEAM FOR DIRECT-WRITING ON WAFER  ELECTRON BEAM DIRECT-WRITING EQUIPMENT  E-BEAM MACHINES CAPABLE OF :  - WAFER SIZE : SIX INCHES ,  - THROUGHPUT : 15 TO 20 LAYERS PER HOUR AT 1 UM ,  - DIE SIZE : NO LIMITATION ,  - MINIMUM FEATURE SIZE : 0.5 UM ,  - SPOT SIZE : VARIABLE ,  - REGISTRATION ACCURACY : 0.1 UM .  THIS EQUIPMENT SHOULD ALSO BE SUITABLE FOR RETICLE AND MASK MAKING . PROTOTYPE MACHINES MEETING ALL THESE REQUIREMENTS APART FROM SPEED MUST BE AVAILABLE WITHIN 1983 .  III . PLASMA ETCHING  A . MINIMUM PERFORMANCES OF THE EQUIPMENT  - MATERIALS TO BE ETCHED  - SIO2 , DOPED AND UNDOPED .  - SI3N4 .  - POLYSILICON , DOPED AND UNDOPED .  - SILICIDES AND POLYCIDES .  - ALUMINIUM AND ALUMINIUM ALLOYS .  - OTHER METALS FOR CONTACTS AND INTERCONNECTIONS .  - ORGANIC POLYMERS FOR MULTILEVEL RESISTS AND MULTILEVEL METALLIZATION .  - STRUCTURES TO BE ETCHED IN PRODUCTION  - PITCH ( LINE PLUS SPACING ) : 3 UM .  - MINIMUM LINEWIDTH : 1 TO 1.5 UM .  - PRECISION : MORE OR LESS 10 % OF LINEWIDTH FOR THE CRITICAL STRUCTURES .  - SELECTIVITY AND ANISOTROPY  THE SELECTIVITY HAS TO BE ADEQUATE AND FOR EACH LAYER IT SHOULD BE POSSIBLE TO ETCH COMPLETELY ANISOTROPICALLY .  - THROUGHPUT  THE MINIMUM THROUGHPUT SHOULD BE 50 WAFERS PER HOUR FOR THE SLOWEST PROCESS . THE SLOWEST PROCESS WILL PROBABLY BE THE ETCHING THROUGH 0.8 UM OF THERMAL SIO2 WITH A SELECTIVITY OF 10 : 1 OVER SI AND WITH A PITCH OF 3 UM . THE ETCHING OF OTHER LAYERS ( E . G . 0.4 UM UNDOPED POLYSILICON OVER SIO2 ) SHOULD BE MUCH FASTER .  B . DESIGN OF THE EQUIPMENT  WE CONSIDER A PARALLEL PLATE REACTOR WITH THE FOLLOWING FEATURES :  - DESIGN CONCEPT  MOST IMPORTANT IS THE USE OF A MODULAR DESIGN CONCEPT SO THAT THE EQUIPMENT CAN BE OPTIMALLY ADAPTED FOR EACH APPLICATION .  - LOAD LOCK  UNDESIRED SPECIES ( E . G . WATER VAPOUR ) SHOULD BE BLOCKED FROM THE REACTION CHAMBER AND POST-ETCHING EFFECTS MUST BE AVOIDED . THIS CAN BE REACHED WITH A VACUUM LOCK CONTAINING THE CASSETTES . STRIPPING OF THE PHOTORESIST IN THE UNLOAD-LOCK SHOULD BE CONSIDERED AS AN OPTION .  - ELECTRODE AND CHAMBER CONSTRUCTION  - INDIVIDUALLY DRIVEN THERMOSTATS FOR UPPER AND LOWER ELECTRODE AND FOR THE REACTION CHAMBER . THE RANGE FOR TEMPERATURE CONTROL IS 15 TO 100 } C STANDARD AND UP TO 150 } C AS AN OPTION .  - ELECTRODE DISTANCE ADJUSTABLE BETWEEN : 5 TO 70 MM ( BATCH ORIENTED SYSTEM ) ,  5 TO 70 MM ( SINGLE WAFER SYSTEM ) .  - THE ELECTRODE ASSEMBLY MUST BE SUITED FOR OPERATION AT HIGH FREQUENCIES ( UNTIL 27.12 MHZ ) , E . G . AVOID PARASITIC PLASMA ANYWHERE IN THE REACTOR .  - BOTH PARALLEL PLASMA ETCHING ( PE ) AND REACTIVE ION ETCHING ( RIE ) MUST BE POSSIBLE IN THE SYSTEM ( ANODE AND CATHODE COUPLING ) .  - VACUUM DESIGN  - THE REGION OF INTEREST IS BETWEEN 10 MTORR AND 10 TORR .  - ADJUSTABLE PUMPING SPEED .  - AUTOMATIC AND MANUAL PRESSURE CONTROL WITH SIMPLE SWITCHING BETWEEN THE TWO MODES .  - USE OF NON-CORROSIVE MATERIALS FOR SEALS ( FITTINGS , O-RINGS ) AND TUBING .  - GAS CABINET  FLEXIBLE HANDLING OF ONE TO THREE GASSES WITH ONE TO THREE MASS FLOW CONTROLLERS , PREFERENTIALLY EXTENDABLE TO FIVE GASES ( NUMBER OF GASES IS AN OPTION ) .  - CONTROLS  - THE FOLLOWING PARAMETERS MUST BE CONTROLLABLE :  GASLINE ( S ) IN USE ,  FLOWRATE ,  PROCESS TIME ,  TIME TO STABILIZE ,  TIME TO OVERETCH ,  RF POWER ,  TEMPERATURE OF BOTH ELECTRODES ,  VOLTAGE ON ELECTRODE .  - THE ELECTRICAL SIGNAL FROM THE SENSORS ( PRESSURE SENSOR , ETC . ) MUST BE EASILY ACCESSIBLE ( E . G . ON A STANDARD PLUG ) FOR PROCESS MONITORING .  - AT LEAST ONE WINDOW TO LOOK INTO THE PLASMA AND ADDITIONAL FLANGE ( S ) TO HOOK UP SOME ANALYTICAL TOOLS FOR PROCESS MONITORING SHOULD BE AVAILABLE .  - AUTOMATIC ETCHING CONTROL SYSTEM  - A KEYBOARD AND NECESSARY MEMORY FOR THE STEP BY STEP COMMAND OF THE PROCESS OR THE MAINTENANCE SEQUENCE .  - A PLUG-IN PROM , USER PROGRAMMEMED , FOR AUTOMATIC ETCHING .  - WAFER HANDLING  AUTOMATIC WAFER HANDLING , CASSETTE TO CASSETTE LOAD AND UNLOAD WITHOUT WAFER DAMAGE OR CONTAMINATION .  THE SYSTEM SHOULD HANDLE THREE INCH WAFERS OF UP TO 150 MM DIAMETER .  - MAINTENANCE AND SAFETY  - EASY DISMANTLING FOR CLEANING AND REPAIR .  - STANDARDIZATION OF FLANGES , SEALS , PLUGS , ETC . , AND SPARE PARTS .  IV . TESTING EQUIPMENT  EUROPEAN TESTERS FOR INTEGRATED CIRCUITS SHOULD BE DEVELOPED WITH THE FOLLOWING CHARACTERISTICS :  - OF THE INTEGRAL ANALOG / DIGITAL TYPE ,  - OF MODULAR DESIGN , IN ORDER TO BE ADAPTABLE TO BOTH DEVELOPMENT AND PRODUCTION TESTING TASKS ,  - DEVELOPMENT IN TWO PHASES , AS FAR AS THE DIGITAL PART IS CONCERNED . THE FIRST STEP SHOULD BE A TESTER FOR CLOCK-RATES OF 10 TO 20 MHZ , THE SECOND STEP AIMING AT 50 TO 100 MHZ . THIS STEPWISE DEVELOPMENT HAS THE ADVANTAGE THAT THE TECHNOLOGICAL KNOW-HOW BUILT UP IN THE FIRST PHASE CAN BE USED TO TACKLE THE PROBLEMS THAT HAVE TO BE FACED IN THE SECOND DEVELOPMENT ROUND . MOREOVER , THE HIGH SPEED TEST DEVELOPMENT CAN THUS BE ADAPTED TO THE DEVELOPING REQUIREMENTS OF THE EUROPEAN IC INDUSTRY IN THE HIGH SPEED BIPOLAR CIRCUITS ,  - TESTING OF DEVICES WITH AN INCREASING NUMBER OF PINS ( FROM 64 TO 128 ) ,  - SUBSTANTIAL PARTS OF THE TEST SYSTEM HAVE TO BE " ECL-SPECIFIC " ,  - TESTING OF MEMORY DEVICES ALONE HAS BEEN EXCLUDED , HOWEVER " ON-THE-CHIP " MEMORIES ARE BECOMING INCREASINGLY IMPORTANT AND THEREFORE THEIR TESTING HAS TO BE COVERED ,  - ONE SINGLE HIGH LEVEL TEST LANGUAGE CONCEPT SHOULD BE SUPPLIED FOR THE DIFFERENT TESTER CONFIGURATIONS .  V . CAD FOR VLSI  1 . ARCHITECTURE  THE PROBLEMS TO BE TACKLED ARE THE DISCIPLINES OF SPECIFICATION , SIMULATION AND TESTING AT THE ARCHITECTURAL DESIGN PHASE AND THE ARCHITECTURAL STRATEGIES LIKE ERROR MANAGEMENT AND STRUCTURED LOGIC . THE FOLLOWING ACTIVITIES APPEAR TO BE REQUIRED :  - IMPROVEMENT IN KNOWLEDGE OF COMPUTER TECHNIQUES BY VLSI DESIGNERS THROUGH :  ( A ) TRANSFER OF KNOW-HOW FROM COMPUTER MANUFACTURERS ;  ( B ) BETTER INTEGRATION OF COMPUTER SCIENCE AND ELECTRONIC ENGINEERING TRAINING IN UNIVERSITIES .  - RESEARCH ON :  ( A ) LINKING OF BEHAVIOURAL AND STRUCTURAL DESIGN BY DEVELOPMENT OF SUITABLE LANGUAGES AND SIMULATORS ;  ( B ) SYNTHESIS OF LOGIC FROM RTL DESCRIPTION ;  ( C ) ERROR MANAGEMENT INCLUDING FAULT-TOLERANT ASPECTS OF VLSI ARCHITECTURE ;  ( D ) STRUCTURED LOGIC INCLUDING MINIMIZATION FOR PLAS ( PROGRAMMABLEABLE LOGIC ARRAYS ) AND AUTOMATIC PROGRAMMEMING OF PLAS AND ROMS ( READ ONLY MEMORIES ) ;  ( E ) FIRMWARE GENERATION AND SIMULATION AIDS ;  ( F ) PARALLEL PROCESSING MACHINES FOR SIGNAL PROCESSING .  2 . LANGUAGE AND DATA STRUCTURE  2.1 . DESIGN DATA MANAGEMENT  CONVENTIONAL GRAPHIC IC DESIGN SYSTEMS ARE BASED UPON A BOTTOM UP REPRESENTATION OF THE CIRCUIT BEING DESIGNED . THIS IS CONSIDERED INADEQUATE FOR COPING WITH THE PROBLEMS OF VLSI DESIGN , AND INSTEAD , A SPECIFICATION OF A FILE MANAGEMENT OR DESIGN MANAGEMENT SYSTEM MUST BE FORMULATED WITH RESPECT TO THE FOLLOWING PURPOSES :  ( A ) TO AID THE MANAGEMENT OF A LARGE NUMBER OF FILES REPRESENTING ALTERNATIVE REPRESENTATIONS OF MANY MODULES OF A SYSTEM ;  ( B ) TO PROTECT THE INTEGRITY OF A DESIGN INVOLVING A TEAM EFFORT ;  ( C ) TO MANAGE DESIGN MODIFICATIONS ;  ( D ) TO AID RE-PARTITIONING OF A DESIGN ;  ( E ) TO MANAGE THE PROVISION OF DESIGN DOCUMENTATION .  RESEARCH PROJECTS MUST BE INITIATED WHICH WILL ENHANCE THE NORMAL FILING SYSTEM OR OPERATING SYSTEM TO PROVIDE THE ABOVE FACILITIES . THE SMALLEST UNIT OF DATA IN A TRANSACTION WILL BE A COMPLETE FILE , AND SO CONVENTIONAL DATA BASES ARE NOT APPROPRIATE . THE IMPLEMENTATION MUST BE CARRIED OUT WITH PORTABILITY IN MIND . A STANDARD LANGUAGE MUST BE USED WITH WELL-DEFINED INTERFACES TO STANDARD FILING SYSTEMS . THIS PROJECT SHOULD BE A JOINT PROJECT BETWEEN IC DESIGNERS , CAD TOOL SPECIALISTS , AND COMPUTER SCIENTISTS .  2.2 . USER INTERFACE  SOME DESIGN ACTIVITIES ARE HIGHLY INTERACTIVE AND DEMAND A GUARANTEED FAST RESPONSE FROM THE COMPUTER WHILE NOT DEMANDING A VERY POWERFUL COMPUTER . AN EXAMPLE IS DESIGN SPECIFICATION USING GRAPHICAL TECHNIQUES . SUCH ACTIVITIES CAN BE SUPPORTED ON A SMALL COMPUTER DEDICATED TO A SINGLE USER . OTHER ACTIVITIES ARE NOT PRIMARILY INTERACTIVE , BUT DO REQUIRE VERY POWERFUL COMPUTING FACILITIES . AN EXAMPLE IS SIMULATION . SUCH ACTIVITIES NEED POWERFUL TIME-SHARED SYSTEMS .  IT IS IMPORTANT THAT THE COMPUTERS SUPPORTING THESE RELATED ACTIVITIES SHOULD BE INTIMATELY CONNECTED . TECHNIQUES FOR CONTROLLING TASKS SPLIT BETWEEN TWO OR MORE COMPUTERS , AND FOR ALLOWING FLEXIBLE MOVEMENT OF DATA BETWEEN THESE TASKS , SHOULD BE INVESTIGATED . GENERAL PRINCIPLES APPLICABLE TO A WIDE RANGE OF HARDWARE SHOULD BE ESTABLISHED .  THE PRESENT TREND IN HARDWARE DESIGN SPECIFICATION IS TO USE TEXT BASED LANGUAGE DESCRIPTIONS WHICH ARE CONVENIENT FOR EXPRESSING THE HIERARCHICAL STRUCTURE , MODULARITY , AND REPETITIVITY WHICH IS INEVITABLE WITH VLSI . HOWEVER , DESIGNERS STILL TEND TO THINK IN TERMS OF DIAGRAMS , AND GRAPHICAL AIDS WILL CONTINUE TO BE VALUABLE IN THE DESIGN PROCESS . A PROJECT OUGHT TO BE LAUNCHED TO INVESTIGATE METHODS OF COMBINING TEXTUAL AND GRAPHICAL REPRESENTATIONS ALLOWING EACH TO BE CONVERTED AUTOMATICALLY INTO THE OTHER , SO THAT THE MOST APPROPRIATE INTERFACE CAN BE FREELY CHOSEN AT EACH PART OF THE DESIGN PROCESS .  2.3 . SIMULATION  SOFTWARE TOOLS FOR SIMULATION , TEST AND VERIFICATION HAVE TO SPAN THE DESIGN SPECTRUM FROM RTLS DOWN TO TRANSISTOR LEVEL . ACTIVITY SHOULD BE DIRECTED TOWARDS THE DEVELOPMENT OF A FLEXIBLE MULTILEVEL STRUCTURAL DESCRIPTION LANGUAGE FOR NMOS AND CMOS VLSI . AUTOMATIC COMPILER GENERATION INTO THE SYNTAX OF PRESENTLY USED SINGLE LEVEL TOOLS AND , MORE IMPORTANTLY , DIRECTLY INTO THE DATA STRUCTURE OF MIXED MODE SIMULATORS NEEDS INVESTIGATION . MIXED MODE SIMULATION TECHNIQUES NEED CONSIDERABLE ATTENTION IN THE AREA OF DATA STRUCTURES , ALGORITHMS , AND MODELS .  IT IS STRONGLY RECOMMENDED TO PAY SPECIAL ATTENTION TO VLSI NETWORK ANALYSIS RATHER THAN PURE SIMULATION IN ORDER TO REDUCE DESIGN TIME AND ENSURE DESIGN CORRECTNESS . THIS IS A COMPLETELY NEW RESEARCH DOMAIN WHICH LOOKS ENTIRELY FEASIBLE BASED ON THE DATA STRUCTURES AND ALGORITHMS OF PRESENTLY EXISTING MIXED MODE SIMULATORS .  2.4 . VERIFICATION  INSTEAD OF INTENSIVE VERIFICATION OF MANUALLY PERFORMED OR INTERACTIVE DESIGN STEPS , THE GOAL SHOULD BE TO AUTOMATE AS MUCH AS POSSIBLE ( SILICON COMPILATION , STANDARD CELL TECHNIQUE , ETC . ) TO MAKE VERIFICATION UNNECESSARY . TO FIND A SOLID BASIS FOR THE USE OR CREATION OF SUCH TOOLS , A STUDY SHOULD BE INITIATED WHICH COMPARES THE DIFFERENT APPROACHES AS WELL AS DIFFERENT HANDCRAFTED LAYOUTS TO FIND OBJECTIVE CRITERIA FOR THE FUNDAMENTAL PRINCIPLES OF EFFICIENCY IN LAYOUT .  THE HIERARCHICAL DESIGN OF VLSI IS OBVIOUS . THE VERIFICATION BETWEEN THE DIFFERENT LEVELS OF HIERARCHY IS A PROBLEM BUT CANNOT BE AVOIDED . IN SPITE OF THE HIERARCHY , THE COMPLEXITY AND AMOUNT OF DATA IS ENORMOUS AND WITH TODAY'S TOOLS LEADS TO UNECONOMIC COMPUTER TIMES . THEREFORE , FURTHER CANDIDATES FOR RESEARCH AND DEVELOPMENT ARE DEDICATED HARDWARE MODULES ( E . G . DESIGN RULE CHECKERS , PATTERN MEMORY PLUS COUNTERS AND SHIFT REGISTERS , OR HARDWARE LANGUAGE PROCESSORS WHICH PRODUCE THE APPROPRIATE DATA STRUCTURES ) .  2.5 . INFLUENCE OF NEW COMPUTER ARCHITECTURES  ON THE BASIS OF THE ASSUMPTION THAT :  - SOFTWARE IS NOW EXPENSIVE AND SHOULD BE OPTIMIZED WHILE HARDWARE IS CHEAPER AND CAN BE USED MORE FREELY ,  - IN THE PAST FEW YEARS A LOT OF HIGH PERFORMANCE PARALLEL PROCESSORS HAVE BEEN DEVELOPED AND IMPLEMENTED ,  - THE ARCHITECTURE OF A MACHINE SHOULD FIT THE PROBLEM IT IS TO SOLVE ,  INVESTIGATION IN THE FOLLOWING TWO AREAS IS PROPOSED :  ( A ) DEVELOPMENT OF NEW PARALLEL ALGORITHMS AND NEW DATA STRUCTURES IN ANY CAD BRANCH , TO EXPLOIT AND IMPLEMENT THE MAXIMUM PARALLELISM ;  ( B ) STUDY OF NEW SPECIAL PURPOSE HARDWARE PROCESSOR TO BE INTERFACED WITH CURRENTLY EXISTING COMPUTER SYSTEMS TO IMPROVE PART OF THEIR PERFORMANCE BY AT LEAST ONE ORDER OF MAGNITUDE .  3 . TESTING : SUMMARY OF RECOMMENDATIONS  THE TEAM ON TESTING RECOMMEND ORGANIZING FUTURE WORK IN ACCORDANCE WITH THREE MAIN AREAS AND THE RELATED TOPICS LISTED BELOW .  MAIN AREA OF ACTIVITIES  * RESEARCH * SPECIFICATION AND EVALUATION * DEVELOPMENT  1 . TEST DATA GENERATION  - FUNCTIONAL LEVEL TESTING ( METHODS AND STRATEGIES ) * +  - ELEMENT LEVEL ATPG * +  - ATPG FOR LSI CELLS , REGULAR LOGIC , ETC . * +  - FAULT TYPES AND MODELS * +  - FAULT SIMULATION STRATEGIES * +  - MODULAR ATPG SYSTEM * * + * +  - LANGUAGE FOR MTPG * * + * +  - INTEGRATED ATDG SYSTEM * * + * +  2 . DESIGN FOR TESTABILITY  - PARTITIONING * +  - RAM DESIGN FOR TESTABILITY * +  - MICROPROGRAMMEMED UNITS * +  - DESIGN FOR TESTABILITY GENERAL TECHNIQUES * +  - HARDWARE IMPLEMENTED SELF-TESTING * +  - SOFTWARE / FIRMWARE SELF-TESTING * +  3 . DATA ACQUISITION AND DATA MANAGEMANT  - DADM SYSTEM * * + * +  - PROGRAMME DEVELOPMENT TOOLS * * + * +  4 . DEVICE MODELLING : SUMMARY OF RECOMMENDATIONS  THE PRESENT REPORT ON DEVICE MODELLING COVERS THREE MAIN AREAS :  - NUMERICAL DEVICE SIMULATION ,  - ANALYTICAL MODELS ,  - TABLE MODELS .  FOR EACH OF THEM , THE MAIN RECOMMENDATIONS ARE SUMMARIZED BELOW .4.1 . NUMERICAL DEVICE SIMULATION  THE MAIN TARGET OF THIS SUBPROJECT IS THAT OF STIMULATING EUROPEAN RESEARCH CENTRES AND LABORATORIES TO DEVELOP ADVANCED DEVICE-SIMULATION PACKAGES , AND MAKE THEM AVAILABLE TO EUROPEAN IC MANUFACTURERS . THIS SHOULD ALLOW REACHING AN INDEPENDENCE WITH RESPECT TO AMERICAN AND JAPANESE COUNTERPARTS . THE NEED FOR SUCH AN ACTIVITY STEMS FROM THE FACT THAT , DUE TO THE IMPORTANCE OF TWO - , AND EVEN THREE-DIMENSIONAL EFFECTS , NUMERICAL DEVICE SIMULATION REPRESENTS THE ONLY PREDICTIVE TOOL WHICH CAN PRACTICALLY BE USED FOR DEVICE DESIGN . IT IS THEREFORE RECOMMENDED THAT AT LEAST FOUR SIMULATION PACKAGES BE DEVELOPED , NAMELY :  - 2-D MOSFET SIMULATOR ,  - 2-D SIMULATOR FOR BIPOLAR DEVICES ,  - 3-D MOSFET SIMULATOR ,  - 3-D SIMULATOR FOR BIPOLAR DEVICES .  FOR EACH OF THEM , DETAILED SPECIFICATIONS HAVE BEEN DEFINED CONCERNING THE PHYSICAL PHENOMENA TO BE INCORPORATED IN THE PROGRAMME , THE PHYSICAL AND GEOMETRICAL DEVICE STRUCTURE , AND I / O GRAPHICAL CAPABILITIES .  4.2 . ANALYTICAL MODELS ( MOSFETS ONLY )  AN ACTIVITY IN THIS AREA IS ESSENTIAL FOR TWO MAIN REASONS : FROM THE ONE HAND ANALYTICAL MODELS TRADING OFF ACCURACY AND SIMPLICITY ARE MOSTLY SUITED FOR CIRCUIT DESIGNERS IN CAD CIRCUIT SIMULATION PROGRAMMES ; ON THE OTHER HAND , THE FUNCTIONAL DEPENDENCE OF RELEVANT ELECTRICAL PARAMETERS ON GEOMETRICAL AND PHYSICAL DEVICE STRUCTURE IS MOST EASILY IDENTIFIED IN ANALYTICAL MODELS , WHICH CAN , THEREFORE , PROVIDE SOME INSIGHT IN THE PHYSICAL PHENOMENA OCCURING WITHIN A DEVICE .  THE FOLLOWING ANALYTICAL MODELS SHOULD BE DEVELOPED :  SURFACE CHANNEL MOSFETS LONG CHANNEL , LOW VOLTAGE ( LEVEL 1 ) LONG CHANNEL , HIGH VOLTAGE ( LEVEL 2 ) SHORT CHANNEL , LOW VOLTAGE ( LEVEL 3 ) SHORT CHANNEL , HIGH VOLTAGE ( LEVEL 4 )  BURIED CHANNEL MOSFETS LONG CHANNEL ( LEVEL 1 ) SHORT CHANNEL ( LEVEL 2 )  4.3 . PHYSICAL MODEL  AGAIN , DETAILED SPECIFICATIONS ARE PROVIDED FOR EACH OF THE ABOVE MODELS . IN ADDITION TO THE DEVELOPMENT OF THE MODELS , THE PROBLEM OF PARAMETER IDENTIFICATION SHOULD BE TACKLED AND SOLVED , ESPECIALLY AS FAR AS CHARGES ( OR CAPACITANCES ) ARE CONCERNED .  4.4 . TABLE MODELS  THE NEED FOR TABLE MODELS HAS BEEN RECOGNIZED FOR TIMING SIMULATION PURPOSES . IN SUCH SIMULATORS , THE CAPACITANCES ARE RATHER POORLY HANDLED , BEING ASSUMED AS CONSTANTS ; THEREFORE , THE ACTIVITY IN THIS AREA SHOULD AIM AT DEVELOPING TABLES FOR BOTH CURRENTS AND CAPACITANCES . THE MOST IMPORTANT PROBLEM TO BE SOLVED IS THAT OF PROVIDING THE SCALING RULES , WHILE MAINTAINING THE COMPUTATIONAL SIMPLICITY WHICH IS NEEDED IN ORDER TO STRONGLY REDUCE THE CPU TIME , WITH RESPECT TO THAT NEEDED WITH ANALYTICAL MODELS .