CELEX: 31984R3385
Language: en
Date: 1984-11-27 00:00:00
Title: Council Regulation (EEC) No 3385/84 of 27 November 1984 temporarily suspending the autonomous Common Customs Tariff duties on a number of industrial products

Avis juridique important

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31984R3385

Council Regulation (EEC) No 3385/84 of 27 November 1984 temporarily suspending the autonomous Common Customs Tariff duties on a number of industrial products  

Official Journal L 321 , 10/12/1984 P. 0001 - 0048

+++++COUNCIL REGULATION ( EEC ) NO 3385/84 OF 27 NOVEMBER 1984 TEMPORARILY SUSPENDING THE AUTONOMOUS COMMON CUSTOMS TARIFF DUTIES ON A NUMBER OF INDUSTRIAL PRODUCTS  THE COUNCIL OF THE EUROPEAN COMMUNITIES ,  HAVING REGARD TO THE TREATY ESTABLISHING THE EUROPEAN ECONOMIC COMMUNITY , AND IN PARTICULAR ARTICLE 28 THEREOF ,  HAVING REGARD TO THE DRAFT REGULATION SUBMITTED BY THE COMMISSION ,  WHEREAS PRODUCTION OF THE PRODUCTS REFERRED TO IN THIS REGULATION IS AT PRESENT INADEQUATE OR NON-EXISTENT WITHIN THE COMMUNITY AND PRODUCERS ARE THUS UNABLE TO MEET THE NEEDS OF USER INDUSTRIES IN THE COMMUNITY ;  WHEREAS IT IS IN THE COMMUNITY'S INTEREST TO SUSPEND THE AUTONOMOUS COMMON CUSTOMS TARIFF DUTIES ONLY PARTIALLY IN CERTAIN CASES , DUE PARTICULARLY TO THE EXISTENCE OF COMMUNITY PRODUCTION , AND TO SUSPEND THEM COMPLETELY IN OTHER CASES ;  WHEREAS , TAKING ACCOUNT OF THE DIFFICULTIES INVOLVED IN ACCURATELY ASSESSING THE DEVELOPMENT OF THE ECONOMIC SITUATION IN THE SECTORS CONCERNED IN THE NEAR FUTURE , THESE SUSPENSION MEASURES SHOULD BE TAKEN ONLY TEMPORARILY WITH THEIR TERM OF VALIDITY FIXED TO COINCIDE WITH THE INTERESTS OF COMMUNITY PRODUCTION ,  HAS ADOPTED THIS REGULATION :  ARTICLE 1  THE AUTONOMOUS COMMON CUSTOMS TARIFF DUTIES FOR THE PRODUCTS LISTED IN THE TABLES ANNEXED TO THIS REGULATION SHALL BE SUSPENDED AS THE LEVEL INDICATED IN RESPECT OF EACH OF THEM .  THESE SUSPENSIONS SHALL BE VALID :  - FROM 1 JANUARY TO 31 MARCH 1985 FOR THE PRODUCTS LISTED IN TABLE I ,  - FROM 1 JANUARY TO 30 JUNE 1985 FOR THE PRODUCTS LISTED IN TABLE II .  ARTICLE 2  THIS REGULATION SHALL ENTER INTO FORCE ON 1 JANUARY 1985 .  THIS REGULATION SHALL BE BINDING IN ITS ENTIRETY AND DIRECTLY APPLICABLE IN ALL MEMBER STATES .  DONE AT BRUSSELS , 27 NOVEMBER 1984 .  FOR THE COUNCIL  THE PRESIDENT  P . BARRY  ANNEX  TABLE I  CCT HEADING NO * DESCRIPTION * RATE OF AUTONOMOUS DUTY ( % )  EX 39.02 C I A ) * POLYETHYLENE , IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 , HAVING A DENSITY OF NOT LESS THAN 0,92 AND NOT MORE THAN 0,98 FOR THE MANUFACTURE OF TYPEWRITER RIBBON OR SIMILAR RIBBON ( A ) * 0  EX 39.02 C XI * POLY ( VINYL BUTYRAL ) FILM HAVING A GRADUATED COLOURED BAND * 8  ( A ) CONTROL OF THE USE FOR THIS SPECIAL PURPOSE SHALL BE CARRIED OUT PURSUANT TO THE RELEVANT COMMUNITY PROVISIONS .  TABLE II  CCT HEADING NO * DESCRIPTION * RATE OF AUTONOMOUS DUTY ( % )  EX 28.20 A * ALUMINIUM HYDROXIDE OXIDE IN THE FORM OF PSEUDO BOEHMITE * 4  EX 28.47 F * CALCIUM WOLFRAMATE , FOR THE MANUFACTURE OF FERRO-ALLOYS OR DECA-AMMONIUM 4L-OXODODECAWOLFRAMATE ( AMMONIUM PARATUNGSTATE ) ( A ) * 0  EX 28.49 C II * CARBOPLATIN ( INN ) * 0  EX 28.55 A * PHOSPHIDES OF IRON ( FERRO-PHOSPHORUS ) CONTAINING BY WEIGHT :  * - NOT LESS THAN 68 % AND NOT MORE THAN 72 % OF IRON  * - NOT LESS THAN 22 % AND NOT MORE THAN 26 % OF PHOSPHORUS  * - NOT MORE THAN 3,5 % OF SILICON  * OF WHICH NOT LESS THAN 99 % BY WEIGHT IS OF A PARTICLE SIZE OF LESS THAN 20 MICROMETRES , FOR THE MANUFACTURE OF VARNISHES OR PAINTS ( A ) * 0  EX 29.01 D VII * P-CYMENE * 0  EX 29.02 A III * 1 , 2-DIBROMOETHANE * 4  EX 29.08 A III C ) * 2-BROMO-6-METHOXYNAPHTHALENE * 0  EX 29.08 A III C ) * 1 , 2-BIS ( 2 , 4 , 6-TRIBROMOPHENOXY ) ETHANE FOR USE IN THE MANUFACTURE OF ACRYLONITRILE-BUTADIENE-STYRENE ( ABS ) ( A ) * 0  EX 29.08 B I * 2 - ( 2-CHLOROETHOXY ) ETHANOL * 0  EX 29.10 B * 8 , 9-EPOXY-3 - ( 3,4-EPOXYCYCLOHEXYL ) -2 , 4-DIOXASPIRO ( 5.5 ) UNDECANE * 0  EX 29.14 A VII * 1-ISOPROPYL-2 , 2-DIMETHYLTRIMETHYLENE DIISOBUTYRATE * 0  EX 29.14 A XI * 2 , 2-DICHLOROPROPIONIC ACID * 6  EX 29.14 B IV B ) * CROTONIC ACID * 0  EX 29.16 D * 3 , 4-EPOXYCYCLOHEXYLMETHYL-3 , 4-EPOXYCYCLOHEXANECARBOXYLATE * 0  EX 29.21 B II * 0 , 0'-DIOCTADECYL PENTAERYTHRITOL BIS ( PHOSPHITE )  EX 29.21 B II * 1 , 1'-DIMETHYL-2 , 2'-OXYDIETHYLENE TETRAPHENYL BIS ( PHOSPHITE ) * 0  EX 29.22 C II * CYCLOHEX-1 , 3-YLENEDIAMINE ( 1 , 3-DIAMINOCYCLOHEXANE ) * 0  EX 29.22 D VII * PENDIMETHALIN ( ISO ) * 7  EX 29.22 E II * 1 , 8-NAPHTHYLENEDIAMINE * 0  EX 29.23 E * METHYLDOPA ( INN ) * 0  EX 29.23 E * INDENOLOL HYDROCHLORIDE ( INNM ) * 0  EX 29.25 A II * 2-ACRYLAMIDO-2-METHYLPROPANESULPHONIC ACID AND ITS SODIUM OR AMMONIUM SALTS * 0  EX 29.30 * P-PHENYLENE DIISOCYANATE * 0  EX 29.30 * TRANS - ( CYCLOHEX-1 , 4-YLENE DIISOCYANATE ) FOR THE PRODUCTION OF THERMOPLASTIC POLYURETHANE ELASTOMERS ( A ) * 0  EX 29.30 * 3 , 3-DIMETHYLBIPHENYL-4 , 4-DIYLDIISOCYANATE * 0  EX 29.35 Q * TETRAHYDROFURAN , CONTAINING NOT MORE THAN 40 MG PER LITRE IN TOTAL OF TETRAHYDRO-2-METHYLFURAN AND TETRAHYDRO-3-METHYLFURAN FOR THE MANUFACTURE OF ALPHA-4-HYDROXYBUTYL-OMEGA-HYDROXYPOLY ( OXYTETRAMETHYLENE ) ( A ) * 0 EX 29.35 Q * ESTAZOLAM ( INN ) * 0  EX 29.37 * ( 2 , 3-DIOHYDRO-3-OXOBENZ ( D ) ISOTHIAZOL-2-YL ) -N-5-METHYLISOXAZOL-3-YLACETAMIDE S , S-DIOXIDE * 0  EX 29.44 C * CEFTIZOXIME SODIUM ( INNM ) * 0 EX 30.03 A II B ) * ACLARUBICIN HYDROCHLORIDE ( INNM ) * 0  EX 34.02 * ALPHA-METHYL-OMEGA-HYDROXYPOLY ( OXYPROPYLENE ) , HAVING AN AVERAGE MOLECULAR WEIGHT OF BETWEEN 240 AND 260 * 0  EX 34.02 * MIXTURE OF DOCUSATE SODIUM ( INN ) AND SODIUM BENZOATE * 0  EX 34.02 * 2-ALKYL-1 - ( 2 - ( SODIOOXYCARBONYLMETHOXY ) ETHYL ) -1-SODIOOXYCARBONYLMETHYL-2-IMIDAZOLINIUM HYDROXIDE * 0  EX 34.02 * PREPARATION CONTAINING NOT LESS THAN 30 % BY WEIGHT 2-ALKYL-1 - ( 2 - ( SODIOOXYCARBONYLMETHOXY ) ETHYL ) -1-SODIOOXYCARBONYLMETHYL-2-IMIDAZOLINIUM DODECYL SULPHATE * 0  EX 38.19 F II EX 38.19 X * TETRA-ALUMINIUM NONAMAGNESIUM DICARBONATE HEXACOSAHYDROXIDE HEPTA HYDRATE COATED WITH A SURFACE ACTIVE AGENT * 0  EX 38.19 X * A MIXTURE OF 5-ETHYL-2-METHYL-2-OXO-1 , 3 , 2L5-DIOXAPHOSPHORAN-5-YLMETHYL METHYL METHYLPHOSPHONATE AND BIS ( 5-ETHYL-2-METHYL-2-OXO-1 , 3 , 2L5-DIOXAPHOSPHORAN-5-YLMETHYL METHYLPHOSPHONATE * 0  EX 38.19 X * BUTYLETHYLMAGNESIUM DISSOLVED IN ORGANIC SOLVENTS TO A CONCENTRATION OF NOT LESS THAN 19 % AND NOT MORE THAN 30 % BY WEIGHT * 0  EX 38.19 X * MIXTURE OF AMINES DERIVED FROM DIMERIZED FATTY ACIDS WITH AN AVERAGE MOLECULAR WEIGHT OF BETWEEN 520 AND 550 * 0  EX 38.19 X * MIXTURE OBTAINED BY FERMENTATION CONTAINING NOT LESS THAN 5 % BY WEIGHT PEPTIDES HAVING THE STRUCTURE OF THE A CHAIN OF HUMAN INSULIN IN THE FORM OF A SALT OF THE S-SULPHONATE DERIVATIVE * 0  EX 38.19 X * MIXTURE OBTAINED BY FERMENTATION CONTAINING NOT LESS THAN 5 % BY WEIGHT PEPTIDES HAVING THE STRUCTURE OF THE B CHAIN OF HUMAN INSULIN IN THE FORM OF A SALT OF THE S-SULPHONATE DERIVATIVE * 0  EX 38.19 X * CRUDE LITHIUM HYPOCHLORITE * 0  EX 38.19 X * REACTION MIXTURE CONTAINING BENZYL 3-ISOBUTYRYLOXY-1-ISOPROPYL , 2 , 2-DIMETHYLPROPYL PHTHALATE AND BENZYL 3-ISOBUTYRYLOXY-2 , 2 , 4-TRIMETHYLPENTYL PHTHALATE * 0  EX 38.19 X * MIXTURE OF 2 - ( PERFLUOROALKYL ) ETHANETHIOLS CONTAINING C6 TO C14 PERFLUOROALKYL CHAINS * 0  EX 39.01 C I A ) * THERMOSETTING RESIN ARISING FROM THE ALKALI-CATALYZED POLYCONDENSATION OF PHENOL AND FORMALDEHYDE , IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 * 4  EX 39.01 C III A ) * POLYESTER FILM , HAVING A THICKNESS OF NOT LESS THAN 74 MICROMETRES AND NOT MORE THAN 76 MICROMETRES , FOR USE IN THE MANUFACTURE OF FLEXIBLE MAGNETIC DISCS ( FLOPPY DISCS ) ( A ) * 0  EX 39.01 C III A ) * REFLECTING LAMINATED SHEETING , METALLIZED , WHETHER OR NOT DYED , CONSISTING OF TWO OR MORE SHEETS OF POLYESTER AND COATED ON ONE SIDE WITH AN ADHESIVE WHICH IS PROTECTED BY A RELEASE SHEET * 0  EX 39.01 C III A ) * POLYESTER FILM , DYED IN THE MASS OF A THICKNESS OF NOT MORE THAN 15 MICROMETRES AND METALLIZED ON ONE SIDE * 6  EX 39.01 C IV * POLY ( IMINOMETHYLENE-1 , 3-PHENYLENEMETHYLENEIMINOADIPOYL ) IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 * 0  EX 39.02 C I A ) * POLYETHYLENE , IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 , HAVING A DENSITY OF NOT LESS THAN 0,958 AT 23+ C AND CONTAINING BY WEIGHT , NOT MORE THAN :  * - 50 PPM ALUMINIUM  * - 2 PPM CALCIUM  * - 2 PPM CHROMIUM  * - 2 PPM IRON  * - 2 PPM NICKEL  * - 2 PPM TITANIUM  * - 8 PPM VANADIUM  * FOR THE MANUFACTURE OF CHLOROSULPHONATED POLYETHYLENE ( A ) * 0  EX 39.02 C XII * COPOLYMER OF ACRYLIC ACID HAVING NOT MORE THAN 10 % BY WEIGHT OF ALKYL ESTERS OF METHACRYLIC ACID FOR USE AS A THICKENER IN TEXTILE PRINTING PASTES ( A ) * 0  EX 39.02 C XIV A ) * IONOMER RESIN CONSISTING OF A SALT OF A COPOLYMER OF ETHYLENE AND METHACRYLIC ACID * 0  EX 39.02 C XIV A ) * IONOMER RESIN CONSISTING OF A SALT OF A TERPOLYMER OF ETHYLENE , ISOBUTYL ACRYLATE , AND METHACRYLIC ACID * 0  EX 39.02 C XIV A ) * COPOLYMERS OF ETHYLENE WITH ACRYLIC ACID , OR WITH METHACRYLIC ACID , CONTAINING NOT LESS THAN 3 % AND NOT MORE THAN 30 % OF ACRYLIC ACID OR METHACRYLIC ACID BY WEIGHT , IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 * 0  EX 39.02 C XIV A ) * COPOLYMER OF TETRAFLUORETHYLENE AND HEXAFLUORPROPYLENE COMPOUNDED WITH ONE OF THE FOLLOWING :  * - 5 TO 25 % BY WEIGHT OF BARIUM SULPHATE  * - 3 TO 5 % BY WEIGHT OF DIBISMUTH TRIOXIDE  * - 7 TO 9 % BY WEIGHT OF DIBISMUTH CARBONATE DIOXIDE  * - 11 TO 14 % BY WEIGHT OF TUNGSTEN  IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 * 0  EX 39.02 C XIV A ) * POLYMERIZATION PRODUCTS OF A ( POLYBUTADIENE ) POLYOL AND TWO LACTAMS N , N'-LINKED BY THE BIVALENT ACRYL RADICAL OF A DICARBOXYLIC ACID * 0  EX 39.02 C XIV A ) * COPOLYMER OF ETHYLENE WITH CHLOROTRIFLUOROETHYLENE , IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 * 0  EX 39.02 C XIV A ) * TERPOLYMER OF ETHYLENE WITH CHLOROTRIFLUOROETHYLENE AND HEXAFLUORO ( 2-METHYLPROPENE ) IN ONE OF THE FORMS MENTIONED IN NOTE 3 ( B ) TO CHAPTER 39 * 0  EX 56.01 A * ACETALIZED , MULTICOMPONENT SPUN FIBRES WITH A MATRIX FIBRIL STRUCTURE , CONSISTING OF EMULSION POLYMERIZED POLY ( VINYL ALCOHOL ) AND VINYLCHLORIDE * 0  EX 59.01 B I * POLYVINYL ALCOHOL FIBRES , WHETHER OR NOT ACETALIZED * 0  EX 59.17 A * NEEDLE PUNCHED SYNTHETIC FIBRE FELTS ON A WOVEN SYNTHETIC FIBRE BASE COATED OR COVERED ON ONE SIDE WITH POLYTETRAFLUOROETHYLENE FILM , FOR THE MANUFACTURE OF FILTRATION PRODUCTS ( A ) * 0  EX 69.09 B * YARN OF CONTINUOUS CERAMIC FILAMENTS , EACH FILAMENT OF WHICH CONTAINS NOT LESS THAN 12 % BY WEIGHT OF DIBORON TRIOXIDE , NOT MORE THAN 26 % BY WEIGHT OF SILICON DIOXIDE AND NOT LESS THAN 60 % BY WEIGHT OF DIALUMINIUM TRIOXIDE * 0  EX 69.09 B * PLATES MADE OF DIALUMINIUM TRIOXIDE AND TITANIUM CARBIDE WITH DIMENSIONS OF NOT MORE THAN 48 BY 48 MM , FOR THE MANUFACTURE OF MAGNETIC HEADS ( A ) * 0  EX 70.20 A * MATS , OF NON-TEXTILE GLASS FIBRES , OF A WEIGHT PER SQUARE METRE OF NOT MORE THAN 120 GRAMS AND A FIBRE DIAMETER , EXCLUDING ANY COATING , OF NOT MORE THAN 7 MICROMETRES , FOR THE MANUFACTURE OF FILTRATION PRODUCTS ( A ) * 0  EX 70.20 B * YARNS , SPUN FROM CONTINUOUS GLASS FILAMENTS HAVING A DIAMETER OF NOT LESS THAN 5,7 MICROMETRES AND NOT MORE THAN 6,5 MICROMETRES OF 33 OR 34 TEX OR A MULTIPLE THEREOF * 0  EX 70.20 B * YARNS OBTAINED FROM CONTINUOUS SPUN GLASS FILAMENTS HAVING A DIAMETER OF NOT LESS THAN 12,5 MICROMETRES AND NOT MORE THAN 13,5 MICROMETRES TREATED WITH RESORCINOLFORMALDEHYDE , OF NOT LESS THAN 340 TEX AND NOT MORE THAN 680 TEX * 7  EX 77.02 * GROUND AND POLISHED MAGNESIUM SHEETS WHOSE DIMENSIONS DO NOT EXCEED 770 BY 1 020 MM , COATED ON ONE SIDE WITH EPOXY RESIN , INSENSITIVE TO LIGHT * 0  EX 81.04 K I * TITANIUM SPONGE * 0  EX 84.18 C II B ) * COMPONENTS OF SEPARATORS FOR THE SEPARATION OF GASES FROM GAS MIXTURES , CONSISTING OF A BUNDLE OF PERMEABLE HOLLOW FIBRES PASSING THROUGH A BLOCK OF PLASTIC MATERIAL AT ONE END AND SEALED AT THE OTHER END - THE WHOLE BEING ENCLOSED WITHIN A METAL CONTAINER , WHETHER OR NOT PERFORATED , OF AN OVERALL LENGTH OF NOT LESS THAN 300 MM AND NOT MORE THAN 3 700 MM AND A DIAMETER OF NOT MORE THAN 350 MM * 0  EX 84.18 C II B ) * PARTS OF EQUIPMENT FOR THE FILTRATION AND PURIFICATION OF WATER , CONSISTING OF A BUNDLE OF HOLLOW FIBRES OF ARTIFICIAL PLASTIC MATERIAL WITH PERMEABLE WALLS , EMBEDDED IN A BLOCK OF ARTIFICIAL PLASTIC MATERIAL AT ONE END AND PASSING THROUGH A BLOCK OF ARTIFICIAL PLASTIC MATERIAL AT THE OTHER END , THE WHOLE BEING ENCLOSED IN AN ARTIFICIAL PLASTIC CONTAINER ( A ) * 0  EX 84.18 C II B ) * APPARATUS FOR CATALYTIC CONVERSION OF NITROGEN OXIDES INTO NITROGEN AND WATER , CONSISTING OF SHAPED AND FIRED UNITS IN HONEYCOMB STRUCTURE OF A MIXTURE OF VANADIUM OXIDES OR VANADIUM SULPHATES AND TITANIUM DIOXIDE OR BARIUM SULPHATE IN A METALLIC BASKET NOT EXCEEDING 120 BY 120 BY 160 CM * 0  EX 84.18 C II B ) * PARTS OF EQUIPMENT FOR THE PURIFICATION OF WATER BY REVERSE OSMOSIS , CONSISTING ESSENTIALLY OF PLASTIC-BASED MEMBRANES , SUPPORTED INTERNALLY BY TEXTILE MATERIALS WHICH ARE WOUND ROUND A PERFORATED TUBE OF PLASTIC MATERIAL AND HOUSED IN A PLASTIC CYLINDER * 0  EX 84.55 C * WINCHESTER OR THIN FILM TECHNOLOGY MAGNETIC HEADS FOR DISC FILE PERIPHERALS , AS WELL AS CARRYING ARMS EQUIPPED WITH SUCH MAGNETIC HEADS , CAPABLE OF RECORDING TO A DENSITY OF NOT LESS THAN 10 TRACKS PER MILLIMETRE * 0  EX 84.55 C * DOT MATRIX DISPLAYS , WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 15 BY 90 BY 280 MM EXCLUDING CABLES AND CONNECTORS , CONSISTING OF A LAYER OF LIQUID CRYSTALS BETWEEN TWO SHEETS OR PLATES WITH 30 720 DOTS ( ARRANGED IN 64 LINES AND 480 COLUMNS ) , MOUNTED ON A PRINTED-CIRCUIT BOARD COMPRISING ELECTRONIC COMPONENTS PROVIDING DRIVE FUNCTIONS , WITH OR WITHOUT CABLE AND CONNECTOR * 0  EX 84.55 C * DOT MATRIX DISPLAYS CONSISTING OF A LAYER OF LIQUID CRYSTAL BETWEEN TWO GLASS SHEETS OR PLATES WITH A MAXIMUM OF 15 360 DOTS ( ARRANGED IN 64 LINES AND 240 COLUMNS ) , COMPLETE WITH AN INTERFACE ELECTRONICS BOARD IN C-MOS TECHNOLOGY WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 181 BY 76 BY 15 MM , WITH NOT MORE THAN 544 CONNECTING AREAS * 0  EX 84.55 C * MAGNETIC READ/WRITE ELEMENTS IN THIN FILM TECHNOLOGY FOR THE MANUFACTURE OF MAGNETIC HEADS FOR DISC FILE PERIPHERALS , CAPABLE OR RECORDING TO A DENSITY OF NOT LESS THAN 10 TRACKS PER MM , IN THE FORM OF SHEETS MEASURING NOT MORE THAN 48 BY 48 MM AND CONTAINING NOT LESS THAN 200 ELEMENTS OR IN THE FORM OF STRIPS MEASURING NOT MORE THAN 4 BY 48 MM AND CONTANING NOT LESS THAN 10 ELEMENTS ( A ) * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , COMPRISING UV-ERASABLE PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) , WITH A STORAGE CAPACITY OF 256 K BITS CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED :  * - TWO UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) , IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A STORAGE CAPACITY OF 128 K BITS AND A QUARTZ WINDOW ON THE UPPER SURFACE  * - A DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - A DECOUPLING CAPACITOR  * - TWO RESISTANCES  * THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 7832 MM-30  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , CONSTITUTING UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) , WITH A STORAGE CAPACITY OF 256 K BITS , CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED :  * - FOUR UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) , IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS , EACH WITH A STORAGE CAPACITY OF 64 K BITS AND A QUARTZ WINDOW ON THE UPPER SURFACE  * - ONE DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - ONE DECOUPLING CAPACITOR  * THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 7832 MC-35  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , CONSISTING OF TWO STACKED SUBSTRATE LAYERS EACH WITH TWO STATIC RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS S-RAMS ) , IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A STORAGE CAPACITY OF 2 K BITS AND WITH A TOTAL STORAGE CAPACITY OF EITHER 8 K BY 1 BIT , OR 4 K BY 2 BITS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 13 BY 13 MM , WITH NOT MORE THAN 23 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES :  * 4598601 5121850 5121934 5121935 5122148 5123059 5123120 5123128 5123129 5123337 5123339  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , COMPRISING STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 32 K BITS CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS , ON WHICH ARE MOUNTED :  * - TWO STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A STORAGE CAPACITY OF 16 K BITS  * - A DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - A DECOUPLING CAPACITOR  * THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 8804 C-20 EDH 8804 CL-20  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , COMPRISING STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 64 K BITS CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED :  * - FOUR STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A STORAGE CAPACITY OF 16 K BITS  * - A DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - A DECOUPLING CAPACITOR  * THE ASSEMBLIES HAVE NOT MORE THAN 28 CONNECTING PINS AND BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 8808 B-20 EDH 8808 C-10 EDH 8808 C-12 EDH 8808 C-15 EDH 8808 C-20 EDH 8808 CL-15 EDH 8808 CL-20  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , COMPRISING STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 256 K BITS CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED :  * - FOUR STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A CAPACITY OF 64 K BITS  * - A DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - A DECOUPLING CAPACITOR  * THE ASSEMBLIES HAVE NOT MORE THAN 28 CONNECTING PINS AND BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 8832 MC-20  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , CONSISTING OF TWO STACKED SUBSTRATE LAYERS EACH WITH TWO QUASI-STATIC RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY , OTHER THAN DYNAMIC ( N-MOS QUASI-STATIC RAMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A STORAGE CAPACITY OF 14 K BITS AND WITH A TOTAL STORAGE CAPACITY OF EITHER 16 K BY 1 BIT OR 8 K BY 2 BITS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 13 BY 13 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES :  * 4599766 4599767 4599768 4599769 4599770 4599771 4599772 4599773 4599774 4599893  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES COMPRISING A UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( EPROM ) , WITH A STORAGE CAPACITY OF 64 K BITS AND A STATIC RANDOM-ACCESS MEMORY OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 32 K BITS , CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS , ON WHICH ARE MOUNTED :  * - ONE UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( EPROM ) IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , WITH A STORAGE CAPACITY OF 64 K BITS AND WITH A QUARTZ WINDOW ON THE UPPER SURFACE  * - TWO STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS , EACH WITH A STORAGE CAPACITY OF 16 K BITS  * - ONE DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - ONE DECOUPLING CAPACITOR  * - TWO RESISTANCES  * THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 90804 BS-25 ( 15 ) EDH 90804 BS-30 ( 20 )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES COMPRISING UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) WITH A STORAGE CAPACITY OF 128 K BITS AND STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 128 K BITS CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS , ON WHICH ARE MOUNTED :  * - TWO UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS , EACH WITH A STORAGE CAPACITY OF 64 K BITS AND A QUARTZ WINDOW ON THE UPPER SURFACE  * - TWO STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS , EACH WITH A STORAGE CAPACITY OF 64 K BITS  * - ONE DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - ONE DECOUPLING CAPACITOR  * - TWO RESISTANCES  * THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 91616 CL-30 ( 20 )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * MAGNETIC BUBBLE MEMORIES WITH A STORAGE CAPACITY OF NOT MORE THAN 4 MEGABITS CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 43 BY 44 MM , WITH NOT MORE THAN 42 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * BDL 0133 BDL 0134 BDN 0151 MBM 2011 MBM 2256 FBM 54 DB FBM 64 DA 7110 7114-1  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MAGNETIC BUBBLE COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.55 C * ASSEMBLIES FOR AUTOMATIC DATA-PROCESSING MACHINES , COMPRISING UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) WITH A STORAGE CAPACITY OF 64 K BITS AND STATIC RANDOM-ACCESS MEMORY IN C-MOS TECHNOLOGY ( C-MOS S-RAM ) WITH A STORAGE CAPACITY OF 48 K BITS CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM WITH 28 CONNECTING PINS ON WHICH ARE MOUNTED :  * - A UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( EPROM ) IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT WITH A STORAGE CAPACITY OF 64 K BITS AND A QUARTZ WINDOW ON THE UPPER SURFACE  * - THREE STATIC RANDOM-ACCESS MEMORIES IN C-MOS TECHNOLOGY ( C-MOS S-RAM ) IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS EACH WITH A STORAGE CAPACITY OF 16 K BITS  * - A DECODER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT  * - A DECOUPLING CAPACITOR  * - TWO RESISTANCES  * THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 90806 BS-25 ( 15 ) EDH 90806 BS-30 ( 20 )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ASSEMBLIES COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 84.55 C * COMPONENT FORMING THE ARITHMETIC/LOGIC ELEMENT OF A CENTRAL PROCESSING UNIT , COMPRISING NOT MORE THAN NINE PRINTED CIRCUITS BOARDS , WHOSE DIMENSIONS DO NOT EXCEED 290 BY 310 MM ON EACH OF WHICH ARE MOUNTED NOT MORE THAN 121 ECL GATE ARRAYS OR ECL RANDOM ACCESS MEMORIES ( ECL-RAMS ) AND COMBINATIONS THEREOF CONTAINED IN A FRAMEWORK WHOSE DIMENSIONS DO NOT EXCEED 611 BY 501 BY 596 MM WHICH SERVES AS A HOUSING AND INTERCONNECTOR FOR THE PRINTED CIRCUIT BOARDS , WHICH BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * CO1B 2675 E 500 CO1B 2675 H 500 CO1B 2675 H 501 CO1B 2675 H 502 CO1B 2675 H 503 CO1B 2675 H 504  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO COMPONENTS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 84.59 B * INTEGRALLY FORGED , ROUGH-TURNED COMPONENTS , WITH UNIT WEIGHTS OF MORE THAN 150 TONNES , FOR REACTOR PRESSURE VESSELS * 0  EX 84.61 B * HYDRAULIC FIVE-STAGE VALVE , WITH TWO MAGNETIC VALVES FOR SERVO-CONTROL , CONSISTING ESSENTIALLY OF THREE PLASTIC SECTIONS , FOR INCORPORATION IN WATER SOFTENING DEVICES WITH AUTOMATIC REGENERATION ( THROUGHFLOW AND COUNTERFLOW ) WITH A MAXIMUM CAPACITY OF 650 L ION EXCHANGE VOLUME ( A ) * 0  EX 84.63 B II * INTEGRALLY FORGED AND ROUGHLY SHAPED GENERATOR AND TURBINE SHAFTS OF A WEIGHT EXCEEDING 180 TONNES * 0  EX 85.01 B I B ) * DC ELECTRIC MOTOR , BRUSHLESS , WITH OUTSIDE ROTOR OF A MAXIMUM DIAMETER OF 55 MM , COUPLING FLANGE OF A DIAMETER OF 77 MM AND PRECISION-MADE CHUCK OF A DIAMETER OF 44 MM , FOUR-PHASE WINDING , RATED SPEED OF 3 600 RPM , SUPPLY VOLTAGE FROM 10,8 TO 13,2 VOLTS AND FITTED WITH WIRES AND CONNECTORS * 0  EX 85.01 B I B ) * HYBRID-TYPE STEP-BY-STEP MOTOR , SIZE 39 MM , OR " SIZE 16 " , WITH ANGLE OF STEP OF 0,9+ , 400 STEPS PER REVOLUTION , 4-PHASE ROTATION SEQUENCE WITH BIPOLAR-TYPE WINDING , CONSISTING OF A ROTOR , OF A LAMINATED STATOR HELD BETWEEN TWO SQUARE FLANGES , NOT MORE THAN 40 MM WIDE , FITTED WITH BITERMINATE SHAFT , WIRES AND CONNECTORS * 0  EX 85.01 B I B ) * DC ELECTRIC MOTOR , BRUSHLESS , WITH AN INCORPORATED ELECTRONIC CONTROL PLATE , OUTSIDE ROTOR WITH CIRCULAR CROSS-SECTION AND MAXIMUM DIAMETER OF 95 MM , ALUMINIUM PRECISION-MADE HUB WITH INSIDE DIAMETER OF 28,6 MM , SPEED OF 300 RPM , SUPPLY VOLTAGE OF 12 VOLTS MORE OR LESS 10 % * 0  EX 85.21 A III AND EX 85.21 A V * CATHODE-RAY TUBES ( COLOUR ) EQUIPPED WITH A PERFORATED MASK ( SO-CALLED " DOT MASK " ) WITH ELECTRON GUNS PLACED IN A TRIANGLE ( " DELTA " TECHNIQUE ) OR PLACED SIDE BY SIDE ( " IN-LINE " TECHNIQUE ) WITH CONVERGENCE ERRORS OF NOT MORE THAN 0,8 MM IN THE CORNERS , HAVING A DIAGONAL ANGLE OF DEFLECTION NOT EXCEEDING 90+ AND WITH MAXIMUM COLOUR DOT SPACING OF LESS THAN 0,4 MM * 0  EX 85.21 A V * COLOUR CATHODE-RAY TUBES , USING SHADOW MASK , IN-LINE TECHNOLOGY IN WHICH IMAGES ARE DISPLAYED ON A SCREEN WITH A USABLE SURFACE NOT EXCEEDING 165 BY 165 MM FOR USE IN ELECTRONIC FLIGHT INSTRUMENT , WARNING AND SYSTEMS DISPLAYS ( A ) * 0  EX 85.21 A V * DISPLAYS IN THE FORM OF A TUBE CONSISTING OF A GLASS HOUSING MOUNTED ON A BOARD WHOSE DIMENSIONS DO NOT EXCEED 350 BY 300 MM EXCLUDING LEADS . THE TUBE CONTAINS ONE OR MORE ROWS OF CHARACTERS OR LINES ARRANGED IN ROWS , EACH CHARACTER OR LINE CONSISTING OF FLUORESCENT OR PHOSPHORESCENT ELEMENTS . THESE ELEMENTS ARE MOUNTED ON A METALLIZED BASE WHICH IS COVERED WITH FLUORESCENT SUBSTANCES OR PHOSPHORESCENT SALTS WHICH GIVE OFF LIGHT WHEN BOMBARDED WITH ELECTRONS * 0  EX 85.21 A V * CATHODE RAY TUBES WITH DOT MASK ( SO-CALLED DOT-MASK TECHNOLOGY ) , WITH ELECTRON GUNS ARRANGED IN TRIANGULAR FASHION ( SO-CALLED DELTA TECHNOLOGY ) , WITH A DISTANCE BETWEEN THE COLOURED DOTS OF 0,31 MM , WITH DEVICES FOR AUTOMATIC CONVERGENCE * 0  EX 85.21 A V * CATHODE RAY TUBES WITH A MEMORY ( DIRECT VIEW STORAGE TUBES ) FOR THE REPRODUCTION OF ALPHANUMERIC AND ANALOGUE DATA , EQUIPPED WITH A SCANNING DEVICE , FOR READING THE IMAGES * 0  EX 85.21 D II * DIGITAL DISPLAYS OF A SIZE NOT EXCEEDING 25 BY 35 MM , CONSISTING OF A PRINTED CIRCUIT BOARD ON WHICH ARE MOUNTED , UNDER A PLASTIC COVER , UP TO 22 LIGHT-EMITTING DIODES MANUFACTURED FROM GALLIUM-BASED SEMI-CONDUCTOR COMPOUNDS . EACH DISPLAY CONSISTS OF A SINGLE CHARACTER WITH OR WITHOUT A PLUS OR MINUS SIGN AND/OR ONE OR TWO DOTS * 0  EX 85.21 D II * DIGITAL DISPLAYS , CONSISTING OF A PRINTED CIRCUIT BOARD OF A SIZE NOT EXCEEDING 35 BY 90 MM WITH A SINGLE LINE OF CHARACTERS , NOT LESS THAN THREE IN NUMBER , COMPRISING LIGHT-EMITTING DIODES MADE FROM GALLIUM-BASED SEMI-CONDUCTOR COMPOUNDS MOUNTED THEREON . EACH CHARACTER IS COMPOSED OF UP TO EIGHT SEGMENTS WITH OR WITHOUT A DECIMAL POINT AND THE LINE OF CHARACTERS HAS A PROTECTIVE COVER OF TRANSPARENT PLASTIC * 0  EX 85.21 D II * MONOLITHIC INTEGRATED CIRCUITS , CONSISTING OF EIGHT INDEPENDENT ELEMENTS CAPABLE OF CONTROLLING THE EIGHT SEGMENTS AND/OR CHARACTERS OF FLUORESCENT OR GAS DISCHARGE DISPLAYS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 7 BY 23 MM , WITH NOT MORE THAN 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES :  * 513 514 534 594 6118 6128 6138  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * READ-ONLY MEMORIES ( ROMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , WITH A STORAGE CAPACITY OF 16 K BY 8 BITS , WITH READ-REGISTER AND SERIAL OUTPUT CONTROL , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 50 BY 16 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR INCLUDING ONE OF THOSE COMBINATIONS :  * FROM 62000 TO 62999  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * READ-ONLY MEMORY IN C-MOS TECHNOLOGY ( C-MOS ROM ) WITH A STORAGE CAPACITY OF 256 K BITS AND A STANDBY CURRENT OF NOT MORE THAN 0,03 MA , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 50 MM , WITH NOT MORE THAN 54 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * HN 61256 HN 613256  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * READ-ONLY MEMORY OF C-MOS TECHNOLOGY ( C-MOS ROM ) WITH A STORAGE CAPACITY OF 1 MEGABIT IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 37 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * HN 62301 P  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS ROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * PROGRAMMABLE , NON-ERASABLE , READ-ONLY MEMORIES ( PROMS ) OF SCHOTTKY TTL TECHNOLOGY , WITH A STORAGE CAPACITY OF 2 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS OR CONTACT AREAS , AND BEARING :* - AN IDENTIFICATION MARKING EITHER CONSISTING OF ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS OR INCLUDING ONE OF THOSE COMBINATIONS :  * 27 S 12 27 S 13 28 L 22 28 LA 22 28 L2 XMFC 29613 29770 29771 38510 5305 5306 5308 5309 53 S 240 53 S 241 54 S 570 54 S 571 5604 5624 6305 6306 6308 6309 63 S 240 63 S 241 6335 6336 7053 7058 74 S 570 74 S 571 76 LS 03 7620 7621 82 S 114 82 S 130 82 S 131 93436 93446 MB 7115 MB 7116 MB 7117 MB 7118  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 11,5  EX 85.21 D II * PROGRAMMABLE , NON-ERASABLE , READ-ONLY MEMORIES ( PROMS ) WITH A STORAGE CAPACITY OF 4 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS OR 28 CONTACT AREAS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * 18 S 42 18 S 46 18 SA 42 18 SA 46 24 S 41 24 SA 41 27 S 15 27 S 25 27 S 26 27 S 27 27 S 28 27 S 29 27 S 30 27 S 31 27 S 32 27 S 33 28 L 42 28 L 45 28L 46 28 P 42 28 P 45 28 R 45 28 S 4 XFD 28 SA 41 28 S 42 28 SA 42 28 S 45 28 S 46 28 SA 46 29620 29621 29622 29623 29624 29625 29626 29627 3604 3624 3625 38510 5340 5341 53 S 440 53 RA 441 53 RS 441 53 S 441 5348 5349 5350 5351 5352 5353 54 S 472 54 S 473 54 S 474 54 S 475 54 S 476 54 S 477 54 S 572 54 S 573 54740 54741 5605 5625 6340 6341 63 S 440 63 RA 441 63 RS 441 63 S 441 6348 6349 6350 6351 6352 6353 HM 6641 7054 7059 7121 7122 7123 7124 7125 7126 74 S 472 74 S 473 74 S 474 74 S 475 74 S 476 74 S 477 74 S 572 74 S 573 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 82 HS 137 82 HS 147 82 S 115 82 S 136 82 S 137 82 S 140 82 S 141 82 S 142 82 S 146 82 S 147 93438 93448 93452 93453  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * PROGRAMMABLE , NON-ERASABLE , READ-ONLY MEMORIES ( PROMS ) WITH A STORAGE CAPACITY OF 8 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS OR 28 CONTACT AREAS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS OR INCLUDING ONE OF THOSE COMBINATIONS :  * 24 S 81 24 SA 81 24 S 86 27 S 180 27 S 181 27 S 185 27 S 35 28 L 85 28 L 86 28 P 85 28 R 35 28 R 85 28 S 2708 28 S 85 28 S 86 28 SA 86 28 S 8 XMFE 29623 29630 29631 29632 29633 29634 29635 29636 29637 29650 29651 29652 29653 3628 5380 5381 5388 5389 53 S 840 53 S 841 54 LS 478 54 S 2708 54 S 454 54 S 455 54 S 478 54 S 479 6380 6381 6388 6389 63 S 840 63 S 841 7050 7055 7060 7127 7128 7129 7130 7131 7132 74 LS 478 74 S 2708 74 S 454 74 S 455 74 S 478 74 S 479 7608 7680 7681 7684 7685 7686 7687 7688 7689 77 S 180 77 S 181 77 S 184 77 S 185 77 S 186 77 S 187 TBPS 81 M 82707 82708 82 HS 185 82 LS 180 82 LS 181 82 S 180 82 S 181 82 S 182 82 S 183 82 S 184 82 S 185 82 S 2708 87 S 180 87 S 181 87 S 184 87 S 185 87 S 186 87 S 187 93450 93451 93460 93461 93465 93466 93 L 450 93 L 451 9460  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) WITH A STORAGE CAPACITY OF 2 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH A QUARTZ WINDOW ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * B 1702 A AMI 702 ADC 82140 PP  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO EPROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) WITH A STORAGE CAPACITY OF 16 K BY 8 BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH A QUARTZ WINDOW ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES :  * 27128  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO EPROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) WITH A STORAGE CAPACITY OF 256 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH A QUARTZ WINDOW ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES OR FIGURES AND LETTERS :  * D 27256 27256 TMS 27256 JL 27 C 256  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO EPROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) , IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS , CONSISTING OF A MULTILAYER SUBSTRATE WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR , TWO RESISTANCES AND TWO EPROMS EACH HAVING A STORAGE CAPACITY OF 128 K BITS AND WITH A TOTAL STORAGE CAPACITY OF 256 K BITS , WITH TWO QUARTZ WINDOWS ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 7832 MM-30  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO EPROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MEMORIES IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS , CONSISTING OF A MULTILAYER SUBSTRATE WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR AND FOUR UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) EACH HAVING A STORAGE CAPACITY OF 64 K BITS AND WITH A TOTAL EPROM CAPACITY OF 256 K BITS , WITH A QUARTZ WINDOW ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 7832 MC-35  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MEMORIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( E2PROMS ) WITH A STORAGE CAPACITY OF 256 BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 10 BY 12 MM , WITH NOT MORE THAN EIGHT CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * NMC 9306  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRICALLY ERASABLE PROGRAMMABLE , READ-ONLY MEMORIES ( E2PROMS ) WITH A STORAGE CAPACITY OF 4 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 33 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * X 2804 A  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( E2PROMS ) WITH A STORAGE CAPACITY OF 16 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 33 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * X 2816 A 52 B 13 52 B 13 H  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( E2PROMS ) WITH A STORAGE CAPACITY OF 64 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * X 2864 A MCM 2864 52 B 33 52 B 33 H  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( E2PROMS ) WITH A STORAGE CAPACITY OF 128 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * X 28128 A  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( E2PROMS ) WITH A STORAGE CAPACITY OF 256 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * X 28256 A  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * DYNAMIC , RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS D-RAMS ) WITH A STORAGE CAPACITY OF 256 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 34 MM , WITH NOT MORE THAN 20 CONNECTING PINS OR CONTACT AREAS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * 41245 PD 41256 D TMM 41257 TMM 4256 AP TMM 4256 P MCM 4256 S TMS 4256 TMS 4257 MCM 4267 S HM 50257 MCM 6256 MCM 6257 8156 81257 82256  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS D-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 5  EX 85.21 D II * DYNAMIC , RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS D-RAMS ) WITH A STORAGE CAPACITY OF 64 K BITS BY 4 IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 34 MM , WITH NOT MORE THAN 20 CONNECTING PINS OR CONTACT AREAS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * TMS 4464 NL  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS D-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 256 BY 4 BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * M 120 2101 21 H 01 2102 2111 21 H 11 2112 21 H 12 8101 8111 9101 91 L 01 9111 91 L 11 9112 91 L 12  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF TTL TECHNOLOGY ( TTL S-RAMS ) WITH A STORAGE CAPACITY OF 1 K BIT , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 30 MM , WITH NOT MORE THAN 22 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * 2205 2510 2511 74 LS 214 74 LS 215 74 LS 314 74 LS 315 74 S 207 74 S 208 74 S 214 74 S 314 93412 93 L 412 93415 93 L 415 93422 93 L 422 93425 93 F 425 93 L 425  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO TTL S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF H-MOS TECHNOLOGY ( H-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 1 K BY 4 BITS AND ACCESS TIME NOT EXCEEDING 70 NS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 23 MM , WITH NOT MORE THAN 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * PD 2149 SY 2149 H AM 2149 TMS 2149  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO H-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF COMPLEMENTARY MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 4 K BY 1 BIT , A MAXIMUM ACCESS TIME NOT EXCEEDING 70 NS AND A STANDBY MODE SUPPLY CURRENT OF LESS THAN 1 MA , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE DIMENSIONS DO NOT EXCEED 9 BY 26 MM , WITH 18 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF/OR INCLUDING ONE OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * 6147 MCM 61 L 47  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 4  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 8 K BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * 4008 4118 PD 421 4801 8104 8108 8112 8114 8185  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES ( S-RAMS ) , WITH A STORAGE CAPACITY OF 16 K BY 1 BIT , A MAXIMUM ACCESS TIME OF 35 NS AND A STANDBY POWER OF NOT MORE THAN 150 MILLIWATTS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 33 MM , WITH NOT MORE THAN 20 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * HM 6267 HP-35 MCM 2016-35 MB 81C 67-35  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 2 K BY 8 BITS AND A MAXIMUM ACCESS TIME OF 45 NS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 33 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * TMM 2018 H-35 TMM 2018 H-45 65161 65162  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORY OF C-MOS TECHNOLOGY ( C-MOS S-RAM ) WITH A STORAGE CAPACITY OF 2 K BY 8 BITS AND WITH A MAXIMUM STANDBY POWER OF 0,025 MILLIWATTS AT 25+ C IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 33 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * TC 5516 A TC 5517 A MB 84-16-20 L MB 84-16-25 L MB 84-17-20 L MB 84-17-25 L MB 84-18-20 L MB 84-18-25 L  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) WITH A STORAGE CAPACITY OF 64 K BITS IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 18 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS OR INCLUDING ONE OF THOSE COMBINATIONS :  * TC 5564 TC 5565 C HM 6264 P-12 HM 6264 P-15 MB 8464 MCM 6164 6264 LFP-15  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS S-RAMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF TWO STACKED SUBSTRATE LAYERS EACH WITH TWO CHIPS , EACH HAVING A STORAGE CAPACITY OF 2 K BITS AND WITH A TOTAL STORAGE CAPACITY OF 8 K BY 1 BIT OR 4 K BY 2 BITS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 13 BY 13 MM , WITH NOT MORE THAN 23 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES :  * 4598601 5121850 5121934 5121935 5122148 5123059 5123120 5123128 5123129 5123337 5123339  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR AND TWO CHIPS EACH HAVING A STORAGE CAPACITY OF 16 K BITS AND WITH A TOTAL STORAGE CAPACITY OF 32 K BITS , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 8804 C-20 EDH 8804 CL-20  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR AND FOUR CHIPS EACH HAVING A STORAGE CAPACITY OF 16 K BITS AND WITH A TOTAL STORAGE CAPACITY OF 64 K BITS , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 8808 B-20 EDH 8808 C-10 EDH 8808 C-12 EDH 8808 C-15 EDH 8808 C-20 EDH 8808 CL-15 EDH 8808 CL-20  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A MULTILAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR AND FOUR CHIPS EACH HAVING A STORAGE CAPACITY OF 64 K BITS AND WITH A TOTAL STORAGE CAPACITY OF 256 K BITS , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 8832 MC-20  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS S-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A STATIC , RANDOM-ACCESS MEMORY ( S-RAM ) WITH A STORAGE CAPACITY OF 256 BITS SUPERIMPOSED BIT-FOR-BIT ON A PROGRAMMABLE , ELECTRICALLY ERASABLE , READ-ONLY MEMORY ( E2PROM ) , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 24 MM , WITH NOT MORE THAN 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * X 2210 X 2443 X 2444  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO S-RAMS SUPERIMPOSED ON E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A STATIC , RANDOM-ACCESS MEMORY ( S-RAM ) WITH A STORAGE CAPACITY OF 1 K BIT , SUPERIMPOSED BIT-FOR-BIT ON AN ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( E2PROM ) , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 24 MM , WITH NOT MORE THAN 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * X 2001 X 2201 A X 2212  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO S-RAMS STACKED ON E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A STATIC , RANDOM-ACCESS MEMORY ( S-RAM ) , WITH A STORAGE CAPACITY OF 2 K BITS , SUPERIMPOSED BIT-FOR-BIT ON AN ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( E2PROM ) , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 24 MM , WITH NOT MORE THAN 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF THE FOLLOWING COMBINATION OF FIGURES AND LETTER :  * X 2002  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO S-RAMS STACKED ON E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A STATIC , RANDOM-ACCESS MEMORY ( S-RAM ) WITH A STORAGE CAPACITY OF 4 K BITS , SUPERIMPOSED BIT-FOR-BIT ON AN ELECTRICALLY ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( E2PROM ) , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 24 MM , WITH NOT MORE THAN 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF THE FOLLOWING COMBINATION OF FIGURES AND LETTER :  * X 2004  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SRAMS STACKED ON E2PROMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * " QUASI-STATIC " RANDOM-ACCESS MEMORIES OF N-MOS TECHNOLOGY ( N-MOS QUASI-STATIC RAMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF TWO STACKED SUBSTRATE LAYERS , EACH WITH TWO CHIPS , EACH HAVING A STORAGE CAPACITY OF 4 K BITS AND WITH A TOTAL STORAGE CAPACITY OF 16 K BY 1 BIT OR 8 K BY 2 BITS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 13 BY 13 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES :  * 4599766 4599767 4599768 4599769 4599770 4599771 4599772 4599773 4599774 4599893  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS QUASI-STATIC RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * RANDOM-ACCESS MEMORIES OF ECL TECHNOLOGY ( ECL-RAMS ) WITH A STORAGE CAPACITY OF 1 K BY 4 BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 10 BY 10 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES OR FIGURES AND LETTERS :  * PB 10474 100474  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ECL-RAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MEMORIES , IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS CONSISTING OF A MULTI-LAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR , TWO RESISTANCES AND ONE UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORY ( EPROM ) HAVING A STORAGE CAPACITY OF 64 K BITS , TWO STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) EACH HAVING A STORAGE CAPACITY OF 16 K BITS AND WICH A TOTAL S-RAM STORAGE CAPACITY OF 32 K BITS , WITH NOT MORE THAN 28 CONNECTING PINS , WITH A QUARTZ WINDOW ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 90804 BS-25 ( 15 ) EDH 90804 BS-30 ( 20 )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MEMORIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MEMORIES , IN THE FORM OF MONOLITHIC INTEGRATED CIRCUITS CONSISTING OF A MULTI-LAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR , TWO RESISTANCES AND TWO UV-ERASABLE , PROGRAMMABLE , READ-ONLY MEMORIES ( EPROMS ) , EACH HAVING A STORAGE CAPACITY OF 64 K BITS AND WITH A TOTAL EPROM CAPACITY OF 128 K BITS , TWO STATIC RANDOM-ACCESS MEMORIES OF C-MOS TECHNOLOGY ( C-MOS S-RAMS ) EACH HAVING A STORAGE CAPACITY OF 64 K BITS AND WITH A TOTAL S-RAM STORAGE CAPACITY OF 128 K BITS , WITH NOT MORE THAN 28 CONNECTING PINS , WITH TWO QUARTZ WINDOWS ON THE UPPER SURFACE AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * EDH 91616 CL-30 ( 20 )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MEMORIES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * FIELD PROGRAMMABLE ARRAY LOGICS ( PALS ) OF BIPOLAR TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , WITH FUSIBLE LINKS , A PROGRAMMABLE AND ARRAY , FIXED OR ARRAY , NOT MORE THAN 20 INPUTS AND NOT MORE THAN 20 INPUTS AND NOT MORE THAN 10 OUTPUTS , WHETHER OR NOT WITH REGISTERS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 19 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * 10 H 8 10 L 8 12 H 6 12 L 6 12 L 10 14 H 4 14 L 4 14 L 8 16 A 4 16 C 1 16 H 2 16 L 2 16 L 6 16 L 8 16 R 4 16 R 6 16 R 8 16 X 4 18 L 4 20 C 1 20 L 2 20 L 10 20 X 4 20 X 8 20 X 10  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO PALS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 5  EX 85.21 D II * PROGRAMMABLE , NON-ERASABLE , LOGIC CIRCUITS ( FIELD PROGRAMMABLE LOGIC ARRAY ) OF TTL SCHOTTKY TECHNOLOGY , WITH NOT MORE THAN 48 AND FUNCTIONS , NOT MORE THAN EIGHT OR FUNCTIONS , AND NOT MORE THAN 16 INPUTS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * FP 54 AS 839 FP 54 AS 840 SN 54 LS 333 SN 54 LS 334 SN 54 LS 335 SN 54 LS 336 FP 74 AS 839 FP 74 AS 840 SN 74 LS 333 SN 74 LS 334 SN 74 LS 335 SN 74 LS 336 82 S 100 82 S 101 93458 93459  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO PROGRAMMABLE LOGIC ARRAYS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 5  EX 85.21 D II * SEMI-CUSTOM LOGIC ARRAY ( GATE ARRAYS ) OF C-MOS TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , WITH NOT LESS THAN 8 000 2-INPUT NAND FUNCTIONS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 39 BY 39 MM , WITH NOT LESS THAN 179 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * MB 66000 VH  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS LOGIC ARRAYS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * SINGLE-CHIP MICROCOMPUTERS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF AN ARITHMETICAL UNIT WITH A CAPACITY OF FOUR BITS PLUS A READ-ONLY MEMORY ( ROM ) WITH A CAPACITY OF NOT LESS THAN 18 K BITS AND NOT MORE THAN 65 K BITS AND A RANDOM-ACCESS MEMORY ( RAM ) WITH A CAPACITY OF NOT LESS THAN 512 BITS AND NOT MORE THAN 4 K BITS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 58 MM , WITH NOT MORE THAN 80 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * CD 3200-3299 TMC 0270-0279 TMC 0500-0599 TMC 0980-0989 TMC 1500-1599 TMC 1980-1999 TP 0310-03299 TP 0450-04599 TP 0480-04899 TP 0500-05999 HD 38800 HD 38820 HD 44796 HD 44800 HD 44801 HD 44820 HD 44840 HD 44860  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SINGLE-CHIP MICROCOMPUTERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * CENTRAL PROCESSING UNIT OF H-MOS TECHNOLOGY ( H-MOS CPU ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A 16 BY 16 BIT SERVICE MEMORY , A 16 BY 20 BIT SERVICE MEMORY , A 32 BY 32 BIT SERVICE MEMORY , AN 8 BY 8 BIT SERVICE MEMORY , A 16 BIT REGISTER , TWO 20 BIT REGISTERS , AN 8 BIT REGISTER , ONE 12 BIT REGISTER , A 5 BIT COUNTER AND TIMING NETWORK , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 25 BY 25 MM , WITH NOT MORE THAN 68 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * LSI-604041855  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO H-MOS CENTRAL PROCESSING UNITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * CONTENTION RESOLVING LOCAL AREA NETWORK ( LAN ) CONTROLLERS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 53 BY 16 MM , WITH NOT MORE THAN 48 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS OR INCLUDING ONE OF THOSE COMBINATIONS :  * MCM 68590 AM 7990 8001 8003 82586  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO CONTENTION RESOLVING LOCAL AREA NETWORK CONTROLLERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * DIRECT-ACCESS MEMORY CONTROLLERS OF N-MOS TECHNOLOGY ( N-MOS DMA CONTROLLER ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 23 BY 82 MM , WITH NOT MORE THAN 64 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS OR INCLUDING ONE OF THOSE COMBINATIONS :  * HD 6844 HD 68 A 44 HD 68 B 44 HD 68450-4 HD 68450-6 HD 68450-8 8237 8257 AM 9517 A CO 21698 MCM 68440 MCM 68450  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS DMA CONTROLLERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * GRAPHIC DISPLAY CONTROLLER ( GDC ) WITH THE CAPACITY FOR CONTROLLING A 256 K WORD 16 BIT MEMORY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 15 BY 52 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * PD 7220  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO GDCS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * HARD-DISC CONTROLLERS OF N-MOS TECHNOLOGY ( N-MOS HDCS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 15 BY 53 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * WD 1010 PD 7261  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS HDCS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MULTI-PROTOCOL COMMUNICATION CONTROLLER OF MOS TECHNOLOGY ( MOS-MPCC ) FOR THE TRANSMISSION AND RECEIVING OF DATA SPECIALIZED IN THE SYNCHRONOUS MODE , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 54 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES :  * 16456 2652 68652 8273 8274  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MULTI-PROTOCOL COMMUNICATION CONTROLLERS ( MOS-MPCC ) COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ARITHMETIC-LOGIC UNITS OF H-MOS TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF ONE 32 BIT REGISTER , ONE 24 BIT REGISTER , ONE 4 BIT REGISTER , TWELVE 1 BIT REGISTERS , TWO 16 BY 24 BIT SERVICE MEMORIES , ONE LOGIC NETWORK PERFORMING ARITHMETIC AND LOGIC OPERATIONS , DECODIFYING LOGIC , AN ERROR DETECTION AND MANAGEMENT LOGIC , ONE 8 BIT COUNTER AND A TIMING NETWORK , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 23 BY 82 MM , WITH NOT MORE THAN 64 CONNECTING PINS AND BEARING :  * - THE IDENTIFICATION MARKING :  * ALU 0486  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ARITHMETIC-LOGIC UNITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * LOGIC CONTROL CIRCUITS OF H-MOS TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF ONE 7 BIT REGISTER , THREE TIMERS , ONE MULTIPLEXER , SEQUENTIAL AND COMBINING NETWORKS INTENDED TO PERFORM CONTROL OPERATIONS , DECODIFYING LOGIC , ERROR DETECTION AND MANAGEMENT LOGIC AND A TIMING NETWORK , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 23 BY 82 MM , WITH NOT MORE THAN 64 CONNECTING PINS AND BEARING :  * - THE IDENTIFICATION MARKING :  * MIC 0482  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO LOGIC CONTROL CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * LOGIC CIRCUIT OF H-MOS TECHNOLOGY ( N-MOS LC ) SERVING AS A CLOCK GENERATOR FOR CENTRAL PROCESS UNIT , MAIN MEMORY AND INPUT/OUTPUT INTERFACES , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 25 BY 25 MM , WITH NOT MORE THAN 68 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * H 108982 ( MCC )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO H-MOS LOGIC CIRCUITS ( H-MOS LCS ) COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * SEQUENCE CONTROL CIRCUITS OF H-MOS TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF ONE 32 BIT REGISTER , THREE 16 BIT REGISTERS , ONE 16 BY 16 BIT SERVICE MEMORY , ONE 7 BY 17 BIT LAST-IN FIRST-OUT ( LIFO ) MEMORY , ONE ADDER CIRCUIT , DECODIFYING LOGIC , PRIORITY LOGIC , ERROR DETECTION AND MANAGEMENT LOGIC , ONE 16 BIT MULTIPLEXER , ONE 8 BIT COUNTER AND A TIMING NETWORK , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 23 BY 82 MM , WITH NOT MORE THAN 64 CONNECTING PINS AND BEARING :  * - THE IDENTIFICATION MARKING :  * CSS 0484  * OR * - OTHER IDENTIFICATION MARKINGS RELATING TO SEQUENCE CONTROL CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ERROR CORRECTION AND DETECTION UNIT ( ECDU ) OF BIPOLAR TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 62 MM , WITH NOT MORE THAN 48 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * 2960 74 F 630 74 F 631 DP 8400 74 LS 630 74 LS 631  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ERROR CORRECTION AND DETECTION UNITS ( ECDUS ) COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ERROR DETECTION AND CORRECTION CIRCUIT OF H-MOS TECHNOLOGY CAPABLE OF DETECTING AND CORRECTING SINGLE BIT ERRORS AND DETECTING ALL DOUBLE BIT ERRORS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 25 BY 25 MM , WITH NOT MORE THAN 68 CONTACT AREAS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES :  * 8206  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO H-MOS ERROR DETECTION AND CORRECTION CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * BURST ERROR PROCESSOR ( BEP ) OF H-MOS TECHNOLOGY FOR DETECTING AND CORRECTING MULTIPLE ERRORS DERIVED FROM A LINE OF MAGNETIC DISCS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 54 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * Z 8065 AM 9520 AM 9521  * OR  * - ANY OTHER IDENTIFICATION MARKING RELATING TO H-MOS BURST ERROR PROCESSOR COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRONIC CONTROL CIRCUIT OF BIPOLAR TECHNOLOGY IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT FOR THE CONTROL OF DYNAMIC RANDOM-ACCESS MEMORIES ( D-RAMS ) , CAPABLE OF MULTIPLEXING ADDRESSES AND GENERATING TIMING , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 62 MM , WITH NOT MORE THAN 48 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * DP 8408 DP 8409  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ELECTRONIC CONTROL CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * N-MOS PROGRAMMABLE COMMUNICATION INTERFACES ( N-MOS PCIS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTER :  * 8251 A  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS PCIS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 11,5  EX 85.21 D II * ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE ( EPCI ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 16 BY 38 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES :  * 2661  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO EPCIS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * SERIAL INTERFACES , CAPABLE OF IMPLEMENTING THE DATA STREAM ENCODING , DECODING AND ASSOCIATED CONTROL FUNCTIONS FOR A LOCAL AREA NETWORK , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 33 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF THE FOLLOWING COMBINATION OF FIGURES OR FIGURES AND LETTERS OR ONE OF THOSE COMBINATIONS :  * AM 7991 8002 8023 82501  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SERIAL INTERFACE DEVICES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * N-MOS PROGRAMMABLE INTERVAL TIMERS ( N-MOS PITS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES :  * 8253  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO N-MOS PITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 11,5  EX 85.21 D II * C-MOS CLOCK CIRCUITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 54 MM , WITH NOT MORE THAN 42 CONNECTING PINS , FOR THE PRODUCTION OF AUTOMATIC TIME-SWITCHES , INSTRUMENT PANEL CLOCKS AND OF A SIMILAR TYPE FOR MOTOR VEHICLES ( A ) , AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * HI 2060 HI 2065 T 3605  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO CLOCK CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * C-MOS CLOCK CIRCUITS , OPERATING FROM A SINGLE 1,5 V POWER SUPPLY , WITH A LIQUID CRYSTAL DISPLAY ( LCD ) DRIVER , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 15 BY 21 MM , WITH NOT MORE THAN 56 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * TC 8219 AF  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS CLOCK CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * P-MOS 12/24-HOUR CLOCK CIRCUITS , INCORPORATING AN ELAPSED TIME FACILITY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 53 BY 14 MM , WITH NOT MORE THAN 42 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * MM 53124 LM 8363  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO CLOCK CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * AMPLIFIER , IN THE FORM OF A MONOLITHIC INTEGRATED ANALOGUE CIRCUIT , CONTAINED IN A HOUSING WHOSE DIMENSIONS DO NOT EXCEED 2 BY 4 BY 4 MM , WITH NOT MORE THAN 10 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * V 35 C 05  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO AMPLIFIERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION  * THIS AMPLIFIER IS FOR THE MANUFACTURE OF PRODUCTS FALLING WITHIN SUBHEADING 90.19 B I ( A ) * 0  EX 85.21 D II * TRANSCEIVERS WITH FOUR CHANNELS ( QUAD BUS ) OF ALP SCHOTTKY TECHNOLOGY WITH ON-CHIP D TYPE REGISTERS AND INTERNAL ODD 4 BIT PARITY GENERATOR/CHECKER , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 9 BY 28 MM , WITH NOT MORE THAN 20 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * AM 2907  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO TRANSCEIVERS ( QUAD BUS ) COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * FOUR-LINE DRIVERS OF ADVANCED , LOW-POWER SCHOTTKY TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 20 BY 7 MM , WITH NOT MORE THAN 16 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * AM 26LS29 SN 75172 SN 75174  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO FOUR-LINE DRIVERS OF ALPS TECHNOLOGY COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * 16 BIT MICROPROCESSOR OF BIPOLAR TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 67 BY 24 MM , WITH NOT MORE THAN 52 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * AM 29116  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO 16 BIT MICROPROCESSORS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * NUMERIC PROCESSOR EXTENSION UNIT OF H-MOS TECHNOLOGY ( H-MOS NPX ) CONTAINING NOT MORE THAN 14 REGISTERS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A PACKAGE WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 15 BY 52 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATION OF FIGURES AND LETTER :  * C 8087-3 8087-2 80287  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO H-MOS NPXS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * FLOPPY-DISC DATA SEPARATOR ( FDDS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A PACKAGE WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 10 MM , WITH NOT MORE THAN EIGHT CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * FDC 9216 FDC 9216-B WD 9216-00 WD 9216-01  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO FDDS , COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * C-MOS-PHONEME SPEECH SYNTHESIZER , WITH A SUPPLY CURRENT OF LESS THAN 10 MA , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * SC 01 SSI 263  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO PHONEME SPEECH SYNTHESIZERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * TRIPLE VIDEO DIGITAL TO ANALOGUE CONVERTER ( VDAC ) , EACH CHANNEL HAVING A CAPACITY OF NOT MORE THAN 8 BITS WITH A MAXIMUM CONVERSION TIME OF NOT MORE THAN 25 NANOSECONDS , IN THE FORM OF A HYBRID INTEGRATED CIRCUIT WHETHER OR NOT INCORPORATING THREE RANDOM ACCESS MEMORIES ( RAMS ) EACH WITH A STORAGE CAPACITY OF NOT MORE THAN 2 K BITS , CONTAINED IN HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 54 BY 62 MM , WITH NOT MORE THAN 61 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF ONE OF THE FOLLOWING COMBINATIONS OF LETTERS AND FIGURES :  * VDAC 444 TD RGB DAC 4 T RGB DAC 8 E RGB DAC 8 T  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO TRIPLE VDACS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ELECTRONICALLY ADJUSTABLE DIFFERENTIAL AMPLIFIERS FOR AT LEAST THE FULL RANGE OF SIGNALS FROM 0 TO NOT LESS THAN 400 MHZ IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING , WHOSE EXTERNAL DIMENISIONS DO NOT EXCEED 11 BY 11 MM , WITH NOT MORE THAN 16 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR CONTAINING THE FOLLOWING COMBINATION OF FIGURES :  * 0078-10  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO AMPLIFIERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * STATIC , RANDOM-ACCESS MEMORIES OF BIPOLAR TECHNOLOGY ( BIPOLAR SRAMS ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT AND WITH A STORAGE CAPACITY OF 64 BY 9 BITS , CONTAINED IN A HOUSING WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 15 BY 40 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * 82 S 09  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO BIPOLAR SRAMS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * 16 BIT MICROPROCESSOR IN H-MOS TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF A CENTRAL PROCESSING UNIT ( CPU ) , A TIMING GENERATOR , TWO INDEPENDENT DMA CHANNELS , A PROGRAMMABLE INTERRUPT CONTROLLER , THREE PROGRAMMABLE 16 BIT TIMERS , PROGRAMMABLE MEMORY AND EXTERNAL CHIP SELECTION LOGIC , A PROGRAMMABLE WAIT STATE GENERATOR WITH BUS CONTROL UNIT , CONTAINED IN A HOUSING WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 25 BY 25 MM , WITH NOT MORE THAN 68 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * C 80186  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO 16 BIT MICROPROCESSORS COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * 8 BIT ( OCTAL ) DYNAMIC MEMORY BIPOLAR DRIVER IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 16 BY 33 MM , WITH NOT MORE THAN 20 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * AM 2965 AM 2966  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO 8 BIT DYNAMIC MEMORY BIPOLAR DRIVERS COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * BUS INTERFACE CIRCUITS OF BIPOLAR TECHNOLOGY WITH 9 OR 10 BITS REGISTERS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSTING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 9 BY 34 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF NUMBERS AND LETTERS :  * AM 29821 AM 29823 AM 29824 AM 29843 AM 29844  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO BUS INTERFACE CIRCUITS WHICH COMPLY WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * MULTIPLE BUS INTERFACE CIRCUIT ( MULTIPLE BUS BUFFER ) OF LOW POWER SCHOTTKY TECHNOLOGY FOR INTERFACING THE ERROR CORRECTION AND DETECTION UNIT SYSTEM DATA BUS AND DYNAMIC RANDOM ACCESS MEMORY ( D-RAM ) , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 33 MM , WITH NOT MORE THAN 24 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF NUMBERS AND LETTERS :  * AM 2961  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ERROR CORRECTION MULTIPLE BUS BUFFERS WHICH COMPLY WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * STATUS AND SHIFT CONTROL UNIT OF BIPOLAR TECHNOLOGY IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 57 MM WITH NOT MORE THAN 42 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * AM 2904  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO STATUS AND SHIFT CONTROL UNITS COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * AMPLIFIER , IN THE FORM OF A MONOLITHIC INTEGRATED ANALOGUE CIRCUIT WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 3 BY 3 MM FOR USE IN THE MANUFACTURE OF PRODUCTS FALLING WITHIN SUBHEADING 90.19 B I ( A ) * 0  EX 85.21 D II * TEXT-CO-PROCESSOR , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 25 BY 25 MM , WITH NOT MORE THAN 68 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * C 82 730  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO TEXT-CO-PROCESSORS COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * SINGLE-CHIP-MICROCOMPUTER , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF AN ARITHMETIC-LOGIC UNIT WITH A CAPACITY OF 8 BITS PLUS AN ELECTRONIC , PROGRAMMABLE , READ-ONLY MEMORY ( EPROM ) UV ERASABLE WITH A CAPACITY OF 32 K BITS AND A RANDOM ACCESS MEMORY ( RAM ) WITH A CAPACITY OF 1 K BIT , TWO 16 BIT COUNTERS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 15 BY 50 MM , WITH A QUARTZ WINDOW AND NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF THE FOLLOWING COMBINATION OF FIGURES OR INCLUDING THIS COMBINATION :  * 8751  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SINGLE-CHIP-MICROCOMPUTERS WHICH CONFORM TO THE FOREGOING DESCRIPTION * 0  EX 85.21 D II * SUBSCRIBER LINE AUDIO-PROCESSING CIRCUIT ( SLAC ) WITH TWO DIGITAL SIGNAL PROCESSORS , AN ANALOGUE-DIGITAL CONVERTER AND A DIGITAL-ANALOGUE CONVERTER , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * AM 7901 AM 7905  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SLACS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * MONOLITHIC INTEGRATED CIRCUIT IN THE FORM OF PULSE CODE MODULATION ( PCM ) OF N-MOS TECHNOLOGY , WITH ENCODING DECODING AND FILTER FUNCTIONS AND A MAXIMUM DATA CLOCK FREQUENCY OF MORE THAN 3,5 MHZ , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 8 BY 26 MM , WITH NOT MORE THAN 20 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES :  * 2913  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO INTEGRATED CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 8,5  EX 85.21 D II * NON-VOLATILE MEMORY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONSISTING OF C-MOS S-RAM , WITH A CAPACITY OF 16 K BITS AND INTERNAL POWER SUPPLY , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 33 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF THE FOLLOWING COMBINATION :  * MK 48 Z 02 ( B )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO NON-VOLATILE MEMORIES WHICH CONFORM TO THE FOREGOING DESCRIPTION * 0  EX 85.21 D II * SINGLE-CHIP MICROCOMPUTERS IN C-MOS TECHNOLOGY , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF AN ALU WITH A CAPACITY OF 32 BITS PLUS A ROM WITH A CAPACITY OF 24 K BITS AND A RAM WITH A CAPACITY OF 2 K BITS , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS ARE NOT LESS THAN 30 BY 30 MM , WITH A MINIMUM OF 88 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * MB 8764  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SINGLE-CHIP MICROCOMPUTERS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * SUBSCRIBER LINE INTERFACE CIRCUIT ( SLIC ) WITH DIRECT INTERNAL RELAY DRIVE , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 18 BY 39 MM WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR FIGURES AND LETTERS :  * 5502 ICME 00155/RIFA ( PBL ) 3735  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO SLICS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * INPUT OUTPUT CIRCUIT N-MOS TECHNOLOGY FOR DATA CONTROL EQUIPPED WITH A TIMING CONTROL WITH A STATIC RANDOM ACCESS MEMORY ( S-RAM ) WITH A CAPACITY OF 128 BY 8 BITS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 16 BY 54 MM , WITH NOT MORE THAN 40 CONNECTING PINS AND BEARING :  * . AN IDENTIFICATION MARKING EITHER CONSISTING OF ONE OF THE FOLLOWING COMBINATIONS OF FIGURES OR LETTERS AND FIGURES OR INCLUDING ONE OF THOSE COMBINATIONS :  * 6532 CO 10750  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO INPUT OUTPUT CONTROL CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * 4-CHANNEL DRIVE CIRCUIT FOR STEPPING MOTOR , OF BIPOLAR TECHNOLOGY , WITH INCORPORATED DIODES , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 6 BY 20 MM , WITH 16 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * HA 13007 75437 A  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MOTOR DRIVE CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ANALOG/DIGITAL MONOLITHIC INTEGRATED CIRCUIT USED TO CONTROL BRUSHLESS MOTORS , MAINTAINING THEM AT A CONSTANT SPEED , CONTAINED IN A HOUSING WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 6 BY 25 MM , WITH 18 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * MGA 3015 A  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO INTEGRATED CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * ANALOG/DIGITAL MONOLITHIC INTEGRATED CIRCUIT OF BIPOLAR TECHNOLOGY FOR INTERFACE SIGNALS BETWEEN THE PERIPHERAL HARD-DISK MEMORY UNIT AND THE CENTRAL UNIT , CONTAINED IN A HOUSING WHOSE DIMENSIONS DO NOT EXCEED 15 BY 50 MM , WITH NOT MORE THAN 40 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING IN OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * AD 581 C  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO INTEGRATED CIRCUITS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * VOLTAGE-MULTIPLIER CIRCUIT FOR OPERATING STEPPING MOTORS , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 6 BY 24 MM , WITH NOT MORE 20 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * P 20 A579  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO VOLTAGE-MULTIPLIER CIRCUITS COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * MEMORY MANAGEMENT UNIT OF H-MOS TECHNOLOGY ( H-MOS MMU ) WITH A MAXIMUM ADDRESSING CAPACITY OF 16 M BYTES , IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 25 BY 82 MM , WITH NOT MORE THAN 64 CONNECTING PINS OR 68 CONTACT AREAS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * 68451 L 6 68451 L 8 68451 L 10 68451 ZBL 6 68451 ZBL 8 68451 ZBL 10  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO H-MOS MMUS COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.21 D II * ELECTRONIC CIRCUIT OF ADVANCED LOW POWER SCHOTTKY ( ALPS ) TECHNOLOGY FOR THE ASYNCHRONOUS CONTROL OF SIGNAL LINES ( BUS ) AND THE CONVERSION OF A LOCAL BUS INTO A MULTIPLEXED BUS ( BAM ) IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 37 BY 13 MM , WITH NOT MORE THAN 28 CONNECTING PINS AND BEARING THE IDENTIFICATION MARKING :  * 68452  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO ALPS BAMS CONFORMING TO THE FOREGOING DESCRIPTION * 0  EX 85.21 * CATHODE RAY TUBE CONTROLLER ( CRTC ) OF N-MOS TECHNOLOGY IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 62 BY 16 MM WITH NOT MORE THAN 48 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * AM 8052 D 8275 H P 8275 H  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO CRTCS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * DISPLAY CONTROLLER AND CHARACTER GENERATOR ( DCCG ) FOR LIQUID CRYSTAL DOT MATRIX DISPLAY SYSTEM IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT OF C-MOS TECHNOLOGY CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 20 BY 26 MM , WITH NOT MORE THAN 60 CONNECTING PINS , AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * HD 61830  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO C-MOS DISPLAY CONTROLLER AND CHARACTER GENERATORS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTIONS * 0  EX 85.21 D II * VIDEO DIGITAL TO ANALOG CONVERTER ( VDAC ) WITH A MAXIMUM CONVERSION TIME OF 10 NANOSECONDS , IN THE FORM OF A HYBRID INTEGRATED CIRCUIT , CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 20 BY 35 MM , WITH NOT MORE THAN 24 CONNECTING PINS AND BEARING :  * - AN IDENTIFICATION MARKING CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATION OF FIGURES AND LETTERS :  * VDAC 0405 H VDAC 0605 H VDAC 0805 H  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO VDACS COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 0  EX 85.21 D II * MEMORIES IN THE FORM OF A MONOLITHIC INTEGRATED CIRCUIT CONSISTING OF A MULTI-LAYER SUBSTRATE , WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 17 BY 39 MM , ON WHICH ARE MOUNTED A DECODER , A DECOUPLING CAPACITOR TWO RESISTANCES AND ONE UV-ERASABLE , PROGRAMMABLE READ-ONLY MEMORY ( EPROM ) HAVING A STORAGE CAPACITY OF 64 K BITS AND A QUARTZ WINDOW ON THE UPPER SURFACE AND THREE STATIC RANDOM-ACCESS MEMORIES IN C-MOS TECHNOLOGY ( C-MOS S-RAM'S ) EACH HAVING A STORAGE CAPACITY OF 16 K BITS AND A TOTAL CAPACITY OF 48 K BITS WITH NOT MORE THAN 28 CONNECTING PINS . THE ASSEMBLIES BEAR :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF OR INCLUDING ONE OF THE FOLLOWING COMBINATIONS OF FIGURES AND LETTERS :  * EDH 90 806 BS-25 ( 15 ) EDH 90 806 BS-30 ( 20 )  * OR  * - OTHER IDENTIFICATION MARKINGS RELATING TO MEMORIES COMPLYING WITH THE ABOVE DESCRIPTION * 0  EX 85.22 C II * ELECTROMAGNETIC DISPLAYS CONSISTING OF SEVEN ELECTROMAGNETIC COILS , WHICH BY MEANS OF THE RESIDUAL MAGNETISM IN THE STATORS PROVIDE INDEFINITE MEMORY , AND SEVEN PIVOTING LIGHT-REFLECTING SEGMENTS EACH OF WHICH IS ATTACHED TO A BAR MAGNET . THE DISPLAY IS CONTAINED IN A HOUSING WHOSE EXTERIOR DIMENSIONS DO NOT EXCEED 28 BY 36 BY 50 MM * 0  EX 85.22 C II * PORTABLE MACHINES FOR READING AND WRITING BRAILLE WITH TACTILE READ-OUT AND MAGNETIC TAPE CASSETTE RECORDING SYSTEMS , MICROPHONE AND SPEAKER , EQUIPPED WITH A STANDARD ELECTRO-MECHANICAL BRAILLE TYPEWRITER KEYBOARD AND AN ELECTROMECHANICAL BRAILLE READ-OUT UNIT WITH 20 CHARACTERS , ALL CONTAINED IN A CASE WHOSE EXTERIOR DIMENSIONS DO NO EXCEED 24 BY 36 BY 11 CM * 0  EX 90.13 * LIQUID CRYSTAL DEVICES ( LCD ) , WHOSE EXTERNAL DIMENSIONS DO NOT EXCEED 40 BY 154 MM WITH NOT MORE THAN 192 CONTACTS AREAS , CONSISTING OF A LAYER OF LIQUID CRYSTAL BETWEEN TWO GLASS SHEETS OR PLATES WITH A MINIMUM OF 7 AND A MAXIMUM OF 32 FIGURES OR LETTERS , AND BEARING :  * - AN IDENTIFICATION MARKING EITHER CONSISTING OF ONE OF THE FOLLOWING COMBINATION OF FIGURES OR INCLUDING ONE OF THOSE COMBINATIONS :  * FROM 1000000-0001 TO 9999999-9999  * - OR OTHER IDENTIFICATION MARKING RELATING TO LIQUID CRYSTAL DEVICES COMPLYING WITH THE ABOVEMENTIONED DESCRIPTION * 4  EX 90.19 A III * HEART VALVES AND PARTS THEREOF * 0  EX 98.04 A II * NON-FIBROUS PLASTIC PEN-TIPS WITH AN INTERNAL CHANNEL * 0  ( A ) CONTROL OF THE USE FOR THIS SPECIAL PURPOSE SHALL BE CARRIED OUT PURSUANT TO THE RELEVANT COMMUNITY PROVISIONS .