Patent Abstract:
A electronic device is provided. The electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are symmetrically disposed with respect to a first point; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a Divisional Application of U.S. patent application Ser. No. 12/402,589, which was filed on Mar. 12, 2009, which is all incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to an electronic device, and more particularly to a capacitor with a floating metal ring. 
     2. Description of the Related Art 
     Capacitors are essential passive elements in integrated circuits. In integrated circuits, differential signals on two electrodes of a capacitor are easily affected by nearby routed conducting lines.  FIG. 1  shows a capacitor of symmetric metal-oxide-metal (MOM) structure. Electrodes E 10  and E 11  and an oxide layer therebetween form a capacitor CP 1 . If there is a conducting line L 10  near the capacitor CP 1 , parasitic capacitors are formed between the conducting line L 10  and the electrodes E 10  and E 11 .  FIG. 2  shows an equivalent circuit of the MOM structure and the conducting line L 10 . Referring to  FIGS. 1 and 2 , C 10  represents the parasitic capacitor between the conducting line L 10  and the electrode E 10 , and C 11  represents the parasitic capacitor between the conducting line L 10  and the electrode E 11 . Noise on the conducting line L 10  directly affects the differential signals on the electrodes E 10  and E 11 . Moreover, since the electrode E 11  is farther away than the electrode E 10  from the conducting line, the parasitic capacitor C 11  is smaller than the parasitic capacitor C 10 , so that, the differential signals on the electrodes E 10  and E 11  suffer unequal effects from the conducting line L 10 . 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of an electronic device comprises first and second electrodes and a first floating metal ring. The first and second electrodes are formed in a first layer. The first floating metal ring is formed in the first layer and encloses the first electrode and the second electrode. The first electrode and the second electrode are formed in an L-type shape, a ladder-type shape, a finger-type shape, a zipper-type shape, or a hook-type shape. 
     Another exemplary embodiment of an electronic device comprises first and second electrodes and a first floating metal ring. The first and second electrodes are formed in a first layer and are symmetrically disposed with respect to a first point. The first floating metal ring is formed in the first layer and encloses the first electrode and the second electrode. In some embodiments, the floating metal ring is symmetrically disposed with respect to the first point. 
     Another exemplary embodiment of an electronic device comprises first and second electrodes and a first floating metal ring. The first and second electrodes are formed in a first layer and are disposed in rotational symmetry with respect to a first symmetry point. The floating metal ring is formed in a first layer and encloses the first electrode and the second electrode. In some embodiments, the floating metal ring is disposed in rotational symmetry with respect to the first symmetry point. 
     Another exemplary embodiment of an electronic device comprises a first electrode, a second electrode, and a floating plate. The first and second electrodes are formed in a first layer. The floating plate is disposed under the first electrode and the second electrode. In some embodiments, the electronic device further comprises two walls disposed two sides of the electronic device. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a capacitor of symmetric metal-oxide-metal (MOM) structure; 
         FIG. 2  shows an equivalent circuit of the MOM structure and the nearby conducting line of  FIG. 1 ; 
         FIG. 3   a  shows an exemplary embodiment of a capacitor; 
         FIG. 3   b  shows an exemplary embodiment of a capacitor; 
         FIG. 4  shows the capacitor of  FIG. 3   a  and a nearby conducting line; 
         FIG. 5  shows an equivalent circuit of the capacitor and the nearby conducting line of  FIG. 4 ; 
         FIG. 6  shows an equivalent circuit transformed from the equivalent circuit of  FIG. 5  by Y-Δ transformation; 
         FIGS. 7   a  and  7   b  show the electrodes with zipper-type shapes in the capacitor of  FIG. 3   a;    
         FIG. 7   c  shows a woven structure formed by overlapping the electrodes with the zipper-type shapes of  FIGS. 7   a  and  7   b  in two layers; 
         FIGS. 8   a  and  8   b  show the electrodes with hook-type shapes in the capacitor of  FIG. 3   a;    
         FIG. 8   c  shows another woven structure formed by overlapping the electrodes with the hook-type shapes of  FIGS. 8   a  and  8   b  in two layers; 
         FIGS. 9   a  and  9   b  show the electrodes with L-type shapes in the capacitor of  FIG. 3   a;    
         FIG. 9   c  shows a woven structure formed by overlapping the electrodes with the L-type shapes of  FIGS. 9   a  and  9   b  in two layers; 
         FIGS. 10   a  and  10   b  show the electrodes with ladder-type shapes in the capacitor of  FIG. 3   a;    
         FIG. 10   c  shows another woven structure formed by overlapping the electrodes with the ladder-type shapes of  FIGS. 10   a  and  10   b  in two layers; 
         FIG. 11  shows an exemplary embodiment of a capacitor; 
         FIG. 12  shows an exemplary embodiment of the floating plate of the capacitor in  FIG. 11 ; and 
         FIG. 13  shows an exemplary embodiment of a capacitor. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     Capacitors are provided. In an exemplary embodiment of a capacitor in  FIG. 3   a , a capacitor CP 3  comprises electrodes E 30  and E 31 , an insulator (not shown), and a floating metal ring R 30   a . The insulator can be oxide, so that the capacitor CP 3  has a metal-oxide-metal (MOM) structure. In this embodiment, the electrodes E 30  and E 31 , the insulation layer, and the floating metal ring R 30   a  are formed in the same layer. Referring to  FIG. 3   a , each of the electrodes E 30  and E 31  has a finger-type shape, and the electrodes E 30  and E 31  are symmetrically disposed with respect to a point SP 3 . Fingers of the electrodes E 30  and E 31  extend toward the symmetry axis SA 3  and are alternately disposed. The floating metal ring R 30   a  encloses the electrodes E 30  and E 31  and is symmetrically disposed with respect to the point SP 3 . Referring to  FIG. 4 , it is assumed that there is a conducting line L 30  near the capacitor CP 3 . Due to the floating metal ring R 30   a , noise on the conducting line L 30  does not directly affect the differential signals on the electrodes E 30  and E 31 . 
       FIG. 5  shows an equivalent circuit of the capacitor CP 3  and the conducting line L 30 . A parasitic capacitor C 30  is formed between the floating metal ring R 30   a  and the electrode E 30 , and a parasitic capacitor C 31  is formed between the floating metal ring R 30   a  and the electrode E 31 . A parasitic capacitor C 32  is formed between the conducting line L 30  and the capacitor CP 3 . Since the electrodes E 30  and E 31  and the floating metal ring R 30   a  are symmetrically disposed with respect to the point SP 3 , the parasitic capacitors C 30  and C 31  between the floating metal ring R 30   a  and the electrodes E 30  and E 31  have the same capacitance, so that the differential signals on the electrodes E 30  and E 31  suffer equal effects from the conducting line L 30 . 
     In another aspect, the capacitance between the electrodes E 30  and E 31  can be increased due to the disposition of the floating metal ring R 30   a .  FIG. 6  shows an equivalent circuit transformed from the equivalent circuit in  FIG. 5  by Y-Δ transformation. Capacitors C 60 -C 62  in  FIG. 6  are formed according to the capacitors C 30 -C 32  in  FIG. 5 , and shown in following equations: 
     
       
         
           
             
               
                 c 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 60 
               
               = 
               
                 
                   c 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   61 
                 
                 = 
                 
                   
                     
                       c 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       32 
                       × 
                       c 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       30 
                     
                     
                       
                         c 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         32 
                       
                       + 
                       
                         2 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         c 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         30 
                       
                     
                   
                   = 
                   
                     
                       
                         c 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         32 
                       
                       
                         
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             32 
                           
                           
                             c 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             30 
                           
                         
                         + 
                         2 
                       
                     
                     &lt; 
                     
                       
                         c 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         32 
                       
                       2 
                     
                   
                 
               
             
             , 
             
               
 
             
             ⁢ 
             and 
           
         
       
       
         
           
             
               
                 c 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 62 
               
               = 
               
                 
                   
                     c 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       30 
                       2 
                     
                   
                   
                     
                       c 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       32 
                     
                     + 
                     
                       2 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       c 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       30 
                     
                   
                 
                 = 
                 
                   
                     
                       c 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       30 
                     
                     
                       
                         
                           c 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           32 
                         
                         
                           c 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           30 
                         
                       
                       + 
                       2 
                     
                   
                   &lt; 
                   
                     
                       c 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       30 
                     
                     2 
                   
                 
               
             
             , 
           
         
       
     
     wherein, c 30 -c 32  and c 60 -c 62  represent the capacitance of the capacitance capacitors C 30 -C 32  and C 60 -C 62 , respectively. 
     According to above equations, since the capacitor CP 3  and C 62  are coupled in parallel, the capacitance between the electrodes E 30  and E 31  is increased from cp 3  to cp 3 +c 62 , wherein cp 3  represents the capacitance of the capacitor CP 3 . Moreover, the values c 60  and c 61  of the parasitic capacitors C 60  and C 61  between the conducting line L 30  and the electrodes E 30  and E 31  are equal, and each of the values c 60  and c 61  is less than 
                 c   ⁢           ⁢   32     2     ,         
so that the differential signals on the electrodes E 30  and E 31  suffer equal effects from the conducting line L 30 , and the effects on the differential signals are weak.
 
     In the embodiment of  FIG. 3   a , the floating metal ring R 30   a  strictly encloses the electrodes E 30  and E 31 . In some embodiments, a floating metal ring R 30   b  has a breaking  301 , so that the floating metal ring R 30   b  does not strictly enclose the electrodes E 30  and E 31 . Moreover, the floating metal ring R 30   b  is symmetrically disposed with respect to a symmetry axis SA 3 . 
     In the embodiment of  FIG. 3   a , the capacitor CP 3  is formed by a single layer with the electrodes E 30  and E 31 , the insulator, and the floating metal ring R 30   a . In other embodiments, the capacitor CP 3  can be form by a plurality of layers with electrodes. Each of the layers comprises electrodes E 30  and E 31  and the insulator, and at least one layer comprises the floating metal ring R 30   a . Referring to  FIG. 3   a , the electrodes E 30  and E 31  with the finger-type shape are symmetrically disposed with respect to the point SP 3 . However, the shapes of the electrodes E 30  and E 31  are not limited to the finger-type shape. The electrodes E 30  and E 31  can have any shape to be symmetrically disposed with respect to the point SP 3 . 
     In some embodiments, the electrodes E 30  and E 31  can be disposed in rotational symmetry with respect to a symmetry point. For example, the electrodes E 30  and E 31  of the capacitor CP 3  can have zipper-type shapes as shown in  FIGS. 7   a  and  7   b  or hook-type shapes as shown in  FIGS. 8   a  and  8   b . The electrodes E 30  and E 31  with the zipper-type shapes in  FIGS. 7   a  and  7   b  are respectively disposed in rotational symmetry with respect to symmetry points SP 7   a  and SP 7   b . The electrodes E 30  and E 31  with the hook-type shapes in  FIGS. 8   a  and  8   b  are respectively disposed in rotational symmetry with respect to symmetry points SP 8   a  and SP 8   b . If the capacitor CP 3  is formed by electrodes in a plurality of layers, each of the layers comprises electrodes E 30  and E 31  with the zipper-type shape or the hook-type shape and the insulator, and at least one layer comprises the floating metal ring R 30   a . In following, it is assumed that the capacitor CP 3  is formed by electrodes in two layers. When the electrodes E 30  and E 31  of one layer have the zipper-type shape as in  FIG. 7   a  and those of the other layer have the zipper-type shape as in  FIG. 7   b , the capacitor CP 3  is formed in a woven structure by overlapping the two layers, as shown in  FIG. 7   c . Similarly, when the electrodes E 30  and E 31  of one layer have the hook-type shape as in  FIG. 8   a  and those of the other layer have the hook-type shape as in  FIG. 8   b , the capacitor CP 3  is formed in a woven structure, as shown in  FIG. 8   c , by overlapping the two layers. Moreover, according to symmetric geometry, the electrodes E 30  and E 31  with the figure-type shape and the floating metal ring R 30   a  as in  FIG. 3   a  are also disposed in rotational symmetry with respect to a symmetry point SP 3 . In  FIGS. 7   c  and  8   c , two layers of a capacitor are coupled together through vias represented by dark blocks. 
     According to above description, electrodes in one layer of a capacitor are disposed in rotational symmetry with respect to a symmetry point, and a floating metal ring in the same layer encloses the electrodes. Noise on a nearby conducting line does not directly affect differential signals on the electrodes. The differential signals suffer equal effects from the conducting line, and the effects on the differential signals are weak. 
     In other some embodiments, the electrodes E 30  and E 31  can be disposed in asymmetry. For example, the electrodes E 30  and E 31  of the capacitor CP 3  can have L-type shapes as shown in  FIGS. 9   a  and  9   b  or ladder-type shapes as shown in  FIGS. 10   a  and  10   b.    
     If the capacitor CP 3  is formed by electrodes in a plurality of layers, each of the two layers comprises electrodes E 30  and E 31  with the L-type shape or the ladder-type shape and the insulator, and at least one layer comprises the floating metal ring R 30   a . In following, it is assumed that the capacitor CP 3  is formed by electrodes in two layers. When the electrodes E 30  and E 31  of one layer have the L-type shape as in  FIG. 9   a  and those of the other layer have the L-type shape as in  FIG. 9   b , the capacitor CP 3  is formed in a woven structure by overlapping the two layers, as shown in  FIG. 9   c . Similarly, when the electrodes E 30  and E 31  of one layer have the ladder-type shape as in  FIG. 10   a  and those of the other layer have the ladder-type shape as in  FIG. 10   b , the capacitor CP 3  is formed in a woven structure, as shown in  FIG. 10   c , by overlapping the two layers. In  FIGS. 9   c  and  10   c , two layers of a capacitor are coupled together through vias represented by solid blocks. 
     According to the above description, a capacitor comprises two electrodes disposed in asymmetry and two connected floating metal rings, each enclosing the electrode in the same layer, so that noise on a nearby conducting line does not directly affect differential signals on the electrodes. 
     In another embodiment of a capacitor in  FIG. 11 , a capacitor CP 11  comprises electrodes E 110  and E 111 , an insulator (not shown), and a floating plate  110 . The electrodes E 110  and E 111  can have a symmetric shape, such as the sharps of  FIGS. 3   a ,  7   a ,  7   b ,  8   a , and  8   b . The floating plate  110  is disposed under the electrodes E 110  and E 111 . A parasitic capacitor is formed between the floating plate  110  and the electrode E 110 , and another parasitic capacitor is formed between the floating plate  110  and the electrode E 111 . Since the electrodes E 110  and E 111  have the symmetric shape, these parasitic capacitors between the floating plate  110  and the electrodes E 110  and E 111  have the same capacitance, so that the differential signals on the electrodes E 110  and E 111  suffer equal effects from the conducting line L 110 . Thus, the floating plate  110  can shield against imbalance capacitance effect between the line L 110  and the electrodes E 110  and E 111 . 
     In the embodiment of  FIG. 11 , the surface of the floating plate  110  is smooth. In some embodiments, the floating plate  110  can have trenches or slices or other kinds of holds. The floating plate  110  with trenches in  FIG. 12  is given as an example. 
     Moreover, the capacitor CP 11  of  FIG. 11  may further comprise walls. As shown in  FIG. 13 , the capacitor CP 11  further comprises walls W 30  and W 31  which are disposed two sides of the capacitor CP 11 . In this embodiment, the walls W 30  and W 31  are disposed the two opposite sides of the capacitor CP 11 . One wall W 30  is formed by an upper conductive line  130  and lower conductive lines  132 , and the upper conductive line  130  is connected with the lower conductive lines  132 . There are holds formed between the lower conductive lines  132  the upper conductive line  130 , and the corresponding side of the capacitor CP 11 . The other wall W 31  is formed by an upper conductive line  132  and lower conductive lines  133 , and the upper conductive line  132  is connected with lower the conductive lines  133 . There are holds formed between the lower conductive lines  133 , the upper conductive line  132 , and the corresponding side of the capacitor CP 11 . The walls W 30  and W 31  and the floating plate  110  can shield against imbalance capacitance effect between the line L 130  and the electrodes E 110  and E 111 . 
     The floating metal rings, the floating plate, and the walls which are provided to shield against imbalance capacitance are not limited to a capacitor element. In some embodiments, the floating metal rings, the floating plate, and the walls can be used to shield against imbalance capacitance occurred in a resistor element or any other circuit, such as an amplifier circuit. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 7