Patent Abstract:
A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode, depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer, and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.

Full Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to ferroelectric non-volatile integrated circuits, and specifically to a simplified fabrication technique which minimizes etching-induced ferroelectric stack damage.  
         BACKGROUND OF THE INVENTION  
         [0002]    A gate stack of a state-of-the-art ferroelectric (FE) memory transistor includes formation of a self-aligned FE stack, which includes deposition and etching of a top electrode material, the ferroelectric material, and a bottom electrode material. There are some serious problems associated with state-of-the-art techniques, which result in a less than desirable yield, such as re-deposition of etched and masking material on the structure, usually as a result of etching the top electrode material, the FE material and the bottom electrode material to form the FE self-aligned stack. Additionally, plasma etching of the FE material may damage the non-volatile properties of the material, which property cannot be restored completely.  
         SUMMARY OF THE INVENTION  
         [0003]    A method of fabricating a non-volatile ferroelectric memory transistor includes preparing a silicon substrate, including forming an active region on the substrate, implanting ions to form a source region and a drain region in the active region; forming a bottom electrode, depositing a ferroelectric layer over the active region; depositing a top electrode; depositing an insulating oxide layer over the active region; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode.  
           [0004]    A non-volatile ferroelectric memory transistor includes a silicon substrate having an active region formed thereon; a source region and a drain region formed about a gate region in the active region; a bottom electrode formed above the gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; a top electrode formed on the ferroelectric layer, an insulating oxide layer, and a source electrode, a gate electrode and a drain electrode.  
           [0005]    An object of the invention is to fabricate a ferroelectric non-volatile memory transistor which does not require gate stack etching  
           [0006]    A further object of the invention is to fabricate a ferroelectric non-volatile memory transistor with minimal etching-induced damage.  
           [0007]    Another object of the invention is to provide a fabrication process for a ferroelectric non-volatile memory transistor which is less complex than prior art techniques  
           [0008]    This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    FIGS.  1 - 4  depict steps in the fabrication process of the invention for a MFMOS FE non-volatile memory transistor.  
         [0010]    [0010]FIG. 5 depicts a MFMOS FE non-volatile memory transistor constructed according to the invention  
         [0011]    [0011]FIG. 6 depicts a MFMS FE non-volatile memory transistor constructed according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0012]    The ferroelectric memory transistor of the invention may be formed on a silicon-on-insulator (SOI) substrate, such as Separation by IMplantation of Oxygen (SIMOX), or, it may be formed in a bulk silicon substrate. The description herein will concentrate on the formation of the structure on a bulk silicon substrate, however, as used herein, “silicon substrate” refers to either a SOI substrate or to a bulk silicon substrate  
         [0013]    The method of the invention overcomes the problems associated with etchings to form a self-aligned ferroelectric (FE) gate stack, and to also overcome the problems associated with etching-induced damage. The fabrication method of the invention for a FE non-volatile memory transistor does not require etching of the FE material of the gate stack. Further, the top electrode and the bottom electrode do not need to be self-aligned.  
         [0014]    Referring initially to FIG. 1, the process sequence begins with a substrate  10 . As previously noted, this may be a bulk or SOI substrate State-of-the-art processes are followed for device isolation, with shallow trench isolation (STI) being is used as the preferred technique for device isolation, resulting in the formation of oxide areas  11  Implantation of Boron ions, at a dose of about 1·10 12  cm −2  to 5·10 13  cm −2 , and at an energy level of 30 keV to 60 keV results in the formation of p-well  12 , forming an active region on substrate  10 . A gate region is oxidized, resulting in a gate oxide  14 , when fabricating a metal-ferro-metal oxide semiconductor (MFMOS) transistor. As will be explained later herein, a surface channel is formed when fabricating a metal-ferro-metal semiconductor (MFMS) transistor. A bottom electrode  16  is deposited by CVD. Bottom electrode  16  is preferably formed of Iridium, deposited to a thickness of between about 100 nm and 200 nm. A layer of photoresist is applied to the desired areas, and bottom electrode  16  is etched, leaving sufficient bottom electrode material to corer a gate region. Bottom electrode  16  has a predetermine area located within a peripheral boundary.  
         [0015]    Arsenic ions are implanted at a dose of about 1·10 15  cm −2  to 3·10 15  cm −2 , and at an energy level of 20 keV to 40 keV, to form a source region  18  and a drain region  20 , which are located about a gate region, resulting in the structure depicted in FIG. 1.  
         [0016]    An oxide layer  22  is formed by chemical vapor deposition (CVD) to a thickness of between about 200 nm and 400 nm, which is thicker than that of bottom electrode  16  Oxide layer  22  is thinned by chemical-mechanical polishing (CMP) to the upper surface of bottom electrode  16 , exposing the bottom electrode, as shown in FIG. 2.  
         [0017]    Referring to FIG. 3, a FE layer  24  is formed by CVD to a thickness of between about 100 nm and 400 nm. The FE material may be any of the following: Pb(Zr, Ti)O 3  (PZT), SrBi 2 Ta 2 O 9  (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 , or LiNbO 3 . A top electrode  26 , preferably formed of Platinum, is deposited by CVD to a thickness of between about 100 nm and 300 nm Photoresist is applied to specific regions of the structure, and the top electrode is etched, resulting in the structure shown in FIG. 3 Using the method of the invention, the selectivity of etching of top electrode  26  vs. FE layer  24  is not critical.  
         [0018]    Turning to FIG. 4, a barrier insulation layer  28  is deposited by CVD A material such as TiO 2  is suitable for this layer, if required, and may be deposited to a thickness of between about 10 nm and 30 Barrier insulation layer  28  is provided to stop the diffusion of H 2  into the FE layer during annealing. An oxide layer  30  is next deposited by CVD. Photoresist is applied prior to etching of contact holes in the insulating oxide. The structure is then metallized, and then etched, forming source electrode  32 , gate electrode  34 , and drain electrode  36 , resulting in the final MFMOS memory transistor structure shown at 38 in FIG. 5.  
         [0019]    Referring to FIG. 6, similar fabrication processes may be applied to formation of a MFMS non-volatile transistors, shown generally at  40  In this instance, however, a surface channel n-layer  42  is formed in place of gate oxide layer  14  in FIGS.  1 - 5 . Surface channel  42  is formed by implantation of Arsenic ions, at a dose of about 1·10 11  cm −2  to 5·10 12  cm −2 , and at an energy level of about 15 keV to 30 keV, resulting in a n-layer between p-well  12  and bottom electrode  16 .  
         [0020]    As depicted in the drawings, top electrode  26  and bottom electrode  16  are not self-aligned. When the electrodes are partially overlapped, as in the embodiments of the invention, the effective remnant charge is reduced by A OVERLAP /A BOT , where A OVERLAP  is the area of overlap between top electrode  26  and bottom electrode  16 , and A BOT  is the area of bottom electrode  16   
         [0021]    When the top electrode is larger than the bottom electrode, the bottom electrode is generally completely covered by the top electrode, and the effective remnant charge is the same as that of a self-aligned gate stack of the same size electrodes The top electrode may also cover portions of source region  18  and/or drain region  20 , and the charge on the FE material will induce a charge on the source/drain junction. This induced charge makes the source region and/or drain region more conductive when the memory cell is programmed to a high conductive state and less conductive when the memory cell is programmed to a low conductive state Thus, this form of overlap does not produce any undesirable effects.  
         [0022]    While contact etching has to extend through FE layer  24 , the contact via is located a short distance laterally away from bottom electrode  16 , and, because the etched area is relatively small, any plasma etching damage is minimal The method of the invention eliminates the need to etch the FE layer for a self-aligning process The only etching which occurs to the FE layers if the formation of via holes, which is quite minimal, and not likely to result in any loss of non-volatile properties in the FE layer.  
         [0023]    Thus, a method and structure for a MFMOS/MFMS non-volatile memory transistor having a simplified and less damaging etching process has been disclosed It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.

Technology Classification (CPC): 7