Patent Abstract:
A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material.

Full Description:
FIELD OF THE INVENTION 
   The present invention relates generally to electronic fuses (efuses) and more particularly to diffusion barrier layers serving as efuses. 
   BACKGROUND OF THE INVENTION 
   In a conventional semiconductor integrated circuit (chip), there are efuses that can be programmed so as to determine the mode of operation of the chip. Therefore, there is a need for an efuse structure (and a method for forming the same) that is better than the efuses of the prior art. 
   SUMMARY OF THE INVENTION 
   The present invention provides an electrical fuse fabrication method, comprising forming a first electrode in a substrate; forming a dielectric layer on top of said first electrode; forming an opening in said dielectric layer such that said first electrode is exposed to a surrounding ambient through said opening; forming a fuse element on side walls and bottom walls of said opening such that said first electrode and said fuse element are electrically coupled together; and filling said opening with a dielectric material. 
   The present invention provides an efuse structure that is better than the efuses of the prior art. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-1M  show cross-section views used to illustrate a fabrication process for forming a semiconductor structure, in accordance with embodiments of the present invention. 
       FIGS. 2A-2C  show cross-section views used to illustrate a fabrication process for forming another semiconductor structure, in accordance with embodiments of the present invention. 
       FIGS. 3A-3H  show cross-section views used to illustrate a fabrication process for forming an alternative semiconductor structure, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-1M  show cross-section views used to illustrate a fabrication process for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process for forming the semiconductor structure  100  starts with a dielectric layer  110  on top of a front-end-of-line layer (not shown). The front-end-of-line (FEOL) layer contains semiconductor devices such as transistors, resistors, capacitors, etc. (not shown). The dielectric layer  110  comprises a dielectric material such as SiCOH or SiLK on top of the FEOL layer. The dielectric layer  110  can be referred to as an inter-level dielectric layer  110  of a back-end-of-line layer (not shown). Both the dielectric layer  110  and the front-end-of-line layer can comprise oxide, diamond, glass, ceramic, quartz, or polymer. 
   Next, with reference to  FIG. 1B , in one embodiment, trenches  111   a  and  111   b  are formed in the dielectric layer  110 . The trenches  111   a  and  111   b  can be formed by lithographic and etching processes. The trench  111   a  is later used for forming a M1 metal line (not shown), whereas the trench  111   b  is later used for forming a first electrode of an efuse structure (not shown). 
   Next, with reference to  FIG. 1C , in one embodiment, a diffusion barrier layer  112  is formed on top of the dielectric layer  110  (including on the bottom walls and the side walls of the trenches  111   a  and  111   b ). The diffusion barrier layer  112  comprises a diffusion barrier material such as Ta, Ti, Ru, RuTa, TaN, TiN, RuN, RuTaN, a noble metal, or a nitride material of the noble metal. The diffusion barrier layer  112  can be formed by CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or ALD (Atomic Layer Deposition). 
   Next, in one embodiment, an electrically conductive layer  114  is formed on top of the diffusion barrier layer  112  resulting in the trenches  111   a  and  111   b  being filled. The electrically conductive layer  114  comprises an electrically conductive material such as Cu or Al. The electrically conductive layer  114  can be formed by an electroplating process. 
   Next, in one embodiment, portions of the electrically conductive layer  114  outside the trenches  111   a  and  111   b  are removed. More specifically, these portions of the electrically conductive layer  114  can be removed by a CMP (Chemical Mechanical Polishing) process performed on the top surface  114 ′ of the electrically conductive layer  114  until the top surface  110 ′ the dielectric layer  110  is exposed to the surrounding ambient resulting in the semiconductor structure  100  of FIG.  1 C′. The portions of the diffusion barrier layer  112  in the trenches  111   a  and  111   b  can be referred to as diffusion barrier regions  112   a  and  112   b , respectively, as shown in FIG.  1 C′. Similarly, the portions of the electrically conductive layer  114  in the trenches  111   a  and  111   b  can be referred to as a M1 metal line  114   a  and a first electrode  114   b  of the efuse structure, respectively, as shown in FIG.  1 C′. 
   Next, with reference to  FIG. 1D , in one embodiment, an electrically insulating cap layer  120  is formed on top of the semiconductor structure  100  of FIG.  1 C′. The electrically insulating cap layer  120  can be formed by CVD of a dielectric material such as Si 3 N 4 , SiC, SiC(N,H) or SiO 2  on top of the semiconductor structure  100  of FIG.  1 C′. 
   Next, in one embodiment, a dielectric layer  130  is formed on top of the electrically insulating cap layer  120 . The dielectric layer  130  comprises a dielectric material such as SiCOH or SiLK. The thickness of the dielectric layer  130  is in the range from 500 angstroms to 10,000 angstroms. The dielectric layer  130  can be formed by CVD or spin-on process. 
   Next, with reference to  FIG. 1E , in one embodiment, via holes  131   a  and  131   b  and trenches  133   a  and  133   b  are formed in the dielectric layer  130  and the electrically insulating cap layer  120 . More specifically, the via holes  131   a  and  131   b  and trenches  133   a  and  133   b  can be formed by a conventional dual damascene process. The via hole  131   a  and the trench  133   a  are later used for forming a via and a M2 metal line (not shown), respectively, whereas the via hole  131   b  and the trench  133   b  are later used for forming an efuse (not shown) of the efuse structure. 
   Next, with reference to  FIG. 1F , in one embodiment, a diffusion barrier layer  132  is formed on exposed surfaces of the semiconductor structure  100  of  FIG. 1E . The diffusion barrier layer  132  can be formed by CVD, PVD, or ALD of a diffusion barrier material such as Ta, Ti, Ru, RuTa, TaN, TiN, RuN, or RuTaN on exposed surfaces of the semiconductor structure  100  of  FIG. 1E . 
   Next, with reference to  FIG. 1G , in one embodiment, electrically conductive regions  134   a  and  134   b  are formed in the via holes  131   a  and  131   b  and the trenches  133   a  and  133   b . More specifically, the electrically conductive regions  134   a  and  134   b  can be formed by (i) depositing an electrically conductive material such as Cu or Al on top of the semiconductor structure  100  of  FIG. 1F  including inside the via holes  131   a  and  131   b  and the trenches  133   a  and  133   b  and then (ii) removing the excessive electrically conductive material and portions of the diffusion barrier layer  132  outside the via holes  131   a  and  131   b  and the trenches  133   a  and  133   b  resulting in the semiconductor structure  100  of  FIG. 1G . The step (i) can be an electroplating process, whereas the step (ii) can be a CMP process. 
   With reference to  FIG. 1G , it should be noted that the diffusion barrier regions  132   a  and  132   b  are what remain of the diffusion barrier layer  132  ( FIG. 1F ). The diffusion barrier regions  132   b  will serve as an efuse  132   b  (also called the fuse element  132   b ) of the subsequently formed efuse structure. 
   Next, with reference to  FIG. 1H , in one embodiment, an electrically insulating cap region  140  is formed on top of the electrically conductive region  134   a  and the diffusion barrier region  132   a  of the semiconductor structure  100  of  FIG. 1G  such that the electrically conductive region  134   b  remains exposed to the surrounding ambient. The electrically insulating cap region  140  can be formed by CVD of a dielectric material such as Si 3 N 4 , SiC, SiC(N,H) or SiO 2  on top of the semiconductor structure  100  of  FIG. 1G  followed by lithographic and etching processes. 
   Next, in one embodiment, the electrically conductive region  134   b  is removed resulting in the semiconductor structure  100  of  FIG. 1I . More specifically, the electrically conductive region  134   b  can be removed by using wet etching. 
   Next, with reference to  FIG. 1J , in one embodiment, a dielectric layer  150  is formed on top of the semiconductor structure  100  of  FIG. 1I . The dielectric layer  150  comprises a dielectric material such as SiCOH or SiLK. The dielectric layer  150  can be formed by (i) spin-on or (ii) CVD followed by a CMP process. 
   Next, with reference to  FIG. 1K , in one embodiment, via holes  151   a  and  151   b  are formed in the dielectric layer  150 . The via holes  151   a  and  151   b  can be formed by lithographic and etching processes. Next, the via hole  151   a  is extended down through the electrically insulating cap region  140  by using RIE (Reactive Ion Etching) resulting in a via hole  151   a ′ of  FIG. 1L . 
   Next, with reference to  FIG. 1M , in one embodiment, diffusion barrier regions  152   a  and  152   b  are formed on the side walls and bottom walls of the via holes  151   a ′ and  151   b . The diffusion barrier regions  152   a  and  152   b  comprise a diffusion barrier material such as Ta, Ti, Ru, RuTa, TaN, TiN, RuN, RuTaN, a noble metal, or a nitride material of the noble metal. The formation of the diffusion barrier regions  152   a  and  152   b  is similar to the formation of the diffusion barrier region  112   a  and  112   b.    
   Next, in one embodiment, electrically conductive regions  154   a  and  154   b  are formed in the via holes  151   a ′ and  151   b , respectively. The electrically conductive regions  154   a  and  154   b  comprise an electrically conductive material such as Cu or Al. The formation of the electrically conductive regions  154   a  and  154   b  is similar to the formation of the electrically conductive regions  114   a  and  114   b  described earlier. The electrically conductive region  154   b  will serve as a second electrode  154   b  of the efuse structure. It should be noted that the first electrode  114   b , the efuse  132   b , and the second electrode  154   b  constitute an efuse structure  114   b + 132   b + 154   b.    
   In one embodiment, the efuse structure  114   b + 132   b + 154   b  can be programmed by blowing off the efuse  132   b  such that the first electrode  114   b  and the second electrode  154   b  are electrically disconnected from each other. More specifically, the efuse  132   b  can be blown off by sending a sufficiently large current through the efuse  132   b.    
     FIGS. 2A-2C  show cross-section views used to illustrate a fabrication process for forming a semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, the fabrication process for forming the semiconductor structure  200  starts with the semiconductor structure  200  of  FIG. 2A , wherein the semiconductor structure  200  of  FIG. 2A  is similar to the semiconductor structure  100  of  FIG. 1H . The formation of the semiconductor structure  200  of  FIG. 2A  is similar to the formation of the semiconductor structure  100  of  FIG. 1H . 
   Next, in one embodiment, a top portion  134   b ′ of the electrically conductive region  134   b  is removed resulting in an electrically conductive region  234   b  being left in the via hole  131   b  as shown in FIG.  2 A′. The electrically conductive region  134   b  can be removed by wet etching. In one embodiment, the removal of the top portion  134   b ′ is controlled such that a resistance of the resulting combination of the diffusion barrier regions  132   b  and the electrically conductive region  234   b  is equal to a pre-specified value. 
   Next, with reference to  FIG. 2B , in one embodiment, a dielectric layer  250  is formed on top of the semiconductor structure  200  of FIG.  2 A′. The dielectric layer  250  comprises a dielectric material such as SiCOH or SiLK. The dielectric layer  250  can be formed by (i) spin-on or (ii) CVD followed by a CMP process. 
   Next, with reference to  FIG. 2C , in one embodiment, diffusion barrier regions  252   a  and  252   b  and electrically conductive regions  254   a  and  254   b  are formed in the dielectric layer  250  in a manner which is similar to the manner in which the diffusion barrier regions  152   a  and  152   b  and the electrically conductive regions  154   a  and  154   b  are formed in  FIG. 1M . The electrically conductive region  254   b  will serve as a second electrode  254   b  of an efuse structure of the semiconductor structure  200  of  FIG. 2C . It should be noted that the first electrode  114   b , the efuse  132   b , the electrically conductive region  234   b , and the second electrode  254   b  are parts of an efuse structure  114   b + 132   b + 234   b + 254   b.    
   In one embodiment, the efuse structure  114   b + 132   b + 234   b + 254   b  can be programmed in a manner which is similar to the manner in which the efuse structure  114   b + 132   b + 154   b  of semiconductor structure  100  of  FIG. 1M  is programmed. It should be noted that the efuse structure  114   b + 132   b + 234   b + 254   b  can be used as a resistor. 
     FIGS. 3A-3H  show cross-section views used to illustrate a fabrication process for forming a semiconductor structure  300 , in accordance with embodiments of the present invention. More specifically, the fabrication process for forming the semiconductor structure  300  starts with the semiconductor structure  300  of  FIG. 3A , wherein the semiconductor structure  300  of  FIG. 3A  is similar to the semiconductor structure  100  of  FIG. 1F . The formation of the semiconductor structure  300  of  FIG. 3A  is similar to the formation of the semiconductor structure  300  of  FIG. 1F . 
   Next, with reference to FIG.  3 A′, in one embodiment, a dielectric layer  334  is formed on top of the diffusion barrier layer  132  resulting in the via holes  131   a  and  131   b  and the trenches  133   a  and  133   b  being filled. The dielectric layer  334  comprises a dielectric material such as SiLK or SiCOH. The dielectric layer  334  can be formed by CVD or spin-on process. 
   Next, with reference to  FIG. 3B , in one embodiment, an electrically insulating cap region  340  is formed on top of the dielectric layer  334  such that (i) the electrically insulating cap region  340  does not overlap the via hole  131   a  and the trench  133   a  and (ii) the via hole  131   b  and the trench  133   b  are directly beneath the electrically insulating cap region  340 . The electrically insulating cap region  340  can be formed by CVD or spin-on process of a dielectric material such as Si 3 N 4 , SiC, SiC(N,H) or SiO 2  on top of the semiconductor structure  300  of FIG.  3 A′ followed by lithographic and etching processes. 
   Next, in one embodiment, the electrically insulating cap region  340  is used as a blocking mask to etch down the dielectric layer  334  until portions of the dielectric layer  334  inside the via hole  131   a  and the trench  133   a  are completely removed resulting in the semiconductor structure  300  of  FIG. 3C . The step of etching down the dielectric layer  334  can be performed by using RIE. 
   Next, with reference to  FIG. 3D , in one embodiment, a diffusion barrier layer  350  is formed on exposed surfaces of the semiconductor structure  300  of  FIG. 3C . The diffusion barrier layer  350  can be formed by CVD, PVD, or ALD of a diffusion barrier material such as TaN or TiN on exposed surfaces of the semiconductor structure  300  of  FIG. 3C . 
   Next, with reference to  FIG. 3E , in one embodiment, an electrically conductive layer  360  is formed on top of the semiconductor structure  300  of  FIG. 3D  resulting in the via hole  131   a  and the trench  133   a  are filled. The electrically conductive layer  360  comprises an electrically conductive material such as Cu or Al. The electrically conductive layer  360  can be formed by an electroplating process. 
   Next, in one embodiment, (i) portions of the electrically conductive layer  360  and the diffusion barrier layer  350  outside the via hole  131   a  and trench  133   a , (ii) portions of the dielectric layer  334  outside the via hole  131   b  and the trench  133   b , and (iii) the electrically insulating cap region  340  are removed resulting in the semiconductor structure  300  of  FIG. 3F . These removals can be performed by a CMP process. 
   Next, with reference to  FIG. 3G , in one embodiment, an electrically insulating cap layer  370  is formed on top of the semiconductor structure  300  of  FIG. 3F . The electrically insulating cap layer  370  comprises a dielectric material such as Si 3 N 4 , SiC, SiC(N,H) or SiO 2 . The electrically insulating cap layer  370  can be formed by CVD or spin-on process. 
   Next, in one embodiment, a dielectric layer  380  is formed on top of the electrically insulating cap layer  370 . The dielectric layer  380  comprises a dielectric material such as SiCOH or SiLK. The dielectric layer  380  can be formed by CVD or spin-on process. 
   Next, with reference to  FIG. 3H , in one embodiment, diffusion barrier regions  382   a  and  382   b  and the electrically conductive regions  384   a  and  384   b  are formed in the dielectric layer  380  in a manner which is similar to the manner in which the diffusion barrier regions  152   a  and  152   b  and electrically conductive regions  154   a  and  154   b  are formed in  FIG. 1M . The electrically conductive region  384   b  will serve as a second electrode  384   b  of an efuse structure of the semiconductor structure  300  of  FIG. 3H . It should be noted that the first electrode  114   b , the efuse  132   b , and the second electrode  384   b  constitute an efuse structure  114   b + 132   b + 384   b.    
   In one embodiment, the structure of the semiconductor structure  300  of  FIG. 3H  is similar to the structure of the semiconductor structure  100  of  FIG. 1M  except that the semiconductor structure  300  comprises the diffusion barrier region  350   a . The diffusion barrier regions  132   a  and  350   a  can be collectively referred to as a diffusion barrier region  132   a + 350   a . The thickness of the diffusion barrier region  132   a + 350   a  can be customized to a desired thickness by adjusting the thickness of the diffusion barrier region  350   a . As a result, in comparison with the diffusion barrier region  132   b  of  FIG. 1M , the diffusion barrier region  132   a + 350   a  of  FIG. 3H  improves the prevention of diffusion of the electrically conductive material of the electrically conductive region  360   a  through the diffusion barrier region  132   a + 350   a . In one embodiment, the efuse structure  114   b + 132   b + 384   b  can be programmed in a manner which is similar to the manner in which the efuse structure  114   b + 132   b + 154   b  of semiconductor structure  100  of  FIG. 1M  is programmed. 
   In summary, with reference to  FIG. 1M , the diffusion barrier regions  132   a  and  132   b  (i) are similar and (ii) can be formed simultaneously, wherein the diffusion barrier region  132   b  can be used as an efuse of the efuse structure  114   b + 132   b + 154   b . In  FIG. 2C , the electrically conductive region  234   b  is left in the via hole  131   b  so as to decrease the resistance of the efuse. As a result, the resistance of the efuse can be tuned to a desired value. Therefore, the efuse structure  114   b + 132   b + 234   b + 254   b  can also be used as a resistor having a desired resistance. In  FIG. 3H , the electrically conductive region  360   a  is surrounded by the diffusion barrier region  132   a + 350   a  whose thickness can be at any desirable value. 
   In the embodiments described above, the dielectric layer  110  is the first inter-level dielectric layer. In an alternative embodiment, the dielectric layer  110  can be second, third, or any inter-level dielectric layer of the back-end-of-line layer. 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Classification (CPC): 7