Patent Abstract:
A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

Full Description:
FIELD OF THE INVENTION 
     The present disclosure relates, in general to memory devices, and more particularly, to a nonvolatile memory device and method of making the same. 
     RELATED ART 
     It has been shown that non-volatile memory single-transistor bitcells having a dielectric with embedded silicon nanocrystals can be charged with electrons using hot carrier injection (HCI injection), HCI injection with reverse well/source bias, or Fowler-Nordheim (FN) tunneling. The nanocrystals can be discharged with Fowler-Nordheim tunneling through either a top or a bottom dielectric with respect to the nanocrystals. The array architecture considerations of either FN tunneling program/erase or HCI program/FN erase for single-transistor bitcells are also understood. While vertical FN programming is a very low current operation, it results in a long programming time (e.g., on the order of 1-10 msec) and an inefficient bitcell with either two transistors per bitcell or two parallel conductors in a bitline direction. HCI programming results in an efficient bitcell and fast programming (e.g., on the order of 1-10 μsec) at the expense of high programming current (e.g., on the order of 100-200 μA). 
     It also has been shown that source-side injection in a split-gate bitcell in combination with an oxide-nitride-oxide (ONO) storage layer can be used with either hot hole erase or with erase through the thin top oxide of a SONOS device. However, hot hole erase results in oxide degradation leading to read disturb, and thin top oxide erase of an ONO layer results in susceptibility to read disturb for erase times on the order of between 100 msec to 1 sec. 
     Accordingly, a bitcell combining high reliability program/erase operations and low write power is needed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which: 
     FIG. 1 is a cross-sectional view of a nonvolatile memory device having a split gate with nanoclusters embedded within a dielectric layer for charge storage according to one embodiment of the present disclosure; 
     FIG. 2 is a cross-sectional view of a nonvolatile memory device having a split gate with nanoclusters embedded within a dielectric layer and disposed under polysilicon spacers according to another embodiment of the present disclosure; 
     FIG. 3 is a schematic diagram of a nonvolatile memory device according to another embodiment of the present disclosure; and 
     FIG. 4 is a cross-sectional view of a nonvolatile memory device including a shallow implant according to another embodiment of the present disclosure. 
    
    
     Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present disclosure. 
     DETAILED DESCRIPTION 
     FIG. 1 is a cross-sectional view of a nonvolatile memory device  10  having a split gate with nanoclusters embedded within a dielectric layer for charge storage according to one embodiment of the present disclosure. Memory device  10  includes a substrate having a bitcell well  12  of a first conductivity type overlying a deep well  14  of a second conductivity type, opposite the first conductivity type. In one embodiment, the first conductivity type includes p-type and the second conductivity type includes n-type dopant. 
     Memory device  10  also includes a select gate transistor  15 , the select gate transistor including gate dielectric  16  and gate electrode  18 . Memory device  10  further includes a control gate transistor  21 , the control gate transistor including at least a first dielectric  22 , a layer of nanoclusters  24 , a second dielectric  26 , and a gate electrode  28 . In one embodiment, the structure of first dielectric  22 , layer of nanoclusters  24 , and second dielectric  26  form a charge storage structure, the nanoclusters being used for charge storage. In addition, the first dielectric  22  includes a top oxide/nanocluster surface and forms an F/N tunneling dielectric. The second dielectric  26  includes a bottom oxide/nanocluster surface and forms the bottom dielectric. In one embodiment, the nanoclusters comprise silicon nanocrystals. 
     The select gate transistor  15  is separated from the control gate transistor  21  by a narrow dielectric  20 . Narrow dielectric  20  has a dimension on the order of less than 200 angstroms (&lt;20 nm) between the select gate and control gate transistors. Narrow dielectric  20  can include, for example, a narrow oxide sidewall dielectric. Memory device  10  also includes source/drain regions  30  and  32 . The various layers and doped regions, as discussed herein, of memory device  10  can be fabricated, respectively, using techniques known in the art. 
     In one embodiment, the memory device  10  includes a split gate device in which a layer of nanoclusters is embedded between first and second dielectric layers, wherein the split gate device is utilized for non-volatile charge storage. That is, the split gate device has a control gate transistor with nanoclusters embedded between a bottom and top dielectric, and a select gate transistor with a gate dielectric. The first and second dielectric layers include dielectrics having a thickness on the order of 35-70 Å. In addition, the transistors of the split gate device are separated by a narrow dielectric area, such that source side injection is possible. 
     Examples of source side injection with biases as applied to the 1-bit storage cell of memory device  10  are provided in Table 1 and Table 2. That is, Table 1 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler-Nordheim tunneling through the top dielectric  26  of the 1-bit storage cell of memory device  10 . In addition, Table 2 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler-Nordheim tunneling through the bottom dielectric  22  of the 1-bit storage cell of memory device  10 . Read current flows in the opposite direction to the write current. 
     In the embodiment of FIG. 1, the bitcell operating voltages are as follows. Bitcell well  12  of memory device  10  includes a p-type well at a bitcell well voltage, Vpw. Select gate  18  includes a polysilicon select gate, wherein a select gate voltage, Vsg, is applied to the same. Control gate  28  includes a polysilicon control gate, wherein a control gate voltage, Vcg, is applied to the same. Source and drain regions ( 30 ,  32 ) are at respective source/drain voltages, Vsource/Vdrain. In the tables, Vdd represents a positive supply voltage, b/c Vt represents the bitcell threshold voltage, and “float” represents neither coupled to a voltage or ground. 
     
       
         
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Bitcell operating voltages for erase through top oxide for 1-bit storage. 
               
             
          
           
               
                   
                   
                 Select 
                 Control 
                   
                 Bitcell P- 
                 Deep N- 
               
               
                 Terminal 
                 Source 
                 Gate 
                 Gate 
                 Drain 
                 Well 
                 Well 
               
               
                   
               
               
                 Programming, 
                 5 V 
                 1 V 
                 5 V 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 selected bitcell 
               
               
                 Programming, 
                 5 V 
                 0 V 
                 0 V or 5 V 
                 5 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
               
               
                 bitcell 
               
               
                 Erase, selected 
                 −6 V or 
                 −6 V or 0 V 
                 6 V 
                 −6 V or 
                 −6 V   
                 0 V 
               
               
                 sector 
                 float 
                   
                   
                 float 
               
               
                 Erase, 
                 0 V or float 
                 0 V 
                 0 V 
                 0 V or float 
                 0 V 
                 0 V 
               
               
                 unselected 
               
               
                 sector 
               
               
                 Read, selected 
                 0 V 
                 Vdd 
                 Vdd or 
                 1 V 
                 0 V 
                 Vdd 
               
               
                 bitcell 
                   
                   
                 0 V, but 
               
               
                   
                   
                   
                 &gt;b/c Vt 
               
               
                 Read, 
                 0 V 
                 0 V 
                 Vdd or 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
                   
                   
                 0 V, but 
               
               
                 bitcell 
                   
                   
                 &gt;b/c Vt 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Bitcell operating voltages for erase through bottom oxide for 1-bit storage. 
               
             
          
           
               
                   
                   
                 Select 
                 Control 
                   
                 Bitcell P- 
                 Deep N- 
               
               
                 Terminal 
                 Source 
                 Gate 
                 Gate 
                 Drain 
                 Well 
                 Well 
               
               
                   
               
               
                 Programming, 
                 5 V 
                 1 V 
                 5 V 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 selected bitcell 
               
               
                 Programming, 
                 5 V 
                 0 V 
                 0 V or 5 V 
                 5 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
               
               
                 bitcell 
               
               
                 Erase, selected 
                 6 V or float 
                 0 V 
                 −6 V   
                 6 V or float 
                 6 V 
                 6 V 
               
               
                 sector 
               
               
                 Erase, 
                 0 V or float 
                 0 V 
                 0 V 
                 0 V or float 
                 0 V 
                 0 V 
               
               
                 unselected 
               
               
                 sector 
               
               
                 Read, selected 
                 0 V 
                 Vdd 
                 Vdd or 
                 1 V 
                 0 V 
                 Vdd 
               
               
                 bitcell 
                   
                   
                 0 V, but &gt; 
               
               
                   
                   
                   
                 b/c Vt 
               
               
                 Read, 
                 0 V 
                 0 V 
                 Vdd or 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
                   
                   
                 0 V, but &gt; 
               
               
                 bitcell 
                   
                   
                 b/c Vt 
               
               
                   
               
             
          
         
       
     
     FIG. 2 is a cross-sectional view of a nonvolatile memory device  40  having a split gate with nanoclusters embedded within a dielectric layer and disposed under polysilicon spacers according to another embodiment of the present disclosure. In the embodiment of FIG. 2, the device  40  is built with control gates  52  formed by poly spacers. Accordingly, two bits can be stored, one bit on either side of the select gate  44 . 
     In one embodiment, a write operation for the device  40  of FIG. 2 has a low programming current on the order of approximately 1-10 μA and a fast programming time on the order of approximately 1-10 μsec. The erase operation operates on a block of bitcells with low erase current and an erase time on the order of approximately 10-100 msec. In typical non-volatile memory devices, the select gate uses a thin gate oxide on the order of approximately 50-100 Å oxide, wherein the thin gate oxide is similar to a low voltage transistor oxide. However, in device  40  of the present disclosure, the select gate  44  includes a high voltage oxide with a thickness on the order of approximately 70-90 Å. Such a high voltage oxide is similar to an input/output transistor (I/O) oxide. The 90 Å-thick oxide is necessary if the bitcell well  12  is biased at +6V or −6V to enable splitting the erase voltages between the bitcell well  12  and a corresponding control gate. 
     In another embodiment, the device  40  includes a nanocluster-based memory device having select gate transistor  58 ; a thin film storage stack consisting of a bottom oxide  46  having a thickness on the order of 50-70 Å, a layer of nanoclusters  48  on the order of 20-25% surface coverage, and a top oxide  50  of a high temperature oxide (HTO) having a thickness on the order of approximately 50 Å; and sidewall spacer control gates  52  on both sides of the select gate  44 , over the thin film storage (TFS) stack. Top oxide  50  includes HTO since HTO is a deposited oxide and minimizes the number of electron or hole trap sites in the deposited oxide, as compared with a large number of electron or hole trap sites in a low temperature oxide (e.g., TEOS). Accordingly, the thin film storage stack includes top oxide  50 , nanoclusters  48 , and bottom oxide  46  in the region disposed below a respective gate electrode  52 . In addition, memory device  40  is configured for source-side injection programming and for Fowler-Nordheim tunneling erase through the top oxide  50 . The various layers and doped regions, as discussed herein, of memory device  40  can be fabricated, respectively, using techniques known in the art. 
     Examples of source side injection with biases as applied to the 2-bit storage cell of memory device  40  are provided in Table 3 and Table 4. That is, table 3 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler-Nordheim tunneling through the top dielectric  50  of the 2-bit storage cell of memory device  40 . In addition, table 4 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler-Nordheim tunneling through the bottom dielectric  46  of the 2-bit storage cell of memory device  40 . Read current flows in the opposite direction to the write current. 
     In the embodiment of FIG. 2, the bitcell operating voltages are as follows. Bitcell well  12  of memory device  10  includes a p-type well at a bitcell well voltage, Vpw. Select gate  44  includes a polysilicon select gate, wherein a select gate voltage, Vsg, is applied to the same. Control gates  52  include polysilicon control gates, wherein a first and second control gate voltage, Vcg 1 , Vcg 2 , is applied to the same, respectively. Source and drain regions ( 30 ,  32 ) are at respective source/drain voltages, Vsource/Vdrain. In the tables, Vdd represents a positive supply voltage, b/c Vt represents the bitcell threshold voltage, Vo represent a programmed threshold voltage in which the nanocrystals are charged with one or more electrons, and “float” represents neither coupled to a voltage or ground. 
     
       
         
               
             
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 Bitcell operating voltages for erase through top oxide for 2-bit storage. 
               
             
          
           
               
                   
                   
                 Select 
                 Control 
                 Control 
                   
                 Bitcell 
                 Deep N- 
               
               
                 Terminal 
                 Source 
                 Gate 
                 Gate 1 
                 Gate 2 
                 Drain 
                 P-Well 
                 Well 
               
               
                   
               
               
                 Programming, 
                 5 V 
                 1 V 
                 5 V  
                 5 V or 0 V 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 selected bitcell, 
               
               
                 left bit 
               
               
                 Programming, 
                 0 V 
                 1 V 
                 5 V or 0 V 
                 5 V 
                 5 V 
                 0 V 
                 Vdd 
               
               
                 selected bitcell, 
               
               
                 right bit 
               
               
                 Programming, 
                 5 V 
                 0 V 
                 0 V or 5 V 
                 0 V or 5 V 
                 5 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
               
               
                 bitcell 
               
               
                 Erase, selected 
                 −6 V or 
                 −6 V or 
                 6 V 
                 6 V 
                 −6 V or 
                 −6 V   
                 0 V 
               
               
                 sector 
                 float 
                 0 V  
                   
                   
                 float 
               
               
                 Erase, 
                 0 V or 
                 0 V 
                 0 V 
                 0 V 
                 0 V or 
                 0 V 
                 0 V 
               
               
                 unselected 
                 float 
                   
                   
                   
                 float 
               
               
                 sector 
               
               
                 Read, selected 
                 0 V 
                 Vdd 
                 Vdd or 
                 (Vdd + 
                 1 V 
                 0 V 
                 Vdd 
               
               
                 bitcell 
                   
                   
                 0 V, but 
                 Vo) or 
               
               
                   
                   
                   
                 &gt;b/c Vt 
                 Vo 
               
               
                 Read, 
                 0 V 
                 0 V 
                 (Vdd + 
                 Vdd or 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
                   
                   
                 Vo) or 
                 0 V, but 
               
               
                 bitcell 
                   
                   
                 Vo 
                 &gt;b/c Vt 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 Bitcell operating voltages for erase through bottom oxide for 2-bit storage. 
               
             
          
           
               
                   
                   
                 Select 
                 Control 
                 Control 
                   
                 Bitcell 
                 Deep N- 
               
               
                 Terminal 
                 Source 
                 Gate 
                 Gate 1 
                 Gate 2 
                 Drain 
                 P-Well 
                 Well 
               
               
                   
               
               
                 Programming, 
                 5 V 
                 1 V 
                 5 V 
                 5 V or 0 V 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 selected bitcell, 
               
               
                 left bit 
               
               
                 Programming, 
                 0 V 
                 1 V 
                 5 V or 0 V 
                 5 V 
                 5 V 
                 0 V 
                 Vdd 
               
               
                 selected bitcell, 
               
               
                 right bit 
               
               
                 Programming, 
                 5 V 
                 0 V 
                 0 V or 5 V 
                 0 V or 5 V 
                 5 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
               
               
                 bitcell 
               
               
                 Erase, selected 
                 6 V or 
                 0 V 
                 −6 V  
                 −6 V  
                 6 V or 
                 6 V 
                 6 V 
               
               
                 sector 
                 float 
                   
                   
                   
                 float 
               
               
                 Erase, 
                 0 V or 
                 0 V 
                 0 V 
                 0 V 
                 0 V or 
                 0 V 
                 0 V 
               
               
                 unselected 
                 float 
                   
                   
                   
                 float 
               
               
                 sector 
               
               
                 Read, selected 
                 0 V 
                 Vdd 
                 Vdd or 
                 (Vdd + 
                 1 V 
                 0 V 
                 Vdd 
               
               
                 bitcell, left bit 
                   
                   
                 0 V, but 
                 Vo) or 
               
               
                   
                   
                   
                 &gt;b/c Vt 
                 Vo 
               
               
                 Read, selected 
                 0 V 
                 Vdd 
                 (Vdd + 
                 Vdd or 
                 1 V 
                 0 V 
                 Vdd 
               
               
                 bitcell, right bit 
                   
                   
                 Vo) or 
                 0 V, but 
               
               
                   
                   
                   
                 Vo 
                 &gt;b/c Vt 
               
               
                 Read, 
                 0 V 
                 0 V 
                 Vdd or 
                 Vdd or 
                 0 V 
                 0 V 
                 Vdd 
               
               
                 unselected 
                   
                   
                 0 V, but 
                 0 V, but 
               
               
                 bitcell 
                   
                   
                 &gt;b/c Vt 
                 &gt;b/c Vt 
               
               
                   
               
             
          
         
       
     
     FIG. 3 is a schematic diagram of a nonvolatile memory device  70  according to another embodiment of the present disclosure. Memory device  70  includes an array of bit cells arranged in rows and columns, including bit cells according to the various embodiments disclosed herein, indicated by reference numerals  72 ,  74 ,  76 , and  78 , for example. Memory device  70  further includes a row decoder  80 , column decoder  82 , sense amplifiers  84 , and control circuit  88  for controlling row decoder  80  and column decoder  82 . Row decoder  80  receives address information via address input  90 . Column decoder  82  receives address information via address input  92 . Sense amplifiers receive signal information from column decoder  82  and output the amplified information or data out on data output  94 . Row decoder  80  decodes address information received on address input  90  and outputs information on appropriate word lines  96 ,  98 . Column decoder  82  decodes address information received on address input  92  and receives information via bit lines  100 ,  102 ,  104 . 
     In one embodiment, the bit cell  72  includes a memory device having a select gate transistor  112  and sidewall transistors  114 ,  116  disposed on opposite sides of gate transistor  112 . Sidewall transistors  114  and  116  include dielectric nanocluster thin film storage memory stacks  118  and  120 , respectively. The dielectric nanocluster thin film storage memory stacks  118  and  120  comprise stacks similar to those of FIGS. 1,  2  or  4 . Bit cell  72  further includes source/drain regions  122  and  124  coupled to corresponding bit lines  102  and  104 , respectively. Still further, bit cell  72  includes a deep well region coupled to a voltage potential VWE , as indicated by reference numeral  126 . 
     FIG. 4 is a cross-sectional view of a nonvolatile memory device  130  including shallow implants ( 132 ,  134 ) according to another embodiment of the present disclosure. No assumptions have been made for the charge-neutral control gate threshold voltage of the spacer device of control gate transistors ( 54 ,  56 ). Using shallow antimony or arsenic implants ( 132 ,  134 ) performed after select gate formation ( 44 ), the threshold voltage Vt of a respective spacer device can be below zero volts (0 V), thereby alleviating the need for biasing the control gates during a read operation. In other words, the memory device  40  is fabricated with a selectively lower channel doping under a respective spacer device using self-aligned counter doped implants of arsenic (As) or antimony (Sb). Counter dopants of As and Sb are selected due to their ability to not substantially diffuse in subsequent processing steps. In addition, the spacer devices have a channel region on the order of approximately 200-1000 angstroms, i.e., short channel device. Accordingly, the threshold voltage of the spacer devices is lowered without degradation of performance characteristics of the short channel spacer devices. 
     Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed. 
     In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. 
     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Technology Classification (CPC): 6