Patent Abstract:
It is an aspect of the embodiments discussed herein to provide a semiconductor device including: a substrate; a base on the substrate; an integrated circuit chip on the base; and a ball grid array type package material made of a resin and encapsulating the integrated circuit chip.

Full Description:
TECHNICAL FIELD  
       [0001]     The embodiments discussed herein are directed to a semiconductor device provided with a Ball Grid Array (BGA) package.  
       BACKGROUND ART  
       [0002]     Recently, demands for reduction in size, in thickness and in weight of portable electronic equipment such as digital video cameras, digital portable phones, and laptop personal computers have been increased. In order to respond to these demands, about 70% reduction in size has been realized in three years in semiconductor devices such as a recent VLSI or the like. However, it cannot be said that this is a sufficient amount, and that improvement in the part packaging density on a packaged substrate is cited as an important problem. Accordingly, research and development into this problem have been conducted.  
         [0003]     As a conventional semiconductor package, for example, a Through Hall Mount Device (THD) package and a Surface Mount Device (SMD) package have been adopted. In the through hall mount device package, mounting is performed by inserting a lead wire into a through hall provided to a printed board. As an example for it, a Dual Inline Package (DIP), a Pin Grid Array (PGA) and the like can be cited. In the surface mount type package, mounting is conducted by soldering a lead wire on the surface of the substrate. As this example, a Quad Flat Package (QFP), a Tape Carrier Package (TCP), a Ball Grid Array (BGA), a Chip Size Package (CSP), and the like can be cited.  
         [0004]     As for the BGA or the CSP, a semiconductor integrated circuit (IC) chip is attached and fixed on one surface of a printed board. On the other surface of the printed board, a plurality of external connection terminals made of solder balls are attached. A plurality of electrodes of the IC chip are led-through to the external connection terminals.  FIG. 9  is a perspective view showing a conventional BGA package, and  FIG. 10  is a cross sectional view showing the conventional BGA package.  
         [0005]     In the conventional BGA package, an IC chip (semiconductor integrated circuit)  105  is mounted on one surface of a printed board  101  for an interposer. As an insulating layer composing the printed board  101 , a glass epoxy resin layer, a polyimide layer, or the like are used, for example. In addition, on the other surface of the printed board  101 , a plurality of external connection terminals  108  made of solder balls are provided. Bonding wires  106  are connected to a plurality of electrodes  110  provided on the upper surface of the IC chip  105 , and the other ends of the bonding wires  106  are connected to lands  102  provided to the printed board  101 . A conductive layer (not shown) is provided in the printed board  101 . The lands  102  are connected to the external connection terminals  108  via the conductive layer. Then, a package resin  107  to cover the IC chip  105  and so on is formed. Thus, a packaged semiconductor device is composed.  
         [0006]     When the semiconductor device is installed on a mother printed board  151 , as shown in  FIG. 11 , after each external connection terminal  108  of the semiconductor device is abutted on a printed board terminal  152  provided to the mother printed board  151 , the lower portions of the respective external connection terminals  108  are melted and welded to the printed board terminals  152  by reflowing.  
         [0007]     When such an installation is performed, however, as shown in  FIG. 12 , the printed board  101  for the interposer sometimes bends backward due to the thermal stress caused by the reflowing. As a result, the IC chip  105  which is inside the semiconductor device also bends. When a piezoelectric device such as a ferroelectric capacitor or the like composing a ferroelectric memory is contained in the IC chip  105 , since a compressive stress or a tensile stress is applied on the piezoelectric device, normal operations are impossible. In particular, when a ferroelectric memory is provided, data storage functions may be lost, data readout becomes disabled, or malfunctions may occur.  
         [0008]     Furthermore, even in a chip which shows no problems at the time of reflowing, moisture may penetrate into the inside the IC chip with extended use. This results in expansion and distortion of the chip, and may cause malfunctions as described above.  
         [0009]     Patent Document 1: Japanese Patent Application Laid-open No. 2001-60638  
         [0010]     Patent Document 2: Japanese Patent Application Laid-open No. 2001-156095  
         [0011]     Patent Document 3: Japanese Patent Application Laid-open No. 2001-85458  
         [0012]     Patent Document 4: Japanese Patent Application Laid-open No. Hei 7-45735  
       SUMMARY  
       [0013]     It is an aspect of the embodiments discussed herein to provide a semiconductor device including a substrate; a base on the substrate; an integrated circuit chip on the base; and a ball grid array type package material made of a resin and encapsulating the integrated circuit chip. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1A  is a cross sectional view showing a method for manufacturing a semiconductor device according to a first embodiment in process order;  
         [0015]      FIG. 1B  is a cross sectional view showing a method for manufacturing a semiconductor device, following  FIG. 1A  in process order;  
         [0016]      FIG. 1C  is a cross sectional view showing a method for manufacturing a semiconductor device, following  FIG. 1B  in process order;  
         [0017]      FIG. 2  is a cross sectional view showing the semiconductor device according to the first embodiment;  
         [0018]      FIG. 3  is a cross sectional view showing a semiconductor device according to a second embodiment;  
         [0019]      FIG. 4  is a cross sectional view showing a semiconductor device according to a third embodiment;  
         [0020]      FIG. 5  is a graph showing temperature characteristics of an iron-manganese-silicon base stress inductive shape-memory alloy;  
         [0021]      FIG. 6  is a cross sectional view showing a semiconductor device according to a fourth embodiment;  
         [0022]      FIG. 7  is a cross sectional view showing a semiconductor device according to a fifth embodiment;  
         [0023]      FIG. 8  is a cross sectional view showing a detail of a printed circuit board  1   c  in the fifth embodiment;  
         [0024]      FIG. 9  is a perspective view showing a conventional BGA package;  
         [0025]      FIG. 10  is a cross sectional view showing the conventional BGA package;  
         [0026]      FIG. 11  is a cross sectional view showing a relation between the conventional BGA package and a mother printed board;  
         [0027]      FIG. 12  is a cross sectional view showing a bend of a printed board  11 ;  
         [0028]      FIG. 13A  is a cross sectional view showing a method for manufacturing a printed circuit board in process order;  
         [0029]      FIG. 13B  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13A  in process order;  
         [0030]      FIG. 13C  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13B  in process order;  
         [0031]      FIG. 13D  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13C  in process order;  
         [0032]      FIG. 13E  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13D  in process order;  
         [0033]      FIG. 13F  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13E  in process order;  
         [0034]      FIG. 13G  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13F  in process order;  
         [0035]      FIG. 13H  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13G  in process order;  
         [0036]      FIG. 13I  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13H  in process order;  
         [0037]      FIG. 13J  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13I  in process order;  
         [0038]      FIG. 13K  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13J  in process order;  
         [0039]      FIG. 13L  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13K  in process order;  
         [0040]      FIG. 13M  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13L  in process order;  
         [0041]      FIG. 13N  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13M  in process order;  
         [0042]      FIG. 13O  is a cross sectional view showing the method for manufacturing the printed circuit board following  FIG. 13N  in process order; and  
         [0043]      FIG. 14  is a view showing an example of a printed circuit board. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0044]     As a result of earnest studies to solve the above-described problems, the present inventor has found that in a conventional BGA package, since a resin layer  107  exists only above an IC chip  105 , variation of stress acting on the semiconductor device is large, which creates bending and distortion described above.  
         [0045]     The present inventor has paid attention to such problems and has come up with various forms of the embodiment shown below.  
         [0046]     Hereinafter, embodiments will be explained with reference to attached drawings.  
       First Embodiment  
       [0047]     A first embodiment will be explained. A cross sectional structure of a semiconductor device will be explained here together with its method for manufacturing for convenience&#39; sake.  FIG. 1A  to  FIG. 1C  are cross sectional views showing a method for manufacturing a semiconductor device according to the first embodiment, and  FIG. 2  is a cross sectional view showing the semiconductor device according to the first embodiment.  
         [0048]     In the first embodiment, as shown in  FIG. 1A , a base  3  made of a resin is formed on a printed circuit board  1  on which lands  2  are provided. The height of the base  3  is about 100 μm to about 200 μm, for example. As the printed circuit board  1 , for example, a glass epoxy substrate is usable.  
         [0049]     Next, as shown in  FIG. 1B , an adhesive  4  is applied to the base  3 , and a semiconductor integrated circuit chip (IC chip)  5  is mounted thereon and fixed. A silver paste may be used instead of the adhesive  4 . As the IC chip  5 , for example, a chip provided with a ferroelectric memory is use. The height of the IC chip  5  is, for example, about 200 μm.  
         [0050]     Next, as shown in  FIG. 1C , terminals (not shown) provided to the IC chip  5  and the lands  2  are connected with bonding wires  6 . Thereafter, the IC chip  5 , the bonding wires  6 , and so on are encapsulated with a package resin  7 . The thickness of the package resin  7  with reference to the upper surface of the IC chip  5  is preferably 40 μm or more. Furthermore, it is preferable to use a material containing fillers as the package resin  7 . Next, a number or the like to identify the IC chip  5  is marked on the upper surface of the package resin  7  using laser beams or the like. On the back face of the printed circuit board  1 , solder balls  8 , for example, are placed as external connection terminals. Thereafter, though not shown, dicing is conducted. Note that as a resin composing the base  3 , a resin similar to the package resin  7  is used, for example. In this case, it is preferable to set the filler content of the resin composing the base  3  higher than that of the package resin  7 .  
         [0051]     As described above, a BGA package structured semiconductor device is completed. This semiconductor device is mounted above a mother printed board  51  and used, as shown in  FIG. 2 .  
         [0052]     In the first embodiment, the base  3 , whose material is similar to that of the package resin  7 , exists below the IC chip  5 . Accordingly, even when a stress is acting on the package resin  7  associated with moisture absorption and reflowing, the stress acts on the IC chip  5  substantially in a uniform fashion from the surroundings. Accordingly, even when a piezoelectric device such as a ferroelectric capacitor composing a ferroelectric memory is contained, malfunctions and the like never occur.  
         [0053]     The filler content of the resin composing the base  3  is adjusted to be higher than that of the package resin  7  so that the amount of the moisture absorption is lower than that of the package resin  7 . Accordingly, it becomes possible to relax the compression stress more.  
         [0054]     Furthermore, in the present embodiment, since the thickness of the package resin  7  with reference to the upper surface of the IC chip  5  is set to be 40 μm or more, no damage extends to the IC chip  5  even when marking is conducted by a laser beam.  
       Second Embodiment  
       [0055]     Next, a second embodiment will be explained next.  FIG. 3  is a cross sectional view showing a semiconductor device according to the second embodiment.  
         [0056]     In the second embodiment, a multi chip package (MCP) tape  9  is stuck on the printed circuit board  1 , and the IC chip  5  is fixed thereon. The other points are structured similarly to those in the first embodiment.  
         [0057]     In the second embodiment thus structured, the MCP tape  9  acts similarly to the base  3  in the first embodiment. As a result, the similar effects to those of the first embodiment can be obtained.  
       Third Embodiment  
       [0058]     Next, a third embodiment will be explained.  FIG. 4  is a cross sectional view showing a semiconductor device according to the third embodiment.  
         [0059]     In the third embodiment, an adhesive  4   a  is applied to the base  3 , and a metal plate  11  made of a shape-memory alloy is stuck thereon. In addition, an adhesive  4   b  is applied to the metal plate  11 , and the IC chip  5  is mounted thereon and fixed. The shape-memory alloy composing the metal plate  11  is, for example, an iron-manganese-silicon (Fe—Mn—Si) base stress inductive shape-memory alloy, and has temperature characteristics as shown in  FIG. 5 . That is, this shape-memory alloy phase-transforms at a reflowing temperature of about 240° C. to about 270° C. as a boundary. Note that a silver paste or the like may be used instead of the adhesives  4   a  and  4   b.    
         [0060]     In the third embodiment thus structured, even when a thermal stress occurs at the time of reflowing, the metal plate  11  formed from the shape-memory alloy intends to restore to the original shape. Accordingly, stress does not act on the IC chip  5 , and no malfunctions occur in the ferroelectric memory and the like.  
         [0061]     Note that the base  3  is not necessarily provided but it is preferable that the base  3  is provided in order to obtain an integrated effect.  
       Fourth Embodiment  
       [0062]     Next, a fourth embodiment will be explained.  FIG. 6  is a cross sectional view showing a semiconductor device according to the fourth embodiment.  
         [0063]     In the fourth embodiment, the adhesive  4   a  is applied to the printed circuit board  1  and the metal plate  11  made of the shape-memory alloy is stuck thereon. The adhesive  4   b  is further applied to the metal plate  11 , and a metal plate  11   a  made of another shape-memory alloy is stuck thereon. An adhesive  4   c  is applied to the metal plate  11   a , and the IC chip  5  is mounted thereon and fixed. Note that, as the shape-memory alloy composing the metal plate  11   a , a material that phase-transforms at about 85° C. to about 100° C. as a boundary is used. Furthermore, a silver paste or the like may be used instead of the adhesives  4   a  to  4   c.    
         [0064]     In the fourth embodiment thus structured, effects similar to those in the third embodiment can be obtained owing to the function of the metal plate  11 . Furthermore, since the metal plate  11   a  is provided, even when the temperature rises to about 85° C. to about 100° C. at the point of use, and thermal stress is generated in the package resin  7 , this thermal stress is cancelled by a restoration force of the metal plate  11   a . Accordingly, stress does not act on the IC chip  5  and no malfunctions occur in the ferroelectric memory and the like. The temperature about 85° C. to about 100° C. is, for example, a temperature to reach when the semiconductor device is installed on a car, for example.  
         [0065]     Note that though the base  3  is not provided in the fourth embodiment, the base  3  may be provided between the printed circuit board  1  and the adhesive  4   a.    
       Fifth Embodiment  
       [0066]     Next, a fifth embodiment will be explained.  FIG. 7  is a cross sectional view showing a semiconductor device according to the fifth embodiment, and  FIG. 8  is a cross sectional view showing a detail of a printed circuit board  1   c  in the fifth embodiment.  
         [0067]     In the fifth embodiment, a printed circuit board  1   c  includes two sheets of glass epoxy substrates  1   a  and  1   b , and a metal plate  12  sandwiched between them. The metal plate  12  is made of, for example, a shape-memory alloy that phase-transforms at about 150° C. to about 200° C. The IC chip  5  is fixed on the printed circuit board  1   c  with the adhesive  4 . Note that the temperature about 150° C. to 200° C. is a temperature to cure the package resin  7 .  
         [0068]     In the printed circuit board  1   c , a plurality of through holes are formed, as shown in  FIG. 8 , an insulating film  13  is formed in the inside surface thereof, and a conductive material  14  is embedded in the inside thereof. The land  2  is formed on the conductive member  14 , and the bonding wire  6  is connected to the land  2 . On the back face side of the printed circuit board  1   c , the conductive material  14  and the solder ball  8  are connected via a conductive layer  15 .  
         [0069]     In the fifth embodiment thus formed, thermal stress produced at the time of curing is cancelled by a restoration force of the metal plate  12 . Accordingly, malfunctions accompanying the thermal stress can be prevented.  
         [0070]     It should be noted that though the base  3  is not provided in the fifth embodiment, the base  3  may be provided between the printed circuit board  1   c  and the adhesive  4 .  
         [0071]     Note that the metal plate  12  may be smaller than the glass epoxy substrate  1   b  and  1   c  in planar view. In the event, a routed wiring, a through hole and so on may be formed on the outside of the metal plate  12 .  
         [0072]     Here, a method for manufacturing a printed circuit board suitable for the fifth embodiment will be explained.  FIG. 13A  to  FIG. 13O  are cross sectional views showing the method for manufacturing a printed circuit board.  
         [0073]     First, as shown in  FIG. 13A , a resist pattern  203  is formed on the surface of an insulating layer  202  side of a base material made by stacking a conductive layer  201  and the insulating layer  202  with each other.  
         [0074]     Next, as shown in  FIG. 13B , the insulating layer  202  is patterned using the resist pattern  203  as a mask. Then, the resist pattern  203  is removed.  
         [0075]     Then, as shown in  FIG. 13C , a conductive layer  204  is formed by, for example, a sputtering method on the insulating layer  202  and in the openings of the insulating layer  202 .  
         [0076]     Thereafter, as shown in  FIG. 13D , flattening is conducted to the conductive layer  204  by an etch-back method or a CMP method.  
         [0077]     Then, as shown in  FIG. 13E , an insulating layer  205  is formed over the insulating layer  202  and the conductive layer  204 . In addition, a resist pattern  217  is formed on the insulating layer  205 .  
         [0078]     Next, as shown in  FIG. 13F , the insulating layer  205  is patterned using the resist pattern  217  as a mask. Then, the resist pattern  217  is removed.  
         [0079]     Then, as shown in  FIG. 13G , a conductive layer  206  is formed by, for example, a sputtering method on the insulating layer  205  and in the openings of the insulating layer  205 .  
         [0080]     Thereafter, as shown in  FIG. 13H , flattening is conducted to the conductive layer  206  by an etch-back method or a CMP method.  
         [0081]     Then, as shown in  FIG. 13I , an insulating layer  216  and a shape-memory alloy film  207  are formed over the entire surface.  
         [0082]     Next, as shown in  FIG. 13J , a resist pattern  208  is formed on the shape-memory alloy film  207 .  
         [0083]     Then, as shown in  FIG. 13K , the shape-memory alloy film  207  is patterned using the resist pattern  208  as a mask.  
         [0084]     Thereafter, as shown in  FIG. 13L , the resist pattern  208  is removed. Then, an interlayer insulating film  209  is formed on the shape-memory alloy film  207  and in the openings of the shape-memory alloy film  207 .  
         [0085]     Then, as shown in  FIG. 13M , flattening is conducted to the interlayer insulating film  209  by an etch-back method or a CMP method. Then, an insulating layer  210  is formed over the entire surface and a resist pattern  211  is formed thereon. The insulating layer  210  is patterned using the resist pattern  211  as a mask.  
         [0086]     Furthermore, as shown in  FIG. 13N , the interlayer insulating film  209  and the insulating layer  216  are patterned using the resist pattern  211  as a mask. As a result, a portion of the insulating layer  206  is exposed.  
         [0087]     Then, as shown in  FIG. 13O , the resist pattern  211  is removed. Thereafter, a conductive layer  212  reaching the conductive layer  206  is formed over the whole surface. The conductive layer  212  may be formed by a sputtering method. In addition, it is also possible to form a W film as the conductive layer  212  and form a W plug from it.  
         [0088]     By repeating the formation and the pattering of a conductive layer and an insulating layer similar to those, the formation of a printed circuit board as shown in  FIG. 14  is completed. In this printed circuit board, conductive layers  213  and  214  are connected to the conductive layer  212 , and a land  215  is connected to the conductive layer  214 . The conductive layer  201  is patterned, to which the solder ball  8  is connected. Insulating layers  221  and  222  are formed in the surroundings of routed wirings composed of these conductive layers.  
         [0089]     Furthermore, it is possible to combine the respective embodiments with each other. For example, the fifth embodiment and each of the first to the fourth embodiments may be combined. In addition to that, a titanium-nickel (Ti—Ni) base alloy may be used instead of the iron-manganese-silicon base alloy as a shape-memory alloy.  
         [0090]     It should be noted that provision of a shape memory member in a printed board is disclosed in Patent Document 1, but the temperature of its phase-transformation is not disclosed. Accordingly, it is not clear in what manner and how it functions.  
         [0091]     In Patent Documents 2 and 3, formation of the bump unit with the shape-memory alloy is disclosed. In Patent Document 4, it is disclosed to use a shape-memory alloy for a part of the semiconductor device cap. However, neither of the thermal stresses at the time of reflowing and curing can be relaxed.  
         [0092]     The order of embodiments does not has a particular meaning and has nothing to do with the importance of the embodiments.  
       INDUSTRIAL APPLICABILITY  
       [0093]     As described above, according to the embodiment, even when thermal stresses and/or stresses accompanying moisture absorption may occur, these stresses are relaxed. Accordingly, even when a piezoelectric device such as a ferroelectric capacitor is provided in an integrated circuit chip, the possible malfunctions thereof can be avoided.

Technology Classification (CPC): 7