Patent Abstract:
A system and method for utilizing a feedback-based delay stabilization and power optimization circuit. One embodiment of the present invention is directed to an electronic circuit comprising an indicator operable to generate an indicator signal that is proportional to an actual operating speed of an integrated circuit that includes the indicator; and a comparator operable to compare the indicator signal to a reference signal and to generate from the comparison an error signal that is proportional to a difference between the operating speed and a desired operating speed. A signal combining circuit may then generate a feedback signal for a power supply based upon the error signal and an output signal of the power supply.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    The performance of an integrated circuit (IC) typically depends on several parameters that influence the speed at which the IC operates. Three such parameters are the IC&#39;s voltage supply, the IC&#39;s operating temperature, and the thickness of the IC&#39;s transistor-gate oxides. Variations in these parameters from respective nominal values may affect the delay time of signals that propagate within the IC, and thus, may vary the operating speed of the IC from a nominal speed. For example, if the voltage supply is lower than the nominal value, logic gates within the IC may operate more slowly because the rise times between logic-0 and logic1 are longer due to the lower drive signal. Similarly, as the temperature of the IC decreases logic circuits operate more quickly due to the decrease in the transistor on resistances. Furthermore, the thinner the gate-oxides, the faster the transistors, and thus, the faster the logic circuits. Conversely, the higher the supply voltage, the more quickly the logic gates operate, and the higher the temperature or the thicker the gate-oxides, the more slowly the logic gates operate.  
           [0002]    Because these parameters may vary, the IC manufacturer typically accommodates these variations by predicting a best-case scenario and a worst-case scenario and designing the IC for a nominal case that is between the best- and worst-case scenarios. In a best-case scenario, the voltage supply is at its highest rated value, the IC operates at its lowest rated temperature, and the manufacturing process parameters (e.g., gate-oxide thickness) have their “fastest” values, such that the IC operates at its highest speed. Conversely, in the worst-case scenario, the voltage supply is at its lowest specified level, the temperature of the IC is at its highest rated value, and the manufacturing-process parameters have their “slowest” values, such that the IC operates at its slowest speed. By predicting the worst-case parameter values, an engineer can typically design an IC to operate adequately even under worst-case conditions.  
           [0003]    However, it is becoming more difficult to design an IC to operate properly over the range from worst-case to best-case conditions. For example, a designer may include compensation circuitry on the IC to stabilize the IC&#39;s operation over this range. But, as ICs become more dense (more transistors per unit area), there is less area in which to include compensation circuitry. Moreover, as ICs include more circuitry, the time for an engineer to design an IC that can operate over a wide range of parameter variations increases, thus, increasing the design time and time to market.  
           [0004]    Therefore, a need has arisen for a new way to compensate for the affect that parameter variations have on the operation of an IC.  
         SUMMARY OF THE INVENTION  
         [0005]    One aspect of the present invention is directed to a system and method for utilizing a feedback-based delay stabilization and power optimization circuit. One embodiment of the present invention is directed to an electronic circuit comprising an indicator operable to generate a indicator signal that is proportional to an actual operating speed of an integrated circuit that includes the indicator; and a comparator operable to compare the indicator signal to a reference signal and to generate from the comparison an error signal that is proportional to a difference between the operating speed and a desired operating speed. A signal combining circuit may then generate a feedback signal for a power supply based upon the error signal and an output signal of the power supply.  
           [0006]    One advantage of a circuit realized according to an embodiment of the invention is that a manufacturer of a typical integrated circuit can design a circuit with a smaller ratio between the delays associated with the best-case and worst-case scenarios. In one a conventional system, the ratio between the frequency of the best-case scenario and the worst-case scenario of a conventional system is approximately 2.4. In one embodiment of the invention, using a feedback-based delay stabilization circuit to adjust the power supply voltage results in the ratio from best-case to worst-case scenarios being improved to 1.3. Therefore, knowing this reduced ratio, a manufacturer can design the integrated circuit with an overall delay time that is smaller, and more efficient with less design effort.  
           [0007]    Another advantage of using a feedback-based delay stabilization circuit is the optimization of power use from the power supply for the integrated circuit. As the frequency of the monitored circuit is at its highest, i.e., best-case scenario, the voltage from the voltage supply may be adjusted lower since voltage compensation is not required to overcome other variations. As a result, power is saved at operating temperatures or process characteristics that are near the best-case scenario. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0009]    [0009]FIG. 1 is a block diagram of a feedback-based delay stabilization circuit according to an embodiment of the invention;  
         [0010]    [0010]FIG. 2 is a block diagram of an electronic system that includes more than one of the feedback-based delay stabilization circuit of FIG. 1 according to an embodiment of the invention; and  
         [0011]    [0011]FIG. 3 is a block diagram of an electronic system that includes feedback-based delay stabilization circuit of FIG. 1 according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0012]    Generally, a technique according to an embodiment of the invention calls for controlling one or more operating parameters of an IC such that the IC operates closer to its nominal operating point than it would without this parameter control. Therefore, this technique allows the IC designer more leeway when designing the IC, because the parameter control effectively reduces the range between the worst-case and best-case operating points.  
         [0013]    [0013]FIG. 1 is a block diagram a feedback-based delay-stabilization circuit  100 , which forces an IC  110  toward or to its nominal operating point by controlling the level of the supply voltage to the IC  110  according to an embodiment of the invention. The circuit  100  is coupled to a power supply  120 , which provides power to the IC  110 . The circuit  100  monitors the frequency of a signal—here a signal from a ring oscillator  112 —within the IC  110  and is able to adjust the supply voltage from the power supply  120  in response to a change in the frequency of the monitored frequency. The circuit  100  includes the ring oscillator  112 , one or more frequency dividers  151 A and  151 B, a phase-frequency detector  114  (PFD), a low-pass filter  119  (LPF), a biasing block  116 , a signal combining block  118 , and a clamp  130 , all of which are described in greater detail below.  
         [0014]    Because the ring oscillator  112  is disposed on the IC  110 , the frequency of the signal output from the ring oscillator is proportional to the operating point of the IC  110 . The ring oscillator  112  is designed such that its output signal has a nominal value when the IC  110  is operating at its nominal operating point, i.e., when the parameters such as supply voltage, temperature, and gate-oxide thickness are all at their nominal values. But if these operating parameters are on average skewed toward a best-case operating condition, then the frequency of the oscillator signal is higher than the nominal value, and thus reflects that the IC  110  is operating “faster” than nominal. Conversely, if these parameters are on average skewed toward a worst-case operating condition, then the frequency of the oscillator signal is lower than the nominal value, and thus reflects that the IC  110  is operating “slower” than nominal. Consequently, the frequency of the oscillator signal provides a noninvasive measurement of the operating point of the IC  110 . And as the operating point of the IC  110  fluctuates due to changes in the operating parameters, the frequency of the oscillator signal also changes, thus tracking the fluctuations in the operating point. For example, if the temperature of the IC  110  rises or the supply voltage falls, then the frequency of the oscillator signal will decrease, thus indicating the slower operation of the IC  110 . Conversely, if the temperature falls or the supply voltage rises, then the frequency of the oscillator signal will increase, thus indicating the faster operation of the IC  110 .  
         [0015]    As discussed below, one can use the ring oscillator  112  to drive the IC  110  toward its nominal operating point. Specifically, the feedback circuit  100  controls the supply voltage to the IC  110  so as to drive the frequency of the oscillator signal toward its nominal value, and thus, drive the IC  110  toward its nominal operating point. More specifically, a reference-clock generator  150 , which is external to the IC  110 , generates a signal having the nominal frequency of the ring oscillator  112 . Alternatively, if the generator  150  does not generate the reference clock having the nominal frequency of the oscillator  112 , then one or both of the frequency dividers  151 A and  151 B may be programmed so that the generator  150  effectively generates the reference clock having the nominal frequency. For example, suppose that the nominal frequency is 100 MHz, but that the generator  150  generates a 200 MHz reference clock. Then, one can program the divider  151 B to divide the frequency of the reference clock by two.  
         [0016]    The outputs of the ring oscillator  112  and the reference-clock generator  150  (possibly divided by the frequency dividers  151 A and  151 B) are fed into the PFD  114 , which generates a binary up/down voltage error signal, signifying which of the two frequencies is higher. The LPF  119  smoothens the voltage error to set the bandwidth of the feedback loop formed by the circuit  100  and the power supply  120 . The resulting filtered signal is then input to a biasing block  116  that limits and/or otherwise adjusts the voltage error signal. For example, the error signal, if left unbiased, may cause the power supply  120  to provide a supply voltage VDD that is higher than the IC  110  can tolerate. Therefore, there may be conventional circuitry within the biasing block  116  to limit the supply voltage to an acceptable level. Further, the biasing block  116  may be used to manipulate the error signal to a magnitude-based error signal or a percentage-based error signal.  
         [0017]    The biased voltage-error signal is input to a signal combining block  118  that combines the error signal with the supply voltage V DD . If the error signal is a magnitude-based error signal, then the two inputs to the combining block  118  are summed as is shown in FIG. 1. In an alternative embodiment, the error signal is a percentage-based error signal, in which case, the two inputs are multiplied. For example, suppose the power supply  120  is designed to maintain V DD  at the same voltage that is provided to the sense input  124 , the present supply voltage is 1.0 V, and the supply voltage VDD that will cause nominal operation of the IC  110  is 1.1 V. Therefore, one can design the circuit  100  such that under these instantaneous conditions, the bias circuit  116  will generate a 0.1 V magnitude-based error signal. Consequently the combiner  118  will sum with V DD =1 to obtain the desired 1.1 V feedback signal, which causes the supply to generate the desired V DD =1.1V. Alternatively assuming the same instantaneous conditions, one can design the circuit  100  such that the circuit  116  will generate a 110% percentage-based error signal. Consequently the combiner  118  will multiply V DD =1 by 1.1 (110%) to obtain the desired 1.1 V feedback signal, which causes the supply to generate the desired V DD =1.1V.  
         [0018]    Once the supply voltage VDD is adjusted to a level that causes nominal operation of the IC  110 , the frequency of the ring-oscillator signal then has the nominal value, i.e., the same frequency as the reference clock, thus stabilizing the IC  110  at its nominal operating point.  
         [0019]    If the power supply  120  does not have a feedback node  124 , then a voltage regulator (not shown) may be included either on or off the IC  110  to allow the above-described control of the supply voltage V DD .  
         [0020]    To summarize, the circuit  100  and the power supply  120  form a voltage-lock loop for controlling VDD  122  based on the difference between the frequency of the ring-oscillator signal  112  and the reference-clock. If the ring-oscillator frequency is lower than its nominal value, then the circuit  100  causes the supply  120  to increase the level of VDD so as to speed up the operation of the IC  110 ; conversely, if the ring-oscillator frequency is higher than its nominal value, then the circuit  100  causes the supply  120  to decrease the level of VDD so as to slow down the operation of the IC  110 .  
         [0021]    Still referring to FIG. 1, a clamp  130  allows one to set limits for the maximum and minimum levels of V DD . For example, if V DD    122  is too high, then the IC  110  may be damaged. Likewise, if V DD    122  is too low, then the integrated circuit may cease to function at all. As such, the voltage clamp circuit  130  may be placed between the combining block  112  and the sense input  124  such that voltage limits are imposed on the levels allowed for V DD . For example, where the IC  110  is designed for a nominal voltage input of 5.0 volts, the voltage clamp circuit  130  limits the maximum allowable level of V DD  to 5.7 volts and the minimum allowable level to 4.3 volts. Although the clamp  130  may prevent the circuit  100  from driving the IC  110  all the way to its nominal operating point, it typically allows the circuit  100  to drive the IC  110  closer to its nominal operating point than it would be without the circuit  100 .  
         [0022]    In one embodiment of the invention, the voltage clamp circuit  130  is realized by using an analog-to-digital converter (not shown) to convert the feedback signal from the combiner  118  to a digital value. The analog-to-digital converter may have a limit such that when the analog feedback signal exceeds a maximum or minimum limit, the analog-to-digital converter claims the digital value to a respective predetermined maximum or minimum value, thus clamping V DD  at a respective predetermined maximum or minimum voltage level. This clamped digital value may be provided directly to the feedback node  124 , or the circuit  130  may convert the clamped digital value back to an analog signal with a digital-to-analog converter (not shown).  
         [0023]    In another embodiment of the invention, the IC  110  may be powered by more than one power supply  120 . For example, a core power supply (not shown) and an I/O voltage supply (not shown) can be respectively used to power the core (e.g., memory or logic array) and the I/O circuitry of the IC  110 . As an example, the core power supply may be used to power the internal logic functions of the IC  110  and the I/O power supply may be used to power the input/output drivers of the IC  110 . The core supply voltage is often lower than the I/O supply voltage. For example, in a typical 0.13-micron process, the core supply voltage may be between 0.9 and 1.2 V and the I/O supply voltage between 3.0 and 3.5 V. Because the speed of the core is often more critical to the operation of the IC  110  than the speed of the I/O circuitry, the ring oscillator  112  may be formed in the same region of the IC  110  as the core, and thus the IC  110  may include one circuit  100  to control only the core supply voltage. Alternatively, a second ring oscillator disposed in the same region of the IC  110  as the I/O circuitry and a second circuit  100  may be used to control the I/O supply voltage. Or a single circuit  100  may be used to control both the core and I/O supply voltages.  
         [0024]    In another embodiment, the operating point of the IC  110  may be measured by means other than the ring oscillator  112 . For example, the IC  110  may include a circuit (not shown) for generating a voltage signal (not shown) that is dependent on temperature or on process variations such as gate-oxide thickness. The IC  110  may also include a comparison circuit (not shown) to compare this voltage signal to a voltage reference (internal or external, not shown), and to control V DD  as discussed above based on this comparison. That is, the dependent voltage signal effectively takes the place of the signal from the ring oscillator  112 .  
         [0025]    [0025]FIG. 2 shows an embodiment of the invention where a system includes multiple ICs powered by a common supply  220  and each having a respective feedback circuit  100  of FIG. 1 (the IC  212  has two feedback circuits  100  as discussed below). Generally, the circuits  100  act in concert to set the common supply voltage V DD  to a “best fit” value. Although this scheme may not force the ICs as close to their respective nominal operating points as if each IC were powered by a separate supply, it often does force the ICs closer to their respective nominal operating points as compared to a situation where the circuits  100  are omitted.  
         [0026]    More specifically, a power supply  220  may be used to supply power to a number of different integrated circuits, such IC 1    210 , IC 2    211 , and IC 3    212 . A respective feedback-based delay stabilization circuit  100 —minus the combiner  118  and clamp  130 —is included in the ICs  210 ,  211 , and  212 . A common combiner  290  combines each of the feedback signals and the supply voltage V DD  in a predetermined manner to generate a master feedback signal. For example, the combiner  290  may divide the value of each feedback signal by the number of feedback signals, and then sum the results with the supply voltage. This causes the supply  220  to generate a level for V DD  that takes into account the average value of he feedback signals. Alternatively, if the operation of one of the ICs is more critical than the operation of the other ICs, then the combiner  290  may weight the feedback signal from that IC more highly than the feedback signals from the other ICs such that the fractional weights of each feedback signal sums to unity.  
         [0027]    Still referring to FIG. 2, an IC may include more than one feedback-based delay stabilization circuit  100  as shown with respect to IC 3    212 . In a situation such as this, the operating point at more than one area of the IC 3    212  is monitored. A common reference-clock generator  150  (shown in FIG. 1 but not shown here for clarity) may supply a common reference clock to the circuits  100 , or a respective generator  150  generating the same or different reference frequencies may be provided for each circuit  100 . Furthermore, the IC  212  may be supplied by more than one power supply  220  (only one supply shown in FIG. 2). As such, the first circuit  100  may be associated with the first power supply  220  and the second circuit  100  may be associated with the second power supply.  
         [0028]    [0028]FIG. 3 is a block diagram of an electronic system, such as a computer system  300  that includes an IC  110  having a feedback-based delay-stabilization circuit  100  of FIG. 1. The electronic system includes a processor  301  coupled to a bus  305 . The bus  305  is coupled to the IC  110 , which may communicate with the processor  301  via the bus  305 . The IC  110 , which may be a memory device, is powered by an associated power supply  320  via a V DD  connection  322 . As discussed above in conjunction with FIG. 1, the circuit  100  generates a feedback signal (based on a comparison to a reference signal from a reference clock which is not shown for clarity) on a sense input line  324  which is coupled to a sense input terminal of the power supply  320 . As such, V DD  is adjusted based upon the operating speed of the IC  110  as described above.  
         [0029]    The preceding discussion is presented to enable a person skilled in the art to make and use the invention. The general principles described herein may be applied to embodiments and applications other than those detailed below without departing from the spirit and scope of the present invention. The present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

Technology Classification (CPC): 7