Patent Abstract:
Undue power consumption is reduced in the capacitance between data electrodes during addressing in a display panel. The power consumption associated with the capacitance is reduced to half as compared with the conventional panel, because the current associated with the discharge of the capacitance is independent of the power supply in the case of a combination of “L reset”, where the capacitance between data electrodes is discharged through a backward current path on the current sink terminal side, and “H reset”, where the capacitance between data electrodes is discharged through a backward current path on the current supply terminal side.

Full Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a driving method of a display panel such as a plasma display panel (PDP), a plasma addressed liquid crystal (PALC), a liquid crystal display (LCD) or a field emission display (FED), and to a thin type display device.  
         DESCRIPTION OF THE PRIOR ART  
         [0002]    A display panel is used as a device replacing a CRT in various fields. For example, a PDP is commercialized as a wall-hung TV set having a large screen above 40 inches. One of challenges to high definition and a large screen is a countermeasure against capacitance between electrodes.  
           [0003]    As shown in FIG. 16, a display panel comprises scan electrodes S 1 , S 2 , . . . , S N  for row selection and data electrodes A 1 , A 2 , . . . , A M  for column selection, which are arranged in a matrix. The suffix of the reference letter indicates an arrangement order of the electrode. A unit display area is defined at each of intersections of the scan electrodes S 1 -S N  and the data electrodes A 1 -A M , and a display element is disposed at each of the unit display area. FIG. 16 typically shows display elements of a first row and a second row in the (m+1)th column. As shown in FIGS. 17A to  17 D using symbols, display elements of a PDP and a PALC are discharge cells. An LCD has liquid cells as the display elements, while an FED has field emitters as the display elements. Furthermore, a commercialized surface discharge type PDP has two electrodes arranged for each row, and only one of the two electrodes is used for the row selection. Therefore, the electrode structure of the surface discharge type PDP is considered as a simple matrix similar to that of other types from the viewpoint of the display element selection.  
           [0004]    Contents of display are set by line sequential addressing as shown in FIG. 18. An address period TA of one frame is divided into row selection periods Ty whose number is the same as the number of lines N of the screen. Each of the scan electrodes S 1 -S N  is biased to a predetermined potential to be active in any one of the row selection periods Ty. Usually, the scan electrode is activated in order from an end of the arrangement in every row selection period. In synchronization with this row selection, display data of a row are outputted from data electrodes A 1 -A M  for each row selection period. Namely, potential of all data electrodes A 1 -A M  are controlled at the same time corresponding to the display data. The potential is controlled in a binary manner or in a multivalued manner for gradation display.  
           [0005]    The binary control of the potential of the data electrodes A 1 -A M  utilizes a switching circuit having a push-pull structure according to an embodiment of the present invention as shown in FIG. 5. Only one switching element Q 1 , constituting a pair of switching elements Q 1  and Q 2 , is turned on so as to connect the data electrode A m  to a power supply terminal of a driving power source (a high potential terminal of a voltage output). Otherwise, only the other switching element Q 2  is turned on so as to connect the data electrode A m  to a current sink terminal of the driving power source (a ground terminal, in general). ON or OFF of each switching element Q 1  or Q 2  is determined by the display data D m  of the corresponding column.  
           [0006]    [0006]FIG. 20 is a time chart for controlling the data electrode in the conventional driving method.  
           [0007]    It is supposed that a pair of switches SW 1  and SW 2  control the potential of the data electrode A m . The switch SW 1  corresponds to the above-mentioned switching element Q 1 , and the switch SW 1  corresponds to the switching element Q 2 .  
           [0008]    In a push-pull structure, it must be avoided that a pair of switches SW 1  and SW 2  are turned on at the same time, which causes a short circuit of the driving power source. Therefore, in order to prevent the short circuit securely when the row selection is switched under the condition where the display data D m  are different between n-th (1≦n&lt;N) row selection and the next (n+1)th row selection, both the switches SW 1  and SW 2  are turned off between the row selection periods Ty. In other words, in the n-th row selection period Ty, when one of the switches SW 1  and SW 2  is turned on, the switch SW 1  or the switch SW 2  is turned on at the starting stage of the row selection period Ty and is turned off before the end point of the row selection period Ty. This operation is performed by controlling the switches SW 1  and SW 2  using the AND signal of the timing signal TSC turning on and off in the row selection period and the display data D m  of the corresponding m-th column.  
           [0009]    In the conventional method, the on and off timings of the switch SW 1  are the same as those of the switch SW 2  for the start point of the row selection period Ty. In addition, the on and off timings of the switching element is also the same between the neighboring data electrodes. The conventional driving method had a problem in that there was much loss of power for charging a capacitance between the neighboring data electrodes. Hereinafter, this problem will be explained in detail.  
           [0010]    It is supposed that the addressing is performed in a pattern in which potential of the data electrodes are switched oppositely between the m-th column and the neighboring (m+1)th column as shown in FIG. 20, and the potential are switched in both columns every row selection period Ty. In this pattern, the display data D m  of the m-th column and the display data D m+1  of the (m+1)th column are set  0  or  1  alternately. The contents of the display are as shown in FIG. 19.  
           [0011]    [0011]FIG. 21 shows the problem of the conventional method.  
           [0012]    The problem is that when biasing the data electrode to the polarity opposite to the charge stored between the data electrodes, current canceling the charge must be supplied as being explained below.  
           [0013]    [Step  1 ] At the time point just before the end of the row selection period Ty, the switches SW 1   m  and SW 2   m  of the m-th column and the switches SW 1   m+1  and SW 2   m+1  of the (m+1)th column are off (high impedance state). The capacitance between the data electrodes is charged so that the m-th column side has the positive polarity (+) and the (m+1)th column side has the negative polarity (−). The letters in the parentheses indicate potentials in FIG. 21.  
           [0014]    [Step  2 ] At the time point when the switches SW 2   m  and SW 1   m+1  are turned on at the same time, the data electrode A m  is connected to the ground, and the potential of the data electrode A m+1  drops to −Va, so that current Ia canceling the charge stored in the capacitance between the data electrodes starts to flow from the power source passing through the switch SW 1   m+1 . This current Ia is accumulated as power consumption of the display panel. At the moment when the stored charge is cancelled (discharged) completely, the voltage between the data electrodes becomes zero volts.  
           [0015]    [Step  3 ] Following the current Ia, new current Ib flows for charging the capacitance between the data electrodes to a polarity opposite to the previous polarity. This current Ib is also supplied by the power source and is accumulated as power consumption. The current Ia is equal to the current Ib in the principle.  
           [0016]    As explained above, the conventional driving method consumes power for discharging and charging the capacitance between the data electrodes. Furthermore, there is a method for reducing the power consumption, in which a reset period is provided so that all the switches SW 2   m  and SW 2   m+1  of the current sink side are turned on. When the switches SW 2   m  and SW 2   m+1  are turned on, the data electrodes are connected via the ground side power source line, so that the stored charge is discharged. However, there are two problems in this method. One of the problems is that since a period for turning off all the switches SW 1   m , SW 1   m+1 , SW 2   m  and SW 2   m+1  in the current supplying side and the current sink side is required in order to prevent the short circuit of the power source after the reset period, the row selection period Ty is elongated due to the period, resulting in drop of the display speed. The other problem is that the potential of the data electrodes A m  and A m+1  are switched every row selection period Ty even if the display data D m  and D m+1  are constant as in the case where a line in the column direction is drawn, thereby power is consumed for charging and discharging the capacitance between the data electrodes.  
           [0017]    An object of the present invention is to reduce undesired power consumption due to the capacitance between the data electrodes.  
         SUMMARY OF THE INVENTION  
         [0018]    In the display panel to which the present invention is applied, during the period satisfying setting conditions in addressing, one of neighboring data electrodes is connected to a power source terminal, and the data electrodes are connected to each other by a short circuit of a current path including a diode provided between the other data electrode and the power source terminal and a power source line, so that charge stored in capacitance between the data electrodes is discharged.  
           [0019]    The principle of the present invention is shown in FIGS. 1 and 2. For the data electrode A m  of the m-th column that is any noted column, backward current paths P 1  and P 2  are formed in parallel with each of switches SW 1   m  and SW 2   m  controlling the potential in binary manner. The backward current paths P 1  and P 2  are obtained by connecting diodes, or using switching elements having parasitic diodes as the switches SW 1   m  and SW 2   m . The backward means the direction in which the current supply terminal side (high potential side) of the power source is a cathode and the current sink terminal side (low potential side) is an anode. In the same way, for the data electrode A m+1  of the (m+1)th column too, a switching circuit having backward current paths P 1  and P 2  is provided.  
           [0020]    In the addressing to which the present invention is applied, in synchronization with the row selection the data electrode A m  is switched from the bias potential (Va) to the ground potential ( 0 ), and oppositely the data electrode A m+1  is switched from the ground potential ( 0 ) to the bias potential (Va). This switching control has a first process called “L reset” and a second process called “H reset”.  
           [0021]    The L reset includes a step of discharging the capacitance between the data electrodes using the backward current path P 2  of the current sink terminal side (ground side) as shown in FIG. 1.  
           [0022]    [Step  1 ] At the tie point just before the end of the row selection period Ty, the switches SW 1   m  and SW 2   m  of the m-th column and the switches SW 1   m+1  and SW 2   m+1  of the (m+1)th column are off (high impedance state). The capacitance between the data electrodes is charged in the manner that the m-th column side is the positive polarity (+), and the (m+1)th column side is the negative polarity (−).  
           [0023]    [Step  2 ] When only the switch SW 2   m  is turned on, the potential of the data electrode A m+1  drops to −Va. As a result, current Ia flows from the ground line to the data electrode A m+1  via the backward current path P 2  that is parallel with the switch SW 2   m+1 . At the same time, the current Ia flows from the data electrode A m  to the ground line via the switch SW 2   m . Namely, the charge between the data electrodes is discharged by a closed loop including the ground line, and power source does not supply current.  
           [0024]    [Step  3 ] The current Ia flows until the data electrode A m+1  becomes the ground potential ( 0 ).  
           [0025]    [Step  4 ] When the switch SW 1   m+1  is turned on while the switch SW 2   m  is turned off, current Ib charging the capacitance flows from the current supply line to the data electrode A m+1  until the potential of the data electrode A m+1  rises from the ground potential to the bias potential (Va).  
           [0026]    In the L reset, though the current Ia and the current Ib flow in the same way as the conventional method, the current Ia related to the discharge of the capacitance does not depend on the current supply from the power source. Therefore, power consumption related to the capacitance is a half of the conventional method.  
           [0027]    H reset includes a step of discharging the capacitance between the data electrodes using the backward current path P 1  of the current supply terminal side as shown in FIG. 2.  
           [0028]    [Step  1 ] The switches SW 1   m , SW 2   m , SW 1   m+1  and SW 2   m+1  are off (high impedance state). The capacitance between the data electrodes is charged in the manner that the m-th column side is positive (+), and the (m+1)th column side is negative (−).  
           [0029]    [Step  2 ] When only the switch SW 1   m+1  is turned on, the potential of the data electrode A m  rises from Va to Va. As a result, the current Ia flows from the data electrode Am to the current supply line passing through the backward current path P 1  that is parallel with the switch SW 1   m . At the same time, the current Ia flows from the current supply line to the data electrode A m+1  via the switch SW 2   m . Namely, the charge between the data electrodes is discharged by a closed loop including the current supply line, and power source does not supply current.  
           [0030]    [Step  3 ] The current Ia flows until the data electrode A m+1  becomes the bias potential (Va).  
           [0031]    [Step  4 ] When the switch SW 2   m  is turned on while the switch SW 1   m+1  is turned on, the current Ib charging the capacitance between the data electrodes flows until the potential of the data electrode A m  drops to ground potential.  
           [0032]    In the H reset, though the current Ia and the current Ib flow in the same way as the conventional method, the current Ia relating to the discharge of the capacitance does not depend on the current supply from the power source. Therefore, power consumption relating to the capacitance is a half of the conventional method.  
           [0033]    The above-mentioned L reset and H reset are effective in the case where the switching of the display data in the neighboring data electrodes are opposite to each other as explained above. However, it is unnecessary for controlling the switches SW 1   m , SW 2   m , SW 1   m+1  and SW 2   m+1  to decide whether the display data are different between the n-th row and the (n+1)th row in each column, or whether the display data are different between the neighboring columns. The L reset and the H reset are realized by shifting the control timing between the switch SW 1  and the switch SW 2  for all columns, or by shifting the control timing of the switches SW 1  and SW 2  between the odd column and the even column. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]    [0034]FIG. 1 is a diagram showing the principle of the present invention.  
         [0035]    [0035]FIG. 2 is a diagram showing the principle of the present invention.  
         [0036]    [0036]FIG. 3 is a block diagram of a main portion of a display device according to a first embodiment.  
         [0037]    [0037]FIG. 4 is a functional block diagram of a driver according to the first embodiment.  
         [0038]    [0038]FIG. 5 is a schematic circuit diagram of the driver according to the first embodiment.  
         [0039]    [0039]FIG. 6 is an equivalent circuit diagram of an FET.  
         [0040]    [0040]FIG. 7 is a time chart of data electrode control according to the first embodiment.  
         [0041]    [0041]FIG. 8 is a time chart of the data electrode control according to the first embodiment.  
         [0042]    [0042]FIGS. 9A to  9 D are diagrams each showing an example of a delay circuit.  
         [0043]    [0043]FIG. 10 is a schematic circuit diagram of the driver according to a variation of the first embodiment.  
         [0044]    [0044]FIG. 11 is a block diagram of a main portion of a display device according to a second embodiment.  
         [0045]    [0045]FIG. 12 is a time chart of the data electrode control according to the second embodiment.  
         [0046]    [0046]FIG. 13 is a block diagram of a main portion of a display device according to a third embodiment.  
         [0047]    [0047]FIG. 14 is a block diagram of a main portion of a display device according to a fourth embodiment.  
         [0048]    [0048]FIG. 15 is a block diagram of a main portion of a display device according to a fifth embodiment.  
         [0049]    [0049]FIG. 16 is a schematic diagram of an electrode matrix.  
         [0050]    [0050]FIGS. 17A to  17 D are diagrams each showing an example of a display element.  
         [0051]    [0051]FIG. 18 is a time chart showing a scheme of line sequential addressing.  
         [0052]    [0052]FIG. 19 is a diagram showing an example of a display pattern.  
         [0053]    [0053]FIG. 20 is a time chart of data electrode control in the conventional driving method.  
         [0054]    [0054]FIG. 21 is a diagram showing a conventional problem. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0055]    As shown in FIG. 3, a display device  1  comprises a display panel  11  having a screen including M×N display elements and a drive unit  21  for controlling potential of scan electrodes S 1 -S N  and data electrodes A 1 -A M . The drive unit  21  includes a controller  31 , a power source circuit  41 , a driver  51  of the scan electrodes S 1 -S N  and a driver  61  of the data electrodes A 1 -A M . The driver  61  includes a plurality of integrated circuit chips  71   1 - 71   k  having the same structure being charged in controlling 256 data electrodes A 1 -A M , for example. The controller  31  transfers display data D 1 -D M  of M columns selected in each row selection period Ty of the addressing to the driver  61  serially and gives control signals LAT, SUS and TSC that will be explained later to the driver  61 .  
         [0056]    As shown in FIG. 4, in the driver  61 , a set of the integrated circuit chips  71   1 - 71   k  constitute four functional blocks including a shift register  101 , a latch circuit  111 , an output control circuit  121  and an output circuit  131 . The shift register  101  inputs display data D 1 -D M  serially and outputs the display data D 1 -D M  in parallel. The output control circuit  121  generates switching signals corresponding to combinations of the display data D 1 -DM latched in accordance with the signal LAT and control signals SUS, TSC and TSC′. The control signal SUS is a low-active signal for separating all data electrodes A 1 -A M  as a single unit from the high potential side terminal of the power source and is non-active continuously in the addressing. The timing signal TSC repeats on and off at the row selection period in the addressing, so as to prevent the power source from a short circuit. The timing signal TSC′ is a control signal unique to the present invention and is a timing signal TSC that passed through the delay circuit  81 . The output circuit  131  changes the connection state of the data electrodes A 1 -A M  with the power source circuit  41  in accordance with the switching signal from the output control circuit  121 .  
         [0057]    As shown in FIG. 5, the above-mentioned output control circuit  121  is a set of logic circuits  201 , each of which is provided for each of the data electrodes A 1 -A M . In addition, the output circuit  131  is also a set of switching circuits  301 , each of which is provided for each of the data electrodes A 1 -A M .  
         [0058]    The logic circuit  201 , which includes a plurality of gate circuits  211 - 216 , outputs switching signals UP and DOWN having logical levels indicated by a truth table in FIG. 5. The switching circuit  301  comprises a pair of field effect transistors (hereinafter referred to as transistors) Q 1  and Q 2  connected serially as a switching element between the power source terminals, and protection diodes D 1  and D 2  connected between the source and the drain of the transistors Q 1  and Q 2  in the opposite direction. The transistor Q 1  of the current supply terminal side of the power source is controlled by the switching signal UP, while the transistor Q 2  of the current sink terminal side is controlled by the switching signal DOWN.  
         [0059]    As shown in FIG. 6, in the FET (field effect transistor), a backward current path, which includes a parasitic diode do and a parasitic resister r 0 , is formed in parallel with the closed circuit including the switch SW and an inner resister R 0 . Therefore, even if the diodes D 1  and D 2  are omitted in the switching circuit  301 , the parasitic diode d 0  can be used for realizing the L reset and the H reset. However, characteristics of the parasitic diode do may vary and can be defective, so it is desirable to provide the diodes D 1  and D 2  adding to the parasitic diode d 0 .  
         [0060]    As shown in FIG. 7, in a first embodiment, the timing signal TSC is delayed so that the on and off timings of the switching signal UP are shifted from that of the switching signal DOWN for the row selection period Ty. In other words, the switching signal DOWN corresponds to the timing signal TSC, while the switching signal UP corresponds to the timing signal TSC′ that is delayed from the timing signal TSC by the time t. By this timing setting, only the switching signal DOWN is turned on at the boundary of the row selection and the L reset is realized in the case where the change of the display data D m  and D m+1  given to the neighboring data electrodes A m  and A m+1  are opposite to each other as shown in FIG. 8. The time t (the delay time of the delay circuit  81 ) is selected in accordance with the time constant of the discharge current path connecting the neighboring data electrodes to each other in the L reset, so as to be longer than the time necessary for discharging the charge stored in the capacitance between the neighboring data electrodes.  
         [0061]    In the delay by an RC circuit shown in FIG. 9A and an LC circuit shown in FIG. 9B, the signal is delayed by the time constant determined by the circuit constant. It is possible to delay the signal by the time corresponding to the sum of the delay time of the buffer circuits that are connected in series. In the delay by the shift register, the delay time can be adjusted by setting the frequency of the clock given to a flip-flop.  
         [0062]    As shown in FIG. 10, the L reset can be also realized by providing a delay circuit  81   b  for each of the data electrodes A 1 -A M  instead of delaying the timing signal TSC. The switching signal DOWN is given directly to the transistor Q 2  of the switching circuit  301  from the logic circuit  201   b  generating the signal corresponding to the combination of the timing signal TSC and the display data D m , while the switching signal UP is given to the transistor Q 1  via the delay circuit  81   b.    
         [0063]    [0063]FIG. 11 shows only the elements related to the data electrode and control thereof.  
         [0064]    In a second embodiment, the timing signal TSC is delayed so that the on and off timings of the switching signals UP and DOWN are different between an odd column and an even column.  
         [0065]    The display device  2  comprises a display panel  12  and a drive unit  22 . The drive unit  22  includes a controller  32 , a power source circuit  42 , a driver  62 A for odd column data electrodes, a driver  62 B for even column data electrodes and a delay circuit  82 . The driver  62 A comprises a plurality of integrated circuit chips  72   1 - 72   k , while the driver  62 B comprises a plurality of integrated circuit chips  72   k+1 - 72   2k . The structure in which the drivers of the data electrode are disposed at both sides in the column direction is suitable for the case where the column pitch is small. The controller  32  transfers the display data D odd  of odd columns to the driver  62 A serially and transfers the display data D even  of even columns to the driver  62 B serially every row selection period Ty in the addressing. The control signals LAT and SUS are given to the drivers  62 A and  62 B commonly. The timing signal TSC is given only to the driver  62 A, while the signal TSC′, which is delayed from the timing signal TSC, is given to the driver  62 B.  
         [0066]    By this circuit structure, the L reset in which only the switching signal DOWN is turned on at the boundary of the row selections or the H reset in which only the switching signal UP is turned on can be realized when the change of the display data D m  and D m+1  are opposite between the neighboring data electrodes A m  and A m+1  as shown in FIG. 12.  
         [0067]    According to the first embodiment and the second embodiment mentioned above, the integrated circuit chips, which were used conventionally, can be used for constituting the driver. In addition, the delay time of the signal can be adjusted, so as to support various display panels having different capacitance between the data electrodes. Therefore, the drive unit can be used for various display panels.  
         [0068]    As shown in FIG. 13, in a third embodiment, display data of an even column are delayed from that of an odd column, so that the on and off timings of the switching signals UP and DOWN are different between the odd column and the even column.  
         [0069]    The display device  3  includes a display panel  13 , a controller  33  and a driver  63  being in charge of controlling all data electrodes A 1 -A M . The driver  63  comprises a shift register  103 , a latch circuit  113 , an output control circuit  123  and an output circuit  143 . The output circuit  143  is a set of circuits that are similar to the switching circuit  301  shown in FIG. 10, while the output control circuit  123  is a set of circuits that are similar to the logic circuit  201   b  shown in FIG. 10. In the display device  3 , the latch circuit  113  is structured to latch by one step for odd columns and by two steps for even columns. By this structure, the second step of latch is delayed, so that the on and off timings of the switching signals UP and DOWN are shifted for realizing the L reset and the H reset. Furthermore, it is possible to structure the on and off control of the delay can be performed, so that the switching control related to the L reset and the H reset is performed only for a specific display pattern.  
         [0070]    As shown in FIG. 14, in a fourth embodiment, the control signal LAT is delayed so that the on and off timings of the switching signals UP and DOWN are different between an odd column and an even column.  
         [0071]    The display device  4  comprises a display panel  14  and a drive unit  24 . The drive unit  24  includes a controller  34 , a power source circuit  44 , a driver  64 A of data electrodes of odd columns, a driver  64 B of data electrodes of even columns and a delay circuit  84 . The driver  64 A comprises a plurality of integrated circuit chips  74   1 - 74   k , while the driver  64 B comprises a plurality of integrated circuit chips  74   k+1 - 74   2k . The controller  34  transfers display data D odd  of odd columns to the driver  64 A serially and transfers display data D even  of even columns to the driver  64 B serially every row selection period Ty in addressing. The control signals SUS and TSC to the drivers  64 A and  64 B commonly. The control signal LAT is given only to the driver  64 A, while the signal TSC′ that is delayed from the control signal LAT is given to the driver  64 B.  
         [0072]    As shown in FIG. 15, in a fifth embodiment, a driver having delay means is used for delaying display data of an odd column from display data of an even column, so that the on and off timings of the switching signals UP and DOWN are different between the odd column and the even column.  
         [0073]    The display device  5  comprises a display panel  15  and a drive unit  25 . The drive unit  25  includes a controller  35 , a power source circuit  45 , a driver  65 A of data electrodes of odd columns and a driver  65 B of data electrodes of even columns. The controller  35  transfers the display data D odd  of the odd columns to the driver  65 A serially and transfers the display data D even  of the even columns to the driver  65 B serially every row selection period Ty in the addressing. The control signals LAT, SUS and TSC are given to the drivers  65 A and  65 B commonly. The control signal LAT is given only to the driver  64 A, while a signal TSC′ delayed from the control signal LAT is given to the driver  64 B.  
         [0074]    The driver  65 A includes a two-step latch circuit  115 A for latching display data D odd  of odd columns outputted by a shift register (not shown) in parallel. The driver  65 B includes a one-step latch circuit  115 B for latching display data D even  of even columns outputted by a shift register (not shown) in parallel. Since the latch circuit  115 A is different from the latch circuit  115 B about the step number, the on and off timings of the switching signals UP and DOWN are different between the odd column and the even column. Each of the drivers  65 A and  65 B comprises a plurality of integrated circuit chips.  
         [0075]    According to the fifth embodiment, an integrated circuit chip having delay function for constituting the driver  65 A can be used as mixed with the conventional integrated circuit chip having no delay function for constituting the driver  65 B, so that the stocked conventional components are also used for realizing the present invention without waste.  
         [0076]    Industrial Availability  
         [0077]    As explained above, undesired power consumption due to capacitance between data electrodes in a display panel can be reduced by applying the present invention.

Technology Classification (CPC): 6