Patent Abstract:
The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device.

Full Description:
[0001]    This application claims priority to U.S. provisional Application Ser. No. 61/751,381, filed Jan. 11, 2013, which is herein incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to an electronic device package structure, and more particularly, to an electronic component package structure isolating moisture and a method for manufacturing the same. 
         [0004]    2. Description of Related Art 
         [0005]    In the manufacturing process of electronic components, the electronic components require a packaging operation for use in various applications such as computers, mobiles or digital camera. Therefore, the reliability of the packaging of the electronic components directly affects the performance of electronic devices. 
         [0006]      FIG. 1A  is a schematic cross-sectional view of a general electronic device package structure  100   a . In  FIG. 1A , an electronic chip  110   a  is positioned on a substrate  120   a , and electrically connected to a bonding pad  130   a . The bonding pad  130   a  is sandwiched between the electronic chip  110   a  and the substrate  120   a . A first passivation layer  140   a  is sandwiched between the bonding pad  130   a  and the substrate  120   a . A conductive layer  150   a  is formed on the electronic chip  110   a , and electrically connected to the bonding pad  130   a  to form a T-contact. In which, the conductive layer  150   a  has a first side end  151   a  and a second side end  152   a  opposite to the first side end  151   a , and the bottom surface of the second side end  152   a  contacts the first passivation layer  140   a . Then, a second passivation layer  160   a  covers the conductive layer  150   a . The first side end  151   a  is exposed, and the second side end  152   a  is exposed at a sidewall of the general electronic device package structure  100   a . A solder ball  170   a  is formed on the first side end  151   a  of the conductive layer  150   a.    
         [0007]    In the general electronic device package structure, the second passivation layer only covers the conductive layer, but the second side end of the conductive layer is exposed at the sidewall of the general electronic device package structure. The moisture from the surrounding may enter into the electronic device package structure along the second side end of the conductive layer, causing the degradation of the T-contact, or even decreasing the performance of the general electronic device. Therefore, there is a need for an improved electronic device package structure and a method for manufacturing thereof to prevent the moisture of the surrounding entering into the improved electronic device package structure, so as to enhance the tolerance and reliability of the improved electronic device. 
       SUMMARY 
       [0008]    For solving the aforementioned issues, one embodiment of the present disclosure is to provide an electronic device package structure isolating moisture. The electronic device package structure includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer and a solder ball. 
         [0009]    The electronic chip is positioned on the substrate. The bonding pad is sandwiched between the substrate and the electronic chip and electrically connected to the electronic chip. The first passivation layer is sandwiched between the substrate and the bonding pad. The conductive layer is positioned on a sidewall of the electronic chip and electrically connected to the bonding pad, and has a first side end and a second side end opposite to the first side end. The bottom surface of the second side end contacts the first passivation layer. The second passivation layer is positioned on the conductive layer. The first side end of the conductive layer is exposed, and the second side end of the conductive layer is covered. The second passivation layer simultaneously contacts the top surface and sidewall of the conductive layer, and completely covers the second side end of the conductive layer with the first passivation layer. The solder ball is positioned on the exposed first side end of the conductive layer. 
         [0010]    Another embodiment of the present disclosure is to provide a method for manufacturing an electronic device package structure. The method includes several operations. A semiconductor wafer is provided, and has several electronic chips thereon. A bonding pad is formed under and electrically connected to each of the electronic chips. A first passivation layer is formed under the bonding pad. A conductive layer is formed on a sidewall of each of the electronic chips, and electrically connected to the bonding pad. The conductive layer has a first side end and a second side end. The bottom surface of the second side end of the conductive layer contacts the first passivation layer. The conductive layer is disconnected from a conductive layer on a sidewall of the adjacent electronic chip. A second passivation layer is formed on the conductive layer. The first side end of the conductive layer is exposed, and the second side end of the conductive layer is covered. The second passivation layer simultaneously contacts the top surface and sidewall of the conductive layer, and completely covers the second side end of the conductive layer with the first passivation layer. A solder ball is formed on the first side end of the conductive layer. A disconnection area between the conductive layers of the adjacent electronic chips is diced to separate the electronic chips, so as to provide the electronic device package structure. 
         [0011]    In the electronic device package structure, the second passivation layer simultaneously contacts the top surface and sidewall of the conductive layer, and completely covers the second side end of the conductive layer with the first passivation layer. The electronic device package structure may prevent the outside moisture entering into the electronic device package structure and reduce the degradation of the electronic device, so as to enhance the tolerance and reliability of the electronic device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0013]      FIG. 1A  is a schematic cross-sectional view of a general electronic device package structure  100   a;    
           [0014]      FIG. 1B  is a schematic cross-sectional view of an electronic device package structure  100   b  according to one embodiment of the present disclosure; 
           [0015]      FIG. 2A  is a sub-pattern  200   a  of a general mask for manufacturing a general conductive layer; 
           [0016]      FIG. 2B  is a sub-pattern  200   b  of a mask for manufacturing a conductive layer according to one embodiment of the present disclosure; 
           [0017]      FIG. 2C  is a sub-pattern  200   c  of a mask for manufacturing a conductive layer according to one embodiment of the present disclosure; 
           [0018]      FIGS. 3A-3I  are schematic cross-sectional views at various stages of fabricating an electronic device package structure according to one embodiment of the present disclosure; and 
           [0019]      FIGS. 4A-4E  are schematic cross-sectional views at various stages of fabricating an electronic device package structure according to one embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    The embodiments of the transparent conductive structure and a method for manufacturing the same of the present disclosure are discussed in detail below, but not limited the scope of the present disclosure. The same symbols or numbers are used to the same or similar portion in the drawings or the description. And the applications of the present disclosure are not limited by the following embodiments and examples which the person in the art can apply in the related field. 
         [0021]    The singular forms “a,” “an” and “the” used herein include plural referents unless the context clearly dictates otherwise. Therefore, reference to, for example, a metal layer includes embodiments having two or more such metal layers, unless the context clearly indicates otherwise. Reference throughout this specification to “one embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, the figures are intended; rather, these figures are intended for illustration. 
         [0022]      FIG. 1B  is a schematic cross-sectional view of an electronic device package structure  100   b  according to one embodiment of the present disclosure. In  FIG. 1B , an electronic chip  110   b  is positioned on a substrate  120   b , and electrically connected to a bonding pad  130   b . The bonding pad  130   b  is sandwiched between the electronic chip  110   b  and the substrate  120   b . A first passivation layer  140   b  is sandwiched between the bonding pad  130   b  and the substrate  120   b . A conductive layer  150   b  is formed on the electronic chip  110   b , and electrically connected to the bonding pad  130   b  to form a T-contact. In which, the conductive layer  150   b  has a first side end  151   b  and a second side end  152   b  opposite to the first side end  151   b , and the bottom surface of the second side end  152   b  contacts the first passivation layer  140   b . Then, a second passivation layer  160   b  covers the conductive layer  150   b . The first side end  151   b  of the conductive layer  150   b  is exposed, and the second side end  152   b  of the conductive layer  150   b  is covered. A solder ball  170   b  is formed on the first side end  151   b  of the conductive layer  150   b . In which, the second passivation layer  160   b  simultaneously contacts the top surface and sidewall of the conductive layer  150   b , and completely covers the second side end  152   b  of the conductive layer  150  with first passivation layer  140   b.    
         [0023]    According to one embodiment of the present disclosure, the electronic chip  110   b  includes an integrated circuit device, a photoelectric device, a microelectromechanical (MEM) device, a surface acoustic wave (SAW) device and a combination thereof. 
         [0024]    According to one embodiment of the present disclosure, the first passivation layer  140   b  includes epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. 
         [0025]    According to one embodiment of the present disclosure, the conductive layer  150   b  includes copper (Cu), aluminum (Al), nickel (Ni), gold (Au) or a combination thereof. 
         [0026]    According to one embodiment of the present disclosure, the second passivation layer  160   b  includes epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. 
         [0027]    In  FIG. 1B , the electronic device package structure  100   b  further includes a barrier layer  180  sandwiched between the substrate  120   b  and the electronic chip  110   b . According to one embodiment of the present disclosure, the bonding pad  130   b  and the barrier layer  180  are on the same surface. According to one embodiment of the present disclosure, the barrier layer  180  includes epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. 
         [0028]    In  FIG. 1B , the electronic device package structure  100   b  further includes an adhesive layer  190  sandwiched between the conductive layer  150   b  and the electronic chip  110   b . According to one embodiment of the present disclosure, the adhesive layer  190  includes epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. 
         [0029]      FIG. 2A  is a sub-pattern  200   a  of a general mask for manufacturing a general conductive layer. In  FIG. 2A , the sub-pattern  200   a  of the general mask has a plurality of light transmissive areas (white portion) and at least one shading area (oblique portion), and a sub-pattern  210   a  and a sub-pattern  220   a  are adjacent sub-patterns. In which, one of the light transmissive areas of the sub-pattern  210   a  connects one of the light transmissive areas of the sub-pattern  220   a.    
         [0030]      FIG. 2B  is a sub-pattern  200   b  of a mask for manufacturing a conductive layer according to one embodiment of the present disclosure. In  FIG. 2B , the sub-pattern  200   b  of the mask has a plurality of light transmissive areas (white portion) and at least one shading area (oblique portion), and a sub-pattern  210   b  and a sub-pattern  220   b  are adjacent sub-patterns. In which, the sub-pattern  210   b  and the sub-pattern  220   b  have a separating channel  230  therebetween. The separating channel  230  is part of the shading area, so as to separate the light transmissive areas of the sub-pattern  210   b  and the light transmissive areas of the sub-pattern  220   b.    
         [0031]      FIG. 2C  is a sub-pattern  200   c  of a mask for manufacturing a conductive layer according to one embodiment of the present disclosure. In  FIG. 2C , the sub-pattern  200   c  of the mask has a plurality of shading areas (oblique portion) and at least one light transmissive area (white portion), and a sub-pattern  210   c  and a sub-pattern  220   c  are adjacent sub-patterns. In which, the sub-pattern  210   c  and the sub-pattern  220   c  have a separating channel  240  therebetween. The separating channel  240  is part of the light transmissive area, so as to separate the shading areas of the sub-pattern  210   c  and the shading areas of the sub-pattern  220   c.    
         [0032]      FIGS. 3A-3I  are schematic cross-sectional views at various stages of fabricating an electronic device package structure according to one embodiment of the present disclosure. In  FIG. 3A , electronic chips  310  are positioned on a substrate  320 , and electrically connected to a bonding pad  330 , wherein the bonding pad  330  is sandwiched between the electronic chips  310  and the substrate  320 . A first passivation layer  340  is sandwiched between the bonding pad  330  and the substrate  320 . A conductive layer  350  is formed on the electronic chip  310 , and electrically connected to the bonding pad  330 . In which, the bottom surface of the conductive layer  350  contracts the first passivation layer  340 . In  FIG. 3A , a trench  360  is formed to separate an electronic device package substrate  300   a  and an adjacent electronic device package substrate  300   b.    
         [0033]    According to one embodiment of the present disclosure, the method further includes forming a barrier layer sandwiched between the substrate and the electronic chips. According to one embodiment of the present disclosure, the method further includes forming an adhesive layer sandwiched between the electronic chips and the conductive layer. 
         [0034]    In  FIG. 3B , a photo-resist layer  370   a  is formed on the conductive layer  350 . Then, a developing process is performed by applying the mask having the sub-pattern as shown in  FIG. 2B  or  2 C, to form a photo-resist layer  370   b  having the sub-pattern as the mask, as shown in  FIG. 3C . According to one embodiment of the present disclosure, the photo-resist layer  370   b  is formed by applying a negative photo-resist agent and a clear mask, wherein the clear mask has the sub-pattern as shown in  FIG. 2B . According to one embodiment of the present disclosure, the photo-resist layer  370   b  is formed by applying a positive photo-resist agent and a dark mask, wherein the dark mask has the sub-pattern as shown in  FIG. 2C . 
         [0035]    In  FIG. 3D , a photo-resist layer  370   b  is removed to form a photo-resist layer  370   c  having a recess in the trench  360 , so that part of the conductive layer  350  is exposed. It is noted that, the recess of the photo-resist layer  370   c  is corresponded to the separating channel  230  or  240  of the sub-pattern of the mask as shown in  FIG. 2B  or  2 C. 
         [0036]    In  FIG. 3E , the exposed conductive layer  350  is etched, so as to expose part of the first passivation layer  340  in the trench  360  to form conductive layers  350   a  and  360   b . In which, the conductive layer  350   a  has a first side end  351   a  and a second side end  352   a , and the conductive layer  350   b  has a first side end  351   b  and a second side end  352   b . The second side end  352   a  of the conductive layer  350   a  is disconnected from the second side end  352   b  of the conductive layer  350   b . However, in general methods, there is no an etching process of a conductive layer, so that the conductive layer of the general electronic device package structure is connected to a conductive layer of the adjacent electronic device package structure. 
         [0037]    In  FIG. 3F , after the photo-resist layer  370   c  (see  FIG. 3E ) is removed, the conductive layers  350   a  and  350   b  are exposed. Then, metal is deposited on the conductive layers  350   a  and  350   b  to thicken the conductive layers  350   a  and  350   b , as shown in  FIG. 3G . 
         [0038]    In  FIG. 3H , a second passivation layer  380  is formed on the conductive layers  350   a  and  350   b . First side ends  351   a  and  351   b  of the conductive layers  350   a  and  350   b  are exposed, and second side ends  352   a  and  352   b  of the conductive layers  350   a  and  350   b  are covered. In which, the second passivation layer  380  simultaneously contacts top surfaces and sidewalls of the conductive layers  350   a  and  350   b , and completely covers the second side ends  352   a  and  352   b  of the conductive layers  350   a  and  350   b  with the first passivation layer  340 . Then, a solder ball  390   a  is formed on the first side end  351   a  of the conductive layer  350   a , and a solder ball  390   b  is formed on the first side end  351   b  of the conductive layer  350   b . By dicing along the trench  360 , individual electronic device package structure  300   a  and  300   b  are provided, as shown in  FIG. 3I . 
         [0039]      FIGS. 4A-4E  are schematic cross-sectional views at various stages of fabricating an electronic device package structure according to one embodiment of the present disclosure. In  FIG. 4A , followed the structure as shown in  FIG. 3B , a developing process is performed by applying the mask having the sub-pattern as shown in  FIG. 2B  or  2 C, to form a photo-resist layer  410   a  having the sub-pattern as the mask. According to one embodiment of the present disclosure, the photo-resist layer  410   a  is formed by applying a positive photo-resist agent and a clear mask, wherein the clear mask has the sub-pattern as shown in  FIG. 2B . According to one embodiment of the present disclosure, the photo-resist layer  410   a  is formed by applying a negative photo-resist agent and a dark mask, wherein the dark mask has the sub-pattern as shown in  FIG. 2C . 
         [0040]    In  FIG. 4B , a photo-resist layer  410   a  (see  FIG. 4A ) is removed to form a photo-resist layer  410   b  having an embossment in the trench  360 , so that part of the conductive layer  350  is exposed. It is noted that, the embossment of the photo-resist layer  410   b  is corresponded to the separating channel  230  or  240  of the sub-pattern of the mask as shown in  FIG. 2B  or  2 C. 
         [0041]    In  FIG. 4C , metal is deposited on the exposed conductive layers  350  to thicken the conductive layers  350 . Then, the photo-resist layer  410   b  is removed to form the conductive layers  350  having a recess, as shown in  FIG. 4D . 
         [0042]    In  FIG. 4E , the recess of the conductive layer  350  is etched to expose part of the first passivation layer  340  in the trench  360 , so as to form the conductive layers  350   a  and  360   b . In which, the conductive layer  350   a  has a first side end  351   a  and a second side end  352   a , and the conductive layer  350   b  has a first side end  351   b  and a second side end  352   b . The second side end  352   a  of the conductive layer  350   a  is disconnected from the second side end  352   b  of the conductive layer  350   b.    
         [0043]    Then, as shown in  FIGS. 3H-3I , the second passivation layer  380 , the solder balls  390   a  and  390   b , and the dicing process along the trench  360  are sequentially formed, so as to separate into the individual electronic device package structure  300   a  and  300   b.    
         [0044]    It is noted that, the first passivation layer contacts the bottom surface of the second side end of the conductive layer, and the second passivation layer simultaneously contacts the top surface and sidewall of the conductive layer, so that the first passivation layer and the second passivation layer completely covers the second side end of the conductive layer to prevent moisture entering into the electronic device package structure. Because the degradation of the electronic device is reduced, the reliability of the electronic device may be enhanced. 
         [0045]    Although embodiments of the present disclosure and their advantages have been described in detail, they are not used to limit the present disclosure. It should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the present disclosure. Therefore, the protecting scope of the present disclosure should be defined as the following claims.

Technology Classification (CPC): 7