Patent Abstract:
A high voltage analog switch operable by a binary signal is implemented in a low voltage semiconductor process. The switch has three parallel circuit paths, with each path comprising at least three series connected transistors. Control signals are selectively applied to the control terminals of the transistors to control the switch and selectively turn on or turn off each of the three circuit paths depending on the input voltage range, so that the breakdown voltage of all of the transistors is never exceeded in any mode of operation.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit under 35 USC 119(e) of provisional patent application No. 61/237,233, which was filed on Aug. 26, 2009, and which is hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates to semiconductor circuits, and more specifically to a high voltage switch implemented in a low voltage semiconductor process. 
       BACKGROUND OF THE INVENTION 
       [0003]    Advanced integrated circuit fabrication processes, such as CMOS can produce chips with low power consumption, high logic density and high speed of operation. However, these modern processes manufacture integrated circuits that operate at low voltages, due to the lowered breakdown voltages of the transistors that are fabricated. These low voltage IC&#39;s are difficult to interface with circuits operating at higher voltage levels, unless special processes are used that can produce low voltage and high voltage devices in the same IC, but these special processes can have disadvantages such as limited performance capabilities. 
         [0004]    One particular area of technology using low voltage ICs, but required to interface to higher voltage circuits is implantable medical devices for the purpose of functional electrical stimulation (FES). Such devises stimulate nerve bundles with electrodes in close proximity to the nerve tissue. The ability to process high voltage signals using high voltage tolerant circuits such as analog switches, with integrated circuits built using low voltage advanced CMOS processes, is highly desirable. 
       SUMMARY OF THE INVENTION 
       [0005]    A high voltage analog switch operable by a binary signal is implemented in a low voltage semiconductor process. The binary signal is converted to control signals with fixed voltage levels: ground and supply voltages Vdd and 2×Vdd. An additional control voltage is used which is equal to the switch input voltage level plus an added offset voltage. The switch has three parallel circuit paths, with each path comprising at least three series connected MOSFET transistors. The control signals are selectively applied to the gates of the transistors to control the switch and selectively turn on or turn off each of the three circuit paths depending on the input voltage range, so that the breakdown voltage of any of the transistors is never exceeded in any mode of operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  shows a block diagram of a high voltage switch according to an embodiment of the present invention. 
           [0007]      FIG. 2  shows an exemplary table of relative voltage levels generated within a switch controller for the high voltage switch of  FIG. 1 . 
           [0008]      FIG. 3  shows a circuit diagram of an exemplary switch module for the high voltage switch of  FIG. 1 . 
           [0009]      FIG. 4  shows a table of on/off states for the transistors of the switch module of  FIG. 3 . 
           [0010]      FIG. 5  shows a table of gate voltages for the switched transistors of the switch module of  FIG. 3 . 
           [0011]      FIG. 6  shows a table of node voltages within the switch module of  FIG. 3 . 
           [0012]      FIG. 7  shows a circuit diagram for an alternate embodiment of the high voltage switch of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]      FIG. 1  shows a block diagram of a high voltage analog switch (HVS)  100  according to an embodiment of the present invention. An input voltage Vin is coupled to a first terminal  105  of switch  100  which is coupled to the input of switch module  110 . Terminal  115  is the output terminal of switch  100 . Input line  101  couples binary signal S to switch  100  and controls the operation of switch  100 . When S=a binary “1” or high, then switch  100  is ON and Vin is connected to Vout. When S=“0” or low, then switch  100  is OFF and Vin is disconnected from Vout. 
         [0014]    Switch module  110  is controlled by switch controller  120 , which receives binary signal S. Switch controller  110  includes voltage level controller  125 , level shifters  130  and  135  and gate voltage controller  140 . Input line  101  couples signal S to voltage level controller  120 , which generates control signals C and Cb. Cb is the logical complement of C. Control signals C and Cb are coupled to respective level shifters  130  and  135 , which generate respective control signals U and Ub. Ub is the logical complement of U. Input voltage Vin and control signals C, Cb, U and Ub are coupled to gate voltage controller  140 , which generates the gate control voltages needed to control the operation of switch module  110  by way of multiple control lines  141 . When a gate voltage follows the input voltage Vin, the voltage applied to the gate is equal to the input voltage and a small offset voltage Voffset, in which case the gate control voltage=Vin+Voffset. Switch  100  receives a first supply voltage Vdd and a second supply voltage=2×Vdd, which are not shown in  FIG. 1 . 
         [0015]    Switch  100  can be implemented in a low voltage CMOS process forming MOSFET transistors with a breakdown voltage of, for example 3.3 volts, operating with a typical first supply voltage Vdd=3.0 volts and a typical second supply voltage 2×Vdd, but with the capability of switching an input voltage Vin of approximately 6 volts (or approximately 2×Vdd) without exceeding the breakdown voltage of any of the MOSFET transistors in switch  100 . 
         [0016]    Switch  100  is a floating switch in that when switch  100  is in the off state, the input voltage Vin and the output voltage Vout can be at any voltage potential. 
         [0017]      FIG. 2  shows an exemplary table of relative voltage levels for control lines C, Cb, U and Ub within switch controller  120  for the switch of  FIG. 1 . Switch controller  120  converts binary signal S to control signals with three voltage levels: ground and supply voltages Vdd and 2×Vdd. Switch  100  is in the OFF state, if C=Gnd, Cb=Vdd, U=Vdd and Ub=2×Vdd. Switch  100  is in the ON state, if C=Vdd, Cb=Gnd, U=2×Vdd and Ub=Vdd. 
         [0018]      FIG. 3  shows a circuit diagram of an exemplary switch module  310  for the high voltage switch of  FIG. 1 . Switch module  310  includes three parallel circuit paths ( 301 ,  302  and  303 ), where each path is made of three series connected MOSFET transistors. The bulk terminal of each transistor is usually connected to the source terminal of the corresponding transistor. The breakdown voltage limit across any terminals to the bulk terminal of each individual transistor is not a concern throughout the discussion below. Circuit path  301  includes transistors M 1 , M 2  and M 3  of a first polarity controlled by respective gate control voltages: Vdd, V 1 M and Vdd and with node voltages V 1   a  and V 1   b  between the transistors. Circuit path  302  includes transistors M 4 , M 5  and M 6  of a first polarity controlled by respective gate control voltages: V 2 L, V 2 M and V 2 L and with node voltages V 2   a  and V 2   b  between the transistors. The voltage levels for V 2 L, V 2 M and V 2 L are not limited to the three voltage levels previously mentioned: Gnd, Vdd and 2×Vdd. These voltages also depend on the input voltage Vin in some modes of operation, as will be described with respect to  FIG. 5 . Circuit path  303  includes transistors M 7 , M 8  and M 9  of a second polarity controlled by respective gate control voltages: Vdd, V 3 M and Vdd and with node voltages V 3   a  and V 3   b  between the transistors. 
         [0019]    The first (M 1 , M 4 , M 7 ) and the third (M 3 , M 6 , M 9 ) transistors in each of the three circuit paths are voltage range limiting transistors, which limit the voltage across the middle transistors (M 2 , M 5 , M 8 ) and prevent the voltages across all of the transistors from exceeding their breakdown voltages. 
         [0020]      FIG. 4  shows the on/off state of each of the transistors in the three circuit paths as switched on or off by gate voltage controller  140  in accordance with the input voltage range. When switch  100  is in the ON state, the ON state resistance of the switch is assumed to be significantly lower than the load resistance connected to the output of switch  100  such that the output voltage Vout at terminal  115  can be considered to be equal to the input voltage Vin at terminal  105 . 
         [0021]    When switch  100  is in the ON state, and the input voltage is in the low range of: 0&lt;Vin&lt;Vdd−Vt, where Vt is the typical threshold voltage of a MOSFET transistor, then the first circuit path  301  transistors M 1 , M 2  and M 3  are turned on by gate voltage controller  140 . 
         [0022]    When switch  100  is in the ON state, and the input voltage is in the middle range of: Vdd−Vt&lt;Vin&lt;Vdd+Vt, then the second circuit path transistors M 4 , M 5  and M 6  are turned on by gate voltage controller  140 . Since transistors M 4 , M 5  and M 6  in the second circuit path  302  have the same polarity as transistors M 1 , M 2  and M 3  in the first circuit path  301 , transistors M 4 , M 5  and M 6  are also turned on by gate voltage controller  140 , when Vin is in the middle voltage range. 
         [0023]    When switch  100  is in the ON state, and the input voltage is in the high range of: Vdd+Vt&lt;Vin&lt;2×Vdd, then only the third circuit path  303  transistors M 7 , M 8  and M 9  are turned on by gate voltage controller  140 . 
         [0024]    When switch  100  is in the OFF state, and the input voltage is in the low range of: 0&lt;Vin&lt;Vdd−Vt, then only the first circuit path  301  transistors M 1  and M 3  are turned on by gate voltage controller  140 . 
         [0025]    When switch  100  is in the OFF state, and the input voltage is in the middle range of: Vdd−Vt&lt;Vin&lt;Vdd+Vt, then only the first circuit path transistors M 1  and M 3  are turned on by gate voltage controller  140 . 
         [0026]    When switch  100  is in the OFF state, and the input voltage is in the high range of: Vdd+Vt&lt;Vin&lt;2×Vdd, then only the third circuit path  303  transistors M 7  and M 9  are turned on by gate voltage controller  140 . Since the middle transistors (M 2 , M 5  and M 8 ) of all three paths ( 301 ,  302  and  303 ) are turned off when switch  100  is in the OFF state, there will be no current flow between the input voltage Vin at terminal  105  and the output voltage Vout at terminal  115 . 
         [0027]    The turning on and off of the various circuit paths overlap for different input voltage ranges to some extent since the transistors are not completely turned on or off as the input voltage Vin varies from one range to another range and there may still be some conduction of current within the transistors, except for transistors M 2 , M 5  and M 8  in the OFF state. Switch  100  uses three circuit paths operating at three different (but with some overlap) voltage ranges in order to provide a relatively undistorted connection in the on state between Vin and Vout across the input voltage range of Vin. 
         [0028]      FIG. 3  shows that the gate voltages connected to transistors M 1  and M 3  in the first circuit path  301  and transistors M 7  and M 9  in the third circuit path  303  in all states of operation are set to the first supply voltage Vdd. The table in  FIG. 5  shows the gate voltages applied to the other transistors (M 2 , M 4 , M 5 , M 6  and M 8 ) in switch module  310  as a function of the state of switch  100  and the range of the input voltage Vin. For transistors M 4 , M 5  and M 6  in the second circuit path  302 , when the input voltage Vin is in the middle or high range, the gate voltages of these transistors follow the input voltage, plus an offset voltage Voffset. The offset voltage Voffset is slightly greater than Vt such that the gate voltages of transistors M 4 , M 5  and M 6  are always higher than the input voltage Vin by Vt to keep transistors M 4 , M 5  and M 6  on. The gate voltages of the other transistors in the table in  FIG. 5 , are either set to Vdd or 0V, when switch  100  is in the OFF state. 
         [0029]    When switch  100  is in the OFF state and no current flow is allowed in all three paths, then the gate voltages for M 2  and M 5  are at zero volts, and the gate voltage for transistor M 8  is set to Vdd. The gate voltages for transistors M 1 , M 3 , M 4 , M 6 , M 7  and M 9  are set to Vdd for limiting the source voltages and the drain voltages of transistors M 2 , M 5  and M 8  within one Vdd. The source voltages and the drain voltages for transistors M 1 , M 3 , M 4 , M 6 , M 7  and M 9  are also limited to within one Vdd for the input voltage at terminal  105  and the output voltage at terminal  115  varying within the voltage range between 0V and 2×Vdd. 
         [0030]      FIG. 6  shows a table of node voltages for the switch module of  FIG. 3 . Based on the node voltages for different input and output voltage ranges in the ON and OFF states, it can be observed that the voltages across the different terminals of all the transistors are less than the breakdown voltage of any of the transistors in switch  100 . 
         [0031]      FIG. 7  shows a circuit diagram for an alternate embodiment of the high voltage switch  700  of the present invention. For purposes of simplifying the diagram, electronic circuits equivalent to the level shifters  130  and  135  of  FIG. 1  are not shown in  FIG. 7 . An equivalent to the gate voltage controller  140  of  FIG. 1  is part of the circuit of  FIG. 7 . Control signals C, Cb, U and Ub, discussed previously, are shown connected to switch  700  to the gates of various transistors of switch  700 . The third path  303  in  FIG. 3  is equivalent to transistors M 9 , M 10  and M 11  in  FIG. 7 . Since the first path  301  and the second path  302  in  FIG. 3  have transistors with the same polarity, some transistors in the two paths can be combined together if proper gate voltage controls are applied. Transistors M 1  and M 4  in  FIG. 3  are combined together as transistor M 5  in  FIG. 7 . Similarly, transistors M 3  and M 6  in  FIG. 3  are combined together as transistor M 8  in  FIG. 7 . Transistor M 19  in  FIG. 7  is equivalent to transistor M 2  in  FIG. 3 . Due to the specific gate voltage controller design shown in  FIG. 7 , transistors M 5  in  FIG. 3  is replaced by transistors M 6  and M 7  in  FIG. 7 . Transistors M 15  and M 16  connected in between M 6  and M 7  at node Z are used to ensure that no current flows through transistors M 6  and M 7  during the OFF state. 
         [0032]    When switch  700  is turned ON by input signal S=“1” (not shown in  FIG. 7 ), then transistors M 5 , M 19  and M 8  form a circuit path between Vin and Vout that is turned on when the input voltage Vin is in the low range: 0&lt;Vin&lt;(Vdd−Vsg 4 ) where Vsg 4  is the source-to-gate voltage of transistor M 4 . For the input voltage range Vin&lt;˜(Vdd−Vsg 4 ), PMOS transistor M 4  is in the triode region of operation such that Vx is equal to Vdd. Node Y is floating between Vdd and 0V, since M 14  (the source voltage of M 14  is equal to Vx and hence, equal to Vdd, since transistor M 13  is on) and M 18  are off. The gate voltages of this first circuit path (transistors M 5 , M 19  and M 18 ) are all at Vdd. This circuit path is similar to the first circuit path  301  as discussed with regard to  FIG. 3 . 
         [0033]    When switch  700  is turned ON and the input voltage Vin is in the middle range, ˜Vdd−Vsg 4 &lt;Vin&lt;(2×Vdd)−Vsg 4 , then transistors M 5 , M 6 , M 7  and M 8  form a circuit path between Vin and Vout, similar to the second circuit path  302  discussed with regard to  FIG. 3 . Transistor M 1  in  FIG. 7  is biased as a current source set by a proper gate bias voltage Vswb. Transistors M 1 , M 2  and M 4  form a source follower, such that the voltage at node X will follow Vin with an offset voltage such that Vx=Vin+Vsg 4 , where Vx=voltage at node X. Node Y will follow node X such that Vx=Vy, since transistors M 12 , M 13  and M 14  are conducting for this input voltage range. Therefore, transistors M 5 , M 6 , M 7  and M 8  are turned on with their gate to source voltages equal to Vsg 4 . The on resistance for this Vin range is smaller if a small (W/L) is used for transistor M 4 , as this will maximize Vsg 4 . In the upper reaches of this Vin input voltage range, the branch M 9 , M 10  and M 11  is also turned on. 
         [0034]    When switch  700  is turned ON and the input voltage Vin is in the high range 2×Vdd&gt;Vin&gt;|Vtp|+Vdd, (where Vtp is the typical threshold voltage for a PMOS transistor) then a circuit path from Vin to Vout is connected through transistors M 9 , M 10  and M 11 . This circuit path is similar to the third circuit path  303  as discussed with regard to  FIG. 3 . 
         [0035]    When switch  700  is turned OFF and the input voltage Vin is in the low range: 0&lt;Vin&lt;Vdd−Vtn, the gate voltages of transistors M 5  and M 8  are equal to Vdd (transistor M 3  is on) and hence, transistors M 5  and M 8  are turned on. No conduction path is established between transistors M 5  and M 8  since M 19  is off and nodes Y and Z are at 0V to keep transistors M 6  and M 7  off. 
         [0036]    When switch  700  is turned OFF and the input voltage Vin is in the high range: Vdd+|Vtp|&lt;Vin&lt;2×Vdd, (where Vtp is the typical threshold voltage for a PMOS transistor), transistors M 9  and M 11  are on, but transistor M 10  is turned off. Transistors M 5  and M 8  are also turned on in the middle input voltage range: Vdd−Vtn&lt;Vin&lt;2×Vdd. Transistors M 5 , M 8 , M 9  and M 11  during their periods of operation limit the voltage swings across the inner transistors M 6 , M 7 , M 10  and M 19 , which are always off when switch  700  is off. 
         [0037]    When switch  700  is in the OFF state, the gate voltages of M 9  and M 11  are at Vdd, forcing the source and drain voltages of M 10  to be between Vdd+|Vtp 9 , 11 | and 2×Vdd, even though Vin and/or Vout may vary rail-to-rail between 0V and 2×Vdd. Hence, M 9 -M 11  will not be under stress when switch  700  in the off state. 
         [0038]    In all of these various operational configurations, the voltages across the different terminals of all the transistors are less than the breakdown voltage, whether switch  700  is on or off. 
         [0039]    Although the preceding description describes various embodiments of the system, the invention is not limited to such embodiments, but rather covers all modifications, alternatives, and equivalents that fall within the spirit and scope of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.

Technology Classification (CPC): 7