Patent Abstract:
A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

Full Description:
BACKGROUND 
     The present invention relates to field effect transistor (FET) devices, and more specifically, to methods for fabricating FET devices. 
     FET devices include source, drain, and channel regions. The source and drain regions include doped ions. The source and drain regions may be doped using ion implantation methods following the formation of the source and drain regions, or may be doped during the formation of the source and drain regions. Stress liner material may be formed proximal to the channel regions. The stress liner material often enhances the carrier mobility and performance of the FET devices. 
     BRIEF SUMMARY 
     According to one embodiment of the present invention, a method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. 
     According to another embodiment of the present invention, a field effect transistor device includes a gate stack portion disposed on a substrate, a first cavity region in the substrate arranged on a first side of the gate stack portion, a second cavity region in the substrate arranged on a second side of the gate stack portion, a first epitaxially grown silicon material disposed in the first cavity region and the second cavity region, and a second epitaxially grown silicon material disposed in the first cavity region and the second cavity region, the second epitaxially grown silicon material in contact with the first epitaxially grown silicon material. 
     According to yet another embodiment of the present invention, a field effect transistor device includes a first gate stack portion disposed on a substrate, a second gate stack portion disposed on the substrate, a cavity region in the substrate arranged between the first gate stack portion and the second gate stack portion, a first stressor portion disposed in the cavity region adjacent to a channel region of the first gate stack portion, a second stressor portion disposed in the cavity region adjacent to a channel region of the second gate stack portion, and a doped material disposed in the cavity region on the substrate, the first stressor portion and the second stressor portion. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIGS. 1-7  illustrate side views of a method for forming field effect transistor (FET) devices and the resultant structure of the devices. 
         FIGS. 8-10  illustrate side views of an alternate method for forming field effect transistor devices and the resultant structure of the devices. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1-7  illustrate side view of a method for forming field effect transistor (FET) devices and the resultant structure of the devices. Referring to  FIG. 1 , gate stacks  102   a  and  102   b , referred to collectively as gate stacks (gate stack portions)  102  hereinafter, are formed on a silicon on insulator (SOI) substrate  100 . The gate stacks  102  may include, for example, a dielectric layer  104  such as a high-K layer or oxide layer and a metal layer  106  disposed on the dielectric layer  104 . A silicon capping layer  108  is disposed on the metal layer  106 . A spacer (spacer portion)  110  is patterned over the gate stacks  102  and a portion of the substrate  100 . The spacer  110  may include, for example, a nitride or oxide material. In the illustrated embodiment, the spacer  110  also includes a hardmask portion over the gate stacks  102 . 
       FIG. 2  illustrates the resultant structure following an anisotropic etching process such as, for example, reactive ion etching (RIE) that forms a trench (cavity region)  202  in the substrate  100  between the gate stacks  102   a  and  102   b . Once the trench  202  is formed, the gate stacks  102  that will become n-type (NFET) devices, for example gate stack  102   a , may be isolated by patterning a layer of nitride (not shown) over the gate stacks  102 , leaving the gate stacks  102  that will become p-type (PFET) devices exposed. 
       FIG. 3  illustrates regions  302  that may be formed by implanting ions, such as, for example, boron ions, in the substrate  100 . In the illustrated embodiment, the regions  302  facilitate isolating adjacent devices such as devices to be formed by gate stacks  102   a  and  102   b . The regions  302  are formed in the substrate  100  below the channels  202 , however, in some embodiments, the sidewalls of the channels  202  may also be implanted with ions using, for example, an angled implant process. In alternate embodiments, the regions  302  may not be formed with ion implantation. 
       FIG. 4  illustrates the resultant structure following the epitaxial growth of a silicon-containing material (epi-silicon)  402  on the exposed portions of the substrate  100 . In the illustrated embodiment, the epi-silicon  402  may include, for example, SiGe with greater than 30% (by atomic percentage) Ge content. Alternate embodiments may include between 20-50% Ge content. The epi-silicon  402  material may be undoped, low doped, or counter doped (e.g., doping an n-type region with p-type dopants or doping a p-type region with n-type dopants). In alternate exemplary embodiments, the epi-silicon material  402  may include, for example, SiC or other compound that may be used to form NFET devices. The formation of epi-silicon  402  SiC material includes multiple cycles of epitaxial SiC growth and etching to form the material  402 . The carbon (C) content in the epi-silicon SiC may range from approximately 1% to 5%. The epi-silicon SiC may be undoped, low doped (i.e., doped with phosphorous or arsenic) or counter doped. 
       FIG. 5  illustrates the resultant structure following an etching process that removes portions of the epi-silicon material  402 . The etching process may include, for example, a hydrogen chlorine (HCl) etch preformed in the epitaxy chamber, or other etching processes such as NH 4 OH or Tetramethylammonium Hydroxide (TMAH) wet etching processes. The etching process etches the epi-silicon material  402  at a faster rate than the silicon substrate  100 . The crystalline structure of the epi-silicon material  402  and the etching process results in the formation of stress regions  501  partially defined by a plane  500  arranged [1,1,1] (using Miller index notation). The stress regions  501  are adjacent to the channel regions  503  of the devices. The etching process exposes a portion of the substrate  100  in the region  502 , between the devices. 
       FIG. 6  illustrates the resultant structure following the epitaxial growth of doped silicon material  602  that forms the source regions (S) and drain regions (D) of devices  601   a  and  601   b , hereinafter devices  601 . In the illustrated embodiment, the doped silicon material  602  includes a doped SiGe material that is epitaxially grown from the exposed substrate  100  and the stress regions  501 . The dopant may include, for example boron, arsenic, or phosphorous ions. 
       FIG. 7  illustrates the resultant structure following the removal of a portion of the spacer  110  that exposes the gate stacks  102   a  and  102   b  and defines gate regions (G) of the gate stacks  102 . The portion of the spacer material  110  may be removed by, for example, a chemical mechanical polishing process, or a suitable etching process. Once the gate regions (G) have been exposed, a silicide may be formed on the exposed source, gate, and drain regions, and conductive contact material may be formed on the regions (not shown). 
     In an alternate embodiment, a similar etching process described above in  FIG. 5  may remove portions of the epi-silicon material  402  and the SOI substrate  100 . The etching process may include etchant parameters such as etchant chemicals that selectively etch both the epi-silicon material  402  and the silicon substrate  100  material.  FIG. 8  illustrates the resulting structure following the removal of portions of the epi-silicon material  402  and the SOI substrate  100  that results in the formation of undercut regions  802 . The undercut regions  802  may expose a portion of the gate stacks  102 . 
       FIG. 9  illustrates the resultant structure following the epitaxial growth of doped silicon material  602  that is similar to the process described above in  FIG. 6 . 
       FIG. 10  illustrates the resultant structure following the removal of a portion of the spacer  110  that is similar to the process described above in  FIG. 7 . 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
     The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Technology Classification (CPC): 7