Patent Abstract:
A method for inspecting an active-matrix-display-panel array substrate includes: a first step of applying a voltage V 1  to the data terminal of a transistor while the transistor conducts, bringing the transistor into a non-conductive state, applying a voltage V 1 +ΔV to the data terminal, bringing the transistor into a conductive state, and measuring charge ΔQ; a second step of applying a voltage V 0  to the data terminal when the transistor does not conduct and the data terminal voltage is V 3 , and measuring a voltage Q 1  flowing through the transistor when the transistor conducts; a third step of applying a voltage V 0 ′ to the data terminal when the transistor does not conduct and the data terminal voltage is V 4 , and measuring charge Q 2  flowing when the transistor conducts; and a fourth step of determining a capacitance of the capacitor based on ΔV, ΔQ, V 0 , V 0 ′, V 3 , V 4 , Q 1 , and Q 2 .

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method and apparatus for inspecting array substrates in active-matrix display panels. More specifically, the present invention relates to an inspection method and an inspection apparatus which are applicable to the inspection of array substrates used in active-matrix display panels, such as organic electroluminescent (EL) panels and liquid-crystal panels.  
         [0003]     2. Description of the Related Art  
         [0004]     In recent years, with the advancement of display performance, attention has been focused on flat panel displays, such as liquid crystal panels (hereinafter referred to as “LCDs”) and organic electroluminescent panels or organic light emitting diode (hereinafter referred to as “OLEDs”). In the manufacturing processes of such flat panel display substrates, a test for checking whether the array substrates are formed without any defect is performed (this test will hereinafter be referred to as “array test”). For the array test, it is important to measure the capacitances of pixel-voltage-storing capacitors (hereinafter referred to as “storage capacitors”) for storing data. Specifically, a predetermined voltage is applied to the data terminal of a thin-film transistor (TFT) array to charge the storage capacitor and the amount of charge is read and divided by the voltage value to thereby determine the capacitance of the capacitor.  
         [0005]     In the related art, it is often difficult to accurately measure only the capacitance of the storage capacitor. This is because of the parasitic capacitance of the TFT, which serves as a switching device for switching current flowing to the storage capacitor in the array substrate. In the TFT, a layer that provides a source electrode and a layer that provides a data electrode are laminated at two corresponding opposite portions of the top surface of a layer that provides a gate electrode. A space formed between the source electrode and the data electrode generates a parasitic capacitance. During the array test, when a voltage for testing is applied to the TFT data terminal coupled to the data line of the array substrate and charge, or electric charge, flowing into the storage capacitor is measured, there is a problem in that the measurement cannot be accurately performed since the parasitic capacitance in the TFT causes a measurement error.  
         [0006]     Examples of the known art for testing arrays include Japanese Unexamined Patent Application Publication No. 2004-93644. Different voltages are applied to each gate electrode in the TFT array in the array substrate twice and the capacitance and the charge stored in a storage capacitor are measured to detect a punch-through voltage abnormality in the array substrate. In the technology described in that document, however, no consideration is given to the influence of the parasitic capacitance generated between the data electrode and the source electrode in the TFT array.  
         [0007]     In any array testing, there will be no problem if the parasitic capacitance generated between the data terminal and the source terminal in the TFT, which serves as a switching device, is negligibly small compared to the capacitance of the storage capacitor. Otherwise, there is a problem in that an error occurs in the measurement of the storage capacitance and, consequently, the punch-through voltage cannot be correctly inspected.  
       SUMMARY OF THE INVENTION  
       [0008]     Accordingly, the present invention has been conceived in view of the foregoing situation, and an object of the present invention is to provide an array-substrate inspection method and an array-substrate inspection apparatus which can perform precise inspection of a storage capacitor by allowing individual measurement of parasitic capacitance generated in a switching device and the capacitance of a storage capacitor.  
         [0009]     To achieve the object described above, the present invention provides a method for inspecting an array substrate in an active-matrix display panel. The array substrate has a switching transistor having a data terminal, a source terminal, and a gate terminal, a pixel drive circuit connected to the source terminal of the transistor, and a pixel-voltage storing capacitor connected to the pixel drive circuit and the source terminal. The method includes: a first step of applying a voltage V 1  to the data terminal while the transistor is in a conductive state, bringing the transistor into a non-conductive state, applying a different voltage V 1 +ΔV to the data terminal while the transistor is in the non-conductive state, bringing the transistor into the conductive state, and measuring an amount of charge ΔQ flowing through the transistor; and a second step of applying a voltage V 0  to the data terminal when the transistor is in the non-conductive state with the voltage applied to the data terminal being a voltage V 3  different from the voltage V 0 , and a potential of the capacitor being V C ; and measuring an amount of voltage Q 1  flowing through the transistor when the transistor is brought into the conductive state. The method further includes: a third step of applying a voltage V 0 ′ to the data terminal when the transistor is in the non-conductive state with the voltage applied to the data terminal being a voltage V 4  different from the voltage V 3 , and the potential of the capacitor being the potential V C ; and measuring an amount of charge Q2 flowing through the transistor when the transistor is brought into the conductive state; and a fourth step of determining a capacitance C S  of the capacitor based on values of ΔV, ΔQ, V 0 , V 0 ′, V 3 , V 4 , Q 1 , and Q2.  
         [0010]     In the second step and the third steps, the values of the voltages V 0  and V 0 ′ may be or may not be equal to each other.  
         [0011]     Prior to either or both of the second step and the third step, the voltage applied to the data terminal may be increased, while the gate voltage of the transistor when it is in the conductive state is maintained at a constant value, to thereby bring the transistor into the non-conductive state. This can cause the potential of the transistor to have a value that is obtained by subtracting a threshold voltage V th  of the transistor from a gate voltage V G  of the transistor, that is, to have a value that satisfies V C =V G −V th .  
         [0012]     According to the present invention, in the fourth step, the capacitance C S  of the capacitor can be determined based on equation 1 below:  
               C   S     =         Δ   ⁢           ⁢     V   ⁡     (       Q   1     -     Q   2       )         +       (       V   4     -     V   3       )     ⁢   Δ   ⁢           ⁢   Q         Δ   ⁢           ⁢     V   ⁡     (       V   4     -     V   3       )                   (   1   )             
 
 where ΔV′=V 2 −V 1 . 
 
         [0013]     Further, a parasitic capacitance C ds  of the transistor or another transistor can be determined based on equation 2 below:  
               C   ds     =         Δ   ⁢           ⁢     V   ⁡     (       Q   1     -     Q   2       )             (       V   4     -     V   3       )     ⁢   Δ   ⁢           ⁢   Q       ⁢         Δ   ⁢           ⁢   V   ⁢     (       Q   1     -     Q   2       )       +       (       V   4     -     V   3       )     ⁢   Δ   ⁢           ⁢   Q         Δ   ⁢           ⁢     V   ⁡     (       V   4     -     V   3       )                     (   2   )             
 
         [0014]     As another preferred embodiment, instead of satisfying V C =V G −V th  in the second step or the third step, the method may further include a step of applying, prior to the second step, the voltage V 1  to the data terminal of the transistor when it is in the conductive state; and reducing the gate voltage to bring the transistor into the non-conductive state, while maintaining the voltage V 1  of the data terminal, to thereby set the potential of the capacitor to V 1 . The method may also include a step of applying the voltage V 2  to the data terminal of the transistor when it is the conductive state, and reducing the gate voltage to bring the transistor into the non-conductive state, while maintaining the voltage V 2  of the data terminal, to thereby set the potential of the capacitor to V 2 .  
         [0015]     The present invention further provides an apparatus for inspecting an array substrate in an active-matrix display panel. The array substrate has a switching transistor having a data terminal, a source terminal, and a gate terminal, a pixel drive circuit connected to the source terminal of the transistor, and a pixel-voltage storing capacitor connected to the pixel drive circuit and the source terminal. The apparatus includes a voltage source, a charge measuring circuit, a processing unit, and storing means. The processing unit controls: a first operation of causing the voltage source to apply a voltage V 1  to the data terminal while the transistor is in a conductive state, so as to bring the transistor into a non-conductive state, to apply a different voltage V 1 +ΔV to the data terminal while the transistor is in the non-conductive state, and to bring the transistor into the conductive state; causing the charge measuring circuit to measure an amount of charge ΔQ flowing through the transistor; and causing the storing means to store the amount of charge ΔQ; and a second operation of causing the voltage source to apply a voltage V 0  to the data terminal when the transistor is in the non-conductive state, the voltage applied to the data terminal is a voltage V 1  different from the voltage V 0 , and a potential of the capacitor is V C ; causing the charge measuring circuit to measure an amount of charge Q 1  flowing through the transistor, when the transistor is brought into the conductive state; and causing the storing means to store the amount of charge Q 1 . The processing unit further controls a third operation of causing the voltage supply to apply a voltage V 0 ′ to the data terminal when the transistor is in the non-conductive state with the voltage applied to the data terminal being a voltage V 2  different from the voltage V 1 , and the potential of the capacitor being V C ; causing the charge measuring circuit to measure an amount of charge Q2 flowing through the transistor, when the transistor is brought into the conductive state; and of causing the storing means to store the amount of charge Q 2 . The processing unit performs a fourth operation of determining a capacitance of the capacitor based on values of ΔV, V 0 , V 0 ′, V 3 , and V 4  and values of ΔQ, Q 1 , and Q 2  stored by the storing means.  
         [0016]     Thus, according to the present invention, since the capacitance of the storage capacitor and parasitic capacitance generated in a TFT which serves as a switching device can be measured as individual values, the capacitance of the storage capacitor in the array circuit can be accurately measured. The method and the apparatus of the present invention allow measurement with an accuracy of 1 fF or less. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIGS. 1A  to  1 C are block diagrams each illustrating a pixel circuit to be tested in the present invention;  
         [0018]      FIG. 2  is a circuit diagram schematically showing a pixel circuit to be tested in the present invention;  
         [0019]      FIG. 3  is a flow chart showing a measurement procedure according to the present invention;  
         [0020]      FIG. 4  is a flow chart of a first step;  
         [0021]      FIGS. 5A  to  5 C are diagrams showing a state transition of the circuit configuration in the first step;  
         [0022]      FIG. 6  is a flow chart of a second step;  
         [0023]      FIGS. 7A  to  7 D are diagrams showing a state transition of the circuit configuration in the second step;  
         [0024]      FIG. 8  is a flow chart of an alternative example of the second step;  
         [0025]      FIG. 9  is a block diagram of a test circuit suitable for carrying out the present invention;  
         [0026]      FIG. 10  is a block diagram showing an example of the circuit of a horizontal shift register shown in  FIG. 9 ; and  
         [0027]      FIG. 11  is a block diagram showing an example of the circuit of a vertical shift register shown in  FIG. 9 .  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]     An inspection apparatus and an inspection method for an array circuit according to embodiments of the present invention will be described below with reference to the accompanying drawings. A preferred embodiment for carrying out the present invention will be described with reference to FIGS.  1  to  11 .  
         [0029]      FIGS. 1A  to  1 C each show one pixel  158 , which is an example of the circuit configuration of an LCD or an OLED to be measured in the present invention.  FIG. 1A  shows a circuit configuration common to an LCD and an OLED. Typically, a pixel drive circuit  186 , which includes a transparent electrode made of ITO (indium tin oxide), is connected to a source line coupled to a source terminal (S) of a switching TFT  182  and is switched by the TFT  182 . An input is connected to a data terminal (D) of the TFT  182  via a data line Dm ( 154 ) and a wiring line  164  (hereinafter referred to as a “data line” for the TFT  182 ). A capacitor  184  (capacitance C S ) for storing a voltage is connected between a ground line  188  and a wiring line that couples the pixel drive circuit  186  and the TFT  182 . A gate voltage is supplied to a gate terminal (G) of the TFT  182  and is connected to a gate line Gn ( 152 ) via a wiring line  162  (hereinafter referred to as a “gate line” for the TFT  182 ). Here, m and n are positive integers indicating the column and row numbers in the array.  FIG. 1B  shows the circuit configuration of an LCD in which the pixel drive circuit  186  includes an ITO electrode  190 .  FIG. 1C  shows the circuit configuration of an OLED in which the pixel drive circuit  186  includes a wiring line  196  for supplying current, a TFT  192 , and an ITO electrode  194 . As shown in  FIG. 2 , the TFT  182  has parasitic capacitance C ds . When the TFT  182  is in a conductive state, that is, an ON state, there is resistance R ON  between the data terminal and the source terminal.  
         [0030]     Next, a method for measuring the capacitance of the voltage-storing capacitor  184  in each pixel in the present invention will be described with reference to FIGS.  2  to  7 . FIG.  3  is a flow chart showing an embodiment of the entire measuring method of the present invention. First, a first step, including a first voltage-varying process (S 1 ) and a first charge-measuring process (S 2 ), is performed on a pixel array of interest.  FIG. 4  is a flow chart showing the first step and  FIGS. 5A  to  5 C are diagrams showing a state transition of the pixel circuit in the first charge-measuring process.  
         [0031]     First, a voltage V 1  is applied to the data line  154  for the transistor  182  (S 11 ). V 1  is a voltage that satisfies the expression V 1 &lt;V Gon −V th , where V th  indicates a threshold voltage for the transistor  182  and V Gon  indicates a gate voltage suitable for bringing the transistor  182  into a conductive state under a data terminal voltage typically applied in the present embodiment. Next, while the data terminal voltage is maintained at V 1 , V Gon  is applied to a gate voltage V G . As a result, the gate voltage V G  becomes greater than V 1 +V th , so that the transistor  182  in the TFT array is brought into a conductive state (S 12 ). Next, when the transistor  182  in the conductive state, this state is maintained for a predetermined period of time or more. The predetermined period of time refers to the time required until the capacitor  184  is completely charged, i.e., until a voltage across the capacitor  184  can be regarded as being equal to or being sufficiently close to the voltage V 1  at the data terminal, as shown in  FIG. 5A . Whether or not the predetermined period of time has passed can be expressed by the time required until an increase in a measurement value of a connected charge meter per unit time is determined to be “0” or sufficiently small. A time constant c in this case is determined by τ=R ON ×C S , based on the capacitance C S  of the capacitor  184  and the ON resistance R ON  of the transistor  182 . Whether or not the predetermined period of time has passed can also be determined by connecting an ammeter, instead of the charge meter, and measuring the current value.  
         [0032]     Thereafter, a gate voltage V Goff  suitable for bringing the transistor  182  into a non-conductive state, that is, an OFF state, under a voltage typically applied to the data terminal is applied to the gate voltage V G  to thereby bring the transistor  182  into the non-conductive state (S 13 ). Next, the data terminal voltage is set to V 1 +ΔV (S 14 ). The voltage ΔV, however, satisfies V 1 +ΔV&lt;V Gon −V th . When the transistor  182  is left in the non-conductive state, the voltage across the capacitor  184  becomes V C1 , which is different from the data terminal voltage V 1 +ΔV, as shown in  FIG. 5B , since the capacitor  184  is not connected to the data terminal. In this state, the voltage V C1  across the capacitor  184  can be determined by the following equation:  
               V     C   ⁢           ⁢   1       =       V   1     +         C   ds         C   ds     +     C   S         ⁢   Δ   ⁢           ⁢   V               (   3   )             
 
         [0033]     Next, the first charge-measuring process is performed (S 2 ). Specifically, the voltage V Gon  is applied to the gate terminal while the data terminal voltage is maintained at V 1 +ΔV, to thereby bring the transistor  182  into the conductive state (S 15 ). When this state is maintained for a certain period of time, as shown in  FIG. 5C , the voltage across the capacitor  184  becomes V 1 +ΔV, which is equal to the data terminal voltage, thereby reaching a steady state. At this point, the amount of charge ΔQ flowing to the capacitor  184  is expressed by:
 
Δ Q=C   S ( V   C1 −( V   1   +ΔV ))  (4)
 
 The amount charge ΔQ is measured (S 16 ). Then, the capacitance C S  is given by:  
               C   S     =         Δ   ⁢           ⁢   Q     +         Δ   ⁢           ⁢     Q   2       +     4   ⁢     C   ds     ⁢   Δ   ⁢           ⁢   Q   ⁢           ⁢   Δ   ⁢           ⁢   V             2   ⁢           ⁢   Δ   ⁢           ⁢   V               (   5   )             
 
         [0034]     A second step, including a second voltage-varying process (S 3 ) and a second charge-measuring process (S 4 ), is performed.  FIG. 6  is a flow chart showing the second step and  FIGS. 7A  to  7 D are diagrams showing a state transition of each pixel in the second voltage-varying process.  
         [0035]     First, a voltage V 2  is applied to the data terminal and the voltage V Gon  is applied to the gate terminal to bring the transistor  182  into the conductive state, and this state is maintained for a predetermined period of time or more. A voltage V C  across the capacitor  184  is initialized to the voltage V 2  (S 29 ). The voltages V 2  and V Gon  satisfy V 2 &lt;V Gon −V th . This voltage V Gon  does not necessarily have to be the same as V Gon  in the first step. The voltage V 2  and the voltage V 1  may also be equal to each other. In this case, the voltage across the capacitor  184  is V 2 , as shown in  FIG. 7A . Next, the gate voltage is reduced to V Goff  (S 30 ). Subsequently, a voltage V 3  is applied to the data terminal (S 31 ). At this point, the voltage V 3  is higher than the voltage V 2  and satisfies V 3 &gt;V Gon −V th . Next, the gate voltage V G  is increased to V Gon  (S 32 ). At this point, although the source terminal voltage increases so as to bring the transistor  182  into the conductive state, the voltage between the gate terminal and the source terminal cannot exceed the threshold voltage V th , because of V 3 &gt;V Gon −V th . Eventually, the transistor  182  does not go into the conductive state and thus remains in the non-conductive state. A voltage V C , or V C2 , across the capacitor  184  at this point is given by V C2 =V G −V th  (V G =V Gon ) (S 32  and  FIG. 7B ). If the transistor  182  does not operate properly, it should be noted that the voltage V C2  at this point does not satisfy V C2 =V G −V th .  
         [0036]     Thereafter, the gate voltage V G  is reduced to the voltage V Goff  (S 33 ) so that the conductive/non-conductive state of the transistor  182  does not change due to a data-terminal-voltage varying process that is performed next. At this point, since the transistor  182  is in the non-conductive state, the voltage across the capacitor  184  does not become V 3 , which is equal to the voltage at the data terminal, but is maintained at V C2 =V G −V th , expressed by the gate voltage V G  and the threshold voltage V th  of the transistor  182 .  
         [0037]     Next, while the transistor  182  is in the non-conductive state, the data terminal voltage is set to V 0 , which is different from V 3  (S 34 ). The voltage V 0  satisfies V 0 &lt;V Gon −V th . The voltage V 0  may be the same as either or both of the voltages V 1  and V 2  described above. Thus, the voltage V C , or V C3 , across the capacitor  184  at this point becomes as shown in  FIG. 7C  and as given by the following expression:  
               V     C   ⁢           ⁢   3       =       V     C   ⁢           ⁢   2       +         C   ds         C   ds     +     C   S         ⁢     (       V   0     -     V   3       )                 (   6   )             
 
         [0038]     Here, the second charge-measuring process (S 4 ) is performed. While the data terminal voltage is maintained at V 0 , the gate voltage is increased to the voltage V Gon  to thereby turn on the transistor  182  (S 35 ). The amount of charge flowing through the data line is then measured (S 36 ). At this point, when the ON state of the transistor  182  is maintained for a predetermined period of time or more until the steady state is reached after current flows from the data line via the ON resistance R ON , the voltage across the capacitor  184  becomes equal to the data terminal voltage V 0 , as shown in  FIG. 7D . The amount of charge Q 1  flowing into the capacitor  184  is given by:  
               Q   1     =         C   S     ⁡     (       V     C   ⁢           ⁢   3       -     V   0       )       =       C   S     ⁡     (       V     C   ⁢           ⁢   2       -         C   S         C   S     +     C   ds         ⁢     V   0       -         C   ds         C   S     +     C   ds         ⁢     V   3         )                 (   7   )             
 
         [0039]     Additionally, the applied voltage V 3  is replaced with a different voltage V 4  (where V 4 &gt;V Gon −V th ) and the second voltage-varying process and the second charge-measuring process are repeated. The repeated processes correspond to a third step that includes a third voltage-varying process (S 5 ) and a third charge-measuring process (S 6 ). The voltages V 0  in the second voltage-varying process and the third voltage-varying process do not necessarily have to be equal to each other and thus may be different from each other. When the transistor  182  is brought into the non-conductive state (this process corresponds to S 33 ) and the voltage V 0  is applied to the data terminal (this process corresponds to S 34 ). Thereafter, in a fourth step shown in  FIG. 3 , computation is performed (S 7 ). A voltage V C4  across the capacitor  184  is expressed by:  
               V     C   ⁢           ⁢   4       =       V     C   ⁢           ⁢   2       +         C   ds         C   ds     +     C   S         ⁢     (       V   0     -     V   4       )                 (   8   )             
 
 The amount of charge Q 2  flowing from the data line to the capacitor  184  after the transistor  182  is brought into the conductive state is expressed by:  
               Q   2     =         C   S     ⁡     (       V     C   ⁢           ⁢   4       -     V   0       )       =       C   3     ⁡     (       V     C   ⁢           ⁢   2       -         C   S         C   S     +     C   ds         ⁢     V   0       -         C   ds         C   S     +     C   ds         ⁢     V   4         )                 (   9   )             
 
         [0040]     Therefore, when ΔV′=V 4 −V 3 , a difference ΔQ′ between the amount of charge in the second charge-measuring process and the amount of charge in the third charge-measuring process (i.e., ΔQ′=Q 1 −Q 2 ) is given by:  
               Δ   ⁢           ⁢     Q   ′       =         Q   1     -     Q   2       =           C   ds     ⁢     C   S           C   S     +     C   ds         ⁢   Δ   ⁢           ⁢     V   ′                 (   10   )             
 
         [0041]     Thus, equation 5 for C S  provides the following equations:  
               C   S     =         Δ   ⁢           ⁢     V   ⁡     (       Q   1     -     Q   2       )         +     Δ   ⁢           ⁢     V   ′     ⁢   Δ   ⁢           ⁢   Q         Δ   ⁢           ⁢   V   ⁢           ⁢   Δ   ⁢           ⁢     V   ′                 (   11   )                 C   ds     =         Δ   ⁢           ⁢     V   ⁡     (       Q   1     -     Q   2       )           Δ   ⁢           ⁢     V   ′     ⁢   Δ   ⁢           ⁢   Q       ⁢         Δ   ⁢           ⁢     V   ⁡     (       Q   1     -     Q   2       )         +     Δ   ⁢           ⁢     V   ′     ⁢   Δ   ⁢           ⁢   Q         Δ   ⁢           ⁢   V   ⁢           ⁢   Δ   ⁢           ⁢     V   ′                   (   12   )             
 
 Since ΔV and ΔV′ are given, measuring ΔQ, Q 1 , and Q 2  (ΔQ′) can determine the capacitance C S  of the capacitor  184  and the parasitic capacitance C ds  of the transistor  182 , respectively, from equations 11 and 12 illustrated above. 
 
         [0042]     As described above, according to a preferred embodiment of the present invention, in addition to the known first step, while a voltage with which the transistor  182  goes into the conductive state, i.e., a voltage that brings the transistor  182  into the conductive state under a data terminal voltage typically used, is applied to the gate in the second and third voltage varying processes (S 3  and S 5 ), two selected voltages that cause the voltage between the gate terminal and the source terminal to be less than or equal to the threshold voltage V th , thereby bringing the transistor  182  into the non-conductive state, are applied as data terminal voltages, respectively, to cause the voltage across the capacitor  184  to be equal to the voltage V G −V th . This scheme is utilized to eliminate the term V C2 , thereby making it possible to determine the capacitance C S  of the capacitor  184  and the parasitic capacitance C ds  of the transistor  182 , without actually measuring the voltage V C2  of the capacitor.  
         [0043]     Although the voltage-varying and charge-measuring processes described above are illustrated with the sequence of the first, second, and the third processes for convenience of description, the sequence for carrying out those processes is arbitrary and thus is not restricted to the embodiment described above. According to another preferred embodiment, the sequence can be such that, after the first step is performed, the second step is performed, the first step is performed again, and the third step and the fourth step are performed. According to still another preferred embodiment, as the result of the first step, either of the results for the first time or the second time the first step is performed can be used. Also, the average of the first-step results for the first time and the second time it is performed can be used. Such an arrangement provides an advantage in that more systematic measurement is possible. Repeating the processes described above while changing data lines to which a voltage is applied allows measurement of the capacitance of the storage capacitor for each pixel.  
         [0044]     In another embodiment of the present invention, in the second and third voltage-varying processes, a scheme, which is not as accurate as the scheme described above, for causing a voltage across the capacitor  184  to become substantially V G −V th  can be used instead of processes S 29  to S 32  shown in  FIG. 6 . Specifically, referring to  FIG. 8 , first, the V Goff  is applied to the gate terminal to bring the transistor  182  into the non-conductive state (S 50 ). Next, a voltage V 2  that satisfies V 2 &lt;V G −V th  is applied to the data terminal (S 51 ). Subsequently, V Gon  is applied to the gate terminal to bring the transistor  182  into the conductive state (S 52 ). Further, the data terminal voltage is increased to a voltage V 3  that satisfies V 3 &gt;V Gon −V th  (S 53 ). As a result, the voltage between the gate terminal and the source terminal becomes less than or equal to the threshold voltage V th , so that the transistor  182  goes into the non-conductive state. A voltage V C2  across the capacitor  184  becomes substantially V G −V th  (V G =V Gon ). However, since electric charge moves to the capacitor  184  via the parasitic capacitance C ds  in the process in which the data terminal voltage is increased to V 3 , the accuracy is not so high. Thus, this method is effective for a case in which high accuracy is not required. Since the remaining processes are analogous to process S 33  and the subsequent processes shown in  FIG. 6 , descriptions thereof will not be given hereinafter. In this case, at least two of the voltages V 1 , V 2 , and V 0  may be equal to each other.  
         [0045]      FIG. 9  shows an example of a measuring apparatus  200  that can be used for realizing the method and the apparatus of the present invention. This measuring apparatus  200  includes a variable voltage source  222 , a charge meter  213 , and a memory  212 . The entire operation of the measuring apparatus  200  is controlled by a central processing unit (CPU)  211 . The measuring apparatus  200  is connected to a TFT array  102 , which includes a plurality of pixels (some of which are denoted with reference numerals  156 ,  158 , and  169 ). Selection of a gate line  152  by a vertical (V) shift register  142  and selection of a data line  154  by a horizontal (H) shift register  140  can define a data line voltage and a gate line voltage to be applied to a specific pixel. The H shift register  140  is provided with a clock signal terminal CLK_H ( 128 ), a pulse input terminal Start_H ( 130 ), and a shift direction terminal Dir_H ( 126 ). The V shifter register  142  is provided with a clock signal terminal CLK_V ( 148 ), a pulse input terminal Start_V ( 146 ), a shift direction terminal Dir_V ( 150 ), and an enable terminal ENB_V ( 149 ). The clock signal terminals  128  and  148 , the pulse input terminals  130  and  146 , the shift direction terminals  126  and  150 , and the enable terminal  149  output timing signals for performing operations described below under the control of the CPU  211 .  
         [0046]     In accordance with a clock signal supplied to the corresponding input terminal, each shift register shifts a signal, supplied to the corresponding pulse input terminal, in a direction defined by a signal supplied to the corresponding shift direction terminal. Examples of the circuits of the H shift register  140  and the V shift register  142  are schematically illustrated in  FIGS. 10 and 11 , respectively, and the operations thereof will be described below.  
         [0047]     Referring to  FIG. 10 , the H shift register  140  includes U shift registers HSR 1  to HSR U , including HSRm  1402 . According to the number of clock signals supplied to the clock terminal CLK_H ( 128 ), the H shift register  140  shifts a logic-high signal, supplied to the pulse input terminal Start_H ( 130 ), in a direction specified by the shift direction terminal Dir_H ( 126 ). Further, the H shift register  140  closes a relay ( 1404  in this case) coupled to the corresponding shift register (HSRm  1402  in this case) that stores the logic-high signal. As a result, a signal supplied to a data terminal  124  is output to the data line  154  (Dm in the illustrated example). Thus, data lines that have not been selected are released. The H shift register  140  may have an enable terminal. In such a case, the specified relay  1404  is closed, only when the logic of the enable terminal is high. A system for short-circuiting an unselected data line to another signal line may be employed for the H shift register  140 .  
         [0048]     Referring now to  FIG. 11 , the V shift register  142  includes V shift registers VSR 1  to VSR V , including VSRn  1502 . The V shift register  142  shifts a logic-high signal, supplied to the pulse input terminal Start_V ( 146 ), in a direction specified by the shift direction terminal Dir_V ( 150 ), according to the number of clock signals supplied to the clock terminal CLK_V ( 148 ). In this example, only when a logic-high signal is output from the shift register VSRn  1502  and a logic-high signal is supplied to the enable terminal ENB_V ( 149 ), a logic-high signal is output from an AND circuit  1504 , which is connected to the output of the shifter register  1502 . The output logic-high signal is then buffered and amplified by a buffer  1506  to cause an ON voltage V on  to be output to the gate line Gn  152 . On the other hand, a shift register that has not been selected outputs a logic-low signal, which is buffered and amplified by a corresponding buffer. Consequently, an OFF voltage V off  is output to a gate line that has not been selected.  
         [0049]     The enable terminal ENV_V ( 149 ) may be eliminated from the V shift register  142 . In such a case, the AND circuit  1504  is not provided, so that merely selecting a shift register causes the ON voltage V on  to be output to the gate line.  
         [0050]     Referring back to  FIG. 9 , the variable voltage source  222  for applying a voltage to a selected data line and the charge meter  213  for measuring the amount of charge that moves via the data lines during the application of a voltage from the variable voltage source  222  are connected in series with the power-supply terminal  124  for the H shift register  140 . The setting of the variable voltage source  222  and the setting of the charge meter  213  are controlled by the CPU  211  and the measurement value of the charge meter  213  is stored in the memory  212  via the CPU  211 .  
         [0051]     Each pixel, for example, the pixel  158 , in the TFT array  102  is connected to the corresponding gate line (Gn) via the line  162  and is similarly connected to the corresponding data line (Dm) via the line  164 .  
         [0052]     The measuring apparatus  200  has been illustrated merely as an example, and it is apparent to those skilled in the art that various configurations different from the above-described configuration can be employed to carry out the present invention disclosed in the appended claims. For example, various systems can be employed for the charge meter  213  for measuring the amount of charge movement. In the present invention, systems other than those described above can also be applied to the shift register  140  and/or the V shifter register  142 . Furthermore, in the present invention, various systems other than those described above can be applied to the circuits of the LCD and the OLED shown in  FIG. 1 . In the embodiment described above, although the line  188  has been described as a ground line connected to ground for the sake of simplifying the description, it may be a power-supply line at a different potential. In the description given above, the TFT is an n-type TFT, but the present invention is similarly applicable to a p-type TFT, although the polarity is reversed in such a case.

Technology Classification (CPC): 6