Patent Abstract:
A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair operation. Each of the fuse units includes a plurality of fuses, and is configured in such a manner that m mats correspond to one fuse or n mats correspond to one fuse, where m and n are natural numbers equal to or more than 1 and different from each other.

Full Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2012-0056120 filed on May 25, 2012, in the Korean Intellectual Property Office, which is incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a semiconductor circuit, and more particularly, to a column repair circuit. 
         [0004]    2. Related Art 
         [0005]    In general, a semiconductor memory apparatus includes a is plurality of mats, and each mat includes numerous memory cells. A failure in any one of the numerous memory cells may cause the semiconductor memory apparatus to malfunction, which may lead to the entire semiconductor memory apparatus to be discarded as a defective product. Therefore, a repair circuit is used to replace the failed memory cell with a cell included in a redundancy circuit. When a failure occurs in a memory cell, the repair circuit recognizes the failed memory cell in advance, and when access to the corresponding memory cell is requested, the repair circuit replaces the memory cell with the cell included in the redundancy circuit. Here, the redundancy circuit refers to a group of spare memory cells which are separately prepared. 
         [0006]    A variety of methods may be used to replace a failed memory cell with a redundancy memory cell. Such methods may include replacing a memory cell by row, replacing a memory cell by column, and replacing a memory cell by memory cell. 
         [0007]    The method for replacing a memory cell by column corresponding to bit lines is generally used. In this method, when a failure occurs in a memory cell of a mat, a fuse is cut to replace a column including the failed memory cell with a redundancy column. 
         [0008]    The above-described column repair method is advantageous in that a memory cell may be repaired using column addresses of the mat. However, when failures uniformly occur in memory cells of a plurality of mats, fuses of all corresponding mats must be cut. Furthermore, even when memory cell failures occur in portions of the mats, fuses of all corresponding mats must be cut. Thus, unnecessary repair time may be required, and excessive fuse cutting may reduce the reliability of the semiconductor apparatus. 
       SUMMARY 
       [0009]    In an embodiment of the present invention, a column repair circuit of a semiconductor memory apparatus which includes a plurality of mats performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair operation. Each of the fuse units includes a plurality of fuses, and is configured in such a manner that m mats correspond to one fuse and n mats correspond to another fuse, where m and n are natural numbers greater than or equal to 1 and differ from each other. 
         [0010]    In an embodiment of the present invention, a column repair circuit includes a combined mat address generation unit and at least two fuse units. The combined mat address generation unit is configured to receive mat addresses, perform one or more combination steps according to a method of combining the received mat addresses by adjacent addresses and recombining the combination results by adjacent values, and outputs the received mat addresses and the combination results of the respective combination steps as combined mat addresses of the respective steps. The two or more fuse units each include a plurality of fuses corresponding to the is combined mat addresses based on respective bits of a column address, and are configured to replace a corresponding column of the inputted column address with a redundancy column depending on whether or not a fuse corresponding to a selected combined mat address is cut, wherein each of the fuse units receives the combined mat addresses outputted at any one step of the method described above. 
         [0011]    In an embodiment of the present invention, a column repair circuit includes a combined mat address generation unit and at least two fuse units. The combined mat address generation unit is configured to receive x mat addresses, performs a plurality of combination steps according to a method of combining the received x mat addresses by adjacent addresses and recombining the combination results by adjacent values, and outputs the x mat addresses, x/2 combination results, x/4 combination results, and x/8 combination results as combined mat addresses of the respective steps. The two or more fuse units each include a plurality of fuses corresponding to the combined mat addresses based on respective bits of a column address, and are configured to replace a corresponding column of the inputted column address with a redundancy column depending on whether or not a fuse corresponding to a selected combined mat address is cut, wherein each of the fuse units receives the combined mat addresses outputted at any one of the steps of the method described above. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0013]      FIG. 1  is a block diagram of a column repair circuit according to an embodiment of the present invention, 
           [0014]      FIG. 2  is a block diagram of a first fuse unit of  FIG. 1 , 
           [0015]      FIG. 3  is a circuit diagram of a first fuse set of  FIG. 2 , 
           [0016]      FIG. 4  illustrates a column repair operation according to an embodiment of the present invention, 
           [0017]      FIG. 5  is a block diagram of a column repair circuit according to an embodiment of the present invention, 
           [0018]      FIG. 6  is a circuit diagram of a combined mat address generation unit of  FIG. 5 , 
           [0019]      FIG. 7  is a circuit diagram of a combined mat address selection unit which may be additionally included in the combined mat address generation unit of  FIG. 5 , 
           [0020]      FIGS. 8A and 8B  are block diagrams of first and second fuse units of  FIG. 5 , respectively, 
           [0021]      FIGS. 9A and 9B  are circuit diagrams of first fuse sets of  FIGS. 8A and 8B , respectively, and 
           [0022]      FIG. 10  illustrates a column repair operation according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Hereinafter, a column repair circuit according to the present invention will be described below with reference to the accompanying drawings through various embodiments. 
         [0024]      FIG. 1  is a block diagram of a column repair circuit according to an embodiment of the present invention. 
         [0025]    The column repair circuit illustrated in  FIG. 1  includes a combined mat address generation unit  1  and a fuse unit  2 . 
         [0026]    The combined mat address generation unit  1  is configured to receive mat addresses MATADD&lt; 0 ˜ 15 &gt;, combine the received addresses by adjacent address, and output the combined addresses as combined mat addresses MAT&lt; 0 ˜ 7 &gt;.  FIG. 1  illustrates a case in which the received mat addresses MATADD&lt; 0 ˜ 15 &gt; include 16 addresses where two adjacent addresses are combined to output eight combined mat addresses MAT&lt; 0 ˜ 7 &gt;. The combined mat address generation unit  1  is not limited to the embodiment of the present invention, but may receive various numbers of mat addresses MATADD and output various numbers of combined mat addresses MAT by combining the received mat addresses by a plurality of addresses. 
         [0027]    The fuse unit  2  includes first to fourth fuse units  20  to  50  configured to receive the combined mat addresses MAT&lt; 0 ˜ 7 &gt; and a column address YADD&lt; 2 : 9 &gt; to generate redundancy column enable signals REN 1  to REN 4 , respectively. The column address YADD&lt; 2 : 9 &gt; is a code signal which is not decoded. The fuse unit  2  may include a fuse corresponding to each column address. In this embodiment of the present invention, the fuse unit  2  may include a fuse is corresponding to each bit of the column address, in order to perform a repair operation. 
         [0028]    According to the embodiment of the present invention, fuse sets (not illustrated) corresponding to the respective bits of the 8-bit column address YADD&lt; 2 : 9 &gt;are provided to repair 256 columns. It is difficult to repair all the columns using only one fuse unit. 
         [0029]    Accordingly, an efficient number of fuse units  20  to  50  may be included by taking into consideration factors such as available area for the fuse units as well as the repair yield. 
         [0030]    The combined mat address generation unit  1  receives the mat addresses MATADD&lt; 0 ˜ 15 &gt;, combines the received mat addresses MATADD&lt; 0 ˜ 15 &gt; by adjacent address, and outputs the combination results as the mat addresses MAT&lt; 0 ˜ 7 &gt;. The received mat addresses MATADD&lt; 0 ˜ 15 &gt; are divided into a plurality of groups each including adjacent addresses. When any one of the addresses of one group is selected, a combined mat address corresponding to the selected address is selected and outputted to the fuse unit  2 . 
         [0031]    Referring to  FIG. 1 , the combined mat address generation unit  1  receives  16  mat addresses MATADD&lt; 0 ˜ 15 &gt;, and divides the received mat addresses MATADD&lt; 0 ˜ 15 &gt; into eight groups each including two adjacent addresses. For example, the mat addresses MATADD&lt; 0 &gt; and MATADD&lt; 1 &gt; may be combined and outputted, and the mat addresses MATADD&lt; 2 &gt; and MATADD&lt; 3 &gt; may be combined and outputted. In this way, eight combined mat addresses MAT&lt; 0 ˜ 7 &gt; are generated. When any one of the mat addresses MATADD&lt; 0 &gt; and MATADD&lt; 1 &gt; is selected, the corresponding combined mat address MAT&lt; 0 &gt; may be selected and outputted, and when any one of the mat addresses MATADD&lt; 2 &gt; and MATADD&lt; 3 &gt; is selected, the corresponding combined mat address MAT&lt; 1 &gt; may be selected and outputted. In this way, the selection for the eight combined mat addresses MAT&lt; 0 ˜ 7 &gt; is controlled. In this embodiment of the present invention, the combined mat addresses MAT are generated by combining the mat addresses by two adjacent addresses. However, the combined mat addresses MAT may be generated by combining the mat addresses by two or more addresses. 
         [0032]    Each of the first to fourth fuse units  20  to  50  of the fuse unit  2  includes a fuse which is cut depending on whether or not a failure occurred in a corresponding memory cell. The fuse unit  2  determines whether or not to repair a column designated by the combined mat addresses MAT&lt; 0 ˜ 7 &gt; and the column address YADD&lt; 2 : 9 &gt; selected according to whether or not the fuse is cut. 
         [0033]      FIG. 2  is a block diagram of the first fuse unit  20 . The detailed descriptions of the configuration of the first fuse unit  20  may also be applied to the second to fourth fuse units  30  to  50 . 
         [0034]    The first fuse unit  20  includes first to eighth fuse sets  21  to  28  and a comparator  29 . 
         [0035]    The number of the first to eighth fuse sets  21  to  28  corresponds to the bit number of the column address YADD&lt; 2 : 9 &gt;. Each of the fuse sets  21  to  28  includes a plurality of fuses corresponding to the number of the combined mat addresses MAT&lt; 0 ˜ 7 &gt;. 
         [0036]    For example, referring to  FIG. 3 , the first fuse set  21  includes a plurality of fuse FUSE 1  to FUSE 8  allocated to the first column address bit YADD&lt; 2 &gt;. The fuses FUSE 1  to FUSE 8  are connected to a plurality of transistors N 1  to N 8  to receive the combined mat addresses MAT&lt; 0 ˜ 7 &gt;, respectively. Depending on whether or not the fuses FUSE 1  to FUSE 8  are cut, the state of a first fuse signal YFUSE&lt; 2 &gt; is determined. 
         [0037]    When none of the fuses are cut, a deactivated first fuse signal YFUSE&lt; 2 &gt; is outputted regardless of which one of the combined mat addresses MAT&lt; 0 ˜ 7 &gt; is selected. On the other hand, when any one of the combined mat addresses MAT&lt; 0 ˜ 7 &gt; is selected and a fuse corresponding to the selected address is cut, an activated first fuse signal YFUSE&lt; 2 &gt; is outputted. 
         [0038]    The second to eighth fuse sets  22  to  28  include a plurality of fuses allocated to the second to eighth column address bits YADD&lt; 3 : 9 &gt;, respectively, and operate in a similar manner to the first fuse set  21  so as to output second to eighth fuse signals YFUSE&lt; 3 ˜ 9 &gt;. 
         [0039]    The comparator  29  is configured to receive the column address YADD&lt; 2 : 9 &gt;, compare the received column address YADD&lt; 2 : 9 &gt; to the first to eighth fuse signals YFUSE&lt; 2 ˜ 9 &gt;, and output a first redundancy column enable signal REN 1 . When the first to eighth fuse signals YFUSE&lt; 2 ˜ 9 &gt; are matched with the inputted column address YADD&lt; 2 : 9 &gt;, the first redundancy column enable signal REN 1  is activated. 
         [0040]    When the first redundancy column enable signal REN 1  is activated, columns of two mats corresponding to the selected combined mat address may be replaced with redundancy columns. 
         [0041]    Similarly, when the second to fourth redundancy column enable signals REN 2  to REN 4  are activated according to the above-described manner, columns of two mats corresponding to the selected combined mat address may be replaced with redundancy columns. 
         [0042]      FIG. 4  illustrates the column repair operation according to an embodiment of the present invention. 
         [0043]      FIG. 4  illustrates a case in which failures occur in specific cells of first, third, fourth, and eighth mats in a main cell region. According to the embodiment of the present invention, two mat addresses are combined to perform a column repair operation. Although a failure occurs in a memory cell belonging to the first mat, corresponding columns of the first and second mats are replaced with redundancy columns. When failures occur in the same columns of the third and fourth mats, the repair operation may be performed more efficiently than when a repair operation is performed in one mat. 
         [0044]    However, when column failures occur in the all mats due to reasons such as a tainted fabrication environment, all fuses corresponding to the mats must be cut, which is inefficient in terms of repair time and reliability. In order to remove the inefficiency, a repair operation may be set to be performed only by collectively is repairing a plurality of mats. Inefficienty would then be measured in terms of the repair operation. 
         [0045]      FIG. 5  is a block diagram of a column repair circuit according to an embodiment of the present invention, illustrating a configuration for solving the above-described problems. 
         [0046]    The repair circuit illustrated in  FIG. 5  includes a combined mat address generation unit  1 _ 1  and a fuse unit  2 _ 1 . 
         [0047]    The combined mat address generation unit  1 _ 1  is configured to receive mat addresses MATADD&lt; 0 ˜ 15 &gt; and to perform one or more combination steps according to a method of combining the received mat addresses MATADD&lt; 0 ˜ 15 &gt; by adjacent address and recombining the combination results by adjacent value. The combined mat address generation unit  1 _ 1  outputs the received mat addresses MATADD&lt; 0 ˜ 15 &gt; and the combination results of the aforementioned steps as first to fourth combined mat addresses MAT_ 16 &lt; 0 ˜ 15 &gt;, MAT_ 8 &lt; 0 ˜ 7 &gt;, MAT_ 4 &lt; 0 ˜ 3 &gt;, and MAT_ 2 &lt; 0 ˜ 1 &gt;, respectively.  FIG. 5  illustrates a case in which the received mat addresses MATADD&lt; 0 ˜ 15 &gt; include  16  addresses, and each two adjacent addresses are combined at each step, but the present invention is not limited thereto. For example, the combined mat address generation unit  1 _ 1  may receive various numbers of mat addresses MATADD, combine the received mat addresses MATADD by a plurality of addresses, and output various combined mat addresses MAT. 
         [0048]    The fuse unit  2 _ 1  includes first to fourth fuse units  200  to  500 . The first to fourth fuse units  200  to  500  are configured to receive a column address YADD&lt; 2 : 9 &gt; and the first to fourth combined mat addresses MAT_ 16 &lt; 0 ˜ 15 &gt;, MAT_ 8 &lt; 0 ˜ 7 &gt;, MAT_ 4 &lt; 0 ˜ 3 &gt;, and MAT_ 2 &lt; 0 ˜ 1 &gt;, to generate redundancy column enable signals REN 1  to REN 4 , respectively. 
         [0049]    According to the embodiment of the present invention, the first fuse unit  200  receives the first combined mat addresses MAT_ 16 &lt; 0 ˜ 15 &gt; and performs a column repair operation for one mat. The second fuse unit  300  receives the second combined mat addresses MAT_ 8 &lt; 0 ˜ 7 &gt; and performs a column repair operation for two mats. The third fuse unit  400  receives the third combined mat addresses MAT_ 4 &lt; 0 ˜ 3 &gt; and performs a column repair operation for four mats. The fourth fuse unit  500  receives the fourth combined mat addresses MAT_ 2 &lt; 0 ˜ 3 &gt; and performs a column repair operation for eight mats. 
         [0050]      FIG. 6  is a circuit diagram of the combined mat address generation unit  1 _ 1 . 
         [0051]    In  FIG. 6 , the combined mat address generation unit  1 _ 1  is divided into a first address combination unit  1 _ 11  and a second address combination unit  1 _ 12 , for convenience of description. The first and second address combination units  1 _ 11  and  1 _ 12  similar configuration, and the process of combining  16  mat addresses MATADD&lt; 0 ˜ 15 &gt; is divided into two parts. Hereafter, the detailed configuration of the first address combination unit  1 _ 11  will be described. The descriptions may be applied to the second address combination unit  1 _ 12 . 
         [0052]    The first address combination unit  1 _ 11  includes eight buffer sections  1 A to  8 A, four first combination sections  1 B to  4 B, two second combination sections  1 C and  2 C, and one third combination section  1 D. 
         [0053]    The buffer sections  1 A to  8 A are configured to buffer the eight mat addresses MATADD&lt; 0 ˜ 7 &gt; to output the buffered addresses as the first combined mat addresses MAT_ 16 &lt; 0 ˜ 7 &gt;. The buffer sections  1 A to  8 A include inverters IV 1  to IV 8  and buffer stages BUF 1  to BUF 8 , respectively, to buffer the eight mat addresses MATADD&lt; 0 ˜ 7 &gt;. 
         [0054]    The first combination sections  1 B to  4 B are configured to divide the eight first combined mat addresses MAT_ 16 &lt; 0 ˜ 7 &gt; by two adjacent addresses, and to select a corresponding second combined mat address among the four second combined mat addresses MAT_ 8 &lt; 0 ˜ 3 &gt; when any one of each two adjacent addresses is selected. The first combination sections  1 B to  4 B include NAND gates ND 1  to ND 4  and buffer stages BUF 9  to BUF 12 , respectively. The NAND gates ND 1  to ND 4  are configured to receive two adjacent addresses among the inverted mat addresses MADADD&lt; 0 ˜ 7 &gt;, and the buffer stages BUF 9  to BUF 12  are configured to buffer outputs of the NAND gates ND 1  to ND 4 , respectively. 
         [0055]    The second combination sections  1 C and  2 C are configured to divide the four second combined mat addresses MAT_ 8 &lt; 0 ˜ 3 &gt; by two adjacent addresses, to select a corresponding third mat address is between the two third combined mat addresses MAT_ 4 &lt; 0 ˜ 1 &gt;, when any one of each two adjacent addresses is selected. The second combination sections  1 C and  2 C include NOR gates NR 1  and NR 2  and buffer stages BUF 13  and BUF 14 , respectively. The NOR gates NR 1  and NR 2  are configured to receive two adjacent output signals among the output signals of the NAND gates ND 1  to ND 4 , and the buffer stages BUF 13  and BUF 14  are configured to buffer outputs of the NOR gates NR 1  and NR 2 , respectively. 
         [0056]    The third combination section  1 D is configured to select and output the fourth combined mat address MAT_ 2 &lt; 0 &gt; when any one of the two third combined mat address MAT_ 4 &lt; 0 ˜ 1 &gt; is selected. The third combination section  1 D includes a NAND gate ND 5  configured to receive the output signals of the NOR gates NR 1  and NR 2 . 
         [0057]    The first address combination unit  1 _ 11  receives the eight mat addresses MATADD&lt; 0 ˜ 7 &gt;, and generates the eight first combined mat addresses MAT_ 16 &lt; 0 ˜ 7 &gt;, the four second combined mat addresses MAT_ 8 &lt; 0 ˜ 3 &gt;, the two third combined mat addresses MAT_ 4 &lt; 0 ˜ 1 &gt;, and the one fourth combined mat address MAT_ 2 &lt; 0 &gt;. 
         [0058]    Similarly, the second address combination unit  1 _ 12  receives the other eight mat addresses MADADD&lt; 8 ˜ 15 &gt;, and generates the other eight first combined mat addresses MAT_ 16 &lt; 8 ˜ 15 &gt;, the other four second combined mat addresses MAT_ 8 &lt; 4 ˜ 7 &gt;, the other two third combined mat addresses MAT_ 4 &lt; 2 ˜ 3 &gt;, and the other fourth combined mat address MAT_ 2 &lt; 1 &gt;. 
         [0059]    The combined mat address generation unit may additionally include a combined mat address selection unit configured to output the third combined mat addresses MAT _ 4 &lt; 0 ˜ 3 &gt; instead of the fourth combined mat addresses MAT_ 2 &lt; 0 ˜ 1 &gt;, depending on the number of fuses which are to be included in a redundancy circuit. For example, the existing redundancy circuit includes 256 fuses. In this embodiment of the present invention, however, 240 fuses are needed when addresses are combined and outputted in the above-described manner. Therefore, when 256 fuses are to be used, the third combined mat addresses MAT_ 4 &lt; 0 ˜ 3 &gt; may be outputted instead of the fourth combined mat addresses MAT  2 &lt; 0 ˜ 1 &gt;. 
         [0060]      FIG. 7  is a circuit diagram of a combined mat address selection unit  1 _ 13  which may be additionally included in the combined mat address generation unit. 
         [0061]    The combined mat address selection unit  1 _ 13  includes a fuse FUSE 9 , a first selector  1 _ 13   a,  and a second selector  1 _ 13   b.    
         [0062]    Whether or not to cut the fuse FUSE 9  is determined according to an initial setting. Accordingly, a third combined mat address MAT_ 4  or a fourth combined mat address MAT_ 2  is selected. 
         [0063]    A select signal SEL is determined according to whether or not the fuse FUSE 9  is cut. The selectors  1 _ 13   a  and  1 _ 13   b  are provided for the respective addresses, and each includes two pass gates PG 1  and PG 2  or PG 3  and PG 4  and one inverter IV 9  or IV 10 . The operation of the first selector  1 _ 13   a  will be described as follows. When the select signal SEL is deactivated according to whether or not the fuse FUSE 9  is cut, the first pass gate PG 1  is turned on to output the third combined mat address MAT_ 4 &lt; 0 &gt;. On the other hand, when the select signal SEL is activated according to whether or not the fuse FUSE 9  is cut, the second pass gate PG 2  is turned on to output the fourth combined mat address MAT_ 2 &lt; 0 &gt;. The operation of the second selector  1 _ 13   b  is performed in a similar manner. 
         [0064]      FIGS. 8A and 8B  are block diagrams of the first and second fuse units  200  and  300 , respectively. The third and fourth fuse units  400  and  500  may be configured in a similar manner as described with reference to  FIGS. 8A and 8B . 
         [0065]    The first and second fuse units  200  and  300  of  FIGS. 8A  and  8 B may be configured and operated in a similar manner to the first fuse unit  20  of  FIG. 2 . 
         [0066]    The first and second fuse units  200  and  300  include first to eighth fuse sets  210  to  280  and  310  to  380  and comparators  290  and  390 , respectively. The numbers of the first to eighth fuse sets  210  to  280  and  310  to  380  correspond to the bit number of the column address YADD&lt; 2 : 9 &gt;. 
         [0067]    Each of the fuse sets  210  to  280  included in the first fuse unit  200  includes a plurality of fuses corresponding to the number of the first combined mat addresses MAT  16 &lt; 0 ˜ 15 &gt;. 
         [0068]    For example, referring to  FIG. 9A , the first fuse set  210  of the first fuse unit  200  includes a plurality of fuses FUSE 10  to FUSE 25  allocated for the first column address bit YADD&lt; 2 &gt;. The fuses FUSE 10  to FUSE 25  are connected to  16  transistors N 9  to N 24  to is receive the first combined mat addresses MAT_ 16 &lt; 0 ˜ 15 &gt;, respectively. The state of a first fuse signal YFUSE_ 16 &lt; 2 &gt; is determined according to whether or not the fuses FUSE 10  to FUSE 25  are cut. 
         [0069]    When none of the fuses are cut, a deactivated first fuse signal YFUSE_ 16 &lt; 2 &gt; is outputted regardless of which one of the first combined mat addresses MAT  16 &lt; 0 ˜ 15 &gt; is selected. On the other hand, when any one of the first combined mat addresses MAT_ 16 &lt; 0 ˜ 15 &gt; is selected and a fuse corresponding to the selected address is cut, an activated first fuse signal YFUSE_ 16 &lt; 2 &gt; is outputted. 
         [0070]    The second to eighth fuse sets  220  to  280  include a plurality of fuses allocated for the second to eighth column address bits YADD&lt; 3 : 9 &gt;, and operate in a similar manner to the first fuse set  210  so as to output second to eighth fuse signals YFUSE_ 16 &lt; 3 ˜ 9 &gt;, respectively. 
         [0071]    The comparator  290  is configured to receive the column address YADD&lt; 2 : 9 &gt;, compare the column address YADD&lt; 2 : 9 &gt; to the first to eighth fuse signals YFUSE_ 16 &lt; 3 ˜ 9 &gt;, and output a first redundancy column enable signal REN 1 . When the first to eighth fuse signals YFUSE- 16 &lt; 2 ˜ 9 &gt; are matched with the inputted column address YADD&lt; 2 : 9 &gt;, the first redundancy column enable signal REN 1  is activated. 
         [0072]    When the first redundancy column enable signal REN 1  is activated, a column of a mat corresponding to a selected first combined mat address may be replaced with a redundancy column. 
         [0073]    Similarly, each of the fuse sets  310  to  380  included in the second fuse unit  300  includes a plurality of fuses corresponding to the number of the second combined mat addresses MAT  8 &lt; 0 ˜ 7 &gt;. 
         [0074]    For example, referring to  FIG. 9B , the first fuse set  310  of the second fuse unit  300  includes a plurality of fuses FUSE 26  to FUSE 33  allocated for the first column address bit YADD&lt; 2 &gt;. The fuses FUSE 26  to FUSE 33  are connected to eight transistors N 25  to N 32  to receive the second combined mat addresses MAT_ 8 &lt; 0 ˜ 7 &gt;, respectively. The state of a first fuse signal YFUSE_ 8 &lt; 2 &gt; is determined according to whether or not the fuses FUSE 26  to FUSE 33  are cut. 
         [0075]    When none of the fuses are cut, a deactivated first fuse signal YFUSE_ 8 &lt; 2 &gt; is outputted regardless of which one of the second combined mat addresses MAT  8 &lt; 0 ˜ 7 &gt; is selected. On the other hand, when any one of the second combined mat addresses MAT_ 8 &lt; 0 ˜ 7 &gt; is selected and a fuse corresponding to the selected address is cut, the activated first fuse signal YFUSE_ 8 &lt; 2 &gt; is outputted. 
         [0076]    The second to eighth fuse sets  320  to  380  include a plurality of fuses allocated for the second to eighth column address bits YADD&lt; 3 : 9 &gt; and operate in a similar manner to the first fuse set  310  so as to output second to eighth fuse signals YFUSE_ 8 &lt; 3 ˜ 9 &gt;. 
         [0077]    The comparator  390  is configured to receive the column address YADD&lt; 2 : 9 &gt;, compare the column address YADD&lt; 2 : 9 &gt; to the first to eighth fuse signals YFUSE_ 8 &lt; 3 ˜ 9 &gt;, and output a second redundancy column enable signal REN 2 . When the first to eighth fuse signals YFUSE_ 8 &lt; 21   9 &gt; are matched with the inputted column address YADD&lt; 2 : 9 &gt;, the second redundancy column enable signal REN 2  is activated. 
         [0078]    When the second redundancy column enable signal REN 2  is activated, columns of two mats corresponding to a selected second combined mat address may be replaced with redundancy columns. 
         [0079]    Fuse sets (not illustrated) included in the third and fourth fuse units  400  and  500  may also include a plurality of fuses corresponding to the numbers of the third and fourth combined mat addresses MAT_ 4 &lt; 0 ˜ 3 &gt; and MAT_ 2 &lt; 0 ˜ 1 &gt;, respectively. According to the above-described operation, the third fuse unit  400  activates a third redundancy column enable signal REN 3 , and the fourth fuse unit  500  activates a fourth redundancy column enable signal REN 4 . 
         [0080]    When the third redundancy column enable signal REN 3  is activated, columns of four mats corresponding to a selected third combined mat address may be replaced with redundancy columns. 
         [0081]    When the fourth redundancy column enable signal REN 4  is activated, columns of eight mats corresponding to a selected fourth combined mat address may be replaced with redundancy columns. 
         [0082]      FIG. 10  illustrates the column repair operation according to an embodiment of the present invention. 
         [0083]    In a main cell region, a failure may occur in memory cells of individual columns, or a column failure may occur in the entire mats due to factors such as tainted process environments. 
         [0084]    According to an embodiment of the present invention, when an individual memory cell failure occurs in a seventh mat, the first fuse unit  200  may activate the first redundancy column enable signal REN 1  to replace a single column with a redundancy column. 
         [0085]    When a column failure occurs in first to eighth mats, the fourth fuse unit  500  may activate the fourth redundancy column enable signal REN 4  to replace columns of eight mats with redundancy columns. 
         [0086]    When a column failure occurs in the fifth and sixth mats, the second fuse unit  300  may activate the second redundancy column enable signal REN 2  to replace columns of two mats with redundancy columns. 
         [0087]    When a column failure occurs in the second and third mats, the third fuse unit  400  may activate the third redundancy column enable signal REN 3  to replace columns of four mats with redundancy columns. 
         [0088]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the column repair circuit described herein should not be limited based on the described embodiments. Rather, the column repair circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Technology Classification (CPC): 6