Patent Abstract:
A current output circuit with bias control and a method thereof are provided. The current output circuit includes a current mirror circuit comprising a first transistor and a second transistor having respectively two drains, and a control circuit coupled to the current mirror circuit. The control circuit receives drain voltages of the first transistor and the second transistor, and adjusts a respective gate bias of the first transistor and the second transistor according to a respective drain voltage thereof.

Full Description:
FIELD OF THE INVENTION 
     The present invention is related to a current output circuit, and more particularly to a current output circuit with bias control. 
     BACKGROUND OF THE INVENTION 
     A digital-to-analog-converter (DAC) generates an analog signal (voltage or current type) in response to a digital data. The DAC can be applied in many applications such as communication interface, Ethernet PHY, xDSL controller). Please refer to  FIG. 1 , showing a sample of a conventional DAC. The conventional DAC  10  comprises a plurality of DAC units  11 ,  12 , . . . and  1   n . Each DAC unit  11 ,  12 , . . . , in comprises a switch  111 ,  121 , . . . ,  1   n   1  and a current source  113 ,  123 , . . . ,  1   n   3 . The switch  111  ( 121 , . . . ,  1   n   1 ) can be implemented by a pair of transistors ( 1111 ,  1113 ) (( 1211 ,  1213 ), . . . , ( 1   n   11 ,  1   n   13 )). Each of the current sources  113 ,  123 , . . . , and  1   n   3  is implemented by a respective transistor. The respective gate of the pair of transistors  1111 ,  1113 ,  1211 ,  1213 , . . . ,  1   n   11 ,  1   n   13  of each DAC unit  11 ,  12 , . . . ,  1   n  receives a digital signal D 1+ , D 1− , D 2+ , D 2− , . . . , D n+ , D n− , provides analog currents to a load (not shown in  FIG. 1 ) between PAD 1  and PAD 2  according to the digital signal, and produces an output signal V out  between PAD 1  and PAD 2 . 
     With the development of the semiconductor process, the operational adapted is gradually decreasing, and it is more and more difficult to fulfill the requirement for many specifications such as 802.3. For example, an amplitude of the transmission signal is 5V for the 10M transmission mode of the Ethernet. Please refer to  FIG. 2 , showing a circuit diagram of a conventional Current Steering DAC. The DAC  20  comprises a plurality of DAC units  11 ,  12 , . . . and  1   n  (the diagram only shows one DAC unit  11 ), and an impedance  13  comprising a first matching impedance Z 1  and a second matching impedance Z 2 . 
     When the DAC  20  is implemented with a 0.18 μm CMOS Process, the operational voltage V DD  is 1.8V. Please refer to  FIG. 2  again, wherein the single-side amplitude peak value of the first analog signal V out  is 1.25V, and there is only 0.55V (1.8-1.25) at two terminals of the DAC unit  11  when the voltage between the first pad PAD 1  and the second pad PAD 2  reaches the peak value. Therefore, it is possible to affect the working voltage of the current source  113  (implemented by a transistor  113 ) of the DAC unit  11 , and make the operational point of the transistor  113  enter a triode region, which results in a reduced current and a decreased amplitude of the DAC unit  11 . The mentioned phenomenon will be more serious if the operational voltage V DD  is even lower. 
     The conventional solution is to increase the area of the transistor  113  for decreasing the saturation drain-source voltage (V DS,SAT ) thereof, which makes the operational point of the transistor  113  difficult to enter the triode region. However, the mentioned solution will increase the whole area of the circuit, and thus increase the cost as well as decrease the competitive ability accordingly. 
     In order to overcome the drawbacks in the prior art, a current output circuit with bias control and a method thereof are provided in the present invention. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a current output circuit with bias control and a method thereof. The current output circuit of the present invention can be operated steadily and without distortion under a low operational voltage. 
     In an embodiment according to the present invention, a current output circuit is provided, comprising a reference current source for providing a reference current, a current mirror circuit comprising a first transistor and a second transistor, wherein the drain of the second transistor outputs an output current corresponding to the reference current, and a control circuit, coupled to the current mirror circuit and the reference current source, receiving drain voltages of the first transistor and the second transistor and adjusting a respective gate bias of the first transistor and the second transistor according to a respective drain voltage thereof. 
     In another embodiment according to the present invention, an apparatus is provided, comprising a converter comprising an output node and a plurality of converting units, wherein each of the converting units comprises a controlled current sourcing unit to receive a control voltage and to provide a controlled current according to the control voltage, and a switch coupled to the controlled current sourcing unit to provide the controlled current to the output node according to a digital signal. The apparatus further comprises a control circuit coupled to the converter to monitor a potential of the controlled current sourcing unit and thereby produce the control voltage. 
     In another embodiment according to the present invention, a current outputting method is described, comprising providing a reference current, using a current mirror circuit comprising a first transistor and a second transistor to output an output current, wherein the output current is corresponding to the reference current. The outputting method further comprises the steps of comparing a drain voltage of the first transistor with a drain voltage of the second transistor for obtaining a comparison result, and adjusting a respective gate potential of the first transistor and the second transistor according to the first comparison result. 
     In another embodiment according to the present invention, a digital-to-analog converter (DAC) is provided, comprising a first DAC unit responsive to a first control signal for generating a first signal, a second DAC unit responsive to a second control signal for generating a second signal, a summing circuit responsive to said first and second signals for providing an analog output, and a control circuit for monitoring a potential of one of the first and second DAC units to output a control signal to control the first and second DAC units. 
     In another embodiment according to the present invention, a method for converting a digital signal to an analog signal, comprising monitoring a first potential of a first digital-to-analog converter (DAC) unit to produce a control voltage, adjusting the first DAC unit and a second DAC unit in response to the control voltage, utilizing the first DAC unit to convert a digital signal into a first analog signal in response to a first control signal, utilizing the second DAC unit to convert a digital signal to a second analog signal in response to a second control signal, and summing the first and second analog signals for providing an analog output. 
     The present invention may best be understood through the following descriptions with reference to the accompanying drawings, wherein: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing a conventional DAC comprising a plurality of digital to analog converting units; 
         FIG. 2  is a circuit diagram of a conventional Current Steering DAC; 
         FIG. 3  is a diagram showing a current output circuit according to the present invention; 
         FIG. 4  is a diagram showing a bias outputting circuit applicable to a DAC according to the present invention; and 
         FIG. 5  is a diagram showing the present invention applicable to a Current Steering DAC. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Please refer to  FIG. 3 , showing a current output circuit according to the present invention. A circuit  30  comprises a current output circuit  31  and a first circuit  33 , wherein an internal circuit  333  of the first circuit  33  receives a second current I Q2  from the current output circuit  31 . 
     In this embodiment, the current output circuit  31  comprises a current mirror circuit  310 , a feedback control circuit  320  and a reference current source  330  for providing a reference current I Q1 . The current mirror circuit  310  comprises a first transistor  310 A and a second transistor  310 B, wherein a terminal A 1  with a second potential V 2  of the first transistor  310 A is coupled to the feedback control circuit  320  and a terminal A 2  of the first transistor  310 A is coupled to the lower operational voltage (ex: GND), and a control terminal A 3  of the first transistor  310 A receives a control potential V CT  for causing the current flowing through the first transistor  310 A to be the reference current I Q1 . Because of the current mirror structure of the first transistor  310 A and the second transistor  310 B, the current flowing through the second transistor  310 B will be a second current I Q2  proportioned to the reference current I Q1 . In other words, it is related to the aspect ratio of the first transistor  310 A and the second transistor  310 B. In an embodiment, The feedback control circuit  320  comprises a comparison circuit  3201  and a third transistor  3203 , and is coupled between the reference current source  330  and the current mirror circuit  310 . The comparison circuit  3201  comprises a first terminal D 1 , a second terminal D 2  and an output terminal. The first terminal D 1  is coupled to the drain B 1  with a first potential V 1  of the second transistor  310 B. The second terminal D 2  is coupled to the drain A 1  with the second potential V 2  of the first transistor  310 A, and a third potential V 3  is generated at the output terminal of the comparison circuit  3201 . The third transistor  3203  comprises a third terminal D 3  coupled to the terminal A 1  of the first transistor  310 A and a fourth terminal D 4  coupled to the reference current source  330 . The gate G 1  of the third transistor  3203  is coupled to the output terminal of the comparison circuit  3201  and receives the third potential V 3 , so that the first potential V 1  substantially equals to the second potential V 2 . Furthermore, the first circuit  33  can be any circuit requiring a reference current I Q2  provided by the second transistor  310 B, or it can comprise the second transistor  310 B to receive the second current I Q2 . Besides, the first circuit  33  can further comprise a fourth transistor (not shown in  FIG. 3 ), wherein a gate of the fourth transistor receives the control potential V CT  and form another current mirror circuit with the first transistor  310 A. 
     Please refer to  FIG. 4 , showing a bias outputting circuit according to the present invention applicable to the first circuit  33 . The DAC  40  comprises a bias outputting circuit  41  according to the present invention and a DAC unit  43 . In this embodiment, the DAC unit  43  comprises a switch  433  and a current source  420  implemented by a transistor  310 B. The bias outputting circuit  41  comprises a first transistor  310 A, a feedback control circuit  320  and a reference current source  330 , wherein the first transistor  310 A of the bias outputting circuit  41  and the transistor  310 B of the DAC unit  43  form a current mirror circuit. Furthermore, in  FIG. 3  and  FIG. 4 , there is an omissible transistor coupled between the reference current source  330  and the third transistor  3203 . 
     Please refer to  FIG. 5 , which is a diagram showing the present invention applicable to a DAC. The DAC  50  comprises the bias outputting circuit  41  according to the present invention and a plurality of DAC units  43 . Each DAC unit  43  comprises a switch  433  and a current source  413 , wherein an embodiment of the current source  413  is a transistor  310 B. Each current source  413  receives a control voltage V CT  and outputs a current according to the control voltage V CT . 
     In this embodiment, the switch  433  of each DAC unit  43  receives corresponding digital signals, i.e. the respective D 1+  and D 1−  (D 2+  and D 2− , D n+  and D n− ) for converting the digital signals to current signals. Each current signal is summed up to form an analog outputting signal outputted at PAD 1  and PAD 2 . In  FIG. 5 , there are a plurality of transistors coupled between a transistor  4331  and the PAD 1  as well as between a transistor  4333  and the PAD 2 , for increasing the performance of the DAC unit  43 . Furthermore, there is a transistor coupled between the reference current source  330  and the third transistor  3203 , which is added for the transistors coupled between the transistor  4331  and the PAD 1  as well as between the transistor  4333  and the PAD 2 . The above-mentioned transistors are all omissible. 
     Please refer to  FIGS. 3-5 , wherein the output terminal of the comparison circuit  3201  of the feedback control circuit  320  outputs the third potential V 3  by comparing the first terminal D 1  with the second terminal D 2  thereof. The transistor  3203  receives the third potential V 3  to make the drain-source voltage (V DS ) of the second transistor  310 B be adjusted the same as the drain-source voltage (V DS ) of the first transistor  310 A, thereby causing the second current I Q2  to substantially correspond to the reference current I Q1 . 
     It is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Technology Classification (CPC): 7