Patent Abstract:
There is disclosed an image processing circuit for displaying a plurality of sub-pictures which have different image signal sources on a common screen. The inventive subject digitalizes an original image analog signal by use of a corresponding sampled signal upon a multiple picture processing, saves the digitalized data almost simultaneously, and uses a dual-port memory for reading the data, whereby the circuit simplifies the generating process of a control timing signal and renders the PIP process easy to carry out, when controlling the dual-port memory by read-write operation. The apparatus for carrying out the invention includes a keyboard or remocon for data input/output, a microcomputer for controlling the entire process, a controller for controlling display processes, an analog switching device, an A/D converter for converting the analog signal to a digital signal, a dual-port memory for dealing with various image signals, and three D/A converters for converting digital data to analog data.

Full Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a picture-in-picture (hereinafter referred to as PIP) television set and a video tape recorder, and more particularly, to a image processing circuit capable of producing multiple pictures simultaneously on a common display screen. 
     Generally, in a PIP display, a B-channel picture (hereinafter referred to as sub-picture), being inserted at a predetermined area of an A-channel picture (hereinafter referred to as main picture), is displayed at a size corresponding to that of one-ninth of main picture. Such image processing techniques, which display main picture and sub-picture from different image sources respectively on one display screen, are applied to television and VTR systems. 
     Each VT and TVR maker applies specific format for a PIP system, and the PIP processing systems have different properties from one another in accordance with each specific format. For example, some processing systems use a method which samples both the main picture signal and the sub-picture signal simultaneously to convert those to digital data, while the other processing systems use a method which converts only the sub-picture to digital data. Additionally, there is disclosed the method of displaying within the main picture a small picture having a different picture source from the main picture. However, by the remarkable progress of PIP technique, a technique which displays simultaneously the multiple different pictures has been disclosed. In addition, there is disclosed another prior art which displays two sub-pictures simultaneously in a main picture, whereby one of the two pictures is a still picture while the other is a moving picture. 
     In the beginning techniques for displaying the multiple pictures disclosed recently, the PIP system includes four sets of a PIP controller, a line memory and a field memory respectively, and displays the picture on the screen by a write control signal of the controller during the reading process of the image signal. 
     This method is already a widely-known technique, which samples sequentially B-Y, R-Y and Y signals. In this processing method, since the line memory and the field memory are constituted separately, the control methods thereof are also independent of each other. Accordingly, the image data can be written and read respectively. Therefore, in the above-mentioned conventional method, since each of the line memory and the field memory is controlled independently each of other, the control timing signals must be produced effectively to control the memories. In attaining the goal, there has been a problem in which the construction of the circuit becomes complicated and raises the production cost of the system employing this known method. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the present invention to provide a circuit for digitalizing an original image analog signal by use of a corresponding sampled signal during multiple picture processing, saving the digitalized data almost simultaneously, and using a dual-port memory for reading the data, whereby the circuit simplifies the process of generating a control timing signal and renders the PIP process easy to carry out, when controlling the dual-port memory by read/write operation. 
     It is another object of the present invention to provide a circuit capable of producing multiple pictures. 
     According to one aspect of the present invention, a image processing circuit for displaying a plurality of sub-pictures having different image signal sources on a common screen includes a keyboard or remocon means for data input/output, a microcomputer for controlling the entire process, a controller for controlling displaying process, an analog switching device for selecting a luminance signal and color difference signal from the controller, an A/D converter for converting the analog signal into a digital signal, a dual-port memory for dealing with various image signals, and first, second, and third D/A converters for converting digital data to analog data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects as well as advantages of the present invention will become clear by the following description of the present invention with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram illustrating schematically an image signal processing circuit according to the present invention; 
     FIG. 2 is a specific block diagram illustrating in more detail a controller of FIG. 1 according to the invention; 
     FIGS. 3a-3c are timing charts of the multiple picture selecting output data from a microcomputer according to the present invention; 
     FIGS. 4a-4d represent waveforms of the switching signal of an analog switching stage and of the A/D converting clock signal at a line of FIG. 1 according to the present invention; 
     FIGS. 5a-5f are diagrams representing the reading and writing of multiple pictures according to the present invention; and 
     FIGS. 6a-6i are specific diagrams for a timing that is requested in color encoder according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The invention will now be described in detail with reference to the drawings. 
     FIG. 1 is a block diagram illustrating schematically an image signal processing circuit according to the present invention. A keyboard or remote controller (i.e., a remocon) 100 is capable of inputting an instruction word of the multiple picture mode established an user. A microcomputer 200 checks the instruction word for processing the multiple picture inut through said keyboard or remocon 100, produces the clock and data for processing the multiple pictures through the lines 201 and 202, and recognizes whether the data is effective or not by the data received through a strobe line 203. 
     A controller 500 receives through the lines 503-506 the vertical and horizontal synchronizing signals of the main picture and sub-pictures from a synchronizing separator (not shown) for the video signal and receives a first and a second reference frequency produced in the oscillator through the lines 501 and 502, thereby to control the displaying of the multiple pictures on a monitor by the data from microcomputer 200. An analog switching device 300 selects and inputs the luminance signal Y and color difference signals B-Y and R-Y from lines 301 and 303 in the sequence of R-Y→Y→Y→B-Y→Y→Y by the switching signals for selecting luminance signal Y and color difference signals B-Y and R-Y from lines 304-306 of the controller. 
     An analog/digital converter 400 converts the output data of the analog switching device 300 into digital data by the signal of the clock terminal CLK in the A/D converter, wherein the signal is from the controller 500. A dual-port memory 600 provided with two ports of input/output terminals accessable independently from each port bidirectionally, outputs the signals of DT, CAS, RAS, WE and SC through the lines 604-608 connected with the controller 500 in response to the vertical and horizontal synchronizing signals of the main picture and the sub-picture, the address signal being produced to a line 603, stores and reads the video signal digitized by said analog/digital converter 400 through the data lines 603 and 602 of the access ports in accordance with the window of the designated multiple picture, and outputs the corresponding video data to the serial port by the control signal at the random port from controller 500. 
     A first, a second and a third D/A converter 700, 800 and 900 divides the digital data from dual-port memory 600 into the luminance signals and the color difference signal in accordance with the D/A conversion sampling produced from controller 500, thereby converting the data into an analog signal; and color encoder 1000 encodes, by the sub-picture position determining signal and the pedestal clamping signal of the composite synchronizing signal through lines 509 and 510 of controller 500, the digital signal produced in first, second and third D/A converters 700, 800 and 900 with the main picture video signal, thereafter to display it in the form of a multiple picture. 
     FIG. 2 is a specific block diagram illustrating in more detail the controller of FIG. 1 according to the invention. A command decoder 10, connected with said microcomputer 200 through lines 201-203, decodes the data from said microcomputer 200 to identify if it is the multiple picture selecting signal, thereby producing the control signal for performing the read/write function according to said identification; a writing controller 20, connected with said command decoder 10 through a line 11, produces the writing control signal by the picture selecting information produced from the command decoder 10 and vertical/horizontal synchronizing signal of the sub-picture input through lines 506 and 507. 
     A writing timing signal generator 40 uses the picture producing timing control signal from writing controller 20 for determining the desired number of the pictures and performing the various sub-functions, and uses a first reference signal and the sub-picture vertical/horizontal synchronizing signals at lines 506 and 507, thereby to generate the column, refresh clock of dual-port memory 600 and the luminance YS and color B-YS, R-YS switching signals through lines 304, 305 and 306 which are required in switching device 300 shown in FIG. 1, generates the sampling clock signal for converting the signal into the digital data required in said analog/digital converter 400, generates the clock signal for converting the &#34;m&#34; bit data requested in dual-port memory 600 and the latch clock required for latching the output data in analog/digital converter 400, and generates all clock signals produced when writing the sub-picture data. 
     A first latch 50 latches the digital data through a line ADD (i.e., lead 401 as shown in FIG. 1) from the analog/digital converter 400 by the timing clock signal through a line 45 coupled to writing timing signal generator 40. A data converter 60 converts the digital data received via lead 51 into the corresponding &#34;m&#34; bit data suitable for the processing characteristics of dual-port memory 600 in accordance with the data converting clock from said writing timing signal generator 40 via lead 46. 
     A writing address signal generator 70 uses the input signals received through the input lines 506 and 507 of said sub-picture vertical/horizontal synchronizing signals and the control signal at line 22 of said write controller 20, and uses the column and refresh clocks produced from the writing timing signal generator 40, thereby to generate the column and row signals for writing the image data and thereafter address signals for refreshing the memory. 
     A multiplexer 90 selects the column and row address signals and the address signal for memory refreshing at lines 71-73 from said writing address signal generator 70 by the control signals produced from said writing timing signal generator 40, thereby to select the memory refreshing address, the image data writing signal and output address signals for processing the multiple pictures in said dual-port memory 600. A memory timing generator 80 generates the RAS, CAS, DT and WE control signals required in said dual-port memory 600 by the timing clock for memory and the control signal for memory processing generated in said writing timing signal generator 40. 
     A reading controller 30 receives the address signals for choosing the memory area from said writing address signal generator 70 via lead 74, and receives from said command decoder 10 the read control signal indicating that the picture information exists in said dual-port memory 600 thereby to produce the reading control signal by the vertical synchronizing signal of the main picture produced through the line 503. A reading timing signal generator 110 receives the first reference signal (a=f sc ) (a&gt;0), and inputs the main picture horizontal synchronizing signal and the position information of identifying signal produced from said reading controller 30 to logicalize these signals, and thereafter to generate the clock for the digital/analog conversion, the window control signal and BFP signal produced through lines 501, 508-510 and BFP. 
     A reading address signal generator 288 uses the position information signal representing the position of the small a picture-in-picture for to be displayed through line 111 connected with reading timing signal generator 110 and the main picture horizontal synchronizing signal input through the line 504, and uses the enabling signal for starting to read out from the read controller 30 to logicalize said input signals, thereby generating the address signal for reading the image data; a second latch 120 latches the data from said dual-port memory 600 by the signal output from said reading timing signal generator 110. 
     A data spectrum and data controller 130 converts the data received from second latch 120 via lead 121 into the format corresponding to the order of B-Y, R-Y and Y outputted said second latch 120 according to the signal received via lead 113 from said reading timing signal generator 110. 
     FIG. 3 is a timing diagram for the picture selection produced in a microcomputer 200 according to the present invention, wherein 3a represents a waveform of data at line 201 connected with the microcomputer 200, 3b represents a waveform of data clock signal at line 202 connected with the microcomputer 200, and 3c represents a waveform of a strobe signal at line 203 connected with the microcomputer 200. 
     FIG. 4 represents waveforms of the switching signals of an analog switching stage 300 of FIG. 1 according to the present invention and of the A/D converting clock signal at line 511 shown in FIG. 1, wherein 4a represents a waveform of a luminance switching signal at line 304, 4b represents a waveform of a R-Y switching signal at line 306, 4c represents a waveform of a B-Y switching signal at line 305, and 4d represents a waveform of a clock signal for converting an analog signal into a digital signal. 
     FIG. 5 is a diagram representing the reading and writing of the multiple pictures in accordance with the present invention, wherein 5A is a view of an example illustrating a section where the sub-picture is written, 5B is a view of an example illustrating the position where the sub-picture is read, 5C is an illustration representing the written position in which the sub-picture is displayed on the basis of a sub-picture vertical synchronizing signal, 5D is an illustration representing the section to be written in which the sub-picture is displayed on the basis of a sub-picture horizontal synchronizing signal, 5E is an illustration representing the positions where the sub-pictures are displayed on the basis of the sub-picture vertical synchronizing signal, 5F is an illustration representing the positions where the sub-pictures are displayed on the basis of the sub-picture horizontal synchronizing signal. 
     FIG. 6 is a specific diagram for a timing that is requested in a color encoder 1000 according to the present invention. Accordingly, an embodiment of the present invention will be explained in detail with reference to FIGS. 1 to 6. In order to produce the sub-picture within the main picture on a common screen in a video receiver system such as TV and VTR, a user pushes a sub-picture selecting key through a keyboard or remocon 100. And then the microcomputer 200 decodes the command key from said keyboard or remocon 100, thereby to identify whether it is the information for selecting the multiple pictures. When the information for selecting the multiple pictures is identified the microcomputer 200 produces the data and the control clock signals in form of the waveforms shown in FIG. 3 to input those through the lines 201-203 to a controller 500. A command decoder 10 in the controller 500 of FIG. 2 receives the data through the line 201, but latches the data line 201 by the clock signal at line 202. 
     The strobe signal at line 203 allows the controller to identify whether the input data of line 201 is the effective data. Accordingly, this is like the command decoder 10 decodes the data to identify if the system is in an &#34;on&#34; state in order to process the sub-picture. And command decoder 10, which controls the dual-port memory 600 to read and write the data, specifies the 1 byte as the predetermind bit to produce the multiple picture selecting information by changing of the flag, and this signal is at line 11 to the write controller 20. 
     When writing the PIP and the multiple pictures, the write controller 20 generates, by the sub-picture vertical and horizontal synchronizing signals of lines 506 and 507 and the picture selecting information produced in command decoder 10, the timing signal for processing the multiple pictures to input this signal through a line 21 to a writing timing signal generator 40. If this is input to a writing address signal generator 70 by using the predetermined high-order bits produced through a line 22, this signal becomes the memory high-order address for the sub-picture writing processing to input to the address for selecting the area of the dual-port memory 600. Writing timing signal generator 40 receives the sub-picture vertical/horizontal signal through the lines 506 and 507, and inputs the second reference signal (b=f sc ) through a line 502 to output the memory column clock signal through a line 41 by said vertical synchronizing signal preferentially. 
     The memory timing generator 80 generates the writing timing signal for processing the sub-picture by the control signal produced through a line 44 and the memory timing clock signal produced through a line 43. The second reference signal (b=f sc ) enables the switching signal to be generated so that the color difference signal R-Y and B-Y and the luminance signal Y as shown in FIG. 4a-4c are selected to be input through the lines 304-306. Further, said generated switching signal is inputted to the analog switching means of FIG. 1. In addition, the A/D clock as shown in FIG. 4d is generated to be input through line 511 to the analog/digital converter 400 of FIG. 1. 
     In FIG. 1, when line 304 is logic high, the analog switching means 300 transmits the luminance signal Y to the analog/digital converter 400, and by the A/D clock which is produced through the line 511 connected with the writing timing signal generator 40, the analog luminance signal is digitized into K(K&gt;0) bits. 
     Likewise, the color difference signals R-Y and B-Y take the process as described above by the switching signal through the lines 305 and 306, and the timing of the switching signal is represented in FIG. 4b and 4c. Namely, the sequence of sampling is repeated in order of R-Y, Y, Y, B-Y, Y, and Y. The digitized data of K bits are signal the first latch 50 of FIG. 2, so that those are latched by the clock signal through a line 45 connected with the writing timing generator 40. Latched data of &#34;K&#34; bits should be converted in the form of the data format of the dual-port memory 600, thereby to be written in the dual-port memory 600, and then said data conversion is performed by data converter 60 so that the data is converted into the &#34;m&#34; (m&gt;0) bits to be conformed with the data format of the dual-port memory 600 by the data converting clock generated in said writing timing signal generator 40. 
     In the meanwhile, by the control signal through the line 22 connected with the writing controller 20, the memory row addresses to be used in the dual-port memory 600 are produced to be input to the writing address signal generator 70. These address signals become of the high-order X bits (X&gt;0) of addresses in the dual-port memory 600. In the writing address signal generator 70, the high-order X bits and the low-order Y bits (Y&gt;0) are generated by the sub-picture horizontal synchronizing signal input through the line 506, thereafter to become the row addresses requested in the entire dual-port memory 600. These signals are input into the multiplexer 90. The column clock signal is generated to count the column address through the line 41 connected with the writing timing signal generator 40, so that it is transmitted to writing address signal generator 70. The writing address signal generator 70 generates the column address signal into the dual-port memory 600 to be written during the period of the sub-picture horizontal synchronization by utilizing the column clock. Said generated column addresses are input into multiplexer 90. 
     Furthermore, the memory timing clocks, which are supplied from the line 43 of the writing timing generator 40, are input to the memory timing generator 80. Memory timing generator 80 generates the RAS, CAS, WE and DT signals using memory timing clocks to supply those through the lines 604-607 to the dual-port memory 600. The writing row column address from multiplexer 90 selects the address to be output to line 603 by the output control signal of the line 44, address being generated from the writing timing signal generator 40. In the memory timing generator 80, the row, column addresses and the control signals (RAS, CAS, WE and DT) are generated by the control signal generated from the writing timing signal generator 40 so that those are supplied to the dual-port memory 600. 
     In FIG. 5, the sub-picture writing position is shown, wherein, in the sub-picture video one field section, after the period that &#34;e&#34; has elapsed from the rising edge of the sub-picture vertical synchronizing signal, the data sampling is started. Subsequently, the data sampling is performed for the time &#34;t&#34;, so that the sampled data is written in the memory. Thereafter, data is not written for the f period. That is, the writing position can be well represented as shown in FIG. 5C. Further in view of the sub-picture horizontal synchronizing period, after the period of g has elapsed from the rising edge of the sub-picture horizontal synchronizing signal, the sampling and writing of the data are started. Subsequently, the data sampling is performed for the time &#34;u&#34;, thereafter to write the sampled data, and this writing of data is not performed for the period &#34;h&#34;. 
     The relationship of this example can be represented as shown in FIG. 5D. In using dual-port memory 600, the writing and reading are performed simultaneously. If the sub-picture enable signal is input in form of signal as shown in FIG. 3a, the writing is performed as described above, and the reading is performed in the following manner. In case that the data, which is input from the microcomputer 200 to the command decoder 10, is the sub-picture enable signal, this signal is supplied through line 12 to the reading controller 30. In reading controller 30, after a plurality of vertical synchronizing signals of the main picture, the row address starting point of the dual-port memory 600 is produced so as to read the data for displaying on the sub-picture area from the dual-port memory 600. When the row address starting point is input to the reading address signal generator 288, the reading address signal generator 288 generates the address signal of the dual-port memory 600, the address signal being required for the reading by the picture position information signal from the read timing signal generator 110 and the main picture horizontal synchronizing signal on line 504. 
     Meanwhile, in the generated address signal, the reading address is selected in response to the control of the reading timing signal generator 110 which inputs the first reference frequency (a fsc) signal received through the line 501 and the main picture vertical synchronizing signal and the main picture horizontal synchronizing signal received through the lines 503 and 504, thereby to generate the timing required for the data reading. And the reading timing signal generator 110 generates through the lines 508-510 and BFP the D/A clocks of the first, second and third digital/analog converters 700, 800 and 900 of FIG. 1, the YS signal indicating the position where the sub-picture is to be screened, the BFP signal being the main picture video burst flag pulse required in the color encoder 1000, and the PCLMP being the main picture pedestal clamping pulse. This timing relationship is represented in FIG. 6. 
     Therefore, the reading timing signal generator 110 produces the DTsignal which is required for reading the data from the dual-port memory 600 to supply through the line 114 to the memory timing generator 80. The memory timing generator 80 produces the RAS, CAS, WE and DT signals to supply those through the lines 604-607 to the dual-port memory 600. 
     Now, the data reading from the dual-port memory 600 will be explained. The SC (Serial Clock) signal on the line 112 connected with the read timing signal generator 110 is input to the second latch 120 thereby to latch the data read from the dual-port memory 600 so as to convert this into the &#34;m&#34; bit read data. Latched data converted into the format conforming with the corresponding bit in the first, second and third digital/analog converter 700, 800 and 900. For this purpose, firstly after data is converted in the data spectrum and data controller 130, the Y (K bits), R-Y (K bits) and B-Y (K bits) are transmitted to the first, second and third digital/analog converter 700, 800 and 900, thereby to be converted into the analog signals Y, R-Y and B-Y respectively by the D/A clock on line 508. The signals from the first, second and third digital/analog converters 700, 800 and 900 are input to the color encoder 1000, and in the color encoder 1000, the main picture video signal on line 1001, and the sub-picture component and the PCLMP, YS and BFP signals through the lines 509, 510 and BFP are composed so that the composite video outputs of new multiple pictures are produced. 
     As described above, according to the present invention, there are advantages of the invention which make it easy to customize the construction of such embodiments in a TTL circuit which, can process the multiple pictures having different picture sources to a user&#39;s taste for TV and VTR and can reduce the production cost by simplification of the construction. 
     The foregoing description shows only a preferred embodiment of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiment shown and described is illustrative only, and not restrictive.

Technology Classification (CPC): 7