Patent Abstract:
Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/813,778, filed on Jun. 15, 2006, the disclosure thereof incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present invention relates generally to integrated circuit manufacture. More particularly, the present invention relates to incorporating multiple integrated circuit dies in a single package. 
     In integrated circuit technology, it is desirable to incorporate multiple integrated circuit dies in a single package, for example to reduce the footprint of the package, and to ensure the dies experience the same environmental conditions. One way to achieve both of these objectives is to stack the dies on top of each other. 
     SUMMARY 
     In general, in one aspect, the invention features an integrated circuit package comprising: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires. 
     In some embodiments, the first wirebond integrated circuit die comprises a redistribution layer comprising traces electrically coupling the electrically conductive bumps to the second electric contacts of the first wirebond integrated circuit die. In some embodiments, the second wirebond integrated circuit die further comprises: fifth electric contacts disposed near a first edge of the second wirebond integrated circuit die; and a redistribution layer comprising sixth electric contacts disposed near a second edge of the second wirebond integrated circuit die, and traces electrically coupling the fifth and sixth electric contacts; wherein the fourth electric contacts are disposed near the second edge of the second wirebond integrated circuit die; and wherein the sixth electric contacts are electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by the second electrically conductive wires. In some embodiments, the substrate and the first wirebond integrated circuit die are mechanically coupled by a first adhesive; and wherein the flip-chip integrated circuit die and the second wirebond integrated circuit die are mechanically coupled by a second adhesive. Some embodiments comprise an encapsulant surrounding the first wirebond integrated circuit die, the flip-chip integrated circuit die, the second wirebond integrated circuit die, and the electrically conductive wires. In some embodiments, the first wirebond integrated circuit die comprises a system-on-a-chip (SoC) electric circuit; wherein the flip-chip integrated circuit die comprises a flash memory; and wherein the second wirebond integrated circuit die comprises a synchronous dynamic random access memory (SDRAM). 
     In general, in one aspect, the invention features a method for fabricating an integrated circuit package, the method comprising: providing a substrate comprising first electric contacts; providing a first wirebond integrated circuit die comprising second electric contacts; mechanically coupling the first wirebond integrated circuit die to the substrate; electrically coupling the second electric contacts of the first wirebond integrated circuit die to the first electric contacts of the substrate using first electrically conductive wires; providing a flip-chip integrated circuit die comprising third electric contacts; electrically coupling the third electric contacts of the flip-chip integrated circuit die to the second electric contacts of the first wirebond integrated circuit die using electrically conductive bumps; providing a second wirebond integrated circuit die comprising fourth electric contacts; mechanically coupling the second wirebond integrated circuit die to the flip-chip integrated circuit die; and electrically coupling the fourth electric contacts of the second wirebond integrated circuit die to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, using second electrically conductive wires. 
     Some embodiments comprise providing, on the first wirebond integrated circuit die, a redistribution layer comprising traces electrically coupling the electrically conductive bumps to the second electric contacts of the first wirebond integrated circuit die. Some embodiments comprise providing fifth electric contacts disposed near a first edge of the second wirebond integrated circuit die; providing a redistribution layer comprising sixth electric contacts disposed near a second edge of the second wirebond integrated circuit die, and traces electrically coupling the fifth and sixth electric contacts; wherein the fourth electric contacts are disposed near the second edge of the second wirebond integrated circuit die; and electrically coupling the sixth electric contacts of the redistribution layer to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by the second electrically conductive wires. Some embodiments comprise mechanically coupling the substrate and the first wirebond integrated circuit die using a first adhesive; and mechanically coupling the flip-chip integrated circuit die and the second wirebond integrated circuit die using a second adhesive. Some embodiments comprise surrounding the first wirebond integrated circuit die, the flip-chip integrated circuit die, the second wirebond integrated circuit die, and the electrically conductive wires with an encapsulant. In some embodiments, the first wirebond integrated circuit die comprises a system-on-a-chip (SoC) electric circuit; wherein the flip-chip integrated circuit die comprises a flash memory; and wherein the second wirebond integrated circuit die comprises a synchronous dynamic random access memory (SDRAM). 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  shows a side view, not necessarily drawn to scale, of an integrated circuit package comprising a stack of three integrated circuit dies according to some embodiments of the present invention. 
         FIG. 2  shows a top view of the redistribution layer of  FIG. 1  according to some embodiments of the present invention. 
         FIG. 3  shows a side view, not necessarily drawn to scale, of an integrated circuit package comprising a stack of three integrated circuit dies with a redistribution layer on the top die according to some embodiments of the present invention. 
         FIG. 4  shows a top view of the redistribution layer of  FIG. 3  according to some embodiments of the present invention. 
         FIG. 5  shows a process for fabricating integrated circuit packages according to embodiments of the present invention. 
       The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention provide integrated circuit packages comprising stacks of integrated circuit dies. According to some embodiments, an integrated circuit package comprises a substrate, a wirebond integrated circuit die atop the substrate, a flip-chip integrated circuit die atop the wirebond integrated circuit die, and a second wirebond integrated circuit die atop the flip-chip integrated circuit die. The contacts of the lower wirebond integrated circuit die are wirebonded to the substrate contacts. The contacts of the flip-chip integrated circuit die, which can be ball grid array (BGA) contacts, are connected to the contacts of the first wirebond integrated circuit die by electrically conductive bumps. The contacts of the upper wirebond integrated circuit die are wirebonded to the contacts of the lower wirebond integrated circuit die, or the contacts of the substrate, or both. 
     Redistribution layers can be used atop either or both of the wirebond integrated circuit dies. A redistribution layer can be used atop the lower wirebond integrated circuit die to connect the electrically conductive bumps to wirebond pads on the lower wirebond integrated circuit die. Another redistribution layer can be used atop the upper wirebond integrated circuit die to connect the wirebond pads from one edge of the upper wirebond integrated circuit die to wirebond pads on another edge, for example when the upper wirebond integrated circuit die is so large that wirebonds are only possible from one edge. 
     An adhesive can be used to mechanically couple the lower wirebond integrated circuit die to the substrate, and to mechanically couple the upper wirebond integrated circuit die to the flip-chip integrated circuit die. Mechanical coupling between the lower wirebond integrated circuit die and the flip-chip integrated circuit die is achieved by the electrically conductive bumps, but can be augmented by underfill techniques using an adhesive. The adhesives can include silver epoxy and the like. An encapsulant can be used to surround the stack of integrated circuit dies and the wirebond wires. 
     In some embodiments, the lower wirebond integrated circuit die comprises a system-on-a-chip (SoC) electric circuit, the flip-chip integrated circuit die comprises a flash memory, and the upper wirebond integrated circuit die comprises a synchronous dynamic random access memory (SDRAM). In other embodiments, other integrated circuits can be used. 
       FIG. 1  shows a side view, not necessarily drawn to scale, of an integrated circuit package  100  comprising a stack of three integrated circuit dies according to some embodiments of the present invention. Integrated circuit package  100  comprises a substrate  102 , a wirebond integrated circuit die  104 , a flip-chip integrated circuit die  106 , and a wirebond integrated circuit die  108 . 
     Substrate  102  has electric contacts  110  that can be connected to other devices, terminals, and the like. Wirebond integrated circuit die  104  has electric contacts (that is, wirebond pads)  112  that are connected by electrically conductive wires  124 A to electric contacts  110  of substrate  102 . Electrically conductive wires  124 A can be implemented as gold wires and the like. 
     Flip-chip integrated circuit die  106  has electric contacts (that is, balls)  114  that are connected by electrically conductive bumps  120  to wirebond pads  112  of wirebond integrated circuit die  104 . In some embodiments, a redistribution layer (RDL)  122  is used to connect electrically conductive bumps  120  to some or all of wirebond pads  112 . 
       FIG. 2  shows a top view of redistribution layer  122  of  FIG. 1  according to some embodiments of the present invention. Redistribution layer  122  includes electric contacts (that is, bump pads)  202  for connection to respective electrically conductive bumps  120  of flip-chip integrated circuit die  106 , electric contacts  204  for connection to respective wirebond pads  112  of wirebond integrated circuit die  104 , and electrically conductive traces  206  connecting respective bump pads  202  and electric contacts  204 . 
     Referring again to  FIG. 1 , wirebond integrated circuit die  108  has electric contacts (that is, wirebond pads)  116 . Wirebond pads  116  can be connected by electrically conductive wires  124 B to electric contacts  110  of substrate  102 , or can be connected by electrically conductive wires  124 C to wirebond pads  112  of wirebond integrated circuit die  104 , or both. Electrically conductive wires  124 B-C can be implemented as gold wires and the like. 
     In various embodiments, some or all of wirebond pads  112  on wirebond integrated circuit die  104  are electrically coupled to the integrated circuit within wirebond integrated circuit die  104 . But in some embodiments, some of wirebond pads  112  are not coupled to the integrated circuit, but are provided instead for connections between other elements of integrated circuit package  100 . For example, some of wirebond pads  112  can be used to provide connections between balls  114  of flip-chip integrated circuit die  106  and electric contacts  110  of substrate  102 . As another example, in embodiments where electrically conductive wires  124 B are not used, some of wirebond pads  112  can be used to provide connections between wirebond pads  116  of wirebond integrated circuit die  108  and electric contacts  110  of substrate  102 . 
     Integrated circuit dies  104 - 108  and electrically conductive wires  124  can be surrounded by an encapsulant  126 . 
     While  FIG. 1  depicts connections on two edges of each integrated circuit die  104 - 108 , three or more edges can connected as shown in  FIG. 1 . However, in some embodiments, the topmost wirebond integrated circuit die  108  is so large that one or more of its edges cannot be wirebonded. In these embodiments, a redistribution layer is used atop the topmost wirebond integrated circuit die  108  to connect the electric contacts  116  from the other edge. 
       FIG. 3  shows a side view, not necessarily drawn to scale, of an integrated circuit package  300  comprising a stack of three integrated circuit dies with a redistribution layer on the top die according to some embodiments of the present invention. As can be seen in  FIG. 3 , the left edge of the top die, wirebond integrated circuit die  108 , so overhangs the lower wirebond integrated circuit die  104  that wirebond connections are not possible for electric contacts  116  on that edge. In such embodiments, a redistribution layer (RDL)  302  is used to connect wirebond pads  116  on the left edge to some of the wirebond pads  116  on the right edge. 
       FIG. 4  shows a top view of redistribution layer  302  of  FIG. 3  according to some embodiments of the present invention. Redistribution layer  302  includes electric contacts  402  for connection to respective wirebond pads  116  on the left edge of wirebond integrated circuit die  108 , electric contacts  404  for connection to respective wirebond pads  116  on the right edge of wirebond integrated circuit die  108 , and electrically conductive traces  406  connecting respective electric contacts  402  and  404 . 
       FIG. 5  shows a process  500  for fabricating integrated circuit packages according to embodiments of the present invention. For example, process  500  can be used to fabricate integrated circuit package  100  of  FIG. 1  and integrated circuit package  300  of  FIG. 3 . For clarity, process  500  is discussed with reference to integrated circuit package  100  of  FIG. 1 . Although in the described embodiments, the elements of process  500  are presented in one arrangement, other embodiments feature other arrangements, as will be apparent to one skilled in the relevant arts after reading this description. 
     Referring to  FIG. 5 , process  500  provides substrate  102  comprising electric contacts  110  (step  502 ). Process  500  also provides wirebond integrated circuit die  104  comprising wirebond pads  112  (step  504 ). Process  500  mechanically couples wirebond integrated circuit die  104  to substrate  102  (step  506 ), for example using an adhesive such as silver epoxy and the like. Process  500  also electrically couples wirebond pads  112  of wirebond integrated circuit die  104  to electric contacts  110  of substrate  102  using electrically conductive wires  124 A (step  508 ). 
     Process  500  also provides flip-chip integrated circuit die  106  comprising balls  114  (step  510 ), and electrically couples balls  114  to wirebond pads  112  of wirebond integrated circuit die  104  using electrically conductive bumps  120  (step  512 ). In some embodiments, a redistribution layer  122  is used to electrically couple wirebond pads  112  to electrically conductive bumps  120 , as described above in detail with reference to  FIG. 2 . 
     Process  500  also provides wirebond integrated circuit die  108  comprising wirebond pads  116  (step  514 ), and mechanically couples wirebond integrated circuit die  108  to flip-chip integrated circuit die  106  (step  516 ), for example using an adhesive such as silver epoxy and the like. Process  500  also electrically couples wirebond pads  116  of wirebond integrated circuit die  108  to wirebond pads  112  of wirebond integrated circuit die  104  using electrically conductive wires  124 C (step  518 ), or electrically couples wirebond pads  116  to electric contacts  110  of substrate  102  using electrically conductive wires  124 B (step  520 ), or both. In some embodiments, a redistribution layer  302  is used to electrically couple wirebond pads  116  on one edge of wirebond integrated circuit die  108  to wirebond pads  116  on another edge, as described above in detail with reference to  FIG. 4 . 
     Finally, process  500  surrounds integrated circuit dies  104 - 108  and electrically conductive wires  124  with an encapsulant  126  (step  522 ). 
     A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

Technology Classification (CPC): 7