Patent Abstract:
An apparatus and method for generating an elevated output voltage. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of a first phase and the second switch couples the second boot node to the output node during a first portion of a second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 09/944,948, filed Aug. 30, 2001 now U.S. Pat. No. 6,414,882. 
    
    
     TECHNICAL FIELD 
     The present invention relates to voltage generating circuits, and, more particularly, to a method and circuit for generating a pumped output voltage from a low input voltage. 
     BACKGROUND OF THE INVENTION 
     In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, a typical application of a charge pump circuit is in a conventional dynamic random access memory (“DRAM”), to generate a boosted word line voltage VCCP having an amplitude greater than the amplitude of a positive supply voltage VCC or a negative substrate or back-bias voltage Vbb that is applied to the bodies of NMOS transistors in the DRAM. A charge pump may also be utilized in the generation of a programming voltage VPP utilized to program data into memory cells in non-volatile electrically block-erasable or “FLASH” memories, as will be understood by those skilled in the art. 
     FIG. 1 a  is a block diagram of a dynamic random access memory (“DRAM”)  100  including a charge pump circuit. The DRAM  100  includes an address decoder  102 , control circuit  104 , and read/write circuitry  106 , all of which are conventional. The address decoder  102 , control circuit  104 , and read/write circuitry  106  are all coupled to a memory-cell array  108 . In addition, the address decoder  102  is coupled to an address bus, the control circuit  104  is coupled to a control bus, and the read/write circuit  106  is coupled to a data bus. The pumped output voltage VCCP from a charge pump circuit  110  may be applied to a number of components within the DRAM  100 , as understood by those skilled in the art. In the DRAM  100 , the charge pump circuit  110  applies the pumped output voltage VCCP to the read/write circuitry  106 , which may utilize this voltage in a data buffer (not shown) to enable that buffer to transmit or receive full logic level signals on the data bus. The charge pump circuit  110  also applies the voltage VCCP to the address decoder  102  which, in turn, may utilize the voltage to apply boosted word line voltages to the array  108 . In operation, external circuitry, such as a processor or memory controller, applies address, data, and control signals on the respective busses to transfer data to and from the DRAM  100 . 
     FIG. 1 b  is a functional block diagram of an electrically erasable and programmable or FLASH memory  150  having an array  152  of FLASH cells (not shown), and including a charge pump  153 . When contained in a FLASH memory, the charge pump circuit  153  would typically generate a boosted programming voltage VPP that is utilized to program data into nonvolatile memory cells in the array  152 , as understood by those skilled in the art. The FLASH memory  150  includes an address decoder  154 , control circuit  156 , and read/program/erase circuitry  158  receiving signals on address, control, and data busses, respectively. The address decoder  154 , control circuit  156 , and circuitry  158  are conventional components, as understood by those skilled in the art. During programming, the control circuit  156  and read/program/erase circuitry  158  utilize the boosted voltage VPP generated by the charge pump circuit  153  to provide the mernory-cell array  152  with the required high voltage for programming FLASH memory cells in the array, as understood by those skilled in the art. The address decoder  154  decodes address signals applied on the address bus and utilizes the boosted voltage VPP to access corresponding FLASH memory cells or blocks of memory cells in the array  152 . The circuit  158  places read data from addressed cells in the array  152  onto the data bus during normal operation of the FLASH memory  150 . 
     FIG. 2 a  illustrates a conventional charge pump circuit  200 . A pulse generator  204 , typically driven by a clock signal CLK, provides pulse signals to a boot circuit  208  which generates a pumped voltage VCCP. The boot circuit  208  includes two pump stages  210  and  212  that operate in an interleaved fashion to provide a VCCP voltage at an output node  250 . The pump stages  210  and  212  are identical, and the following description of the pump stage  210  can be applied to the pump stage  212 . FIG. 2 b  shows a signal diagram illustrating the signals at a boot node  220  and a node  230 . Prior to time t 0 , the nodes  220  and  230  are pre-charged to VCC through transistors  270  and  272 , respectively. The gates of the transistors  270  and  272  are coupled to nodes  232  and  222 , respectively, to allow for the full VCC voltage to be applied to the respective nodes during pre-charge. Similarly, nodes  222  and  232  are pre-charged to VCC through transistors  274  and  276 , which have gates coupled to the nodes  230  and  220 , all respectively. 
     At time t 0 , the pulse generator  204  provides a HIGH output signal to the pump stage  210 . In response, the boot node  220  is booted through a capacitor  264 . Similarly, as seen in FIG. 2 b , a capacitor  260  boots the node  230  as well. However, note that the voltage at the node  230  is not sufficient to switch transistor  244  ON. Eventually, at a time t 1 , the pulse generator provides a HIGH output signal to the capacitor  262  to further drive the node  230 . At this time, the voltage on the node  230  is booted to a level sufficient to switch ON the transistor  244  in order to charge the output node  250 . From time t 1  to t 2 , the boot node  220  discharges into the output node  250 . At a time t 2 , in response to the signal applied to the capacitors  262  and  264  going LOW, the voltage of the nodes  220  and  230  go LOW as well. Although not shown in FIG. 2 b , the voltage of the nodes  222  and  232  of the pump stage  212  behave in a manner similar to that shown for the pump stage  210  during the time the pump stage  210  is inactive, that is, between times t 2  and t 3 . As a result, the output voltage VCCP can be maintained at a relatively constant elevated voltage level. 
     Although the conventional charge pump circuit  200  can provide a pumped voltage VCCP, the efficiency of the charge pump circuit  200  may become an issue as device operating voltages continue to decrease. In a sever case where the operating voltage is too low, the output of such a charge pump circuit may not be sufficient to drive the circuitry requiring pumped voltages. A simple solution has been to include multiple boot circuits to provide sufficient drive levels. However, this solution typically results in increased power consumption, and increased pump size, and consequently, increased die size, which are generally considered undesirable. Therefore, there is a need for a charge pump circuit that can efficiently generate a sufficient pumped output voltage from relatively a low supply voltage. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to an apparatus and method for generating an elevated output voltage in response a first set of pulses during a first phase and a second set of pulses during a second phase. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of the first phase and the second switch couples the second boot node to the output node during a first portion of the second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 a  and  1   b  are functional block diagrams of a DRAM and of a FLASH memory, respectively, according to the prior art. 
     FIG. 2 a  is a schematic diagram of conventional charge pump circuit, and FIG. 2 b  is a signal diagram illustrating various signals of the charge pump circuit of FIG. 2 a.    
     FIG. 3 is a schematic diagram illustrating a pulse generator according to an embodiment of the present invention. 
     FIG. 4 is a signal diagram illustrating the output of the pulse generator of FIG.  3 . 
     FIG. 5 is a schematic diagram illustrating a boot circuit according to an embodiment of the present invention. 
     FIG. 6 is a signal diagram illustrating various signals of the boot circuit of FIG.  5 . 
     FIG. 7 is a functional block diagram of a computer system including a memory device having a charge pump circuit according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the present invention are directed to an apparatus and method for generating an elevated output voltage from a relatively low input voltage. The apparatus conserves charge within the system of the apparatus to improve efficiency. Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
     FIG. 3 illustrates a pulse generator  300  according to an embodiment of the present invention. The pulse generator  300  includes an active low set-reset (S-R) latch  304  formed from cross-coupled NAND gates. A true signal of an input clock signal POSC is applied to a first input of the latch  304 , and a complement of the POSC signal is applied to a second input of the latch  304 . Provision of an appropriate clock signal is well understood by those of ordinary skill in the art, and will not be discussed in any greater detail herein in the interest of brevity. The outputs of the latch  304  are provided through respective inverters to a second S-R latch  308  also formed from cross-coupled NAND gates. A first output of the latch  308  is provided to a pulse circuit  312   a  and a second output is provided to a similar pulse circuit  312   b . The structure and operation of the pulse circuits  312   a  and  312   b  are identical, and consequently, the description of the pulse circuit  312   a  is applicable to the pulse circuit  312   b . As will be explained in more detail below, the operation of the pulse circuits  312   a  and  312   b  is in an interleaved fashion. 
     As discussed previously, the pulse circuit  312   a  has an input coupled to one of the outputs of the latch  308 . The input signal is provided to chain of inverters  320   a  having an output providing an output signal PH 1 A. The input signal is also provided to a pulse sub-circuit  324   a  having a delay circuit  326   a  The pulse sub-circuit  324   a  generates a pulse having a pulse width based on the delay of the delay circuit  326   a . The output of the pulse sub-circuit  324   a  is coupled to a chain of inverters  330   a  having an output that provides an output signal PH 2 B. The pulse circuit  312   a  further includes a NAND gate  332   a  having an input coupled to the output of the pulse sub-circuit  324   a  and another input coupled the output of the second inverter of the chain of inverters  320   a . The output of the NAND gate  332   a  is provided to a chain of inverters  334   a , which has an output that provides an output signal PH 2 C. 
     The output signals of the pulse generator  300  in response to the POSC signal are illustrated in FIG.  4 . The PH 1 A, PH 1 B, and PH 1 C signals are provided by the pulse circuit  312   a , and the PH 2 A, PH 2 B, and PH 2 C signals are provided by the pulse circuit  312   b . In response to a LOW POSC signal, the output signal of the latch  308  coupled to the pulse circuit  312   a  goes HIGH. The HIGH output signal of the latch  308  propagates through the chain of inverters  320   a  to provide a HIGH PH 1 A signal at time t 0 . The PH 1 B signal initially goes HIGH as well because the NAND gate  328   a  of the pulse sub-circuit  324   a  receives a HIGH signal at both its inputs. The PH 1 C signal remains low for the time being because of the HIGH and LOW signals applied to the inputs of the NAND gate  332   a . At a time t 1 , the HIGH output signal has eventually propagated through the inverter and the delay circuit  326   a  to the second input of the NAND gate  328   b , causing the PH 1 B signal to go LOW. As a result, the PH 1 C signal then goes HIGH because of the output of the NAND gate  332   b  is forced LOW in response to the output of the pulse sub-circuit  324   a  going HIGH. 
     When the POSC signal goes HIGH, the signal provided by the output of the latch  308  coupled to the pulse circuit  312   a  switches logic levels. In response, at time t 2 , the PH 1 A and PH 1 C signals go low. Concurrently, the output of the latch  308  that is coupled to the input of the pulse circuit  312   b  switches from LOW to HIGH. Consequently, as previously explained with respect to the pulse circuit  312   a , the PH 2 A and PH 2 B signals go HIGH. At time t 3 , the input signal to the pulse circuit  312   b  has propagated through the delay circuit  326   b  and caused the PH 2 B signal to go low. Additionally, as the output signal of the NAND gate  324   b  switches from LOW to HIGH, the PH 2 C signal goes HIGH. Eventually, when the POSC signal goes LOW again, the PH 2 A and PH 2 C signals return LOW at time a t 4 . 
     FIG. 5 illustrates a boot circuit  500  according to an embodiment of the present invention. The boot circuit can be coupled to the phase generator  300  illustrated in FIG. 3 to create a charge pump circuit. The boot circuit  500  include two pump circuits  504   a  and  504   b . Operation of the two pump circuits can generally be described as being interleaved, that is, the output node of the boot circuit  500  is driven by one of the pump circuits  504   a  and  504   b  at a given time. As will be explained in more detail below, the two pump circuits  504   a  and  504   b  are coupled so that excess charge of a boot node of one of the pump circuits is discharged into the boot node of the other pump circuit after driving the output node. This is in contrast with the conventional charge pump, where any excess charge on the boot nodes of the respective pump circuits are simply left to discharge to a lower potential. As a result of conserving charge within the boot nodes of the boot circuit  500 , output current of the boot circuit  500  can be maintained at a lower operating voltage. Similarly, the operating voltage can be maintained, but power consumption would be reduced while providing the same output current. 
     The two pump circuits  504   a  and  504   b  are essentially identical, and consequently, the description of the structure of the pump circuit  504   a  applies to the pump circuit  504   b  as well. The pump circuit  504   a  includes three pump stages  520   a ,  530   a , and  540   a , each driven by a different output signal of the phase generator to which the boot circuit  500  is coupled. Where the boot circuit  500  is coupled to the phase generator  300  (FIG.  3 ), pump stage  520   a  is driven at a node  521   a  by the PH 1 A signal, the pump stage  530   a  is driven at a node  531   a  by the PH 1 B signal, and the pump stage  540   a  is driven at a node  541   a  by the PH 1 C signal. The signals are used to pump the charge of a node coupled to a respective capacitor. As illustrated in FIG. 5, the PH 1 A signal is used to increase the charge of a boot node  522   a  through a boot capacitor  525   a . The PH 1 B signal is used to increase the charge of nodes  532   a  and  533   a  through capacitors  537   a  and  538   a , respectively, and the PH 1 C signal is used to increased the charge of nodes  542   a  and  543   a  through capacitors  546   a  and  547   a , respectively. Each of the nodes  522   a ,  532   a ,  533   a ,  542   a , and  543   a  are pre-charged to at least a voltage of (VCC−Vt) through a respective diode connected transistor  510 . Additionally, the nodes  522   a ,  532   a ,  533   a , and  542   a  are further pre-charged through a respective transistor coupled to VCC and having a gate driven by node  533   b  of the pump circuit  504   b , and the node  543   a  is further pre-charged through transistor  544   a  having a gate coupled to the node  533   a.    
     As mentioned previously, excess charge of the boot node of one pump circuit is discharged to the boot node of the other pump circuit in order to conserve charge within the entire boot circuit  500 . With respect to the pump circuit  504   a , the boot node  522   a  receives the excess charge from the boot node  522   b  through the transistor  523   a . The gate of the transistor  523   a  is also controlled by the voltage of a node in the pump circuit  504   b , namely, the node  543   b.    
     In addition to sharing excess charge of the boot nodes of the pump circuits  504   a  and  504   b , the nodes coupled to the gates of the transistors that couple the respective boot nodes to output node  550  are additionally pre-charged by a voltage provided by the other pump circuit. For example, the node  532   a , which is coupled to the gate of the transistor  552   a , is pre-charged by the node  534   b  of the pump circuit  504   b . The additional charge on the node driving the transistor that couples a boot node to the output node  550  allows for the full charge of the boot node to be provided to the output node  550  without being limited by a relatively low gate voltage. 
     Operation of the boot circuit  500  will be explained with reference to the signal diagram of FIG.  6 . It will be assumed that the boot circuit  500  is receiving input signals from a phase circuit providing clock signals according to the timing diagram of FIG. 4, for example, the phase circuit  300  (FIG.  3 ). Specifically, the PH 1 A, PH 1 B, and PH 1 C signals are applied to the nodes  521   a ,  531   a , and  541   a , respectively, of the pump circuit  504   a . The PH 2 A, PH 2 B, and PH 2 C signals are applied to the nodes  521   b ,  531   b , and  541   b , respectively, of the pump circuit  504   b.    
     As illustrated in FIGS. 4 and 6, the first pump phase is defined between times t 0  and t 1 , and the second pwnp phase is defined between times t 2  and t 4 . At the time t 0 , the PH 1 A and PH 1 B signals go HIGH (FIG.  4 ), thus, booting up the boot node  522   a  (the P 1 A signal) and the nodes  532   a  (the P 1 B 1  signal) and  533   a  (the P 1 B 2  signal, not shown), respectively (FIG.  6 ). As illustrated in FIG. 6, and as will be explained in more detail below, the boot node  522   a  is pre-charged by the excess charge from the boot node  522   b  (the P 2 A signal) from the previous pump phase. The P 1 B 1  signal switches ON the transistor  552   a  to couple the boot node  522   a  to the output node  550 . The boot node  522   a  discharges into the output node  550  and pulls down the node  532   a  through series connected diode coupled transistors  514   a  until the P 1 B 1  signal goes LOW in response to the PH 1 B signal going LOW (FIG. 4) at time t 1 . The PH 1 C signal goes HIGH concurrently, booting up the nodes  542   a  and  543   a . This in turn switches ON both transistors  523   b  and  535   b . The transistor  523   b  allows for the excess charge of the boot node  522   a  from the present pump phase to be discharged into the boot node  522   b  in preparation for the following pump phase. As illustrated in FIG. 6, during times t 1  to t 2 , the P 1 A signal discharges as the P 2 A signal charges. The transistor  535   b  couples the node  543   a  to the node  532   b  (the P 2 B 1  signal) for pre-charging the node in preparation for the second pump phase. 
     At time t 2 , the PH 1 A and PH 1 C signals go LOW and the PH 2 A and PH 2 B signals go HIGH. Consequently, the boot node  522   b , and the nodes  532   b  and  533   b , are charged, and the P 2 A, P 2 B 1 , and P 2 B 2  signals, respectively, are booted by the active signals. As mentioned previously, during the previous pump phase, both the boot node  522   b  and the node  532   b  are pre-charged prior to the PH 2 A and PH 2 B signals going HIGH by discharging the boot node  522   a  and the node  543   a  of the boot circuit  504   a . Thus, the overall voltage of the boot node  522   b  and the node  532   b  is greater than would be if the charge was not conserved within the boot circuit  500 . The P 2 B 1  signal switches ON the transistor  552   b  to couple the boot node  522   b  to the output node  550 . The boot node  522   b  begins to discharge into the output node  550  to drive the VCCP signal. Note that the P 2 B 1  signal decreases as the boot node  522   b  (the P 2 A signal) discharges because of the diode coupled transistors  514   b . Further note that the P 2 C 2  signal increases during times t 2  and t 3  because the P 2 B 2  signal, which is booted by PH 2 B signal, drives the gate of the transistor  544   b  so that the full voltage of VCC can be applied to the node  543   b.    
     At time t 3 , the PH 2 B signal goes LOW, switching OFF the transistor  552   b . Concurrently, the PH 2 C signal goes HIGH, driving the voltage on the nodes  542   b  and  543   b  (the P 2 C 1  and P 2 C 2  signals, respectively). The P 2 C 2  signal switches ON the transistor  523   a  to couple the boot node  522   b  to the boot node  522   a  in order to pre-charge that node with any excess charge. The conservation of charge is illustrated in FIG. 6, that is, as the P 2 A signal decreasing between time t 3  and t 4  while the P 1 A signal correspondingly increases. The P 1 C 2  signal also switches ON the transistor  535   a  to allow the P 2 C 2  signal to precharge the node  532   a  (the P 1 B 1  signal) in preparation of the next pump phase of the charge pump. At time t 4 , the PH 2 A and PH 2 C signals go LOW, and the PH 1 A and PH 1 B signals go HIGH again to repeat the first pump phase. 
     In another embodiment of the present invention, multiple boot circuits and/or multiple pulse circuits can be utilized to provide an elevated voltage to a device. For example, multiple charge pump circuits can be operated in a staggered fashion in order to provide a sufficient pumped voltage level. Alternatively, multiple boot circuits coupled to a pulse circuit can be utilized as well. 
     It will be appreciated that although the previous description of the boot circuit  500  was made with reference to the pulse generator  300 , modifications may be made to the particular structure of the boot circuit  500  and the pulse generator  300  without departing from the scope of the present invention. It will be further appreciated that although the use of charge pump circuits has been made with respect to DRAM and FLASH memory, in particular, one skilled in the art will realize the charge pump circuit may be utilized in any type of integrated circuit requiring a pumped voltage, including other types of volatile and non-volatile memory devices. 
     FIG. 7 is a block diagram of a computer system  700  including computing circuitry  702 . The computing circuitry  702  contains a memory  701 , that can be a volatile memory, such as a DRAM, or a non-volatile memory, such as a FLASH memory. The computing circuitry  702  could also contain both a DRAM and FLASH memory. The memory  701  includes charge pump circuitry according to embodiments of the present invention. The computing circuitry  702  performs various computing functions, such as executing specific software to perform specific calculations or tasks. In addition, the computer system  700  includes one or more input devices  704 , such as a keyboard or a mouse, coupled to the computer circuitry  702  to allow an operator to interface with the computer system. Typically, the computer system  700  also includes one or more output devices  706  coupled to the computer circuitry  702 , such output devices typically being a printer or a video terminal. One or more data storage devices  708  are also typically coupled to the computer circuitry  702  to store data or retrieve data from external storage media (not shown). Examples of typical storage devices  708  include hard and floppy disks, tape cassettes, and compact disc read-only memories (CD-ROMs). The computer circuitry  702  is typically coupled to the memory device  701  through appropriate address, data, and control busses to provide for writing data to and reading data from the memory device. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, some of the components described above may be implemented using either digital or analog circuitry, or a combination of both. Therefore, the present invention is to be limited only by the appended claims.

Technology Classification (CPC): 6