Patent Abstract:
A logic system for performing scan test with single scan clock and related method. The logic system includes a first clock domain, which performs logic operations and scan tests with a first clock signal, and a second clock domain, which performs logic operations witha second clock signal and performs scan tests withthe first clock signal.

Full Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a multiple clock domain logic system, and more particularly, to a system and method for performing scan tests with a single scan clock.  
         [0003]     2. Description of the Prior Art  
         [0004]     Digital logic circuits are commonly applied in many electronic devices. A digital logic circuit includes combinational circuits and sequential circuits. The combinational circuits generate output signals according to current input signals. The sequential circuits, which have memory functionality, can generate output signals according to previous input signals along the time axis.  
         [0005]     Devices for circuit debugging and testing are usually required when designing and producing a digital logic circuit. Circuit testing devices in the art include a plurality of flip flop scan cells (as shown in  FIG. 1 ) linked together to form a scan chain (such as the scan chain  200  shown in  FIG. 2 ). Loading predetermined logic values into a scan chain to debug a digital logic circuit is known as a scan test.  
         [0006]     Please refer to  FIG. 1  showing a block diagram of a D-type flip flop scan cell  100  in the prior art. The D-type flip flop scan cell  100  comprises a D-type flip flop  102  and a multiplexer  104  for selectively outputting a function input signal D or a scan input signal SI according to a scan enable signal SE. When the scan enable signal SE is in a scan enable state, the multiplexer output end  138  sends the scan input signal SI to the D-type flip flop  102 . When the scan enable signal SE is in a scan disable state, the multiplexer output end  138  sends the function input signal D to the D-type flip flop  102 . The D-type flip flop  102  outputs a corresponding output signal through an output end  116  according to the inputted signal received from the multiplexer  104  or outputs a corresponding complementary output signal through a complementary output end  118  according to the inputted signal received from the multiplexer  104 . Please refer to  FIG. 2  showing a scan chain  200  in the prior art. A plurality of D-type flip flop scan cells  210 ,  230  is linked together to form a scan chain  200 . A scan input end  234  of the next D-type flip flop scan cell  230  is electrically connected with a data output end  220  of the previous D-type flip flop scan cell  210  to form the scan chain  200 . When the scan enable signal is in a scan enable state, the scan input signal is inputted into the scan chain  200  sequentially according to a clock signal Clk. The goal in providing the sequential circuits, such as the D-type flip flop scan cells  210 ,  230 , with predetermined logic values respectively to debug the logic system is accomplished.  
         [0007]     Some logic systems need at least two clock signals for synchronization. The combination of devices operating according to the same clock signal is defined as a clock domain. Accordingly, a logic system of this kind includes at least two clock domains. The devices of each clock domain operate according to the clock signal of a specific frequency corresponding to the clock domain.  
         [0008]     A multiple clock domain logic system  500  is shown in  FIG. 3 . The D-type flip flop scan cells  512 ,  514 ,  516 ,  522 ,  524 ,  532  of the logic system  500  rely on the clock signals of different frequencies as the base for synchronization so that the scan cells  512 ,  514 ,  516 ,  522 ,  524 ,  532  belong to the different clock domains  510 ,  520 ,  530 . Hence when the multiple clock domain logic system  500  of the prior art is performing a scan test, the clock domains  510 ,  520 ,  530  receive the scan input signals scan_in_ 1 , scan_in_ 2 , scan_in_ 3  respectively to perform the scan test and output the scan output signals scan_out_ 1 , scan_out_ 2 , scan_out_ 3  respectively. Please refer to  FIG. 4 . Corresponding to the number of the scan input signals scan_in_ 1 , scan_in_ 2 , scan_in_ 3  and the scan output signals scan_out_ 1 , scan_out_ 2 , scan_out_ 3 , a scan test equipment should include enough number of input ports and output ports for performing the scan test. However, the price of the scan test equipment corresponds to the amount of scan input signals scan_in_ 1 , scan_in_ 2 , scan_in_ 3  and scan output signals scan_out_ 1 , scan_out_ 2 , scan_out_ 3 . Furthermore, while loading a shorter scan chain with one of the scan signals is completed during a scan test, only a part of loading a longer scan chain with one of the scan signals is completed so that the input ports and the output ports corresponding to the shorter scan chain are idling and waiting for the full completion of loading the longer scan chain. As a result, the scan test equipment is not fully utilized while shortening the time for the scan test is impossible.  
         [0009]     Known in the art, a conventional apparatus for linking the scan chains of different clock domains with latches is shown in  FIG. 5 . The elements of  FIG. 5  correspond to the elements of  FIG. 3  while the scan chains of different clock domains are linked with D latches  702 ,  704 . However, all clock signals clk 1 , clk 2 , clk 3  should be provided for performing the scan test of the multiple clock domain logic system  700 , and the arrangement of the scan chains in  FIG. 5  should be first linking the D-type flip flop scan cells of the same clock domain and second linking the clock domains according to the order of the frequencies of the clock signals of the clock domains; rather than first adjusting the amount of the scan chains according to the amount of input ports and output ports and second equalizing the lengths of the scan chains to load the scan chains in parallel to solve the problem of the idling status of the input ports and the output ports. As a result, the known in the art apparatus of linking the scan chains of different clock domains with latches is not a solution of the above-mentioned problem.  
       SUMMARY OF INVENTION  
       [0010]     It is therefore a primary objective of the claimed invention to provide a system and method for performing scan tests with a single scan clock to solve the above-mentioned problem.  
         [0011]     The present invention provides a logic system for performing scan tests with a single scan clock and a related method. The system includes a first clock domain for performing logic operations and scan tests with a first clock signal. The first clock domain includes a first clock input for inputting the first clock signal. Further included is a multiplexer for selectively outputting the first clock signal or a second clock signal according to a mode signal. The system further includes a second clock domain for performing logic operations with the second clock signal and for performing scan tests withthe first clock signal.  
         [0012]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0013]      FIG. 1  is a block diagram of a D-type flip flop scan cell according to the prior art.  
         [0014]      FIG. 2  is a block diagram of a scan chain according to the prior art.  
         [0015]      FIG. 3  is a block diagram of a multiple clock domain logic system according to the prior art.  
         [0016]      FIG. 4  is a scan chain diagram of the multiple clock domain logic system of  FIG. 3 .  
         [0017]      FIG. 5  is a block diagram of a multiple clock domain logic system according to the prior art.  
         [0018]      FIG. 6  is a block diagram of the multiple clock domain logic system according to the first embodiment of the present invention.  
         [0019]      FIG. 7  is a clock tree diagram of the multiple clock domain logic system of  FIG. 6 .  
         [0020]      FIG. 8  is a block diagram of a D-type flip flop scan cell according to the second embodiment of the present invention.  
         [0021]      FIG. 9  is a scan chain diagram of the multiple clock domain logic system according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0022]     When the multiple clock domain logic system according to the present invention performs logic operations, each clock domain performs logic operations according to the corresponding clock signal. When the system performs scan tests, all clock domains are linked together to perform scan tests according to the same clock signal.  
         [0023]      FIG. 6  is a block diagram of a multiple clock domain logic system  900  for performing scan tests with a single scan clock according to the present invention.  FIG. 6  illustrates a multiple clock domain logic system  900  for performing logic operations with a first clock signal clk 1 , a second clock signal clk 2 , and a third clock signal clk 3  and for performing scan tests with the first clock signal clk 1 . The logic system  900  comprises a first clock domain  910  for performing logic operations and scan tests with the first clock signal clk 1 . The first clock domain  910  comprises a first clock input end  912  for inputting the first clock signal clk 1 . The logic system  900  further comprises a second clock domain composite module  902  comprising a second multiplexer  940  for selectively outputting the first clock signal clk 1  or the second clock signal clk 2  as a second clock domain driving signal. The second clock domain composite module  902  further comprises a second clock domain  920  for performing logic operations with the second clock signal clk 2  and for performing scan tests with the first clock signal clk 1 . The second clock domain  920  comprises a second clock input end  922  electrically connected to an output end  948  of the second multiplexer  940  for inputting the first clock signal clk 1  or the second clock signal clk 2 . In this embodiment, the logic system  900  further comprises a third clock domain composite module  903  which is similar to the second clock domain composite module  902  so further details in structure are therefore not repeated. The third clock domain  930  performs logic operations with the third clock signal clk 3  and performs scan tests with the first clock signal clk 1 .  
         [0024]     Please refer to  FIG. 7  showing a clock tree diagram of the multiple clock domain logic system  900  in  FIG. 6 . The first clock domain  910  comprises a plurality of D-type flip flop scan cells  914 ,  916 ,  918  for performing logic operations and scan tests according to the first clock signal clk 1 . Each D-type flip flop scan cells  914 ,  916 ,  918  comprises a scan cell clock input end for inputting the first clock signal clk 1 . When logic operations are performed, the second multiplexer  940  selectively output the second clock signal clk 2  to the second clock domain  920  according to a mode signal tmode, and the third multiplexer  950  selectively output the third clock signal clk 3  to the third clock domain  930  according to the mode signal tmode. Therefore, D-type flip flop scan cells  924 ,  926  of the second clock domain  920  and a D-type flip flop scan cell  934  of the third clock domain  930  perform logic operations respectively according to the second clock signal clk 2  and the third clock signal clk 3 . When scan tests are performed, the second multiplexer  940  and the third multiplexer  950  selectively output the first clock signal clk 1  to the second clock domain  920  and the third clock domain  930  according to the mode signal tmode. As a result, all of the D-type flip flop scan cells  924 ,  926  of the second clock domain  920  and the D-type flip flop scan cell  934  of the third clock domain  930  perform scan tests according to the first clock signal clk 1 .  
         [0025]     The characteristic that clock signals arriving at corresponding D-type flip flop scan cells at the same time is so-called clock tree balance characteristic. Further, the characteristic that clock signals arriving at corresponding D-type flip flop scan cells at almost the same time is called clock tree quasi-balance characteristic. Please refer to  FIG. 7 . In this embodiment, buffers  962 ,  964 ,  966 ,  968 ,  970 ,  972 ,  974  are installed to make the system  900  have the clock tree balance characteristic or the clock tree quasi-balance characteristic with respect to the first clock signal clk 1  so that a clock skew phenomenonof the system  900  is avoided. That is, the asynchrony phenomenon—that clock signals cannot reach corresponding elements at the same time is avoided.  
         [0026]     Please refer to  FIG. 8  showing a block diagram of a D-type flip flop scan cell according to the second embodiment of the present invention. The difference between the second embodiment and the first embodiment is that a clock signal multiplexer is installed in each D-type flip flop scan cell of the second embodiment for selectively inputting a clock signal into the scan cell. For example, the D-type flip flop scan cell  924  of the second clock domain comprises a clock signal multiplexer for selectively outputting the first clock signal clk 1  or the second clock signal clk 2  to the D-type flip flop installed in the scan cell  924  according to the mode signal tmode. When performing logic operations, the scan enable signal SE selects the function input signal D and the mode signal tmode selects the second clock signal clk 2  (CK 2  of  FIG. 8 ) for the D-type flip flop installed in the scan cell  924 . When performing scan tests, the scan enable signal SE selects the scan input signal SI and the mode signal tmode selects the first clock signal clk 1  (CK 1  of  FIG. 8 ) for the D-type flip flop installed in the scan cell  924 . Therefore, the second embodiment fulfills the goal of the present invention by providing the apparatus of the D-type flip flop scan cell shown in  FIG. 8  rather than installing the multiplexers  940 ,  950  for the corresponding clock domains  920 ,  930  illustrated in the first embodiment.  
         [0027]     Please refer to  FIG. 9  showing a scan chain diagram of the multiple clock domain logic system  900  according to the present invention. When scan tests are performed, the D-type flip flop scan cells  914 ,  916 ,  918 ,  924 ,  926 ,  934  in different clock domains are linked together to form at least one scan chain. The scan input end (SI) of the next D-type flip flop scan cell is electrically connected to the data output end (Q) of the previous D-type flip flop scan cell so that the output signal of the previous scan cell is the scan input signal of the next scan cell. Firstly the scan input signal scan_in is inputted through the D-type flip flop scan cell  914 , into the first scan cell  914  of the scan chain. Accordingly, the scan input signal scan_in shifts along the scan cells of the scan chain. Therefore, the D-type flip flop scan cells  914 ,  916 ,  918 ,  924 ,  926 ,  934  receive logic values carried by the scan input signal scan_in respectively, and output a scan output signal scan_out carrying the scan cell calculation result namely the scan test result.  
         [0028]     In contrast to the prior art, all the D-type flip flop scan cells of the multiple clock domain logic system  900  according to the present invention perform scan tests with the same clock signal, the first clock signal clk 1 , so that it is permissible firstly to adjust the number of scan chains according to the number of input ports and output ports of the scan test equipment and secondly to equalize the lengths of the scan chains to load the scan chains in parallel to solve the prior art problem of the idling status of the input ports and the output ports. As a result, the amount of the input ports and the output ports can be minimized so that the cost of scan test is reduced.  
         [0029]     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 6