Patent Abstract:
Chopper stabilized amplifiers combining low clock noise and linear frequency characteristics. The chopper stabilized amplifiers are used in offset correction circuitry, with the output of the chopper stabilized amplifiers being integrated by an integrator. The integrator operates on alternate cycles, with a sample and hold circuit sampling the integrator output when the integrator is not integrating, with the output of the sample and hold being coupled to the main amplification path to cancel offset after at least some amplification is achieved. Autozeroing of amplifiers in the offset correction circuitry is also disclosed. The invention is applicable to operational amplifiers and instrumentation amplifiers.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Patent Application No. 60/844,734 filed Sep. 15, 2006. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of chopper stabilized operational and instrumentation amplifiers. 
     2. Prior Art 
     Chopper stabilized operational and instrumentation amplifiers are well known in the prior art. In a typical operational amplifier, the signal amplification path includes a plurality of cascaded amplifiers, or stages of amplification defining the signal path. If the amplifier input were shorted, the input offset primarily of the first amplifier or stage would be amplified, typically to saturate the output of the operational amplifier. When used in a feedback circuit, this does not happen, but instead the input offset causes the input to the amplifier to effectively be equal to the actual input to the circuit shifted by an amount equal to the input offset. Ideally, with a very high DC gain in the signal path, the input to an operational amplifier circuit in a feedback application will be very near zero, substantially independent of the operational amplifier output. 
     The input offset of integrated circuit operational amplifiers is reasonably low and satisfactory for many applications, but not the higher precision applications. Using an operational amplifier as an example, in the prior art, in order to cancel at least part of the input offset, the input of a chopper amplifier is also coupled to the amplifier input, with the output of the chopper amplifier being integrated and the output of the integrator being combined with the signal in the signal path after at least some signal path amplification. Since the main contributor of offset in the signal path is the input or first amplifier in the cascaded amplifiers, injection of the offset correction after at least the first stage of the cascaded amplifiers substantially reduces the effective input offset of the cascaded amplifiers in the signal path. If the gain of the chopper amplifier path is high, it will even cancel the offset of cascaded stages following that input stage. The chopper amplifier (input and output choppers enclosing an amplifier) converts the input offset to AC by the input chopper and amplifies the AC, with the output chopper operating at the same frequency reconverting AC to DC responsive to the input offset in the signal path for integration and then injection into the signal path. The net effect is that any input offset of the cascaded amplifiers defining the signal path results in an input to the integrator, which integrates the input offset and injects a DC result into the signal path to drive and maintain the input offset of the cascaded amplifiers substantially at zero. This is a substantial improvement in input offset of higher precision operational amplifiers and instrumentation amplifiers. 
     However, there are various other sources of offset as well as sources of noise in such a configuration. Not only is offset undesirable because of its effect on accuracy, but also chopper induced noise is undesirable, and may cause problems especially in systems capable of responding to such frequencies or whose performance is degraded by noise in the system. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is block diagram of a current mode instrumentation amplifier (CMIA) which may incorporate the present invention. 
         FIG. 2  illustrates a three stage amplifier topology which may incorporate the present invention. 
         FIG. 3  illustrates a chopper stabilized version of a three stage amplifier which may incorporate the present invention. 
         FIG. 4   a  illustrates the incorporation of a sample and hold function in the offset correction path of an operational amplifier. 
         FIGS. 4   b  and  4   c  illustrate the incorporation of a sample and hold function in the offset correction path of an instrumentation amplifier. 
         FIG. 5   a  illustrates a 12 dB roll-off at low frequencies. 
         FIG. 5   b  illustrates the elimination of the 12 dB roll-off at low frequencies of  FIG. 5   a.    
         FIG. 6  illustrates the effect of parasitic capacitance in the chopper input offset correction path. 
         FIG. 7   a  illustrates the implementation of an autozero on the chopper amplifier and sample and hold in the correction path of an instrumentation amplifier. 
         FIG. 7   b  illustrates the implementation of an autozero on the chopper amplifier and sample and hold in the correction path of an operational amplifier. 
         FIG. 7   c  illustrates an instrumentation amplifier similar to the instrumentation amplifier of  FIG. 7   a  and incorporating additional coupling capacitors in the offset correction path. 
         FIGS. 8   a  through  8   d  illustrate a noise simulation for an exemplary embodiment of the present invention. 
         FIG. 9  is an exemplary timing diagram for the embodiment of  FIG. 7   a.    
         FIG. 10  illustrates one alternate timing diagram. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The low-offset instrumentation amplifier designs of the present invention contain a technique that combines chopper-noise suppression with a linear (in dB) frequency characteristic. The technique uses a sample-and-hold circuit to reduce the chopper-ripple-noise, the noise being the result of the offset of the chopper sense amplifier which is not fully suppressed by the integrator behind it. This sample and hold circuit is embedded in a frequency-compensation topology in a way that ensures a linear 6 dB/oct roll-off (see U.S. Patent Application Publication No. 2006/0176108 entitled “Frequency Stabilization of Chopper-Stabilized Amplifiers”, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated by reference). 
     This technique of chopper-noise suppression can be generally applied in low-offset chopper-stabilized operational amplifiers, instrumentation amplifiers, and sense amplifiers. 
     Topology Overview 
     One embodiment is a current mode instrumentation amplifier (CMIA). The key application is high side current sense amplifier as shown in  FIG. 1 . 
     Design challenges for an exemplary application:
         Low offset voltage   High CMRR+accuracy+bandwidth         CMIA   Gain depends on R1 and R2         gm3=gm4         matching       

     A three stage amplifier topology is chosen as shown in  FIG. 2  to achieve the high DC open loop gain needed for accuracy. A chopper stabilized version of a three stage amplifier is shown in  FIG. 3 . 
     To achieve a unity gain frequency of 1 MHz with a 100 pF load and a gain margin of 60°, the following exemplary values are chosen: 
     
       
         
           
             
               
                 
                   
                     
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                           ( 
                           
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             Cm2=32 pF 
           
         
       
    
     First assume offsets V os,eq ≈V os3 +V os4 ≈20 mV, while Vos 6 , Vos 7  and Vos 8  are zero. 
     The integrator built around gm 6  and Cint will integrate a current until Vfb=Vin, thus inducing a voltage Vint, which will induce a current through gm 5  to compensate the error current caused by the offset sources Vos 3  and Vos 4 . This assumed that gm 7  and gm 8  are equal. 
     If gm 7  is not present, gm 8  would charge the integrator until V fb =0, and the output voltage would be approaching zero. 
     Another way to look at this circuit: The high voltage gain, low bandwidth amplifier gm 7 ,  8 ; gm 6 ; gm 5 ; gm 2 ; gm 1  dominates at low frequencies and will therefore dominate the offset performance, while the lower voltage gain, high bandwidth path gm 3 ,  4 ; gm 2 ; gm 1  will achieve the high bandwidth. 
     However Vos 7  and Vos 8  are not zero. The choppers will modulate these offsets, creating an offset-less amplifier for DC. The offsets will create square wave current at the input of the integrator gm 6  and triangular wave voltage at the output gm 6 . 
     Assume Cint=32 pF gm 7 =gm 8 =25 uA/V gm 5 =2.5 uA/V which is 40 times lower than gm 3 , 4 . Thus the DC component of Vint will need to be 40 times higher than Vos 3 , 4             0.8V in order to fully compensate the offset.
     If Vos 7 , 8 =20 mV and the chopper frequency fc=16 kHz, then the top voltage of the triangular wave at Vint and Vfb ( FIG. 3 ) would be: 
     
       
         
           
             
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     A concern is that the output of gm 6  can drive both the dc component to compensate Vos 3  and Vos 4 , and the triangular wave. Moreover, the triangular wave will produce a ripple at the system output (clock noise), which is undesirable. 
     An important way to reduce this output ripple is: 
     To transform the residual triangular wave Vint to a signal in which there is no AC component. Implementing a sample and hold function behind the integrator in the offset correction loop as shown in  FIG. 4   a  for an operational amplifier, and as shown in  FIGS. 4   b  and  4   c  for an instrumentation amplifier can do this. 
     The capacitor CM 6  ( FIG. 4   c ) is implemented for frequency compensation. It is connected to the virtual ground input of the active integrator. The capacitor and active integrator are part of the frequency compensation topology in combination with choppers See U.S. Patent Application Publication No. 2006/0176108 entitled “Frequency Stabilization of Chopper-Stabilized Amplifiers”, hereinbefore incorporated by reference and referred to here for frequency compensation techniques for eliminating the 12 dB roll-off at low frequencies of  FIG. 5   a  to obtain the linear 6 dB roll-off of  FIG. 5   b.    
     The sample and hold circuit works closely together with this frequency-compensation topology to strongly reduce the clock ripple, while it does not destroy the straight 6 dB/oct rolloff under certain conditions. The following describes improvements on the circuits of  FIG. 4 . 
     If now Vos 6 ≠0, and assume that there is a parasitic capacitance C at the output of gm 7 , 8 , this will induce a residual input offset voltage. This may be explained as follows. 
     Assuming the parasitic capacitance C will be charged with + or −Vos 6 , resistor R of  FIG. 6  can be viewed as a switched capacitor resistor, as follows: 
     
       
         
           
             R 
             = 
             
               1 
               
                 4 
                 ⁢ 
                 fcC 
               
             
           
         
       
     
     Through this resistor a current 
             I   =       2   ⁢     V     os   ⁢           ⁢   6         R           
will flow. The system now needs an equivalent input offset voltage to compensate for the capacitor current.
 
     
       
         
           
             
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                     ⁢ 
                     
                         
                     
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                       7,8 
                     
                   
                 
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                 ⁢ 
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     If Vos 6 =10 mV, gm 7 , 8 =25 uA/V, fc=16 kHz and C=0.4 pF (optimistic guess), then Voff,eq=10.24 uV. 
     Conclusion: this must be corrected. 
     Which means making the parasitic C&lt;0.4 pF by way of careful design and layout, making gm 7  and gm 8  larger and the chopper frequency lower, which would mean that the integrator cap should become larger, to accommodate the larger ripple. 
     A fundamentally better solution is to cancel Vos 6 . Therefore in preferred embodiments, an autozero around gm 6  is implemented, as in  FIG. 7   a.    
     In the instrumentation amplifier of  FIG. 7   a  the functions of integration and autozeroing are combined around gm 6 . The sample and hold function is implemented before gm 5  by Csh. 
     Another way to reduce the clock ripple is to autozero the chopper amplifiers gm 7  and gm 8 . This is also shown in  FIG. 7   a . The autozeroing of the chopper amplifiers is optional, but desirable for best performance, as is the autozeroing of the integrator amplifier. In that regard, the sample and hold essentially eliminates the AC ripple at the chopper frequency, while the autozeroing improves the DC offset, separate parameters. Autozeroing of the chopper amplifiers is also a remedy against residual offset caused by clock skew, when the chopper clock does not have a 50% duty cycle. 
     Switches are shown in  FIG. 7   a  for the sample and hold of the output of the integrator as well as for the autozeroing of the integrator amplifier gm 6  and of the choppers CH 2   a  and CH 2   b  and CH 1  around the chopper amplifiers gm 7  and gm 8 . 
     The noise simulation of the exemplary embodiment is shown in  FIGS. 8   a  through  8   d.    
     The input transconductance amplifiers gm 3 , gm 4 , gm 7  and gm 8  may be in accordance with U.S. patent application Ser. No. 11/054,140 entitled “Accurate Voltage to Current Converters for Rail-Sensing Current-Feedback Instrumentation Amplifiers” filed on Feb. 8, 2005 and assigned to the assignee of the present invention, the disclosure of which is also hereby incorporated by reference. 
     The performance of the instrumentation amplifier of  FIG. 7   a  may be improved by adding additional coupling capacitors in the offset correction loop shown in  FIG. 7   c . In particular, while not shown, there will be some parasitic capacitance on the inputs to gm 7  and gm 8 . Because in the circuit of  FIG. 7   a , gm 8  has a capacitively coupled input (Caz 81  and Caz 82 ) and gm 7  does not, this lack of symmetry will cause an error easily corrected by capacitively coupling the input to gm 7  also, as shown in  FIG. 7   c . The addition of matching coupling capacitors Caz 71  and Caz 72  provides symmetry to eliminate this source of error, and otherwise does not effect the operation of the circuit. 
     For an operational amplifier, the circuit of  FIG. 7   a  may be altered by the elimination of gm 4 , gm 7  and the associated chopper CH 2   a  and associated switches, as shown in  FIG. 7   b . Again the autozeroing of the chopper amplifier and the autozeroing of the integrator amplifier are optional. 
       FIG. 9  is an exemplary timing diagram for the embodiment of  FIG. 7   a . The amplifier clock (oscillator) is divided by 2 to control the integrator, the integrator integrating when the integrator control is high, and having its input disconnected when low. The integrator, when integrating, will integrate the square wave output of the chopper over one full cycle of the chopper, giving the triangular wave form shown as Integrator out. During the next full chopper cycle, the integrator input is disconnected, so the integrator output does not change. At the end of each integration, the sample and hold (SH) is clocked, storing the output of the integrator on the holding capacitor SH. Then the integrator capacitors are disconnected from the output of the integrator (Integrator Cap high), after which the integrator amplifier gm 6  is autozeroed. The chopper amplifiers CH 2   a  and CH 2   b  are autozeroed when the integrator is not integrating, namely on the inverse of the integrator control (“not as gm 7  gm 8 ”). 
     The timing diagram of  FIG. 9  is exemplary only, as there are many alternatives that may be used. By way of example,  FIG. 10  shows an alternate timing diagram. The main difference in this diagram is that the integrator clock starts in the middle of the chopper clock, resulting in a different integrator output waveform. Also delays may be imposed between clocks as desired to avoid any undesirable influence between successive operations. 
     In the present invention, the insertion of the sample and hold will cause an additional time delay Tsh in the chopper loop, which is inversely equal to the sample frequency fsh: Tsh=1/fsh. This delay can easily result in a non-linear roll-off of the frequency characteristic, or can even cause instability of the feedback system. This non-linearity or instability will not occur if the sample and hold has been inserted directly after the integrator, as shown in  FIGS. 4 and 7   a  and  7   b , and if the sample and hold clock frequency fsh is on the order of 4 times larger than the frequency fAchp 0  at which the chopper path loop gain is 0 dB: Achp=(Gm 7 /ωC 6 )(Gm 5 /Gm 3 , 4 )=1. In this case, the sample and hold adds a 45 degree phase delay to the chopper loop, which is satisfactory. The loop will be unstable when the additional phase is more than 90 degrees at a sample frequency fsh lower than 2 times the frequency fAchp 0  at which the chopper loop gain is 0 dB. 
     While certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Technology Classification (CPC): 7