Patent Abstract:
A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays.

Full Description:
BACKGROUND 
       [0001]    Thin-film-transistor (TFT) technology is important for fabrication of circuitry that requires the ability to flex and in large area devices such as flat panel displays, imagers, and detectors that require active areas that are large compared to the current size of semiconductor wafers. However, a significant limitation of the TFT technology results from the difficulty in fabricating useful PMOS devices in a-Si Amorphous silicon (a-Si) or other thin film semiconductor materials such as Zinc Oxide and thin-film polysilicon. As a result of this difficulty, many TFT circuits only use NMOS transistors, which can cause problems when trying to implement logic with full rail-to-rail output voltage levels, i.e., signals ranging from ground to the power supply voltage. In particular, TFT logic circuits generally lose signal level from the dynamic voltage range and therefore cannot be easily cascaded in the way that conventional CMOS circuits can. 
         [0002]      FIG. 1  shows a circuit diagram for a conventional NMOS inverter  100  that can be fabricated using thin-film transistors in a-Si or other material. Inverter  100  includes two NMOS transistors  110  and  120 . Transistor  110  has a gate and a drain connected to supply voltage Vdd and a source connected to an output node  115 . Transistor  120  has a drain connected to output node  115 , a gate connected to receive an input signal IN, and a source connected to ground. 
         [0003]    In operation, when an input signal IN is high, ideally at supply voltage Vdd, transistor  120  carries a saturation current which also flows from supply voltage Vdd through transistor  110 . Accordingly, when input signal IN is high, inverter  100  acts as a voltage divider, and output signal OUT is pulled to a voltage that will not be the ground voltage but instead depends on the sizes of transistors  110  and  120 . When input signal IN is low (ideally at the ground voltage), transistor  120  will be off, and transistor  110  will pull up output node  115  to a voltage that is lower than supply voltage Vdd by at least the threshold voltage of transistor  110 . Accordingly, the output signal OUT from inverter  100  does not have the full rail-to-rail voltage range from ground to supply voltage Vdd. 
         [0004]    The problem of being unable to provide output signals with the full rail-to-rail voltage swings limits the number of such logic gates that may be serially connected or cascaded without additional signal correction or conditioning. Accordingly, systems and methods that are able to provide rail-to-rail signal range in TFT circuits and NMOS circuits are desired. 
       SUMMARY 
       [0005]    In accordance with an aspect of the invention, a logic circuit includes a logic stage connected to a supply voltage and a level shifter connected to a voltage higher than the supply voltage. In one embodiment, the level shifter includes: a first NMOS transistor having a gate and drain connected to the higher voltage and a source connected to a first node; and a second NMOS transistor connected between the first node and a reference voltage and having a gate to which a first input signal of the logic circuit is applied. The logic stage includes: a third NMOS transistor coupled between the supply voltage and a second node and having a gate connected to the first node; and a fourth NMOS transistor coupled between the second node and the reference voltage and having a gate to which the first input signal of the logic circuit is applied. An output signal of the logic circuit that is provided at the second node has full rail-to-rail voltage swings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a circuit diagram of a conventional NMOS inverter. 
           [0007]      FIG. 2  is a circuit diagram of an inverter in accordance with an embodiment of the invention. 
           [0008]      FIG. 3  is a circuit diagram of a NAND gate in accordance with an embodiment of the invention. 
           [0009]      FIG. 4  is a circuit diagram of a NOR gate in accordance with an embodiment of the invention. 
           [0010]      FIG. 5  illustrates a branch of a decoder circuit that can be constructed using inverters, NAND gates, and NOR gates in accordance with embodiments of the invention. 
           [0011]      FIG. 6  illustrates a circuit in accordance with an embodiment of the invention integrating decoder circuits and a TFT array in the same thin film. 
       
    
    
       [0012]    Use of the same reference symbols in different figures indicates similar or identical items. 
       DETAILED DESCRIPTION 
       [0013]    In accordance with an aspect of the present invention, dual rail logic using a supply voltage and a higher voltage can provide full rail-to-rail (e.g., the supply voltage to a reference voltage or ground) swings and maintain the constant levels when required. The dual rail a-Si logic can be used to build in basic logic circuit blocks such as inverters, NAND gates, and NOR gates and therefore can construct virtually all the logic circuits commonly built using CMOS technology. One particular application of the invention is in a flat panel display where the NMOS a-Si logic described herein can be used to build edge electronics to drive the gate lines. In contrast, a conventional manufacturing process fabricates edge electronics for flat panel displays in silicon chips that must be attached to the panels. 
         [0014]      FIG. 2  illustrates an inverter  200  in accordance with an embodiment of the invention employing a level shifter  210  and an inverting stage  220 . Level shifter  210  operates at a voltage VddH that is higher than the supply voltage Vdd of inverter  200 , but level shifter  210  is otherwise similar to the conventional NMOS inverter of  FIG. 1 . In particular, level shifter  210  includes a loading TFT  212  and a driving TFT  214  connected in series between voltage VddH and ground. Both TFTs  212  and  214  are N-type. Loading TFT  212  has a gate and a drain coupled to higher voltage VddH and a source coupled to an internal node  216 . Driving TFT  214  has a drain connected to node  216 , a source connected to ground, and a gate connected to the input signal IN. 
         [0015]    Inverting stage  220  includes a loading TFT  222  and a driving TFT  224  connected in series between supply voltage Vdd and ground. Both TFTs  222  and  224  are N-type. Loading TFT  222  has a drain connected to power supply Vdd, a source connected to an output node  226 , and a gate driven by level shifter  210 . Driving TFT  224  has a drain connected to output node  226 , a source connected to ground, and a gate connected to receive an input signal IN. 
         [0016]    When the input signal IN is low, preferably near ground voltage, driving TFT  214  in level shifter  210  is non-conductive, and loading TFT  212  pulls node  216 , and therefore an internal signal  IN  applied to the gate of TFT  222 , up to a voltage that is lower than voltage VddH by the threshold voltage Vt of TFT  212 . In accordance with an aspect of the invention, voltage VddH is selected to be higher than supply voltage Vdd by at least the sum of the threshold voltages of TFTs  212  and  222 , e.g., VddH≧Vdd+2Vt if TFTs  212  and  222  have the same threshold voltage Vt. As a result, the voltage of internal signal  IN  is greater than supply voltage Vdd by at least the threshold voltage Vt of TFT  222 . TFT  222  can then pull the output signal OUT to supply voltage Vdd because the gate-to-source V GS  of TFT  222  is greater than or equal to the threshold voltage Vt of TFT  222  even when the source (output node  226 ) of TFT  222  is at supply voltage Vdd. Also, input signal IN being low makes TFT  224  non-conductive, so that TFT  224  does not prevent TFT  222  from pulling output signal OUT to voltage Vdd. Inverter  200  thus inverts the low input signal IN to produce output signal OUT fully at supply voltage level Vdd. 
         [0017]    When input signal IN is high, preferably near supply voltage Vdd, driving TFT  214  in level shifter  210  is conductive. The sizes of TFTs  212  and  214  in level shifter  210  are selected so that TFT  214  pulls internal signal  IN , which is applied to the gate of loading TFT  222  in inverting stage  220 , low enough that TFT  222  is in non-conductive. The high input signal IN also puts driving transistor  224  in inverting stage  220  in the conductive mode, and with loading TFT  222  being non-conductive, driving TFT  224  pulls output signal OUT to the ground voltage. Inverter  200  thus inverts the high input signal IN to produce output signal OUT fully at ground voltage. 
         [0018]    The level of output signal OUT of inverter  200  can thus change from ground to supply voltage Vdd when input signal IN changes from supply voltage Vdd to ground. Inverter  200  thus has rail-to-rail output capability, and one or more additional inverters of the same type as inverter  200  can be cascaded with inverter  200  without worrying about a signal losing dynamic range. Additionally, all of TFTs  222 ,  224 ,  212 , and  214  are NMOS devices that can be fabricated in a-Si or other thin-film semiconductors using processes well known in the art. 
         [0019]    Other logic gates such as NAND gates and NOR gates can be built in thin films using similar techniques.  FIG. 3 , for example, shows a NAND gate  300  in accordance with an embodiment of the invention. NAND gate  300  includes two level shifters  310  and  320  and a logic stage  330 . The level shifters  310  and  320  receive the input signals A and B of NAND gate  300 , and logic stage  330  produces the output signal OUT. 
         [0020]    Level shifter  310 , which operates at higher voltage VddH, receives input signal A and produces an internal signal Ā that is applied to the gate of a TFT  332  in logic stage  330 . Level shifter  310  includes a loading TFT  312  and a driving TFT  314  that are connected in the same manner as TFTs in level shifter  210  of  FIG. 2 . In the same manner as the operation of level shifter  210  described above in regard to  FIG. 2 , internal signal Ā from level shifter is in a high state or a voltage about VddH−Vt when input signal A is low and is in a low state or a voltage that keeps a connected transistor  332  non-conductive when input signal A is high. 
         [0021]    Level shifter  320 , which operates at higher voltage VddH, similarly includes a loading TFT  322  and a driving TFT  324  that are connected in the same manner as the TFTs in level shifter  210  of  FIG. 2 . TFT  324  receives input signal B and produces an internal signal  B . In the same manner as described above, internal signal  B  from level shifter  320  is in a high state or a voltage of about VddH−Vt when input signal B is low and is in a low state or a voltage that keeps a connected transistor  334  non-conductive when input signal B is high. 
         [0022]    Logic stage  330  includes the pair of TFTs  332  and  334  connected in parallel between supply voltage Vdd and an output node  335  and a pair of TFTs  336  and  338  that are connected in series between output node  335  and ground. TFTs  332  and  334  have gates connected to respectively receive internal signals Ā and  B  from respective level shifters  310  and  320 . Input signals A and B are respectively applied to the gates of TFTs  336  and  338 . 
         [0023]    In operation, when at least one of input signals A and B is low, at least one of transistors  336  and  338  is non-conductive, and at least one of internal signals Ā and  B  is in a high state, i.e., at least voltage VddH−Vt. Voltage VddH is greater than supply voltage Vdd by at least 2Vt, so that at least one of TFTs  332  and  334  is conductive and able to pull output signal OUT fully to supply voltage Vdd. Accordingly, if either or both of input signals A and B are in the low state, output signal OUT of NAND gate  300  is a high state that is fully up to supply voltage Vdd. 
         [0024]    When both input signals A and B are high (preferably near supply voltage Vdd), internal signals Ā and  B  are both in a sufficiently low state that both TFTs  332  and  334  are non-conductive. The high input signals A and B also make both TFTs  336  and  338  conductive, so that the series connected TFTs  336  and  338  pull output signal OUT fully to ground. Accordingly, when both input signals A and B are high, NAND gate  300  drives output signal OUT to a low state that is fully ground. NAND gate  300  thus provides the desired logical operation and a full rail-to-rail voltage swing. 
         [0025]      FIG. 4  shows a NOR gate  400  in accordance with an embodiment of the invention. NOR gate  400  includes level shifters  310  and  320  that are connected to receive input signals A and B and that generate respective internal signals Ā and  B  as described above in regard to  FIG. 3 . NOR gate  400  also includes a logic stage  430  including TFTs  432 ,  434 ,  436 , and  438 . TFTs  432  and  434  are connected in series between supply voltage Vdd and an output node  435 . Internal signals Ā and  B  from level shifters  310  and  320  are respectively applied to the gates of TFTs  432  and  434 . TFTs  436  and  438  are connected in parallel between output node  435  and ground, and input signals A and B are respectively applied to the gates of TFTs  436  and  438 . 
         [0026]    When at least one of the input signals A and B applied to NOR gate  400  is high, at least one of transistors  436  and  438  is conductive, and at least one of internal signals Ā and  B  is in a low state, i.e., a voltage such that the corresponding TFT  432  or  434  is non-conductive. As a result, no current flows from supply voltage through transistors  432  and  434  to node  435 , and one or both of transistors  436  and  438  are conductive and pull the output signal OUT on output node  435  to ground. Accordingly, if either or both of input signals A and B are in the high state, output signal OUT of NOR gate  300  in is a low state that is fully at the ground or reference voltage. 
         [0027]    When both input signals A and B are low (preferably near ground), both transistors  436  and  438  are non-conductive. Internal signals Ā and  B  are both in a high state, i.e., at least voltage Vdd+Vt, so that series connected TFTs  432  and  434  pull the output signal on node  435  up to supply voltage Vdd. Accordingly, when both input signals A and B are low, NOR gate  400  drives output signal OUT to a high state that is fully the supply voltage Vdd. NOR gate  400  thus provides the desired logical operation and a full rail-to-rail voltage swing. 
         [0028]    The embodiments of this invention described above enable rail-to-rail output capability in a TFT circuit containing only NMOS transistors fabricated in a-Si or other thin film semiconductor materials such as Zinc Oxide and polysilicon. As a result, TFT logic can cascade many functional blocks to produce more complicated functions. In contrast, fabrication of such complex circuits with other thin-film technologies that suffer from loss of dynamic signal range would be difficult or impossible. The TFT circuitry can further include charge pumps or other circuits to generate the higher voltage VddH from the supply voltage Vdd, so that the existence or use of voltage VddH is transparent or unknown to the user of the TFT circuit. 
         [0029]    One example of complex logic that can be fabricated using the logic gates described above is a decoder circuit.  FIG. 5  shows the example of one branch  500  of a 4-bit decoder. Decoder branch  500  includes a NOR gate  400  having input terminals connected to the output terminals of two NAND gates  300 , and each NAND gate  300  has an inverter  200  connected to one of its input terminals. The logic gates in decoder branch  500  are thus cascaded in three levels. With the illustrated connections, decoder branch  500  asserts and output signal ĀB  C D high only when the four input signals A, B, C, and D meet the conditions of signal A being low, signal B being high, signal C being low, and signal D being high, e.g., when the input signals represent the 4-bit binary value 0101. Techniques for combining inverters, NAND gates, and NOR gates to design decoder branches decoding other binary value are well known in the art and generally require more levels of logic gates when the number of input bits increases. For complex decoders, more levels of logic gates would be a problem if each level lost more of the dynamic signal range. Since each of gates  200 ,  300 , and  400  has rail-to-rail output capability the gates can be easily cascaded as needed and complex logic such as decoder circuits can be implemented. 
         [0030]    TFT decoders can be used in large TFT array applications, such as flat panel displays.  FIG. 6 , for example, illustrates a thin-film circuit  600  including row decoder logic  610 , column logic  620 , and a TFT array  630  that can all be fabricated using techniques described herein in a thin film of a flat panel display. With a conventional architecture, array  630  has gate lines  632  that need to be driven to high one by one sequentially, for example, to refresh of pixels in the flat panel display. Row decoder  610 , which is constructed from inverters  200 , NAND gates  300 , and NOR gates  400  of the types described above, can perform this function and provides full rail-to-rail signal range even though decoder  610  includes only NMOS transistors. In contrast, some current systems require silicon chips to be bonded on the edge of a panel to provide address decoding for a TFT array fabricated on the panel. The embodiment of this invention illustrated in  FIG. 6  can integrate decoder  610  and column logic  620  directly on the panel edge using the same TFT fabrication process as used for array  630 . 
         [0031]    Although the invention has been described with reference to particular embodiments, the description is only an example of the invention&#39;s application and should not be taken as a limitation. For example, although the above described embodiments of the invention use only NMOS transistors in a thin-film where useful PMOS transistors are difficult fabricate, some alternative embodiments of the invention use only PMOS transistors in a thin film such as some organic semiconductors where NMOS devices are difficult to fabricate. A purely PMOS embodiment, for example, can include a logic stage made solely of PMOS transistors and PMOS level shifters that are driven by the supply voltage and a negative voltage. The level shifters in the PMOS implementation apply gate voltages to PMOS pull-down TFT in the logic stage, so that the gate voltages are either sufficiently positive to make the PMOS transistors non-conductive or negative enough that PMOS pull-down TFTs can pull an output signal to ground giving the logic stage a full rail-to-rail dynamic signal range for the output signal or signals. Various other adaptations and combinations of the features of the embodiments disclosed are within the scope of the invention as defined by the following claims.

Technology Classification (CPC): 7