Patent Abstract:
An enhanced digital signal driver circuit that allows the driving of digital signals with a larger voltage swing than that which is typically allowed by the associated IC technology is provided. The driver circuit employs PFETs and NFETs that clip the voltage present across both the drain-to-source and gate-to-source junctions of a driving PFET and a driving NFET of the driver circuit. The clipping PFETs and NFETs ensure that the drain-to-source and gate-to-source voltages of all of the FETs of the driver circuit are within the voltage design limits of the associated IC technology when the imposed power supply and digital signal voltages are substantially higher than those for which the associated IC technology was designed.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    CMOS-based (complementary metal-oxide-semiconductor) digital logic IC (integrated circuit) technologies have been devised over the last several years which operate at progressively lower power supply voltages with each passing design generation. Lower supply voltages dictate lower voltage swings for the associated digital signals, which typically traverse between ground and the power supply voltage. The benefits of using lower supply voltages are lower power consumption and faster signal switching times. CMOS logic IC power supply voltages currently available include, for example, 3.3 volts (V), 2.5 V, 1.8 V, and 1.5 V. Due to the multitude of IC technologies available, a mix of these technologies may be used in any particular electronic product.  
           [0002]    One consequence of this mixing of technologies is that a digital signal with a relatively high voltage swing, such as a signal switching between 0 and 3.3 V, may have to be driven either off-chip or on-chip via input/output (I/O) pads using IC technology designed for lower voltages swings, such as from 0 to 2.5 V. Typically, for economic considerations, a single IC technology is utilized for the I/O pads of an IC. As lower voltage IC technology, such as 2.5 V circuitry, generally provides higher performance than that associated with higher voltages, such as 3.3 V, lower voltage IC technology is normally selected for all I/O pads of an IC. Therefore, the desirable solution in most cases is to employ low-voltage IC technology for all I/O signals, no matter what voltage range they traverse.  
           [0003]    [0003]FIG. 1 shows a standard digital signal driver circuit  1 , consisting of a pair of complementary MOS FETs (Field Effect Transistors) structured as a CMOS inverter. A PFET (p-channel FET) P 1  and an NFET (n-channel FET) N 1  are connected in series between a power supply voltage V DD  and a ground reference. The gate terminals of P 1  and N 1  are connected together and driven by an input signal V IN . The source terminal of P 1  and the drain terminal of N 1  are connected together to drive an output signal V OUT .  
           [0004]    [0004]FIG. 2 graphically shows the operation of the standard driver circuit  1 . As V IN  rises from LOW logic state at about zero volts up to a HIGH logic state of essentially V DD  volts, P 1  turns OFF and N 1  turns ON, thereby driving V OUT  from about V DD  volts down to near zero volts. Oppositely, when V IN  then returns from its HIGH state down to its low voltage level, P 1  returns to its ON state, N 1  shuts off, thereby driving V OUT  up close to V DD  volts.  
           [0005]    Therefore, each of the FETs P 1  and N 1  must be able to handle drain-to-source voltages of approximately V DD  volts. Unfortunately, in the case of a V DD  power supply voltage of approximately 3.3 V, IC technology that is designed to support a V DD  of 2.5 V cannot reliably handle such significantly higher power supply and digital signal voltages. For example, assume the standard driver circuit  1  was manufactured using 2.5 V technology. If a V DD  of 3.3 V is employed to support input is and output signals switching between zero and 3.3 V, P 1  and N 1 , each will periodically have about 3.3 V across their drain-to-source junctions. As P 1  and N 1  are designed for 2.5 V operation, the overvoltage across each FET is likely to cause their eventual breakdown, resulting in the ultimate failure of the standard driver circuit  1 . Additionally, the extensive voltage swing in the input signal V IN  periodically places 3.3 V across the gate-to-source junctions of both P 1  and N 1 , which also are only designed to handle 2.5 V. This gate-to-source overvoltage promotes breakdown of the FET gate oxide, causing even more permanent damage to the FETs involved.  
           [0006]    Alternately, as displayed in FIG. 3, small linearizing resistors R P  and R N  may be connected in series with P 1  and N 1 , respectively, resulting in a modified driver circuit  2 . Although any current passing through the resistors R P  and R N  will cause a small portion of the high voltage power supply V DD  to appear across the resistors, the voltage across each of the FETs P 1  and N 1  is likely to still be too high to guarantee proper operation of the modified driver circuit  2 .  
           [0007]    From the foregoing, a need exists for a driver circuit that drives digital signals and utilizes a power supply voltage that both exhibit higher voltage levels than those for which the associated IC technology was designed. Such a driver circuit would operate under those high voltage conditions without suffering significant voltage breakdown or other reliability problems.  
         SUMMARY OF THE INVENTION  
         [0008]    Embodiments of the invention, to be discussed in detail below, utilize PFETs and NFETs that clip the voltage present across both the drain-to-source and gate-to-source junctions of a driving PFET and driving NFET of the driver circuit. The clipping PFETs and NFETs ensure that the drain-to-source and gate-to-source voltages of all of the FETs of the driver circuit are within the voltage design limits of the associated IC technology when the imposed power supply and digital signal voltages are substantially higher than those for which the associated IC technology was designed.  
           [0009]    Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a schematic diagram of a standard digital signal driver circuit from the prior art.  
         [0011]    [0011]FIG. 2 is an idealized voltage vs. time graph describing the operation of the standard digital signal driver circuit of FIG. 1.  
         [0012]    [0012]FIG. 3 is a schematic diagram of a modified driver circuit from the prior art.  
         [0013]    [0013]FIG. 4 is a schematic diagram of a digital signal driver circuit according to an embodiment of the invention.  
         [0014]    [0014]FIG. 5A and FIG. 5B are schematic diagrams of two alternative active voltage dividers that generate bias voltages for the digital signal driver circuit of FIG. 4.  
         [0015]    [0015]FIG. 6 is an idealized voltage vs. time graph describing the operation of the digital signal driver circuit of FIG. 4.  
         [0016]    [0016]FIG. 7 is a schematic diagram of a second digital signal driver circuit according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]    One embodiment of the invention, an enhanced digital signal driver circuit  100 , is displayed in FIG. 4. A p-channel FET P DRIVE  and an n-channel FET N DRIVE  are employed to drive an output signal V OUT  to a logic HIGH or LOW, depending on the voltage level of an input signal V IN . In the case of FIG. 4, a logic HIGH for either V IN  or V OUT  corresponds with a high voltage power supply V DDH , and a logic LOW is essentially at a ground reference point. Assuming that the enhanced driver circuit  100  is implemented using technology suited for lower power supply voltages, the presence of voltage of the magnitude of V DDH  would cause reliability problems within the enhanced driver circuit  100  without the surrounding circuitry shown. For example, if V DDH  were approximately 3.3 V, and the circuit used to implement the enhanced driver circuit  100  were designed for 2.5 V operation, the presence of 3.3 V across the drain-to-source junction or the gate-source junction of either P DRIVE  or N DRIVE  would likely cause reliability problems, and possibly permanent damage, to those FETs, as described above in relation to the prior art standard driver circuits  1  and  2 .  
         [0018]    To alleviate this problem, the enhanced driver circuit  100  includes additional circuitry that “clips,” or reduces, the voltage imposed on the driving FETs P DRIVE  and N DRIVE . With respect to P DRIVE , a PFET P CLIP1  is positioned in series with P DRIVE  between the source of P DRIVE  and the output signal V OUT . P CLIP1  clips the voltage across the drain-to-source junction of P DRIVE  by sharing part of the high voltage power supply level V DDH  that will exist across P DRIVE  and P CLIP1  whenever V OUT  is driven LOW, close to the ground voltage reference. With each of P DRIVE  and P CLIP1  sharing a portion of V DDH , both of those two FETs will be operating within their voltage design limits, thus eliminating the reliability concerns associated with older driver circuits.  
         [0019]    A second P FET , P CLIP2 , addresses the problem of potentially excessive voltage across the gate-to-source junction of P DRIVE  by sharing that voltage with P DRIVE . For example, with V IN  at a logic LOW level, V OUT  will be driven HIGH, thus causing both the source and drain of P DRIVE  to reside at or near V DDH  volts. If V IN  were to be asserted directly at the gate of P DRIVE , the gate-to-source (and gate-to-drain) junction of P DRIVE  would have to handle the full magnitude of V DDH , potentially causing gate oxide breakdown of P DRIVE , as described above. However, with P CLIP2  residing between the input signal V IN  and the gate of P DRIVE , the possibility for V DDH  volts to be impressed across the gate-to-source (or gate-to-drain) junction of P DRIVE  is eliminated due to P CLIP2  accepting part of that voltage.  
         [0020]    Concerning the bottom portion of the enhanced driver circuit  100 , as depicted in FIG. 4, the driving FET N DRIVE  is similarly protected by way of a pair of clipping NFETs, N CLIP1  and N CLIP2 . These clipping NFETs work in a fashion analogous to the clipping PFETs P CLIP1  and P CLIP2 , described above. The drain-to-source junction of N DRIVE  is protected by the use of N CLIP1  between the drain of N DRIVE  and the output signal V OUT  during those times when V OUT  is at a logic HIGH level as a result of V IN  being forced toward the ground reference voltage. Similarly, N CLIP2 , which is positioned between the input signal V IN  and the gate of N DRIVE , protects N DRIVE  from gate oxide breakdown by limiting the voltage across the gate-to-source (and gate-to-drain) junction of N DRIVE  when V IN  is at the logic HIGH state, at about V DDH  volts.  
         [0021]    To ensure that the clipping FETs operate properly, the gate of each of the clipping FETs is biased at a voltage level which prevents each clipping FET from operating in saturation during those times when the FET is required to clip the voltage across a junction of the associated driving FET. For example, the gates of P CLIP1 , and P CLIP2  are tied to a voltage V LBIAS , which resides at an intermediate value between V DDH /2 and the ground reference voltage. Likewise, the gates of N CLIP1  and N CLIP2  have a voltage V HBIAS  forced thereupon at an intermediate value between V DDH  and V DDH /2.  
         [0022]    In the specific example of FIG. 5A, V HBIAS  and V LBIAS  are generated by way of an active voltage divider  200  formed from a set of four stacked PFETS P B1 , P B2 , P B3  and P B4  connected in series between V DDH  and ground. Each of the stacked PFETs is essentially in the OFF state, as the gate and source of each stacked PFET are connected together. As a result of the stacked configuration, V HBIAS  maintains a voltage of approximately 3V DDH /4, while V LBIAS  resides at about V DDH /4. Optionally, other circuits providing similar bias voltages may also be employed. In addition, low bias voltage V LBIAS  and high bias voltage V HBIAS  each may be coupled to the ground voltage reference via capacitors C H  and C L  to stabilize their voltage levels. These capacitors may be of substantial capacity (on the order of a microfarad, for example), especially if one such active voltage divider  200  is employed to service several enhanced driver circuits  100 .  
         [0023]    [0023]FIG. 5B displays an alternate active voltage divider  250  that uses four stacked NFETs N B1 , N B2 , N B3  and N B4 , with the gate of each NFET connected to the drain of that same NFET. The alternate active voltage divider  250  generates essentially the same values for V HBIAS  and V LBIAS  as those associated with the active voltage divider  200  of FIG. 5A.  
         [0024]    The effects of the clipping FETs, as biased by the high and low bias voltages, can be seen in the waveform diagrams of FIG. 6, while referencing the enhanced driver circuit  100  of FIG. 4. As V IN  proceeds from a logic LOW level to a logic HIGH of about V DDH  volts, the drain of N CLIP2  rises to that level. With V HBIAS  driving the gate of N CLIP2  to some voltage less than V DDH  to prevent saturation of N CLIP2  (3V DDH /4, in this case), N CLIP2  develops a significant voltage across its drain-to-source junction, thereby allowing the voltage at the gate of N DRIVE  (indicated by the reference point V NCLIP2 ) to rise to some level significantly less than V DDH  while still allowing the gate of N DRIVE  to be driven high enough to turn ON N DRIVE . This action aids in pulling the drain of N DRIVE  and the source of N CLIP1  (indicated by the reference point V NCLIP1 ) toward ground. With the gate of N CLIP1  biased at V HBIAS , N CLIP1  is turned ON as well, pulling the output signal V OUT  approximately to the ground reference voltage.  
         [0025]    As V OUT  is pulled LOW, thus pulling the source of P CLIP1  along with it, P CLIP1  tends toward the OFF state since the gate of P CLIP1  is held at the voltage level V LBIAS . At the same time, with V IN  causing a HIGH logic level at the drain of P CLIP2 , and the gate of P CLIP2  being held at the low bias voltage V LBIAS , P CLIP2  is essentially ON, thereby forcing the gate of P DRIVE  to a logic HIGH. Hence, P DRIVE  is turned OFF as well, causing the drain of P CLIP1  (indicated by the reference point V PCLIP1 ) to reside at a voltage near the midpoint between V DDH  and ground, at which V OUT  is driven.  
         [0026]    In the case that V IN  then is driven toward the ground reference voltage, the drain of P CLIP2  is pulled to ground as well. With the gate of P CLIP2  being held at V LBIAS  (in this case, V DDH /4), P CLIP2  conducts at less than the saturation level, causing a significant voltage drop across the drain-to-source junction of P CLIP2 . As a result, the voltage at the gate of P DRIVE  (i.e., V PCLIP2 ), drops to an intermediate voltage between V DDH  and ground which is low enough to turn ON P DRIVE , which, in turn, causes the source of P DRIVE  and the drain of P CLIP1  (denoted by V PCLIP1 ) to raise essentially to V DDH . With the gate of P CLIP1 , being maintained at V LBIAS , P CLIP1  is turned ON as well, causing V OUT  to rise essentially to V DDH .  
         [0027]    With V OUT  being pulled HIGH, along with the drain of N CLIP1 , N CLIP1  tends toward the OFF state because of the gate of N CLIP1  being held at V HBIAS . At the same time, the LOW logic level of V IN  is forced upon the drain of N CLIP2 , thus causing N CLIP2  to be essentially turned ON, ensuring the source of N CLIP2  and the gate of N DRIVE  (i.e. V NCLIP2 ) are brought down to essentially ground. N DRIVE  is thus essentially OFF, along with N CLIP1 . In that state, the drain of N DRIVE  and the source of N CLIP1  (indicated by V NCLIP1 ) reside at an intermediate voltage between V DDH  and ground.  
         [0028]    Thus, whether V IN  attains the logic HIGH level (at about V DDH  volts) or the logic LOW level (at about ground), none of the FETs of the enhanced driver circuit  100  sustain a voltage beyond which the FETs can safely handle. The maximum voltage across any FET will be in the neighborhood of V DDH /2, depending on the physical characteristics of the FETs and the actual voltage levels of V HBIAS  and V LBIAS . As a result, the FETs should be implemented using an IC technology that can handle voltages of about V DDH /2 in order to prevent any damage or reliability problems due to overvoltage. For example, assuming IC technology of 2.5 volts is employed for the enhanced driver circuit  100 , a V DDH  of 3.3 V, as well as input and output signal voltage swings between ground and 3.3 V, are handled effectively. However, power supply and signal voltage levels well in excess of 5 V would not be applicable to the use of 2.5 V IC technology.  
         [0029]    Other embodiments based upon the enhanced driver circuit  100  may also be employed in accordance with the present invention. For example, FIG. 7 shows a second enhanced driver circuit  300  comprising the FETs of the enhanced driver circuit  100  of FIG. 4 with a couple of additional linearizing resistors R P  and R N  connected in series with P CLIP1  and N CLIP1 . The junction of R P  and R N  form the signal output V OUT . Other modifications of the enhanced driver circuit  100  may also be employed in accordance with the inventive concepts described herein.  
         [0030]    Due to the additional FETs employed in enhanced driver circuit  100  over that required for the standard driver circuit  1 , the total amount of capacitance of the enhanced driver circuit  100  that is charged and discharged when the input signal V IN  changes logic states causes the enhanced driver circuit  100  to operate more slowly in most cases than the standard driver circuit  1  of similar IC technology. As a result, embodiments of the present invention are particularly well-suited for applications that value small circuit footprint and design flexibility over the highest possible circuit switching speeds. For example, many system interface bus implementations, such as Peripheral Component Interconnect X (PCIX), a popular 64-bit computer bus architecture capable of running at bus speeds of up to 133 Megahertz (MHz), would benefit from employment of embodiments of the invention. Other systems requiring similar performance characteristics could particularly benefit the use of such driver circuits.  
         [0031]    From the foregoing, the invention provides a simple digital signal driver circuit capable of driving high-voltage digital signals using comparatively low-voltage IC technology while eliminating the circuit damage and operational reliability problems exhibited by other driver circuits. Embodiments other than those shown above are also possible. As a result, the invention is not to be limited to the specific forms and arrangements of components so described and illustrated; the invention is limited only by the claims.

Technology Classification (CPC): 7