Patent Abstract:
Realizing a stabilized gain slope without increasing circuit scale or entailing extra time or care for correcting impedance. A resonant circuit that is made up of a capacitor and an inductor is provided in an output stage outside a feedback loop for realizing peaking at a particular frequency and for realizing a gain slope having a desired slope of, for example, 1 dB or more.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor circuit, and particularly to a semiconductor circuit used in CATV (CAble TeleVision) hybrid IC (HIC).  
           [0003]    2. Description of the Related Art  
           [0004]    In HIC (hybrid IC) broadband amplifiers for CATV, a plurality of stages of amplifiers are connected in series via coaxial cable, and a desired gain slope must be established across the entire employed frequency band to correct for characteristic lost in the coaxial cable. Gain slope is such that gain increases with higher frequencies within the bandwidth.  
           [0005]    Realization of desired gain slope in the frequency bands employed has become more difficult in recent years as the frequency bandwidths that are used have extended to higher frequencies.  
           [0006]    [0006]FIG. 1 and FIG. 2 are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open application No. 85810/83.  
           [0007]    In the circuits shown in FIG. 1 and FIG. 2, a parallel resonant circuit is formed by inductor L 101 , which is provided in a bias feedback circuit, and capacitor C 102 , which is provided between the base and emitter of transistor Tr  101 . In addition, damping resistor R 106  connected in a series with capacitor C 102  between the base and emitter of transistor Tr 101  is provided to control Q in the resonant circuit.  
           [0008]    In a circuit configured according to the foregoing description, the resonance frequency is altered by changing the element constants of inductor L 101  and capacitor C 102 , thereby regulating the peaking frequency.  
           [0009]    [0009]FIG. 3 and FIG. 4 are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.  
           [0010]    In the circuit shown in FIG. 3, a serial resonant circuit is formed by capacitor C 112  and inductor-L 11  in an interstage circuit provided between two amplifier circuits, and in the circuit shown in FIG. 4, FET (Field Effect Transistor) Tr 113  is provided such that inductor L 111  is connected in parallel between the source and drain, and a parallel resonant circuit is formed by inductor L 111  and the capacitance between the source and drain of FET Tr 113 .  
           [0011]    In the circuits configured according to the foregoing description, alteration of resonance frequency is realized by changing the gate bias to vary the capacitance between the source and drain of FET Tr 113 , thereby regulating peaking frequency.  
           [0012]    However, the above-described circuits of the prior art have the following drawbacks:  
           [0013]    (1) In the circuits shown in FIG. 1 and FIG. 2, resonance frequency is altered by changing the element constants of inductor L 101  and capacitor C 102  to regulate the peaking frequency, but the impedance on the input side and output side change according to the amount of peaking because inductor L 101  and capacitor C 102  are provided in the feedback circuit.  
           [0014]    The resulting circuit therefore has the three factors of input and output impedance and gain slope, and design and adjustment consequently require considerable time and trouble.  
           [0015]    (2) In the circuits shown in FIG. 3 and FIG. 4, the resonance frequency is changed and the peaking frequency adjusted by changing the gate bias to change capacitance between the source and drain of the FET, and these circuits therefore require a variable bias to allow change of the gate bias. These circuits also require the additional provision of an FET. As a result both the scale and cost of the circuit is increasing.  
           [0016]    In the circuit shown in FIG. 3, moreover, capacitor C 111  and inductor L 111  between active elements must also be changed to alter the resonance frequency, and mismatching between elements having gain tends to cause problems in characteristics such as oscillation and instability.  
         SUMMARY OF THE INVENTION:  
         [0017]    The object of the present invention is to provide a semiconductor circuit that can realize a stable gain slope without increasing the circuit scale or necessitating extra time for correcting impedance.  
           [0018]    In this invention, a resonant circuit is provided outside a feedback loop for effecting peaking at a particular frequency and for realizing a gain slope having a desired inclination, for example, an inclination of 1 dB or more. As a result, the oscillation operation need not be considered when designing the circuit.  
           [0019]    In addition, in a case in which a resonant circuit is provided in the output stage of a feedback loop, change in impedance occurs only on the output side and change in impedance does not occur on the input side. A circuit can therefore be designed and adjusted while considering only two factors and without taking the input side into consideration, thereby facilitating adjustment.  
           [0020]    Finally, the invention does not entail enlargement of circuit scale because additional active elements are not necessary.  
           [0021]    The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIG. 1 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open No. 85810/83.  
         [0023]    [0023]FIG. 2 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open No. 85810/83.  
         [0024]    [0024]FIG. 3 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.  
         [0025]    [0025]FIG. 4 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.  
         [0026]    [0026]FIG. 5 is a circuit diagram showing a semiconductor circuit according to the first embodiment of the present invention.  
         [0027]    [0027]FIG. 6 shows one example of the configuration of chip inductance that including a capacitance component.  
         [0028]    [0028]FIG. 7 is an equivalent circuit diagram of the chip inductance shown in FIG. 6.  
         [0029]    [0029]FIG. 8 shows the gain characteristic with respect to frequency for a case in which a resonant circuit is not applied in the circuit shown in FIG. 5.  
         [0030]    [0030]FIG. 9 shows the gain characteristic with respect to frequency in the circuit shown in FIG. 5.  
         [0031]    [0031]FIG. 10 is a circuit diagram showing a semiconductor circuit according to the second embodiment of the present invention.  
         [0032]    [0032]FIG. 11 is a circuit diagram showing a semiconductor circuit according to the third embodiment of the present invention.  
         [0033]    [0033]FIG. 12 is a circuit diagram showing a semiconductor circuit according to the fourth embodiment of the present invention.  
         [0034]    [0034]FIG. 13 is a circuit diagram showing a semiconductor circuit according to the fifth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0035]    First Embodiment  
         [0036]    [0036]FIG. 5 is a circuit diagram showing a semiconductor circuit according to the first embodiment of the present invention. This circuit is only the alternating-current portion of the semiconductor circuit of this invention.  
         [0037]    As shown in FIG. 5, this embodiment is made up of FET Q 1  having its gate terminal connected to the input terminal and its source terminal connected to ground; resistor R 1  and capacitor C 1  connected in a series between the drain terminal and gate terminal of FET Q 1 ; and capacitor C 2  and inductor L 1  connected in parallel between the output terminal and the drain terminal of FET Q 1 ; wherein a feedback loop is formed by FET Q 1 , resistor R 1 , and capacitor C 1 . This feedback loop is provided for maintaining the band and impedance.  
         [0038]    In a semiconductor circuit configured according to the foregoing description, peaking is brought about by the resonance brought about by inductor L 1  and capacitor C 2 , and as a result, the resonance frequency can be changed and a desired slope, for example, of 1 dB or more, can be conferred upon gain by altering the element constants of this inductor L 1  and capacitor C 2 .  
         [0039]    In this embodiment, although impedance changes because the constants of elements constituting the circuit are altered, only impedance on the output side undergoes change because the circuit that generates resonance is provided outside the feedback loop, and impedance on the input side does not change.  
         [0040]    As a result, this embodiment can reduce the time and trouble required in designing and adjusting as compared with the circuits shown in FIG. 1 and FIG. 2 in which impedance changes on both the input side and output side.  
         [0041]    This invention can also dispense with the need for variable bias for altering the gate bias of the FET shown in FIG. 3 and FIG. 4, because the resonance frequency is modified by simply altering the constants of elements. As a result, a slope can be imposed on gain without increasing circuit scale. In addition, oscillation resulting from mismatching of impedance does not occur because the alteration of element constants does not take place in interstage elements.  
         [0042]    Although inductor L 1  and capacitor C 2  are connected in parallel in this embodiment, peaking can be similarly effected if these elements are connected in a series.  
         [0043]    In the semiconductor circuit configured as described hereinabove, the resonant circuit composed of inductor L 1  and capacitor C 2  can also be constituted only by chip inductance that includes a capacitance component.  
         [0044]    [0044]FIG. 6 shows an example of the configuration of chip inductance including a capacitance component, and FIG. 7 is an equivalent circuit diagram of the chip inductance shown in FIG. 6.  
         [0045]    As shown in FIG. 6, the chip inductance of this example includes internal conductors that constitute the L component that are linked in a number of layers in a helical spring form in a ceramic unit with the portions that constitute the C component interposed between the conductors. A resonant circuit including an L component and C component is thus formed as shown in FIG. 7.  
         [0046]    [0046]FIG. 8 shows the gain characteristic with respect to frequency for a case in which a resonant circuit is not applied in the circuit shown in FIG. 5, and FIG. 9 shows the gain characteristic with response to frequency in the circuit shown in FIG. 5.  
         [0047]    As shown in FIG. 9, the circuit shown in FIG. 5 realizes a gain slope having a desired inclination of, for example, 1 dB or more in a desired frequency band.  
         [0048]    Second Embodiment  
         [0049]    [0049]FIG. 10 is a circuit diagram showing a semiconductor circuit according to the second embodiment of the present invention. This circuit is only the alternating-current portion of the semiconductor circuit of this invention.  
         [0050]    As shown in FIG. 10, this embodiment is made up of: FET Q 1  having its gate terminal connected to the input terminal and its source terminal connected to ground; resistor R 1  and capacitor C 1  connected in a series between the drain terminal and gate terminal of FET Q 1 ; FET Q 2  having its gate terminal connected to the drain terminal of FET Q 1  and its source terminal connected to ground; resistor R 2  and capacitor C 3  connected in a series between the drain terminal and gate terminal of FET Q 2 ; and capacitor C 2  and inductor L 1  connected in parallel between the output terminal and the drain terminal of FET Q 2 ; wherein a first feedback loop is formed by FET Q 1 , resistor R 1 , and capacitor C 1 ; and a second feedback loop is formed by FET Q 2 , resistor R 2 , and capacitor C 3 .  
         [0051]    In a semiconductor circuit configured as described hereinabove, the circuit generating resonance is provided outside the feedback loops, and as a result, only the output side impedance changes and the input side impedance does not change, as in the circuit described in the first embodiment. This construction allows a reduction of the time and trouble necessary for designing and adjusting the circuit.  
         [0052]    Third Embodiment  
         [0053]    Although two feedback loops are formed in the circuit shown in FIG. 10, a similar effect can be obtained with only one of the feedback loops.  
         [0054]    [0054]FIG. 11 is a circuit diagram showing a semiconductor circuit according to the third embodiment of the present invention. This circuit is only the alternating-current portion of the semiconductor circuit of this invention.  
         [0055]    As shown in FIG. 11, the resonant circuit constituted by inductor L 1  and capacitor C 2  in this embodiment is provided outside the feedback loop constituted by FET Q 1 , resistor R 1 , and capacitor C 1 . As a result, only the output side impedance changes and the input side impedance undergoes no change, whereby the time and trouble required for design and adjustment can be reduced.  
         [0056]    Although the feedback loop is constituted by FET Q 1 , resistor R 1 , and capacitor C 1  in this embodiment, the same effect can be obtained if the feedback is formed using FET Q 2  if the resonant circuit is provided outside the feedback loop.  
         [0057]    Fourth Embodiment  
         [0058]    The same effect can be obtained in the circuit shown in FIG. 10 even in the case of a feedback loop that effects feedback from the drain terminal of FET Q 2  to the gate terminal of FET Q 1 .  
         [0059]    [0059]FIG. 12 is a circuit diagram showing a semiconductor circuit according to the fourth embodiment of the present invention.  
         [0060]    In the embodiment shown in FIG. 12, only the output side impedance changes and the input side impedance undergoes no change because the resonant circuit constituted by inductor L 1  and capacitor C 2  is provided outside the feedback loop constituted by FET Q 1  and Q 2 , resistor R 1 , and capacitor C 1 . This embodiment therefore reduces the time and trouble required for design and adjustment.  
         [0061]    Although a circuit has been described in this embodiment in which FETs were connected in two stages, the invention is not limited to two FETs, and the same effect can be obtained in a case in which a plurality of FETs are connected in multiple stages as long as the resonant circuit is provided outside the feedback loop.  
         [0062]    Fifth Embodiment  
         [0063]    [0063]FIG. 13 is a circuit diagram showing the semiconductor circuit according to the fifth embodiment of the present invention.  
         [0064]    As shown in FIG. 13, inputted signals in this embodiment are distributed into two differing signals, the two distributed signals are each amplified by amplifier circuit  12  and  13 , and the signals amplified by amplifiers  12  and  13  are then synthesized and outputted.  
         [0065]    Transformer T 1  grounded by way of capacitors C 34  and C 35  is provided as a distributing means that distributes signals inputted by way of input terminal  1  into two signals of different phase, and transformer T 2  that is grounded by way of capacitor C 37  is provided as a synthesizing means for synthesizing the two signals amplified by amplifiers  12  and  13 .  
         [0066]    Amplifier circuit  12  is made up of: FETs Q 11 -Q 13  connected in multiple stages; thermistor Rt 11  and resistor R 13  connected together in parallel and provided as the gate resistance of FET Q 11 , the second FET; inductor L 13  provided between the gate terminal of FET Q 11  and a connection point between thermistor Rt 11  and resistor R 13 ; resistor R 11 , capacitor C 11 , and thermistor Rt 12  connected in a series between the gate terminal, i.e., the input of amplifier circuit  12 , and the drain terminal of FET Q 12 ; resistor R 12  and capacitor C 12  connected in a series between the drain terminal of FET Q 12  and a prescribed potential; capacitor C 13  connected between the drain terminal of FET Q 12  and the other connection point between thermistor Rt 11  and resistor R 13 ; inductor L 11  and resistor R 17  connected in a series between the drain terminal of FET Q 12  and the source terminal of FET Q 11 ; capacitor C 15  connected between the connection point between inductor L 11  and resistor R 17  and the prescribed potential; resistor R 14 , capacitor C 14 , and thermistor Rt 13  connected in a series between the drain terminal of FET Q 12  and the drain terminal of FET Q 13 ; resistor R 16  connected to the gate terminal of FET Q 13 ; and resistor R 15 , inductor L 12 , and capacitor C 16  provided connected in parallel between the drain terminal of FET Q 13  and the output terminal of amplifier circuit  12 ; the drain terminal of FET Q 11  and the source terminal of FET Q 13  being connected.  
         [0067]    Amplifier circuit  13  is made up of: FETs Q 21 -Q 23  connected in multiple stages; thermistor Rt 21  and resistor R 23  connected together in parallel and provided as the gate resistance of FET Q 21 , the second FET; inductor L 23  provided between the gate terminal of FET Q 21  and a connection point between thermistor Rt 21  and resistor R 23 ; resistor R 21 , capacitor C 21 , and thermistor Rt 22  connected in a series between the gate terminal, i.e., the input of amplifier circuit  13 , and the drain terminal of FET Q 22 ; resistor R 22  and capacitor C 22  connected in a series between the drain terminal of FET Q 22  and a prescribed potential; capacitor C 23  connected between the drain terminal of FET Q 22  and the other connection point between thermistor Rt 21  and resistor R 23 ; inductor L 21  and resistor R 27  connected in a series between the drain terminal of FET Q 22  and the source terminal of FET Q 21 ; capacitor C 25  connected between the connection point between inductor L 21  and resistor R 27  and a prescribed potential; resistor R 24 , capacitor C 24 , and thermistor Rt 23  connected in a series between the drain terminal of FET Q 22  and the drain terminal of FET Q 23 ; resistor R 26  connected to the gate terminal of FET Q 23 ; and resistor R 25 , inductor L 22 , and capacitor C 26  provided connected in parallel between the drain terminal of FET Q 23  and the output terminal of amplifier circuit  13 ; the drain terminal of FET Q 21  and the source terminal of FET Q 23  being connected.  
         [0068]    The gate terminal of FET Q 13  and the gate terminal of FET Q 23  are connected by way of resistors R 16  and R 26 .  
         [0069]    On the input side of transformer T 1  are provided: capacitor C 33  and inductor L 31  connected in a series between transformer T 1  and input terminal  1 , capacitor C 31  and resistor R 31  connected in a series between the connection point between capacitor  33  and inductor L 31  and the prescribed potential, and capacitor C 32  connected between the connection point between capacitor  33  and inductor L 31  and the prescribed potential; and on the output side of transformer T 2  are provided: inductor L 32  and capacitor C 39  connected in a series between transformer T 2  and output terminal  2 , and capacitor C 38  connected between the connection point between inductor L 32  and capacitor C 39  and the prescribed potential.  
         [0070]    In addition, between amplifier circuit  12  and amplifier circuit  13  are provided: resistor R 41  connected between the source terminal of FET Q 11  and the source terminal of FET Q 21 , resistors R 39  and R 40  connected in a series between the gate terminal of FET Q 11  and the gate terminal of FET Q 21 , resistors R 33  and R 34  connected in a series between the connection point between resistor R 39  and resistor R 40  and transformer T 1 , resistor R 32  and thermistors Rt 31  and Rt 32  connected in a series between the connection point between resistor R 33  and transformer T 1  and the prescribed potential, resistor R 35  connected between the prescribed potential and the connection point between resistor R 34  and the connection point between resistors R 39  and R 40 , resistor R 37  connected between the source terminal of FET Q 12  and the source terminal of FET Q 22 , resistor R 36  connected between the source terminal of FET Q 12  and the prescribed potential, resistor R 38  connected between the source terminal of FET Q 22  and the prescribed potential, resistors R 42  and R 43  connected between transformer T 2  and the connection point between resistor R 16  and resistor R 26 , resistor R 44  and capacitor C 40  connected in parallel between the prescribed potential and the connection point between resistor R 42  and R 43 , and capacitor C 36  connected between the prescribed potential and the connection point between resistor R 42  and transformer T 2 ; and power supply voltage Vdd is impressed to the connection point between resistor R 33  and resistor R 34  as well as to the connection point between resistor R 42  and transformer T 2 .  
         [0071]    Thermistors Rt 11 , Rt 21 , and Rt 31  are thermally sensitive resistance elements in which resistance changes with a negative temperature characteristic according to the ambient temperature, and thermistors Rt 12 , Rt 13 , Rt 22 , Rt 23 , and Rt 32  are thermally sensitive resistance elements in which resistance changes with a positive temperature characteristic according to the ambient temperature.  
         [0072]    In a semiconductor circuit configured according to the foregoing description, peaking is brought about by resonance generated by inductor L 12  and capacitor C 16  (similarly, by resonance generated by inductor L 22  and capacitor C 26 ). As a result, the resonance frequency can be changed by changing the element constants of-this inductor L 12  and capacitor C 16  (similarly, the element constants of inductor L 22  and capacitor C 26 ), and moreover, Q can be controlled by resistors R 15  and R 25  for Q damping, and gain can therefore be set to a slope of 1 dB or more.  
         [0073]    In this embodiment, impedance changes because the constants of elements that constitute the circuit are changed, but only the output side impedance changes and the input side impedance undergoes no change. Because the resonant circuit constituted by inductor L 12  and capacitor C 16  is provided outside the feedback loop that uses FETs Q 11 -Q 13  in amplifier circuit  12  and the resonant circuit constituted by inductor L 22  and capacitor C 26  is provided outside the feedback loop that uses FETs Q 21 -Q 23  in amplifier circuit  13 .  
         [0074]    The embodiment therefore enables a reduction of time and trouble in design and adjustment.  
         [0075]    In addition, modification of the resonant frequency by altering the element constants obviates the need for variable bias for altering the gate bias of the FET, whereby a slope can be set to gain without increasing the scale of the circuit. Further, oscillation due to mismatching of impedance does not occur because alteration of the element constants does not take place in interstage elements.  
         [0076]    In this embodiment, thermistors Rt 11  and Rt 21  having a negative temperature characteristic are provided as the gate resistance of FETs Q 11  and Q 21 , respectively.  
         [0077]    In amplifier circuit  12 , fluctuations in gain characteristic with respect to ambient temperature in the gain slope that is generated in the resonant circuit constituted by inductor L 12  and capacitor C 16  are thus canceled out by fluctuations in the value of Q with respect to ambient temperature in the circuit constituted by capacitor C 13 , thermistor Rt 11 , and inductor L 13 , and the inclination of the gain slope outputted from amplifier circuit  12  is therefore uniform despite variations in the ambient temperature.  
         [0078]    Similarly, in amplifier circuit  13 , fluctuations in gain characteristic with respect to ambient temperature in the gain slope that is generated in the resonant circuit constituted by inductor L 22  and capacitor C 26  are canceled out by fluctuations in the value of Q with respect to ambient temperature in the circuit constituted by capacitor C 23 , thermistor Rt 21 , and inductor L 23 , and the inclination of the gain slope outputted from amplifier circuit  13  is therefore uniform despite variations in the ambient temperature.  
         [0079]    In this embodiment, thermistors Rt 31  and Rt 32  are connected in a series between prescribed potential and the connection point between resistor R 33  and transformer T 1 .  
         [0080]    As a result, the current in the vicinity of a prescribed temperature is therefore at a minimum, and the circuit current increases as the ambient temperature falls from the prescribed temperature and also increases as the ambient temperature rises from the prescribed temperature, thereby enabling prevention of deterioration of distortion characteristic due to change in temperature.  
         [0081]    In this embodiment, moreover, resistor R 43  having a resistance of 10-100 Ω is provided between resistor R 42  and the connection point between resistor R 16  and resistor R 26 , and capacitor C 40  is provided between the prescribed potential and the connection point between resistor R 42  and resistor R 43 , the circuit constants of these components being set according to termination conditions.  
         [0082]    Thus, in the case in which fluctuation in potential occurs at point A in the figure, the fluctuation in potential (wave) is absorbed by resistor R 43 , and a standing wave is not generated, thereby enabling prevention of deterioration by even distortion (principally CSO) that is caused by the standing wave.  
         [0083]    While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.

Technology Classification (CPC): 7