Patent Abstract:
The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.

Full Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a shift register and a display device. Specifically, the present invention relates to a shift register suitable for a drive circuit of a display device and a display device including the shift register. 
       BACKGROUND ART 
       [0002]    An active matrix display device creates images by writing a voltage in accordance with display data into pixels selected for each line individually and sequentially from pixels arranged in a matrix pattern. In order to select pixels for each line individually and sequentially, a shift register allowing an output signal (scanning signal) to sequentially shift depending on a clock signal is used as a gate driver. If dot sequential drive is performed, a similar shift register is formed in a source driver. 
         [0003]    Further, in a liquid crystal display device and the like, a gate driver may be integrally formed in a production process of a thin-film transistor (TFT) in a pixel. For example, when a TFT in a pixel is made of amorphous silicon, it is preferable that a shift register functioning as a gate driver be also made of amorphous silicon for a reduction in production costs. Thus, in recent years, the formation of a gate driver on a panel, that is, gate monolithic fabrication, has been developed. The term “gate monolithic fabrication” is also associated with the terms such as “gate driver-free”, “built-in gate driver in panel”, and “gate in panel”. 
         [0004]    A TFT made of amorphous silicon (hereinafter, also referred to as a-Si TFT) has low mobility, and therefore needs a high driving voltage. Accordingly, particularly in a large-sized display device, a high voltage needs to be supplied to a scanning signal line in order to drive an a-Si TFT in a pixel. Therefore, the channel width of the a-Si TFT in a gate driver is set to be large, and for example, it is set in mm order or cm order in the whole TFT. 
         [0005]    As such an a-Si TFT for agate driver, an a-Si TFT including a combination of a U-shaped source electrode line and an I-shaped drain electrode line is disclosed (see, for example, Patent Literature 1). 
         [0006]    A technology for forming a TFT for an optical sensor in a liquid crystal display device is disclosed (see, for example, Patent Literature 2). 
       CITATION LIST 
     Patent Literature 
       [0007]    Patent Literature 1: JP 2004-274050 A Patent Literature 2: JP 2009-145716 A 
       SUMMARY OF INVENTION 
     Technical Problem 
       [0008]    However, when a shift register is formed using a TFT having a conventional comb-shaped source/drain structure described in Patent Literature 1, display quality of a display device including such a shift register may be deteriorated. In addition, operation margin of the shift register may be reduced and the shift register may malfunction in operation. 
         [0009]      FIG. 10  shows an exemplary configuration of a shift register that is gate-monolithically fabricated. 
         [0010]    A shift register  100  includes a plurality of unit circuits  110  ( . . . , SRn−1, SRn, SRn+1, . . . ). Each unit circuit  110  is provided with input terminals INa and INb, an output terminal OUT, a power supply terminal VSS, and a clock terminal CK. 
         [0011]    The output signals OUT are sent out (fed into corresponding scanning signal lines) from the respective unit circuits  110  as output signals SROUT 1  to SROUTn, and each output signal is simultaneously fed into an input terminal INa of the next unit circuit  110  and an input terminal INb of the previous unit circuit  110 . A low level potential VSS which is a low-level power source voltage of each unit circuit  110  is fed into the power supply terminal VSS. A clock signal CK 1  is fed into a clock terminal CK of an odd-numbered unit circuit  110  and a clock signal CK 2  is fed into a clock terminal CK of an even-numbered unit circuit  110 . As shown in  FIG. 12 , the clock signals CK 1  and CK 2  have such phases that their high level periods do not overlap each other. 
         [0012]      FIG. 11  shows an exemplary configuration of each unit circuit of the shift register  100 . 
         [0013]    The each unit circuit  110  is provided with transistors  111   a  to  111   d  which are n-channel TFTs and capacitance  112 . 
         [0014]    In the transistor  111   a,  the gate and the drain are connected to the input terminal INa, and the source is connected to the gate of the transistor  111   d.  In the transistor  111   d,  the drain is connected to the clock terminal CK, and the source is connected to the output terminal OUT. That is, the transistor  111   d  functions as a transmission gate and controls the passage and cutout of a clock signal that is fed into the clock terminal CK. The capacitance  112  is connected between the gate of the transistor  111   d  and the source of the transistor  111   d.  A node with the same potential as the gate of the transistor  111   d  is referred to as netA. 
         [0015]    In the transistor  111   b,  the gate is connected to the input terminal INb, the drain is connected to the node netA, and the source is connected to the power supply terminal VSS. In the transistor  111   c,  the gate is connected to the input terminal INb, the drain is connected to the output terminal OUT, and the source is connected to the power supply terminal VSS. 
         [0016]    Operation of the shift register  100  is described below with reference to  FIG. 12 . 
         [0017]    The transistors  111   c  and  111   d  each are in a high impedance state until a shift pulse is fed into the input terminal INa. Therefore, in such a period, a low level voltage is held in the output terminal OUT. 
         [0018]    When a gate pulse of an output signal SROUT (OUTn−1 in  FIG. 12 ) sent out from the previous unit circuit, that is, a shift pulse, is fed into the input terminal INa, a period for generating an output pulse starts in the output terminal OUT, and the transistor  111   a  is turned ON to start the charge of the capacitance  112 . The charge of the capacitance  112  increases a potential of the node netA, which allows the transistor  111   d  to be turned ON. This causes a clock signal fed through the clock terminal CK to appear in the drain of the transistor  111   d.  At the instant when the clock pulse is fed into the clock terminal CK, the potential of the node netA is boosted due to a bootstrap effect of the capacitance  112 . As a result, the incoming clock pulse is transferred to the output terminal OUT of each unit circuit and is sent out from the output terminal OUT as a gate pulse (here, a pulse of an output signal SROUTn). 
         [0019]    After the completion of the feeding of the gate pulse into the input terminal INa, the transistor  111   a  is turned OFF. Then, in order to release charge retention caused by floating of the node netA and floating of the output terminals OUT of the unit circuits, the transistors  111   b  and  111   c  are turned ON by a reset pulse fed into the input terminal INb, and the node netA and the output terminal OUT are connected to the power supply voltage VSS. Thereafter, the transistor  111   d  is turned OFF. After the completion of the feeding of the reset pulse, the period of generation of the output pulse from the output terminal OUT ends and the period of retention of a low level voltage starts again. 
         [0020]    Thus, the gate pulse is sequentially fed into each gate line. 
         [0021]    The structures of these transistors are described. The transistors  111   a  to  111   d  each have a comb-shaped source/drain structure as shown in  FIGS. 13 and 14 . That is, a source electrode  118  and a drain electrode  119  are disposed facing each other on a gate electrode  114 , and a tooth of a comb of the source electrode  118  and a tooth of a comb of the drain electrode  119  are alternately arranged. 
         [0022]    As shown in  FIG. 15 , the transistors  111   a  to  111   d  are bottom gate TFTs, and each include the gate electrode  114  disposed on a substrate (not shown), a gate insulating film  115  disposed on the electrode  114 , an i layer  116  (semiconductor active layer) disposed on the film  115 , an n+ layer  117  (impurity diffused layer) disposed on the layer  116 , the source electrode  118  disposed on the layer  117 , and the drain electrode  119  disposed on the electrode  118 . 
         [0023]    However, in the shift register  100  as shown in  FIG. 16 , even when the transistor  111   d  is in an OFF state, the potential of the node netA may undulate, that is, the potential may be variable. This is because, in the transistor  111   d,  parasitic capacitance  113  is generated at a portion where the gate electrode  114  overlaps the drain electrode  119 , and the potential of the node netA is affected by change in potential of a clock signal CK even when the transistor  111   d  is in an OFF state. As a result, a leakage current may generate in the transistor  111   d.    
         [0024]    Further, in the shift register  100 , the transistors  111   c  and  111   d  each are in a high impedance state in a period where the output terminal OUT holds a low level voltage, whereby the output terminal OUT is turned into a floating state. Accordingly, such an output terminal OUT may not hold a low level voltage because of noise transmitted by, for example, cross coupling of a scanning signal line and a source signal line. In order to prevent such a problem, sink-down transistors are formed. The transistors connect the output terminal OUT with the low level power supply voltage VSS during the (voltage) low level holding period. 
         [0025]    In the low-level holding period, the transistor  111   b  is also in a high impedance state, and therefore, the node netA is turned into a floating state. Therefore, in order to prevent the transistor  111   d  from leaking, the sink-down transistors for connecting the node netA with the low level power supply voltage VSS in the low-level holding period may be formed. 
         [0026]    However, such sink-down transistors each also have a comb-shaped source/drain structure shown in  FIGS. 13 and 14 , and therefore, the parasitic capacitance may be generated between the source electrode  118  and the drain electrode  119 . Therefore, the sink-down transistors may not operate with good performance. 
         [0027]    In addition, in the transistor  111   a,  if the parasitic capacitance between the gate and drain is large, the initial rise in the voltage of the first node netA may be slow at the time of the application of a gate voltage Vgd, and the voltage of the node netA does not completely rise before a bootstrap effect is exerted, which may result in insufficient output. Further, even if the transistor  111   a  is in an OFF state at the time of sending an output signal, discharge occurs through the parasitic capacitance between the gate and drain and the parasitic capacitance between the gate and source, which may result in a voltage drop of the node netA. 
         [0028]    The problems described above may cause deterioration of display quality of a display device including a shift register that is gate-monolithically fabricated, reduction in operation margin of the shift register, and malfunctions in operation in the shift register. 
         [0029]    The present invention has been made in view of the above-mentioned state of the art, and an object of the present invention is to provide a shift register and a display device, each of which can operate stably. 
       Solution to Problem 
       [0030]    The present inventors made various investigations on a shift register which can operate stably, and noted a structure of a TFT forming the shift register. The present inventors found that in a bottom gate TFT having a comb-shaped source/drain structure, a reduction in parasitic capacitance can be achieved by a gate electrode provided with at least one of a cut and an opening in at least one of a region overlapping with a source electrode and a region overlapping with a drain electrode. Thereby the above-described problems have been solved, leading to completion of the present invention. 
         [0031]    That is, the present invention relates to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, 
         [0032]    the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, 
         [0033]    the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode. 
         [0034]    The configuration of the shift transistor of the present invention is not especially limited by other components as long as it essentially includes such components. 
         [0035]    Preferable embodiments of the shift register of the present invention are described in more detail below. 
         [0036]    The gate electrode preferably has the cut for suppressing parasitic capacitance more effectively. The gate electrode preferably has the opening for reducing parasitic capacitance and suppressing an increase in wiring resistance. 
         [0037]    The shift register preferably includes a clock terminal into which a clock signal is fed and an output terminal through which an output signal is sent out, and 
         [0038]    the shift register includes an output transistor disposed between the clock terminal and the output terminal, the output transistor switching passage and cutout of the clock signal according to a gate potential. 
         [0039]    The thin-film transistor is preferably the output transistor, and 
         [0040]    the at least one of a cut and an opening is formed in a region overlapping with one electrode connected to the clock terminal, the one electrode being selected from the source electrode and the drain electrode. Thus, the potential of a node which is connected to a gate of the output transistor can be suppressed from undulating in response to change in potential of a clock signal. Accordingly, the effect of the present invention can be particularly suitably achieved. 
         [0041]    In this case, the gate electrode is preferably provided with no cut and no opening in a region overlapping with one electrode selected from the source electrode and the drain electrode, the one electrode being connected to the output terminal. Thereby, a bootstrap effect can be improved. 
         [0042]    The thin-film transistor may be a transistor for applying a low level voltage to the output terminal at times other than a time of sending of the output signal, and 
         [0043]    the at least one of a cut and an opening is formed in a region overlapping with the source electrode and a region overlapping with the drain electrode. 
         [0044]    The thin-film transistor may be a transistor (sink-down transistor)for applying a low level voltage to a node connected to a gate of the output transistor during a period other than a period for turning the output transistor ON, and 
         [0045]    the at least one of a cut and an opening is formed in a region overlapping with the source electrode and a region overlapping with the drain electrode. 
         [0046]    The shift register may include a first transistor in which source or drain is connected to the gate of the output transistor, 
         [0047]    the thin-film transistor is a transistor for applying a low level voltage to a node connected to a gate of the first transistor during a period for turning the output transistor ON, and 
         [0048]    the at least one of a cut and an opening is formed in a region overlapping with the source electrode and a region overlapping with the drain electrode. 
         [0049]    Thereby, malfunctions in operation due to the parasitic capacitance can be effectively suppressed in the sink-down transistors. 
         [0050]    The shift register may include a cascade connection of a plurality of unit circuits and an input terminal into which a start pulse is fed or an output signal is fed from the previous circuit, 
         [0051]    the thin-film transistor is a transistor in which one of a source and a drain is connected to the gate of the output transistor and a gate and the other of the source and the drain are connected to the input terminal, 
         [0052]    the at least one of a cut and an opening is formed in a region overlapping with the source electrode and a region overlapping with the drain electrode. Thereby, insufficient output caused by slow initial rise in the voltage of a node that is connected to a gate of an output transistor and discharge in the transistor can be suppressed. 
         [0053]    The thin-film transistor is preferably formed of amorphous silicon. Thereby, the yield of the shift register can be remarkably increased. 
         [0054]    The present invention also relates to a display device, comprising: 
         [0055]    a plurality of pixel circuits arranged in a matrix pattern; and 
         [0056]    a driver including the shift register according to any one of the present invention. Thereby, the display device of the present invention includes the shift register that can operate stably in a driver, which can result in an increase in yield and a reduction in costs. 
       Advantageous Effects of Invention 
       [0057]    The shift register and the display device of the present invention can operate stably. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0058]      FIG. 1  is a block diagram showing a configuration of a shift register of Embodiment 1. 
           [0059]      FIG. 2  is a circuit diagram of a unit circuit included in the shift register of Embodiment 1. 
           [0060]      FIG. 3  is a timing chart of the shift register of Embodiment 1. 
           [0061]      FIG. 4  is a block diagram showing a configuration of a liquid crystal display device of Embodiment 1. 
           [0062]      FIG. 5  is a plan view schematically showing a configuration of a TFT of Embodiment 1. 
           [0063]      FIG. 6  is an enlarged view of  FIG. 5 . 
           [0064]      FIG. 7  is a cross-sectional view taken along the line A 1 -A 2  in  FIG. 6 . 
           [0065]      FIG. 8  is a timing chart of the shift register of Embodiment 1. 
           [0066]      FIG. 9  is a plan view schematically showing a configuration of the TFT of Embodiment 1. 
           [0067]      FIG. 10  is a block diagram showing a configuration of a conventional shift register. 
           [0068]      FIG. 11  is a circuit diagram of a unit circuit included in the conventional shift register. 
           [0069]      FIG. 12  is a timing chart of the conventional shift register. 
           [0070]      FIG. 13  is a plan view schematically showing a configuration of a conventional TFT. 
           [0071]      FIG. 14  is an enlarged view of  FIG. 13 . 
           [0072]      FIG. 15  is a cross-sectional view taken along the line X 1 -X 2  in  FIG. 14 . 
           [0073]      FIG. 16  is a timing chart of the conventional shift register. 
           [0074]      FIG. 17  is a plan view schematically showing a configuration of the TFT of Embodiment 1. 
           [0075]      FIG. 18  is a plan view schematically showing a configuration of the TFT of Embodiment 1. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0076]    The present invention will be mentioned in more detail referring to the drawings in the following embodiments, but is not limited to these embodiments. 
         [0077]    In the following description, a high-level potential is referred to as “VGH”, a low level potential is referred to as “VGL” unless otherwise noted, and the potential of the power supply terminal VSS is equal to a low level potential VGL. The name of a signal fed or sent out through a terminal in a circuit is the same as that of the terminal. For example, a signal fed through a clock terminal CK is named a clock signal CK. Further, n and m each are an integer of 2 or more, i is an integer of 1 or more and n or less, and j is an integer of 1 or more and m or less. 
       Embodiment 1 
       [0078]    A shift register  1  is constituted by cascade-connecting n unit circuits  10  as shown in  FIG. 1 . Each unit circuit  10  includes input terminals INa and INb, clock terminals CK and CKB, a power supply terminal VSS, a clear terminal CLR, and an output terminal OUT. 
         [0079]    A start pulse SP, an end pulse EP, clock signals CK 1  and CK 2  of two phases, a clear pulse CP, and a low level potential VSS are fed into the shift register  1  from outside. The start pulse SP is fed into the input terminal INa of the first unit circuit  10 . The end pulse EP is fed into the input terminal INb of an n-th unit circuit  10 . The clock signal CK 1  is fed into the clock terminals CK of the odd-numbered unit circuits  10  and clock terminals CKB of the even-numbered unit circuits  10 . The clock signal CK 2  is fed into the clock terminals CK of the even-numbered unit circuits  10  and the clock terminals CKB of the odd-numbered unit circuits  10 . The clear pulse CP is fed into the clear terminals CLR of all the unit circuits  10 . The low level potential VSS is fed into the power supply terminals VSS of all the unit circuits  10 . Output signals OUT of the unit circuits  10  are sent out to the outside as the respective output signals SROUT 1  to SROUTn, and each of the output signals is simultaneously fed into the input terminal INa of the next unit circuit  10  and the input terminal INb of the previous unit circuit  10 . 
         [0080]    As shown in  FIG. 2 , each unit circuit  10  includes transistors  11   a  to  11   j  which are n-channel TFTs, and capacitance  12 . The drain of the transistor  11   a  is connected to the clock terminal CK, and the source is connected to the output terminal OUT. The drain and the gate of the transistor  11   b  are connected to the input terminal INa, and the source of the transistor  11   b  is connected to the gate of the transistor  11   a.  The capacitance  12  is formed between the gate and the source of the transistor  11   a.  The drain of the transistor  11   c  is connected to the output terminal OUT, and the drain of the transistor  11   d  is connected to the gate of the transistor  11   a.  The gate of the transistor  11   c  and the gate of the transistor  11   d  are connected to the input terminal INb, and the source of the transistor  11   c  and the source of the transistor  11   d  are connected to the power supply terminal VSS. 
         [0081]    The drain of the transistor  11   e  is connected to the output terminal OUT, the gate of the transistor  11   e  is connected to the clock terminal CKB, and the source of the transistor  11   e  is connected to the power supply terminal VSS. The drain of the transistor  11   f  is connected to the gate of the transistor  11   a,  the gate of the transistor  11   f  is connected to the clear terminal, and the source of the transistor  11   f  is connected to the power supply terminal VSS. 
         [0082]    The drain of the transistor  11   g  is connected to the gate of the transistor  11   a,  and the source of the transistor  11   g  is connected to the power supply terminal VSS. The source of the transistor  11   h,  the drain of the transistor  11   i,  and the drain of the transistor  11   j  are connected to the gate of the transistor  11   g.  The drain and the gate of the transistor  11   h  are connected to the clock terminal CKB. The gate of the transistor  11   i  is connected to the gate of the transistor  11   a,  and the source of the transistor  11   i  is connected to the power supply terminal VSS. The gate of the transistor  11   j  is connected to the clock terminal CK, and the source of the transistor  11   j  is connected to the power supply terminal VSS. 
         [0083]    The transistor  11   a  is formed between the clock terminal CK and the output terminal OUT, and functions as an output transistor (transmission gate) for switching passage and cutout of a clock signal depending on the gate potential thereof. The gate of the transistor  11   a  is capacitively coupled with a conductive terminal (source) on the output terminal OUT side. Therefore, in a period in which the transistor  11   a  is in an ON state and the clock signal CK is in a high level, the gate potential of the transistor  11   a  is higher than the high-level potential of the clock signal CK. Hereinafter, a node to which the gate of the transistor  11   a  is connected is referred to as netA. 
         [0084]      FIG. 3  shows a timing chart of the shift register  1 . 
         [0085]      FIG. 3  shows voltage changes of input/output signals of an odd-numbered unit circuit  10  and the node netA. A clock signal CK 1  is fed into each of the odd-numbered unit circuits  10  through the clock terminal CK, and a clock signal CK 2  is fed into each of the odd-numbered unit circuits  10  through the clock terminal CKB. The clock signal CK 1  has a high potential period slightly shorter than one-half of the cycle of the clock signal CK 1 . The clock signal CK 2  is delayed by half the cycle of the clock signal CK 1 . That is, the clock signals CK 1  and CK 2  have such phases that their high level periods do not overlap with each other. 
         [0086]    Before the start of shift operation, a start pulse SP (not shown) is in high level during the same period as the high potential period of the clock signal CK 1 . After the end of the shift operation, an end pulse (not shown) is in high level during the same period as the high potential period of the clock signal CK 1 . 
         [0087]    At the time t 1 , the input signal INa (output signal sent out of the previous unit circuit  10 ) changes from low level to high level, and thereby the potential of the node netA also changes to high level via the diode-connected transistor  11   b.  As a result, the transistor  11   a  is turned ON. 
         [0088]    At the time t 2 , the input signal INa changes to low level, and thereby the transistor  11   b  is turned OFF and the node netA is turned into a floating state, but the transistor  11   a  is held in an ON state. 
         [0089]    At the time t 3 , the clock signal CK (clock signal CK 1 ) changes from low level to high level, and thereby the potential of the node netA changes to a level about twice as large as the amplitude Vck (=VGH−VGL) of the clock signal by a bootstrap effect. The clock signal CK passes through the transistor  11   a  without voltage drop because the gate potential of the transistor  11   a  is sufficiently high. 
         [0090]    In the period from the time t 3  at which the clock signal CK changes to high level to the time t 4 , the potential of the node netA changes to a level about twice as large as Vck and the output signal OUT changes to high level. 
         [0091]    At the time t 4 , the potential of the node netA changes to high level and the output signal OUT changes to low level. 
         [0092]    At the time t 5 , the input signal INb (output signal sent out of the next unit circuit  10 ) changes from low level to high level, and thereby the transistors  11   c  and  11   d  are turned ON. In the period where the transistor  11   c  is in an ON state, a low level potential is applied to the output terminal OUT. Further, when the transistor  11   d  is turned ON, the potential of the node netA changes to low level and the transistor  11   a  is turned OFF. 
         [0093]    At the time t 6 , the input signal INb changes to low level, the transistors  11   c  and  11   d  are turned OFF. At this time, the node netA is turned into a floating state, but the transistor  11   a  is held in an OFF state. Ideally, the transistor  11   a  is held in an OFF state and the output signal OUT is held in low level until the input signal INa again changes to high level. 
         [0094]    The transistor  11   e  is turned ON when the clock signal CKB (clock signal CK 2 ) is in high level. Every time the clock signal CKB changes to high level, a low level potential is applied to the output terminal OUT. Thus, the transistor  11   e  operates to repeatedly set the output terminal OUT at low level to stabilize the output signal OUT. 
         [0095]    The transistor  11   f  is turned ON when a clear signal CLR (clear pulse CP) is in high level. At this time, a low level potential is applied to the node netA. Thus, the transistor  11   f  operates to initialize the potential of the node netA to low level. 
         [0096]    The transistor  11   h  is turned ON when the clock signal CKB (clock signal CK 2 ) is in high level. At this time, a high level potential of the clock signal CKB is applied to a node netB. The transistor  11   i  is turned ON when the potential of the node netA is not lower than Vck. At this time, a low level potential is applied to the node netB. The transistor  11   j  is turned ON when the clock signal CK (clock signal CK 1 ) is in high level. At this time, a low level potential is applied to the node netB. 
         [0097]    Therefore, the potential of the node netB is in high level when the clock signal CK is in low level, the clock signal CKB is in high level, and the potential of the node netA is in low level. The potential of the node netB is in low level in the rest of the time. The transistor  11   g  is turned ON when the potential of the node netB is in high level. At this time, a low level potential is applied to the node netA. Thus, the transistors  11   g  to  11   j  each operate to hold a low level potential applied to the node netA. 
         [0098]    As described above, the transistors  11   c  and  11   e  are transistors (sink-down transistors) that operate to apply a low level voltage to the output terminal OUT during a period other than the period for sending out the output signal OUT. 
         [0099]    The transistors  11   d,    11   f  to  11   h,  and  11   j  are transistors (sink-down transistors) that operate to apply a low level voltage to the node netA that is connected to the gate of the transistor  11   a,  during a period other than the period for turning the transistor  11   a  (output transistor) ON. 
         [0100]    The transistor  11   i  is turned ON when the input signal INa is fed, and operates to apply a low level voltage to the node netB. Therefore, the transistor  11   g  is not turned ON during such a period, and the input signal INa can be applied to the node netA. Thus, the transistor  11   i  is a transistor (sink-down transistor) which operates to apply a low level voltage to the node netB that is connected to the gate of the transistor  11   g,  during a period for turning the transistor  11   a  (output transistor) ON. 
         [0101]    The shift register  1  is used for, for example, a drive circuit of a display device.  FIG. 4  is a block diagram showing a configuration of a liquid crystal display device including the shift transistor  1 . 
         [0102]    As shown in  FIG. 4 , the liquid crystal display device of the present embodiment is an active matrix display device, and includes a pixel array  2 , a display-control circuit  3 , a gate driver  4 , and a source driver  5 . In the present embodiment, the shift register  1  is used as the gate driver  4 . 
         [0103]    The pixel array  2  and the gate driver  4  are formed on a transparent insulating substrate such as a glass substrate. The source driver  5  is formed in a flexible printed circuit board. The display-control circuit  102  is formed in a control substrate. Thus, the gate driver  4  is monolithically formed on the substrate together with the pixel array  2 . The gate driver  4  may include all gate drivers of “gate monolithic”, “gate driver-free”, “built-in gate driver in panel”, and “gate in panel”. 
         [0104]    The pixel array  2  includes n scanning signal lines G 1  to Gn, m data signal lines S 1  to Sm, and (m×n) pixel circuits Pij. The scanning signal lines G 1  to Gn are arranged in parallel to one another, and the data signal lines S 1  to Sm are arranged in parallel to one another and perpendicular to the scanning signal lines G 1  to Gn. A pixel circuit Pij is arranged in the vicinity of the intersection of the scanning signal line Gi and the data signal line Sj. Thus, the (m×n) pixel circuits Pij are arranged in m rows and n columns to form a two-dimensional pattern (matrix pattern). The scanning signal line Gi is connected to all the pixel circuits Pij arranged in i-th row. The data signal line Sj is connected to all the pixel circuits Pij arranged in j-th column. A TFT (not shown) for a pixel is formed in each pixel circuit Pij as a switching element. Gate of the TFT for a pixel is connected to the scanning signal line Gi, drain of the TFT is connected to the data signal line Sj, and a source of the TFT for a pixel is connected to a pixel electrode (not shown). 
         [0105]    Control signals such as a horizontal synchronizing signal 
         [0106]    NC and a vertical synchronizing signal VSYNC, and display data DT are fed from outside the liquid crystal display device of the present embodiment. Based on such signals, the display-control circuit  3  feeds clock signals CK 1  and CK 2  and a start pulse SP into the gate driver  4  and feeds a control signal SC and a display data DT into the source driver  5 . 
         [0107]    The gate driver  4  includes n shift registers  1 . The shift registers  1  control output signals individually and sequentially from SROUT 1  to SROUTn in high level (a selected state), based on the clock signals CK 1  and CK 2 . The output signals SROUT 1  to SROUTn are fed into the scanning signal lines G 1  to Gn, respectively. Thereby, the scanning signal lines are selected individually and sequentially from G 1  to Gn, and thereby pixel circuits Pij arranged in one row are selected at a time. 
         [0108]    The source driver  5  applies a voltage depending on the display data DT to each of the data signal lines S 1  to Sm based on the control signal SC and the display data DT. Thereby, the voltage depending on the display data DT is written in the selected pixel circuits Pij arranged in one row. Thus, the liquid crystal display device  100  displays an image. 
         [0109]      FIGS. 5 to 7  each show a configuration of the transistor  11   a  (output transistor). 
         [0110]    The transistor  11   a  is a bottom gate thin-film transistor having a comb-shaped source/drain structure, as shown in  FIG. 5 . The channel width in one transistor is set to several millimeters to several centimeters, and the channel length in one transistor is set to several micrometers to tens of micrometers in one transistor. 
         [0111]    As shown in  FIG. 7 , a gate electrode  14  formed of a metal material, a gate insulating film  15  formed of a silicon-containing insulating film such as SiN, an i layer  16  (semiconductor active layer) formed of amorphous silicon, a n+ layer  17  formed of amorphous silicon which contains impurities (for example, phosphorus), a source electrode  18  and a drain electrode  19  that are formed of a metal material are stacked in this order on a transparent insulating substrate (not shown) such as a glass substrate. 
         [0112]    The TFT for a pixel is a bottom gate thin-film transistor similarly to the TFT included in the shift register  1 . The gate electrode  14  is formed of the same metal material as the gate electrode of the TFT for a pixel. The gate insulating film  15  is formed of the same insulating material as the gate insulating film of the TFT for a pixel. The i layer  16  is formed of the same semiconductor material as the i layer of the TFT for a pixel. The n+ layer  17  is formed of the same material as the n+ layer of the TFT for a pixel. The source electrode  18  and the drain electrode  19  are formed of the same metal material as the source electrode and the drain electrode of the TFT for a pixel. 
         [0113]    As shown in  FIG. 5 , the gate electrode  14  is formed in a squared U-shape when viewed in plan. The gate insulating film  15  is uniformly formed so as to cover the gate electrode  14 . The i layer  16  is formed in a squared U-shape when viewed in plan, similarly to the gate electrode  14 . Although a large portion of the i layer  16  is disposed within an area where the gate electrode  14  is formed, the i layer  16  partly projects from an area where the gate electrode  14  is formed and overlaps drain branch portions  19   b.  The n+ layer  17  is formed in an area where the i layer  16  overlaps the source electrode  18  or an area where the i layer  16  overlaps the drain electrode  19 . The n+ layer  17  makes Ohmic connections between the i layer  16  and the source electrode  18  and between the i layer  16  and the drain electrode  19 . 
         [0114]    The source electrode  18  and the drain electrode  19  each are shaped like a comb when viewed in plan. Specifically, the source electrode  18  includes a source trunk portion  18   a  and a plurality of source branch portions  18   b  that are branched from the trunk portion  18   a  and correspond to teeth of a comb. The source trunk portion  18   a  is formed in a squared U-shape when viewed in plan within an area overlapping with the gate electrode  14 , and arranged along the outer edge of the gate electrode  14 . Each source branch portion  18   b  is shaped like a straight line when viewed in plan within an area overlapping with the gate electrode  14 . The source branch portions  18   b  extend in parallel to one another from the source trunk portion  18   a  toward a space at the center of the gate electrode  14 . 
         [0115]    The drain electrode  19  includes a drain trunk portion  19   a  and a plurality of drain branch portions  19   b  that are branched from the drain trunk portion  19   a  and correspond to teeth of a comb. The drain trunk portion  19   a  is shaped like a straight line when viewed in plan, and disposed at a space at the center of the gate electrode  14  so as not to overlap the gate electrode  14 . The drain branch portion  19   b  is shaped like a straight line when viewed in plan, and extend in parallel to one another from the drain trunk portion  19   a  toward a space between the source branch portions  18   b.    
         [0116]    Thus, the source electrode  18  and the drain electrode  19  are disposed to face each other, and each source branch portion  18   b  and each drain trunk portion  19   a  are alternately arranged. 
         [0117]    As shown in  FIGS. 5 and 6 , the gate electrode  14  has cuts  14   a  in a region overlapping with the drain branch portions  19   b.  Thereby, parasitic capacitance  13  generated between the gate electrode  14  and the drain electrode  19  can be effectively reduced. Accordingly, as shown in  FIG. 8 , when the transistor  11   a  is in an OFF state, the potential of the node netA can be suppressed from undulating in response to change in potential of the clock signal CK. As a result, the operation of the shift register  1  can be stabilized. 
         [0118]    On the other hand, parasitic capacitance generated between the gate electrode  14  and the source electrode  18  may function as capacitance which contributes to a bootstrap effect, i.e., capacitance  12 . Accordingly, the gate electrode  14  has no cut in a region overlapping with the source electrode  18 . 
         [0119]      FIG. 9  shows a configuration of the transistor  11   b  and sink-down transistors (transistors  11   c  to  11   j ). 
         [0120]    These transistors each have a structure different from that of the transistor  11   a  (output transistor). In each transistor, the gate electrode  14  has cuts  14   b  also within an area overlapping with the source branch portions  18   b.  Thereby, in addition to the parasitic capacitance generated between the gate electrode  14  and the drain electrode  19 , parasitic capacitance generated between the gate electrode  14  and the source electrode  18  can be effectively reduced. Accordingly, malfunctions in operation in the sink-down transistors due to the parasitic capacitance can be effectively suppressed. Further, output shortage resulting from slow initial rise in potential of the node netA and occurrence of electric discharge through the transistor  11   b,  which are caused by the parasitic capacitance of the transistor  11   b,  can be suppressed. 
         [0121]    According to the present embodiment, when the output transistor is in an OFF state, the potential of the node netA can be suppressed from undulating in response to change in potential of the clock signal CK. Further, the sink-down transistors and the transistor  11   b  can favorably operate. As a result, the operation of the shift register  1  can be stabilized. 
         [0122]    Embodiment 1 shows the liquid crystal display device, but the display device of the present invention is not particularly limited thereto as long as the display device includes a shift register having a TFT. Examples of the display device of the present invention include an organic or inorganic EL display and a plasma display. 
         [0123]    In the transistor  11   a,  as shown in  FIG. 17 , the gate electrode  14  may be provided with openings  24   a  instead of the cuts  14   a  in a region overlapping with the drain branch portions  19   b.    
         [0124]    Similarly, in the transistor  11   b  and the sink-down transistors (transistors  11   c  to  11   j ), as shown in  FIG. 18 , the gate electrode  14  may be provided with openings  24   a  instead of the cuts  14   a  in an area overlapping with the drain branch portions  19   b.  Further, the gate electrode  14  may be provided with openings  24   b  instead of the cuts  14   b  in an area overlapping with the source electrode  18 . 
         [0125]    Such embodiments achieve a reduction in parasitic capacitance and prevention of an increase in wiring resistance. Of course, both the cuts and the openings may exist in each transistor. 
         [0126]    The shape of the gate electrode  14  viewed in plan is not particularly limited to a squared U-shape, and may be, for example, a rectangle or an L shape. 
         [0127]    The source branch portions  18   b  may not be perpendicular to the source trunk portion  18   a.  The drain branch portions  19   b  may not be perpendicular to the drain trunk portion  19   a.  The angle between each branched portion and each trunk portion may be optionally set. 
         [0128]    The semiconductor material is not particularly limited to amorphous silicon. Examples of the semiconductor material include polycrystalline silicon, CG silicon, and microcrystal silicon (μc-Si: microcrystal silicon). Particularly in a TFT made of amorphous silicon, a comb-shaped source/drain structure is advantageously used because a channel width can be increased to improve a drive ability. On the other hand, the source/drain structure that is shaped like teeth of a comb is likely to increase parasitic capacitance. In the case where the TFT of the present invention is prepared using amorphous silicon, a remarkable reduction in parasitic capacitance can be achieved. Thereby, the yield of the shift register can be remarkably increased and costs can be remarkably reduced. 
         [0129]    The present application claims priority to Patent Application No. 2009-267938 filed in Japan on Nov. 25, 2009 under the Paris Convention and provisions of national law in a designated State, the entire contents of which are hereby incorporated by reference. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           1 : Shift register 
           2 : Pixel array 
           3 : Display-control circuit 
           4 : Gate driver 
           5 : Source driver 
           10 : Unit circuit 
           11   a  to  11   j:  Transistor 
           12 ,  13 : Capacitance 
           14 : Gate electrode 
           14   a,    14   b:  Cut 
           15 : Gate insulating film 
           16 : i Layer 
           17 : n+ Layer 
           18 : Source electrode 
           18   a:  Source trunk portion 
           18   b:  Source branch portion 
           19 : Drain electrode 
           19   a:  Drain trunk portion 
           19   b:  Drain branch portion 
           24   a,    24   b:  Opening

Technology Classification (CPC): 6