Patent Abstract:
A variable gain element for adjusting a magnitude of an input signal. The variable gain element includes a first differential transistor pair having a first transistor coupled to a second transistor. A second differential transistor pair couples the second transistor to a supply voltage and to an output terminal of the first transistor. A load resistor couples the output terminal to the supply voltage. A control voltage applied to an input of the second differential pair causes a varying amount of current cancellation through the load resistor.

Full Description:
FIELD OF THE INVENTION 
     This invention generally relates to variable gain circuitry. More specifically, this invention relates to a variable gain element for adjusting an amplitude of an input signal. 
     BACKGROUND OF THE INVENTION 
     Cellular telephone usage has continued to increase in popularity. Cellular telephone manufacturers constantly strive to improve the performance of their products to gain market share. Specifically, manufacturers try to minimize the energy necessary to power the cellular telephone; this reduces battery drain and thus increases the available talk time of a cellular telephone on a single battery charge. Talk time is a critical performance specification that consumers use to compare various cellular telephones on the market. 
     Manufacturers are also constantly striving to improve the appearance of their products. Thus, manufacturers are always looking for ways to reduce the size of the cellular phones because consumers desire cellular telephones that are small and easy to carry. 
     Yet another design goal is to minimize the cost of the cellular telephone. A manufacturer can gain a significant competitive advantage if it can design a functioning cellular telephone at a low cost. 
     To meet the needs of minimizing battery drain, reducing the size of cellular telephones, and minimizing the manufacturing cost, more and more of the electrical circuit functions are accomplished through the use of integrated circuit technology. 
     Much of the functionality of the cellular telephone transceiver are embedded in integrated circuits. One key circuit block of both the receiver and the transmitter is a variable gain element. This can be in the form of a variable gain amplifier and/or variable gain attenuator. 
     For example, in a conventional cellular telephone transmitter, at least one variable gain element is needed to vary the transmitted output power in accordance with the cellular telephone standard. A cellular telephone that is close to a base station does not have to transmit as much power as a cellular telephone further away from the base station. 
     FIG. 1 shows a prior art variable gain element  10  suitable for integrated circuit technology. In any particular transmitter or receiver, the variable gain element  10  can be used at a radio frequency (RF), at an intermediate frequency (IF), or both. 
     At the core if variable gain element  10  is a pair of emitter coupled transistors, Q 1  and Q 2 . A differential signal input is applied to input ports  18  and  20 . A DC current source  16  couples the emitters of Q 1  and Q 2  to ground. 
     The collectors of Q 1  and Q 2  are each connected to emitter coupled differential pairs. For example, in the collector of Q 1  there is an emitter coupled pair Q 3  and Q 4 , and in the collector of Q 2  there is an emitter coupled pair Q 5  and Q 6 . The base terminals of Q 4  and Q 5  are connected together at port  32 , where a DC reference voltage is applied. The base terminals of Q 3  and Q 6  are connected together at control port  30 , where a DC control voltage is applied. The collector terminals of Q 3 , Q 4 , Q 5 , and Q 6  are each coupled to supply voltage  36  through separate resistors. The attenuated or amplified signal is coupled from the collector of Q 3  at output port  34 . If a differential output is desired, the complementary output signal can be coupled from the collector of Q 6 . 
     In operation, the differential input signal is applied to input ports  18  and  20 . The gain of the Q 1 /Q 2  differential pair is related to g m *R as is known in the art. However, the g m  here is manipulated by steering current away from load resistor  40  to decrease the gain (e.g. attenuate) or to load resistor  40  to increase the gain. This current steering is accomplished by altering the DC control voltage applied to control port  30 . For example, as the DC control voltage increases above the DC reference voltage at port  32 , the gain increases and the output signal increases in magnitude. Conversely, as the DC control voltage decreases below the DC reference voltage at port  32 , the gain decreases and the output signal appearing at output port  34  decreases in magnitude. 
     The variable gain element  10  has several drawbacks. First, the noise performance varies as a function of gain. For example, at maximum gain (Vcntl&gt;Vbias), transistors Q 3  and Q 6  are fully on, while Q 4  and Q 5  are essentially turned off. As the attenuation gain is decreased by about 6 dB (e.g. Vcntl reduced), transistors Q 3 , Q 4 , Q 5 , and Q 6  are all conducting and thus contribute to the overall noise performance of the variable gain element  10 . As the gain if further decreased to a minimum gain (e.g. Vcntl lowered below Vbias), only transistors Q 4  and Q 5  are conducting, and the noise power drops. Thus, there is a peaking in the noise power produced from the variable gain element  10 . 
     A second drawback relates to the intermodulation performance of the variable gain element. The intermodulation components of the variable gain element  10  peak at about a 6 dB cutback in the gain, and this degradation in the intermodulation performance degrades the overall performance of the transceiver. Thus, there is a need for a variable gain element suitable for integrated circuit implementation that has improved noise and intermodulation performance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a prior art circuit diagram of a variable gain element; 
     FIG. 2 is a circuit diagram of a variable gain element in accordance with a first embodiment of the present invention; and 
     FIG. 3 is a circuit diagram of a variable gain element in accordance with a second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 2 is a circuit diagram of a variable gain element  40  in accordance with a first embodiment of the present invention. The variable gain element  40  includes a first differential pair  41  with the emitters  43  and  45  of first transistor  42  and second transistor  44 , respectively, coupled through a current source  46  to ground. 
     To increase the linearity of the variable gain element  40 , degeneration resistors  48  and  50  may optionally couple the emitters  43  and  45 , respectively, to the current source  46 . It will be obvious to those skilled in the art that other forms of degeneration may be employed. For example, inductors may be used in place of resistors to provide RF linearity without incurring a DC voltage drop. Alternatively, separate current sources can individually couple emitters  43  and  45  directly to ground, and a single degeneration resistor then couples emitters  43  and  45  together (again to avoid a DC voltage drop across the degeneration resistance). 
     The collector  47  of first transistor  42  is coupled to a supply voltage  62  through load resistor  60 . A single ended version of the output signal is extracted from the collector  47  at output port  61 . 
     A second differential pair  51  couples the collector  49  of second transistor  44  to both the collector  47  of first transistor  42  and to the supply voltage  62 . The second differential pair  51  includes third transistor  52  with its emitter coupled to the emitter of fourth transistor  54  at point. The coupled emitters at point  53  are connected to the collector  49  of second transistor  44 . The collector of fourth transistor  54  is coupled to the supply voltage  62 , and the collector of third transistor  52  is coupled to the collector  47  of first transistor  42 . 
     A DC reference voltage  56  is applied to the base of fourth transistor  54 , and a DC control voltage  58  is applied to the base of third transistor  52 . The governing equations for the cancellation of current to control the gain/attenuation of variable gain element  40  is as follows: 
     
       
           I   1   =I   Q   +I   s   (1) 
       
     
     
       
           I   2   =I   Q   −i   s   (2) 
       
     
     
       
           i   L   =I   1   +I   3   (3) 
       
     
     
       
         
           
             
               
                 
                   
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     where: 
     I 1  represents the emitter current of first resistor  42 , 
     I Q  represents the half the quiescent current established by current source  46 , 
     I s  represents the small signal current, 
     I 2  represents the emitter current of second transistor  44 , 
     I L  represents the current passing through load resistor  60 , 
     I 3  represents the emitter current of third transistor  52 , 
       VC  represents the DC control voltage (−0.5≦V c ≦0.5), and 
     V T  represents the thermal voltage (˜26 mV at room temperature). 
     In operation, a differential AC input signal is applied to the input of the first differential pair  41 . As shown, the input comprises the base  55  of first transistor  42  and the base  57  of second transistor  44 . The variable gain element  40  utilizes signal current cancellation to vary the gain. The signal current is the current produced by the AC input signal (as opposed to the DC quiescent current). 
     In operation, first transistor  42  and second transistor  44  are biased to conduct at all times (e.g. 360 degree conduction angle). As V cntrl  increases to a maximum voltage above V cm , third transistor fully conducts while fourth transistor is essentially cut off. Therefore, all of the collector current traveling through second transistor  44  travels through third transistor  52 , and the signal current component I s  cancels through load resistor  60 . Thus, at maximum attenuation, the current passing through load resistor  60  is substantially  2 I Q . 
     As V cntrl  decreases, fourth transistor  54  begins to conduct, and the current I 3  passing through third transistor  52  decreases. Therefore, there is less small signal current cancellation at load resistor  60  so that the gain increases (attenuation decreases). At the maximum gain/minimum attenuation setting, corresponding to V cntrl &lt;V cm , the current passing through load resistor  60  is substantially I Q +I s . The use of AC coupling can remove the DC current component for all gain settings as is known in the art. Attenuation ranges of 30 to 50 dB can be obtained. 
     The variable gain element  40  utilizes two less transistors than the prior art variable gain element  10 . Therefore, the variable gain element  40  has two less transistors to contribute to both noise and intermodulation power so that noise and intermodulation performance is improved over the prior art. 
     FIG. 3 is a circuit diagram of a variable gain element  70  in accordance with a second embodiment of the present invention. The variable gain element  70  includes a first differential pair of first transistor  72  and second transistor  74 . The emitters are coupled through a first current source  76  to ground. Once again, degeneration in the emitters of first transistor  72  and second transistor  74  can be used to increase the linearity. 
     First voltage source  86  and second voltage source  84  is shown to have a common mode voltage component V cm  to DC bias first transistor  72  and second transistor  74 . A control voltage V cntrl  component is applied to the base of first transistor  72  to adjust the gain of the variable gain element  70 . 
     The collector of first transistor  72  is coupled to a supply voltage  84  through first load resistor  78 . The collector of second transistor  74  is connected directly to the supply voltage  84  or alternatively coupled through a resistor of the same value as first load resistor  78 . A second load resistor  80  is coupled from the supply voltage  84  to ground through second current source  82 . 
     In the illustrated embodiment, the actual input signal is applied to the variable gain element  70  by current coupling the input signal to first current source  76  and second current source  82 . This can be accomplished through the use of conventional current mirror circuitry as is known in the art. 
     When first transistor  72  is biased fully on by V cntrl , all of current I 2  passes through first transistor  72  and first load resistor  78 . Since the signal current is is mapped both to first current source  76  and second current source  82 , the differential voltage drop across the load  86  is substantially zero. Conversely, when second transistor  74  is fully conducting, most of current  12  passes is directed through second transistor  74  so that there is negligible current drop across first load resistor  78 . Therefore, the differential output voltage is proportional to the second load resistance times the current I 1 . 
     The previous description of the preferred embodiments are provided to enable any person skilled in the art to practice the preferred embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. For example, the preferred embodiments have been described with the use of bipolar junction transistors (BJTs). The embodiments are equally applicable with the use of field effect transistors (FETs). The base terminal of the BJT corresponds to the gate terminal of the FET, the collector terminal of the BJT corresponds to the drain terminal of the FET, and the emitter terminal of the BJT corresponds to the source terminal of the FET. 
     In addition, the loads can comprise elements other than resistors. For example, inductive loads can be utilized.

Technology Classification (CPC): 7