Patent Abstract:
An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION  
         [0001]    This application is based upon and claims priority from prior French Patent Application No. 02 13755, filed on Nov. 4, 2002, the entire disclosure of which is herein incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention pertains to an output buffer register, and finds applications, in particular, in electronic systems comprising a system bus and functional modules linked to the system bus by way of appropriate communication ports, in particular microprocessors.  
           [0004]    2. Description of the Related Art  
           [0005]    An output buffer register is a circuit which is intended to be arranged at the output of a functional module, upstream of a communication port of master type which links it to the bus. Its function is to deliver output signals of the functional module.  
           [0006]    According to a known design rule applied by the person of ordinary skill in the art, all of the output signals can be delivered on the respective data outputs of flip-flops. This makes it possible to limit the latency introduced at the output.  
           [0007]    The micro-architecture of a known output buffer register, in accordance with the diagram of FIG. 1, complies with this design rule.  
           [0008]    The output buffer register comprises a single flip-flop register  436  or input register, and an input multiplexer  435 .  
           [0009]    The register  436  comprises a given number N of flip-flops, each having a data input, a data output and an enable input. The multiplexer  435  comprises N first inputs  435   a,  N second inputs  435   b,  N outputs  435   c  and a selection input  435   d.    
           [0010]    The N inputs  435   a  of the multiplexer respectively receive the N input signals data_in. The N outputs  435   c  of the multiplexer are respectively linked to the N data inputs of the register  436 . The N data outputs  436   b  of the respective flip-flops of the register  436  deliver N output signals data_out, respectively. These N output signals are moreover delivered on the N inputs  435   b  of the multiplexer  435 .  
           [0011]    The N enable inputs  436   c  of the respective flip-flops of the register  436  receive a clock signal CLK. Moreover, an update_data signal is received on the selection input  435   d  of the multiplexer  435 . This signal is an enable signal which is for example delivered by a state machine.  
           [0012]    The register  436  in combination with the multiplexer  435  makes it possible to latch the values of the output signals when the update_data signal is at 0.  
           [0013]    This prior art complies with the aforesaid design rule, since the output signals are delivered by data outputs of flip-flops.  
           [0014]    On the other hand, the update_data signal drives N enable inputs, namely the inputs  435   d  of the N flip-flops of the multiplexer  435 . This often requires the introduction of what is referred to as a “buffer tree”, which increases the intricacy of the micro-structure and introduces some latency at the input of the buffer register.  
           [0015]    Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.  
         SUMMARY OF THE INVENTION  
         [0016]    The invention aims to remedy this drawback of the prior art.  
           [0017]    For this purpose, a first aspect of the invention relates to an output buffer register which comprises:  
           [0018]    a first flip-flop register comprising a given number N of flip-flops each having a data input, a data output and an enable input;  
           [0019]    a second flip-flop register comprising N flip-flops, each having a data input, a data output and an enable input;  
           [0020]    a third flip-flop register comprising a flip-flop having a data input, a data output and an enable input; and  
           [0021]    an output multiplexer having N first inputs, N second inputs, N outputs and a selection input.  
           [0022]    The enable inputs of the flip-flops of the first, second, and third registers receive one and the same clock signal. The data inputs of the N flip-flops of the first register respectively receive N input signals. The data outputs of the N flip-flops of the first register are respectively linked to the N first inputs of the output multiplexer. The N outputs of the output multiplexer deliver N respective output signals. The data inputs of the N flip-flops of the second register are respectively linked to the N outputs of the output multiplexer. The N data outputs of the N flip-flops of the second register are respectively linked to the N second inputs of the output multiplexer. The data input of the third register receives an enable signal. Finally, the data output of the third register is linked to the selection input of the output multiplexer.  
           [0023]    The drawback of the output buffer register in accordance with the prior art that was mentioned in the introduction does not exist with the output buffer register according to the invention. Specifically, the enable signal enters on the data input of the third flip-flop only. The advantages of the invention as compared with the prior art are especially noticeable for high values of N (typically for N greater than 10).  
           [0024]    Certainly, the output buffer register according to the invention requires 2N+1 flip-flops while that according to the prior art comprises only N. When N is large, this amounts to doubling the number of flip-flops, this having consequences on the area of silicon occupied by the output register.  
           [0025]    Furthermore, the micro-structure of the output buffer register according to the invention does not comply with the design rule presented in the introduction, since the output signals are delivered by an output multiplexer. This introduces some latency at the output. Nevertheless, this latency is acceptable having regard to the gain in time at the input of the buffer register.  
           [0026]    A second aspect of the invention relates to a method for delivering output signals with the aid of an output buffer register, the method comprising the steps of:  
           [0027]    applying a given number N of input signals to the data inputs of N respective flip-flops of a first flip-flop register comprising a given number N of flip-flops each having a data input, a data output and an enable input;  
           [0028]    linking the data outputs of the N flip-flops of the first register respectively to N first inputs of an output multiplexer having N first inputs, N second inputs, N outputs, and a selection input;  
           [0029]    linking the data inputs of N flip-flops of a second flip-flops register comprising N flip-flops each having a data input, a data output and an enable input, respectively to the N outputs of the output multiplexer which deliver N respective output signals;  
           [0030]    linking the N data outputs of the N flip-flops of the second register respectively to the N second inputs of the output multiplexer;  
           [0031]    linking the data output of a third flip-flop register comprising a flip-flop having a data input, a data output and an enable input, to the selection input of the output multiplexer;  
           [0032]    applying an enable signal to the data input; and  
           [0033]    applying one and the same clock signal to the enable inputs of the flip-flops of the first, second and third registers.  
           [0034]    Finally, a third aspect of the invention relates to an electronic system comprising a system bus and at least one system module connected to the system bus by way of an appropriate communication port. The system module comprises an output buffer register according to the first aspect of the invention, which is arranged upstream of the communication port. According to an embodiment of the present invention, an integrated circuit can include an output buffer register, according to the first aspect of the invention, and thereby provide the significant benefits of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0035]    Other characteristics and advantages of the invention will become further apparent on reading the description that follows. The latter is purely illustrative and should be read in conjunction with the appended drawings in which:  
         [0036]    [0036]FIG. 1 is a diagram of a buffer register according to the prior art;  
         [0037]    [0037]FIG. 2 is a schematic diagram of an exemplary electronic system according to the invention; and  
         [0038]    [0038]FIG. 3 is a diagram of an exemplary embodiment of an output buffer register according to the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0039]    In FIG. 2, an electronic system  10 , such as a microprocessor, comprises a system bus  12  and at least one system module  11 .  
         [0040]    The system module is linked to the system bus  12  by way of an appropriate communication port  44 , such as a master port. Such a system module can be a microprocessor core, an interface for accessing to resources external to the microprocessor (in particular memories), or any other functional module, or the like.  
         [0041]    In one example, the system module  11  comprises elements forming a combinatorial logic unit  43  (known as “glue” in the jargon of the person skilled in the art), and an output buffer circuit  42  arranged downstream of the logic unit  43  and upstream of the port  44 . This circuit  42  has the function of delivering output signals emanating from the logic unit  43 , so that they are transmitted on the bus  12 . Instead of the logic unit  43 , it is possible to envision any other element or any combination of elements performing a function of the system module  11 .  
         [0042]    For the sake of generality, the output buffer register  42  is considered to transmit a given number N of signals. Preferably, N is greater than 10. In one example, N is equal to 126.  
         [0043]    [0043]FIG. 2 shows an exemplary embodiment of an output buffer register  42  according to the invention. The register  42  comprises three registers with flip-flops and an output multiplexer.  
         [0044]    The register  42  thus comprises a first flip-flops register  431  or data input register. The register  431  comprises N flip-flops each having a data input, a data output and an enable input. The N data inputs  431  a of the N flip-flops respectively receive N input signals data_in. The N data outputs  431   b  of the N flip-flops are linked to N first respective inputs  434   a  of an output multiplexer  434 , having N first inputs  434   a,  N second inputs  434   b,  N outputs  434   c  and a selection input  434   d.  The N outputs  434   c  of the output multiplexer  434  deliver N output signals data_out.  
         [0045]    The register  42  further comprises a second flip-flops register  432  or latching register. The register  432  also has N flip-flops, each having a data input, a data output and an enable input. The N data inputs  432   a  of the N flip-flops of the register  432  are respectively linked to the N outputs  434   b  of the output multiplexer  434 , so as respectively to receive the N output signals. Further, the N data outputs of the flip-flops of the register  432  are respectively linked to the N second inputs of the output multiplexer  434 .  
         [0046]    The register  42  further comprises a third flip-flop register  433  or enable register. The register  433  comprises a flip-flop that has a data input  433   a,  a data output  433   b  and an enable input  433   c.  The data input  433   a  receives the update_data enable signal delivered by a state machine forming part of a combinatorial logic unit  43 . The data output  433   b  is linked to the selection input of the output multiplexer  434 .  
         [0047]    The enable inputs  431   c,    432   c  and  433   c  of the respective flip-flops of the registers  431 ,  432  and  433 , respectively receive the signal CLK, that is the system clock signal.  
         [0048]    The manner of operation of the output buffer register  42  of FIG. 3 is as follows.  
         [0049]    Let us assume that at a given instant, the update_data signal switches from 0 to 1. At the next clock pulse, the value 1 is stored in the enable register  433 . Further, the current values of the N input signals are stored in the input register  432 . The N first inputs  434   a  of the output multiplexer  434  are selected by the signal delivered by the data output  433   b  of the register  433 . Consequently, the current values of the N input signals are delivered by the N outputs  434   c  of the multiplexer  434  as the N output signals, this being so irrespective of the previous values of the output signals, which were stored in the register  432 . At the next clock pulse, the new values of the N output signals are stored in the latching register  432 .  
         [0050]    Let us now assume that the update_data signal switches back to 0. At the next clock pulse, the value 0 is stored in the enable register  433 . The second inputs  434   b  of the multiplexer  434  are therefore selected. Consequently, the values of the N output signals, which were previously stored in the latching register  432 , are delivered by the N outputs of the multiplexer  434  as the N output signals, this being so irrespective of the (possibly new) values of the N input signals. Stated otherwise, the values of the N output signals are latched by the latching register  432 .  
         [0051]    In one exemplary embodiment, the flip-flops are D type flip-flops.  
         [0052]    The present invention is not limited to the examples described above. Many alternative embodiments are possible without departing from the scope defined by the appended claims. For example, it should be obvious to those of ordinary skill in the art in view of the present discussion that alternative embodiments of the new and novel output buffer circuit may be implemented in an integrated circuit comprising a circuit supporting substrate that supports at least a portion of the new and novel output buffer circuit discussed above. Additionally, the new and novel integrated circuit may be implemented in a computer system comprising at least one integrated circuit thereby providing the advantages of the present invention to such computer system.  
         [0053]    While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those of ordinary skill in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention.  
         [0054]    Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.

Technology Classification (CPC): 6