Patent Abstract:
Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this configuration, a wiring resistance of the gate line can be lowered with minimizing the change of the process and without increasing the thickness of the gate line.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of Korea Patent Application No. 2003-87793 filed on Nov. 29, 2003, which is incorporated herein by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a flat panel display and method of fabricating the same and, more particularly, to an active matrix flat panel display and method of fabricating the same.  
         [0004]     2. Description of the Related Art  
         [0005]     An active matrix flat panel display can be provided with pixels arranged in a matrix form. In an active matrix flat panel display, the pixel generally comprises at least one thin film transistor, a pixel electrode controlled by the thin film transistor, and an opposite electrode corresponding to the pixel electrode. If an organic emission layer is interposed between the pixel electrode and the opposite electrode, the device is typically described as an organic light-emitting device, whereas if a liquid crystal layer is interposed therebetween, the device is typically called a liquid crystal display.  
         [0006]     Such an active matrix flat panel display typically comprises pixels defined by a plurality of gate lines and a plurality of data lines. The pixels can be arranged in a matrix form, and the matrix-like arranged pixels may be referred to as a pixel array. A gate driving circuit applying scan signals to the gate lines in sequence and a data driving circuit applying data signals to the data lines may be placed in the periphery of the pixel array.  
         [0007]     Here, the wiring resistance of the gate line can cause the scan signal applied from the gate driving circuit to the gate line to be delayed. Further, the delay of the scan signal can deteriorate the picture quality at the pixels positioned far from the gate driving circuit. Hence, as the flat panel device becomes large, this problem can seriously affect the quality of the image on the flat panel display.  
         [0008]     To solve the foregoing problems, another gate driving circuit can additionally be provided in the periphery of the pixel array. Thus one gate line can receive the scan signal from two gate driving circuits at both sides. However, this structure can increase the size of the panel.  
         [0009]     Alternatively, to solve the foregoing problems, the gate line may be made thicker, thereby reducing its sheet resistance. However, a thick gate line can cause stress imbalance with other layers.  
       SUMMARY OF THE INVENTION  
       [0010]     The present invention can provide a flat panel display in which a voltage drop in a gate line is decreased. It can also provide a method for making such a flat panel display.  
         [0011]     A flat panel display can include a substrate, a gate line formed on the substrate along a predetermined direction, and a gate electrode electrically connected to the gate line. The gate electrode may have a different sheet resistance than the gate line.  
         [0012]     A flat panel display can alternatively include a substrate, a gate line formed on the substrate along a predetermined direction, and a gate electrode electrically connected to the gate line. The gate line may have been doped with ions.  
         [0013]     A method of fabricating a flat panel display may include providing a substrate having a wiring region and a first transistor region, forming a first active layer on the first transistor region, forming a gate line and a first gate electrode in the wiring region and the first transistor region, respectively. It may also include doping the gate line with ions while masking the first gate electrode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a plan view of an organic light-emitting device according to an embodiment of the present invention.  
         [0015]      FIGS. 2A, 2B ,  2 C,  2 D, and  2 E are cross-sectional views for illustrating a method of fabricating an organic light-emitting device according to an embodiment of the present invention.  
         [0016]      FIG. 3  is a graph showing a sheet resistance change of a gate line to the dose of an ion implantation.  
         [0017]      FIG. 4  is a graph showing an estimated thickness of the gate line with the decreased sheet resistance. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like numbers refer to like elements throughout the specification.  
         [0019]     As shown in  FIG. 1 , a plurality of gate lines  131  may be arranged in a predetermined direction. A plurality of data lines  155  may be arranged in a direction crossing the gate lines  131 . The data lines  155  and the gate lines  131  may be insulated from each other. A plurality of common power lines  157  may be arranged in a direction crossing the gate line  131  and parallel with the data lines  155 . The common power lines  157  and the gate lines  131  may be insulated from each other.  
         [0020]     The plurality of gate lines  131 , the plurality of data lines  155 , and the plurality of common power lines  157  may define pixels arranged in a matrix form. The matrix-like arrangement of pixels may be called a pixel array. Each pixel may include a switching thin film transistor  210 , a driving thin film transistor  230 , a capacitor  220 , and an organic light-emitting diode  240 .  
         [0021]     The switching thin film transistor  210  may include a semiconductor layer  110  having source/drain regions; a gate electrode  135  connected to the gate line  131 ; and source/drain electrodes  150  connected to the source/drain regions of the semiconductor layer  110  via a contact hole. Further, the driving thin film transistor  230  may include a semiconductor layer  113  having source/drain regions, a gate electrode  133 , and source/drain electrodes  153  connected to the source/drain regions of the semiconductor layer  113  via a contact hole.  
         [0022]     The capacitor  220  may include a lower electrode  132  connected to the gate electrode  133  of the driving thin film transistor  230 . It may also be connected to one of the source/drain electrodes  150  of the switching thin film transistor  210  via the contact hole. The capacitor  220  may also include an upper electrode  158  connected to one of the source/drain electrodes  153  of the driving thin film transistor  230  via the contact hole and the common power line  157 . A pixel electrode  170  may be connected to the other of the source/drain electrode  153  of the driving thin film transistor  230  through a via hole  165   a.    
         [0023]     A gate driving circuit  500  applying scan signals to the gate lines  131  in sequence, and a data driving circuit  600  applying data signals to the data lines  153  may be placed in the periphery of the pixel array.  
         [0024]     The gate line  131  may be ion doped thereby providing it with a low wiring resistance. This low wiring resistance may lower the voltage drop in the gate line  131 . Further, the gate line  131  may have a low wiring resistance as compared with the gate electrode  135  of the switching thin film transistor  210  and the gate electrode  133  of the driving thin film transistor  230 .  
         [0025]     As shown in  FIG. 2A , a substrate  100  can include a wiring region (A), a first transistor region (B) and a second transistor region (C). The wiring region (A) may be a region on which the gate line may be formed. The first transistor region (B) may be a region on which the switching thin film transistor may be formed. The second transistor region (C) may be a partial circuit region on which a circuit thin film transistor with a type different from the switching thin film transistor may be formed.  
         [0026]     A buffer layer  105  may be formed on the substrate  100 . The buffer layer  105  may protect the thin film transistor from impurities emitted from the substrate  100 . The buffer layer  105  can be made of a silicon oxide layer, a silicon nitride layer, or a stacked multi-layer thereof.  
         [0027]     A first active layer  110  and a second active layer  115  may be formed on the buffer layer  105  of the first and second transistor regions (B, C). The first and second active layers  110  and  115  can be made of amorphous silicon or polycrystalline silicon. A gate insulating layer  120  may be formed on substantially the entire surface of the substrate  100  including the first and second active layers  110  and  115 . A conductive layer  130  may be formed on the gate insulating layer  120 .  
         [0028]     The conductive layer  130  may preferably be made of one or more of the following: aluminum (Al), aluminum alloy, molybdenum (Mo), and molybdenum alloy. A particularly suitable molybdenum alloy may be a molybdenum-tungsten alloy. Further, the conductive layer  130  may be about 150 to about 400 nm thick. Such a thickness may help to ensure that the gate wiring formed in the process described below has the proper wiring resistance.  
         [0029]     A first photoresist pattern  310  covering a predetermined portion of the wiring region (A) may be formed on the conductive layer  130 , a portion of the first active layer  110  excluding the ends thereof, and the whole area of the second transistor region (C).  
         [0030]     As shown in  FIG. 2B , the conductive layer  130  may be etched using the first photoresist pattern  310  as a mask. Thus a gate line  131  and a first gate electrode  135  may be formed on the wiring region (A) and the first transistor region (B), respectively. Using the first photoresist pattern  310  and the first gate electrode  135  as a mask, both ends of the first active layer  110  may be doped with a first ion so that first source/drain regions  110   a  are formed at both ends of the first active layer  110 . Thus, a first channel region  110   b  interposed between the first source/drain regions  110   a  may be defined.  
         [0031]     The doping process may be performed using an ion-showering method. An ion-showering method may allow the ions to be active at a low temperature as compared with a temperature of ion implantation method. Additionally, in this method, discharged particles may be accelerated and injected without mass separation. Hence, during the ion-doping process, a significant amount of hydrogen ions may permeate into a film.  
         [0032]     The first ion may be doped by ion-showering with the first photoresist pattern  310  thickly left on the first gate electrode  135 . Therefore the gate insulating layer  120  and the first semiconductor layer  110  under the first gate electrode  135  may be protected from having the hydrogen ion injected into them.  
         [0033]     Thus, the gate insulating layer  120  and the first semiconductor layer  110  can keep their layer properties and their interface properties. Further, the threshold voltage, electron mobility, and reliability of the thin film transistor may improve. For this, the first photo resist pattern  310  may be about 5000 Å or more thick.  
         [0034]     As shown in  FIG. 2C , after the first photoresist pattern  310  of  FIG. 2B  is removed, a second photoreist pattern  320  may be formed completely covering the wiring region (A) and the first transistor region (B) and covering the conductive layer  130  except for both ends of second active layer  115 . Then, the conductive layer  130  may be etched using the second photoresist pattern  320  as a mask, thereby forming a second gate electrode  137 .  
         [0035]     Using the second photoresist pattern  320  and the second gate electrode  137  as a mask, both ends of the second active layer  115  may be lightly doped with a second ion. Thus lightly-doped source/drain regions  115   a  may be formed at both ends of the second active layer  115 . Thus, a second channel region  115   b  interposed between the lightly-doped source/drain regions  115   a  may be defined. The second ion preferably may have a type different from the first ion. For example, the first ion may be a p-type, and the second ion may be an n-type.  
         [0036]     Like the first ion doping process, the doping process may be performed using ion-showering method. The second ion may be doped by ion-showering with the second photoresist pattern  320  thickly remaining on the second gate electrode  137 . Thus the gate insulating layer  120  and the second semiconductor layer  115  under the second gate electrode  137  may be protected from hydrogen ion injecting. Similarly, the second photo resist pattern  320  may be about 5000 Å or more thick.  
         [0037]     As shown in  FIG. 2D , the second photoresist pattern  320  of  FIG. 2C  may be removed. Next, a third photoreist pattern  330  may be formed exposing the wiring region (A), but completely covering the first transistor region (B) as well as the second gate electrode  137  and its lateral sides. Using the third photoresist pattern  330  as a mask, the gate line  131  and the second active layer  115  may be highly doped with the second ion. Thus highly-doped source/drain regions  115   c  may be formed in the second active layer  115   c . To make the highly doped source/drain region  115   c  have proper electric conductivity, the second ion may preferably be injected with about 3.0E15 ions/cm 2  to about 5.0E15 ions/cm 2 . The doping process may be performed using ion-showering.  
         [0038]     At this time, the gate line  131  may be doped with the second ion. Thus the wiring resistance can be low. The gate electrodes  135  and  137  may be masked by the foregoing photoresist patterns  310 ,  320 , and  330  in the above-described ion doping process. Thus they may not be doped with ions. Hence, the wiring resistance of the gate line  131  may be low compared to that of the gate electrodes  135  and  137 . Thus, a voltage drop in the gate line  131  may be effectively eliminated, and noticeable signal delay may be prevented.  
         [0039]     As shown in  FIG. 2E , the third photoresist pattern  330  of  FIG. 2D  may be removed exposing the gate electrodes  135  and  137 . An interlayer  140  may be formed on the exposed gate electrodes  135  and  137 . The interlayer  140  may preferably be made of silicon oxide.  
         [0040]     Next, a contact hole may be formed in the interlayer  140 , and source/drain electrode materials may be laminated over the interlayer  140 . Then, the laminated source/drain electrode materials may be patterned to form a first source/drain electrode  150  and a second source/drain electrode  155  on the interlayer  140 . The first and second source/drain electrodes  150  and  155  may be in contact with the first and second active layers  110  and  115 , respectively, through the contact hole.  
         [0041]     Thereafter, sequential processes may be performed by any suitable method (such as a typical conventional method), thereby fabricating the organic light-emitting device.  
         [0042]     As shown in  FIG. 3 , the more the dose of ion doping increases, the more the sheet resistance of the gate line decreases. However, the sheet resistance of the gate line may decreased by about 9% to about 15% when the dose of ion implantation is in a range of between about 3.0E15 ions/cm 2  and about 5.0E15 ions/cm 2 . Such a range may be a proper dose of ion implantation for forming the source/drain region on the semiconductor layer. Consequently, the sheet resistance of the gate line may be about 85% to about 91% as compared with that of the gate electrodes  135  and  137  of  FIG. 2E  which are not doped with ions.  
         [0043]     As shown in  FIG. 4 , when the dose of ion implantation is about 3.0E15 ions/cm 2 , the sheet resistance of the gate line may decreased by 9%. This may have the same effect as the gate line having a thickness of about 3000 Å (at a point of ‘p’). Similarly, when the dose of ion implantation is about 5.0E15 ions/cm 2 , the sheet resistance of the gate line may decrease by 15%. This may have the same effect as the gate line having a thickness of about 3800 Å (at a point of ‘q’). By way of comparison, the thickness of the gate line doped with the ions may substantially be about 2000 Å. Therefore, the voltage drop may be prevented without increasing the thickness of the gate line.  
         [0044]     As described above, the wiring resistance of a gate line can be selectively lowered while minimizing the change of the process and without increasing the thickness of the gate line. Further, a semiconductor layer may be doped with ions by ion-showering using a photoreist pattern and a gate electrode as a mask. Thus a thin film transistor may be saved from deterioration.  
         [0045]     While the present invention has been described with reference to a particular embodiment, the disclosure has been made for purpose of illustrating the invention by way of examples and not to limit the scope of the invention. One skilled in the art can change the described embodiments without departing from the scope of the invention.

Technology Classification (CPC): 7