Patent Abstract:
A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of application Ser. No. 14/459,433, filed Aug. 14, 2014, which is a divisional of application Ser. No. 12/535,489, filed Aug. 4, 2009, which is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-209121 filed on Aug. 15, 2008, the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     An aspect of the embodiments discussed herein is directed to a semiconductor device having a multilayer interconnection structure. 
     BACKGROUND 
     In current semiconductor integrated circuit devices, a multilayer interconnection structure has been used to interconnect among semiconductor elements. In ultrafine and ultra high-speed semiconductor devices, in order to reduce the problem of signal delay (RC delay), a low-resistance copper (Cu) pattern is used as a wiring pattern. 
     In order to form a copper wire, a so-called damascene method or dual-damascene method has been used. The damascene method is a method of forming a wire in which a Cu layer is buried in a wire groove or a via hole formed in an interlayer insulating layer using chemical mechanical polishing (CMP). 
     When the Cu wire is formed, a diffusion-reducing barrier is formed to reduce the diffusion of Cu atoms into an interlayer insulating layer. For the diffusion-reducing barrier, in general, refractory metals, such as tantalum (Ta), titanium (Ti), and tungsten (W), and conductive nitrides of the above refractory metals have been used. 
     However, the above materials have a higher resistivity than that of Cu; hence, in order to further decrease the wiring resistance, the thickness of the diffusion-reducing barrier may be decreased as small as possible. Accordingly, Japanese Laid-open Patent Publication No. 2007-59660 discusses a technique that a Cu—Mn alloy is used instead of the diffusion-reducing barrier. The reason for this is that MnSi x O y  is formed in a self-alignment manner at the interface between an interlayer insulating layer and a Cu wire by a reaction of Mn with O 2  and Si, which are contained in the interlayer insulating layer, and that Mn oxides function as a diffusion-reducing layer. However, at the interface between the interlayer insulating layer and the Cu wire, when Mn which is not allowed to react with O 2  contained in the interlayer insulating layer dissolves in the Cu wire, the resistance of the Cu wire may increase. 
     SUMMARY 
     According to an aspect of an embodiment, a semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a plan view illustrating the structure of a semiconductor device  50   a  according to a first embodiment; 
         FIG. 1B  is a cross-sectional view of the semiconductor device  50   a  taken along the line X-Y illustrated in  FIG. 1A ; 
         FIGS. 2A-2B  are views each illustrating a method of manufacturing the semiconductor device  50   a  according to the first embodiment; 
         FIGS. 3A-3B  are views each illustrating the method of manufacturing the semiconductor device  50   a  according to the first embodiment; 
         FIGS. 4A-4B  are views each illustrating the method of manufacturing the semiconductor device  50   a  according to the first embodiment; 
         FIGS. 5A-5B  are views each illustrating the method of manufacturing the semiconductor device  50   a  according to the first embodiment; 
         FIG. 6A  is a plan view illustrating the structure of a semiconductor device  50   b  according to a second embodiment; 
         FIG. 6B  is a cross-sectional view of the semiconductor device  50   b  taken along the line X-Y illustrated in  FIG. 6A ; 
         FIG. 7A  is a plan view illustrating the structure of a semiconductor device  50   c  according to a third embodiment; and 
         FIG. 7B  is a cross-sectional view of the semiconductor device  50   c  taken along the line X-Y illustrated in  FIG. 7A . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, a first embodiment, a second embodiment, and a third embodiment will be described. However, the present technique is not limited to the embodiments mentioned above. 
     In the first embodiment,  FIGS. 1A to 6B  are views illustrating a semiconductor device  50   a  and a method of manufacturing the same in detail. 
     According to the structure of the semiconductor device  50   a  of the first embodiment and to the method of manufacturing the same, a contact area between an insulating layer containing oxygen and a second barrier layer containing Mn may be increased. Hence, Mn may be sufficiently consumed by the formation of Mn oxides at a portion at which the contact area between the insulating layer and the second barrier layer is increased, and an increase in resistance of a copper wire may be reduced. 
       FIGS. 1A and 1B  each illustrate the structure of the semiconductor device  50   a  of the first embodiment.  FIG. 1A  is a plan view of the semiconductor device  50   a .  FIG. 1B  is a cross-sectional view taken along the line X-Y illustrated in  FIG. 1A . 
     In the semiconductor device  50   a  of the first embodiment illustrated in  FIG. 1A , a fourth interlayer insulating layer is represented by reference numeral  15   b , second wires (Cu wire) are each represented by reference numeral  19   b , and a third wire is represented by reference numeral  19   c . The fourth interlayer insulating layer  15   b  is formed so as to cover an n-type MOS transistor forming region  30   a  and a p-type MOS transistor forming region  30   b . The fourth interlayer insulating layer  15   b  is preferably formed of SiO 2 . As a material forming the interlayer insulating layer  15   b , a material is preferably used which has a higher resistance against chemical mechanical polishing (CMP) than that of a third interlayer insulating layer  14   b  which will be described later. 
     The second wires  19   b  are formed so as to be partly overlapped with the n-type MOS transistor forming the region  30   a  and the p-type MOS transistor forming the region  30   b . The second wires  19   b  each have an approximately rectangular shape or an approximately circular shape. The second wires  19   b  are each preferably formed so as to be electrically connected to the n-type MOS transistor forming the region  30   a  and the p-type MOS transistor forming the region  30   b . The second wires  19   b  are preferably formed of copper (Cu) which has a low resistivity. 
     The third wire  19   c  is formed in the vicinity of the p-type MOS transistor forming the region  30   b . The third wire  19   c  has an approximately rectangular shape. The third wire  19   c  is not electrically connected to the n-type MOS transistor forming the region  30   a  and the p-type MOS transistor forming the region  30   b . The third wire  19   c  is preferably formed of Cu which has a low resistivity. 
     In  FIG. 1B , the semiconductor device  50   a  according to the first embodiment includes a transistor forming layer  60  and a multilayer interconnection structure  40   a . The transistor forming layer  60  has the n-type MOS transistor forming the region  30   a  and the p-type MOS transistor forming the region  30   b . The multilayer interconnection structure  40   a  has first wires  19   a , the second wires  19   b , and the third wire  19   c . In addition, in  FIG. 1B , constituents similar to those described with reference to  FIG. 1A  are designated by the same reference numerals. 
     As illustrated in  FIG. 1B , a silicon substrate  1  has an n-type conductivity. An element isolation region  2  has a shallow trench isolation structure. The n-type MOS transistor forming region  30   a  and the p-type MOS transistor forming region  30   b  are defined by the element isolation region  2 . 
     In the n-type MOS transistor forming region  30   a , a p-type well region is represented by reference numeral  3   a , a gate insulating film is represented by reference numeral  4   a , a gate electrode is represented by reference numeral  5   a , a source region is represented by reference numeral  7   a , a drain region is represented by reference numeral  8   a , and a silicide layer is represented by reference numeral  9   a.    
     The p-type well region  3   a  is formed by performing ion-implantation of a p-type impurity in the silicon substrate  1 . The gate insulating film  4   a  is formed on the silicon substrate  1  in the p-type well region  3   a . The gate electrode  5   a  is formed on the silicon substrate  1  with the gate insulating film  4   a  interposed therebetween. Sidewalls  6   a  are formed on side walls of the gate electrode  5   a . The sidewalls  6   a  may be formed using silicon oxide (SiO 2 ) which is an insulating material. The source region  7   a  and the drain region  8   a  are formed in the p-type well region  3   a  of the silicon substrate  1 . The silicide layers  9   a  are provided on the gate electrode  5   a  and in the surface of the silicon substrate  1  in the source region  7   a  and the drain region  8   a.    
     In the p-type MOS transistor forming region  30   b , an n-type well region is represented by reference numeral  3   b , a gate insulating film is represented by reference numeral  4   b , a gate electrode is represented by reference numeral  5   b , a source region is represented by reference numeral  7   b , a drain region is represented by reference numeral  8   b , and a silicide layer is represented by reference numeral  9   b.    
     The n-type well region  3   b  is formed by performing ion-implantation of an n-type impurity in the silicon substrate  1 . The gate oxide film  4   b  is formed on the silicon substrate  1  in the n-type well region  3   b . The gate electrode  5   b  is formed on the silicon substrate  1  with the gate oxide film  4   b  interposed therebetween. Sidewalls  6   b  are formed on side walls of the gate electrode  5   b . The sidewalls  6   b  may be formed using silicon oxide (SiO 2 ) which is an insulating material. The source region  7   b  and the drain region  8   b  are formed in the n-type well region  3   b  of the silicon substrate  1 . The silicide layers  9   b  are provided on the gate electrode  5   b  and in the surface of the silicon substrate  1  in the source region  7   b  and the drain region  8   b.    
     A protective layer  11  is formed so as to cover the silicon substrate  1 , that is, so as to cover the n-type MOS transistor forming region  30   a  and the p-type MOS transistor forming region  30   b  on the silicon substrate  1 . The protective layer  11  is preferably formed, for example, of silicon nitride (SiN). The protective layer ills formed to protect the n-type MOS transistor forming region  30   a  and the p-type MOS transistor forming region  30   b.    
     A first interlayer insulating layer  12  is formed on the protective layer  11 . The first interlayer insulating layer  12  is preferably formed, for example, of silicon oxide (SiO 2 ). The first interlayer insulating layer  12  is formed to ensure the insulation between the n-type MOS transistor forming region  30   a  and the p-type MOS transistor forming region  30   b.    
     Openings  24   a  are formed to penetrate the protective layer  11  and the first interlayer insulating layer  12  so that conductive materials to be filled in the openings  24   a  are electrically connected to the gate electrode  5   a , the source region  7   a , and the drain region  8   a  of the n-type MOS transistor forming region  30   a . Openings  24   b  are formed to penetrate the protective layer  11  and the first interlayer insulating layer  12  so that conductive materials to be filled in the openings  24   b  are electrically connected to the gate electrode  5   b , the source region  7   b , and the drain region  8   b  of the p-type MOS transistor forming region  30   b.    
     A wire  10   a  is formed by burying a conductive material in each opening  24   a . A wire  10   b  is formed by burying a conductive material in each opening  24   b . The conductive materials are each preferably formed, for example, of copper (Cu). In addition, the wire  10   a  and the corresponding opening  24   a  are collectively called a contact via, and the wire  10   b  and the corresponding opening  24   b  are also collectively called a contact via. 
     In the multilayer interconnection structure  40   a , a second interlayer insulating layer is represented by reference numeral  13   a , a third interlayer insulating layer is represented by reference numeral  14   a , a fourth interlayer insulating layer is represented by reference numeral  15   a , a second interlayer insulating layer is represented by reference numeral  13   b , a third interlayer insulating layer is represented by reference numeral  14   b , a fourth interlayer insulating layer is represented by reference numeral  15   b , a first barrier layer is represented by reference numeral  16   a , a second barrier layer is represented by reference numeral  17   a , a conductive layer is represented by reference numeral  18   a , the first wire is represented by reference numeral  19   a , a first barrier layer is represented by reference numeral  16   b , a second barrier layer is represented by reference numeral  17   b , a conductive layer is represented by reference numeral  18   b , the second wire is represented by reference numeral  19   b , a first barrier layer is represented by reference numeral  16   c , a second barrier layer is represented by reference numeral  17   c , a conductive layer is represented by reference numeral  18   c , the third wire is represented by reference numeral  19   c , a dummy plug is represented by reference numeral  20   c , and openings are represented by reference numerals  21   a ,  21   b , and  21   c.    
     The second interlayer insulating layer  13   a  is formed on the first interlayer insulating layer  12 . The second interlayer insulating layer  13   a  is preferably formed, for example, of silicon carbide (SiC). The second interlayer insulating layer  13   a  preferably has a thickness of 15 nm to 30 nm. The second interlayer insulating layer  13   a  functions as an etching stopper when the openings  21   a , which will be described later, are formed. 
     The third interlayer insulating layer  14   a  is formed on the second interlayer insulating layer  13   a . The third interlayer insulating layer  14   a  is preferably formed, for example, of a low dielectric-constant material having a relative dielectric constant of 3.2 or less. As the low dielectric-constant material, for example, methylated-hydrogen silsesquioxane (MSQ) having a relative dielectric constant of 2.6, SiLK K or porous SiLK K, which are the registered trade names of Dow Chemical Company, a hydrocarbon-based polymer, or carbon-containing SiO 2  (SiOC) may be preferably used. The third interlayer insulating layer  14   a  is used to reduce the problem of signal delay (RC delay) in the multilayer interconnection structure. The third interlayer insulating layer  14   a  preferably has a thickness of 100 nm to 300 nm. 
     The fourth interlayer insulating layer  15   a  is formed on the third interlayer insulating layer  14   a . The fourth interlayer insulating layer  15   a  is preferably formed, for example, of SiO 2 . The fourth interlayer insulating layer  15   a  functions as a protective layer for the third interlayer insulating layer  14   a  having a low resistance against chemical mechanical polishing (CMP). The fourth interlayer insulating layer  15   a  preferably has a thickness of 15 nm to 30 nm. 
     The openings  21   a  are formed to penetrate the second interlayer insulating layer  13   a , the third interlayer insulating layer  14   a , and the fourth interlayer insulating layer  15   a  so that conductive materials to be filled in the openings  21   a  are electrically connected to the respective wires  10   a . The first wire  19   a  is formed of the conductive layer  18   a  buried in the opening  21   a . The conductive layer  18   a  is preferably formed, for example, of copper (Cu). 
     The first barrier layer  16   a  and the second barrier layer  17   a  are sequentially provided between the opening  21   a  and the conductive layer  18   a . The first barrier layer  16   a  is formed at the opening  21   a  side. The second barrier layer  17   a  is formed at the conductive layer  18   a  side. 
     Since the Cu wire is formed in the opening  21   a , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   a . As the material described above, for example, titanium (Ti), titanium nitride (TiN), titanium silicide nitride (TiSiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), or tantalum nitride (TaN) may be used. In addition, the first barrier layer  16   a  may be formed using a laminate including at least two layers of the above materials. The first barrier layer  16   a  preferably has a thickness of 3 nm to 10 nm. Incidentally, the first barrier layer  16   a  may only be formed when it is necessary. 
     The second barrier layer  17   a  is formed between the first barrier layer  16   a  and the conductive layer  18   a . Since the third interlayer insulating layer  14   a  is formed of SiOC, the fourth interlayer insulating layer  15   a  is formed of SiO 2 , and Mn also reacts with Si, the composition of Mn-containing oxides forming the second barrier layer  17   a  is represented by Mn x Si y O z (x:y:z is in the range of 1:1:3 to 1:3:5). In addition, the second barrier layer  17   a  preferably has a thickness of 1 nm to 5 nm. 
     The second interlayer insulating layer  13   b  is formed on the fourth interlayer insulating layer  15   a . The second interlayer insulating layer  13   b  is preferably formed, for example, of silicon carbide (SiC) as with the second interlayer insulating layer  13   a . The second interlayer insulating layer  13   b  preferably has a thickness of 15 nm to 30 nm. 
     The third interlayer insulating layer  14   b  is formed on the second interlayer insulating layer  13   b . As with the third interlayer insulating layer  14   a , the third interlayer insulating layer  14   b  is preferably formed, for example, of a low dielectric-constant material having a relative dielectric constant of 3.2 or less. The third interlayer insulating layer  14   b  preferably has a thickness of 100 nm to 300 nm. 
     The fourth interlayer insulating layer  15   b  is formed on the third interlayer insulating layer  14   b . As with the fourth interlayer insulating layer  15   a , the fourth interlayer insulating layer  15   b  is preferably formed, for example, of SiO 2 . The fourth interlayer insulating layer  15   b  functions as a protective layer for the third interlayer insulating layer  14   b  having a low CMP resistance. The fourth interlayer insulating layer  15   b  preferably has a thickness of 15 nm to 30 nm. 
     The openings  21   b  are formed to penetrate the second interlayer insulating layer  13   b , the third interlayer insulating layer  14   b , and the fourth interlayer insulating layer  15   b  so that conductive materials to be filled in the openings  21   b  are electrically connected to the respective first wires  19   a . The second wire  19   b  is formed of the conductive layer  18   b  buried in the opening  21   b . The conductive layer  18   b  is preferably formed, for example, of copper (Cu). 
     The first barrier layer  16   b  and the second barrier layer  17   b  are sequentially provided between the opening  21   b  and the conductive layer  18   b . The first barrier layer  16   b  is formed at the opening  21   b  side. The second barrier layer  17   b  is formed at the conductive layer  18   b  side. 
     Since the Cu wire is formed in the opening  21   b  as with the first barrier layer  16   a , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   b . The first barrier layer  16   b  preferably has a thickness of 3 nm to 10 nm. Incidentally, the first barrier layer  16   b  may only be formed when it is necessary. 
     As with the second barrier layer  17   a , the second barrier layer  17   b  is formed between the first barrier layer  16   b  and the conductive layer  18   b . Since the third interlayer insulating layer  14   b  is formed of SiOC, the fourth interlayer insulating layer  15   b  is formed of SiO 2 , and Mn also reacts with Si, the composition of Mn-containing oxides forming the second barrier layer  17   b  is represented by Mn x Si y O z (x:y:z is in the range of 1:1:3 to 1:3:5). In addition, the second barrier layer  17   b  preferably has a thickness of 1 nm to 5 nm. 
     The opening  21   c  is formed to penetrate the second interlayer insulating layer  13   b , the third interlayer insulating layer  14   b , and the fourth interlayer insulating layer  15   b . Unlike the opening  21   b , a conductive material to be filled in the opening  21   c  is not electrically connected to the first wire  19   a . The third wire  19   c  is formed by burying the conductive layer  18   c  in the opening  21   c . The conductive layer  18   c  is preferably formed, for example, of copper (Cu). 
     The dummy plug  20   c  is formed in a lower part of the opening  21   c . The dummy plug  20   c  has, for example, a cylindrical shape and is formed to have a width smaller than that of the opening  21   c . The dummy plug  20   c  is formed to increase formation areas of the second interlayer insulating layer  13   b , the third interlayer insulating layer  14   b , the conductive layer  18   c , and the second barrier layer  17   c . Accordingly, at a portion at which the contact area of the third wire  19   c  with the second interlayer insulating layer  13   b  and the third interlayer insulating layer  14   b  is increased, Mn may be sufficiently consumed by the formation of Mn oxides. Hence, the resistance of the Cu wire may be maintained at a low level. 
     In addition, although the resistivity of Cu is 1.55 Ω·cm, the resistivity of Mn is 136 Ω·cm. Hence, it is understood that the resistivity of Mn is significantly larger than that of Cu. Accordingly, when Mn is not sufficiently consumed between the third wire  19   c  and the third and fourth interlayer insulating layers  14   b  and  15   b , and when Mn dissolves in the Cu wire, the resistance of the Cu wire disadvantageously increases. 
     The first barrier layer  16   c  and the second barrier layer  17   c  are sequentially provided between the opening  21   c  and the conductive layer  18   c . The first barrier layer  16   c  is formed at the opening  21   c  side. The second barrier layer  17   c  is formed at the conductive layer  18   c  side. 
     Since the Cu wire is formed in the opening  21   c , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   c  as with the first barrier layer  16   b . The first barrier layer  16   c  preferably has a thickness of 3 nm to 10 nm. Incidentally, the first barrier layer  16   c  may only be formed when it is necessary. 
     As with the second barrier layer  17   b , the second barrier layer  17   c  is formed between the first barrier layer  16   c  and the conductive layer  18   c . Since the third interlayer insulating layer  14   b  is formed of SiOC, the fourth interlayer insulating layer  15   b  is formed of SiO 2 , and Mn also reacts with Si, the composition of Mn-containing oxides forming the second barrier layer  17   c  is represented by Mn x Si y O z (x:y:z is in the range of 1:1:3 to 1:3:5). In addition, the second barrier layer  17   c  preferably has a thickness of 1 nm to 5 nm. 
       FIGS. 2A to 5B  are views illustrating a method of manufacturing the semiconductor device  50   a  according to the first embodiment. 
       FIG. 2A  is a view illustrating the state in which a part of the multilayer interconnection structure  40   a  is formed on the transistor forming layer  60  illustrated in  FIG. 1B . 
     First, on the first interlayer insulating layer  12  (not illustrated in  FIG. 2A ) of the transistor forming layer  60 , the second interlayer insulating layer  13   a  composed, for example, of SiC having a thickness of 15 nm to 30 nm is formed by a chemical vapor deposition (CVD) method or the like. The first interlayer insulating layer  12  functions as an etching stopper when the openings  21   a  are formed which will be described later. 
     Next, the third interlayer insulating layer  14   a  composed, for example, of SiOC having a thickness of 100 nm to 300 nm is formed on the second interlayer insulating layer  13   a . The fourth interlayer insulating layer  15   a  is formed using a silane gas (such as trimethylsilane), for example, by a plasma chemical vapor deposition (CVD) method. The third interlayer insulating layer  14   a  is preferably formed, for example, from a low dielectric constant material having a relative dielectric constant of 3.2 or less. 
     Subsequently, on the third interlayer insulating layer  14   a , the fourth interlayer insulating layer  15   a  is formed, for example, from SiO 2  having a thickness of 15 nm to 30 nm. The fourth interlayer insulating layer  15   a  is formed using a silane gas (such as SiH 2 Cl 2 , SiH 4 , Si 2 H 4 , or Si 2 H 6 ) by a CVD method or the like. The fourth interlayer insulating layer  15   a  functions as a protective layer for the third interlayer insulating layer  14   a  having a low CMP resistance. 
     Next, by a lithography operation and an etching operation, the openings  21   a  are formed which penetrate the fourth interlayer insulating layer  15   a , the third interlayer insulating layer  14   a , and the second interlayer insulating layer  13   a  and which communicate with the wires  10   a  and  10   b  (not illustrated in  FIG. 2A ). The fourth interlayer insulating layer  15   a  is etched, for example, by a reactive ion etching (RIE) method using a C 4 F 6 /Ar/O 2  mixed gas including C 4 F 6  which is a fluorine-containing gas. The third interlayer insulating layer  14   a  is etched, for example, by an RIE method. The second interlayer insulating layer  13   a  is etched, for example, by an RIE method using a CH 2 F 2 /N 2 /O 2  mixed gas including CH 2 F 2  which is a fluorine-containing gas. For this etching, the chamber temperature is set to room temperature or the like, and the gas flow rates are set, for example, to 10 to 35 sccm for CH 2 F 2 , 50 to 100 sccm for N 2 , and 15 to 40 sccm for O 2 . 
     Subsequently, for example, by a physical vapor deposition (PVD) method, such as a sputtering method, the first barrier layer  16   a  composed, for example, of Ta having a thickness of 2 nm to 5 nm is formed. Since the Cu wire is formed in the opening  21   a , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   a . Incidentally, the first barrier layer  16   a  may only be formed when it is necessary. 
     Next, a CuMn alloy layer (not illustrated) composed, for example, of an alloy of Cu and manganese (Mn) having a thickness of 5 nm to 30 nm is formed so as to cover an inside wall of the opening  21   a  provided with the first barrier layer  16   a . The CuMn alloy layer contains 0.2 to 1.0 atomic percent of Mn atoms and preferably contains 0.5 atomic percent or less thereof. Besides the CuMn alloy layer, a layer composed of a mixture containing Mn in Cu may also be used. In addition, when the CuMn alloy layer reacts, the second barrier layer  17   a  which will be described later is formed, and hence the CuMn alloy layer may not be illustrated in  FIG. 2A . However, in a manufacturing process which will be described later, the CuMn alloy layer is illustrated. 
     Next, in a subsequent operation, by a heat treatment performed after the conductive layer  18   a  is buried in the opening  21   a , before Cu is diffused to the second interlayer insulating layer  13   a , the third interlayer insulating layer  14   a , and the fourth interlayer insulating layer  15   a , which are exposed to the side wall of the opening  21   a , Mn is diffused to the second interlayer insulating layer  13   a , the third interlayer insulating layer  14   a , and the fourth interlayer insulating layer  15   a . In addition, since Mn is allowed to react with oxygen contained in the third interlayer insulating layer  14   a  and the fourth interlayer insulating layer  15   a , the second barrier layer  17   a  composed of Mn-containing oxides is formed. 
     In the operation described above, although Mn is used as a metal material forming the alloy layer other than Cu, when a metal material is available which has a higher diffusion rate in Cu that that of Cu, and whose oxide has a Cu diffusion-reducing effect and superior adhesion to Cu, the above metal material may also be used as well as Mn. As the metal material described above, for example, besides Mn, niobium (Nb), zirconium (Zr), chromium (Cr), vanadium (V), yttrium (Y), technetium (Tc), or rhenium (Re) may be mentioned. 
     Since the CuMn alloy layer also functions as a seed layer of electrolytic plating, the thickness thereof is controlled to an appropriate value to form a buried wire in accordance with the wire dimension. In this embodiment, a CuMn alloy layer having a thickness, for example, of 5 nm to 30 nm is formed. 
     In this operation, the second barrier layer  17   a  is formed so as to cover the side wall of the opening  21   a . However, since Mn in the second barrier layer  17   a  is diffused by a subsequent heat treatment and is allowed to react with oxygen in the third interlayer insulating layer  14   a  and the fourth interlayer insulating layer  15   a , a CuMn alloy layer including Mn-containing oxides is formed; hence, the CuMn alloy layer covering the inside wall of the opening  21   a  may not have a uniform thickness. 
     Next, by an electrolytic plating method, the conductive layer  18   a  composed of Cu having a thickness of 0.5 μm to 2.0 μm is deposited so as to be buried in the opening  21   a . In this embodiment, although the conductive layer  18   a  composed of Cu is formed, the conductive layer  18   a  may be an alloy layer composed of Cu and a metal other than Cu, and as the metal other than Cu, a material is used which does not increase the resistance of a wire even when it is contained in Cu. 
     Subsequently, a heat treatment is performed at 100 to 250° C. for 1 to 60 minutes. By this heat treatment, Mn is diffused from the CuMn alloy layer and is allowed to react with oxygen contained in the third interlayer insulating layer  14   a  and the fourth interlayer insulating layer  15   a  exposed to the side wall of the opening  21   a . In addition, the second barrier layer  17   a  composed of Mn-containing oxides is formed to have a thickness of 1 nm to 5 nm on the side wall of the opening  21   a  provided with the first barrier layer  16   a.    
     Next, for example, by a CMP method, the first barrier layer  16   a , the second barrier layer  17   a , and the conductive layer  18   a  are partly removed approximately to the middle of the fourth interlayer insulating layer  15   a  by polishing, so that the first wire  19   a  composed of Cu is formed in the opening  21   a.    
       FIG. 2B  is a view illustrating the state in which the second interlayer insulating layer  13   b , the third interlayer insulating layer  14   b , and the fourth interlayer insulating layer  15   b  are sequentially formed in that order on the fourth interlayer insulating layer  15   a.    
     First, as in the case illustrated in  FIG. 2A , the second interlayer insulating layer  13   b  composed, for example, of SiC having a thickness of 15 nm to 30 nm is formed on the fourth interlayer insulating layer  15   a  (not illustrated in the figure) by a CVD method or the like. The fourth interlayer insulating layer  15   a  functions as an etching stopper when the openings  21   b  and  21   c  are formed which will be described later. 
     Subsequently, as in the case illustrated in  FIG. 2A , the third interlayer insulating layer  14   b  composed, for example, of SiOC having a thickness of 100 nm to 300 nm is formed on the second interlayer insulating layer  13   b  by a plasma CVD method or the like. 
     Next, the fourth interlayer insulating layer  15   b  composed, for example, of SiO 2  having a thickness of 15 nm to 30 nm is formed on the third interlayer insulating layer  14   b  by a CVD method or the like. 
       FIG. 3A  is a view illustrating the state in which openings  21   g  are formed by a lithography operation and an etching operation which penetrate the fourth interlayer insulating layer  15   b  and which each have a grooved shape in the third interlayer insulating layer  14   b.    
     As in the case illustrated in  FIG. 2A , the fourth interlayer insulating layer  15   b  is etched, for example, by an RIE method using a C 4 F 6 /Ar/O 2  mixed gas including C 4 F 6  which is a fluorine-containing gas. 
     As in the case illustrated in  FIG. 2A , the third interlayer insulating layer  14   b  is etched, for example, by an RIE method. By these etching operations, the openings  21   g  are formed which penetrate the fourth interlayer insulating layer  15   b  and which each have a grooved shape in the third interlayer insulating layer  14   b.    
       FIG. 3B  is a view illustrating the state in which the openings  21   b  and  21   c  are formed by a lithography operation and an etching operation which penetrate the fourth interlayer insulating layer  15   b  and which each have a via shape in the third interlayer insulating layer  14   b.    
     As in the case illustrated in  FIG. 2A , the fourth interlayer insulating layer  15   b  is etched, for example, by an RIE method using a C 4 F 6 /Ar/O 2  mixed gas including C 4 F 6  which is a fluorine-containing gas. 
     As in the case illustrated in  FIG. 2A , the third interlayer insulating layer  14   b  is etched, for example, by an RIE method. By this etching operation, the third interlayer insulating layer  14   b  located under the openings  21   g  is etched. By this etching operation, the second interlayer insulating layer  13   b  is exposed at the bottom of the openings  21   b  and  21   c.    
     The second interlayer insulating layer  13   b  is etched, for example, by an RIE method using a CH 2 F 2 /N 2 /O 2  mixed gas including CH 2 F 2  which is a fluorine-containing gas. For this etching, the chamber temperature is set to room temperature or the like, and the gas flow rates are set, for example, to 10 to 35 sccm for CH 2 F 2 , 50 to 100 sccm for N 2 , and 15 to 40 sccm for O 2 . By this etching operation, the via-shaped openings  21   b  and  21   c  are formed in the third interlayer insulating layer  14   b  and the second interlayer insulating layer  13   b.    
     The opening  21   b  is formed so that a conductive material to be filled in the opening  21   b  is electrically connected to the first wire  19   a . On the other hand, the opening  21   c  is formed on the fourth interlayer insulating layer  15   a  under which the first wire  19   a  is not provided. That is, in the opening  21   c , the third wire  19   c  is formed which will be described later. The width of the via shape is not particularly limited. Since it is intended to increase the surface area of the opening, a width smaller than that of the opening  21   g  is preferable. 
       FIG. 4A  is a view illustrating the state in which a first barrier layer  16   d  composed, for example, of Ta having a thickness of 3 nm to 10 nm is formed, for example, by a PVD method, such as a sputtering method, so as to cover the openings  21   g ,  21   b , and  21   c , and the fourth interlayer insulating layer  15   b . Since the Cu wire is formed in the openings  21   g ,  21   b , and  21   c , as in the case of the first barrier layer  16   a , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   d . Incidentally, the first barrier layer  16   d  may only be formed when it is necessary. 
       FIG. 4B  is a view illustrating the state in which while the first barrier layer  16   d  covers inside walls of the openings  21   g ,  21   b , and  21   c , a CuMn alloy layer  17   g  composed, for example, of an alloy of Cu and manganese (Mn) having a thickness of 5 nm to 30 nm is formed. Since the CuMn alloy layer  17   g  also functions as a seed layer of electrolytic plating which will be described later, the thickness thereof is controlled to an appropriate value to form a buried wire in accordance with the wire dimension. In this embodiment, a CuMn alloy layer having a thickness of 5 nm to 30 nm is formed. The CuMn alloy layer contains 0.2 to 1.0 atomic percent of Mn atoms and preferably contains 0.5 atomic percent or less. In addition, as the CuMn alloy layer  17   g , a layer composed of a mixture including Cu and Mn may also be used as well as the alloy. 
     In addition, since the surface area of the CuMn alloy layer  17   g  is increased by the presence of the openings  21   g ,  21   b , and  21   c , the CuMn alloy layer  17   g  formed to cover the openings  21   g ,  21   b , and  21   c  has a small thickness as compared to that of the CuMn alloy layer which is formed to cover the openings  21   a  by a sputtering method. 
     In this operation, the second barrier layer  17   a  is formed so as to cover the side walls of the openings  21   g ,  21   b , and  21   c . However, in a subsequent operation, since Mn in the second barrier layer  17   a  is diffused by a heat treatment and is allowed to react with oxygen in the third interlayer insulating layer  14   b  and the fourth interlayer insulating layer  15   b , a CuMn alloy layer including Mn-containing oxides is formed; hence the CuMn alloy layer covering the inside walls of the openings  21   g ,  21   b , and  21   c  may not have a uniform thickness. 
     In addition, since the opening  21   c  is formed, the CuMn alloy layer  17   g  may be formed to have a small thickness as compared to that obtained when the opening  21   c  is not formed, that is, when the surface area of the opening is not increased. The total amount of the CuMn alloy layer sputtered on the inside walls of the openings  21   g ,  21   b , and  21   c  is constant in one sputtering operation. Hence, when the surface area, that is, sputtered area, is large, the thickness of the CuMn alloy layer  17   g  formed by sputtering may be decreased. 
       FIG. 5A  is a view illustrating the state in which a conductive layer  18   d  composed of Cu having a thickness of 0.5 μm to 2.0 μm is deposited by an electrolytic plating method so as to be buried in the openings  21   g ,  21   b , and  21   c . In this embodiment, the conductive layer  18   d  composed of Cu is formed; however, the conductive layer  18   d  may be an alloy layer including Cu and a metal other than Cu, and as the metal other than Cu, a material is used which does not increase the resistance of a wire even when it is contained in Cu. 
     Next, a heat treatment is performed at 100 to 250° C. for 1 to 60 minutes. By the heat treatment performed after the conductive layer  18   d  is buried in the openings  21   g ,  21   b , and  21   c , before Cu is diffused to the second interlayer insulating layer  13   b , the third interlayer insulating layer  14   b , and the fourth interlayer insulating layer  15   b  exposed to the side walls of the openings  21   g ,  21   b , and  21   c , Mn is diffused to the second interlayer insulating layer  13   b , the third interlayer insulating layer  14   b , and the fourth interlayer insulating layer  15   b . Subsequently, Mn is allowed to react with oxygen in the third interlayer insulating layer  14   b  and the fourth interlayer insulating layer  15   b , and a second barrier layer  17   h  composed of Mn-containing oxides is formed. 
     In addition, by this heat treatment, Mn is diffused from the CuMn alloy layer  17   g  and is allowed to react with oxygen in the third interlayer insulating layer  14   b  and the fourth interlayer insulating layer  15   b  exposed to the side walls of the openings  21   g ,  21   b , and  21   c . Subsequently, the second barrier layer  17   h  composed of Mn-containing oxides is formed on the side walls of the openings  21   g ,  21   b , and  21   c  each provided with the first barrier layer  16   d  to have a thickness of 1 nm to 5 nm. In this embodiment, since the third interlayer insulating layer  14   b  is formed of SiOC, the fourth interlayer insulating layer  15   b  is formed of SiO 2 , and Mn also reacts with Si, the composition of the Mn-containing oxides forming the second barrier layer  17   h  is represented by Mn x Si y O z  (x:y:z is 1:1:3 to 1:3:5). 
     In this case, since the CuMn alloy layer  17   g  having a small thickness is formed as described above, the ratio of Mn of the CuMn alloy layer  17   g  forming the second barrier layer  17   h  on the side walls of the openings  21   g ,  21   b , and  21   c  is large than that of Mn dissolved in Cu. Hence, an increase in resistance of the Cu wire caused by dissolution of Mn in the conductive layer  18   d  may be suppressed. 
       FIG. 5B  is a view illustrating the case in which, for example, by a CMP method, the first barrier layer  16   d , the second barrier layer  17   h , and the conductive layer  18   d  are partly removed approximately to the middle of the fourth interlayer insulating layer  15   b  by polishing, so that the second wire  19   b  composed of Cu is formed in the opening  21   b , and the third wire  19   c  composed of Cu is formed in the opening  21   c . The operations described above with reference to  FIGS. 2B to 5B  are repeatedly performed, so that the semiconductor device  50   a  including the multilayer interconnection structure  40   a  is formed. 
     According to the semiconductor device  50   a  of the first embodiment, the contact area between the insulating layers containing oxygen and the second barrier layer containing Mn may be increased. Hence, Mn may be sufficiently consumed by the formation of Mn oxides at a portion at which the contact area between the insulating layers and the second barrier layer is increased. As a result, an increase in resistance of the copper wire may be reduced. 
     In the second embodiment,  FIGS. 6A and 6B  are views each illustrating the structure of a semiconductor device  50   b  having a multilayer interconnection structure  40   b . In the second embodiment, constituents similar to those described in the first embodiment will be designated by the same reference numerals, and a description thereof will be omitted. 
       FIGS. 6A and 6B  each illustrate the structure of the semiconductor device  50   b  of the second embodiment.  FIG. 6A  is a plan view of the semiconductor device  50   b .  FIG. 6B  is a cross-sectional view taken along the line X-Y illustrated in  FIG. 6A . 
     As illustrated in  FIG. 6A , in the semiconductor device  50   b  of the second embodiment, reference numeral  15   b  indicates a fourth interlayer insulating layer, reference numeral  19   b  indicates a second wire (Cu wire), reference numeral  19   c  indicates a third wire, and reference numeral  19   e  indicates a fourth wire. 
     The fourth wire  19   e  has a concavo-convex portion  22  in a plane direction of a Cu wire. The concavo-convex portion  22  is formed to increase the surface area of the fourth wire  19   e  and that of the Cu wire. 
     As illustrated in  FIG. 6B , the semiconductor device  50   b  of the second embodiment has a transistor forming layer  60  and the multilayer interconnection structure  40   b . The multilayer interconnection structure  40   b  has first wires  19   a , the second wires  19   b , the third wire  19   c , and the fourth wire  19   e . Constituents illustrated in  FIG. 6B  similar to those described with reference to  FIG. 6A  are designated by the same reference numerals. 
     The fourth wire  19   e  is formed by burying a conductive layer  18   e  in an opening  21   e . The opening  21   e  is formed by opening a third interlayer insulating layer  14   b  and the fourth interlayer insulating layer  15   b . The opening  21   e  is formed so that a conductive material to be filled therein is not electrically connected to the first wire  19   a . The conductive layer  18   e  is preferably formed, for example, of copper (Cu). 
     The concavo-convex portion  22  is formed along the periphery of the opening  21   e . The concavo-convex portion  22  is formed to have an X-Y direction width smaller than the width of the opening  21   e  in the X-Y direction. The concavo-convex portion  22  is formed to increase a contact area between insulating layers containing oxygen and a second barrier layer  17   e  which will be described below. Hence, as in the first embodiment, Mn may be sufficiently consumed by the formation of Mn oxides at a portion at which the contact area of the second barrier layer  17   e  with the third interlayer insulating layer  14   b  and the fourth interlayer insulating layer  15   b  is increased. Accordingly, the resistance of the Cu wire may be maintained at a low level. 
     A first barrier layer  16   e  and the second barrier layer  17   e  are sequentially formed between the opening  21   e  and the conductive layer  18   e . The first barrier layer  16   e  is formed at the opening  21   e  side. The second barrier layer  17   e  is formed at the conductive layer  18   e  side. 
     Since the Cu wire is formed in the opening  21   e , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   e . The first barrier layer  16   e  preferably has a thickness of 3 nm to 10 nm. Incidentally, the first barrier layer  16   e  may only be formed when it is necessary. 
     The second barrier layer  17   e  is formed between the first barrier layer  16   e  and the conductive layer  18   e . Since the third interlayer insulating layer  14   b  is formed of SiOC, the fourth interlayer insulating layer  15   b  is formed of SiO 2 , and Mn also reacts with Si, the composition of Mn-containing oxides forming the second barrier layer  17   e  is represented by Mn x Si y O z  (x:y:z is 1:1:3 to 1:3:5). In addition, the second barrier layer  17   e  preferably has a thickness of 1 nm to 5 nm. 
     According to the structure of the semiconductor device  50   b  of the second embodiment, besides the structure of the semiconductor device  50   a  of the first embodiment, the fourth wire  19   e  having a concavo-convex portion in a plane direction of the Cu wire is formed. Hence, even in the case in which a dummy plug may not be formed under the Cu wire, the contact area between the interlayer insulating layers and the second barrier layer containing Mn may be increased. Accordingly, Mn may be sufficiently consumed by the formation of Mn oxides at a portion at which the contact area of the second barrier layer with the insulating layers is increased. As a result, the resistance of the Cu wire may be maintained at a low level. 
     In the third embodiment,  FIGS. 7A and 7B  are views each illustrating the structure of a semiconductor device  50   c  having a multilayer interconnection structure  40   c . In the third embodiment, constituents similar to those described in the first embodiment will be designated by the same reference numerals, and a description thereof will be omitted. 
       FIGS. 7A and 7B  each illustrate the structure of the semiconductor device  50   c  of the third embodiment.  FIG. 7A  is a plan view of the semiconductor device  50   c .  FIG. 7B  is a cross-sectional view taken along the line X-Y illustrated in  FIG. 7A . 
     As illustrated in  FIG. 7A , in the semiconductor device  50   c  of the third embodiment, reference numeral  15   b  indicates a fourth interlayer insulating layer, reference numeral  19   b  indicates a second wire (Cu wire), reference numeral  19   c  indicates a third wire, and reference numeral  19   f  indicates a fifth wire. 
     Slit portions  23  are formed inside the fifth wire  19   f . The slit portions  23  are formed, for example, of an insulating material such as SiO 2 . 
     However, when the slit portions  23  are formed, since the cross-sectional area of the wire is decreased, an increase in wiring resistance unfavorably occurs. Hence, the rate of decrease in cross-sectional area caused by the formation of the slit portions  23  may be set lower than the rate of increase in resistance caused by Mn intrusion. The slit portions  23  are formed to increase the surface area between the insulating layer containing oxygen and a second barrier layer, which will be described later, in the fifth wire  19   f . For example, the slit portions  23  are preferably formed so as to decrease a 1 μm-wide fifth wire  19   f  by approximately 2.5% and so as to decrease a 3 μm-wide fifth wire  19   f  by approximately 5%. In addition, the surfaces of the slit portions  23  may be formed inside the fifth wire  19   f . That is, the slit portions  23  may have a grooved shape formed inside the fifth wire  19   f.    
     As illustrated in  FIG. 7B , the semiconductor device  50   c  of the third embodiment has a transistor forming layer  60  and the multilayer interconnection structure  40   c . The multilayer interconnection structure  40   c  has first wires  19   a , the second wires  19   b , the third wire  19   c , and the fifth wire  19   f . In this embodiment, constituents illustrated in  FIG. 7B  similar to those described with reference to  FIG. 7A  are designated by the same reference numerals. 
     The fifth wire  19   f  is formed by burying a conductive layer  18   f  in an opening  21   f . The opening  21   f  is formed by opening a third interlayer insulating layer  14   b  and a fourth interlayer insulating layer  15   b . A conductive material to be filled in the opening  21   f  is not electrically connected to the first wire  19   a . The conductive layer  18   f  is preferably formed, for example, of copper (Cu). 
     In the fifth wire  19   f , the slit portions  23  are formed. The slit portions  23  are formed of an insulating material containing oxygen, such as SiO 2 . 
     However, when the slit portions  23  are formed, since the cross-sectional area of the wire is decreased, an increase in wire resistance unfavorably occurs. Hence, the rate of decrease in cross-sectional area caused by the formation of the slit portions  23  may be set lower than the rate of increase in resistance caused by Mn intrusion. The slit portions  23  are formed to increase the surface area between the insulating material containing oxygen and a second barrier layer  17   f , which will be described below, in the fifth wire  19   f . For example, the slit portions  23  are preferably formed so as to a decrease a 1 μm-wide fifth wire  19   f  by approximately 2.5% and so as to decrease a 3 μm-wide fifth wire  19   f  by approximately 5%. 
     A first barrier layer  16   f  and the second barrier layer  17   f  are sequentially formed between the opening  21   f  and the conductive layer  18   f . The first barrier layer  16   f  is formed at the opening  21   f  side. The second barrier layer  17   f  is formed at the conductive layer  18   f  side. 
     Since the Cu wire is formed in the opening  21   f , a material which reduces Cu diffusion and which has superior adhesion to Cu is used for the first barrier layer  16   f . The first barrier layer  16   f  preferably has a thickness of 3 nm to 10 nm. Incidentally, the first barrier layer  16   f  may only be formed when it is necessary. 
     The second barrier layer  17   f  is formed between the first barrier layer  16   f  and the conductive layer  18   f . Since the third interlayer insulating layer  14   b  is formed of SiOC, the fourth interlayer insulating layer  15   b  is formed of SiO 2 , and Mn also reacts with Si, the composition of Mn-containing oxides forming the second barrier layer  17   f  is represented by Mn x Si y O z (x:y:z is in the range of 1:1:3 to 1:3:5). In addition, the second barrier layer  17   f  preferably has a thickness of 1 nm to 5 nm. 
     According to the structure of the semiconductor device  50   c  of the third embodiment, besides the structure of the semiconductor device  50   a  of the first embodiment, the slit portions  23  are formed. Hence, even when a dummy plug may not be formed under the Cu wire, the contact area between the second barrier layer containing Mn and the insulating material containing oxygen may be increased. Accordingly, Mn may be sufficiently consumed by the formation of Mn oxides at a portion at which the contact area of the second barrier layer with the insulating material is increased. As a result, the resistance of the Cu wire may be maintained at a low level. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the embodiment. Although the embodiment(s) of the present invention has (have) been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Technology Classification (CPC): 7