Patent Abstract:
A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole&#39;s upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.

Full Description:
RELATED APPLICATION(S) 
       [0001]    This application claims the benefit under 35 USC § 119(e) of Korean Patent Application No. 10-2005-0129865 filed Dec. 26, 2005, which is incorporated herein by reference in its entirety. 
       FIELD OF INVENTION 
       [0002]    The present invention relates to a semiconductor device and a method for manufacturing the same. 
       BACKGROUND OF THE INVENTION 
       [0003]    In general, there has been a rapid change toward high performance in next generation semiconductor devices. As a result, a via hole size has become reduced and the aspect ratio thereof has become increased. Thus, superior step coverage, via filling capability and high speed operation of a device has become necessary. To this end, a method for forming a metal interconnection on a damascene pattern using copper has been suggested as a useful method. As an example of conventional methods for forming copper interconnection, there is a method including the steps of forming a diffusion barrier layer and a seed layer for forming copper through physical vapor deposition, forming a copper interconnection layer on the seed layer through electroplating to fill a via with the copper interconnection, and performing chemical mechanical polishing.  FIGS. 1 to 3  are sectional views representing a method for forming a metal interconnection of a semiconductor device according to the related art. 
         [0004]    First, referring to  FIG. 1 , after an interlayer dielectric layer  30  is formed on a semiconductor substrate  10  having a conductive layer  20  thereon, a hole  40  is formed by partially etching the interlayer dielectric layer  30 . 
         [0005]    Then, referring to  FIG. 2 , a diffusion barrier layer  50  and a seed layer  60  including copper are sequentially stacked in the hole  40  and on the surface of the interlayer dielectric layer  30 . 
         [0006]    In detail, the seed layer  60  and the diffusion barrier layer  50  are formed through a PVD (Plasma Vapor Deposition) process. However, a reduction of the via size and an increase of the step difference may cause a poor step coverage, so that overhang A or a deposition discontinuous point B may occur. 
         [0007]    Referring to  FIG. 3 , a copper interconnection layer  70  is deposited on the seed layer  60  through electroplating so as to fill the hole  40 . 
         [0008]    However, a void C is formed in the hole  40  due to the overhang A and the deposition discontinuous point B. As described above, according to the related art, the overhang, the deposition discontinuous point and voids cause the increase of the contact resistance so that the reliability of the semiconductor device is reduced. 
         [0009]    Further, according to the related art, such overhang, deposition discontinuous point and voids may become serious problems because the aspect ratio of the hole may increase as the degree of integration of the semiconductor device increases. 
       BRIEF SUMMARY 
       [0010]    Embodiments of the present invention can solve the above problems occurring in the prior art. An embodiment of the present invention can provide a semiconductor device and a method for manufacturing the same, capable of preventing an overhang or a void from being generated due to a step difference in the process of forming a diffusion barrier layer and a seed layer. 
         [0011]    Another embodiment of the present invention is to provide a semiconductor device and a method for manufacturing the same, capable of preventing the performance degradation of the semiconductor device caused by an overhang or a void, thereby preventing the reliability of the semiconductor device from being degraded. 
         [0012]    To achieve the above, embodiments of the present invention provide a semiconductor device comprising: a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate and provided with a hole having a tapered angle on the upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer. 
         [0013]    Another aspect of the present invention provides a method comprising: forming an interlayer dielectric layer on the semiconductor substrate having a conductive layer; forming a first photoresist layer having a predetermined thickness on the interlayer dielectric layer; exposing an entire surface of the first photoresist layer; forming a shielding layer on the exposed first photoresist layer; forming and patterning a second photoresist layer on the shielding layer; etching the shielding layer exposed by the patterned second photoresist layer; developing and removing a predetermined portion of the first photoresist layer which is exposed by the etched shielding layer; and forming a hole by etching the interlayer dielectric layer exposed by the removal of the predetermined portion of the first photoresist layer. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0014]      FIGS. 1 to 3  are sectional views illustrating a method for forming a metal interconnection of a semiconductor device according to the related art; and 
           [0015]      FIGS. 4 to 12  are sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    Hereinafter, a semiconductor device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be explained in detail with reference to accompanying drawings. 
         [0017]    In the following description, the expression “formed on each layer” may include the meaning of both “formed directly on each layer” and “formed indirectly on each layer”. 
         [0018]      FIGS. 4 to 12  illustrate a method for forming a metal interconnection of a semiconductor device in accordance with an exemplary embodiment of the present invention. 
         [0019]    Referring to  FIG. 4 , an interlayer dielectric layer  120  is formed on a semiconductor substrate  100  where a conductive layer  110  is formed. 
         [0020]    Then, referring to  FIG. 5 , a photoresist is coated on the interlayer dielectric layer  120  to a predetermined thickness so as to form a first photoresist layer  130 . The first photoresist layer  130  can have a thickness such that the width of the undercut portion can be controlled. 
         [0021]    In a specific embodiment, the first photoresist layer  130  can have a thickness within a range of about 50 nm to about 200 nm. That is, when the thickness of the first photoresist layer  130  is less than 50 nm, an undercut hardly occurs, and when the thickness of the first photoresist layer  130  exceeds 200 mm, the undercut excessively occurs so that a taper angle of the interlayer dielectric layer  120  is excessively increased. 
         [0022]    For instance, according to an embodiment of the present embodiment, an undercut having a proper size may be obtained by forming the first photoresist layer  130  with a thickness of about 100 nm. 
         [0023]    Subsequently, a blank exposure process can be performed to expose the entire surface of the first photoresist layer  130  to light without using a photo mask. 
         [0024]    Then, referring to  FIG. 6 , a shielding layer  140  can be formed on the first photoresist layer  130 . 
         [0025]    The shielding layer  140  functions to protect the first photoresist layer  130  except for the regions of the first photoresist layer  130  exposed in a subsequent process from making contact with a developer. 
         [0026]    In one embodiment a middle metal layer formed by depositing a metal can be used as the shielding layer  140 . However, the present invention is not limited thereto. That is, in other embodiments, an insulating layer such as an oxide layer or a nitride layer can be used as the shielding layer  140 . 
         [0027]    The middle metal layer  140  can be deposited through PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). 
         [0028]    In a specific embodiment, the middle metal layer  140  can be aluminum deposited on the first photoresist layer  130  through CVD. 
         [0029]    The middle metal layer  140  can support a second photoresist layer  150 , described below, and serves as a mask when removing the first photoresist layer  130 . 
         [0030]    Referring to  FIG. 7 , a second photoresist layer  150  can be formed on the middle metal layer  140  and patterned for forming a trench. 
         [0031]    For example, the second photoresist layer  150  can be exposed to light through a predetermined photo mask so that the second photoresist layer  150  is patterned on the middle metal layer  140 . Accordingly, a predetermined portion of the middle metal layer  140  is exposed. 
         [0032]    Then, referring to  FIG. 8 , the exposed middle metal layer  140  can be etched so that a predetermined portion of the first photoresist layer  130  is exposed. 
         [0033]    In this case, a wet etching process or a dry etching process can be used as a method for etching the middle metal layer  140 . 
         [0034]    In one embodiment, the exposed middle metal layer  140  can be etched through RIE (Reactive Ion Etch). 
         [0035]    A predetermined portion of the first photoresist layer  130  positioned under the middle metal layer  140  is exposed as the predetermined portion of the middle metal layer  140  is removed. 
         [0036]    Then, referring to  FIG. 9 , the exposed first photoresist layer  130  can be developed. 
         [0037]    Since the first photoresist layer  130  is blank-exposed in the previous process, the undercut, which is sunk in at a predetermined angle and removed, may occur as the exposed portion of the first photoresist layer  130  is developed. 
         [0038]    As the first photoresist layer  130  has been partially undercut, overhang can be prevented from being generated in the following process of forming the diffusion barrier layer  170  and the seed layer  180 . 
         [0039]    Referring to  FIG. 10 , as the exposed portion of the first photoresist layer  130  is removed, a predetermined portion of the interlayer dielectric layer  120  can be exposed. The exposed portion of the interlayer dielectric layer  120  can be etched so as to form a hole  160  for the interconnection between layers. Accordingly, a predetermined portion of the conductive layer  110  is exposed. 
         [0040]    The hole  160  can be formed as a trench, a via hole or a contact hole depending on the desired application. 
         [0041]    In an embodiment, a wet etching process or a dry etching process can be used for etching the interlayer dielectric layer  120 . The interlayer dielectric layer  120  can be etched such that the hole  160  is formed therein, and the upper portion thereof is sunk at a predetermined angle. 
         [0042]    In this case, the upper portion of the hole  160  has a width wider than the width of the lower portion of the hole  160 . 
         [0043]    If the interlayer dielectric layer  120  is etched through the dry etching process, the lower portion of the hole  160  can have a width identical to a width of a middle portion of the hole  160 , and the upper portion of the hole can have a width wider than the width of the lower portion of the hole. 
         [0044]    That is, according to the exemplary embodiment of the present invention, since the lower portion of the first photoresist layer  130  formed on the interlayer dielectric layer  120  is undercut to be sunk at a predetermined angle, the etching rate may increase at the upper portion of the interlayer dielectric layer  120 . Accordingly, after the etching process has been performed, the hole  160  is formed in the interlayer dielectric layer  120  and the upper portion of the interlayer dielectric layer  120  is sunk at a predetermined angle. 
         [0045]    The upper portion of the interlayer dielectric layer  120  and the lower portion of the first photoresist layer  130 , being sunk in at predetermined angles, form sink parts  161 . 
         [0046]    Referring to  FIG. 11 , the first photoresist layer  130 , the middle metal layer  140  and the second photoresist layer  150  can be removed leaving a hole  160  in the interlayer dielectric layer  120  having a tapered angle at the upper portion of the hole  160 . 
         [0047]    Referring to  FIG. 12 , a diffusion barrier layer  170  and a seed layer  180  can be sequentially stacked on the interlayer dielectric layer  120 . 
         [0048]    The diffusion barrier layer  170  prevents a metal interconnection layer to be filled in the hole in the following process from diffusing into the interlayer dielectric layer  120 , and the seed layer  180  accelerates the growth of the metal interconnection layer. 
         [0049]    In detail, the diffusion barrier layer  170  can be formed on the interlayer dielectric layer  120  and the exposed portion of the conductive layer  110 , and the seed layer  180  can be formed on the diffusion barrier layer  170 . 
         [0050]    The diffusion barrier layer  170  may be formed of a single TaN layer, a single Ta layer, or a dual TaN/Ta layer. 
         [0051]    Referring to  FIG. 12 , the diffusion barrier layer  170  may include a dual layer of TaN/Ta  171  and  172 . 
         [0052]    Since the upper portion of the interlayer dielectric layer  120  is chamfered at a predetermined angle, the diffusion barrier layer  170  and the seed layer formed on the interlayer dielectric layer  120  are also chamfered at a predetermined angle. 
         [0053]    Accordingly, the overhang does not occur in the process of forming the diffusion barrier layer  170  and the seed layer  180  so a void which may generate in the metal interconnection layer to be filled in the hole  160  can be prevented. After forming the diffusion barrier layer  170  and the seed layer  180 , a process of forming the metal interconnection layer can be performed to interconnect the layers. 
         [0054]    Embodiments of the present invention can be applied to both single damascene process and dual damascene process, and can be applied to the process for forming the contact hole and the via hole. 
         [0055]    The semiconductor device and the method for manufacturing the same according to the exemplary embodiment of the present invention can prevent an overhang from being generated due to a step difference of a hole in the process of forming a diffusion barrier layer and a seed layer. 
         [0056]    Further, according to embodiments of the present invention, the performance degradation of the semiconductor device caused by an overhang or a void can be prevented, so that the reliability of the semiconductor device can be improved. 
         [0057]    The embodiments and the accompanying drawings illustrated and described herein are intended to not limit the present invention, and it will be obvious to those skilled in the art that various changes, variations and modifications can be made to the present invention without departing from the technical spirit of the invention.

Technology Classification (CPC): 7