Patent Abstract:
A fan driving circuit drives a first fan and a second fan which are connected in parallel and connected to an anode of a direct current power. The fan driving circuit includes a pulse width modulation signal generation module, a phase lock and delay module, a first pulse output comparator and a first capacitor. The width modulation signal generation module is connected between an external power and the first fan. The phase lock and delayed module is electrically connected to the pulse width modulation signal generation module. The first capacitor is connected between the DC and the ground. The first fan is supplied as normal by a PWM power supply, the second fan is powered by “shadow” and out-of-phase pulses taken from an inductor in the first fan and stored in the capacitor, to achieve a “two-for-one” power supply aspect, which saves power and reduces operational noise.

Full Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The disclosure relates to fan driving circuits, and particularly to a fan driving circuit which reduces energy consumption. 
         [0003]    2. Description of Related Art 
         [0004]    A typical fan continuously consumes electrical energy to drive the fan to rotate. Thus, the typical fan driving circuit consumes much electrical energy. In addition, the parts of the driving circuit are prone to fatigue and accordingly have a short working lifetime. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a circuit diagram of a fan driving circuit of a first embodiment of the present disclosure. 
           [0006]      FIG. 2  is a circuit diagram of a fan driving circuit of a second embodiment of the present disclosure. 
           [0007]      FIG. 3  is a circuit diagram of a fan driving circuit of a third embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]      FIG. 1  is a circuit diagram of a fan driving circuit  100  of an embodiment of the present disclosure. 
         [0009]    In one embodiment, the fan driving circuit  100  includes a first fan Fan 1  and a second fan Fan 2 . The first fan Fan 1  and the second fan Fan 2  are electrically connected to an anode of a direct current (DC) power source. The fan driving circuit  100  includes a pulse width modulation signal generation module  101 , a phase lock and delay module  103 , a first pulse output comparator U 2  and a first capacitor C 1 . The fan driving circuit  100  uses an inductor of the first fan Fan 1  to generate Lenz current when the pulse width modulation signal generation module  101  is in the non-working stage of the cycle. The Lenz current is stored in the first capacitor C 1  and drives the second fan Fan 2 . 
         [0010]    One terminal of the pulse width modulation signal generation module  101  is electrically connected to an external power source, and another terminal of the pulse width modulation signal generation module  101  is electrically connected to the first fan Fan 1 . The pulse width modulation signal generation module  101  generates pulses to drive the first fan Fan 1  and (indirectly) the second fan Fan 2 . 
         [0011]    In one embodiment, the pulse width modulation signal generation module  101  includes a second capacitor C 2  and a voltage comparator U 1 . The voltage comparator U 1  includes a first input, a second input and an output. The first input of the voltage comparator U 1  is electrically connected to the external power, the second input of the voltage comparator U 1  is a reference voltage terminal, and the output of the voltage comparator U 1  is electrically connected to the first fan Fan 1 . When a voltage of the external power source is greater than a reference voltage of the voltage comparator, the output of the voltage comparator U 1  outputs high level signals to the pulse width modulation signal generation module  101  to cause the pulse width modulation signal generation module  101  to be in the working stage of the cycle and output positive waves. When the voltage of the external power source is less than the reference voltage of the voltage comparator U 1 , the output of the voltage comparator U 1  outputs low level signals to the pulse width modulation signal generation module  101  to put the pulse width modulation signal generation module  103  in the non-working stage of the cycle. The phase lock and delay module  103  is electrically connected to the pulse width modulation signal generation module  101 . The phase lock and delay module  103  sends pulse width modulation signals to the pulse width modulation signal generation module  101  to make the pulse width modulation signal generation module  101  generate corresponding, but phase-retarded, pulses. 
         [0012]    The phase lock and delay module  103  generates pulse width modulation signals with a phase difference of 180 degrees to the pulse width modulation signal generation module  101  to make the pulse width modulation signal generation module  101  generate different-phase waves to drive the second fan Fan 2 . 
         [0013]    The first phase output comparator U 2  includes a first input, a second input and an output. The first input of the first phase output comparator U 2  is electrically connected to the phase lock and delay module  103  to receive the pulse width modulation signal generated by the phase lock and delay module  103 . The second input of the first phase output comparator U 2  inputs the reference voltage. The output of the first phase output comparator U 2  is electrically connected between the second fan Fan 2  and ground. The first phase output comparator U 2  outputs pulses to drive the second fan Fan 2  according to the pulse width modulation signal generation module  101 . 
         [0014]    The first capacitor C 1  is electrically connected between an anode of the direct current DC and ground. The fan driving circuit  100  uses the inductor of the first fan Fan 1  to produce inducted Lenz current when the pulse width modulation signal generation module  101  is in the non-working stage of the cycle. The Lenz current is stored in the capacitor C 1  to previously drive the second fan Fan 2 . As previously mentioned, the phase lock and delay module  103  generates pulse width modulation signals with the phase difference of 180 degrees. In other words, the pulse width modulation signal generation module  101  outputs a positive wave where the phase difference is between 0 to 180 degrees behind when the first fan Fan 1  is in the working stage of the cycle. When the working stage of the first fan Fan 1  has expired, the pulse width modulation signal generation module  101  stops working. The inductor of the first Fan 1  generates Lenz current and the Lenz current is stored in the first capacitor C 1  to drive the second fan Fan 2 . The phase lock and delay module  103  outputs pulse width modulation signals to the pulse width modulation generation module  101  with a phase difference of between 180 to 360 degrees to make the pulse width modulation signal generation module  101  output a positive wave to drive the second fan Fan 2 . The fan driving circuit  100  works in cycles, which saves energy and reduces noise. 
         [0015]    In one embodiment, the fan driving circuit  100  further includes a third capacitor C 3  and a resistor R 1 . The third capacitor C 3  is electrically connected to ground. The resistor R 1  is electrically connected to the second capacitor C 2 . The third capacitor C 3  and the resistor R 1  collectively form a filter circuit which converts the triangular wave generated by the pulse width modulation signal generation module  101  into square wave, to drive the first fan Fan 1  and the second fan Fan 2 . 
         [0016]    In one embodiment, the fan driving circuit  100  is used in desktop computers (DT), servers, emergency power supply systems (EPS) and various switched products (such as LAN switches). 
         [0017]      FIG. 2  is a circuit diagram of a fan driving circuit  100  of a second embodiment. 
         [0018]    In this embodiment, compared with the fan driving circuit  100  in  FIG. 1 , the fan driving circuit  100  further includes a third fan Fan 3  and a second phase output comparator U 3 . The third fan Fan 3  is electrically connected to the first fan Fan 1  and the second fan Fan 2  in parallel and is also electrically connected to the anode of the DC. 
         [0019]    In this embodiment, the second phase output comparator U 3  includes a first input, a second input and an output. The first input of the second phase output U 3  is electrically connected to the phase lock and delay module  103 . The second input of the second phase output comparator U 3  is electrically connected to pulse width modulation signal generation module  101 . The output of the second phase output comparator U 3  is electrically connected to the third fan Fan 3 . The second phase output comparator U 3  outputs pulses to the third fan Fan 3 . 
         [0020]    In this embodiment, the phase lock and delay module  103  is electrically connected to the pulse width modulation signal generation module  101 . The phase lock and delay module  103  generates pulse width modulation signals with a phase difference of only 120 degrees to the pulse width modulation signal generation module  101 . 
         [0021]      FIG. 3  is a circuit diagram of a fan driving circuit  100  of a third embodiment of the present disclosure. 
         [0022]    In the third embodiment, comparing with the fan driving circuit  100  in  FIG. 2 , the fan driving circuit  100  further includes a first switch K 1 , a second switch K 2  and a third switch K 3 . A first electrode of the first switch K 1 , a first terminal of the second switch K 2  and a first terminal of the third switch K 3  are respectively electrically connected to the first fan Fan 1 , the second fan Fan 2  and the third fan Fan 3 . A second terminal of the first switch K 1 , a second terminal of the second switch K 2  and a second terminal of the third switch K 3  are grounded. A control of the first switch K 1 , a control terminal of the second switch K 2  and a control terminal of the third switch K 3  are respectively electrically connected to the output terminal of the voltage comparator U 1 , the first phase output comparator U 2  and the second phase output comparator U 3 . 
         [0023]    The first switch K 1 , the second switch K 2 , and the third switch K 3  are N-type metal oxide field effect transistors. The first terminals of the first switch K 1 , the second switch K 2 , and the third switch K 3  are the drain terminals of the N-type metal oxide field effect transistors. The second terminals of the first switch K 1 , the second switch K 2 , and the third switch K 3  are source terminals of the N-type metal oxide field effect transistors. The control terminals of the first switch K 1 , the second switch K 2  and the third switch K 3  are the gate terminals of the N-type metal oxide field effect transistors. 
         [0024]    When the pulse width modulation signal generation module  101  outputs positive phases to make the control electrode of the first switch K 1  to be high level, the first switch K 1  turns on and starts working. 
         [0025]    When the pulse width modulation signal generation module  101  stops working, the control electrode of the first switch K 1  outputs low level signals, and the first fan Fan 1  is in the “resting” stage. The inductor of the first switch K 1  uses the pulse width modulation signal generation module  101  in the non-working stage of the cycle to generate a Lenz current. The Lenz current is stored in the capacitor C 1  and is used to drive the second fan Fan 2 . 
         [0026]    After the second fan Fan 2  gets to the “resting” stage of the cycle, namely after a phase difference of 120 degrees, the pulse width modulation signal generation module  101  stops working, the control electrode of the second switch K 2  outputs low level signals, and the second fan Fan 2  stops receiving power. The inductor of the second switch K 1  uses the pulse width modulation signal generation module  101  in the non-working stage of the cycle to generate a Lenz current. The Lenz current is stored in the capacitor C 1  and is used to previously drive the third fan Fan 3 . 
         [0027]    In other embodiments, the number of the fan driving circuit  100  can be 4 or 5 or more. 
         [0028]    Thus, the fan driving circuits  100  of the embodiments use the inductor of the first-working fan to generate Lenz currents to drive the subsequent fans when the pulse width modulation signal generation module  101  is in the first non-working stage of the cycle, which saves energy and reduces noise.

Technology Classification (CPC): 5