Patent Abstract:
A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application of application Ser. No. 12/778,315, filed May 12, 2010, U.S. Publication No. 2011-0278546 and published on Nov. 17, 2011. 
    
    
     FEDERAL RESEARCH STATEMENT 
     This invention was made with Government support under Government Contract No.: FA8650-08-C-7806 awarded by Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention. 
    
    
     FIELD OF INVENTION 
     The present invention relates to semiconductor nanowire tunnel field effect transistors. 
     DESCRIPTION OF RELATED ART 
     A nanowire tunnel field effect transistor (FET) includes doped portions of nanowire that contact the channel region and serve as source and drain regions of the device. The source region may include, p-type doped silicon material, while the drain region may include n-type doped silicon material. 
     BRIEF SUMMARY 
     According to one embodiment of the present invention, a nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an n-type doped silicon portion extending from the first distal end, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate. 
     According to another embodiment of the present invention, a nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an n-type doped silicon portion extending from the first distal end, a portion of the n-type doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate. 
     According to yet another embodiment of the present invention, a nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIGS. 1-8  illustrate an exemplary method for forming a tunnel field effect transistor (FET) device. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1-8  illustrate a cross-sectional views of a method for forming a FET device. Referring to  FIG. 1 , a silicon on insulator (SOI) layer  102  is defined on a buried oxide (BOX) layer  104  that is disposed on a silicon substrate  100 . The SOI layer  102  includes a SOI pad region  106 , a SOI pad region  108 , and a silicon nanowire  110 . A gate  112  is formed around a portion of the nanowire  110 , and capped with a capping layer  116  that may include, for example, a polysilicon material. A hardmask layer  118  such as, for example, silicon nitride (Si 3 N 4 ) is formed on the capping layer  116 . The gate  112  may include layers of materials (not shown) such as, for example, a first gate dielectric layer (high K layer), such as silicon dioxide (SiO 2 ) around the nanowire  110 , a second gate dielectric layer (high K layer) such as hafnium oxide (HfO 2 ) formed around the first gate dielectric layer, and a metal layer such as tantalum nitride (TaN) formed around the second gate dielectric layer. 
       FIG. 2  illustrates spacer portions  202  formed along opposing sides of the capping layer  116 . The spacers are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by reactive ion etching (RIE). The spacer portions  202  are formed around portions of the nanowire  110  that extend from the capping layer  116  and surround portions of the nanowires  110 . 
       FIG. 3  illustrates the resultant structure following the implantation and activation of n-type ions in the SOI pad region  106  and the adjacent portion of the nanowire  110  that defines a drain region (D). The ions may be implanted by for example, forming a protective mask layer over the SOI pad region  108  and the adjacent nanowire  110  prior to ion implantation. Alternatively, the ions may be implanted at an angle such that the capping layer  116  and spacer  202  may absorb ions and prevent ions from being implanted in an undesired region. 
       FIG. 4  illustrates the resultant structure following the formation of a conformal hardmask layer  402  over the exposed surfaces of the device. The conformal hardmask layer  402  may include for example, silicon dioxide, silicon nitride, or any other sacrificial material that will inhibit epitaxial growth and may be easily removed. 
       FIG. 5  illustrates the resultant structure following removal of a portion of the nanowire  110  that extended between the SOI pad region  108  and the channel region of the gate  112 . The portion of the nanowire  110  may be removed by, for example, patterning and removing a portion of a portion of the conformal hardmask layer  402  and performing an etching process such as, for example, a wet chemical or vapor etching process that etches exposed silicon, and removes the exposed silicon nanowire  110 . The portion of the conformal hardmask layer  402  is removed using a process that preserves the conformal hardmask layer  402  in the region that will become the drain region (described below); the removal process is controlled to avoid compromising the integrity of the hardmask layer  118  over the gate  112  and the integrity of the spacer  202 . 
       FIG. 6  illustrates the resultant structure following an optional isotropic etching process may be performed to remove a portion of the nanowire  110  that is surrounded by the spacer wall  202  and the gate  112  to recess the nanowire  110  into the gate  112 , and form a cavity  602  defined by the gate  112 , the nanowire  110  and the spacer wall  202 . Alternate embodiments may not include the isotropic etching process that forms the cavity  602 . The lateral etching process that forms cavity  602  may be time based. Width variation in spacer  202  may lead to variations in the position of the edges of the recessed nanowire  110 . The etching rate in the cavity  602  depends on the size of the cavity, with narrower orifice corresponding to slower etch rates. Variations in the nanowire size will therefore lead to variations in the depth of cavity  602 . 
       FIG. 7  illustrates the resultant structure following the removal of an exposed portion of the BOX layer  104  that exposes a portion of the silicon substrate  100 . 
       FIG. 8  illustrates cross-sectional views of the resultant structures following a selective epitaxial growth of silicon to form a source region (S)  802 . The source region  802  is epitaxially grown in the cavity  602  (of  FIG. 7 ) from the exposed nanowire  110  in the gate  112  to form the source region  802 . The source region  802  is epitaxially grown from the SOI pad region  108  and the exposed portion of the silicon substrate  100 . The source region  802  is formed by epitaxially growing, for example, in-situ doped silicon (Si), a silicon germanium (SiGe), or germanium (Ge) that may be p-type doped. As an example, a chemical vapor deposition (CVD) reactor may be used to perform the epitaxial growth. Precursors for silicon epitaxy include SiCl 4 , SiH 4  combined with HCL. The use of chlorine allows selective deposition of silicon only on exposed silicon surfaces. A precursor for SiGe may be GeH 4 , which may obtain deposition selectivity without HCL. Precursors for dopants may include B 2 H 6  for p-type doping. Deposition temperatures may range from 550° C. to 1000° C. for pure silicon deposition, and as low as 300° C. for pure Ge deposition. 
     Once source region (S)  802  is formed, the doping may be activated by, for example, a laser or flash anneal process. The laser or flash annealing may reduce diffusion of ions into the channel region  804  of the gate  112 , and result in a high uniform concentration of doping in the source region  802  with an abrupt junction in the nanowires  110 . 
     The hardmask layer  402  and  118  may be removed by, for example, a RIE process. A silicide may be formed on the source region  802  the drain region D and the gate region. Examples of silicide forming metals include Ni, Pt, Co, and alloys such as NiPt. When Ni is used the NiSi phase is formed due to its low resistivity. For example, formation temperatures include 400-600° C. Once the silicidation process is performed, capping layers and vias for connectivity (not shown) may be formed and a conductive material such as, Al, Au, Cu, or Ag may be deposited to form contacts. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one ore more other features, integers, steps, operations, element components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
     The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Technology Classification (CPC): 7