Patent Abstract:
The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.

Full Description:
BACKGROUND 
   The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. 
   Embedded systems typically comprise flash memory such as serial flash or parallel flash for storing data and code. An embedded system requires a plurality of pins (address pins, data pins, and control pins) to access a parallel flash. Fewer pins are required to access a serial flash. For example, an embedded system only requires four pins (an enabling pin CE, a clock pin SCLK, a data input pin SI, and a data output pin SO) to access the serial flash. Additional commands and addresses, however, must be issued each time the serial flash is accessed. If the embedded systems access the serial flash too frequently, large number of additional commands and addresses will be issued and the performance of the embedded system may be decreased. Additionally, the serial flash is controlled by vendor specific instructions, which vary between manufacturers, resulting in compatibility problems. 
   SUMMARY 
   An object of the invention is to provide a command controller applied in an embedded system. The embedded system comprises a processor, a plurality of access devices and a serial flash. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The command controller comprises a direct reader and a command interpreter. The direct reader processes a first command to generate a first instruction according to a trapping input wherein the first command can be from the processor or any access device and the first instruction is shifted to the serial flash for reading data in the serial flash. The command interpreter interprets a second command to generate a second instruction according to the trapping input wherein the second command is from the processor and the second instruction is shifted to the serial flash for reading data from or writing data to the serial flash. 
   Another object of the invention is to provide a prefetch module applied in an embedded system. The embedded system comprises a processor, a plurality of access devices and a serial flash. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch module comprises a command interpreter and a prefetch buffer. The command interpreter interprets a second command to generate a second instruction wherein the second command is from the processor and the second instruction is shifted to the serial flash for reading data from or writing data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash. 
   A further object of the invention is to provide an embedded system. The embedded system comprises a serial flash, a processor, a plurality of access devices, and a command controller. The processor and the plurality of access devices send various commands. The command controller processes the various commands to generate and send various instructions to the serial flash to read data from or write data to the serial flash. 
   A further object of the invention is to provide an embedded system. The embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the flash. 
   A further object of the invention is to provide a method of controlling a command controller applied in an embedded system. The method comprises: processing a first command from a processor to generate a first instruction according to a trapping input and shifting the first instruction to the serial flash for reading data; and interpreting a second command from the processor or any access device to generate a second instruction according to the trapping input and shifting the second instruction to the serial flash for reading or writing data. 
   Yet another object is to provide a method of controlling a prefetch buffer applied in an embedded system. The method comprises: continually storing data in the prefetch buffer until the prefetch buffer is full, and transmitting data from/to the serial flash. 

   
     DESCRIPTION OF THE DRAWINGS 
     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: 
       FIG. 1  shows a block diagram of an embedded system according to an embodiment of the invention; 
       FIG. 2A  shows a block diagram of the serial flash interface; 
       FIG. 2B  is a flow chart of access command interpreting process; 
       FIG. 3A  shows a block diagram of the command controller; 
       FIG. 3B  shows another block diagram of the command controller; 
       FIG. 4A  shows a schematic diagram of the command register in  FIG. 2 ; 
       FIGS. 4B˜4E  show schematic diagrams of a series of instructions, data, and address sent to the serial flash  110  different operations of the command controller; 
       FIG. 5  is a flow chart of a prefetch buffer reading control method applied to an embedded system; 
       FIG. 6  is a flow chart of a prefetch buffer writing control method applied to an embedded system. 
   

   DESCRIPTION OF THE INVENTION 
   A detailed description of the invention is provided in the following. Please refer to  FIG. 1 .  FIG. 1  shows a block diagram of an embedded system  100  according to one embodiment of the invention. The embedded system  100  comprises a serial flash  110 , a processor  120 , a flash DMA engine  130 , an access device  140 , a serial flash request arbiter  150 , a serial flash interface  160 , a prefetch buffer controller  170  and a prefetch buffer  180 . The processor  120 , flash DMA engine  130 , and access device  140  can access the serial flash  110 . For example, the processor  120  can read/write the serial flash  110  and the flash DMA engine  130  can move data in the serial flash  110  to a DRAM (not shown). If there are more than two elements requesting access to the serial flash  110  at the same time, the serial flash request arbiter  150  chooses one element to send a command through the bus BUS_ 2  to access the serial flash  110 . Additionally, the command can be issued by the processor  120  directly through the bus BUS_ 1  without going through bus BUS_ 2 . The prefetch buffer controller  180  is utilized to collect and translate several single read access requests to the burst read access for reducing total access time. A detailed description of reducing access time through the prefetch buffer controller  180  will be described later and access to the serial flash is provided in the following. 
   Please refer to  FIG. 2A .  FIG. 2A  shows a block diagram of the serial flash interface  160 . The serial flash interface  160  comprises a command controller  210 , a write data register  220 , an address register  230 , a command register  240 , an instruction register  250  and a parallel-serial shift register  260 . The command controller  210  interprets the flash command (access command COM access  from bus BUS_ 1  or direct command COM write /COM read  from bus BUS_ 2 ) to the flash instruction with the help of the plurality of registers and trapping input TRAPin. Finally the parallel-serial shift register  260  converts the instruction from a parallel form to a serial form and shifts the instruction to the serial flash  110  (in  FIG. 1 ). A detailed description of access command interpreting process is provided in the following. 
   Please refer to  FIG. 2B .  FIG. 2B  is a flow chart of access command interpreting process. Steps of the process are given in the following.
         Step  20 : The processor  120  sets the plurality of registers  220 - 250  through the bus BUS_ 1  initially.   Step  22 : The access command COM access  is issued from the processor  120  to the command controller  210  through the bus BUS_ 1 .   Step  24 : A corresponding action (e.g. bulk erase, byte read, byte write . . . ) is determined according to the value of command register  240 , which is set in the previous step  20 .   Step  26 : The command controller  210  performs interpretation to generate a series of instructions, data, and address. For example, in the case of byte write action, vendor-dependent instruction is generated first, data to be written and writing address are generated in turn. Please note that the vendor-dependent instruction is generated according to the instruction register  250 , data written to the serial flash  110  is temporarily stored in the write data register  220 , and the writing address is temporarily stored in the address register  230 .       

   Further discussion of the instruction register  250  is provided in the following. There are various kinds of instruction register implementation. Please note that the implementation of instruction register is only meant to serve as an example, and is not meant to be taken as a limitation. For example, if the space of instruction register is large enough to store the whole instruction sets of a specific serial flash vendor, the instruction register  250  does not need to be set (or initialized) each time of command interpreting process. Otherwise, the instruction register  250  needs to be reset (or re-initialized) each time of command interpreting process. Additionally, different serial flash vendor provides different instruction sets, thus, the instruction register  250  needs to further update its content if the vendor of serial flash changes. Similarly, if the space of the instruction register  250  is large enough to store a plurality of instruction sets corresponding to different serial flash vendor, the instruction register  250  can simply provide the instruction set of the current vendor according to the trapping input TRAP in  rather than reset again. 
   Please refer to  FIG. 3A .  FIG. 3A  shows a block diagram of the command controller  210 . The command controller  210  comprises a direct reader  320 , a command interpreter  310 , and a multiplexer (MUX)  330 . The direct reader  320  processes the read command COM read  (from bus BUS_ 2 ) to generate an instruction INS temp     —     2  according to the trapping input TRAP in . For example, if the trapping input TRAP in  from the vendor is ST, then the direct reader  320  generates the interpreted instruction INS temp     —     2  equal to “03h”. If the trapping input TRAP in  from the vendor is ATMEL, then the direct reader  320  generates the interpreted instruction INS temp     —     2  equal to “E8h”. The command interpreter  310  also interprets the access command COM access  (from bus BUS_ 1 ) to generate another instruction INS temp     —     1  according to the trapping input TRAP in . For example, in a read status access, if the trapping input TRAP in  from the vendor is ST, then the command interpreter  310  generates the interpreted instruction INS temp     —     1  equal to “05h”. If the trapping input TRAP in  from the vendor is ATMEL, then the command interpreter  310  generates the interpreted instruction INS temp     —     1  equal to “D7h”. The MUX  330  selects one instruction from the instructions INS temp     —     1  and INS temp     —     2  to be the interpreted instruction INS com . After the interpreted instruction is generated, the corresponding flash data REG data  and the flash address REG add  will be sent in turn. 
   In the case of access command COM access  (through bus BUS_ 1 ), if the corresponding action handled by the command interpreter  310  is to perform reading (determined by the register value REG com ), the command interpreter  310  sends the interpreted instruction INS temp     —     1  (according to the trapping input TRAP in  and the register value REG ins ), and the reading address from register value REG add . Similarly, if the corresponding action is to perform writing (determined by the register value REG com ), the command interpreter  310  sends the interpreted instruction INS temp     —     1  (according to the trapping input TRAP in  and the register value REG ins ), the writing data from register value REG data , and the writing address from register value REG add . 
   In the case of read command COM read  (through bus BUS_ 2 ), the corresponding action handled by the direct reader  320  is to perform reading. The direct reader  320  sends the interpreted instruction INS temp     —     2  (according to the trapping input TRAP in  and the register value REG ins ), and the reading address from register value REG add . 
   Please refer to  FIG. 3B .  FIG. 3B  shows another block diagram of the command controller  210 . Compared with the previous one in  FIG. 3A , the key difference is that the direct reader  320  is replaced by the reader/writer  420 . The reader/writer  420  not only can handle the read command COM read  but also the write command COM write . 
   Please refer to  FIGS. 4A˜4E .  FIG. 4A  shows a schematic diagram of the command register  240  in  FIG. 2 .  FIGS. 4B˜4E  show schematic diagrams of a series of instructions, data, and addresses sent to the serial flash  110  in different operations (e.g. bulk erase, byte read, byte write . . . ) of the command controller  210 . The command register  240  comprises a byte read segment  411 , a byte write segment  412 , a bulk erase segment  413 , a WRSR (write status register) segment  414 , and a RDSR (read status register) segment  415 . For example, the size of each segment in the register  240  is equal to one bit. In  FIG. 4B , a bulk erase instruction is generated after the bulk erase segment  413  is set by the processor  120 . The command interpreter  320  processes the bulk erase access command COM access  to output the bulk erase instruction INS com  according to the trapping input TRAP in . No other flash data REG data  or flash address REG add  is followed with the bulk erase instruction INS com  and sent to the serial flash  110 . In  FIG. 4C , a read status instruction is generated after the RDSR segment  415  is set by the processor  120 . The command interpreter  310  processes the RDSR command COM access  to output RDSR instruction INS com  according to trapping input TRAP in . No other flash data REG data  or REG add  is followed with the RDSR instruction INS com  and sent to the serial flash  110 . After the RDSR command COM access  is triggered and completed, the return status is available from the serial flash  110 . In  FIG. 4D , a write status instruction is generated after the WRSR segment  414  is set by the processor  120 . The command interpreter  320  processes the WRSR command COM access  to output WRSR instruction INS com  according to the trapping input TRAP in . In  FIG. 4E , a byte program instruction is generated after the byte write segment  412  is set by the processor  120 . The command interpreter  320  processes the byte write command COM access  to output byte write instruction INS com  according to the trapping input TRAP in . After the access command COM access  is triggered, a series comprising instruction, address, data and handshaking is generated and sent to the serial flash  110 . Then the byte data can be written to the assigned address of the serial flash  110 . 
   From the description set forth above, it is clear that the command controller translates various commands to corresponding instructions, even though these instructions are based on different instruction sets provided by different serial flash vendors. Thus, compatibility issues can be solved. A detailed description of the prefetch buffer  170  (in  FIG. 1 ) is provided below. 
   Please refer to  FIG. 5 .  FIG. 5  is a flow chart of a prefetch buffer reading control method applied to an embedded system. Steps of the method are given in the following.
         Step  502 : The prefetch buffer is idle.   Step  504 : A processor or any other access device issues a request to a serial flash request arbiter to read wanted data.   Step  506 : The prefetch buffer controller determines if data in the prefetch buffer is the wanted data. If yes, proceed to step  508 ; Otherwise proceed to step  510 .   Step  508 : The prefetch buffer controller returns data in the prefetch buffer to the processor or any other access and continues fetching until the prefetch buffer is full.   Step  510 : The prefetch buffer controller determines if data is being fetched from a serial flash and if it is ready to be read by the processor or any other access device. If yes, proceed to step  512 ; Otherwise proceed to step  514 .   Step  512 : Wait and determine whether data is ready. If yes, proceed to step  508 ; Otherwise proceed to step  514 .   Step  514 : Abort previous command if present and issue a new request to a serial flash interface.       

   Please refer to  FIG. 6 .  FIG. 6  is a flow chart of a prefetch buffer writing control method applied to an embedded system. Steps of the method are given in the following.
         Step  602 : A processor or any other access device issues a request to a serial flash request arbiter to write data to a serial flash.   Step  604 : The processor or any other access device writes data to the prefetch buffer until full.   Step  606 : The processor or any other access device sets a plurality of related parameters (e.g. a written address or a serial flash vendor).   Step  608 : The processor or any other access device triggers a command controller to translate and send commands to the serial flash.   Step  610 : The command controller polls a serial flash status.   Step  612 : Determine if the serial flash is ready. If yes, proceed to step  614 ; Otherwise, proceed to step  612 .   Step  614 : The command controller sends a write enable instruction to the serial flash.   Step  616 : The command controller sends sequence of an interpreted instruction (OP code), a writing address, and data until the prefetch buffer is full.       

   Compared with the related art, the prefetch buffer of the present invention can translate several single access requests into a burst access. Hence access frequency decreases and performance is increased. Additionally, the command controller can translate various commands to corresponding instructions even though these instructions are provided by different instruction sets from different serial flash vendors. 
   While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 6