Patent Abstract:
An electronic device, including: a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.

Full Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to the field of integrated circuits; more specifically, it relates to a footprint for a flip-chip contact pad array module and corresponding integrated circuit chip.  
         BACKGROUND OF THE INVENTION  
         [0002]    Typical high input/output (I/O) count flip-chip modules use multiple wiring layers for signal, power and ground I/O escape from under the chip to the pins of the module. Fabrication of multiple wiring layer modules is costly and time consuming. Any method to reduce the number of wiring layers without reducing I/O count would be welcome by the industry.  
         SUMMARY OF THE INVENTION  
         [0003]    A first aspect of the present invention is an electronic device, comprising: a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.  
           [0004]    A second aspect of the present invention is a method of fabricating an electronic device, comprising: forming a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.  
           [0005]    A third aspect of the present invention is an electronic device comprising; an array of substrate contact pads on a surface of a substrate, the array of contact pads arranged in rows and columns of contact pads; the columns of substrate contact pads spaced apart a first predetermined distance in a first direction; the rows of substrate contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction; and the array of contact pads aligned under an integrated circuit chip having a corresponding array of chip contact pads, corresponding substrate contact pads and chip contact pads electrically connected by controlled collapse chip connections. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0006]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0007]    [0007]FIG. 1 is a plan view of an exemplary flip-chip module;  
         [0008]    [0008]FIG. 2 is a cross-sectional view through line  2 - 2  of the flip chip module of FIG. 1;  
         [0009]    [0009]FIG. 3 is a plan view of an exemplary integrated circuit chip illustrating symmetry of a chip contact pad footprint according to the present invention;  
         [0010]    [0010]FIG. 4 is a plan view of one quadrant of an integrated circuit chip according to a first embodiment of the present invention;  
         [0011]    [0011]FIG. 5 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 4;  
         [0012]    [0012]FIG. 6 is a plan view of one quadrant of an integrated circuit chip according to a second embodiment of the present invention;  
         [0013]    [0013]FIG. 7 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 6;  
         [0014]    [0014]FIG. 8 is a plan view of one quadrant of an integrated circuit chip according to a third embodiment of the present invention;  
         [0015]    [0015]FIG. 9 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 8;  
         [0016]    [0016]FIG. 10 is a plan view of one quadrant of an integrated circuit chip according to a fourth embodiment of the present invention; and  
         [0017]    [0017]FIG. 11 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 10. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]    [0018]FIG. 1 is a top view of an exemplary flip-chip module. In FIG. 1, an integrated circuit chip  100  is flip-chip mounted to a module  105  having a multiplicity of pins  115 . Each pin is electrically connected to a module contact pad  120  (see FIG. 2) by a conductive wire  125  within module  105 . Conductive wires may also be formed on top surface  110  of module  105 . Pins  115  may carry digital or analog signals, power or ground.  
         [0019]    [0019]FIG. 2 is a cross-sectional view through line  2 - 2  of the flip chip module of FIG. 1. FIG. 2 is at a larger scale than FIG. 1 in order to better illustrate the salient features of the interconnection between integrated circuit chip  100  and module  105 . In FIG. 2, module contact pads  120  are mechanically and electrically connected to chip contact pads  130  on a top surface  135  of integrated circuit chip  100  by solder bumps, solder balls or controlled collapse chip connections (C4). The name flip-chip module as applied to the combination of integrated circuit chip  100  and module  105  is readily apparent as integrated circuit chip  100  has been “flipped” upside down so the top surface  135  of the integrated circuit chip is facing top surface  110  of module  1   05  in order to connect the integrated circuit chip  100  to the module.  
         [0020]    While only one wiring layer is illustrated in FIGS. 1 and 2, the invention is applicable to modules having multiple wiring layers. For example, with two wiring layers, escaping wires in a second wiring layer would be positioned under the escaping wires of the first layer between columns of module contact pads. Alternatively, the first wiring layer may be on the surface of the module and the second wiring layer within the module. However, the invention reduces the number of wiring layers that would be required in a module from the number that would otherwise be required without the present invention as described infra. It should also be noted that while a pin grid array module has been illustrated in FIGS. 1 and 2, the present invention is applicable to other types of modules such as ball grid arrays, solder column grid arrays and land grid arrays.  
         [0021]    Further, it should be noted that modules constitute only one type of substrate to which the present invention is applicable. Other types of substrates include but are not limited to, single wiring layer or multi-layer wiring layer integrated circuit chip modules, single wiring layer or multi-layer wiring layer printed circuit boards, single wiring layer or multi-layer wiring layer flexible circuit boards, single wiring layer or multi-layer wiring layer interposers, single wiring layer or multi-layer wiring layer ceramic substrates, single wiring layer or multi-layer wiring layer organic substrates and integrated circuit chips.  
         [0022]    Contact pads and wires interconnecting contact pads may be formed by any number of methods well known in the art.  
         [0023]    [0023]FIG. 3 is a plan view of an exemplary integrated circuit chip illustrating symmetry of a chip contact pad footprint according to the present invention. In FIG. 3, integrated chip  145  is divided into four equal size quadrants labeled I, II, III and IV which are defined by a vertical axis  150  and a horizontal axis  155 , the horizontal axis being perpendicular to the vertical axis and the two axes crossing at a center  160  of integrated circuit chip  145 . Each quadrant I, II, III and IV is divided into two equal triangular sections defined by diagonal axes  165  and  170 . Quadrant I is divided into a first section Ia and a second section Ib by diagonal axis  165  extending from center  160  to a first corner  175  of integrated circuit chip  145 . Quadrant II is divided in to a first section IIa and a second section IIb by diagonal axis  170  extending from center  160  to a second corner  180  of integrated circuit chip  145 . Quadrant III is divided in to a first section IIIa and a second section IIIb by diagonal axis  165  extending from center  160  to a third corner  185  of integrated circuit chip  145 . Quadrant IV is divided in to a first section IVa and a second section IVb by diagonal axis  170  extending from center  160  to a fourth corner  190  of integrated circuit chip  145 .  
         [0024]    Exemplary contact pad footprint  195 A in section Ia of quadrant I and exemplary contact pad footprint  195 B in section Ib of quadrant I are symmetrical about diagonal axes  165 . Exemplary contact pad footprint  195 C in section IIa of quadrant II and exemplary contact pad footprint  195 D in section IIb of quadrant II are symmetrical about diagonal axes  170 . Exemplary contact pad footprint  195 E in section IIIa of quadrant III and exemplary contact pad footprint  195 F in section IIIb of quadrant III are symmetrical about diagonal axes  165 . Exemplary contact pad footprint  195 G in section IVa of quadrant IV and exemplary contact pad footprint  195 H in section IVb of quadrant IV are symmetrical about diagonal axes  170 . Additionally quadrants I and II are symmetrical about vertical axis  150 , quadrants III and IV are symmetrical about vertical axis  150 , quadrants I and IV are symmetrical about horizontal axis  155  and quadrants II and III are symmetrical about horizontal axis  155 . Thus, in the present example, the contact pad footprint in only one quadrant (only one section of one quadrant if the quadrant is symmetrical about a diagonal axis) need be illustrated and described to fully disclose any particular embodiment of the entire contact pad footprint of an integrated chip or module according to the present invention and this approach will be taken in describing the present invention from hereon. However, the present invention is applicable to non-symmetrical footprints as well. Further, it should be readily apparent that the contact pad footprint on an integrated circuit chip is a mirror image of the corresponding contact pad footprint of the module, so when a chip contact pad footprint is described, the description is applicable to the corresponding module contact pad footprint and vice versa. The module contact pads may carry digital or analog signals, power or ground.  
         [0025]    [0025]FIG. 4 is a plan view of one quadrant of an integrated circuit chip according to a first embodiment of the present invention. In FIG. 4, an integrated chip quadrant  200  is defined by a first side  205  and a second side  210 , perpendicular to and meeting the first side at a corner  215  of the integrated circuit chip quadrant. Integrated chip quadrant  200  corresponds to quadrant I of integrated circuit chip  145  in FIG. 3. A diagonal axis  220  extends from a center  225  of the whole integrated circuit chip of which integrated circuit chip quadrant  200  is one quadrant thereof, to corner  215  of the integrated circuit chip. Diagonal axis  220  divides the integrated circuit chip quadrant  200  into two equal sections  230 A and  230 B. First section  230 A is bounded in part by second side  210  and second section  230 B is bounded in part by first side  205 . A horizontal axis  235  runs in the direction parallel to second side  210 . Columns are defined as running perpendicular to an edge of the chip and rows are defined as running parallel to the of the chip.  
         [0026]    In first section  230 A, a first array  245 A of chip contact pads  250  is arranged in a multiplicity of columns  255  and rows  260 . Columns  255  are spaced apart on a pitch P 1 . Pitch is defined as a distance between centers of adjacent chip contact pads or between centers of adjacent module contact pads unless otherwise noted. Rows  260  are spaced apart on a pitch P 2 . P 2  is less than P 1 . A second array  245 B of chip contact pads  250  in second section  230 B is a mirror image of first array of chip contact pads  245 A about diagonal axis  220 . First and second arrays  245 A and  245 B constitute one quarter of a full chip contact pad footprint. The full chip contact pad footprint is obtained by applying the symmetry rules described supra and illustrated in FIG. 3 to integrated circuit chip quadrant  200 . Note in the present embodiment of the present invention, chip contact pads  250  are in a peripheral region (that area nearest sides  205  and  210 ) of integrated circuit chip quadrant  200  and an interior region (that area nearest center  225 ) contains no chip contact pads. Replicating integrated circuit chip quadrant  200  three times as described supra in reference to FIG. 3 will produce a full chip contact pad footprint. It should be pointed out that FIG. 4 also describes the corresponding module contact pad footprint. Because P 1  is not equal to P 2 , the chip contact pad footprint (or the module contact pad footprint) of the present invention defines a dual pitch contact pad footprint.  
         [0027]    [0027]FIG. 5 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 4. In FIG. 5, a line  265  defines where a side of an integrated circuit chip aligns to module substrate  270  (for example side  210  in FIG. 4). Columns  275  of module contact pads  280  correspond, for example, to columns  255  in FIG. 4 and rows  285  of module contact pads  280  correspond, for example, to rows  260  of FIG. 4. Continuing the present example, columns  275  have the same pitch P 1  as columns  255  in FIG. 4 and rows  285  have the same pitch P 2  as rows  260  in FIG. 4. Connected to module contact pads  280  are module conductive wires  290 . Conductive wires  290  have a minimum fabrication width and a minimum fabrication space. Pitch P 1  is adjusted to a rule that requires P 1  be at least large enough to accommodate the same number less one of conductive wires  290  of at least minimum width and spacing (greater than minimum widths and/or space may be used) as there are module contact pads  280  in each column  275 . This rule maximizes the number of I/Os that can escape from under any given integrated chip per module wiring level. Pitch P 2  conforms to a rule that states P 2  can be no less than a minimum fabrication distance between the centers of two adjacent module contact pads. Particular values for pitch P 1  increase if wires  290  are wider than minimum widths and/or the spaces between wires are greater than minimum spacing. Thus, pitches P 1  and P 2  as well as all subsequent pitches described infra, are based on module conductive wire width, module conductive wire space, module contact pad dimension and module contact pad spacing ground rules and not on integrated circuit chip ground rules. Note there is no requirement that the dimensions (i.e. diameter) of chip contact pads be the same as the dimensions (i.e. diameter) of module contact pads.  
         [0028]    [0028]FIG. 6 is a plan view of one quadrant of an integrated circuit chip according to a second embodiment of the present invention. In FIG. 6, an integrated circuit chip quadrant  200 A is similar to integrated circuit chip quadrant  200  of FIG. 4 except for the addition of an array  295  of chip contact pads  250 A in an interior region  300  of integrated circuit chip quadrant  200 A. Rows of array  295  are spaced apart on a pitch P 4  and columns of array  295  are spaced apart on a pitch P 3 . Pitch P 3  is larger than pitch P 1  of FIG. 4 to allow space for conductive wires from contact pads of array  295  to run between columns as illustrated in FIG. 7 and described infra. P 4  may or may not be equal to P 3 . In one example, P 4  is greater than P 2 .  
         [0029]    [0029]FIG. 7 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 6. In FIG. 7, line  265  defines where a side of an integrated circuit chip aligns to a module substrate  270 A (for example side  210  in FIG. 6). Columns  275  of module contact pads  280  correspond, for example, to columns  255  in FIG. 6, and rows  285  of module contact pads  280  correspond, for example, to rows  260  of FIG. 6. Continuing the example, columns  275  have the same pitch P 3  as columns  255  in FIG. 6, and rows  285  have the same pitch P 2  as rows  260  in FIG. 6. Connected to module contact pads  280  and  280 A are module conductive wires  305 . Pitch P 3  is adjusted to a rule that requires P 3  be at least large enough to accommodate the same number less one of conductive wires  305  of at least minimum width and spacing (greater than minimum widths and/or space may be used) as there are module contact pads  280  in each column  275  plus an additional number of conductive wires from module contact pads  280 A of array  295 . The exact number of additional conductive wires being a function of the density of module contact pads in both interior and peripheral regions of the module contact pad footprint.  
         [0030]    [0030]FIG. 8 is a plan view of one quadrant of an integrated circuit chip according to a third embodiment of the present invention. In FIG. 8, an integrated circuit chip quadrant  200 B is similar to integrated circuit chip quadrant  200  of FIG. 4 except the pitch of chip contact pad columns  255 ,  255 A,  255 B,  255 C and  255 D is variable, in that P 5  is less than P 1 , P 6  is less than P 5 , and P 7  is less than P 6 . The pitch of columns  255  near corner  215  may be reduced because there are less conductive wires on/in an attached module to escape from under integrated circuit chip quadrant  200 B near corner  215 . Reduction of the value of the column-to-column spacing near the corners of the integrated chip and corresponding corners on the module allows for more chip contact pads and more corresponding module contact pads.  
         [0031]    [0031]FIG. 9 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 8. In FIG. 9, lines  265 A and  265 B indicate where the sides of an integrated chip (for example sides  210  and  205  of FIG. 8) align to module substrate  270 B. The number of conductive wires  290 ,  290 A,  290 B,  290 C and  290 D escaping between columns of module contact pads  275 ,  275 A,  275 B,  275 C and  275 D becomes progressively less the closer the columns are to “corner”  310 .  
         [0032]    [0032]FIG. 10 is a plan view of one quadrant of an integrated circuit chip according to a fourth embodiment of the present invention. In FIG. 10, an integrated circuit chip quadrant  200 C is similar to integrated circuit chip quadrant  200  of FIG. 4 except that chip contact pads  250  are arranged in column pairs  315  instead of single columns. The chip contact pads  250  in each column pair are spaced apart on a pitch P 8  and column pairs  315  are spaced apart on a pitch P 9 . Pitch P 9  is measured from the centers of column pairs (not the centers of chip contact pads as for all other aforementioned pitches). Pitch P 8  may or may not be equal to pitch P 2 .  
         [0033]    [0033]FIG. 11 is a plan view of a portion of a flip-chip module substrate having a module contact pad footprint corresponding to the chip contact pad footprint of FIG. 10. In FIG. 11, column pairs  320  of module contact pads  280  correspond, for example, to column pairs  315  in FIG. 10. Continuing the example, column pairs  320  have the same pitch P 9  as column pairs  315  in FIG. 10. Conductive wires  325  have a minimum fabrication width and a minimum fabrication space. Pitch P 9  is adjusted to a rule that requires P 9  be at least large enough to accommodate the same number less one of conductive wires  325  at least minimum width and spacing (greater than minimum widths and/or space may be used) as there are module contact pads  280  in each column pair  320 . Pitch P 8  is adjusted to be at least as large as the minimum fabrication distance between module contact pads  280 .  
         [0034]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example, some module contact pads and corresponding chip contact pads may be used to electrically connect to power or ground planes within the module, in which case the spacing between columns of module and chip contact pads may be reduced since there are fewer signal wires to escape from each column. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Technology Classification (CPC): 7