Patent Abstract:
A self-biasing reference current generator that is compact and capable of implementation in a bipolar semiconductor process or a CMOS process and that generates a reference current output as well as the bias currents required by the reference current generator itself

Full Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     This invention relates generally to monolithic reference current generators and, more specifically, to a very compact self-biasing current generator that can be implemented in a bipolar semiconductor process or in a complementary metal oxide semiconductor (CMOS) process. 
     In the field of analog integrated circuit (IC) design, it is very common to provide a reference current that is proportional to a reference voltage, the reference current being provided though a current mirror. 
     FIG. 1 shows a typical prior art circuit for providing a reference current lout at the output of a current mirror. An operational amplifier forces the junction between resistor R 1  and the source terminal of device M 1  to a reference voltage Vref, thereby generating a current I that is equal to Vref/R 1  through components M 1 , M 2 , and R 1 . While this circuit appears simple, it requires the operational amplifier along with its bias circuit. A reference current generator such as this is often used to provide stable current sources to critical analog circuits inside a chip. If the current generator requires another bias circuit elsewhere in the chip for its own biasing, it increases the size, power requirements, and complexity of the entire current reference circuit. The biasing circuit for the operational amplifier of FIG. 1 will most likely be very simple and inaccurate, causing undesirable errors in the offset, offset drift, and other parameters of the operational amplifier. 
     It would therefore be advantageous to provide a self-biasing reference current generator that is compact and capable of implementation in a bipolar semiconductor process or a CMOS process and that generates a reference current output as well as the bias currents required by the rest of the circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating a typical prior art reference current generator. 
     FIG. 2 is a circuit diagram of a reference current generator in accordance with a first embodiment of the present invention. 
     FIG. 3 is a circuit diagram of a reference current generator in accordance with a second embodiment of the present invention. 
     FIG. 4A is a circuit diagram illustrative of the principle by which the reference current generators of FIGS. 2 and 3 operate. 
     FIG. 4B is an equivalent circuit diagram of the circuit of FIG.  4 A. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring generally to FIGS. 2 and 3, there are shown detailed circuit diagrams of alternative embodiments of a reference current generator in accordance with the present invention. Both of these circuits operate by the principles illustrated in the circuit diagrams of FIGS. 4A and 4B, which are described in detail hereinbelow. Referring now to FIG.  4 A and its equivalent circuit of FIG. B, it is assumed that device pairs MN 10  and MN 20  and MP 10  and MP 20  are matched pairs with the same W/L ratio. It is also assumed t at the input voltage reference has a negligible source impedance. The circuits are configured such that the current through devices MN 10  and MP 10  is equal to the current through devices MN 20  and MP 20 . The operational amplifier  100  of FIGS. 4A and 4B drives the common gate of MN 10  and MN 20  such that the voltage drops across diode connected PMOSFETs MP 10  and MP 20 , are equal, and thereby forces this condition. The combination of voltage Vref, resistor R 1 , and resistor R 2  is replaced with a voltage source having a value equal to Vref{R 2 /(R 1 R 2 )}and having an output impedance expressed by R 1 /R 2 (=R 1 R 2 /). Devices MN 10  and MN 20  operate under the same bias condition, making their gate to source voltages (Vgs) identical. Since MN 10  and MN 20  share the common gate connection, voltage at their source nodes are the same. Hence,                R3   ·   I     =         V                 r                   ef   ·   R2         R1   +   R2       +         R1   ·   R2       R1   +   R2       ·   I               (   1   )                                
     Solving equation (1) for I yields              I   =           R2     R1   +   R2         R3   -       R1   ·   R2       R1   +   R2           ·   V                   r                 ef             (   2   )                 =     Vref       R3   ·     (     1   +     R1   R2       )       -   R1                            (   3   )                                
     As shown by equation (3), this circuit creates a reference current I which is proportional to the reference voltage Vref. The transimpedance is give by the following expression:          R3   ·     (     1   +     R1   R2       )       -   R1                          
     It is clear from equation (2)that the following condition must be met:              R3   &gt;       R1   ·   R2       R1   +   R2               (   4   )                                
     This condition dictates the polarity of the operational amplifier connection. 
     Referring now to the first embodiment of the present invention illustrated in FIG. 2, the differential amplifier formed by the common gate input stage MN 3 , MN 6 , followed by the common source stage MN 1 , MN 2 , and the loads MP 7  and MP 2 , forces the gate voltage of current source devices MP 1  and MP 3  so that the same amount of current flows through devices MN 3  and MN 6 . This current is mirrored by another current source device MP 4  to provide the output current, lout. Device MP 5 , MP 6 , and MP 9  serve as cascode devices for the current source devices MP 4 , MP 1 , and MP 3 , respectively, enhancing the output impedance of the current sources. 
     Devices MN 5  and R 4  provide a proper bias current for the differential pair MN 1  and MN 2 , by establishing a proper voltage at the common source node of the differential pair. MN 5  and R 4  also provide a proper bias voltage for the common gate connection for MN 3  and MN 6 . Current through MN 4  is used to establish the common gate bias voltage for the cascode devices MP 5 , MP 6 , and MP 9 , via MP 8 . 
     Self-biasing circuits in general require a start-up circuit to keep the circuit from going into a zero current state. This start-up function is achieved by devices MPS 1 , MPS 2 , MNS, MN 7 , and MN 8  of FIG.  2 . If devices MN 3 , MN 4 , MN 5 , and MN 6  conduct zero current, MNS also is in zero current state because all of these NMOSFETs share a common gate node. Under this condition, the voltage drop across diode connected PMOSFETs, MPS 1  and MPS 2 , is close to zero, turning on both MN 7  and MN 8  by driving the common gate node of MN 7  and MN 8  high toward the power supply voltage. Drain currents through MN 7  and MN 8  will turn on MP 8  and MP 2 , which in turn will turn on all remaining PMOSFETs in FIG.  2 . Currents through MP 1 , MP 6 , MP 3 , and MP 9  drive gates of all NMOSFETs, completing the start-up function. The device sizes of MPS 1  and MPS 2  are chosen such that the voltage drop across them is large enough to turn off MN 7  and MN 8  once the reference current generator reaches it equilibrium. 
     The second embodiment of the present invention illustrated in FIG. 3 is suited for power supply voltages as low as 1.8 volts or less. Devices MN 1  an MN 3  may be regarded as a common gate differential amplifier with an active load formed by MP 1  and MP 2 . Device MP 8  serves as a cascode device to increase the impedance of the active load. Device MP 6  guarantees that MP 1  and MP 2  operate under the same bias condition. This stage is followed by a common source amplifier form by devices MP 3  and MP 9  with its load formed by MN 4  and resistor R 5 . This common source amplifier sets up the common gate node for devices MN 1 , MN 2 , and MN 3  such hat the currents through devices MN 1  and MN 3  are equal in value. Devices MN 2  and MP 7  along with resistor R 4  establish a proper bias voltage for the common gate connection for MP 6 , MP 8 , MP 9 , MPS 2 , and MP 5 . Devices MPS  1 , MPS 2 , MPS 3 , and MN form a start-up circuit. A current source formed by MP 4  and MP 5  provides the output current Iout. 
     The self-biasing reference current generator circuits of FIGS. 2 and 3 may be conventionally implemented in either a bipolar semiconductor process or a CMOS process.

Technology Classification (CPC): 7