Patent Abstract:
An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to integrated circuits and more particularly the input stages of CMOS logic integrated circuits supplying a logic signal according to an analog input signal. 
         [0003]    2. Description of the Related Art 
         [0004]    Generally speaking, the input stages of integrated circuits have inputs having a switch level centered around half of the supply voltage. This condition is easily obtained for example using the input stage represented in  FIG. 1 . In  FIG. 1 , the input stage INST 1  comprises a balanced inverter comprising a PMOS transistor MP 1  and an NMOS transistor MN 1 . The gate of the transistors MP 1  and MN 1  is connected to the input Vin of the circuit. The drains of the transistors MN 1  and MP 1  are connected to the output Vout of the circuit. The source of the transistor MP 1  receives the supply voltage Vdd. The source of the transistor MN 1  is connected to the ground. 
         [0005]    The transistors MN 1  and MP 1  have similar threshold voltages in absolute value. When the transistors MN 1  and MP 1  have the same geometric dimensions, the transistor MN 1  has a conductance two to three times greater than the conductance of the transistor MP 1 . This property is due to the mobility of the electrons that is two to three times greater that the mobility of the holes. If the width-to-length ratio W/L of the transistor MP 1  is two or three times greater than the ratio of the transistor MN 1 , the two transistors then have the same conductance if they further receive the same substrate-gate voltage in absolute value. Due to its symmetry, the input stage INST 1  has a switch threshold voltage equal to half of the supply voltage (Vdd/2). Depending on whether the input voltage Vin is greater or lower than the switch threshold voltage, the voltage of the output signal Vout is equal to 0 or Vdd. 
         [0006]    Certain applications require a switch threshold that is not equal to Vdd/2, but to another fraction of the supply voltage Vdd, or to a fixed voltage not linked to the voltage Vdd. In addition, the threshold voltages of the n- and p-channel MOS transistors can be different in absolute value. In certain applications, the input stages must be able to operate at low voltage, close to the threshold voltages of the transistors of the integrated circuit. 
         [0007]    In such situations, a voltage comparator comparing the voltage applied at input with a reference voltage is generally used. Typically, such a comparator is produced using a differential amplifier. An example of an input stage comprising a differential amplifier is represented in  FIG. 2 . The input stage INST 2  represented in  FIG. 2  comprises a current mirror differential amplifier DAMP comprising an input receiving the input voltage Vin and an output O 1  connected to the output Vout of the input stage INST 2  through three cascade-arranged inverters I 1 ,I 2 ,I 3 . 
         [0008]    Classically, the amplifier DAMP comprises an input branch receiving the input voltage Vin and a reference branch receiving a reference voltage Vref 1 . The input branch comprises a p-channel MOS transistor MP 2  the source of which receives the supply voltage Vdd and the drain of which is connected to the drain of an n-channel MOS transistor MN 2 . The gate of the transistor MN 2  receives the input voltage Vin. The reference branch comprises a p-channel MOS transistor MP 3  the source of which receives the supply voltage Vdd and the drain of which is connected to the drain of an n-channel MOS transistor MN 3 . The gate of the transistor MP 2  is connected to the gate and to the drain of the transistor MP 3 . 
         [0009]    The sources of the transistors MN 2  and MN 3  are connected to the drain of an n-channel MOS transistor MN 4  the source of which is connected to the ground. A reference voltage VrefN is applied to the gate of the transistor MN 4 , such that the saturation current of the transistor MN 4  is equal to a reference current IrefN. IrefN therefore represents the maximal current likely to pass through the transistor MN 4 . The output O 1  of the amplifier DAMP is connected to the drains of the transistors MP 2  and MN 2 . 
         [0010]    If the voltage Vin is greater than the voltage Vref 1 , the voltage VO 1  at the output O 1  decreases by tending towards the voltage GND 1  of the drain of the transistor MN 4 . Conversely, if the voltage Vin is lower than the voltage Vref 1 , then the voltage VO 1  is equal to the supply voltage Vdd. The output O 1  supplies a signal biased under a low current. The inverter I 1  is produced with transistors designed to be able to switch rapidly despite a low current available at the output O 1 . The W/L ratios of the transistors of the inverters I 1 , I 2  and I 3  have increasing values from I 1  to I 3 , to shape the signal coming from the output O 1  and to supply a logic signal at the output Vout. 
         [0011]    The amplifier DAMP imposes certain limitations on the value of the reference voltage Vref 1 . Indeed, the amplifier DAMP only operates in the presence of a sufficient positive current i in the reference branch (comprising the transistors MP 3  and MN 3 ). The transistor MN 3  must therefore allow a minimum current to pass. For this purpose, the voltage Vref 1  must be greater than the threshold voltage Vtn of the transistor MN 3 . To reduce the effect of the constraint imposed by this condition, native n-channel transistors are preferably used that have a lower threshold voltage Vtn. 
         [0012]    In addition, if the voltage Vref 1  is lower than the threshold voltage Vtn of the transistor MN 3 , the input stage does not operate at all. The output voltage Vout can then vary randomly, which can be a dangerous operating condition for the integrated circuit equipped with the input stage. As a result, to maintain the amplifier DAMP in a fully operational state, in given temperature and supply voltage conditions, and for a given manufacturing chain, the voltage Vref 1  must be sufficiently greater than the threshold voltage Vtn of the transistor MN 3 . This condition proves to be all the more restrictive as the variations in the voltage Vtn can be totally decorrelated from the variations in the voltage Vref 1 . 
         [0013]    Typically, the transistor MN 3  has for example a threshold voltage Vtn at ambient temperature of 450 mV, this voltage possibly varying by ±100 mV according to the manufacturing conditions. The temperature coefficient, i.e., the variation rate of the threshold voltage according to the temperature is equal to approximately −2 mV/° C. The result is that, in a recommended temperature variation range from −40 to +85° C., the threshold voltage of the transistor MN 3  can vary from 230 to 680 mV. To guarantee the operation of the amplifier DAMP, the voltage Vref 1  must be greater than 700 mV when the threshold voltage Vtn of the transistor MN 3  reaches 680 mV. If the voltage Vref 1  has its own variation range, it can reach 1 volt. 
         [0014]    Furthermore, the current passing through each of the input and reference branches must be low to limit the current consumption of the circuit. 
       BRIEF SUMMARY OF THE INVENTION 
       [0015]    An embodiment of the present invention provides an input stage for integrated circuits that does not have the limitations described above. To this end, one principle of one embodiment is to keep the transistor MN 3  on, by adjusting the reference voltage. 
         [0016]    Thus, one embodiment includes a circuit that measures the current i in the reference branch (transistors MP 3 , MN 3 ) of the comparator and that increases the reference voltage so that the current i remains greater than a minimum positive value. 
         [0017]    More particularly, one embodiment includes a device comprising a comparator for comparing the voltage of an input signal of the comparator with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. 
         [0018]    According to one embodiment, the device comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator. 
         [0019]    According to one embodiment of the present invention, the comparator comprises an input branch receiving the input signal and a reference branch receiving the reference voltage, the parameter representative of the operation of the comparator being a current passing through the reference branch. 
         [0020]    According to one embodiment of the present invention, the comparator does not operate correctly if the current measured is below a positive limit value. 
         [0021]    According to one embodiment of the present invention, the feedback circuit comprises a measuring stage supplying a measuring current proportional to the parameter to be measured, a reference voltage source, and means for raising the reference voltage when the measuring current is lower than a minimum current. 
         [0022]    According to one embodiment of the present invention, the feedback circuit comprises a resistor for raising the impedance of the reference voltage source and for raising the reference voltage under the effect of a current passing through the resistor and appearing when the current measured is lower than a minimum current. 
         [0023]    According to one embodiment of the present invention, the feedback circuit comprises a capacitor for absorbing oscillations appearing in the reference voltage. 
         [0024]    According to one embodiment of the present invention, the comparator comprises a first current mirror differential amplifier comprising an input branch receiving the input signal and a reference branch receiving the reference voltage. 
         [0025]    According to one embodiment of the present invention, the comparator comprises several inverters cascade-connected to an output of the differential amplifier for putting the output signal of the differential amplifier into the form of a logic signal. 
         [0026]    According to one embodiment of the present invention, the comparator comprises a second differential amplifier cascade-connected to an output of the first amplifier, and several inverters cascade-mounted at an output of the second differential amplifier, for putting the output signal of the first differential amplifier into the form of a logic signal. 
         [0027]    One embodiment of the present invention also relates to an integrated circuit comprising an input stage, characterized in that the input stage comprises a device as defined above, and an input connected to the input of the comparator. 
         [0028]    One embodiment of the present invention also relates to an acquisition method for acquiring an input signal in an integrated circuit, comprising steps of comparing the voltage of an input signal with a reference voltage, and supplying a binary output signal the value of which results from the comparison of the input signal with the reference voltage, 
         [0029]    characterized in that it comprises steps of measuring a parameter representative of the operation of a comparator having performed the comparison step, and of raising the reference voltage, while the measured parameter reveals a faulty operation of the comparator. 
         [0030]    According to one embodiment of the present invention, the parameter representative of the operation of the comparator is a current passing through a reference branch of the comparator. 
         [0031]    According to one embodiment of the present invention, the comparator is not operating correctly if the current measured is below a positive limit value. 
         [0032]    According to one embodiment of the present invention, the method comprises steps of supplying a measuring current proportional to the parameter to be measured, and of raising the reference voltage when the measuring current is lower than a minimum current. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0033]    These and other features and advantages of the present invention shall be presented in greater detail in the following description of an embodiment of the present invention, given in relation with, but not limited to the following figures, in which: 
           [0034]      FIG. 1  already described represents an input stage according to previous practices, 
           [0035]      FIG. 2  already described represents another input stage according to previous practices, 
           [0036]      FIG. 3  represents an input stage according to one illustrated embodiment, 
           [0037]      FIG. 4  represents voltage curves showing the operation of the input stage according to the embodiment illustrated in  FIG. 3 , 
           [0038]      FIG. 5  shows another input stage according to a second illustrated embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0039]      FIG. 3  represents an input stage of an integrated circuit according to the present invention. In  FIG. 3 , the input stage INST 3  comprises an input Vin, an output Vout, and a comparator for comparing the voltage applied to the input Vin with a reference voltage Vref 2 . The comparator comprises a differential amplifier DAMP connected to the input Vin of the input stage, and three cascade-arranged inverters I 1 , I 2 , I 3  connected between an output O 1  of the amplifier DAMP and the output Vout of the input stage INST 3 . The amplifier comprises an input branch Vin receiving the input voltage and a reference branch receiving the reference voltage Vref 2 . 
         [0040]    According to one embodiment, the input stage INST 3  comprises a feedback circuit FBCT that adjusts the reference voltage Vref 2  so that the current in the reference branch remains greater than a minimum positive value imin. 
         [0041]    The amplifier DAMP is similar to the amplifier described with reference to  FIG. 2 . Thus, the amplifier DAMP comprises an input branch receiving the input voltage Vin and a reference branch receiving a reference voltage Vref 2 . The input branch comprises a p-channel MOS transistor MP 2  the source of which receives the supply voltage Vdd and the drain of which is connected to the drain of an n-channel MOS transistor MN 2 . The gate of the transistor MN 2  receives the input voltage Vin. The reference branch comprises a p-channel MOS transistor MP 3  the source of which receives the supply voltage Vdd and the drain of which is connected to the drain of an n-channel MOS transistor MN 3 . The gate of the transistor MP 2  that is at a voltage GP, is connected to the gate and to the drain of the transistor MP 3 . 
         [0042]    The sources of the transistors MN 2  and MN 3  are connected to the drain of an n-channel MOS transistor MN 4  the source of which is connected to the ground. A reference voltage VrefN is applied to the gate of the transistor MN 4 , such that a reference current IrefN circulates in the transistor MN 4 . The output O 1  of the amplifier DAMP is connected to the drains of the transistors MP 2  and MN 2 . The current i circulating in the reference branch is identical to the current circulating in the input branch if the transistors MP 2  and MP 3  have the same physical properties, and in particular the same channel length and width. 
         [0043]    If the voltage Vin is greater than the voltage Vref 2 , the voltage VO 1  at the output O 1  decreases by tending towards the voltage GND 1  of the drain of the transistor MN 4 . Conversely, if the voltage Vin is lower than the voltage Vref 2 , then the voltage VO 1  is equal to the supply voltage Vdd. The output O 1  supplies a signal biased under a low current. The inverter I 1  is produced with transistors designed to be able to switch rapidly despite a low current available at the output O 1 . In other words, the transistors of the inverter I 1  have low channel width W and length L to capacitively load the output O 1  as little as possible, in order to optimize the switch speed of the inverter. The W/L ratios of the transistors of the inverters I 1 , I 2  and I 3  have increasing values from I 1  to I 3 , to shape the signal coming from the output O 1  and to supply a logic signal at the output Vout. 
         [0044]    If the voltage GND 1  is too low to be compatible with a classic inverter, the inverter I 1  may be made up of to be a differential amplifier, of the amplifier DAMP type for example. 
         [0045]    The circuit FBCT comprises p-channel MOS transistors MP 4 , MP 5  the source of which receives the supply voltage Vdd, n-channel MOS transistors MN 5 , MN 6  the source of which is connected to the ground, an n-channel MOS transistor MN 7 , and a resistor R. The gate of the transistor MP 4  receives the voltage GP from the gates of the transistors MP 2  and MP 3 . The gate and the drain of the diode-mounted transistor MN 5  are connected to the drain of the transistor MP 4 . The gate of the transistor MP 5  receives a reference voltage VrefP, such that the saturation current of the transistor MP 5  is equal to a reference current IrefP. The drain of the transistor MP 5  is connected to the drain of the transistor MN 6 , and to the drain and to the gate of the diode-mounted transistor MN 7 . The source of the transistor MN 7  is connected to the gate of the transistor MN 3  and linked to a reference voltage source Vref through the resistor R. 
         [0046]    The NMOS transistors of the amplifier DAMP and of the circuit FBCT are preferably native n-channel transistors. 
         [0047]    The reference voltage Vref 2  that is applied to the gate of the transistor MN 3  is substantially equal to the voltage Vref possibly increased by the voltage that appears on the resistor R under the effect of the current i 2  that appears on the drain of the transistor MN 7 . 
         [0048]    The operation of the circuit FBCT according to the embodiment illustrated in  FIG. 3  is shown by  FIG. 4 .  FIG. 4  represents in the shape of curves, examples of variations in the reference voltages Vref and Vref 2 , and in the threshold voltage Vtn, according to a parameter P characterizing the operating environment of the integrated circuit, i.e., particularly operating temperature, supply voltage, or variation in the manufacturing chain. If the reference voltage Vref applied to the amplifier DAMP is situated in an area NW (marked by dotted lines in the figure) below the variation curve of the voltage Vtn, the amplifier DAMP does not operate, as the current i passing through the transistor MN 3  is zero. With the input stages of previous practices such as the input stage INST 2  shown in  FIG. 2 , it was therefore necessary to choose a reference voltage Vref 1  that was always much greater than the threshold voltage Vtn, so as to have a margin of safety in relation to the variations in the voltages Vref 1  and Vtn. On the contrary, in the input stage INST 3  according to the present invention, the reference voltage Vref can be chosen at a lower value that can be situated in the area NW. 
         [0049]      FIG. 4  also represents a vertical straight line T passing through a point of intersection P 1  between the variation curve of the voltage Vtn and the variation curve of the voltage Vref. The straight line T delimits a normal operating area NA on the left-hand side, and a secure operating area SA on the right-hand side of the straight line T. 
         [0050]    When the reference voltage Vref is greater than the threshold voltage Vtn of the transistor MN 3  (i.e., when the voltage Vref is situated in the area NA), the circuit FBCT does not change this reference voltage (Vref 2 =Vref). On the other hand, when the reference voltage Vref is insufficient to bias the amplifier (Vref&lt;Vtn) (i.e., when the voltage Vref is situated in the area SA on the right-hand side of the straight line T), the circuit FBCT applies to the gate of the transistor MN 3  of the amplifier DAMP a voltage Vref 2  equal to the voltage Vref to which the voltage R.i 2  (Vref 2 =Vref+R.i 2 ) is added. The voltage Vref 2  is thus fixed at a value greater than the voltage Vtn, so that the current i circulating in the transistor MN 3  is greater than the minimum fixed value imin. 
         [0051]    In practice, the circuit FBCT measures the current i passing through the transistor MP 2  using a current mirror comprising the transistor MP 3 , and applies a current to the resistor R if the current i measured is lower than a certain value. For this purpose, the current that circulates in the transistor MP 3  is copied in the transistor MN 5 , then in the transistor MN 6 . The transistor MN 5  tends to impose in the transistor MN 6  a current i 1  proportional to the current i (i 1 =K.i). The proportionality coefficient K depends on the ratio of the mirror chain formed by the transistors MP 3 , MP 4 , MN 5  and MN 6 . More precisely, the ratio K is proportional to the ratio WR=(WMP 4 /WMP 3 ).(WMN 6 /WMN 5 ,) in which WMP 4 , WMP 3 , WMN 5 , WMN 6  are respectively the channel widths of the transistors MP 4 , MP 3 , MN 5  and MN 6 . 
         [0052]    If the current i 1  in the transistor MN 6  is lower than the saturation current IrefP of the transistor MP 5 , the transistor MP 5  draws more current than the transistor MN 6 . The result is that the voltage VO 2  increases and therefore that the voltage Vref 2  increases too. The transistor MN 3  then draws more current, and therefore causes the intensity of the current I to increase. Equilibrium is achieved when i 1  (=K.i)=IrefP. 
         [0053]    Therefore, the choice of the voltage VrefP enables the value of the minimum positive current i imin, which must circulate in the reference branch and in the input branch, to be adjusted to the equilibrium of the feedback loop: 
         [0000]        I min= I ref P/K    (1) 
         [0054]    This choice is useful because the aim is to find a compromise between the current consumption and the reaction rate of the input circuit. If the input signal has a frequency in the order of a few tens of kHz, the current i must be equal to at least about a hundred nA. If the input signal has a frequency in the order of a few MHz, the current i must be equal to at least a few μA. 
         [0055]    The reference voltage source Vref has a low impedance. The presence of the resistor R enables the voltage Vref 2  to be increased under the effect of the current i 2 . The value of the resistor R influences the feedback loop formed by the circuit FBCT. The higher the value of this resistor, the higher the gain of the feedback loop formed by the circuit FBCT, which tends to increase the risk of appearance of oscillations.  FIG. 5  shows another embodiment of a feedback circuit that overcomes this disadvantage. The circuit FBCT comprises, as shown in  FIG. 5 , a capacitor C enabling the feedback loop to be stabilized. The capacitor C can be inserted between the drain of the transistor MN 6  or the source of the transistor MN 7  and the ground ( FIG. 5 ). 
         [0056]    The current circulating in the input branch (transistors MP 2 , MN 2 ) is substantially equal to the current i circulating in the reference branch (transistors MP 3 , MN 3 ) if the input voltage Vin is greater than or equal to the voltage Vref 2 . The result is that two branches of the differential amplifier tend to impose a maximum current equal to 2i in the transistor MN 4 . Now, the maximum current that can pass through the transistor MN 4  is equal to its saturation current IrefN. Therefore, the current i will be controlled by the feedback circuit FBCT if IrefN&gt;2i, i.e.: 
         [0000]      i&lt; I ref N/ 2.   (2) 
         [0057]    In the opposite case, the maximum current would be controlled by the transistor MN 4 , and equal to IrefN/2, while the circuit FBCT would tend to impose a voltage O 2 =Vdd, and therefore to saturate the voltage Vref 2  to a maximum voltage, close to Vdd−Vtn, without being capable of reaching the value of the current i in the transistor MP 3 . The condition IrefN&gt;2i also ensures that the transistor MN 4  will not be saturated, and therefore that the voltage GND 1  will remain sufficiently low for the voltage O 1  in the low state to be close to the ground, which is compatible with the use of the inverter I 1 . 
         [0058]    As K.i=IrefP in equilibrium, the condition (2) is equivalent to the following condition: 
         [0000]        I ref P &lt;( K/ 2). I ref N.    (3) 
         [0059]    Therefore, the conditions (1) and (3) enable the values to be chosen of IrefP and IrefN to be determined according to the desirable minimum value imin of the current i in the reference branch. 
         [0060]    The circuit FBCT that has just been described makes it possible not to impose a high reference voltage Vref, while respecting a sufficient margin of safety on the differential amplifier operation. 
         [0061]    It can be advantageous in certain applications to choose a voltage source that supplies a reference voltage Vref lower than or equal to the threshold voltage Vtn, such that the reference voltage Vref 2  that is applied to the gate of the transistor MN 3  is always adjusted by the circuit FBCT to a minimum value guaranteeing that the differential amplifier DAMP operates correctly. 
         [0062]    It will be understood by those skilled in the art that various alternative embodiments and applications of the present invention are possible. Thus, the present invention is not limited to measuring current in the reference branch. Indeed, it is possible to consider measuring the voltage GND 1  to detect a correct operation of the differential amplifier. If the voltage GND 1  is zero or too close to the ground, the current passing through the reference and input branches is insufficient. 
         [0063]    In addition, certain applications may not need a shaped signal at output Vout of the comparator. In this case, the inverters I 1 , I 2 , I 3  cascade-mounted at the output of the differential amplifier DAMP are not necessary. 
         [0064]    The present invention does not necessarily apply to an integrated circuit. Generally speaking, the present invention can be applied to any device that must detect the presence of voltages that can be low.

Technology Classification (CPC): 7