Patent Abstract:
An amplifier arrangement is provided which comprises first and second biasing power supply circuits, a push-pull amplifier comprising a pair of transistors, a DC amplifier having a non-inverting input terminal connected to a junction point at which one half of a predetermined potential fed from the first biasing power supply circuit is applied and an inverting input terminal connecting a feedback loop through which the output the amplifier is fedback, a second biasing power supply circuit having a junction point at which the output of the DC amplifier is applied, and means responsive to an output of the DC amplifier for applying either of the first and second predetermined potentials fed from the first and second biasing circuits in accordance with the amount of feedback from the output of the push-pull amplifier to produce an output signal showing a biasing current, whereby the output signal is applied to each base of the push-pull transistors so as to balance the half potential of the first biasing power supply circuit with the potential at the output of the push-pull amplifier.

Full Description:
This is a continuation, of application serial no. 071,865 (now abandoned) filed Sept. 4, 1979. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a push-pull amplifier, and more particularly to an amplifier circuit which makes it possible to automatically adjust a biasing current. 
     FIG. 1 is a circuit diagram of a conventional push-pull amplifier. 
     Referring to FIG. 1, Q 1  and Q 2  denote NPN and PNP transistors, respectively, R 1  and R 2  resistors for stabilizing a biasing current I B , Z L  load including reactance, V BS  /2 biasing power supply circuit, and +V CC  and -V CC  DC voltage power supplies, respectively. 
     If the input voltage e i  is 0 volts, the electric potential at the output terminal P is approximately 0 volts. Since no load current I L  flows, only a biasing current I B  ≃[V BS  -(V BE1  +V BE2 )]/(R 1  +R 2 ) flows between transistors Q 1  and Q 2 . 
     However, assuming that the input voltage e i  varies towards positive-going swing, the load current I L  flows in the direction of the solid line shown in FIG. 1 from the transistor Q 1 . Due to the voltage drop I L  R 1  across the resistor R 1 , the biasing current I B  decreases. 
     If the input voltage e i  further increases and I L  R 1  ≧V BS  -(V BE1  +V BE2 ) holds, the transistor Q 2  will be completely cut off. 
     In this condition, the push-pull circuit becomes equal to an emitter-follower circuit in which only transistor Q 1  is used, resulting in deterioration in the transient characteristics if the load Z L  includes reactance. 
     On the other hand, when the input voltage e i  varies towards negative-going swing, the load current I&#39; L  flows in the direction of the broken line in FIG. 1 to the transistor Q 2 . 
     Accordingly, when I&#39; L  R 2  ≧V BS  -(V BE1  +V BE2 ) holds, transistor Q 1  is completely cut off, resulting in the same phenomenon. 
     In order to prevent this the push-pull circuit may, for instance, be greately biased to effect class &#34;A&#34; amplification. Thus, if the circuit is designed so that a biasing current I B  flows, serving as an idling current whose value is of the order of magnitude of the load current I L , some improvement may be expected. 
     However, with this conventional circuit, a low efficiency of amplification will be obtained. Moreover, in order not to allow transistors Q 1  and Q 2  to be completely cut off, the minimum impedance value of the load is limited to a predetermined value. Therefore, this method is not very satisfactory. 
     SUMMARY OF THE INVENTION 
     With the above in mind, an object of the present invention is to provide a push-pull amplifier circuit which makes it possible to keep a biasing current constant independent of the load current. 
     Another object of the present invention is to provide a push-pull amplifier circuit including a feedback loop for automatically adjusting a biasing current to obtain good transfer characteristics. 
     A further object of the present invention is to provide a push-pull amplifier circuit wherein the feedback loop mentioned above is designed so as to have a gain of unity to improve linearity of the transfer characteristics of the push-pull amplifier. 
     According to the present invention, there is provided an amplifier comprising a push-pull amplifier connected to a biasing power supply circuit for supplying a biasing current through a first diode to the push-pull amplifier, and a DC amplifier connected to an input of the push-pull amplifier via a second diode connected with the first diode in logical-sum fashion so as to balance the half potential of the biasing power supply circuit with the potential at the output of the push-pull amplifier, thereby maintaining the biasing current constant independent of the load current flowing during rated operation of the push-pull amplifier. 
     Further in accordance with the present invention, there is provided an amplifier arrangement which comprises a first and a second biasing power supply circuits, a push-pull amplifier comprising a pair of transistors, a DC amplifier having a noninverting input terminal connected to a junction point which one half of a predetermined potential fed from the first biasing power supply circuit is applied and having an inverting input terminal connected to a feedback loop through which the output of the amplifier is fedback, a second biasing power supply circuit having a junction point at which the output of the DC amplifier is applied, and means responsive to an output of the DC amplifier for applying either of the first and second predetermined potentials fed from the first and second biasing circuits in accordance with the amount of feedback from the output of the push-pull amplifier to produce an output signal is applied to each base of the push-pull transistors so as to balance the half potential of the first biasing power supply circuit with the potential at the output of the push-pull amplifier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of a push-pull amplifier circuit according to the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a circuit diagram of a conventional push-pull amplifier circuit, 
     FIG. 2 is a circuit diagram of a push-pull amplifier circuit according to the present invention, 
     FIG. 3 is a graph illustrating characteristics of load current versus biasing electric potential according to the present invention, 
     FIG. 4 is a graph illustrating load current versus biasing electric current characteristics and transfer characteristics according to the present invention, 
     FIG. 5 is a graph illustrating load current versus biasing current characteristics and transfer characteristics according to conventional push-pull amplifier circuit, 
     FIG. 6 is a circuit diagram of a modification of a push-pull amplifier circuit according to the present invention, 
     FIG. 7 is a circuit diagram of another embodiment of a push-pull amplifier circuit according to the present invention, and 
     FIG. 8 is a circuit diagram wherein a push-pull circuit according to the present invention is applied to a high fidelity amplifier. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG., 2, Q&#39; 1  and Q&#39; 2  denote NPN and PNP transistors, respectively, R&#39; 1  and R&#39; 2  are resistors for stabilizing a biasing current I&#39; B , Z&#39; L  is a load including reactance, V&#39; BS  /2 is a biasing power supply circuit, and +V&#39; CC  and -V&#39; CC  respectively, are positive and negative DC power supplies. A and V&#34; BS  /2 denote a DC amplifier and biasing power supply circuits, respectively, which are newly added in the present invention. 
     D 1 , D 2 , D 3 , and D 4  denote diodes for preventing reverse direction current in the biasing power supply circuits and for applying either of the output of the biasing circuit already provided in the prior art circuit and the output of the biasing circuit newly added according to the present invention in accordance with the amount of feedback from the output of the push-pull amplifier. 
     Now, let the gain of the DC amplifier be designated by A. Then, suppose that settings are made such that the offset voltage is zero, biasing voltages V&#39; BS  /2 and V&#34; BS  /2 are equal, the emitter resistances R&#39; 1  and R&#39; 2  of the transistors Q&#39; 1  and Q&#39; 2  equal each other, the forward voltages V D  across diodes D 1 , D 2 , D 3  and D 4  equal each other, and the forward voltages V BET  between base and emitter electrodes of the transistors Q&#39; 1  and Q&#39; 2  equal each other. 
     Electric potentials e a  and e o  at output terminal C of the DC amplifier and at output terminal p&#39; of the push-pull amplifier are determined from the input voltage e i  and the load current I&#34; L  as follows; ##EQU1## If the gain of the DC amplifier is sufficiently large, equations (1) and (2) may be regarded as the following equations (1)&#39; and (2)&#39;, respectively: 
     
         e.sub.a ≃e.sub.i +R&#39;.sub.1 I&#34;.sub.L          (1)&#39; 
    
     
         e.sub.o ≃e.sub.i                             (2)&#39; 
    
     Equation (1)&#39; shows that the output e a  of the DC amplifier varies according to increase and decrease of the load current, and the current flow direction. 
     Equation (2)&#39; shows that the output voltage e o  of the push-pull amplifier is independent of increases and decreases of the load current. 
     The concept expressed by the above equations (1), (2), (1)&#39; and (2)&#39; is essential for the present invention. Accordingly, it is important to refer to details of the derivation thereof for a better understanding of the present invention. 
     In FIG. 2, a non-inverting input terminal and an inverting input terminal of the differential amplifier are connected to the input voltage e i  and the output terminal p&#39; of the push-pull amplifier, respectively. Accordingly, assuming that the gain of the differential amplifier is A, the output voltage e a  is expressed by the following equation; 
     
         e.sub.a =(e.sub.i -e.sub.o)A                               (i) 
    
     Suppose that e a  &gt;e i , the diode D 2  becomes conductive, and D 1  becomes nonconductive, then D 4  becomes conductive, and D 3  becomes nonconductive. The following equations are derived on the basis of this supposition. 
     Calculating the output voltage e a  of the differential amplifier from the path through the diode D 2  to the load Z&#39; L , the following equation is obtained. 
     
         e.sub.a =e.sub.o +R&#39;.sub.1 (I&#39;.sub.B +I&#34;.sub.L)+V.sub.BET +V.sub.D -V&#34;.sub.BS /2                                             (ii) 
    
     Calculating the biasing current I&#39; B  flowing in transistors Q&#39; 1  and Q&#39; 2  from the path through the diode D 4  to the load Z&#39; L , the following equation is obtained. ##EQU2## Substitution of equation (iii) into equation (ii) gives: ##EQU3## Taking into account R&#39; 1  =R&#39; 2 , and V&#39; BS  /2=V&#34; BS  /2 
     
         e.sub.a =2e.sub.o -e.sub.i +R&#39;.sub.1 I&#34;.sub.L              (iv) 
    
     is obtained. Elimination of e a  from equations (i) and (iv) gives: ##EQU4## Similarly, elimination of e o  from equations (1) and (iv) gives: ##EQU5## In the above calculation, it was assumed that e a  &gt;e i , but if assuming that e a  &lt;e i , the diode D 2  becomes nonconductive, the diode D 1  becomes conductive, the diode D 4  becomes nonconductive, and D 3  becomes conductive. From the path through the diode D 3  to the load Z&#39; L , a calculation of the output voltage e a  of the differential amplifier is carried out to obtain the following equation similar to the equation (ii), 
     
         e.sub.a =e.sub.o -R&#39;.sub.2 (I&#39;.sub.B -I&#34;.sub.L)-V.sub.BET -V.sub.D +V&#34;.sub.BS /2                                             (ii)&#39; 
    
     Furthermore, from the path through the diode D 1  to the load Z&#39; L , a calculation of the biasing current I&#39; B  flowing in transistors Q&#39; 1  and Q&#39; 2  is carried out to obtain the following equation, ##EQU6## Substitution of equation (iii)&#39; into equation (ii)&#39;, in consideration of R&#39; 1  =R&#39; 2  and V&#39; BS  /2=V&#34; BS  /2, gives 
     
         e.sub.a =2e.sub.o -e.sub.i +R&#39;.sub.1 I&#34;.sub.L              (iv)&#39; 
    
     which is the same as equation (iv). Similarly, from equations (i) and (iv)&#39; e a  and e o  are obtained with the same formulation as equations (1) and (2). Accordingly, it is understood that equations (1) and (2) always hold irrespective of the signs of the terms. As A goes to infinity, equations (1) and (2) become 
     
         e.sub.a ≃e.sub.i +R&#39;.sub.1 I&#34;.sub.L          (1)&#39; 
    
     
         e.sub.o ≃e.sub.i                             (2)&#39; 
    
     Thus, equations (1)&#39; and (2)&#39; are obtained. 
     Suppose that the base electrode voltages of the transistors Q&#39; 1 , Q&#39; 2  with respect to ground are V BG1 , and V BG2 , respectively. 
     The values of the voltages V BG1  and V BG2  are classified into the following cases, in accordance with the states of the diodes D 1  to D 4 , and the polarity of the load current I&#34; L   
     (1) I&#34; L  ≧O (when I&#34; L  flows in the direction of the arrow in FIG. 2.) 
     
         V.sub.BG1 =V&#39;.sub.BS /2+e.sub.i +R&#39;.sub.1 I&#34;.sub.L -V.sub.D (3) 
    
     
         V.sub.BG2 =V.sub.BS /2+e.sub.i +V.sub.D                    (4) 
    
     (2) I&#34; L  &lt;O (when I&#34; L  flows in the direction opposite to the arrow in FIG. 2.) 
     
         V.sub.BG1 =V&#39;.sub.BS /2+e.sub.i -V.sub.D                   (3)&#39; 
    
     
         V.sub.BG2 =-V&#39;.sub.BS /2+e.sub.i +R&#39;.sub.1 I&#34;.sub.L +V.sub.D (4)&#39; 
    
     In equation (3), diode D 2  is conducting but the diode D 1  is cut off because of the inverse bias. 
     In equation (4), diode D 4  is conducting but the diode D 3  is cut off because of the reverse bias. 
     On the other hand, in equation (3)&#39; the diode D 1  is conducting, but the diode D 2  is cut off and in equation (4)&#39; the diode D 3  is conducting, but the diode D 4  is cut off. 
     Thus, it is possible to apply either of the output of each biasing circuit, thereby maintaining a biasing current constant independent of the load current. 
     FIG. 3 is a graph of the voltages V BG1  and V BG2  against the load current I&#34; L . 
     In FIG. 3, I&#34; L  and voltages are abscissas and ordinates, respectively, and the input voltage e i  is indicated on the V axis. 
     The graph of the voltages V BG1  and V BG2  has a rotational symmetry with respect to the value e i  on the V axis. When the transistor Q&#39; 1  becomes operative so that load current I&#34; L  flows in the positive direction, the voltage V BG1  increases by the voltage drop occurring across the emitter resistor R&#39; 1  of the transistor Q&#39; 1 , thereby keeping the potential level of the output terminal P equal to that of e i . 
     On the contrary, when the transistor Q&#39; 2  becomes operative so that the load current I&#34; L  flows in the negative direction, V BG2  is lowered by the voltage drop produced across the emitter resistance R&#39; 2  of the transistor Q&#39; 2 , thereby keeping the potential e o  at the output P of the push-pull circuit equal to that of e i . 
     Thus, a constant biasing voltage is applied to whichever transistor is not conducting. 
     That is, constant biasing voltage potentials V&#39; BS  /2-V D  and -V&#39; BS  /2+V D  are applied between the bases of transistors Q&#39; 1  and Q&#39; 2 , respectively, and the output of the push-pull circuit. Accordingly, it is possible to maintain a constant bias current I&#39; B  =[V&#39; BS  α/2-(V D  +V BET )]/R&#39; 1  between the emitter electrodes of the transistors Q&#39; 1  and Q&#39; 2 . 
     It will now be shown that, according to the present invention, irrespective of the value of the load current I&#34; L , neither of the transistors Q&#39; 1  and Q&#39; 2  constituting the push-pull amplifier are ever put in the nonconducting state. 
     FIG. 4 is a graph illustrating the relationship between the load current I&#34; L  and the emitter currents of the transistors Q&#39; 1  and Q&#39; 2  according to the present invention. 
     FIG. 5 shows a similar relationship according to a conventional circuit. 
     As will be seen from FIG. 4, a predetermined bias current I&#39; B  flows in the transistor which is not conducting. 
     On the contrary, in the conventional circuit shown in FIG. 5, a bias current flows only when the load current I L  is in the vicinity of zero. When the load current I L  increases or decreases, one of the transistors Q 1  or Q 2  will be cut off. 
     Another drawback of the conventional circuit is that the transfer characteristic of the push-pull amplifier has curved portion where the load current is in the vicinity of zero, as shown by a broken line in FIG. 5, while, as shown by a broken line in FIG. 4, the transfer characteristic of a push-pull circuit according to the present invention has good linearity since a large negative feedback is supplied to the push-pull circuit. 
     FIG. 6 shows a circuit which is a modified version of the present invention, using transistors to provide the selecting of either of the outputs of each biasing circuit and push-pull operation, in place of the diodes used in the basic circuit shown in FIG. 2. 
     In FIG. 6, Q 3  and Q 4  denote NPN transistors, Q 5  and Q 6  PNP transistors, R&#34; 1 , R&#34; 2  resistors for stabilizing a bias current, Z&#34; L  a load including reactance, V BB  /2 bias power supply circuit, +V c  and -V c  plus and minus power supplies, and A&#39; a DC amplifier. 
     The basic operation is the same as that of the basic circuit shown in FIG. 2, but by making judicious use of inverse voltages between the base and emitter electrodes of transistors Q 3 , Q 4 , Q 5  and Q 6 , the same effect as with the diodes in the basic circuit is obtained. It is to be noted that these transistors also effect the push-pull operation. 
     FIG. 7 shows a circuit in which performance is improved in practice wherein a sum output between common emitter electrodes of the transistors is obtained similarly to the FIG. 6 circuit, but the output of the common emitter is not directly connected to the load, but it is Darlington-connected to a push-pull amplifier comprising separate transistors. 
     Referring to FIG. 7, Q&#34; 1  and Q&#34; 2  denote NPN and PNP transistors, R&#34; 1 , R&#34; 2  resistors for stabilizing bias current, Z&#39;&#34; L  a load including reactance, V&#39; BB  /2 bias power supply circuit, +V&#39; c  and +V&#34; cc  plus DC power supply circuits, -V&#39; c  and -V&#39; cc  minus DC power supply circuits, A&#34;DC amplifier, Q&#39; 3 , Q&#39; 4 , Q&#39; 5 , and Q&#39; 6  transistors which have the same function as the diodes of the basic circuit shown in FIG. 2 with the addition of a current amplification function. 
     The operation of this circuit is the same as the basic circuit. This circuit is characterized in that transistors Q&#39; 3 , Q&#39; 4  are connected to transistor Q&#34; 1  of the push-pull circuit by Darlington-connection, and transistors Q&#39; 5  and Q&#39; 6  are also connected to transistor Q&#34; 2  of the push-pull circuit by Darlington-connection. With this circuit, it is possible to lessen the load on the DC amplifier circuit A&#34;, and also that on the input power supply. 
     As stated above, the present invention provides for high linearity even for reactance loads. Accordingly, this circuit is widely applicable to various kind of stabilized power supply circuit. 
     Particularly, if the circuit of FIG. 7 is used as a stabilizing circuit and using a reference power supply as an input e i , not only a good source ability for supplying a current but also a good sink ability for absorbing current will be obtained, thereby improving performance over that of a conventional amplifier. 
     Reference is finally made to the embodiment applicable to a high fidelity amplifier illustrated in FIG. 8, wherein Q&#39;&#34; 1  and Q&#39;&#34; 2  denote NPN and PNP transistors, R&#34;&#34; 1 , R&#34;&#34; 2  resistors for stabilizing bias current, Z&#34;&#34; L  a load including reactance, V&#34; BB  /2 bias power supply circuit, +V&#34; c  and -V&#39;&#34; c  plus DC power supply circuits, -V&#34; c  and -V&#34; c  minus DC power supply circuits, and Q&#34; 3 , Q&#34; 4 , Q&#34; 5  and Q&#34; 6  transistors which have the same function as the corresponding transistors Q&#39; 3 , Q&#39; 4 , Q&#39; 5  and Q&#39; 6  shown in FIG. 7. 
     In this example, two DC amplifiers are employed, whereby an amplifier A&#39;&#34; for adjusting the bias is included within a feedback loop for the amplifier A&#34;&#34; which sets the gain. 
     It is to be understood that modifications and variations of the embodiments of the invention disclosed herein may be resorted to without departing from the spirit of the invention and the scope of the appended claims.

Technology Classification (CPC): 7