Patent Abstract:
Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2 n  control bits normally required can be reduced to 2 (n-1)  by jointly controlling pairs of the current sources with one of the 2 (n-1)  current control bits and inverses of two other ones of the 2 (n-1)  current control bits.

Full Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates to digital-to-analog converters (DACs), and in particular, to DACs used for phase interpolation. 
     2. Related Art 
     Conventional phase interpolation DACs have their precision and physical size determined by the number 2 n  of steps that are available. In a unary-weighted current steering DAC circuit architecture, the large number 2 n  of control signals, or bits, needed to control each of the current sources can be problematic in terms of the amount of physical area required to route so many signals. Further, another large layout area is required to perform the necessary decoding operations for the n-bit digital signal to create the 2 n  control signals necessary for the DAC. 
     Accordingly, it would be desirable to have a technique for reducing the number of DAC control signals while maintaining the same precision or resolution. 
    
    
     
       BRIEF DESCRIPTION OF TI-IE DRAWINGS 
         FIG. 1  is a partial schematic diagram of a conventional phase interpolating DAC. 
         FIG. 2  depicts the circuitry of  FIG. 1  with devices turned on and off to present the output signal with a different phase. 
         FIG. 3  is a partial schematic diagram of a phase interpolating DAC in accordance with one embodiment of the presently claimed invention. 
         FIGS. 4 ,  5 ,  6  and  7  depict the circuitry of  FIG. 3  with different current sources enabled and disabled to provide currents with different phases. 
         FIG. 8  is a functional blank diagram depicting the decoding of the original digital input signal to provide the current control bits. 
         FIG. 9  is a functional block diagram of an exemplary embodiment of an integrated circuit design and fabrication system operated in accordance with computer instructions. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. Moreover, to the extent that the figures illustrate diagrams of the functional blocks of various embodiments, the functional blocks are not necessarily indicative of the division between hardware circuitry. Thus, for example, one or more of the functional blocks (e.g., processors, memories, etc.) may be implemented in a single piece of hardware (e.g., a general purpose signal processor, random access memory, hard disk drive, etc.). Similarly, any programs described may be standalone programs, may be incorporated as subroutines in an operating system, may be functions in an installed software package, etc. 
     Referring to  FIG. 1 , a conventional phase interpolating DAC includes current steering circuitry in the form of differential amplifiers, which are often implemented using bipolar junction transistors Qi, Qiz, Qq, Qqz and resistances R 1 , R 2 , interconnected substantially as shown. A current source Iref provides current to the input branch of a current mirror circuit formed by totem-pole-coupled N-type MOSFETs N 1 , N 2 , with the first transistor N 1  being diode-coupled and the second transistor N 2  having its gate electrode biased to be in a constant on state. In accordance with well-known principles, this input current Iref is replicated, or mirrored, as the channel current of each of the tail current sources formed by transistors N 00 , N 01 , N 02 , . . . , N 63  (for a 64-bit DAC). Conduction of the channel current through each of these transistors N 00 , N 01 , N 02 , . . . , N 63  is enabled and disabled by switches S 00 , S 01 , S 02 , . . . , S 64 , typically implemented as additional N-MOSFETs, each of which is turned on and off, i.e., enabled and disabled, respectively, by a corresponding one of the current control bits  00 ,  01 ,  02 , . . . ,  64 . (The current mirror transistors N 00 , N 01 , N 02 , N 63  are often implemented as thick gate devices for 2.5 volt operation, while the switching transistors S 00 , S 01 , S 02 , . . . , S 63  are often implemented as thin gate devices for operation at 1.2 volts.) Accordingly, as depicted in  FIG. 1 , when the first 16 current sources are turned on, the first 16 current control bits  00 ,  01 ,  02 , are asserted, i.e., at a high signal state, thereby allowing current flow through their corresponding current mirror output transistors N 00 , N 01 , N 02 , . . . , N 15 . 
     Referring to  FIG. 2 , providing current at the next phase is achieved by de-asserting the first control bit  00  to turn off the first switch S 00 , while asserting control bit  16  to turn on the next downstream switch S 16 , thereby enabling current flow through its current mirror transistor N 16 . As can be seen, the full complement of 2 n  control bits are necessary, thereby requiring a large area for routing the signals and a corresponding large area for the decode logic to provide the signals. 
     As is well known in the art, this circuitry is operated in this manner so that a given amount of current is being steered out of the DAC at all times, thereby requiring a number m of adjacent current sources to be turned on at all times. Accordingly, to adapt forward to the next step in phase, one leading control bit is asserted to turn on the corresponding leading current source, while simultaneously de-asserting a lagging control bit to turn off the corresponding lagging current source. This ensures that only m bits are enabled. 
     As discussed in more detail below, a DAC in accordance with the presently claimed invention effectively partitions decoding between the CMOS digital logic (not shown) and the unary current source bank. The decode logic (discussed in more detail below) generates an intermediate set of control bits, adapting to the next step by turning on a leading control bit without turning off the lagging control bit. The subsequent adaptation then turns off the lagging bit. Accordingly, at any point in time either m/2 or m/2+1 bits out of 2 n  bits are enabled. Each of these 2 n  control bits and their inversions are used to control the current DAC. Hence, while there are effectively still 2 n  control signals used, half of them are space- and logic-efficient inversions of the original decoded control bits. 
     The current steering DAC is implemented using 2 n  unary current sources (e.g., output branches of a current mirror circuit) and efficiently decodes m/2 or m/2+1 bits to determine which of the m unary current sources should be enabled. The look-ahead and look-behind circuit structure uses the adjacent nature of the “on” control bits to decode which unary current sources should be enabled. Thus, for a current steering DAC in accordance with the presently claimed invention, n is an integer three or greater, so 2 n  is greater than or equal to eight, and m is an even integer 2 n −2 (corresponding to such look-ahead and look-behind circuit structure). 
     Conduction of current through each of the current sources is enabled and disabled with two serially coupled switches that provide switching on two levels. On one level, each of the two 2 n-1  non-inverted control bits  00 ,  01 ,  02 , . . . ,  31  is used to turn on two adjacent switches, i.e., for a total of 2 n  switches. On another level, inverted versions of the control bits  00   z ,  01   z ,  02   z , . . . ,  31   z  (where “z” indicates an inverted control bit) from ahead and behind the current DAC phase step are used to turn on and off the other two switches in the pair of DAC current paths. 
     Accordingly, at any two current sources controlled by a control bit k on the first level of switches, one of the second-level switches will have the inversion of control bit k+m/2 while the other second-level switch will have the inversion of control bit k−m/2. By way of example, in a 64 weight current DAC (where n=6, 2 n =64 and m=16), 16 current sources always need to be enabled at a given time. Accordingly, if control bit  08  is controlling current sources  16  and  17 , the second level control bits will be  16   z  and  00   z . This look-ahead, look-behind circuit structure effectively decodes the m/2 or rn/2+1 bits to give 2 n  precision from a 2 n-1  decoder logic arrangement. 
     Referring to  FIG. 3 , in accordance with one embodiment of the presently claimed invention, as discussed above, the first 16 current sources are turned on due to the enablement of their two levels of switches. In other words, with the first 16 current sources enabled, control bits  00 ,  01 ,  02 , . . . ,  07  are asserted high, thereby turning on first-level switches T 00 , T 01 , T 02 , . . . and T 15 . Additionally, inverted forms of look-ahead and look-behind control bits are asserted, thereby turning on second-level switches S 00 , S 01 , S 02 , . . . and S 15 . 
     Referring to  FIG. 4 , to enable the next current phase, while still keeping only 16 current sources turned on, the first-level switches T 16  and T 17  are turned on, second-level switch S 00  is turned off and second-level switch S 16  is turned on, while adjacent second-level switch S 17  remains off. Accordingly, current flow through leading current source transistor N 16  is enabled, while current flow through lagging current source transistor N 00  is disabled. 
     Referring to  FIG. 5 , the next current phase is provided by completing enablement of the leading current source transistor pair N 16  and N 17  and disabling the lagging current source transistor pair N 00  and N 01  by turning on leading second-level switch S 17  and turning off lagging first-level switches T 00  and T 01 . 
     Referring to  FIG. 6 , the next current phase is provided by partially enabling the next leading current source transistor pair and partially disabling the lagging current source transistor pair. In other words, first-level switches T 18  and T 19  are turned on by control bit  09 , second-level switch S 18  is turned on by inverted control bit  17   z  and second-level switch S 02  is turned off by inverted control hit  09   z , while second-level switch S 19  remains off and first-level switches T 02  and T 03  remain on. 
     Referring to  FIG. 7 , the next current phase is provided by completing enablement of the leading current source transistor pair N 18  and N 19  and completing disablement of the lagging current source transistor pair N 02  and N 03 . This is done by turning on leading second-level switch S 19  and turning off lagging first-level switches T 02  and T 03 . 
     Referring to  FIG. 8 , as discussed above, the CMOS digital logic is simplified by only requiring decode logic  82  to provide 2 n-1  control bits  00 ,  01 ,  02 , . . . , (n−1), plus inversion circuitry  84  to provide their inverted versions  00   z ,  01   z ,  02   z , . . . , (n−1)z. 
     Referring to  FIG. 9 , integrated circuit (IC) design systems  94  (e.g., work stations or other forms of computers with digital processors) are known that create integrated circuits based on executable instructions stored on a computer readable medium  92 , e.g., including memory such as but not limited to CD-ROM, DVD-ROM, other forms of ROM, RAM, hard drives, distributed memory, or any other suitable computer readable medium. The instructions may be represented by any programming language, including without limitation hardware descriptor language (HDL) or other suitable programming languages. The computer readable medium contains the executable instructions (e.g., computer code) that, when executed by the IC design system  94 , cause an IC fabrication system  96  to produce an IC  98  that includes the devices or circuitry as set forth herein. Accordingly, the devices or circuits described herein may be produced as ICs  98  by such IC design systems  94  executing such instructions. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.

Technology Classification (CPC): 7