Patent Abstract:
A step wave power converter includes a plurality of transformers each configured to receive a Direct Current (DC) voltage from one or more independently generated power sources. Each transformer comprising a primary winding and a secondary winding. A plurality of bridge circuits control different DC voltage inputs from one of the multiple independently generated power sources into the primary windings. One or more processors are configured to use a Phase-Shifted Carrier Pulse Width Modulation (PSCPWM) scheme to operate the bridge circuits in order to produce steps for a step wave Alternating Current (AC) output from the secondary windings.

Full Description:
This application claims priority from provisional application Ser. No. 60/820,942, filed Jul. 31, 2006, which is incorporated by reference in its entirety. U.S. Pat. No. 6,198,178, entitled: Step Wave Power Converter, issued Mar. 6, 2001, is also incorporated in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The disclosure relates generally to power converters. 
     BACKGROUND OF THE INVENTION 
     The general class of multilevel inverters comprises of, among others, a type known as Cascaded Multilevel Inverters. Cascaded inverters have been used in the industry for high power applications. Among the techniques for controlling these cascade converters include a carrier-based Pulse Width Modulation (PWM) scheme known as phase-shifted carrier PWM (PSCPWM). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a single-phase cascaded multilevel inverter. 
         FIG. 2  is a diagram of a single-phase step wave inverter. 
         FIG. 3  is a diagram showing a phase-shifted carrier PWM scheme. 
         FIG. 4  shows an asymmetrically sampled sine-triangle PWM scheme. 
         FIG. 5  shows an output voltage from a cascaded inverter. 
         FIG. 6  shows an output voltage from the step wave inverter shown in  FIG. 2 . 
         FIG. 7  shows the diagram of a 5-level step wave inverter. 
         FIG. 8  shows waveforms from a 5-level step wave inverter 
     
    
    
     DETAILED DESCRIPTION 
     A Phase-Shifted Carrier Pulse Wave Modulation (PSCPWM) scheme is implemented in a step wave power converter for a stand-alone inverter mode of operation. The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings. 
       FIG. 1  shows a single-phase cascaded inverter  10 . The inverter  10  comprises N II-bridges  12  and is capable of producing (2N+1) voltage levels from a Direct Current (DC) power source  14 . Each bridge  12  consists of switching gates S k1 -S k4 , (k=1, 2, . . . N, where k is the k th  bridge and N is the number of bridges) which are controlled in response to signals from a control board (not shown). Each switching gate S k1 -S k4  may be fitted with an antiparallel diode to allow shorting current to flow. The switching gates in certain embodiments could use Insulated Gate Bipolar Transistor (IGBT) modules having four IGBTs or Metal Oxide Semiconductor Field Effect Transistor (MOSFET). However, other type of switching devices could also be used. 
     Activating gates S 13  and S 12  and deactivating gates S 11  and S 14  in Bridge# 1  creates a voltage V o,1 =V DC,1 . Deactivating gates S 13  and S 11  and activating gates S 12  and S 14  in Bridge# 1  shorts V o,1 =0. 
     The cascaded inverter topology requires that all the DC sources  14  be isolated from each other. This isolation feature allows the outputs of the H-bridges  12  to be added together vectorially. This fact is illustrated in  FIG. 1 . At any time instant t, V o,1 (t), V o,2 (t), . . . , V o,N (t) are the output voltages of Bridge # 1 , Bridge# 2 , . . . , Bridge #N, respectively. Since the DC sources  14  are isolated from each other, the inverter output voltage V op (t), is given by the sum of individual H-bridge output voltages and is expressed by the following equation:
 
 V   op ( t )= V   o,1 ( t )+ V   o,2 ( t )+ . . . + V   o,N ( t )  (1)
 
     The schematic of a single-phase step wave power converter  20  with N H-bridges  12  is shown in  FIG. 2 . In general, each H-bridge  12  can be supplied from a separate DC source  14 . This is shown in  FIG. 2  where the DC voltage sources  14  for Bridge # 1 , Bridge# 2 , . . . , Bridge #N are represented by V DC,1 , V DC,2 , . . . , V DC,N  respectively. The inverter  20  also comprises of N transformers  16 . The output of each bridge  12  is tied to the primary winding  16 A of the corresponding transformer  16 . 
     As seen in  FIG. 2 , Bridge # 1 , Bridge # 2 , . . . , Bridge #N are tied to the primary windings  16 A of transformers T 1 , T 2 , . . . , T N  respectively. The outputs  18  of Bridge # 1 , Bridge # 2 , . . . , Bridge #N are designated by V o,1 , V o,2 , V o,N  respectively, and the output voltage at the corresponding transformers  16  are designated by V SEC,1 , V SEC,2 , . . . , V SEC,N , respectively. The secondary windings  16 B of all the transformers  16  are tied in series. The resultant inverter voltage  22 , V op,SW , is the sum of the transformer voltages. If at any given time instant t, the instantaneous transformer voltages are V SEC,1 (t), V SEC,2 (t), . . . , V SEC,N (t) then V op,SW (t) is given by:
 
 V   op,SW ( t )= V   SEC,1 ( t )+ V   SEC,2 ( t )+ . . . + V   SEC,N ( t )  (2)
 
     For both topologies in  FIG. 1  and  FIG. 2 , the output voltages of the individual H-bridges  12  are isolated from each other and thus can be added up to yield the resultant inverter voltage. For this to happen in a cascaded inverter  10  in  FIG. 1 , the DC sources  14  for the individual H-bridges  12  are isolated from each other. This allows the output of one H-bridge  12  to feed into the next H-bridge  12  without causing any circulating currents. 
     In the case of a Step Wave Inverter  20  in  FIG. 2 , the DC sources  14  may or may not be isolated from each other. However, the outputs of the individual H-bridges  12  are isolated from the rest of the bridges in the inverter  20  through the use of transformers  16 . In both the cascaded inverter  10  and the Step Wave Inverter  20 , the outputs  18  of the individual H-bridges  12  are isolated from the rest of the bridges. Since in both the cascaded inverter and the Step Wave Inverter the outputs of the individual H-bridges are isolated from the rest of the bridges, and also because the individual H-bridge outputs get combined to give the resultant inverter voltage, similar PWM techniques can be employed for both the topologies. Applying the same gating signals to control the power transistors in the two topologies will result in inverter waveforms that are identical to each other, differing only in magnitude. This underlying principle is used in this invention whereby a PWM technique commonly used for Cascaded Multilevel inverter is applied for the Step Wave Inverter. 
     PSCPWM Scheme for Cascaded Inverters 
     For the case of operation of one single-phase H-bridge inverter  10  with 3-level naturally sampled modulation, the analytical solution for all the harmonics is known. It has also been shown that for series-connected single-phase bridges some dominant harmonics can be cancelled by appropriately phase-shifting the carriers for the bridges. This modulation process is denoted as phase-shifted carrier PWM, or PSCPWM. 
     The underlying principle of PSCPWM is to retain sinusoidal reference waveforms for the two phase legs of each H-bridge  12  that are phase shifted by 180° and then to phase shift the carriers of each bridge to achieve additional harmonic cancellation around the even carrier multiple groups. 
     To illustrate,  FIG. 3  shows the carrier waveforms  36  and  38  and reference waveforms  30  and  32  for the 2 single-phase H-bridges  12  that are connected in series to form a 5-level cascaded inverter.  FIG. 3  shows two sinusoidal reference waveforms  30  and  32 . Each waveform is assigned for one leg of the H-bridge  12 . For instance, in  FIG. 3  Sine Ref # 1  is used as a reference for Leg a for both the H-bridges in the inverter  10 , and Sine Ref # 2  is used as a reference for Leg b for both the H-bridges  12 . Sine Ref # 1  and Sine Ref # 2  are phase shifted by 180°.  FIG. 3  also shows the carriers, Carrier # 1  and Carrier # 2  that are the carrier waveforms for Bridge  41  and Bridge # 2  respectively. 
     In general, a cascaded inverter  10  with N bridges  12  will have N carriers where Carrier # 1 , Carrier # 2 , . . . , Carrier #N are the carrier waveforms for Bridge # 1 , Bridge # 2 , . . . , Bridge #N respectively. The two reference waveforms  30  and  32  are phase shifted from each other by 180°, and each reference waveform is assigned to one leg of the H-bridges, as discussed for the case of 5-level inverter. As before, Sine Ref # 1  is used as a reference for Leg a of all the N H-bridges in the inverter, and Sine Ref # 2  is used as a reference for Leg b for all the N H-bridges in the inverter. 
     In  FIG. 3 , the carrier frequency is chosen as 5 times the reference waveform frequency for illustration purposes. For actual inverter operation the carrier frequency is typically a few tens to a few hundreds of times the fundamental frequency.  FIG. 3  also shows the normalized amplitudes of the carrier waveforms  36  and  38  and reference waveforms  30  and  32  as 1 and M respectively, where M is the modulation index, and 0≦M≦1. 
     Modulation index M is the ratio of peaks of the carrier and reference waveforms. In other words, for a single H-bridge  12 , a modulation index of M will result in an output voltage with peak of M*V DC , and the fundamental component of this output voltage has a RMS value of M*V DC /√{square root over (2)}. For N cascaded bridge inverters 10 operating with DC voltage V DC , the RMS value of the fundamental component of the output voltage is given by: 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       op 
                       , 
                       
                         
                           CASC 
                           - 
                         
                         ⁢ 
                         RMS 
                       
                     
                   
                   = 
                   
                     
                       N 
                       * 
                       M 
                       * 
                       
                         V 
                         DC 
                       
                     
                     
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     The output voltage waveform also contains harmonics due to switching action of the converter. For sine PWM the dominant harmonics are located near the multiples of the switching frequency. For cascaded bridges, PSCPWM can be used be cancel some of these harmonics. Theoretical analysis has shown that optimum harmonic cancellation is achieved by phase shifting each carrier by (i−1) π/N, where i is the i th  H-bridge and N is the number of series-connected H-bridges. 
     Therefore, for two cascaded H-bridges  12 , the carriers need to be phase shifted by 90°, for three cascaded H-bridges the carriers need to be phase shifted by 60°, and so on. In other words if the carrier waveforms  36  and  38  have periods of ΔT, then for two cascaded H-bridges  12 , the carriers need to be phase shifted by ΔT/4, for three cascaded H-bridges the carriers need to be phase shifted by ΔT/6, and so on. This is illustrated in  FIG. 3  where the carriers  36  and  38  for two cascaded H-bridges  12  are shown phase shifted by ΔT/4. It should be noted here that in order for harmonic cancellation to take place all the DC voltage sources should have the same magnitude, i.e.
 
 V   DC,1   =V   DC,2   = . . . =V   DC,N   =V   DC   (4)
 
       FIG. 3  shows the “naturally sampled” sine-triangle modulation, which is quite difficult to implement in a digital modulation system. The modern popular alternative is to implement the modulation system using a “regular sampled” PWM strategy, where the low-frequency reference waveforms  30  and  32  are sampled and then held constant during each carrier interval. These sampled values are compared against the triangular carrier waveforms  36  and  38  to control the switching process of each phase leg, instead of the sinusoidally varying reference. 
     For triangular carriers  36  and  38 , sampling can be symmetrical or asymmetrical. For symmetrical sampling, the references  30  and  32  are sampled at either the positive or negative peaks of the carriers  36  and  38  and then held constant for the entire carrier interval. For asymmetrical sampling the references  30  and  32  are sampled every half carrier  36  and  38  at both the positive and negative carrier peaks. 
     Sampling the reference signals  30  and  32  produce a stepped waveform which is phase delayed with respect to the original reference waveforms  30  and  32 . For symmetrical sampling, this delay is one half the carrier interval, while for asymmetrical sampling this delay is one quarter the carrier interval. 
     In the digital implementation this phase delay can be compensated by phase advancing the reference waveforms  30  and  32  by the appropriate time interval. The most common implementation for a digital PWM controller is using a digital controller around a microcontroller or a Digital Signal Processor (DSP). Good harmonic performance may be achieved by using 3-level asymmetrical regular sampled PWM for each H-bridge  12  in the cascaded inverter  10 . The waveform synthesis for the cascaded converter  10  and step wave converter  20  may be similar. Therefore the 3-level asymmetrical regular sampled PWM is used for also implementing PSCPWM for the step wave inverter. 
       FIG. 4  shows the switching waveforms for both legs of an H-bridge  12 , selected as Bridge # 1  in  FIG. 1  for illustration.  FIG. 4  shows two half-periods  36 A and  36 B of the carrier wave  36 , labeled Interval  1  and Interval  2  respectively. 
     The reference waveform samples for Leg a corresponding to Interval  1  and Interval  2  are Ref_Val  1   a  and Ref_Val  2   a  respectively, and the reference waveform samples for Leg b corresponding to Interval  1  and Interval  2  are Ref_Val  1   b  and Ref_Val  2   b  respectively. The reference samples are obtained after adjusting for the one quarter of the carrier period introduced due to sampling. 
     As can be seen, the switched waveforms for each leg are obtained by comparing the carrier wave  36  with the reference sample values. Each phase leg of the inverter switches to the upper DC rail (V DC )  14 A when the reference value Ref_Val  1   a , Ref_Val  2   a , Ref_Val  1   b , or Ref_Val  2   b  exceeds the carrier wave  36 , and switches to the lower DC rail ( 0 )  14 B when the reference value falls below the carrier. 
     Following this scheme, the control signals for the power transistors can be generated. For the H-bridge under example (Bridge # 1  of the cascaded inverter shown in  FIG. 1 ) the states of the switches in the H-bridge corresponding to the switching waveforms are as indicated in  FIG. 4 . 
     Waveform  50 A shows the output voltage of Leg b at node  12 B. During Interval  1  the reference value  1  Ref_Val  1   b  exceeds the carrier waveform  36 A for the time interval t 0 -t 2 . Accordingly, the output voltage at node  12 B is set to +V DC  during the time interval t o -t 2  by activating switch S 13  (i.e. turning the switch ON) and deactivating switch S 14  (i.e. turning the switch OFF). During time interval t 2 -t 3  the carrier waveform  36 A exceeds the reference value Ref_Val  1   b . Accordingly, the output voltage at node  12 B is set to 0 during the time interval t 2 -t 3  by activating switch S 14  (i.e. turning the switch ON) and deactivating switch S 13  (i.e. turning the switch OFF). During Interval  2  carrier waveform  36 B exceeds the reference value Ref_Val  2   b  for the time interval t 3 -t 4 . Accordingly, the output voltage is set to 0 during the time interval t 3 -t 4  by activating switch S 14  and deactivating switch S 13  During time interval t 4 -t 6  the reference value Ref_Val  2   b  exceeds the carrier waveform  36 B. Accordingly, the output voltage is set to +V DC  during the time interval t 4 -t 6  by activating switch S 13  and deactivating switch S 14 . 
     Waveform  50 B shows the output voltage of Leg a at node  12 A. During Interval  1  the reference value Ref_Val  1   a  exceeds the carrier waveform  36 A for the time interval t 0 -t 1 . Accordingly, the output voltage at node  12 A is set to +V DC  during the time interval t 0 -t 1  by activating switch S 11  and deactivating switch S 12 . During time interval t 1 -t 3  the carrier waveform  36 A exceeds the reference value Ref_Val  1   a . Accordingly, the output voltage at node  12 A is set to 0 during the time interval t 1 -t 3  by activating switch S 12  and deactivating switch S 11 . During Interval  2  carrier waveform  36 B exceeds the reference value Ref_Val  2   a  for the time interval t 3 -t 5 . Accordingly, the output voltage is set to 0 during the time interval t 3 -t 5  by activating switch S 12  and deactivating switch S 11  During time interval t 5 -t 6  the reference value Ref_Val  2   a  exceeds the carrier waveform  36 B. Accordingly, the output voltage is set to +V DC  during the time interval t 5 -t 6  by activating switch S 11  and deactivating switch S 12 . 
     The combination of waveforms  50 A and  50 B produce waveform  50 C where the output of Bridge # 1  (V op,1 ) is equal to 0 during the time interval t 0 -t 1 , moves to V DC  during the time interval t 1 -t 2 , moves to 0 during the time interval t 2 -t 4 , moves to V DC  during the time interval t 4 -t 5 , moves to 0 during the time interval t 5 -t 6  etc. 
       FIG. 5  shows a sketch of the cascaded inverter output voltage, V op,CASC  (before any filtering is performed. It can be seen that the resulting inverter voltage comprises of (2N+1) levels, and each level has the magnitude V DC . 
     Using PSCPWM in Step Wave Conversion 
     The PSCPWM is selected for the single-phase configuration of step wave inverter for stand-alone application whereby the converter performs DC-AC power conversion to supply a local load. The details of implementation of PSCPWM for a 5-level step wave inverter given below show that the inherent transformer leakage inductance can be used to eliminate external inductance and filter the output voltage. 
     Referring again to  FIG. 2 , the PSCPWM described above for cascaded inverter  10  in  FIG. 1  can also be used with the step wave power converter  20  shown in  FIG. 2 . As mentioned for the case of the cascaded inverter, the desired harmonic elimination can be attained when all the DC voltage sources  14  have the same magnitude. This condition has been expressed earlier by Eq. 4. In practice this condition is directly achieved by tying all the H-bridges  12  to the same DC source  14  with magnitude, say V DC . 
     Any DC voltage source  12  can be used e.g. a battery bank, a photovoltaic array, a fuel cell etc. The N transformers  16  that are part of the inverter  20  are identical, with the primary to secondary winding ratio 1:R. Thus a pulse of V DC  on the primary  16 A of any transformer  16  will result in a voltage pulse of R*V DC  on the secondary winding  16 B of the transformer  16 . 
     In applying the PSCPWM technique to the step wave inverter  20 , the sine-triangle modulation and the generation of gating signals for the power transistors is the same as the cascaded inverter. As mentioned previously, the 3-level asymmetrical regular sampled PWM provides good harmonic performance for implementing PSCPWM. 
     A sketch of the resulting inverter voltage before any filtering is performed is shown in  FIG. 6 . As with the cascaded inverter, the inverter voltage comprises of 2N+1 levels. A comparison of  FIG. 5  and  FIG. 6  shows that there is a difference in the magnitude of each level. For the step wave inverter the presence of transformers results in each level being of the magnitude R*V DC . 
     For cascaded inverter  10  ( FIG. 1 ) operating with a modulation index M the expression for the RMS value of the fundamental component of the output voltage has been given in Eq. 3. Following the discussion above, for a step wave inverter  20  operating with a modulation index M the expression for the RMS value of the fundamental component of the output voltage is given by: 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       op 
                       , 
                       
                         
                           SW 
                           - 
                         
                         ⁢ 
                         RMS 
                       
                     
                   
                   = 
                   
                     
                       N 
                       * 
                       M 
                       * 
                       
                         V 
                         DC 
                       
                       * 
                       R 
                     
                     
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     The PSCPWM scheme was tested with a 3-level asymmetrical regular sampling on a prototype single-phase step wave inverter  20 . The prototype was designed for operation with high-density Li-ion battery pack. The AC output  22  of the inverter  20  was 120V, 60 Hz, 2.4 kW continuous output power. The inverter  20  can be designed for 5-level operation i.e. with 2H-bridges and 2 transformers. One implementation used DC and AC operating voltages resulting in transformer voltage ratio of 1:1.43. The carrier frequency was chosen as 4500 Hz, thus yielding a carrier to fundamental ratio of 4500/60=75. 
     A digital implementation of PSCPWM is carried out as shown in  FIG. 7  using a digital signal processor (DSP)  70 . The two reference waveform tables can be stored in on-chip memory as look-up tables. The PWM signals for controlling the switches in the inverter can be generated by encoding the asymmetrically sampled sine-triangle PWM scheme illustrated in  FIG. 4  that has already been described above. In  FIG. 7 , the PWM signals for Leg a and Leg b for Bridge# 1 are labeled as PWM 1   a  and PWM 1   b  respectively and the PWM signals for Leg a and Leg b for Bridge#  2  are labeled as PWM 2   a  and PWM 2   b  respectively.  FIG. 7  also shows the block for deadband circuit  61  for generating control signals for switches, and the block for driver circuit  62  for the necessary gate drive. 
       FIG. 8  shows the load voltage and load current for the 5-level step wave inverter for a non-linear load comprising of 2 computers and a resistive load bank. For stand-alone inverter operation it is expected that the inverter  20  will supply a near-sinusoidal voltage to an AC load. The limits for the different voltage harmonics are specified in IEEE 519-1992 standard. 
     In order to attain a sine-wave quality and reduce the harmonic content in the output voltage for all stand-alone inverters, some sort of filtering is applied in the output  22  in  FIG. 2 . This kind of filtering can be achieved by some combination of inductors and capacitors.  FIG. 2  shows a simple LC-filter  80 ,  82  comprised of the components L f  and C f  and a load  84  at the output  22  of the step wave inverter  20 . 
     The size and values of the filter components  80  and  82  depend upon the magnitude of harmonics present in the output voltage and the level of attenuation desired. A high harmonic content in the output voltage  22  results in large L f  and C f . The superior harmonic performance of the PSCPWM scheme results in output voltage that inherently has a low harmonic content. This ensures that the filter components L f  and C f  are small. 
     Furthermore, from  FIG. 2 , it can be seen that the leakage inductance of the transformers  16  is in series with the filter inductance  82 . If each transformer  16  has an equivalent leakage inductance of L σ  referred to the secondary side  16 B of the transformers  16 , then for N transformers  16  the total filter inductance is given by:
 
 L   filter   =L   f +( N*L   σ )
 
     Thus, it can be seen that the transformer leakage inductance contributes to the total filter inductance. This can be used to reduce the size of the external inductance, L f . With a proper choice of the filter capacitance, C f , it is possible to eliminate L f . This useful feature is demonstrated on a prototype step wave inverter with PSCPWM. The leakage inductance of each transformer is measured to be 60 μH, giving a total of 120 μH for the 2 transformers  16 . It is found that using only the leakage inductance of the transformers and a 15 μF filter capacitor gives excellent power quality for the output voltage for different kinds of loads. As can be seen in  FIG. 6  the load voltage is nearly sinusoidal and meets all the limits for harmonics specified in IEEE 519-1992. 
     The system described above can use dedicated processor systems, micro controllers, programmable logic devices, or microprocessors that perform some or all of the operations. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. 
     For the sake of convenience, the operations are described as various interconnected functional blocks or distinct software modules. This is not necessary, however, and there may be cases where these functional blocks or modules are equivalently aggregated into a single logic device, program or operation with unclear boundaries. In any event, the functional blocks and software modules or features of the flexible interface can be implemented by themselves, or in combination with other operations in either hardware or software. 
     Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention may be modified in arrangement and detail without departing from such principles. I claim all modifications and variation coming within the spirit and scope of the following claims.

Technology Classification (CPC): 8