Patent Abstract:
A current measurement circuit for measuring a current is provided. The current measurement circuit includes a current integrating unit with a capacitor array, a comparator coupled to the current integrating unit, and a control unit coupled to the comparator and the current integrating unit. The current integrating unit integrates the current on the capacitor array to obtain an input voltage. The comparator compares the input voltage with a specific voltage to generate a compare output. The control unit generates a control signal to apply to the capacitor array of the current integrating unit according to the compare output. A magnitude of the current is obtained according to the control signal and the capacitance of the capacitor array.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/217,904, filed on Jun. 5, 2009, the entirety of which is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a current measurement circuit, and more particularly, to a current measurement circuit which measures current over a wide dynamic range. 
         [0004]    2. Description of the Related Art 
         [0005]    Current measuring circuits are required in many devices.  FIG. 1  shows a conventional current measurement circuit  100  disclosed in U.S. Publication 2008/0303507, which may be applied in thin film applications such as active matrix displays. The current measurement circuit  100  comprises a charge integrating circuit  2 , a comparator circuit  4  and a logic circuit  6 . The charge integrating circuit  2  integrates a charge from a current  10  to be measured and applies a change in voltage to a comparator circuit  4 . The comparator circuit  4  compares the input voltage  12  with a threshold voltage level and provides an output  14  responsive thereto to the logic circuit  6 . The logic circuit  6  generates a feedback signal  16  according to the comparator output  14  and provides the feedback signal  16  to the charge integrating circuit  2 . Then, the charge integrating circuit  2  integrates a charge from the received feedback signal  16 , which is opposite to the integrated charge from the current  10 . 
         [0006]    In  FIG. 1 , an integration time for integrating the current  10  is proportional to the current  10  being measured. For example, when a small current is being measured, the integration time is long and vice versa. A relatively long setup period is required, which is used to accurately set the input voltage  12  of the comparator  4  at a threshold value. 
         [0007]    Furthermore, in  FIG. 1 , a feedback capacitor C is coupled to and between the input of the comparator circuit  4  and the output of the logic circuit  6 . During a measurement period, the voltage applied to the feedback capacitor C by the logic circuit  6  is stepped, which will produce a step-up voltage at the input of the comparator circuit  4 . Ideally, the voltage at the input of the comparator circuit  4  should be constant so that the current  10  to be measured is independent of the resistance of the current source  60  and transient currents which can occur in thin film devices due to sudden changes in a bias voltage may be prevented. 
         [0008]    Therefore, a current measurement circuit for decreasing the duration of the initial integration period (setup period), reducing the difference in measurement time for large and small currents and reducing the step-up voltage at the input of the comparator circuit is desired. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    A current measurement circuit and a measuring method for measuring a current are provided. An exemplary embodiment of a current measurement circuit for measuring a current comprises a current integrating unit with a capacitor array, a comparator coupled to the current integrating unit, and a control unit coupled to the comparator and the current integrating unit. The current integrating unit integrates the current on the capacitor array to obtain an input voltage. The comparator compares the input voltage with a specific voltage to generate a compare output. The control unit generates a control signal which is applied to the capacitor array of the current integrating unit according to the compare output. A magnitude of the current is obtained according to the control signal and the capacitance of the capacitor array. 
         [0010]    Furthermore, an exemplary embodiment of a measuring method for measuring a current is provided. The current is integrated on a capacitor array of a current integrating unit to obtain an input voltage. The input voltage is compared with a specific voltage to generate a compare output by a comparator. A control signal is generated to apply to the capacitor array of the current integrating unit according to the compare output by a control unit. A magnitude of the current is obtained according to the control signal and the capacitance of the capacitor array by the control unit. 
         [0011]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0013]      FIG. 1  shows a conventional current measurement circuit; 
           [0014]      FIG. 2  shows a current measurement circuit for measuring a current according to an embodiment of the invention; 
           [0015]      FIG. 3  shows an example of waveforms illustrating the signals of the current measurement circuit in  FIG. 2 ; 
           [0016]      FIG. 4  shows another example of waveforms illustrating the switching of the signal received by the control unit and the codes of the control signal applied to the capacitors of  FIG. 2 ; 
           [0017]      FIG. 5  shows another example of waveforms illustrating the switching of the signal received by the control unit and the codes of the control signal of  FIG. 2 ; and 
           [0018]      FIG. 6  shows another example of waveforms illustrating the switching of the signal received by the control unit and the codes of the control signal of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0020]      FIG. 2  shows a current measurement circuit  200  for measuring a current I according to an embodiment of the invention. The current I to be measured is provided by a current source  210 . In the embodiment, the current source  210  is a photo diode. The current measurement circuit  200  comprises a comparator  220 , a Schmitt inverter  230  with hysteresis, a control unit  240  and a current integrating unit  250 . The comparator  220  comprises three series connected inverters  221 ,  222  and  223 , a capacitor C 5  coupled between the inverters  221  and  222 , and a capacitor C 6  coupled between the inverts  222  and  223 . Furthermore, the comparator  220  further comprises three offset correction switches SW 1 , SW 2  and SW 3 , each connected with the corresponding inverter in parallel. For example, the switch SW 1  is connected with the inverter  221  in parallel, which comprises two transistors connected in series. In one embodiment, the comparator  220  only comprises a single inverter having an offset correction switch in order to reduce size for the current measurement circuit  200 . In addition, the comparator  220  further comprises two inverters  224  and  225  connected in series. The inverter  224  generates a signal  51  to switch the switches SW 1 , SW 2  and SW 3  according to a reset signal S RESET , and the inverter  225  generates a signal S 2  according to the signal  51 . When the switches SW 1 , SW 2  and SW 3  are turned off by the signal  51  at the end of a reset state, charge may be injected into each input terminal of the inverters  221 ,  222  and  223 . In the meantime, the transistors controlled by the signal S 2  are used to provide compensation for the charge injection. The Schmitt inverter  230  is coupled to and between the comparator  220  and the control unit  240  and generates a signal S 4  to the control unit  240  according to an output signal S 3  of the comparator  220 . In the current measurement circuit  200 , the Schmitt inverter  230  is used to prevent occurrence of an undefined signal S 4  state during a reset state. The current integrating unit  250  comprises a capacitor array comprising a plurality of capacitors C 1 , C 2 , C 3  and C 4 , each having one terminal coupled to an input node N in  of the comparator  220  and another terminal driven by a control signal B[3:0] derived from the control unit  240 . The control signal B[3:0] is a multi-bit binary signal which is composed of four bit signals B[ 3 ], B[ 2 ], B[ 1 ] and B[ 0 ], wherein the bit signal B[ 0 ] is a Least Significant Bit (LSB) and the bit signal B[ 3 ] is a Most Significant Bit (MSB). In addition, the current integrating unit  250  further comprises four buffers  252 ,  254 ,  256  and  258 , wherein each buffer formed by two inverters connected in series is coupled to the corresponding capacitor and is used to buffer the bit signal before the bit signal is applied to the corresponding capacitor. In the embodiment, capacitances of the capacitors C 1 , C 2 , C 3  and C 4  are binary weighted, such as C 1 :C 2 :C 3 :C 4 =1:2:4:8. 
         [0021]      FIG. 3  shows an example of waveforms illustrating the signals of the current measurement circuit  200  in  FIG. 2 . In  FIG. 3 , the value of the control signal B[3:0] is represented by a decimal format. A signal V IN  represents a voltage of the input node N in  for the comparator  220 . At the start of the measurement process, the current measurement circuit  200  is reset by setting the signal S RESET  to low during a reset state. During the reset state, the switches SW 1 , SW 2  and SW 3  which are separately connected between the input and output terminals of the inverters  221 ,  222  and  223  in the comparator  220  are turned on. Thus, the input and output voltages of the inverters  221 ,  222  and  223  may become equal to the threshold voltages of the inverters  221 ,  222  and  223 , respectively. In the embodiment, the threshold voltages of the inverters  221 ,  222  and  223  are equal in order to simplify description. Also, the voltage of the signal V IN  is set equal to the threshold voltage of the inverter  221  of the comparator  220  during the reset state. Furthermore, the control signal B[3:0] applied to the capacitors C 1 , C 2 , C 3  and C 4  are set to a initial value during the reset state. The initial value is chosen according to the polarity of the current I. In  FIG. 3 , it is assumed that a negative current is being measured which means that the capacitors C 1 , C 2 , C 3  and C 4  must supply a positive charge flow at the input node N in  and therefore the control signal B[3:0] initially has a low voltage. 
         [0022]    When the signal S RESET  rises to a high level, the current measurement circuit  200  enters a measurement state to integrate the current I on an equivalent capacitance at the input node N in , wherein the equivalent capacitance is obtained according to the capacitances of the capacitors C 1 , C 2 , C 3  and C 4 . Thus, the voltage of the signal V IN  starts to fall and the signal S 4  of the Schmitt inverter  230  switches to a low level when the signal V IN  falls below the threshold voltage of the comparator  220 . Next, the low state of the signal S 4  is detected by the control unit  240  which in response changes/increases the control signal B[3:0] causing a positive voltage step-up at the input node N in  which raises the voltage at the input of the comparator  220  above the threshold voltage and causes the signal S 4  to return to a high level. After increasing the control signal B[3:0], the current I continues to be integrated at the input node N in  and the voltage of the signal V IN  therefore falls. If the voltage of the signal V IN  again falls below the threshold voltage of the comparator  220 , the signal S 4  would eventually become low again and then the control unit  240  would increase the control signal B[3:0] by one LSB. As shown in  FIG. 3 , the control unit  240  increases the control signal B[3:0] by one LSB at the start of every integration period. For example, the control unit  240  sets the control signal B[3:0] to “1” at the start of an integration period TP 1 , and then the control unit  240  sets the control signal B[3:0] to “2” at the start of an integration period TP 2 . During the measurement state, the process of detecting the switching of the signal S 4  and stepping-up of the voltage of the level of the signal V IN  applied to the capacitors C 1 , C 2 , C 3  and C 4  is continued until either the measurement state is completed, i.e. a certain measurement time is reached, or the maximum code of the control signal B[3:0] is reached. This process of changing the voltages applied to the capacitors C 1 , C 2 , C 3  and C 4  in order to compensate for the charge being integrated at the input node N in  is repeated throughout the measurement state. At the end of the measurement state, a measurement result indicates the magnitude of the current I which can be generated by the control unit  240  according to the changes in the level of the voltage applied to the capacitors C 1 , C 2 , C 3  and C 4  and the time periods at which the signal S 4  is switched. In  FIG. 3 , the value of control signal B[3:0] and time intervals of the integration periods TP 1  and TP 2  are used as an example for description, and does not limit the invention. 
         [0023]    Specifically, a magnitude of the current I can be calculated by the control unit  240  according to the code of the control signal B[3:0], the capacitances of the capacitors C 1 , C 2 , C 3  and C 4  and the time periods at which the signal S 4  switches.  FIG. 4  shows another example of waveforms illustrating the switching of the signal S 4  and the codes of the control signal B[3:0] applied to the capacitors C 1 , C 2 , C 3  and C 4  of  FIG. 2 . Referring to  FIG. 2  and  FIG. 4  together, first, the code of the control signal B[3:0] is set to F 0  and the switches SW 1 , SW 2  and SW 3  are turned on during a reset period TP RESET . Thus, the voltage of the signal V IN  is set close to the threshold voltage of the comparator  220 . Next, at the start of an integration period TP 1 , the code of the control signal B[3:0] is changed to a new value F 1 . The chosen value of F 1  must ensure that following the reset period TP RESET  the signal S 4  initially rises to a high level. When the voltage of the signal V IN  has a value equal to the threshold voltage of the comparator  220  due to a high to low transition of the signal V IN , the signal S 4  switches to a low level. The integration of the current I between the switching processes, for example between times t 1  and t 2 , must therefore be equal to the charge injected onto or removed from the input node N in  by changing the control signal B[3:0]. 
         [0024]    If the smallest capacitor in the binary weighted capacitor array formed by the capacitors C 1 , C 2 , C 3  and C 4  has a value C, the amount of charge injected onto the input node N in  will be (F 2 −F 1 )×C×V when the code of the control signal B[3:0] is changed from F 1  to F 2 , where V represents the magnitude of the logic voltage of the control signal B[3:0] and (F 2 −F 1 )×C represents the effective capacitance to which the change in voltage was applied. Therefore, the average current I integrated during the integration periods from t 1  to t 5  can be calculated as 
         [0000]        I =( F 5 −F 1)× C×V /( t 5 −t 1). 
         [0000]    It is to be noted that, the integration period TP 1  is not used in the calculation of the current I for the following reason. When the signal S 4  switches to a low level at time t 1 , t 2 , t 3  and so on, the voltage of the signal V IN  has a particular value equal to the threshold voltage of the comparator  220 . At time t 0 , the voltage of the signal V IN  is below the threshold voltage of the comparator  220  but the actual value of the signal V IN  is not known. Therefore, using the integration period TP 1  to calculate the current I may introduce errors into the calculated result. Specifically, the integration period TP 1  represents a setup period of the current measurement circuit  200 . 
         [0025]    The threshold voltage of the comparator  220  in  FIG. 2  depends on charge injection effects which occur at the end of the reset period TP RESET , which is not easily predicted. Thus, it may be necessary to determine the value of F 1  by a process in which the code of the control signal B[3:0] is stepped-up until the signal S 4  switches to a high level, as shown in  FIG. 5 .  FIG. 5  shows another example of waveforms illustrating the switching of the signal S 4  and the codes of the control signal B[3:0] of  FIG. 2 . Referring to  FIG. 2  and  FIG. 5  together, the signal S 4  is in a low state at the end of the reset period TP RESET . The code of the control signal B[3:0] is increased and then the signal S 4  is monitored by the control unit  240 . The measurement begins when the signal S 4  is at a high level, but if the signal S 4  is still at a low level then the code of the control signal B[3:0] is increased once again. This process of increasing the code of the control signal B[3:0] and monitoring the signal S 4  is repeated until the signal S 4  rises to a high level (e.g. at time t 6 ). The integration period TP 1  represents the setup period for the current measurement circuit  200 . 
         [0026]      FIG. 6  shows another example of waveforms illustrating the switching of the signal S 4  and the codes of the control signal B[3:0] of  FIG. 2 . The signal S 4  rises to a high level at the end of the reset period TP RESET  even without the code of the control signal B[3:0] being changed. Therefore, the code of the control signal B[3:0] is first decreased until the signal S 4  switches to a low level, and then the code of the control signal B[3:0] is increased so as to set the signal S 4  to a high level. 
         [0027]    Referring to  FIG. 2 , the first code of the control signal B[3:0] following reset (i.e. F 1  of  FIGS. 3-6 ) may be periodically determined rather than during each measurement. In addition, a time delay from switching the code of the control signal B[3:0] to the signal S 4  changing must be taken into account in the control unit  240  by inserting an appropriate delay between changing the control signal B[3:0] and subsequent monitoring of the signal S 4 . When the quantity of the current I is small, the control unit  240  may increase or decrease the code of the control signal B[3:0] by one LSB during an integration period. However, when the quantity of the current I is large, the control unit  240  may increase or decrease the code of the control signal B[3:0] by a larger increment. Therefore, in order to measure large-sized currents, the charge corresponding to each transition in the code of the control signal B[3:0] must be increased. For the control signal B[3:0], larger code steps may also be needed during the setup period when large currents are being measured. 
         [0028]    If the capacitors C 1 , C 2 , C 3  and C 4  are not switched simultaneously, voltage spikes may be generated in the signal V IN . The polarity of the voltage spikes depend on the timing of the switching of the individual bits of the control signal B[3:0] applied to the capacitors C 1 , C 2 , C 3  and C 4 . The polarity of the spikes may determine whether the signal S 4  is prematurely switched. For example, by delaying the rising edges of the signals applied to the capacitors C 1 , C 2 , C 3  and C 4  compared to the falling edges, the voltage spikes may have a negative polarity so as to avoid premature switching of the signal S 4 . 
         [0029]    It is to be noted that, the operation of the current measurement circuit  200  described above is for measurement of a negative current. The operation of the current measurement circuit  200  depends on the polarity or sign of the current I. For example, the current measurement circuit  200  can be used to measure a positive current, but the control signal applied to the capacitors C 1 , C 2 , C 3  and C 4  and the signal S 4  must have inverted logic. Furthermore, the changes in voltage applied to the capacitors C 1 , C 2 , C 3  and C 4  by the control unit  240  during a measurement state are arranged to compensate for charges associated with the current I which is integrated on the capacitance at the input node N in , so that the voltage of the signal V IN  is maintained at a voltage level that is close to the threshold voltage of the comparator  220 . 
         [0030]    According to the embodiments of the invention, the current measurement circuit is able to correct for variation in the threshold voltage of the comparator so as to minimize the duration of the initial integration period (i.e. setup period). Furthermore, by using a plurality of feedback capacitors with lower values, the magnitude of the voltage step-up at the input of the current measurement circuit may be reduced. Therefore, the situation where the input voltage is constant, is better approximated. 
         [0031]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 6