Patent Abstract:
An amplifier circuit includes a circuit input, and a circuit output. An inverter, including first and second MOS transistors is connected between first and second supply voltages, and has an inverter input connected to the circuit input, and an inverter output, which provides an inverter output current corresponding to a circuit input voltage. A first resistive element comprises a third MOS transistor and a fourth MOS transistor of opposite conductivity types, and each having their gate and drain terminals connected to the inverter output and the circuit output, and having their respective source terminals connected to respective ones of the first and second supply voltages. A second resistive element includes a fifth MOS transistor and a sixth MOS transistor of opposite conductivity types, and each having its drain-source path connected between the circuit output and the circuit input, and having its gate connected to a respective voltage source.

Full Description:
This application is a continuation of application Ser. No. 09/590,364, filed on Jun. 9, 2000 now abandoned. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     This invention relates to an amplifier circuit, and in particular to an amplifier which is suitable for use at radio frequencies, and is suitable for integration using CMOS fabrication techniques, with low supply voltages. As such, the device is suitable for use in hand-held portable radio devices, such as mobile phones, for example. 
     BACKGROUND OF THE INVENTION 
     Amplifier circuits, such as those shown in FIG. 1, are known which include a first pair of CMOS transistors  16 ,  18  in an inverter structure  12 , with the inverter output  20  supplied to the amplifier output terminal  22 . The input voltage  14 , supplied to the inverter input, produces an output current which depends on the transconductances of the transistors  16 ,  18 . The amplifier output terminal is also connected to the gate terminals and to the drain terminals of two further CMOS transistors  24 ,  26 . The output current is drawn through these transistors  24 ,  26 , which act as resistors, in that the current through their drains depends on their gate voltages. The gate voltages, and hence the amplifier output  22 , therefore depend on the output current. 
     As a result, by designing the circuit such that the first pair of transistors are larger than the second pair, an inverting amplifier having a gain greater than unity can be obtained. 
     FIG. 2 shows a small signal model for such a circuit, in which transistors  24  and  26  have each been represented by their equivalent resistances. 
     The current i T  flowing from the output to the drain of each of the transistors  16 ,  18  is given by: 
     
       
           i   T   =g   m16   ·V   i   +g   m18   ·V   i   =V   i ( g   m16   +g   m18 ) 
       
     
     Thus,            V   o     =             -   1         g     m   24       +     g     m   26           -       V   i          (       g     m   16       +     g     m   18         )              
     ∴     A   v       =         V   o       V   i       =     -     (         g     m   16       +     g     m   18             g     m   24       +     g     m   26           )             ,                          
     where A v  is the voltage gain of the circuit. 
     Normally, the devices are chosen such that g m16 =g m18 , and g m24 =g m26  and set such that g m16 =K.g m26    
     Thus,            A   v     =       -       g     m   16         g     m   24           =     -   K                            where   ,       g   m     =       2      β                   I   D           ,                          
     I D  Being the current through a device, so          A   v     =           I     D   16         I     D   24           =   K                            
     The ratio of currents between transistors  16 / 18  and transistors  24 / 26  is set to            I     D     16   /   18           I     D     24   /   26           =     K   2                            
     For a low-noise amplifier, there are two requirements which are of particular note here. Firstly, it is preferable to match the signal source impedance to the amplifier input impedance, to provide optimum power transfer to the output. Secondly, it is necessary to have a good noise figure, for example of 2 dB or less. However, matching the signal source impedance to the amplifier input impedance produces a noise figure of at least 3 dB, which means that it is not possible to produce an acceptable noise performance. 
     SUMMARY OF THE INVENTION 
     The present invention provides an amplifier circuit which is suitable for integration using CMOS techniques, and for use at radio frequencies, while providing good performance in terms of its noise figure. 
     According to a first aspect of the present invention, there is provided an amplifier circuit, comprising: 
     a circuit input, and a circuit output; 
     an inverter connected between first and second supply voltages, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage; 
     a first resistive element connected to the inverter output and to the circuit output, and providing a voltage output corresponding to the inverter output current; and 
     a second resistive element providing a feedback resistance between the circuit output and the circuit input, the feedback resistance being adjustable such that the active input impedance of the amplifier can be set to any required value. 
     According to another aspect of the invention, there is provided an amplifier circuit, comprising: 
     a circuit input, and a circuit output; 
     an inverter, comprising first and second MOS transistors ( 16 , 18 ) connected between first and second supply voltages, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage; 
     a first resistive element, comprising at least a third MOS transistor ( 24  or  26 ), connected to the inverter output and to the circuit output, and providing a voltage output corresponding to the inverter output current; and 
     a second resistive element, comprising at least a fourth MOS transistor ( 30  or  32 ), having its drain and source terminals connected between the circuit output and the circuit input, and having its gate connected to a voltage source to have a voltage applied thereto such that the fourth MOS transistor operates in its linear region. 
     According to another aspect of the invention, there is provided an amplifier circuit, comprising: 
     a circuit input, and a circuit output; 
     an inverter, comprising first and second MOS transistors ( 16 ,  18 ) connected between first and second supply voltages, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage; and 
     a resistive element comprising third and fourth MOS transistor ( 30 , 32 ), being of opposite conductivity types, each having its drain source path connected between the circuit output and the circuit input, and having its gate connected to a respective voltage source to have a voltage applied thereto such that it operates in its linear region. 
     According to another aspect of the invention, there is provided an amplifier circuit, comprising: 
     a circuit input, and a circuit output; 
     an inverter, comprising at least a first MOS transistor ( 16  or  18 ) connected between the circuit output and a first supply voltage, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage; 
     a first resistive element, comprising a second MOS transistor ( 24  or  26 ), having its gate and drain connected to the inverter output and to the circuit output, and its source connected to the first supply voltage, providing a voltage output corresponding to the inverter output current; 
     a second resistive element, comprising third and fourth MOS transistors ( 30 , 32 ), the third and fourth transistors being of opposite conductivity types, and each having its drain-source path connected between the circuit output and the circuit input, and having its gate connected to a respective voltage source; and, 
     a third resistive element connected between the circuit output and a second supply voltage. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: 
     FIG. 1 shows an amplifier circuit in accordance with the prior art; 
     FIG. 2 shows a small signal model for the circuit of FIG. 1; 
     FIG. 3 is a circuit diagram of an amplifier circuit according to a first aspect Of the present invention; 
     FIG. 4 shows a small signal model of the circuit of FIG. 3; 
     FIG. 5 represents the input resistance of FIG. 3; 
     FIG. 6 represents the circuit of FIG. 1 for noise analysis; 
     FIG. 7 represents the noise of the circuit of FIG. 1; 
     FIG. 8 represents the noise factor of the circuit of FIG. 1; 
     FIG. 9 represents the circuit of FIG. 3 for noise analysis; 
     FIG. 10 represents the noise factor of FIG. 3; 
     FIG. 11 is a circuit diagram of an amplifier circuit according to another aspect of the present invention; 
     FIG. 12 is a circuit diagram of an amplifier circuit according to another aspect of the present invention; 
     FIG. 13 is a circuit diagram of an amplifier circuit according to another aspect of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 shows an amplifier circuit in accordance with the invention. 
     The circuit is based around an amplifier  10  of known type as mentioned above in relation to FIG. 1, which includes an inverter  12 . A circuit input  14  is connected to the gate terminals of a first PMOS transistor  16  and a second NMOS transistor  18 . The PMOS transistor  16  has its source terminal connected to a positive supply voltage Vdd, and its drain terminal connected to an inverter output  20 . The NMOS transistor  18  has its source terminal connected to a negative supply voltage Vss, and its drain terminal connected to the inverter output  20 . 
     The inverter output terminal  20  is also connected to the circuit output  22 . A third PMOS transistor  24  has its source terminal connected to a positive supply voltage Vdd, and its gate and drain terminals connected to the inverter output  20 . A fourth NMOS transistor  26  has its source terminal connected to a negative supply voltage Vss, and its gate and drain terminals connected to the inverter output  20 . 
     Thus, an input voltage applied at the input terminal  14  produces a corresponding current flowing at the inverter output  20 , the size of which depends on the transconductances of the first and second transistors  16 ,  18 . 
     The currents in the drains of the third and fourth transistors  24 ,  26 , conversely, depend on the gate voltages of those transistors. The gate voltages of these transistors, and hence also the circuit output voltage at the output terminal  22 , therefore takes a value which produces the required currents. 
     If the third and fourth transistors  24 ,  26  are matched with the first and second transistors  16 ,  18 , the gate voltage of the third and fourth transistors (that is, the circuit output voltage) is equal to the gate voltage of the first and second transistors (that is, the circuit input voltage) and so the amplifier circuit  10  inverts the input with unity gain. 
     If, by contrast, the third and fourth transistors  24 ,  26  are smaller than the first and second transistors  16 ,  18  by a particular factor, then the currents in the third and fourth transistors are correspondingly smaller than those in the first and second transistors. This produces a given ratio in the transconductance between the first and second, and the transconductance of the third and fourth transistors, and the amplifier gain has the same factor. 
     The third and fourth transistors act as a resistive element, producing an output voltage which depends on the current supplied thereto. 
     The circuit of FIG. 3 also includes a feedback section  28 , which includes a fifth NMOS transistor  30  and a sixth PMOS transistor  32 . The gate of the fifth NMOS transistor  30  is connected to a control voltage P 1  at a terminal  34 , its source terminal is connected to the circuit output terminal  22 , and its drain terminal is connected to the circuit input terminal  14 . The gate of the sixth PMOS transistor  32  is connected to a control voltage P 2  at a terminal  36 , its source terminal is connected to the circuit input terminal  14 , and its drain terminal is connected to the circuit output terminal  22 . 
     The control voltages P 1 , P 2  are selected such that they bias the fifth and sixth transistors  30 ,  32  to operate in their linear region, where they behave in a resistive manner. The voltages P 1  and P 2  will be within the range of the supply voltages Vss to Vdd. Typically, P 1  will be in the range: 
     
       
         ( Vdd+Vss )/2 &lt;P   1 &lt; Vdd   
       
     
     , and P 2  will typically be in the range: 
     
       
           Vss   ≦P   2 ≦( Vdd+Vss )/2 
       
     
     Therefore, the control voltages P 1 , P 2  are typically above and below the mid supply voltage, respectively. 
     Moreover, the effective resistance values of these devices can be controlled by the applied control voltages. However, the resistance values will be sufficiently high that no, or negligible, current will flow in the transistors, meaning that there will be no, or negligible, voltage drop across them, and the DC voltage at the input terminal  14  will be biassed to the DC level at the circuit output  22 . That is, the resistive devices  30 ,  32  allow current to flow between the output  22  and the input  14 , such that the input  14  will be charged until its voltage is equal to the voltage of the output  22 . This is the DC quiescent operating point. Application of a signal to the input will cause a difference between the voltages on input  14  and output  22 , thus causing a current to flow through devices  30 ,  32 . 
     In principle, the fifth and sixth transistors  30 ,  32  could be replaced by one or more resistors, but it is not possible to fabricate resistors with sufficient accuracy in a CMOS process for this to be a useful option. Moreover, the circuit of FIG. 3 allows the option of controlling the resistance by adjusting the control voltages P 1 , P 2 . 
     In cases where no adjustment of the input impedance is required, it is also possible to connect the gates of the fifth and sixth transistors to the first and second voltage supply rails respectively. The sizes of the fifth and sixth transistors can then be designed to provide the required amplifier parameters. 
     The gain of the circuit of FIG. 3 is represented in the small signal model shown in FIG.  4 . 
     In FIG.  4 , 
     
       
           V   o ( g   m     24     +g   m     26   )+ V   i ( g   m     16     +g   m     18   )+( V   o   −V   i ) g   m     30   =0 
       
     
     
       
           V   o ( g   m     24     +g   m     26     +g   m     30   )=− V   i ( g   m     16     +g   m     18     −g   m     30   ) 
       
     
     Therefore,          A   v     =         V   o       V   i       =     -     (         g     m   16       +     g     m   18       -     g     m   30             g     m   24       +     g     m   26       +     g     m   30           )                                
     The input resistance of the circuit of FIG. 3 is shown in FIG.  5 .          R   IN     =       R   f       1   +     A   v                 Therefore   ,                  R   IN     =       1   /     g     m   30           1   +     A   v                                  
     The input resistance can be matched to the source impedance (for example 50 Ω) to provide optimum power matching. 
     However, from a noise point of view, the noise factor of the circuit of FIG. 3 is much lower than that of FIG.  1 . 
     For the purposes of noise analysis, the circuit of FIG. 1 may be represented by FIG. 6, where R p  is the input resistance of M 16/18  (mainly poly resistance of the gates). 
     The noise of the amplifier can be represented by N VA , as shown in FIG. 7, resulting in a noise factor represented by FIG. 8, in which the source resistance is represented by R S .            V   _     ni   2     =           4      KT       R   p       ·       (       R   S     //     R   P       )     2       +         4      KT       R   S              (       R   S     //     R   p       )     2                                
     where K is Boltzmann&#39;s constant and T is the temperature. 
     Normally, for power match, R p =R S    
     Therefore,            V   _     ni   2     =         4      KT       R   p       ·       (       R   p     2     )     2     ·   2                 V   _     ni   2     =     2   ·   KT   ·     R   p                              
     and the Noise Factor, F, equals:        F   =         (       2   ·   K   ·   T   ·     R   p       +     N   VA       )         KTR   p     ·     A   V   2         ·     A   v   2               F   =     2   +       N   VA       KTR   p                                
     Thus, in the circuit of FIG. 1, F must be greater than two. 
     In comparison, for the purposes of noise calculations, the circuit of FIG. 3 may be represented by FIG.  9 . 
     The input impedance is set by feedback resistor R f , where            R   S     =       R   f       1   +     A   V           ,                          
     to provide power match 
     Thus, the noise factor is as given in FIG.  10 .            V   _     ni   2     =             4      KT       R   S       ·       (       R   S     2     )     2       +         4      KT       R   f       ·       (       R   S     2     )     2         =       KT        (       R   S     +       R   S       R   f         )       2                              
     So, assuming 
     
       
         
           R 
           f 
           ≈A 
           V 
           ·R 
           S 
         
       
     
     
       
         
           
             
               
                 V 
                 _ 
               
               ni 
               2 
             
             = 
             
               
                 KT 
                  
                 
                   ( 
                   
                     
                       R 
                       S 
                     
                     + 
                     
                       
                         R 
                         S 
                       
                       
                         A 
                         V 
                       
                     
                   
                   ) 
                 
               
               = 
               
                 KTR 
                  
                 
                   ( 
                   
                     1 
                     + 
                     
                       1 
                       
                         A 
                         V 
                       
                     
                   
                   ) 
                 
               
             
           
         
                 
         
             
         
      
     
     Therefore, noise factor        F   =           KTR   S          (     1   +     1     A   V         )       +     4        KTR   p       +     N     V                 A           KT   ·     R   S                 F   =     1   +     1     A   V       +       4        R   p         R   S       +       N     V                 A         KTR   S                                
     If, for example, Av is 10, Rp is 5 Ω and Rs is 50 Ω, then, 
     
       
           F= 1+0.1+(4×5)/50+ N   VA   /KTRs= 1+0.5+ N   VA   /KTRs= 1.5+ N   VA   /KTRs   
       
     
     According to the circuit of FIG. 1, the noise figure was N VA /KTRp, whereas now it includes Rs which is ten times larger than Rp, so that the noise factor is reduced in value. 
     For example, if N VA =K.T.25 
     Noise figure of FIG.  1 =2+(K.T.25/K.T.5) 
         F=7 ( 8.4 dB) 
     Noise figure of FIG.  3 =1.5+(K.T.25/K.T.50) 
     
       
             F=2 ( 3.0 dB) 
       
     
     Thus, as mentioned above, the circuit of FIG. 3 has a much better noise factor than that of FIG.  1 . 
     For any value of the gain from the circuit input to output, the resistance value of the feedback transistors  30 ,  32  can be set to give any desired value of the active input impedance. The transistor parameters, such as the device sizes, can be designed to provide the required amplifier parameters such as gain and input impedance. Further, the transistor resistances can be controlled in the circuit of FIG. 1 by adjusting the gate voltages. 
     The circuit of FIG. 3 shows fifth and sixth transistors  30 ,  32  in the feedback loop connecting the output to the input. However, depending on the required feedback resistance, it may be possible to provide just one such transistor. 
     Further, or alternatively, either of the third and fourth transistors  24 ,  26  may be removed, and replaced by a resistor or current source. 
     FIG. 11 shows an alternative embodiment according to a further aspect of the invention, in which the third and fourth transistors  24 ,  26  may be removed, providing that the feedback loop has the fifth and sixth transistors  30 ,  32 . In this case, the fifth and sixth transistors  30 ,  32  act as a load to the output  22 , and define the gain of the amplifier. They also define the input resistance as shown in FIG.  5 . 
     FIG. 12 shows an alternative embodiment according to a third aspect of the invention, in which the first and third transistors  16  and  24  of FIG. 3 are removed, and replaced with a resistor  34  connected between Vdd and the output  22 . Alternatively, the transistors  16 ,  24  could be replaced with a current source (not shown), rather than a resistor  34 . 
     In a further embodiment according to a fourth aspect of the invention, as shown in FIG. 13, the second and fourth transistors  18  and  26  of FIG. 3 are removed, (ie. a mirror of FIG.  12 ), and replaced with a resistor  34 . As above, the transistors  18 ,  26  could also be replaced with a current source (not shown), rather than a resistor  34 . 
     The circuit has been described herein with reference to its fabrication using CMOS techniques. However, it will be recognised that any form of field MOS devices may be used in the circuit. 
     Thus, the circuit can act as an amplifier with optimum power transfer to the output, yet with low noise. 
     Moreover, the circuit can be used to provide general input impedance termination, for example being designed with unity gain, or with any desired gain, but with its input impedance being controllable as described above.

Technology Classification (CPC): 7