Patent Abstract:
Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. application Ser. No. 11/770,455 filed on Jun. 28, 2007, the contents of which are incorporated herein by reference 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to reconfigurable circuits, and more particularly, to programmable via devices and methods for fabrication thereof. 
       BACKGROUND OF THE INVENTION 
       [0003]    Reconfigurable circuits have been widely used in the semiconductor industry for field programmable gate arrays (FPGAs) and for repair of a defective memory element. The FPGA consists of a set of simple, configurable logic blocks in an array with interspersed switches that can rearrange interconnections between the logic blocks. 
         [0004]    Reconfigurable circuits are also expected to play a significant role in three-dimensional integration technology that is being currently developed. Three-dimensional integration fabricates multilayer structures that can form a single chip combination with different functionalities. In these multilayer (and multifunctional) systems, reconfigurable circuit connection is typically needed to provide controllable logic functionality, memory repair, data encryption, as well as other functions. 
         [0005]    A programmable via is an enabling technology for high-performance reconfigurable logic applications without the trade offs in low logic gate density and power. Phase change materials are an attractive option for this application, but to date, have drawn the most attention from semiconductor memory developers as a possible replacement to flash memory. 
         [0006]    Programmable vias implementing phase change materials have been developed. One notable challenge that exists, however, with regard to the practical implementation of programmable vias in logic devices, is being able to scale the programmable via process technology to integrate with the current technology node. To date, programmable via process technology is not readily scalable. 
         [0007]    Therefore, scalable programmable via technology would be desirable. 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention provides programmable via devices and methods for the fabrication thereof. In one aspect of the invention, a programmable via device is provided. The programmable via device comprises a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer. 
         [0009]    In another aspect of the invention, a method of fabricating a programmable via device is provided. The method comprises the following steps. A substrate is provided. A dielectric layer is formed on the substrate. A heater is formed over at least a portion of a side of the dielectric layer opposite the substrate. A first oxide layer is deposited over the side of the dielectric layer opposite the substrate, so as to surround at least a portion of the heater. A pair of first conductive vias is formed, wherein each of the first conductive vias extends through the first oxide layer and is in contact with the heater. A first capping layer is deposited over a side of the first oxide layer opposite the dielectric layer. At least one programmable via is formed extending through the first capping layer and the first oxide layer, between the pair of first conductive vias, and in contact with the heater, the programmable via comprising at least one phase change material. A second capping layer is formed over the programmable via. A second oxide layer is deposited over a side of the first capping layer opposite the first oxide layer. The pair of first conductive vias is extended through the first capping layer and the second oxide layer. A second conductive via is formed through the second oxide layer and in contact with the second capping layer. 
         [0010]    In yet another aspect of the invention, a method of performing a logic function is provided. The method comprises the following steps. A programmable via device is provided. The programmable via device comprises a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer. An OFF switching pulse is passed through the heater, when the programmable via is in a conductive state, the OFF switching pulse being configured to amorphize at least a portion of the phase change material in the programmable via to switch the programmable via to a resistive state and/or an ON switching pulse is passed through the heater, when the programmable via is in a resistive state, the ON switching pulse being configured to anneal at least a portion of the phase change material in the programmable via to switch the programmable via to a conductive state. 
         [0011]    A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a diagram illustrating an exemplary programmable via device according to an embodiment of the present invention; 
           [0013]      FIGS. 2A-E  are diagrams illustrating an exemplary methodology for fabricating a programmable via device according to an embodiment of the present invention; 
           [0014]      FIGS. 3A-C  are graphs illustrating operation of a phase change material according to an embodiment of the present invention; 
           [0015]      FIG. 4  is a diagram illustrating an exemplary methodology for performing a logic function with the programmable via device of  FIG. 1  according to an embodiment of the present invention; 
           [0016]      FIG. 5  is a graph illustrating resistance-current (R-I) characteristics for switching the programmable via device of  FIG. 1  to an OFF state according to an embodiment of the present invention; 
           [0017]      FIG. 6  is a graph illustrating R-I characteristics for switching the programmable via device of  FIG. 1  to an ON state according to an embodiment of the present invention; and 
           [0018]      FIG. 7  is a graph illustrating cycling data from an endurance test of the programmable via device of  FIG. 1  performed at room temperature according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0019]      FIG. 1  is a diagram illustrating exemplary programmable via device  100 . Programmable via device  100  comprises a substrate  102 , a dielectric layer  104 , a heater  106 , oxide layers  108  and  110 , capping layers  112  and  114 , conductive vias  116 ,  118  and  120  and programmable via  122 . 
         [0020]    Specifically, programmable via device  100  comprises dielectric layer  104  over substrate  102 . Substrate  102  can comprise any suitable semiconductor material, including, but not limited to, silicon (Si). Dielectric layer  104 , an insulating layer, can comprise any suitable dielectric material, including, but not limited to, oxides such as silicon dioxide (SiO 2 ). 
         [0021]    Heater  106  is present on a side of dielectric layer  104  opposite substrate  102 . As shown in  FIG. 1 , heater  106  extends laterally over a portion of dielectric layer  104 . To achieve the best efficiency of electrical-thermal transformation (i.e., from heater to programmable via), according to an exemplary embodiment heater  106  comprises a thin layer of a refractory metal having a thickness of between about five nanometers (nm) and about 100 nm with a relatively high resistivity of between about 100 ohm centimeter (Ωcm) and about 10,000 Ωcm, e.g., of between about 500 Ωcm and about 3,000 Ωcm. Suitable refractory metals include, but are not limited to, tantalum nitride (TaN) and metals having the formula Ta x Si y N z , wherein x, y and z are each between zero and about one. 
         [0022]    Oxide layer  108  is present over dielectric layer  104  and surrounds heater  106 . As will be described in detail below, oxide layer  108  has conductive vias  116  and  120  and programmable via  122  extending therethrough. According to an exemplary embodiment, oxide layer  108  comprises SiO 2 . 
         [0023]    Capping layer  112  is present over a side of oxide layer  108  opposite dielectric layer  104 . According to an exemplary embodiment, capping layer  112  comprises silicon nitride (SiN). SiN is a preferred capping material because of its dielectric properties and effectiveness as an etch stop during fabrication (see description below). 
         [0024]    Programmable via  122  extends through capping layer  112  and oxide layer  108 , e.g., and is in contact with heater  106 . Programmable via  122  comprises a phase change material. Suitable phase change materials include, but are not limited to, one or more of ternary alloys of germanium (Ge), antimony (Sb) and tellurium (Te) (GST), such as Ge 2 Sb 2 Te 5 , GeSb, GeSb 4  and doped derivatives thereof with substitution/addition of other elements, such as nitrogen (N) and Si. 
         [0025]    Capping layer  114  is present over programmable via  122 . Capping layer  114  extends laterally a distance beyond programmable via  122  to provide adequate coverage over programmable via  122 , but not so far as to make contact with either of conductive vias  116  or  120 . According to an exemplary embodiment, capping layer  114  comprises a titanium nitride—titanium alloy (TiN/Ti). TiN/Ti provides both a good diffusion barrier between conductive via  118  and the phase change material in programmable via  122  and good adhesion between conductive via  118  and the phase change material in programmable via  122 . 
         [0026]    Oxide layer  110  is present over a side of capping layer  112 /capping layer  114  opposite oxide layer  108 /capping layer  112 , respectively. According to an exemplary embodiment, oxide layer  110  comprises SiO 2 . 
         [0027]    Conductive vias  116  and  120  extend through oxide layers  108  and  110  and capping layer  112 , and make contact with heater  106 . Conductive vias  116  and  120  can each comprise any suitable standard complementary metal-oxide-semiconductor (CMOS) process metal(s), including, but not limited to, one or more of tungsten (W) and copper (Cu). Conductive via  118  is present between conductive vias  116  and  120 , and extends through oxide layer  110  making contact with capping layer  114 . Like conductive vias  116  and  120 , conductive via  118  can also comprise any suitable standard CMOS process metal(s), including, but not limited to, one or more of W and Cu. 
         [0028]    Having points of contact present between conductive vias  116 / 120  and heater  106 , and between conductive via  118  and capping layer  114 , i.e., contact points  103 / 105  and  107 , respectively, can introduce an amount of resistance within the device (referred to hereinafter as “internal contact resistance”). Internal contact resistance affects the operating voltage of the device. Namely, the larger the internal contact resistance, the larger a starting voltage to programmable function of the device, i.e., operating voltage required to switch logic states of the device. 
         [0029]    Depending on the structure of the device/method used to form the device, the effect of internal contact resistance on operating voltage can be significant. For example, U.S. patent application Ser. No. 11/612,631, filed on Dec. 19, 2006 by Chen et al., entitled “Programmable Via Structure and Method of Fabricating Same,” the disclosure of which is incorporated by reference herein, describes a programmable via structure formed using a lift-off process. The lift-off process can permit oxidation of/between contact surfaces to occur that can increase the internal contact resistance of the device raising the operating voltage, e.g., to ten volts or greater. 
         [0030]    As will be described in detail below, programmable via device  100  is fabricated so as to have little, if any, internal contact resistance, i.e., less than about 10 −4  ohm square centimeter (Ωcm 2 ). As a result, programmable via device  100  has an operating voltage of less than about five volts, e.g., between about two volts and about three volts. 
         [0031]      FIGS. 2A-E  are diagrams illustrating exemplary methodology  200  for fabricating a programmable via device, such as programmable via device  100  described in conjunction with the description of  FIG. 1 , above. The fabrication techniques described herein are CMOS compatible and thus readily scalable to meet various technology node feature size requirements. 
         [0032]    In step  202 , substrate  102  is provided. Dielectric layer  104  is formed on substrate  102 . According to an exemplary embodiment, substrate  102  comprises Si and dielectric layer  104  comprises an oxide layer (as described above) grown on substrate  102  using a thermal oxidation process. Alternatively, dielectric layer  104  can comprise an oxide layer deposited on substrate  102  using a conventional deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) and chemical solution deposition and evaporation. With either technique, dielectric layer  104  is formed having a thickness of between about five nm and about 2,000 nm, e.g., between about 100 nm and about 500 nm. 
         [0033]    Heater material layer  230  is then deposited on dielectric layer  104 . According to an exemplary embodiment, heater material layer  230  comprises a refractory metal (as described above) and is deposited on dielectric layer  104  using a CVD technique, such as low pressure chemical vapor deposition (LPCVD). 
         [0034]    In step  204 , heater material layer  230  is patterned to form heater  106 . According to an exemplary embodiment, photolithography is used to pattern heater material layer  230 , wherein a photoresist is deposited on heater material layer  230 , masked and patterned with the footprint of heater  106 . A conventional dry etch, such as reactive ion etching (RIE) is then used to form heater  106 . 
         [0035]    In step  206 , oxide layer  108  is deposited over dielectric layer  104  so as to surround heater  106 . According to an exemplary embodiment, oxide layer  108  is deposited using CVD. As shown in step  206 , oxide layer  108  takes on the topography of heater  106  on dielectric layer  104 . 
         [0036]    In step  208 , vias  234  and  236  are formed through oxide layer  108 . According to an exemplary embodiment, vias  234  and  236  are formed using photolithography, wherein a photoresist is deposited on oxide layer  108 , masked and patterned with the vias. A deep RIE is then be used to form vias  234  and  236  through oxide layer  108 , with heater  106  acting as an etch stop. 
         [0037]    In step  210 , each of vias  234  and  236 , formed in step  208 , above, are filled with a metal such as one or more of W and Cu (as described above) to form conductive vias. The metal will establish a direct contact point between each of the vias and the heater. This process insures that little, if any, internal contact resistance will be generated by the device structure. Chemical mechanical planarization (CMP) is then used to planarize vias  234 / 236  and oxide layer  108 . 
         [0038]    In step  212 , capping layer  112  is deposited over a side of oxide layer  108  opposite dielectric layer  104 . According to an exemplary embodiment, capping layer  112  is deposited on oxide layer  108  using CVD. 
         [0039]    In step  214 , via  238  is formed through oxide layer  108  and capping layer  112  between vias  234  and  236 . According to an exemplary embodiment, via  238  is formed using photolithography, wherein a photoresist is deposited on capping layer  112 , masked and patterned with the via. A deep RIE is then used to form via  238  through oxide layer  108  and capping layer  112 , with heater  106  acting as an etch stop. 
         [0040]    In step  216 , via  238  formed in step  214 , above, is filled with a phase change material (as described above). CMP is then used to planarize the phase change material with capping layer  112  as an etch stop. As a result, programmable via  122  is formed. 
         [0041]    In step  218 , capping layer  240  is deposited over a side of capping layer  112  opposite oxide layer  108 . According to an exemplary embodiment, capping layer  240  is deposited over capping layer  112  using CVD. In step  220 , capping layer  240  is patterned to form capping layer  114 , covering and extending laterally a distance beyond programmable via  122 , so as to provide adequate coverage over programmable via  122  (as described above). According to an exemplary embodiment, capping layer  114  is formed using photolithography, wherein a photoresist is deposited on capping layer  240 , masked and patterned with the footprint and location of capping layer  114 . A RIE is then used to form capping layer  114 , with capping layer  112  as an etch stop. 
         [0042]    In step  222 , oxide layer  110  is deposited over a side of capping layer  112  opposite oxide layer  108 , and covering capping layer  114 . According to an exemplary embodiment, oxide layer  110  is deposited over capping layer  112  using CVD. 
         [0043]    In step  224 , via  242  is formed through oxide layer  110 , and vias  244  and  246  are formed through oxide layer  110  and capping layer  112 . According to an exemplary embodiment, a two-step etching process is used to form vias  242 ,  244  and  246 . Namely, a photoresist is deposited on oxide layer  110 , masked and patterned with each of the vias. An oxide-selective RIE is then used to etch vias  242  and  244 / 246  through oxide layer  110 , with capping layers  114  and  112 , respectively, as etch stops. A second, nitride-selective RIE is then used to etch vias  244 / 246  through capping layer  112 . 
         [0044]    In step  226 , each of vias  244  and  246 , formed in step  224 , above, are filled with a metal such as one or more of W and Cu (as described above) to form conductive vias. Since vias  244  and  246  in conjunction with vias  234  and  236  (formed in steps  208  and  210 ), respectively, will comprise conductive vias of the device, it is preferable that the same metal be used to fill vias  234 / 244  and vias  236 / 246 . Via  242 , formed in step  224 , above, is also filled with a metal such as one or more of W and Cu (as described above), forming conductive via  118 . 
         [0045]    CMP is then used to planarize the metal with oxide layer  110  as an etch stop. As a result, via  244  extends via  234  to form conductive via  116  and via  246  extends via  236  to from conductive via  120 . 
         [0046]    Programmable via device  100  is thus formed. Advantageously, the device is planar which permits easy integration into logic circuits. 
         [0047]      FIGS. 3A-C  are graphs illustrating operation of the phase change material used in the programmable via of programmable via device  100 , described, for example, in conjunction with the description of  FIG. 1 , above.  FIG. 3A  is a graph illustrating two theta (deg) (x-ray diffraction) evolution of the crystal structure of Ge 2 Sb 2 Te 5  from amorphous (no line), to face-centered cubic (fcc) to hexagonal close-packed (hcp) on heating (with temperature measured in degrees Celsius (° C.)). In  FIG. 3A , at room temperature (e.g., about 27° C.), and up to moderately elevated temperatures (e.g., up to between about 400° C. and about 500° C.), the material is stable in two phases, a crystalline phase which is a moderately good conductor of electricity (i.e., about 200 microohms centimeter (μΩcm), and an amorphous phase which is insulating.  FIG. 3B  is a graph illustrating resistivity (measured in μΩcm) versus temperature (measured in ° C.) for two phase change material samples, i.e., Ge 2 Sb 2 Te 5  and doped SbTe, showing different resistivities of different phases. The phases are interconverted by thermal cycling. 
         [0048]      FIG. 3C  is a graph illustrating thermal cycling for SET and RESET processes of the phase change material, as a function of temperature and time. Namely, the thermal cycling comprises a “RESET” (or OFF) pulse and a “SET” (or ON) pulse. The “RESET” (or OFF) pulse involves a conversion from crystalline to amorphous form. In this step, the temperature is raised above melting, followed by a rapid quench in a time t 1  as a result of which a disordered arrangement of atoms in the melt is retained. The “SET” (or ON) pulse involves an anneal at a lower temperature, for a longer time t 2 , which enables the amorphous form to crystallize. 
         [0049]      FIG. 4  is a diagram illustrating exemplary methodology  400  for performing a logic function with programmable via device  100 , described, for example, in conjunction with the description of  FIG. 1 , above. The phase change material used in programmable via  122  can be switched between resistive (OFF-amorphous) and conductive (ON-crystalline) states by passing a current pulse through heater  106  which is in contact with programmable via  122 . 
         [0050]    Specifically, in step  402  programmable via device  100  is in an ON state. In step  404 , an abrupt, e.g., a 10 nanosecond (ns) ramp up, a 50 ns plateau and a two ns ramp down, high-current, e.g., greater than one milliamp (mA), pulse is passed through heater  106  to melt and quench/amorphize a thin region of the phase change material adjacent to the heater. OFF switching pulses are described in detail in conjunction with the description of  FIG. 5 , below. Another exemplary OFF switching pulse can comprise a 19 ns ramp up, a 20 ns plateau and a two ns ramp down, at a current of greater than one mA. 
         [0051]    In step  406 , programmable via device  100  is now in a resistive (OFF-amorphous) state, and can remain in the OFF state until switched again. In step  408 , an ON switching operation is accomplished by applying a relatively low current, e.g., less than or equal to about 0.5 mA, longer pulse, e.g., a 200 ns ramp up, a 1,000 ns plateau and a 200 ns ramp down, through heater  106  to anneal the amorphous phase change material to a crystalline state. ON switching pulses are described in detail in conjunction with the description of  FIG. 6 , below. Programmable via device  100  is now back in the conductive (ON-crystalline) state. The state of programmable via device  100 , resistive or conductive, can be read through conductive vias  118  and  120 . 
         [0052]      FIG. 5  is a graph  500  illustrating resistance-current (R-I) characteristics for switching programmable via device  100 , described, for example, in conjunction with the description of  FIG. 1 , above, to an OFF state. According to an exemplary embodiment, 50 ns pulses with gradually increased power were applied to heater  106  from the ON state. Specifically, a ten ns ramp up, a 50 ns plateau and a two ns ramp down were employed. After each pulse, programmable via device  100  was switched back to the ON state. When the pulse current reached about two milliamps (mA), the programmable via resistance started to increase and finally reached the OFF state. 
         [0053]      FIG. 6  is a graph  600  illustrating R-I characteristics for switching programmable via device  100 , described, for example, in conjunction with the description of  FIG. 1 , above, to an ON state. Starting from an OFF state, one microsecond (μs) pulses with gradually increased power were applied to heater  106 , finally implementing switching of the device to the ON state. Specifically, a 200 ns ramp up, a 1,000 ns plateau and then a 200 ns ramp down were employed. 
         [0054]      FIG. 7  is a graph  700  illustrating cycling data from an endurance test performed on programmable via device  100 , described, for example, in conjunction with the description of  FIG. 1 , above, at room temperature. The endurance test results show a stable sense margin without obvious degradation within the ON/OFF cycles. 
         [0055]    Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.

Technology Classification (CPC): 6