Patent Abstract:
An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a wide range of communications channels. Interoperability and Bit Error Rate performance are optimized through compensation of pre-cursor inter-symbol interference, which is performed adaptively in the receiver as opposed to the transmitter.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to communications systems and more particularly to equalization apparatus and adaptation methods for automatically eliminating pre-cursor inter-symbol interference caused by a serial communication channel for a binary, Non-Return-to-Zero (NRZ), serial data stream without requiring transmit pre-equalization. 
         [0003]    2. Description of the Related Art 
         [0004]    Many communications and computing systems use serial transceivers to interconnect high bandwidth devices. The data bits of the communications and computing systems may be processed in groups, such as bytes or words, but transmitted as a series of bits. The serial transceivers separate and aggregate the bits in a device referred to as a Serializer/Deserializer (SerDes). In a typical Serializer/Deserializer (SerDes) application, the biggest challenge is to guarantee that every transmitted data bit is correctly received. In the case of backplane transceivers that must operate above 1 Gb/s data rates, the loss and dispersion characteristics of the channel make it so that a certain amount of signal conditioning is required in order to recover the channel impaired signal arriving at the receiver without error. 
         [0005]    One form of channel impairment is inter-symbol interference, generally caused by dispersion of the signal as it travels along the channel. A data pulse travelling over a channel is dispersed or smeared by stretching the pulse such that it extends over a longer duration when it exits the channel than it extended when it was introduced into the channel. The stretched pulse can be thought of having pre-cursor and post-cursor distortions and these pre-cursor and post-cursor distortions result in inter-symbol interference. The inter-symbol interference caused by pre-cursor distortion can be easily corrected by using pre-emphasis in the transmitter, but for a fully adaptive system, this would require an out-of-band or in-band communication link between the receiver and the transmitter. Thus, a limitation of this system is the fact that the transmitter coefficients must be updated and set as a function of the channel, and as such can only be adapted based on criteria that is obtained in the receiver. For the system to be fully adaptive, update information must be passed from the receiver to the transmitter in an out-of-band or in-band fashion. 
         [0006]    However, providing such a communications link between the receiver and transmitter is unattractive in certain applications. For example, there may be interoperability issues in some applications that do not provide specific methods for receiver-to-transmitter communication. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a receiver based equalization apparatus and adaptation method for automatically eliminating pre-cursor inter-symbol interference caused by a serial communication channel for a binary, Non-Return-to-Zero (NRZ), serial data stream without requiring transmit pre-equalization. 
         [0008]    A system in accordance with the principles of the present invention includes a receiver with an adaptive continuous equalizer. 
         [0009]    One aspect of the present invention is that the adaptive continuous equalizer has an initial shaping filter with two signal paths. The first signal path is a pure broadband gain that can be adapted. The second signal path has a high pass filter that is cascaded with a broadband gain that can be adapted. The two signal paths are summed and represent the output of the initial shaping filter. 
         [0010]    Another aspect of the present invention is that the adaptive continuous equalizer has a second shaping filter which uses the output of the first filter stage as an input. The second shaping filter has two signal paths. The first signal path is a pure broadband gain that can be adapted. The second signal path has a delay element cascaded with a broadband gain that can be adapted. The two signal paths are summed and represent the output of the adaptive continuous equalizer. 
         [0011]    Another aspect of the present invention is that the output of the adaptive continuous equalizer may be combined with a DFE to enhance the performance of the overall equalizer, where the output of the adaptive continuous equalizer is used as an input to the DFE. 
         [0012]    Another aspect of the present invention is that the DFE may have a plurality of symbol spaced coefficients, where each co-efficient may be programmed independent of another co-efficient and or any of the adaptive continuous equalizer gains. 
         [0013]    Another aspect of the present invention is that all the coefficients and various stages of gain in the adaptive continuous equalizer in its entirety are all adapted based on time domain criteria extracted solely from the incoming data stream, where a co-efficient and gain update engine makes updates automatically and iteratively. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1   a  illustrates effects of dispersion on a data pulse. 
           [0015]      FIG. 1   b  illustrates a simplified block diagram of a system with transmit and receive equalization. 
           [0016]      FIG. 2   a  illustrates a simplified block diagram of the equalization system in accordance with the present invention. 
           [0017]      FIG. 2   b  illustrates a simplified block diagram of the adaptive continuous equalizer system coupled with a DFE in accordance with the present invention. 
           [0018]      FIG. 3  illustrates a block diagram of the Co-Efficient and Gain Update block in accordance with the present invention. 
           [0019]      FIG. 4  outlines Co-Efficient and Gain update equations in accordance with the present invention. 
           [0020]      FIG. 5  outlines Co-Efficient and Gain update algorithm in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    In the context of an exemplary 10 Gb/s integrated circuit-type Serializer/Deserializer (SerDes), reference is made to the accompanying drawings, which form a part of the specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized as structural changes may be made without departing from the scope of the present invention. 
         [0022]      FIG. 1   a  illustrates the effect the channel has on a data pulse  102  with a given Unit Interval (UI)  104  and amplitude A  116 . In addition to the data being delayed in time by a factor of t delta    114 , the data channel will cause a temporal dispersion, or smearing, of the data pulse  102 . The result will be a pulse  106 , which has an amplitude  118  that will be scaled by α, where α&lt;1, and a temporal duration which is greater than a single UI, such that the post-cursor elements  108  will affect bits that have not yet been sent, and pre-cursor elements  110  will mix with bits that have already been sent. 
         [0023]    A basic SerDes system  150  is described in  FIG. 1   b , where a TX serial bit stream generated by a transmitter  120  is passed through a pre-emphasis filter  118  before being launched into the channel  132 . The pre-emphasis driver will produce a filtered output  130  which will have been filtered to compensate for the effects of the pre-cursor dispersion  110 . The coefficients  124 ,  126  and  128 , in combination with the cursor bit, first pre-cursor bit, and second pre-cursor bit respectively, will be used to pre-distort the output data stream  130  in such a way that the effects of the pre-cursor dispersion  110  will be cancelled. On the receiver side, a linear AGC  134  is cascaded with a DFE  138 , where the DFE output  140  will be fed back and linearly added to the AGC output  142  to form the fully equalized data stream  144 . Since the DFE is driven by decisions, which represent bits that have been sent prior to the cursor bit, its output  140  can be used to cancel the effects of the post cursor dispersion  108 . The AGC gain  136  is set to scale the incoming data stream  133  such that when it is combined with the output of the DFE filter, the original signal amplitude is recovered. The combination of the pre-filtering in the transmitter and post filtering in the receiver allow for the signal pulse to be fully reshaped, where the dispersion caused by the channel can be completely eliminated. 
         [0024]      FIG. 2   a  illustrates a block diagram of the channel equalization apparatus in accordance with the present invention. The system  200  comprises of a transmitter driver  120 , a non-ideal data channel  132 , an adaptive equalizer  204 , and a receiver block  146 . The transmit driver  120  forwards the serial data stream through the channel  132  in a generic binary format and without pre-filtering. 
         [0025]    The adaptive continuous equalizer  204  in  FIG. 2   a  has two major components: a post-cursor equalizer  206  and a pre-cursor equalizer  208 . The post-cursor equalizer  206  is constructed using the high-pass filter  212 , programmable gain element G DC    214  and programmable gain element G HF    210 . The pre-cursor equalizer  208  is constructed using the delay element  218 , the programmable gain element G AGC    220  and programmable gain element G PRE    222 . 
         [0026]    The output of the channel  133  forms the input to the post-cursor stage, and is split into two concurrent paths as it enters  206 . The data stream is scaled by G DC  in the DC gain path  228 . In the parallel high-pass path  230 , the same data stream is filtered by  212  and scaled by G HF . The output of  210  and  214  are summed at  216  to form the output of the post-cursor stage  234 . The output  234  of the post-cursor stage  206  forms the input for the pre-cursor stage  208 . The input to the pre-cursor stage is scaled by G PRE  in the PRE gain path  234 . In the AGC path  232 , the data is delayed by a factor τ, where τ&lt;UI. The delay signal is subsequently scaled by G AGC . The output of  220  and  222  are summed at  224  to produce the output of the adaptive continuous equalizer  226 . 
         [0027]      FIG. 2   b  shows the case where the adaptive continuous equalizer  204  is combined with an adaptive DFE filter  138  to produce an enhanced equalizer  202 . The output of the adaptive continuous equalizer  226  may be summed with the fed-back response  140  of the DFE  138  to produce a further equalized continuous data stream  144 . The RX block  146  will process the equalized data stream  144 . 
         [0028]    The Co-Efficient and Gain Update block  300  takes in the serial bit stream  144 , which it uses to calculate the updated co-efficient and gain values for the equalizer  204  and the enhanced equalizer  202 . The Co-Efficient and Gain Update block  300 , in accordance with the present invention, will use only time domain signal quality metrics to update the co-efficients and gains of the equalizer  204  and enhanced equalizer  202 , without the requirement of performing any frequency domain analysis on the incoming data stream. It is sufficient to obtain limited information about the data amplitude and the actual recovered bit stream to adapt and converge either the equalizer  204  or the enhanced equalizer  202 . 
         [0029]      FIG. 3  shows a more detailed block diagram of the Co-Efficient and Gain Update block  300 . Three (3) slicers  306 ,  304 , and  308  are used to sample the incoming data stream. Slicers  304  and  308  are configured to sample data with a positive voltage offset  310  and negative voltage offset  312  respectively, while slicer  306  slices the input data stream at the optimum voltage with no offset applied. The offsets  310  and  312  represent the desired or target signal amplitude against which the actual signal amplitude will be compared against. The output of the slicers  304  and  308  will generate information about the amplitude of the signal. The use of three (3) slicers, conceptually, ensures that enough information about the amplitude of the signal is obtained for every bit that is sampled by the system. The proposed system conceptually embodies the most basic method for extracting the necessary update criteria from the data stream. The use of fewer than three (3) slicers, or more than three (3) slicers, would constitute a subset of the functionality described herein. 
         [0030]    The decisions of each slicer are de-multiplexed into parallel data streams, namely data stream  315 , and two monitor streams  317  and  319 , which correspond to slicer decisions made by  306 ,  304 , and  308  respectively. All three (3) parallel data streams are stored in a separate storage array, and subsequently fed into the Co-Efficient and Gain Adaptation logic  316 . The adaptation logic uses a set of equations to generate updates to the Co-Efficient and Gains of the equalizer  204  and the enhanced equalizer  202 . The equations used in the update logic are defined in  FIG. 4 , and they require information from the three (3) sets of data words stored in separate storage arrays in order to produce update information for the co-efficients and gains  324  that are used in the equalizer  202  and the enhanced equalizer  202  described in  FIG. 2   a  and  FIG. 2   b  respectively. 
         [0031]    For this discussion, the de-multiplexing ratio used to generate the data words  315 ,  317 ,  319  is arbitrary. It is only necessary to state that the order of the bits in each de-multiplexed word is preserved, such that the least significant bit in the word is the first bit latched, and the most significant word is the last bit latched. In order to adapt the system described in  200 , specific information about the incoming data stream must be extracted. The most straight-forward method of extracting the information required is to latch three sets of data, where the first word  317  represents the data latched using a slicer  304  that has a positive voltage offset  310 , the second word  315  represents the data latched using a slicer  306  with no voltage offset, and the third word  319  represents the data latched using a slicer  308  that has a negative voltage offset  312 . 
         [0032]    The co-efficient and gain updates are based on an approximation of the Least Mean Squares criterion, which is defined by the following equation: 
         [0000]      C′ x ←C x +μ×ε×Dx.  Equation 1 
         [0033]    Since the target systems are based on digital signaling, the actual analog values required to perform the exact co-efficient update are not readily available. However, the update equation may be approximated and simplified to take advantage of the binary nature of the data stream. 
         [0034]    The decimal parameter D x  in Equation 1 refers to the amplitude of a given data bit x. D x  may be reduced to the polarity of the received data bit b x . In a binary NRZ system the decision threshold for the data slicer has no voltage offset at the input. The data signal polarity is then defined by sgn(b x ). The value of sgn(b x ) is defined in table  409  of  FIG. 4 . If the data bit is larger than the decision threshold and has a binary value “1”, then the polarity is defined as sgn(b x )=+1. If the data bit is smaller than the decision threshold and has a binary value “0”, then the polarity is defined as sgn(b x )=−1. When specifically associated to the cursor, or data bit of reference for the update equations of filter coefficients and gains, sgn(b x )=sgn(b 0 ). 
         [0035]    The decimal parameter ε can be reduced to the polarity of the difference between the target signal amplitude and the actual signal amplitude for a given sampled data bit, and can be defined by sgn(ε). If the actual data signal is a smaller value than the desired or target signal value, then sgn(ε)=+1. If the actual data signal is larger than the desired or target signal value, then sgn(ε)=−1. When specifically associated with a selected cursor, or data bit of reference for the update equations of filter coefficients and gains, sgn(ε)=sgn(ε 0 ). 
         [0036]    Equation 1 can then be simplified to: 
         [0000]      C′ x ←C x +μ×sgn(ε 0 )×sgn(b x ).   Equation 2 
         [0037]    A bit within the data word  315  may arbitrarily be selected to represent the cursor (b 0 )  414 , which will in turn provide the reference point from which to compute the sgn(b x ) parameters for any update equation, and will also provide a bit location to extract the corresponding sgn(ε) information from the monitor channel outputs  317  and  319 . The bits in the words  317  and  319  contain sgn(ε) information for all the bits contained in  315 , thus by extracting the bits from  317  and  319  which have the same bit location as  414 , the sgn(ε) information for the cursor bit b 0  can be extracted. Table  408  may then be used to determine the value of sgn(ε 0 ). If the cursor  414  from  315  has a positive polarity, then the corresponding sgn(ε) bit from  317  is relevant. If the cursor  414  from  315  has a negative polarity, then the corresponding sgn(ε) bit from  319  is relevant. 
         [0038]    Update equations for the post-cursor equalizer stage are derived as a function of the filter architecture. Instead of adapting the post-cursor equalizer stage based on a frequency domain analysis, updates for G HF    220  and G DC    214  are performed using time domain information about the polarity of cursor b 0 , the polarity of the difference between the desired amplitude of cursor b 0  and the actual receive signal amplitude, and the polarity of the first post-cursor b 1 . The equations  416  and  414  are used to update G HF    220  and G DC    214  respectively, and are defined as: 
         [0000]      G′ HF ←G HF −μ×sgn(ε 0 )×sgn(b 1 ).  Equation 3 
         [0000]      G′ DC ←G DC +μ×sgn(ε 0 )×sgn(b 0 ).  Equation 4 
         [0039]    Update equations for the pre-cursor equalizer stage are derived as a function of the filter architecture. Instead of adapting the pre-cursor equalizer stage based on a frequency domain analysis, updates for G AGC    210  and G PRE    222  are performed using time domain information about the polarity of cursor b 0 , the polarity of the difference between the desired amplitude of cursor b 0  and the actual receive signal amplitude, and the polarity of the first pre-cursor b -1 . The equations  412  and  418  are used to update G AGC    210  and G PRE    222  respectively, and are defined as: 
         [0000]      G′ AGC ←G AGC +μ×sgn(ε 0 )×sgn(b 0 ).  Equation 5 
         [0000]      G′ PRE ←G PRE +μ×sgn(ε 0 )×sgn(b -1 ). Equation 6 
         [0040]    If a DFE is included in the equalizer configuration as shown in  FIG. 2   b , the updates for the DFE coefficients  148  are straightforward as per equation  410 . The DFE only equalizes post cursor ISI, and thus the index x in sgn(b x ) can only be positive, and denotes bits that were received previous to the cursor b 0 . 
         [0041]    The step size μ can be selected as a value which is typically much smaller than the maximum co-efficient or gain value, and may be selected as a different value for each update equation  410 ,  412 ,  414 ,  416 , and  418 . 
         [0042]      FIG. 5  outlines a flow diagram  500  that shows the update algorithm that is used to adapt the various gains and coefficients  324  used in the equalizer circuit  204  and enhanced equalizer  202  described in  FIG. 2   a  and  FIG. 2   b  respectively. All equations may be updated simultaneously, by iteration. The step size can be changed for each set of equations to increase the rate of convergence or improve the precision of the acting co-efficient or gain. The equalizer can be converged to the optimum setting for any number of channels.

Technology Classification (CPC): 7