Patent Abstract:
A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. application Ser. No. 11/321,322, which was filed on Dec. 28, 2005, and which is incorporated by reference in its entirety for all purposes. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This present invention relates generally to memory systems, components, and methods, and more particularly to fully buffered memory controllers that efficiently retire entries in a replay queue. 
       BACKGROUND OF THE INVENTION 
       [0003]    Conventional computer memory subsystems are often implemented using memory modules. A computer circuit board is assembled with a processor having an integrated memory controller, or coupled to a separate memory controller. The processor having the integrated memory controller or the separate memory controller is connected by a memory bus to one or more memory module electrical connectors (the bus may also connect to additional memory permanently mounted on the circuit board). System memory is configured according to the number of and storage capacity of the memory modules inserted in the electrical connectors. 
         [0004]    As processor speeds have increased, memory bus speeds have been pressured to the point that the multi-point (often referred to as “multi-drop”) memory bus model no longer remains viable. Referring to  FIG. 1 , one current solution uses a “point-to-point” memory bus model employing buffered memory modules. In  FIG. 1 , a computer system  100  comprises a host processor  105  communicating across a front-side bus  108  with a memory controller  110  that couples the host processor to various peripherals (not shown except for system memory). Memory controller  110  communicates with a first buffered memory module  0  across a high-speed point-to-point bus  112 . A second buffered memory module  1 , when included in system  100 , shares a second high-speed point-to-point bus  122  with first memory module  0 . Additional high-speed point-to-point buses and buffered memory modules can be chained behind memory module  1  to further increase the system memory capacity. 
         [0005]    Buffered memory module  0  is typical of the memory modules. A memory module buffer (MMB)  146  connects module  0  to a host-side memory channel  112  and a downstream memory channel  122 . A plurality of memory devices (Dynamic Random Access Memory Devices, or “DRAMs” like DRAM  144 , are shown) connect to memory module buffer  146  through a memory device bus (not shown in  FIG. 1 ) to provide addressable read/write memory for system  100 . 
         [0006]    As an exemplary memory transfer, consider a case in which processor  105  needs to access a memory address corresponding to physical memory located on memory module  1 . A memory request issues to memory controller  110 , which then sends a memory command, addressed to memory module  1 , out on host memory channel  112 . Memory controller  110  also designates an entry  115  corresponding to the memory command into replay queue  111 . Prior entries corresponding to prior memory commands may be ahead of entry  115  in queue  111 . 
         [0007]    For tractability reasons, entry  115  may be retired from the queue  111  only after two conditions are met. First, memory controller  110  only retires an entry after a corresponding non-error response is received. Second, memory controller  110  only retires an entry if all prior entries have been retired. 
         [0008]    The MMB  146  of buffered memory module  0  receives the command, resynchronizes it, if necessary, and resends it on memory channel  122  to the MMB  148  of buffered memory module  1 . MMB  146  detects that the command is directed to it, decodes it, and transmits a DRAM command and signaling to the DRAMs controlled by that buffer. If the memory transfer was successful, MMB  148  sends a non-error response through memory module  0  back to memory controller  110 . Memory controller  110  retires entry  115  from replay queue  111  after the non-error response is received, but only if all prior entries have also been retired. 
         [0009]    Due to economies, the size of the replay queue  111  is limited. Therefore, entries need to be retired as quickly as possible. Due to northbound bandwidth limitations of high-speed point-to-point bus  112 , receipt of non-error responses such as write acknowledges may be delayed. Delayed receipt of such a write acknowledgement may in turn delay the retirement of subsequent entries that were entered into replay queue  111  after entry  115 . The delayed retirement of an entry and subsequent entries limits the amount of space available in replay queue  111  for new entries. 
         [0010]    Because of the forgoing limitations, the amount of free space in replay queues of memory controllers is limited. The disclosure that follows solves this and other problems. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0011]      FIG. 1  is a diagram showing a conventional memory controller. 
           [0012]      FIG. 2  is a diagram of a memory controller that retires two entries from a replay queue in response to a single non-error response. 
           [0013]      FIG. 3  is a flowchart showing how the memory controller of  FIG. 2  retires the entries. 
           [0014]      FIG. 4A  is a timing diagram showing the operation illustrated in  FIG. 2 . 
           [0015]      FIG. 4B  is a timing diagram showing an alternative operation of the memory controller of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION  
       [0016]      FIG. 2  shows one example of a memory controller  200  that retires two replay queue entries according to a single non-error response. The memory controller  200  includes an issue engine  201 , a memory  202  and a replay queue  203 . The issue engine  201  performs the functions described in the flowcharts of  FIG. 3 . The timing of the signals shown in  FIG. 2  is depicted in the timing diagram in  FIG. 4   a.    
         [0017]    Memory controller  200  sends memory command  204   a  to memory module  1 . In this example memory command  204   a  is a burst length eight read command including a starting address for a multicycle read operation. In other examples memory command is any type of read command. An entry  204   b  corresponding to memory command  204   a  is created in replay queue  203 . Upon receiving memory command  204   a , memory module  1  starts reading data beginning with the start address. As memory module  1  is reading data, it sends back the read data in non-error memory response  204   c.    
         [0018]    Next memory controller  200  sends memory command  205   a  to memory module  0  that is north of memory module  1 . In this example memory command  205   a  is a burst length four write command that provides write data to memory module  0  during four successive strobes. In other examples memory command  205   a  is any type of write command. An entry  205   b  corresponding to memory command  205   a  is created in replay queue  203 . Entry  205   b  is a consecutive entry with respect to entry  204   b . Upon receiving memory command  205   a , memory module  0  begins writing the data provided with memory command  205   a . Memory module  0  begins writing data concurrently with memory module  1  reading data according to memory command  204   b.    
         [0019]    Memory controller  200  sends memory command  206   a  to memory module  1  that is south of memory module  0 . Memory command  206   a  is a burst read command similar to memory command  204   a . An entry  206   b  corresponding to memory command  206   a  is created in replay queue  203 . 
         [0020]    Memory module  0  finishes writing data according to the burst length four write command  205   a . However, since memory module  1  is still sending read data via Memory Module Buffer (MMB)  245  of memory module  0  there is no bandwidth available for memory module  0  to send a non-error response  205   c . The non-error response  204   c  including the read data consumes all of the bandwidth in the northbound direction. Accordingly, the memory controller  200  does not observe a non-error response including a write acknowledgement at this time. 
         [0021]    After data is read according to memory command  204   a , memory module  1  begins reading data according to memory command  204   c . As memory module  1  is reading data, it sends back the read data in non-error memory response  206   c . Non-error response  206   c  consumes all of the bandwidth in the northbound direction and is sent immediately after non-error responses  204   c . According to conventional FBD protocol, memory controller  200  must continue to wait to observe non-error response  205   c  until bandwidth is available. As used within the specification, the FBD protocol refers to, for example, any revision of the FBD specification on the JEDEC website. Non-error response  205   c  may include explicit signals such as idle patterns or write acknowledgements. 
         [0022]    Memory controller  200  receives non-error response  204   c . Entry  204   b  is retired from the replay queue  203  because there are no prior entries pending. Although memory controller  200  has not received an explicit non-error response  205   c  corresponding to entry  205   b , memory controller  200  may also retire entry  205   b  in response to non-corresponding non-error response  204   c . This is in contrast to conventional FBD protocol where memory controller  200  must continue to wait for non-error response  205   c . Thus two entries may be retired in response to a single non-error response  204   c.    
         [0023]    Entry  205   b  may be retired upon receipt of non-corresponding non-error response  204   c  because of the following occurrences. First, entry  205   b  corresponds to a write to a memory module that is north of a memory module that was read. Second, the write occurs concurrently with the read from the southern memory module. Third, an alert corresponding to memory command  205   a  was not received. An alert corresponding to memory command  205   a  would have taken priority over non-error response  204   c . Accordingly, the receipt of non-error response  204   c  implicitly signals memory controller  200  that an alert was not issued and that memory command  205   a  must have been successful. Thus, entry  205   b  may be advantageously retired early before a corresponding non-error response  205   c  is received. 
         [0024]    Next non-error response  206   c  is received. Entry  206   b  may advantageously be retired immediately because there are no prior entries in memory queue  203 . Had memory controller  200  waited for a corresponding non-error response  205   c  before retiring entry  205   b , prior entry  205   b  would exist causing a delay in retiring  206   b . Thus memory controller  200  retires entries  205   b  and  206   b  early compared to a conventional memory controller. 
         [0025]    Finally, non-error response  205   c  including a write acknowledgement may be received. Since memory controller  200  has already been signaled that memory command  205   a  was successful, memory controller  200  may forgo observation of explicit non-error response  205   c . Optionally forgoing explicit write acknowledgement  205   c  due to the presence of the aforementioned occurrences advantageously increases southbound occupancy. The increase in southbound occupancy increases maximum bandwidth by as much as 50% over conventional systems with similar replay queue limitations. 
         [0026]    The above process is illustrated in a flowchart in  FIG. 3 . Referring to  FIG. 3 , the memory controller  200  issues a read command to cause a first memory module to be read in block  300 . In block  301 , a write command is issued to cause a second memory module that is farther north than the first memory module to be concurrently written. Next the memory controller  200  creates a first entry corresponding to the read command in a replay queue  203  in block  302 . In block  303  a second entry is created corresponding to the write command. 
         [0027]    Next, in block  304  the memory controller  200  waits for a non-error response corresponding to the read command. If the non-error response is received in block  305 , the memory controller  200  retires both entries in block  306 A. If the non-error response is not received, in block  306 B memory controller  200  resets the branch and then replays the contents of replay queue  203 . 
         [0028]      FIG. 4A  shows a timing diagram for the system illustrated in  FIG. 2 . DIMM  1  receives a read command  204   a  from memory controller  200  and begins reading data at T 6 . DIMM  0  receives a write command  205   a  and begins writing data at T 7  concurrently with DIMM  1  reading data. As DIMM  1  is reading data a transmission  204   c  from DIMM  1  begins at T 7 . Transmission  204   c  continues up to T 10 , thereby preventing the memory controller  200  from immediately observing an explicit write acknowledge  205   c.    
         [0029]    Meanwhile, DIMM  1  receives a read command  206   a  from memory controller  200  at T 9  and begins reading. Immediately after DIMM  1  completes transmission  204   c , transmission  206   c  begins at T 11 . Memory controller  200  is still unable to observe an explicit write acknowledgement  205   c  because transmissions  204   c  and  206   c  consume all of the northbound bandwidth. 
         [0030]    Meanwhile, memory controller  200  starts receiving the read data transmission  204   c  from DIMM  1  at T 8 . When the transmission is completed at T 11 , memory controller  200  retires entry  204   b  from the replay queue  203 . Memory controller  200  also retires entry  205   b  from the replay queue  203  in response to receiving non-corresponding non-error response  204   c . Non-corresponding non-error response  204   c  was not sent in response to memory command  205   a  and does not correspond to entry  205   b . Nonetheless, entry  205   b  is retired. Finally, at T 15  memory controller  200  receives non-error response  206   c  and retires entry  206   b.    
         [0031]    It is not necessary for memory controller  200  to observe write acknowledge  205   c  at a first opening T 15 . Bandwidth may be saved for other transmissions by forgoing explicit observation of write acknowledge  205   c.    
         [0000]      FIG. 4B  shows a timing diagram according to a different series of transmissions than illustrated in  FIG. 2 . The memory controller  200  causes DIMM  1  to start a first read T 6  and DIMM  0  to start writing data at T 7 . The memory controller  200  also causes DIMM  0  to start a second read at T 10 . 
         [0032]    Memory controller  200  begins receiving a non-error response corresponding to the first read at T 8 . When the complete non-error response corresponding to the first read is received at T 11 , entries associated with the first read and the write are both retired. In other words, the entry associated with the write is retired in response to a non-corresponding non-error response. Finally, the memory controller  200  retires an entry associated with the second read at T 15 . 
         [0033]    The system described above can use dedicated processor systems, micro controllers, programmable logic devices, or microprocessors that perform some or all of the operations. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. 
         [0034]    For the sake of convenience, the operations are described as various interconnected functional blocks or distinct software modules. This is not necessary, however, and there may be cases where these functional blocks or modules are equivalently aggregated into a single logic device, program or operation with unclear boundaries. In any event, the functional blocks and software modules or features of the flexible interface can be implemented by themselves, or in combination with other operations in either hardware or software. 
         [0035]    Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention may be modified in arrangement and detail without departing from such principles. I claim all modifications and variation coming within the spirit and scope of the following claims.

Technology Classification (CPC): 6