Patent Abstract:
The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost,

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor structure and a method for making the same, and more particularly to a semiconductor structure having a through via and a method for making the same. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  shows a cross-sectional view of a conventional semiconductor structure. The conventional semiconductor structure  1  has a plurality of wafers  11  and an underfill  12 . Each of the wafers  11  has a first surface  111 , a second surface  112 , a first redistribution layer (RDL)  113 , a second redistribution layer (RDL)  114 , a plurality of chips  117 , a plurality of through vias  115  and a plurality of bumps  116 . The first redistribution layer (RDL)  113  is disposed on the first surface  111 . The second redistribution layer (RDL)  114  is disposed on the second surface  112 . The chips  117  are disposed in the wafer  11 , and exposed to the first surface  111  and the second surface  112 . The through vias  115  are disposed in the chips  117 , exposed to the first surface  111  and the second surface  112 , and electrically connect the first redistribution layer (RDL)  113  and the second redistribution layer (RDL)  114 . The humps  116  are disposed on the second redistribution layer (RDL)  114 , and electrically connected to the through vias  115 . The underfill  12  is disposed between two adjacent wafers  11 , and encapsulates the bumps  116 , so as to connect the wafers  11 . 
         [0005]    The conventional semiconductor structure  1  has the following disadvantages. The conventional semiconductor structure  1  is formed by stacking the wafers  11 . For electrically connecting the chips  117 , the through vias  115  are formed in each chip  117 , and then the first redistribution layer (RDL)  113 , the second redistribution layer (RDL)  114  and the bumps  116  are formed in each wafer  11 , which leads to a high manufacturing cost. Moreover, the pitch between the bumps  116  of the wafers  11  is narrowed to reduce the size of the product, so the underfill  12  is difficult to fill up the gap between the bumps  116  and encapsulate the bumps  116  when the wafers  11  are connected. Thus the yield rate of the product is reduced. 
         [0006]    Therefore, it is necessary to provide a semiconductor structure and a method for making the same to solve the above problems. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention is directed to a semiconductor structure. The semiconductor structure comprises a second chip, a first chip, a groove, a through via and at least one electrical connecting element. The second chip has a second active surface and at least one second conductive pad. The second conductive pad is exposed to the second active surface. The first chip is disposed on the second chip, and has a first active surface and at least one first conductive pad. The first conductive pad is exposed to the first active surface, and has at least one through hole. The groove is disposed in the first chip, communicates with the through hole of the first conductive pad, and exposes the first conductive pad and the second conductive pad. The through via is disposed in the groove, and electrically connects the first conductive pad and the second conductive pad. The electrical connecting element is disposed on the first chip, and electrically connected to the through via. 
         [0008]    The present invention is further directed to a semiconductor structure. The semiconductor structure comprises a second chip, a third chip, a first chip, at least one first conductive pad, a groove, a through via and at least one electrical connecting element. The second chip has a second active surface and at least one second conductive pad. The second conductive pad is exposed to the second active surface. The third chip is disposed on the second chip, and has a third active surface. The first chip is disposed on the third chip, and has a first active surface. The first conductive pad has at least one through hole, and is disposed in the first chip or the third chip. The groove is disposed in the first chip and the third chip, communicates with the through hole of the first conductive pad, and exposes the first conductive pad and the second conductive pad. The through via is disposed in the groove, and electrically connects the first conductive pad and the second conductive pad. The electrical connecting element is disposed on the first chip, and electrically connected to the through via. 
         [0009]    The present invention is further directed to a method for making a semiconductor structure. The method comprises the following steps: (a) providing a first wafer and a second wafer, wherein the first wafer has a first active surface and at least one first conductive pad, the first conductive pad is exposed to the first active surface, and has at least one through hole, the second wafer has a second active surface and at least one second conductive pad, the second conductive pad is exposed to the second active surface; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove, wherein the groove communicates with the through hole of the first conductive pad, and exposes the first conductive pad and the second conductive pad; (d) forming a through via in the groove, wherein the through via electrically connects the first conductive pad and the second conductive pad; and (e) forming at least one electrical connecting element on the first wafer, wherein the electrical connecting element is electrically connected to the through via. 
         [0010]    The present invention is further directed to a method for making a semiconductor structure. The method comprises the following steps: (a) providing a first wafer, a third wafer, a second wafer and at least one first conductive pad, wherein the first wafer has a first active surface, the third wafer has a third active surface, the second wafer has a second active surface and at least one second conductive pad, the second conductive pad is exposed to the second active surface, the first conductive pad has at least one through hole and is disposed in the first wafer or the third wafer; (b) disposing the third wafer on the second wafer, and disposing the first wafer on the third wafer; (c) removing part of the first wafer and part of the third wafer, so as to form a groove, wherein the groove communicates with the through hole of the first conductive pad, and exposes the first conductive pad and the second conductive pad; (d) forming a through via in the groove, wherein the through via electrically connects the first conductive pad and the second conductive pad; and (e) forming at least one electrical connecting element on the first wafer, wherein the electrical connecting element is electrically connected to the through via. 
         [0011]    Therefore, in the present invention, the wafers or the chips are penetrated and electrically connected by forming only one through via, which leads to a simplified process and a low manufacturing cost. Moreover, in the present invention, the wafers and the chips are connected directly or by a bonding material, and a plurality of bumps are not needed. Therefore, the present invention avoids the disadvantage that the underfill can not completely encapsulate the bumps, and the yield rate is increased. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a cross-sectional view of a conventional semiconductor structure; 
           [0013]      FIGS. 2 to 12  are schematic views of a method for making a semiconductor structure according to a first embodiment of the present invention; 
           [0014]      FIGS. 13 to 20  are schematic views of a method for making a semiconductor structure according to a second embodiment of the present invention; 
           [0015]      FIG. 21  is a cross-sectional view of a semiconductor structure according to a third embodiment of the present invention; and 
           [0016]      FIG. 22  is a cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]      FIGS. 2 to 12  show schematic views of a method for making a semiconductor structure according to a first embodiment of the present invention. As shown in  FIG. 2 , a first wafer  21  and a second wafer  22  are provided. The first wafer  21  has a first active surface  211  and at least one first conductive pad  212 . The first conductive pad  212  is exposed to the first active surface  211 , and has at least one through hole  213 . The second wafer  22  has a second active surface  221  and at least one second conductive pad  222 . The second conductive pad  222  is exposed to the second active surface  221 . In this embodiment, the shape of the first conductive pad  212  and the through hole  213  thereof is circular, and the through hole  213  is disposed at the center of the first conductive pad  212 , as shown in  FIG. 3 . However, in other embodiments, the shape of the first conductive pad  212  and the through hole  213  thereof can be square, and the through hole  213  is disposed at the center of the first conductive pad  212 , as shown in FIG,  4 , alternatively, the first conductive pad  212  has a plurality of through holes  213 , as shown in  FIG. 5 . 
         [0018]    As shown in  FIG. 6 , the first wafer  21  is disposed on the second wafer  22 . In this embodiment, the first wafer  21  and the second wafer  22  are connected by a bonding material  23 , and the second active surface  221  of the second wafer  22  faces the first active surface  211  of the first wafer  21 . The material of the bonding material  23  is silicon oxide (SiO 2 ) or benzocyclobutene (BCB). However, in other embodiments, the first wafer  21  and the second wafer  22  can be connected by anodic bonding. In another embodiment, the second wafer  22  may further comprises a second back surface  223 , and the second back surface  223  of the second wafer  22  faces the first active surface  211  of the first wafer  21 , that is, in comparison with  FIG. 6 , the second wafer  22  is reversed upside down. 
         [0019]    As shown in  FIG. 7 , preferably, part of the first wafer  21  is removed, so as to reduce the thickness of the first wafer  21 . As shown in  FIG. 8 , part of the first wafer  21  is removed, so as to form a groove  24 . The groove  24  communicates with the through hole  213  of the first conductive pad  212 , and exposes the first conductive pad  212  and the second conductive pad  222 . In this embodiment, part of the first wafer  21  is removed by dry etching, and SF6 or CF4 is used as the etching gas of dry etching. 
         [0020]    The cross-sectional area of the groove  24  is smaller than or equal to those of the first conductive pad  212  and the second conductive pad  222 , and the cross-sectional area of the groove  24  is larger than or equal to that of the through hole  213  of the first conductive pad  212 . However, in other embodiments, under the situation described above “the second back surface  223  of the second wafer  22  faces the first active surface  211  of the first wafer  21 ”, part of the second wafer  22  must be removed at the same time, so as to form the groove  24  in order to expose the second conductive pad  222 . 
         [0021]    As shown in  FIGS. 9 to 11 , a through via  25  (FIG,  11 ) is formed in the groove  24 , and the through via  25  electrically connects the first conductive pad  212  and the second conductive pad  222 . In this embodiment, the method for forming the through via  25  is described below. As shown in  FIG. 9 , a first insulating layer  251  is formed on the first wafer  21 . As shown in  FIG. 10 , part of the first insulating layer  251  is removed, so as to expose the first conductive pad  212  and the second conductive pad  222 . As a result, only the first insulating layer  251  disposed on the side wall of the groove  24  is remained, which defines a first central groove  252 . As shown in  FIG. 11 , a conductor  253  is formed in the first central groove  252 , and fills up the first central groove  252 . However, in other embodiments, the conductor  253  can be formed only on the side wall of the first central groove  252 , and defines a second central groove (not shown). After that, a second insulating layer (not shown) is further formed in the second central groove, and fills up the second central groove. 
         [0022]    As shown in  FIG. 12 , a protective layer  28  and at least one electrical connecting element  26  are formed on the first wafer  21 . The protective layer  28  is disposed on a first back surface  214  of the first wafer  21 , and has an opening so as to expose the through via  25 . The electrical connecting element  26  is disposed in the opening, and electrically connected to the through via  25 , at the same time, a stacked wafer structure is formed. In this embodiment, the electrical connecting element  26  is a pad. However, in other embodiments, the electrical connecting element  26  can be a redistribution layer (RDL). Preferably, the stacked wafer structure is cut, so as to form a plurality of semiconductor structures  2  according to the first embodiment of the present invention, and then the semiconductor structures  2  are disposed on a substrate (not shown) or a circuit board (not shown). 
         [0023]      FIG. 12  shows a cross-sectional view of a semiconductor structure according to the first embodiment of the present invention. The semiconductor structure  2  comprises a first chip  21  (the first chip  21  is formed by cutting the first wafer  21 , and thus they are designated by the same reference numbers), a second chip  22  (the second chip  22  is formed by cutting the second wafer  22 , and thus they are designated by the same reference numbers), a groove  24 , a through via  25 , a protective layer  28  and at least one electrical connecting element  26 . In this embodiment, the semiconductor structure  2  further comprises a bonding material  23 . 
         [0024]    The second chip  22  has a second active surface  221  and at least one second conductive pad  222 . The second conductive pad  222  is exposed to the second active surface  221 . In this embodiment, the bonding material  23  is disposed between the first chip  21  and the second chip  22 , preferably, the material of the bonding material  23  is silicon oxide (SiO 2 ) or henzocyclobutene (BCB). 
         [0025]    The first chip  21  is disposed on the second chip  22 , and has a first active surface  211  and at least one first conductive pad  212 . The first conductive pad  212  is exposed to the first active surface  211 , and has at least one through hole  213 . In this embodiment, the thickness of the first chip  21  is smaller than or equal to that of the second chip  22 , and the second active surface  221  of the second chip  22  faces the first active surface  211  of the first chip  21 . However, in other embodiments, the second chip  22  further comprises a second hack surface  223 , and the second back surface  223  of the second chip  22  faces the first active surface  211  of the first chip  21 , that is, in comparison with  FIG. 12 , the second chip  22  is reversed upside down. 
         [0026]    The groove  24  is disposed in the first chip  21 , communicates with the through hole  213  of the first conductive pad  212 , and exposes the first conductive pad  212  and the second conductive pad  222 . In this embodiment, the cross-sectional area of the groove  24  is smaller than or equal to those of the first conductive pad  212  and the second conductive pad  222 , and the cross-sectional area of the groove  24  is larger than or equal to that of the through hole  213  of the first conductive pad  212 . However, in other embodiments, under the situation described above “the second back surface  223  of the second chip  22  faces the first active surface  21 . 1  of the first chip  21 ”, the groove  24  is further disposed in the second chip  22 . 
         [0027]    The through via  25  is disposed in the groove  24 , and electrically connects the first conductive pad  212  and the second conductive pad  222 . In this embodiment, the through via  25  comprises a first insulating layer  251  and a conductor  253 . The first insulating layer  251  is disposed on the side wall of the groove  24 , and defines a first central groove  252 . The conductor  253  is disposed in the first central groove  252 , and fills up the first central groove  252 . However, in other embodiments, the conductor  253  can be formed only on the side wall of the first central groove  252 , and defines a second central groove (not shown), and the through via  25  further comprises a second insulating layer (not shown). The second insulating layer is disposed in the second central groove, and fills up the second central groove. 
         [0028]    The protective layer  28  is disposed on a first back surface  214  of the first chip  21 , and has an opening so as to expose the through via  25 . The electrical connecting element  26  is disposed in the opening, and electrically connected to the through via  25 . In this embodiment, the electrical connecting element  26  is a pad. However, in other embodiments, the electrical connecting element  26  can be a redistribution layer (RDL). 
         [0029]      FIGS. 13 to 20  show schematic views of a method for making a semiconductor structure according to a second embodiment of the present invention. As shown in  FIG. 13 , a first wafer  21 , a third wafer  27 , a second wafer  22  and at least one first conductive pad  212  are provided. The first wafer  21  has a first active surface  211 . The third wafer  27  has a third active surface  271 . The second wafer  22  has a second active surface  221  and at least one second conductive pad  222 . The second conductive pad  222  is exposed to the second active surface  221 . The first conductive pad  212  has at least one through hole  213 , and is disposed in the first wafer  22  or the third wafer  27 . In this embodiment, the first conductive pad  212  is disposed in the first wafer  22 , and exposed to the first active surface  211 . However, in other embodiments, as shown in  FIG. 21 , at least one third conductive pad  272  is further provided. The third conductive pad  272  has a through hole  273 , disposed in the third wafer  27 , and exposed to the third active surface  271 . Alternatively, as shown in  FIG. 22 , the first conductive pad  212  is disposed in the third wafer  27 , and exposed to the third active surface  271 . 
         [0030]    As shown in  FIG. 14 , the third wafer  27  is disposed on the second wafer  22 , and the first wafer  21  is disposed on the third wafer  27 . In this embodiment, the first wafer  21 , the second wafer  22  and the third wafer  27  are connected by a bonding material  23 . The second active surface  221  of the second wafer  22  and the third active surface  271  of the third wafer  27  face the first active surface  211  of the first wafer  21 . However, in other embodiments, the third wafer  27  further comprises a third back surface  274 . The third back surface  274  of the third wafer  27  faces the first active surface  211  of the first wafer  21 , that is, in comparison with  FIG. 14 , the third wafer  27  is reversed upside down. 
         [0031]    As shown in  FIG. 15 , preferably, part of the first wafer  21  is removed, so as to reduce the thickness of the first wafer  21 . As shown in  FIG. 16 , part of the first wafer  21  and part of the third wafer  27  are removed, so as to form a groove  24 . The groove  24  communicates with the through hole  213  of the first conductive pad  212 , and exposes the first conductive pad  212  and the second conductive pad  222 . As shown in FIGs,  17  to  19 , a through via  25  ( FIG. 19 ) is formed in the groove  24 . The through via  25  electrically connects the first conductive pad  212  and the second conductive pad  222 . In this embodiment, the method for forming the through via  25  is described below. As shown in  FIG. 17 , a first insulating layer  251  is formed on the first wafer  21 . As shown in  FIG. 18 , part of the first insulating layer  251  is removed, so that the first insulating layer  251  has a plurality of sections  254 , and exposes the first conductive pad  212  and the second conductive pad  222 . As a result, only the first insulating layer  251  disposed on the side wail of the groove  24  is remained, which defines a first central groove  252 . As shown in  FIG. 19 , a conductor  253  is formed in the first central groove  252 , and fills up the first central groove  252 . However, in other embodiments, the conductor  253  can be formed only on the side wall of the first central groove  252 , and defines a second central groove (not shown). In the end, a second insulating layer (not shown) is further formed in the second central groove, and fills up the second central groove. 
         [0032]    As shown in  FIG. 20 , a protective layer  28  and at least one electrical connecting element  26  are formed on the first wafer  21 . The protective layer  28  is disposed on a first back surface  214  of the first wafer  21 , and has an opening so as to expose the through via  25 . The electrical connecting element  26  is disposed in the opening, and electrically connected to the through via  25 , at the same time, a stacked wafer structure is formed. Preferably, the stacked wafer structure is cut, so as to form a plurality of semiconductor structures  3  according to the second embodiment of the present invention, and then the semiconductor structures  3  are disposed on a substrate (not shown) or a circuit board (not shown). 
         [0033]      FIG. 20  shows a cross-sectional view of a semiconductor structure according to the second embodiment of the present invention. The semiconductor structure  3  comprises a first chip  21  (the first chip  21  is formed by cutting the first wafer  21 , and thus they are designated by the same reference numbers), a second chip  22  (the second chip  22  is formed by cutting the second wafer  22 , and thus they are designated by the same reference numbers), a third chip  27  (the third chip  27  is formed by cutting the third wafer  27 , and thus they are designated by the same reference numbers), at least one first conductive pad  212 , a groove  24 , a through via  25 , a protective layer  28  and at least one electrical connecting element  26 . In this embodiment, the semiconductor structure  3  further comprises a bonding material  23 . The second chip  22  has a second active surface  221  and at least one second conductive pad  222 . The second conductive pad  222  is exposed to the second active surface  221 . The third chip  27  is disposed on the second chip  22 , and has a third active surface  271 . The first chip  21  is disposed on the third chip  27 , and has a first active surface  211 . 
         [0034]    In this embodiment, the thickness of the first chip  21  is smaller than or equal to those of the second chip  22  and the third chip  27 . The second active surface  221  of the second chip  22  and the third active surface  271  of the third chip  27  face the first active surface  211  of the first chip  21 . However, in other embodiments, the second chip  22  further comprises a second back surface  223 . The third chip  27  further comprises a third back surface  271 . The second back surface  223  of the second chip  22  and the third back surface  271  of the third chip  27  face the first active surface  211  of the first chip  21 , that is, in comparison with  FIG. 20 , the second chip  22  and the third chip  27  are reversed upside down. 
         [0035]    In this embodiment, the bonding material  23  is disposed between the first chip  21  and the third chip  27 , and disposed between the second chip  22  and the third chip  27 , and the material of the bonding material  23  is silicon oxide (SiO 2 ) or benzocyclobutene (BCB). The first conductive pad  212  has at least one through hole  213 , and is disposed in the first chip  21  or the third chip  27 . In this embodiment, the first conductive pad  212  is disposed in the first chip  21 , and exposed to the first active surface  211 . 
         [0036]    The groove  24  is disposed in the first chip  21  and the third chip  27 , communicates with the through hole  213  of the first conductive pad  212 , and exposes the first conductive pad  212  and the second conductive pad  222 . In this embodiment, the cross-sectional area of the groove  24  is smaller than or equal to those of the first conductive pad  212  and the second conductive pad  222 , and the cross-sectional area of the groove  24  is larger than or equal to that of the through hole  213  of the first conductive pad  212 . However, in other embodiments, under the situation described above “the second back surface  223  of the second chip  22  faces the first active surface  211  of the first chip  21 ”, the groove  24  is further disposed in the second chip  22 . 
         [0037]    The through via  25  is disposed in the groove  24 , and electrically connects the first conductive pad  212  and the second conductive pad  222 . In this embodiment, the through via  25  comprises a first insulating layer  251  and a conductor  253 . The first insulating layer  251  is disposed on the side wall of the groove  24 , has a plurality of sections  254 , exposes the first conductive pad  212 , and defines a first central groove  252 . The conductor  253  is disposed in the first central groove  252 , and fills up the first central groove  252 . However, in other embodiments, the conductor  253  can be formed only on the side wall of the first central groove  252 , and defines a second central groove (not shown), and the through via  25  further comprises a second insulating layer (not shown). The second insulating layer is disposed in the second central groove, and fills up the second central groove. 
         [0038]    The protective layer  28  is disposed on a first back surface  214  of the first chip  21 , and has an opening so as to expose the through via  25 . The electrical connecting element  26  is disposed in the opening, and electrically connected to the through via  25 . In this embodiment, the electrical connecting element  26  is a pad. However, in other embodiments, the electrical connecting element  26  can be a redistribution layer (RDL). 
         [0039]      FIG. 21  shows a cross-sectional view of a semiconductor structure according to a third embodiment of the present invention. The semiconductor structure  4  according to the third embodiment is substantially the same as the semiconductor structure  3  ( FIG. 20 ) according to the second embodiment, and the same elements are designated by the same reference numbers. The difference between the semiconductor structure  4  and the semiconductor structure  3  is that the semiconductor structure  4  further comprises a third conductive pad  272 . The third conductive pad  272  has at least one through hole  273 , is disposed in the third chip  27 , and exposed to the third active surface  271 . The groove  24  further communicates with the through hole  273  of the third conductive pad  272 , and further exposes the third conductive pad  272 . The cross-sectional area of the groove  24  is smaller than or equal to that of the third conductive pad  272 , and the cross-sectional area of the groove  24  is larger than or equal to that of the through hole  273  of the third conductive pad  272 . 
         [0040]      FIG. 22  shows a cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention. The semiconductor structure  5  according to the fourth embodiment is substantially the same as the semiconductor structure  3  ( FIG. 20 ) according to the second embodiment, and the same elements are designated by the same reference numbers. The difference between the semiconductor structure  5  and the semiconductor structure  3  is that the first conductive pad  212  of the semiconductor structure  5  is disposed in the third chip  27 , and exposed to the third active surface  271 . 
         [0041]    Therefore, in the present invention, the wafers (the first wafer  21  and the second wafer  22 , or, the second wafer  22  and the third wafer  27 , or, the first wafer  21 , the second wafer  22  and the third wafer  27 ) or the chips (the first chip  21  and the second chip  22 , or, the second chip  22  and the third chip  27 , or, the first chip  21 , the second chip  22  and the third chip  2 ) are penetrated and electrically connected by forming only one through via  25 . The method according to the present invention leads to a simplified process and a low manufacturing cost compared with the method in prior art, since the wafers are connected after the through via  115  are formed in each wafer  11 . Moreover, in the present invention, the wafers and the chips are connected directly or by a bonding material  23 , and a plurality of bumps are not needed. Therefore, the present invention avoids the disadvantage that the underfill  12  can not completely encapsulate the bumps  116  ( FIG. 1 ), and thus the yield rate is increased. 
         [0042]    While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined by the appended claims.

Technology Classification (CPC): 7