Patent Abstract:
A bias current generating circuit generates a reliable and consistent bias current, irrespective of variation in applied power, process and temperature. In one embodiment, the bias current generator generates a bias current using a PTAT current generator and an IPTAT current generator comprising exclusively active circuit elements, for example transistors. No passive elements, such as resistors, are employed. The generated bias current is substantially a function of the respective aspect ratios of transistors of current paths of the device. In this manner, the resulting generated bias current has greatly reduced susceptibility to variation in applied power, process and temperature.

Full Description:
RELATED APPLICATIONS  
       [0001]     This application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2004-0093100, filed on Nov. 15, 2004, the content of which is incorporated herein by reference in its entirety.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to an integrated circuit device, and more particularly, to a bias current generating circuit for an integrated circuit device.  
       BACKGROUND OF THE INVENTION  
       [0003]     Bias current generating circuits are commonly employed in integrated circuit devices in order to generate a bias current from an external power supply voltage. An ideal bias current generating circuit generates a consistent bias current that is independent of variation in applied power, process parameters and temperature.  
         [0004]     A conventional bias current generation circuit is disclosed in U.S. Pat. No. 6,201,436, the content of which is incorporated herein by reference. Such a circuit employs a first current generator in which a first generated current is proportional to absolute temperature (PTAT), or increases with increased temperature, and a second current generator in which a second generated current is inverse-proportional to absolute temperature (IPTAT), or decreases with increased temperature. The first and second generated currents are summed to generate a combined bias current with reduced susceptibility to variation in temperature and applied power.  
         [0005]     In the conventional design, the PTAT and IPTAT current generators employ a resistor to generate the respective first and second currents. Since resistors are highly susceptible to process variation and operating temperature variation, the resulting bias current in the conventional approach is likewise susceptible to process and temperature variations.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention is directed to a bias current generating circuit that generates a reliable and consistent bias current, irrespective of variation in applied power, process and temperature.  
         [0007]     In particular, in one embodiment, the bias current generator of the present invention generates a bias current using a PTAT current generator and an IPTAT current generator comprising exclusively active circuit elements, for example transistors. No passive elements, such as resistors, are employed. The generated bias current is substantially a function of the respective aspect ratios of transistors of current paths of the device. In this manner, the resulting generated bias current has greatly reduced susceptibility to variation in applied power, process and temperature.  
         [0008]     In one aspect, the present invention is directed to a bias current generator. The generator includes a proportional-to-absolute-temperature (PTAT) current generator comprising exclusively active circuit elements that generates a first current that is proportional to operating temperature. An inverse-proportional-to-absolute-temperature (IPTAT) current generator comprising exclusively active circuit elements generates a second current that is inversely proportional to the operating temperature. A summing circuit sums the first and second currents to generate a bias current.  
         [0009]     In one embodiment, the bias current is generated substantially independent of the operating temperature.  
         [0010]     In another embodiment, the PTAT current generator comprises: a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between a first reference voltage and a first node, a gate of the first PMOS transistor being coupled to the first node and a gate of the second PMOS transistor being coupled to a first bias voltage; and a third PMOS transistor and a fourth PMOS transistor connected in series between the first reference voltage and a second node, a gate of the third PMOS transistor being coupled to the first node and a gate of the fourth PMOS transistor being coupled to the first bias voltage; an NMOS cascode current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a third node, a gate of the first NMOS transistor being coupled to a second bias voltage and a gate of the second NMOS transistor being coupled to the second node; and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and a fourth node, a gate of the third NMOS transistor being coupled to the second bias voltage and a gate of the fourth NMOS transistor being coupled to the second node; a first diode connected in series between the third node and a second reference voltage; and a second diode connected in series between the fourth node and the second reference voltage.  
         [0011]     In another embodiment, the first reference voltage comprises a power supply voltage and the second reference voltage comprises a ground voltage.  
         [0012]     In another embodiment, the first diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the third node and a base and collector of which are connected to the second reference voltage and wherein the second diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the fourth node and a base and collector of which are connected to the second reference voltage.  
         [0013]     In another embodiment, the first bias voltage is at a voltage level that is sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level that is sufficient to saturate the first and third NMOS transistors.  
         [0014]     In another embodiment, the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, a gate of the fifth PMOS transistor being coupled to the first node and a gate of the sixth PMOS transistor being coupled to the first bias voltage; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, the fifth and sixth NMOS transistors each being configured in a diode configuration; a seventh PMOS transistor connected between the first reference voltage and a sixth node, the gate of the seventh PMOS transistor being coupled to the sixth node; and a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, a gate of the seventh NMOS transistor being coupled to the second node, and a gate of the eighth NMOS transistor being coupled to the fifth node.  
         [0015]     In another embodiment, the summing circuit comprises: an eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node, a gate of the eighth PMOS transistor being coupled to the first node and a gate of the ninth PMOS transistor being coupled to the first bias voltage; a tenth PMOS transistor connected between the first reference voltage and the seventh node, a gate of the tenth PMOS transistor being coupled to the sixth node; a ninth NMOS transistor connected between the seventh node and the second reference voltage, the gate of the ninth NMOS transistor being coupled to the seventh node; and a tenth NMOS transistor connected between a bias node at which the bias current is drawn and the second reference voltage, the gate of the tenth NMOS transistor being coupled to the seventh node.  
         [0016]     In another embodiment, the bias current generator further comprises a bias voltage generator including a first bias voltage generator that generates the first bias voltage and a second bias voltage generator that generates the second bias voltage. The first bias voltage generator comprises: an eleventh PMOS transistor and an eleventh NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the eleventh PMOS transistor being coupled to the first node, the gate of the eleventh NMOS transistor being coupled to a junction between the eleventh PMOS transistor and the eleventh NMOS transistor; a twelfth PMOS transistor and a twelfth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the twelfth PMOS transistor being coupled to a junction between the twelfth PMOS transistor and the twelfth NMOS transistor, the gate of the twelfth NMOS transistor being coupled to the gate of the eleventh NMOS transistor; and a thirteenth PMOS transistor, a fourteenth PMOS transistor and a thirteenth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the thirteenth PMOS transistor being coupled to the gate of the twelfth PMOS transistor, the gate of the fourteenth PMOS transistor being coupled to a junction between the fourteenth PMOS transistor and the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor being coupled to the gate of the twelfth NMOS transistor, wherein the junction of the fourteenth PMOS transistor and the thirteenth NMOS transistor provides the first bias voltage. The second bias voltage generator comprises: a fifteenth PMOS transistor and a fifteenth NMOS transistor in series between the first reference voltage and an eighth node, the gate of the fifteenth PMOS transistor being coupled to the first node, the gate of the fifteenth NMOS transistor being coupled to a junction between the fifteenth PMOS transistor and the fifteenth NMOS transistor; a sixteenth PMOS transistor, a fourteenth NMOS transistor and a sixteenth NMOS transistor in series between the first reference voltage and the eighth node, the gate of the sixteenth PMOS transistor being coupled to the first node, the gate of the fourteenth NMOS transistor being coupled to a junction between the sixteenth PMOS transistor and the fourteenth NMOS transistor, the gate of the sixteenth NMOS transistor being coupled to the gate of the fifteenth NMOS transistor; and a third diode connected in series between the eighth node and the second reference voltage, wherein the junction of the sixteenth PMOS transistor and the fourteenth NMOS transistor provides the second bias voltage.  
         [0017]     In another embodiment, the third diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the eighth node and a base and collector of which are connected to the second reference voltage.  
         [0018]     In another embodiment, the bias current generator further comprises a start-up circuit that ensures that transistors in the PTAT current generator and the IPTAT current generator initialize beyond a degenerate bias.  
         [0019]     In another embodiment, the start-up circuit comprises: a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor and a twentieth NMOS transistor connected in series between the first reference voltage and the second reference voltage, gates of the seventeenth and eighteenth PMOS transistors each being coupled to the second reference voltage, a gate of the nineteenth NMOS transistor being coupled to the second bias voltage and a gate of the twentieth NMOS transistor being coupled to the second node; a seventeenth NMOS transistor connected in series between the first node and the second reference voltage; and an eighteenth NMOS transistor connected in series between the first bias voltage and the second reference voltage.  
         [0020]     In another embodiment, the summing circuit comprises: a first current mirror that generates a first mirrored current in response to the first current generated by the PTAT;. a second current mirror that generates a second mirrored current in response to the second current generated by the PTAT; and a third current mirror that generates the bias current based on the sum of the first mirrored current and the second mirrored current.  
         [0021]     In another embodiment, the first current is generated further as a function of a first aspect ratio of at least one transistor along a first current path relative to a second aspect ratio of at least one transistor along a second current path, the second current path and first current path being in a current mirror configuration, the first and second aspect ratios for corresponding transistors in the first and second current paths being different.  
         [0022]     In another embodiment, the second current is generated further as a function of a voltage generated in the PTAT current generator that is divided by an active circuit element in the IPTAT current generator to generate the second current.  
         [0023]     In another embodiment, the PTAT current generator comprises: a first current path comprising a plurality of transistors; and a second current path comprising a plurality of transistors, at least one of the plurality of transistors of the second current path corresponding to one of the plurality of transistors of the first current path, at least one pair of the corresponding transistors of the first and second current paths having a different aspect ratio, wherein the first current is generated in response to the different aspect ratio of the corresponding transistors of the first and second current paths.  
         [0024]     In another embodiment, the IPTAT current generator comprises: a third current path comprising a plurality of transistors, wherein the second current is generated as a function of a voltage generated in the PTAT current generator that is divided by a transistor in the third current path to generate the second current.  
         [0025]     In another embodiment, the PTAT current generator comprises: a first diode connected in series between a first reference voltage and a third node; a second diode connected in series between the first reference voltage and a fourth node; a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between the third node and a first node, and a third PMOS transistor and a fourth PMOS transistor connected in series between the fourth node and a second node, gates of the first and third PMOS transistors being coupled to the second node, and gates of the second and fourth PMOS transistors being coupled to a first bias voltage; and an NMOS cascode current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a second reference voltage, and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and the second reference voltage, gates of the first and third NMOS transistors being coupled to a second bias voltage, and gates of the second and fourth NMOS transistors being coupled to the first node.  
         [0026]     In another embodiment, the first reference voltage comprises a power supply voltage and the second reference voltage comprises a ground voltage.  
         [0027]     In another embodiment, the first diode comprises an NPN-type bipolar junction transistor, an emitter of which is connected to the third node and a base and collector of which are connected to the first reference voltage and wherein the second diode comprises an NPN-type bipolar junction transistor, an emitter of which is connected to the fourth node and a base and collector of which are connected to the first reference voltage.  
         [0028]     In another embodiment, the first bias voltage is at a voltage level that is sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level that is sufficient to saturate the first and third NMOS transistors.  
         [0029]     In another embodiment, the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, the fifth and sixth PMOS transistors each being configured in a diode configuration; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, a gate of the fifth NMOS transistor being coupled to the second bias voltage and a gate of the sixth NMOS transistor being coupled to the first node; a seventh PMOS transistor and an eighth PMOS transistor connected in series between the first reference voltage and a sixth node, a gate of the seventh PMOS transistor being coupled to the fifth node, and a gate of the eighth PMOS transistor being coupled to the second node; and a seventh NMOS transistor connected between the sixth node and the second reference voltage, the gate of the seventh NMOS transistor being coupled to the sixth node.  
         [0030]     In another embodiment, the summing circuit comprises: an eighth NMOS transistor and a ninth NMOS transistor connected in series between a seventh node and the second reference voltage, a gate of the eighth NMOS transistor being coupled to the second bias voltage and a gate of the ninth NMOS transistor being coupled to the first node; a tenth NMOS transistor connected between the seventh node and the second reference voltage, a gate of the tenth NMOS transistor being coupled to the sixth node; and a ninth PMOS transistor connected between the first reference voltage and the seventh node, the gate of the ninth PMOS transistor being coupled to the seventh node; and a tenth PMOS transistor connected between the first reference voltage and a bias node at which the bias current is drawn, the gate of the tenth NMOS transistor being coupled to the seventh node.  
         [0031]     In another aspect, the present invention is directed to a bias current generator. A proportional-to-absolute-temperature (PTAT) current generator generates a first current that is proportional to operating temperature. The PTAT current generator comprises a first current path comprising a plurality of transistors; and a second current path comprising a plurality of transistors, at least one of the plurality of transistors of the second current path corresponding to one of the plurality of transistors of the first current path, at least one pair of the corresponding transistors of the first and second current paths having a different aspect ratio, wherein the first current is generated in response to the different aspect ratio of the corresponding transistors of the first and second current paths. An inverse-proportional-to-absolute-temperature (IPTAT) current generator generates a second current that is inversely proportional to the operating temperature. The IPTAT current generator comprises a third current path comprising a plurality of transistors. The second current is generated as a function of a voltage generated in the PTAT current generator that is divided by a transistor in the third current path to generate the second current. A summing circuit sums the first and second currents to generate a bias current.  
         [0032]     In one embodiment, the PTAT current generator comprises exclusively active circuit elements.  
         [0033]     In another embodiment, the IPTAT current generator comprises exclusively active circuit elements.  
         [0034]     In another embodiment, the bias current is generated substantially independent of the operating temperature.  
         [0035]     In another embodiment, the PTAT current generator comprises: a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between a first reference voltage and a first node, a gate of the first PMOS transistor being coupled to the first node and a gate of the second PMOS transistor being coupled to a first bias voltage; and a third PMOS transistor and a fourth PMOS transistor connected in series between the first reference voltage and a second node, a gate of the third PMOS transistor being coupled to the first node and a gate of the fourth PMOS transistor being coupled to the first bias voltage; an NMOS cascode current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a third node, a gate of the first NMOS transistor being coupled to a second bias voltage and a gate of the second NMOS transistor being coupled to the second node; and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and a fourth node, a gate of the third NMOS transistor being coupled to the second bias voltage and a gate of the fourth NMOS transistor being coupled to the second node; a first diode connected in series between the third node and a second reference voltage; and a second diode connected in series between the fourth node and the second reference voltage.  
         [0036]     In another embodiment, the first reference voltage comprises a power supply voltage and the second reference voltage comprises a ground voltage.  
         [0037]     In another embodiment, the first diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the third node and a base and collector of which are connected to the second reference voltage and wherein the second diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the fourth node and a base and collector of which are connected to the second reference voltage.  
         [0038]     In another embodiment, the first bias voltage is at a voltage level that is sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level that is sufficient to saturate the first and third NMOS transistors.  
         [0039]     In another embodiment, the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, a gate of the fifth PMOS transistor being coupled to the first node and a gate of the sixth PMOS transistor being coupled to the first bias voltage; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, the fifth and sixth NMOS transistors each being configured in a diode configuration; a seventh PMOS transistor connected between the first reference voltage and a sixth node, the gate of the seventh PMOS transistor being coupled to the sixth node; and a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, a gate of the seventh NMOS transistor being coupled to the second node, and a gate of the eighth NMOS transistor being coupled to the fifth node.  
         [0040]     In another embodiment, the summing circuit comprises: an eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node, a gate of the eighth PMOS transistor being coupled to the first node and a gate of the ninth PMOS transistor being coupled to the first bias voltage; a tenth PMOS transistor connected between the first reference voltage and the seventh node, a gate of the tenth PMOS transistor being coupled to the sixth node; a ninth NMOS transistor connected between the seventh node and the second reference voltage, the gate of the ninth NMOS transistor being coupled to the seventh node; and a tenth NMOS transistor connected between a bias node at which the bias current is drawn and the second reference voltage, the gate of the tenth NMOS transistor being coupled to the seventh node.  
         [0041]     In another embodiment, the bias current generator further comprises a bias voltage generator including a first bias voltage generator that generates the first bias voltage and a second bias voltage generator that generates the second bias voltage. The first bias voltage generator comprises: an eleventh PMOS transistor and an eleventh NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the eleventh PMOS transistor being coupled to the first node, the gate of the eleventh NMOS transistor being coupled to a junction between the eleventh PMOS transistor and the eleventh NMOS transistor; a twelfth PMOS transistor and a twelfth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the twelfth PMOS transistor being coupled to a junction between the twelfth PMOS transistor and the twelfth NMOS transistor, the gate of the twelfth NMOS transistor being coupled to the gate of the eleventh NMOS transistor; and a thirteenth PMOS transistor, a fourteenth PMOS transistor and a thirteenth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the thirteenth PMOS transistor being coupled to the gate of the twelfth PMOS transistor, the gate of the fourteenth PMOS transistor being coupled to a junction between the fourteenth PMOS transistor and the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor being coupled to the gate of the twelfth NMOS transistor, wherein the junction of the fourteenth PMOS transistor and the thirteenth NMOS transistor provides the first bias voltage. The second bias voltage generator comprises: a fifteenth PMOS transistor and a fifteenth NMOS transistor in series between the first reference voltage and an eighth node, the gate of the fifteenth PMOS transistor being coupled to the first node, the gate of the fifteenth NMOS transistor being coupled to a junction between the fifteenth PMOS transistor and the fifteenth NMOS transistor; a sixteenth PMOS transistor, a fourteenth NMOS transistor and a sixteenth NMOS transistor in series between the first reference voltage and the eighth node, the gate of the sixteenth PMOS transistor being coupled to the first node, the gate of the fourteenth NMOS transistor being coupled to a junction between the sixteenth PMOS transistor and the fourteenth NMOS transistor, the gate of the sixteenth NMOS transistor being coupled to the gate of the fifteenth NMOS transistor; and a third diode connected in series between the eighth node and the second reference voltage, wherein the junction of the sixteenth PMOS transistor and the fourteenth NMOS transistor provides the second bias voltage.  
         [0042]     In another embodiment, the third diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the eighth node and a base and collector of which are connected to the second reference voltage.  
         [0043]     In another embodiment, the bias current generator further comprises a start-up circuit that ensures that transistors in the PTAT current generator and the IPTAT current generator initialize beyond a degenerate bias.  
         [0044]     In another embodiment, the start-up circuit comprises: a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor and a twentieth NMOS transistor connected in series between the first reference voltage and the second reference voltage, gates of the seventeenth and eighteenth PMOS transistors each being coupled to the second reference voltage, a gate of the nineteenth NMOS transistor being coupled to the second bias voltage and a gate of the twentieth NMOS transistor being coupled to the second node; a seventeenth NMOS transistor connected in series between the first node and the second reference voltage; and an eighteenth NMOS transistor connected in series between the first bias voltage and the second reference voltage.  
         [0045]     In another embodiment, the summing circuit comprises: a first current mirror that generates a first mirrored current in response to the first current generated by the PTAT; a second current mirror that generates a second mirrored current in response to the second current generated by the PTAT; and a third current mirror that generates the bias current based on the sum of the first mirrored current and the second mirrored current.  
         [0046]     In another embodiment, the first current is generated further as a function of a first aspect ratio of at least one transistor along a first current path relative to a second aspect ratio of at least one transistor along a second current path, the second current path and first current path being in a current mirror configuration, the first and second aspect ratios for corresponding transistors in the first and second current paths being different.  
         [0047]     In another embodiment, the second current is generated further as a function of a voltage generated in the PTAT current generator that is divided by an active circuit element in the IPTAT current generator to generate the second current.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0048]     The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.  
         [0049]      FIG. 1  is a circuit diagram of a first embodiment of a bias current generating circuit in accordance with the present invention.  
         [0050]      FIG. 2  is a circuit diagram of a second embodiment of a bias current generating circuit in accordance with the present invention.  
         [0051]      FIG. 3  is a circuit diagram of a third embodiment of a bias current generating circuit in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0052]      FIG. 1  is a circuit diagram of a first embodiment of a bias current generating circuit in accordance with the present invention. With reference to  FIG. 1 , the bias generating circuit includes a proportional-to-absolute-temperature (PTAT) current generator  200 , an inverse-proportional-to-absolute-temperature (IPTAT) current generator  400 , and a summing circuit  500 .  
         [0053]     In one embodiment, the PTAT current generator  200  and the IPTAT current generator  400  employ exclusively active elements, such as NMOS and PMOS transistors and bipolar junction transistors, and therefore do not include passive elements, such as resistors. The PTAT current generator  200  generates a first sub-current I 1  that is proportional to temperature. The IPTAT current generator  400  generates a second sub-current I 2  that is inverse-proportional to temperature. The summing circuit  500  sums the first sub-current I 1  and the second sub-current I 2  to generate a sum current I 3  that is used to generate a bias current I bias . Since the PTAT current generator  200  and the IPTAT current generator  400  do not employ passive elements such as resistors, the bias current generating circuit of  FIG. 1  has near insusceptibility to variation in process, applied voltage, and temperature.  
         [0054]     In this embodiment, the PTAT current generator  200  includes a PMOS cascode current mirror  211 , an NMOS cascode current mirror  220 , and first and second PNP-type bipolar junction transistors  210 ,  209 .  
         [0055]     The PMOS cascode current mirror  211  includes a first PMOS transistor  208  and a second PMOS transistor  206  coupled in series between a first reference voltage VDD and a first node  240 . The PMOS cascode current mirror  211  further includes a third PMOS transistor  207  and a fourth PMOS transistor  205  coupled in series between the first reference voltage VDD and a second node  242 . Gates of the first PMOS transistor  208  and the third PMOS transistor  207  are coupled to the first node  240 . Gates of the second PMOS transistor  206  and the fourth PMOS transistor  205  are coupled to a first bias voltage Vcasp.  
         [0056]     The NMOS cascode current mirror  220  includes a first NMOS transistor  204  and a second NMOS transistor  202  coupled in series between the first node  240  and a third node  244 . The NMOS cascode current mirror  220  further includes a third NMOS transistor  203  and a fourth NMOS transistor  201  coupled in series between the second node  242  and a fourth node  246 . Gates of the first NMOS transistor  204  and the third NMOS transistor  203  are coupled to a second bias voltage Vcasn. Gates of the second NMOS transistor  202  and the fourth NMOS transistor  201  are coupled to the second node  242 .  
         [0057]     A first bipolar junction transistor  210  is coupled in a diode configuration between the third node  244  and a second reference voltage GND. The base of the first bipolar junction transistor  210  is coupled to the second reference voltage GND. A second bipolar junction transistor  209  is coupled in a diode configuration between the fourth node  246  and the second reference voltage GND. The base of the second bipolar junction transistor  209  is coupled to the second reference voltage GND.  
         [0058]     By virtue of the operation of the current mirror configuration, the first sub-current I 1 , flowing through the first and second PMOS transistors  208  and  206  and the first and second NMOS transistors  204  and  202  is equal to the first mirror sub-current I 1 ′ flowing through the third and fourth PMOS transistors  207  and  205  and the third and fourth NMOS transistors  203  and  201 . According to the circuit configuration, the gate voltages of the third and fourth NMOS transistors  202 ,  201  are the same, therefore: 
 
 V   be1   +V   gs201   =V   be2   +V   gs202   (1) 
 
 where the voltage at the fourth node, V be1 , is the base-emitter voltage of the second bipolar junction transistor  209 , V gs201  is the gate-source voltage of the fourth NMOS transistor  201 , the voltage at the third node, V be2 , is the base-emitter voltage of the first bipolar junction transistor  210 , and V gs202  is the gate-source voltage of the third NMOS transistor  202 . 
 
         [0059]     Since the base-emitter voltage of a bipolar junction transistor can be represented as:  
               V   be     =         V   T     ·   ln     ⁢           ⁢       I   C       I   S                 (   2   )             
 
 where V T  represents thermal voltage), I C  is the collector current through the transistor and I S  is the bipolar junction transistor saturation current, 
        and since the gate-source voltage of a MOS transistor can be represented as:  
               V   gs     =           2   ⁢     I   D           μ   n     ⁢       C   ox     ⁡     (     W   /   L     )             +     V   th               (   3   )             
 
 where I D  is drain current), μ n  is electron mobility, C ox  is the gate unit capacitance, W/L is the aspect ratio of the transistor and V th  is the transistor threshold voltage, then, ignoring the base current, equations (2) and (3) above can be substituted into equation (1) above to give:  
                     V   T     ·   ln     ⁢           ⁢       I   1   ′       I   S209         +         2   ⁢     I   1   ′           μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       201           +     V   th201       =           V   T     ·   ln     ⁢           ⁢       I   1       I   S210         +         2   ⁢     I   1           μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       202           +     V   th202               (   4   )             
 
 If the transistor body effect is considered negligible, and the threshold voltage of the fourth NMOS transistor is assumed to be equal to the threshold voltage of the third NMOS transistor, V th201 =V th202 , and the first sub-current I 1  is considered equal to the first mirrored sub current I 1 ′, I 1 =I 1 ′, then equation (4) can be rewritten as:  
                   V   T     ·   ln     ⁢           ⁢       I   S210       I   S209         =           2   ⁢     I   1           μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       201           ⁢     (             (     W   /   L     )     201         (     W   /   L     )     202         -   1     )               (   5   )             
 
 With respect to current I 1 :  
               I   1     =         μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       201     ⁢       (         kT   q     ·   ln     ⁢           ⁢   m     )     2         2   ⁢       (       n     -   1     )     2                 (   6   )             
 
 where k is the Boltzman constant, T is absolute temperature, m=I S210 /I S209 , q is the electron charge value and n=(W/L) 201 /(W/L) 202 . The parameter μ n C ox  is proportional to T −1.5 , so the first sub-current I 1  is proportional to T 0.5 , I 1 ∝T 0.5 , and especially in the operational range of the bias circuit, namely in the industrial temperature range between −55 C and 125 C, the proportional rate is linear. In one embodiment, both m and n are chosen to be greater than 1 and, in one example, n=2 and m=7. 
       
 
         [0061]     The gate voltage V gn  of the fourth NMOS transistor  201  is used to generate the second sub-current I 2  at the IPTAT current generator  400 , and can be represented as the sum of the base-emitter voltage of the second bipolar junction transistor  209 , V be1 , and the gate-to-source voltage of the fourth NMOS transistor  201 , V gs201 . Substituting equation (3) above provides:  
                     V   gn     =       ⁢       V   be1     +     V   gs201                   =       ⁢       V   be1     +         2   ⁢     I   1           μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       201           +     V   th                   =       ⁢       V   be1     +     V   th     +       kT   q     ·       ln   ⁢           ⁢   m         n     -   1                         (   7   )             
 
         [0062]     Returning to equation (2), and differentiating V be1  with respect to absolute temperature T provides:  
                 ∂     V   be1         ∂   T       =           ∂     V   T         ∂   T       ⁢   ln   ⁢           ⁢     I   C209       +         V   T       I   C209       ⁢       ∂     I   C209         ∂   T         -         ∂     V   T         ∂   T       ⁢   ln   ⁢           ⁢     I   S209       -         V   T       I   S209       ⁢       ∂     I   S209         ∂   T                   (   8   )             
 
         [0063]     If the base current of the second bipolar junction transistor  209  is considered negligible, and ignored, then the current flowing through the second bipolar junction transistor I c209  is substantially the same as the first sub-current I 1 . Since the first sub-current I 1  is proportional to T 0.5 , then: 
 
 I   C209   =c·T   0.5   (9) 
 
 where c represents a proportional constant, and T is absolute temperature. 
 
         [0064]     The saturation current of the second bipolar junction transistor  209 , I S209  can be represented as: 
 
 I   S209   =b·T   2.5   e   −E     g     /kT   (10) 
 
 where b represents a proportional constant and E g  is the bandgap energy of silicon, or 1.12 eV. 
 
         [0065]     From equations (9) and (10), it can be derived that:  
                   ∂     V   T         ∂   T       ⁢   ln   ⁢           ⁢     I   C209       =         V   T     T     ⁢   ln   ⁢           ⁢     I   C209               (   11   )                     V   T       I   C209       ⁢       ∂     I   C209         ∂   T         =             V   T       cT   0.5       ·     1   2       ⁢     cT     -   0.5         =         V   T     /   2     T               (   12   )                     ∂     V   T         ∂   T       ⁢   ln   ⁢           ⁢     I   S209       =         V   T     T     ⁢   ln   ⁢           ⁢     I   S209               (   13   )                     V   T       I   S209       ⁢       ∂     I   S209         ∂   T         =           5   2     ⁢       V   T     T       +         E   g       kT   2       ⁢     V   T         =         2.5   ⁢     V   T       T     +         E   g     /   q     T                 (   14   )             
 
 Substituting equations (11)-(14) into equation (8) provides for the temperature coefficient of the base-emitter voltage of the second bipolar junction transistor  209 , or the temperature coefficient of V be1 :  
                       ∂     V   be1         ∂   T       =       ⁢           V   T     T     ⁢   ln   ⁢           ⁢     I   C209       +         V   T     /   2     T     -         V   T     T     ⁢   ln   ⁢           ⁢     I   S209       -       2.5   ⁢     V   T       T     -         E   g     /   q     T                   =       ⁢         V   be1     -     2   ⁢     V   T       -       E   g     /   q       T                   (   15   )             
 
 In one example, the base-emitter voltage of the second bipolar junction transistor V be1 =0.8V, the thermal voltage V T =26 mV, the parameter Eg/q=1.12V, and the absolute operating temperature T=300K. In this case, the resulting temperature coefficient of the base-emitter voltage of the second bipolar junction transistor is equal to −1.2 mV/C. 
 
         [0066]     Returning to equation (7), the temperature coefficient of the first term of the equation is −1.2 mV/C, the temperature coefficient of the second term of the equation is −2.5 mV/C, and the temperature coefficient of the third term of the equation is 0.4 mV/C. The stated coefficients are typical values, and can change from process to process.  
         [0067]     In view of the above, it can be concluded that the gate voltage of the fourth NMOS transistor  201 , V gn201 , is inversely proportional to temperature, and especially in the industrial operating range of −55 C to 125 C, V gn  is proportionally reduced, in other words, V gn  decreases with increasing temperature.  
         [0068]     Although the third term of equation (7) increases with temperature, for typical values of m and n (for example, m=7 and n=2), the slope of this term is 0.4 mV/C. Therefore, as temperature rises, the combined decrease of the first two terms dominates over the increase of the third term in equation (7). Thus, the net effect is that gate voltage of the fourth NMOS transistor V gn201  approximately decreases linearly with increasing temperature in the temperature range of interest. Therefore, the PTAT current generator circuit  200  generates both a first sub-current I 1  and a voltage V gn  that decrease with temperature. This voltage V gn  is used to generate the IPTAT current, as described below. Since no integrated resistors are used in the PTAT current generator  200 , the generated first sub-current I 1  is not sensitive to process variations.  
         [0069]     The IPTAT current generator  400  includes a control voltage supply  410  and a second sub-current generator  412 .  
         [0070]     The control voltage supply  410  includes a fifth PMOS transistor  401  and a sixth PMOS transistor  402  coupled in series between the first reference voltage VDD and a fifth node  414 . The gate of the fifth PMOS transistor is coupled to the first node  240  and the gate of the sixth PMOS transistor is coupled to the first bias voltage Vcasp. The control voltage supply  410  further includes a fifth NMOS transistor  403  and a sixth NMOS transistor  404  coupled in series between the fifth node  414  and the second reference voltage GND. The gates of the fifth NMOS transistor  403  and the sixth NMOS transistor  404  are coupled to their sources, so that the fifth and sixth NMOS transistors  403 ,  404  are diode-connected and therefore operate as diodes.  
         [0071]     The second sub-current generator  412  of the IPTAT current generator  400  includes a seventh PMOS transistor  407  coupled in series between the first reference voltage VDD and a sixth node  416 . The gate of the seventh PMOS transistor  407  is coupled to the sixth node  416 . The second sub-current generator  412  of the IPTAT current generator  400  further includes a seventh NMOS transistor  405  and an eighth NMOS transistor  406  coupled in series between the sixth node  416  and the second reference voltage GND. The gate of the seventh NMOS transistor  405  is coupled to the second node  242  at the gate of the fourth NMOS transistor V gn201 , and the gate of the eighth NMOS transistor  406  is coupled to the fifth node  414 .  
         [0072]     The control voltage supplier  410  operates to ensure that the voltage supplied by the fifth node  414  to the gate of the eighth NMOS transistor  406 , V g406 , causes the eighth NMOS transistor to operate in the linear region. By ensuring operation of the eighth NMOS transistor  406  in the linear region, the eighth NMOS transistor operates in the same manner that a resistor operates.  
         [0073]     As described above, the voltage at the gate of the fourth NMOS transistor V gn201  is inversely proportional to operating temperature. Since that voltage is applied to the gate of the seventh NMOS transistor  405 , the second sub-current I 2  is generated to be inversely proportional to the operating temperature.  
         [0074]     The drain current I 2  of the eighth NMOS transistor  406  can be represented as:  
               I   2     =         1       1   /     g   m405       +     r   ds406         ·     V   gn       ≈       V   gn       r   ds406                 (   16   )             
 
 where g m405  is the transconductance of the seventh NMOS transistor  405 , V gn  is the gate voltage of the eighth NMOS transistor  406 , V g406 , and r ds406  is the drain-source resistance of the eighth NMOS transistor  406 . The approximation of equation (16) holds true if r ds406 &gt;&gt;1/g m405 , which can be achieved by providing the eighth NMOS transistor  406  with a relatively small aspect ratio (W/L ratio). 
 
         [0075]     The resistance of the eighth NMOS transistor  406 , r ds406 , can be expressed as:  
               r     ds   ⁢           ⁢   406       =     1       μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       406     ⁢     (       V     g   ⁢           ⁢   406       -     V   th       )                 (   17   )             
 
         [0076]     The gate voltage of the NMOS transistor  406 , V g406 , can be represented as:  
               V     g   ⁢           ⁢   406       =         V     gs   ⁢           ⁢   404       +     V     gs   ⁢           ⁢   403         =             2   ⁢     I     D   ⁢           ⁢   404             μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       404           +     V   th     +         2   ⁢     I     D   ⁢           ⁢   403             μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       403           +     V   th       =             2   ⁢           ⁢           I   1     ⁡     (     W   /   L     )       401     /       (     W   /   L     )     208               μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       404         +         2   ⁢           ⁢           I   1     ⁡     (     W   /   L     )       401     /       (     W   /   L     )     208               μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       403         +     2   ⁢     V   th         =                 2   ⁢       (     W   /   L     )     401           (     W   /   L     )     208           μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       404         ⁢         μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       201     ⁢       (       kT   g     ⁢   ln   ⁢           ⁢   m     )     2         2   ⁢       (       n     -   1     )     2             +           2   ⁢         (     W   /   L     )     401         (     W   /   L     )     208             μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       403         ⁢         μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       201     ⁢       (       kT   g     ⁢   ln   ⁢           ⁢   m     )     2         2   ⁢       (       n     -   1     )     2             +     2   ⁢     V   th         =           kT   q     ·       ln   ⁢           ⁢   m         n     -   1         ⁢     (               (     W   /   L     )     401     ⁢       (     W   /   L     )     201             (     W   /   L     )     208     ⁢       (     W   /   L     )     404           +             (     W   /   L     )     401     ⁢       (     W   /   L     )     201             (     W   /   L     )     208     ⁢       (     W   /   L     )     403           +     )       +     2   ⁢     V   th                         (   18   )             
 
 where m=I S210 /I S209  and where n=(W/L) 201 /(W/L) 202 , from equation (6) above, and where the body effect of the fifth NMOS transistor is considered negligible. 
 
         [0077]     Now, substituting equation (18) into equation (17), provides another expression for the resistance of the eighth NMOS transistor  406 , r ds406 :  
               r     ds   ⁢           ⁢   406       =       (   1   )               μ   n     ⁢         C   ox     ⁡     (     W   /   L     )       406                 [           kT   q     ·       ln   ⁢           ⁢   m         n     -   1         ⁢     (                     (     W   /   L     )     401     ⁢       (     W   /   L     )     201             (     W   /   L     )     208     ⁢       (     W   /   L     )     404           +                       (     W   /   L     )     401     ⁢       (     W   /   L     )     201             (     W   /   L     )     208     ⁢       (     W   /   L     )     403                 )       +     V   th       ]                     (   19   )             
 
         [0078]     It can be seen in this representation that the first term of the bracket in the denominator is proportional to temperature and the second term of the bracket in the denominator, or V th , is inversely proportional to temperature, which is a known property of MOSFET devices. In this manner, the effective resistance of the eighth NMOS transistor  406 , r ds406 , is made to be independent of temperature, the resistance value r ds406  being exclusively controlled according to the aspect ratio (W/L), or the ratio of channel width W to channel length L, of the fifth PMOS transistor  401 , the fifth NMOS transistor  403 , the sixth NMOS transistor  404  and the eighth NMOS transistor  406 , the fourth NMOS transistor  201 , and the first PMOS transistor  208 . By controlling the aspect ratios in this manner, the eighth NMOS transistor can be made to operate as a resistor, while not being subject to temperature-dependence. Therefore, the IPTAT  400  including the eighth NMOS transistor  406  can be made to generate a second sub-current I 2  that is inversely proportional to temperature, since the gate voltage of the eighth NMOS transistor  406 , V g406 , is inversely proportional to temperature, while not being subject to temperature-dependent operation. This assumes that the effect of μ n  in equation (19) is not considered. If this effect is considered, μ n αT 1.5  as mentioned previously, and r ds406  increases with temperature. Returning to equation (16), as temperature increases, the numerator (V gn ) decreases, while the denominator increases. Therefore, in this manner, the second sub-current I 2  decreases with temperature. Resistors are highly sensitive to process variation and are also temperature-dependent. Therefore, by eliminating resistors in the present configuration, sensitivity to process variation and temperature dependence in greatly reduced.  
         [0079]     During operation, the first bias voltage V casp  and the second bias voltage V casn  ensure that the PMOS transistors  205 ,  206 , and  402  and the NMOS transistors  203 ,  204  respectively operate in the saturation region. In addition, in one embodiment, the respective aspect ratios of the first and third PMOS transistors  208 ,  207 , the second and fourth NMOS transistors  206 ,  205 , and the first and third PMOS transistors  204 ,  203  are the same. This is because I 1 =I 1 ′ in the PTAT current generator circuit  200 .  
         [0080]     The transistors having different aspect ratios are the fourth and second NMOS transistors  201 ,  202  and the second and first bipolar junction transistors  209 ,  210 . This ensures that m and n of equation (6) are not 1. If m and n are 1, equation (6) will no longer hold true.  
         [0081]     The summing circuit  500  includes a first summing circuit current mirror  520 , a second summing circuit current mirror  530 , and a third summing circuit current mirror  540 .  
         [0082]     The first summing circuit current mirror  520  includes an eighth PMOS transistor  508  and a ninth PMOS transistor  509  coupled in series between the first reference voltage VDD and a seventh node  514 . The gate of the eighth PMOS transistor  508  is coupled to the first node  240  and the gate of the ninth PMOS transistor  509  is coupled to the first bias voltage V casp . The first summing current mirror  520  provides a mirrored current of the first sub-current I 1  to the seventh node  514 .  
         [0083]     The second summing circuit current mirror  510  comprises a tenth PMOS transistor  510  coupled between the first reference voltage VDD and the seventh node  514 . The gate of the tenth PMOS transistor  510  is coupled to the sixth node  416 . The second summing current mirror  530  provides a mirrored current of the second sub-current I 2  to the seventh node  514 .  
         [0084]     At the seventh node, the mirrored currents of the first and second sub-currents I 1 , I 2  are combined, or summed, to provide a sum current I 3 . The sum current I 3  is applied to the third summing circuit current mirror  540 , which includes a ninth NMOS transistor  511  coupled between the seventh node  514  and the second reference voltage GND, and an tenth NMOS transistor  512  coupled between a bias node  516  and the second reference voltage GND. The gates of the ninth and tenth NMOS transistors  511 ,  512  are coupled to each other and to the seventh node. The sum current I 3  flows through the ninth NMOS transistor  511  and is mirrored at the tenth NMOS transistor  512 , which draws the resulting bias current I bias  from a circuit connected to the bias node  516 .  
         [0085]     As mentioned above, the mirrored current of the first sub-current I 1  is proportional to temperature, while the mirrored current of the second sub-current I 2  is inversely proportional to temperature. Therefore, the summed bias current I bias , which is a mirrored current of the sum current I 3 , can be represented as:  
               I   bias     =       [             (     W   /   L     )     508         (     W   /   L     )     208       ⁢     I   1       +           (     W   /   L     )     510         (     W   /   L     )     407       ⁢     I   2         ]     ·         (     W   /   L     )     512         (     W   /   L     )     511                 (   20   )             
 
         [0086]     Therefore, by controlling the respective aspect ratios of the transistors  208 ,  407 ,  508 ,  510 ,  511 , and  512 , the bias current I bias  can be maintained at a constant value that is entirely dependent on the aspect ratios of the transistors and is independent of temperature and process variation. The first sub-current I 1  and the second sub-current I 2  should be weighted ((W/L) 508 /(W/L) 208  and (W/L) 510 /(W/L) 407 ) before they are summed, so that the summation is constant with regard to temperature. Also, since different applications require a different bias current, this summation should be amplified or attenuated before it is applied, for example according to ((W/L) 512 I/(W/L) 511 ). Equation (20) ensures this.  
         [0087]      FIG. 2  is a circuit diagram of a second embodiment of a bias current generating circuit in accordance with the present invention. With reference to  FIG. 2 , the bias generating circuit includes a proportional-to-absolute-temperature (PTAT) current generator  200 , an inverse-proportional-to-absolute-temperature (IPTAT) current generator  400 , and a summing circuit  500 , as described above, and further includes a bias voltage generator  300  and a start-up circuit  100 .  
         [0088]     The bias voltage generator  300  includes a first voltage generator  320  and a second voltage generator  330 . The first bias voltage generator  320  generates the first bias voltage V casp  that is provided to the PMOS cascode current mirror  210  of the PTAT current generator  200 . The second bias voltage generator  330  generates the second bias voltage V casn  that is provided to the NMOS cascode current mirror  220  of the PTAT current generator  200 .  
         [0089]     The first bias voltage generator  320  includes an eleventh PMOS transistor  307  and an eleventh NMOS transistor  308  coupled in series between the first reference voltage VDD and the second reference voltage GND. In addition, a twelfth PMOS transistor  311  and a twelfth NMOS transistor  309  are coupled in series between the first reference voltage VDD and the second reference voltage GND. Also, thirteenth and fourteenth PMOS transistors  312 ,  313  and a thirteenth NMOS transistor  310  are coupled in series between the first reference voltage VDD and the second reference voltage GND. The gate of the eleventh PMOS transistor  307  is coupled to the first node  240 . The gate of the eleventh NMOS transistor  308  is coupled to a junction between the eleventh PMOS transistor  307  and the eleventh NMOS transistor  308 , and is coupled to gates of the twelfth and thirteenth NMOS transistors  309 ,  310 . The gate of the twelfth PMOS transistor  311  is coupled to a junction between the twelfth PMOS transistor  311  and the twelfth NMOS transistor  309 , and is coupled to the gate of the thirteenth PMOS transistor  312 . The gate of the fourteenth PMOS transistor  313  is coupled to a junction between the fourteenth PMOS transistor  313  and the thirteenth NMOS transistor  310 , and provides the first bias voltage V casp  to the startup circuit  100 , the PTAT current generator  200  and the IPTAT current generator  400 .  
         [0090]     The second bias voltage generator  330  includes a fifteenth PMOS transistor  301  and a fifteenth NMOS transistor  305  coupled in series between the first reference voltage VDD and an eighth node  518 . In addition, a sixteenth PMOS transistor  302 , a fourteenth NMOS transistor  303  and a sixteenth NMOS transistor  304  are coupled in series between the first reference voltage VDD and the eighth node  518 . A third PNP-type bipolar junction transistor  306  is coupled in a diode configuration between the eighth node and the second reference voltage GND. The gates of the fifteenth and sixteenth PMOS transistors  301 ,  302  are coupled to the first node  240 . The gate of the fifteenth NMOS transistor  305  is coupled to a junction between the fifteenth PMOS transistor  301  and the fifteenth NMOS transistor  305 , and is coupled to a gate of the sixteenth NMOS transistor  304 . The gate of the fourteenth NMOS transistor  303  is coupled to a junction between the sixteenth PMOS transistor  302  and the fourteenth NMOS transistor  303 , and provides the second bias voltage V casn  to the PTAT current generator  200  and the startup circuit  100 . The base of the third bipolar junction transistor  306  is coupled to the second reference voltage GND.  
         [0091]     The second bias voltage V casn  can be determined as follows: 
 
 V   casn   =V   be3   +V   ds304   +V   gs303   (21) 
 
 where V be3  is the base-emitter voltage of the third bipolar junction transistor  306 , V ds304  is the drain-source voltage drop across the sixteenth NMOS transistor  304 , and V gs303  is the gate-source voltage at the fourteenth NMOS transistor  303 . 
 
         [0092]     To generate a suitable voltage for V be3 , the combination of the currents flowing through the fifteenth and sixteenth PMOS transistors  301  and  302  should, in combination, be p times the current flowing through transistor  207 , where p represents the aspect ratio of third bipolar junction transistor  306  to that of the first bipolar junction transistor  209 . It is common for p to be chosen as 1, therefore,  
                   (     W   L     )     301     +       (     W   L     )     302       =     p   ⁢           ⁢       (     W   L     )     207               (   22   )             
 
         [0093]     In view of equation (22), to generate a suitable voltage for V ds304 , it should be maintained that:  
                   (     W   L     )     304     +       (     W   L     )     305       =     p   ⁢           ⁢       (     W   L     )     201     ⁢           ⁢   and             (   23   )                     (     W   /   L     )     304         (     W   /   L     )     305       =         (     W   /   L     )     302         (     W   /   L     )     301               (   24   )             
 
         [0094]     To generate a suitable voltage for V gs303 , it should be maintained that:  
                   (     W   /   L     )     303         (     W   /   L     )     203       =           (     W   /   L     )     304         (     W   /   L     )     201       =         (     W   /   L     )     302         (     W   /   L     )     207                 (   25   )             
 
         [0095]     The first bias voltage V casp  can be determined as follows: 
 
 V   casp   =VDD+V   ds312   +V   gs313 |  (26) 
 
 where V ds312  is the drain-source voltage of the thirteenth PMOS transistor  312  and has a negative value, and V gs313  is the gate-source voltage of the fourteenth PMOS transistor  313 , and has a negative value. 
 
         [0096]     To ensure a suitable value for V ds312 , and V gs313 , the sizes of the transistors should be selected such that:  
                     (     W   /   L     )     307         (     W   /   L     )     207       ·         (     W   /   L     )     309         (     W   /   L     )     308       ·         (     W   /   L     )     312         (     W   /   L     )     311         =           (     W   /   L     )     313         (     W   /   L     )     205       ⁢           ⁢   and             (   27   )                     (     W   /   L     )     310         (     W   /   L     )     309       =         (     W   /   L     )     312         (     W   /   L     )     311               (   28   )             
 
 in order to ensure that the second, fourth and sixth PMOS transistors  206 ,  205 ,  402 , operate in the saturation region. 
 
         [0097]     The bias voltage generator  300  of  FIG. 2  is an exemplary embodiment of a voltage generator for generating the first and second bias voltages. Other embodiments for generating the first and second bias voltages are equally applicable to the principles of the present invention.  
         [0098]     The start-up circuit  100  of  FIG. 2  ensures that the PTAT current generator can overcome degenerate bias upon system start-up. Degenerate bias refers to a state in which a transistor fails to conduct current, even though the transistor is in an on state.  
         [0099]     The start-up circuit  100  includes seventeenth and a eighteenth PMOS transistors  101 ,  102  and nineteenth and twentieth NMOS transistors  105 ,  106  coupled in series between the first reference voltage VDD and the second reference voltage GND. An seventeenth NMOS transistor  103  is coupled between the first node  240  and the second reference voltage GND. An eighteenth NMOS transistor  104  is coupled between the first bias voltage V casp  and the second reference voltage GND. Gates of the seventeenth and eighteenth PMOS transistors  101 ,  102  are coupled to the second reference voltage GND. Gates of the seventeenth and eighteenth NMOS transistors  103 ,  104  are coupled to a junction between the sixteenth PMOS transistor  102  and the nineteenth NMOS transistor  105 . A gate of the nineteenth NMOS transistor  105  is coupled to the second bias voltage V casn . A gate of the twentieth NMOS transistor  106  is coupled to the second node  242 .  
         [0100]     When power is applied to the system, if transistors  204  and  202  carry no current, then transistors  105  and  106  likewise do not carry current. It follows that no current flows through transistors  101  and  102 . Therefore, the voltage at the drain node of transistor  105 , namely V st , must be high, which turns on  103  and  104 . In this case, in the start-up circuit, the voltages at the second node V gp  and the second bias voltage V casn  become low voltages. This, in turn, causes the activation of the first and second PMOS transistors  208 ,  206  and current is injected into the first and second NMOS transistors  204 ,  202 . This, in turn, raises the voltage levels of the second node V gp  and the second bias voltage V casn . As a result, transistors  201 ,  202 ,  203  and  204  are turned on, and transistors  105  and  106  are likewise turned on. A relatively small aspect ratio (W/L) (1 μm/20 μm) ratio is selected for transistors  101  and  102 , such that when transistors  101  and  102  are turned on, the voltage V st  is much less than the threshold voltage. Thereafter, when current flows through NMOS transistors  201 ,  202 ,  203  and  204 , NMOS transistors  103  and  104  are turned off, having no effect on the normal operation of the circuit. In this manner, the circuit is successfully started at power-up in a manner that overcomes degenerate bias.  
         [0101]      FIG. 3  is a circuit diagram of a third embodiment of a bias current generating circuit in accordance with the present invention. Like the second embodiment described above, the bias current generating circuit of the third embodiment includes a start-up circuit  100 A, a PTAT current generator  200 A, a bias voltage generator  300 A, an IPTAT current generator  400 A and a summing circuit  500 A.  
         [0102]     In the third embodiment, the purpose and operation of the start-up circuit  100 A, the PTAT current generator  200 A, the bias voltage generator  300 A, the IPTAT current generator  400 A and the summing circuit  500 A are essentially the same as those equivalent circuits of the first embodiment and second embodiment of  FIGS. 1 and 2 . However, in the summing circuit  100 A, PMOS transistors  103 A,  104 A are used, instead of the seventeenth and eighteenth NMOS transistors  103 ,  104 . In the PTAT current generator  200 A, NPN-type bipolar junction transistors  210 A,  209 A are positioned in series between the first reference voltage VDD and the PMOS cascode current mirror. In the second bias voltage generator  300 A, an NPN-type bipolar junction transistors  306 A, PMOS transistors  303 A,  304 A,  305 A and NMOS transistors  301 A,  302 A are employed. In the first bias voltage generator  320 A, PMOS transistors  309 A,  310 A and NMOS transistors  307 A,  308 A,  311 A,  312   a , and  313 A are used. In the IPTAT current generator  400 A, PMOS transistors  403 A,  404 A,  405 A,  406 A, and NMOS transistors  401 A,  402 A are employed. In the summing circuit  500 A, the first summing circuit current mirror  520 A comprises NMOS transistors  508 A,  509 A, the second summing circuit current mirror  530 A comprises NMOS transistor  510 A, and the third summing circuit current mirror  540 A comprises PMOS transistors  51 A,  512 A.  
         [0103]     In this manner, the third embodiment of the present invention, like the first and second embodiments above, generates a bias current I bias  that is a combination of a first sub-current I 1  that is proportional to increased temperature, and a second sub-current I 2  that is inversely proportional to increased temperature in a manner that mitigates or eliminates the effects of temperature and process variance.  
         [0104]     While this invention has been particularly shown and described with references to preferred embodiments, thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Classification (CPC): 6