Patent Abstract:
A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification of the low frequency differential inputs.

Full Description:
RELATED APPLICATIONS 
   This application claims benefit of and priority to U.S. Provisional Application Ser. No. 60/993,745 filed Sep. 14, 2007 and 60/994,077 filed Sep. 17, 2007 which are incorporated herein by this reference. 

   FIELD OF THE INVENTION 
   This invention relates to an improved low noise, low power amplifier system and more particularly to such an improved low noise, low power amplifier system which enables more precise control over gain levels. 
   BACKGROUND OF THE INVENTION 
   Amplifiers with capacitor defined gain have advantages over resistor implemented amplifiers as capacitors do not introduce noise as resistors do nor do they introduce the self heating problem that resistors do. Capacitor implemented amplifiers are very stable and if the signal varies slowly e.g. 100 Hz there can be generally a naturally high input impedance. They are also easy to drive using lower current. One shortcoming of such devices is that they do not perform well at low and near d.c. frequencies. If a low frequency signal is introduced into a capacitor the current will be very small and easily overwhelmed by stray noise current. See A LOW-POWER LOW-NOISE CMOS AMPLIFIER FOR NEURAL RECORDING APPLICATIONS by Harrison et al., IEEE Journal of Solid State Circuits, Vol. 38, No. 6, June 2003, pages 958-965 incorporated herein in its entirety by this reference. 
   SUMMARY OF THE INVENTION 
   It is therefore an object of this invention to provide an improved low noise, low power amplifier system. 
   It is a further object of this invention to provide such an improved low noise, low power amplifier system which is capable of precisely amplifying even low, and near d.c. frequencies and even d.c. 
   It is a further object of this invention to provide such an improved low noise, low power amplifier system which employs a differential approach and can independently control input common mode and output common mode levels. 
   It is a further object of this invention to provide such an improved low noise, low power amplifier system which has high input common mode rejection. 
   It is a further object of this invention to provide such an improved low noise, low power amplifier system which has rail to rail input range limited only by the switches. 
   The invention results from the realization that an improved low power, low noise amplifier system which obtains the advantages of a capacitor gain amplifier even at low, near d.c. frequencies and even at d.c. can be achieved using at least one differential amplifier with capacitor feedback whose input is coupled to an input chopper and whose output is coupled to an output chopper which choppers synchronously, selectively, alternately swap the differential input and output of the amplifier and deliver it through a low pass filter. 
   The subject invention, however, in other embodiments, need not achieve all these objectives and the claims hereof should not be limited to structures or methods capable of achieving these objectives. 
   This invention features a low power, low noise amplifier system including at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output. First and second input capacitors are interconnected with the first and second differential amplifier input terminals. First and second feedback circuits containing first and second feedback capacitors, respectively, are interconnected with the amplifier differential input and output terminals. An input chopper switch circuit receives a low frequency differential input and selectively, alternately swaps those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier. An output chopper switch receives and selectively, alternately swaps the amplifier differential outputs synchronously with the input chopper switch circuit. A low pass filter responsive to the swapped differential outputs provides a low noise, low power amplification of the low frequency differential inputs. 
   In a preferred embodiment the amplifier system may further include a second amplifier having third and fourth differential input terminals, third and fourth differential output terminals and provides a differential output. Third and fourth input capacitors are interconnected with the third and fourth differential amplifier input terminals. Third and fourth feedback circuits containing third and fourth feedback capacitors, respectively, are interconnected with the amplifier differential input and output terminals. The first and second feedback circuits may include a resistor in parallel with each feedback capacitor. The first and second feedback circuits may include a pseudo resistance element in parallel with each feedback capacitor. The input and output chopper switch circuits may be switched at a frequency that is substantially higher than the highest frequency component of the input signal. The amplifier system may further include an analog to digital converter coupled to the low pass filter output with the analog to digital converter having a sampling bandwidth that is greater than the bandwidth of the low pass filter. The amplifier system may further include a common mode feedback and offset cancellation circuit for setting the input common mode independently of the output common mode levels of the amplifier and compensating for the amplifier offset. The common mode feedback and offset cancellation circuit may include a differential output low pass filter responsive to the amplifier offset, a common mode voltage reference for defining the input common mode level, a summing circuit for combining the differential output low pass filter outputs with the common mode voltage reference, first and second voltage buffers responsive to the summing circuit, and first and second level setting resistors responsive to the first and second buffers, respectively, to apply the combined input common mode levels and offset compensation to the amplifier input terminals. The low pass filter may include a pair of capacitors, an input filter chopper circuit for selectively, alternately interconnecting the differential output of the amplifier to the capacitors and an output filter chopper circuit for selectively, alternately interconnecting the capacitors to the summing circuit in synchronism with the input filter chopper circuit and the input and output chopper circuits. The common mode feedback and offset cancellation circuit may include a common mode voltage reference interconnected with one input terminal of the amplifier to control the input common mode voltage level and an error amplifier responsive to the differential output of the low pass filter interconnected with the other input terminal of the amplifier to compensate for amplifier offset. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which: 
       FIG. 1  is a schematic diagram for an improved amplifier system according to this invention; 
       FIG. 2  is a set of traces of signals occurring in the system of  FIG. 1 ; 
       FIG. 3  is a schematic diagram of an another version of the invention of  FIG. 1  employing chopped input common mode feedback and offset compensation; 
       FIG. 4  is a schematic diagram showing the low pass filter of  FIG. 3  in more detail; 
       FIG. 5  is a view similar to  FIG. 3  showing another version of chopped input common mode feedback and offset compensation; 
       FIG. 6  is a view similar to  FIG. 3  showing yet another version of chopped input common mode feedback and offset compensation; 
       FIG. 7  is a diagram of a typical chopper switch circuit; and 
       FIG. 8  is a diagram of an amplifier with a typical pseudo resistance element usable in the system of  FIG. 1 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings. If only one embodiment is described herein, the claims hereof are not to be limited to that embodiment. Moreover, the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion, restriction, or disclaimer. 
   There is shown in  FIG. 1  an improved low power, low noise amplifier system  10 , according to this invention which includes an input chopper switch circuit  12 , also known as a swapper or cross point switch and an output chopper switch circuit  14 . Between chopper switch circuits  12  and  14  is a capacitive gain amplifier circuit  16  including differential transconductance amplifier  18 , having input capacitors  20  and  22  and feedback capacitors  24  and  26 . The gain of amplifier  18  is a function of the ratio of capacitor  20  to capacitor  24  and capacitor  22  to capacitor  26 . For example, the feedback capacitors  24  and  26  could be 2 ρF and the input capacitors  20 ,  22  could be 20 ρF for a gain of 10 or the input capacitors  20 ,  22  could be 200 ρF for a gain of 100. Chopper switch circuits  12  and  14  are operated in synchronism by a clock signal from clock  28  having a frequency F c , that is substantially higher than the highest frequency component of the input signal, for example, 100 kHz. Preferably the output chopper switch circuit  14  makes after the input chopper switch circuit  12  breaks to allow amplifier  18  to settle. The entire system  10  operates differentially and provides an output from output chopper switch circuit  14  to output filter  30  which includes a pair of resistors  32 ,  34  with capacitor  36  between them. The differential inputs to input chopper switch circuit  12  are labeled V in+   40 , V in−   42  while the differential output is labeled V out−   44  and V out+   46 . At an operating frequency of 100 kHz typically capacitor  36  will be 10 ρF and filter resistors  32  and  34  could be 200 kΩ. In operation the differential input at  40 ,  42  is chopped by input chopper switch circuit  12 , which is interconnected through capacitor  20  and  22  to the differential input of amplifier  18 . The output of input chopper switch circuit  12  is shown interconnected directly to input capacitors  20 ,  22  and then to the input terminals  50 ,  52  of amplifier  18 , but this is not a necessary limitation. For example, resistances  54 ,  56  may be disposed in series with input capacitors  20  and  22 . Similarly while feedback capacitors  24  and  26  are shown directly interconnected between the input terminals  50 ,  52  and the output terminals  58 ,  60  of amplifier  18  this is not a necessary limitation as there may be resistors  62 ,  64 , shown in phantom, in series with those feedback capacitors. After the chopped signal is gained up by amplifier  18  by a ratio of capacitor  20  to capacitor  24  or capacitor  22  to capacitor  26 , the amplified output is delivered to the output chopper switch circuit  14  which then delivers it to filter  30 . 
   Clock  28  provides a two phase signal, in the first phase the inputs  40 ,  42  are connected straight through input chopper switch circuit  12  and straight through output chopper switch circuit  14 . In the other phase inputs  40  and  42  are crossed so that input  40  goes to capacitor  22  and input  42  goes to capacitor  20 . Likewise in that other phase output chopper switch circuit  14  is crossed. In this way the low noise, low current demands of a capacitive gain amplifier are achieved while permitting low frequency, for example 10 Hz, near d.c. or even d.c. inputs to be processed. 
   Frequently the improved amplifier system  10 ,  FIG. 1 , is coupled at its output with an analog to digital converter (ADC)  47 . Analog to digital converter  47  will have a sampling bandwidth that is greater than the bandwidth of the low pass filter. By chopping the lower frequency or d.c. input to higher frequencies there results larger signal currents because the capacitors don&#39;t pass very much d.c. current. This results in a more precise gain. Although only one amplifier circuit  16  is shown there may be two or more stages as indicated by second stage amplifier circuit  16 ′. 
   The efficacy of this improved amplifier  10 ,  FIG. 1 , can be seen with reference to  FIG. 2  which is a family of traces showing the signals throughout the system. Assuming a differential input of 1 millivolt d.c. V in    70  which is the input to input chopper switch circuit  12 , the output of that input chopper switch  12  appears as the essentially square wave  72 . This is passed through input capacitors  20  and  22  to the input of amplifier  18 . Assuming a ratio of capacitor  20  to capacitor  24  and capacitor  22  to capacitor  26  of 100 to 1 there will be a gain of 100 so that the output  72  of amplifier  18  will swing between +100 and −100 millivolts. This is submitted to output chopper switch circuit  14  and after “de-chopping” appears as at  74  which is greatly magnified but shows that the output to filter  30  is between 99.85 and 99.95 millivolts, an excellent result. 
   The feedback circuit in  FIG. 1 , including feedback capacitors  24  and  26 , may further include feedback resistors  80 ,  82  in parallel with feedback capacitors  24  and  26 . These are typically very high impedance devices, 1 GΩ or greater. These present a very large impedance effecting only a unity gain but allow a very small current to flow when there is a difference between the input and output of amplifier  18 . These feedback circuits have very little current noise and present very high impedance at 100 kHz. The use of a 1 GΩ resistor allows d.c. to flow at very low frequency when the feedback capacitor is blocking. Without that feedback resistor the input could saturate the amplifier. 
   This invention also contemplates a common mode feedback and offset cancellation circuit  90 ,  FIG. 3 . Common mode feedback and offset cancellation circuit  90  includes low pass filter,  92 , which receives the differential output of amplifier  18  and provides time averaged positive and negative averages V 0posavg    94  and V 0negavg    96  to a summing circuit  98  including series summing resistors  100  and  102  and parallel summing resistors  104 ,  106  which may be in the neighborhood of 1 GΩ and are both connected to the output of voltage reference  108  which provides the common mode reference voltage V cm . These time averaged positive and negative outputs on lines  94  and  96  and the common mode voltage from source  108  are combined in the summing circuit  98  and delivered to buffers  110  and  112  which through level setting resistors  114  and  116 , typically 1 GΩ, are interconnected to the differential input amplifier  18  and thus provide for any offset of amplifier  18  as well as compensation for the time average drift of the differential output. 
   Low pass filter  92  is shown in greater detail in  FIG. 4 , as including capacitors  120 ,  124  between an input filter chopper switch circuit  126  and output filter chopper switch circuit  128 . The differential output from amplifier  18  is fed to input filter chopper switch circuit  126  whose output is interconnected through capacitors  120  and  124  to output filter chopper switch circuit  128  whose output in turn provides the time averaged outputs at  94  and  96  to summing circuit  98 . In this particular case summing circuit  98  has added filter capacitors  130  and  132 . Common mode reference voltage source  108  is shown as a battery  134  and voltage buffers  110  and  112  are shown implemented with field effect transistors. Chopper switch circuits  126 , and  128  are operated by clock circuit F c  from clock  28 ,  FIG. 1 , as are chopper switch circuits  12  and  14 ,  FIG. 4 , all of which are operated in synchronism. In this embodiment with but one amplifier circuit  16  input chopper switch circuit  12  is connected straight through while input chopper switch circuit  14  is crossed. Were there two stages the double inversion would require the output chopper switch  14  to be connected straight through also. Input filter chopper circuit  126  is crossed while output filter chopper circuit  128  is connected straight through. 
   The output of common mode feedback and offset cancellation circuit  90  in  FIG. 3 , and  90   a  in  FIG. 4  provides common mode voltage equally to both differential inputs through level setting resistors  114  and  116  and the offset correction is also split between the input terminals  50 ,  52  of amplifier  18 , but this is not a necessary limitation of the invention. For example, as shown in  FIG. 5  where the summing circuits and voltage buffers of  FIG. 3  have been replaced with error amplifier  140 . Here the common mode voltage reference V cm    108   a  is connected through 1 GΩ resistor  114  directly to one input  50  of amplifier  18  so that it introduces the compensation common mode voltage signal on one of the differential inputs only. Similarly the time averaged offset error output of error amplifier  140  is delivered through 1 GΩ resistor  116  to the other input terminal  52  of amplifier  18  so that the offset cancellation occurs on only one of the differential inputs. 
   In yet another embodiment error amplifier  142 ,  FIG. 6 , can be a fully differential error amplifier. V icm  at the output of differential error amplifier  142  is the output common mode voltage of that error amplifier and it is the input common mode voltage for amplifier  18  so this embodiment once again provides a balanced offset cancellation and common mode voltage level application to the differential input of amplifier  18 . As shown with reference to  FIGS. 3 ,  4 ,  5 , and  6  there is close control over the input common mode to capacitors  20 ,  22 . This coupled with the ability inherent in every differential amplifier  18  to control its common mode output, enables the system to control both the input and the output common mode levels resulting in a much higher input common mode rejection and a better rail to rail input range. 
   As indicated previously chopper switch circuits  12 ,  14 ,  126  and  128  may be any variety of swapper circuits or cross point switches. A typical simplified schematic depiction of one is shown in  FIG. 7  indicated at  12   a  as containing four switches  150 ,  152 ,  154  and  156 . In one phase of the clock signal F c  switches  150  and  156  are open, switches  152  and  154  are closed which provides the cross over mode. In the other phase switches  150  and  156  would be closed and switches  152  and  154  would be open providing the straight through mode. 
   Although in  FIG. 1  it was disclosed that feedback capacitors  24  and  26  could have high impedance resistances  80  and  82  in parallel with them an alternative to that is the use of pseudo resistances as taught by A LOW-POWER LOW-NOISE CMOS AMPLIFIER FOR NEURAL RECORDING APPLICATIONS by Harrison et al., IEEE Journal of Solid State Circuits, Vol. 38, No. 6, June 2003, pages 958-965 incorporated fully herein by this reference. There a pair of field effect transistors  180 ,  182 ,  FIG. 8 , are connected in series with each other and in parallel with capacitor  24 . A similar circuit (not shown) would be used with respect to capacitor  26 . Transistors  180  and  182  turn on when there is a difference between the input and output of amplifier  18 . They are generally biased to the nearly off position: they conduct a very low current when necessary and approximate a very large impedance in the GΩ range maintaining a unity gain. 
   Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments. 
   In addition, any amendment presented during the prosecution of the patent application for this patent is not a disclaimer of any claim element presented in the application as filed: those skilled in the art cannot reasonably be expected to draft a claim that would literally encompass all possible equivalents, many equivalents will be unforeseeable at the time of the amendment and are beyond a fair interpretation of what is to be surrendered (if anything), the rationale underlying the amendment may bear no more than a tangential relation to many equivalents, and/or there are many other reasons the applicant can not be expected to describe certain insubstantial substitutes for any claim element amended. 
   Other embodiments will occur to those skilled in the art and are within the following claims.

Technology Classification (CPC): 7