Patent Abstract:
A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. Ser. No. 11/088,072, filed Mar. 23, 2005 now U.S. Pat. No. 7,094,680, which is a continuation of U.S. Ser. No. 09/776,329, filed Feb. 2, 2001 now U.S. Pat. No. 6,951,804, both of which are hereby incorporated by reference in their entireties. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to formation of one or more barrier layers and, more particularly, to one or more barrier layers formed using chemisorption techniques. 
   2. Description of the Related Art 
   In manufacturing integrated circuits, one or more barrier layers are often used to inhibit diffusion of one or more materials in metal layers, as well as other impurities from intermediate dielectric layers, into elements underlying such barrier layers, such as transistor gates, capacitor dielectrics, transistor wells, transistor channels, electrical barrier regions, interconnects, among other known elements of integrated circuits. 
   Though a barrier layer may limit to prevent migration of unwanted materials into such elements, its introduction creates an interface at least in part between itself and one or more metal layers. For sub half-micron (0.5 μm) semiconductor devices, microscopic reaction at an interface between metal and barrier layers can cause degradation of integrated circuits, including but not limited to increased electrical resistance of such metal layers. Accordingly, though barrier layers have become a component for improving reliability of interconnect metallization schemes, it is desirable to mitigate “side effects” caused by introduction of such barrier layers. 
   Compounds of refractory metals such as, for example, nitrides, borides, and carbides are targets as diffusion barriers because of their chemical inertness and low resistivities (e.g., sheet resistivities typically less than about 200 μΩ-cm). In particular, borides such as, including but not limited to titanium diboride (TiB 2 ), have been used as a barrier material owing to their low sheet resistivities (e.g., resistivities less than about 150 μΩ-cm). 
   Boride barrier layers are conventionally formed using chemical vapor deposition (CVD) techniques. For example, titanium tetrachloride (TiCl 4 ) may be reacted with diborane (B 2 H 6 ) to form titanium diboride (TiB 2 ) using CVD. However, when Cl-based chemistries are used to form boride barrier layers, reliability problems can occur. In particular, boride layers formed using CVD chlorine-based chemistries typically have a relatively high chlorine (Cl) content, namely, chlorine content greater than about 3 percent. A high chlorine content is undesirable because migrating chlorine from a boride barrier layer into adjacent interconnection layer may increase contact resistance of such interconnection layer and potentially change one or more characteristics of integrated circuits made therewith. 
   Therefore, a need exists for barrier layers for integrated circuit fabrication with little to no side effects owing to their introduction. Particularly desirable would be a barrier layer useful for interconnect structures. 
   SUMMARY OF THE INVENTION 
   An aspect of the present invention is film deposition for integrated circuit fabrication. More particularly, at least one element from a first precursor and at least one element from a second precursor is chemisorbed on a surface. The at least one element from the first precursor and the at least one element from the second precursor are chemisorbed to provide a tantalum-nitride film. This sequence may be repeated to increase tantalum-nitride layer thickness. This type of deposition process is sometimes called atomic layer deposition (ALD). Such a tantalum-nitride layer may be used as a barrier layer. 
   Another aspect is forming the tantalum-nitride layer using in part annealing of at least one tantalum-nitride sublayer. This annealing may be done with a plasma. 
   Another aspect is using a plasma source gas as a nitrogen precursor. The plasma source gas may be used to provide a plasma, which may be sequentially reacted or co-reacted with a tantalum containing precursor. 
   In another aspect, a method of film deposition for integrated circuit fabrication includes forming a tantalum nitride layer by sequentially chemisorbing a tantalum precursor and a nitrogen precursor on a substrate disposed in a process chamber. A nitrogen concentration of the tantalum nitride layer is reduced by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer. 
   In another aspect, a method of film deposition for integrated circuit fabrication includes forming a tantalum nitride layer with a first nitrogen concentration on a substrate by an atomic layer deposition process. An upper portion of the tantalum nitride layer is exposed to a plasma annealing process to form a tantalum-containing layer with a second nitrogen concentration. A metal-containing layer is then deposited on the tantalum-containing layer. 
   In another aspect, a method of film deposition for integrated circuit fabrication includes forming a tantalum-containing layer with a sheet resistance of about 1,200 μΩ-cm or less by a plasma annealing process on a tantalum nitride layer deposited by an atomic layer deposition process on a substrate. 
   In yet another aspect, a method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is then deposited on the tantalum nitride layer by a deposition process. 
   These and other aspects of the present invention will be more apparent from the following description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
       FIGS. 1 and 4  depict schematic illustrations of exemplary portions of process systems in accordance with one or more integrated circuit fabrication aspects of the present invention; 
       FIGS. 2   a - 2   c  depict cross-sectional views of a substrate structure at different stages of integrated circuit fabrication; 
       FIGS. 3   a - 3   c  depict cross-sectional views of a substrate at different stages of chemisorption to form a barrier layer; and 
       FIG. 5  depicts a cross-sectional view of a substrate structure at different stages of integrated circuit fabrication incorporating one or more tantalum-nitride barrier sublayers post plasma anneal. 
   

   DETAILED DESCRIPTION 
     FIG. 1  depicts a schematic illustration of a wafer processing system  10  that can be used to form one or more tantalum-nitride barrier layers in accordance with aspects of the present invention described herein. System  10  comprises process chamber  100 , gas panel  130 , control unit  110 , along with other hardware components such as power supply  106  and vacuum pump  102 . For purposes of clarity, salient features of process chamber  100  are briefly described below. 
   Process Chamber 
   Process chamber  100  generally houses a support pedestal  150 , which is used to support a substrate such as a semiconductor wafer  190  within process chamber  100 . Depending on process requirements, semiconductor wafer  190  can be heated to some desired temperature or within some desired temperature range prior to layer formation using heater  170 . 
   In chamber  100 , wafer support pedestal  150  is heated by an embedded heating element  170 . For example, pedestal  150  may be resistively heated by applying an electric current from an AC power supply  106  to heating element  170 . Wafer  190  is, in turn, heated by pedestal  150 , and may be maintained within a desired process temperature range of, for example, about 20 degrees Celsius to about 500 degrees Celsius. 
   Temperature sensor  172 , such as a thermocouple, may be embedded in wafer support pedestal  150  to monitor the pedestal temperature of 150 in a conventional manner. For example, measured temperature may be used in a feedback loop to control electric current applied to heating element  170  from power supply  106 , such that wafer temperature can be maintained or controlled at a desired temperature or within a desired temperature range suitable for a process application. Pedestal  150  may optionally be heated using radiant heat (not shown). 
   Vacuum pump  102  is used to evacuate process gases from process chamber  100  and to help maintain a desired pressure or desired pressure within a pressure range inside chamber  100 . Orifice  120  through a wall of chamber  100  is used to introduce process gases into process chamber  100 . Sizing of orifice  120  conventionally depends on the size of process chamber  100 . 
   Orifice  120  is coupled to gas panel  130  in part by valve  125 . Gas panel  130  is configured to receive and then provide a resultant process gas from two or more gas sources  135 ,  136  to process chamber  100  through orifice  120  and valve  125 . Gas sources  135 ,  136  may store precursors in a liquid phase at room temperature, which are later heated when in gas panel  130  to convert them to a vapor-gas phase for introduction into chamber  100 . Gas panel  130  is further configured to receive and then provide a purge gas from purge gas source  138  to process chamber  100  through orifice  120  and valve  125 . 
   Control unit  110 , such as a programmed personal computer, work station computer, and the like, is configured to control flow of various process gases through gas panel  130  as well as valve  125  during different stages of a wafer process sequence. Illustratively, control unit  110  comprises central processing unit (CPU)  112 , support circuitry  114 , and memory  116  containing associated control software  113 . In addition to control of process gases through gas panel  130 , control unit  110  may be configured to be responsible for automated control of other activities used in wafer processing—such as wafer transport, temperature control, chamber evacuation, among other activities, some of which are described elsewhere herein. 
   Control unit  110  may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. CPU  112  may use any suitable memory  116 , such as random access memory, read only memory, floppy disk drive, hard disk, or any other form of digital storage, local or remote. Various support circuits may be coupled to CPU  112  for supporting system  10 . Software routines  113  as required may be stored in memory  116  or executed by a second computer processor that is remotely located (not shown). Bi-directional communications between control unit  110  and various other components of wafer processing system  10  are handled through numerous signal cables collectively referred to as signal buses  118 , some of which are illustrated in  FIG. 1 . 
   Barrier Layer Formation 
     FIGS. 2   a - 2   c  illustrate exemplary embodiment portions of tantalum-nitride layer formation for integrated circuit fabrication of an interconnect structure in accordance with one or more aspects of the present invention. For purposes of clarity, substrate  200  refers to any workpiece upon which film processing is performed, and substrate structure  250  is used to denote substrate  200  as well as other material layers formed on substrate  200 . Depending on processing stage, substrate  200  may be a silicon semiconductor wafer, or other material layer, which has been formed on wafer  190  (shown in  FIG. 1 ). 
     FIG. 2   a , for example, shows a cross-sectional view of a substrate structure  250 , having a dielectric layer  202  thereon. Dielectric layer  202  may be an oxide, a silicon oxide, carbon-silicon-oxide, a fluoro-silicon, a porous dielectric, or other suitable dielectric formed and patterned to provide contact hole or via  202 H extending to an exposed surface portion  202 T of substrate  200 . More particularly, it will be understood by those with skill in the art that the present invention may be used in a dual damascene process flow. 
     FIG. 2   b  illustratively shows tantalum-nitride layer  204  formed on substrate structure  250 . Tantalum-nitride layer  204  is formed by chemisorbing monolayers of a tantalum containing compound and a nitrogen containing compound on substrate structure  250 . 
   Referring to  FIG. 2   c , after the formation of tantalum-nitride layer  204 , a portion of layer  204  may be removed by etching in a well-known manner to expose a portion  202 C of substrate  200 . Portion  202 C may be part of a transistor gate stack, a capacitor plate, a node, a conductor, or like conductive element. Next, contact layer  206  may be formed thereon, for example, to form an interconnect structure. Contact layer  206  may be selected from a group of aluminum (Al), copper (Cu), tungsten (W), and combinations thereof. 
   Contact layer  206  may be formed, for example, using chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or a combination thereof. For example, an aluminum (Al) layer may be deposited from a reaction of a gas mixture containing dimethyl aluminum hydride (DMAH) and hydrogen (H 2 ) or argon (Ar) or other DMAH containing mixtures, a CVD copper layer may be deposited from a gas mixture containing Cu(hfac) 2  (copper (II) hexafluoro acetylacetonate), Cu(fod) 2  (copper (II) heptafluoro dimethyl octanediene), Cu(hfac) TMVS (copper (I) hexafluoro acetylacetonate trimethylvinylsilane) or combinations thereof, and a CVD tungsten layer may be deposited from a gas mixture containing tungsten hexafluoride (WF 6 ). A PVD layer is deposited from a copper target, an aluminum target, or a tungsten target. 
   Moreover, layer  206  may be a refractory metal compound including but not limited to titanium (Ti), tungsten (W), tantalum (Ta), zirconium (Zr), hafnium (Hf), molybdenum (Mo), niobium (Nb), vanadium (V), and chromium (Cr), among others. Conventionally, a refractory metal is combined with reactive species, such as for example chlorine (Cl) or fluorine (F), and is provided with another gas to form a refractory metal compound. For example, titanium tetrachloride (TiCl 4 ), tungsten hexafluoride (WF 6 ), tantalum pentachloride (TaCl 5 ), zirconium tetrachloride (ZrCl 4 ), hafnium tetrachloride (HfCl 4 ), molybdenum pentachloride (MOCl 5 ), niobium pentachloride (NbCl 5 ), vanadium pentachloride (VCl 5 ), or chromium tetrachloride (CrCl 4 ) may be used as a refractory metal-containing compound gas. 
   Though layer  206  is shown as formed on layer  204 , it should be understood that layer  204  may be used in combination with one or more other barrier layers formed by CVD or PVD. Accordingly, layer  204  need not be in direct contact with layer  206 , but an intervening layer may exist between layer  206  and layer  204 . 
   Monolayers are chemisorbed by sequentially providing a tantalum containing compound and a nitrogen containing compound to a process chamber. Monolayers of a tantalum containing compound and a nitrogen containing compound are alternately chemisorbed on a substrate  300  as illustratively shown in  FIGS. 3   a - 3   c.    
     FIG. 3   a  depicts a cross-sectional view of an exemplary portion of substrate  300  in a stage of integrated circuit fabrication, and more particularly at a stage of barrier layer formation. Tantalum layer  305  is formed by chemisorbing a tantalum-containing compound on surface portion  300 T of substrate  300  by introducing a pulse of a tantalum containing gas  135  (shown in  FIG. 1 ) into process chamber  100  (shown in  FIG. 1 ). Tantalum containing gas  135  (shown in  FIG. 1 ) may be a tantalum based organometallic precursor or a derivative thereof. Examples of such precursors include but are not limited to pentakis(ethylmethylamino) tantalum (PEMAT; Ta(N(Et)Me) 5 ), pentakis(diethylamino) tantalum (PDEAT; Ta(NEt 2 ) 5 ), pentakis(dimethylamino) tantalum (PDMAT; Ta(NMe 2 ) 5 ) or a derivative thereof. Other tantalum containing precursors include TBTDET (tBuNTa(NEt 2 ) 3  or C 16 H 39 N 4 Ta), tantalum halides (e.g., TaX 5 , where X is F, B or C) or a derivative thereof. 
   Wafer  190  is maintained approximately below a thermal decomposition temperature of a selected tantalum precursor or a derivative thereof to be used and maintained at a pressure of approximately less than 100 Torr. Additionally, wafer  190  may be heated by heating element  170 . An exemplary temperature range for precursors identified herein is approximately 20 to 400 degrees Celsius. For example, approximately 150 to 300 degrees Celsius may be used for PEMAT. 
   Though temperatures below a thermal decomposition temperature may be used, it should be understood that other temperatures, namely those above a thermal decomposition temperature, may be used. An example temperature ranges above a thermal decomposition temperature is approximately 400 to 600 degrees Celsius. Accordingly, some thermal decomposition may occur; however, the main, more than 50 percent, deposition activity is by chemisorption. More generally, wafer surface temperature needs to be high enough to induce significant chemisorption of precursors instead of physisorption, but low enough to prevent significant decomposition of precursors. If the amount of decomposition during each precursor deposition is significantly less than a layer, then the primary growth mode will be ALD. Accordingly, such a film will tend to have ALD properties. However, it is possible if a precursor significantly decomposes, but an intermediate reactant is obtained preventing further precursor decomposition after a layer of intermediate reactant is deposited, then an ALD growth mode may still be obtained. 
   While not wishing to be bound by theory, it is believed that this tantalum-containing precursor combines tantalum atoms with one or more reactive species. During tantalum layer  305  formation, these reactive species form byproducts that are transported from process chamber  100  by vacuum system  102  while leaving tantalum deposited on surface portion  300 T. However, composition and structure of precursors on a surface during atomic-layer deposition (ALD) is not precisely known. A precursor may be in an intermediate state when on a surface of wafer  190 . For example, each layer may contain more than simply elements of tantalum (Ta) or nitrogen (N); rather, the existence of more complex molecules having carbon (C), hydrogen (H), and/or oxygen (O) is probable. Additionally, a surface may saturate after exposure to a precursor forming a layer having more or less than a monolayer of either tantalum (Ta) or nitrogen (N). This composition or structure will depend on available free energy on a surface of wafer  190 , as well as atoms or molecules involved. Once all available sites are occupied by tantalum atoms, further chemisorption of tantalum is blocked, and thus the reaction is self-limiting. 
   After layer  305  of a tantalum containing compound is chemisorbed onto substrate  300 , excess tantalum containing compound is removed from process chamber  10  by vacuum system  102  (shown in  FIG. 1 ). Additionally, a pulse of purge gas  138  (shown in  FIG. 1 ) may be supplied to process chamber  10  to facilitate removal of excess tantalum containing compound. Examples of suitable purge gases include but are not limited to helium (He), nitrogen (N 2 ), argon (Ar), and hydrogen (H 2 ), among others, and combinations thereof that may be used. 
   With continuing reference to  FIGS. 3   a - c  and renewed reference to  FIG. 1 , after process chamber  100  has been purged, a pulse of ammonia gas (NH 3 ) 136 is introduced into process chamber  100 . Process chamber  100  and wafer  190  may be maintained at approximately the same temperature and pressure range as used for formation of layer  305 . 
   In  FIG. 3   b , a layer  307  of nitrogen is illustratively shown as chemisorbed on tantalum layer  305  at least in part in response to introduction of ammonia gas  136 . While not wishing to be bound by theory, it is believed that nitrogen layer  307  is formed in a similar self-limiting manner as was tantalum layer  305 . Each tantalum layer  305  and nitrogen layer  307  in any combination and in direct contact with one another form a sublayer  309 , whether or not either or both or neither is a monolayer. Though ammonia gas is used, other N containing precursors gases may be used including but not limited to N x H y  for x and y integers (e.g., N 2 H 4 ), N 2  plasma source, NH 2 N(CH 3 ) 2 , among others. 
   After an ammonia gas compound is chemisorbed onto tantalum layer  305  on substrate  300  to form nitrogen monolayer  307 , excess ammonia gas compound is removed from process chamber  10  by vacuum system  102 , and additionally, a pulse of purge gas  138  may be supplied to process chamber  10  to facilitate this removal. 
   Thereafter, as shown in  FIG. 3   c , tantalum and nitrogen layer deposition in an alternating sequence may be repeated with interspersed purges until a desired layer  204  thickness is achieved. Tantalum-nitride layer  204  may, for example, have a thickness in a range of approximately 0.0002 microns (2 Angstrom) to about 0.05 microns (500 Angstrom), though a thickness of approximately 0.001 microns (10 Angstrom) to about 0.005 microns (50 Angstrom) may be a sufficient barrier. Moreover, a tantalum-nitride layer  204  may be used as a thin film insulator or dielectric, or may be used as a protective layer for example to prevent corrosion owing to layer  204  being relatively inert or non-reactive. Advantageously, layer  204  may be used to coat any of a variety of geometries. 
   In  FIGS. 3   a - 3   c , tantalum-nitride layer  204  formation is depicted as starting with chemisorption of a tantalum containing compound on substrate  300  followed by chemisorption of a nitrogen containing compound. Alternatively, chemisorption may begin with a layer of a nitrogen containing compound on substrate  300  followed by a layer of a tantalum containing compound. 
   Pulse time for each pulse of a tantalum containing compound, a nitrogen containing compound, and a purge gas is variable and depends on volume capacity of a deposition chamber  100  employed as well as vacuum system  102  coupled thereto. Similarly, time between each pulse is also variable and depends on volume capacity of process chamber  100  as well as vacuum system  102  coupled thereto. However, in general, wafer  190  surface must be saturated by the end of a pulse time, where pulse time is defined as time a surface is exposed to a precursor. There is some variability here, for example (1) a lower chamber pressure of a precursor will require a longer pulse time; (2) a lower precursor gas flow rate will require a longer time for chamber pressure to rise and stabilize requiring a longer pulse time; and (3) a large-volume chamber will take longer to fill, longer for chamber pressure to stabilize thus requiring a longer pulse time. In general, precursor gases should not mix at or near the wafer surface to prevent co-reaction (a co-reactive embodiment is disclosed elsewhere herein), and thus at least one gas purge or pump evacuation between precursor pulses should be used to prevent mixing. 
   Generally, a pulse time of less than about 1 second for a tantalum containing compound and a pulse time of less than about 1 second for a nitrogen containing compound is typically sufficient to chemisorb alternating monolayers that comprise tantalum-nitride layer  204  on substrate  300 . A pulse time of less than about 1 second for purge gas  138  is typically sufficient to remove reaction byproducts as well as any residual materials remaining in process chamber  100 . 
   Sequential deposition as described advantageously provides good step coverage and conformality, due to using a chemisorption mechanism for forming tantalum-nitride layer  204 . With complete or near complete saturation after each exposure of wafer  190  to a precursor, each of uniformity and step coverage is approximately 100 percent. Because atomic layer deposition is used, precision controlled thickness of tantalum-nitride layer  204  may be achieved down to a single layer of atoms. Furthermore, in ALD processes, since it is believed that only about one atomic layer may be absorbed on a topographic surface per “cycle,” deposition area is largely independent of the amount of precursor gas remaining in a reaction chamber once a layer has been formed. By “cycle,” it is meant a sequence of pulse gases, including precursor and purge gases, and optionally one or more pump evacuations. Also, by using ALD, gas-phase reactions between precursors are minimized to reduce generation of unwanted particles. 
   Co-Reaction 
   Though it has been described to alternate tantalum and nitrogen containing precursors and purging in between as applied in a sequential manner, another embodiment is to supply tantalum and nitrogen containing precursors simultaneously. Thus, pulses of gases  135  and  136 , namely, tantalum and nitrogen containing compounds, are both applied to chamber  100  at the same time. An example is PEMAT and NH 3 , though other tantalum-organic and nitrogen precursors may be used. Step coverage and conformality is good at approximately 95 to 100 percent for each. Moreover, deposition rate is approximately 0.001 to 0.1 microns per second. Because a co-reaction is used, purging between sequential pulses of alternating precursors is avoided, as is done in ALD. 
   Wafer surface temperature is maintained high enough to sustain reaction between two precursors. This temperature may be below chemisorption temperature of one or both precursors. Accordingly, temperature should be high enough for sufficient diffusion of molecules or atoms. 
   Wafer surface temperature is maintained low enough to avoid significant decomposition of precursors. However, more decomposition of precursors may be acceptable for co-reaction than for sequentially reacting precursors in an ALD process. In general, wafer  190  surface diffusion rate of molecules or atoms should be greater than precursors&#39; reaction rate which should be greater precursors&#39; decomposition rate. 
   For all other details, the above-mentioned description for sequentially applied precursors applies to co-reaction processing. 
   Plasma Anneal 
   After forming one or more combinations of layers  305  and  307 , substrate structure  250  may be plasma annealed. Referring to  FIG. 4 , there is illustratively shown a schematic diagram of an exemplary portion of a process system  10 P in accordance with an aspect of the present invention. Process system  10 P is similar to process system  10 , except for additions of one or more RF power supplies  410  and  412 , showerhead  400 , gas source  405 , and matching network(s)  411 . Notably, a separate plasma process system may be used; however, by using a CVD/PVD process system  10 P, less handling of substrate structure  250  is involved, as layer  204  may be formed and annealed in a same chamber  100 . 
   Showerhead  400  and wafer support pedestal  150  provide in part spaced apart electrodes. An electric field may be generated between these electrodes to ignite a process gas introduced into chamber  100  to provide a plasma  415 . In this embodiment, argon is introduced into chamber  100  from gas source  405  to provide an argon plasma. However, if argon is used as a purge gas, gas source  405  may be omitted for gas source  138 . 
   Conventionally, pedestal  150  is coupled to a source of radio frequency (RF) power source  412  through a matching network  411 , which in turn may be coupled to control unit  110 . Alternatively, RF power source  410  may be coupled to showerhead  400  and matching network  411 , which in turn may be coupled to control unit  110 . Moreover, matching network  411  may comprise different circuits for RF power sources  410  and  412 , and both RF power sources  410  and  412  may be coupled to showerhead  400  and pedestal  150 , respectively. 
   With continuing reference to  FIG. 4  and renewed reference to  FIG. 3   c , substrate structure  250  having one or more iterations or tantalum-nitride sublayers  309  is located in process chamber  401 . Argon (Ar) gas from gas source  405  is introduced into chamber  401  to plasma anneal substrate structure  250 . While not wishing to be bound by theory, it is believed that plasma annealing reduces nitrogen content of one or more sublayers  309  by sputtering off nitrogen, which in turn reduces resistivity. In other words, plasma annealing is believed to make tantalum-nitride layer  204  more tantalum-rich as compared to a non-plasma annealed tantalum-nitride layer  204 . For example, a 1:1 Ta:N film may be annealed to a 2:1 Ta:N film. Tantalum-nitride films having a sheet resistance of approximately equal to or less than 1200 microohms-cm for 0.004 micron (40 Angstrom) films may be achieved. 
   It will be appreciated that other non-chemically reactive gases with respect to layer  204  may be used for physically displacing nitrogen from layer  204 , including but not limited to neon (Ne), xenon (Xe), helium (He), and hydrogen (H 2 ). Generally, for a plasma-gas that does not chemically react with a tantalum-nitride film, it is desirable to have a plasma-gas atom or molecule with an atomic-mass closer to N than to Ta in order to have preferential sputtering of the N. However, a chemically reactive process may be used where a gas is selected which preferentially reacts for removal of N while leaving Ta. 
   Referring to  FIG. 5 , there is illustratively shown a cross sectional view of layer  204  after plasma annealing in accordance with a portion of an exemplary embodiment of the present invention. Plasma annealing may be done after formation of each nitrogen layer  307 , or may be done after formation of a plurality of layers  307 . With respect to the latter, plasma annealing may take place after approximately every 0.003 to 0.005 microns (30 to 50 Angstroms) of layer  204  or after formation of approximately every 7 to 10 sublayers  309 . However, plasma annealing may be done after formation of a sublayer  309 , which is approximately 0.0001 to 0.0004 microns (1 to 4 Angstroms). 
   Plasma annealing with argon may be done with a wafer temperature in a range of approximately 20 to 450 degrees Celsius and a chamber pressure of approximately 0.1 to 50 Torr with a flow rate of argon in a range of approximately 10 to 2,000 standard cubic centimeters per minute (sccm) with a plasma treatment time approximately equal to or greater than one second. Generally, a tantalum-nitride film should be annealed at a temperature, which does not melt, sublime, or decompose such a tantalum-nitride film. 
   The specific process conditions disclosed in the above description are meant for illustrative purposes only. Other combinations of process parameters such as precursor and inert gases, flow ranges, pressure ranges and temperature ranges may be used in forming a tantalum-nitride layer in accordance with one or more aspects of the present invention. 
   Although several preferred embodiments, which incorporate the teachings of the present invention, have been shown and described in detail, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. By way of example and not limitation, it will be apparent to those skilled in the art that the above-described formation is directed at atomic layer CVD (ALCVD); however, low temperature CVD may be used as described with respect to co-reacting precursors. Accordingly, layers  305  and  307  need not be monolayers. Moreover, it will be appreciated that the above described embodiments of the present invention will be particularly useful in forming one or more barrier layers for interconnects on semiconductor devices having a wide range of applications. 
   While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Technology Classification (CPC): 7