Patent Abstract:
Methods for forming conductors and global bus configurations for reducing an interference signal from electromagnetic interference (EMI) source are provided. First and second conductor lines are formed on an integrated circuit in a twisted pair configuration. A differential amplifier is formed on the integrated circuit and coupled to each of the first and second conductor lines. The first and second signals are respectively transmitted through the first and second conductor lines and are modified by the interference signal. The modified first and second signals are differentially amplified by the differential amplifier so that the interference signal is substantially cancelled.

Full Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to CMOS imagers, in particularly, methods for reducing an interference signal to a global bus and a fabrication of a global bus of a CMOS image sensor. 
       BACKGROUND OF THE INVENTION 
       [0002]    Image sensors find applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications and consumer products. In many smart image sensors, it is desirable to integrate on chip circuitry to control the image sensor and to perform signal and image processing on the output image. Charge-coupled devices (CCDs), which have been one of the dominant technologies used for image sensors, however, do not easily lend themselves to large scale signal processing and are not easily integrated with complimentary metal oxide semiconductor (CMOS) circuits. 
         [0003]    CMOS image sensors are increasing being developed to handle applications having increased frame rates. In order to provide an increased frame rate, CMOS image sensors typically use a multi-channel read out of pixels of the image sensor. The multi-channel readout may be used to increase the frame rate, even with limitations in an amplifier speed of a gain stage and a speed of an analog-to-digital (ADC) conversion stage of the CMOS image sensor. Different channels of image sensor may be susceptible to different levels of electromagnetic interference (EMI) from an EMI source, such as another signal line on the image sensor. Because a multi-channel readout is used, any asymmetrical differential coupling among the channels of the CMOS image sensor may produce a channel mismatch into the ADC conversion stage. The resulting digitized image may include a column fixed pattern noise (FPN). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The invention is best understood from the following detailed description when read in connection with the accompanied drawing. Included in the drawing are the following figures: 
           [0005]      FIG. 1  is a block diagram illustrating a CMOS image sensor system; 
           [0006]      FIG. 2  is a circuit diagram illustrating a global bus between column sample and hold (S/H) circuitry and amplifier circuitry of the CMOS image sensor of  FIG. 1 ; 
           [0007]      FIG. 3A  is a block diagram illustrating conductor layout including a global bus; 
           [0008]      FIG. 3B  is a cross section diagram along line A-A′ illustrating parasitic capacitance coupled to the global bus due to the conductor layout shown in  FIG. 3A ; 
           [0009]      FIG. 3C  is a circuit diagram of the amplifier circuitry during column readout, including the parasitic capacitance shown in  FIG. 3B ; 
           [0010]      FIG. 3D  is a circuit diagram illustrating one channel of a global bus and different parasitic capacitances that may be coupled to the global bus; 
           [0011]      FIG. 4A  is a block diagram of a conductor layout including a global bus configuration according to an embodiment of the present invention; 
           [0012]      FIGS. 4B and 4C  are cross section diagrams illustrating a parasitic capacitance coupled to the global bus due to the conductor layout shown in  FIG. 4A , along respective lines A-A′ and B-B′; 
           [0013]      FIG. 4D  is a circuit diagram of the amplifier circuitry during column readout, including the parasitic capacitance shown in  FIGS. 4B and 4C ; 
           [0014]      FIG. 5  is a block diagram of a conductor layout including a global bus configuration according to another embodiment of the present invention; 
           [0015]      FIG. 6A  is an overhead view illustrating a portion of a global bus configuration; 
           [0016]      FIG. 6B  is a cross section of the global bus configuration shown in  FIG. 6A  along line A-A′; 
           [0017]      FIG. 7A  is an overhead view of a portion of a global bus configuration according to an embodiment of the present invention; 
           [0018]      FIG. 7B  is an exploded overhead view of the portion of the global bus shown in  FIG. 7A , illustrating a twist in a portion of the signal and reset busses; 
           [0019]      FIGS. 7C ,  7 D and  7 E are cross sectional diagrams of the global bus configuration shown in  FIG. 7A , along respective lines A-A′, B-B′ and C-C′; 
           [0020]      FIG. 8A  is an overhead view of a global bus formed from a number of the signal and reset bus twists shown in  FIG. 7A , according to an embodiment of the present invention; 
           [0021]      FIG. 8B  is an exploded overhead view of the global bus shown in  FIG. 8A ; 
           [0022]      FIG. 9A  is a cross section diagram of the global bus configuration shown in  FIG. 6A , along line A-A′, illustrating an example of width dimensions of the global bus; 
           [0023]      FIG. 9B  is a cross section diagram of the global bus configuration shown in  FIG. 7A  along line C-C′, illustrating an example of width dimensions of the global bus, according to an embodiment of the present invention; 
           [0024]      FIG. 9C  is a cross section diagram with respect to a length of the global bus configuration shown in  FIG. 6A ; 
           [0025]      FIG. 9D  is a cross section diagram along a length of the global bus configuration shown in  FIG. 8A , illustrating a twisted pair configuration, according to an embodiment of the invention; 
           [0026]      FIG. 9E  is a cross section diagram of the global bus configuration shown in  FIG. 6A , illustrating various parasitic capacitances coupled to the global bus; 
           [0027]      FIGS. 9F and 9G  are cross section diagrams of the global bus along respective lines C-C′ and A-A′ illustrating various parasitic capacitances; 
           [0028]      FIG. 10  is a flow chart illustrating a method for fabricating the global bus configuration shown in  FIGS. 8A and 8B  according to an embodiment of the present invention; 
           [0029]      FIG. 11A  is an overhead view diagram of a global bus configuration according to another embodiment of the present invention; 
           [0030]      FIGS. 11B ,  11 C and  11 D are cross section diagrams of the global bus shown in  FIG. 11A  along respective lines A-A′, B-B′, and C-C′; 
           [0031]      FIG. 11E  is a plane view of the global shown in  FIG. 11  along conductive layer M 3 ; and 
           [0032]      FIG. 12  is a flow chart illustrating a method of fabricating the global bus shown in  FIGS. 11A-11E  according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0033]    In the following detailed description, reference is made to the accompanied drawings which form a part hereof, and which illustrates specific embodiments of the present invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention. It is also understood that structural, logical or procedural changes may be made to the specific embodiment disclosed without departing from the scope of the present invention. 
         [0034]      FIG. 1  is a block diagram of a CMOS image sensor  100  including pixel array  102 . Pixel array  102  of image sensor  100  includes a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in the array are turned on at the same time by a row select line and the pixels of each column are selected for output by a column select line. A plurality of row and column lines are provided for the entire array. 
         [0035]    The row lines are selectively activated by a row driver (not shown) in response to row address decoder  104  and the column select lines are selectively activated by a column driver (not shown) in response to column address decoder  108 . Thus, a row and column address is provided for each pixel. CMOS image sensor  100  is operated by control circuit  110 , which controls address decoders  104 ,  108  for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry, which apply driving voltages to the drive transistors of the selected row and column lines. 
         [0036]    Each column of the array contains sample and hold circuitry (S/H), designated generally as  106 , including sample and hold capacitors and switches associated with the column driver that read and store a pixel reset signal (i.e. reset) and a pixel image signal (i.e. signal) for selected pixels (described further with respect to  FIG. 2 ). A differential signal (reset-signal) is produced by programmable gain amplifier (PGA) circuit  114  for each pixel, which is digitized by analog-to-digital converter  116  (ADC). ADC  116  supplies the digitized pixel signals to image processor  118 , which forms and outputs a digital image. 
         [0037]    Control circuit  110  also provides a gain, V cm , to PGA  114  and controls clock generator  112 , which applies clock signals φ 1 , φ 2  to PGA circuit  114  for controlling a reset and column readout of pixels by PGA  114 . 
         [0038]      FIG. 2  is a circuit diagram illustrating a portion of S/H circuit  106 , global bus  206  and PGA  114 . S/H circuit  106  includes column S/H circuits  202  and  204  corresponding to respective even and odd rows. For example, if color filters included on pixel array  102  ( FIG. 1 ) are arranged in a Bayer pattern, S/H circuits  202   a  and  202   b  may store reset and image signals corresponding to respective red and green pixels of an even row. In addition, column S/H circuits  204   a ,  204   b  may store reset and image signals corresponding to blue and green pixels of an odd row. Group switches (GS) ( FIG. 3D ) may be used select the rows (i.e. corresponding to column S/H circuits  202  or  204 ), and the reset signals (chx_rst) and image signals (chx_sig) for channels x=1,2 are provided to global bus  206 . 
         [0039]    Each column S/H circuit  202 ,  204  includes switches sample reset (SHR) and sample pixel (SHS), used to perform a correlated double sampling (CDS) procedure in conjunction with switch sh. Column S/H circuits  202 ,  204  also include column select switches φ 10 , φ 20 , φ 11  and φ 22 , associated with selection of the corresponding column. A reset signal and an image signal from the associated pixel are stored on respective capacitors Cs and provided to global bus  206  according to the column switch selection. 
         [0040]    Global bus  206  includes first channel signal lines  208   a ,  208   b  coupled to amplifier circuit  212   a  and second channel signal lines  210   a ,  210   b  coupled to amplifier circuit  212   b . Amplifier circuit  212   b  is the same as amplifier circuit  212   a , except that amplifier circuit  212   b  receives channel  2  reset and image signals (i.e. ch 2 _rst and ch 2 _sig from column S/H circuits  202   a ,  204   a ), whereas amplifier circuit  212   a  receives channel  1  reset and image signals (i.e. ch 1 _rst and ch 1 _sig from column circuits  202   b ,  204   b ). Amplifier circuits  212  each includes a differential amplifier  214  and feedback capacitor (CF). Amplifier circuits  212  also receive gain Vcm, for example from control circuit  110  ( FIG. 1 ). Responsive to clock signals φ 1  and φ 2  and gain Vcm, amplifier circuits  212  may be provided in a gain stage, as shown in  FIG. 3C  or in a reset stage (not shown). 
         [0041]    The reset and image signal lines from the column S/H circuits  202 ,  204  are inputs to the amplifier circuits  212  and common to the entire column S/H circuitry shown in  FIG. 2 . Because the channel  1  signal lines  208  and channel  2  signal lines  210  are of high impedance, careful layout of the global bus  206  is desirable to prevent interference from various electromagnetic interference (EMI) sources. An EMI source may include, for example, a signal line placed near the global bus, such as a clock signal. A parasitic capacitance may be formed between the EMI source and a conductor of the global bus. 
         [0042]      FIGS. 3A-3D  illustrate a conductor layout that includes global bus  206 . In particular,  FIG. 3A  is a block diagram illustrating the conductor layout;  FIG. 3B  is a cross section diagram along line A-A′ illustrating parasitic capacitance coupled to the global bus due to the conductor layout;  FIG. 3C  is a circuit diagram of the amplifier circuitry during column readout when the parasitic capacitance is included; and  FIG. 3D  is a circuit diagram illustrating one channel of global bus  206  and different parasitic capacitances that may be coupled to the global bus. 
         [0043]    As shown in  FIG. 3A , clock conductors  302   a ,  302   b  are formed relative to first channel conductors  306   a ,  306   b  and second channel conductors  308   a ,  308   b  of a global bus configuration. Clock conductors  302   a  and  302   b  carry respective clock signals φ 1  and φ 2 . First channel conductors  306   a ,  306   b  correspond to channel  1  signal lines  208   a ,  208   b  and carry channel  1  reset and image signals, respectively. Second channel conductors  308   a ,  308   b  correspond to channel  1  signal lines  210   a ,  210   b  and carry channel  2  reset and image signals, respectively. 
         [0044]    First channel conductors  306  are shielded from second channel conductors  304  and other signal conductors by grounded conductors  304   b  and  304   c . Similarly, second channel conductors  308  are shielded from first channel conductors  306  and clock conductors  302  by the grounded conductors  304   a  and  304   b.    
         [0045]    Although the second channel conductors  308   a ,  308   b  and first channel conductors  306   a  and  306   b  may be shielded by the grounded conductors  304   a - c , as the global bus conductors  306 ,  308  become longer, a fringe capacitance may be seen on the high impedance first channel conductor  308   a , for example, from any signal lines, such as clock signal φ 1  (via clock conductor  302   a ). Global bus  206 , thus, may be susceptible to interfering sources, i.e. EMI sources even with shielding by ground conductors  304 . 
         [0046]    For example,  FIG. 3B  is a cross section diagram along line A-A′ from clock conductor line  302   a  through second channel conductor  308   a  that carries a channel  2  reset signal (ch 2 _rst). A parasitic capacitance Ca may be coupled between clock conductor  302   a  carrying φ 1  and second channel conductor  308   a.    
         [0047]    As illustrated in the circuit diagram of  FIG. 3C , when parasitic capacitance Ca is coupled to second channel conductor line  308   a , an equivalent circuit for amplifier  212   b  includes clock signal φ 1  coupled to amplifier circuit  212   b  via parasitic capacitance Ca. 
         [0048]    For example, a parasitic capacitance Ca of about 1 aF/μm becomes about 1 fF for a 1,000 μm long column signal line. A channel  1  differential output from amplifier circuit  212   a  may be represented by Vo 1 =Cs/Cf (Vrst−Vsig). A differential output from Channel  2  (amplifier circuit  212   b ), in contrast, may be represented by Vo 2 =Cs/Cf (Vrst−Vsig) +Ca/Cf*(Vφ 1 ). When Cf and φ 1  are respectively 1 pF and 3 V, the channel mismatch between amplifier circuits  212   a  and  212   b  is about 1/1,000*3 V or about 3 mV. A 3 mV channel mismatch is equivalent to about 3 least significant bits (LSB) in 10 bit ADC and 12 times an LSB in 12 bit ADC at a PGA gain of x1. If the PGA gain is increased by x16, the mismatch may become about 48 times an LSB in 10 bit ADC and about 192 times an LSB in 12 bit ADC. 
         [0049]    Because of parasitic capacitance, further shielding of the high impedance global bus signal lines  208 ,  210  decreases the feedback factor for the first gain stage of amplifier circuits  212  ( FIG. 2 ). This may result in more power and greater layout area of the first gain stage of PGA  114 . At the same time, the clock and column signal lines typically cannot be located farther from signal lines  208  and  210  because of the available size of the chip area for CMOS image sensor  100 . 
         [0050]    Although  FIG. 3B  illustrates a parasitic capacitance coupled to first channel conductor  304   a  that transmits a reset signal, in general, as shown in  FIG. 3D , the global bus  206  may be susceptible to at least three different parasitic capacitances. Capacitance Cpr between a general EMI source and the reset line is similar to Ca shown in  FIG. 3B . A second parasitic capacitance Cps may be coupled to a channel of the global bus between a further EMI source and the signal line. A third parasitic capacitance Csr may be coupled between the signal line and the reset line of a channel of the global bus. Typically, parasitic capacitances Cps and Cpr are minimized in order to optimize speed and power consumption by the amplifier circuit  212 . Coupling capacitance Csr is typically nulled using a switch (not shown) on the amplifier circuit  212  site to set the inputs of the amplifier circuit  212  to a common mode voltage. However, the effects on the feedback factor of amplifier circuit  212  are more pronounced than the parasitic capacitances CPS and CPR. 
         [0051]      FIGS. 4A-4D  illustrate global bus  206  having a twisted pair configuration, according to an embodiment of the present invention. In particular,  FIG. 4A  is a block diagram of a conductor layout including a twisted pair global bus configuration;  FIG. 4B  is a cross section diagram, taken along lines A-A′, illustrating a parasitic capacitance coupled to the signal line of the global bus;  FIG. 4C  is a cross section diagram, taken along lines B-B′, illustrating a parasitic capacitance coupled to the reset line of the global bus; and  FIG. 4D  is a circuit diagram of the amplifier circuitry during column readout, when the parasitic capacitances included in the twisted pair global bus are included. 
         [0052]    As shown in  FIG. 4A , a twisted pair configuration of conductors  406   a ,  406   b  of Channel  1  and of conductors  408   a  and  408   b  of Channel  2  define respective twisted pairs  406  and  408 . Twisted pairs  406  and  408  are each shielded by respective grounded conductors  404   a - 404   c . Clock conductors  402   a ,  402   b , that respectively carry clock signals φ 1  and φ 2 , are provided near twisted pair  408 . 
         [0053]    As shown in the cross section diagrams of  FIGS. 4B and 4C , parasitic capacitance Ca/2 is coupled between clock conductor  402   a  and conductor  408   a , that carries the channel  2  reset signal. Because conductors  408   a ,  408   b  are twisted, as shown in  FIG. 4C , parasitic capacitance Ca/2 is also coupled between clock conductor  402   a  and conductor  408   b , that carries the channel  2  image signal. 
         [0054]    As shown in  FIG. 4D , because of the twisted pair  408  configuration, the parasitic coupling due to clock signal φ 1  is evenly distributed to the channel  2  reset and signal lines. Accordingly, when amplifier circuit  212   b  operates in differential mode, the differential output of channel  2  becomes Vo 2 =Cs/Cf*(Vrst−Vsig)+0.5*Ca/Cf*(Vφ 1 ). An interference signal of one or more EMI sources may be substantially canceled by the common mode rejection of differential amplifier  214 . Accordingly a channel mismatch between outputs of amplifiers  212   a  and  212   b , may also be minimized. 
         [0055]    A change of common mode input level is typically about 0.5 Ca/(Cp+0.5 Ca)*Vφ 1  or approximately 1.5 mV, where Ca and Cp (i.e., a general parasitic capacitance) for example, may be about 1 fF and 1 pF, respectively. A common mode rejection of amplifier  212  is typically over 40 dB. In this example, 15 μV at the output of amplifier circuit  212  is provided. If the gain of amplifier circuit is x16, the final output becomes about 250 μV, which is about 0 LSB in both 10 bit and 12 bit ADC. Accordingly, a common mode rejection of amplifier circuit  212  may be suitable with a twisted pair configuration of global bus  206 , to reduce the effects of EMI sources on the reset and image signals carried by global bus  206 . 
         [0056]      FIG. 5  is a block diagram of a conductor layout including another global bus configuration, according to another embodiment of the present invention. Each channel conductor  506 ,  508  of the global bus  206  is twisted with a corresponding ground conductor  504 , that carries a ground signal. Channel  1  conductors  506   a,b  respectively carry the channel  1  reset and image signals and are twisted with ground conductors  504  to form respective twisted pairs  510   a,b.  Similarly, channel  2  conductors  508   a,b  respectively carry the channel  2  reset and image signals and are twisted with ground conductors  504  to form respective twisted pairs  512   a,b.  Clock conductors  502   a,b  respectively carry clock signals φ 1  and φ 2 . Ground conductors  504  may be used to shield the conductor lines  506  and  508  of the two channels of global bus  206  that are provided to respective amplifier circuits  212   a,b  ( FIG. 2 ). 
         [0057]    As described above, each channel of global bus  206  may be formed from signal and reset conductors arranged as a twisted pair, in order to reduce EMI from external sources and crosstalk from neighboring wires. When the conductors are not twisted, in contrast, the two conductors may be exposed to different EMI. Twisting the conductors may decrease interference, because a loop area between the conductors (which determines the magnetic coupling into the signal) is typically reduced. Often, the two conductors carrying equal and opposite signals (i.e. in a differential mode) are combined by subtraction at the amplifier circuit  212  ( FIG. 2 ). The noise signals from the two conductors typically cancel each other in the differential amplification because the two conductors are exposed to similar electromagnetic interference. Accordingly, the greater the number twists in the two conductors, the greater the attenuation of crosstalk. 
         [0058]    Typically, in CMOS image sensors having a serial readout architecture, one or more global buses carries the differential pixel signals (i.e. signal and reset signals) that are sampled on the column S/H circuits  202 ,  204  to the amplifier  114  ( FIG. 2 ). Columns are typically divided into small groups, for example typically 32 columns. The selected column is transferred onto a local bus and then to the global bus  206  ( FIG. 2 ) through column select and group select switches. A column select, generated by a column decoder  108  ( FIG. 1 ) is used to transfer addressed column signals onto the local bus. Column decoder  108  also generates a group select pulse used by the group switches (GS) to connect the local bus that contains the addressed columns to global bus  206  ( FIG. 3D ). 
         [0059]      FIGS. 6A and 6B  illustrate a portion of global bus configuration  600  where a reset bus  604  and a signal bus  602  are placed next to each other on one conductive layer. In particular  FIG. 6A  is an overhead view of a portion of global bus configuration  600  relative to the bus routing width (W); and  FIG. 6B  is a cross section taken along lines A-A′ of global bus configuration  600 . 
         [0060]    As shown in  FIGS. 6A and 6B , global bus configuration  600  includes a ground bus  606   a , signal bus  602  and reset bus  604  on one conductive layer, for example metal (M) M 4 . In addition, ground bus  606   a  is connected to ground bus  606   b  on a different conductive layer by via  608 , for example M 2 . Signal bus  602  and reset bus  604  are typically placed on a top conductive layer typically having a lowest sheet resistance. 
         [0061]    The configuration of signal bus  602  and reset bus  604  is similar to the conductors  306   a,b  or  308   a,b  global bus configuration illustrated in  FIGS. 3A and 3B . As described above, global bus configuration  600  may receive an unequal interference from one or more EMI sources, thus causing an imbalance on the reset and image signals transmitted to amplifier circuits  212  ( FIG. 2 ). If more than one channel is provided, a channel mismatch may occur. In addition, because the top conductive layer is used for routing signal bus  602  and reset bus  604 , the EMI effect may become more pronounced for this top conductive layer configuration. Furthermore, the bus routing width (W) may occupy a large layout/chip area for a large number of differential pair architectures. 
         [0062]      FIGS. 7A-7E ,  8 A and  8 B illustrate a global bus configuration  700  according to an example embodiment of the present invention. In particular,  FIG. 7A  is an overhead view of a portion of global bus configuration  700  illustrating a bus routing width (W/2);  FIG. 7B  is an exploded overhead view of the portion of global bus configuration  700  shown in  FIG. 7A ;  FIG. 7C  is a cross section diagram of global bus configuration  700  along line A-A′;  FIG. 7D  is a cross section diagram of global bus configuration  700  along line B-B′;  FIG. 7E  is a cross section diagram of global bus configuration  700  along line C-C′;  FIG. 8A  is an overhead view illustrating a bus routing length of global bus configuration  700 ; and  FIG. 8B  is an exploded overhead view of global bus configuration  700  shown in  FIG. 8A . 
         [0063]    As shown in  FIGS. 7A-7E , signal bus portion  702  and reset bus portion  704  are routed on alternate layers, for example, M 3  and M 4 . Accordingly, signal bus portion  702  includes a segment  702   a  provided on M 4  and a segment  702   c  provided on M 3 . Signal bus  702  also includes a via segment  702   b  having vias  710  connected to group switches ( FIG. 7D ). Similarly, reset bus portion  704  also includes a first segment  704   a  provided on M 3  and a second segment  704   c  provided on M 4 . In addition, reset bus  704  includes via section  704   b  having vias  712  connected to group switches ( FIG. 3D ). 
         [0064]    Each adjacent via section  702   b ,  704   b  ( FIG. 7D ) provide a twist (T) of the signal bus  802  and reset bus  804  ( FIG. 8B ). As shown in  FIGS. 7C and 7E , signal bus  702  and reset bus  704  are provided in a twisted pair configuration relative to the Z-axis. 
         [0065]    Global bus configuration  700  also includes ground bus  706  that is formed among the conductive layers, for example M 2 -M 4 , by ground bus conductors  706   a - c  coupled by vias  708 . Although four vias  710 ,  712  for connection to the group switches and one via  708  for connection of ground bus layers  706   a - c  are shown, it is understood that any suitable number of vias  710 ,  712  may be used as long as a connection is ensured. A larger number of vias may minimize an impedance and/or provide additional connection between conductive layers. 
         [0066]    As shown in  FIGS. 8A and 8B , signal bus portion  702  is repeated along a length of global bus configuration  700  to produce signal bus  802 . Similarly, reset bus portion  704  is repeated along a length of global bus configuration  700  to form reset bus  804 . Via section  702   b  is used to connect section  702   a  and  702   c  of the alternating M 3  and M 4  layers. Similarly, via section  704   b  is used to connect reset section  704   a  and  704   c  on the alternating M 3  and M 4  layers along the length of global  700 . In  FIGS. 8A and 8B , five twists are formed by via sections  702   b ,  704   b.    
         [0067]    Although  FIGS. 8A and 8B  illustrates a global bus having 5 twists, for a typical pixel imager, for example, C25A(MI2030), a number of columns on each side is about 870. If 32 columns per group exist, a total of 27 groups select switches exist. In this example, signal bus  802  and reset bus  804  twist around each other at least 27 times for global bus configuration  700 . It is understood that a number of twists could be increased or decreased according to the respective layout and design requirements. 
         [0068]    Typically, global bus design and CMOS image sensors use two wide parallel metal layers to connect group signals to the amplifier  114  ( FIG. 2 ), for example, as shown in  FIG. 6A . Types, sizes, total heights of these buses as well as a twisted pair height (x dimension) and savings are shown in Table 1. In general, the inventors have determined that a height savings is typically larger than 40% of the original global bus height. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Comparison of side by side and twisted global bus configurations 
               
             
          
           
               
                   
                 # of 
                   
                   
                 Twisted 
                   
                   
               
               
                   
                 Bus 
                 Bus 
                 Total Bus 
                 Pair 
                   
                   
               
               
                   
                 Pairs 
                 Layer and 
                 Height 
                 Height 
                 Savings 
                 Savings 
               
               
                 Design 
                 (N) 
                 Height (H) 
                 (μm) 
                 (μm) 
                 (μm) 
                 (%) 
               
               
                   
               
             
          
           
               
                 A 
                 4 
                 M4/2.75 
                 36.25 
                 21.25 
                 15.0 
                 41 
               
               
                 B 
                 2 
                 M4/2.75 
                 17.11 
                 9.61 
                 7.5 
                 44 
               
               
                 C 
                 2 
                 M4/2.75 
                 21.11 
                 12.61 
                 9.5 
                 45 
               
               
                 D 
                 1 
                 M4/1.50 
                 9.24 
                 5.74 
                 3.5 
                 38 
               
               
                   
               
             
          
         
       
     
         [0069]      FIGS. 9A-9G  illustrate examples of typical dimensions and parasitic capacitances for global bus configuration  600  ( FIG. 6A ) and global bus configuration  700  ( FIG. 7A ). In particular,  FIG. 9A  is a cross section diagram of global bus configuration  600  illustrating typical global bus dimensions relative to the bus routing width;  FIG. 9B  is a cross section diagram of global bus configuration  700  taken along line C-C′ ( FIG. 7E ) illustrating typical global bus dimensions relative to the global bus routing width;  FIG. 9C  is a cross section of global bus configuration  600  illustrating typical global bus dimensions relative to a global bus length (L);  FIG. 9D  is a cross section of a length of global bus configuration  700  illustrating twist segments (D) dimensions and a global bus length (L);  FIG. 9E  is a cross section of a width of global bus configuration  600  illustrating various parasitic capacitances coupled to the global bus;  FIG. 9F  is a cross section of global bus  700  taken along line an C-C′ ( FIG. 7E ) illustrating various parasitic capacitances coupled to the global bus; and  FIG. 9G  is a cross section of global bus configuration  700  taken along line an A-A′ ( FIG. 7C ) illustrating various parasitic capacitances coupled to the global bus. 
         [0070]    Typically, for CMOS imagers, the number of twists (T) is about 27, a number of groups (G) is about 27, twist segments (D) are typically about 53.40 μm, bus length (L) is typically about 3045 μm, the spacing (d) between signal bus  602  and reset bus  604  ( FIG. 9A ) is typically about 1.00 μm and spacing k ( FIGS. 9A and 9B ), i.e. the spacing between ground bus  606   a ,  706   a , and signal bus  602 ,  702  or reset bus  604 ,  704  is typically about 0.75 μm. The parasitic capacitances Cps, Cpr and Csr are described above. 
         [0071]    An example of analysis of size and height savings by global bus configuration  700  as compared with global bus configuration  600  is described below, where the effects of the parasitic capacitances ( FIGS. 9E-9G ) are also considered. 
         [0072]    For global bus configuration  600  ( FIG. 9E ): 
         [0000]        Cps 1 =Cpr 1=( L*  0.44*ε)/0.75 =Cu,    
         [0000]        Cps 2 =Cpr 2=( L* 2.75*ε)/1.24 =3.78 *Cu,  and 
         [0000]        Csr 1=( L* 0.44*ε)/1.0=0.75 *Cu.    
         [0000]    For global bus configuration  700  ( FIGS. 9F and 9G ): 
         [0000]        Cpr 3 =Cps 5 ˜Cu,    
         [0000]        Cps 3 =Cpr 4=( L* 0.34*ε)/0.75=0.77 *Cu,    
         [0000]        Cps 4 =Cpr 5=( T*D* 2.75*ε)*( L/L )/0.45=4.93 *Cu , and 
         [0000]        Csr 2=(2 *T*D* 2.75*ε)*( L/L )/0.45=9.9* Cu,    
         [0000]    where ε represents permittivity. 
         [0073]    Let Cp(total, node_p)=Cp(total, node_n). Then for global bus configuration  600  ( FIG. 9E ), the total parasitic capacitance Cp 1  becomes: 
         [0000]        Cp 1(total, node —   n )= Cps 1 +Cps 2+2 *Csr 1, or 
         [0000]        Cp 1(total, node —   n )= Cu+ 3.78 *Cu +2*0.75* Cu =6.28 *Cu.    
         [0000]    The total parasitic capacitance Cp 2  for global bus configuration  700  ( FIGS. 9F and 9G ) becomes: 
         [0000]        Cp 2(total, node —   n )=2* Cps 3 +Cps 4+2 *Cps 5+2 *Csr 2, or 
         [0000]        Cp 2(total, node_n)=2*0.77 *Cu +4.93 *Cu +2 *Cu +2*9,9 *Cu =18.37 *Cu,    
         [0000]    where node n and node p are shown in  FIG. 3D . Accordingly, twisted pair global bus configuration  700  may be more susceptible to parasitic capacitances that may affect the ASC operation speed and power. However, global bus configuration  700  provides a smaller layout footprint, for example, about 45% smaller (based on the dimensions shown in  FIGS. 9A and 9B ). In addition, the twisted pair global bus configuration  700  may provide significant EMI immunity to differential signals that are transferred through a long global bus. 
         [0074]      FIG. 10  is a flow chart illustrating a method of fabricating global bus configuration  700  ( FIG. 8A ), according to an embodiment of the present invention. In step  1000 , alternating segments of reset bus  804  and signal bus  802  ( FIG. 8B ) are formed on a first conductive layer, for example, M 3 , along a bus routing length of global bus configuration  700 . In step  1002 , a dielectric layer is formed over the alternating segments on the first conductive layer. 
         [0075]    hi step  1004 , vias are formed through the dielectric layer at respective ends of each segment of the reset bus and signal bus on the first conductive layer, for example, to form via sections  702   b  and  704   b , as shown in  FIG. 8B . In step  1006 , alternating segments of the signal bus  802  and reset bus  804  are formed on a second conductive layer, for example, M 4 . 
         [0076]    The alternating segments on the second conductive layer are formed such that ends of each segment on the second conductive layer correspond to the ends of segments on the first conductive layer. The vias are formed to connect the corresponding segments of the reset bus on the first conductive layer to the segments of the reset bus on the second conductive layer. In addition, the vias are also formed to connect the corresponding segments of the signal bus on the first conductive layer to the segments of the signal bus on the second conductive layer. A twisted pair configuration of the reset bus and the signal bus are thus formed on two conductive layers. 
         [0077]      FIGS. 11A-11E  illustrate a twisted pair global bus configuration  1100  according to another embodiment of the present invention. In particular,  FIG. 11A  is an overhead view of global bus configuration  1100 ;  FIG. 11B  is a cross section view of global bus configuration  1100  along line A-A′;  FIG. 11C  is a cross section view of global bus  1100  configuration along line B-B′;  FIG. 11D  is a cross section view of global bus configuration  1100  along line C-C′; and  FIG. 11E  is a plane view of global bus  1100  at conductive layer M 3 . 
         [0078]    As shown in  FIGS. 11A-11E , global bus  110  includes interlocking S-shaped reset segments  1102  and S-shaped signal segments  1104  that are both provided on one conductive layer, for example, M 3 . Connecting segments  1106 A connect S-shaped signal segments  1104  and connecting segments  1106 B connect S-shaped reset segments  1102 . Connecting segments  1106 A,  1106 B are formed on another conductive layer, for example M 4  and are connected to corresponding S-shaped reset segments  1102  and S-shaped signal segments  1104  by respective vias  1108   a ,  1108   b . The S-shaped reset segments  1102  and signal segments  1104  are interconnected on one conductive layer such that they form a twisted pair (i.e. are interlocked). 
         [0079]    Although four vias  1108  are shown between M 3  and M 4  and one via  1108  is shown between M 2  and M 3  in  FIG. 11A , it is understood that any suitable number of vias  1108  may be provided according to, for example, impedance considerations. Ground bus  1110  is shown on conductive layer M 2  to illustrate formation of global bus configuration  1100  on the conductive layers. Vias  1108   a  and  1108   b  may be used to connect S-shaped reset segments  1102  and S-shaped signal segments  1104  to corresponding group switches for selecting a row of pixel array  102  ( FIG. 1 ). 
         [0080]      FIG. 12  is a flowchart illustrating a method of forming global bus configuration  1100  ( FIG. 11A-11E ). In step  1200 , first and second interlocking S-shaped segments of a reset bus and a signal bus are formed on a first conductive layer, for example, M 3 . The second S-shaped segments are formed adjacent to the first S shaped segments and offset from the first S shaped segments relative to the bus routing length of global bus  1100  ( FIG. 11A ). In step  1202 , a dielectric layer is formed over the first and second S shaped segments on the first conductive layer. In step  1204 , vias are formed through the dielectric layer at respective ends of each segment formed on the first conductive layer, for example, as shown in  FIG. 11A . 
         [0081]    In step  1206 , connecting segments are formed on a second conductive layer, for example M 4 , such that ends of the connecting segments correspond to ends of the first and second S-shaped segments formed on the first layer. The vias are formed to connect the corresponding S-shaped segments of the reset bus and the corresponding S-shaped segments of the signal bus. Thus, a twisted pair global bus configuration  1100  is formed. 
         [0082]    Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.

Technology Classification (CPC): 7