Patent Abstract:
An apparatus includes connectors and a circuit. Each connector is capable of receiving and coupling a different voltage regulator module to a circuit board. The circuit is coupled to the connectors to form a multiple phase voltage regulator system out of the voltage regulator modules that are received by the connectors. The circuit establishes the number of phases of the multiple phase voltage regulator system based on the number of voltage regulator modules that are received by the connectors.

Full Description:
BACKGROUND 
     The invention generally relates to a multiple phase voltage regulator system. 
     A DC-to-DC voltage regulator typically is used to convert a DC input voltage to either a higher or a lower DC output voltage. One type of voltage regulator is a switching regulator that is often chosen due to its small size and efficiency. The switching regulator typically includes one or more switches that are rapidly opened and closed to transfer energy between an inductor (a stand-alone inductor or a transformer, as examples) and an input voltage source in a manner that regulates an output voltage. 
     As an example, referring to FIG. 1, one type of switching regulator is a Buck switching regulator  10  that receives an input DC voltage (called V IN ) and converts the V IN  voltage to a lower regulated output voltage (called V OUT ) that appears at an output terminal  11 . To accomplish this, the regulator  10  includes switches  20  and  21  (a combination of a metal-oxide-semiconductor field-effect-transistor (MOSFET) and a passive diode or twin MOSFETs, for example). Switch  20  is operated (via a voltage called V SW ) in a manner to regulate the V OUT  voltage, as described below. 
     Referring also FIGS. 2 and 3, in particular, the switch  20  opens and closes to control energization/de-energization cycles  19  (each having a constant duration called T S ) of an inductor  14 . In each cycle  19 , the regulator  10  asserts, or drives high, the V SW  voltage during an on interval (called T ON ) to close the switch  20  and transfer energy from an input voltage source  9  to the inductor  14 . During the T ON  interval, a current (called I L ) of the inductor  14  has a positive slope. During an off interval (called T OFF ) of the cycle  19 , the regulator  10  deasserts, or drives low, the V SW  voltage to open the switch  20  and isolate the input voltage source  9  from the inductor  14 . At this point, the level of the I L  current is not abruptly halted, but rather, the switch  21  begins conducting to transfer energy from the inductor  14  to a bulk capacitor  16  and a load (not shown) that are coupled to the output terminal  11 . The bulk capacitor  16  serves as a stored energy source that is depleted by the load, and additional energy is transferred from the inductor  14  to the bulk capacitor  16  during each T ON  interval. 
     For the Buck switching regulator, the ratio of the T ON  interval to the total switching period, T S  (summation of T ON +T OFF ), called a duty cycle, generally governs the ratio of the V OUT  to the V IN  voltages. Thus, to increase the V OUT  voltage, the duty cycle may be increased, and to decrease the V OUT  voltage, the duty cycle may be decreased. 
     As an example, the regulator  10  may include a controller  15  (see FIG. 1) that regulates the V OUT  voltage by using a pulse width modulation (PWM) technique to control the duty cycle. In this manner, the controller  15  may include an error amplifier  23  that amplifies the difference between a reference voltage (called V REF ) and a voltage (called V P  (see FIG.  1 )) that is proportional to the V OUT  voltage. Referring also to FIG. 5, the controller  15  may include a comparator  26  that compares the resultant amplified voltage (called V C ) with a sawtooth voltage (called V SAW ) and provides the V SW  signal that indicates the result of the comparison. The V SAW  voltage is provided by a sawtooth oscillator  25  and has a constant frequency (i.e., 1/T S ). 
     Due to the above-described arrangement, when the V OUT  voltage increases, the V C  voltage decreases and causes the duty cycle to decrease to counteract the increase in V OUT . Conversely, when the V OUT  voltage decreases, the V C  voltage increases and causes the duty cycle to increase to counteract the decrease in V OUT . 
     The voltage regulator may be made in the form of a voltage regulator module (VRM), a semiconductor package, or chip, that may be inserted into a corresponding connector slot, for example. More particularly, multiple VRMs, such as the VRMs  37  and  38  that are depicted in FIG. 6, may be coupled in parallel to form a multiple phase voltage regulator system  36 . In this manner, referring also FIGS. 7 and 8, energization/de-energization cycles  40   a  (depicted by an internal switching voltage of the VRM  37  called V SW1 ) of the VRM  37  is interleaved with respect to the energization cycles  40   b  (depicted by an internal switching voltage of the VRM  38  called V SW2 ) of the VRM  38 . As depicted in FIGS. 7 and 8, the effective switching period (called T S1 ) of the system  36  is one half as long as the switching period (called T S2 ) of either VRM  37  or  38 . Thus, the system  36  operates at twice the switching frequency of the VRM  37 ,  38 , an operation that provides better transient response performance than either VRM  37 ,  38  may provide by itself. More than two VRMs (three or four, for example) may be coupled together in parallel and interleaved accordingly to further increase the overall switching frequency of the system  36 . 
     For purposes of ensuring that each VRM  37 ,  38  operates in the appropriate time slot, the energization/de-energization cycles of VRMs  37  and  38  may be controlled by synchronization signals to regulate the phasing of the system  36 . In this manner, the VRM  37  may receive a SYNC 1  signal that is depicted in FIG. 9, and the VRM  38  may receive a SYNC 2  signal that is depicted in FIG.  10 . The SYNC 1  signal includes pulses  42   a , each of which enables a particular energization/de-energization cycle of the VRM  37 . The pulses  42   a  are interleaved with pulses  42   b  of the SYNC 2  signal. Each pulse  42   b  of the SYNC 2  signal enables a particular energization/de-energization cycle of the VRM  38 . 
     A system of interleaved VRMs (such as the system  36 , for example) may supply power to a computer system. In this manner, a motherboard may include several slots, or connectors, to receive VRMs. For purposes of providing flexibility in the number of VRMs that are used and thus, the number of phases of the system, the connectors typically appear in an ordered sequence on the motherboard. This sequence defines the placement of the VRMs to form a particular multiple phase system. If the VRMs are not inserted into the appropriate slots, then the appropriate synchronization signals may not be furnished to the slots, and thus, the power supply system may not function properly. 
     For example, a particular motherboard may have four VRM slots: Slot 1 , Slot 2 , Slot 3  and Slot 4 . To establish a two phase voltage regulator system, an ordering scheme that is imposed by the motherboard may require that the two VRMs are inserted in Slot 1  and Slot 2 , as Slot 1  and Slot 2  receive the synchronization signals to implement a two phase interleaved switching regulator system. Thus, if the VRMs are inserted into Slot 1  and Slot 3 , for example, the voltage regulator system may not function properly. Therefore, such an arrangement does not allow flexibility in the insertion and use of the VRMs. 
     Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of a switching voltage regulator of the prior art. 
     FIGS. 2,  3 ,  4  and  5  are signal waveforms that illustrate operation of the regulator of FIG.  1 . 
     FIG. 6 is a schematic diagram of a multiple phase voltage regulator system of the prior art. 
     FIGS. 7 and 8 are waveforms depicting different switching signals that control energization/de-energization cycles of different voltage regulator modules of the system of FIG.  6 . 
     FIGS. 9 and 10 are waveforms depicting synchronization signals used to control the voltage regulator modules of the system of FIG.  6 . 
     FIG. 11 is a schematic diagram of a multiple phase voltage regulator system according to an embodiment of the invention. 
     FIGS. 12,  13 ,  14 ,  15 ,  16 ,  17 ,  18 ,  19 ,  20 ,  21  and  22  are waveforms illustrating operation of the system of FIG. 11 according to an embodiment of the invention. 
     FIG. 23 is a schematic diagram of a portion of the multiplexing circuitry of the system of FIG. 7 according to an embodiment of the invention. 
     FIG. 24 is a schematic diagram of another portion of the multiplexing circuitry of the system of FIG. 11 according to an embodiment of the invention. 
     FIGS. 25 and 26 are schematic diagrams of the phased synchronization generator of the system of FIG. 11 according to different embodiments of the invention. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 11, an embodiment  50  of a multiple phase voltage regulator system in accordance with the invention includes connector slots  52  (slots  52   a ,  52   b ,  52   c  and  52   d  shown as examples), each of which may receive a corresponding switching voltage regulator module (VRM)  51 . The actual number of VRMs  51  that are received, or inserted, into the slots  52  establishes the number of phases of the system  50 . For example, if two VRMs  51  are inserted into the slots  52 , then a two phase voltage regulator system is established. Similarly, if four VRMs  51  are inserted into the slots  52 , then a four phase voltage regulator system is established. 
     Unlike conventional arrangements, the slots  52  are not ordered for purposes of establishing which slots  52  are to be used to form a particular number of phases. In this manner, multiplexing circuitry  56  of the system  50  routes the appropriate signals to the slots  52  that are connected to the VRMs  51  to establish a number of phases (for the system  50 ) that is equal to the number of inserted VRMs  51 . Thus, the insertion of two VRMs  51  into any two of the slots  52  establishes a two phase system  50 , the insertion of three VRMs  51  into any three of the slots  52  establishes a three phase system  50 , etc. In some embodiments of the invention, if only one VRM  51  is inserted into one of the slots  52 , then a single phase voltage regulator system is established. As an example, the system  50  may reside on a motherboard of a computer system for purposes of providing power to components ( one or more microprocessors  55 , for example) of the computer system. Thus, due to the routing of the synchronization signals by the multiplexing circuitry  56 , the&#39;slots  52  are interchangeable. 
     More specifically, in some embodiments of the invention, the multiplexing circuitry  56  selectively routes synchronization signals to the slots  52 . The synchronization signals control the timing of the energization/de-energization cycles of VRMs  51  that are inserted into the slots  52  for purposes of establishing interleaved operation. The synchronization signal that is routed to a particular slot  52  is a function of whether a VRM  51  is inserted into that slot  52  and the total number of VRMs  51  that are inserted into the slots  52 . If no VRM  51  is inserted into a particular slot  52 , then the multiplexing circuitry  56 , in some embodiments of the invention, grounds the synchronization line that is associated with that slot  52 . Otherwise if a VRM  51  is inserted into a particular slot  52 , the multiplexing circuitry  56  routes a synchronization signal to that slot  52  to establish the appropriate timing for the inserted VRM  51 . 
     Each slot  52  has a voltage input pin connector contact that receives an input voltage (called V IN ), and each slot  52  has an output pin connector contact that is coupled to an output terminal line  53 . The output terminal lines  53  are coupled together to provide an output voltage (called V OUT ) at an output node  58  that furnishes power to the computer system. In some embodiments of the invention, the slots  52  may provide multiple output voltages on multiple output terminals. However, regardless of the types of VRMs  51  that are used, the voltage input terminals of the slots  52  are coupled together in parallel, and the voltage output terminals of the slots  52  are coupled together in parallel. 
     The output terminals of the multiplexing circuitry  56  are coupled to synchronization communication lines that communicate the synchronization signals from the multiplexing circuit  56  to the slots  52 . For example, a synchronization signal communication line  60  is coupled between an output terminal of the multiplexing circuitry  56  and a conductive contact of the slot  52   a ; a synchronization signal communication line  62  is coupled between an output terminal of the multiplexing circuitry  56  and a conductive contact of the slot  52   b ; a synchronization signal communication line  64  is coupled between an output terminal of the multiplexing circuitry  56  and a conductive contact of the slot  52   c ; and a synchronization signal communication line  66  is coupled between an output terminal of the multiplexing circuitry  56  and a conductive contact of the slot  52   d . The input terminals of the multiplexing circuit  56  receive synchronization signals from conductive lines  59  that are coupled to the output terminals of a phase synchronized generator  54 . Based on which slots  52  have inserted VRMs  51  and the number of inserted VRMs  51 , the multiplexing circuitry  56  selectively routes the synchronization signals from the conductive lines  59  to the slots  52 . 
     For purposes of determining which slots  52  have inserted VRMs  51 , in some embodiments of the invention, each slot  52  provides a presence signal (called PRES 1 #, PRES 2 #, PRES 3 # and PRES 4 #, as examples). As an example, each presence signal may be formed by a terminal of an associated pullup resistor that has its other terminal coupled to a positive supply voltage and ground. When a VRM  51  is inserted into a particular slot  52 , the VRM  51  pulls the presence signal low to indicate that the VRM  51  is present in the slot  52 . Otherwise, the presence signal remains in a high logic state to indicate the absence of a VRM in the associated slot  52 . Other techniques and arrangements may be used to generate the presence signals. 
     Exemplary synchronization signals called PhaseA, PhaseB, PhaseC, PhaseD, PhaseE, PhaseF, PhaseG and PhaseH are depicted in FIGS. 12,  13 ,  14 ,  15 ,  16 ,  17 ,  19  and  20 , respectively. All of these synchronization signals may be generated by the phased synchronization generator  54  from a master system clock signal (called CLK), as described below. As described below, the phase synchronized generator  54  also generates two synchronization signals called PhaseI (FIG. 21) and PhaseJ (FIG. 22) that the generator  54  uses to generate the other synchronization signals. The multiplexing circuitry  56  selects the appropriate synchronization signals and routes the selected synchronization signals to the appropriate slots  52  based on the particular multiple phase interleaved voltage regulator system to be established. The synchronization signals are synchronized to the rising, or positive, edges of a master clock signal (called CLK), and each cycle of a particular synchronization signal lasts for twelve cycles of the CLK signal, in some embodiments of the invention. As depicted, each synchronization signal has a duty cycle of one half, though the synchronization criteria is established by the relative phase of the rising (or falling) edge of each synchronization signal to any other. This lends itself to edge, as well as level-triggered synchronization. Therefore, a particular synchronization signal enables the energization/de-energization cycle of a particular VRM for six cycles of the CLK signal and disables the energization/de-energization cycle for six cycles of the CLK signal. Therefore, the synchronization signals are distinguishable by their different phases. The multiplexing circuitry  56  selects a particular group of the synchronization signals and routes the synchronization signals from the selected group to the appropriate slot  52  to implement a particular interleaved voltage regulator system, as described below. 
     For example, for a two phase interleaved voltage regulator system, the multiplexing circuitry  56  selects the PhaseA and PhaseD synchronization signals from the conductive lines  59  and routes the PhaseA and PhaseD synchronization signals to the two slots  52  that have inserted VRMs  51 . As depicted in FIGS. 12 and 15, the PhaseA and PhaseD synchronization signals are 180° out of phase to implement the two phase interleaved operation. 
     For a three phase interleaved voltage regulator system, the multiplexing circuitry  56  selects the PhaseA, PhaseC and PhaseE synchronization signals from the conductive lines  59  and routes the PhaseA, PhaseC and PhaseE synchronization signals to the three slots  52  that have inserted VRMs  51 . As depicted in FIGS. 12,  14  and  16 , the PhaseA synchronization signal is 120° out of phase with the PhaseC synchronization signal, and the PhaseE synchronization signal is 120° out of phase with the PhaseC synchronization signal and 240° out of phase with the PhaseA synchronization signal to implement the three phase interleaved operation. 
     The PhaseA (FIG.  12 ), PhaseB (FIG.  13 ), PhaseD (FIG. 15) and PhaseF (FIG. 17) synchronization signals may be used for a four way interleaved voltage regulator system. The PhaseB signal is 90° out of phase with the PhaseA signal; the PhaseD signal is 90° out of phase with the PhaseB signal; and the PhaseF signal is 90° out of phase with the PhaseD signal. 
     The multiplexing circuitry  56  may select the PhaseA (FIG.  12 ), PhaseH (FIG.  20 ), Phase C (FIG.  14 ), PhaseE (FIG. 16) and PhaseG (FIG. 19) synchronization signals to implement a six way interleaved voltage regulator system. For this implementation, six VRMs  51  are inserted into six (only four slots  52  are depicted in FIG. 11) of the slots  52 . The PhaseH signal is 60° out of phase with the PhaseA signal; the PhaseC signal is 60° out of phase with the PhaseH signal; the PhaseD signal is 60° out of phase with the PhaseC signal; the PhaseE signal is 60° out of phase with the PhaseD signal and the PhaseG signal is 60° out of phase with the PhaseE signal. 
     If only one VRM  51  is inserted into the slots  52 , then the multiplexing circuitry  56  may select any (the PhaseA synchronization signal, for example) of the synchronization signals and route the selected synchronization signal to the slot  52  that has the inserted VRM  51  to establish a single phase voltage regulator system. 
     Referring to FIG. 23, a circuit  56 A of the multiplexing circuitry  56  includes a 2:1 (two input lines  69  that are selected by one select line  67 ) multiplexer  100  and a 16:4 (sixteen input lines  70  that are selected by four select lines  80 ) multiplexer  102  that provide the synchronization signals to the synchronization communication lines  60  and  62 , respectively. One input terminal of the multiplexer  100  receives the PhaseA synchronization signal, and the other input terminal  69  is coupled to ground. A select input terminal  67  of the multiplexer  100  receives the PRES 1 # signal, and the non-inverting output terminal of the multiplexer  100  is coupled to the synchronization signal communication line  60 . Thus, due to this arrangement, when the PRES 1 # signal has a logic one level to indicate that no VRM  51  is inserted into the slot,  51   a , the multiplexer  100  furnishes a logic zero to the synchronization signal communication line  60 . When the PRES 1 # signal has a logic zero level to indicate that a VRM  51  is inserted into the slot  51  a, the multiplexer  100  routes the PhaseA synchronization signal to the synchronization signal communication line  60 . Because the multiplexing circuitry  56  always selects the PhaseA synchronization signal regardless of the number of phases of the system  30 , the multiplexing circuit  56  routes the PhaseA synchronization signal to the slot  51   a  as long as a VRM  51  has been inserted into the slot  51   a . As described above, the PhaseA synchronization signal is used regardless of the number of phases of the system  10 . 
     The multiplexer  102  of the multiplexing circuitry  56 A has its output terminal coupled to the synchronization communication line  62  to route the appropriate synchronization signal (if any) to the corresponding contact of the slot  52   b . Select lines  80  of the multiplexer  102  receive, in the order of most significant bit (MSB) to least significant bit (LSB), the PRES 1 #, PRES 2 #, PRES 3 # and PRES 4 # signals. For purposes of convenience, the sixteen input terminals  70  of the multiplexer  102  are labeled in order from the least significant to the most significant using the following sixteen identifiers: D 0 , D 1 , D 2 , D 3 , . . . D 14  and D 15 . Thus, using this notation, “D0” refers to the input terminal  70  that is selected when the bits that are indicated by the select lines  80  indicate “0,” “D3” refers to the input terminal  70  that is selected when the bits that are indicated by the select lines  80  indicate “3,” D 15  refers to the input terminal  70  that is selected when the bits that are indicated by the select lines  80  indicate “15,” etc. 
     The input terminals  70  are basically divided into contiguous groups  70   a ,  70   b ,  70   c  and  70   d . The input terminals of the groups  70   d  (including the D 12 , D 13 , D 14  and D 15  input terminals  70 ) and  70   b  (including the D 4 , D 5 , D 6  and D 7  input terminals  70 ) are selected when the PRES 2 # signal has a logic one level to indicate that a VRM  51  is not inserted into the slot  52   b . Each input terminal of the groups  70   b  and  70   d  is coupled to ground. Therefore, when no VRM  51  is inserted into the slot  52   b , the multiplexer  102  grounds the synchronization signal communication line  62 . 
     The input terminals of the group  70   c  (including the D 8 , D 9 , D 10  and D 11  input terminals  70 ) are selected when the PRES 2 # signal has a logic zero level to indicate that a VRM  51  is inserted into the slot  52   b  and the PRES 1 # signal has a logic one level to indicate that a VRM  51  is not inserted into the slot  52   a . Each input terminal of the group  70   c  receives the PhaseA synchronization signal. Therefore, the multiplexer  102  routes the PhaseA synchronization signal to the slot  51   b  as long as a VRM  51  has been inserted into the slot  52   b  and no VRM  51  is inserted into the slot  52   a . As described above, the PhaseA synchronization signal is used regardless of the number of phases of the system  50 . 
     The input terminals of the group  70   a  (including the D 0 , D 1 , D 2  and D 3  input terminals  70 ) are selected when both the PRES 2 # and PRES# 1  signals have a logic zero levels to indicate that VRMs  51  are inserted into both slots  52   a  and  52   b . When this condition occurs, the multiplexer  102  selects the appropriate input terminal from the group  70  to establish the appropriate phase of the system. Because the slots  52   a  and  52   b  have inserted VRMs  51 , the number of phases depends on whether VRMs  51  are inserted into the other slots  52   c  and  52   d . In this manner, if VRMs  51  are inserted into both slots  52   c  and  52   d , then the PRES 3 # and PRES 4 # signals have logic zero levels to cause the multiplexer  102  to select the DO input terminal  40 , a terminal  70  that receives the PhaseB synchronization for purposes of establishing four phases for the regulator system  10 . If a VRM  51  is inserted into the slot  52   c  and not into the slot  52   d , then the PRES 3 # has a logic zero level and the PRES 4 # signals has a logic one level. This condition causes the multiplexer  102  to select the D 1  input terminal  70 , a terminal  70  that receives the PhaseC synchronization signal for purposes of establishing three phases for the regulator system  10 . Similarly, a three phase system  10  is also established if a VRM  51  is inserted into the slot  52   d  and not into the slot  52   c , a condition that causes the multiplexer  102  to select the D 2  input terminal, a terminal that receives the PhaseC synchronization signal. If a VRM  51  is neither inserted into the slot  52   c  nor the slot  52   d , then only two VRMs  51  are inserted into the slots  52 , and the multiplexer  102  selects the D 3  input terminal, a terminal that receives the PhaseD synchronization signal for purposes of establishing two phases (the first phase being established by the PhaseA signal that is communicated by the multiplexer  100  to the synchronization signal communication line  60  and the second phase being established by the PhaseD signal that is communicated by the multiplexer  100  to the synchronization signal communication line  62 ). 
     Referring to FIG. 24, another circuit  56 B of the multiplexing circuitry  56  includes a 16:4 (sixteen input lines  86  (each individually designated by the letters a-p) that are selected by four select lines  82 ) multiplexer  104  and a 16:4 (sixteen input lines  94  (each individually designated by the letters a-p) that are selected by four select lines  96 ) multiplexer  106  that provide the synchronization signals to the synchronization signal communication lines  64  and  66 , respectively. 
     The multiplexer  104  of the circuit  56 B has its output terminal coupled to the synchronization communication line  64  to route the appropriate synchronization signal (if any) to the corresponding contact of the slot  52   c . The select lines  82  of the multiplexer  104  receive, in the order of most significant bit (MSB) to least significant bit (LSB), the PRES 1 #, PRES 2 #, PRES 3 # and PRES 4 # signals. For purposes of convenience, the sixteen input terminals  83  of the multiplexer  104  are labeled in order from the least significant to the most significant using the following sixteen identifiers: D 0 , D 1 , D 2 , D 3 , . . . D 14  and D 15 , as described above for the multiplexer  102 . 
     The multiplexer  104  selects one of the input terminals  86   c ,  86   d ,  86   g ,  86   h ,  86   k ,  86   l ,  86   o  or  86   p  (corresponding to the D 2 , D 3 , D 6 , D 7 , D 10 , D 11 , D 14  and D 15  input terminals) when the PRES 3 # signal has a logic one level to indicate that a VRM  51  is not inserted into the slot  52   c . Each of the input terminals  86   c ,  86   d ,  86   g ,  86   h ,  86   k ,  86   l ,  86   o  and  86   p  is coupled to ground. Therefore, when no VRM  51  is inserted into the slot  52   c , the multiplexer  104  grounds the synchronization signal communication line  64 . 
     The multiplexer  104  selects one of the input terminals  86   m  and  86   n  (corresponding to the D 12  and D 13  input terminals  86 ) are selected when the PRES 3 # signal has a logic zero level to indicate that a VRM  51  is inserted into the slot  52   c  and the PRES 1 # and PRES 2 # signals each have a logic one level to indicate that the absence of a VRM  51  in both slots  52   a  and  52   b . Each of the input terminals  86   m  and  86   n  receives the PhaseA synchronization signal. Therefore, the multiplexer  104  routes the PhaseA synchronization signal to the slot  51   c  as long as a VRM  51  has been inserted into the slot  52   c  and no VRM  51  is inserted into the slots  52   a  and  52   b . As described above, the PhaseA synchronization signal is used regardless of the number of phases of the system  50 . 
     The multiplexer  104  selects one of the input terminals  86   a ,  86   f  or  86   j  for purposes of establishing a two or four phase system  50  when a VRM  51  is inserted into the slot  52   c  and at least one VRM  51  is inserted into the slots  52   a  and  52   b . In this manner, if VRMs  51  are inserted into all four slots  52   a ,  52   b ,  52   c  and  52   d , the multiplexer  104  selects the input terminal  86   a  to route the PhaseD synchronization signal to the synchronization signal communication line  64  to establish one of the phases of a four phase system  50 . Otherwise, the multiplexer  104  selects one of the input terminals  86   f  or  86   j  when a VRM  51  is inserted into the slot  52   c , no VRM is inserted into the slot  52   d  and only one VRM  51  is inserted into one of the slots  52   a  or  52   b . The selection of the input terminal  86   f  or  86   j  routes the PhaseD synchronization signal to the synchronization signal communication line  64  to establish one of the phases of a two phase system  50 . 
     The multiplexer  104  selects the input terminal  86   b  when VRMs  51  are inserted into each of the three slots  52   a ,  52   b  and  52   c , and no VRM  51  is inserted into the slot  52   d . The selection of the input terminal  86   b  routes the PhaseE synchronization signal to the synchronization signal communication line  64  to establish one of the phases of a three phase system  50 . 
     The multiplexer  104  selects either the input terminal  86   e  or  86   i  when only one VRM  51  is inserted into the slot  52   a  or  52   b ; a VRM  51  is inserted into the slot  52   c ; and a VRM  51  is inserted into the slot  52   d . The selection of the input terminal  86   e  or  86   i  routes the PhaseC synchronization signal to the synchronization signal communication line  64  to establish one of the phases of a three phase system  50 . 
     The multiplexer  106  of the circuit  56 B has its output terminal coupled to the synchronization communication line  66  to route the appropriate synchronization signal (if any) to the corresponding contact of the slot  52   d . The select lines  96  of the multiplexer  106  receive, in the order of most significant bit (MSB) to least significant bit (LSB), the PRES 1 #, PRES 2 #, PRES 3 # and PRES 4 # signals. For purposes of convenience, the sixteen input terminals  94  (each individually designated by the letters a-p) of the multiplexer  106  are labeled in order from the least significant to the most significant using the following sixteen identifiers: D 0 , D 1 , D 2 , D 3 , . . . D 14  and D 15 , as described above for the multiplexer  102 . 
     The multiplexer  106  selects one of the input terminals  94   b ,  94   d ,  94   f ,  94   h ,  94   j ,  94   l ,  94   n  or  94   p  (corresponding to the D 1 , D 3 , D 5 , D 7 , D 9 , D 11 , D 13  and D 15  input terminals) when the PRES 4 # signal has a logic one level to indicate that a VRM  51  is not inserted into the slot  52   d . Each of the input terminals  94   b ,  94   d ,  94   f ,  94   h ,  94   j ,  94   l ,  94   n  and  94   p  is coupled to ground. Therefore, when no VRM  51  is inserted into the slot  52   d , the multiplexer  106  grounds the synchronization signal communication line  66 . 
     The multiplexer  106  selects the input terminal  94   o  (corresponding to the D 14  input terminal  94 ) when the PRES 4 # signal has a logic zero level to indicate that a VRM  51  is inserted into the slot  52   d  and the PRES 1 #, PRES 2 # and PRES 3 # signals each have a logic one level to indicate that only one VRM  51  is present in the system  50 . The input terminals  94   o  receives the PhaseA synchronization signal. Therefore, the multiplexer  106  routes the PhaseA synchronization signal to the slot  52   d  to establish a single phase system  50  when the only VRM  51  present in the system  50  is inserted into the slot  52   d.    
     The multiplexer  106  selects one of the input terminals  94   g ,  94   k  or  94   m  for purposes of establishing a two phase system  10  when a VRM  51  is inserted into the slot  52   d  and only one VRM  51  is inserted into the slots  52   a ,  52   b  or  52   c . The input terminals  94   g ,  94   k  and  94   m  each receive the PhaseD signal for purposes of establishing one of the two phases of the system  50  when only two VRMs are inserted into one of the slots  52   a ,  52   b  or  52   c  and the slot  52   d.    
     The multiplexer  106  selects the input terminal  94   a  when VRMs  51  are inserted into all four slots  52   a ,  52   b ,  52   c  and  52   d . The selection of the input terminal  94   a  routes the PhaseF synchronization signal to the synchronization signal communication line  66  to establish one of the phases of a four phase system  50 . 
     The multiplexer  106  selects either the input terminal  94   c ,  94   e  or  94   i  when a VRM  51  is inserted into the slot  52   d ; and only two VRMs  51  are inserted into the slots  52   a ,  52   b  and  52   c . The selection of one of the input terminals  94   c ,  94   e  and  94   i  routes the PhaseE synchronization signal to the synchronization signal communication line  64  to establish one of the phases of a three phase system  50 . 
     Referring to FIG. 25, in some embodiments of the invention, the phase synchronization generator  54  includes D-type flip flops  150   b ,  150   c ,  150   d  and  150   e  that are each clocked by the CLK signal and provide the PhaseA, PhaseB, PhaseC, PhaseD, PhaseE, PhaseF, PhaseG and PhaseH synchronization signals. In this manner, the non-inverting output terminal of the flip-flop  150   b  provides the PhaseA synchronization signal, and the inverting output terminal of the flip-flop  150   b  provides the PhaseD synchronization signal. The non-inverting output terminal of the flip-flop  150   c  provides the PhaseB synchronization signal, and the inverting output terminal of the flip-flop  150   c  provides the PhaseF synchronization signal. The non-inverting output terminal of the flip-flop  150   d  provides the PhaseC synchronization signal, and the inverting output terminal of the flip-flop  150   d  provides the PhaseG synchronization signal. The non-inverting output terminal of the flip-flop  150   e  provides the PhaseE synchronization signal, and the inverting output terminal of the flip-flop  150   e  provides the PhaseH synchronization signal. 
     The generator  54  also includes a D-type flip-flop  150   a  that is clocked by the SYS_CLK signal and furnishes two signals (called PhaseI and PhaseJ) that are intermediate signals that are used to generate the synchronization signals, as described below. The non-inverting output terminal of the flip-flop  150   a  provides the PhaseI synchronization signal, and the inverting output terminal of the flip-flop  150   a  provides the PhaseJ synchronization signal. 
     The non-inverting input terminal of the flip-flop  150   a  receives a signal (called L 1 ) from the output terminal of logic  160  that combines the following synchronization signals in the following manner to produce the L 1  signal: 
     
       
           L   1 =(Phase A ∩Phase B ∩Phase C ∩Phase H )∪(Phase D ∩Phase E ∩Phase F ∩Phase G )  Eq. 1 
       
     
     The non-inverting input terminal of the flip-flop  150   b  receives a signal (called L 2 ) from the output terminal of logic  180  that combines the following synchronization signals in the following manner to produce the L 2  signal: 
     
       
           L   2 =(Phase I ∩Phase E ∩Phase F ∩Phase G )∪(Phase J ∩Phase A ∩Phase B ∩Phase H )∪(Phase J ∩Phase A ∩Phase F ∩Phase G )  Eq. 2 
       
     
     The non-inverting input terminal of the flip-flop  150   c  receives a signal (called L 3 ) from the output terminal of logic  220  that combines the following synchronization signals in the following manner to produce the L 3  signal: 
     
       
           L   3 =(Phase J ∩Phase A ∩Phase G ∩Phase H )∪(Phase B ∩Phase C ∩Phase H )  Eq. 3 
       
     
     The non-inverting input terminal of the flip-flop  150   d  receives a signal (called L 4 ) from the output terminal of logic  240  that combines the following synchronization signals in the following manner to produce the L 4  signal: 
     
       
           L   4 =(Phase J ∩Phase A ∩Phase B ∩Phase H )∪(Phase J ∩Phase B ∩Phase C ∩Phase D )∪(Phase B ∩Phase C ∩Phase H )  Eq. 4 
       
     
     The non-inverting input terminal of the flip-flop  150   e  receives a signal (called L 5 ) from the output terminal of logic  260  that combines the following synchronization signals in the following manner to produce the L 5  signal: 
       L   5 =(Phase I ∩Phase G ∩)Phase J ∩Phase D )∪(Phase B ∩Phase E ∩Phase C ∩Phase F )  Eq. 5 
     The phase synchronized generator may assume numerous different forms. For example, FIG. 26 depicts an embodiment  500  of another phased synchronized generator in accordance with the invention that may be used in place of the generator  54 . In some embodiments of the invention, the phase synchronized generator  54  includes SR-type flip flops  300   b ,  300   c ,  300   d  and  300   e  that are each clocked by the SYS_CLK signal and provide the PhaseA, PhaseB, PhaseC, PhaseD, PhaseE, PhaseF, PhaseG and PhaseH synchronization signals. In this manner, the non-inverting output terminal of the flip-flop  300   b  provides the PhaseA synchronization signal, and the inverting output terminal of the flip-flop  300   b  provides the PhaseD synchronization signal. The non-inverting output terminal of the flip-flop  300   c  provides the PhaseB synchronization signal, and the inverting output terminal of the flip-flop  300   c  provides the PhaseF synchronization signal. The non-inverting output terminal of the flip-flop  300   d  provides the PhaseC synchronization signal, and the inverting output terminal of the flip-flop  300   d  provides the PhaseG synchronization signal. The non-inverting output terminal of the flip-flop  300   e  provides the PhaseE synchronization signal, and the inverting output terminal of the flip-flop  300   e  provides the PhaseH synchronization signal. 
     The generator  500  also includes an SR-type flip-flop  300   a  that is clocked by the SYS_CLK signal and furnishes two signals (called PhaseI and PhaseJ) that are intermediate signals that are used to generate the synchronization signals, as described below. The non-inverting output terminal of the flip-flop  300   a  provides the PhaseI synchronization signal, and the inverting output terminal of the flip-flop  300   a  provides the PhaseJ synchronization signal. 
     The S input terminal of the flip-flop  300   a  receives a signal (called S 1 ) from an output terminal of logic  310  that combines the following synchronization signals in the following manner to produce the S 1  signal: 
     
       
           S   1 =(Phase A ∩Phase B ∩Phase C ∩Phase H )∪(Phase D ∩Phase E ∩Phase F ∩Phase G )  Eq. 6 
       
     
     The R input terminal of the flip-flop  300   a  receives a signal (called R 1 ) from another output terminal of the logic  310  that combines the following synchronization signals in the following manner to produce the R 1  signal: 
     
       
           R   1 =((Phase A ∩Phase F )∪(Phase B ∩Phase E ))∪((Phase C ∩Phase D )∪(Phase G ∩Phase H ))  Eq. 7 
       
     
     The S input terminal of the flip-flop  300   b  receives a signal (called S 2 ) from an output terminal of logic  340  that combines the following synchronization signals in the following manner to produce the S 2  signal: 
     
       
           S   2 =Phase I ∩Phase E ∩Phase F ∩Phase G   Eq. 8 
       
     
     The R input terminal of the flip-flop  300   b  receives a signal (called R 2 ) from another output terminal of the logic  310  that combines the following synchronization signals in the following manner to produce the R 2  signal: 
     
       
           R   2 =(Phase I ∩Phase H )∪(Phase B ∩Phase E )∪(Phase C ∩Phase F )  Eq. 9 
       
     
     The S input terminal of the flip-flop  300   c  receives a signal (called S 3 ) from an output terminal of logic  360  that combines the following synchronization signals in the following manner to produce the S 3  signal: 
     
       
           S   3 =Phase J ∩Phase A ∩Phase G ∩Phase H   Eq. 10 
       
     
     The R input terminal of the flip-flop  300   c  receives a signal (called R 3 ) from another output terminal of the logic  360  that combines the following synchronization signals in the following manner to produce the R 3  signal: 
     
       
           R   3 =(Phase I ∩Phase G )∪Phase E ∪(Phase D ∩Phase G )  Eq. 11 
       
     
     The S input terminal of the flip-flop  300   d  receives a signal (called S 4 ) from an output terminal of logic  380  that combines the following synchronization signals in the following manner to produce the S 4  signal: 
     
       
           S   4 =Phase J ∩Phase A ∩Phase B ∩Phase H   Eq. 12 
       
     
     The R input terminal of the flip-flop  300   d  receives a signal (called R 4 ) from another output terminal of the logic  360  that combines the following synchronization signals in the following manner to produce the R 4  signal: 
     
       
           R   4 =(Phase I ∩Phase E )∪Phase F ∪(Phase A ∩Phase E )  Eq. 13 
       
     
     The S input terminal of the flip-flop  300   e  receives a signal (called S 5 ) from an output terminal of logic  400  that combines the following synchronization signals in the following manner to produce the S 5  signal: 
     
       
           S   5 =(Phase I ∩Phase G )∪(Phase J ∩Phase D )∪(Phase C ∩Phase F )  Eq. 14 
       
     
     The R input terminal of the flip-flop  300   e  receives a signal (called R 5 ) from another output terminal of the logic  400  that combines the following synchronization signals in the following manner to produce the R 5  signal: 
       R   5 =Phase J ∩Phase A ∩Phase F ∩Phase G   Eq. 15 
     While the invention has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the invention.

Technology Classification (CPC): 7