Patent Abstract:
A method of retaining the integrity of a photoresist pattern is provided where the patterned photoresist is treated prior to etching the principle layer. The pre-etch treatment encompasses a plasma treatment. In some embodiments employing an anti-reflective coating (ARC) layer, an isolation/protective layer is used to isolate the ARC from the photoresist. In some embodiments, the pre-etch treatment, advantageously provides for patterning the isolation/protection layer.

Full Description:
BACKGROUND 
     1. Field of the Invention 
     This invention relates to a method for manufacturing integrated circuits and, more specifically to a method for retaining the integrity of a photoresist pattern during the manufacture of semiconductor integrated circuits. 
     2. Related Art 
     In the manufacture of semiconductor integrated circuits, a variety of photolithographic steps are employed. These photolithographic steps encompass forming a layer of photosensitive material, photoresist, overlying a surface of a semiconductor wafer or substrate and defining a pattern therein. Typically, the pattern formed is used to mask portions of an underlying layer to allow unmasked portions of the underlying layer to be removed. The removal of the material of such underlying layers is often performed using a plasma etching process, for example a reactive ion etch process. While in some etch processes the photoresist layer maintains its integrity, that is little or no photoresist is removed and the cross-sectional profile of the resist remains essentially unchanged, in other etch processes the photoresist is removed at a rate comparable to the removal rate of the underlying layer. This loss of integrity is known to affect the patterning of the underlying layer. For example, in some cases the desired feature sizes, as defined by the original photoresist pattern, are not reproduced. In some embodiments portions of the desired features are missing and in some cases both feature size and presence are affected. 
     Various attempts have been made to improve photoresist integrity during semiconductor processing. For example, it is generally known that baking the photoresist layer, often referred to as a hard bake, after the pattern is formed and immediately prior to a plasma etch improves integrity. In addition, it is known that a blanket exposure of the patterned photoresist with an ultraviolet (UV) light improves photoresist integrity. It is also known to use both a hard bake and UV exposure in combination to improve photoresist integrity. However, such independent or combined use of bakes and blanket UV exposure are at best marginally acceptable for some necessary etch processes, for example some metal etch processes. 
     Therefore it would be desirable for there to be a process for forming a patterned photoresist layer with improved integrity for use in some etch processes. It would also be desirable for this process to be readily integrated into standard semiconductor processing. 
     SUMMARY 
     A method of retaining the integrity of an as formed pattern of a photoresist layer after a plasma etch process is provided. Embodiments in accordance with the present invention provide a plasma treatment for a patterned photoresist layer. In some embodiments an I-line photoresist is employed; in other embodiments a deep UV (DUV) photoresist is employed. 
     The plasma treatment of the present invention is advantageously performed prior to a plasma etch process for etching a layer or layers underlying the patterned photoresist. In some embodiments of the present invention the plasma treatment provided additionally serves to etch a silicon oxide layer formed over an underlying metal layer. In some embodiments of the present invention a plasma encompassing a fluorocarbon is employed for the plasma treatment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. For ease of understanding and simplicity, where elements are common between illustrations, common numbering of those elements is employed between illustrations. 
     FIGS. 1 a  and  1   b  are cross-sectional views of a portion of a semiconductor integrated circuit depicting portions of a patterned photoresist layer; 
     FIG. 2 is a cross-sectional view of a portion of a semiconductor integrated circuit showing an etched pattern having severe photoresist degradation in a manner common to the prior art; and 
     FIGS. 3 a  and  3   b  are cross-sectional views of the portion of the semiconductor integrated circuit depicted in FIGS. 1 a  and/or  1   b  at subsequent stages of a process in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     As embodiments of the present invention are described with reference to the drawings, various modifications or adaptations of the specific methods and or structures may become apparent to those skilled in the art. For example, in some embodiments of the present invention, a silicon oxynitride layer is employed in place of a silicon oxide layer. All such modifications, adaptations or variations that rely upon the teachings of the present invention, and through which these teachings have advanced the art, are considered to be within the spirit and scope of the present invention. 
     In FIG. 1 a , a cross-sectional view of an embodiment of a semiconductor integrated circuit depicting a patterned photoresist layer is shown. A metal layer  20  is represented overlying a semiconductor substrate  10 . Metal layer  20  encompasses aluminum, copper or any of the alloys of aluminum and copper as are known. In addition, layer  20  includes any of the known multilayer metal films, for example an aluminum film overlying a barrier layer of titanium nitride (TiN). 
     Layer  30  is an anti-reflective coating (ARC). Such ARC layers  30  are used to reduce or eliminate the effects of standing waves formed by reflections during exposure of the photoresist layer (not shown) from which photoresist portions  50  are formed. As known, the use of ARC layers often improves the resolution of an image projected onto the photoresist layer for forming portions  50 . As depicted, ARC layer  30  is an inorganic material, for example TiN or titanium tungsten (TiW), and is patterned with underlying metal layer  20 . In some embodiments an organic ARC layer (not shown) is used. Typically, such organic ARC layers are patterned when the photoresist layer is developed to form portions  50 . Finally, in some embodiments of the present invention, no ARC layer  30  is employed. 
     Photoresist portions  50  are formed by projecting an image onto the photoresist layer (not shown) and subsequently developing that image. Portions  50  can be formed from a variety of materials. Typically, such materials are sensitive to a specific, narrow range of the electromagnetic spectrum. For example, some photoresist materials are sensitive to the mercury vapor I-line at 365 nanometers (nm), while other materials are sensitive to what is known as the deep ultra violet (DUV) range at about 245 nm. While in some embodiments of the present invention, an I-line photoresist material having a thickness  52  of approximately 1.3 micron (μm) or a DUV sensitive photoresist material having a thickness  52  of approximately 1.0 μm is employed, it will be understood that embodiments of the present invention also encompass other appropriate photosensitive materials and thicknesses; for example, G-line (436 nm) and electron beam resist materials. 
     Still referring to FIG. 1 a , semiconductor substrate  10  is depicted as having a minimum of complexity for simplicity and ease of understanding only. Thus it is understood that embodiments of the present invention include alternate substrates  10  having a variety of complexity. For example, in some embodiments substrate  10  is an N-type or P-type substrate, or is an N-type or P-type substrate encompassing N and/or P-type well regions (not shown) and/or an epitaxial layer (not shown). Alternatively, in some embodiments, substrate  10  encompasses a silicon on insulator (SOI) structure, or any other appropriate semiconductor substrate material or structure. 
     Turning now to FIG. 1 b , another embodiment of the present invention is depicted incorporating an isolation/capping layer  40 . As known, some photosensitive materials are not compatible with some ARC materials. Thus where photoresist portions  50  are to be formed, for example of a DUV photoresist material, a TiN or TiW ARC layer  30  will typically interact with the DUV photoresist material if direct contact between the materials occurs. Hence to prevent this interaction between the ARC material and DUV photoresist, capping/isolation layer  40  is used. An additional benefit of capping layer  40  is to provide for improved adhesion of the DUV photoresist than would be possible if the DUV photoresist were disposed directly on ARC layer  30 . Generally layer  40  is a silicon oxide material formed by chemical vapor deposition or other appropriate method and has a thickness of between 10 to 80 nm. However, other materials, for example a silicon oxynitride, can also be advantageously employed. 
     Thus, FIGS. 1 a  and  1   b , as described, are representative of a photoresist pattern, prior to etching the underlying metal layer  20 . In addition, it will be understood that both FIGS. 1 a  and  1   b  are consistent with semiconductor processing as known and serve as common points from which prior art processes and embodiments of the present invention diverge. 
     Turning now to FIG. 2, a cross-sectional view of a portion of a semiconductor integrated circuit showing an etched pattern having severe photoresist degradation is depicted. FIG. 2 is meant to be representative of the structures of FIGS. 1 a  and/or  1   b  after etching of layer  20  to form metal portions  22  in the manner of the prior art. As shown, after etch, residual photoresist portions  55  are markedly changed with respect to portions  50  as depicted in FIGS. 1 a  and/or  1   b . The essentially square corners of portions  50  (FIGS. 1 a  and  1   b ) are gone and residual thickness  54  is significantly less than thickness  52  (FIGS. 1 a  and  1   b ). As shown, the severe degradation depicted by portions  55  results in associated degradation of metal portions  22 . For example, corners  24  are deformed from the original shape of photoresist portions  50 . While not shown, it has been reported that some processes for etching metal layer  20  to form metal portions  22  will remove essentially all of original photoresist portions  50  resulting in metal portions  22  with severe deformations. Thus it can be seen that a method for preventing such severe deformation of photoresist portions  50  (FIGS. 1 a  and  1   b ) is desirable. 
     FIG. 3 a  is a cross-sectional view of the portion of the semiconductor integrated circuit depicted in FIG. 1 b  after a plasma treatment in accordance with embodiments of the present invention. Photoresist portions  60  are depicted overlying patterned isolation portions  45 , ARC layer  30 , metal layer  20  and substrate  10 . It should be noted that while treated photoresist portions  60  are depicted having rounded corners  62 , this representation is presented solely to distinguish treated portions  60  from untreated portions  50  (FIGS. 1 a  and  1   b ). Thus after treatment, photoresist portions  60  may or may not have such rounded corners  62 . 
     In some embodiments of the present invention after photoresist portions  50  (FIG. 1 b ) are defined, substrate  10  is positioned in a vacuum chamber (not shown) and treated with a plasma for a predetermined time. For example, in some embodiments a plasma formed from fluoroform (CHF 3 ), carbon tetrafluoride (CF 4 ), nitrogen (N 2 ) and argon (Ar) is ignited in a vacuum chamber at a pressure of between approximately 100 to 300 milliTorr (mT) using between approximately 100 to 600 watts (W) of electrical energy. Once ignited, the plasma is maintained for a predetermined time sufficient to adequately treat portions  50  and form treated photoresist portions  60 . It has been found that a time of between approximately 5 to 20 seconds (sec) is appropriate. It will be understood that the above mentioned ranges for pressure, electrical energy and time are dependent upon, among other things, the specific resist employed for portions  50 . Thus, these ranges are given for illustrative purposes and are not intended to be limiting. Rather, any appropriate combination of pressure, electrical energy and time that results in forming treated photoresist portions  60  is within both the scope and spirit of the present invention. 
     It will also be understood that within each appropriate gas mixture used for forming treated portions  60 , the specific ratio of the individual components of the mixture can vary to meet specific requirements. Therefore, some embodiments of the present invention encompass gas mixtures of CHF 3  with a flow rate of between approximately 30 to 60 standard cubic centimeters per minute (sccm), CF 4  with a flow rate between approximately 0 to 40 sccm, N 2  with a flow rate of between approximately 10 to 40 sccm and Ar with a flow rate of between approximately 150 to 450 sccm. It will be understood that, as for the other ranges previously mentioned, the above flow rate ranges are likely to be different where different resist materials are used for forming photoresist portions  50  (FIG. 1 b ). Thus, these flow rate ranges are given for illustrative purposes and are not intended to be limiting. Hence, any appropriate combination of pressure, electrical energy, time and gas flow rates that results in forming treated photoresist portions  60  is within both the scope and spirit of the present invention. 
     Still referring to FIG. 3 a , it has been found that for embodiments having a silicon oxide or silicon oxynitride isolation/capping layer  40  (FIG. 1 b ), the above described plasma treatment for forming treated portions  60  also serves to etch layer  40  to form etched isolation portions  45 . Thus, in some embodiments of the present invention a plasma is maintained in the vacuum chamber for a predetermined time sufficient to both form isolation/capping portions  45  and treated photoresist portions  60 , respectively. For example, where photoresist portions  50  (FIG. 1 b ) are a DUV resist material and isolation layer  40  is a silicon oxide material having a thickness of approximately 20 nm, it has been found that 15 sec in a plasma formed from a gas mixture of 50 sccm CHF 3 , 20 sccm N 2  and 300 sccm Ar, at a pressure of approximately 150 mT and at 500 W of electrical energy advantageously form treated portions  60 . 
     Turning now to FIG. 3 b , the structure of FIG. 3 a  is depicted subsequent to etching ARC layer  30  and metal layer  20  to form patterned ARC portions  35  and metal portions  25 . In addition, treated photoresist portions  60  (FIG. 3 a ) are represented as post-etch photoresist portions  65  having rounded corners  67 . While the exact shape of post-etch portions  65  vary, as represented herein, post-etch portions  65  retain most of their original shape after metal etch. As a result of retaining the integrity of the photoresist pattern, the dimensions of the underlying metal portions  25  are much improved as compared to prior art metal portions  22  (FIG.  2 ). 
     Thus it can be seen that embodiments in accordance with the present invention have been described that provide for retaining the integrity of a photoresist pattern during a subsequent plasma etch process. It is known that metal etch processes employed in the semiconductor arts require some interaction with the photoresist to attain the highest anisotropic character. Thus it is significant that embodiments of the present invention allow for sufficient interaction with the photoresist to provide this anisotropy, while not allowing degradation to the degree common in the prior art. It will also be understood that embodiments of the present invention have been described that are readily integrated into a typical semiconductor fabrication process. For example, in some embodiments of the present invention the aforementioned plasma treatment is accomplished using a standard oxide etch system, for example a LAM® 4520 or the like (LAM is a registered trademark of LAM Research, Inc., Fremont, Calif.), while in some embodiments the plasma treatment is incorporated as a preliminary step of a monolithic metal etch process. 
     In addition, it will be realized that embodiments of the present invention incorporate various combinations of photoresist materials and ARC materials both with and without a capping or isolation layer. Thus, for example, in some embodiments an I-line resist material is used with both a capping layer and an ARC layer, while other embodiments incorporate a DUV resist material, an organic ARC material and no capping layer.

Technology Classification (CPC): 7