Patent Abstract:
A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

Full Description:
BACKGROUND 
       [0001]    The present invention relates to switching devices and, more specifically, to field effect transistors (FETs) formed with carbide drains and sources. 
         [0002]    Switching devices based on nanostructures such as carbon nanotubes, graphene, or semiconducting nanowires have potential due to the high carrier mobility and small dimensions that such nanostructures can provide. However, one of the many challenges a technology based on such nanostructures must overcome is compatibility with the high layout density that traditional silicon CMOS technology currently supports. For high layout density, the source/drain and gate contacts to the switching device built around each nanostructure must all be precisely positioned. In silicon CMOS, this precise positioning is enabled by using gate shadowing to define implanted junction profiles and by the self-aligned silicide process. 
       SUMMARY 
       [0003]    According to one embodiment of the present invention, a field effect transistor is disclosed. The field effect transistor of this embodiment, a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion. The field effect transistor also includes a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nano structure. 
         [0004]    According to another embodiment a method of forming a field effect transistor is disclosed. The method of this embodiment includes forming a substrate; forming an insulating layer over the substrate; forming an insulating carbon layer over the substrate; depositing one or more nanostructures on an upper surface of the insulating carbon layer; covering at least a portion of the one or more nanostructures and any insulating carbon under the covered nanostructures with a gate stack; and converting exposed portions of the insulating carbon layer to a metal carbide. 
         [0005]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0006]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0007]      FIG. 1  shows an early stage in the production of FET according to one embodiment of the present invention; 
           [0008]      FIG. 2  shows the structure of  FIG. 1  after an active region has been patterned into the carbon layer. 
           [0009]      FIG. 3  shows the structure shown in  FIG. 2  after a gate stack has been formed over a portion of the active region. 
           [0010]      FIG. 4  shows the structure of  FIG. 3  after spacers have been formed on the sidewalls of the gate stack. 
           [0011]      FIG. 5  shows the structure of  FIG. 4  after the carbon first portion and carbon second portion have been converted to a metal carbide. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    One embodiment of the present invention is directed to a self-aligned carbide source/drain contact formation process for a FET having a nanostructure based channel region. In particular, disclosed herein is a platform for building self-aligned devices from any deposited nanostructure, including carbon nanotubes, graphene, or semiconducting nanowires. The nanostructures are deposited on an insulating carbon underlayer, and a gate stack is patterned atop the nanostructures. Metal is then deposited everywhere. Any region of the carbon under-layer not protected by the gate stack is converted to a metal carbide contact, and the metal is then removed selectively to the metal carbide contacts, resulting in metal carbide source/drain contacts which are self-aligned to the gate stack. 
         [0013]    With reference now to  FIG. 1 , an example of a wafer in the production process of a FET according to one embodiment of the present invention is shown. The wafer includes a substrate  102 . The substrate  102  may be formed of any material but, in one embodiment, is formed of silicon or a silicon based material. An insulating layer  104  is formed on top of the substrate  102 . The insulating layer  104  may be formed of any electrical insulator. In one embodiment, the insulating layer  104  is formed of a silicon nitride. In another embodiment, the insulating layer  104  is a Buried silicon OXide (BOX) layer. 
         [0014]    A carbon layer  106  is formed over the insulating layer  104 . As will be shown in greater detail below, both the source and drain of a FET is formed in this layer. In one embodiment, the carbon layer  106  is an insulating carbon layer that remains insulating even when exposed to high (greater than annealing) temperatures. On example of such an insulating carbon is a diamond based layer. The diamond based layer may be a crystalline film, a polycrystalline film, or a nano or ultranano crystalline diamond film. The diamond film may be deposited by a variety of chemical vapor deposition (CVD) processes including, without limitation, thermal, hot-wire or microwave assisted CVD. In one embodiment, the carbon layer may be a diamondlike, or an amorphous carbon material. 
         [0015]    One or more nanostructures  108  are formed or deposited on top of the carbon layer  106 . For example, the nanostructures  108  may be carbon nanotubes, graphene, or semiconducting nanowires. In one embodiment, the nanostructures  108  become conductive when voltage is applied to them and non-conductive otherwise. As shown in greater detail below, the nanostructures  108  form the channel of a FET in one embodiment. 
         [0016]      FIG. 2  shows the structure of  FIG. 1  after an active region  202  has been patterned into the carbon layer  106 . As shown, a disposable hard mask such as silicon dioxide may have been deposited and patterned over the active region, and then the exposed portions of the carbon layer  106  removed. Of course, the carbon layer  106  could have been formed as shown in  FIG. 2  directly. Alternately, instead of removing the non-active regions of the carbon, the non-active regions of carbon could be covered by a hardmask such as silicon nitride. 
         [0017]    Each active region  202  may be used to form one or more FETs. The number of nanostructures  108  is variable and may be one or more. It will be understood that the more nanostructures  108  used to form a channel, the more current the FET will carry in the “on” state. 
         [0018]      FIG. 3  shows the structure shown in  FIG. 2  after a gate stack  302  has been formed over a portion of the active region  202 . The gate stack  302  includes a gate dielectric layer  304 . The dielectric layer  304  may be formed of any type of dielectric. 
         [0019]    The gate stack  302  also includes a gate  306 . The gate may be formed of any appropriate gate material, including polysilicon (which can be doped and/or silicided) and metal. 
         [0020]    The orientation of the gate stack  302  may be varied. However, in one embodiment, the gate stack  302  is not parallel to one or more of the nanostructures  108 . In one embodiment, the gate stack  302  has a length w and is disposed such that the l is substantially perpendicular to a nanostructure length l. The angle between w and l is not limited an may vary from 1 to 179 degrees. The gate stack  302  preferably causes the active region to be divided into at least a first portion  308  and a second portion  310 . It shall be understood that multiple gate stack  302  may be placed on a single active region  202 , forming stacked FETs, and that one gate stack  302  can run over multiple active regions  202 , forming multiple FETs with gates that are tied together. 
         [0021]    In one embodiment, the exposed portions of the nanostructures  108  may be modified at this point in the production run. The modification may include, but is not limited to, chemical doping or implanting and may vary depending on the circumstances. 
         [0022]      FIG. 4  shows the structure of  FIG. 3  after spacers  402  have been formed on the sidewalls of the gate stack  302 . In  FIG. 4  (and  FIG. 5  below), the portion of the gate stack  302  (and the spacers  402  formed on its side) extending beyond the active region are not shown in order to illustrate the structure more clearly. 
         [0023]    The spacers  402  may be formed, for example, by a conform material deposition followed by an anistropic etch. In one embodiment, the spacers  402  are formed of a silicon nitride material. 
         [0024]      FIG. 5  shows the structure of  FIG. 4  after the carbon first portion  308  and carbon second portion  310  have been converted to a metal carbide. The structure shown in  FIG. 5  may be (with addition of one or more connectors) operated as a FET. The metal carbide first portion  308 ′ and the metal carbide second portion  310 ′ are separated by an insulating carbon portion  502 . The insulating carbon portion  502  is formed by the portion of the active region  202  that is covered by the gate stack  302  and spacers  402 . 
         [0025]    The first portion  308  and carbon second portion  310  may be converted to the metal carbide first portion  308 ′ and the metal carbide second portion  310 ′ by depositing a metal over the structure of  FIG. 4 , annealing to a temperature high enough to for the metal and carbon to react, and etching the remaining unreacted metal to form a metal carbide from the first portion  308  and the second portion  310 . To enable this process, the metal must not react with the spacers formed on the gate sidewall. The metal may or may not react with the exposed portions of the deposited nanostructures  108 . The metal may or may not react with the gate material. Removal of the un-reacted metal must be performed selectively to the gate metal, metal carbide, spacers, and any other expose material on the wafer. 
         [0026]    The metal carbide first portion  308 ′ may form a source contact and the metal carbine second portion  310 ′ may form a drain contract, or vice versa, to the portion of the nanostructure  108  that is underneath the gate. Regardless, the source and drain are separated by insulating carbon portion  502 . Accordingly, in the absence of an external voltage applied to the gate  306 , the source and drain are electrically separated. 
         [0027]    A portion of the nanostructure  108  is under the gate stack  302 . Application of a voltage to the gate  306  will cause that portion of the nanostructure  108  under the gate stack  302  to become conductive. Once conductive, the nanostructure  108  electrically couples the metal carbide first portion  308 ′ and the metal carbide second portion  310 ′ and allows for current to pass between them. 
         [0028]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0029]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
         [0030]    The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0031]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Technology Classification (CPC): 1