Patent Abstract:
An amplifier circuit includes a first amplifier amplifying an input signal and outputting a first amplified signal, a second amplifier amplifying the first amplified signal and outputting a second amplified signal, and a feedback circuitry feeding back the second amplified signal to the input of the second amplifier. The feedback circuitry includes a feedback transistor that keeps the input level of the second amplifier constant.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     The application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-220000, filed on Aug. 28, 2008, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The present invention relates to an amplifier circuit and may be used in a high-speed optical communication apparatus or the like. 
     BACKGROUND 
     In recent years, the amount of communication has been ever-increasing due to popularization of broadband networks, such as the Internet, and establishment of a large-capacity photonic network has been demanded accordingly. Under the present circumstances, a network at a communication speed of 10 Gbps is in the mainstream. Development of transmitters including an optical modulator and receivers adaptable to a communication speed to 40 Gbps has been demanded to cope with a further increase in the amount of communication. In order to modulate an optical signal of 40 Gbps, an optical modulator of LiNbO3 (LN modulator) is used, for example. Driving the LN modulator at 40 Gbps requires an amplifier circuit capable of a high-speed and large-amplitude modulated output. 
       FIG. 7  illustrates a two-stage feedback amplifier circuit according to a related art. In  FIG. 7 , the two-stage feedback amplifier circuit  70  includes an amplifier circuit of a two-stage configuration, in which an output of a second-stage amplifier is fed back to a bias of a first-stage amplifier. That is, electric signals including modulation information input to “IN” and “IN” (negative logic) are amplified by corresponding two stages of transistors T 1  and T 2  and T 3  and T 4 , respectively, and are output from output terminals “OUT”. The output of the transistor T 2  is fed back to the bias of the transistor T 1 , which is a first-stage amplifier, whereas the output of the transistor T 4  is fed back to the bias of the transistor T 3 , which is a first-stage amplifier. Accordingly, an amplification gain of a high-frequency component increases. 
     That is, a feedback current from the output of the transistor T 2  flows through resistors R 2  and R 3  and is fed back to the bias of the transistor T 1 . Likewise, a feedback current from the output of the transistor T 4  flows through resistors R 5  and R 6  and is fed back to the bias of the transistor T 3 . The configuration enables an increase in amplification gain of a high-frequency component and a broader amplification band. 
       FIG. 8  illustrates a configuration of a two-stage feedback amplifier circuit according to a related art. In the two-stage feedback amplifier circuit  80  illustrated in  FIG. 8 , source follower transistors T 5  and T 6  are connected between resistors R 2  and R 3  and between resistors R 5  and R 6 , respectively. A feedback current from an output of a transistor T 2  is supplied to a bias of a transistor T 1 , which is a first-stage amplifier, via the transistor T 5 . A feedback current from an output of a transistor T 4  is supplied to a bias of a transistor T 3 , which is a first-stage amplifier, via the transistor T 6 . 
     The following configuration of a multistage high-frequency power amplifier circuit including a plurality of cascaded power amplifying transistors has been known and disclosed in Japanese Unexamined Patent Application Publication No. 2004-193846, for example. That is, in the configuration, distortion of a signal is reduced by allowing a sufficient idle current to flow to an amplifying transistor before the last stage even in a region of a low output power level, thereby enhancing power efficiency. 
     Also, a related art of an amplifier circuit to suppress an influence of feedback capacitance and to realize a broad band at low cost is described in Japanese Unexamined Patent Application Publication No. 08-256024. Also, there is known an amplifier circuit including total-feedback amplifier circuits and level-shift amplifier circuits alternately connected in multi-stages. In the amplifier circuit, a capacitance component provided between transistors of the level-shift amplifier circuit suppresses emitter negative feedback resistance in high frequencies, increases the gain of high frequencies, and realizes a broader bandwidth. Such an amplifier circuit is disclosed in Japanese Unexamined Patent Application Publication No. 10-247831, for example. 
     In the case where the two-stage feedback amplifier circuit illustrated in  FIG. 7  or  8  is used as a driver of an LN optical modulator of a high-speed optical communication apparatus on a transmission side, a signal level necessary to drive the optical modulator is obtained by adjusting the amount of current flown to a current source I. That is, when the LN optical modulator is connected to the output terminals “OUT” and the amplifier circuit is used as a driver of the LN optical modulator, an output amplitude of the driver depends on the amount of current flowing in the current source I, and thus the output amplitude is adjusted by adjusting the amount of current, whereby an output level necessary to drive the optical modulator used is obtained. 
     However, if the amount of current flowing in the current source I is changed in the amplifier circuit illustrated in  FIG. 7  or  8 , the potentials at respective points A, B, and C illustrated in  FIGS. 7 and 8  change at the same time. Particularly, the potential at point C corresponds to a gate potential of the transistor T 2 , which is a second-stage amplifier. An abnormal operation of the transistor T 2  occurs due to a change in potential level at point C, and as a result an output waveform significantly degrades. This is the same in the gate potential on the transistor T 4  side. 
     SUMMARY 
     An amplifier circuit includes a first amplifier amplifying an input signal and outputting a first amplified signal, a second amplifier amplifying the first amplified signal and outputting a second amplified signal, and a feedback circuitry feeding back the second amplified signal to the input of the second amplifier. The feedback circuitry includes a feedback transistor that keeps the input level of the second amplifier constant. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an amplifier circuit according to a first embodiment; 
         FIGS. 2A and 2B  illustrate waveforms of output signals when the amplifier circuit according to the first embodiment is used, wherein  FIG. 2A  illustrates a waveform of an output signal when an output amplitude is set to 4 Vp-p, whereas  FIG. 2B  illustrates a waveform of an output signal when an output amplitude is set to 2 Vp-p; 
         FIGS. 3A and 3B  illustrate waveforms of output signals in a conventional circuit, wherein  FIG. 3A  illustrates a waveform of an output signal when an output amplitude is set to 4 Vp-p whereas  FIG. 3B  illustrates a waveform of an output signal when an output amplitude is set to 2 Vp-p; 
         FIG. 4  illustrates an amplifier circuit according to a second embodiment; 
         FIG. 5  illustrates an amplifier circuit according to a third embodiment; 
         FIG. 6  illustrates an amplifier circuit according to a modification of the third embodiment; 
         FIG. 7  illustrates an amplifier circuit according to a related art; and 
         FIG. 8  illustrates an amplifier circuit according to another related art. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures. 
       FIG. 1  illustrates an amplifier circuit according to a first embodiment. In  FIG. 1 , the amplifier circuit of the first embodiment includes transistors T 11  to T 16 , resistors R 11  to R 16 , and current sources I 1  and I 2 . Here, the transistors T 11  and T 12  the transistors T 13  and T 14  function as a two-stage amplifier circuit. The transistors T 11  and T 12  amplify a signal (modulation signal) input from an input terminal “IN” and output a signal generated at a drain (point A) of the transistor T 12  as an output signal of specific amplitude from a terminal “OUT”. Likewise, the transistors T 13  and T 14  amplify a signal (modulation signal) input from an input terminal “IN” (negative logic) and output a signal generated at a drain (point A′) of the transistor T 14  as an output signal of specific amplitude from a terminal “OUT”. 
     Those outputs are supplied to an LN optical modulator (not illustrated), the LN optical modulator modulates laser light in accordance with the output signals (amplitude modulated output) supplied from the above-described terminals (OUT), and transmits the modulated light to a receiver through an optical fiber cable and a repeater (not illustrated). 
     A bias voltage is applied to a drain of the transistor T 11 , which is a first-stage amplifier, via the resistor R 13 , and also a bias voltage is applied to a drain of the transistor T 13  via the resistor R 16 . Likewise, a bias voltage is applied to the drain of the transistor T 12 , which is a second-stage amplifier, via the resistor R 12 , and also a bias voltage is applied to the drain of the transistor T 14  via the resistor R 15 . The resistors R 11  and R 14  are voltage-dividing resistors. The potential at point B is determined by set values (resistance values) of the resistors R 11  and R 12 , whereas the potential at point B′ is determined by set values (resistance values) of the resistors R 14  and R 15 . 
     In  FIG. 1 , the transistor T 15  is connected between point B and one end of the resistor R 13  (point D). Specifically, one end of the resistor R 13  (point D) connects to a source of the transistor T 15 , and a drain of the transistor T 15  connects to a junction point between the resistors R 11  and R 12  (point B). A gate voltage (described below) is applied to a gate of the transistor T 15  (point E). 
     Likewise, one end of the resistor R 16  (point D′) connects to a source of the transistor T 16 , and a drain of the transistor T 16  connects to a junction point between the resistors R 14  and R 15  (point (B′). A gate voltage (described below) is applied to a gate of the transistor T 16  (point E′). 
     Also, the amplifier circuit according to the first embodiment illustrated in  FIG. 1  is supplied with power VDD. A current flowing through the resistors R 11  and R 12  and the transistor T 12  (and the resistors R 14  and R 15  and the transistor T 14 ) flows in the current source I 1 , whereas a current flowing through the resistor R 11 , the transistor T 15 , the resistor R 13 , and the transistor T 11  (and the resistor R 14 , the transistor T 16 , the resistor R 16 , and the transistor T 13 ) flows in the current source I 2 . 
     In the above-described configuration, when signals are supplied from “IN” and “IN” (negative logic), the signals are amplified by the corresponding two stages of amplifiers (the transistors T 11  and T 12  and the transistors T 13  and T 14 ), and a differential output of the both signals is supplied from the terminals “OUT” to the above-described LN optical modulator. The current source I 1  is adjusted to specific current value so that an amplitude modulated output corresponding to the optical modulator may be obtained. For example, the adjustment is performed in a range from 40 mA to 160 mA. 
     At the time, the potential levels at points B and B′ change, as described above in relation to the related arts. That is, the resistance values of the resistors R 11 , R 12 , R 14 , and R 15  are fixed, but a reference current value changes, so that the potential levels at points B and B′ change. In the first embodiment, however, unlike in the related arts, the transistor T 15  is placed between point B and point D and also the transistor T 16  is placed between point B′ and point D′. With the configuration, even when the potential levels at points B and B′ change, the potential levels at points D and D′ are kept. 
     Therefore, a gate signal E is applied to the gate of the transistor T 15 , whereby change of the potential level at point D is prevented. Likewise, a gate signal E′ is applied to the gate of the transistor T 16 , whereby change of the potential level at point D′ is prevented. With the configuration, the potential levels at points C and C′ are kept. Accordingly, the transistors T 12  and T 14  in output stages may be normally driven without affecting the gate voltages of the transistors T 12  and T 14 , which are second-stage amplifiers, so that an output at an amplitude level corresponding to the optical modulator may be supplied to the optical modulator. 
     The gate signals E and E′ applied to the gates of the transistors T 15  and T 16  may set the potential levels at points D and D′, calculated by the following expressions.
 
Voltage( D )=potential at point  C +(resistance value of  R 13×(current value of current source  I 2/2))
 
Voltage( D ′)=potential at point  C ′+(resistance value of  R 16×(current value of current source  I 2/2))
 
Therefore, the amplifiers in the last stages may be normally operated and a normal drive signal may be supplied to the optical modulator without affecting the potential levels at points D and D′ by supplying gate signals satisfying the above-described condition to the gates of the transistors T 15  and T 16 , even when the current value of the current source I 1  is adjusted.
 
       FIGS. 2A and 2B  illustrate waveforms of output signals when the amplifier circuit illustrated in  FIG. 1  is used.  FIG. 2A  illustrates a waveform of an output signal when an output amplitude is set to 4 Vp-p, whereas  FIG. 2B  illustrates a waveform of an output signal when an output amplitude is set to 2 Vp-p. In the first embodiment, as illustrated in  FIGS. 2A and 2B , the waveform of the output signal does not change even when the current source I 1  is adjusted and when the output amplitude is adjusted from 4 Vp-p to 2 Vp-p, so that the transistors T 12  and T 14  in the output stages are normally driven and that a favorable signal waveform may be supplied to the optical modulator. 
       FIGS. 3A and 3B  are for comparison with the waveforms in the above-described embodiment and illustrate waveforms of output signals in a conventional circuit. As can be understood, the waveform at the output amplitude set to 2 Vp-p illustrated in  FIG. 3B  is significantly degraded compared to the waveform at the output amplitude set to 4 Vp-p illustrated in  FIG. 3A . 
     Accordingly, as described above in the first embodiment, a normal drive signal may be supplied to the optical modulator without affecting the gate voltages of the amplifiers in the last stages by providing the transistors T 15  and T 16  and by applying gate signals satisfying the above-described condition to the gates of the transistors T 15  and T 16 , even when the output amplitude is adjusted. 
       FIG. 4  illustrates an amplifier circuit according to a second embodiment. The amplifier circuit of the second embodiment has the same configuration as that of the above-described amplifier circuit illustrated in  FIG. 1  except that transistors T 17  and T 18  are provided. Thus, the circuit elements are the same as those in the above-described first embodiment and are denoted by the same reference numerals. 
     The amplifier circuit of the second embodiment includes transistors T 11  to T 18 , resistors R 11  to R 16 , and current sources I 1  and I 2 . The transistors T 11 , T 12 , T 13 , and T 14  have the same configuration as in the first embodiment, and function as a second-stage amplifier circuit. The transistors T 11  and T 12  amplify a signal input from an input terminal “IN” whereas the transistors T 13  and T 14  amplify a signal input from an input terminal “in” (negative logic), so that specific amplitude modulated output is supplied from terminals “OUT” to an LN optical modulator (not illustrated). 
     A bias voltage is applied to a drain of the transistor T 11 , which is a first-stage amplifier, via the resistor R 13 , and also a bias voltage is applied to a drain of the transistor T 13  via the resistor R 16 . 
     In the second embodiment, there is provided the source follower transistor T 17 , to which a potential at a junction point between the resistors R 11  and R 12  is applied as a gate voltage. A bias voltage is applied to the transistor T 11 , which is a first-stage amplifier, by driving the transistor T 17 . Also, there is provided the source follower transistor T 18 , to which a potential at a junction point between the resistors R 14  and R 15  is applied as a gate voltage. A bias voltage is applied to the transistor T 13 , which is a first-stage amplifier, by driving the transistor T 18 . 
     In the second embodiment, a drain of the transistor T 15  connects to a source of the transistor T 17 , and a source of the transistor T 15  connects to the resistor R 13 . Likewise, a drain of the transistor T 16  connects to a source of the transistor T 18 , and a source of the transistor T 16  connects to the resistor R 16 . Furthermore, specific gate signals E and E′ are applied to gates of the transistors T 15  and T 16 , as in the first embodiment. 
     With the configuration, when signals are supplied from “IN” and “IN” (negative logic) as in the first embodiment, the input signals are amplified by the corresponding two stages of amplifiers (the transistors T 11  and T 12  and the transistors T 13  and T 14 ), and a differential output of the both signals is output from the terminals “OUT” to the LN optical modulator (not illustrated). The current source I 1  is adjusted to specific current value so that an amplitude-modulated output corresponding to the optical modulator may be obtained. 
     At this time, the potential levels at points B and B′ illustrated in  FIG. 4  change as in the first embodiment. That is, the resistance values of the resistors R 11 , R 12 , R 14 , and R 15  are fixed, but the value of flowing current changes, so that the potential levels at points B and B′ change. In the circuit illustrated in FIG.  4 , however, the transistor T 15  is placed between point B and point D and also the transistor T 16  is placed between point B′ and point D′. With the configuration, the potential levels at points D and D′ are not affected. 
     That is, the gate signal E is applied to the gate of the transistor T 15 , whereby change of the potential level at point D is suppressed. Likewise, the gate signal E′ is applied to the gate of the transistor T 16 , whereby change of the potential level at point D′ is suppressed. With the configuration, the potential levels at points C and C′ are kept, so that the transistors T 12  and T 14 , which are second-stage amplifiers, are normally driven and that a drive signal with specific amplitude may be supplied to the optical modulator. 
     In the second embodiment, too, the gate signals E and E′ applied to the gates of the transistors T 15  and T 16  may set the potential levels at points D and D′, calculated by the above-described expressions. 
     Therefore, a normal drive signal may be supplied to the optical modulator without affecting the gate voltages of the amplifiers in the last stages by applying gate voltages satisfying the above-described condition, even when the current value of the current source I 1  is adjusted. 
       FIG. 5  illustrates an amplifier circuit according to a third embodiment. The amplifier circuit of the third embodiment has basically the same configuration as that of the above-described amplifier circuit according to the first embodiment except that the field-effect transistors are replaced by bipolar transistors. Thus, the circuit elements are the same as those in the above-described first embodiment except the transistors are denoted by the same reference numerals. 
     In  FIG. 5 , the amplifier circuit of the third embodiment includes transistors T 21  to T 26 , resistors R 11  to R 16 , and current sources I 1  and I 2 . The transistors T 21  and T 22  and the transistors T 23  and T 24  function as a two-stage amplifier circuit. The transistors T 21  and T 22  amplify a signal input from an input terminal “IN”, and output a signal generated at a collector of the transistor T 22  (point A) as an output signal of specific amplitude from a terminal “OUT”. Likewise, the transistors T 23  and T 24  amplify a signal input from an input terminal “IN” (negative logic), and output a signal generated at a collector of the transistor T 24  (point A′) as an output signal of specific amplitude from a terminal “OUT”. 
     A bias voltage is applied to a collector of the transistor T 21 , which is a first-stage amplifier, via the resistor R 13 , and also a bias voltage is applied to a collector of the transistor T 23  via the resistor R 16 . Likewise, a bias voltage is applied to a collector of the transistor T 22 , which is a second-stage amplifier, via the resistor R 12 , and also a bias voltage is applied to a collector of the transistor T 24  via the resistor R 15 . The resistors R 11  and R 14  are voltage-dividing resistors. The potential at point B is determined by set values (resistance values) of the resistors R 11  and R 12 , whereas the potential at point B′ is determined by set values (resistance values) of the resistors R 14  and R 15 . 
     In the third embodiment, too, the transistor T 25  is connected between point B and one end of the resistor R 13  (point D). Specifically, one end of the resistor R 13  (point D) connects to an emitter of the transistor T 25 , and a collector of the transistor T 25  connects to a junction point between the resistors R 11  and R 12  (point B). A base voltage is applied to a base of the transistor T 25 . 
     Likewise, one end of the resistor R 16  (point D′) connects to an emitter of the transistor T 26 , and a collector of the transistor T 26  connects to a junction point between the resistors R 14  and R 15  (point B′). A base voltage is applied to a base of the transistor T 26 . 
     In the above-described configuration, when signals are supplied from “IN” and “IN” (negative logic), the signals are amplified by the corresponding two stages of amplifiers (the transistors T 21  and T 22  and the transistors T 23  and T 24 ) as in the above-described embodiments, and a differential output of both signals is supplied from the terminals “OUT” to the above-described LN optical modulator. The current source I 1  is adjusted to specific current value so that an amplitude modulated output corresponding to the optical modulator may be obtained. 
     At this time, unlike in the related arts, the transistor T 25  is provided between point B and point D, and also the transistor T 26  is provided between point B′ and point D′ in the third embodiment. Accordingly, even when the potential levels at points B and B′ change, the potential levels at points D and D′ are kept. 
     Therefore, a base voltage E is applied to the base of the transistor T 25 , whereby change of the potential level at point D is prevented. Likewise, a base voltage E′ is applied to the base of the transistor T 26 , whereby change of the potential level at point D′ is prevented. 
     With the configuration, the potential levels at points C and C′ are kept, so that the transistors T 22  and T 24 , which are second-stage amplifiers in output stages, may be normally driven and that an output at an amplitude level corresponding to the optical modulator may be supplied to the optical modulator without affecting the base voltages of the transistors T 22  and T 24 . 
     In the third embodiment, too, the base voltages E and E′ applied to the bases of the transistors T 25  and T 26  may set the potential levels at points D and D′, calculated by the above-described expressions. 
     On the other hand,  FIG. 6  illustrates a modification of the amplifier circuit according to the third embodiment. The amplifier circuit illustrated in  FIG. 6  has the same circuit configuration as that of the amplifier circuit illustrated in  FIG. 5  except that transistors T 27  and T 28  are provided. The transistors T 27  and T 28  are bipolar transistors. 
     In the configuration, a normal drive signal may be supplied to the optical modulator without affecting the base voltages of the amplifiers in the last stage by applying base voltages satisfying the condition of the above-described expressions, even when the current value of the current source I 1  is adjusted. 
     In the amplifier circuits according to the above-described embodiments, even when the output level of the amplifier circuit is adjusted, the second-stage amplifiers may be normally operated and a stable output may be supplied from the amplifier circuit without affecting the input of the second-stage amplifiers. Accordingly, an output at an amplitude level corresponding to the optical modulator connected to the amplifier circuit of the present invention may be supplied. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Technology Classification (CPC): 7