Patent Abstract:
A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.

Full Description:
FIELD OF THE INVENTION 
   The present invention relates to the field of field effect transistors (FET); more specifically, it relates to an FET having a gate to source/drain spacing optimized for improved FET performance and a method and system for determining the gate to source/drain spacing for optimizing the performance of the FET. 
   BACKGROUND OF THE INVENTION 
   A most important issue for the semiconductor industry is integrated circuit performance scalability. Scalability is the tracking of performance with decreased transistor size. In general, scalability is adversely affected by the non-scalability of complementary metal-oxide-silicon (CMOS) device technology groundrules below about 250 nm and the non-scalability of process tolerances. Without some technique to overcome CMOS scalability, the trend of decreasing technology groundrules to increase performance cannot be sustained. Therefore, there is a need for a methodology to overcome the scalability issues of CMOS technology. 
   SUMMARY OF THE INVENTION 
   A first aspect of the present invention is a method, comprising: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, one or more source contacts to the source and one or more drain contacts to the drain, each of the one or more source contacts spaced a first distance from the gate electrode and each of the one or more drain contacts spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor. 
   A second aspect of the present invention is the first aspect, wherein the performance parameter is a power cut-off frequency of the field effect transistor. 
   A third aspect of the present invention is the first aspect further including: 
   limiting an amount of the adjusting the first and second distances to prevent a current cut-off frequency of the field effect transistor from being less than a predetermined value. 
   A fourth aspect of the present invention is the first aspect of the present invention, wherein said performance parameter is a current cut-off frequency of said field effect transistor. 
   A fifth aspect of the present invention is the first aspect, wherein a distance between the source and drain defines a channel length, extending in a lengthwise direction, of the field effect transistor, the first and second distances extending along the lengthwise direction. 
   A sixth aspect of the present invention is the first aspect, wherein the adjusting the first and second distances comprises increasing only the first distance, increasing only the second distance or increasing both the first and second distances. 
   A seventh aspect of the present invention is the first aspect, further including: limiting an amount of the adjusting the first and second distances to prevent a total area of the field effect transistor from exceeding a pre-determined limit. 
   An eighth aspect of the present invention is the first aspect further including: simulating a first circuit capable of oscillation, the first circuit including at least one field effect transistor having the fast design; measuring a simulated first oscillation rate of the first circuit; comparing the first oscillation rate to a predetermined oscillation rate; and adjusting a device geometry, other than the first and second distances, of the reference design and repeating the adjusting the first distance and the second distance if the first oscillation rate is less than the predetermined oscillation rate. 
   A ninth aspect of the present invention is the first aspect, further including: 
   simulating a first circuit capable of oscillation, the first circuit including at least one field effect transistor having the fast design; measuring a simulated first oscillation rate of the first circuit; simulating a second circuit capable of oscillation, the second circuit including at least one field effect transistor having the reference design; measuring a simulated second oscillation rate of the second circuit; comparing the first and second oscillation rates; and adjusting a device geometry, other than the first and second distances, of the reference design and repeating the adjusting the first distance and the second distance if the first oscillation rate is less than the second oscillation rate. 
   A tenth aspect of the present invention is the first aspect, further including: designing the field effect transistor. 
   An eleventh aspect of the present invention is the first aspect, wherein the source comprises multiple source regions, the drain comprises multiple drain regions, the channel comprises multiple channel regions between respective pairs of the source and drain regions, the gate electrode comprising a spine and multiple fingers extending from the spine, the fingers over respective channel regions, and at least one source contact of the one or more source contacts in each source region and at least one drain contact of the one or more drain contacts in each drain region. 
   A twelfth aspect of the present invention is the tenth aspect, wherein each of the at least one source contact of the one or more source contacts is equally spaced between adjacent fingers of the multiple fingers and wherein each of the at least one drain contact of the one or more drain contacts is equally spaced between adjacent fingers of the multiple fingers. 
   A thirteenth aspect of the present invention is the first aspect, wherein the reference design is for a field effect transistor to be fabricated on a silicon-on-insulator substrate. 
   A fourteenth aspect of the present invention is the first aspect, further including: generating a set of pairs of incremented first and second distances from the first and second distances; generating a set of power cut-off frequencies corresponding to the pairs of incremented first and second distances; and selecting a pair of incremented first and second distances corresponding to a maximum power cut-off frequency of the set of power cut-off frequencies, the adjusting the first distance and the second distance comprising substituting the pair of incremented first and second distances for the first and second distances. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1A  is a top view and  FIG. 1B  is a cross-sectional view through line  1 B- 1 B of  FIG. 1A  of an exemplary reference FET layout not optimized for performance according to embodiments of the present invention; 
       FIG. 2  is a schematic cross-sectional diagram of an exemplary FET illustrating the parasitic capacitances; 
       FIG. 3  is a top view of an exemplary fast FET layout having a gate to source/drain contact spacings optimized for performance according to embodiments of the present invention; 
       FIG. 4  is a schematic top view of an exemplary fast multi-finger FET having a gate to source/drain contact spacings optimized for performance according to embodiments of the present invention; 
       FIG. 5  is a flowchart of method for optimizing the performance of an FET according to embodiments of the present invention; 
       FIG. 6  is a flowchart of the method step  220  of  FIG. 5 ; 
       FIG. 7  is an exemplary plot of the current cut-off frequency and the power cut-off frequency versus gate pitch ratios of simulated FETs with increased gate pitch divided according to embodiments of the present invention by a simulated reference FET having a reference gate pitch; 
       FIG. 8  is a plot of average Fmax versus gate voltage for actual FETs having different designed gate pitches; 
       FIG. 9  is a circuit diagram of an exemplary ring oscillator; 
       FIG. 10  is a simulation plot of ring oscillator delay versus gate to source/drain contact capacitance; and 
       FIG. 11  is a schematic block diagram of a general-purpose computer for practicing the embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1A  is a top view and  FIG. 1B  is a cross-sectional view through line  1 B- 1 B of  FIG. 1A  of an exemplary reference FET layout not optimized for performance according to embodiments of the present invention. In  FIG. 1A , a device  100  includes sources  105  and drains  110  and gate electrodes  115  on opposite sides of the source/drains. Device  100  comprises three reference transistors T 1 , T 2  and T 3  with transistors T 1  and T 2  sharing a common drain and transistors T 2  and T 3  sharing a common source. Transistor T 1 , T 2  and T 3  may be N-channel field effect transistors (FETs) or NFETs or P-channel FETs or PFETs. Each of transistors T 1 , T 2  and T 3  have a channel width W in a widthwise direction and a channel length L in a lengthwise direction, the widthwise and lengthwise directions being perpendicular. The extent of L depends upon how far sources  105  and drains  110  extend under gate electrodes  115 . 
   A set of source/drain contacts  120  are formed over sources  105  and drains  110 . Device  100  is surrounded by a shallow trench isolation (STI)  125 . Gate electrodes  115  are spaced apart in the lengthwise direction on a pitch PCp 0  and contacts  120  are spaced apart in the lengthwise direction on a pitch CAp 0 . Contacts  120  to sources  105  are spaced in the lengthwise direction a distance Ds 0  from gate electrodes  115  and contacts  120  to drains  110  are spaced in the lengthwise direction a distance Dd 0  from gate electrodes  115 . In one example Dd 0  and Ds 0  are equal. Gate electrodes  115  have a dimension Wpc in the lengthwise direction and contacts  120  have a dimension Wca in the lengthwise direction. If Wpc and Wca are held constant, then Ds 0 , Dd 0  and (Ds 0 +Dd 0 ) are a function of CAp 0  and a function of PCp 0 . 
   In  FIG. 1B , it can be further seen that gate electrodes  115  are formed on top of a gate dielectric  130  and that sources  105  and drains  110  are separated by a channel region  135  under gate electrodes  115 . Sources  105 , drains  110  and channels  135  are formed in a silicon layer  140  (along with STI  125 ), which is formed on top of a buried oxide layer (BOX)  145 , which is formed on top of a silicon substrate  150 . A silicon-on-insulator (SOI) substrate  155  is therefore comprised of silicon layer  140 , BOX  145  and substrate  150 . In one example, silicon layer  140  is single crystal-silicon. Gate electrodes  115  and contacts  120  are embedded in a dielectric layer  160  formed on top of silicon layer  140 . In one example, gate electrodes  115  comprise doped or undoped polysilicon and contacts  120  comprise tungsten or other metals. 
   Returning to  FIG. 1A , current FET design practice minimizes CAp 0  and PCp 0  and thus Ds 0  and Dd 0  in an effort to decrease the size and increase the performance of transistors T 1 , T 2  and T 3 . By performance we mean the two operating frequencies described infra. However, minimizing CAp 0  and PCp 0  does not necessarily increase the operating frequencies, nor increase the operating frequencies as much as the methods of the present invention, because of gate to source/drain capacitance as described infra. Furthermore, the current design practice of minimizing CAp 0  and PCp 0  and thus Ds 0  and Dd 0  may actually reduce the maximum operating frequencies of the transistors. 
     FIG. 2  is a schematic cross-sectional diagram of an exemplary FET illustrating the parasitic capacitances. In  FIG. 2 , three capacitances exist, the intrinsic gate capacitance Ca and the parasitic capacitances Cb and Cc. Ca is the capacitance between the gate electrode and the channel region of the FET. There may also be components (gate overlap capacitances) of Ca between the gate electrode and the source and drain when the gate overlaps the source/drains. Cb is the capacitance between the source and the silicon substrate and the drain and silicon substrate. Cc is the capacitance between the gate and the contacts to the source and to the drain and is a function of the source contact to gate electrode spacing Ds and the drain contact to gate electrode spacing Dd. 
   Because of the thickness of the BOX, Cb is so small as to have no significant effect on operating frequency and Ca is a constant for a given gate dielectric thickness, gate geometry and gate dielectric material. The embodiments of the present invention are directed to fast FETs having reduced values of Cc by increasing the values of Ds and Dd in the fast FETs (see  FIG. 3  and description infra) compared to a reference FET such as described in  FIGS. 1A and 1B  and described supra. 
     FIG. 3  is a top view of an exemplary fast FET layout having a gate to source/drain contact spacings optimized for performance according to embodiments of the present invention described infra. In  FIG. 3 , a fast device  100 A is similar to the reference device  100  of  FIG. 1A  except the contact pitch CAp 1  is greater than CAp 0  of  FIG. 1A , the gate electrode pitch PCp 1  is greater than PCp 0  of  FIG. 1A , the source contact to gate electrode spacing Ds 1  is greater than Ds 0  of  FIG. 1A  and the drain contact to gate electrode spacing Dd 1  is greater than Dd 0  of  FIG. 1A . Also transistors T 1 , T 2  and T 3  of  FIG. 1A  are replaced by fast transistors T 4 , T 5  and T 6  respectively. The only difference between transistors T 1 /T 2 /T 3  and transistors T 4 /T 5 /T 6  are the contact to gate spacings (Dsx and Ddx, where x=0 or 1); all other transistor physical parameters (i.e. doping levels, materials, thicknesses, etc) are the same. 
   The embodiments of the present invention are applicable to multi-finger FETs.  FIG. 4  is a schematic top view of an exemplary fast multi-finger FET having a gate to source/drain contact spacings optimized for performance according to embodiments of the present invention described infra. In  FIG. 4 , an FET  165  includes multiple source regions  170 A and multiple drain regions  170 B. Source and drain regions  170 A and  170 B are surrounded by STI  180 . FET  165  also includes a gate electrode  185 . Gate  185  includes multiple fingers  190 A and multiple fingers  190 B integrally connected to a spine  190 C. Spine  190 C is over STI  180 . A multiplicity of source contacts  195 A are provided to sources  170 A and a multiplicity of drain contacts  195 B are provided to drains  170 B. There are also contacts  195 C to gate electrode  185 . 
   Source contacts  195 A are spaced a distance Ds from fingers  190 A and drain contacts  195 B are spaced a distance Dd from fingers  190 B. Distances Ds and Dd are selected for increased performance of fast FET  165  according to embodiments of the present invention described infra. 
   Therefore, based on  FIGS. 1A ,  1 B,  3  and  4  and the descriptions thereof supra, a fast FET is defined as an FET having a source/drain contact to gate electrode spacing greater than the source/drain contact to gate electrode spacing of a reference FET, holding all other physical design parameters of the fast FET (except overall size of the fast FET) to values of the reference FET. 
   The performance of an FET may be measured by the two operating frequencies, (1) the current cut-off frequency (Ft) and (2) the power cut-off frequency (Fmax). Fmax is defined herein and in the claims as the maximum frequency of an FET beyond which power gain of the FET drops below unity. At frequencies higher than Fmax, an oscillator utilizing that FET will no longer oscillate. Ft is defined herein and in the claims as the maximum frequency of an FET beyond which the current gain of the FET drops below unity. The Fmax and Ft of fast FETs T 4 /T 5 /T 6  of  FIG. 3  can be determined from known parameters of reference FETs T 1 /T 2 /T 3  of  FIG. 1A  and T 4 /T 5 /T 6  as defined by the equations (1) through (5). Equations (1) through (5) are used in the algorithm illustrated in  FIGS. 4 and 5  and described infra. Term C 1  of equations (1), (2) and (4) is the summation of the capacitors Ca and Cc of  FIG. 2  for a fast FET. 
   
     
       
         
           
             
               
                 
                   F 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   max 
                 
                 ≈ 
                 
                   
                     Ft 
                     
                       2 
                       ⁢ 
                       π 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         Rg 
                         ⁡ 
                         
                           ( 
                           
                             C 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           ) 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
   
   where:
         Ft is defined by equation (2)   Rg is defined by equation (5); and   C 1  is defined by equation (4).       

   
     
       
         
           
             
               
                 Ft 
                 = 
                 
                   
                     gm 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   
                     2 
                     ⁢ 
                     π 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     C 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   where:
         gm 1  is defined by equation (3); and   C 1  is defined by equation (4).
 
 gm 1= gm 0+Δ gm[ 1 −e   (D0-D1) ]  (3)
       

   where:
         D 0  is the contact to gate electrode spacing of a reference FET having a known source contact to gate electrode spacing Ds 0  and a known drain contact to gate electrode spacing Dd 0  and where Ds 0 =Dd 0 =D 0 ;   D 1  is the contact to gate electrode spacing of a fast FET having a known source contact to gate electrode spacing Ds 1  and a known drain contact to gate electrode spacing Dd 1  and where Ds 1 =Dd 1 =D 1 ;   gm 0  is the transconductance of the reference FET having the contact to gate electrode spacing Ds=Dd=D 0  (gm can be measured using the formula gm=Iout/Vin); and   Δgm=gm 1 −gm and is the maximum difference in gm between the reference FET and the fast FET and is empirically determined.       

   
     
       
         
           
             
               
                 
                   C 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
                 = 
                 
                   Ca 
                   + 
                   
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       0 
                     
                     
                       ( 
                       
                         D 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           1 
                           / 
                           D 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         0 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 4 
                 ) 
               
             
           
         
       
     
   
   where:
         Ca is the intrinsic gate capacitance;   C 0  is the known capacitance between the source contact and the gate electrode (Cd) or between the drain contact and the gate electrode (Cs), with Cd=Cs; and   D 0  and D 1  are as defined for equation (3).
 
 Rg=Rg 0+ ΔR wire( D 1− D 0)  (5)
       

   where:
         Rg 0  is the known gate electrode resistance of the reference FET;   ΔRwire is the resistance per length of an additional (e.g. metal) wire required to wire up the gate electrode to a circuit node; and   D 0  and D 1  are as defined for equation (3).       

   The term ΔRwire (D 1 −D 0 ) of equation (5) takes into consideration, that since the fast FET is larger than the reference FET that it would replace in a circuit, that the wire from a node in that circuit to the gate electrode will be longer. The ΔRwire (D 1 −D 0 ) of equation (5) may be replaced by other terms as circuit layouts warrant or may be left out entirely. 
   It should be understood, that equations (1) trough (5) are specific to the case where Dd 0 =Ds 0  and Dd 1 =Ds 1  (the fast FET and the reference FET are symmetrical). When Dd 0 ≠Ds 0  and Dd 1 ≠Ds 1 , equations similar to equations (1) though (5) may be developed and used in the algorithm illustrated in  FIGS. 5 and 6  and described infra. 
     FIG. 5  is a flowchart of method for optimizing the performance of an FET according to embodiments of the present invention. In step  200 , a device family and a reference device is selected from a technology database  205 . Technology database includes device design geometry rules and parametric operating ranges by device family. Device families include (1) NFET or PFET, (2) thick or thin gate dielectric FETs and (3) high or low threshold voltage FETs and combinations thereof to give a few examples. Device design geometry rules include, for example, minimum and maximum line widths and spacings, examples of which include minimum channel length, minimum gate electrode pitch, minimum source/drain contact pitch and minimum source/drain contact to gate electrode spacing. Device design specifications include, for example, power supply voltages (i.e. Vdd and Vss), Fmax, Ft, gm and power consumption. In step,  210  a family of Fmax 1  to Fmax n  and Ft 1  to Ft n  values are calculated based on a set of source/drain contact to gate electrode spacing values (Ds 1   1  to Ds 1   n  and Dd 1   1  to Dd 1   n ) using the values of Ds 0 , Dd 0 , gm 0 , Δgm, Rg 0  and ΔRwire from the reference device and equations (1) through (5) in the case Ds 0 =Dd 0  and Ds 1   1 =Dd 1   1 =D 1   1  through Ds 1   n =Dd 1   n =D 1   n  or variants of equations (1) through (5) thereof in the case Ds 1   1 ≠Dd 1   1  through Ds 1   n ≠Ds 1   n . A reference device may be an actual pre-designed device or a simulated device. The values of Ds 1   1  to Ds 1   n  and Dd 1   1  to Dd 1   n  and Fmax 1  to Fmax n  and Ft 1  to Ft n  may be stored in a lookup table or content addressable register. 
   The following steps assume a symmetrical FET where Ds 0 =Dd 0  and Ds 1   1 =Dd 1   1 =D 1   1  through Ds 1   n =Dd 1   n =D 1   n . In the case where the FET is not symmetrical and Ds 1   1 ≠Dd 1   1  through Ds 1   n ≠Ds 1   n  then Ds 1   cur  and Dd 1   cur  should be substituted for the term D 1   cur . 
   In step  220 , the source/drain contact to gate electrode spacing that results in a fast FET having a desired performance is selected. In step  225 , the fast FET is verified to see if it meets device design specifications and circuit design specifications (from a circuit design specification database  230 ). The circuit selected may be a ring oscillator circuit as illustrated in  FIG. 9  and described infra, or another circuit sensitive to FET performance. Verification is performed using simulation programs acting on a simulated circuit containing fast FETs. Additionally, in step  235 , simulation programs acting on simulated circuits containing reference FETs may be performed and the maximum oscillation frequencies of the two simulated circuits compared. The simulated circuits selected may be ring oscillator circuits as illustrated in  FIG. 9  and described infra, or other circuits that are sensitive to FET performance. If in step  235 , the fast FET is verified (the simulation results are acceptable) or the circuit having the fast FET is significantly faster than the circuit having the reference FET, the design of the fast FET is complete, otherwise the method proceeds to step  240 . 
   In step  240 , the device design geometry of the reference FET is adjusted based on device design geometry rules or a new reference FET with a different design geometry is selected and the method returns to step  210 . Examples of device design geometry adjustments include a change in FET channel width and FET channel length. Examples of different device design reference FET geometries include different FET channel widths, FET channel lengths and different numbers of gate electrode fingers. Provision is allowed for an exit from the method (error) if possible geometry adjustments are exhausted or a predetermined number of attempts at adjustments has been reached. 
     FIG. 6  is a flowchart of the method step  220  of  FIG. 5 . In step  245 , the maximum Fmax (Fmax max ) is selected from the calculated Fmax 1  to Fmax n  values and the corresponding source/drain contact to gate electrode spacing D 1   max  determined. Fmax cur  is assigned the value of Fmax max  and D 1   cur  is assigned the value of D 1   max . In step  250 , it is determined if the value of D 1   cur  is below a minimum source/drain contact to gate electrode spacing allowed. Step  250  allows increasing source/drain contact to gate electrode spacing for other reasons besides speed, for example, current crowding. If D 1   cur  is not below the minimum source/drain contact to gate electrode spacing value then the method proceeds to step  255 , otherwise the method proceeds to step  260 . 
   In step  255  it is determined if the value of D 1   cur  is above a maximum source/drain contact to gate electrode spacing allowed. Step  255  allows decreasing source/drain contact to gate electrode spacing in order not to increase the area of the fast FET beyond a predetermined area. If D 1   cur  is not above the maximum source/drain contact to gate electrode spacing value then the method proceeds to step  265 , otherwise the method proceeds to step  270 . 
   In step  265  it is determined if the value of Ft corresponding to D 1   cur  is below a minimum value for Ft allowed. Step  265  is optional. If Ft is not below the minimum value for Ft the selection of a value for D 1   cur  is complete, otherwise the method proceeds to step  275 . One can choose to simply maximize Fmax and ignore the corresponding value of Ft. 
   Returning to steps  260  and  270 , in step  260  the value of D 1   cur  is incremented and the method proceeds to step  280  or in step  270  value of D 1   cur  is decremented and the method proceeds to step  280 . The amount of incrementing or decrementing is fixed to track with the granularity of the D 1   1  to D 1   n  Steps  260  and  270  also track the previous values of D 1 cur and determine if values have already been used, in which case an error is generated indicating the method cannot proceed. 
   In step  280  the value of Fmax corresponding to D 1   cur  is determined, Fmax cur  is assigned this value and the method returns to step  250 . 
   Returning to step  275 , in step  275  the value of Fmax corresponding to a minimum value of Ft is determined and Fmax cur  is assigned this value of Fmax, and D 1   cur  is assigned the value of D 1   1  through D 1   n  corresponding the Fmax cur  and the method returns to step  250 . 
   Alternatively, the method can be restructured to maximize Ft and keep Fmax within pre-determined limits. 
     FIG. 7  is an exemplary plot of the current cut-off frequency and the power cut-off frequency versus gate pitch ratios of simulated FETs with increased gate pitch divided according to embodiments of the present invention by a simulated reference FET having a reference gate pitch. Other than the gate-electrode pitch varying all other FET design parameters are held constant. In  FIG. 7 , Ft is indicated by curve  300 , the maximum value of Ft is indicated by point  305 , Fmax is indicated by curve  310 , and the maximum value of Fmax is indicated by point  315 . The horizontal axis is gate electrode pitch ratio (fast FET/reference FET). As discussed supra, the source/drain contact to gate electrode spacing is related to gate electrode pitch. In some cases, the FET design rules are framed in terms of source/drain contact pitch and gate electrode pitch with the source/drain contacts being equidistant between adjacent gates over the same well (a symmetrical FET) and this is a more useful number to report out of the algorithm than the actual source/drain contact to gate electrode spacing. In  FIG. 7 , it can be seen that the maximum value of Fmax occurs at a gate pitch ratio of about 2 and the maximum value of Ft occurs at a gate pitch ratio of about 2.25. Thus the larger (the greater the gate electrode pitch the larger the device) device (the fast FET, pitch=about 2) is faster than the smaller device (reference device pitch=1), which is contrary to conventional design methodology, where the fast FET would be designed to be smaller than the reference FET. 
     FIG. 8  is a plot of average Fmax versus gate voltage for actual FETs having different designed gate pitches. In  FIG. 8 , curve  320  represents Vg versus Ft for a gate electrode pitch of about 0.25 microns, while curve  325  represents Vg versus Ft for a gate electrode pitch of about 0.5 microns. Again, the larger FET is faster, holding all other parameters other than pitch constant. 
     FIG. 9  is a circuit diagram of an exemplary ring oscillator. In  FIG. 9 , a ring oscillator  330  includes three inverter stages  335 ,  340  and  345  comprising respectively NFET N 1  and PFET P 1 , NFET N 2  and PFET P 2 , and NFET N 3  and PFET P 3 . The input of ring oscillator  330  is connected to the input of first stage  335 . The output of first stage  335  is connected to the input of second stage  340 . The output of second stage  340  is connected to the input of third stage  345 . The output of third stage  345  is connected to the output of the ring oscillator and to the input of the first stage. Ring oscillator  330  is exemplary of ring oscillators in general in that there must be an odd number of inverter stages. 
     FIG. 10  is a simulation plot of ring oscillator delay versus gate to source/drain contact capacitance. Curve  350  represents a plot of gate to contact capacitance (Cc of  FIG. 2  or C 0 D 0 /D (see equation (4)).  FIG. 10  shows that by decreasing the source/drain contact to gate electrode capacitance the delay through the oscillator decreases and the speed of the oscillator increases. Since the embodiments of the present invention teach increasing the source/drain contact to gate electrode spacing of an FET increase the switching speed of an FET relative to a reference FET, it follows that circuits utilizing an FET having a greater source/drain contact to gate electrode spacing would be faster than a circuit having an FET having a reference a source/drain contact to gate electrode spacing. 
     FIG. 11  is a schematic block diagram of a general-purpose computer for practicing the embodiments of the present invention. In  FIG. 11 , computer system  400  has at least one microprocessor or central processing unit (CPU)  405 . CPU  405  is interconnected via a system bus  410  to a dynamic random access memory (DRAM) device  415  and a read-only memory (ROM) device  420 , an input/output (I/O) adapter  425  for connecting a removable data and/or program storage device  430  and a mass data and/or program storage device  435 , a user interface adapter  440  for connecting a keyboard  445  and a mouse  450 , a port adapter  455  for connecting a data port  460  and a display adapter  465  for connecting a display device  470 . 
   Either of devices  415  and  420  contains the basic operating system for computer system  400 . Removable data and/or program storage device  430  may be a magnetic media such as a floppy drive, a tape drive or a removable hard disk drive or optical media such as CD ROM or a digital video disc (DVD) or solid state memory such as ROM or DRAM or flash memory. Mass data and/or program storage device  435  may be a hard disk drive or an optical drive. In addition to keyboard  445  and mouse  450 , other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface  440 . Examples of display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD). 
   One of devices  415 ,  420 ,  430  or  435  includes a computer code  475  (illustrated by way of example in device  415 ), which is a computer program that comprises computer-executable instructions. Computer code  475  includes an algorithm optimizing the performance of an FET (e.g. the algorithm of  FIGS. 5 and 6 ). CPU  405  executes computer code  475 . Any of devices  415 ,  420 ,  430  or  435  may include input data  480  (illustrated by way of example in device  435 ) required by computer code  475 . Display device  470  displays output from computer code  475 . 
   Any or all of devices  415 ,  420 ,  430  and  435  (or one or more additional memory devices not shown in  FIG. 11 ) may be used as a computer usable medium (or a computer readable medium or a program storage device) having a computer readable program embodied therein and/or having other data stored therein, wherein the computer readable program comprises computer code  475 . Generally, a computer program product (or, alternatively, an article of manufacture) of the computer system  400  may comprise the computer usable medium (or the program storage device). 
   Thus the present invention discloses a process for supporting computer infrastructure, integrating, hosting, maintaining, and deploying computer-readable code into the computer system  400 , wherein the code in combination with the computer system  400  is capable of performing a method for optimizing the performance of an FET. 
   Thus the embodiments of the present invention provide a methodology to overcome the scalability issues of CMOS technology. Specific applications of the present invention include, but are not limited to radio frequency and millimeter-wave, digital circuits and analog circuits using CMOS devices. 
   The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Technology Classification (CPC): 6