Patent Abstract:
An electronic system including a shift register is disclosed. The shift register includes a first transistor, a first trigger circuit, a second transistor, and a second trigger circuit. The first transistor receives a first input signal. The first trigger circuit is serially connected to the first transistor between a first level and a second level and is connected with the first transistor in a first node. The second transistor receives a second input signal inverted to the first input signal. The second trigger circuit receives the level of the first node, is serially connected to the second transistor between a third level and the second level, and is connected with the second transistor in a second node.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority of Taiwan Patent Application No. 98141855, filed on Dec. 8, 2009, the entirety of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to an electronic system, and more particularly to an electronic system including a shift register. 
     2. Description of the Related Art 
       FIG. 1  is a schematic diagram of a conventional shift register. The shift register  100  is composed of D-type flip-flops  101 - 104 . The D-type flip-flops  101 - 104  are connected in series with one another. The D-type flip-flops  101 - 104  shift a start signal START according to rising edges of a clock signal CLK. 
       FIG. 2  is a schematic diagram of another conventional shift register. The shift register  200  comprises shift register cells  201 - 204 . The shift register cells  201 - 204  shift a start signal START according to clock signals CLK and XCLK. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of an electronic system comprises a power transforming unit and a display panel. The power transforming unit provides an operational voltage. The display panel receives the operational voltage and comprises a gate driver, a source driver, a first pixel and a second pixel. The gate driver is coupled to a first gate line and a second gate line and comprises a shift register and a signal generating unit. The shift register comprises a first transistor, a first trigger circuit, a second transistor, and a second trigger circuit. The first transistor receives a first input signal. The first trigger circuit is serially connected to the first transistor between a first level and a second level and is connected with the first transistor in a first node. The second transistor receives a second input signal inverted to the first input signal. The second trigger circuit receives the level of the first node, is serially connected to the second transistor between a third level and the second level, and is connected with the second transistor in a second node. The signal generating unit provides the first, the second, and the third levels. The source driver is coupled to a first data line and a second data line. The first pixel is coupled to the first gate line and the first data line. The second pixel is coupled to the second gate line and the second data line. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by referring to the following detailed descriptions and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a schematic diagram of a conventional shift register; 
         FIG. 2  is a schematic diagram of another conventional shift register; 
         FIG. 3A  is a schematic diagram of an exemplary embodiment of a shift register of the invention; 
         FIG. 3B  is a timing diagram of the output signals OUT 1 -OUT 4 ; 
         FIG. 4A  is a schematic diagram of another exemplary embodiment of a shift register of the invention; 
         FIG. 4B  is a timing diagram of the output signals OUT 1 -OUT 4  shown in  FIG. 4A ; 
         FIG. 5  is a schematic diagram of another exemplary embodiment of a shift register of the invention; 
         FIG. 6A  is a schematic diagram of an exemplary embodiment of the trigger circuit shown in  FIG. 3A  and  FIG. 4A ; 
         FIG. 6B  a schematic diagram of another exemplary embodiment of the trigger circuit; 
         FIG. 7  shows a control timing diagram of the trigger circuit; 
         FIG. 8A  a schematic diagram of an exemplary embodiment of a gate driver; 
         FIG. 8B  a schematic diagram of another exemplary embodiment of a gate driver; 
         FIG. 9  a schematic diagram of an exemplary embodiment of the switching unit shown in  FIG. 8 ; and 
         FIG. 10  a schematic diagram of an exemplary embodiment of an electronic system. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 3A  is a schematic diagram of an exemplary embodiment of a shift register of the invention. The shift register comprises various shift register cells. The invention does not limit the number of the shift register cells. For clarity,  FIG. 3A  only shows four shift register cells  311 - 314 . 
     As shown in  FIG. 3A , the shift register cell  311  comprises a transistor MP 1  and a trigger circuit TP 1 . The transistor MP 1  receives an input signal XIN. The trigger circuit TP 1  and the transistor MP 1  are coupled to a node NP 1 . The trigger circuit TP 1  is serially connected to the transistor MP 1  between levels V 1  and V 2 . In one embodiment, the level V 1  is an alternating current (AC) level and inverted to the input signal XIN. In addition, the level V 2  is maintained in a low level, such as a grounding level. 
     When a start signal START activates the trigger circuit TP 1 , the trigger circuit TP 1  outputs the level V 2  to the node NP 1 . When the start signal START does not activate the trigger circuit TP 1 , the transistor MP 1  outputs the level V 1  to the node NP 1 . 
     The shift register cell  312  comprises a transistor MP 2  and a trigger circuit TP 2 . The transistor MP 2  receives an input signal IN. The trigger circuit TP 2  and the transistor MP 2  are coupled to a node NP 2 . The trigger circuit TP 2  is serially connected to the transistor MP 2  between levels V 3  and V 2 . In one embodiment, the level V 3  is an AC level and inverted to the input signal IN. In this embodiment, the input signal IN is inverted to the input signal XIN. In one embodiment, the level V 1  is the same as the input signal IN and the level V 3  is the same as the input signal XIN. 
     When the level (i.e. an output signal OUT 1 ) of the node NP 1  is sufficient to activate the trigger circuit TP 2 , the trigger circuit TP 2  outputs the level V 2  to the node NP 2 . When the level of the node NP 1  is not sufficient to activate the trigger circuit TP 2 , the transistor MP 2  outputs the level V 3  to the node NP 2 . 
     The shift register cell  313  comprises a transistor MP 3  and a trigger circuit TP 3 . The transistor MP 3  receives the input signal XIN. The trigger circuit TP 3  is connected with the transistor MP 3  in a node NP 3 . The trigger circuit TP 3  is serially connected to the transistor MP 3  between the levels V 1  and V 2 . Since a function of the level of the node NP 3  is similar to a function of the level of the node NP 1 , the description of the function of the level of the node NP 3  is omitted for brevity. 
     The shift register cell  314  comprises a transistor MP 4  and a trigger circuit TP 4 . The transistor MP 4  receives the input signal IN. The trigger circuit TP 4  and the transistor MP 4  are coupled to a node NP 4 . The trigger circuit TP 4  is serially connected to the transistor MP 4  between the levels V 3  and V 2 . Since a function of the level of the node NP 4  is similar to a function of the level of the node NP 2 , the description of the function of the level of the node NP 4  is omitted for brevity. 
     In this embodiment, the transistors MP 1 -MP 4  are P-type transistors. As shown in  FIG. 3A , the gates of the transistors MP 1  and MP 3  receive the input signal XIN. The sources of the transistors MP 1  and MP 3  receive the level V 1 . The drain of the transistor MP 1  is coupled to the node NP 1 . The drain of the transistor MP 3  is coupled to the node NP 3 . The gates of the transistors MP 2  and MP 4  receive the input signal IN. The sources of the transistors MP 2  and MP 4  receive the level V 3 . The drain of the transistor MP 2  is coupled to the node NP 2 . The drain of the transistor MP 4  is coupled to the node NP 4 . 
     Furthermore, the levels of the nodes NP 1 -NP 4  are served as output signals OUT 1 -OUT 4  of the shift register  310 , respectively.  FIG. 3B  is a timing diagram of the output signals OUT 1 -OUT 4 . When a trigger circuit is activated, a corresponding output signal is equal to a low level (i.e. the level V 2 ). When the trigger circuit is not activated, a corresponding output signal is equal to a high level. In this embodiment, only one output signal is equal to the low level at the same time. 
       FIG. 4A  is a schematic diagram of another exemplary embodiment of a shift register of the invention.  FIG. 4A  is similar to  FIG. 3A  with the exception that trigger circuits TN 1 -TN 4  are coupled to N-type transistors MN 1 -MN 4 , respectively. Taking the transistors MN 1  and MN 3  as an example, the gates of the transistors MN 1  and MN 3  receive the input signal XIN. The sources of the transistors MN 1  and MN 3  receive the level V 2 . The drain of the transistor MN 1  is coupled to the node NN 1 . The drain of the transistor MN 3  is coupled to the node NN 3 . Additionally, the gates of the transistors MN 2  and MN 4  receive the input signal IN. The sources of the transistors MN 2  and MN 4  receive the level V 2 . The drain of the transistor MN 2  is coupled to the node NN 2 . The drain of the transistor MN 4  is coupled to the node NN 4 . 
     When the start signal START activates the trigger circuit TN 1 , the trigger circuit TN 1  outputs the level V 1  to the node NN 1 . When the start signal START does not activate the trigger circuit TN 1 , the transistor MN 1  outputs the level V 2  to the node NN 1 . Similarly, when the level (i.e. the output signal OUT 1 ) of the node NN 1  is sufficient to activate the trigger circuit TN 2 , the trigger circuit TN 2  outputs the level V 3  to the node NN 2 . When the level of the node NN 1  is not sufficient to activate the trigger circuit TN 2 , the transistor MN 2  outputs the level V 2  to the node NN 2 . 
     Furthermore, the levels of the nodes NN 1 -NN 4  are served as the output signals OUT 1 -OUT 4  of the shift register  410 .  FIG. 4B  is a timing diagram of the output signals OUT 1 -OUT 4  shown in  FIG. 4A . In this embodiment, when a trigger circuit is activated, a corresponding output signal is in a high level. When the trigger circuit is not activated, the corresponding output signal may be in a low level. As shown in  FIG. 4B , only one output signal is in the high level at the same time. In other words, only one trigger circuit is activated at the same time. 
       FIG. 5  is a schematic diagram of another exemplary embodiment of a shift register of the invention.  FIG. 5  is similar to  FIG. 4A  with the exception that shift register cells  511 - 514  comprise P-type transistors MI 1 -MI 4 , respectively. Further, the levels V 1  and V 3  shown in  FIG. 5  are different from the levels V 1  and V 3  shown in  FIG. 4A . The levels V 1  and V 3  shown in  FIG. 5  are direct current (DC) levels. 
     In this embodiment, the levels V 1  and V 3  shown in  FIG. 5  are high, such as 10V and the level V 2  is low, such as 0V. Additionally, the input signal IN of  FIG. 5  is inverted to the input signal XIN of  FIG. 5 . The input signals IN and XIN are AC signals. 
     The shift register cell  511  comprises transistors MI 1  and MN 1 , and a trigger unit TI 1 . The transistors MI 1  and MN 1  are serially connected to the trigger unit TI 1  between the levels V 1  and V 2 . The trigger unit TI 1  and the transistor MN 1  are coupled to the node NN 1 . The gates of the transistors MI 1  and MN 1  receive the input signal IN. 
     In this embodiment, the source of the transistor MI 1  receives the level V 1  and the source of the transistor MN 1  receives the level V 2 . When the start signal START activates the trigger unit TI 1 , the level of the node NN 1  is equal to the level V 1 . When the start signal START does not activate the trigger unit TI 1 , the level of the node NN 1  is equal to the level V 2 . 
     The shift register cell  512  comprises transistors MI 2  and MN 2 , and a trigger unit TI 2 . The transistors MI 2  and MN 2  are serially connected to the trigger unit TI 2  between the levels V 3  and V 2 . The trigger unit TI 2  and the transistor MN 2  are coupled to the node NN 2 . The gates of the transistors MI 2  and MN 2  receive the input signal XIN. 
     In this embodiment, the source of the transistor MI 2  receives the level V 3  and the source of the transistor MN 2  receives the level V 2 . When the level of the node NN 1  is sufficient to activate the trigger unit TI 2 , the level of the node NN 2  is equal to the level V 3 . When the level of the node NN 1  is not sufficient to activate the trigger unit TI 2 , the level of the node NN 2  is equal to the level V 2 . 
     The shift register cell  513  comprises transistors MI 3  and MN 3 , and a trigger unit TI 3 . The transistors MI 3  and MN 3  are serially connected to the trigger unit TI 3  between the levels V 1  and V 2 . The trigger unit TI 3  and the transistor MN 3  are coupled to the node NN 3 . The gates of the transistors MI 3  and MN 3  receive the input signal IN. In this embodiment, the source of the transistor MI 3  receives the level V 1  and the source of the transistor MN 3  receives the level V 2 . 
     The shift register cell  514  comprises transistors MI 4  and MN 4 , and a trigger unit TI 4 . The transistors MI 4  and MN 4  are serially connected to the trigger unit TI 4  between the levels V 3  and V 2 . The trigger unit TI 4  and the transistor MN 4  are coupled to the node NN 4 . The gates of the transistors MI 4  and MN 4  receive the input signal XIN. In this embodiment, the source of the transistor MI 4  receives the level V 3  and the source of the transistor MN 4  receives the level V 2 . 
     As shown in  FIG. 5 , the structures of all shift register cells are the same (e.g. each shift register cell comprises a P-type transistor, an N-type transistor, and a trigger unit). In some embodiment, any particular shift register cell in  FIG. 5  can be replaced by anyone shift register cell in  FIG. 3A  or  FIG. 4A , or any particular shift register cell in  FIG. 3A  or  FIG. 4A  can be replaced by anyone shift register cell in  FIG. 5 . 
     The shift register cells in  FIGS. 3A ,  4 A, and  5 A execute a shifting action according to a small amount of input signals. Thus, complexity of the shift register can be reduced. Taking the shift register cell  311  shown in  FIG. 3A  as an example, the shift register cell  311  shifts the start signal START to generate the output signal OUT 1  according to the input signal XIN and the levels V 1  and V 2 . 
     In one embodiment, the input signal XIN is inverted to the level V 1 . In other words, one inverter is utilized to invert one of the input signals XIN and the level V 1  to generate an inverted input signal. Thus, the complexity of the shift register is reduced. 
       FIG. 6A  is a schematic diagram of an exemplary embodiment of the trigger circuit shown in  FIG. 3A  and  FIG. 4A . The trigger circuit shown in  FIG. 3A  or  4 A can be replaced by the trigger circuit shown in  FIG. 6A . For clarity,  FIG. 6A  only shows the shift register cell  411  of  FIG. 4A  to describe a connection relationship between the trigger circuit TN 1  and the transistor MN 1 . 
     As shown in  FIG. 6A , the trigger circuit TN 1  comprises a reset transistor MR and a capacitor C. The capacitor C is coupled between the gate and the drain of the reset transistor MR. In this embodiment, the reset transistor MR is an N-type transistor. Additionally, the trigger circuit TN 1  further comprises a current source CS and a setting transistor MS. 
     The current source CS provides a fixed current I. In this embodiment, the current source CS consists of a P-type transistor MI. As shown in  FIG. 6A , the gate of the transistor MI receives a grounding level GND and the source of the transistor MI receives a high voltage VDD to provide the fixed current I. 
     The setting transistor MS receives the level V 1  and couples to the node NN 1 . In this embodiment, the setting transistor MS is utilized to increase the level of the node NN 1  such that the level of the node NN 1  is in a high level. Thus, the setting transistor MS is referred to as a pull-high transistor. In another embodiment, if the trigger circuit shown in  FIG. 6A  is applied in  FIG. 3A , the setting transistor MS is coupled between the node NP 1  and the level V 2  to reduce the level of the node NP 1  such that the level of the node NP 1  is in a low level. AT this time, the setting transistor MS is referred to as a pull-low transistor. 
     Further, the start signal START shown in  FIG. 6A  represents an output signal of a previous shift register cell. The output signal OUT 1  shown in  FIG. 6A  represents a signal transmitted to the next shift register. Taking the shift register cell  413  shown in  FIG. 4A  as an example, the start signal START shown in  FIG. 6A  is the output signal OUT 2  shown in  FIG. 4A . The output signal OUT 1  shown in  FIG. 6A  is the output signal OUT 3  shown in  FIG. 4A . 
       FIG. 6B  a schematic diagram of another exemplary embodiment of the trigger circuit.  FIG. 6B  is similar to  FIG. 6A  except for the addition of a transmitting transistor MT. The transmitting transistor MT transmits the fixed current I to the capacitor C. In this embodiment, the reset transistor MR is an N-type transistor and the setting transistor MS and the transmitting transistor MT are P-type transistors. 
     The reset transistor MR comprises a gate receiving the start signal START, a source receiving the level V 2 , and a drain coupled to the drain of the transmitting transistor MT. The setting transistor MS comprises a gate coupled to the drain of the transmitting transistor MR, a drain coupled to the node NN 1 , and a source receiving the level V 1 . The transmitting transistor MT comprises a gate receiving the start signal START, a source coupled to the current source CS and a drain coupled to the drain of the reset transistor MR. 
       FIG. 7  shows a control timing diagram of the trigger circuit. Since the control timing of  FIG. 6A  is similar to the control timing of  FIG. 6B ,  FIG. 7  only shows the control timing of  FIG. 6A . During the period P 1 , the start signal START is in a high level such that the reset transistor MR is turned on to reset the capacitor C. At this time, the gate voltage VG 1  of the setting transistor MS is low. Since the level V 1  is a low level, the setting transistor MS is turned off. During the period P 1 , the input signal XIN is a high level such that the transistor MN 1  is turned on. 
     During the period P 2 , the start signal is low, the transmitting transistor MR is turned off. Thus, the current source CS charges the capacitor C. During the period P 2 , the gate voltage VG 1  of the setting transistor MS is lower than the low level at the very start because the reset transistor MR is controlled from a turn-on state to a turn-off state. Then, the gate voltage VG 1  of the setting transistor MS is gradually increased because the capacitor C is charged. During the period P 2 , the setting transistor MS is turned on. Since the level V 1  is high, the setting transistor MS pulls the level (i.e. the output signal OUT 1 ) of the node NN 1  to a high level. At this time, since the input signal XIN is low, the transistor MN 1  is turned off. 
     During the period P 3 , the charge of the capacitor C is maintained in a preset value. Thus, the gate voltage VG 1  of the setting transistor MS is high. At this time, the reset transistor MR, the setting transistor MS, and the transistor MN 1  are turned off. 
     During the period P 4 , the input signal XIN is high such that the transistor MN 1  is turned on. Thus, the output signal OUT 1  is low. At this time, the reset transistor MR and the setting transistor MS are turned off. 
     Referring to  FIG. 7 , the start signal START is shifted by the shift register of the invention. The shifted result is shown as the output signal OUT 1 . Since the shift register of the invention arrives to a shift function according to a small number of control signals. Thus, the complexity of the shift register can be reduced. 
     For example, the shift register  310  shown in  FIG. 3A  shifts the start signal START according to the levels V 1 -V 3  and the input signals XIN and IN. In one embodiment, when the level V 1  is inverted to the level V 2 , only one level (e.g. V 1 ) is required and utilized to generate the invented level (e.g. V 2 ). In another embodiment, when the level V 1  is equal to the input signal IN and the level V 2  is equal to the input XIN, only one level (e.g. V 1 ) is required and utilized to generate the inverted level (e.g. V 2  and XIN) and the non-inverted level (e.g. IN). 
     The invention does not limit the application field of the shift register. In one embodiment, the shift register is applied within a gate driver or a data driver of a display panel, but the disclosure is not limited thereto. In other embodiments, the shift register is combined with other circuits. For brevity, a gate driver is given as an example. 
       FIG. 8A  a schematic diagram of an exemplary embodiment of a gate driver. The gate driver  800  is coupled to gate lines GL 1 -GL 4 . The invention does not limit the number of the gate lines. In this embodiment, only four gate lines are shown, but the disclosure is not limited thereto. Further, the gate driver  800  comprises a signal generating unit  810 , a shift register  830 , and a buffer unit  850 . 
     The signal generating unit  810  generates input signals XIN and IN and levels V 1 -V 3  according to input voltage V I . In one embodiment, the signal generating unit  810  is a level shifter. In another embodiment, the input signal XIN is inverted to the input signal IN. In this embodiment, the input signals XIN and IN are AC signals. In other embodiments the level V 1  is inverted to or equal to the level V 2 . In other words, the levels V 1  and V 2  are AC levels or DC levels. 
     The shift register  830  receives the signals output from the signal generating unit  810  to shift a start signal START. The shift register  830  may be the shift register shown in  FIG. 3A ,  FIG. 4A , and  FIG. 5 . The invention does not limit the structure of each shift register cell. In one embodiment, the structures of all shift register cells are the same. In another embodiment, the structures of a portion of shift register cells may be different from the structures of the remainder. 
     The buffer unit  850  increases the driving capability of the output signals OUT 1 -OUT 4  of shift register  830  such that the output signals OUT 1 -OUT 4  of shift register  830  is capable of driving the pixels coupled to the gate lines GL 1 -GL 4 . In this embodiment, the buffer unit  850  comprises buffer strings  851 - 854 . The buffer strings  851 - 854  are composed of various buffers. 
       FIG. 8B  a schematic diagram of another exemplary embodiment of a gate driver. The gate driver  800 ′ comprises a buffer unit  820 , a shift register  840 , a switching unit  860  and a signal generating unit  880 . In this embodiment, the shift register  840  is the shift registers shown in  FIG. 3A ,  FIG. 4A  and  FIG. 5 . 
     The signal generating unit  880  comprises level shifters  882  and  884 . The level shifter  882  generates a signal S BIN  to a buffer string  821 . The level shifter  884  generates input signals XIN and IN and levels V 1 -V 3  to the shift register  840 . In other embodiments, the signal generating unit  880  may comprise a single level shifter to generate signals required by the buffer unit  820  and the shift register  840 . 
     The buffer string  821  amplifies the driving capability of the signal S BIN  and serves the amplified signal as an output signal S BOUT . The output signal S BOUT  is transmitted to the switching unit  860 . The switching unit  860  selectively transmits the output signal S BOUT  to the gate lines GL 1 -GL 4  according to the output signals OUT 1 -OUT 4  of the shift register  840 . 
     In this embodiment, since the buffer unit  820  only comprises a single buffer string (i.e.  821 ), the size of the gate driver  800 ′ can be substantially reduced. Additionally, the start signal START received by the shift register  840  can be provided by a timing controller (not shown), but the disclosure is not limited thereto. 
       FIG. 9  a schematic diagram of an exemplary embodiment of the switching unit shown in  FIG. 8 . The switching unit  860  comprises switches  861 - 864 . The switches  861 - 864  are controlled by the output signals OUT 1 -OUT 4  of the shift register  840 . For example, assuming the output signals OUT 1 -OUT 4  shown in  FIG. 9  are the output signals OUT 1 -OUT 4  shown in  FIG. 4B . 
     When the output signal OUT 1  is in a high level, the switch  861  transmits the output signal S BOUT  of the buffer string  821  to the gate line GL 1 . At this time, switches  862 - 864  transmit low levels AGND to the gate lines GL 2 -GL 4 . Thus, the levels of the gate lines GL 2 -GL 4  are low. Similarly, when the output signal OUT 2  is in a high level, the switch  862  transmits the output signal S BOUT  of the buffer string  821  to the gate line GL 2 . At this time, switches  861 ,  863  and  864  transmit low levels AGND to the gate lines GL 1 , GL 3  and GL 4 . 
     The gate drivers shown in  FIG. 8A  and  FIG. 8B  can be applied to an electronic system. The electronic system may be a personal digital assistant (PDA), a cellular phone, a digital camera (DSC), a television, a global positioning system (GPS), a car display, an avionics display, a digital photo frame, a notebook computer (NB), a personal computer (PC). 
       FIG. 10  a schematic diagram of an exemplary embodiment of an electronic system. The electronic system  1000  comprises a power transforming unit  1010  and a display panel  1030 . The power transforming unit  1010  converts an input power V IN  to generate an operation voltage V OP . The display panel  1030  receives the operation voltage V OP  to display an image. In one embodiment, the input power V IN  is an AC power or a DC power. In this embodiment, the operation voltage V OP  is a DC voltage. 
     The display panel  1030  comprises a gate driver  1031 , a source driver  1033  and pixels P 11 ˜P mn . The gate driver  1031  provides scan signals to gate lines GL 1 ˜GL n . The source driver  1033  provides data signals to data lines DL 1 ˜DL n . The pixels P 11 ˜P mn  receives the data signals according to the scan signals of the gate lines GL 1 ˜GL n  and display the corresponding brightness according to the data signals. 
     In one embodiment, the gate driver  1031  sequentially activates the gate lines GL 1 ˜GL n . Thus, the gate driver  1031  requires a shift register. In another embodiment, the source driver  1033  sequentially provides data signals to data lines DL 1 ˜DL n . Thus, the source driver  1033  also requires a shift register. The gate driver  1031  and the source driver  1033  can utilize the shift register shown in  FIG. 3A ,  FIG. 4A  or  FIG. 5 . In addition, since the application of the scan signals provided by the gate driver  1031  and the application of the data signals provided by the source driver  1033  are well known to those skilled in the field, such descriptions are omitted for brevity. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 6