Patent Abstract:
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a high etch selectivity, that may be used in manufacturing a variety of electronic devices such as integrated circuits (ICs) and micro electro-mechanical (MEM) devices. The etching solution is formed by adding 35% ammonium hydroxide solution to a hot 12.5% TMAH solution at about 70° C. at a rate of 1% by volume, every hour. Such an etch solution and method provides a simple, inexpensive, single step self initiating poly etch that has etch stop ratios of over 200 to 1 over underlying insulator layers and TiN layers.

Full Description:
TECHNICAL FIELD  
       [0001]     This application relates generally to semiconductor devices and device fabrication and, more particularly, to etching polysilicon layers without a separate oxide decapping procedure.  
       BACKGROUND  
       [0002]     The semiconductor device industry has a market driven need to reduce the size of devices such as transistors, capacitors and electrically conductive interconnects in order to produce smaller integrated circuit devices (ICs). Smaller ICs result in improved operational speed and clock rate, and reduced power requirements in both the standby and operational modes. Smaller ICs need thinner dielectric layers, thinner diffusion layers and more closely spaced conductive interconnect layers, such as doped polycrystalline silicon (poly). Producing these closely spaced (finer pitch) poly lines requires improved poly etching techniques. Micro electro-mechanical (MEM) devices may use etched poly patterns as a portion of the device. Reducing the size of MEM devices increases their utility and decreases their price and power consumption in many cases.  
         [0003]     It is known to improve poly pitch by use of plasma etch techniques to increase the slope of the etched poly sidewall to approaching 90 degrees, and to reduce the amount of sideways etching that occurs under the edge of the photo resist mask. However, plasma etch processes are slow, require substantial expensive equipment, and may have problems with what may be known as etch selectivity ratios. The etch selectivity ratio is the rate of etching of a first material divided by the rate of etch of a second material. A high etch selectivity of a material layer being etched over the underlying layer is important in IC and MEM manufacture, since it allows increased margin for timed etches by providing what may be called an etch stop. The increasingly small and reliable integrated circuits (ICs) devices will likely be used in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).  
         [0004]     Thus there exists a need in the art for a simple, inexpensive and uniform poly etch method that has both a high poly etch rate (to decrease manufacturing cost), and high etch selectivity of poly over the underlying single crystal silicon, doped oxide, or other material layers. It is known to etch poly layers using wet chemical etch tanks. Wet etching is simple and inexpensive, but there is an issue with the etch uniformity, both in terms of across the single wafer variations, and in lot to lot variations over time. One reason for this lack of uniformity in poly etching relates to the fact that if a poly layer is exposed to the oxygen in the air, which may be hard to avoid, the surface atoms of the poly oxidize to form what may be called a native oxide. Such a native oxide may be from 10 to 20 Angstroms ( 521  ) in thickness, and the oxide may grow in a few hours. Wet chemical etches that have high poly etch rates and high etch selectivity over underlying oxides may be non uniform since the etching of the poly can not begin until the native oxide, which may be call a cap oxide, is etched (or decapped). Since the thickness of the oxide cap is a variable that depends at least in part on how long the poly layer has been exposed, and the storage conditions, then the amount of time it takes to decap the poly layer before etching begins may result in non-uniform etching.  
         [0005]     It is known to place the wafers having the poly layer to be etched in a decapping solution, such as a hydrofluoric acid (HF) bath, prior to placing the wafers in a poly etch bath. However, the wafers must be washed in deionized water (DI water) and dried prior to going into the poly etch bath, and such a washing procedure may cause sufficient native oxide to regrow to again inhibit the initiation of the poly etch. Further, the variations in the amount of time that pass between the end of the decap process and the beginning of the poly etch may again result in lot to lot variations in the amount of poly etched. Yet further, the need to have two different wet chemical baths and the increase in production time and cost make this solution less than optimal. There may also be an operator safety issue in having an acid bath in the same general vicinity as the typically caustic poly etch bath, since acids and bases should not be mixed without safety precautions.  
       SUMMARY  
       [0006]     The above-mentioned issues are addressed by the present invention and will be understood by reading and studying the following specification. A method of etching a polysilicon layer consists essentially of adding a spike of an ammonium hydroxide solution to a bath of tetra methyl ammonium hydroxide (TMAH) solution, and then immersing the substrate with the polysilicon layer in the solution. In an embodiment, the substrate is immersed in the ammonium hydroxide and TMAH solution within one hour of when the ammonium hydroxide spike was added. The substrate is removed after the preselected etch time period, and the substrate is washed to remove the ammonium hydroxide and TMAH etching solution from the substrate, and the substrate is dried. The ammonium hydroxide and TMAH solution provides a rapid decap and polysilicon etch rate in a temperature range of approximately 60° C. to 90° C. It is possible to increase the etch rate by use of a pressure cooker type arrangement that allows the temperature of the TMAH to be raised to above the boiling point of the solution. The etch process may also be preformed on a spin vacuum chuck with either pressure spray dispense nozzles, carrier gas mist dispense nozzles, or with low pressure stream flow dispense nozzles. The TMAH concentration has a broad manufacturing tolerance and may vary between 2.5% and 25% in deionized (DI) water, but a preferred concentration is 12.5% to account for both dilution due to repeated spikes of ammonium hydroxide solution, and to account for evaporation during the course of the life of the etch bath. One method of controlling the life of the etch bath is to maintain the pH of the solution at a greater value than 13. The ammonium hydroxide solution used as the spike concentration is preferably approximately 35% in water, and the volume of the spike may vary from as low as 0.2% to as much as 2% of the total volume of the etch bath.  
         [0007]     The decapping etch rate of the native silicon oxide layer on the top surface of the polysilicon layer may be greater than 800 Angstroms per minute. The etch rate of the polysilicon layer is approximately 4000 Angstroms per minute with the etch rate of the underlying oxide layer less than 20 Angstroms per minute.  
         [0008]     These and other aspects, embodiments, advantages, and features will become apparent from the following description and the referenced drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  illustrates an embodiment of an etch system;  
         [0010]      FIG. 2  illustrates an embodiment of a tank etch system;  
         [0011]      FIG. 3A  illustrates a possible flow diagram for an embodiments of the etch method of  FIG. 1 ;  
         [0012]      FIG. 3B  illustrates a possible flow diagram for an embodiments of the etch method of  FIG. 2 ;  
         [0013]      FIG. 4A  shows an embodiment of a contact in a dielectric layer having a layer of polysilicon with a patterned photoresist layer;  
         [0014]      FIG. 4B  shows the embodiment of  FIG. 4A  after etching in accordance with the invention, showing a contact in a dielectric layer having patterned polysilicon conductors;  
         [0015]      FIG. 5  is a simplified diagram for an embodiment of a controller coupled to an electronic device; and  
         [0016]      FIG. 6  illustrates a diagram for an embodiment of an electronic system having devices. 
     
    
     DETAILED DESCRIPTION  
       [0017]     The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.  
         [0018]     The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure or a micro electro-mechanical (MEM) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors or as semiconductors.  
         [0019]     The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.  
         [0020]      FIG. 1  shows an embodiment of an illustrative spin spray etch polysilicon (poly) etch. A spin spray system  100  has a vacuum spin assembly  102  having a vacuum pump and spin motor assembly  104 , connected via a valve and shaft  106  to a vacuum substrate holder (chuck)  108 , using the vacuum pressure to hold substrate  110 , which may illustratively be silicon. The substrate  110  is placed on the chuck  108 , and the vacuum valve  106  opens to provide vacuum pressure from the vacuum pump  104  to hold the substrate  110  on the spin chuck  108 .  
         [0021]     The wafer  110  either remains stationary, or spins at a predetermined speed or program of spin speeds, while an etch mixture is dispensed from dispense fixture  112 , illustratively shown as a shower head drip system. The subject matter is not so limited, and the fixture  112  may be a simple open tube nozzle, a high pressure atomizer (using purge gas  114  to break the etchant into tiny droplets), a linear array of drip nozzles, or other liquid dispense methods. The dispense fixture  112  receives materials such as a purge gas  114  through control valve  116 , or deionized water (DI water)  118  through valve  120 , or tetra methyl ammonium hydroxide (TMAH)  122  through valve  124 , or ammonium hydroxide  126  through valve  128 , or mixtures thereof, via pipe  130 .  
         [0022]     The etchants may be stored and dispensed in their final solution concentrations, or they may be mixed in pipe  130 . As an illustrative example, the TMAH  122  may be in the form of 100% TMAH and the valve  124  may be opened sufficiently to provide a 10% mixture of TMAH mixed with 90% DI water  118  through valve  120 . Alternatively, the TMAH  122  may be stored in the form of a 10% solution and dispensed through valve  124  directly through pipe  130  and dispense fixture  112  onto the substrate  110  without any mixing with any of the other stored materials  114 ,  118  or  126 .  
         [0023]     In an embodiment, the TMAH is provided as a 12.5% solution in DI water, and is mixed with 35% ammonium hydroxide during an initial decap etch stage prior to the main poly etch cycle. The TMAH storage  122  has a thermocouple and heater element to maintain a TMAH temperature of 90° C. The substrate  110  may be spun slowly during the initial oxide decap etch, or it may be held stationary in a puddle etch.  
         [0024]      FIG. 2  illustrates an embodiment of an illustrative tank poly etch system  200 . A hot plate  202  containing a thermocouple or other temperature controlling device maintains the tank  204  and the etch solution  206  in the tank at a predetermined temperature, in an embodiment 90° C. The etch solution has a surface  208  with etch substrates  210  immersed below the level of the surface  208 . Prior to immersing the substrates  210 , or simultaneous to immersing the substrates, or after a predetermined time period has elapsed since the last time an ammonium hydroxide spike was added to the solution  206 , in an embodiment one hour, a fixed volume of ammonium hydroxide  212  is added to the etch solution  206 , in an embodiment 1% of the volume of the etch solution  206 . In an embodiment, the pH of the solution  206  is maintained above a value of 13. The level of the etch solution  206  should always be high enough to cover all of the substrates  210 .  
         [0025]      FIG. 3A  illustrates a flow chart of steps for a spin etch  300  using the apparatus shown in  FIG. 1 . At  302  a substrate is placed on the vacuum chuck, and then an oxide decap etch using a mixture of ammonium hydroxide and TMAH at a temperature of 90° C. occurs at  304 , while the substrate remains stationary. After a fixed time period the ammonium hydroxide solution is turned off and the TMAH solution continues to flow, while the substrate slowly spins to agitate the etch solution and replace depleted portions of the etch solution at  306 . This continues for a predetermined time period, when the TMAH solution is turned off and the DI water rinse solution is turned on at  308 . The substrate continues to spin while the DI water rinse is progressing, until a predetermined time period expires, and the DI water is turned off. At  310  the substrate spins at a higher speed to dry the substrate, and the purge gas (typically nitrogen) may be turned on to blow dry the substrate. At  312  the substrate is removed from the chuck, typically by automated handling equipment, and moved to further substrate processing  314 , such as photoresist removal, or dielectric deposition, or various memory or MEM fabrication steps.  
         [0026]      FIG. 3B  illustrates a flow chart for a tank etch  320  using the apparatus of  FIG. 2 . At  322  the temperature of a TMAH bath is measured and maintained at a predetermined temperature, in an embodiment 90° C. A measured small amount of ammonium hydroxide solution, in an embodiment 1% of the etch solution volume, is added to the hot TMAH at  324 , a process that may be known as spiking. At least one substrate containing a poly layer to be etched, typically patterned photo-resist coated wafers, are immersed in the bath at  326 , and left to etch for a predetermined time period. In an embodiment the etch rate of poly is about 4,000 Å/minute. At  328  the substrates are removed from the etch bath and rinsed in DI water, or other washing procedures, and then dried at  330 . Spin drying or blow drying may typically be used. Alternatively, the imaged photo resist layer may be removed prior to drying the wafer, or even prior to washing the wafer. At  332  the substrate is moved to further substrate processing, such as photoresist removal, or dielectric deposition, or various memory or MEM fabrication steps.  
         [0027]      FIG. 4A  illustrates a semiconductor device  400  prior to decap and poly etch in accordance with the present invention. A substrate  402 , illustratively a semiconductor wafer, has a diffused region  404 , covered by a dielectric layer, such as silicon oxide layer  406 . The dielectric layer  406  has a hole, or contact recess  408  formed through the dielectric  406  to contact the diffused region  404 . A deposited layer of conductive TiN  410  covers the flat portion of the contact recess  408 . A layer of polysilicon  420 , which may be either doped or undoped, overlays the dielectric  406 , and fills the contact recess  408 .  
         [0028]     The polysilicon layer  420  may have what may be known as a native oxide layer  424  that may form in varying thicknesses due to exposure of the polysilicon layer  420  to the oxygen or moisture in the air during the time period after the polysilicon deposition, during the patterning process, and before the poly etch process. Removing this native oxide, also known as an oxide cap, may be known as a decapping process. A patterned photoresist layer  422  is formed on those portions of the polysilicon layer  420  that are desired to remain after the poly etch process.  
         [0029]      FIG. 4B  illustrates the semiconductor device  400  after decap and poly etch in accordance with the present invention. There are etched poly lines shown going into the plane of the figure, and the photoresist layer has been removed to better show the finished poly lines. There may be a remaining cap oxide layer on the tops of the etched poly lines  412  or  414 , or the photoresist removal process may strip off the cap oxide along with the photoresist. Any possible remaining oxide cap is not shown in this figure, but whether or not the cap oxide still exists does not affect the device or the processing of the device.  
         [0030]     A number of patterned and etched poly lines are shown with an orientation that is into and out of the plane of the figure. The poly lines such as  412  may be used to make an electrical contact to the diffused region  404  through the TiN layer  410 , and may also make contact with an overlaying layer of metal, such as aluminum. The TiN layer may be used in the contact recess  408  to prevent aluminum to silicon alloy spikes, or to prevent impurity contamination from reaching the sensitive electrical region at the diffusion to substrate boundary. Since the poly line  412  may be unintentionally (or intentionally) not completely covering the bottom of the contact recess  408 , it may be important to have a poly etch process that has a large poly to TiN etch ratio, so that the TiN may act as an etch stop. In a similar fashion, the poly lines  414  on the top of the dielectric layer  406  should have a etch process that has a large poly to oxide etch ratio, so as to not unnecessarily thin the protective dielectric layer  406 .  
         [0031]     Structures such as shown in  FIG. 4  may be used in any integrated circuit or transistor devices, such as flash memory devices as well as other memory, logic or information handling devices and systems. Embodiments of these information handling devices include wireless systems, telecommunication systems, computers and integrated circuits.  
         [0032]      FIG. 5  illustrates a diagram for an electronic system  500  having one or more devices having etched poly layers formed according to various embodiments of the present invention. Electronic system  500  includes a controller  502 , a bus  504 , and an electronic device  506 , where bus  504  provides electrical conductivity between controller  502  and electronic device  506 . In various embodiments, controller  502  and/or electronic device  506  include an embodiment for a conductive TiN layer in the contact recesses, and etched polysilicon lines as previously discussed herein. Electronic system  500  may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers.  
         [0033]      FIG. 6  depicts a diagram of an embodiment of a system  600  having a controller  602  and a memory  606 . Controller  602  and/or memory  606  include an etched conductive poly layer as described herein. System  600  also includes an electronic apparatus  608 , and a bus  604 , where bus  604  may provide electrical conductivity and data transmission between controller  602  and electronic apparatus  608 , and between controller  602  and memory  606 . Bus  604  may include an address, a data bus, and a control bus, each independently configured. Bus  604  also uses common conductive lines for providing address, data, and/or control, the use of which may be regulated by controller  602 . In an embodiment, electronic apparatus  608  includes additional memory devices configured similarly to memory  606 . An embodiment includes an additional peripheral device or devices  610  coupled to bus  604 . In an embodiment controller  602  is a processor. Any of controller  602 , memory  606 , bus  604 , electronic apparatus  608 , and peripheral device or devices  610  may include a signal conductor layer having an etched poly layer in accordance with the disclosed embodiments. System  600  may include, but is not limited to, information handling and telecommunication systems, and computers. Peripheral devices  610  may include displays, additional storage memory, or other control devices that may operate in conjunction with controller  602  and/or memory  606 .  
         [0034]     The use of an integrated decapping and polysilicon etch in a single etch bath has cost and time of manufacture benefits over etch systems that use separate etch baths for the decap etch versus the poly etch. Typically, a dilute hydrofluoric acid (HF) is used to remove the cap oxide, since HF solutions may be buffered to provide an etch rate that is consistent over a fairly long time period. After the HF decapping etch, the substrates must be washed and dried because of safety concerns with acids in general, and that acids and basic solutions such as TMAH have exothermic reactions when mixed. Thus, the poly etch process requires two different and typically incompatible etch baths that should not be located near each other due to safety concerns. This increases the cost and the amount of fabrication area needed for the etch process, and causes increased safety concern and chemical disposal problems. In addition, the time to etch the poly has increased, which also increases manufacturing cost.  
         [0035]     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of embodiments of the present invention, including TiN layers with graded compositions. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the present invention includes any other applications in which embodiments of the above structures and fabrication methods are used. The scope of the embodiments of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Technology Classification (CPC): 1