Patent Abstract:
A common-mode feedback circuit is provided for fully-differential operational amplifier stages of a multistage amplifier. A first stage of the circuit establishes a substantially constant current output level for a feedback generating stage of the circuit. An exemplary embodiment using MOSFET devices illustrates using a diode-connected MOSFET and mirror MOSFET first stage and a generating the current for a common-source connected MOSFET second stage connected to the respective outputs for said fully-differential operational amplifier. An output stage of the circuit provides feedback voltage at a first level when inputs to said fully-differential operational amplifier are in equilibrium and at a second level for balancing said fully-differential operational amplifier when inputs to said fully-differential operational amplifier are not in equilibrium.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     Not applicable.  
       STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Not applicable.  
       REFERENCE TO AN APPENDIX  
       [0003]     Not applicable.  
       BACKGROUND  
     TECHNICAL FIELD  
       [0004]     The technology described herein is generally related to the field of integrated circuits (“IC”) and, more particularly to operational amplifier circuits.  
       DESCRIPTION OF RELATED ART  
       [0005]     Two-stage complementary-metal-oxide-silicon (“CMOS”) operational amplifier (“op-amp”) circuits are ubiquitous in electronic circuit design, providing relatively high voltage gain, very high input impedance, very low output impedance, and good rejection of common-mode signals (two signal voltages of the same phase, frequency and amplitude on the inputs). One class of CMOS op-amp circuits has a differential input and a single output.  FIG. 1A  (Prior Art) illustrates a basic, two-stage, differential op-amp. In CMOS IC implementations, two or more differential amplifier stages are used where the gain of each stage is frequency dependent; the response of a multistage op-amp is a composite of the individual responses of the internal stages.  
         [0006]     One problem with two-stage CMOS op-amp circuits is an inability to both source and sink a large current to the output. For example, consider a CMOS op-amp where the first stage, input, devices are p-channel metal-oxide-silicon field-effect-transistors (“MOSFET”) and the second stage consists of a p-channel pull-up device that provides a constant bias current and an n-channel pull-down device in a common-source gain configuration. As such, the current that can be sourced from the positive power supply to the output is limited to the bias current in the p-channel device. The current that can be sunk from the output to the negative power supply (or ground) is greater, due to the gain of the common-source configuration. Conversely, an op-amp with n-channel inputs can source large currents but can only sink up to the bias current in the output stage. In general it is undesirable to increase the output current capability by increasing the bias currents as that would lead to large standby mode power dissipation.  
         [0007]     Common-mode feedback has been used in an operational amplifier having differential inputs and differential outputs wherein a predetermined common-mode output voltage independent of common-mode input voltage and input voltage variation is provided. U.S. Pat. No. 4,573,020, Feb. 25, 1886, by Whatley, for a FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER WITH D.C. COMMON-MODE FEEDBACK, uses D.C. common-mode feedback to provide a common-mode output voltage of the differential operational amplifier.  
       BRIEF SUMMARY  
       [0008]     The present invention generally provides for an improved, common-mode feedback circuit.  
         [0009]     The foregoing summary is not intended to be inclusive of all aspects, objects, advantages and features of the present invention nor should any limitation on the scope of the invention be implied therefrom. This Brief Summary is provided in accordance with the mandate of 37 C.F.R. 1.73 and M.P.E.P. 608.01(d) merely to apprise the public, and more especially those interested in the particular art to which the invention relates, of the nature of the invention in order to be of assistance in aiding ready understanding of the patent in future searches.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1A  (PRIOR ART) is a schematic block diagram of a two-stage differential amplifier.  
         [0011]      FIG. 1B  is an electrical circuit diagram of an exemplary implementation of a two-stage differential amplifier employing the present invention.  
         [0012]      FIG. 2  is an exemplary embodiment of a common-mode feedback device in accordance with the present invention as may be employed in a two-stage differential amplifier as shown in  FIG. 1B . 
     
    
       [0013]     Like reference designations represent like features throughout the drawings. The drawings in this specification should be understood as not being drawn to scale unless specifically annotated as such.  
       DETAILED DESCRIPTION  
       [0014]     The op-amp in its basic form typically consists of two or more differential amplifier stages. Using conventional symbols,  FIG. 1A  (Prior Art) shows a two-stage op-amp. The first stage, “STAGE  1 ,” is a fully-differential amplifier OP-AMP  1 , having two inputs, a non-inverting input “+Vin 1 ,” an inverting input “−Vin 1 ,” and respective outputs “+Vout 1 ,” “−Vout 1 ,” and a common-mode feedback device “CMFBD.” The second stage, “STAGE  2 ,” OP-AMP  2 , has inputs “+Vin 2 ,” “−Vin 2 ” connected respectively to the outputs +Vout 1 , −Vout 1  of STAGE  1  and a single output “Vout.” 
         [0015]      FIG. 1B  is a schematic diagram of an exemplary BiCMOS embodiment for a circuit implementing a two-stage op-amp device incorporating a common-mode feedback device to be described in depth with respect to  FIG. 2  hereinafter. This is a type of exemplary two-stage differential amplifier that is able to both source and sink a large current at its output OUT  102 . This exemplary circuit  100  is a folded-cascode, fully-differential input stage class op-amp followed by a push-pull, single-ended output stage class op-amp. It will be noted by those skilled in the art that a pair of bipolar input transistors Q 1 , Q 2  form the differential pair input stage. Four MOSFETs M 1 , M 2 , M 3 , and M 8  establish bias currents. Resistors R 5  and R 6  provide a load for the input transistors Q 1 , Q 2 . A pair of MOSFETs M 9 , M 10  are cascode devices. A pair of MOSFETs M 5 , M 6  provide an active load for the output. The differential output signals V 1 (+), V 2 (−) of the differential input stage are at the drain terminals of the active load MOSFETs M 5 , M 6  respectively. The push-pull single-ended output stage comprises a first pair of MOSFETs M 7 , M 12 . A second pair of MOSFETs M 4 , M 11  mirror the output signal at the drain of MOSFET M 5  around to the gate of MOSFET M 12 .  
         [0016]     As the first stage is a fully-differential op-amp in that both the input and output signals are differential, a CMFB device HB 1  is required on the first stage output to set the DC level of the outputs to be at a reference voltage potential between the two power supply rails  201 ,  203  potentials, e.g., a VDD potential and ground, GND, (or other secondary supply potential depending on the implementation) when a differential voltage is applied to the inputs of STAGE  1 .  
         [0017]     An improved common-mode feedback circuit HB 1  which may be employed with the circuit  100  of  FIG. 1B  is shown in  FIG. 2 .  FIG. 2  illustrates an exemplary implementation of a common-mode feedback circuit device, CMFC/HB 1   200 , in accordance with the present invention that has significant advantages over known manner CMFBD circuits such as shown by Whatley, supra. Reference to both FIGURES is made in the following detailed description of an exemplary structure of the present invention.  
         [0018]     In the CMFC/HB 1   200 , first pair of n-channel MOSFETs M 21 , M 23  receives the differential output voltages V 1 , V 2  (see also  FIG. 1A , “+Vout 1 ,” “−Vout 2 ”) from the first stage of the amplifier  100  at respective CMFC input terminal ports  202 ,  204 . MOSFET M 21  has a gate region  21 G connected to the CMFC input terminal port  202  for receiving the first output voltage V 1  of the amplifier  100  first stage,  FIG. 1B . MOSFET M 21  has a drain region  21 D connected by a CMFC input terminal port  201 ′ to one power supply rail  201 , GND, of the amplifier  100 . The source  21 S of MOSFET M 21  is connected to the source  23 S of the second MOSFET M 23 . The gate  23 G of MOSFET M 23  is connected to the CMFC input terminal port  204  and thus to the second output voltage V 2  of the first stage of the amplifier  100 . The drain  23 D of MOSFET M 23  is connected to the power supply rail  201 , GND.  
         [0019]     A third input terminal port  203 ′ to the CMFB  200  supplies power supply voltage VDD from power supply rail  203  to the CMFB through a second pair of n-channel MOSFETs M 25 , M 26  by being connected to and thereby biasing the respective source regions  25 S,  26 S. The gate regions  25 G,  26 G are connected to each other and to the drain region  26 D of MOSFET M 26 . The drain region  25 D of MOSFET M 25  is connected to the source regions  21 S,  23 S of the V 1 -V 2  receiving MOSFETs M 21 , M 23 , respectively.  
         [0020]     A third pair of MOSFETs M 22 , M 24  provide a CMFB output level “Vcmo” as DC common-mode feedback to the amplifier  100  via its first stage MOSFET M 6 . A n-channel MOSFET M 22  has its source region  22 S connected to the source regions  21 S,  23 S of the V 1 /V 2  input MOSFETs M 21 , M 23 , respectively. MOSFET M 22  has a body region connected to the body regions of MOSFETs M 21  and M 23 . Note that in this particular implementation, the substrate is p-type and p-channel FETs are formed in an n-well body region. While the exemplary embodiment(s) described herein is illustrative of using semiconductor devices having a specific transistor polarity implementation, it will be recognized by those skilled in the art that an implementation of reverse polarity devices can be made. No limitation on the scope of the invention is intended by the exemplary embodiment(s) and none should be implied therefrom. The drain region  22 D of MOSFET M 22  is gate coupled. The drain region  22 D of MOSFET M 22  is also connected to the drain region  24 D and gate  24 G of a p-channel  24 S of MOSFET M 24  is connected to the GND rail  201 . The gate region  24 G is connected to the drain region  24 D and Vcmo output.  
         [0021]     Compared to devices such as taught by Whatley, this exemplary common-mode feedback device of the present invention eliminates several devices, combines others, and reduces the total power supply current required for operation while still providing a DC common-mode output voltage Vcmo for the over all op-amp ( FIG. 1B ) functionality at the necessary level for operation of its push-pull output stage.  
         [0022]     Referring again to both  FIGS. 1B and 2 , operation of the present invention will be described. Assume initially that the amplifier  100  is in a steady-state condition with no differential signal applied. In this case, a CMFC/HB 1   200  will also be in a steady-state condition; currents through transistors M 21 , M 22  and M 23  are matched according to their geometric size ratios.  
         [0023]     For example, when transistors M 21 , M 22  and M 23  are substantially identical in size, if the drain current of transistor M 21  is “I,” then the drain current of transistor M 22 , which is geometrically equal to two transistors identical to M 21 , would be twice “I” or “2I.” The drain current of transistor M 23  would be “I,” the same as the current in transistor M 21 . Because of the well-known characteristics of FETs, this will cause the gate-to-source voltage of the three FET devices M 21 , M 22  and M 23  to be equal. With their source terminals  21 S,  22 S,  23 S all connect to the same node N 20 , the gate voltage of each FET M 21 , M 22  and M 23  will be equal. FET M 22  therefore sets a reference voltage established by the gate-to-source voltage of FET M 24 , and the CMFC HB 1  input terminal ports  202 ,  204 , voltages “V 1 ” and “V 2 ,” respectively, will be forced to a voltage equal to this reference.  
         [0024]     In a first stage of the CMFC HB 1   200 , the FET M 26  is “diode-connected.” A common current source circuit—not shown, but represented here as an ideal current by symbol “I 1 ”—is connected to the drain  26 D and gate  26 G of FET M 26 . The current source circuit is effectively a bias current which would be known in the art to be established by any number of circuits such as a band gap reference circuit. Current I 1  pulls down on the gate  26 G and drain  26 D, establishing a voltage on the gate that is a function of the current. FET M 25  is a “mirror FET” with the same connects of its gate  25 G and source  25 S as FET M 26 . Therefore, the current out of the drain  25 D of FET M 25  will tend to be equal to the current in FET M 26  which is I 1 . Thus, a current I 1 ′ out of the drain  25 D of FET M 25  flows into the node  207  connected to source regions M 21  S, M 23  of HB 1  second stage and source region M 22  of the HB 1  third stage of the CMFC/HB 1   200 . Thus, the output of the first stage is at a level such that it drives a common-source second stage. The third stage FETs M 22 , M 24  coupled to the second as described above thus provide the proper aforementioned Vcmo output.  
         [0025]     Now assume that this equilibrium state is disturbed by a differential input signal +Vin 1 , −Vin 2  to the amplifier  100 . The voltage at CMFC/HB 1   200  input  202  “V 1 ” will, for example, decrease while the voltage at CMFC/HB 1   200  input  204  “V 2 ” will, for example, increase. As a result of these changes, the drain current in FET M 21  will increase and the drain current in FET M 22  will decrease, but the equilibrium point of the CMFC/HB 1   200  is not affected. The circuit is still balanced as long as the total current through FET M 21  and FET M 23 , determined by summing the individual drain current of each device, is equal to the drain current of FET M 22 . In this case the common-mode feedback circuit does not affect the overall operation of the amplifier  100 .  
         [0026]     Note that when a differential signal of the opposite polarity—such that the voltage at CMFC/HB 1   200  input  202  “V 1 ” increases and the voltage at CMFC/HB 1   200  input  204  “V 2 ” decreases—would also produce the same result.  
         [0027]     If the equilibrium state is disturbed by a common-mode change such that the voltage at CMFC/HB 1   200  input  202  “V 1 ” and the voltage at CMFC/HB 1   200  input  204  “V 2 ” both change in the same direction, then the feedback circuit will operate to restore the amplifier  100  to equilibrium. For example, suppose that both CMFC inputs  202 ,  204  “V 1 ” and “V 2 ,” respectively, decrease in voltage. Transistors M 21  and M 23  will attempt to increase the amount of current flowing through them. Since the current available to the three FETs M 21 , M 22  and M 23  is fixed at “I 1 ” by the bias device M 25 , the increase in current through FETs M 21  and M 23  causes a corresponding decrease in the current flowing through FET M 22 . This reduced current causes the reference voltage “Vcmo” formed by the gate-to-source voltage of device M 24  to also decrease. The reference voltage “Vcmo” is then supplied to the amplifier circuit  100  first stage through CMFC/HB 1   200  output terminal port  206 .  
         [0028]     It can now be recognized that externally to the common-mode feedback circuit  200 , the amplifier  100  will respond in a known manner to the output “Vcmo” to increase the voltages at input terminals  202  and  203  “V 1 ” and “V 2 ” respectively. The CMFC/HB 1   200  circuitry is brought back into equilibrium, where the current through M 21  and M 23  is equal, and the current through M 22  is twice that value.  
         [0029]     The above analysis can be extended to the case where the common-mode imbalance is caused by both CMFC inputs  202 ,  204  wherein “V 1 ” and “V 2 ” are increasing in voltage.  
         [0030]     It will be understood that while a two-stage amplifier has been used as an exemplary embodiment, the concept can be readily adapted to implementations having more stages.  
         [0031]     Moreover, it will be understood by those skilled in the art that the concept of the present invention can be readily adapted to implementations using bipolar technology, BiCMOS technology, and the like integrated circuit design and fabrication processes.  
         [0032]     The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. For example, while the exemplary embodiment(s) described herein is illustrative of using semiconductor devices having a specific transistor polarity implementation, it will be recognized by those skilled in the art that an implementation of reverse polarity devices can be made. No limitation on the scope of the invention is intended by the exemplary embodiment(s) and none should be implied therefrom. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . ”

Technology Classification (CPC): 7