Patent Abstract:
Aspects for a power converter with power factor correction (PFC) circuit are described. The aspects include a buck/boost circuit for achieving a DC voltage from an AC input voltage signal line without developing an inrush current from the AC input voltage line, and a DC/DC converter circuit coupled to the buck/boost circuit for converting the DC voltage to a desired voltage level. The aspects are achieved in a straightforward, cost effective, and adaptable manner.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates to power converters, and more particularly to providing a power factor correction circuit that eliminates an inrush current limit circuit for a power converter. 
     BACKGROUND OF THE INVENTION 
     An important consideration in the design of power converters is that a power converter provide a high power factor. Power factor correction (PFC) circuits are commonly used in desktop computers where a high power factor is required. The power factor of power converters generally refers to the ratio of the true power to the product of the voltage and current in the circuit. A high power factor is one which approximates or exceeds 0.9, with the maximum power factor being 1.0. 
     One type of power converter, a boost-type power converter, is a well-known and practical choice for a high power-factor converter used in motor drive and power supply applications. While this converter circuit realizes the line current waveform needed to comply with line harmonic standards, both present and anticipated, and can provide a nearly full conduction angle, a boost converter requires the output voltage to always be higher than the peak input voltage. If a lower voltage is needed as, for example, in motor drives operating at lower speeds, then, the voltage reduction function must be performed separately. This adds to the converter cost and complexity. Boost-type converters must also have power on input current surge limiting circuits, and output short-circuit current limiting circuits. 
     Buck-type power converters are also generally well-known in the art, and are frequently used in DC to DC converters. They can also used as AC to DC power converters. A major limitation of buck-type converters is that the duration for which power can be extracted from a single-phase line supply (input conduction angle) decreases when the converter output voltage increases. A consequence of this limitation is the cost of the power converter increases while the benefits derived from using it decrease, especially when a wide range of output voltages (motor speeds) is required. 
     A need exists for a power factor correction circuit that avoids limitations of prior art circuits. In particular, a need exists for a power factor correction circuit that eliminates an inrush current limit circuit and that allows the DC voltage to be lower than the peak of AC line voltage. The present invention addresses such a need. 
     SUMMARY OF THE INVENTION 
     The present invention provides aspects for a power converter with power factor correction circuit. The aspects include a buck/boost circuit for achieving a DC voltage from an AC input voltage signal line without developing an inrush current from the AC input voltage and a DC/DC converter circuit coupled to the buck/boost circuit for converting the DC voltage to a desired voltage level. The PFC circuit in accordance with the present invention is straightforward, cost effective and capable of being easily adapted to current technology. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a conventional PFC circuit configuration. 
     FIG. 2 shows a PFC circuit in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     The present invention relates to power factor correction circuits, such as for a processing system. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein. 
     FIG. 1 depicts a conventional PFC circuit configuration  10 . The PFC circuit configuration  10  includes a boost stage portion  11  coupled to a DC/DC converter portion  12 . The boost stage portion  11  includes an AC line voltage input  13  coupled to a rectifier bridge  14  wherein the rectifier bridge  14  is coupled to a capacitor  16 . The capacitor  16  is coupled to a low resistance relay  20  and a resistor  18 . The resistor  18  is coupled to an inductor  24  wherein the inductor  24  is coupled to two diodes  22 ,  26 . The inductor  24  is further coupled to a transistor  30  wherein the transistor  30  is coupled to a pulse width modulator (PWM)  28 . The stage portion  11  also includes a bulk capacitor  32  coupled to the diode  26 . 
     The DC/DC converter portion  12  includes a transformer  36  coupled to a diode  40  and a transistor  38  wherein the transistor  38  is coupled to a pulse width modulator  34 . The diode  40  is coupled to a diode  42  and an inductor  46 . The inductor  46  is coupled to a capacitor  48  and an error amplifier  44 . The boost stage  11  develops a high voltage (i.e. 400V) across the bulk capacitor  32  and the DC/DC converter portion  12  converts the high voltage to a lower voltage (for example, 5V) output. 
     In this circuit, the diode  22  acts as a bypass diode and is used to prevent saturation of boost inductor  24 . Unfortunately, this configuration introduces a problem of inrush current because of capacitor  32  charging at turn-on time. That is, at turn-on time, capacitor  32  is charged by the high resistance of resistor  18 , which is later on bypassed by the low resistance relay  20 . The inrush current produced can be hundreds of amperes if it is not limited by some external means. A further problem with the circuit  10  is its ability to boost the voltage higher than the peak of the input voltage. 
     In accordance with the present invention, a circuit  50 , as shown in FIG. 2, prevents the above problems while providing power factor correction. The circuit  50  includes a buck/boost portion  51  coupled to a DC/DC converter portion  53 . Although the DC/DC converter portion  53  is represented in a slightly different manner than DC/DC converter portion  12  of circuit  10  (FIG.  1 ), DC/DC converter  53  operates similarly to any forward converter, including DC/DC converter portion  12  of circuit  10  (FIG.  1 ), to develop an isolated DC output voltage, as is well appreciated by those skilled in the art. 
     The buck/boost portion  51  includes an AC line voltage input  52  coupled to a rectifier bridge  54 , wherein the rectifier bridge  54  is coupled to a capacitor  56 . The capacitor  56  is coupled to a resistor  58  and transistor  60 , wherein the resistor  58  and transistor  60  are coupled to a driver  62 . The driver  62  is coupled to a buck/boost controller  64  and inverter  65 . The transistor  60  is further coupled to an inductor  66 , which in turn is coupled to a transformer  66 . Transistor  60  and inductor  66  are also coupled to a diode  72 , while transformer  68  is also coupled to diode  74 . The diode  74  is further coupled to a capacitor  76 , a transistor  78 , and the buck/boost controller  64 . The buck/boost portion  51  also includes a bulk capacitor  80  coupled to the diode  72 . 
     For the operation of circuit  50 , with the AC line current represented by lac=A sin(wt)/(1+k sin(wt)), the line current is quasi-sinusoidal. Further, with the voltage developed across capacitor  80  given by V=(d/1−d)×Vacsin(wt), where ‘d’ represents the duty cycle of the signal, the voltage across capacitor  80  can be lower than the peak of the AC line voltage (Vac). To achieve the desired sine wave, the current flowing through inductor  66  is integrated and applied to the standard buck/boost controller module  64 . In addition, with the rectifier bridge  54  being inverted as compared with the standard rectifier bridge for PFC circuits, the output of the rectifier bridge  54  is a negative fullwave voltage, which is converted into a positive DC voltage by the switching action of transistor  60 , inductor  66 , and diode  72 . 
     As is clear from the circuit  50 , the voltage across capacitor  80  is developed by the switching action of transistor  60  and diode  72 . Thus, there is no path for inrush current at the time of turn-on of AC input voltage. Accordingly, the circuit  50  does not need to include components that account for an inrush current in the buck/boost converter portion  51 . In this manner, the PFC circuit  50  in accordance with the present invention eliminates an inrush limit circuit, while also allowing the DC voltage to be lower than the peak of AC line voltage 
     Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Technology Classification (CPC): 8