Patent Abstract:
Display device wherein the change of the amount of light of the light-emitting elements caused by change of the number of light-emitting elements that emit light simultaneously is small. This display device includes: a display panel having light-emitting elements arranged in matrix fashion; data lines for applying anode potential to light-emitting elements of the same column; scanning lines for applying cathode potential to light-emitting elements of the same row; and a control circuit that adjusts the voltage between the anode and the cathode of the light-emitting elements in accordance with the number of light-emitting elements that emit light simultaneously. The control circuit suppresses changes of the voltage between the anode and the cathode of the light-emitting elements caused by a change in the number of light-emitting elements that emit light simultaneously. In this way, change of the amount of light of the light-emitting elements is suppressed.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates a display device using organic electroluminescence elements, light-emitting diodes or other similarly light-emitting elements. More particularly, the present invention relates to a display device having a driving circuit which can suppresses changes of light emission intensity of the light emitting elements.  
           [0003]    2. Description of the Related Art  
           [0004]    Display devices are known employing for example organic EL (electroluminescence) elements. Organic EL elements can be driven with low DC voltage. In addition, organic EL elements are light-emitting elements, so, compared with optically transparent elements such as liquid-crystal elements, they provide a wide field of view angle, a bright display surface and are of small thickness and light weight. Organic EL elements can therefore be employed as large-capacity display devices for various applications.  
           [0005]    A technique for driving organic EL display devices is disclosed in for example Japanese Laid-open publication number 301355/1994.  
           [0006]    The electrical characteristic of an organic EL element is disclosed in FIG. 7 of this publication. An organic EL element emits light when current flows in the forward direction between the anode and cathode. However, the light emission intensity of an organic EL element depends not merely on the current between the anode and cathode but also on the voltage between the anode and cathode. Consequently, in order to match the light emission intensity of the organic EL element accurately with the design value, it is necessary to control both the current and the voltage between the anode and cathode.  
           [0007]    An organic EL display device comprises a large number of organic EL elements arranged in matrix fashion. With such a construction, when a large number of organic EL elements emit light simultaneously, the amount of current flowing to ground becomes very large. The cathode potential of the organic EL elements therefore rises, due to the internal resistance of the drive circuit. Consequently, the voltage between the anode and cathode of the individual organic EL elements is decreased. That is, the light emission intensity of the individual organic EL elements may be lowered due to a large number of organic EL elements emitting light simultaneously.  
         SUMMARY OF THE INVENTION  
         [0008]    An object of the present invention is to provide a display device wherein the change of the amount of light of the light-emitting elements caused by change of the number of light-emitting elements that emit light simultaneously is small.  
           [0009]    For this purpose, a display device according to the present invention comprises: a display panel comprising light-emitting elements arranged in matrix fashion; a plurality of data lines that apply anode potential to light-emitting elements of the same column; a plurality of scanning lines that apply cathode potential to light-emitting elements of the same row; and a control circuit that adjusts the voltage between the anode and cathode of the light-emitting elements in accordance with the number of light-emitting elements that emit light simultaneously.  
           [0010]    The control circuit suppresses change of the voltage between the anode and cathode of the light-emitting elements caused by change of the number of light-emitting elements that emit light simultaneously. In this way, change of the amount of light of the light-emitting elements is suppressed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    Other objects and advantages of the present invention will be described with reference to the appended drawings.  
         [0012]    [0012]FIG. 1A is a circuit diagram illustrating the overall layout of a display device according to a first embodiment;  
         [0013]    [0013]FIG. 1B is a circuit diagram illustrating an example layout of a positive electrode output circuit illustrated in FIG. 1A;  
         [0014]    [0014]FIG. 1C is a circuit diagram illustrating an example layout of a negative electrode output circuit illustrated in FIG. 1A;  
         [0015]    [0015]FIG. 2 is a diagram given in explanation of the operation of a drive circuit according to a first embodiment;  
         [0016]    [0016]FIG. 3A is a circuit diagram illustrating the overall layout of a display device according to a second embodiment;  
         [0017]    [0017]FIG. 3B is a circuit diagram illustrating an example layout of a positive electrode output circuit illustrated in FIG. 3A;  
         [0018]    [0018]FIG. 4A is a circuit diagram illustrating the overall layout of a display device according to a third embodiment; and  
         [0019]    [0019]FIG. 4B is a circuit diagram illustrating an example layout of a positive electrode output circuit illustrated in FIG. 4A.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]    Embodiments of the present invention are described below with reference to the drawings. In the drawings, the size of the various constituent components, their shape and arrangement relationships are shown only diagrammatically to a degree such as to enable the present invention to be understood; also, numerical conditions described below are given merely by way of example.  
         [0021]    First Embodiment  
         [0022]    [0022]FIG. 1A to FIG. 1C are circuit diagrams illustrating the layout of a display device according to a first embodiment of the present invention.  
         [0023]    As shown in FIG. 1A, this matrix type display device comprises a display panel  100 , a shift register  110 , AND gate  120 , display number counter  130 , address decoder  140 , display data RAM (random access memory)  150 , negative electrode control RAM  160 , positive electrode output circuits  170 - 1  to  170 -n and negative electrode output circuits  180 - 1  to  180 -n.  
         [0024]    Display panel  100  comprises n×n (for example 128×128) organic EL elements EL 11  to ELnn, data lines SEG 1  to SEGn and scanning lines COM 1  to COMn. EL elements of the same column are connected with the same data line. Also, EL elements of the same row are connected with the same scanning line.  
         [0025]    Shift register  110  inputs serial display data DA with a timing supplied by clock CK and converts the data DA into n-bit parallel signals. In the display data of the present embodiment, high-level indicates “ignited” and low-level indicates “not ignited”.  
         [0026]    AND gate  120  inputs the display data DA and clock signal CK, and outputs the logical product of these signals.  
         [0027]    Display number counter  130  inputs the output signal of AND gate  120  and counts the number of high-level signals. The count result is output. The output count value indicates the number of “ignited” data items in the display data of a single row.  
         [0028]    Address decoder  140  outputs for example a 64-bit address signal A to display data RAM  150  and negative electrode control RAM  160 . Address signal A is employed as the write address and read address of RAM  150  and  160 .  
         [0029]    Display data RAM  150  stores the display data DA that is input from shift register  110 . In addition, display data RAM  150  outputs the bits of the storage data to positive electrode output circuits  170 - 1  to  170 -n.  
         [0030]    Negative electrode control RAM  160  stores the count value of display number counter  130 . Also, negative electrode control RAM  160  generates a negative electrode control signal using this stored value and outputs this to negative electrode output circuits  180 - 1  to  180 -n. 3-bit negative electrode control signals are supplied to each of the negative electrode output circuits  180 - 1  to  180 -n. The negative electrode control signals SK 1 , SK 2 , SK 3  that are supplied to negative electrode output circuits  180 - 1  are shown in FIG. 1. There are no particular restrictions on the method of determining the value of the negative electrode control signal. In this embodiment, when the count value is 1 to 32, only signal SK 1  is high-level; when the count value is 33 to 64, only signal SK 2  is high-level; and when the count value is 65 or more, only signal SK 3  is made high-level. With this method, negative electrode control signals SK 1 , SK 2  and SK 3  can be generated using only the most higher three bits of the count value. The negative electrode output circuits that are not selected are supplied with low-level negative electrode control signals which are also 3-bit.  
         [0031]    Positive electrode output circuits  170 - 1  to  170 -n input display data of corresponding bits from display data RAM  150 . The bits of the display data DA are subjected to inverted value/DA conversion when they are written to RAM  150 , before being input to positive electrode output circuits  170 - 1  to  170 -n. Positive electrode output circuits  170 - 1  to  170 -n output potentials corresponding to the values of the display data DA to the corresponding data lines to SEG 1  to SEGn. As shown in FIG. 1B, positive electrode output circuit  170 - 1  comprises a constant-current element  171 , a pMOS transistor  172  and an nMOS transistor  173 . Constant-current element  171  inputs power source voltage Vs (for example 20 volt) being supplied for the data line and outputs a constant current. Constant-current element  171  is constituted by for example an MOS transistor of fixed gate potential. pMOS transistor  172  is connected at its source to the output of constant-current element  171 , is connected at its drain to data line SEG 1  and is connected at its gate with the lowest bit of display data RAM  150 . Also, nMOS transistor  173  is connected at its source with the ground line, is connected at its drain with data line SEG 1  and is connected at its gate with the lowest bit of display data RAM  150 . Consequently, when the input display data/DA is low-level, positive electrode output circuit  170 - 1  outputs a prescribed high level voltage and when the input display data/DA is high-level potential outputs a prescribed low-level potential i.e. zero volts. The construction of the other positive electrode output circuits  170 - 2  to  170 -n is the same as the construction of positive electrode output circuit  170 - 1 .  
         [0032]    The negative electrode output circuits  180 - 1  to  180 -n discharge the current that is input from the cathodes of organic EL elements EL 11  to ELnn through scanning lines COM 1  to COMn to the ground line. The negative electrode output circuit  180 - 1  corresponding to scanning line COM 1  adjusts the cathode potential of organic EL elements EL 11  to Eln 1  in accordance with the signals SK 1 , SK 2  and SK 3  that are input from negative electrode control RAM  160 . As shown in FIG. 1C, negative electrode output circuit  180 - 1  comprises an OR gate  181 , pMOS transistor  182  and three nMOS transistors  183 - 1 ,  183 - 2  and  183 - 3 . OR gate  181  outputs the logical sum of signals SK 1 , SK 2  and SK 3 . pMOS transistor  182  is connected at its source with power source Vc being supplied for the scanning line (for example 20 volt), is connected at its drain with scanning line COM 1  and is connected at its gate with the output of OR gate  181 . nMOS transistor  183 - 1  is connected at its source with the ground line, is connected at its drain with scanning line COM 1  and inputs signal SK 1  from its gate. nMOS transistor  183 - 2  is connected at its source with the ground line and at its drain is connected with scanning line COM 1  and inputs signal SK 2  from its gate. nMOS transistor  183 - 3  is connected at its source with the ground line, is connected at its drain with scanning line COM 1  and inputs signal SK 3  from its gate. The ratios of the ON resistances of nMOS transistors  183 - 1 ,  183 - 2 ,  183 - 3  may be selected at will. In this embodiment, the ratios of the ON resistances of nMOS transistors  183 - 1 ,  183 - 2  and  183 - 3  are set to 4:2:1. The ratios of the ON resistances can be set by the gate widths of nMOS transistors  183 - 1 ,  183 - 2 , and  183 - 3 , for example. The constructions of the other negative electrode output circuits  180 - 2  to  180 -n are the same as the construction of negative electrode output circuit  180 - 1 .  
         [0033]    Next, the principles of operation of a display device according to this embodiment will be described using FIG. 1A to FIG. 1C and FIG. 2. Hereinbelow, the case where n=128 will be described by way of example.  
         [0034]    [0034]FIG. 2 is a concept diagram given in explanation of the operation of the display device illustrated in FIG. 1A to FIG. 1C.  
         [0035]    First of all, the operation of reading display data DA will be described.  
         [0036]    Display data DA is input to shift register  110  from outside in serial form synchronized with clock CK. The input display data DA is converted to data corresponding to one row worth of data, namely 128-bit parallel data. Simultaneously, display data DA in serial form and clock CK are also input to AND gate  120 . The output of AND gate  120  is input to display number counter  130 . As a result, the display number counter  130  counts the number of “ignition” data contained in one row of display data DA. The converted display data DA is sequentially stored in display data RAM  150  and the count value is simultaneously stored in negative electrode control RAM  160 . The storage position of the display data and the storage position of the count value are determined in accordance with the address signal A that is output from address decoder  140 .  
         [0037]    Next, the operation of displaying the first row of display panel  100  will be described. The operation of displaying the second and subsequent rows of display panel  100  is the same as in the case of the first row.  
         [0038]    Address decoder  140  outputs an address signal A corresponding to the display data of the first row. This address signal A is input to RAM  150  and  160 . Display data RAM  150  outputs of 128-bit data/DA (i.e. the inverted value of the display data DA) corresponding to the address signal A to positive electrode output circuits  170 - 1  to  170 -n. Also, negative electrode control RAM  160  outputs negative electrode control signals SK 1 , SK 2  and SK 3  to negative electrode output circuit  180 - 1 .  
         [0039]    Positive electrode output circuits  170 - 1  to  170 -n (n=128) input the corresponding bits of data/DA. As described above, positive electrode output circuits  170 - 1  to  170 -n output high level when data/DA is low level and output low level when the bit signal is high-level (see FIG. 1B) . The outputs of positive electrode output circuits  170 - 1  to  170 -n are applied to the anodes of the organic EL elements EL 11 , EL 21 , . . . , ELnn through data lines SEG 1  to SEGn.  
         [0040]    Negative electrode output circuit  180 - 1  inputs negative electrode control signals SK 1 , SK 2  and SK 3 . pMOS transistor  182  turns OFF when any of negative electrode control signals SK 1 , SK 2  and SK 3  is high-level. Also, nMOS transistor  183 - 1  turns ON when signal SK 1  is high-level, nMOS transistor  183 - 1  turns ON when signal SK 2  is high-level and nMOS transistor  183 - 3  turns ON when signal SK 3  is high-level. Low-level potential (ground potential) is therefore applied through scanning line COM 1  to the cathodes of organic EL elements EL 11 , EL 21 , . . . , ELn 1  of the first row.  
         [0041]    As a result, forward voltage is applied to the organic EL elements whose anodes have high-level potential applied to them while the voltage between the anode and cathode of organic EL elements which have low-level potential applied to their anodes is zero volts. For example, when positive electrode output circuit  170 - 1  is outputting high level and the other positive electrode output circuits  170 - 2  to  170 -n are outputting low level, organic EL element EL 11 , since forward voltage is being applied thereto, emits light, but the other organic EL elements do not emit light (see FIG. 2).  
         [0042]    As described above, when the number of organic EL elements that are simultaneously ON is 1 to 32, only signal SK 1  is high-level; when the number is 33 to 64, only signal SK 2  is high-level; when it is 65 or more, only signal SK 3  is high-level. Consequently, when the number of organic EL elements that are simultaneously ON is 1 to 32, only nMOS transistor  173  is turned ON; when the number is 33 to 64, only nMOS transistor  174  is turned ON; when it is 65 or more, only nMOS transistor  175  is turned ON. Also, as described above, the ratios of the ON resistances of nMOS transistors  183 - 1 ,  183 - 2  and  183 - 3  are set to 4:2:1. Consequently, if the ON resistance of an nMOS transistor is taken as R, the resistance of negative electrode output circuit  180 - 1  when the number of organic EL elements that are ON is 1 to 32 is 4R, when this number is 33 to 64 is 2R and when it is 65 or more is R.  
         [0043]    The current that flows out to ground from scanning line COM 1  through negative electrode output circuits  180 - 1  to  180 -n becomes larger as the number of organic EL elements that are simultaneously ON is increased. As a result, if the resistance of negative electrode output circuit  180 - 1  is fixed, the amount of voltage drop of the negative electrode output circuit  180 - 1  increases as the number of organic EL elements that are simultaneously ON is increased, so the voltage between the anodes and cathode of the organic EL elements that are in the ON state becomes smaller. In contrast, with the display device of this embodiment, the resistance of negative electrode output circuit  180 - 1  becomes smaller as the number of organic EL elements that are simultaneously ON is increased. Consequently, with the display device of this embodiment, change of the voltage between the anode and cathode of the organic EL elements can be suppressed so, as a result, changes of light emission intensity of the organic EL elements can be suppressed.  
         [0044]    In addition, this embodiment has the advantage that, since the resistance of negative electrode output circuits  180 - 1  to  180 -n is controlled using display number counter  130  and negative electrode control RAM  160 , the display device circuit layout can be simple.  
         [0045]    In this embodiment, the resistance of negative electrode output circuits  180 - 1  to  180 -n is controlled using three nMOS transistors  183 - 1  to  183 - 3 , but four or more transistors could be employed.  
         [0046]    Second Embodiment  
         [0047]    [0047]FIG. 3A. and FIG. 3B are circuit diagrams illustrating the layout of a display device according to a second embodiment of the present invention. In FIG. 3A, structural elements given the same reference symbols as in FIG. 1A are respectively the same as in FIG. 1A.  
         [0048]    As shown in FIG. 3A, a display device according to this embodiment comprises a decoder  310 . In addition, the internal construction of negative electrode output circuits  320 - 1  to  320 -n of the display device of this embodiment differs from the first embodiment.  
         [0049]    Decoder  310  inputs a negative electrode control signal from negative electrode control RAM  160  and outputs gate control signals. Here, outputs gate control signals G 1 , G 2 , . . . , G 8  are input to the negative electrode output circuits  320 - 1 . The number of gate control signals and G 1  to G 8  which are high-level signals is determined in accordance with the value of the binary number indicated by the negative electrode control signal. For example, when the value of the negative electrode control signal is 000, only signal G 1  is set to high level; when the value of the negative electrode control signal is 001, gate control signals G 1  and G 2  are set to high level; and when the value of the negative electrode control signal is 010 the gate control signals G 1 , G 2  and G 3  are set to high level. When the value of the negative electrode control signal is 111, all of the gate control signals G 1  to G 8  are set to high level. In this embodiment, the higher three bits of the count value of the display number counter  130  are employed as the value of the negative electrode control signal. The number of high-level gate control signals therefore increases when the count value becomes larger.  
         [0050]    The negative electrode output circuits  320 - 1  to  320 -n discharge to the ground line the current output from the cathodes of organic EL elements EL 11  to ELnn through scanning lines COM 1  to COMn. As shown in FIG. 3B, negative electrode output circuit  320 - 1  comprises an OR gate  321 , a pMOS transistor  322 , and eight nMOS transistors  323 - 1 ,  323 - 2 , . . . ,  323 - 8 . OR gate  321  outputs the logical sum of signals G 1  to G 8 . pMOS transistor  322  is connected at its source with power source Vc being provided to the scanning line (for example 20 volt), is connected at its drain with scanning line COM 1  and is connected at its gate with the output of OR gate  321 . nMOS transistors  323 - 1  to  323 - 8  are connected at their sources with the ground line, are connected at their drains with scanning line COM 1  and input corresponding signals G 1  to G 8  from their gates. The ON resistances of nMOS transistors  323 - 1  to  323 - 8  are the same. The constructions of the other negative electrode output circuits  320 - 2  to  320 -n are the same as the construction of negative electrode output circuit  320 - 1 .  
         [0051]    Next, the principles of operation of a display device according to this embodiment will be described. Hereinbelow the description will be given taking as an example the case where n=128.  
         [0052]    The operation of reading display data DA is the same as in the case of the first embodiment, so the description thereof will not be repeated.  
         [0053]    Hereinbelow, the operation of displaying the first row of display panel  100  will be described. The operation of displaying the second and subsequent rows of display panel  100  is the same as in the case of the first row.  
         [0054]    Address decoder  140  outputs address signal A corresponding to the display data of the first row. This address signal A is input to RAM  150  and  160 . Display data RAM  150  outputs 128-bit data/DA (i.e. the inverted value of display data DA) corresponding to address signal A to the positive electrode output circuits  170 - 1  to  170 -n. Also, negative electrode control RAM  160  outputs negative electrode control signals G 1  through G 8  to negative electrode output circuit  180 - 1 .  
         [0055]    Positive electrode output circuits  170 - 1  to  170 -n (n=128) input the corresponding bits of the data/DA. As described above, when the data/DA is low-level, positive electrode output circuits  170 - 1  to  170 -n output high level and when the bit signal is high level output low level (see FIG. 1B). The outputs of positive electrode output circuits  170 - 1  to  170 -n are applied to the anodes of the organic EL elements EL 11  to ELnn through data lines SEG 1  to SEGn.  
         [0056]    Decoder  310  inputs negative electrode control signals SK 1 , SK 2  and SK 3 . Also, as described above, decoder  310  makes some or all of the gate control signals G 1  to G 8  high level and makes the other gate control signals low level. In this way, the nMOS transistors corresponding to the high-level gate control signals are turned ON and the nMOS transistors corresponding to the low-level gate control signals are turned OFF. Since some or all of the nMOS transistors  323 - 1  to  323 - 8  are ON, scanning line COM 1  is low level.  
         [0057]    As a result, forward voltage is applied to the organic EL elements which have high-level potential applied to their anodes but the voltage between the anode and cathode of the organic EL elements which have low-level potential applied to their anodes is zero volts. For example, when positive electrode output circuit  170 - 1  outputs high level and the other positive electrode output circuits  170 - 2  to  170 -n output low level, forward voltage is applied to the organic EL element EL 11 , so this emits light but the other organic EL elements do not emit light.  
         [0058]    As described above, in this embodiment, the number of high-level gate control signals becomes larger as the count value of the display number counter  130  becomes larger. Consequently, in the-case of negative electrode output-circuit  180 - 1 , more nMOS transistors are turned ON as the count value becomes larger. The resistance of negative electrode output circuit  180 - 1  is the combined ON resistance of the nMOS transistors that are turned ON. The resistance of negative electrode output circuit  180 - 1  therefore becomes smaller as the count value is increased. With the display device of this embodiment, changes of the voltage between the anodes and cathode of the organic EL elements can therefore be suppressed and, as a result, changes in the light emission intensity of the organic EL elements EL can be suppressed.  
         [0059]    In this embodiment, the resistance of the negative electrode output circuits  180 - 1  to  180 -n was controlled using eight nMOS transistors; however, nine or more transistors or seven or less transistor could be employed.  
         [0060]    Third Embodiment  
         [0061]    [0061]FIGS. 4A and 4B is a circuit diagram illustrating the construction of a display device according to a third embodiment of the present invention. In FIG. 4A structural elements that have the same reference symbols as in FIG. 1A are respectively the same as in FIG. 1A.  
         [0062]    As shown in FIG. 4A and FIG. 4B, a display device according to this embodiment comprises a negative electrode controller  410 . Furthermore, the internal structure of the negative electrode output circuits  420 - 1  to  420 -n of the display device of this embodiment is different from that of the first embodiment.  
         [0063]    [0063]FIG. 4B is a circuit diagram illustrating the internal structure of negative electrode controller  410  and negative electrode output circuit  420 - 1 . Only portions of the negative electrode controller  410  of FIG. 4B that are associated with negative electrode output circuit  420 - 1  are illustrated.  
         [0064]    Negative electrode controller  410  comprises an OR gate  411  and a digital/analogue converter  412 . OR gate  411  inputs negative electrode control signals SK 1 , SK 2  and SK 3  from negative electrode control RAM  160  and outputs the logical sum of these signals as control signal CL 1 . Digital/analogue converter  412  inputs the signal values of the negative electrode control signals SK 1  to SK 3  as 3-bit binary information and outputs an analogue voltage signal CL 2  of a value corresponding to this information.  
         [0065]    Negative electrode output circuit  420 - 1  comprises a pMOS transistor  421  and nMOS transistor  422 . pMOS transistor  421  is connected at its source with power source Vc (for example 20 volt) and is connected at its drain with scanning line COM 1  and inputs signal CL 1  from its gate. nMOS transistor  422  is connected at its source with the ground line and is connected at its drain with scanning line COM 1  and inputs signal CL 2  from its gate.  
         [0066]    Next the principles of operation of a display device according to this embodiment will be described. Hereinbelow the case where n=128 will be taken as an example.  
         [0067]    The operation of reading display data DA is the same as in the case of the first embodiment so the description thereof will not be repeated.  
         [0068]    The operation of displaying the first row of display panel  100  will now be described. The operation of displaying the second and subsequent rows of display panel  100  is same as in the case of the first row.  
         [0069]    Address decoder  140  outputs address signal A corresponding to the display data of the first row. This address signal A is input to RAM  150  and  160 . Display data RAM  150  outputs 128 bit data/DA (i.e. the inverted value of the display data DA) corresponding to address signal A to positive electrode output circuits  170 - 1  to  170 -n. Also, negative electrode control RAM  160  outputs negative electrode control signals SK 1 , SK 2  and SK 3  to negative electrode controller  410 .  
         [0070]    Positive electrode output circuits  170 - 1  to  170 -n (n=128) output corresponding bits of the data/DA. As described above, positive electrode output circuits  170 - 1  to  170 -n output high level when data/DA is low level and output low level when the bit signal is high level (see FIG. 1B) . The outputs of positive electrode output circuits  170 - 1  to  170 -n are applied to the anodes of organic EL elements EL 11  to ELnn through data lines SEG 1  to SEGn.  
         [0071]    Negative electrode controller  410  inputs negative electrode control signals SK 1  to SK 3 . The output CL 1  of OR gate  411  is high-level except for when all of signals SK 1  to SK 3  are zero. pMOS transistor  421  is therefore OFF. Also, digital/analogue converter  412  outputs analogue voltage CL 2 . Consequently, nMOS transistor  422  is turned ON. As a result, scanning line COM 1  becomes low-level i.e. ground potential. Consequently, in the same way as in the first embodiment described above, of the organic EL elements EL 11 , EL 21 , . . . , ELn 1  that are connected with scanning line COM 1 , the organic EL elements that are connected with high-level data lines emit light.  
         [0072]    As described above, the value of the analogue voltage signal CL 2  changes in accordance with the values of negative electrode control signals SK 1  to SK 3 , so the ON resistance of nMOS transistor  422  changes in accordance with the values of signals SK 1  to SK 3 . Specifically, the ON resistance of nMOS transistor  422  becomes smaller as the count value of counter  130  becomes larger. Consequently, with the display device of this embodiment, changes of the voltage between the anode and cathode of the organic EL elements can be suppressed, so, as a result, changes of light emission intensity of the organic EL elements EL can be suppressed.  
         [0073]    With the display device of this embodiment, the ON resistance of the scanning line is controlled solely by a single nMOS transistor  422 , so the number of transistors can be reduced.  
         [0074]    In this embodiment, the negative electrode control signals were 3-bit signals, but they could be signals of four bits or more and they could be signals of two bits. The precision of control of the ON resistance can be increased as the number of bits is increased.  
         [0075]    The number of organic EL elements of the display panel  100  is not restricted but the advantages of the present invention become more marked as the number of organic EL elements becomes larger.  
         [0076]    In the first to the third embodiments, display panel  100  was constituted by organic EL elements, but the present invention could also be applied to display panels employing light-emitting elements of other types, for example light-emitting diodes.

Technology Classification (CPC): 6