Patent Abstract:
A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Full Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a method for designing a semiconductor device; and more particularly, to a high voltage generator and a memory device using the same. 
       DESCRIPTION OF RELATED ARTS 
       [0002]    Recently, an input/output path of a multi bit structure has been designed according to a data operation mode to improve a data transmission speed. In case of using the multi bit structure, the number of data which can be simultaneously read or written by addressing can be great. Accordingly, although semiconductor memory devices have the same data capacity, each of the semiconductor memory devices can have different structures. Particularly, the semiconductor memory devices can have the different structures related to outputting the data. For instance, the number of the data which are input and output during accessing the data once can be set with an x4, x8, or x16 operation mode. Thus, the semiconductor memory device reads or writes the number of the data corresponding to the data operation mode. 
         [0003]    Hence, the semiconductor memory device is designed to satisfy all of the x4, x8, and x16 operation modes and can perform an operation process according to each of the different data operation modes. The semiconductor memory device finally operates according to the operation mode selected from the x4, x8, and x16 operation modes. 
         [0004]    As for the semiconductor memory device, as an external power supply voltage VDD has been decreased and a high speed operation has been required, a word line WL voltage has been boosted to secure a low voltage margin and a data sensing speed from memory cells has been improved. Generally, in case of a cell including a transistor and a capacitor, the cell transistor is formed with an N-type metal oxide semiconductor (NMOS) transistor having an area smaller than a P-type metal oxide semiconductor (PMOS) transistor. 
         [0005]    Accordingly, a high voltage VPP greater than the external power supply voltage VDD as much as the threshold voltage of the cell transistor is used to read and write the logic low data and the logic high data without causing a loss in a data signal. Since the high voltage VPP needs to maintain an electric potential greater than the external power supply voltage VDD, the external power supply voltage VDD is raised to be used as the high voltage VPP in the semiconductor memory device. In most dynamic random access memory (DRAM) devices, the high voltage VPP is generated and used through a charge pumping operation. 
         [0006]      FIG. 1  is a diagram illustrating a plurality of typical word lines enabled by a data operation mode. 
         [0007]    A bank  10  includes the word lines WL 1 , WL 2  and WL 3  enabled according to the different data operation modes, i.e., x4, x8, and x16. If the data operation mode is one of the x4 and x8 operation modes, the word lines WL 2  and WL 3  are enabled in the bank  10  which is divided into two blocks (e.g., an upper block and a lower block). When the data operation mode is the x16 operation mode, the number of word lines is increased by one compared to when the data operation mode is one of the x4 and x8 operation modes. When the data operation mode is the x16 operation mode, the number of the word lines becomes two times greater than when the data operation mode is one of the x4 and x8 operation modes. A high voltage generator needs to have a driving force two times greater when the data operation mode is the x16 operation mode than when the data operation mode is one of the x4, and x8 operation modes. 
         [0008]      FIG. 2  is a block diagram of a typical high voltage generator. 
         [0009]    The typical high voltage generator includes a high voltage detection unit  20  for comparing a reference voltage VREF with a high voltage VPP and enabling an oscillator enable signal PPES if the high voltage VPP is lower than the reference voltage VREF, an oscillator  40  for receiving the oscillator enable signal PPES and generating a clock signal OSC having a predetermined frequency, and a high voltage pumping unit  60  for receiving the clock signal OSC generated in the oscillator  40  and performing a charge pumping operation to output the high voltage VPP. 
         [0010]      FIG. 3  is a block diagram of a typical arrangement of a plurality of banks and a plurality of high voltage generators. 
         [0011]    The first to fourth high voltage generating units  12 A,  12 B,  12 C, and  12 D are respectively assigned to the first to fourth banks  10 A,  10 B,  10 C, and  10 D. A peripheral circuit  14  is placed in the center of a memory chip. 
         [0012]      FIG. 4  is a graph illustrating a width ΔV changing with a voltage level of a high voltage VPP generated in a typical high voltage generator. 
         [0013]    The high voltage VPP cannot be uniformly maintained because of a delay due to a response time of the high voltage detection unit  20  (see  FIG. 2 ). Thus, the high voltage VPP fluctuates within a width ΔV. 
         [0014]    As explained with respect to  FIG. 1 , when the data operation mode is the x16 operation mode, the high voltage generator has the driving force two times greater than when the operation mode is one of the x4 and x8 operation modes. 
         [0015]    Accordingly, the following two methods are used to correspond to a difference in the driving forces between when the high voltage generator is set based on the x16 operation mode and when the high voltage generator is set based on the x4 or x8 operation mode. 
         [0016]    The first method is used when the high voltage generator is set based on the x16 operation mode. The second method is used when high voltage generator is set based on the x4 or x8 operation mode. According to the second method, the half of the high voltage generating units  12 A,  12 B,  12 C, and  12 D (herein, only four high voltage generators are shown) are used when the high voltage generator is set based on the x4 or x8 operation modes. 
         [0017]    However, when the first method is used, if the response time of the high detection unit  20  is slow, the width ΔV changing with the voltage level of the high voltage VPP with respect to a target voltage VPP_TARGET becomes large since a pumping operation ability of the high voltage generators is greater than when the second method is used. 
         [0018]    In case of using the second method, since the high voltage generators are not uniformly arranged throughout a chip when the data operation mode is one of the x4 and x8 operation modes, it is difficult to control portions of the chip apart from each of the high voltage generators. 
       SUMMARY OF THE INVENTION 
       [0019]    It is, therefore, an object of the present invention to provide a high voltage generator, wherein the high voltage generator minimizes a width changing with a voltage level of a high voltage VPP with respect to a target voltage VPP_TARGET by making an amount of pumped electric charges vary depending on a data operation mode. 
         [0020]    It is another object of the present invention to provide a memory device having a word line driving high voltage generator placed to minimize a width changing with a voltage level of a high voltage VPP for driving word lines with respect to a target voltage VPP_TARGET by making a period of an oscillator vary depending on an x4, x8 or x16 operation mode. 
         [0021]    In accordance with one aspect of the present invention, there is provided a high voltage generator, including: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals. 
         [0022]    In accordance with another aspect of the present invention, there is provided a word line driving high voltage generator of a semiconductor memory device capable of processing one of a first operation mode and a second operation mode depending on a data operation mode, and including the number of word lines enabling according to the operation mode, including: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal depending on a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
           [0024]      FIG. 1  is a diagram illustrating a plurality of typical word lines enabled by a data operation mode; 
           [0025]      FIG. 2  is a block diagram of a typical high voltage generator; 
           [0026]      FIG. 3  is a block diagram of a typical arrangement of a plurality of banks and a plurality of high voltage generators; 
           [0027]      FIG. 4  is a graph illustrating a width ΔV changing with a voltage level of a high voltage VPP generated in a typical high voltage generator; 
           [0028]      FIG. 5  is a diagram of a high voltage generator in accordance with an embodiment of the present invention; 
           [0029]      FIGS. 6A to 6C  are circuit diagrams of oscillators in accordance with first to third specific embodiments of the present invention; and 
           [0030]      FIG. 7  is a graph illustrating a width ΔV changing with a voltage level of a high voltage VPP generated in a high voltage generator with respect to a target voltage VPP_TARGET in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0031]    Hereinafter, detailed descriptions on certain embodiments of the present invention will be provided with reference to the accompanying drawings. 
         [0032]      FIG. 5  is a diagram of a high voltage generator in accordance with an embodiment of the present invention. 
         [0033]    The high voltage generator in accordance with the embodiment of the present invention includes a high voltage detection unit  200 , an oscillator frequency selection unit  300 , an oscillator  400 , and a high voltage pumping unit  600 . 
         [0034]    The high voltage detection unit  200  compares a high voltage VPP with a reference voltage VREF and enables an oscillator enable signal PPES if the high voltage VPP is lower than the reference voltage VREF. 
         [0035]    The frequency selection unit  300  outputs a first control signal A or a second control signal B in response to the enabled enable signal PPES and an operation signal based on a data operation mode (e.g., an x4, x8, or x16 operation mode). The x4, x8, and x16 operation modes indicate the number of data input and output during accessing the data once. 
         [0036]    The oscillator  400  generates a clock signal OSC having a different frequency in response to the first control signal A or the second control signal B. 
         [0037]    The high voltage pumping unit  600  receives the clock signal OSC and performs a charge pumping operation to output the high voltage VPP corresponding to the clock signal OSC. 
         [0038]    Detailed explanations of the high voltage detection unit  200  and the high voltage pumping unit  600  will be omitted herein since embodiment of these as a typical high voltage detection unit and a typical high voltage pumping unit, would be understood by people skilled in this art. Hereinafter, the frequency selection unit  300  and the oscillator  400  will be explained in detail. 
         [0039]    The frequency selection unit  300  includes a first control signal generating unit  320  comprising an AND gate AND 2  receiving the oscillator enable signal PPES and an x16 operation signal x16, and a second control signal generating unit  340  comprising an OR gate OR 2  receiving an x4 or x8 operation signal x4 or x8 and an AND gate AND 4  receiving an output signal of the OR gate OR 2 . 
         [0040]    The frequency selection unit  300  outputs the first control signal A in response to the oscillator enable signal PPES of the high voltage detection unit  200  and the x16 operation signal x16, and outputs the second control signal B in response to the oscillator enable signal PPES of the high voltage detection unit  200  and the x4 or x8 operation signal. 
         [0041]      FIG. 6A  is a circuit diagram of an oscillator in accordance with a first specific embodiment of the present invention. 
         [0042]    The oscillator  400 A includes a first oscillator unit  420 A, a second oscillator unit  440 A, and an output unit NAND 1 . The first oscillator unit  420 A generates a clock signal with a high frequency in response to a first control signal A. The second oscillator unit  440 A generates a clock signal with a frequency lower than the clock signal generated in the first oscillator unit  420 A in response to a second control signal. The output unit NAND 1  outputs a final output clock signal OSC in response to the output signals of the first oscillator unit  420 A and the second oscillator unit  440 A. 
         [0043]    The first oscillator unit  420 A includes a NAND gate NAND 3 , and the first inverters INV 3 . The NAND gate NAND 3  receives the first control signal A and final output signals of the first inverters INV 3 . The first inverters INV 3  are coupled with each other in series and receive an output signal of the NAND gate NAND 3 . 
         [0044]    The second oscillator unit  440 A includes a NAND gate NAND 5 , and a plurality of second inverters INV 5 . The NAND gate NAND 5  receives the second control signal B and final output signals of the second inverters INV 5 . The second inverters INV 5  are coupled with each other in series and receive an output signal of the NAND gate NAND 5 . Also, the second inverters INV 5  have more stages than the first inverters INV 3 . 
         [0045]    The output unit NAND 1  includes an NAND gate NAND 1  receiving the output signals of the first inverters INV 3  and the second inverters INV 5 . 
         [0046]      FIG. 6B  is a circuit diagram of an oscillator in accordance with a second specific embodiment of the present invention. 
         [0047]    The oscillator  400 B in accordance with the second embodiment of the present invention includes an OR gate OR 3 , a NAND gate NAND 7 , a plurality of first inverters INV 7 , a NAND gate NAND 9 , a plurality of second inverters INV 9 , a first pass gate G 7 , and a second pass gate G 9 . The OR gate OR 3  receives a first control signal A and a second control signal B. The NAND gate NAND 7  receives an output signal of the OR gate OR 3  and a final output clock signal OSC. The first inverters INV 7  are coupled with each other in series and receive an output signal of the NAND gate NAND 7 . The NAND gate NAND 9  receives output signals of the first inverters INV 7  and the second control signal B. The second inverters INV 9  are coupled with each other in series and receive an output signal of the NAND gate NAND 9 . The first pass gate G 7  transfers the output signals of the first inverters INV 7  to the NAND gate NAND 7  in response to the first control signal A and a reverse signal /A of the first control signal. The second pass gate G 9  transfers the output signals of the second inverters INV 9  to the NAND gate NAND 7  in response to the second control signal and a reverse signal /B of the second control signal. 
         [0048]      FIG. 6C  is a circuit diagram of an oscillator in accordance with a third specific embodiment of the present invention. 
         [0049]    The oscillator  400 C includes an OR gate OR 4 , a NAND gate NAND 11 , a plurality of inverters INV 11 , a plurality of N-type metal oxide semiconductor (NMOS) transistors N 1 , N 2 , N 3 , N 4 , and N 5 , and a plurality of NMOS capacitors C 1 , C 2 , C 3 , C 4 , and C 5 . The OR gate OR 4  receives a first control signal A and a second control signal B. The NAND gate NAND 11  receives an output signal of an OR gate OR 4  and a final output clock signal OSC. The inverters INV 11  are coupled to each other in series and receive an output signal of the NAND gate NAND 11 . One terminal of each of the NMOS transistors N 1 , N 2 , N 3 , N 4  and N 5  is coupled to respective nodes M 1 , M 2 , M 3 , M 4 , and M 5  of the inverters INV 11  and receive the second control signal B. The NMOS capacitors C 1 , C 2 , C 3 , C 4 , and C 5  are disposed between a ground voltage terminal VSS and the other terminal of the respective N 1 , N 2 , N 3 , N 4 , and N 5 . 
         [0050]    The oscillators  400 A,  400 B, and  400 C receive the first control signal A or the second control signal B according to the data operation mode (e.g., the x4, x8 or x16 operation mode) to generate a different oscillator frequency OSC. In other words, if the data operation mode is the x16 operation mode, the first control signal A is enabled. If the data operation mode is one of the x4 and x8 operation modes, the second control signal B is enabled. If the oscillators  400 A,  400 B, and  400 C receive the first control signal A, a clock signal having a frequency two times greater than that generated while the oscillators  400 A,  400 B, and  400 C receive the second control signal B is generated. The frequency of the clock signal generated by the first control signal A is two times greater than the frequency of the clock signal generated by the second control signal B. 
         [0051]    Referring to  FIG. 5 , the high voltage pumping unit  600  performs the charge pumping operation corresponding to the clock signal OSC to generate the high voltage VPP. The high voltage pumping unit  600  receiving the clock signal OSC generated in response to the first control signal A operates with a speed two times faster than a normal speed. That is, the high voltage pumping unit  600  pumps an amount of electric charges two times greater than a normal amount to output the high voltage VPP. The high voltage pumping unit  600  receiving the clock signal OSC generated in response to the second control signal B operates with the normal speed. Accordingly, the amount of the electric charges pumped by the high voltage pumping unit  600  to output the high voltage VPP is reduced by the half. 
         [0052]      FIG. 7  is a graph illustrating a width ΔV_NEW changing with a voltage level of a high voltage VPP generated in a high voltage generator with respect to a target voltage VPP_TARGET in accordance with an embodiment of the present invention. 
         [0053]    In a typical high voltage generator, when a data operation mode is one of x4 and x8 operation modes, if a response time of the high voltage detection unit  20  (see  FIG. 2 ) is slow, an amount of electric charges pumped once is large because the typical high voltage generator is designed based on an x16 operation mode. Accordingly, there is a considerable width ΔV OLD changing with a voltage level of a high voltage VPP with respect to the target voltage VPP_TARGET. 
         [0054]    However, when the high voltage generator is designed according to this embodiment of the present invention, if a response time of the high voltage detection unit  200  (see  FIG. 5 ) is the same as the typical high voltage detection unit  20  (see  FIG. 2 ), an amount of electric charges corresponding to the x4 or the x8 operation mode is pumped to output the high voltage VPP. Accordingly, there can be a reduced width ΔV_NEW changing with a voltage level of the high voltage VPP with respect to the target voltage VPP_TARGET. 
         [0055]    The high voltage generators according to this embodiment of the present invention supply different amounts of electric charges according to the different data operation modes (e.g., the x4, x8 or x16 operation mode). Accordingly, the amount of electric charges to generate the high voltage VPP to each of the banks is uniformly supplied and thus, the high voltage generators corresponding to all of the banks can operate regardless of the x4, x8, and x16 operation modes. The semiconductor memory device including the high voltage generators uses all of the high voltage generators to enable the number of word lines corresponding to the x4, x8, and x16 operation modes. 
         [0056]    According to this embodiment of the present invention, a width changing with a voltage level of a high voltage VPP with respect to a target voltage V_TARGET is reduced to obtain the high voltage VPP. Also, a plurality of high voltage generators are uniformly arranged to a plurality of banks and thus, it is possible to stably control all of the banks. Furthermore, regardless of the operation modes, all of the high voltage generators are used and thus, efficiency in circuits of the semiconductor memory device can be improved. 
         [0057]    The present application contains subject matter related to the Korean patent application No. KR 2005-0090918, and 2006-0030937, respectively filed in the Korean Patent Office on Sep. 29, 2005, and Apr. 5, 2006 the entire contents of which being incorporated herein by reference. 
         [0058]    While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Technology Classification (CPC): 6