Patent Abstract:
A method of fabricating a semiconductor device includes a dry etching process of a silicon surface. The dry etching process is conducted by an etching gas containing at least one gas species selected from the group consisting of: HBr, HCl, Cl 2 , Br 2  and HI, wherein the dry etching process includes a first step conducted at a first temperature; and a second step conducted at a second temperature.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     The present application is based on Japanese priority application No. 2005-002972 filed on Jan. 7, 2005, the entire contents of which are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention generally relates to semiconductor devices and more particularly to a fabrication method of semiconductor device that uses an anisotropic etching process and a semiconductor device fabricated by such a fabrication process.  
         [0003]     Conventionally, polysilicon gate electrode of semiconductor devices is formed by an anisotropic dry etching process of a polysilicon film by using an RIE process.  
         [0004]     With such an anisotropic dry etching process, Si atoms ejected from the polysilicon film with the etching process cause reaction with the etching gas to form a byproduct, and such a byproduct protects the sidewall surface of the gate electrode pattern from further etching as they are deposited on such a sidewall surface. As a result, the polysilicon gate electrode is formed in the state that it is defined by a pair of straight sidewall surfaces perpendicular to the substrate surface.  
         [0005]     Further, such an anisotropic etching process has been used also for formation of STI (shallow trench isolation) structures that include a device isolation trench.  
       REFERENCES Reference 1 Japanese Laid-Open Patent Application 2004-152784  
     SUMMARY OF THE INVENTION  
       [0006]      FIGS. 1A-1D  show the method of forming a polysilicon gate electrode according to a related art that uses a conventional RIE process.  
         [0007]     Referring to  FIG. 1A , there is deposited a polysilicon film  13  on a silicon substrate  11  via a thermal oxide film  12  that functions as a gate insulation film, and a resist pattern corresponding to the desired polysilicon gate electrode is formed on the polysilicon film  13  by a photolithographic process.  
         [0008]     Further, in the step of  FIG. 1C , the polysilicon film  13  is patterned by an RIE process while using the resist pattern R 1  as a mask, and a polysilicon gate electrode pattern  13 G is formed as a result of the RIE process.  
         [0009]     With such a dry etching process, it should be noted that the Si atoms ejected from the polysilicon film  13  as a result of the etching cause a reaction with the halogen etching gas admixed with oxygen, such as an HBr gas, and there occurs formation of a byproduct such as SiBr x O y , or the like, wherein such a byproduct functions as a sidewall protective film that protects the sidewall surface of the polysilicon gate electrode pattern  13 G from further etching. As a result, the polysilicon gate electrode pattern  13 G is formed to have a straight sidewall surface generally perpendicular to the principal surface of the silicon substrate  11 .  
         [0010]     Here, it should be noted that silicon of n-type has a higher reactivity than p-type, and thus, it is necessary to form such a sidewall protective film to have a larger thickness, when to form a gate electrode by patterning an n-type polysilicon film with good controllability of etching, as compared with the case of forming the same polysilicon gate electrode by patterning a p-type or non-doped polysilicon film.  
         [0011]     The process of  FIG. 1C  is continued until the thermal oxide film  12  is exposed, wherein it is generally practiced to continue the dry etching process in the step of  FIG. 1D  (over etching) for ensuring that the polysilicon film  13  is removed from the surface of the thermal oxide film  12  completely except for the gate electrode  13 G  
         [0012]     Meanwhile, the inventor of the present invention has discovered a problem that the shape of the sidewall surfaces of the gate electrode pattern  13 G tends to become irregular as shown in  FIGS. 2 and 3  when such ordinary patterning process of polysilicon gate electrode, which relies on the conventional RIE process, is applied for formation of the gate electrode having the gate length of 80 nm or less. Here, it should be noted that  FIG. 3  is a diagram showing the sketch of the cross-section of the n-type polysilicon gate electrode of the photograph of  FIG. 2 .  
         [0013]     Referring to  FIGS. 2 and 3 , it can be seen that the polysilicon gate electrode pattern  13 G experiences erosion at the bottom part thereof. It is believed that such erosion of the sidewall surface of the polysilicon gate electrode is caused by dropping off of silicon crystal grains.  
         [0014]     In the overetching process of  Figure 1D , it should be noted that there no longer occurs substantial etching of fresh silicon film with the dry etching process, and thus, the supply of the reaction byproduct to the sidewall surface of the polysilicon gate electrode  13 G as in the case of  FIG. 1C  should be depleted. It is believed that with such depletion of the reaction byproduct, the sidewall protective film, formed by the byproduct, is vanished, and this is the reason why lateral etching has been caused at the sidewall surface of the polysilicon gate electrode  13 G as shown in  FIGS. 2 and 3 .  
         [0015]     Because the lateral etching of the sidewall surface of the polysilicon gate electrode starts from where the sidewall protective film has vanished, the polysilicon gate electrode pattern can have various different shapes other than those shown in  FIGS. 2 and 3 , such as the one shown in  FIG. 4 .  
         [0016]     It is possible that such lateral etching at the sidewall surface of the polysilicon gate electrode has already been caused at the time of the over etching process in the conventional fabrication process of conventional semiconductor devices that have a gate length exceeding 100 nm. However, this problem has never attracted attention probably because the effect of such lateral etching only causes negligible effect with such a conventional semiconductor device having the gate length exceeding 100 nm.  
         [0017]     On the other hand, with the semiconductor devices having the gate length of 100 nm or less, such irregular lateral etching occurring at the sidewall surfaces of the gate electrode is not ignorable at all, as such irregularity may cause substantial change of device characteristics such as deviation of gate length from the designed value, increase of gate resistance, and the like.  
         [0018]     As noted previously, the problem of lateral etching at the time of patterning of the polysilicon gate electrode becomes particularly serious when patterning an n-type polysilicon gate electrode pattern, in which the reactivity of the n-type polysilicon film is large and thus a thick sidewall protection film is required.  
         [0019]     This further means that there may even be a possibility that the polysilicon gate electrode pattern shape may be different between the p-type polysilicon gate electrode and n-type polysilicon gate electrode even when the p-type polysilicon film and the n-type polysilicon film are formed on a common silicon substrate and patterned at the same time, due to the enhanced sidewall lateral etching in the n-type polysilicon gate electrode at the time of the overetching step of  FIG. 1D .  
         [0020]     In a first aspect, the present invention provides a method of fabricating a semiconductor device comprising a dry etching process of a silicon surface,  
         [0021]     said dry etching process being conducted by an etching gas containing at least one gas species selected from the group consisting of: HBr, HCl, Cl 2 , Br 2  and HI, said dry etching process comprising a first step conducted at a first temperature and a second step conducted at a second temperature.  
         [0022]     In another aspect, the present invention provides a dry etching method of a silicon surface, comprising: a first step conducted at a first temperature; and a second step conducted at a second temperature, said first and second steps being conducted by an etching gas containing at least one gas species selected from the group consisting of HBr, HCl, Cl 2 , Br 2  and HI, wherein a deposition gas containing one or both of oxygen and sulfur is added to said etching gas.  
         [0023]     According to the present invention, the sidewall surface of the structure formed by the dry etching process is effectively protected from etching by changing the temperature in the second step of the dry etching process or by adding a deposition gas containing oxygen and not attacking the deposits on the sidewall surface of the foregoing structure, to the etching gas in the foregoing second step.  
         [0024]     Thus, in the case of forming a polysilicon gate electrode by such a dry etching process, the problem of attacking of the sidewall surface of the gate electrode associated with the overetching process is successfully suppressed by conducting the overetching process after the patterning of the polysilicon gate electrode in the form of the foregoing second step, and it becomes possible to obtain a polysilicon gate electrode of desired cross-sectional shape with desired gate length.  
         [0025]     Further, in the case of forming a device isolation trench in a silicon substrate, too, it becomes possible to form a tapered part forming a shallow angle at the bottom part of the device isolation trench by forming the main part of the device isolation trench in the foregoing first step and then conducting the dry etching process comprising the foregoing second step. With this, the withstand voltage of the device isolation trench is improved and filling of the device isolation trench by a CVD insulation film is facilitated.  
         [0026]     Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIGS. 1A-1D  are diagrams showing a conventional dry etching process of a polysilicon gate electrode;  
         [0028]      FIG. 2  is a diagram showing the problem of the conventional dry etching process of the polysilicon gate electrode;  
         [0029]      FIG. 3  is a diagram showing the problem of  FIG. 2  schematically;  
         [0030]      FIG. 4  is another diagram showing the problem of  FIG. 2  schematically;  
         [0031]      FIGS. 5A-5D  are diagrams showing the dry etching process of a polysilicon gate electrode according to a first embodiment of the present invention;  
         [0032]      FIG. 6  is a diagram showing the cross-section of a polysilicon gate electrode patterned according to the steps of  FIGS. 5A-5D ;  
         [0033]      FIGS. 7A-7G  are diagrams showing the fabrication process of a CMOS device according to a second embodiment of the present invention;  
         [0034]      FIGS. 8A-8D  are diagrams showing the formation process of an STI device isolation structure according to a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     First Embodiment  
       [0035]      FIGS. 5A-5  are diagrams showing the formation of a polysilicon gate electrode pattern according to a first embodiment of the present invention.  
         [0036]     Referring to  FIG. 5A , a polysilicon film  23  is formed on a silicon substrate with a thickness of about 100 nm via a silicon oxide film or a silicon oxynitride film  22  having a thickness of 1-2 nm, and a silicon oxide film  24  acting as a hard mask is formed on the polysilicon film  23  with the thickness of about 30 nm. Further, an organic antireflection coating (BARC)  25  is formed on the hard mask film  24 , and a resist pattern R 2  is formed on the BARC  25  with the shape of the gate electrode pattern to be formed.  
         [0037]     Next, in the step of  FIG. 5B , the structure of  FIG. 5A  is introduced into a plasma etching apparatus of ICP type, for example, and the BARC  25  is subjected to an etching process in a mixed gas ambient of He/O 2 /SO 2  while using the resist pattern R 2  as a mask.  
         [0038]     More specifically, the etching of the BARC  25  is conducted at the substrate temperature of 20° C. under the pressure of 5 mTorr (665 mPa) while supplying a He gas, an oxygen gas and a SO 2  gas with respective flow rates of 60 SCCM, 20 SCCM and 10 SCCM and inducing plasma in the processing space by an RF power of 300 W. Thereby, a bias voltage of 100V is applied to the stage holding the substrate  21  by supplying thereto a high frequency power of 25 W. As a result, the BARC  25  is patterned as shown in  FIG. 5B  and a BARC pattern  25 A corresponding to the gate electrode pattern to be formed is formed on the hard mask film  24 .  
         [0039]     Further, in the step of  FIG. 5B , the resist pattern R 2  is subjected to trimming, and in the step of  FIG. 5C , the foregoing hard mask film  24  is patterned while using the resist pattern R 2  as a mask. Thereby, a hard mask pattern  24 A is formed as a result.  
         [0040]     Further, in the step of  FIG. 5C , the polysilicon film  23 G is patterned while using the hard mask pattern  24 A as a mask, and a desired polysilicon gate electrode pattern  23 G is formed.  
         [0041]     In the step of  FIG. 5C , the patterning of the hard mask  24  is conducted for example at the substrate temperature of 20° C. under the pressure of 5 mTorr (665 mPa) while supplying a CF 4  gas with a flow rate of 100 SCCM and inducing plasma with an RF power of 300 W. Thereby, etching is made by applying a bias voltage of 100V to the stage holding the substrate  21  by supplying a high-frequency power of 25 W thereto.  
         [0042]     Here, it should be noted that etching of the polysilicon film  25  is conducted in two successive etching steps of different conditions, the first being conducted at the substrate temperature of 60° C. under the pressure of 12 mTorr (about 1.6 Pa) while supplying a Cl 2  gas, an HBr gas, a CF 4  gas, and an oxygen gas with respective flow rates of 100 SCCM, 250 SCCM, 150 SCCM and 10 SCCM. Thereby, plasma is induced by an RF power of 500 W and etching is conducted by providing a high-frequency bias power of 34 W to the stage holding the substrate  21 . This first dry etching process may be continued for 21 seconds.  
         [0043]     On the other hand, the second etching step is conducted at the same substrate temperature of 60° C. under the pressure of 6 mTorr (about 0.8 Pa) while supplying a HBr gas and an oxygen gas with respective flow rates of 180 SCCM and 5 SCCM and inducing plasma by supplying an RF power of 350 W. Thereby, the stage holding the substrate  21  is supplied with a high-frequency bias power of 18 W, and the second etching step may be continued for 21 seconds.  
         [0044]     Because oxygen is added to the etching gas used for etching the polysilicon film  23 , the dry etching stops upon exposure of the gate insulation film  22  in the dry etching step of  FIG. 5C . On the other hand, in the state of  FIG. 5C  in which the gate insulation film  22  has just been exposed, there can be a case that a polysilicon residue  23 X remains on the gate insulation film  22  because of variation of the etching rate, or the like.  
         [0045]     Thus, in the present invention, overetching is conducted further in the step of  FIG. 5D  for removing such a residue  23 X completely, wherein the present embodiment changes the substrate temperature and the etching gas composition in such an overetching process that the polysilicon gate electrode pattern  23 G is not subjected to lateral etching.  
         [0046]     More specifically, the overetching process of  FIG. 5D  is conducted by lowering the substrate temperature from 60° C. of  FIG. 5C  to 20° C. and further by adding an SO 2  gas to the etching gas. Thus, an HBr gas, a He gas and an SO 2  gas are supplied with respective flow rates of 150 SCCM, 150 SCCM and 5 SCCM in the step of  FIG. 5D , and the overetching process is conducted under the pressure of 80 mTorr (about 10.7 Pa) for the duration of 40 seconds by inducing plasma with the RF power of 350 W and applying a high-frequency bias power of 65 W to the stage holding the substrate  21 .  
         [0047]     By conducting the overetching of  FIG. 5D  with such a low substrate temperature while adding SO 2  to the etching gas, the sidewall surface of the polysilicon gate electrode pattern  23 G is protected by a deposit primarily of sulfur (S), and the problem of irregular lateral etching of the sidewall surface of the gate electrode pattern explained with reference to  FIG. 3  or  4  is effectively avoided.  
         [0048]      FIG. 6  shows the cross-sectional structure of the n-type polysilicon gate electrode formed with the overetching process of  FIG. 5D .  
         [0049]     Referring to  FIG. 6 , it can be seen that there is caused no sidewall etching that may cause a change of gate length in the polysilicon gate electrode obtained with such a process.  
         [0050]     In the overetching process of  FIG. 5D  it is also possible to add an oxygen gas in addition to the SO 2  gas, which already contains oxygen.  
         [0051]     Because the etching gas used for the overetching process of  FIG. 5D  thus contains oxygen, etching selectivity is secured for the exposed gate insulation film  22 , and damaging of the gate insulation film  22  such as erosion is successfully avoided even in the case the gate insulation film has an extremely small thickness such as 2 nm or less in correspondence to the extremely reduced gate length of ultrafine semiconductor devices.  
         [0052]     In the overetching process of  FIG. 5D , it is also possible to use a film-forming sulfuric carbonyl gas or hydrogen sulfide gas together with an oxygen gas. Further, in the overetching step of  FIG. 5D , it is also possible to use an alkyl compound gas such as ethylene (C 2 H 4 ) in place of the SO 2  gas together with the oxygen gas. In this case, the sidewall surface of the polysilicon gate electrode pattern is protected by a deposit primarily formed of carbon (C).  
         [0053]     Further, it should be noted that the overetching step of  FIG. 5D  is effective not only for the polysilicon gate electrode pattern but also in the overetching of an amorphous silicon pattern for suppressing appearance of irregular cross-sectional structure.  
       Second Embodiment  
       [0054]      FIGS. 7A-7G  are diagrams showing the fabrication process of a CMOS device according to a second embodiment of the present invention.  
         [0055]     Referring to  FIG. 7A , a silicon substrate  41  is defined with a device region  42  of p-type well for an n-channel MOS transistor and a device region  43  of n-type well for a p-channel MOS transistor by an STI device isolation structure, and an SiON film  44  is formed commonly on the device regions  42  and  43  as a gate insulation film with a thickness of 1.5 nm. Further, a polysilicon film  45  constituting the gate electrode is formed on the SiON film  44  with a thickness of 120 nm.  
         [0056]     Next, in the step of  FIG. 7B , the part of the polysilicon film  45  located on the device region  43  of the p-channel MOS transistor is covered with a resist pattern  46 A, and ion implantation of phosphor (P) is conducted into the part of the polysilicon film  45  located on the device region  42  of the n-channel MOS transistor under the acceleration voltage of 10 keV with a dose of 8×10 15  cm −2 . Thereby, the foregoing part of the polysilicon film  45  is doped to n-type.  
         [0057]     Next, in the step of  FIG. 7C , the part of the foregoing polysilicon film  45  located on the device region  42  of the n-channel MOS transistor is covered wit a resist pattern  46 B, and Ge is injected thereto by an ion implantation first with the acceleration voltage of 20 keV with the dose of 1×10 15  cm −2 . With this, the polysilicon film  45  is converted to an amorphous film.  
         [0058]     Further, in the step of  FIGS. 7C , B (boron) is injected into the polysilicon film  45  thus converted to amorphous phase under the acceleration of 5 keV with the dose of 2×10 15  cm −2  to dope the polysilicon film  45  thus converted to amorphous phase to p-type.  
         [0059]     Next, in the step of  FIG. 7D , the resist pattern  46 B is removed and a TEOS oxide film  47  is deposited on the polysilicon film  45  by a CVD process at the substrate temperature of 620° C. with the thickness of 30 nm. Thereby, it is possible to activate the p-type or n-type impurity element introduced into the polysilicon film in the step of  FIG. 7B, 7C  or  7 D.  
         [0060]     Next, in the step of  FIG. 7E , the TEOS oxide film  47  is patterned in accordance with the desired shape of the gate electrodes of the p-channel and n-channel MOS transistors, and the polysilicon film  45  is patterned further while using the TEOS oxide film  47  thus patterned as a hard mask. Thereby, an n-type polysilicon gate electrode  45 A is formed in the device region  42  and the p-type polysilicon gate electrode  45 B is formed on the device region  43 .  
         [0061]     It should be noted that this step of forming the polysilicon gate electrodes  45 A and  45 B is conducted by using a recipe explained previously with reference to  FIG. 5C , and an overetching process explained with reference to  FIG. 5D  is applied thereafter.  
         [0062]     With the present invention, it becomes possible to effectively suppress the change of shape and size of the polysilicon gate electrodes  45 A and  45 B with the overetching in any of the n-type polysilicon gate electrode  45 A and the p-type polysilicon gate electrode  45 B, by conducting the overetching process at a lower substrate temperature and by admixing SO 2  to the etching gas.  
         [0063]     In the step of  FIG. 7E , In (indium) ions are injected obliquely into the device region  42  four times from four directions each time with the angle of 25° while using the polysilicon gate electrode  45 A as a self-alignment mask, and pocket injection region (not illustrated) is formed. Further, while using the polysilicon gate electrode  45 A again as a self-alignment mask, As (arsenic) ions are injected into the device region  42  to form n-type source/drain extension regions  61  at both lateral sides of the n-type polysilicon gate electrode  45 A.  
         [0064]     Further, in the step of  FIG. 7E , As ions are injected obliquely into the device region  43  four times from four directions each time with the angle of 25° while using the polysilicon gate electrode  45 B as a self-alignment mask, and pocket injection region (not illustrated) is formed. Further, while using the polysilicon gate electrode  45 B again as a self-alignment mask, B (boron) ions are injected into the device region  43  to form p-type source/drain extension regions  62  at both lateral sides of the p-type polysilicon gate electrode  45 B.  
         [0065]     Further, in the step of  FIG. 7F , sidewall insulation films  48  are formed on the polysilicon gate electrodes  45 A and  45 B, and P (phosphorus) ions are injected to the device region  42  while using the polysilicon gate electrode  45 A and sidewall film  48  as a self-aligned mask. With this, source/drain diffusion regions  63  of the n-channel MOS transistor are formed in a partially overlapping relationship with the source/drain extension regions  61 . Further, B ions are injected to the device region  43  while using the polysilicon gate electrode  45 B and sidewall film as a self-aligned mask. With this, source/drain diffusion regions  64  of the p-channel MOS transistor are formed in a partially overlapping relationship with the source/drain extension regions  62 .  
         [0066]     Further, in the step of  FIG. 7G , CoSi 2  layers  49  are formed on the polysilicon gate electrodes  45 A and  45 B and on the exposed surfaces of source/drain diffusion regions  63  and  64 .  
         [0067]     With the CMOS device fabricated according to such a process, there occurs no erosion at the sidewall surfaces of the polysilicon gate electrode patterns  45 A and  45 B even when the overetching is applied in the step of  FIG. 7E , and the semiconductor device shows stable operational characteristics even when the gate length is reduced to less than 100 nm, such as 50 nm or 40 nm.  
       Third Embodiment  
       [0068]     It should be noted that the dry etching process of the present invention is effective not only for patterning a polysilicon film to form a gate electrode but also for formation of an STI structure in a silicon substrate formed of a single crystal silicon.  
         [0069]      FIGS. 8A-8D  show the method of forming a device isolation trench in a silicon substrate  81  conducted in an ICP plasma etching apparatus according to a third embodiment of the present invention.  
         [0070]     Referring to  FIG. 8A , there is formed an SiN film  83  on a silicon substrate  81  with a thickness of about 110 nm via an intervening thermal oxide film  82  having a thickness of about 10 nm, and an opening  83 A is formed in a part of the SiN film  83  in correspondence to where the desired device isolation trench is to be formed.  
         [0071]     In the present embodiment, the silicon substrate  81  of the state of  FIG. 8A  is held in the ICP plasma etching apparatus (not illustrated) at a substrate temperature of 60° C., and the thermal oxide film  82  is removed with regard to the silicon substrate  81  at the foregoing opening by a dry etching process conducted at the substrate temperature of 60° C. under the pressure of 5 mTorr (665 mPa) while supplying a CF 4  gas with the flow rate of 100 SCCM and inducing plasma with an RF power of 200 W. Further, a high-frequency bias of 400 volt (peak volt) is applied to the stage holding the substrate, and the dry etching process is conducted for 10 seconds.  
         [0072]     Next, in the step of  FIG. 8B , the silicon substrate  81  of  FIG. 8A  is held in the same ICP plasma etching apparatus at the substrate temperature of 60° C., and the silicon substrate  81  are removed by a dry etching process over the duration of 30 seconds while using the SiN film  83  as a mask, by supplying a HBr gas and an oxygen gas with respective flow rates of 450 SCCM and 13 SCCM and inducing plasma by an RF power of 900 W while applying a high-frequency bias having a peak voltage of 220V. With this, there is formed a device isolation trench  81 A in the silicon substrate  81  in correspondence to the openings  81 .  
         [0073]     After formation of the device isolation trench  81 A in the dry etching process of  FIG. 8B , the dry etching process is continued in the step of  FIG. 8C  with the present embodiment but with a modified dry etching condition.  
         [0074]     In more detail, the substrate temperature is reduced to 40° C. in the same ICP plasma etching apparatus in the step of  FIG. 8C , and the plasma etching is continued under the pressure of 10 mTorr (1.3 Pa) while supplying a HBr gas, an oxygen gas and a SO 2  gas with respective flow rates of 450 SCCM, 7 SCCM and 6 SCCM. Further, plasma is induced by an RF power of 900 W and a high-frequency bias having a peak voltage of 250V is applied to the stage holding the substrate. In this state, the dry etching is continued for about 15 seconds.  
         [0075]     With this, more deposits are formed on the sidewall surface of the device isolation trench  81 A, which increases the depth thereof with the progress of etching, as compared with the case of the step of  FIG. 8B , and as a result, there is formed a tapered part of shallower angle at the bottom of the device isolation trench  81 A. In  FIG. 8B , this tapered part is not shown clearly.  
         [0076]     In the step of  FIG. 8C , the substrate temperature is lowered further to 20° C., and dry etching is continued under the pressure of 10 mTorr (1.3 Pa) while supplying a HBr gas, an oxygen gas and a SO 2  gas with respective flow rates of 450 SCCM, 7 SCCM and 6 SCCM and inducing plasma with an RF power of 900 W. Thereby, a high-frequency bias having a peak voltage of 250V is provided and the dry etching is continued for 15 seconds. With this, a tapered part characterized by further smaller tapered angle is formed at the bottom of the device isolation trench  81 A.  
         [0077]     The device isolation trench  81 A thus formed may have a width of 140 nm corresponding to the design rule and a depth of about 300 nm.  
         [0078]     Further, in the step of  FIG. 8D , the SiN film  83  and the thermal oxide film  82  are removed and a thermal oxidation processing is applied to form a thermal oxide film  84   a  on the surface of the device isolation trench  81 A. And, by filling the device isolation trench  81 A thus covered with the thermal oxide film  84   a  by a CVD oxide film  84 , the desired STI structure is completed.  
         [0079]     It should be noted that the STI structure formed according to such a process may be used for the device isolation structure of the CMOS device explained in the previous embodiment.  
         [0080]     With the STI device isolation structure of such a construction, filling of the trench  81 A with the CVD oxide film  84  is made easily in view of the shallow tapered angle at the bottom part of the device isolation trench  81 A, and fabrication of the semiconductor device is made easily. Further, withstand voltage at the bottom part of the device isolation trench  81 A is improved, while this results in improvement of device isolation characteristics.  
         [0081]     While the process of  FIGS. 8A-8D  is particularly effective for forming a device isolation trench in an n-type well such as the device region  43  of  FIG. 7A , the process of  FIGS. 8A-8D  is useful also at the time of forming the device isolation trenches in the n-type well (device region  43  of  FIG. 7A ) and in the p-type well (device region  42  of  FIG. 7A ) simultaneously.  
         [0082]     Further, it is also possible to form a DRAM by forming a trench in a silicon substrate by a process similar to that of  FIGS. 8A-8D  and by forming a capacitor in such a trench. In this case, leakage of electric charges at the bottom part of the trench capacitor is reduced because of the round shape of the trench bottom surface. Thereby, use of long refreshing time becomes possible.  
         [0083]     Thus, the dry etching process of the present invention is useful not only in the formation of STI structure but also in the fabrication of DRAMs.  
         [0084]     In the description heretofore, the use of the ICP plasma etching apparatus has been assumed. However, the present invention is by no means limited to such a particular plasma etching apparatus but it is also possible to use other generally used plasma etching apparatuses including parallel plate type apparatus.  
         [0085]     Further, the present invention is not limited to a particular embodiment but various variations and modifications may be made without departing from the scope of the invention.

Technology Classification (CPC): 7