Patent Abstract:
Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.

Full Description:
TECHNICAL FIELD 
       [0001]    This invention is directed toward the use of error correcting code within memory systems, and, more particularly, one or more embodiments of this invention relates to decreasing the logic delay associated with calculating and comparing an error correcting code in command, address and data signals coupled between components in memory systems. 
       BACKGROUND OF THE INVENTION 
       [0002]    In memory devices, such as dynamic random access memory (DRAM), as data channel frequencies increase, maintaining signal integrity becomes more important. Thus, error correcting codes (ECCs), such as cyclical redundancy check (CRC), have been proposed for use in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. 
         [0003]    In a memory device, ECCs may be transmitted between a memory controller and the memory device along with command, address and data signals. The signals may be serialized into a packet and transferred along a channel. In a write command, once a packet is received by the memory device, an ECC value is calculated and compared with a known ECC value that was transmitted in the packet. If the values are the same, the command, address, and write data signals are validated and access is provided to a memory array in the memory device. Conversely, if the calculated ECC value is different from the known ECC value, then the command signal in the packet is suppressed and the write data is not sent to the memory array. 
         [0004]      FIG. 1  shows a block diagram of a logic path  100  for calculating and comparing an ECC value in a high frequency memory device in accordance with the prior art. The logic path  100  for calculating the ECC value includes two static logic gates  102  and  106  that are clocked by respective flip flops  104  and  108 . More particularly, a packet is captured by a latch  122  responsive to an input capture clock. The command signals for the write command are sent to a command decoder  110 . In addition, the command signals, address signals and write data signals are sent to a set of first static logic gates (SL 1 )  102 . For example, if 16 bits are captured, 4 command bits would be sent to the command decoder and all 16 bits would be sent to the SL 1   102 . The SL 1   102  completes a first part of the ECC calculation by generating a partial sum of the terms. The partial sum of the terms is output from the SL 1   102 , and latched into a first flip flop  104 . The partial sum is output from the first flip flop  104  and provided to a second set of static logic gates (SL 2 )  106 . The remainder of the ECC calculation is completed in the SL 2   106 . Moreover, the calculated ECC is compared with the transmitted ECC in the SL 2   106 . When the calculated ECC value matches the transmitted ECC value, the SL 2   106  generates an ECC valid signal. From the SL 2   106 , the ECC valid signal is latched into a second flip flop  108  before being provided to an ECC valid logic gate  120 . 
         [0005]    In parallel, a command decoder  110  decodes the command signals in the packet. The decoded command signals are clocked by a first and second flip flop  114  and  118 , respectively, so that the decoded command signal can be provided to the ECC valid logic gate  120  at the same time the ECC valid signal is provided to the ECC valid logic gate  120 . Thus, the decoded command signals are clocked out of the second flip flop  118  at about the same time as the ECC valid signal is clocked out of the second flip flop  108 . The ECC valid logic gate  120  validates the command and provides access to the memory array (not shown) when the calculated ECC value is the same as the transmitted ECC value. Conversely, the ECC valid logic gate  120  suppresses the command, when the calculated ECC value is different from the transmitted ECC value. 
         [0006]    A timing diagram showing the delay for the logic path  100  of  FIG. 1  is shown in  FIG. 2 . In  FIG. 2 , at time T 0  the signals on the packet that are applied to input terminals become valid. At time T 1  and in response to a rising edge of the clock signal, the signals are captured and provided to the SL 1   102  ( FIG. 1 ). The partial sum of terms is output from the SL 1   102  at time T 2 , which is some time period greater than a half period of the clock signal shown at the top of  FIG. 2 . At time T 3  and in response to a rising edge of the clock signal, the partial sum of terms is clocked into the first flip flop  104  and provided to the SL 2   106 . The ECC valid signal is output from SL 2   106  at time T 4  and provided to the second flip flop  108 , which, again, requires a time period greater than a half period of the clock signal for the SL 2   106  to output the ECC valid signal. At time T 5  and in response to a rising edge of the clock signal, the ECC valid signal is clocked into the second flip flop  108 , and the decoded command signal is clocked out of the second flip flop  118 . At time T 6  the decoded command signal and ECC valid signal are provided to the ECC valid logic gate  120 . The ECC valid logic gate  120  generates an array command signal at time T 7 . The array command signal provides access to the memory array. 
         [0007]    It can be seen from  FIG. 2  that it requires two clock periods (i.e., T 1 -T 5 ) after the packet is applied to the memory device to validate the command signals in the packet. The signals from the SL 1   102  cannot be clocked into the first flip flop  104  by the falling edge of the clock signal after T 1  because the SL 1   102  requires more than one half period to complete its calculation. For the same reason, the signals from the SL 2   106  cannot be clocked into the second flip flop  108  by the falling edge of the clock signal following T 3 . Yet considerable time is wasted after the SL 1   102  and SL 2   106  complete their calculations, and the signals from the SL 1   102  and the SL 2   106  are clocked into the flip flops  104  and  108 , respectively, at time T 3  and T 5 , respectively. 
         [0008]    For high frequency clock speeds, the prior art method shown in  FIG. 1  for calculating ECC calculations has delay characteristics greater than one internal memory device clock cycle. When the ECC delay exceeds one clock period, a second clock period delay must be added to the delay to align the ECC calculation with the command signals to validate the command before accessing the memory array. Therefore, when the ECC logic delay is greater than one clock cycle but much less than two clock cycles, an entire second clock period delay is added. 
         [0009]    One solution in the prior art for minimizing the delay associated with calculating and comparing the ECCs values has been to slow down the frequency of the internal memory clock cycle. By slowing down the clock frequency, the calculation and comparison of the ECC can be done in less time. In particular, the SL 1   102  can complete its calculation by the falling edge following the rising edge that clocks the signals into the latch  122 . Similarly, the SL 2   106  can complete its calculation by the falling edge following the rising edge that clocks the signals into the first flip flop  104 . As a result, the calculation and comparison can be done in one clock cycle, rather than having to extend it into two clock cycles. This is not a desirable solution, however, as it reduces the bandwidth of the memory device. 
         [0010]    Therefore, there is a need for decreasing the logic delay associated with calculating and comparing ECCs without reducing the clock frequency. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a block diagram of a logic path for calculating an error code in accordance with prior art. 
           [0012]      FIG. 2  is a timing diagram representative of the time to calculate error code value in accordance with prior art. 
           [0013]      FIG. 3  is a block diagram of a logic path for calculating an error code according to one embodiment of the invention. 
           [0014]      FIG. 4  is a more detailed block diagram of the logic path of  FIG. 3  according to one embodiment of the invention. 
           [0015]      FIG. 5  is a timing diagram representative of the time to calculate error code value in accordance with one embodiment of the invention. 
           [0016]      FIG. 6  is a block diagram of the logic path for calculating an error code according to one embodiment of the invention. 
           [0017]      FIG. 7  is a timing diagram representative of the time to calculate error code value in accordance with one embodiment of the invention. 
           [0018]      FIG. 8  is a block diagram of a memory device using a logic path for calculating an error code according to one embodiment of the invention. 
           [0019]      FIG. 9  is a block diagram of an embodiment of a processor based system using the memory device of  FIG. 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Embodiments of the present invention are directed toward, for example, providing a method of reducing the logic delay associated with calculating ECCs. Certain details are set forth below to provide a sufficient understanding of the embodiments of the invention. However, it will be clear to one skilled in the art that various embodiments of the invention may be practiced without these particular details. 
         [0021]      FIG. 3  shows a block diagram of a logic path  130  for calculating an error code according to one embodiment of the invention. In a write command, the logic path  130  captures a packet and distributes the incoming signals to a command decoder  110  and a set of static logic gates  132  in the same manner in  FIG. 3  as in  FIG. 1 . Therefore, in the interest of brevity, an explanation of the process will not be repeated. The set of static logic gates  132  are similar to the first set of static logic gates  102  in  FIG. 1  in that the set of logic gates  132  calculates a partial sum of terms. The logic path  130  of  FIG. 3  differs from the logic path  100  of  FIG. 1  by completing the ECC calculation and comparing the calculated ECC value with the transmitted ECC value in a set of dynamic logic gates  134 . As in the prior art of  FIG. 1 , if the calculated ECC value is valid, a valid signal is sent from the dynamic logic gates  134  to the ECC valid logic gate  120 . The ECC valid logic gate  120  validates the command before providing it to the memory array (not shown). As previously stated, the ECC valid logic  120  suppresses the decoded command if the calculated ECC value does not match the transmitted ECC value or generates an array command and thus, provides access to the memory array if the calculated ECC value does match the transmitted ECC value. 
         [0022]      FIG. 4  is a detailed block diagram of the logic path  130  in  FIG. 3 . A first input  121  receives the command, address, and data bits from a packet transmitted across a channel. The command, address, and data bits are clocked by latch  122  and provided to the set static logic exclusive-OR (XOR) gates  132 , which calculates a partial sum of the terms of the calculated ECC. The partial sum of the terms is then provided to the dynamic logic  134 . In particular, the partial sum of the terms is first provided to a set of static to dynamic circuits (S2Ds)  136   a . In addition, S2D  136   b  is provided to align an output CLKD to the outputs from the S2D  136   a . The S2Ds  136   a  convert the partial sum of the terms into monotonically rising output signals, which allows functional completeness for downstream logic. Monotonic signals travel in one direction during each evaluation cycle, for example from low to high. The output signals Q and Qb are complementary so that one of them may transition high each clock cycle. When the Q signal is high, the first set of dynamic XOR gates  138  and a second set of dynamic XOR gates  140  are enabled. When the dynamic XOR gates  138  and  140  are enabled, the remaining ECC calculation and comparison is completed without regard to a clock cycle. More particularly, the logic in the two sets of dynamic XOR gates  138  and  140  is completed as the signals are received in the respective gates, rather than relative to a clock cycle. Therefore, the time it takes to calculate the remaining part of the ECC value and compare the calculated ECC value with the transmitted ECC value is determined by the dynamic logic delay rather than by clock period. This dynamic logic delay is less than a clock cycle and thus is completed faster than the delay associated with the prior art. 
         [0023]    In parallel with the above, input  123  receives the transmitted ECC value from the packet and is clocked by flip flop  142 . The transmitted ECC value is provided to an S2D circuit  146 . The transmitted ECC value is further provided to the second set of dynamic XOR gates  140 . As stated above, the calculated ECC value in the first set of dynamic XOR gates  138  is provided to the second set of dynamic XOR gates  140 . In the second set of dynamic XOR gates  140 , the calculated ECC value is compared with the transmitted ECC value. If the calculated ECC value matches the transmitted ECC value, an ECC valid command is provided to ECC valid logic  120 . There is no delay associated with aligning the decoded command signals with the ECC valid signal as they are provided to the ECC valid logic  120 . Rather, the decoded command signals may be provided to the ECC valid logic  120  at a different time than the ECC valid signal. 
         [0024]    The logic path of  FIGS. 3 and 4  calculates and compares the ECC value in less time than it takes in the prior art logic path shown in  FIG. 1 . A timing diagram in accordance with the logic path in  FIG. 4  is shown in  FIG. 5 . The timing events T 0 -T 2  in the timing diagram of  FIG. 5  represents the same timing events T 0 -T 2  of  FIG. 2 , and therefore, will not be repeated in the interest of brevity. At time T 3 , however, the terms of the partial sum are clocked into the set of dynamic logic gates  134  and provided to a plurality of S2D circuits  136   a . As stated above, the dynamic logic gates  134  calculate the remaining part of the ECC value and compare the calculated ECC value with the transmitted ECC value. At time T 4  the decoded command signal is provided to the ECC valid logic  120 . At time T 5  and in response to a rising edge of S2D  136   b  clkD, the monotonic signals are clocked out of the S2Ds  136   a . At time T 6  and when the calculated ECC value matches the transmitted ECC value, an ECC valid signal is provided to ECC valid logic  120 . The ECC valid signal may be provided to ECC valid logic  120  at a different time than the decoded command signal is provided to ECC valid logic  120 . Finally, at time T 7  ECC valid logic  120  generates and provides an array command signal to the memory array. The array command signal is generated and provided to the memory array in less time than it takes in the prior art timing diagram of  FIG. 2 . 
         [0025]    Although  FIGS. 3 and 4  show a write command, the logic path  130  is also applicable to a read command issued by a memory controller. In a read command, the logic path  130  would verify the read command and read address on the memory device before providing access to the memory array. Furthermore, the logic path  130  is also applicable to a read packet received by a memory controller from a memory device. Once the read packet was received by the memory controller, the logic path  130  on the memory controller verifies the read data transmitted from the memory device to the memory controller. 
         [0026]    In another embodiment of the invention, an alternative logic path may be used.  FIG. 6  shows the logic path of  FIG. 1 , but further includes a delay circuit between the first and second clock cycle of the internal memory clock. More particularly, the logic path  160  includes two static logic gates that are clocked by respective flip flops  104  and  108 . The first flip flop  104  is clocked by a first internal clock, similar to the internal clock of  FIG. 1 . The second flip flop  108  is clocked by a delayed internal clock. The delay circuit  124  used to delay the internal clock may be any type of delay circuit. The minimum amount of delay that may be applied to the delay circuit  124  is likely greater than the time it takes the ECC valid signal to be output the second set of static logic gates  106 . Conversely, the maximum amount of delay that may be applied to the delay circuit  124  is likely less than the time marker for when the ECC valid signal is clocked into valid logic. Therefore, the amount of delay will not be longer than one clock period; however, the delay may be close to one clock period. 
         [0027]    A timing diagram for the logic path of  FIG. 6  in accordance with one embodiment is shown in  FIG. 7 .  FIG. 7  shows two clock signals, clock signal A and delayed clock signal B, where delayed clock signal B lags clock signal A by about 70%. Although  FIG. 7  shows a delay of 70%, other delay amounts may be used. Clock signal A represents a clock signal similar to the clock signal in  FIG. 2 . Furthermore time markers T 0 -T 4  are in response to clock signal A and represent the same timing events as in  FIG. 2 . Therefore, time markers T 0 -T 4  will not be repeated for the sake of brevity. Time marker T 5 , however, is in response to clock signal B. In particular, at time T 5  and in response to the rising edge of clock signal B, the ECC valid signal is clocked out of the second flip flop  108 . At time T 6  a decoded command signal and ECC valid signal are provided to ECC valid logic  120 . The ECC valid logic  120  generates array command signal, which provides access to the memory array. Therefore, the time it takes to calculate and compare the ECC value is much less with the delay circuit  124  than without a delay circuit. 
         [0028]      FIG. 8  shows a memory device  700  according to one embodiment of the invention. The memory device  700  is a dynamic random access (“DRAM”), although the principles described herein are applicable to DRAM cells, Flash or some other memory device that receives memory commands. The memory device  700  includes a command decoder  720  that generates sets of control signals corresponding to respective commands to perform operations in memory device  700 , such as writing data to or reading data from the memory device. The memory device  700  further includes an address circuit  730  that selects the corresponding row and column in the array. Both the command signals and address signals are typically provided by an external circuit such as a memory controller (not shown). The memory device  700  further includes an array  710  of memory cells arranged in rows and columns. The array  710  may be accessed on a row-by-row, page-by-page or bank-by-bank basis as will be appreciated by one skilled in the art. The command decoder  720  provides the decoded commands to the array  710 , and the address circuit  730  provides the row and column address to the array  710 . Data is provided to and from the memory device  700  via a data path. The data path is a bidirectional data bus. During a write operation write data are transferred from a data bus terminal DQ to the array  710  and during a read operation read data are transferred from the array to the data bus terminal DQ. 
         [0029]      FIG. 9  is a block diagram of an embodiment of a processor-based system  600  including processor circuitry  602 , which includes the memory device  500  of  FIG. 6  or a memory device according to some other embodiment of the invention. Conventionally, the processor circuitry  602  is coupled through address, data, and control buses to the memory device  500  to provide for writing data to and reading data from the memory device  500 . The processor circuitry  602  includes circuitry for performing various processing functions, such as executing specific software to perform specific calculations or tasks. In addition, the processor-based system  600  includes one or more input devices  604 , such as a keyboard or a mouse, coupled to the processor circuitry  602  to allow an operator to interface with the processor-based system  600 . Typically, the processor-based system  600  also includes one or more output devices  606  coupled to the processor circuitry  602 , such as output devices typically including a printer and a video terminal. One or more data storage devices  608  are also typically coupled to the processor circuitry  602  to store data or retrieve data from external storage media (not shown). Examples of typical storage devices  608  include hard and floppy disks, tape cassettes, compact disk read-only (“CD-ROMs”) and compact disk read-write (“CD-RW”) memories, and digital video disks (“DVDs”). 
         [0030]    Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.

Technology Classification (CPC): 7