Patent Abstract:
A method for fabricating an SOI semiconductor device with reduced floating body effects and a simplified method of fabrication. In the invention, a N-type doped dielectric layer or P-type doped dielectric layer is used to be driven into the semiconductor layer to form source/drain regions of field effect transistors of CMOS and conductive regions. For fabricating a NMOS transistor and a PMOS transistor of the CMOS device, the invention provides a method which an ion implantation process and a photo mask are omitted, by which the method will decrease the complexity of the fabrication process and the cost thereof.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a method for fabricating semiconductor device, and more particularly, to a method for fabricating an SOI semiconductor device. 
     2. Description of Related Art 
     A related art SOI device is disclosed in U.S. Pat. No. 6,110,769 issued to Jeong Hwan Son, titled “SOI (SILICON ON INSULATOR) DEVICE AND METHOD FOR FABRICATING THE SAME”, which is shown in FIGS.  1 A and  1 B- 1 H. Refer to FIG. 1A, which is a cross-sectional view showing a structure of a conventional SOI device. 
     A buried oxide film  25  is formed on a semiconductor substrate  24 . P and N-type heavily doped polysilicon layers  23   a  and  23   b  are formed on the buried oxide film  25  and isolated from each other by an isolation oxide film  26  formed on the buried oxide film  25 . Buried oxide films  22   a  are formed in the p and N-type heavily doped polysilicon layers  23   a  and  23   b  to be spaced apart. 
     A P-type semiconductor layer  20   b  and a first active region are formed on the first buried oxide film  22   a,  spaced apart from the P-type heavily doped polysilicon layer  23   a.  A first oxide film  21  is formed between the P-type semiconductor layer  20   b  and the first active region. 
     An N-type semiconductor layer  20   c  and a second active region are formed on the first buried oxide film  22   a,  spaced apart from the N-type heavily doped. A first oxide film  21  is formed between the N-type semiconductor layer  20   c  and the second active region. 
     A gate oxide film  29  and a first gate electrode  30   a  are successively formed on the first active region on the P-type heavily doped polysilicon layer  23   a.  Source/drain regions  34   a / 34   b  are formed in the first active region at both sides of the first gate electrode  30   a.    
     A gate oxide film  29  and a second gate electrode  30   b  are successively formed on the second active region on the N-type heavily doped polysilicon layer  23   b.  Source/drain region  32   a / 32   b  are formed in the second active region at both sides of the second gate electrode  30   b.    
     Formed is an interlayer insulating film  35  having contact holes on the p and N-type semiconductor layers  20   b  and  20   c  and the source/drain regions  32   a / 32   b  and  34   a / 34   b.  Contact pads  36   a  and  36   f  and line layers  36   b,    36   c,    36   d,  and  36   e  are formed in the contact holes and on the interlayer insulating layer adjoining to the contact holes. 
     The first and second active regions are connected to the p and N-type semiconductor layers  20   b  and  20   c  through the p and N-type polysilicon layers  23   a  and  23   b,  respectively. 
     Refer to FIGS. 1B-1H, are cross-sectional views showing conventional process steps of a method for fabricating the SOI device as shown in FIG. 1A First refer to FIG. 1B, a first semiconductor substrate  20  is provided. The first substrate  20  is etched to form a plurality of trenches. An oxide film is deposited on the substrate  20  and the trenches. Subsequently, a CMP process is performed to form a first oxide film  21  filling the trenches. 
     Next, a first buried oxide film  22  is formed on the first semiconductor substrate  20  by CVD. 
     A photoresist film is formed on the first buried oxide film  22  and patterned to expose areas of the first buried oxide film  22 . Using the patterned photoresist as a mask, the first buried oxide film  22  is removed to expose the first substrate  20 . Next an undoped polysilicon layer is deposited on the first buried oxide film  22  and the first substrate  20 . The undoped polysilicon layer is then etched-back forming a thick undoped polysilicon layer  23 . 
     A second semiconductor substrate  24  is provided and a second buried oxide film  25  is deposited on the second substrate  24 . Subsequently, the second buried oxide film  25  on the second substrate  24  and the undoped polysilicon layer  23  on the first substrate  20  are bonded together by undergoing a high temperature process 
     Refer to FIG.  1 C. The first substrate  20  is polished until the first oxide film  21  using the first oxide film  21  as an etch stop. In order to form a trench isolation region, the semiconductor layer  20   a  between the first oxide film  21 , the first buried oxide film  22 , and the undoped polysilicon layer  23  are etched. An oxide film is deposited on the first oxide film  21 , the semiconductor layer  20   a,  and the trench isolation region and then planarizing the oxide film to form an isolation oxide film  26 . 
     Next, a photoresist film  27  covers the first oxide film  21 , the semiconductor layer  20   a  and the isolation oxide film  26 . The photoresist film  27  is patterned and removed to expose part of the isolation oxide film  26 . Using the patterned photoresist film  27  as a mask, the undoped polysilicon layer  23  is injected with boron ions to create a P-type heavily doped polysilicon layer  23   a.    
     Refer to FIG.  1 D. Subsequently, another photoresist film  28  covers the first oxide film  21 , the semiconductor layer  20   a  and the isolation oxide film  26  and patterned. The photoresist film  28  is then removed to expose part of the isolation oxide film that was covered by the photoresist film  27  in the previous step. Using the patterned photoresist film  28  as a mask, the undoped polysilicon layer  23   a  is injected with phosphorus ions to become an N-type heavily doped polysilicon layer  23   b.    
     Refer to FIG.  1 E. An oxide film and a silicon layer are deposited and etched. The result is a gate oxide film  29  and a first gate electrode  30   a  for an NMOS transistor and a gate oxide film  29  and a second gate electrode  30   b  for a PMOS transistor formed on the semiconductor layer  20   a.    
     Refer to FIG. 1F. A photoresist film  31  is formed and patterned to expose the semiconductor layer  20   a  on both sides of the second gate electrode  30   b  and where the first gate electrode  30   a  is not formed. Using the patterned photoresist film  31  as a mask, the P-type semiconductor layer  20   b  is injected with P-type boron ions to form lightly doped source/drain regions  32   a  and  32   b.    
     Refer to FIG. 1G. A photoresist film  33  is formed and patterned to expose the semiconductor layer  20   a  on both sides of the first gate electrode  30   a  and where the second gate electrode  30   b  is not formed. Using the patterned photoresist film  33  as a mask, the N-type semiconductor layer  20   c  is injected with N-type As ions to form lightly doped source/drain regions  34   a  and  34   b.    
     Refer to FIG.  1 H. Depositing and removing an insulating film  35  to expose areas of the P-type semiconductor layer  20   b,  the N-type semiconductor layer  20   c,  the P-type source/drain regions  32   a  and  32   b  and the N-type source/drain regions  34   a  and  34   b  and form contact holes. A conductive layer is formed to fill the contact holes. The conductive layer is etched to form contact pads  36   a  and  36   f  on the P-type and N-type semiconductor layers  20   b  and  20   c  and line layers  36   b,    36   c,    36   d,    36   e  on the n and p source/drain regions  32   a / 32   b  and  34   a / 34   b.    
     The conventional method for fabricating an SOI semiconductor device as described above comprises implanting P-type ions to form regions  20   b,    32   a,  and  32   b.  Additionally, the conventional method requires implanting N-type ions to form regions  20   c,    34   a,  and  34   b.  Since photoresist films are used as ion-implantation masks, two lithography mask steps and two ion implantation steps need to be performed, which increases the complexity of the fabrication process and the cost thereof. 
     SUMMARY OF THE INVENTION 
     In accordance with the foregoing and other objectives of the present invention, the invention provides a method for fabricating a SOI semiconductor device, which overcomes the drawbacks of the conventional SOI device. 
     A first semiconductor substrate is etched to form a plurality of trenches. An oxide film is deposited on the substrate and the trenches. A first oxide film is deposited which fills the trenches. A first buried oxide film is formed on the first semiconductor substrate. A photoresist film is formed on the first buried oxide film and patterned to expose areas of the first buried oxide film. Using the patterned photoresist as a mask, the first buried oxide film is removed to expose the first substrate. Next an undoped polysilicon layer is deposited on the first buried oxide film and the first substrate. The undoped polysilicon layer is then etched-back. 
     A second buried oxide film is deposited on a second substrate. The second buried oxide film on the second substrate and the undoped polysilicon layer on the first substrate are bonded together by undergoing a high temperature process. 
     The first substrate is polished until the first oxide film is exposed using the first oxide film as an etch stop. In order to form a trench isolation region, the semiconductor layer between the first oxide film, the first buried oxide film, and the undoped polysilicon layer are etched. An oxide film is deposited on the first oxide film, the semiconductor layer, and the trench isolation region and then planarizing the oxide film to form an isolation oxide film. 
     Next, a photoresist film covers the first oxide film, the semiconductor layer and the isolation oxide film. The photoresist film is patterned and removed to expose part of the isolation oxide film. Using the patterned photoresist film as a mask, the undoped polysilicon layer is injected with, for example, boron ions to create a P-type heavily doped polysilicon layer. 
     Subsequently, another photoresist film covers the first oxide film, the semiconductor layer and the isolation oxide film and patterned. The photoresist film is then removed to expose part of the isolation oxide film that was covered by the photoresist film in the previous step. Using the patterned photoresist film as a mask, the undoped polysilicon layer is injected with, for example, phosphorus ions to become an N-type heavily doped polysilicon layer. 
     An oxide film and a silicon layer are deposited and etched. The result is a gate oxide film and a first gate electrode for an NMOS transistor and a gate oxide film and a second gate electrode for a PMOS transistor, formed on the semiconductor layer. A doped dielectric layer, for example, n-doped PSG, is formed over the surface by, for example, CVD. 
     A photoresist film is formed and patterned over the dielectric layer. An area of the doped dielectric layer is removed to expose the semiconductor layer on both sides of the second gate electrode and where the first gate electrode is not formed. Using the patterned photoresist film as a mask, the P-type semiconductor layer is injected with P-type boron ions to form lightly doped source/drain regions. The photoresist film is then removed. 
     Next, the n-dopant inside the doped dielectric layer is driven into the N-type semiconductor layer to form lightly doped source/drain regions. 
     Depositing and removing an insulating film to expose areas of the P-type semiconductor layer, the N-type semiconductor layer, the P-type source/drain regions and the N-type source/drain regions and form contact holes. A conductive layer is formed to fill the contact holes. The conductive layer is etched to form contact pads on the P-type and N-type semiconductor layers and line layers on the n and p source/drain regions. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIG. 1A, which is a cross-sectional view showing a structure of a conventional SOI device. 
     FIGS. 1B-1H are cross-sectional views showing conventional process steps of a method for fabricating the SOI device as shown in FIG. 1A; 
     FIGS. 2A-2L are cross-sectional views showing process steps of a method for fabricating the SOI device according to a preferred embodiment of the present invention; and 
     FIGS. 3I-3L are cross-sectional views showing an SOI device according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Refer to FIGS. 2A-2L, which are cross-sectional views showing process steps of a method for fabricating the SOI device according to a preferred embodiment of the present invention. 
     A first semiconductor substrate  220  is etched to form trenches. A first oxide film  221  is deposited which fills the trenches. 
     Refer to FIG. 2B, a first buried oxide film  222  is formed on the first semiconductor substrate  220 . 
     Refer to FIG. 2C, a photoresist film is formed on the first buried oxide film  222  and patterned to expose areas of the first buried oxide film  222 . Using the patterned photoresist as a mask, the first buried oxide film  222  is removed to expose the first substrate  220 . Next an undoped polysilicon layer is deposited on the first buried oxide film  222  and the first substrate  220 . The undoped polysilicon layer is then etched-back to form an undoped polysilicon layer  223 . 
     A second buried oxide film  225  is deposited on a second substrate  224 . 
     Refer to FIG.  2 D,the second buried oxide film  225  on the second substrate  224  and the undoped polysilicon layer  223  on the first substrate  220  are bonded together by undergoing a high temperature process. 
     Refer to FIG. 2E, the first substrate  220  is polished until the first oxide film  221  is exposed using the first oxide film  221  as an etch stop. In order to form a trench isolation region, the semiconductor layer  220   a  between the first oxide film  221 , the first buried oxide film  222 , and the undoped polysilicon layer  223  are etched. An oxide film is deposited on the first oxide film  221 , the semiconductor layer  220   a,  and the trench isolation region and then planarizing the oxide film to form an isolation oxide film  226 . 
     Refer to FIG. 2F, a photoresist film  227  covers the first oxide film  221 , the semiconductor layer  220   a  and the isolation oxide film  226 . The photoresist film  227  is patterned and removed to expose part of the isolation oxide film  226 . Using the patterned photoresist film  227  as a mask, the undoped polysilicon layer  223  is injected with boron ions to create a P-type heavily doped polysilicon layer  223   a.    
     Refer to FIG. 2G, another photoresist film  228  covers the first oxide film  221 , the semiconductor layer  220   a  and the isolation oxide film  226  and patterned. The photoresist film  228  is then removed to expose part of the isolation oxide film that was covered by the photoresist film  227  in the previous step. Using the patterned photoresist film  228  as a mask, the undoped polysilicon layer  223   a  is injected with phosphorus ions to become an N-type heavily doped polysilicon layer  223   b.    
     Refer to FIG. 2H, an oxide film and a silicon layer are deposited and etched. The result is a gate oxide film  229  and a first gate electrode  230   a  for an NMOS transistor and a gate oxide film  229  and a second gate electrode  230   b  for a PMOS transistor, formed on the semiconductor layer  220   a.    
     Refer to FIG. 2I, A doped dielectric layer  250 , for example, n-doped PSG (Phosphosilicate Glass) or n-doped SOG (Spin-On-Glass), is sequentially formed over the surface of the substrate  224  by, for example, chemical vapor deposition (CVD). 
     Refer to FIG. 2J, a photoresist film  231  is formed and patterned over the doped dielectric layer  250 . An area of the doped dielectric layer  250  is removed to expose the semiconductor layer  220   a  on both sides of the second gate electrode  230   b  and the semiconductor layer  220   b  beside the first gate electrode  230   a,  where the first gate electrode  230   a  and the semiconductor layer  220   a  beside the second gate electrode  230   b  are not exposed. Using the patterned photoresist film  231  as a mask, the P-type semiconductor layer  220   b  is injected with P-type boron ions to form lightly doped source/drain regions  232   a  and  232   b.  The photoresist film  231  is then removed. 
     Refer to FIG. 2K, the N-type dopants inside the doped dielectric layer  250  are driven into the doped N-type semiconductor layer at a high temperature in an environment of inert gas to form n + doped source/drain regions  234   a  and  234   b,  as well as the n + doped semiconductor layer  220   c  as shown in FIG.  2 K. 
     Refer to FIG. 2L, depositing and removing an insulating film  235  to expose areas of the P-type semiconductor layer  220   b,  the N-type semiconductor layer  220   c,  the P-type source/drain regions  232   a  and  232   b  and the N-type source/drain regions  234   a  and  234   b  and form contact holes. A conductive layer is formed to fill the contact holes. The conductive layer is etched to form contact pads  236   a  and  236   f  on the P-type and N-type semiconductor layers  220   b  and  220   c  and line layers  236   b,    236   c,    236   d,    236   e  on the n and p source/drain regions  232   a / 232   b  and  234   a / 234   b.    
     Refer to FIGS. 3I-3L, which are cross-sectional views showing process steps of a method for fabricating the SOI device according to another preferred embodiment of the present invention. The embodiment of the present invention comprises similar steps of forming the SOI device as shown in FIGS.2A-2L through forming the gate oxide film  329  and the first gate electrode  330   a  for an NMOS transistor and a gate oxide film  329  and a second gate electrode  330   b  for a PMOS transistor, formed on the semiconductor layer  320   a,  as shown in FIG.  3 I. 
     Refer to FIG. 3I, a doped dielectric layer  350 , for example, p-doped boronsilicate glass (BSG) or p-doped SOG is formed over the surface of the substrate  324  by, for example, CVD. 
     Refer to FIG. 3J, a photoresist film  331  is formed and patterned over the doped dielectric layer  350 . An area of the doped dielectric layer  350  is removed to expose the semiconductor layer  320   b  on both sides of the second gate electrode  330   a  and the semiconductor layer  320   b  beside the second gate electrode  330   b,  where the first gate electrode  330   b  and the semiconductor layer  320   b  beside the first gate electrode  330   a  is not exposed. Using the patterned photoresist film  331  as a mask, the N-type semiconductor layer  320   a  is injected with N-type As ions to form doped source/drain regions  334   a  and  334   b.  The photoresist film  331  is then removed. 
     Refer to FIG. 3K, the P-type dopants inside the doped dielectric layer  350  is driven into the P-type semiconductor layer beside the first gate electrode  330   b  to form doped source/drain regions  332   a  and  332   b.    
     Refer to FIG. 3L, which is a cross-sectional view showing an SOI device according to an embodiment of the present invention. Depositing and removing an insulating film  335  to expose areas of the N-type semiconductor layer  320   a,  the P-type semiconductor layer  320   c,  the P-type source/drain regions  332   a  and  332   b  and the N-type source/drain regions  334   a  and  334   bc  and form contact holes. A conductive layer is formed to fill the contact holes. The conductive layer is etched to form contact pads  336   a  and  336   f  on the P-type and N-type semiconductor layers  320   b  and  320   c  and line layers  336   b,    336   c,    336   d,    336   e  on the n and p source/drain regions  332   a / 232   b  and  334   a / 334   b.    
     An advantage of the present invention is that only one lithography mask step is required to form the doped regions instead of the two steps required by the conventional method. Another advantage of the present invention is that the channel regions of NMOS and PMOS transistors are electrically connected to first and second conductivity type semiconductor layers, respectively, having contact pads through first and second conductivity type polysilicon layers, thereby reducing floating body effects and thus improving the operation characteristics. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Technology Classification (CPC): 7