Patent Abstract:
A structure having; a body; a pair of capacitors disposed over different portions of a surface of the body; a first one of the capacitors having an upper conductor and a lower conductor separated a dielectric layer; and a second one of the pair of capacitors having an upper conductor and a lower conductor separated a dielectric structure, the dielectric structure having a lower dielectric layer, and an upper dielectric layer, wherein the material of the lower dielectric layer is different from the material of the upper dielectric layer.

Full Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates generally to MMICs having capacitors with different capacitances. 
       BACKGROUND 
       [0002]    As is known in the art, it is sometimes desirable to provide a plurality of different capacitors having different capacitances on a common surface of a substrate providing a Monolithic Microwave Integrated Circuit (MMIC). 
       SUMMARY 
       [0003]    In accordance with the disclosure, a structure is provided, comprising: a body; a pair of capacitors disposed over different portions of a surface of the body; a first one of the capacitors having an upper conductor and a lower conductor separated by a dielectric layer; and a second one of the pair of capacitors having an upper conductor and a lower conductor separated a dielectric structure, the dielectric structure having a lower dielectric layer, and an upper dielectric layer, wherein the material. of the lower dielectric layer being different from the material of the upper dielectric layer. 
         [0004]    The use of different dielectric materials within the metal-insulator-metal (MIM) capacitor dielectric of a MMIC results in lower MMIC cost, higher reliability and higher performance. 
         [0005]    In one embodiment, a method is provided for forming a plurality of metal-insulator-metal (MIM) capacitors on a surface of a body, the capacitors having different insulator dielectric thicknesses. The method includes: forming a plurality of lower metal conductors over the surface of the body, each one of the conductors providing a lower electrode for a corresponding one of the capacitors; depositing a first dielectric layer over the surface of the body, portions of the first dielectric layer being disposed over the plurality of lower conductors; depositing a second dielectric layer over the first dielectric layer including the portions of the first dielectric disposed over the plurality of lower conductors; forming a mask over the second dielectric layer, such mask having a window therein exposing a first portion of the second dielectric layer disposed over a first one of the lower metal conductors while covering a second portion of the second dielectric layer over a second one of the lower metal conductors; exposing the mask to an etch, the etch having a etch rate in the second dielectric layer being greater than the etch rate in the first dielectric layer, the etch removing the second dielectric layer exposed by the window exposing an underlying portion of the first dielectric layer while leaving the underlying portion of the first dielectric layer over the first one of the lower metal conductors; removing the mask exposing both the second dielectric layer over a second one of the lower metal conductors and the underlying portion of the first dielectric layer over the first one of the lower metal conductors; depositing an upper metal layer over the exposed second portion of the second dielectric layer over a second one of the lower metal conductors and the underlying portion of the first dielectric layer over the first one of the lower metal conductors; and patterning the upper metal layer to form an upper electrode for a first one of the capacitors over the first one of the lower electrodes and an upper electrode for a second one of the capacitors. 
         [0006]    With such an arrangement, a capacitor dielectric stack-up is provided with an etch stop layer (the first dielectric layer) allows design flexibility to remove or not remove the top dielectric layer and change the total thickness. 
         [0007]    The layer thicknesses of the dielectric layers can be Chosen so that a capacitor having both layers can withstand the highest DC plus voltage within the MMIC thereby eliminating the need for multiple capacitors in series. If the upper dielectric layer is etched away to leave only the lower dielectric layer, the lower dielectric layer thickness can be chosen so that it has an adequate breakdown rating for DC bypassing with a smaller area. 
         [0008]    The method can be used to eliminate air bridges: When it is required to have a signal cross another conductor on a without being connected, rather than using an air bridge; the upper metal therein when used with high power may sometimes degrade due to the temperature rise caused by the high RF or DC current levels. By eliminating the air bridge as a cross-over in accordance with the disclosure, a cross-over in accordance with the disclosure has a much better heat path than an air bridge so it will be much less prone to failure while still being able to withstand high RF or DC voltage levels without breakdown. 
         [0009]    In one embodiment, the method includes; forming an additional lower conductor over the surface of the body. Portions of the first dielectric layer are also deposited over the additional lower conductor; portions of the second dielectric layer are deposited over the portions of the first dielectric layer over the additional lower conductor; portions of the mask are deposited over a portion of the second insulating layer over the additional lower metal conductors; portions of the upper metal layer are disposed over the second dielectric layer above the additional lower metal conductor. The patterning of the upper metal layer forms a conductor crossing over the additional lower conductor. 
         [0010]    In one embodiment, the thick top dielectric layer over a Field Effect Transistor (FM) region is etched away to eliminate its additional dielectric loading on the FET performance. Therefore the above benefits for capacitors and air bridge elimination can be achieved with little or no performance impact to the PETs. The added flexibility to choose the thicknesses of the two dielectric layers could also be used to even improve the FET performance. 
         [0011]    The details of one or more embodiments of the disclosure are set forth. in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0012]      FIG. 1  is a simplified diagraminatical sketch of an Monolithic Microwave Integrated Circuit (MMIC) according to the disclosure; and 
           [0013]      FIGS. 2A-2K  are simplified diagrammatical sketch of a process used to form the MMIC at various steps in the manufacture thereof according to the disclosure. 
       
    
    
       [0014]    Like reference symbols in the various drawings indicate like elements. 
       DETAILED DESCRIPTION 
       [0015]    Referring now to  FIG. 1 , a body  10 , here for example a semiconductor body, here, for example, GaN, is formed into a Monolithic Microwave Integrated Circuit (MMIC)  12 . Here, for simplicity, the MMIC circuit  12  will be formed having a FET  14  in a PET region  16  of the body  10 , a high voltage capacitor  18 , in a high voltage capacitor region  20  of the body  10 , slow voltage capacitor  22  formed in a low voltage region  24  of the body  10 , and a conductive cross over  26  formed in a cross over region  28  of the body  10 , as indicated. 
         [0016]    More particularly, referring now to  FIGS. 2A-2K , source, and drain electrodes  30 ,  32  are formed in ohmic contact with the body  10 , as shown, using any conventional process. A dielectric layer  34 , here for example a 500 Angstrom thick layer of Silicon Nitride (SiN) is deposited over the upper surface of the body  10  and over the source and drain electrodes  30 ,  32 . A window  36  ( FIG. 2B ) is formed in the dielectric layer  34  to expose the gate region of the FET. A gate electrode  38  ( FIG. 2C ) is formed in Schottky contact with the exposed portion of the body  10 , as shown. 
         [0017]    Next, lower conductors  40 ,  42  and  44  are formed on the first dielectric layer  34  over the high voltage capacitor region  20 , the low voltage capacitor region  24 , and the cross-over region  28  using conventional photolithographic processing, for example. Next, a second. dielectric layer  46  ( FIG. 2D ), here for example a 2000 Angstrom thick layer of Si 3 N 4  is deposited over the surface of the structure; it being noted that the second dielectric layer  46  is deposited on the source electrode  30 , the gate electrode  38 , the drain electrode  32 , and the lower conductors  40 ,  42 ,  44  with portions second dielectric layer  46  being deposited on portions of the first dielectric layer  34 , as shown. 
         [0018]    Next, a mask  48  is formed on the surface of the MMIC, the mask having windows  50  over the source and drain contacts  30 ,  32 , as shown. The portions of the second dielectric layer  46  exposed by the windows  50  are etched away using conventional lithographic etching techniques, for example, to expose the source  30  and drain  32 . 
         [0019]    Next, the mask  48  is removed leaving the structure shown in  FIG. 2E . 
         [0020]    Next, a field plate  52  ( FIG. 2F ) is formed, as shown, using any conventional deposition, photolithographic, etching process. 
         [0021]    Next, a dielectric etch stop layer  54  ( FIG. 2G ), here for example Al 2 O 3  having, for example, a thickness of 50 Angstroms, is deposited over the structure. Next, a fourth dielectric layer  56 , here for example, a 6000 Angstroms thick layer of Si 3 N 4  resulting in the structure shown in  FIG. 2H . 
         [0022]    Next, a mask.  58  is formed on the surface of the structure, the mask  58  having windows  60 ,  62  exposing the FBI region  16  and the low voltage capacitor region  24  but remaining over the high voltage capacitor region  20  and the cross over region  28 , as shown in  FIG. 21 . Next, the mask  58  is exposed to an etchant, here for example SF 6  (sulfur hexafluoride) using a Reactive Ion Etcher to remove portions of the fourth dielectric layer  56  exposed by the windows  60 ,  62 , thereby exposing underlying portions of the etch stop layer  54  producing the structure shown in  FIG. 2J  after the mask  58  is removed. It is noted that the SF 6  etches away the exposed portions of the Si 3 N 4  layer at a substantially higher rate (for example at least two orders of magnitude faster) and therefore in essence stops at the underlying portions of the Al 2 O 3  etch stop layer  54 . 
         [0023]    Next, a new mask  64  ( FIG. 2K ) is formed over the structure with windows  66 ,  68  in the mask  64  exposing portions of the etch stop layer  54  disposed over the source and drain electrodes  30 ,  32 . The exposed portions of the etch stop layer  54  are etched away using a dry etch of Cl 2  and BCl 3    
         [0024]    Next, the mask  64  is removed. A conductor is deposited over the surface of the structure and patterned into the upper conductors  70   a  for the source electrode, the drain electrode  70   b,  the high voltage capacitor  70   d,  the low voltage capacitor  70   c  and the cross over conductor  700  using conventional photolithographic-etching techniques, for example, producing the MMIC  12  shown in  FIG. 1 . 
         [0025]    A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, a two dielectric structure may be formed, by eliminating etch stop layer  54  and making the lower dielectric layer  46  from the same dielectric material that had been used for the etch stop layer  54 . The thickness of the lower dielectric layer  46  is chosen to meet the capacitance and breakdown voltage requirements for capacitor  22  ( FIG. 1 .), For example, the lower dielectric layer  46  may be, a 2000 Angstrom thick layer of Al 2 O 3  and the upper layer  56  may be a 6000 Angstrom thick layer of Si 3 N 4 ; Where the etch rate to a given etch is substantially faster (for example, at least two orders of magnitude faster) to the Si 3 N 4  that to the Al 2 O 3  Thus, such a two-dielectric structure may be used in place of a three-dielectric structure having a lower 2000 Angstrom thick Si 3 N 4  layer, a 50 Angstrom thick Al 2 O 3  middle, etch stop layer , and a 6000 Angstrom thick Si 3 N 4  upper dielectric layer. Accordingly, other embodiments are within the scope of the following claims.

Technology Classification (CPC): 7