Patent Abstract:
A receiver employed in a communication system, for detecting, tracking and combining the various significant components of a multipath fading signal spanned over several symbol periods, consists of a plurality of signal register arrays, a block reference signal creator, a plurality of matched filters, a signal combiner, and a controller. The signal register arrays generates a plurality of moving sections of the received signal with one of the signal register array coupled to the received signal and each one of the rest signal register arrays coupled to its previous signal register array. At beginning of a communication section, the block reference signal creator generates a plurality of sections of a reference signal and holds these sections for a certain amount of time. During normal message transmission, the block reference signal creator generates a plurality of identical sections of the reference signal and holds the section for a symbol period, then generates the next identical section of the reference signal and holds the section for a symbol period. And repeat the processing. Each matched-filter is for finding the correlation between a section of the received signal and a section of the reference signal. The signal combiner is for combining the components from matched filters together. The controller is for monitoring the signals from all matched filters and signal combiners, extracting necessary information, and generating various control signals.

Full Description:
FEDERALLY SPONSORED RESEARCH  
         [0001]    Not Applicable  
         SEQUENCE LISTING OR PROGRAM  
         [0002]    Not Applicable  
         FIELD OF THE INVENTION  
         [0003]    The invention is generally related to the receiver of a communication system. More particularly the invention is related to applying dynamic matched filters for detecting and tracking the components of a multipath signal spanned over several symbol periods in a radio link of a direct sequence spreading spectrum communication system and combining these components efficiently.  
         BACKGROUND OF THE INVENTION  
         [0004]    In a wireless communication system, especially in a mobile communication system, fading occurs from times to times. Buildings, mountains, and foliage on the transmission path between a transmitter and a receiver can cause reflection, diffraction, and scattering on a propagating electromagnetic wave. The electromagnetic waves reflected from various large objects, travel along different paths of varying lengths. If there is an obstacle with sharp irregularities on the transmission path, the secondary waves resulting from the obstructing surface are present around the obstacle. Also if there are small objects, rough surfaces, and other irregularities on the transmission path, scattered waves are created. All these waves will interact with each other and result in multipath fading.  
           [0005]    Under some environments such as in many metropolitan areas, there is no line-of-sight signal. The received signal is a multipath-fading signal from reflection, scattering, and diffraction. Statistically no any particular component of the multipath-fading signal is stable for a relatively long period of time and significant stronger than the rest components in a fairly large region. In order to provide service to these areas with good quality, all these major components of the multipath-fading signal have to be combined in some way so that on average the combined signal will be more stable and stronger than each component.  
           [0006]    Before any attempting to combine the components of a multipath-fading signal, one has to identify all the significant components. This would require that all the significant components must be recognizable. That is, a transmitted symbol must be different from any of its neighbor symbols within the multipath-spanned range so that a delayed version of a transmitted symbol will be not mistaken as a different symbol.  
           [0007]    A direct sequence spread spectrum system can naturally provide a way to distinguish the neighbor transmitted symbols and therefore all the significant components of a multipath-fading signal are recognizable. This is due to the fact that the delayed versions of the transmitted pseudo-noise (PN) signal have poor correlation with the original PN signal.  
           [0008]    As IP originated messages are more and more popular, packet-switched communication system is more and more common. In a packet-switched communication system, a received package could come from total different source than the one before and the one after, and therefore generally there is no any relation between two adjacent packets. When transmission rate is very high, in order to reduce the capacity loss of communication system and obtain multipath information before the information loses its meaning, one could prefer to use matched-filter instead of correlator.  
           [0009]    However, the regular matched filters do not work well. For a regular matched filter, the reference signal is fixed. In a direct sequence spreading spectrum communication system, the reference signal is changing all the time. Some modifications around the matched filter have to be made so that the matched filters are able to detect the various components of a multipath fading signal spanned over several symbol periods even though the reference signal is changing all the time.  
           [0010]    The common method to combine several components of a multipath-fading signal consists of several steps. First, let the received signal pass a delay line with taps. The length of delay line should be long enough that the section of received signal captured by the delay line is equal or larger than range spanned by the multipath fading signal. Second, depending on the relative positions of the significant components, the several corresponding taps are selected. Third, the signal from each of selected taps is weighted by a different weight and is aligned properly by phase. And finally all the weighted signals are added together.  
           [0011]    The common method of combinations has some drawbacks in a direct communication system.  
           [0012]    First, when a multipath-fading signal spans for a large range and when the data rate is high, the above approach could consume a lot of hardware. In a direct sequence communication system, there are 64 chips in each symbol period and a multipath signal spans about 4 symbol periods. If one takes 4 samples in each chip, the delay line will consist of 4×64×4=1024 memory elements. Further suppose there are at most two significant components, in order to be able to select the two corresponding taps, two selective devices are needed with each one is connected to the 1024 memory elements. The selective devices consume a lot of hardware.  
           [0013]    Second, a separate circuit could be needed to monitor each significant component. In order to keep good communication quality, one has to constantly monitor the information related to all the significant paths and adjust the weight, phase, and position associated with each significant component. But in a direct sequence spreading spectrum communication system, the signal from a selective tap does not directly provide the necessary information about that corresponding path. A despreading circuit has to be used to despread the signal of a selective tap and then the information about a corresponding path could be extracted.  
           [0014]    In order to avoid huge selective devices and a plurality of despreading circuits, one perhaps prefers to despread each significant component by common despreading circuit first then combine these components together.  
           [0015]    Based on previous discussions, it would be desirable to provide a mechanism for a receiver of a spreading spectrum communication system to despread all significant multipath components by a bank of matched filters, extract the related information from these despreaded components, and combine all the despreaded significant components efficiently.  
         OBJECTIVES OF THE INVENTION  
         [0016]    The first idea behind the invention is based on the observation that all the significant components of a multipath-fading signal span over a limited range. A bank of matched filters is able to capture all these significant components if each of them can capture the components over a different portion of the limited range.  
           [0017]    The second idea behind the invention is based on the observation that for the purpose of signal combination, it is enough to delay some samples of a despreaded signal instead of the despreaded signal itself for some amount of time.  
           [0018]    The primary objective of the invention is to provide a method for a receiver of a direct sequence spreading spectrum communication system to detect and track the various components of a multipath fading signal spanned over several symbol periods with a bank of matched filters.  
           [0019]    Another objective of the invention is to provide method of delaying the sampled values of a despreaded signal efficiently. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    The accompanying drawings, which are incorporated in and constitute a part of the specification, depict the preferred embodiments of the present invention, and together with the description, serve to explain the principle of the invention. In the figures, like reference numerals refer to the same or similar elements.  
         [0021]    [0021]FIG. 1 illustrates the first embodiment of applying a bank of dynamic matched filters and a signal combiner in a receiver of a communication system.  
         [0022]    [0022]FIG. 2 illustrates the first implementation of the reference signal creator in a FIG. 1.  
         [0023]    [0023]FIG. 3 illustrates the second implementation of the reference signal creator in a FIG. 1.  
         [0024]    [0024]FIG. 4 illustrates the signal combiner in a FIG. 1.  
         [0025]    [0025]FIG. 5 illustrates the second embodiment of applying a dynamic matched filter and a signal combiner in a receiver of a communication system.  
         [0026]    [0026]FIG. 6 illustrates the signal combiner in a FIG. 6.  
         [0027]    [0027]FIG. 7 illustrates the first implementation of the delay line used in FIG. 4 and FIG. 6.  
         [0028]    [0028]FIG. 8 illustrates the second implementation of the delay line used in FIG. 4 and FIG. 6. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]    Detailed description of the preferred embodiments is provided herein. The embodiments illustrate dynamic matched filter bank, signal combiner, and their applications in a receiver of a communication system by way of examples, not by way of limitations. It is to be understood that it could be easy for those skilled in the art to modify the embodiments in many different ways. Therefore, specific details disclosed are not to be interpreted as limitations, but rather as bases for the claims and as representative bases for teaching one to employ the present invention in virtually any appropriately detailed system, structure or manner.  
         [0030]    We assume that there are at most M significant multi-path components and the multipath signal spans over less than L symbols. We further assume that all the significant components of a multipath signal emerging during the communication section will not appear t 0  second earlier than the first significant component detected at the beginning of a communication section.  
         [0031]    Also we assume that there are N chips in each symbol period, there are K samples in each chip. For simplicity, in the example, we let M=2, L=3, N=10, and K=4.  
         [0032]    Let&#39;s denote the frequency of sampling clock by f s , the frequency of the X times of the frequency of the sampling clock by f X , the frequency of chip clock by f c , and the frequency of the symbol clock by f sym . Correspondingly, the period of sampling clock is denoted by T s  seconds, the period of a clock X times of the frequency of the sampling clock by T X  seconds, the period of a chip by T c  seconds, and period of a symbol by T sym  seconds.  
         [0033]    [0033]FIG. 1 shows the first embodiment of applying a bank of dynamic matched filters and a signal combiner in a receiver of a communication system.  
         [0034]    For simplicity, these matched filters are called dynamic matched filters for their reference signals are different from the time to time.  
         [0035]    The received signal S in  is fed into signal register array  105   1 , which consists of a plurality of signal shift registers with the first signal shift register coupled to the received signal S in  and each of the rest signal shift registers cascaded to its previous signal shift register. There is a tapped output signal from each signal shift register. The received signal S in  and all these tapped output signals are sent to matched-filter  115   1 . The tapped output signal from the last signal shift register of the signal registers array  105   1  is also fed to the first signal shift register of signal register array  105   2 . The signal register array  105   2  has same number of signal shift registers as the signal register array  105   1 , with each signal shift register cascaded to its previous signal register. Also there is a tapped output signal from each signal shift register. All these tapped output signals are sent to the matched filter  115   2 .  
         [0036]    There are totally L signal register arrays from  105   1  to  105   L , with one signal register array cascaded by its previous one. All these signal register arrays have exactly the same structures and have same number of tapped output signals. Corresponding to a segment of the received signal S in  in one symbol period, the tapped output signals from each signal register array, are sent to a corresponding matched filter from  115   1  to  115   L . The output signals from a signal register array form a moving section of received signal S in  in sampled version. Each section size is corresponding to a symbol period. The tapped output signals from all these L signal register arrays from  105   1  to  105   L , form a big moving section of received signal S in  in sampled version. The big moving section has a size corresponding to L times the symbol period.  
         [0037]    A shifting clock drive all the signal shift registers of each signal register array. In most case, the shifting clock is the sampling clock.  
         [0038]    For simplicity, we further assume that at the beginning of a communication section, there is an identification sequence of L symbols or LN chips for initial estimation of the parameters related to a multipath fading signal. We also assume all these L symbols have same phase. When there are more than L symbols needed for such estimation, either more hardware or some trade-off may be required. When there are less than L symbols needed for such estimation, only portion of the hardware will be used and the unused portion could be disabled.  
         [0039]    When a communication starts, the reference signal creator  110  generates L symbols of the identification sequence with each symbol for a corresponding matched filter. The reference signal creator  110  will hold these symbols until LT sym−  t 0  seconds after a first component of a multipath signal has been detected. Therefore the output of each matched filter is the correlation between a section of the identification sequence and a corresponding section of received signal S in . When the summation of the output signals from these matched filters has big signal strength, there is good probability that a component of a multipath signal exists. During initialization, all the components spanned over less than L symbol periods of the multipath signal will be caught up.  
         [0040]    LT sym−  t 0  seconds after the first component of a multipath signal has been detected, the reference signal creator  110  will generate L identical reference symbols with one for a corresponding matched filter every symbol period. The reference symbol of any of the L matched filters changes from one symbol period to another.  
         [0041]    Corresponding to L signal register arrays, there are L matched filters from  115   1  to  115   L . Each of these matched filters  115   i , i=1, . . . L, is to find the correlation between its reference signal and its input signal from a corresponding signal register array. The output of matched filters  115   i  is denoted by MF 1 , with i=1, . . . L.  
         [0042]    The controller  120  extracts information from various devices such as matched filters and signal combiner, and provides various control signals to block reference signal generators and signal combiner.  
         [0043]    The information collected from the outputs of all these matched filters are used for not only updating the information about the currently tracked significant components such as the signal strengths, phases, and positions, but also looking for new significant components. A significant component of the multipath-fading signal emerged after initialization, will be detected by the controller  120  from the output signal of each matched filter. When the output from a particular matched filter is significant at a same position for continuous several symbol periods, there is a good probability that a new significant component has emerged.  
         [0044]    When the significant components of the multipath signal is shifted to one side or another side, the controller  120  will properly adjust the instant to update the reference signal creator  110  so that no significant component will not be detected.  
         [0045]    The signal combiner  125  combines the various significant component of a multipath signal together. Taking the output signal of signal combiner  125  as its input signal, the decision circuit  130 , makes a decision on the transmitted symbol.  
         [0046]    [0046]FIG. 2 shows the first implementation of the reference signal creator  110  in a FIG. 1.  
         [0047]    There are L block reference signal generators  140   1  to  140   L , with each one under control of different control signals from the controller  120 .  
         [0048]    When a communication starts, under the control of the controller  120 , the L block reference signal generators  140   1  to  140   L  generate the L symbols of the identification sequence and hold these symbols until LT sym−  t 0  seconds after the first component of a multipath signal has been detected. Then, a normal communication starts. Under the control of the controller  120 , the L block reference signal generators  140   1  to  140   L  generate L identical reference symbols every symbol period. The controller  120  has control on these reference signal generators on when to update their output symbols.  
         [0049]    [0049]FIG. 3 shows the second implementation of the reference signal creator  110  in a FIG. 1.  
         [0050]    There is a block reference signal generator  150  and L registers  155   1  to  155   L .  
         [0051]    When a communication starts, under the control of the controller  120 , the block reference signal generator  150  generates L symbols of the identification sequence and each of the L registers  155   1  to  155   L  will catch one of the L symbols. The L registers  155   1  to  155   L  will hold these symbols until LT sym−  t 0  seconds after the first component of a multipath signal has been detected. Then, the block reference signal generator  150  will generate a new symbol at the interval of every symbol period and each of the L registers  155   1  to  155   L  will catch the same new symbol simultaneously. The controller  120  has control on the block reference signal generator  150  on when to generate a new symbol and the L registers  155   1  to  155   L  on when to catch their input symbols.  
         [0052]    [0052]FIG. 4 shows the signal combiner  125  in a FIG. 1.  
         [0053]    From the assumption that there are at most M possible significant components of a multipath signal, there are M identical mechanisms each for capturing each one of the M components. For simplicity, only the first one will be explained.  
         [0054]    The mechanism for capturing the first component, consists of a demultiplexer  205   A , a sampling device  210   A , a delay line  215   A , and a complex multiplier  220   A .  
         [0055]    The demultiplexer  205   A  takes the output signals of all matched filters  115   1  to  115   L , denoted by MF 1  to MF L  as its input signals. A control signal from the controller  120  makes the demultiplexer  205   A  pass a desired matched filter output signal to a sampling device  210   A .  
         [0056]    Another control signal from the controller  120  makes the sampling device  210   A  take samples from the output of demultiplexer  205   A  at proper instants. The sampling device  210   A  could consist of D flip-flops and be driven by a sampling clock f s .  
         [0057]    The output of sampling device  210   A  is fed to a delay line  215   A . Under the control signals from the controller  120 , a proper delay is inserted. The output of the delay line  215   A  is multiplied at the multiplier  220   A  by a complex weight signal from the controller  120 . The complex weight signal has a magnitude proportional to the average signal strength of the first component and a phase compensating for first component.  
         [0058]    The output signals from all M multiplier  220   A  to  220   B  are added at adder  225 . The summation will be sent to the decision circuit  130  in FIG. 1.  
         [0059]    The output signals of all matched filters are also fed to adder  230 . During the initialization, the threshold logic circuit  235  checks if the output signal of adder  230  has a signal strength stronger than a threshold and flags if a component of a multipath signal has been detected. Both the output signals of adder  230  and threshold logic circuits  235  are sent to controller  120  for extracting the information related to the component at the beginning of a communication section.  
         [0060]    [0060]FIG. 5 shows the second embodiment of applying a dynamic matched filter and a signal combiner in a receiver of a communication system.  
         [0061]    The received signal S in  and the signal register array  305   1  to  305   L  in FIG. 5 are same as the received signal S in  and the signal register array  105   1  to  105   L  in FIG. 1 respectively.  
         [0062]    The output signals from each of the L signal register arrays  305   1  to  305   L  are connected to the demultiplexer  310 . A control signal from controller  325  makes the demultiplexer  310  select output signals from each of signal register arrays by turn. The demultiplexer  310  has to work at a frequency at least L time of the shifting clock of these signal registers. The output of demultiplexer  310  is connected to the matched filter  320 .  
         [0063]    There is a block reference signal generator  315 . At the initial stage of a communication section, the block reference signal generator  315  will generate L reference symbols of the identification sequence with each reference symbol corresponding to a signal register array. After LT sym−  t 0  seconds of the moment when the first component of a multipath signal is detected, the block reference signal generator  315  will generate one symbol or N chips every symbol period. The output of the block reference signal generator  315  is connected to the matched filter  320 .  
         [0064]    The matched filter  320  is used to find the correlation value between the current section of the reference signal and a corresponding section of the received signal represented by the output signals of a signal register array. It works at least L times as fast as the shifting clock of the L signal register arrays  305   1  to  305   L    
         [0065]    The output signal of matched filter  320 , denoted by MF, is sent to both controller  325  and signal combiner  330 .  
         [0066]    The signal combiner  330  is used to combine the up to M significant multipath signals together. The output from signal combiner  330  is sent to decision circuit  335  to make a final decision on which symbol is transmitted.  
         [0067]    [0067]FIG. 6 shows the signal combiner  330  in a FIG. 5.  
         [0068]    As in FIG. 4, among the M exactly same mechanisms for capturing M possible paths, only the first one will be explained.  
         [0069]    The output of matched filter  320  is fed to a sampling device  410   A . The sampling device  410   A  could consists of D flip-flops and be driven by a clock with a frequency at least L times of the shifting clock f s . A control signal from the controller  325  makes the sampling device  410   A  to take samples from the output of matched filter  320  at proper instants.  
         [0070]    The output of sampling device  410   A  is fed to a delay line  415   A . Under the control signals from the controller  325 , a proper delay is inserted. The output of the delay line  415   A  is multiplied at multiplier  420   A  by a complex weight signal from the controller  325 . The complex weight signal has a magnitude proportional to the average signal strength of the first component and a phase compensating for first component.  
         [0071]    The output signals from all M multiplier  420   A  to  420   B  are added at adder  425 . The summation will be sent to the decision circuit  335  in FIG. 5.  
         [0072]    The output signal from the matched filter  320  is also fed to L−1 memory devices  430   1  to  430   L−1 . These devices work at a frequency of L times the shifting frequency of signal registers in the signal register array  305   1  to  305   L . The L−1 output signals from L−1 memory devices  430   1  to  430   L− 1 and the output signal MF from matched filter are sent to an adder  435 . The output signal of the adder  435  will be sent to the controller  325 , which will check the signal at proper instants and find out if there is a significant component.  
         [0073]    [0073]FIG. 7 shows the first implementation of the delay line  215  in FIG. 4 and the delay line  415  in FIG. 6.  
         [0074]    There are K−1=3 memory elements  510   1  to  510   3 . The input signal is fed to the first memory elements  510   1  and each of the rest memory elements is cascaded to its previous one. Sampling clock f s  drives these memory elements  510   1  to  510   3 . They could be a plurality of D flip-flops. Both the input signal and the outputs of memory devices  510   1  to  510   3  are sent to a selecting device  520 .  
         [0075]    Under a control signal from a controller, the selecting device  520  selects one input signal from its K=4 input signals as its output signal.  
         [0076]    There are another N−1=9 memory elements  530   1  to  530   9 . The output signal of the selecting device  520  is fed to the first memory elements  530 , and each of the rest memory elements is cascaded to its previous one. These memory elements are driven by a chip clock f c . They could be a plurality of D flip-flops. Both the input signal to the first memory element  530   1  and the output signals of memory devices  530   1  to  530   9  are sent to a selecting device  540 .  
         [0077]    Under a control signal from a controller, the selecting device  540  selects one input signal from its N=10 input signals as its output signal.  
         [0078]    [0078]FIG. 8 shows the second implementation of the delay line  215  in FIG. 4 and the delay line  415  in FIG. 6.  
         [0079]    Various significant components, after matched filter, are all in one symbol period. Therefore, the maximum delay is no more than a symbol period or N·K samples. The relative position of any multipath component can be represented by no more than ┌log 2 (N·K)┐ binary bit. When N=10 and K=4, we obtain ┌log 2 (N·K)┐=┌log 2 ( 40 )┐=6, where ┌x┐ denotes the smallest integer larger or equal to x. Any delay d in the right range could be unique expressed by 
           d=n   0   ·T   s   +n   1 ·(2 T   s )+ n   2 ·(4 T   s )+ n   3 ·(8 T   s )+ . . . + n   k ·(2 k   T   S ) 
         Where  k =┌log 2  ( N·K )┐−1=5 and  n   1 =1 or 0 for  i =0 , . . . , k.   
         [0080]    The delay line in FIG. 8 consists of ┌log 2 (N·K)┐ memory elements  605  to  655  and ┌log 2 (N·K)┐ demultiplexers  610  to  660 . The memory elements could consist of D flip-flops. Each of these ┌log 2 (N·K)┐ memory elements  605  to  655  is driven by different clock and therefore produces different delay.  
         [0081]    The control signals from a controller will make each of the demultiplexers to select a proper input signal as its output and therefore a desired delay will be generated.  
         [0082]    Input signal is fed to the memory element  605  and the demultiplexer  610 . The memory element  605  is driven by the sampling clock f s . Depending on the value of n 0 , different control signal will be generated. When n 0 =1, a control signal will let demultiplexer  610  pass the output signal of the memory element  605 ; otherwise, the control signal will let demultiplexer  610  pass the input signal of the memory element  605 .  
         [0083]    The output signal of demultiplexer  610  is fed to the memory element  615  and demultiplexer  620 . The memory element  615  is driven by a clock whose frequency is half of the sampling clock f s . Depending on the value of n 1 , different control signal will be generated. When n 1 =1, a control signal will let demultiplexer  620  pass the output signal of the memory element  615 ; otherwise, the control signal will let demultiplexer  620  pass the input signal of the memory element  615 .  
         [0084]    Similarly, the output signal of demultiplexer  620  is fed to the memory element  625  and demultiplexer  630  . The memory element  625  is driven by a clock whose frequency is one-fourth of the sampling clock f s . Depending on the value of n 2 , different control signal will be generated. When n 2 =1, a control signal will let demultiplexer  630  pass the output signal of the memory element  625 ; otherwise, the control signal will let demultiplexer  630  pass the input signal of the memory element  625 .  
         [0085]    In this way, the output signal of demultiplexer  650  (not shown in the figure) is fed to the memory element  655  and demultiplexer  660 . The memory element  655  is driven by a clock whose frequency is 1/32 of the sampling clock f s . Depending on the value of n 5 , different control signal will be generated. When n 5 =1, a control signal will let demultiplexer  660  pass the output signal of the memory element  655 ; otherwise, the control signal will let demultiplexer  660  pass the input signal of the memory element  655 .

Technology Classification (CPC): 7