Patent Abstract:
A test coupon is used to evaluate characteristics of multi-layer printed wiring boards. The coupon includes a multi-layer substrate which has at least first and second wiring layers. The first and second wiring layers are configured to correspond to a tested wiring layer and another wiring layer of the multi-layer printed wiring boards, respectively. Each of first and second through hole groups has a plurality of through holes which pass through the multi-layer substrate and which are arranged in an arranging direction. A first and second conductor patterns which are provided on the first and second wiring layers respectively extend substantially along the arranging direction.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    The present application claims priority under 35 U.S.C. §119 to Japanese Patent Application No.10-310592, filed Oct. 30, 1998. Further, the present application claims priority under 35 U.S.C. §120 to International Application No. PCT/JP99/06014, filed Oct. 28, 1999, entitled “TEST COUPON IN PRINTED WIRING BOARD.” The contents of these applications are incorporated herein by reference in their entirety. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. FIELD OF THE INVENTION  
           [0003]    The present invention relates to a test coupon which is configured to be used to evaluate characteristics of multi-layer printed wiring boards.  
           [0004]    2. DISCUSSION OF THE BACKGROUND  
           [0005]    A conventional test coupon  51  in the printed wiring board is, as shown in FIG. 14, provided separably in a protruding condition on an edge of a printed wiring boards  52 . A plurality of through holes  53 ,  54  are formed along both edges of the test coupon  51 . Directions  55 ,  56  of arrays of the through holes  53 ,  54  are set in parallel to each other and also orthogonal to the edge of the test coupon  51 . Between the arrays of the through holes  53 ,  54 , a plurality of conductor patterns  57  each of which extends in a direction orthogonal to the directions of the arrays of the through holes  53 ,  54  (as indicated by an arrow  58  in FIG. 14) are provided in parallel.  
           [0006]    However, in the test coupon in the conventional printed wiring board, the direction  55 ,  56  of the arrays of the through holes  53 ,  54  crosses perpendicular to a direction  58  in which the conductor patterns  57  are elongated. Therefore, the test coupon  51  increases in size toward a direction of getting away from the edge of the printed wiring boards  52  in proportion to the number of the through holes  53 ,  54 . Consequently, there arises a problem that a projection length of the test coupon  51  to the printed wiring boards  52  becomes long, and hence the whole of the printed wiring boards  52  and the test coupon  51  becomes large-sized.  
         SUMMARY OF THE INVENTION  
         [0007]    According to one aspect of the invention, a test coupon is configured to be provided in a coupon area defined separately from a wiring board area where multi-layer printed wiring boards are arranged and configured to be used to evaluate characteristics of the multi-layer printed wiring boards which have a tested wiring layer. The test coupon includes a multi-layer substrate forming the coupon area. The multi-layer substrate includes at least first and second wiring layers, first and second through hole groups, a first conductor pattern and a second conductor pattern. The first wiring layer is configured to correspond to the tested wiring layer on which a wiring whose characteristics are to be evaluated is provided. The second wiring layer is configured to correspond to another wiring layer of the multi-layer printed wiring boards. Each of first and second through hole groups has a plurality of through holes which pass through the multi-layer substrate and which are arranged in an arranging direction. A first conductor pattern is provided on the first wiring layer and electrically connecting a first through hole of the first through hole group and a second through hole of the second through hole group. A second conductor pattern is provided on the second wiring layer and electrically connecting a third through hole of the first through hole group and a fourth through hole of the second through hole group. The first and second conductor patterns extend substantially along the arranging direction. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    A more complete appreciation of the invention and many of the attendant advantages thereof will become readily apparent with reference to the following detailed description, particularly when considered in conjunction with the accompanying drawings, in which: FIG. 1 is a front view showing printed wiring boards and a test coupon;  
         [0009]    [0009]FIG. 2 is a front view showing the enlarged test coupon;  
         [0010]    [0010]FIG. 3 is a partly enlarged view of FIG. 2;  
         [0011]    [0011]FIG. 4 is a cross-sectional view of FIG. 2 taken along line  3 - 3 ;  
         [0012]    [0012]FIG. 5( a ) is a front view showing a conductor pattern of the first layer, FIG. 5( b ) is a front view showing a conductor pattern of the third layer, FIG. 5( c ) is a front view showing a conductor pattern of the fourth layer, and FIG. 5( d ) is a front view showing a conductor pattern of the seventh layer;  
         [0013]    [0013]FIG. 6( a ) is a front view showing a conductor pattern of the eighth layer, FIG. 6( b ) is a front view showing a conductor of the tenth layer, and FIG. 6( c ) is a front view showing conductor patterns of the second, fifth, sixth, and ninth layers;  
         [0014]    [0014]FIG. 7 is a partially enlarged view of FIG. 6( c );  
         [0015]    [0015]FIG. 8 is a view showing measurement results of the conductor patterns;  
         [0016]    [0016]FIG. 9 is a schematic explanatory diagram of a micro strip line;  
         [0017]    [0017]FIG. 10 is a schematic explanatory diagram of a single-side-shielded internal layer line;  
         [0018]    [0018]FIG. 11 is a schematic explanatory diagram of a double-side-shielded internal layer line;  
         [0019]    [0019]FIG. 12 is a partially enlarged view of the test coupon showing a second embodiment of the present invention;  
         [0020]    [0020]FIG. 13 is a partially enlarged view of the test coupon showing a third embodiment of the present invention; and  
         [0021]    [0021]FIG. 14 is a front view showing the printed wiring boards and the test coupon according to the conventional art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    The preferred embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.  
         [0023]    As shown in FIG. 1, a plurality of printed wiring boards  11  are arranged in a wiring board area El. In a coupon area E 2  that projects from the edge of the wiring board area E 1  and that is defined from the wiring board area E 1  separately, a test coupon  12  is arranged.  
         [0024]    As shown in FIG. 2, a substrate  13  of this test coupon  12  is separably provided to one of the printed wiring boards  11 . The test coupon  12  is formed in the shape of a long and narrow rectangle and is provided in a protruding condition on the edge of the printed wiring board  11 . By this arrangement, a single test coupon  12  makes it possible to conduct a test for the electric connection, the nonconductivity, the characteristic impedance and the like at a time, in place of all the printed wiring boards  11 .  
         [0025]    As shown in FIG. 2 and FIG. 3 which is a partially enlarged view of FIG. 2, a first group of through holes  14 ,  31  composed of a pair of through holes is formed in an end (at the left side of FIG. 2) of the substrate  13  of the test coupon  12 . Further, a second group of through holes  15 ,  32  composed of a pair of through holes is formed in the other end (at the right side of FIG. 2) of the substrate  13 . That is, the first group of through holes  14 ,  31  and the second group of through holes  15 ,  32  are arranged at both ends of the coupon area E 2 .  
         [0026]    Each of the first and second groups of through holes  14 ,  15 ,  31 ,  32  is composed of six through holes  14   a ,  15   a ,  31   a ,  32   a , respectively. The through holes  14   a ,  15   a ,  31   a ,  32   a  are arranged side by side along the longitudinal direction of the substrate  13 , that is, along the edges of the printed wiring boards  11 .  
         [0027]    As shown in FIG. 4, the substrate  13  has a multilayer structure composed of ten layers that are identical to that of the printed wiring boards  11 , where a plurality of nonconductive bases  16  and prepregs  17  are laminated alternately. Surfaces of the prepregs  17  of the outermost layers (a first layer L 1 , a tenth layer L 10 ) are coated with solder resist, which are not shown in the figure. In this embodiment, the first layer Ll of the test coupon  12  refers to a conductor layer formed on the surface of the prepreg  17  of the uppermost part thereof; the second to ninth layers L 2  to L 9  refer to conductor layers formed between respective prepregs  17  and respective nonconductive bases  16 ; and the tenth layer L 10  refers to a conductor layer formed on the surface of the prepreg  17  of the lowermost part thereof.  
         [0028]    As shown in FIG. 4, FIG. 6( c ), and FIG. 7 which is an partially enlarged view of FIG. 6( c ), ground layers  20  to  23  are provided as the second layer L 2 , the fifth layer L 5 , the sixth layer L 6 , and the ninth layer L 9 . These ground layers  20  to  23  are formed in a generally long and narrow rectangle shape so as to cover substantially all over the substrate  13  of the test coupon  12 .  
         [0029]    As shown in FIG. 4, FIG. 5 ( a ) to FIG. 5 ( d ), FIG. 6 ( a ), and FIG. 6( b ), between the first group of through holes  14 ,  31  and the second group of through holes  15 ,  32 , a plurality of conductor patterns  24  to  29  are provided in the layers L 1 , L 3 , L 4 , L 7 , L 8 , L 10 , respectively. The conductor patterns  24 ,  29  of the first layer L 1  and the tenth layer L 10  are provided on the respective prepregs  17 . Further, conductor patterns  25  to  28  of the third layer L 3 , the forth layer L 4 , the seventh layer L 7 , and the eighth layer L 8  are provided on the nonconductive bases  16 . The conductor patterns  24  to  29  are all of the same length and a major portion of each of these patterns has a shape of a long and narrow straight strip elongated in a longitudinal direction of the substrate  13 , only the both ends thereof being bent. The direction of elongation of the conductor patterns  24  to  29  is made to agree with the direction of colinear arrangement of the through holes  14   a ,  15   a ,  31   a ,  32   a.    
         [0030]    One end of each of the conductor patterns  24  to  29  of respective layers L 1 , L 3 , L 4 , L 7 , L 8 , L 9  is connected to the through hole  14   a  of the first group of through holes  14 , respectively. The other end of each of the conductor patterns  24  to  29  is connected to the through hole  15   a  of the second group of through holes  15 , respectively.  
         [0031]    Further, one end of each of the ground layers  20  to  23  of the respective layers L 2 , L 5 , L 6 , L 9  is connected to the through hole  31   a  of the first group of through holes  31 . The other end of each of the ground layers  20  to  23  is connected to the through hole  32   a  of the second group of through holes  32 .  
         [0032]    The conductor patterns each of which is located on each of the neighboring nonconductive bases  16 , that is, the conductor patterns  25 ,  26  of the third layer L 3  and of the fourth layer L 4  are arranged in such positions that both conductor patterns do not overlap each other when viewed in the lamination direction of the nonconductive bases  16 . In other words, the conductor patterns  25 ,  26  are arranged in such positions that both patterns do not face each other in the lamination direction of the nonconductive bases  16  (a vertical direction in FIG. 4). Moreover, as is the case with the conductor patterns  25 ,  26 , the conductor patterns  27 ,  28  of the seventh layer L 7  and of the eighth layer L 8  are arranged in such positions that both conductor patterns do not overlap each other when viewed in the lamination direction of the nonconductive bases  16 . In other words, the conductor patterns  27 ,  28  are arranged in such positions that both conductor patterns do not face each other in the lamination direction of the nonconductive bases  16 .  
         [0033]    In the central part between the first and second groups of through holes  14 ,  15 ,  31 ,  32  on the surface of the substrate  13 , there is pierced a pair of marks  35 ,  36  for indicating a cutting direction when the substrate  13  is cut. Each of the marks  35 ,  36  has a circular shape and positioned in a width direction of the substrate  13 , setting a predetermined distance from each other. Further, the both marks  35 ,  36  serve as signposts so that the substrate  13  can be cut along an imaginary line connecting these marks when the substrate  13  is inspected and the like. In this embodiment, the marks  35 ,  36  are through holes.  
         [0034]    Next, usage of the test coupon in the printed wiring board that was constituted as mentioned above will be described.  
         [0035]    Before separating a plurality of printed wiring boards  11 , a test of the printed wiring boards  11  for the characteristic impedance and the like is conducted at a time using the test coupon  12 . That is, connection terminals of a test instrument not shown in the figure are connected to the respective through holes  14   a ,  15   a ,  31   a ,  32   a  of the test coupon  12 . Then measurement test of the printed wiring board  11  for the characteristic impedance and the like is conducted. In conducting the measurement of the characteristic impedance, since the conductor patterns  25 ,  26  of the layers L 3 , L 4  and the conductor patterns  27 ,  28  of the layers L 7 , L 8  are arranged in such positions that the patterns do not overlap each other when viewed in the lamination direction of the nonconductive bases  16 , the characteristic impedance can be measured accurately.  
         [0036]    Note that the characteristic impedance depends upon the width and thickness of the conductor patterns  24  to  29 . Therefore, in order to inspect the width, thickness and the like of the conductor patterns  24  to  29  of the test coupon  12 , it is necessary to cut the substrate  13  of the test coupon  12  correctly.  
         [0037]    In this case, at the time of cutting the substrate  13 , the substrate  13  is cut along the imaginary line connecting a pair of the marks  35 ,  36 . Thereby, the conductor patterns  24  to  29  are cut in a direction orthogonal to the direction of elongation of the conductor patterns. Therefore, it becomes possible to measure accurately the width and thickness of the conductor patterns  24  to  29 .  
         [0038]    Moreover, when the connection terminals of the test instrument not shown in the figure are connected to the conductor patterns  24  to  29  and variation of the reflection coefficient for the conductor patterns  24  to  29  is investigated, the results as shown in FIG. 8 are obtained. According to FIG. 8, a change of the reflection coefficient is large at positions corresponding to the both ends of the conductor patterns  24  to  29  (ranges between A and B and between C and D in FIG. 8), which indicates instability. However, a variation of the refection pattern at portions (range between B and C in FIG. 8) excluding positions of the both ends of the conductor patterns  24  to  29 , which indicates relative stability. This is because each of the conductor patterns  24  to  29  has been formed to be the straight strip, excluding the both ends thereof. Therefore, in these portions that exhibit stable reflection coefficients, the characteristic impedance can be measured accurately.  
         [0039]    In addition, it is known that the characteristic impedance can be figured out based on known approximate formulas ( 1 ) to ( 3 ) for the characteristic impedance besides direct measurement of the characteristic impedance. That is, as shown in FIG. 9, denoting an interlayer thickness as h, the conductor pattern width as ω, the conductor pattern thickness as t, the dielectric constant as ∈, and the characteristic impedance as Z0, the approximate formula for the characteristic impedance of the micro strip line (the conductor patterns  24 ,  29 ) is expressed by the following equation ( 1 ).  
               Z0   =       60       ɛ   re            L                 n                     5.97                 h         0.846                 ω                +   t                
                  ɛ   re     :                effective                 relative                 dielectric                 constant                                ɛ   re     =       0.475        ɛ   r       +   0.67                                  (   1   )                               
 
         [0040]    As shown in FIG. 10, denoting the interlayer thicknesses as h 1 , h 2 , the conductor pattern width as ω, the conductor pattern thickness as t, the dielectric constant ∈ and the characteristic impedance as Z0, the approximate formula for the characteristic impedance of the single-side-shielded internal layer line is expressed by the following equation ( 2 ). Incidentally, a lamination configuration of this type is not shown in the figure.  
               Z0   =       60       ɛ   re            L                 n                     5.97                   h   1           0.846                 ω                +   t                
                  ɛ   re     :                effective                 relative                 dielectric                 constant                                ɛ   re     =       0.475        ɛ   r       +   0.67                                  (   2   )                               
 
         [0041]    As shown in FIG. 11, denoting the interlayer thicknesses as H, the distance of the conductor from the middle of the layers as S/ 2 , the conductor pattern width as ω, the conductor pattern thickness as t, the dielectric constant ∈ and the characteristic impedance as Z0, an approximate formula for the characteristic impedance of the double-side-shielded internal layer line (the conductor patterns  25 ,  26 ,  27 ,  28 ) is expressed by the following equation ( 3 ).  
               Z0   =     376.7         ɛ   re            (     C1   +   C2   +   C3     )                
          C1   =         2      ω       (     H   -   S   -   t     )       +       2      ω       (     H   +   S   -   t     )                
          C2   =           4        (     H   -   S     )         π                   (     H   -   S   -   t     )            L                   n        (         H   -   S       H   -   S   -   t       +   1     )         -       2   π          (         H   -   S       H   -   S   -   t       -   1     )                   L                   n   (       1       (     1   -     1     H   -   S         )     2       -   1     )                
          C3   =           4        (     H   +   S     )         π                   (     H   +   S   -   t     )            L                   n        (         H   +   S       H   +   S   -   t       +   1     )         -       2   π          (         H   +   S       H   +   S   -   t       -   1     )                   L                   n   (       1       (     1   -     t     H   +   S         )     2       -   1     )                
                  ɛ   re     :                effective                 relative                 dielectric                 constant                                ɛ   re     =       0.475        ɛ   r       +   0.67                                  (   3   )                               
 
         [0042]    However, the printed wiring boards  11  may vary in their materials, manufacturing methods, and shapes of the conductor patterns  24  to  25  and the like. Therefore, if the characteristic impedance is calculated using the approximation formulas ( 1 ) to ( 3 ), there is a case where a calculated value differs largely from an actual measurement value. In such a case, it is preferable that the characteristic impedance is compensated based on a compensation formula that is obtained through actual measurement of the conductor patterns with the use of the test coupon according to the present invention that is adjusted to the specifications of the printed wiring board  11 .  
         [0043]    Therefore, according to this embodiment, the following effects can be obtained.  
         [0044]    (1) According to the test coupon  12  of the printed wiring board  11  in this embodiment, the first and second groups of through holes  14 ,  15 ,  31 ,  32  are provided at the both ends of the coupon area E 2 . Between the first and second groups of through holes  14 ,  15 , the conductor patterns  24  to  29  for electrically connecting the respective through holes  14   a ,  15   a  are provided in the form of an elongated strip. The direction of elongation of the conductor patterns  24  to  29  is made to agree with the direction of colinear arrangement of the through holes  14   a ,  15   a ,  31   a ,  32   a . By virtue of this arrangement, the test coupon  12  can be provided in a long and narrow shape along the edge of the printed wiring board  11  without increasing the dimensions of the test coupon  12  in proportion to the number of the through holes  53 ,  54 . Therefore, the projection length of the test coupon  12  to the printed wiring board  11  can be reduced and hence the whole of printed wiring boards  11  and the test coupon  12  can be smaller.  
         [0045]    ( 2 ) According to the test coupon  12  of the printed wiring board  11  in this embodiment, the through holes  14   a ,  15   a ,  31   a ,  32   a  are arranged side by side in a line parallel to the edge of the printed wiring board  11 . By this arrangement, even when the number of the through holes  14   a ,  15   a ,  31   a ,  32   a  increases, the test coupon can be in an elongated shape along the edge of the printed wiring board  11  with a slightly increased dimension in that direction. Therefore, the projection length of the test coupon  12  to the printed wiring board  11  can be shortened further.  
         [0046]    (3) According to the test coupon  12  of the printed wiring board  11  in this embodiment, the conductor patterns  25 ,  26  of the third layer L 3  and the fourth layer L 4  are arranged in such positions that the conductor patterns  25 ,  26  do not overlap each other when viewed in the lamination direction of the nonconductive bases  16 . Moreover, the conductor patterns  27 ,  28  of the seventh layer L 7  and the eighth layer L 8  are arranged in such positions that the conductor patterns  27 ,  28  do not overlap each other when viewed in the lamination direction of the nonconductive bases  16 . By this arrangement, distances between the conductor patterns  25 ,  26  and between the conductor patterns  27 ,  28 , each pair of the conductor patterns being adjacent to each other, can be secured sufficiently. Therefore, the characteristic impedance can be measured accurately.  
         [0047]    (4) According to the test coupon  12  of the printed wiring board  11  in this embodiment, each of the conductor patterns  24  to  29  is formed to be a straight strip for a major portion thereof and only the both ends thereof are bent. Further, the both ends of the conductor patterns  24  to  29  are electrically connected to the respective through holes  14   a ,  15   a . In other words, a major portion of the conductor patterns  24  to  29  exclusive of the both ends are not bent. Consequently, the reflection coefficients for portions of the conductor patterns  24  to  29 , excluding positions corresponding to the both ends can be stabilized. Therefore, the characteristic impedance can be measured much more accurately.  
         [0048]    (5) According to the test coupon  12  of the printed wiring board  11  in this embodiment, the marks  35 ,  36  are formed in the substrate  13  of the test coupon  12 . These marks  35 ,  36  serve as signposts whereby a cutting direction of the substrate  13  can be readily recognized. By this arrangement, it is possible to cut the conductor patterns  24  to  29  accurately in a direction orthogonal to the directions of elongation of the conductor patterns. Therefore, the width and thickness of the conductor patterns  24  to  29  can be measured accurately.  
         [0049]    It should be noted that the embodiment of this invention may be altered as follows.  
         [0050]    In the embodiment, the invention is put into practice in the form of the single test coupon  12  of the print circuited boards  11  that are intended to provide multiple boards. However, each one of the printed wiring boards  11  may be provided with the test coupon  12 , respectively.  
         [0051]    The number of the layers of the test coupon  12  may be altered to an arbitrary number.  
         [0052]    In the embodiment, the number of the through holes  14   a ,  31   a ,  15   a ,  32   a  of either of the groups of through holes  14 ,  15 ,  31 ,  32  was set to be six. However, this number may be altered to be any number in the range two to five, or no less than seven.  
         [0053]    As the second embodiment of the invention, an enlarged left side view of the test coupon is shown in FIG. 12. This corresponds to FIG. 3 illustrating the test coupon described above. In this example, the first group of through holes  31  is composed of the single through hole  31   a , which is arranged in the same line as the first group of through holes  14 . Although not shown in the figure, the second group of through holes is in the identical configuration. In this embodiment, the test coupon can be in a more compact form.  
         [0054]    As the third embodiment of the invention, an enlarged left side view of the test coupon is shown in FIG. 13. This view also corresponds to FIG. 3 illustrating the test coupon described above. In this example, the second embodiment is further improved to provide a test coupon such that the ground patterns are arranged on both sides of the conductor pattern  24 . Although not shown in the figure, the second group of through holes is in the identical configuration. In this embodiment, electric characteristics of the conductor pattern  24  itself with reduced external noise can be measured.  
         [0055]    According to the first embodiment of the present invention, the projection length of the test coupon to the printed wiring board can be shortened.  
         [0056]    According to the second embodiment of the present invention, in addition to the effect by the first embodiment, accurate data can be obtained when conducting the characteristic test of the printed wiring board.  
         [0057]    Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Technology Classification (CPC): 6