Patent Abstract:
A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.

Full Description:
FIELD OF THE INVENTION 
   The present invention relates generally to semiconductor device fabrication and more particularly to the formation of dummy features and inductors in semiconductor device fabrication. 
   BACKGROUND OF THE INVENTION 
   In a conventional semiconductor chip, the presence of dummy features often has a detrimental impact on the operation of an inductor of the semiconductor chip. Therefore, there is a need for a structure for the dummy features and the inductor (and a method for forming the same) in which the detrimental impact of the dummy features on the operation of the inductor is minimized. 
   SUMMARY OF THE INVENTION 
   The present invention provides a structure, comprising (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface; (b) N semiconductor regions on the substrate, N being a positive integer, wherein the N semiconductor regions comprise dopants; (c) P semiconductor regions on the substrate, P being a positive integer, wherein the P semiconductor regions do not comprise dopants; and (d) M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer, wherein the M interconnect layers include an inductor, wherein the N semiconductor regions do not overlap the inductor in the reference direction, wherein the P semiconductor regions overlap the inductor in the reference direction, and wherein a plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions. 
   The present invention provides a structure of dummy features and inductors (and a method for forming the same) in which the detrimental impacts of the dummy features on the yield of the die containing the features and to the operation of the inductor are minimized. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-1R  illustrate a fabrication process for forming a semiconductor structure, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-1Q  show cross-section views used to illustrate a fabrication process for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process starts with an SOI (Silicon On Insulator) substrate  110 + 120 + 130 . The SOI substrate  110 + 120 + 130  comprises a silicon layer  110 , a silicon dioxide layer  120  on top of the silicon layer  110 , and a silicon layer  130  on top of the silicon dioxide layer  120 . The SOI substrate  110 + 120 + 130  can be formed by a conventional method. 
   Next, with reference to  FIG. 1B , in one embodiment, shallow trench isolation (STI) regions  122  are formed in the silicon layer  130  resulting in silicon regions  130   a,    130   b,  and  130   c.  The STI regions  122  can comprise silicon dioxide. The STI regions  122  can be formed by a conventional method. In one embodiment, the silicon regions  130   a  and  130   c  are actual active silicon regions on which transistors will later be formed, whereas the silicon region  130   b  is a dummy active silicon region to provide a uniform pattern density of silicon regions across the semiconductor structure  100 . It should be noted that no transistor will be formed on the dummy active silicon region  130   b.    
   Next, with reference to  FIG. 1C , in one embodiment, a gate dielectric layer  140  is formed on top of the semiconductor structure  100  of  FIG. 1B . The gate dielectric layer  140  can comprise silicon dioxide. The gate dielectric layer  140  can be formed by thermal oxidation, nitridation, or CVD (Chemical Vapor Deposition), atomic layer deposition (for high-k dielectrics) or other known means. 
   Next, with reference to  FIG. 1D , in one embodiment, a gate electrode layer  150  is formed on top of the gate dielectric layer  140 . The gate electrode layer  150  can comprise poly-silicon, or a suitable metal, or metal/polysilicon stack. The gate electrode layer  150  can be formed by CVD, sputtering, or other means of deposition. 
   Next, in one embodiment, the gate dielectric layer  140  and the gate electrode layer  150  are patterned resulting in (i) gate dielectric regions  140   a,    140   b,  and  140   c  and (ii) gate electrode regions  150   a,    150   b,  and  150   c,  respectively, as shown in  FIG. 1E . More specifically, the gate dielectric layer  140  and the gate electrode layer  150  can be patterned using lithographic and etching processes. In one embodiment, the patterning of the gate electrode layer  150  ( FIG. 1D ) described above results in not only the gate electrode regions  150   a,    150   b,  and  150   c  ( FIG. 1E ) but also resistor regions (not shown) which can be used as resistors in semiconductor structure  100 . In one embodiment, with reference to  FIG. 1E , the actual active silicon region  130   a  and the gate electrode region  150   a  (also called an actual gate electrode region) are later used to form a PFET (p-channel field effect transistor), whereas the actual active silicon region  130   c  and the gate electrode region  150   c  (also called an actual gate electrode region) are later used to form an NFET (n-channel field effect transistor). In one embodiment, the gate electrode region  150   b  is used as a dummy gate electrode region to provide a uniform pattern density of gate electrode regions across the semiconductor structure  100 . It should be noted that the dummy gate electrode region  150   b  will not be used to form any transistor. It should be noted that the locations of the dummy active silicon region  130   b  and the dummy gate electrode region  150   b  are independent from each other. It just happens that, in  FIG. 1E , the dummy gate electrode region  150   b  overlaps the dummy active silicon region  130   b  in the vertical direction (i.e., the direction which is perpendicular to a top surface  131  of silicon layer  130  of  FIG. 1A ). 
   Next, with reference to  FIG. 1F , in one embodiment, a photoresist layer  160  is formed on top of the gate electrode regions  150   b  and  150   c  and the silicon regions  130   b  and  130   c  such that the actual active silicon region  130   a  and the actual gate electrode region  150   a  are exposed to the surrounding ambient. The photoresist layer  160  can be formed by a conventional lithographic process. 
   Next, in one embodiment, halo regions  134   a   1  and  134   a   2  and extension regions  132   a   1  and  132   a   2  are formed in the actual active silicon region  130   a.  More specifically, the halo regions  134   a   1  and  134   a   2  and the extension regions  132   a   1  and  132   a   2  can be formed by implanting ions (p-type dopants for extension regions  132   a   1  and  132   a   2  and n-type dopants for halo regions  134   a   1  and  134   a   2 ) in the actual active silicon region  130   a  using the photoresist layer  160  as a blocking mask. 
   Next, in one embodiment, the photoresist layer  160  is removed resulting in the semiconductor structure  100  of  FIG. 1  G. The photoresist layer  160  can be removed by wet etching. 
   Next, with reference to  FIG. 1H , in one embodiment, a photoresist layer  170  is formed on top of the gate electrode regions  150   b  and  150   a  and the silicon regions  130   b  and  130   a  such that the actual active silicon region  130   c  and the actual gate electrode region  150   c  are exposed to the surrounding ambient. The photoresist layer  170  can be formed by a conventional lithographic process. 
   Next, in one embodiment, halo regions  134   c   1  and  134   c   2  and extension regions  132   c   1  and  132   c   2  are formed in the actual active silicon region  130   c.  More specifically, the halo regions  134   c   1  and  134   c   2  and the extension regions  132   c   1  and  132   c   2  can be formed by implanting ions (n-type dopants for extension regions  132   c   1  and  132   c   2  and p-type dopants for halo regions  134   c   1  and  134   c   2 ) in the actual active silicon region  130   c  using the photoresist layer  170  as a blocking mask. 
   Next, in one embodiment, the photoresist layer  170  is removed resulting in the semiconductor structure  100  of  FIG. 1I . The photoresist layer  170  can be removed by plasma etching. 
   Next, with reference to  FIG. 1J , in one embodiment, spacer regions  180   a   1 ,  180   a   2 ,  180   b   1 ,  180   b   2 ,  180   c   1 , and  180   c   2  are formed on side walls of the gate electrode regions  150   a,    150   b,  and  150   c.  The spacer regions  180   a   1 ,  180   a   2 ,  180   b   1 ,  180   b   2 ,  180   c   1 , and  180   c   2  can comprise silicon nitride. The spacer regions  180   a   1 ,  180   a   2 ,  180   b   1 ,  180   b   2 ,  180   c   1 , and  180   c   2  can be formed by (i) depositing a spacer layer (not shown) on top of the semiconductor structure  100  of  FIG. 1I  and then (ii) anisotropically (vertically) etching the spacer layer resulting in the spacer regions  180   a   1 ,  180   a   2 ,  180   b   1 ,  180   b   2 ,  180   c   1 , and  180   c   2 . 
   Next, with reference to  FIG. 1K , in one embodiment, a photoresist layer  190  is formed on top of the silicon regions  130   b  and  130   c  and the gate electrode regions  150   b  and  150   c  such that the actual active silicon region  130   a  and the actual gate electrode region  150   a  are exposed to the surrounding ambient. The photoresist layer  190  can be formed by a conventional lithographic process. 
   Next, in one embodiment, source/drain regions  136   a   1  and  136   a   2  are formed in the actual active silicon region  130   a.  More specifically, the source/drain regions  136   a   1  and  136   a   2  can be formed by implanting ions (p-type dopants such as boron ions) in the actual active silicon region  130   a  using the photoresist layer  190  as a blocking mask. 
   Next, in one embodiment, the photoresist layer  190  is removed resulting in the semiconductor structure  100  of  FIG. 1L . The photoresist layer  190  can be removed by wet etching. 
   Next, with reference to  FIG. 1M , in one embodiment, a photoresist layer  192  is formed on top of the silicon regions  130   b  and  130   a  and the gate electrode regions  150   b  and  150   a  such that the actual active silicon region  130   c  and the actual gate electrode region  150   c  are exposed to the surrounding ambient. The photoresist layer  192  can be formed by a conventional lithographic process. 
   Next, in one embodiment, source/drain regions  136   c   1  and  136   c   2  are formed in the actual active silicon region  130   c.  More specifically, the source/drain regions  136   c l and  136   c   2  can be formed by implanting ions (n-type dopants such as phosphorous ions) in the actual active silicon region  130   c  using the photoresist layer  192  as a blocking mask. 
   Next, in one embodiment, the photoresist layer  192  is removed resulting in the semiconductor structure  100  of  FIG. 1N . The photoresist layer  192  can be removed by wet etching. It should be noted that because of the photoresist layers  160  ( FIG. 1F ),  170  ( FIG. 1H ),  190  ( FIG. 1K ), and  192  ( FIG. 1M ), the dummy active silicon region  130   b  and the dummy gate electrode region  150   b  are protected from ion bombardment that formed halo regions, extension regions, and source/drain regions of the PFET and the NFET mentioned above. 
   Next, with reference to  FIG. 1O , in one embodiment, a dielectric cap region  194  is formed on top of the dummy active silicon region  130   b  and the dummy gate electrode region  150   b.  More specifically, the dielectric cap region  194  can comprise a dielectric material such as silicon nitride. The dielectric cap region  194  can be formed by (i) depositing a dielectric cap layer (not shown) on top of the semiconductor structure  100  of  FIG. 1N  and then (ii) patterning the dielectric cap layer resulting in the dielectric cap region  194 . In one embodiment, said patterning the dielectric cap layer results in not only the dielectric cap region  194  but also other dielectric cap regions covering resistor regions (which are described above with reference to  FIG. 1E ) such that no surface of the resistor regions is exposed to the surrounding ambient. Because of the dielectric cap region  194 , it is more difficult for the dummy active silicon region  130   b  and the dummy gate electrode region  150   b  to fall off the semiconductor structure  100  under subsequent etching processes. In an alternative embodiment, the dielectric cap region  194  can be formed earlier. In one embodiment, the dielectric cap region  194  can be formed on top of the dummy active silicon region  130   b  and the dummy gate electrode region  150   b  in  FIG. 1E . 
   Next, with reference to  FIG. 1P , in one embodiment, (i) silicide regions  138   a   1 ,  138   a   2 , and  152   a  are formed on the source/drain regions  136   a   1  and  136   a   2  and the actual gate electrode region  150   a,  respectively, as shown, and (ii) silicide regions  138   c   1 ,  138   c   2 , and  152   c  are formed on the source/drain regions  136   c   1  and  136   c   2  and the actual gate electrode region  150   c,  respectively, as shown. The silicide regions  138   a   1 ,  138   a   2 ,  152   a,    138   c   1 ,  138   c   2 , and  152   c  can be formed by (i) depositing a metal layer (not shown) on top of the semiconductor structure  100  of  FIG. 1O , then (ii) heating the semiconductor structure  100  resulting in the metal chemically reacting with silicon of the source/drain regions and the actual gate electrode regions, and then (iii) removing unreacted metal resulting in the silicide regions  138   a   1 ,  138   a   2 ,  152   a,    138   c   1 ,  138   c   2 , and  152   c.  It should be noted that because of the dielectric cap region  194 , no silicide region is formed on top of the dummy active silicon region  130   b  and the dummy gate electrode region  150   b.  Also, because of other dielectric cap regions covering resistor regions (described above) such that no surface of the resistor regions is exposed to the surrounding ambient, no silicide region is formed on top the resistor regions as a result of the silicidation described above. It should be noted that the other dielectric cap regions covering resistor regions do not prevent the resistor regions from being doped during the formation of the halo regions, the extension regions, and the S/D regions of the structure  100  (described above). 
   Next, with reference to  FIG. 1Q , in one embodiment, a dielectric layer  196  is formed on top of the semiconductor structure  100  of  FIG. 1P . More specifically, the dielectric layer  196  can be formed by CVD of a dielectric material on top of the semiconductor structure  100  of  FIG. 1P . 
   Next, in one embodiment, contact regions (not shown) are formed in the dielectric layer  196  to provide electrical access to the source/drain regions  136   a   1 ,  136   a   2 ,  136   c   1 , and  136   c   2  and the gate electrode regions  150   a  and  150   b.    
   In summary, with reference to  FIG. 1N , in the process for forming the PFET and the NFET mentioned above, (i) no dopant enters and (ii) no silicide is formed on top of the dummy active silicon region  130   b  and the dummy gate electrode region  150   b.  As a result, the dummy active silicon region  130   b  and the dummy gate electrode region  150   b  have higher resistances than the case in which the dummy active silicon region  130   b  and the dummy gate electrode region  150   b  are not protected from ion bombardments and silicidation during the formation of the PFET and the NFET mentioned above. 
   Next, in one embodiment, one interconnect layer after another (not shown) is formed on top of the structure  100  of  FIG. 1Q . In one embodiment, the formation of the interconnect layers also results in an inductor (not shown in  FIG. 1Q  but can be seen as an inductor  220  in  FIG. 1R ). 
     FIG. 1R  shows a top-down zoom-out view of the resulting structure  100  after the formation of the interconnect layers including the inductor  220 , in accordance with embodiments of the present invention. In addition to the actual active silicon regions  130   a  and  130   c,  the structure  100  comprises other actual active silicon regions similar to the actual active silicon regions  130   a  and  130   c.  In addition to the actual gate electrode regions  150   a  and  150   c,  the structure  100  comprises other actual gate electrode regions similar to the actual gate electrode regions  150   a  and  150   c.  In addition to the dummy active silicon region  130   b,  the structure  100  comprises other dummy active silicon regions similar to the dummy active silicon region  130   b.  In addition to the dummy gate electrode region  150   b,  the structure  100  comprises other dummy gate electrode regions similar to the dummy gate electrode region  150   b.    
   In one embodiment, with reference to  FIG. 1R , each actual feature  230  can represent any one region of (i) the actual active silicon regions and (ii) the actual gate electrode regions of the structure  100 , whereas each dummy feature  240  can represent any one region of (i) the dummy active silicon regions and (ii) the dummy gate electrode regions of the structure  100 . Although the actual and dummy gate electrode regions and the actual and dummy active silicon regions can (i) overlap one another in the vertical direction, (ii) be of different sizes and shapes, and (iii) be not distributed uniformly across the structure  100  as shown in  FIG. 1Q , but in  FIG. 1R , for simplicity, the features  230  and  240  (i) do not overlap one another in the vertical direction, (ii) are of the same size and shape, and (iii) are distributed uniformly across the structure  100  of  FIG. 1R . In one embodiment, contact regions  222   a  and  222   b  are used to provide electrical access to the inductor  220 . 
   In one embodiment, all the actual features  230  do not overlap the inductor  220  in the vertical direction. In one embodiment, all the dummy features  240  were protected from ion bombardments and silicidation during the formation of the PFET and the NFET mentioned above. In one embodiment, some dummy features  240  overlap the inductor  220  in the vertical direction, whereas other dummy features  240  do not overlap the inductor  220  in the vertical direction. Alternatively, all the dummy features  240  overlap the inductor  220  in the vertical direction. 
   Assume that an electric current flows in the inductor  220 . As a result, the current creates around the inductor  220  a magnetic field (not shown) in which the dummy features  240  reside. Because the dummy features  240  were protected from the ion bombardments and the silicidation resulting in the resistances of the dummy features  240  not being reduced as in the prior art, (i) the loss of the inductance of the inductor  220  due to the presence of electrically conductive regions in the magnetic field is minimized and (ii) the energy dissipation caused by eddy currents induced by the magnetic field of the inductor  220  in the dummy features  240  is also minimized. 
   In summary, as a result of (i) the actual features  230  being away (i.e., not overlapping in the vertical direction) from the inductor  220  and (ii) the resistances of the dummy features  240  not being reduced, (i) the loss of the inductance of the inductor  220  due to the presence of electrically conductive regions in the magnetic field is minimized and (ii) the energy dissipation caused by eddy currents induced by the magnetic field of the inductor  220  in the dummy features  240  is also minimized. 
   In one embodiment, the entire inductor  220  resides in a single interconnect layer. In an alternative embodiment, the inductor  220  resides in multiple interconnect layers of the structure  100 . More specifically, the inductor  220  comprises multiple segments which are electrically coupled together by vias (not shown). 
   In the embodiments described above, the actual features  230  do not overlap the inductor  220  in the vertical direction. In an alternative embodiment, the distance from any actual feature  230  to the inductor  220  in the horizontal direction (i.e., the direction which is perpendicular to the vertical direction) is at least a pre-specified minimum distance (e.g., 3 μm). 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Classification (CPC): 7