Patent Abstract:
Disclosed herein is an arithmetic logic unit over a finite field GF(2 m ). Arithmetic logic units consistent with the present invention are disclosed as implemented using a division algorithm based on a binary greatest common divisor algorithm and a Most Significant Bit-first multiplication algorithm. The arithmetic logic unit can perform both a multiplication and a division using shared logic. Since the arithmetic logic unit has no limitations in the selection of an irreducible polynomial, and it is very regular and easily formed as a module, the arithmetic logic unit of the present invention has high expansibility and flexibility with respect to the size m of a field. Further, since the arithmetic logic unit of the present invention can perform a multiplication and a division using shared logic, it is very suitable to implement an encryption system for application products requiring a small size, such as smart cards or wireless communication devices.

Full Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   This application is related to Korean Patent Application No. 10-2003-0007226 filed Feb. 5, 2003, and takes priority from that date. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates, in general, to arithmetic logic units over a finite field GF (2 m ) and, more particularly, to an arithmetic logic unit, in which a division algorithm based on a binary greatest common divisor algorithm and a most significant bit-first multiplication algorithm share common logic such as common hardware logic, and both a multiplication and a division can be performed using the shared hardware device. 
   2. Description of the Related Art 
   As disclosed in Korean Pat. Appl. No. 1995-22327 (hereinafter referred to as “prior art”), in a conventional multiplication and division unit, a support circuit for multiplication and division operations includes first and second registers for storing input data, a first multiplexer for multiplexing outputs from the second register, an arithmetic logic unit for receiving outputs from the first register and the first multiplexer and arithmetically operating the received outputs in response to an input arithmetic control signal, a shift register capable of reading and writing signals in parallel so as to receive an output from the arithmetic logic unit, perform left and right shifting operations for a multiplication and a division and provide the arithmetic control signal, a gate connected to the arithmetic logic unit so as to gate a negative flag and an overflow flag and output the gated results, and a second multiplexer for receiving and multiplexing the output from the arithmetic logic unit, the output from the gate and the output from the first multiplexer. 
   However, the prior art is problematic in that the multiplication and division unit of the prior art is divided into structures for performing a multiplication and a division, respectively, and it is not possible to share a single hardware device and perform both a multiplication and a division using the shared hardware device, which are technical characteristics to be accomplished by the present invention. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide an arithmetic logic unit, which has functions of performing both a multiplication and a division over a finite field GF(2 m ) using a single hardware device. 
   By way of general background and as well known to those skilled in the art, arithmetic over the finite field GF(p), or Galois Field, can be useful for efficiently performing numeric calculations in computing devices. Because of its convenience in the context of binary computing devices, a finite field GF(2 m ) can be selected. The finite field GF(2), referred to as the Galois Field of order 2, consists of the set of {0, 1}. Accordingly, every element of GF(2 m ) can be expressed as a polynomial having exponents between 0 and m−1, and coefficients that are either 0 or 1. With the selection of an irreducible polynomial associated with the finite field GF(2 m ) for a given m, the coefficients associated with each polynomial term can be treated as a vector, and since the coefficients can only be zero or one, the coefficient vector can be treated as a binary integer. In this way, arithmetic operations can be carried out on the binary representations of the polynomials associated with the finite field GF(2 m ). 
   In order to accomplish the above object, the present invention provides an arithmetic logic unit over a finite field GF(2 m ) proposed to perform a multiplication algorithm of  FIG. 1  and a division algorithm of  FIG. 2 . The arithmetic logic unit comprises a control logic unit, an RS-block unit, an SR-block unit and a UV-block unit, and has a function of performing both a multiplication and a division over the finite field GF(2 m ). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a view showing a Most Significant Bit (MSB)-first multiplication algorithm according to an embodiment of the present invention; 
       FIG. 2  is a view showing a division algorithm according to an embodiment of the present invention; 
       FIG. 3  is a block diagram of an arithmetic logic unit for performing both a multiplication and a division according to an embodiment of the present invention; 
       FIG. 4  is a circuit diagram of a control logic unit of  FIG. 3 ; 
       FIG. 5  is a circuit diagram of an RS-block unit of  FIG. 3 ; 
       FIG. 6  is a circuit diagram of an SR-block unit of  FIG. 3 ; and 
       FIG. 7  is a circuit diagram of a UV-block unit of  FIG. 3 . 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. 
   Reference now should be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components. 
     FIG. 1  is a view showing a multiplication algorithm implemented according to the present invention, and  FIG. 2  is a view showing a division algorithm implemented according to the present invention. The present invention implements a multiplier and a divider capable of executing the above algorithms, respectively, analyzes the structures of the multiplier and the divider, and recognizes, on the basis of the analyzed results, that a hardware device is shareable. The present invention combines the analyzed results to design an arithmetic logic unit having a function of performing both a multiplication and division over a finite field GF (2 m ) using a single hardware device. 
     FIG. 3  is a block diagram of an arithmetic logic unit for performing both a multiplication and a division according to an embodiment of the present invention. The arithmetic logic unit includes a control logic unit  1 , an RS-block unit  2 , an SR-block unit  3  and a UV-block unit  4 , which will be described in detail with reference to  FIGS. 4 to 7 . 
   The control logic unit  1  of  FIG. 4  generates control signals required for the SR-block unit  3  and the UV-block unit  4  while outputting an externally-applied signal mult/div without change to be used as an input to select a multiplication or division operation. 
   That is, the control logic unit  1  generates the signal mult/div in response to an external control signal, and then outputs the signal mult/div to both the SR-block unit  3  and the UV-block unit  4 , thus setting an operation of the arithmetic logic unit to a multiplication or a division. 
   Further, the control logic unit  1  generates control signals Ctrl 1 , Ctrl 2 , Ctrl 3 , state and c-flag used to control the RS-block unit  2 , the SR-block unit  3  and the UV-block unit  4  so as to perform the above multiplication or division operation of the arithmetic logic unit. 
   In this case, the control logic unit  1  includes one-bit registers, state and c-flag, an OR gate El and an XOR gate D 1 , as well as AND gates G 1 , G 2 , G 3 , G 4  and G 5 . 
   The register c-flag is initialized to “1” when starting a division while operating together with the SR-block unit  3 . 
   The AND gate G 1  receives an output value state from the resister state, and also receives an output value b i /z-flag from the SR-block unit  3  through an inverter. 
   The AND gate G 2  receives an output value r 0  from the RS-block unit  2 , and also receives the output value state from the register state through an inverter. 
   The AND gate G 3  receives the output value state from the register state, and updates a value output from the register c-flag, when receiving the output value b i /z-flag from the SR-block unit  3 . 
   The AND gate G 4  receives an output value r 0  from the RS-block unit  2  and also receives an output value a 0 /v 0  from the UV-block unit  4 . 
   The AND gate G 5  receives the output value r 0  from the RS-block unit  2 , and outputs the control signal Ctrl 3  to the RS-block unit  3  when receiving the output value state from the register state through an inverter. 
   The OR gate E 1  outputs a signal used to update the value, output from the register state, using the values output from the AND gates G 1  and G 2 . 
   The XOR gate D 1  outputs the control signal Ctrl 2  to the UV-block unit  4  using the value output from the AND gate G 4 , and a value P m−1 /u 0  output from the UV-block unit  4 . 
   The register c-flag outputs the control signal c-flag to the SR-block unit  3  using the value output from the AND gate G 3 . 
   The RS-block unit  2  of  FIG. 5  performs an operation on R and S in the division algorithm of  FIG. 2 , and transmits the output value r 0  to the control logic unit  1 . 
   That is, the RS-block unit  2  is constructed by arranging a plurality of circuits in cascade, in each of which one-bit registers r and s, an AND gate G 6 , an XOR gate D 2  and a multiplexer MUX 1  are connected to each other, so that, when the control signals Ctrl 1  and Ctrl 3  are received from the control logic unit  1 , the output value r 0  is generated and output to the AND gates G 2 , G 4  and G 5  of the control logic unit  1 . 
   That is, an output value r 1  from a register r 1  is input to both the XOR gate D 2  and the multiplexer MUX 1 , which is constructed to receive a value s 1  output from the register s 1 , and the control signal Ctrl 3  output from the control logic unit  1 . 
   In this case, an output value from the multiplexer MUX 1  is input again to the register S 1  and then an output value from the register s 1  is input to one input terminal of the AND gate G 6 . The control signal Ctrl 1 , output from the control logic unit  1 , is input to the other input terminal of the AND gate G 6 . 
   The register r 0  is constructed to generate the output value r 0 , which is provided to the AND gates G 2 , G 4  and G 5  of the control logic unit  1 , when the XOR gate D 2  generates a new output value using the value output from the AND gate G 6 . 
   In  FIG. 5 , r 1 , ¼, r m−2  and r m−1  and s 2 , ¼, s m−1  and s m  represent one-bit registers, and MUX 1  represents 2-input multiplexers. 
   Meanwhile,  FIG. 6  is a detailed circuit diagram of the SR-block unit  3 . The SR-block unit  3  is constructed so that a plurality of one-bit registers b m−1 /sr 0 , b m−2 /sr 1 , ¼, b 1 /sr m−2  and b 0 /sr m−1  and two-input multiplexers MUX 2 , which are arranged in cascade, are each connected to one OR gate D 3 . 
   The OR gate D 3  receives the signal mult/div from the control logic unit  1  through an inverter, and also receives the output value state from the register state of the control logic unit  1 . 
   The multiplexers MUX 2  output signals cnt 1 , cnt 2 , ¼, cnt m−1  and cnt m  used to update the values b m−1 /sr 0 , b m−2 /sr 1 , ¼, b 1 /sr m−2  and b 0 /sr m−1 , respectively, using the output value from the OR gate D 3 , the output value c-flag from the register c-flag of the control logic unit  1 , and the output values b m−1 /sr 0 , b m−2 /sr 1 , ¼, b 1 /sr m−2  and b 0 /sr m−1 , which are fed back from the registers b m−1 /sr 0 , b m−2 /sr 1 , ¼, b 1 /sr m−2  and b 0 /sr m−1 , respectively 
   After the registers b m−1 /sr 0 , b m−2 /sr 1 , ¼, b 1 /sr m−2  and b 0 /sr m−1  are constructed to update their output values using the signals cnt 1 , cnt 2 , ¼, cnt m−1  and cnt m , which are output from the multiplexers MUX 2 , they feed back the updated values to the multiplexers MUX 2 , and to output the value b i /z-flag to the AND gates G 1  and G 3  of the control logic unit  1 . 
   In this case, the SR-block unit  3  uses m-bit bidirectional shift registers, instead of a log 2 (m+1)-bit counter, so as to implement a counter associated with the count value of the division algorithm of  FIG. 2 . 
   That is, if “0” (zero) is applied to the signal mult/div when the multiplication operation of  FIG. 1  is performed, the values from the bidirectional registers shift in only a left direction because the state value is always “1” (one). 
   Further, if “1” is applied to the signal mult/div when the division operation is performed, the values from the bidirectional registers shift in left and right directions according to the state value. 
     FIG. 7  shows the UV-block unit  4  for performing an operation on U and V in the division algorithm of  FIG. 2 . 
   Referring to  FIG. 7 , the UV-block unit  4  is constructed so that a plurality of registers P m−1 /u 0 , P m−2 /u 1 , ¼, P 1 /u m−2  and P 0 /u m−1  are connected in cascade so as to output a value P m−1 /u 0  to the XOR gate D 1  of the control logic unit  1 . 
   Further, in the UV-block unit  4 , a plurality of registers a 0 /v 0 , a m−1 /v 1 , ¼, a 2 /v m−2  and a 1 /v m−1  are connected in cascade so as to output a value a 0 /v 0  to the AND gate G 4  of the control logic unit  1 . 
   Further, in the UV-block unit  4 , multiplexers MUX 3 , AND gates G 7  and G 8 , and XOR gates D 4  and D 5  are connected in cascade so as to update values output from the registers P m−1 /u 0 , P m−2 /u 1 , ¼, P 1 /u m−2  and P 0 /u m−1  and a 0 /v 0 , a m−1 /v 1 , ¼, a 2 /v m−2  and a 1 /v m−1 . 
   Moreover, the UV-block unit  4  includes an AND gate G 9  that consistently generates “0” in the multiplication mode to allow the multiplexers MUX 3  to select the values output from the registers a 0 /v 0 , a m−1 /v 1 , ¼, a 2 /v m−2  and a 1 /v m−1  in response to the signals mult/div and Ctrl 3 , which are output from the control logic unit  1 , and an AND gate G 10  that consistently generates “0” in the division mode. 
   That is, in  FIG. 7 , the control signal Ctrl 2 , the signal P m−1 /u 0 , and the signal mult/div are input to one multiplexer MUX 3 . The control signal Ctrl 1 , the signal b i /z-flag and the signal multi/div are input to another multiplexer MUX 3 . A value output from the former multiplexer MUX 3  and a value g m−1 /g 1  are input to the AND gate G 7 . The value a m−1 /v 1  and a value output from the latter multiplexer MUX 3  are input to the AND gate G 8 . A value output from the AND gate G 8  and the value P m−2 /u 1  are input to the XOR gate D 4 . A value output from the AND gate G 7  and a value output from the XOR gate D 4  are input to the XOR gate D 5  to allow a value output from the one-bit register P m−1 /u 0  to be updated, and then the value P m−1 /u 0  is output to the control logic unit  1 . 
   Meanwhile, the signal mult/div and the control signal Ctrl 3  are input to the AND gate G 9 . When an output value from the AND gate G 9  and the output values P m−1 /u 0  and a 0 /v 0  from the one-bit registers are input to the other multiplexer MUX 3  to generate an output value, the output value is input to the one-bit register a 0 /v 0 . Therefore, the one-bit register a 0 /v 0  outputs a value a 0 /v 0  thereof to the control logic unit  1 . The output value a 0 /v 0  is re-input to the multiplexer MUX 3 . 
   In this case, the control signal mult/div is input to the AND gate G 10  through an inverter, and the output value a 0 /v 0  from the one-bit register a 0 /v 0  is also input to the AND gate G 10 . The AND gate G 10  consistently generates “0” in the division mode. 
   In this case, Table 1 compares the arithmetic logic unit of the present invention and a conventional multiplication and division unit. 
   
     
       
             
           
             
             
             
             
           
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Performance of conventional dividers and arithmetic logic unit of 
             
             
               present invention 
             
           
        
         
             
                 
                 
                 
               Arithmetic unit of the 
             
             
                 
               Brunner [1] 
               Guo [2] 
               present invention 
             
             
                 
                 
             
           
        
         
             
               Throughput (1/cycles) 
               1/2m 
               1/m 
               1/2m − 1 
             
             
               Delay (cycles) 
               2m 
               5m − 4 
               2m − 1 
             
             
               Maximum processing 
               Tzero − detector + 2T AND2  + 2T XOR  + 2T MUX2   
               T AND2  + 3T XOR2  + T MUX2   
               2T AND2  + 3T XOR2  + T XOR2   
             
             
               delay 
             
             
               Components of circuit 
               AND 2 : 3m + log 2 (m + 1) 
               AND 2 : 16m − 16 
               AND 2 : 3m + 7 
             
             
                 
               XOR 2 : 3 m + log 2 (m + 1) 
               XOR 2 : 10m − 10 
               XOR 2 : 3m + 1 
             
             
                 
               Latch: 4m + log 2 (m + 1) 
               Latch: 44m − 43 
               OR 2 : 2 
             
             
                 
               MUX 2 : 8m 
               MUX 2 : 22m − 22 
               Latch: 5m + 2 
             
             
                 
                 
                 
               MUX 2 : 3m + 2 
             
             
                 
                 
                 
               Inverter: 5 
             
             
               The number of transistors 
               110m + 18log 2 (m + 1) 
               608m − 432 
               88m + 84 
             
             
               Operation 
               Division 
               Division 
               Multiplication/division 
             
             
                 
             
             
               AND i : i-input AND gate, 
             
             
               XOR i : i-input XOR gate, 
             
             
               OR i : i-input OR gate, 
             
             
               MUX i : i-to-1 multiplexer, 
             
             
               T ANDi : transmission delay generated through one AND i  gate, 
             
             
               T XORi : transmission delay generated through one XOR i  gate, 
             
             
               T MUXi : transmission delay generated through one MUX i  gate, and 
             
             
               Tzero-detector: transmission delay generated through log 2 (m + 1)-bit zero-detector. 
             
           
        
       
     
   
   As described above, the present invention provides an arithmetic logic unit over a finite field GF (2 m ), which reduces a calculation delay and the number of transistors used to implement a required hardware device by comparing and analyzing only a divider function of the arithmetic logic unit of the present invention and those of the conventional dividers, as shown in the above Table 1. 
   Further, in the prior art, separate multiplication and division modules were used to implement an arithmetic logic unit over a finite field GF(2 m ). However, the present invention does not require separate multiplication and division modules by utilizing shared logic resources in the arithmetic logic unit. 
   Therefore, the arithmetic logic unit of the present invention is very suitable to implement an encryption system of applications requiring a small area, such as smart cards or wireless communication devices. Further, since the present invention has high expansibility and flexibility with respect to the size m of a field, it can be variously applied to arithmetic logic units over the finite field GF (2 m ), and it is very useful for industries using an encryption system. 
   Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Technology Classification (CPC): 6