Patent Abstract:
A linear decibel-scale variable gain amplifier includes an amplifying stage for generating an output voltage according to a differential input voltage, and a gain-controlling stage for outputting a gain-controlling voltage to the amplifying stage according to a first controlling voltage and a second controlling voltage. A voltage gain of the linear decibel-scale variable gain amplifier is inversely proportional to a simple exponential function, and the value of the simple exponential function is determined by the difference between the first controlling voltage and the second controlling voltage. The value of the voltage gain is unaffected by changes of the thermal voltage.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation-in-part of application of U.S. Ser. No. 10/708202 filed on Feb. 16, 2004, which is still pending. This application is related to a co-pending application “LINEAR-IN-DECIBEL VARIABLE GAIN AMPLIFIER” which belongs to the same assignee and filed on the same day with this application. 

   BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The invention relates to a variable gain amplifier, and more particularly, to a variable gain amplifier having a linear decibel-scale gain with respect to the controlling voltage(s). 
   2. Description of the Prior Art 
   Wireless communication system development continues to rapidly progress. As a result, many types of high band-width high sensitivity transceivers have been proposed. Variable gain amplifiers are often used in these types of transceiver to broaden the processing range of the system. A variable gain amplifier having a linear gain in the decibel (dB) scale with respect to the controlling voltage(s) has the broadest gain range. 
   Please refer to  FIG. 1 , where a circuit diagram of a conventional variable gain amplifier is illustrated. The variable gain amplifier shown in  FIG. 1  is a differential amplifier. The voltage gain Av of the variable gain amplifier can be determined from the half circuit of the differential amplifier. Disregarding the phase, the voltage gain Av of this variable gain amplifier is: 
                 Av   =       Vout   Vin     =     K     1   +     exp   ⁡     (     Vy   Vt     )                     (   1   )               
where K is substantially a constant.
 
   From equation 1 it can be seen that the denominator of the voltage gain Av is not a simple exponential function that it has a constant term “1” in addition to the simple exponential function exp(Vy/Vt). Consequently, the voltage gain Av does not have a simple exponential relationship with the controlling voltage Vy. 
   Please refer to  FIG. 2 .  FIG. 2  is a graph showing the relationship between the voltage gain Av and the controlling voltage Vy of  FIG. 1 . Note that when Vy&lt;Vt, the voltage gain Av does not change exponentially with respect to the change in the controlling voltage Vy. The smaller the controlling voltage Vy, the less the voltage gain Av changes with respect to the change in the controlling voltage Vy. The area where the voltage gain Av does not have a perfect exponential relationship with the controlling voltage Vy is caused by the constant term  1  in the denominator of equation 1. 
   Furthermore, equation 1 contains a term called the thermal voltage Vt, which is a variable that changes in response to the change of temperature. The result is that the relationship between the voltage gain Av and the controlling voltage Vy does not remain constant when temperature changes. 
   SUMMARY OF INVENTION 
   It is therefore one of the objects of the claimed invention to provide a variable gain amplifier having a linear voltage gain in the decibel-scale with respect to the controlling voltage(s) and which will not be influenced by changes in temperature, to solve the above-mentioned problems. 
   According to the disclosed embodiment, a variable gain amplifier comprising: an amplifying stage and a gain controlling stage. The amplifying stage is for generating an output voltage according to a differential input voltage. The gain controlling stage is for adjusting a voltage gain of the amplifying stage according to a first controlling voltage and a second controlling voltage. The gain controlling stage comprising a proportional_to_Vt voltage amplifier, a transconductance unit, a first current transforming unit, a second current transforming unit and an output unit. The gain controlling stage can generate a gain controlling voltage to control the voltage gain of the amplifying stage according to the first controlling voltage and the second controlling voltage. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a circuit diagram of a conventional variable gain amplifier. 
       FIG. 2  is a graph showing the relationship between the voltage gain Av and the controlling voltage Vy of  FIG. 1 . 
       FIG. 3  is a diagram of a variable gain amplifier according to the present invention. 
       FIG. 4  and  FIG. 5  are circuit diagrams of the gain controlling stage of  FIG. 3 . 
       FIG. 6  is a graph showing the relationship between the voltage gain Av and the difference between the first and the second controlling voltages according to equation 11. 
       FIG. 7  is a diagram of a proportional_to_Vt voltage amplifier according to the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 3  showing a schematic diagram of a variable gain amplifier  300  according to the embodiment of the present invention. The variable gain amplifier  300  comprises an amplifying stage  302  for generating an out-put voltage Vout according to an input voltage Vin and a gain controlling voltage V y . A voltage gain, i.e. the ratio between the output voltage Vout and the input voltage Vin, is determined by the gain controlling voltage V y . A gain controlling stage  304  is for generating the gain controlling voltage Vy. 
   In this embodiment, the amplifying stage  302  is substantially the same as the variable gain amplifier shown in  FIG. 1 . Concerning the amplifying stage  302  please refer to  FIG. 1  and the above description describing the variable gain amplifier shown in  FIG. 1 . Referring to equation 1, it can be seen that the value of the voltage gain of the amplifying stage  302  is determined by the gain controlling voltage Vy. 
   Next, please refer to  FIG. 4  and  FIG. 5 , where circuit diagrams of the gain controlling stage  304  according to the embodiment of the present invention are illustrated. The gain controlling stage  304  is for determining the value of the gain controlling voltage Vy output to the amplifying stage  302  according to a first controlling voltage V 1  and a second controlling voltage V 2 . In this embodiment, the gain controlling stage  304  comprises a proportional_to_Vt voltage amplifier  400 , a transconductance unit  401 , a first current transforming unit  403 , a second current transforming unit  405  (as shown in  FIG. 4 ), and an outputting unit  407  (as shown in  FIG. 5 ). 
   The proportional_to_Vt voltage amplifier  400  is for generating a third controlling voltage V 3  and a fourth controlling voltage V 4  according to V 1  and V 2 , wherein the difference (V 4 −V 3 ) is proportional to the thermal voltage Vt and the difference (V 2 −V 1 ). The operation of the proportional_to_Vt voltage amplifier  400  will be—explained later in this description. 
   The transconductance unit  401  comprises a first transistor  472  coupled to the third controlling voltage V 3 , a second transistor  473  coupled to the fourth controlling voltage V 4 , a first bias current source Ibias 1  coupled to the emitter of the first transistor  472  and the emitter of the second transistor  473  for providing a first bias current Ibias 1 , a first current source  402 , a first resistor R 1  coupled between the collector of the first transistor  472  and the first current source  402 , and a second resistor R 2  coupled between the collector of the second transistor  473  and the first current source  402 . 
   The value of the first current I 1  flowing through the collector of the second transistor  473  is determined by the first bias current Ibias 1  and the difference between the third controlling voltage V 3  and the fourth controlling voltage V 4 . In this embodiment, the relationship is as follows: 
   
     
       
         
           
             
               
                 I1 
                 = 
                 
                   Ibias1 
                   / 
                   
                     [ 
                     
                       1 
                       + 
                       
                         exp 
                         ⁡ 
                         
                           ( 
                           
                             
                               V3 
                               - 
                               V4 
                             
                             Vt 
                           
                           ) 
                         
                       
                     
                     ] 
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   Because the transconductance unit  401  is a differential circuit, the collector current of the first transistor  472  is determined by the third controlling voltage V 3 , the fourth controlling voltage V 4 , and the first bias current Ibias 1 . The relationship is similar to that shown in equation 2, only the positions of the terms V 3  and V 4  are exchanged. 
   The first current transforming unit  403  is coupled to the transconductance unit  401  through the second current source  404 . The first current transforming unit  403  comprises a third transistor  474  having the collector and the base being coupled together, a fourth transistor  475 , a second bias current source Ibias 2  coupled to the emitter of the third transistor  474  and the emitter of the fourth transistor  475  for providing a second bias current Ibias 2 , a second current source  404 , a third resistor R 3  coupled between the collector of the third transistor  474  and the second current source  404 , and a fourth resistor R 4  coupled between the collector of the fourth transistor  475  and the second current source  404 . The second current source  404  and the first current source  402  form a current mirror circuit. Additionally, in this embodiment, the ratio between the collector current I 2  of the third transistor  474  and the collector current I 1  of the second transistor  473  is the same as the ratio between the first bias current Ibias 1  and the second bias current Ibias 2 , as follows:
 
 I 2/ I 1= I bias2/ I bias1  (3)
 
   Because the first current transforming unit  403  is also a differential circuit, according to the current relationship shown in equation 3, the ratio between the collector current of the fourth transistor  475  and the collector current I 2  of the third transistor  474  is the same as the ratio between the collector current of the first transistor  472  and the collector current I 1  of the second transistor  473 . In this embodiment, when the first bias current Ibias 1  equals the second bias current Ibias 2 , the collector current of the first transistor  472  will also be equal to the collector current of the fourth transistor  475 , and the collector current I 1  of the second transistor will be equal the collector current I 2  of the third transistor. 
   The second current transforming unit  405  comprises a fifth transistor  476  having the base and the collector coupled to the base of the fourth transistor  475 , a sixth transistor  477  having the base coupled to the base and the collector of the third transistor  474 , and a seventh transistor  478  coupled to the emitter of the fifth transistor  476  and the emitter of the sixth transistor  477  for providing a third bias current Ibias 3 . Due to the loop formed between the third transistor  474 , the fourth transistor  475 , the fifth transistor  476 , and the sixth transistor  477 , the ratio between the collector current I 3  of the sixth transistor  476  and the collector current I 2  of the third transistor  474  is the same as the ratio between the third Ibias 2  and the first bias current Ibias 1 . This is shown in the following equation:
 
 I 3/ I 2= I bias3/ I bias2  (4)
 
   The second current transforming unit  405  is also a differential circuit. Similar to the relationship shown in equation 4, the ratio between the collector current I 4  of the fifth transistor  476  and the collector current I 3  of the sixth transistor  477  is the same as the ratio between the collector current of the fourth transistor  475  and the collector current I 2  of the third transistor  474 . 
   Hence, according to equations 2, 3, 4, and the relationship between I 4  and I 3  described above, the circuit shown in  FIG. 4  is a voltage controlled current amplifier. By way of changing the value of the differential input voltage, i.e. the difference between the third controlling voltage V 3  and the fourth controlling voltage V 4 , the ratio between the output currents I 3  and I 4  is controlled. The ratio is as follows: 
   
     
       
         
           
             
               
                 
                   I4 
                   I3 
                 
                 = 
                 
                   K 
                   · 
                   
                     exp 
                     ⁡ 
                     
                       ( 
                       
                         
                           V3 
                           - 
                           V4 
                         
                         Vt 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 5 
                 ) 
               
             
           
         
       
     
   
   The outputting unit  407  shown in  FIG. 5  comprises a eighth transistor  479  having the base and the collector being coupled together, a ninth transistor  480 , and a fourth bias current source I 4  coupled to the emitter of the eighth transistor  479  and the emitter of the ninth transistor  480 . Please note that the voltage controlled current amplifier shown in  FIG. 4  is coupled to the outputting unit  407  shown in  FIG. 5  through at least one current mirror device (not shown), such that the bias current output by the fourth bias current source is substantially the same as the collector current I 4  of the fifth transistor  476 , and the collector current I 3  of the sixth transistor  477  is substantially the same as the collector current I 3  of the eighth transistor  479 . Although the current mirrors are not shown, a person skilled in the art can easily design such the at least one current mirror device. At this point, the collector current of the eighth transistor  479  will be equal to the collector current I 3  of the sixth transistor  477 , and the collector current of the ninth transistor  480  will be equal to the difference between the collector current I 4  of the fifth transistor  476  and the collector current I 3  of the sixth transistor  477 . The base of the eighth transistor  479  and the base of the ninth transistor  480  are for coupling to the amplifying stage  302  and outputting the gain controlling voltage Vy. Hence, the relationship of the gain controlling voltage Vy, the collector current I 3  of the eighth transistor  479  and the collector current (I 4 −I 3 ) of the ninth transistor  480  is follows: 
   
     
       
         
           
             
               
                 Vy 
                 = 
                 
                   
                     Vt 
                     · 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I4 
                             - 
                             I3 
                           
                           I3 
                         
                         ) 
                       
                     
                   
                   = 
                   
                     Vt 
                     · 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I4 
                             I3 
                           
                           - 
                           1 
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
   
   Accordingly, disregarding the proportional_to_Vt voltage amplifier  400 , the gain controlling stage  304  is for determining the current relation in each stage of the differential circuit according to the difference between the third controlling voltage V 3  and the fourth controlling voltage V 4 , and for determining the value of the gain controlling voltage Vy according to these current relationships. Consequently, the relationship between the gain controlling voltage Vy, the third controlling voltage V 3 , and the fourth controlling voltage V 4  is as follows: 
   
     
       
         
           
             
               
                 Vy 
                 = 
                 
                   Vt 
                   · 
                   
                     ln 
                     ⁡ 
                     
                       [ 
                       
                         
                           K 
                           · 
                           
                             exp 
                             ⁡ 
                             
                               ( 
                               
                                 
                                   V3 
                                   - 
                                   V4 
                                 
                                 Vt 
                               
                               ) 
                             
                           
                         
                         - 
                         1 
                       
                       ] 
                     
                   
                 
               
             
             
               
                 ( 
                 7 
                 ) 
               
             
           
         
       
     
   
   Using the gain controlling voltage Vy output by the gain controlling stage  304  as the controlling voltage Vy of the amplifying stage  302  shown in  FIG. 1 , the voltage gain of the amplifying stage  302 , i.e. the ratio between the output voltage Vout and the input voltage Vin is as follows: 
                 Av   =       Vout   Vin     =     K1     exp   ⁡     [     K2   ⁡     (     V3   -   V4     )       ]                   (   8   )               
where K 1  relates to the output resistance RL of the amplifying stage  302 , and K 2  relates to the thermal voltage Vt of bipolar junction transistors, i.e. K 2  is proportional to 1/Vt. In this embodiment K 1  is a constant, however, the value of K 2  can be influenced by thermal voltage Vt. In other words, any factor influencing the thermal voltage can change the value of K 2 .
 
   Please refer to  FIG. 7  where an embodiment of the proportional_to_Vt voltage amplifier according to the embodiment of the present invention is illustrated. In  FIG. 7  the proportional_to_Vt voltage amplifier  700  has a single input end (V 1 ) and a single output end (V 3 ), however, it is also possible to use two amplifiers as shown in  FIG. 7  to form a differential type proportional_to_Vt voltage amplifier. 
   The proportional_to_Vt voltage amplifier  700  contains a transconductance unit  720 , a current mirror  740 , and a transresistance unit  760 . The transconductance unit  720  contains an operational amplifier  721  and a resistor R, for generating a fifth current I 5  according to the first controlling voltage V 1 , wherein I 5 =V 1 /R. The current mirror  740  is for generating a sixth current I 6  by replicating the fifth current I 5 . The transresistance unit  760  couples to the current mirror  740  and a reference voltage Vref, comprising a tenth transistor  761 , an eleventh transistor  762 , and a fourth current source Ibias 4 . Through the circuit configuration shown in  FIG. 7 , the relationship between the third controlling voltage V 3  and the first controlling voltage V 1  is as follows: 
                   V3   -   Vref     =     V1     R   ·   Gm               (   9   )               
where Gm is the transconductance of the transistors  761  and  762 . Because Gm=Ic/Vt (in this embodiment Ic is substantially equal to Ibias 4 /2), V 1 −Vref will be proportional to the thermal voltage Vt. Combining two proportional_to_Vt voltage amplifiers  700  shown in  FIG. 7  can form a differential proportional_to_Vt voltage amplifier  400  shown in  FIG. 4 , having the relationship between its inputs and outputs be as follows:
   V 4− V 3= K 3· Vt ·( V 1− V 2)  (10) 
   With the proportional_to_Vt voltage amplifier  400  combined in the gain controlling stage  304 , the voltage gain Av of the variable gain amplifier  300  will be as follows: 
                 Av   =       Vout   Vin     =     K1     exp   ⁡     [     K4   ⁡     (     V1   -   V2     )       ]                   (   11   )               
where both K 1  and K 4  are constants. The result is that the voltage gain Av of the variable gain amplifier  300  has a simple exponential relation with the first controlling voltage V 1  and the second controlling voltage V 2 , and the voltage gain Av will not be affected by the thermal voltage.
 
   Please note that the above-mentioned gain controlling stage  304  is just one possible embodiment, the scope of the present invention is not limited by the gain controlling stage. Any circuit that generates the gain controlling voltage Vy being proportional to In(Ia/Ib−K 3 ) can be used in the present invention. Wherein K 3  is a constant, Ia corresponds to the first controlling voltage V 1 , and Ib corresponds to the second controlling voltage V 2 . 
   Please refer to equation 11, through the gain controlling stage  304 , the relationship between the voltage gain Av of the amplifying stage  302 , and the difference between V 1  and V 2 , the gain is a simple exponential function, as shown in  FIG. 6 . Because there is no Vt term in equation 11, the voltage gain Av is not affected by the thermal voltage. That is the value of the voltage gain Av is independent of the thermal voltage. Additionally, in the above-mentioned embodiment, the amplifying stage has two input ends for receiving differential input voltage but only a single output end, however, the amplifying stage according to the present invention can also have two output ends for generating a differential output voltage. 
   In addition, the amplifying stage used with the present invention does not necessarily need to be as shown in  FIG. 1 . Any circuit that has a voltage gain with a denominator containing a constant term and a simple exponential function can be used with the present invention. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 7