Patent Abstract:
A semiconductor power module includes a semiconductor chip thermally interfaced to a ceramic substrate and a leadframe defined by a flexible circuit disposed intermediate the chip and the ceramic substrate. The flexible circuit includes a conductor layer that is selectively encased in an insulated jacket to ensure adequate electrical insulation between the conductor layer and adjacent conductive surfaces. Preferably, the module is constructed for double side cooling by sandwiching the chip between a pair of ceramic substrates and providing intermediate flexible circuit leadframes on both sides of the chip for electrically accessing the chip terminals.

Full Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a power module including at least one semiconductor chip, where the power module is clamped against a cold plate to dissipate heat generated by the chip, and more particularly to a power module having an improved leadframe arrangement for accessing electrical terminals of the chip. 
       BACKGROUND OF THE INVENTION 
       [0002]    Semiconductor power modules house one or more semiconductor power devices such as transistors or diodes, and can be used as components of a power circuit such as a converter or inverter. Ordinarily, the electrical terminals of the chip are wire-bonded to a metal leadframe at the periphery of the chip, and the chip and leadframe can be sandwiched between a pair of ceramic substrates that dissipate heat generated by the chip. The modules are normally constructed as flat rectangular packages that can be clamped against a cold plate (or heat sink), or even sandwiched between a pair of cold plates for double-sided cooling. In the latter case particularly, it can be difficult to ensure that there will be adequate electrical insulation between the metal leadframe of the module and the adjacent cold plates, especially in high voltage applications. A related concern arises in connection with large semiconductor transistor chips such as IGBTs and FETs where the gate terminal is coupled to segmented emitter or source terminals by an array of exposed conductive links because of the close proximity of the metal leadframe to the gate terminal links. Accordingly, what is needed is an improved semiconductor power module leadframe arrangement that is adequately insulated against inadvertent electrical shorting. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention is directed to an improved semiconductor power module including a semiconductor chip thermally interfaced to a ceramic substrate for heat dissipation and a leadframe defined by a flexible circuit disposed intermediate the chip and the ceramic substrate. The flexible circuit comprises an inner conductor pattern that is selectively encased in an insulated jacket to ensure adequate electrical insulation between the leadframe conductor pattern and adjacent conductive surfaces. Preferably, the module is constructed for double side cooling by sandwiching the chip between a pair of ceramic substrates and providing intermediate flexible circuit leadframes on both sides of the chip for electrically accessing the chip terminals. In modules including two or more semiconductor chips, separate ceramic substrates are provided for each chip for low cost and to accommodate different chip thicknesses, and a single flexible circuit leadframe provides electrical interconnects to all of the chips. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is an exploded side view of an actively or passively cooled semiconductor power module according to this invention; 
           [0005]      FIG. 2  is an exploded isometric top view of the semiconductor power module of  FIG. 1 ; 
           [0006]      FIG. 3  is an exploded isometric bottom view of the semiconductor power module of  FIG. 1 ; 
           [0007]      FIG. 4  depicts the lower face of an upper flexible circuit leadframe of the semiconductor power module of  FIG. 1 ; 
           [0008]      FIG. 5  depicts the lower face of a lower flexible circuit leadframe of the semiconductor power module of  FIG. 1 ; 
           [0009]      FIG. 6  is an isometric bottom view of the semiconductor power module of  FIG. 1 ; and 
           [0010]      FIG. 7  is a top view of the semiconductor power module of  FIG. 1 . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0011]    The present invention is directed to a power electronics module including one or more power semiconductor devices such as transistors and diodes that have solderable active areas on their opposing faces. For example, an insulated gate bipolar power transistor, or IGBT, typically has a solderable collector terminal formed on one of its faces and solderable gate and emitter terminals formed on its opposite face. The invention is described herein in the context of a power transistor switch including an IGBT (or FET) and a free-wheeling or anti-parallel diode, but it will be appreciated that the invention is applicable in general to power electronics modules including different numbers and kinds of power semiconductor devices. 
         [0012]    Referring to the drawings, and particularly to  FIG. 1 , the reference numeral  10  generally designates a semiconductor power module according to this invention designed for double-side cooling by upper and lower cold plates  12  and  14 . Referring to  FIGS. 1-3 , the illustrated module  10  houses two semiconductor chips  16  and  18 . The upper face  16   a  of chip  16  is thermally coupled to the upper cold plate  12  through a first upper ceramic substrate  20 , and the upper face  18   a  of chip  18  is thermally coupled to upper cold plate  12  through a second upper ceramic substrate  22 . Similarly, the lower face  16   b  of chip  16  is thermally coupled to the lower cold plate  14  through a first lower ceramic substrate  24 , and the lower face  18   b  of chip  18  is thermally coupled to lower cold plate  14  through a second lower ceramic substrate  26 . An upper flexible circuit leadframe  28  is disposed intermediate the chips  16 ,  18  and the upper ceramic substrates  20 ,  22  for electrically accessing terminals formed on the upper faces  16   a  and  18   a  of chips  16  and  18 . And similarly, a lower flexible circuit leadframe  30  is disposed intermediate the chips  16 ,  18  and the lower ceramic substrates  24 ,  26  for electrically accessing terminals formed on the lower faces  16   b  and  18   b  of chips  16  and  18 . As illustrated in  FIG. 1 , the upper and lower flexible circuit leadframes  28  and  30  each comprise a patterned copper layer  28   a  and  30   a  sandwiched between a pair of patterned insulation layers  28   b,    28   c  and  30   b,    30   c.    
         [0013]    For purposes of discussion, it will be assumed that chip  16  is an insulated-gate-bipolar-transistor (IGBT) and that chip  18  is a free-wheeling or anti-parallel diode. Referring to  FIG. 2 , the IGBT gate terminal  32  and a segmented array of IGBT emitter terminals  34  are formed on the upper face  16   a  of chip  16 . The diode anode terminal  36  is formed on the upper face  18   a  of chip  18 . Referring to  FIG. 3 , the IGBT collector terminal  35  is formed on the lower face  16   b  of chip  16 , and the diode cathode terminal  37  is formed on the lower face  18   b  of chip  18 . 
         [0014]    Referring to  FIGS. 2-3  and  4 , the insulation layers  28   b  and  28   c  of upper flexible circuit leadframe  28  are patterned to provide an array of un-insulated regions  38 ,  40 ,  42  that correspond and register with the gate, emitter and anode terminals  32 ,  34  and  36 . Additionally, the inboard insulation layer  28   c  is patterned to provide a set of three peripheral un-insulated regions  46 ,  48  and  50  for external access to the terminals  32 ,  34  and  36  via the exposed leadframe copper areas  52 ,  54  and  56  of copper layer  28   a.  An exposed leadframe copper pad  58  in the un-insulated region  38  is soldered to the gate terminal  32  of chip  16 , and an insulated leg  60  of the copper layer  28   a  electrically joins the copper pad  58  to the exposed peripheral copper area  52 , which serves as the gate terminal of the module  10 . Exposed leadframe copper pads  62  in the un-insulated regions  40  are soldered to the emitter terminals  34  of chip  16 , and exposed leadframe copper pads  64  in the un-insulated regions  42  are soldered to the anode terminal  36  of chip  18 . An insulated portion  66  of the copper layer  28   a  electrically joins the copper pads  62  and  64  to the exposed peripheral copper areas  54  and  56 . Thus, the insulated portion  66  of the copper layer  28   a  serves to electrically couple the emitter terminals  34  of chip  16  to the anode terminal  36  of chip  18 , and to provide electrical access to the joined emitter and anode terminals  34 ,  36  at the peripheral copper areas  54  and  56 , which serve as low voltage terminals for the module  10 . 
         [0015]    Referring to  FIGS. 2-3  and  5 , the insulation layers  30   b  and  30   c  of lower flexible circuit leadframe  30  are patterned to provide an array of un-insulated regions  70  and  72  that correspond and register with the collector and cathode terminals  35  and  37  of chips  16  and  18 . Additionally, the outboard insulation layer  30   c  is patterned to provide a set of two peripheral un-insulated regions  74  and  76  for external access to the terminals  35  and  37  via the exposed leadframe copper areas  78  and  80  of copper layer  30   a.  Exposed leadframe copper pads  82  in the un-insulated region  70  are soldered to the collector terminal  35  of chip  16 , and exposed leadframe copper pads  84  in the un-insulated region  72  are soldered to the cathode terminal  37  of chip  18 . As seen in  FIG. 5 , an insulated portion  86  of the copper layer  30   a  electrically joins the copper pads  82  and  84  to the exposed peripheral copper areas  78  and  80 . Thus, the insulated portion  86  of the copper layer  30   a  serves to electrically couple the collector terminal  35  of chip  16  to the cathode terminal  37  of chip  18 , and to provide electrical access to the joined collector and cathode terminals  35 ,  37  at the peripheral copper areas  78  and  80 , which serve as high voltage terminals for the module  10 . 
         [0016]    As best seen in  FIG. 6 , the gate terminal  52  and emitter/anode terminals  54 ,  56  provided on upper flexible circuit leadframe  28  and the collector/cathode terminals  78 ,  80  provided on lower flexible circuit leadframe  30  are all accessible on the same (lower) side of module  10 . The upper flexible circuit leadframe  28  extends laterally beyond the lower flexible circuit leadframe  30  so that the lower flexible circuit leadframe  30  does not cover the gate and emitter/anode terminals  52 ,  54 ,  56  of upper flexible circuit leadframe  28 . Of course, the terminals  52 ,  54 ,  56 ,  78 ,  80  may be variously arranged to accommodate the requirements of a given application, and the flexible nature of the leadframes  28 ,  30  allows the terminal portions to be bent out of the plane of the chips  16 ,  18  for connection to an external circuit board or bus bar, if desired. 
         [0017]    As seen in  FIGS. 2-3  and  6 - 7 , the outboard surfaces of the upper and lower ceramic substrates  20 - 26  are each clad with a metal layer (such as copper, aluminum, or any conventional thick film or thin film conductor formulation) to promote heat transfer from the module  10  to the upper and lower cold plates  12  and  14 . Additionally, the inboard surfaces of the substrates  20 - 26  bear a metal cladding that is soldered to the chips  16 ,  18  and the flexible circuit leadframes  28 ,  30 . Referring to  FIG. 2-3 , for example, the inboard face of upper ceramic substrate  20  is clad with a metallization pattern that matches and registers with the gate and emitter terminals  32 ,  34  of chip  16 . The substrate&#39;s metallization pattern is soldered to the exposed copper pads  52  and  62  of upper flexible circuit leadframe  28 , as well as the emitter terminals  34  of chip  16 . And of course, the exposed copper pads  52  and  62  of leadframe  28  are soldered to the gate and emitter terminals  32  and  34  of chip  16 . Corresponding solder joints are formed between each ceramic substrate  20 - 26  and the adjacent chip terminals and leadframe copper pads. 
         [0018]    In summary, the present invention provides an improved semiconductor power module leadframe arrangement. The disclosed leadframe arrangement offers numerous advantages when compared with conventional discrete metal leadframes. First, the use of selectively insulated flexible circuit leadframes ensures that all metal runners between soldered connections are electrically insulated from adjacent conductive components such as the cold plates  12  and  14 . Furthermore, the flexible circuit leadframes and improved cooling allow the module  10  to be considerably thinner than a conventionally semiconductor power module. The module  10  is relatively inexpensive to produce as well because the overall ceramic substrate surface area is considerably reduced compared to a module in which multiple chips are soldered to the same substrate. In the same vein, using separate ceramic substrates for each chip of a multi-chip module enables the use of chips having different thicknesses. 
         [0019]    While the present invention has been described in reference to the illustrated embodiment, it will be understood that numerous modifications and variations in addition to those mentioned above will occur to those skilled in the art. For example, the disclosed apparatus is applicable to modules housing a different number of chips, just one flexible circuit leadframe, and so on. Additionally, the flexible circuit terminals  54 - 56 ,  78 - 80  may be arranged to accommodate planar (i.e., non-pedestal) cold plates  12 ,  14 , if desired, and so forth. Accordingly, it is intended that the invention not be limited to the disclosed embodiment, but that it have the full scope permitted by the language of the following claims.

Technology Classification (CPC): 7