Patent Abstract:
A circuit and method for powering DC devices using DC voltage sources. The present invention provides an improved switching power supply that has reduced switching losses and prevents current backflow under light load conditions. The circuit operates using pulse-frequency modulation in discontinuous conduction mode for powering small loads. A rectifier circuit prevents current backflows into the DC voltage source to prevent overheating and device failure.

Full Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to switching power supply circuits. In particular, the invention relates to circuits that supply power to loads in continuous conduction mode and discontinuous conduction mode.  
         BACKGROUND OF THE INVENTION  
         [0002]    Portable electronic devices typically require the application of a regulated DC voltage in a predetermined range of voltages for satisfactory operation. Many electronic devices rely on unregulated DC supplies such as lithium-ion batteries as a power source. Batteries generally provide a voltage that is substantially fixed over short time periods but slowly decreases throughout its useful lifetime. Consequently, battery voltage is often transformed to a regulated supply voltage having a different voltage value to ensure proper operation of the electronic device.  
           [0003]    The prior art teaches many ways to accomplish this conversion. For example, some portable electronic devices use arrays of capacitors (e.g., charge pumps) to convert the source voltage into a voltage with a different polarity or magnitude. Other devices use switching power supplies to provide a regulated voltage for proper operation. Switching losses inherent in such supplies can limit the power efficiency.  
           [0004]    Certain portable electronic devices utilize unregulated DC supplies that are sensitive to current backflow. For example, lithium-ion batteries can experience heating problems or can be damaged if current flows back into the battery. Therefore, it is desirable to provide a switching power supply that prevents current backflow and minimizes switching losses.  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention relates to a circuit and method for powering DC devices using DC voltage sources. The present invention provides an improved switching power supply that has reduced switching losses and prevents load current reversal under light load conditions. The circuit operates using constant ripple current regulation in continuous and discontinuous mode operation. In discontinuous mode, this is accomplished using pulse-frequency mode modulation. A rectifier circuit prevents current backflow into the DC voltage source, which otherwise can cause overheating and device failure.  
           [0006]    In one aspect, the invention relates to a circuit for generating a regulated output voltage. In one embodiment, the circuit includes an inductor, a first switch, a pulse generator and a rectifier circuit. The inductor has a first terminal and a second terminal. The first switch has a first terminal to receive a first reference voltage, a second terminal in communication with the first terminal of the inductor, and a control terminal for receiving a first control signal. The pulse generator has an input terminal and an output terminal, which provides the first control signal, in communication with the control terminal of the first switch. The rectifier circuit has a first control input terminal in communication with the output terminal of the pulse generator, a second control input terminal in communication with the second terminal of the second switch and a third control input terminal to receive the second reference voltage.  
           [0007]    In one embodiment, the rectifier includes a first comparator, a logic module, and a second switch. The first comparator has a first terminal in communication with the second control input terminal, a second terminal in communication with the third control input terminal, and an output terminal. The logic module has a first input terminal in communication with the first control input terminal, a second input terminal in communication with the output terminal of the first comparator, and an output terminal to provide a second control signal. The second switch has a first terminal to receive a second reference voltage, a second terminal in communication with the first terminal of the inductor, and a control terminal to receive the second control signal. In another embodiment, the second terminal of the first comparator receives a small negative voltage.  
           [0008]    In another embodiment, the pulse generator includes an adaptive pulse generator and an OR gate. The adaptive pulse generator has an input terminal in communication with the input terminal of the pulse generator and an output terminal. The OR gate has a first input in communication with the output terminal of the adaptive pulse generator, a second input in communication with the input terminal of the pulse generator, and an output terminal in communication with the output terminal of the pulse generator. In yet another embodiment, the pulse generator also includes a comparator. The comparator has a first terminal in communication with the second terminal of the inductor, a second terminal to receive a third reference voltage, and an output terminal connected with the input terminal of the adaptive pulse generator. In still another embodiment, the pulse generator includes an overcurrent detector having an input terminal connected to the first inductor terminal and an output terminal connected to the first switch control terminal.  
           [0009]    In still another embodiment, the logic module includes a flip-flop and a NOR gate. The flip-flop has an input terminal in communication with the output terminal of the first comparator, a reset terminal in communication with the first control input terminal, a data terminal to receive the first reference voltage, and an output terminal. The NOR gate has a first NOR input terminal in communication with the first control input terminal, a second NOR input terminal in communication with the output terminal of the flip-flop, and an output terminal in communication with the control output terminal.  
           [0010]    In another embodiment, the second terminal of the second comparator is in communication with the second terminal of the inductor through a voltage divider network. In one embodiment, the voltage divider network includes a first resistor and a second resistor. The first resistor has a first terminal coupled to the second terminal of the second inductor, and a second terminal. The second resistor has a first terminal coupled to the second terminal of the first resistor and a second terminal to receive the second reference voltage.  
           [0011]    In another aspect, the present invention relates to a method for generating a regulated output voltage. The method includes the step of applying a first reference voltage to a series combination of an inductor and a load if an elapsed time is less than a predetermined time or if a voltage across a load is less than a first predetermined voltage. A second reference voltage is applied to the series combination of the inductor and the load if the elapsed time is greater than the predetermined time and if the load voltage is not less than the first predetermined voltage. The application of the second reference voltage is terminated if the voltage across the series combination of the inductor and the load exceeds a second predetermined voltage or if the voltage across the load does not exceed the first predetermined voltage. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    The foregoing and other objects, features and advantages of the invention will become apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed on illustrating the principles of the present invention.  
         [0013]    [0013]FIG. 1 is a functional block diagram of one embodiment of the circuit of the present invention;  
         [0014]    [0014]FIG. 2 is a chart of sample waveforms produced during the operation of the circuit of FIG. 1;  
         [0015]    [0015]FIG. 3 is a block diagram of an embodiment of the rectifier circuit of FIG. 1;  
         [0016]    [0016]FIG. 4 is a block diagram of an embodiment of the pulse generator of FIG. 1;  
         [0017]    [0017]FIG. 5 is a block diagram of an embodiment of the logic module of FIG. 3;  
         [0018]    [0018]FIG. 6 is a schematic diagram of the overcurrent detector of FIG. 4;  
         [0019]    [0019]FIG. 7 is a schematic diagram of the adaptive pulse generator of FIG. 4; and  
         [0020]    [0020]FIG. 8 is a flowchart representation of one embodiment of the method of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    In brief overview, the present invention relates to a circuit and method for providing a regulated DC voltage from a DC source. By maintaining a constant magnitude ripple component in the output current in both continuous and discontinuous conduction modes, regardless of the magnitude of the load, the present invention reduces switching losses under light load conditions. Additional functionality prevents current backflow into the DC source under light load conditions.  
         [0022]    [0022]FIG. 1 depicts one embodiment of the circuit of the present invention. The circuit includes a pulse generator  20 , a switch  28 , a rectifier circuit  32 , an inductor  40 , and a capacitor  46 . In one embodiment, the switch  28  is a field-effect transistor (FET). The circuit is designed to deliver regulated DC power to a load  10  having one terminal  12  connected to capacitor terminal  44  and a second terminal  16  connected to ground  14 .  
         [0023]    The load voltage V 0  is applied to terminal  18  of pulse generator  20 . In one embodiment, the load voltage V 0  is applied to terminal  18  through a voltage divider network (not shown). The voltage divider network provides a proportionately-scaled voltage representative of the voltage V 0 . The pulse generator  20  compares the voltage V 0  to the predetermined reference voltage and generates a signal CHG indicative of whether the voltage across load  10  is less than the reference voltage. This variable pulse width signal CHG is asserted (e.g., changed to a logical HIGH or logical 1 state) at pulse generator output terminal  24  for at least a predetermined time period. If the voltage V 0  across load  10  fails to reach the predetermined reference voltage in the predetermined time period, then the pulse generator  20  maintains the variable pulse width signal CHG in the asserted state. The variable pulse width signal CHG is desasserted when excessive current is detected in the inductor, or when the predetermined time period has elapsed and the voltage V 0  has increased to the reference value.  
         [0024]    The variable pulse width signal CHG is applied to switch terminal  26  to control closure of switch  28  and, therefore, application of DC supply voltage V cc  to the inductor terminal  38 . A change in the magnitude of the current I L  flowing through inductor  40  occurs when the switch  28  is closed. Thus, energy is stored in the inductor  40  and the voltage V 0  across load  10  increases. If the load voltage V 0  increases to match the value of the reference voltage and if the predetermined time period has expired, then the pulse generator  20  deasserts the variable pulse width signal CHG , thereby opening switch  28 . Until both conditions are satisfied, the pulse generator  20  continues to assert the variable pulse width signal CHG.  
         [0025]    When the variable pulse width signal opens switch  28 , the rectifier circuit  32  couples the first inductor terminal  38  to ground  14  at substantially the same time. As inductor  40  discharges, the inductor current I L  decreases in magnitude and capacitor  46  releases its stored charge and provides current to load  10 . At first, the current provided by capacitor  46  maintains the voltage V 0  across load  10  near the reference voltage. When the inductor current I L  and the charge in capacitor  46  sufficiently decrease, the load voltage V 0  drops below the reference voltage value. Consequently, the pulse generator  26  initiates a new charging cycle to maintain the load voltage V 0  in regulation.  
         [0026]    As long as the average load current is greater than one half of the ripple component of the load current, then the current flow I L  through the inductor  40  remains positive. This mode of operation is referred to as continuous conduction mode (CCM) because there is an uninterrupted current flowing through the inductor  40 . A complementary operating mode, referred to as discontinuous conduction mode (DCM), occurs if the current through the inductor  40  decreases to zero for a finite time during operation, such as during sleep mode. During sleep mode, only a small average current is required to maintain the load voltage V 0  in regulation. As a result, the magnitude of the ripple component of the load current exceeds the average value of the inductor current I L . Thus, the current I L  through the inductor  40  reverses direction during part of the discharge period. To avoid this backflow current that can damage some DC sources, the rectifier circuit  32  interrupts the current path to the inductor  40  shortly before reversal of the inductor current I L  can occur. Interrupting the current path allows capacitor  46  to discharge directly into load  10 , maintaining the load voltage V 0  in regulation. This mode of operation is referred to as discontinuous conduction mode (DCM) because the current flow through the inductor  40  is discontinuous.  
         [0027]    [0027]FIG. 2 illustrates the current and voltage waveforms of the circuit of FIG. 1. The waveforms on the left depict the circuit powering a load in CCM operation. The waveforms on the right depict the circuit in DCM operation. I L  depicts the current flowing through inductor  40 . During CCM operation, the inductor current I L  exhibits a ripple about an average current value I 0 . V 0  represents the value of the voltage across the load  10 . During DCM operation, the inductor current I L  includes periods during which its magnitude is zero. V olow  represents the result of the comparison of the magnitude of the load voltage V 0  and the predetermined reference voltage. During CCM operation, V olow  is true (logic HI or logic 1) when the load voltage V 0  is less than the predetermined reference voltage. T on  represents a signal having a substantially fixed predetermined duration that is generated in the pulse generator  20 . CHG represents the variable pulse width signal provided at the pulse generator output terminal  24  that maintains switch  28  closed during its asserted state. CHG is asserted for at least the predetermined minimum period, and can remain asserted for a longer period if necessary to increase the load voltage V 0  to the predetermined reference voltage. DCHG represents a signal generated within the rectifier circuit  32  that is used to control the coupling of the first inductor terminal  38  to ground  14 . UCT represents a signal generated within the rectifier circuit  32  that is used to terminate the coupling of the first inductor terminal  38  to ground  14 . Initiation of the asserted state for signal UCT occurs when the inductor current I L  decreases to near zero to avoid current reversal.  
         [0028]    [0028]FIG. 3 depicts one embodiment of the rectifier circuit  32  of FIG. 1. The rectifier circuit  32  includes a switch  62 , a comparator  68 , and a logic module  78 . The switch  62  includes a first terminal  64  in communication with input terminal  36  of the rectifier circuit  32 , a second terminal  66  connected to ground  14 , and a control terminal  60 . The comparator  68  has one input terminal  70  connected to rectifier terminal  36  and a second input terminal  72  connected to rectifier terminal  34 . By comparing the voltages at the comparator input terminals  70  and  72 , the polarity of the inductor current I L  is determined and is represented by a signal generated at the output terminal  73  of the comparator  68 . In one embodiment, the second comparator terminal  72  is connected to a small negative voltage source (not shown) instead of ground  14  to determine when the inductor current I L  has decreased to a small positive value. The logic module has one input terminal  74  connected to input terminal  30  of the rectifier circuit, a second input terminal  76  connected to the comparator output terminal  73  and an output terminal  80  in communication with the control terminal  60  of switch  62 . The logic module  78  generates a signal DCHG at its output terminal  80  for controlling switch  62  in response to the output signal CHG from the pulse generator  20  and the output signal UCT from the comparator  68 . During CCM operation, control signal DCHG is substantially complementary to the pulse generator output signal CHG. During DCM operation, the combination of control signal DCHG and signal UCT is complementary with the output signal CHG.  
         [0029]    [0029]FIG. 4 depicts one embodiment of the pulse generator  20  of FIG. 1. The pulse generator  20  includes a comparator  94 , an adaptive pulse generator  98 , an OR gate  106 , an AND gate  114  and an overcurrent detector  116 . The comparator  94  has an input terminal  90  to receive a reference voltage V REF , a second input terminal  92  in communication with input terminal  18  of the pulse generator  20 , and an output terminal  93 . The adaptive pulse generator  98  has an input terminal  96  in communication with the output terminal of comparator  94 . The OR gate  106  has an input terminal  102  in communication with output terminal  100  of the adaptive pulse generator  98 , a second input terminal  104  in communication with comparator output terminal  93 , and an output terminal  108 . The AND gate  114  has a first input terminal  110  in communication with OR gate output terminal  108 , a second complemented input terminal  112  and an output terminal  113  connected to terminal  24  of the pulse generator  20 . The overcurrent detector  116  has an input terminal  115  connected to input terminal  22  of the pulse generator  20  and an output terminal  117  connected to the complemented input terminal  112  of the AND gate  114 .  
         [0030]    In operation, comparator terminal  90  receives a reference voltage VREF representative of a desired load voltage V 0  during regulated operation and comparator terminal  92  receives a voltage representative of the instantaneous load voltage V 0 . The comparator  94  generates a signal at its output terminal  93  indicating whether the load voltage V 0  is less than the reference voltage V REF . In one embodiment, a proportionately-scaled voltage representative of the load voltage V 0  is applied to comparator terminal  92  from a voltage divider network (not shown) coupled to load terminal  12  and comparator terminal  92 .  
         [0031]    Comparator  94  provides an output signal V olow  to the adaptive pulse generator input terminal  96  and OR gate input terminal  104 . If V olow  indicates that the load voltage V 0  is less than reference voltage V REF , the adaptive pulse generator  98  asserts a signal at its output terminal  100  for a predetermined minimum time. The OR gate  106  provides an asserted signal at output terminal  108  if at least one of the signals applied to its input terminals  102  and  104  is asserted. Thus, OR gate  106  continues to assert a logical HI or logical 1 signal at terminal  108  beyond the predetermined minimum time if the comparator output signal V olow  indicates that load voltage V 0  is still less than the desired voltage V REF .  
         [0032]    The output signal from OR gate  106  is applied to AND gate input terminal  110 . The output of overcurrent detector  116  is applied to complemented AND gate input terminal  112 . When there is no excess inductor current I L , the output signal from overcurrent detector  116  is low. Consequently, the signal CHG generated by AND gate  114  is determined by the output signal from the OR gate  106 . If the inductor current I L  increases to an unacceptable level, the output signal from the overcurrent detector  116  is asserted. As a result, the pulse generator output signal CHG is deasserted or held low to reduce the inductor current I L .  
         [0033]    [0033]FIG. 5 depicts an embodiment of the logic module  78  of FIG. 3. The logic module  78  includes an edge-triggered D flip-flop  138  and a NOR gate  144 . The D flip-flop  138  has an input terminal  132  in communication with logic module input terminal  76 , a reset terminal R  130  in communication with logic module input terminal  74 , a data terminal D  134  adapted to receive a reference voltage V cc  and an output terminal Q  136 . The NOR gate  144  has one input terminal  142  in communication with logic module input terminal  74 , a second input terminal  140  in communication with the output terminal  136  of the D flip-flop  138 , and an output terminal  143  in electrical communication with logic module output terminal  80 .  
         [0034]    In CCM operation, while inductor  40  is charging, the asserted output signal CHG from the pulse generator  20  resets the flip-flop  138  so that terminal Q  136  is set low. Consequently, the output signal DCHG from NOR gate  144  is low and switch  62  is maintained in an open state. When output voltage V 0  is greater than the desired load voltage represented by V REF  and the minimum time on has expired, the output signal CHG from the pulse generator  20  is deasserted and the output signal DCHG is asserted.  
         [0035]    In DCM operation during the discharge period, the signal UCT received at input terminal  76  is asserted when the inductor current I L  decreases to zero (or a small positive value). Consequently, the signal at the output terminal Q  136  of the flip-flop  138  is asserted and the output signal DCHG of the logic module is deasserted. Switch  62  is thereby open for the remainder of the discharge period.  
         [0036]    [0036]FIG. 6 depicts one embodiment of the overcurrent detector  116  of FIG. 4. The overcurrent detector  116  includes a current monitor  160 , a comparator  162 , and a pulse generator  164 . The current monitor has an output terminal  168 . The comparator  162  has a first input terminal  170  connected to overcurrent detector input terminal  115 , a second input terminal  172  connected to current monitor output terminal  168 , and an output terminal  174 . Pulse generator  164  has an input terminal  176  connected to comparator output terminal  174  and an output terminal  178  connected to complemented AND gate input terminal  112 .  
         [0037]    The current monitor  160  applies a reference voltage at comparator terminal  172  representative of the maximum current density allowable through switch  28 . Comparator terminal  170  receives the voltage at inductor terminal  38 . When the voltage at terminal  170  decreases so that it equals the voltage representative of the maximum allowable current density while the inductor  40  is charging, the output signal of comparator  162  is asserted at output terminal  174 . Pulse generator  164  receives the comparator output signal and consequently generates a logical HIGH pulse of a predetermined minimum time at overcurrent detector output terminal  117  to indicate excess inductor current I L .  
         [0038]    [0038]FIG. 7 depicts one embodiment of the adaptive pulse generator of FIG. 4. The adaptive pulse generator  98  includes a first inverter  190 , a second inverter  192 , a first D flip-flop  194 , a second D flip-flop  196 , a delay module  198 , a current source  200 , a transistor  202 , a capacitor  204 , a current mirror  206 , an inverter  208 , and an inverter  210 . As signal V olow  is asserted, inverters  190  and  192  provide triggers to the first flip-flop  194 , thereby asserting its START signal output. Flip-flop  196  is cleared, asserting the adaptive pulse generator output signal T on  and causing the BUSYN signal output to be deasserted. Deasserting BUSYN opens switch  202 , allowing current source  200  to charge capacitor  204 . After sufficient charging of the capacitor  204 , current mirror  206  is activated so that inverters  208  and  210  trigger flip-flop  196  such that adaptive pulse generator output signal T on  is deasserted.  
         [0039]    [0039]FIG. 8 is a flowchart representation of a method for generating a regulated output voltage in accord with the present invention. A first reference voltage is applied across a series combination of an inductor and a load (Step  10 ). If a predetermined time T has elapsed (Step  12 ) and the voltage V 0  across the load is not less than a first predetermined voltage V 1  (Step  14 ), then a second reference voltage is applied across the series combination of the inductor and the load (Step  16 ). In one embodiment, the second reference voltage is ground. Application of the second voltage is terminated (Step  22 ) if the voltage across the series combination of the inductor and the load exceeds a second predetermined voltage (Step  18 ) or if the voltage V 0  across the load decreases to less than the first predetermined voltage (Step  20 ). In one embodiment, the second predetermined voltage is equal to the second reference voltage. In another embodiment, the method includes the additional step of terminating the application of the first reference voltage if the inductor current exceeds a predetermined current limit.  
         [0040]    While the invention has been particularly shown and described with reference to specific preferred embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Classification (CPC): 8