Patent Abstract:
Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate;
       (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

Full Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2007-0136399, filed on Dec. 24, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a method of fabricating a transistor having a Schottky barrier, and more particularly, to a method of fabricating a a transistor having a Schottky barrier that includes a three dimensional gate formed on a fin type channel. 
         [0004]    2. Description of the Related Art 
         [0005]    Studies have been conducted to scale down a metal oxide semiconductor field effect transistor (MOSFET) which is a unit device of a highly integrated logic circuit in order to increase performance and integration density. As the scale down of the MOSFET is progressed, a distance between source and drain is reduced, and thus, a short channel effect (SCE), that is, a phenomenon that a drain field modulates a gate field to be applied to a channel occurs resulting in the reduction of channel controllability of the gate. This phenomenon causes an electrical characteristic such as punch-through, drain-induced barrier lowering (DIBL), or threshold voltage roll-off. 
         [0006]    The SCE severely occurs in a transistor having a very short gate length, for example, 50 nm or less, and as a result, a switching function which is the basic function of the transistor may be damaged. In order to address this problem, a channel doping method, an ultra-shallow junction method, or a gate dielectric thinning method may be used. However, these methods have a limit due to attendant problems such as a random doping problem and a gate leakage. 
         [0007]    As a method of addressing the scale down problem, a transistor that has an increased contact surface between the channel and the gate by forming a three dimensional gate and has low power consumption by forming a Schottky barrier between a source and drain, and the channel. 
         [0008]    Meanwhile, when a scale down transistor is fabricated, aligning errors between a channel and a source and a drain may occur during the formation of the source and drain are formed after forming the channel due to a plurality of mask processes. 
       SUMMARY OF THE INVENTION 
       [0009]    To address the above and/or other problems, the present invention provides a method of fabricating a transistor having a Schottky barrier that may remove a scale down problem due to aligning error by using two masking processes in a direction perpendicular to each other. 
         [0010]    The present invention also provides a method of fabricating a Schottky barrier transistor that may realize low power consumption and high speed by forming a gate using a metal, in which the Schottky barrier is formed at a low temperature by forming a source and a drain prior to forming the gate. 
         [0011]    According to an aspect of the present invention, there is provided a method of fabricating a Schottky barrier transistor comprising: (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate. 
         [0012]    The annealing may be performed at a temperature of 450 to 600° C. 
         [0013]    The channel may have at least a width of 45 nm or less. 
         [0014]    The forming of the gate electrode comprises forming the gate metal layer covering three surfaces of the channel in the lengthwise direction of the channel forming portion. 
         [0015]    The substrate may be one selected from the group consisting of a group III-V semiconductor substrate, a group II-VI semiconductor substrate, and an epitaxially grown SiGe substrate. 
         [0016]    The source and the drain may be formed of a material selected from the group consisting of Ni, Pd, Pt, Ir, Rh, Co, W, Mo, Ta, Ti, and Er. 
         [0017]    The gate oxide layer may be formed of one high-k material selected from the group consisting of HfO 2 , Al 2 O 3 , La 2 O 3 , ZrO 2 , HfSiO, HfSiON, HfLaO, LaAlO, and SrTiO. 
         [0018]    The gate electrode may be formed of one material selected from the group consisting of TiAlN, MoN, TaCN, W 2 N, TaSiN, TaN, and WC. 
         [0019]    According to another aspect of the present invention, there is provided a method of fabricating a Schottky barrier transistor comprising: forming a metal layer on a silicon substrate; forming metal strips parallel to each other on both sides of a channel forming portion by patterning the metal layer; forming a source forming portion and a drain forming portion, which are metal silicide layers, on a lower side of the metal strip by annealing the silicon substrate; removing the metal strip; forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the silicon substrate; and forming a gate electrode corresponding to the channel layer by patterning the gate metal layer. 
         [0020]    The source and the drain may be formed of a material selected from the group consisting of IrSi, PtSi, Pt 2 Si, Pd2Si, RuSi, NiSi, CoSi 2 , WSi 2 , CrSi 2 , MoSi 2 , VSi 2 , ZrSi 2 , HfSi, TaSi 2 , and TiSi 2 . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
           [0022]      FIG. 1  is a schematic cross-sectional view of a structure of a Schottky barrier transistor fabricated according to an embodiment of the present invention; 
           [0023]      FIG. 2  is a cross-sectional view taken along line II-II of  FIG. 1 ; 
           [0024]      FIGS. 3A through 3D  are drawings for explaining a method of fabricating a Schottky barrier transistor according to an embodiment of the present invention; 
           [0025]      FIG. 4  is a cross-sectional view of a structure of a Schottky barrier transistor fabricated according to another embodiment of the present invention; 
           [0026]      FIG. 5  is a cross-sectional view taken along line V-V of  FIG. 4 ; and 
           [0027]      FIGS. 6A through 6D  are drawings for explaining a method of fabricating a Schottky barrier transistor according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0028]    The present invention will now be described more fully with reference to the accompanying drawings in which exemplary embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and like reference numerals refer to the like elements. 
         [0029]      FIG. 1  is a schematic cross-sectional view of a structure of a Schottky barrier transistor fabricated according to an embodiment of the present invention.  FIG. 2  is a cross-sectional view taken along line II-II of  FIG. 1 . 
         [0030]    Referring to  FIGS. 1 and 2 , a fin type channel  110  is formed in a substrate  100 , and a source  121  and a drain  122  are formed on both sides of the channel in an X direction. A gate oxide layer  130  and a gate electrode  140  are stacked on three surfaces of the fin type channel  110  in a Y direction. The gate oxide layer  130  may be further extended to cover the substrate  100 . 
         [0031]    The substrate  100  may be a silicon substrate, or may be a substrate formed of a group III-V semiconductor material such as GaAs, InGaAs, and InP or a group II-VI semiconductor material. Also, the substrate  100  may be a substrate having a SiGe layer epitaxially grown on a Si layer. 
         [0032]    The fin type channel  110  may be formed to have narrow widths W 1  and W 2 , for example, 45 nm or less. Since the fin type channel  110  may be formed by etching the substrate  100 , the fin type channel  110  and the substrate  100  may be formed as a monolithic structure. The gate oxide layer  130  and the gate electrode  140  are formed to surround the three surfaces of the fin type channel  110 , and thus, a contact area between the fin type channel  110  and the gate electrode  140  may increase. 
         [0033]    The source  121  and the drain  122  are formed of a material that forms a Schottky barrier with the fin type channel  110 . The source  121  and the drain  122  may be formed of a material having a high work function, such as Ni, Pd, Pt, Ir, Rh, etc., a material having a medium work function, such as Co, W, Mo, etc., and a material having a low work function, such as Ta, Ti, Er, etc. The metals having a high work function may be used in a p-MOS transistor and a low work function may be used in an n-MOS transistor. The metals having a medium work function may be selectively used in the n-MOS transistor or the p-MOS transistor. The source  121  and the drain  122  form a Schottky barrier with the fin type channel  110  at a relatively low temperature, for example, 450 to 600° C. 
         [0034]    In the present embodiment, since the Schottky barrier is formed by annealing the fin type channel  110 , the source  121  and the drain  122  after forming the fin type channel  110 , the source  121 , and the drain  122 , the gate oxide layer  130  and the gate electrode  140  respectively may be formed of a high-k material and a metal. Also, even though the Schottky barrier is formed after the gate oxide layer  130  and the gate electrode  140  are formed, the annealing is performed at a low temperature, and thus, the gate oxide layer  130  and the gate electrode  140  respectively may be formed of a high-k material and a metal. 
         [0035]    The gate oxide layer  130  may be formed of a high-k material such as HfO 2 , Al 2 O 3 , La 2 O 3 , ZrO 2 , HfSiO, HfSiON, HfLaO, LaAlO, SrTiO, etc. If such a high-k material is used to form the gate oxide layer  130 , the gate oxide layer  130  may be formed to have a thickness greater than a conventional silicon oxide, and thus, a transistor having a reduced leakage current and low power consumption may be realized. If the gate oxide layer  130  is formed to have a thickness 20 Å or less using a silicon oxide, the gate oxide layer  130  may not function as a gate oxide film due to a high leakage current. However, even though the high-k material having a high dielectric constant is formed to have a thickness greater than that of the silicon oxide, electrical characteristics of the high-k material may be maintained as that of the silicon oxide. When the gate oxide layer  130  is formed of the high-k material and in order to realize the same electrical characteristics as the silicon oxide, the thickness of the high-k material may be increased relative to the dielectric constant of the silicon oxide. If the high-k material having a dielectric constant of ten times greater than that of the silicon oxide is used, theoretically the thickness of the high-k material may be increased to ten times greater than that of the silicon oxide. 
         [0036]    The gate electrode  140  may be formed of TiAlN, MoN, or TaCN when a p-MOS transistor is fabricated and the gate electrode  140  may be formed of W 2 N, TaSiN, TaN, or WC when an n-MOS transistor is fabricated. Such metal gate electrode  140  enables the application of high-k material that is hard to apply to a transistor of the prior art due to a reaction between a polysilicon and the high-k material, and may realize a high speed transistor by reducing a surface resistance characteristic much lower than that of the polysilicon and removing a gate depletion phenomenon. The metal gate electrode  140  may increase an amount of current to be applied to the fin type channel  110 , and thus, may realize a high speed transistor. 
         [0037]    In a transistor having a short channel according to the present embodiment, the sizes of the source  121  and the drain  122  are reduced as the lengths of the gate and the channel  110  are reduced. However, the resistance increase due to the size reduction of the source  121  and the drain  122  may be reduced by forming the source  121  and the drain  122  using a metal. 
         [0038]    Also, a low power consumption and high speed transistor may be realized by forming a Schottky barrier between the channel  110 , and the source  121  and the drain  122  and forming the gate using a metal. 
         [0039]      FIGS. 3A through 3D  are drawings for explaining a method of fabricating a Schottky barrier transistor according to an embodiment of the present invention. 
         [0040]    Referring to  FIG. 3A , in order to form a channel forming portion  212  having a first width W 3 , cavities  220  respectively having a second width W 4  are formed on both sides of the channel forming portion  212  in a substrate  200  using a mask (not shown). The substrate  200  may be a silicon substrate, and may be a substrate formed of a group II-V semiconductor which is a high mobility material such as GaAs, InGaAs, and InP or a group II-VI semiconductor. Also, the substrate  200  may be a substrate having a SiGe layer epitaxially grown on a Si layer. The channel forming portion  212  may have a fin shape. The first width W 3  may be 45 nm or less. 
         [0041]    Referring to  FIG. 3B , a metal material  224  is deposited on the substrate  200 , and the metal material  224  is planarized using a chemical mechanical polishing (CMP) process. As a result, the cavities  220  are filled with the metal material  224  which are a source forming portion  221  and a drain forming portion  222 ′. 
         [0042]    The metal material  224  may be a metal to form a Schottky barrier with the channel forming portion  212 . The metal material  224  may be formed of a material having a high work function, such as Ni, Pd, Pt, Ir, or Rh, a material having a medium work function, such as Co, W, or Mo, and a material having a low work function, such as Ta, Ti, or Er. These metals having a high work function and a low work function respectively may be used in a p-MOS transistor and an n-MOS transistor. The metals may be selectively used according to the fabrication of the n-MOS transistor or the p-MOS transistor. 
         [0043]    A Schottky barrier is formed between the metal material  224  and the channel forming portion  212  by annealing the substrate  200  at a relatively low temperature, for example, 450 to 600° C. for approximately 10 seconds. The annealing process may be performed in a subsequent process. 
         [0044]    Referring to  FIG. 3C , a channel  210 , a source  221 , and a drain  222  are formed by patterning the channel forming portion  212  and the source forming portion  221 ′ and the drain forming portion  222 ′ using a mask having a third width W 5  in a lengthwise direction (the Y direction) of the channel forming portion  212 . In the present embodiment, small sizes of the channel  210 , the source  221 , and the drain  222  may be formed without an aligning error since the channel  210 , the source  221 , and the drain  222  are formed through two steps of patterning which are performed in perpendicular directions from each other. The third width W 5  may be 45 nm or less, and the first width W 3  and the third width W 5  may further shorter as the development of semiconductor patterning technique. 
         [0045]    Referring to  FIG. 3D , a gate oxide layer  230  covering the channel  210 , the source  221 , and the drain  222  is deposited on the substrate  200 , and a gate metal layer (not shown) is deposited on the gate oxide layer  230 . A gate electrode  240  is formed by patterning the gate metal layer. The gate oxide layer  230  and the gate electrode  240  are formed to cover three exposed surfaces of the channel  210 . 
         [0046]    The gate oxide layer  230  may be formed of a high-k material such as HfO 2 , Al 2 O 3 , La 2 O 3 , ZrO 2 , HfSiO, HfSiON, HfLaO, LaAlO, and SrTiO. 
         [0047]    The gate metal layer may be formed of TiAlN, MoN, or TaCN when a p-MOS transistor is fabricated, and may be formed of W 2 N, TaSiN, TaN, or WC when an n-MOS transistor is fabricated. 
         [0048]    Electrode pads (not shown) connected to the source  221 , the drain  222 , and the gate electrode  240  may be formed using conventional semiconductor processes, and thus, the detailed description thereof will be omitted. 
         [0049]    In the method of fabricating a Schottky barrier transistor according to an embodiment of the present invention, an aligning error is not occurred since the channel, the source, and the drain are formed using a second mask in a direction perpendicular to the first mask after forming the channel forming portion, the source forming portion, and the drain forming portion using the first mask. Also, since the source and the drain are formed prior to forming the gate, the annealing for forming the Schottky barrier may be performed ahead of forming the gate. Thus, the gate may be formed of a metal that is weak to high temperature, and may realize a transistor having a short channel. 
         [0050]      FIG. 4  is a cross-sectional view of a structure of a Schottky barrier transistor fabricated according to another embodiment of the present invention, and  FIG. 5  is a cross-sectional view taken along line V-V of  FIG. 4 . 
         [0051]    Referring to  FIGS. 4 and 5 , a fin type channel  310  is formed in a substrate  300 , and in an X direction, a source  321  and a drain  322  are formed on either side of the channel  310 . In a Y direction, a gate oxide layer  330  and a gate electrode  340  are stacked on three surfaces of the channel  310 . 
         [0052]    The substrate  300  may be a silicon substrate. 
         [0053]    The channel  310  has narrow widths W 6  and W 7 , for example, 45 nm or less. The channel  310  may be formed by patterning the substrate  300 , and thus, the channel  310  is formed in one-body with the substrate  300 . A gate oxide layer  330  and a gate electrode  340  are formed to surround three surfaces of the channel  310 , and thus, the contact area between the channel  310  and the gate electrode  340  may be increased. 
         [0054]    The source  321  and the drain  322  are metal suicides formed by metal diffusion of a metal strip (not shown) due to annealing the substrate  300  after forming the metal strip on the substrate  300 , and, in the process of annealing, the source  321  and the drain  322  form a Schottky barrier together with the channel  310 . The source  321  and the drain  322  may be formed of a material having a high work function such as IrSi, PtSi, Pt 2 Si, and Pd2Si, material having a medium work function such as RuSi, NiSi, CoSi 2 , WSi 2 , CrSi 2 , and, MoSi 2 , and a material having a low work function such as VSi 2 , ZrSi 2 , HfSi, TaSi 2 , and TiSi 2 . The metal suicides having a high work function are used to form a p-MOS transistor and the metal silicides having a low work function are used to form an n-MOS transistor. The metal silicides having a medium work function may be selectively used to form the n-MOS transistor or the p-MOS transistor. 
         [0055]    Since the annealing for forming the metal silicides and the Schottky barrier may be performed prior to forming the gate oxide  330  and the gate electrode  340 , the gate oxide layer  330  and the gate electrode  340  may be formed of a high-k material and a metal that are weak to heat. Also, although the annealing for forming the metal suicides and the Schottky barrier is performed after forming the gate oxide  330  and the gate electrode  340 , the annealing is performed at a low temperature, thus, the gate oxide layer  330  and the gate electrode  340  may be formed of a high-k material and a metal, respectively. 
         [0056]    The gate oxide layer  330  may be formed of a high-k material such as HfO 2 , Al 2 O 3 , La 2 O 3 , ZrO 2 , HfSiO, HfSiON, HfLaO, LaAlO, and SrTiO. 
         [0057]    The gate electrode  340  may be formed of TIAIN, MoN, or TaCN when a p-MOS transistor is formed, and may be formed of W 2 N, TaSiN, TaN, or WC when an n-MOS transistor is formed. 
         [0058]    In the transistor according to the present embodiment, the sizes of the source  321  and the drain  322  are reduced as the lengths of the gate and the channel  310  are reduced. However, the resistance increase due to the size reduction of the source  321  and the drain  322  may be reduced by forming the source  321  and the drain  322  using a metal silicide. 
         [0059]    Also, a transistor using low power consumption and working at a high speed may be realized since a Schottky barrier is formed in the transistor and the gate is formed of a metal. 
         [0060]      FIGS. 6A through 6D  are drawings for explaining a method of fabricating a Schottky barrier transistor according to another embodiment of the present invention. 
         [0061]    Referring to  FIG. 6A , after depositing a metal layer (not shown) on a silicon substrate  400 , metal strips  420  respectively having a second width W 9  are formed on either side of a channel forming region having a first-width W 8  by patterning the metal layer. The metal strips  420  may be formed of Ir, Pd, Pt, Ru, Ni, Co, W, Cr, Mo, V, Zr, Hf, Ta, or Ti. The metal strips  420  are formed parallel to each other. 
         [0062]    The silicon substrate  400  is annealed at a temperature of, for example, 450 to 600° C. for 10 seconds to diffuse a metal in the metal strips  420  into the silicon substrate  400 , and thus, metal silicides  420 ′ are formed on a surface of the silicon substrate  400 . 
         [0063]    Referring to  FIG. 6B , the metal strips  420  are removed by acid treatment. Thus, the metal silicides  420 ′ are formed in the silicon substrate  400 , and a channel forming portion  412  having a fin shape is formed between the metal suicides  420 ′. The metal silicides  420 ′ form a Schottky barrier between the metal suicides  420 ′ and the channel forming portion  412 . The metal silicides  420 ′ are a source forming portion and a drain forming portion. 
         [0064]    The metal suicides  420 ′ may be formed of a material having high work function such as IrSi, PtSi, Pt 2 Si, and Pd 2 Si, a material having medium work function such as RuSi, NiSi, CoSi 2 , WSi 2 , CrSi 2 , and MoSi 2 , and a material having low work function such as VSi 2 , ZrSi 2 , HfSi, TaSi 2 , and TiSi 2  according to a metal of the metal strips  420 . The metal silicides  420 ′ having a high work function are used to form a p-MOS transistor, the metal silicides  420 ′ having a low work function are used to form an n-MOS transistor, and the metal silicides  420 ′ having a medium work function may be selectively used to form the p-MOS transistor or an n-MOS transistor. 
         [0065]    Referring to  FIG. 6C , a channel  410 , a source  421 , and a drain  422  are formed by etching the channel forming portion  412  and the metal silicides  420 ′ using a mask (not shown) having a width W 10  in a lengthwise direction (a Y direction) of the channel forming portion  412 . In the present embodiment, since the channel forming portion  412  and the metal silicides  420 ′ are etched in a direction perpendicular to the lengthwise direction (the Y direction) of the channel forming portion  412 , the channel  410 , the source  421 , and the drain  422  may be precisely formed. For example, the channel  410  having small widths W 8  and W 10 , for example, 45 nm or less may be formed. 
         [0066]    Referring to  FIG. 6D , a gate oxide layer  430  covering the channel  410 , the source  421 , and the drain  422  is deposited on the silicon substrate  400 , and a gate metal layer (not shown) is deposited on the gate oxide layer  430 . A gate electrode  440  is formed by patterning the gate metal layer. The gate oxide layer  430  and the gate electrode  440  are formed to cover three exposed surfaces of the channel  410 . 
         [0067]    The gate oxide layer  430  may be formed of a high-k material such as HfO 2 , Al 2 O 3 , La 2 O 3 , ZrO 2 , HfSiO, HfSiON, HfLaO, LaAlO, and SrTiO. 
         [0068]    The gate electrode  440  may be formed of TiAlN, MoN, or TaCN when a p-MOS transistor is fabricated, and may be formed of W 2 N, TaSiN, TaN, or WC when an n-MOS transistor is fabricated. 
         [0069]    Electrode pads (not shown) connected to the source  421 , the drain  422 , and the gate electrode  440  may be formed using conventional semiconductor processes, and thus, the detailed description thereof will be omitted. 
         [0070]    In the method of fabricating a Schottky barrier transistor according to another embodiment of the present invention, an aligning error is not occurred since the channel  410 , the source  421 , and the drain  422  are formed using a second mask in a direction perpendicular to the first mask after forming the channel forming portion, the source forming portion, and the drain forming portion using the first mask. Also, since the source  421  and the drain  422  are formed prior to forming the gate, the annealing for forming the Schottky barrier may be performed ahead of forming the gate. Thus, the gate may be formed of a material that is weak to high temperature, and may realize a transistor having a short channel in which the controllability of the gate is improved. 
         [0071]    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Technology Classification (CPC): 7