Patent Abstract:
An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Korean Patent Application No. 10-2008-0037747, filed on Apr. 23, 2008, the disclosure of which is incorporated by reference herein. 
     BACKGROUND 
     1. Technical Field 
     Embodiments of the present invention relate to emulation systems, and more particularly to an emulation system and a driving method to shorten a data transmission time between an external computer and an emulation board. 
     2. Discussion of Related Art 
     Emulation systems are used to verify intellectual properties (IPs) or products including IPs (e.g., a device-under-test (DUT)). A DUT can be verified in less time using an emulation system as compared to using a simulation. 
     Field programmable gate arrays (FPGAs) may also be utilized when emulating products including IPs. Xilinx™ LX330 is an FPGA that is equipped with about 2,500,000 gates and 900 primary input/output pins. A DUT including an IP formed of tens of millions of gates may be emulated by several FPGAs. 
     For example, assume that a DUT is emulated by means of two LX330 FPGAs. The internal signal lines between the two FPGAs are connected through external input/output pins of the FPGAs. If the number of internal signal lines between the two FPGAs is 9,000, 9,000 signal lines may be interconnected to each other using time division multiplexing at a ratio of 10 multiplexers for every 1 demultiplexer. Due to the inordinate amount of signal lines, it may take a long time to emulate the DUT and transfer results of the emulation to an external computer. 
     Thus, there is a need for emulation systems that can transmit data to an external computer in less time and methods of driving such emulating systems. 
     SUMMARY OF THE INVENTION 
     An exemplary embodiment of the present invention includes an emulation system including: a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit. The first circuit is separate from second circuit. The emulation system may be configured to verify an intellectual property of the device. 
     The emulation system may be connected to a computer through a bus. The bus may include one of small computer system interface (SCSI), peripheral component interconnection (PCI), peripheral component interconnection express (PCI-E), serial advanced technology attachment (S-ATA), parallel advanced technology attachment (P-ATA), or a universal serial bus (USB). 
     The third circuit may be a time division connector. Each of the first and second circuits may include a flipflop and a state value of the flipflop of the first circuit may be transferred to the flipflop of the second circuit through the time division connector while resultant data of the first through third circuits is sent to an external source (e.g., a computer). 
     The emulation system may include a controller for controlling a normal clock for output to the first and second circuits and controlling a shift clock and a selection signal for output to the third circuit. The third circuit may be a time division connector that connects the first circuit to the second circuit in a time division manner and operates in sync with the shift clock. 
     The computer may transfer input data to the first and second circuits, for verifying the first and second circuits, and receive output data of the first and second circuits from an emulation board of the emulation system. 
     The time division connector may includes a plurality of multiplexers receiving signals from output pins of the first and second circuits in response to the selection signal of the controller, and a plurality of demultiplexers transferring signals from the plurality of multiplexers to input pins of the first and second circuits in response to the selection signal of the controller. 
     Flipflops of the first and second circuits may be synchronized to a normal clock and flipflops of the time division connector may be synchronized to a shift clock. The first and second circuits may be formed of field programmable gate arrays. 
     An exemplary embodiment of the present invention includes a method of driving an emulation system with an emulation board including: separate first and second emulators configured to respectively emulate first and second logical parts of a device. The method may be used to verify an intellectual property of the device. The emulation board may be connected to a computer through a bus. The driving method includes transferring input data to the emulation board, applying input data to inputs of the first and second circuits through the emulation board, operating the first and second chips for one normal clock cycle, operating a time division connector connecting the first circuit and the second circuit for one shift clock cycle, transferring output data of the first and second circuits to the emulation board, and setting state values of flipflops of the first and second circuits and transferring the output data to the computer. 
     An exemplary embodiment of the present invention includes a method of driving an emulation system with an emulation board including: separate first and second emulators configured to respectively emulate first and second logical parts of a device. The method includes transferring verification data to the first and second circuits, operating the first and second circuits for a cycle of a clock, and transferring a state value of the first circuit to the second circuit while sending output data of the first and second circuits to an external source. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       Embodiments of the present invention will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified. In the figures: 
         FIG. 1  is a block diagram of a hardware emulation system according to an exemplary embodiment of the present invention; 
         FIG. 2  is a flow chart showing an emulation method including a feed-through path, according to an exemplary embodiment of the present invention; 
         FIG. 3  illustrates durations of steps of the emulation method shown in  FIG. 2 ; 
         FIG. 4  is a block diagram showing a first device divided into first and second logic blocks; 
         FIG. 5  is a block diagram illustrating first and second emulators respectively emulating the first and second logic blocks of  FIG. 4 , according to an exemplary embodiment of the present invention; 
         FIG. 6  is a circuit diagram that illustrates modifications that may be made to the emulators of  FIG. 5  to skip a shifting operation time; 
         FIG. 7  is a circuit diagram of a second device including a circuit with a feed-through path; 
         FIG. 8  is a block diagram showing first and second emulators emulating the second device of  FIG. 7 , according to an exemplary embodiment of the present invention; 
         FIG. 9  is a block diagram that illustrates modifications that may be made to the emulators of  FIG. 8  to remove a feed-through path, according to an exemplary embodiment of the present invention; 
         FIG. 10  is a block diagram of a third device; 
         FIG. 11  is a block diagram showing first and second hardware emulators emulating the third device of  FIG. 10 , according to an exemplary embodiment of the present invention; 
         FIG. 12  is a block diagram of a fourth device; 
         FIG. 13  is a block diagram showing first and second hardware emulators emulating the fourth device of  FIG. 12 , according to an exemplary embodiment of the present invention; 
         FIG. 14  is a block diagram illustrating modifications that may be made to the emulators of  FIG. 13  to remove a feed-through path, according to an exemplary embodiment of the present invention; 
         FIG. 15  is a flow chart showing a method of driving an emulation system according to an exemplary embodiment of the present invention; and 
         FIG. 16  illustrates durations of steps of the emulation method shown in  FIG. 15 . 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Embodiments of the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Hereinafter, exemplary embodiments of the present invention will be described in conjunction with the accompanying drawings. 
       FIG. 1  is a block diagram of a hardware emulation system according to an exemplary embodiment of the present invention. Referring to  FIG. 1 , the hardware emulation system  100  is comprised of a hardware emulation board  50  for verifying a DUT, and a computer  60  connected to the hardware emulation board  50  through a bus  70 . 
     In at least one embodiment of the present invention the bus  70  is a peripheral component interconnection (PCI). However, the computer  60  may be connected with the hardware emulation board  50  through other means such as serial advanced technology attachment (S-ATA), parallel advanced technology attachment (P-ATA), small computer system interface (SCSI), or universal serial bus (USB) (e.g., USB 2.0). The hardware emulation board  50  includes first and second hardware emulators  10  and  20 , a time-division connector  30 , and a controller  40 . 
     An IP having millions of gates or a DUT including such an IP may be verified by means of hardware emulation by dividing the IP or DUT into unit logic blocks having verifiable gates counts. Hardware emulation may operate by employing an FPGA. When a Xilinx™ LX330 is used, an IP or DUT may need to be divided into separate blocks under 2,500,000 gates to be verified. 
     A DUT to be verified may be divided into first and second logic blocks, which have gate counts similar to each other. The DUT may be divided by commercial tools. The first hardware emulator  10  emulates the first logic block and the second hardware emulator  20  emulates the second logic block. By dividing a DUT with a gate count of millions into the first and second logic blocks, thousands of signal lines may be generated between the first and second logic blocks. 
     In one embodiment of the present invention, it is assumed that each of the first and second hardware emulators  10  and  20  is an LX330, which includes 2,500,000 gates and 900 external input/output pins. A time-division connection method may be employed for linking 10,000 internal lines of the emulators  10  and  20  with each other by way of the 900 input/output pins. 
     The time-division connection method may be carried out by sequentially exchanging up to 10,000 internal signals between the first hardware emulator  10  and the second hardware emulator  20  using multiplexers and demultiplexers of a time-division connector  30  in response to a shift clock s_clk (e.g., during a shift operation). 
     The time-division connector  30  operates in a time-division mode. The time-division connection method will be discussed with reference to  FIG. 5 . A controller  40  controls the first and second hardware emulators  10  and  20  using a normal clock n_clk. The controller  40  operates the time-division connector  30  using a shift clock s_clk and a selection signal sel[n:1]. The shift clock s_clk may be a shifted version of the normal clock n_clk. For example, the shift clock s_clk may be out of phase with the normal clock n_clk by a certain angle. 
     The computer  60  is connected to the hardware emulation board  50  through the bus  70  (e.g., a PCI bus). The first and second hardware emulators  10  and  20  are mounted on the hardware emulation board  50 . The computer  60  may apply verification data through the bus  70  to verify the first and second hardware emulators  10  and  20  and accept a result of processing the verification data therefrom. 
     A single DUT may be divided into first and second logical parts for respective emulation by the first and second hardware emulators  10  and  20 . Paths connected between from primary inputs PI and primary outputs PO of the first and second logical parts can be sorted into feed-through paths and non-feed-through paths. A feed-through path is a path from a primary input PI to a primary output PO that does not include latching (or storing) by a storage device, such as a flipflop. A feed-through path will be discussed later in conjunction with  FIG. 4 . A non-feed-through path is a path from a primary input PI to primary output PO without a feeding-through. The non-feed-through path includes storage by a storage device (e.g., a flipflop) on the way from the primary input PI to the primary output PO. 
     A DUT may be divided into first and second parts for respective emulation by the first and second hardware emulators  10  and  20  by granting priority to an area (e.g., a number of gates) of the DUT. Thus, the aforementioned feed-through path may be present in the first hardware emulator  10 , the second hardware emulator  20 , or the first and second hardware emulators  10  and  20 . 
     Embodiments of feed-through paths present in the first hardware emulator  10  are shown in  FIGS. 4 and 5 . The feed-through paths extend from the primary inputs PI of the first hardware emulator  10  to the time-division connector  30 . 
     If the feed-through paths are in the first hardware emulator  10  from the primary inputs PI to the time-division connector  30 , verification data received by the primary inputs PI may be transferred to the second hardware emulator  20  through the time-division connector  30  before activation of the normal clock n_clk of the first hardware emulator  10 . 
     An operation of transferring verification data received by the primary inputs PI to the second hardware emulator  20  through the time-division connector  30  before activation of the normal clock n_clk of the first hardware emulator  10 , is referred to as a ‘shifting for backend data transfer (BDT)’. Conducting or skipping the shifting for BDT will be discussed with reference to  FIGS. 5 and 6 . 
     An unlatched path is present from the primary inputs PI of the first hardware emulator  10  to the primary outputs PO of the second hardware emulator  20  through the time-division connector  30 . In an unlatched path, verification data may be transferred to the second hardware emulator  20  through the time-division connector  30  before activation of the normal clock n_clk of the first hardware emulator  10 . An unlatched path will be discussed with reference to  FIGS. 7 and 8 . 
     An operation that verification data provided into the primary inputs PI of the first hardware emulator  10  is transferred to the second hardware emulator  20  through the non-division connector  30  before activation of the normal clock n_clk of the first hardware emulator  20  is referred to as a ‘shifting for frontend data transfer (FDT)’. Conducting or skipping the shifting for FDT will be discussed with reference to  FIGS. 12 and 13 . 
       FIG. 2  is a flow chart showing an emulation method according to an exemplary embodiment of the present invention, which may be used when a feed-through path is present. Referring to  FIGS. 1 and 2 , the computer  60  prepares new input data for verifying the first and second hardware emulators  10  and  20 . The computer  60  determines pass/fail states of the first and second hardware emulators  10  and  20  by comparing an expected output of the emulators against an actual output of the emulators. For example, the computer compares output data of the emulators with previous input data for verifying the first and second hardware emulators  10  and  20  (S 11 ). 
     Thereafter, the computer  60  transfers new input data to the hardware emulation board  50  for verifying the first and second hardware emulators  10  and  20  (S 12 ). Then, the first and second hardware emulators  10  and  20  receive the new input data from the hardware emulation board  50  (S 13 ). The first and second hardware emulators  10  and  20  execute shifting for BDT in sync with the shift clock s_clk (S 14 ). The first and second hardware emulators  10  and  20  conduct a normal operation in one clock cycle in sync with the normal clock n_clk (S 15 ). The first and second hardware emulators  10  and  20  conduct the shifting for FDT in sync with the shift clock s_clk (S 16 ). The first and second emulators  10  and  20  transfers output data to the hardware emulation board  50  (S 17 ). Then, the hardware emulation board  50  transfers the output data to the computer  60  (S 18 ). 
     The computer  60  determines whether there is other input data to be used for verifying the first and second hardware emulators  10  and  20 . If there is new input data, then step S 11  is resumed. Unless there is new input data, the emulation procedure for the hardware emulation system  100  is terminated (S 19 ). 
       FIG. 3  illustrates durations of steps of the emulation method shown in  FIG. 2 . Referring to  FIGS. 2 and 3 , the operating steps (S 11  to S 18 ) are correspondent to one clock cycle of the first and second hardware emulators  10  and  20 . The step S 11  corresponds to a time t A1 . The step S 12  corresponds to a time t A2 . The step S 13  corresponds to a time t A3 . The step S 14  corresponds to a time t A4 . The step S 15  corresponds to a time t A5 . The step S 16  corresponds to a time t A6 . The step S 17  corresponds to a time t A7 . The step S 18  corresponds to a time t A8 . As a result, one clock cycle of the first and second hardware emulators  10  and  20  is a sum of the times from t A1  to t A8 . Thus, one clock cycle of the emulation system conducting the shifting operations for BDT and FDT is a sum of the times from t A1  to t A8 . 
       FIG. 4  is a block diagram showing a dividing of a first device DUT 1  into first and second logic blocks. Referring to  FIG. 4 , the first device DUT 1  is divided into the first and second logic blocks Logic 1  and Logic 2  (e.g., by means of a commercial tool). A BDT path is generated when the first device DUT 1  is divided into the first and second logic blocks Logic 1  and Logic 2 . In the first logic block Logic 1 , the BDT path is connected from the primary input PI_ 0  to a port  10  that is an interface between the first and second logic blocks Logic 1  and Logic 2 , without passing through a storage device such as a flipflop. The BDT path includes passage through an input node a of an AND gate Inst 0  and an output node of the AND gate Inst 0 . The BDT path is illustrated by a thick broken line in  FIG. 4 . 
     With the BDT path, if the hardware emulators are formed by dividing the first device DUT 1  into the two logic blocks Logic 1  and Logic 2 , signals on their boundary are transferred during a shifting operation, but not during a normal clock operation. If a hardware emulator according to an exemplary embodiment of the present invention includes the BDT path, the shifting operation may be skipped, as will be discussed in conjunction with  FIG. 6 . 
     In the second logic block Logic 2 , the input node a of the AND gate Inst 1  is connected to the primary input PI_ 0  and an input node b of the AND gate Inst 1  is connected to an output of a sixth combination circuit Comb 6  of the second logic block Logic 2 . If the first and second logic blocks Logic 1  and Logic 2  are respectively emulated by the hardware emulators, the boundary between the first and second logic blocks Logic  1  and Logic 2  is connected to external input/output (IO) pins of the hardware emulators. In a normal operation, signals are transferred into the first and second logic blocks Logic 1  and Logic 2 . Signals from the boundary between the first and second logic blocks Logic 1  and Logic 2  are transferred thereinto during the shifting operation. Thus, an output of the AND gate Inst 0  is transferred to an input node a of an AND gate Inst 1  during the shifting operation, and an output of the sixth combination circuit Comb 6  is transferred to the input node b of the AND gate Inst 1  during the normal operation. 
       FIG. 5  is a block diagram illustrating first and second emulations  10  and  20  emulating the first and second logic blocks, according to an exemplary embodiment of the present invention. Referring to  FIGS. 4 and 5 , the first logic block Logic 1  is emulated by the first hardware emulator  10  while the second logic block Logic 2  is emulated by the second hardware emulator  20 . The first and second emulators  10  and  20  according to an exemplary embodiment of the present invention are made of FPGAs. 
     The first hardware emulator Logic 1  includes a plurality of the primary inputs PI_ 0 , PI_ 1 , and PI_ 2 , and a plurality of the primary outputs PO_ 1  and PO_ 3 , first through fifth combination circuits Comb 1 ˜Comb 5 , the AND gate Inst 0 , and first through fifth flipflops FF 1 ˜FF 5 . The second hardware emulator Logic 2  includes a plurality of the primary inputs PI_ 3  and PI_ 4 , a plurality of the primary outputs PO_ 0  and PO_ 2 , sixth through ninth combination circuits Comb 6 ˜Comb 9 , the AND gate Inst 1 , and sixth through eighth flipflops FF 6 ˜FF 8 . 
     The first through fifth flipflops FF 1 ˜FF 5  of the first hardware emulator  10  operate in sync with the normal clock n_clk of the controller  40 . The sixth through ninth flipflops FF 6 ˜FF 9  of the second hardware emulator  20  operate in sync with the normal clock n_clk of the controller  40 . 
     The first and second hardware emulators  10  and  20  are connected to each other by the time-division connector  30 . The time-division connector  30  includes first through eighth shift flipflops S_FF 1 ˜S_FF 8 , first and second multiplexers MUX 1  and MUX 2 , and first and second demultiplexers DEM 1  and DEM 2 . 
     The first and second shift flipflops S_FF 1  and S_FF 2  operate as buffers for outputs of the first hardware emulator  10 . The third and fourth shift flipflops S_FF 3  and S_FF 4  operate as buffers for inputs to the first hardware emulator  10 . The sixth and eighth shift flipflops S_FF 7  and S_FF 8  operate as buffers for outputs of the second hardware emulator  20 . The fifth and sixth shift flipflops S_FF 5  and S_FF 6  operate as buffers for inputs to the second hardware emulator  20 . The first through eighth shift flipflops S_FF 1 ˜S_FF 8  operate in sync with the shift clock s_clk. 
     The output of the AND gate Inst 0  is input to the first shift flipflop S_FF 1  and an output of the second flipflop FF 2  is input to the second shift flipflop S_FF 2 . An output of the fourth combination circuit Comb 4  is input to the third shift flipflop S_FF 3  and an output of the fifth flipflop FF 5  is input to the fourth shift flipflop S_FF 4 . 
     An output of the fifth shift flipflop S_FF 5  is applied to the input node a of the AND gate Inst 1  and an output of the sixth shift flipflop S_FF 6  is input to the sixth combination circuit Comb 6 . An output of the seventh shift flipflop S_FF 7  is input to the seventh combination circuit Comb 7  and an output of the eighth shift flipflop S_FF 8  is input to the eight combination circuit Comb 8 . 
     The first and second shift flipflops S_FF 1  and S_FF 2 , the first and second multiplexers MUX 1  and MUX 2 , and the first and second demultiplexers DEM 1  and DEM 2  of the time-division connector  30 , operate in response to the selection signal sel[n:1]. Outputs of the first and second shift flipflop S_FF 1  and S_FF 2  are transferred to inputs of the fifth and sixth flipflops S_FF 5  and S_FF 6  in response to the selection signal sel[n:1]. Outputs of the seventh and eighth shift flipflop S_FF 7  and S_FF 8  are transferred to inputs of the third and fourth flipflops S_FF 3  and S_FF 4  in response to the selection signal sel[n:1]. 
       FIG. 6  is a circuit diagram that may be used to skip a shifting operation time when a hardware emulator includes the BDT path shown in  FIG. 5 . Referring to  FIGS. 4 through 6 , the BDT path is generated by dividing the first device DUT 1  of  FIG. 4  into two logic parts for respective emulation by the first and second emulators  10  and  20  shown in  FIG. 5 . In the first hardware emulator  10 , the BDT path is connected from the primary input PI_ 0  to the port that is an interface between the first and second logic blocks Logic 1  and Logic 2 , without passing through a flipflop. The BDT path passes through the input node a of the AND gate Inst 0  and the output node of the AND gate Inst 0 . The BDT path is illustrated by a thick broken line in  FIG. 5 . 
     In the second logic block Logic 2 , the input node a of the AND gate Inst 1  is connected to the primary input PI_ 0  and an input node b of the AND gate Inst 1  is connected to the output of the sixth combination circuit Comb 6 . 
     If the first hardware emulator  10  according to an exemplary embodiment of the present invention includes the BDT path, the second hardware emulator  20  is functionally equipped with a combination circuit for making the BDT path, and a plurality of flipflops for storing state values to all inputs of the combination circuit. 
     Status values of the plurality of flipflops are equivalently provided to the second hardware emulator  20  in function transfers state values for all inputs of the combination circuit forming the BDT path of the first hardware emulator  10  while operation results of the first and second hardware emulators  10  and  20  about previous data are sent. 
     The first hardware emulator  10  includes the BDT path illustrated by the thick broken line. The BDT path passes through the primary input PI_ 0 , the input node a of the AND gate Inst 0 , and the output of the AND gate Inst 0 . 
     Current data is transferred to the AND gate Inst 1  of the second hardware emulator  20  by way of the primary input PI_ 0  of the first hardware emulator  10  and the AND gate Inst 0 . This current data may be transferred to the input node a of the AND gate Inst 1  before activation of the normal clock n_clk of the first and second hardware emulators  10  and  20 . 
     The shifting operation, which is synchronized to the shift clock s_clk of the time division connector  30 , may precede the normal clock n_clk of the first and second hardware emulators  10  and  20 . 
     A first state flipflop ST 1  stores a previous state value of the input node b of the AND gate Inst 0  of the first hardware emulator  10 . A second state flipflop ST 2  stores a previous state value of the input node c of the AND gate Inst 0  of the first hardware emulator  10 . 
     The first hardware emulator  10  may be additionally comprised of the first and second state flipflops ST 1  and ST 2  for storing state values of all inputs of the combination circuit (e.g., the AND gate Inst 0 ) forming the BDT path. The first and second state flipflops ST 1  and ST 2  store state values of the inputs of the AND gate Inst 0  according to the previous normal clock n_clk. The state values stored in the first and second state flipflops ST 1  and ST 2  are transferred to first and second state recovery flipflops RST 1  and RST 2  while resultant data of the first and second hardware emulators  10  and  20  is sent to the computer  60  after completing activation of the previous normal clock n_clk. 
     The first state recovery flipflop RST 1  receives a previous state value of an input node b of an AND gate Inst 0 ′ of the first hardware emulator  10  from the first state flipflop ST 1  and restores the previous state value. The second state recovery flipflop RST 2  receives a previous state value of an input node c of the AND gate Inst 0 ′ of the first hardware emulator  10  from the second state flipflop ST 2  and restores the previous state value. 
     The second hardware emulator  20  may be further comprised of the primary input PI_ 0 , the AND gate Inst 0 ′, and the first and second state recovery flipflops RST 1  and RST 2  for restoring the state values of the input nodes b and c of the AND gate Inst 0 ′, which form the BDT path of the first hardware emulator  10 . 
     Before activation of the current normal clock n_clk, the input nodes b and c of the AND gate Inst 0 ′ are set to the state values restored by the first and second state recovery flipflops RST 1  and RST 2 . An input node a of the AND gate Inst 0 ′ may be directly connected to the primary input PI_ 0 . 
     The first and second state flipflops ST 1  and ST 2  store the state values of the input nodes b and c of the AND gate Inst 0  according to the previous normal clock n_clk. Thus, the state values stored in the first and second state flipflops ST 1  and ST 2  are transferred to the first and second state recovery flipflops RST 1  and RST 2  while resultant data of the first and second hardware emulators  10  and  20  is sent to the computer  60  after completing the previous normal clock n_clk. For example, the first hardware emulator  10  transfers an abstracted state value through a state value abstractor and the second hardware emulator  20  restores the abstracted state value through a state value restorer. 
     Consequently, embodiments of the hardware emulation system  100  may provide equality of data transmission speed whether or not a BDT path is present. 
       FIG. 7  is a circuit diagram of a second device DUT 2  including a circuit with a feed-through path. Referring to  FIG. 7 , the second device DUT 2  is comprised of first through seventh combination circuits Comb 1 ˜Comb 7 , first through seventh flipflops FF 1 ˜FF 7 , first and second AND gates I 1  and I 2 , and a multiplexer I 3 . 
     The primary input PI of the second device DUT 2  is connected to the primary output PO through the first and second AND gates I 1  and I 2 , and the multiplexer I 3 . A feed-through path passes from the primary input PI to the primary output PO via an input node a of the AND gate I 1 , an output node of the AND gate I 1 , an input node a of the AND gate I 2 , an output node of the AND gate I 2 , and the multiplexer I 3 . The feed-through path is illustrated by thick broken lines in  FIGS. 7 and 8 . 
       FIG. 8  is a block diagram showing first and second emulators  110  and  120  emulating the second device DUT 2  of  FIG. 7 , according to an exemplary embodiment of the present invention. Referring to  FIGS. 7 and 8 , the second device DUT 2  is emulated by first and second hardware emulators  110  and  120 . The first hardware emulator  110  includes the first through fourth combination circuits Comb 1 ˜Comb 4 , the first through fourth flipflops FF 1 ˜FF 4 , and the first and second AND gates I 1  and I 2 . The second hardware emulator  120  includes the fifth through seventh combination circuits Comb 5 ˜Comb 7 , the fifth through seventh flipflops FF 5 ˜FF 7 , and the multiplexer I 3 . The time division connector  130  interconnects the first hardware emulator  110  to the second hardware emulator  120 . 
     The first and second hardware emulators  110  and  120  operate in sync with the normal clock n_clk provided from a controller  140  (not shown), and the time division connector  130  operates in sync with the shift clock s_clk provided from the controller  140 . The first and second hardware emulators  110  and  120  include feed-through paths denoted by thick broken lines. 
       FIG. 9  is a block diagram illustrating an alternate embodiment of the first and second hardware emulators shown in  FIG. 8 , where the feed-through paths are removed. Referring to  FIG. 9 , the first hardware emulator  210  includes the first through fourth combination circuits Comb 1 ˜Comb 4 , the first through fourth flipflops FF 1 ˜FF 4 , the first and second AND gates I 1  and I 2 , and the first through third state flipflops ST 1 ˜ST 3 . The second hardware emulator  220  includes the fifth through seventh combination circuits Comb 5 ˜Comb 7 , the fifth through seventh flipflops FF 5 ˜FF 7 , the multiplexer  13 , and the first through third state recovery flipflops RST 1 ˜RST 3 . 
     The first and second hardware emulators  210  and  220  operate in sync with the normal clock n_clk provided from a controller  240  (not shown), and the time division connector  230  operates in sync with the shift clock s_clk provided from the controller  240 . The first state flipflop ST 1  stores a previous state value of the input node b of the AND gate I 1  of the first hardware emulator  210 . The second state flipflop ST 2  stores a previous state value of the input node c of the AND gate I 1  of the first hardware emulator  210 . The third state flipflop ST 3  stores a previous state value of the input node b of the AND gate I 2  of the first hardware emulator  210 . 
     The first hardware emulator  210  is further comprised of the plurality of state flipflops ST 1 ˜ST 3  for storing state values of all inputs of the plurality of combination circuits (e.g., the AND gates I 1  and I 2 ) forming the feed-through path. The plurality of state flipflops ST 1 ˜ST 3  store state values of the input nodes of the AND gates I 1  and I 2  according to the previous normal clock n_clk. Thus, the state values stored in the state flipflops ST 1 ˜ST 3  are transferred to the state recovery flipflops RST 1 ˜RST 3  while resultant data of the first and second hardware emulators  210  and  220  is sent after completing the previous normal clock n_clk. 
     The first state recovery flipflop RST 1  receives a previous state value of an input node b of an AND gate I 1  of the first hardware emulator  210  from the first state flipflop ST 1  and restores the previous state value. The second state recovery flipflop RST 2  receives a previous state value of an input node c of an AND gate I 1  of the first hardware emulator  210  from the second state flipflop ST 2  and restores the previous state value. The third state recovery flipflop RST 3  receives a previous state value of an input node b of an AND gate I 2  of the first hardware emulator  210  from the third state flipflop ST 3  and restores the previous state value. 
     The second hardware emulator  220  is comprised of a primary input PI, an AND gate I 1 ′, first and second state recovery flipflops RST 1  and RST 2  for restoring state values of input nodes b and c of the AND gate I 1 ′, an AND gate I 2 ′, and a third state recovery flipflop RST 3  for restoring a state value of an input node b of the AND gate I 2 ′, which form the feed-through path of the second hardware emulator  220 . 
     Before activation of the current normal clock n_clk, a state value of the first state recovery flipflop RST 1  is provided to the input node b of the AND gate I 1 ′ and a state value of the second state recovery flipflop RST 2  is provided to the input node c of the AND gate I 1 ′. Before activation of the current normal clock n_clk, a state value of the third state recovery flipflop RST 3  is provided to the input node b of the AND gate I 2 ′. 
     An input node a of the AND gate I 1 ′ may be directly connected to the primary input PI_ 0  and an input node a of the AND gate I 2 ′ may be directly connected to an output node of the AND gate I 1 ′. 
     The plurality of state flipflops ST 1 ˜ST 3  store state values of the input nodes of the AND gates I 1  and I 2  according to the previous normal clock n_clk. Thus, the state values stored in the first through third state flipflops ST 1 ˜ST 3  are transferred to the first through third state recovery flipflops RST 1 ˜RST 3  while resultant data of the first and second hardware emulators  210  and  220  is sent to an external computer  260  after completing the previous normal clock n_clk. 
     For example, the first hardware emulator  210  transfers an abstracted state value through a state value abstractor and the second hardware emulator  220  restores the abstracted state value through a state value restorer. 
     Consequently, embodiments of the hardware emulation system  200  may operate in a same transmission speed as verification data whether or not a feed-through path is present. 
       FIG. 10  is a block diagram of a third device DUT 3 . Referring to  FIG. 10 , the third device DUT 3  is comprised of first through fifth flipflops FF 1 ˜FF 5 , first through third combination circuits Comb 1 ˜Comb 3 , and first and second primary outputs PO_ 0  and PO_ 1 . 
     The first primary output PO_ 0  is connected to an output of the first combination circuit Comb 1 , which is coupled to outputs of the first and second flipflops FF 1  and FF 2  and the second combination circuit Comb 2 . The second primary output PO_ 1  is connected to an output of the third combination circuit Comb 3 . 
       FIG. 11  is a block diagram showing first and second hardware emulators  310  and  320  emulating the third device DUT 3  of  FIG. 10 , according to an exemplary embodiment of the present invention. Referring to  FIGS. 10 and 11 , the third device DUT 3  is divided into first and second logic parts for respective emulation by the first and second hardware emulators  310  and  320 . The third device DUT 3  does not have an FDT path initially, but the FDT path is included therein after it is has been divided among the first and second hardware emulators  310  and  320 . For example, the FDT path passes from the third flipflop FF 3  to the first combination circuit Comb 1  via the second combination circuit Comb 2 . The FDT path is illustrated by the broken line in  FIG. 11 . 
     When an FDT path is present, an output of the second combination circuit Comb 2  is transferred after the shifting operation, but not during the normal clock operation. 
     Skipping a shifting operation time when the FDT path is present in the first and second hardware emulators  310  and  320  will be discussed in conjunction with  FIGS. 12 through 14 . 
       FIG. 12  is a block diagram of a fourth device DUT 4 . Referring to  FIG. 12 , the fourth device DUT 4  is comprised of first through twelfth combination circuits Comb 1 ˜Comb 12 , and first through sixth flipflops FF 1 ˜FF 6 . 
     A primary output PO of the fourth device DUT 4  is generated from the twelfth combination circuit Comb 12 . The twelfth combination circuit Comb 12  receives outputs of the sixth, seventh, ninth, and tenth combination circuits Comb 6 , Comb 7 , Comb 9 , and Comb 10 . 
       FIG. 13  is a block diagram showing first and second hardware emulators  410  and  420  emulating the fourth device DUT 4  of  FIG. 12 , according to an exemplary embodiment of the present invention. Referring to  FIGS. 12 and 13 , the fourth device DUT 4  is divided into first and second logical parts for respective emulation by the first and second hardware emulators  410  and  420 . The first hardware emulator  410  includes the first through eighth combination circuits Comb 1 ˜Comb 8  and the first through third flipflops FF 1 ˜FF 3 . The second hardware emulator  420  includes the ninth through twelfth combination circuits Comb 9 ˜Comb 12  and the fourth through sixth flipflops FF 4 ˜FF 6 . The time division connector  430  interconnects the first hardware emulator  410  to the second hardware emulator  420 . 
     The first and second hardware emulators  410  and  420  operate in sync with the normal clock n_clk provided from a controller  440  (not shown). The time division connector  430  operates in sync with the shift clock s_clk provided from the controller  440 . The first and second hardware emulators  410  and  420  include an FDT path denoted by a thick solid line. 
       FIG. 14  is a block diagram illustrating the first and second hardware emulators shown in  FIG. 13 , where the FDT path has been removed. Referring to  FIG. 14 , the first hardware emulator  510  includes the first through eighth combination circuits Comb 1 ˜Comb 8  and the first through third flipflops FF 1 ˜FF 3 . 
     The second hardware emulator  520  includes the first through twelfth combination circuits Comb 9 ˜Comb 12 , the fourth and fifth flipflops FF 4  and FF 5 , and first through third state recovery flipflops RFF 1 ˜RFF 3 . A time division connector  530  interconnects the first hardware emulator  510  to the second hardware emulator  530 . The first and second hardware emulators  510  and  520  operate in sync with the normal clock n_clk provided from a controller  540  (not shown). The time division connector  530  operates in sync with the shift clock s_clk provided from the controller  540 . 
     The second hardware emulator  520  is further comprised of the plurality of state recovery flipflops RFF 1 ˜RFF 3  for storing state values of all inputs (i.e., state values of the fourth, sixth, and seventh combination circuits Comb 4 , Comb 6 , and Comb 7 ) to the combination circuit (i.e., the twelfth combination circuit Comb 12 ). 
     State values of the first through third combination circuits Comb 1 ˜Comb 3  are stored in the first through third flipflops FF 1 ˜FF 3 . The state values stored in the first through third flipflops FF 1 ˜FF 3  according to the previous normal clock n_clk are transferred to the first through third state recovery flipflops RFF 1 ˜RFF 3  while resultant data of the first and second hardware emulators  510  and  520  is sent to an external computer  560  (not shown). 
     The first state recovery flipflop RFF 1  stores a state value of the first combination circuit Comb 1  of the first hardware emulator  510  through the time division connector  530 . The second state recovery flipflop RFF 2  stores a state value of the second combination circuit Comb 2  of the first hardware emulator  510  through the time division connector  530 . The third state recovery flipflop RFF 3  stores a state value of the third combination circuit Comb 3  of the first hardware emulator  510  through the time division connector  530 . 
     The second hardware emulator  520  further includes a fourth combination circuit Comb 4 ′, and sixth and seventh combination circuits Comb 6 ′ and Comb 7 ′, in addition to the first through third state recovery flipflops RFF 1 ˜RFF 3 . 
     Therefore, embodiments of the hardware emulation system may operate in the same transmission speed as verification data whether or not a FDT path is present. 
       FIG. 15  is a flow chart showing a method of driving the emulation system of  FIG. 1 , according to an exemplary embodiment of the present invention. Referring to  FIGS. 1 and 15 , the computer  60  prepares new input data for verifying the first and second hardware emulators  10  and  20 . The computer  60  determines pass/fail states of the first and second hardware emulators  10  and  20  by comparing an expected output of the emulators to actual output of the emulators. For example, the computer compares output data of the emulators to previous input data for verifying the first and second hardware emulators  10  and  20  (S 21 ). 
     Thereafter, the computer  60  transfers new input data to the hardware emulation board  50  for verifying the first and second hardware emulators  10  and  20  (S 22 ). Then, the first and second hardware emulators  10  and  20  receive the new input data from the hardware emulation board  50  (S 23 ). 
     As aforementioned by  FIGS. 6 through 9 , the first and second hardware emulators  10  and  20  may skip the shifting operation for BDT. The first and second hardware emulators  10  and  20  conduct the normal operation in one clock cycle in sync with the normal clock n_clk (S 24 ). 
     Next, the first and second emulators  10  and  20  transfers output data to the hardware emulation board  50  (S 25 ). Then, the first and second hardware emulators  10  and  20  execute the shifting operation for FDT in sync with the shift clock s_clk and at the same time the hardware emulation board  50  transfers the output data to the computer  60  (S 26 ). 
     The computer  60  determines whether other input data to be used for verifying the first and second hardware emulators  10  and  20  is present. If new input data is present, the step S 21  is resumed. Unless there is new input data, the emulation procedure for the hardware emulation system  100  is terminated (S 27 ). 
       FIG. 16  illustrates durations of steps of the emulation method shown in  FIG. 15 . Referring to  FIGS. 15 and 16 , the operating steps from S 21  to S 26  are correspondent to one clock cycle of the first and second hardware emulators  10  and  20 . 
     The step S 21  corresponds to a time t B1 . The step S 22  corresponds to a time t B2 . The step S 23  corresponds to a time t B3 . The step S 24  corresponds to a time t B5 . The step S 25  corresponds to a time t B7 . The step S 26  corresponds to a time t B8 . As a result, one clock cycle of the first and second hardware emulators  10  and  20  is a sum of times t B1 , t B2 , t B3 , t B5 , t B7 , and t B8 . 
     Comparing  FIG. 3  with  FIG. 16 , t A1  corresponds to t B1 , t A2  corresponds to t B2 , and t A2  corresponds to t B3 . The time t A4  has no correspondent because the shifting operation for BDT is skipped. Therefore, t B4  is zero, t A5  corresponds to t B5 , t A6  corresponds to t B6 , t A7  corresponds to t B7 , and t A8  corresponds to t B8 . 
     The shifting operation for FDT according to at least one embodiment of the present invention is carried out in the step S 26 , where the hardware emulation board  50  conducts the shifting operation for FDT when transferring output data to the computer  60 . 
     Embodiments of the present invention may be effective in reducing an emulation time by shortening a data transmission time between an emulation system and an external computer. 
     Although exemplary embodiments of the present invention have been described, it is to be understood that the present invention is not limited to these exemplary embodiments, and various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the disclosure.

Technology Classification (CPC): 6