Patent Abstract:
A network switch including a plurality of ports; a memory, and a queue controller. The queue controller is configured to: maintain a list of pointers to a first plurality of buffers in the memory; of the first plurality of buffers, selectively allocate a first buffer to a first port of the plurality of ports; in response to i) the first port receiving a first frame of data, ii) the first buffer being allocated to the first port, and iii) the first frame being stored in the memory, remove the pointer to the first buffer from the list of pointers; transfer, to an output queue associated with a second port of the plurality of ports, the pointer to the first buffer; and in response to the first frame of data being sent from the second port, add the pointer to the first buffer back to the list of pointers.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 12/840,327, filed Jul. 21, 2010, which is a continuation of U.S. application Ser. No. 11/523,185 (now U.S. Pat. No. 7,764,703), filed Sep. 19, 2006, which is a continuation of U.S. application Ser. No. 10/150,147 (now U.S. Pat. No. 7,110,415), filed May 17, 2002. 
     This application is related to U.S. application Ser. No. 10/071,417 (now U.S. Pat. No. 7,035,273), filed Feb. 6, 2002, and U.S. application Ser. No. 10/141,096 (now U.S. Pat. No. 7,209,440), filed May 7, 2002. 
    
    
     BACKGROUND 
     The present invention relates generally to data communications, and particularly to a queuing system implementing multiple classes of service within a network switch. 
     The rapidly increasing popularity of networks such as the Internet has spurred the development of network services such as streaming audio and streaming video. These new services have different latency requirements than conventional network services such as electronic mail and file transfer. New quality of service (QoS) standards require that network devices, such as network switches, address these latency requirements. For example, the IEEE 802.1 standard divides network traffic into several classes of service based on sensitivity to transfer latency, and prioritizes these classes of service. The highest class of service is recommended for network control traffic, such as switch-to-switch configuration messages. The remaining classes are recommended for user traffic. The two highest user traffic classes of service are generally reserved for streaming audio and streaming video. Because the ear is more sensitive to missing data than the eye, the highest of the user traffic classes of service is used for streaming audio. The remaining lower classes of service are used for traffic that is less sensitive to transfer latency, such as electronic mail and file transfers. 
       FIG. 1  shows a simple network  100  in which a network switch  102  connects two devices  104 A and  104 B. Each of devices  104  can be any network device, such as a computer, a printer, another network switch, or the like. Switch  102  transfers data between devices  104  over channels  106 A and  106 B, and can also handle an arbitrary number of devices in addition to devices  104 . Channels  106  can include fiber optic links, wireline links, wireless links, and the like. 
       FIG. 2  is a block diagram of a conventional shared-memory output-queue store-and-forward network switch  200  that can act as switch  102  in network  100  of  FIG. 1 . Switch  200  has a plurality of ports including ports  202 A and  202 N. Each port  202  is connected to a channel  204 , a queue controller  206  and a memory  208 . Each port  202  includes an ingress module  214  that is connected to a channel  204  by a physical layer (PHY)  210  and a media access controller (MAC)  212 . Referring to  FIG. 2 , port  202 A includes an ingress module  214 A that is connected to channel  204 A by a MAC  212 A and a PHY  210 A, while port  202 N includes an ingress module  214 N that is connected to channel  204 N by a MAC  212 N and a PHY  210 N. Each port  202  also includes an egress module  216  that is connected to a channel  204  by a MAC  218  and a PHY  220 . Referring to  FIG. 2 , port  202 A includes an egress module  216 A that is connected to channel  204 A by a MAC  218 A and a PHY  220 A, while port  202 N includes an egress module  216 N that is connected to channel  204 N by a MAC  218 N and a PHY  220 N. 
       FIG. 3  is a flowchart of a conventional process  300  performed by network switch  200 . At power-on, queue controller  206  initializes a list of pointers to unused buffers in memory  208  (step  302 ). A port  202  of switch  200  receives a frame from a channel  204  (step  304 ). The frame enters the port  202  connected to the channel  204  and traverses the PHY  210  and MAC  212  of the port  202  to reach the ingress module  214  of the port  202 . Ingress module  214  requests and receives one or more pointers from queue controller  206  (step  306 ). Ingress module  214  stores the frame at the buffers in memory  208  that are indicated by the received pointers (step  308 ). 
     Ingress module  214  then determines to which channel (or channels in the case of a multicast operation) the frame should be sent, according to methods well-known in the relevant arts (step  310 ). Queue controller  206  sends the selected pointers to the egress modules  216  of the ports connected to the selected channels (step  312 ). These egress modules  216  then retrieve the frame from the buffers indicated by the pointers (step  314 ) and send the frame to their respective channels  204  (step  316 ). These egress modules  216  then release the pointers for use by another incoming frame (step  318 ). The operation of switch  200  is termed “store-and-forward” because the frame is stored completely in the memory  208  before leaving the switch  200 . The store-and-forward operation creates some latency. Because all of the switch ports  202  use the same memory  208 , the architecture of switch  202  is termed “shared memory.” 
     The queue controller  206  performs the switching operation by operating only on the pointers to memory  208 . The queue controller  206  does not operate on the frames. If pointers to frames are sent to an egress module  216  faster than that egress module  216  can transmit the frames over its channel  204 , the pointers are queued within that port&#39;s output queue  216 . Because pointers accumulate only at the output side of switch  200 , the architecture of switch  200  is also termed “output-queued.” Thus switch  200  has a store-and-forward, shared-memory, output-queued architecture. 
     In an output-queued switch, the queue controller must enqueue a frame received on a port to all of the output queues selected for that frame before the next frame is completely received on that port. Thus at any time only one complete frame can be present at each input port, while the output queues can be arbitrarily large. Thus the latency of an output-queued switch has two components: ingress latency and egress latency. Ingress latency is the period between the reception of a complete frame at an ingress module and the enqueuing of the pointers to that frame at all of the output queues to which the frame is destined. Egress latency is the period between enqueuing of the pointers to a frame in an output queue of a port and the completion of the transmission of that frame from that port. 
     Of course, QoS is relevant only when the switch is congested. When the amount of data entering the switch exceeds the amount of data exiting the switch, the output queues fill with pointers to frames waiting to be transmitted. If congestion persists, the memory will eventually fill with frames that have not left the switch. When the memory is full, incoming frames are dropped. When memory is nearly full and free memory buffers are rare, QoS dictates the free buffers be allocated to frames having high classes of service. But when the switch is uncongested, free memory buffers are plentiful, and no preferential treatment of frames is necessary to achieve QoS. 
     QoS is implemented in an output-queued store-and-forward switch by controlling the overall latency for each frame such that frames having a high class of service experience less latency than frames having lower classes of service. Many conventional solutions exist to reduce egress latency. However, solutions for reducing ingress latency in an output-queued store-and-forward switch either do not exist, or have proven unsatisfactory. 
     SUMMARY 
     In general, in one aspect, this specification describes a network switch including a plurality of ports; a memory, and a queue controller. The queue controller is configured to: maintain a list of pointers to a first plurality of buffers in the memory, wherein the first plurality of buffers is available to store a frame of data; of the first plurality of buffers available to store a frame of data, selectively allocate a first buffer to a first port of the plurality of ports; in response to i) the first port receiving a first frame of data, ii) the first buffer being allocated to the first port, and iii) the first frame being stored in the memory, remove the pointer to the first buffer from the list of pointers; transfer, to an output queue associated with a second port of the plurality of ports, the pointer to the first buffer; and in response to the first frame of data being sent from the second port, add the pointer to the first buffer back to the list of pointers, wherein the first buffer is again available to store a frame of data. 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 
    
    
     
       DRAWINGS 
         FIG. 1  shows a simple network in which a network switch connects two devices. 
         FIG. 2  is a block diagram of a conventional shared-memory output-queue store-and-forward network switch that can act as the switch in the network of  FIG. 1 . 
         FIG. 3  is a flowchart of a conventional process performed by the network switch of  FIG. 2 . 
         FIG. 4  is a block diagram of a queue controller suitable for use as the queue controller in the network switch of  FIG. 2 . 
         FIG. 5  depicts the manner in which pointers to buffers circulate within the queue controller of  FIG. 4 . 
         FIG. 6  is a block diagram of an output queue according to one implementation. 
         FIG. 7  depicts the logical structure of the process employed by a free module in allocating pointers to ports according to an implementation having 7 ports and 4 classes of service. 
         FIG. 8  shows details of a priority queue according to one implementation. 
         FIGS. 9A and 9B  show a flowchart of a process of a network switch under control of a queue controller according to one implementation. 
         FIG. 10  shows four ports p 0 , p 1 , p 2 , and p 3  in a switch to illustrate head-of-line blocking. 
     
    
    
     The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears. 
     DETAILED DESCRIPTION 
       FIG. 4  is a block diagram of a queue controller  400  suitable for use as queue controller  206  in network switch  200  of  FIG. 2 . Queue controller  400  can be implemented using hardware, software, or any combination thereof. Queue controller  400  includes a forwarding module  402 , a free module  404 , a plurality of reserve modules  406 A through  406 N, and a plurality of output queues  408 A through  408 N. Each reserve module  406  is connected to one of ingress modules  214 . Each output queue  408  is connected to one of egress modules  216 . 
     Free module  404  and reserve modules  406  each contain one linked list of pointers to buffers in shared memory  208 . Each output queue  408  contains a priority queue for each class of service implemented by switch  400 . Each priority queue contains one linked list of pointers to buffers in shared memory  208 . In one implementation, switch  400  implements four classes of service labeled class 0 through class 3, with class 3 having the highest priority. In this implementation, each output queue  408  contains four priority queues. Other implementations can implement fewer or greater classes of service, as will be apparent to one skilled in the relevant art after reading this description. 
     All of the linked lists for free module  404 , reserve modules  406 , and output queues  408  are stored in a linked-list memory  410 . A memory arbiter  412  arbitrates among competing requests to read and write linked-list memory  410 . Each of free module  404 , reserve modules  406 , and output queues  408  maintains an object that describes its linked list. Each of these objects maintains the size of the list and pointers to the head and tail of the list. Each of free module  404 , reserve modules  406 , and output queues  408  traverses its linked list by reading and writing the “next” links into and out of linked list memory  410 . 
     Free module  404  contains pointers to buffers in memory  208  that are available to store newly-received frames (that is, the buffers have an available status). Each reserve module  406  contains a list of pointers to available buffers that are reserved for the port housing that reserve module.  FIG. 5  depicts the manner in which these pointers circulate within queue controller  400 . Queue controller  400  allocates pointers from free module  404  to reserve modules  406  according to the methods described below (flow  502 ). Buffers associated with pointers in a free module  404  have an available status until a frame is stored in the buffers. Storing a frame in one or more buffers changes the status of those buffers to unavailable. To forward a frame to an output port, the frame is stored in a buffer in memory  208 , and the pointers to that buffer are transferred to the output queue  408  for that output port (flow  504 ). When a frame is sent from an output port to a channel  106 , the pointers for that frame are returned to free module  404 , thereby changing the status of the pointers to available (flow  506 ). 
     Multicast module  414  handles multicast operations. In linked-list memory  410 , pointers associated with the start of a frame also have a vector including a bit for each destined output port for the frame. When an output port finishes transmitting a frame, the output queue passes the frame&#39;s pointers to multicast module  414 , which clears the bit in the destination vector associated with that output port. When all of the bits in the destination vector have been cleared, the frame&#39;s pointers are returned to free module  404 . 
       FIG. 6  is a block diagram of an output queue  408  according to one implementation. Output queue  408  includes an output scheduler  602  and four priority queues  604 A,  604 B,  604 C, and  604 D assigned to classes of service 3, 2, 1, and 0, respectively. Forwarding module  402  enqueues the pointers for each frame to a priority queue selected according to the class of service of the frame. For example, the pointers for a frame having class of service 2 are enqueued to priority queue  604 B. Each egress module  216  can transmit only one frame at a time. Therefore output scheduler  602  selects one of the priority queues at a time based on a priority scheme that can be predetermined or selected by a user of the switch, such as a network administrator. 
     One priority scheme is strict priority. According to strict priority, higher-priority frames are always handled before lower-priority frames. Under this scheme, priority queue  604 A transmits until it empties. Then priority queue  604 B transmits until it empties, and so on. 
     Another priority scheme is weighted fair queuing. According to weighted fair queuing, frames are processed so that over time, higher-priority frames are transmitted more often than lower-priority frames according to a predetermined weighting scheme and sequence. One weighting scheme for four classes of service is “8-4-2-1.” Of course, other weighting schemes can be used, as will be apparent to one skilled in the relevant art after reading this description. 
     According to 8-4-2-1 weighting, in 15 consecutive time units, 8 time units are allocated to class of service 3, 4 time units are allocated to class of service 2, 2 time units are allocated to class of service 1, and 1 time unit is allocated to class of service 0. In one implementation, the sequence shown in Table 1 is used with 8-4-2-1 weighting. 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
             
             
               
                 Time Unit 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
                 7 
                 8 
                 9 
                 10 
                 11 
                 12 
                 13 
                 14 
                 15 
               
               
                 Priority 
                 3 
                 2 
                 3 
                 1 
                 3 
                 2 
                 3 
                 0 
                 3 
                 2 
                 3 
                 1 
                 3 
                 2 
                 3 
               
               
                   
               
             
          
         
       
     
     Thus when none of the priority queues are empty, the sequence of classes of service selected by output scheduler  602  is 3-2-3-1-3-2-3-0-3-2-3-1-3-2-3. When one of the priority queues is empty, its slots in the sequence are skipped. For example, if only priority queue  604 A is empty, the sequence of classes of service selected by output scheduler  602  is 2-1-2-0-2-1-2. 
     In some implementations, free module  404  also employs a priority scheme in satisfying requests for pointers from reserve modules  406 . In some implementations, free module  404  employs strict priority in satisfying these requests. In other implementations, free module  404  employs weighted fair queuing in satisfying these requests. In still other implementations, free module  404  employs no priority scheme in satisfying requests for pointers from reserve modules  406   
       FIG. 7  depicts the logical structure  700  of the process employed by free module  404  in allocating pointers to ports according to an implementation having 7 ports and 4 classes of service. Each class of service has a ring. Class of service 0 has a ring r0. Class of service 1 has a ring r1. Class of service 2 has a ring r2. Class of service 3 has a ring r3. Each port has a station on each ring. 
     Although storing a frame may require multiple buffers, and therefore multiple pointers, free module  404  dispenses pointers to reserve modules  406  one at a time to keep allocation of the pointers both simple and fair. When a reserve module  406  is not full, it requests a pointer. The request includes a priority. In one implementation, the priority is the class of service of the last frame received by the port. In another implementation, the priority is the class of service of the last frame forwarded by the port. 
     Free module  404  first allocates the requests to the stations on structure  700 , and then selects one of the rings to examine using a priority scheme such as weighted fair queuing. Within that ring, free module  404  selects a request by selecting one of the stations on the ring. Free module  404  remembers the last station serviced on each ring, and services the next one so that all stations on a ring are serviced sequentially. If a station has no request for pointers, free module  404  moves on to the next station on the ring. When a pointer has been dispensed to a station on a ring, free module  404  selects another ring according to the priority scheme. When no requests are pending, neither the priority sequence nor the sequential sequence advances. This process ensures that, within a single class of service, requests for free pointers are serviced evenly in a sequential fashion, and that between classes of service, requests for free pointers are serviced according to class of service. As a result, when the switch is congested, ports that receive and forward high-priority frames receive more free pointers. The sizes of the reserves lists for those ports do not decrease as rapidly as those of ports receiving low-priority frames. Therefore, over time, high-priority frames experience less latency than low-priority frames. When flow control is enabled, and the switch is congested, this process ensures that ports receiving high-priority frames assert flow control less often, and therefore handle more frames. Thus even with flow control enabled, the process implements quality of service. 
     Switch  200  can refuse to store and forward frames. This refusal is also known as “discarding” frames or “dropping” frames. A frame is forwarded by enqueuing the pointers for that frame to an output queue. A frame is discarded by not enqueuing the pointers for that frame to an output queue, but instead keeping those pointers in the reserve module  406 . In a multicast operation, where a frame is destined for multiple output queues, that frame may be enqueued to some of the output ports, but not enqueued to others of the output ports, as described below. When a switch discards a frame, some protocols at higher layers, such as transmission control protocol (TCP) detect and retransmit the discarded frame, while other protocols at higher layers, such as user datagram protocol (UDP), take no action. 
     Each reserve module  406  makes a decision to either forward or drop each frame based on a congestion signal generated by the output queue  408  serving the port to which the frame is destined. In some implementations the level of congestion at an output queue depends on class of service. Referring again to  FIG. 6 , each output queue  408  has 4 priority queues  604 , one for each class of service. Free module  404  maintains a count of the number of free pointers, and provides that count to each priority queue  604 . Each priority queue  604  generates a congestion signal based on the count of free pointers and the number of pointers in the priority queue, and provides the congestion signal to each of the reserve modules  406 . Thus, referring again to  FIG. 4 , each reserve module  406  receives four congestion signals from each output queue  408 , one for each class of service, and makes the decision to forward or drop a frame based on the congestion signal generated by the output queue  408  for the class of service of the frame. Thus in a switch having 4 classes of service and N ports, each reserve module  406  receives 4N congestion signals. 
       FIG. 8  shows details of a priority queue  604  according to one implementation. Each priority queue  604  includes a counter  804  that maintains a count of the number of pointers j in the priority queue. A divider  806  such as a shift register divides the output of counter  804  by a scale factor k. In some implementations, scale factor k is user-selectable, and can take on any of the values 1, 2, 4 and 8. In some implementations, a different value of scale factor k can be specified for each class of service. In some implementations, the default value for scale factor k is k=4 for all classes of service. 
     Free module  404  includes a counter  802  that maintains a count of the number of pointers h in the free module. A comparator  808  within priority queue  604  compares the count h with the scaled count j/k, and asserts a “true” congestion signal (for example, a high logic level) at a node  810  when 
     
       
         
           
             
               
                 
                   
                     j 
                     k 
                   
                   ≥ 
                   h 
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     and asserts a “false” congestion signal (for example, a low logic level) otherwise. A reserve module  406  forwards a frame destined for an output queue  408  when the congestion signal generated by that output queue is true for the class of service of the frame, and drops the frame otherwise. For a multicast frame (that is, a frame which is destined for multiple output queues  408 ), reserve modules  406  make the decision to forward the frame separately for each destination output queue  408  based on the congestion signal generated by that output queue. 
       FIGS. 9A and 9B  show a flowchart of a process  900  of a network switch such as switch  200  under control of queue controller  400  according to one implementation. At power-on of switch  200 , queue controller  400  initializes a free module  404  to contain a number of pointers to unused buffers in memory  208  (step  902 ). Queue controller  400  transfers some of these pointers to each reserve module  406  (step  904 ). 
     Each reserve module  406  includes a counter to count the number of pointers in the reserve module. When the number of pointers is below the capacity of the reserve module  406 , the reserve module continually requests pointers from free module  404  (step  906 ). In some implementations, the capacity of each reserve module  406  is 4 pointers, where a frame of maximum size requires 3 pointers. 
     A port  202  of switch  200  receives a frame from a channel  204  (step  908 ). The frame enters the port  202  connected to the channel  204  and traverses the PHY  210  and MAC  212  of the port  202  to reach the ingress module  214  of the port  202 . Ingress module  214  selects one or more pointers from the reserve module  406  for the port  202  (step  910 ). Ingress module  214  stores the frame in memory  208  at the buffers that are indicated by the received pointers (step  912 ). 
     Ingress module  214  then determines the destination channel (or channels in the case of a multicast operation) to which the frame should be sent, according to methods well-known in the relevant arts (step  914 ). Reserve module  406  then determines whether the frame should be forwarded or discarded based on the congestion signal generated for the class of service of the frame by the output queue  408  serving the destination channel (step  916 ). Reserve module  406  forwards the frame to the destination channel when the number of pointers j in the priority queue  604  for the class of service of the frame exceeds the product of the scale factor k and the number of pointers h in free module  404 . When a frame is dropped, the reserve module  406  keeps the pointers for that frame (step  918 ), and process  900  resumes at step  906 . 
     When a frame is forwarded, queue controller  206  sends the selected pointers to the output queues  408  for the ports connected to the destination channels (step  920 ). When the pointers for the frame reach the head of an output queue  408  of a port  202 , the egress module  216  of the port retrieves the frame from the buffers indicated by the pointers (step  922 ) and sends the frame to its channel  204  (step  924 ). The output queue  408  then releases the pointers by returning them to free module  404  (step  926 ). Process  900  then resumes at step  906 . 
     By gradually discarding frames based on class of service as the switch becomes more congested, process  900  effectively reserves more free buffers for frames having high classes of service. Therefore, process  900  serves to minimize the ingress latency for high-priority frames, in accordance with the objectives of quality of service. 
     An example of process  900  is now discussed with reference to  FIG. 1 . Device  104 A has data to transmit to device  104 B. Device  104 A generates a frame of the data, and selects device  104 B as the destination for the frame. Device  104 A then sends the frame to channel  106 A. The frame subsequently arrives at switch  102 . 
     Switch  102  has a memory including a plurality of memory buffers in for storing a frame. The buffers include n available buffers and p unavailable buffers such that m=n+p. Switch  102  reserves g of the n buffers for channel  106 A by sending q pointers to the reserve module  406  for channel  106 A. Switch  102  also reserves some of the remaining available buffers to other channels. When switch  102  receives the frame from channel  106 A, it stores the frame in i of the q buffers, wherein 1≦i≦q, thereby changing the status of the i buffers to unavailable. In one implementation, 1≦i≦3. 
     Switch  102  selectively assigns the frame to channel  106 B (that is, determines whether to send the frame to channel  106 B) based on the number of the buffers j assigned to channel  106 B (that is, the number of pointers h stored in the output queue  408  serving channel  106 B) and the number of the buffers h neither reserved nor assigned to any channel, where i+j≦m and h+q≦n. 
     If the number of the buffers j assigned to channel  106 B and storing frames having the same class of service as the frame is less than the product of the scale factor k and the number of the buffers h neither reserved nor assigned to any channel, switch  102  sends the frame to channel  106 B and changes the status of the i buffers to available. Device  104 B then receives the frame. But if the number of the buffers j assigned to channel  106 B and storing frames having the same class of service as the frame is greater than, or equal to, the product of the scale factor k and the number of the buffers h neither reserved nor assigned to any channel, switch  102  discards the frame and changes the status of the i buffers to available. 
     Implementations of the present invention solve a problem known as head-of-line blocking (HOLB). HOLB occurs when congested flows in a switch cause frames to be dropped from uncongested flows. Consider the following case, illustrated in  FIG. 10 , which shows four ports p 0 , p 1 , p 2 , and p 3  in a switch  902 . All of the ports run at 100 Mbps. All of the frames arriving a port p 0  have class of service 0, while all of the frames arriving a port p 1  have class of service 1. 
     Port p 1  sends all of its frames to port p 3 . Port p 0  sends 50% of its frames to port p 2 , and sends the other 50% of its frames to port p 3 . Port p 2  is uncongested. However, port p 3  is congested because the amount of data arriving at port p 3  is greater than the amount of data port p 3  can transmit. In a conventional switch, the congestion at port p 3  causes both ports p 0  and p 1  to begin dropping frames, including frames destined for uncongested port p 2 . 
     In implementations of the present invention, each port forwards a frame to another port based on the level of congestion in that port. With weighted fair queueing, the output queue&#39;s scheduler empties the priority queues so that the congestion signals asserted by port p 3  will be true for class of service 0 twice as often as for class of service 1 in the steady state. Therefore in port p 3 , the priority queue for class of service 1 will drain twice as fast as the priority queue for class of service 0. 
     Therefore in the steady state, each of ports p 0  and p 1  drops frames destined for port p 3 . However, because port p 2  is uncongested, its congestions signals are always false. Therefore none of the frames destined for port p 2  are dropped. Thus implementations of the present invention implement quality of service while solving head-of-line blocking. 
     The invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits). 
     A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

Technology Classification (CPC): 7