Patent Abstract:
An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an amplifier circuit that samples input signals and outputs signals obtained by applying a gain to the sampled input signals having different voltages. 
         [0003]    2. Description of the Related Art 
         [0004]    In video equipment using a solid-state image pickup device such as a CCD (Charge Coupled Device), a correlation double sampling circuit (CDS) and a variable gain amplifier circuit (PGA) are used so that the noise of a video signal from the solid-state image pickup device is eliminated and the signal itself is amplified with a prescribed gain. In the CDS and PGA, an amplifier circuit composed of a switched capacitor circuit is conventionally used. For example, Patent Document 1 describes a differential amplifier circuit composed of a switched capacitor circuit. 
         [0005]      FIG. 1  shows the conventional differential amplifier circuit composed of the switched capacitor circuit. The differential amplifier circuit  10  shown in  FIG. 1  is composed of a full differential amplifier circuit  11 , switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 , and capacitors Cs and Cf. The differential amplifier circuit  11  is connected to, for example, an external device  12  that outputs signals to be amplified. The external device  12  represents, for example, a solid-state image pickup device that outputs video signals to be amplified. The operations of the differential amplifier circuit  11  are described below. 
         [0006]    At a sampling operation in the differential amplifier circuit  11 , the switches SW 1 , SW 2 , SW 4 , SW 5 , and SW 8  are turned on, and the switch SW 3  is turned off. A reference voltage Vref 2  is supplied to the switches SW 6  and SW 7 . At this time, signals output from the external device  12  are input to input terminals Vip and Vim, and an electrical charge corresponding to a potential difference between a standard voltage Vref 1  and the input signals is stored in the capacitors Cs. Furthermore, both outputs from the full differential amplifier circuit  11  are short-circuited by the switch SW 8 , and an electrical charge corresponding to a potential difference between the standard voltage Vref 1  and the reference voltage Vref 2  is stored in the capacitors Cf via the switches SW 6  and SW 7 . 
         [0007]    Then, when the sampling operation is completed to establish a signal output state, the switches SW 1 , SW 2 , SW 4 , SW 5 , and SW 8  are turned off, and the switch SW 3  is turned on. The switches SW 6  and SW 7  are connected to the outputs of the full differential amplifier circuit  11 . At this time, the one terminal of the capacitors Cs is short-circuited to have the same potential as the other terminal thereof, which in turn moves the electrical charges stored in the capacitors Cs to the capacitors Cf. Accordingly, a potential difference Vop−Vom in the outputs of the full differential amplifier circuit  11  is calculated according to the following formula. 
         [0000]        Vo=Vop−Vom=Cs/Cf×{ ( Vip−V ref1)−( Vim−V ref1)}= Cs/Cf× ( Vip−Vim )  (1) 
         [0008]    From the above formula (1), it is found that the gain of the full differential amplifier circuit  11  in the amplifier circuit  10  is determined by the ratio of the capacitors Cs to the capacitors Cf. 
         [0009]    Patent Document 1: JP-A-2006-174091 
         [0010]    However, the above formula (1) according to the conventional art does not take the offset voltage Voff of the full differential amplifier circuit  11  into consideration, but it includes an error as shown in the following formula (2). 
         [0000]        Vo=Vop−Vom=Cs/Cf× ( Vip−Vim+Voff )  (2) 
       SUMMARY OF THE INVENTION 
       [0011]    The present invention has been made in light of the above circumstances and may provide an amplifier circuit capable of having improved characteristics without being influenced by an offset voltage. 
         [0012]    According to an aspect of the present invention, there is provided an amplifier circuit including a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit. 
         [0013]    Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  shows a conventional differential amplifier circuit composed of a switched capacitor circuit; 
           [0015]      FIG. 2  shows the amplifier circuit  100  of a first embodiment; 
           [0016]      FIG. 3  shows the amplifier circuit  100 A of a second embodiment; and 
           [0017]      FIG. 4  shows the amplifier circuit  100 B of the third embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0018]    According to embodiments of the present invention, at a sampling operation in a differential amplifier circuit, a potential difference between a first reference voltage supplied to a first input terminal and a second reference voltage supplied to a second input terminal is set to be equal to the offset voltage of the differential amplifier circuit, thereby making it possible to cancel the offset voltage. As a result, the characteristics of an amplifier circuit can be improved. 
       First Embodiment 
       [0019]    Referring to the accompanying drawing, a description is now made of a first embodiment of the present invention.  FIG. 2  shows an amplifier circuit  100  of the first embodiment. 
         [0020]    The amplifier circuit  100  of the first embodiment is configured of a first differential amplifier circuit  110 , a second differential amplifier circuit  120 , switches SW 10  SW 20 , SW 30 , SW 40 , SW 50 , SW 60 , SW 70 , and SW 80 , and capacitors Cs 1 , Cs 2 , Cf 1 , and Cf 2 . Note that the capacitors Cs 1  and Cs 2  are capacitors having the same capacitance, and the capacitance of the capacitors Cs 1  and Cs 2  is represented as Cs. Furthermore, the capacitors Cf 1  and Cf 2  are capacitors having the same capacitances, and the capacitance of the capacitors Cf 1  and Cf 2  is represented as Cf. 
         [0021]    In this embodiment, an inverting input terminal T 1  of the differential amplifier circuit  110  is connected to one end of the capacitor Cs 1 , one end of the switch SW 40 , and one end of the capacitor Cf 1 . Furthermore, a non-inverting input terminal T 2  of the differential amplifier circuit  110  is connected to one end of the capacitor Cs 2 , one end of the switch SW 50 , and one end of the capacitor Cf 2 . The other end of the capacitor Cs 1  is connected to one end of the switch SW 10  and one end of the switch SW 30 . The other end of the capacitor Cs 2  is connected to one end of the switch SW 20  and the other end of the switch SW 30 . 
         [0022]    The other ends of the switches SW 10  and SW 20  are connected to the input terminals Vip and Vim of the amplifier circuit  100  of this embodiment, respectively. The input terminals Vip and Vim are connected to an external device  130 . Note that the external device  130  of this embodiment represents, for example, a device that outputs a signal to be amplified by the amplifier circuit  100 , such as a solid-state image pickup device that outputs a video signal or the like to be amplified. 
         [0023]    The other end of the capacitor Cf 1  is connected to either a standard voltage source  140  that generates a standard voltage Vref or a first output terminal T 3  of the differential amplifier circuit  110  via the switch SW 60 . The other end of the capacitor Cf 2  is connected to either a standard voltage source  150  that generates the standard voltage Vref or a second output terminal T 4  of the differential amplifier circuit  110  via the switch SW 70 . Furthermore, the switch SW 80  is connected between the output terminals T 3  and T 4  of the differential amplifier circuit  110 . 
         [0024]    The other end of the switch SW 40  is connected to an inverting input terminal T 5  of the differential amplifier circuit  120 . The inverting input terminal T 5  of the differential amplifier circuit  120  is connected to a first output terminal T 7  of the differential amplifier circuit  120 . The other end of the switch SW 50  is connected to a non-inverting input terminal T 6  of the differential amplifier circuit  120 . The non-inverting input terminal T 6  of the differential amplifier circuit  120  is connected to a second output terminal T 8  of the differential amplifier circuit  120 . Accordingly, the input and output terminals of the differential amplifier circuit  120  are short-circuited. In this embodiment, the voltage of the inverting input terminal T 5  of the differential amplifier circuit  120  is defined as a first reference voltage (voltage Vc 1 ), and the voltage of the non-inverting input terminal T 6  thereof is defined as a second reference voltage (voltage Vc 2 ). 
         [0025]    In this embodiment, the configuration of the differential amplifier circuit  120  is the same as that of the differential amplifier circuit  110 . In other words, the offset voltage of the differential amplifier circuit  120  is set to be equal to that of the differential amplifier circuit  110 . 
         [0026]    With this configuration, the following problem can be solved in this embodiment. For example, when a potential difference between the signals input to the input terminals Vip and Vim is about 1 V in the amplifier circuit  100  of this embodiment, an offset voltage Voff depends on the manufacturing tolerance of transistors inside the differential amplifier circuit  110 . Here, several millivolts (mV) of offset voltages are generated. The gain accuracy demanded under an environment in which the amplifier circuit  100  of this embodiment is used is about 1/1000. Therefore, an error caused by the offset voltage exceeds a tolerance, which results in degradation in the characteristics of the amplifier circuit  100 . 
         [0027]    In order to deal with the above problem, the offset voltage of the differential amplifier circuit  110  is cancelled to eliminate influences due to the offset voltage in this embodiment. 
         [0028]    The operations of the amplifier circuit  100  are described below. 
         [0029]    First, a sampling operation in the amplifier circuit  100  of this embodiment is described. At the sampling operation in the amplifier circuit  100  of this embodiment, the switches SW 10 , SW 20 , SW 40 , SW 50 , and SW 80  are turned on, and the switch SW 30  is turned off. Furthermore, the switches SW 60  and SW 70  are connected to the standard voltage sources  140  and  150  that generate the standard voltage Vref, respectively. 
         [0030]    At this time, signals from the external device  130  are input to the input terminals Vip and Vim of the amplifier circuit  100 , and a reference voltage Vc 1  is supplied to the capacitor Cs 1  via the switch SW 40 . Furthermore, a reference voltage Vc 2  is supplied to the capacitor Cs 2  via the switch SW 50 . Accordingly, an electrical charge corresponding to a potential difference between the reference voltage Vc 1  and the signal supplied to the input terminal Vip is stored in the capacitor Cs 1 . Furthermore, an electrical charge corresponding to a potential difference between the reference voltage Vc 2  and the signal supplied to the input terminal Vim is stored in the capacitor Cs 2 . 
         [0031]    Furthermore, an electrical charge corresponding to a potential difference between the standard voltage Vref and the reference voltage Vc 1  is stored in the capacitor Cf 1  via the switch SW 60 . Furthermore, an electrical charge corresponding to a potential difference between the standard voltage Vref and the reference voltage Vc 2  is stored in the capacitor Cf 2  via the switch SW 70 . 
         [0032]    Here, the input and output terminals of the differential amplifier circuit  120  are short-circuited. Therefore, the reference voltage Vc 1  output from the output terminal T 7  of the differential amplifier circuit  120  and the reference voltage Vc 2  output from the output terminal T 8  thereof are output with the potential difference corresponding to the offset voltage of the differential amplifier circuit  120 . 
         [0033]    Next, an operation in the amplifier circuit  100  of this embodiment after the completion of the sampling operation is described. 
         [0034]    When the sampling operation is completed to establish a signal output state in the amplifier circuit of this embodiment, the switches SW 10 , SW 20 , SW 40 , SW 50 , and SW 80  are turned off, and the switch SW 30  is turned on. Furthermore, the switch SW 60  is connected to the output terminal T 3  of the differential amplifier circuit  110 , and the switch SW 70  is connected to the output terminal T 4  thereof. 
         [0035]    At this time, the capacitors Cs 1  and Cs 2  are short-circuited by the switch SW 30  to have the same potential. Therefore, the electrical charges are moved to the capacitors Cf 1  and Cf 2 . Accordingly, a potential difference (Vop−Vom) between the voltages of the output terminals T 3  and T 4  of the differential amplifier circuit  110  is calculated according to the following formula (3). 
         [0000]        Vo=Vop−Vom=Cs/Cf×{ ( Vip−Vc 1)−( Vim−Vc 2)+ Voff}   (3) 
         [0036]    The offset voltage Voff is included in the above formula (3). Therefore, an error is caused in the output voltage Vo. In this embodiment, however, a potential difference between the reference voltages Vc 1  and Vc 2  is equal to the offset voltage Voff of the differential amplifier circuit  110 . Therefore, the output voltage Vo is finally calculated according to the following formula (4). 
         [0000]        Vo=Vop−Vom=Cs/Cf×{ ( Vip−Vc 1)−( Vim−Vc 1 +Voff )+ Voff}=Cs/Cf× ( Vip−Vim )  (4) 
         [0037]    According to the above formula (4), it is found that the offset voltage Voff is cancelled. 
         [0038]    As described above, the amplifier circuit  100  of this embodiment is provided with the differential amplifier circuit  120  that supplies the reference voltages Vc 1  and Vc 2  having the same potential difference as the offset voltage Voff of the difference amplifier circuit  110 . Therefore, the offset voltage Voff of the differential amplifier circuit  110  can be cancelled. As a result, according to this embodiment of the present invention, the characteristics of the amplifier circuit  100  can be improved without being influenced by the offset voltage. 
       Second Embodiment 
       [0039]    Referring to the accompanying drawing, a description is now made of a second embodiment of the present invention. The second embodiment of the present invention is different from the first embodiment only in that it is provided with switches SW 90  and SW 100  instead of the switch SW 30  of the first embodiment. Therefore, a description is made only of the difference between the first and second embodiments. In addition, components the same as those of the first embodiment are denoted by the same reference numerals and their descriptions are omitted in this embodiment. 
         [0040]      FIG. 3  shows an amplifier circuit  100 A of the second embodiment. In the amplifier circuit  100 A of this embodiment, the switch SW 30  of the first embodiment that short-circuits the capacitors Cs 1  and Cs 2  is replaced by the switches SW 90  and SW 100 . 
         [0041]    One end of the switch SW 90  is connected to one end of the capacitor Cs 1 , and the other end thereof is connected to the input terminal T 5  of the differential amplifier circuit  120 . Furthermore, one end of the switch SW 100  is connected to one end of the capacitor Cs 2 , and the other end thereof is connected to the input terminal T 6  of the differential amplifier circuit  120 . 
         [0042]    The switches SW 90  and SW 100  are turned on and off at the same timing as the switch SW 30  of the first embodiment. In other words, the switches SW 90  and SW 100  are turned off at the sampling operation and turned on when the sampling operation is completed to establish a signal output state. 
         [0043]    With this configuration, the input terminals T 5  and T 6  of the differential amplifier circuit  120  are connected to the capacitors Cs 1  and Cs 2 , respectively, in the signal output state in this embodiment. Accordingly, in this embodiment, the voltages of the input terminals T 1  and T 2  are fixed in the signal output state. Therefore, it is possible to further ensure the time (settling time) required until sampling of the input signals of input voltages using a difference in on-resistance between the switches of the amplifier circuit  100 A is enabled. As a result, the distortions of an output voltage can be reduced. 
       Third Embodiment 
       [0044]    Referring to the accompanying drawing, a description is now made of a third embodiment of the present invention. The third embodiment of the present invention is a modification of the amplifier circuit  100 A of the second embodiment. Therefore, a description is made only of the difference between the second and third embodiments. In addition, components the same as those of the second embodiment are denoted by the same reference numerals and their descriptions are omitted in this embodiment. 
         [0045]      FIG. 4  shows an amplifier circuit  100 B of the third embodiment. The amplifier circuit  100 B of this embodiment is different from the amplifier circuit  100 A of the second embodiment in that it has capacitors C 1  and C 2  for ensuring an output provided in the output terminals T 7  and T 8  of the differential amplifier circuit  120 . 
         [0046]    In this embodiment, the output voltages of the output terminals T 7  and T 8  are ensured by the capacitors C 1  and C 2 . Therefore, a switching noise called a kickback can be reduced. As a result, the characteristics of the amplifier circuit  100 B can be further improved. 
         [0047]    Note that it is described in the first through third embodiments that the configuration of the differential amplifier circuit  120  has the same configuration as that of the differential amplifier circuit  110 . However, the configuration of the differential amplifier circuit  120  is not limited to this. 
         [0048]    For example, the size of internal devices such as transistors constituting the differential amplifier circuit  120  may be different from that of internal devices constituting the differential amplifier circuit  110 . 
         [0049]    If the size of the internal devices constituting the differential amplifier circuit  120  is made smaller than that of the internal devices constituting the differential amplifier circuit  110 , the amplifier circuit of the embodiments of the present invention can be downsized and the consumption power thereof can be reduced. 
         [0050]    Furthermore, if the size of the internal devices constituting the differential amplifier circuit  120  is made larger than that of the internal devices constituting the differential amplifier circuit  110 , an output voltage can be further ensured, which is effective for a large kickback. 
         [0051]    According to the embodiments of the present invention, the characteristics of the amplifier circuit can be improved without being influenced by an offset voltage. 
         [0052]    The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention. 
         [0053]    The present application is based on Japanese Priority Application No. 2008-068460 filed on Mar. 17, 2008, the entire contents of which are hereby incorporated herein by reference.

Technology Classification (CPC): 7