Patent Abstract:
A phase-locked loop circuit includes a phase and frequency detector receiving a reference signal and an output signal of the phase-locked loop circuit for generating a detected signal representing a frequency or phase difference therebetween. A digital charge pump coupled to the phase and frequency detector generates a charge control signal in response to the detected signal. A mixed mode loop filter coupled to the digital charge pump filters the charge control signal and generates an oscillation control signal. A voltage controlled oscillator is coupled to the mixed mode loop filter for generating the output signal of the phase-locked loop circuit by adjusting its oscillation frequency in response to the oscillation control signal. The mixed mode loop filter has both digital and analog characteristics in carrying out filtering the charge control signal, thereby reducing a layout area for the same to be implemented on a semiconductor substrate.

Full Description:
BACKGROUND  
       [0001]     The present invention relates generally to integrated circuit (IC) designs, and more particularly to a phase-locked loop (PLL) circuit with a mixed mode filter for reducing the implementation area of the PLL circuit.  
         [0002]     PLL circuits are commonly used in circuits that generate a high-frequency signal with a frequency being an accurate multiple of the frequency of a reference signal. PLL circuits can also be found in applications where the phase of the output signal has to track the phase of the reference signal, hence the name phase-locked loop. For example, the PLL circuit can be used in a radio receiver or transmitter for generating a local oscillator signal, which is a multiple of a stable, low-noise and often temperature-compensated reference signal. As another example, the PLL circuit can also be used for clock recovery applications in digital communication systems, disk-drive read-channels, etc.  
         [0003]     A conventional PLL circuit typically includes a phase and frequency detector, a charge pump, a loop filter, a voltage control oscillator and a feedback divider. The loop filter can be either analog or digital. The analog loop filter can be a passive filter composed of inductors, capacitors, and resistors, or an active filter composed of resistors, capacitors, and amplifiers. The digital loop filter is composed of building blocks, such as adders, delay units, and multipliers.  
         [0004]     The analog loop filter combines a resistor in series with a capacitor. The stability of the analog PLL circuit is proportional to the values of the resistor and capacitor. Conventionally, the value of capacitor is set approximately from 100 pF to 300 pF in order to avoid instability. The large capacitor causes the PLL circuit to be large in size.  
         [0005]     The digital loop filter combines a digital amplifier, adder and delay unit, and is realizable in a smaller area compared to the analog loop filter. However, a digital-to-analog converter requires an interface with the analog voltage control oscillator. The area of digital-to-analog converter is small at low resolutions and large at high resolutions. In order to obtain a high accuracy, the digital-to-analog converter for the PLL circuit needs to have a high resolution (10˜14 bits). Thus, the area occupied by the digital PLL circuit is large due to the high resolution digital-to-analog converter, in spite of the small area occupied by the digital loop filter.  
         [0006]     As such, it is desirable to have a PLL circuit that provides high accuracy and occupies minimum areas.  
       SUMMARY  
       [0007]     The present invention discloses a phase-locked loop circuit, which includes a phase and frequency detector receiving a reference signal and an output signal of the phase-locked loop circuit for generating a detected signal representing a difference between the reference signal and the output signal in frequency or phase. A digital charge pump is coupled to the phase and frequency detector for generating a charge control signal in response to the detected signal. A mixed mode loop filter is coupled to the digital charge pump for filtering the charge control signal and generating an oscillation control signal. A voltage controlled oscillator is coupled to the mixed mode loop filter for generating the output signal of the phase-locked loop circuit by adjusting its oscillation frequency in response to the oscillation control signal. The mixed mode loop filter has both digital and analog characteristics in carrying out filtering the charge control signal, thereby reducing a layout area for the same to be implemented on a semiconductor substrate.  
         [0008]     The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIGS. 1A and 1B  illustrate a conventional analog PLL circuit.  
         [0010]      FIGS. 2A and 2B  illustrate a conventional digital PLL circuit.  
         [0011]      FIG. 3  illustrates a PLL circuit with a mixed mode loop filter in accordance with one embodiment of the present invention.  
         [0012]      FIG. 4  illustrates a block diagram of the mixed mode loop filter in accordance with one embodiment of the present invention.  
         [0013]      FIG. 5  illustrates a digital adder for the mixed mode loop filter in accordance with one embodiment of the present invention.  
         [0014]      FIG. 6  illustrates an analog integrator for the mixed mode loop filter in accordance with one embodiment of the present invention.  
         [0015]      FIG. 7  illustrates a digital-to-analog converter for the mixed mode loop filter in accordance with one embodiment of the present invention.  
     
    
     DESCRIPTION  
       [0016]      FIG. 1A  illustrates a conventional analog PLL circuit  100 . The phase and frequency detector  102  receives two inputs, a reference frequency signal FREF and an oscillating output signal FOUT from the feedback loop. The phase and frequency detector  102  serves as an “error amplifier” in the feedback loop for minimizing the phase difference, Δφ, between FREF and FOUT. The phase and frequency detector  102  produces a sequence of UP or DOWN pulses to switch the charge pump  104  for charging or discharging a capacitor, as determined by the phase and frequency detector  102 . An analog loop filter  106  is used to limit the rate of change of capacitor voltage, thereby generating a slowly rising or falling voltage that depends on the frequency difference between FREF and FOUT. The voltage controlled oscillator  108  receives signals from the analog loop filter  106 , and increases or decreases its frequency of operation as the signals output from the analog loop filter  106  increase or decrease. The feedback divider  110  in the feedback loop provides an option to increase the frequency of FOUT by a predetermined ratio. The characteristics of the charge pump  104 , the analog loop filter  106  and the voltage-controlled oscillator  108  determine the phase and frequency response of the analog PLL circuit  100 .  
         [0017]      FIG. 1B  schematically illustrates the analog loop filter  106 , which combines a resistor R in series with a capacitor C. The transfer function for the analog loop filter  106  in the S-domain can be described as follows:  
                 T   ⁡     (   S   )       loop_filter     =       Y   X     =       1   +   SCR     SC               (   1   )               
         [0018]     where X represents the signal at node x, Y represents the signal at node y, C represents the capacitance of capacitor C, and R represents the resistance of resistor R. In order to improve the stability of analog loop filter  106 , it is desirable to increase the capacitance of the capacitor C. Conventionally, the capacitance of capacitor C ranges from 100 pF to 300 pF in order to avoid instability. This causes the capacitor C to be large in size. This, in turn, causes the conventional analog PLL circuit to be inefficient in layout area when it is implemented on a semiconductor substrate.  
         [0019]      FIG. 2A  illustrates a conventional digital PLL circuit  150 . The phase and frequency detector  102  receives two inputs, a reference frequency signal FREF and an oscillating output signal FOUT from the feedback loop. The phase and frequency detector  102  produces a sequence of UP or DOWN pulses to switch the digital charge pump  105 . A digital loop filter  107  is connected to the output of the digital charge pump  105 . A digital-to-analog converter  109  interfaces the digital loop filter  107  to the voltage controlled oscillator  108 . The voltage-controlled oscillator  108  increases or decreases its frequency of operation as the control voltage at its input increases or decreases. The feedback divider  110  in the feedback loop provides an option to increase FOUT by a predetermined ratio. The characteristics of the charge pump  105 , the digital loop filter  107 , the digital-to-analog converter  109 , and the voltage controlled oscillator  108  determine the phase and frequency response of the digital PLL circuit  150 .  
         [0020]      FIG. 1B  schematically illustrates the digital loop filter  107 , which combines one or more digital amplifiers  117  and  119  with gains A 1  and A 2 , respectively, one or more adders  111  and  113 , and a multiplier  115 , which multiplies the output from the adder  111  by Z −1 . The transfer function for the digital loop filter  107  in the Z-domain is derived as follows:  
                 T   ⁡     (   Z   )       loop_filter     =       X   Y     =         A   ⁢           ⁢   1       1   -     Z     -   1           +     A   ⁢           ⁢   2                 (   2   )               
         [0021]     where X represents the signal at node x, and Y represents the signal at node y.  
         [0022]     The digital loop filter  107  does not need to be large in order to avoid system instability, so that is can be made in a small area. However, in order to accurately convert the digital outputs of the digital loop filter  107 , the digital-to-analog converter  109  needs to be in high resolution. The higher the resolution, the larger the area occupied by the digital-to-analog converter  109 . Conventionally, the digital-to-analog converter  109  needs to have a resolution between 10 and 14 bits in order to obtain a good accuracy. This results in a large digital-to-analog converter  109 , and therefore causes the digital PLL circuit  150  shown in  FIG. 2A  to be inefficient in layout area when it is implemented on a semiconductor substrate.  
         [0023]      FIG. 3  illustrates the architecture of the proposed PLL circuit  300  with a mixed mode loop filter  306  in accordance with one embodiment of the present invention. The PLL circuit  300  includes a phase and frequency detector  302 , a digital charge pump  304 , a mixed mode loop filter  306 , a voltage controlled oscillator  308  and a feedback divider  310 . The phase and frequency detector  302  receives two inputs, a reference frequency signal FREF and an oscillating output signal FOUT from the feedback loop. The phase and frequency detector  302  produces a sequence of UP or DOWN pulses to switch the digital charge pump  304 . The mixed mode loop filter  306  is connected to the output of the digital charge pump  304 , and outputs analog signals to the voltage controlled oscillator  308 . The voltage-controlled oscillator  308  increases or decreases its frequency of operation as the control voltage at its input increases or decreases. The feedback divider  310  in the feedback loop provides an option to increase FOUT by a predetermined ratio. The characteristics of the charge pump  302 , the mixed mode loop filter  306 , and the voltage controlled oscillator  308  determine the phase and frequency response of the PLL circuit  300 .  
         [0024]      FIG. 4  illustrates a block diagram of the mixed mode loop filter  306  in accordance with one embodiment of the present invention. The mixed mode loop filter  306  includes a digital adder  402 , an analog integrator  406 , and a digital-to-analog converter circuit  404  that interfaces therebetween. The transfer function of the mixed mode loop filter  306  in the Z-domain can be described by equation (2). The following equations can be derived therefrom.  
                 T   ⁡     (   Z   )       loop_filter     =       X   Y     =         (       A   ⁢           ⁢   1     +     A   ⁢           ⁢   2       )     -     A   ⁢           ⁢   2   ×     Z     -   1             1   -     Z     -   1                     (   3   )                   T   ⁡     (   Z   )       loop_filter     =       X   Y     =           (       A   ⁢           ⁢   1     +     A   ⁢           ⁢   2       )     -     A   ⁢           ⁢   2   ×     Z     -   1           1     ×     1     1   -     Z     -   1                       (   4   )                   T   ⁡     (     Z   ,   S     )       loop_filter     =       X   Y     =           (       A   ⁢           ⁢   1     +     A   ⁢           ⁢   2       )     -     A   ⁢           ⁢   2   ×     Z     -   1           1     ×     1   S                 (   5   )               
 The digital adder  402  realizes the first part of the equation, (A 1 +A 2 )−A 2 ×Z −1 , and the analog integrator  406  realizes second part of the equation, 1/S. The conversion from digital-to-analog is accomplished by the digital-to-analog converter  404 . Since the transfer function is realized using both digital and analog circuits, it is named mixed mode loop filter  306 . 
 
         [0025]      FIG. 5  schematically illustrates the digital adder  402  in detail in accordance with one embodiment of the present invention. The digital adder  402  includes two digital amplifiers  401  and  403  with gains A 1  and A 2 , respectively, coupled a node x for receiving the output from the digital charge pump  304  shown in  FIG. 3 . The outputs of the digital amplifiers  401  and  403  are added together by the adder  407 , and then the summation is output to the adder  409 , which also receives an output from a multiplier  405 , which multiplies the output from the amplifier  403  by Z −1 . The adder  409  then subtracts the output of the multiplier  405  from the output of the adder  407 , and generates an output to a node E. The adder  402  is digital in nature and can be made small in size.  
         [0026]      FIG. 6  schematically illustrates the analog integrator  406  in detail in accordance with one embodiment of the present invention. The analog integrator  406  includes a switch device with a PMOS transistor P 1  and an NMOS transistor N 1 . The sources of the PMOS and NMOS transistors P 1  and N 1  are coupled to current sources, respectively. The gates of the transistors P 1  and N 1  receive the input from the digital-to-analog converter  404  (shown in  FIG. 4 ), and their drains are connected together to an output node y. A capacitor C is connected between the output node y and ground. The pulse width of the output of the digital-to-analog converter  404  controls the time for charging or discharging the capacitor C. The current charge and discharge realizes the integration function with the capacitor C of a small capacitance value, such as 2 pF˜15 pF. Thus, the analog integrator  406  can be made small in size.  
         [0027]      FIG. 7  schematically illustrates the analog to digital converter  404  in detail in accordance with one embodiment of the present invention. In this embodiment, the digital-to-analog converter includes a variable delay unit D 1 , a controller T 1 , inverters I 1 , I 2  and three input AND gates N 2 , N 3 . One input to the digital-to-analog converter  404  is a sampling pulse from the phase and frequency decoder, and another is the digital output of the digital adder  402 . The pulse provides the first input to the AND gates N 2 , N 3 , the output of the inverter I 1  and delay unit D 1  provides the second input to the AND gates N 2 , N 3 , and the output of controller T 1  provides the third input to the AND gates N 2 , N 3 . The controller T 1  generates a charging signal to the AND gate N 2  when the output signal from the digital adder  402  is greater than or equal to zero. The controller T 1  generates a discharging signal to the AND gate N 3  when the output signal from the digital adder  402  is smaller than zero. The outputs of the AND gates N 1 , N 2  are connected to the gates of the transistors P 1 , N 1  of the analog integrator  406 . The digital charge pump  304  (shown in  FIG. 3 ) has an infinite gain so that a low resolution digital-to-analog converter  404  (1-bit˜5-bit) is sufficient to interface between the digital adder  402  and the analog integrator  406  to obtain the necessary resolution. A low resolution digital-to-analog converter  404  occupies less area.  
         [0028]     The proposed mixed mode loop filter takes the advantages of the digital loop filter and analog loop filter and results in a PLL circuit that has high accuracy but occupies minimum area. The zero is realized using a digital adder which occupies minimum area, and the pole is realized in analog integrator with a small capacitor which occupies minimum area. A low resolution digital-to-analog converter used to interface the digital adder and analog integrator also occupies a minimum area. Thus, the mixed mode PLL circuit can be realized with a minimum area.  
         [0029]     The following table compares the proposed mixed mode PLL circuit with the conventional analog and digital PLL circuits.  
                                                   TABLE 1                           Comparison of multi-mode PLL verses analog PLL and digital PLL                Analog PLL   Digital PLL   Proposed Mixed           Circuit   Circuit   mode PLL Circuit                        Charge Pump   Analog   Digital   Digital       Loop Filter   Analog   Digital   Mixed-mode       DAC   —   High resolution   Low resolution       Capacitor   Large   —   Small       Accuracy   High   Low   High       Scaleable   No   No   Yes       Area   Large   Large   Small                  
 
         [0030]     The above illustration provides many different embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0031]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.

Technology Classification (CPC): 7