Patent Abstract:
A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.

Full Description:
RELATED APPLICATION  
       [0001]     A related, copending application is entitled “Method of Forming a Transistor with a Bottom Gate,” by Thuy Dao, application Ser. No. 10/871,402, Attorney Docket No. SC13338TP, assigned to Freescale Semiconductor, Inc., and was filed on Jun. 18, 2004. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates in general to semiconductor devices and more specifically to a back-gated semiconductor device with a storage layer and methods for forming thereof.  
         [0004]     2. Description of the Related Art  
         [0005]     Traditional single gate and double gate Fully Depleted Semiconductor-on-Insulator (FDSOI) transistors have advantages related to reduced short channel effects and reduced un-wanted parasitic capacitances. However, when used as a non-volatile memory these transistors require programming, such as hot carrier injection (HCI) programming. HCI programming results in generation of holes because of impact ionization. Because of the floating nature of the body in such FDSOI devices, however, holes generated due to impact ionization may accumulate in the body of such FDSOI devices. Accumulated holes may then generate enough potential to cause problems, such as snap-back of the FDSOI devices.  
         [0006]     Thus, there is a need for improved FDSOI transistors and methods of forming thereof. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.  
         [0008]      FIG. 1  is a side view of one embodiment of two wafers being bonded together to form a resultant wafer, consistent with one embodiment of the invention;  
         [0009]      FIG. 2  shows a side view of one embodiment of a bonded wafer, consistent with one embodiment of the invention;  
         [0010]      FIG. 3  shows a partial cross-sectional side view of one embodiment of a wafer during a stage in its manufacture, consistent with one embodiment of the invention;  
         [0011]      FIG. 4  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0012]      FIG. 5  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0013]      FIG. 6  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0014]      FIG. 7  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0015]      FIG. 8  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0016]      FIG. 9  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0017]      FIG. 10  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0018]      FIG. 11  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0019]      FIG. 12  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0020]      FIG. 13  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention;  
         [0021]      FIG. 14  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention; and  
         [0022]      FIG. 15  shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention. 
     
    
       [0023]     Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.  
       DETAILED DESCRIPTION  
       [0024]     The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.  
         [0025]     A back-gated non-volatile memory (NVM) device with its channel available for contacting to overcome the typical problem of charge accumulation associated with NVMs in semiconductor on insulator (SOI) substrates is provided. A substrate supports the gate. A storage layer is formed on the gate, which may be nanocrystals encapsulated in an insulating layer, but could be of another type such as nitride. A channel is formed on the storage layer. A conductive region, which can be conveniently contacted, is formed on the channel. This results in an escape path for minority carriers that are generated during programming, thereby avoiding charge accumulation in or near the channel. This is achievable with a method that includes bonding two wafers, cleaving away most of one of the wafers, forming the conductive region after the cleaving, and epitaxially growing the source/drains laterally from the channel while the conductive region is isolated from this growth with a sidewall spacer.  
         [0026]      FIG. 1  shows a side view of two wafers  101  and  103  that are to be bonded together to form a resultant wafer ( 201  of  FIG. 2 ), from which non-volatile memory cells may be formed, for example. Wafer  101  includes a layer  109  of gate material, a storage layer  107 , and semiconductor substrate  105 . By way of example, substrate  105  is made of monocrystaline silicon, but in other embodiments, may be made of other types of semiconductor materials such as silicon carbon, silicon germanium, germanium, type III-V semiconductor materials, type II-VI semiconductor materials, and combinations thereof including multiple layers of different semiconductor materials. In some embodiments, semiconductor material of substrate  105  may be strained. Storage layer  107  may be a thin film storage layer or stack and may be made of any suitable material, such as nitrides or nanocrystals. Nanocrystals, such as metal nanocrystals, semiconductor (e.g., silicon, germanium, gallium arsenide) nanocrystals, or a combination thereof may be used. Storage layer  107  may be formed by a chemical vapor deposition process, a sputtering process, or another suitable deposition process.  
         [0027]     Referring still to  FIG. 1 , by way of example, layer  109  includes doped polysilicon, but may be made of other materials such as, amorphous silicon, tungsten, tungsten silicon, germanium, amorphous germanium, titanium, titanium nitride, titanium silicon, titanium silicon nitride, tantalum, tantalum silicon, tantalum silicon nitride, other silicide materials, other metals, or combinations thereof including multiple layers of different conductive materials. An insulator  111  may be formed (e.g., grown or deposited) on layer  109 . In one embodiment, insulator  111  includes silicon oxide, but may include other materials such as e.g. PSG, FSG, silicon nitride, and/or other types of dielectric including high thermal, conductive dielectric materials.  
         [0028]     Wafer  103  may include a substrate  115  (e.g., silicon) with an insulator  113  formed on it. In one embodiment, the material of insulator  113  is the same as the material of insulator  111 . By way of example, wafer  103  includes a metal layer (not shown) at a location in the middle of insulator  113 . This metal layer may be utilized for noise reduction in analog devices built from resultant wafer  201 .  
         [0029]     Wafer  101  is shown inverted so as to be bonded to wafer  103  in the orientation shown in  FIG. 1 . In one embodiment, insulator  111  is bonded to insulator  113  with a bonding material. In other embodiments, wafer  101  may be bonded to wafer  103  using other bonding techniques. For example, in one embodiment, wafer  101  may be bonded to wafer  103  by electrostatic bonding followed by thermal bonding or pressure bonding.  
         [0030]     In some embodiments, wafer  101  does not include insulator  111  where layer  109  is bonded to insulator  113 . In other embodiments, wafer  103  does not include insulator  113  where insulator  111  is bonded to substrate  115 .  
         [0031]     Wafer  101  may include a stress layer  106  formed by implanting a dopant (e.g. H+) into substrate  105 . In some embodiments, the dopant is implanted prior to the formation of storage layer  107 , but in other embodiments, may be implanted at other times including after the formation of storage layer  107  and prior to the formation of layer  109 , after the formation of layer  109  and prior to the formation of insulator  111 , or after the formation of insulator  111 . In other embodiments, the dopant for forming stress layer  106  may be implanted after wafer  103  has been bonded to wafer  101 .  
         [0032]      FIG. 2  shows a side view of resultant wafer  201  after wafer  103  and  101  have been bonded together. The view in  FIG. 2  also shows wafer  201  after a top portion of substrate  105  has been removed, e.g., by cleaving. By way of example, cleaving is performed by dividing substrate  105  at stress layer  106 . Layer  203  is the remaining portion of substrate  105  after the cleaving. One advantage of forming the layer by cleaving is that it may allow for a channel region to be formed from a relatively pure and crystalline structure as opposed to a semiconductor layer that is grown or deposited on a dielectric.  
         [0033]      FIG. 3  shows a partial side cross-sectional view of wafer  201 . Not shown in the view of  FIG. 3  (or in subsequent Figures) are insulator  113  and substrate  115 . After substrate  105  is cleaved to form layer  203 , an oxide layer  303  is formed over layer  203 . Layer  303  may be thicker than layer  203 . Next, as shown in  FIG. 4 , a layer of polysilicon, to form conductive region  401 , may be deposited over oxide layer  303  after a middle portion of oxide layer  303  is patterned and then etched away. Thus, polysilicon layer is deposited directly on the transistor channel. The polysilicon layer may be doped in-situ or doped by implantation. Appropriate doping materials may be used depending on the type of device being manufactured. Conductive region  401  may be used as a well contact. If necessary, an appropriate pre-clean may be performed to remove any interfacial oxide layer. Conductive region  401  may remove minority carriers, such as holes from the channel region  203  of a transistor formed from wafer  201 .  
         [0034]     Next, as shown in  FIG. 5 , polysilicon layer forming conductive region  401  may be planarized by chemical-mechanical polishing, for example. Furthermore, a portion from top part of polysilicon layer forming conductive region  401  may be etched and a nitride cap  501  may be formed on top of conductive region  401 . In one embodiment, nitride cap  501  should be at least as thick as layer  203  so that nitride cap  501  may serve as an implant mask during implantation described with respect to  FIG. 7 . This would ensure the doping of layer  401  is unaltered during implantation. Referring now to  FIG. 6 , a liner  601 , such as an oxide liner may be formed after oxide layer  303  is removed.  
         [0035]     Next, as shown in  FIG. 7 , two implants  701  may be performed. First, amorphization implants may be performed in portions  707 / 709 . By way of example, germanium may be used to perform amorphization implants. Second, source/drain implants may be performed in portions  703 / 705  to form source/drain extensions. Appropriate n-type or p-type dopants may be used as part of this step. The region ( 203 ) under conductive region  401  may serve as a channel region. Referring now to  FIG. 8 , a spacer  801  may be formed on the sidewalls of conductive region  401  (lined by liner  601 ). Spacer  801  may be made of multiple layers of dielectric materials. Spacer  801  may protect certain portions of portions  703 / 705  during subsequent processing. Next, exposed portions of portions  703 / 705  may be etched away.  
         [0036]     Next, as shown in  FIG. 9 , a second spacer  901  may be formed to protect sidewalls of portions  703 / 705 . Furthermore, portions  707 / 709  implanted with amorphization implants may be etched away. Referring now to  FIG. 10 , an oxide layer  1001  may be deposited on wafer  201 . Next, as shown in  FIG. 11 , selected portions of oxide layer  1001  may be etched away. Etching of selected portions of oxide layer  1001  may result in partial etching of liner  601 , as well.  FIG. 12  shows a partial cross-sectional side view of wafer  201  after structures  1201  and  1203  are epitaxially grown on the exposed sidewalls of channel region (including portion  203 ).  
         [0037]     Referring to  FIG. 13  now, an amorphous silicon layer  1301 / 1303  may be deposited. Amorphous silicon layer  1301 / 1303  may be subjected to chemical mechanical polishing and etched back. Next, as shown in  FIG. 14 , a photoresist layer  1401  may be formed on top of a selected portion of wafer  201  and source/drain implants  1403  may be made forming doped source/drain regions  1405  and  1411 . Next, as shown in  FIG. 15 , silicides  1501 ,  1503 , and  1505  may be formed after nitride cap  501  is stripped. Gate silicide  1503  may be formed on top of conductive region  401 . By way of example, silicides may be formed using a silicide implantation (e.g., cobalt or nickel) followed by a heat treatment. Alternatively, silicides may be formed by depositing a layer of metal over the wafer and reacting the metal with the underlying material.  
         [0038]     By way of example, the semiconductor device formed on wafer  201  may be used as a non-volatile memory. The non-volatile memory may include cells formed of the semiconductor device, which may be programmed using techniques such as, hot carrier injection. For example, using HCI, one bit per cell may be stored in storage layer  107  by applying a positive bias voltage to gate  109 , applying a positive voltage to drain region  1411 , grounding source region  1405 , and applying a negative voltage to conductive region  401  or grounding conductive region  401 . HCI programming may result in generation of minority carriers, such as holes because of impact ionization. Conductive region  401  may provide an escape path for holes thereby preventing accumulation of holes in channel region  203 .  
         [0039]     In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.  
         [0040]     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Technology Classification (CPC): 1