Patent Abstract:
A data transfer interface apparatus and method for controlling data transfer. The data transfer interface apparatus includes a first storage unit for storing an input data according to a first clock and for outputting a first output data according to a second clock, a single-port memory coupled to the first storage unit for storing the first output data according to the second clock and for outputting a second output data according to the second clock, and a second storage unit coupled to the single-port memory for storing the second output data according to the second clock and for outputting a third output data according to a third clock.

Full Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a data transfer method and apparatus, and more particularly, to a data transfer interface apparatus with a small chip area for controlling data transfer and method thereof.  
         [0003]     2. Description of the Prior Art  
         [0004]     An important component in electronics is a data transfer interface device. A data transfer interface device performs the important task of transferring and buffering data output from a device A to a device B. Oftentimes, the data from the device A cannot be directly transferred into the device B because of different operating environments in the devices A and B (e.g. the operating frequencies of device A and device B differ), thus necessitating the presence of the data transfer interface device. For instance, the data transfer interface device functions as a buffer positioned between the device A and the device B for coordinating data transfer in different clock domains.  
         [0005]     Presently, the most common embodiment of a data transfer interface device is a first in/first out (FIFO) storage unit. The FIFO storage unit accepts data inputted at a first frequency and outputs data at a second frequency. Among the drawbacks of such an FIFO storage unit that buffers data delivered between two devices, the two more prominent ones are the expense and the chip size taken up by the FIFO storage unit. While expense is a self-explanatory disadvantage, size is a disadvantage because space on the circuit board is at a premium. Bigger chip size means less space available for other parts. In other words, if the FIFO storage unit is used to implement the data transfer interface device, the size of the circuit board is required to be big enough to accommodate the installed FIFO storage unit.  
       SUMMARY OF INVENTION  
       [0006]     It is therefore one of the many objectives of the claimed invention to provide a data transfer interface device and method thereof.  
         [0007]     According to the claimed invention, a data transfer interface apparatus is disclosed. The data transfer interface apparatus comprises a first storage unit for storing an input data according to a first clock and for outputting a first output data according to a second clock, a single-port memory coupled to the first storage unit for storing the first output data according to the second clock and for outputting a second output data according to the second clock, and a second storage unit coupled to the single-port memory for storing the second output data according to the second clock and for outputting a third output data according to a third clock.  
         [0008]     Also according to the claimed invention, a data transfer interface apparatus is disclosed. The data transfer interface apparatus comprises a single-port memory for storing an input data according to a first clock and for outputting a first output data according to a second clock; and a dual-port memory coupled to the single-port memory, for storing the first output data according to the second clock and for outputting a second output data according to a second clock.  
         [0009]     Further according to the claimed invention, a data transfer interface apparatus is disclosed. The data transfer interface apparatus comprises a dual-port memory for storing an input data according to a first clock and for outputting a first output data according to a second clock; and a single-port memory coupled to the dual-port memory, for storing the first output data according to the second clock and for outputting a second output data according to the second clock.  
         [0010]     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0011]      FIG. 1  is a block diagram of a data transfer interface device according to a first embodiment of the present invention.  
         [0012]      FIG. 2  is a schematic diagram illustrating the data transfer interface device applied in the display or television field.  
         [0013]      FIG. 3  is a block diagram of a data transfer interface device according to a second embodiment of the present invention.  
         [0014]      FIG. 4  is a block diagram of a data transfer interface device according to a third embodiment of the present invention.  
         [0015]      FIG. 5  is a block diagram of a data transfer interface device according to a fourth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]     Please refer to  FIG. 1 .  FIG. 1  is a block diagram of a data transfer interface device  10  according to an embodiment of the present invention. In this preferred embodiment, the data transfer interface device  10  comprises two asynchronous storage units (the FIFO storage units  22  and  26 ) and a single-port memory  24 . The two FIFO storage units  22 ,  26 , and the single-port memory  24  are clocked to receive and output data according to clock signals generated by a clock generator  28 , whereof details will be described hereinafter shortly. Please note that the FIFO storage units  22 ,  26  can be embodied by dual-port memories. In addition, one can also choose to implement the FIFO storage units  22 ,  26  by using latch circuits instead, wherein the substitution of FIFO by latch-based circuits is considered well known in the pertinent art. Meanwhile, the single-port memory  24  can be embodied by a well-known SRAM. These are only examples of the FIFO storage units  22 ,  26  and the single-port memory  24 , and are not meant to be taken as limitations.  
         [0017]     The term “single-port memory” or “single-port storage unit” herein, as one of ordinary skill in the art would understand, refers to a storage device having only one port for input/output, which implies a input/output mutual exclusion characteristic, which means the input operation cannot happen when outputting, and vice versa. The term “dual-port memory” or “dual-port storage unit”, on the other hand, refers to a storage device having two ports for accessing, and therefore capable of simultaneous input/output operation. Because of the simultaneous input/output accessing characteristics, a dual-port memory is considered capable of being accessed “asynchronously”, and thus the term “asynchronous storage unit”.  
         [0018]     The data transfer interface device described in the embodiments of the present invention can be used in a variety of applications. For example, it can be used as buffer memory, such as a frame buffer, between display controller and display panel. Pertinent products may include LCD monitor controllers, LCD TV controllers, digital TV controllers, and the like. Please refer to  FIG. 2 , which schematically illustrates such a setup in the display or television field. As shown in  FIG. 2 , the data transfer interface device  10  is positioned between a display controller  11  and a display panel  12 .  
         [0019]     The single-port memory  24  is positioned between the two FIFO storage units  22 ,  26 . For the FIFO storage unit  22 , data (D in ) N  with a data width N is received according to a clock CLK 1  and data (D′ in ) N  with the same data width N is output according to a different clock CLK 2 . For the single-port memory  24 , data (D′ in ) N  output from the FIFO storage unit  22  is received according to the clock CLK 2 , and data (D′ out ) N  with the same data width N is output according to the clock CLK 2 . Finally, for the FIFO storage unit  26 , data (D′ out ) N  output from the single-port memory  24  is received according to the clock CLK 2  and data (D out ) N  with the same data width N is output according to a different clock CLK 3 . For this preferred embodiment, the clocks CLK 1 , CLK 2 , and CLK 3  have different frequencies. In other words, the data transfer interface device  10  according to the preferred embodiment operates under different clock domains defined by these clocks CLK 1 , CLK 2 , and CLK 3 .  
         [0020]     Please note that the FIFO storage units  22 ,  26  are able to read and write data simultaneously while the single-port memory  24  is only able to read data or write data but not both at the same time. Because of this, a guideline regarding the frequencies of the three clocks CLK 1 , CLK 2 , CLK 3  must be properly set so that the FIFO storage units  22 ,  26  and the single-port memory  24  can achieve a constant data flow rate and appear to act as one full-function dual-port storage unit. The guideline is dependent upon the characteristics of the FIFO storage units  22 ,  26  and the single-port memory  24 .  
         [0021]     Please continue referring to  FIG. 1 . In this preferred embodiment, in an attempt to adapting to a full-bandwidth application, the frequency F 2  of the clock CLK 2  is preferrably equal to or larger than the sum of the frequencies F 1 , F 3  of the corresponding clocks CLK 1  and CLK 3 . For example, assuming that the FIFO storage units  22 ,  26 , and the single-port memory  24  each operate with the same data width of 24 bits, the data receiving rate for the FIFO storage unit  22  is 24 bits×F 1 , the data outputting rate for the FIFO storage unit  22  is 24 bits×F 2 , the data receiving rate for the single-port memory  24  is 24 bits×F 2 , the data outputting rate for the single-port memory  24  is 24 bits×F 2 , the data receiving rate for the FIFO storage unit  26  is 24 bits×F 2 , and the data outputting rate for the FIFO storage unit  26  is 24 bits×F 3 . Please note that the frequency F 1  of the clock CLK 1  and the frequency F 3  of the clock CLK 3  are normally preset, for they are usually predominantly determined by the outputting frequency of the preceding circuitry, for example, an LCD controller circuitry, and the receiving frequency of the following component, for example, a display panel, respectively. Therefore, the frequency of the clock CLK 2  needs to be set, in view of the preset frequencies F 1  and F 3 , at such a level that the single-port memory  24  does not act as a bottleneck of the data flow, which is inherent to its single port nature.  
         [0022]     To address the issue in more detail, please refer to the following derivation in terms of internal and external data flow rates. Because of the read/write mutual exclusion nature of the single-port memory  24 , the data flow rate of the single-port memory  24 , i.e., the internal data flow rate of the data transfer interface device  10  can be viewed equivalent to half the sum of the data receiving rate and the data outputting rate, that is, 0.5×(24 bits×F 2 +24 bits×F 2 ). On the other hand, the external data flow rate of the data transfer interface device  10 , which is the sum of the receiving rate and the outputting rate thereof, can be denoted as 24 bits×F 1 +24 bits×F 3 . Accordingly, in order for the data transfer interface device  10  to operate as a full-function dual-port storage unit in a full-bandwidth fashion, the internal data flow rate is required to be equal to or larger than the external data flow rate, which renders the following condition: 
 
0.5×(24 bits× F   2 +24 bits× F   2 )≧24 bits× F   1 +24 bits× F   3  
 
 That is, 
 
 F   2   ≧F   1   +F   3  
 
         [0023]     And as a result, the aforementioned preferrable criterion is so derived. However, such a criterion serves merely as a preferred requirement in order for a full bandwidth application, and is not to be considered as a limitation of the present invention.  
         [0024]     Please further refer to  FIG. 3 , which shows a block diagram of a data transfer interface device  50  according to an alternate embodiment of the present invention. In  FIG. 3 , besides of the two FIFO storage units, herein denoted  62  and  64 , and the single-port memory, herein denoted  64 , as illustrated in  FIG. 1 , the data transfer interface device  50  also includes a data converter  60  at the input portion, which functions to convert M input data (D in ) N  with a data width N into input data (D in ) M×N  with a data width M×N, and a data converter  68  at the output portion, which functions to convert output data (D out ) M×N  with a data width M×N into M output data (D out ) N  with a data width N. It is a common practice in a variety of application fields, such as in LCD monitor controller field, LCD TV controller field, or digital TV controller field, to adopt such data converters when implementing data transfer buffering, and thus the configuration and operation of the data converters  60  and  68  are considered well known to those skilled in the art.  
         [0025]     The above-mentioned embodiments in  FIG. 1  and  FIG. 3  are designed suitable for all sorts of combination of input clock frequency CLK 1  and output clock frequency CLK 3 . When it is known, for example, from the setting of the preceding and following circuitries, that the input data rate, and therefore the input clock frequency CLK 1 , is higher than the output data rate, and therefore the output clock frequency CLK 3 , i.e., F 1 &gt;F 3 , then the inventive data transfer interface device may be optimized to omit one dual-port FIFO storage unit as shown in  FIG. 4 . Referring to  FIG. 4  in conjunction with  FIG. 1 , the FIFO storage unit  22  originally positioned in the front is removed and the clock driving the single-port memory  24  is switched to the input clock CLK 1 , while such optimized data transfer interface device  70  still functions as a full-function dual-port memory and benefits from even more reduced cost and space. Similarly, when it is known, for example, from the setting of the preceding and following circuitries, that the input data rate, and therefore the input clock frequency CLK 1 , is lower than the output data rate, and therefore the output clock frequency CLK 3 , i.e., F 1 &lt;F 3 , then the inventive data transfer interface device may be optimized to omit one dual-port FIFO storage unit as shown in  FIG. 5 . Referring to  FIG. 5  in conjunction with  FIG. 1 , the FIFO storage unit  26  originally positioned in the rear is removed and the clock driving the single-port memory  26  is switched to the output clock CLK 3 , while such optimized data transfer interface device  80  still functions as a full-function dual-port memory and benefits from even more reduced cost and space.  
         [0026]     As one can see, the data transfer interface devices  10 ,  50 ,  70 ,  80  in the embodiments shown in  FIG. 1 ,  FIG. 3 ,  FIG. 4 , and  FIG. 5  are considered much cheaper and take up much less space, resulting from the use of a much less complex single-port memory, while provide for the same functionality of a full-function dual-port storage unit.  
         [0027]     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 6