Patent Abstract:
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals from the redundant bond pad are biased to ground during normal operations of the integrated device. In order to test the relevant internal circuitry, a voltage is applied to a Test Mode Enable bond pad, overcoming the bias that grounds the redundant bond pad. In addition, the signal from the Test Mode Enable bond pad serves to ground any transmission from the main bond pad. As a result, the redundant bond pad may be used to test the relevant internal circuitry given its accessible location in relation to the testing equipment.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a divisional of application Ser. No. 10/869,976, filed Jun. 16, 2004 now U.S. Pat. No. 7,161,372, issued Jan. 9, 2006, which is a continuation of application Ser. No. 10/437,354, filed May 12, 2003, now U.S. Pat. No. 6,781,397, issued Aug. 24, 2004, which is a divisional of application Ser. No. 09/433,513, filed Nov. 3, 1999, now U.S. Pat. No. 6,600,359, issued Jul. 29, 2003; which is a continuation of application Ser. No. 09/164,195, filed on Sep. 30, 1998 now U.S. Pat. No. 6,107,111, issued Aug. 22, 2000; which is a divisional of application Ser. No. 08/760,153, filed Dec. 3, 1996, now U.S. Pat. No. 5,859,442, issued Jan. 12, 1999. 

   BACKGROUND OF THE INVENTION 
   Technical Field: The present invention relates generally to electronic devices and, more specifically, to a circuit for providing a redundant bond pad for probing semiconductor devices. 
   As seen in  FIG. 1 , one or more dies are formed in a conventional manner on a wafer which, in turn, is formed from a semiconductor material such as silicon. Each die has an integrated circuit or device that has been formed but not yet detached from the wafer. Further, each die on the wafer can be tested by placing a set of mechanical probes in physical contact with the die&#39;s bond pads. The bond pads provide a connection point for testing the integrated circuitry formed on the die. The probes apply voltages to the input bond pads and measure the resulting output electrical signals on the output bond pads. Not all bond pads on a die, however, are easily accessible by these devices. Given the arrangement of the dice in  FIG. 1 , for example, it is generally easier to probe the long side of each die, as the short side of each die is usually too close to the other dice to allow sufficient clearance for testing purposes. Thus, it can be difficult to test circuits that are coupled to an inaccessible bond pad. 
   Requiring bond pads to be located only in the areas accessible during testing may lead to inefficient and complex circuit layouts. One known solution, as shown in  FIG. 3 , is to attach another bond pad, one that can be reached by a testing device, to the same wire used by the original bond pad. This solution, however, tends to increase the input capacitance. Attempts at minimizing this capacitance will result in the use of more die space. 
   A second known solution is to multiplex (mux) two input buffers together, as illustrated in  FIG. 4 , once again allowing a testable bond pad to access circuitry. With this mux circuit, however, signals from the original bond pad take longer to reach the die&#39;s integrated circuitry. In addition, if input is designed to be received from multiple input buffers arranged in a parallel configuration, this muxing solution would require duplicating large portions of the input circuitry, once again taking up a great deal of die space. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention provides a circuit allowing an alternate access point to be used in testing the integrated circuitry, wherein the circuitry is usually accessed at another point that is difficult to reach with testing equipment. The resulting advantage of this implementation is that the circuit may be easily tested. As another advantage, the circuit may operate during testing at the same polarity input as used in normal operations of the die without an increase in capacitance. Moreover, the preferred embodiments of this invention may be used to test the circuit without appreciably slowing down the time to input signals. Further, the invention will not require the duplication of circuitry related to the input of data. For purposes of testing in one preferred implementation, the circuit also prevents the use of an input pad employed during normal operation. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       FIG. 1  is a top view of a semiconductor wafer with dice formed thereon, as is known in the art. 
       FIG. 2  is a top view of a die of  FIG. 1 . 
       FIG. 3  is a block diagram demonstrating a solution in the prior art for testing the circuitry on a die. 
       FIG. 4  is a block diagram demonstrating a second such solution in the prior art. 
       FIG. 5A  is a schematic diagram of one exemplary embodiment in accordance with the present invention. 
       FIG. 5B  is a top-down view of a transistor configured for protection against electrostatic discharge. 
       FIG. 5C  is a schematic diagram of the exemplary embodiment of  FIG. 5A  as used with a modified operations circuit. 
       FIG. 6A  is a schematic diagram of a second exemplary embodiment of the present invention. 
       FIG. 6B  is a more detailed schematic diagram of the exemplary embodiment in  FIG. 6A . 
       FIG. 7  is a schematic diagram of a third exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  illustrates the top view of a die  12  that is formed in a conventional manner on a wafer. For purposes of clarity, the wafer and additional dice  12  that may be formed on that wafer have been omitted from  FIG. 2 . The sides of die  12  contain input bond pads  15 , to which external lead wires can be bonded. The bond pads  15  connect to operations circuits  14 , such as row address or decoding circuits, within the die  12 . It is understood in the art that a die could contain a plurality of bond pads  15  and a plurality of operations circuits  14 . Duplication of these elements has been limited in  FIG. 2  for purposes of clarity. Some bond pads  15  are more easily accessible by testing devices than are others. One element affecting accessibility is the spacing between dice  12 . For purposes of distinguishing the accessibility of bond pads as illustrated in  FIG. 1 , areas where the bond pads are more easily accessible are depicted by reference numeral  16 . whereas areas where bond pads are relatively inaccessible are denoted reference numeral  18 . 
   Occasionally, a particular die  12  is configured so that, during a normal operations mode, an operations circuit  14  is connected to an input bond pad  20  that is in an inaccessible area  18  concerning testing devices. Given such inaccessibility, it can be difficult to apply signals to the operations circuit  14  during a test mode. This is particularly true during the probe of dies that are still part of a wafer. Through the current invention, however, a probe bond pad  22  in an accessible area  16  can be connected to the operations circuit  14  during the test mode, thereby allowing for easy testing. 
   An exemplary testing circuit  24 , described below in detail and illustrated in  FIG. 5A , is used to connect the probe bond Dad  22  to the operations circuit  14  during the test mode for that circuit. The operation of the testing circuit  24  is controlled by an enable signal. In the preferred embodiment, this signal is provided by the testing device through a Test Mode Enable bond pad  26 . Thus, during the test mode, the testing device transmits the enable signal by way of the Test Mode Enable bond pad  26 . In response, the testing circuit  24  couples the probe bond pad  22  to the operations circuit  14 , which is normally driven by signals applied to input bond pad  20 . 
     FIG. 5A  is a schematic diagram of one embodiment of the testing circuit  24 . The testing circuit  24  contains a first conducting path  28  from the input bond pad  20  to the operations circuit  14 . The first conducting path  28  is also coupled to the drain of first n-channel transistor Q 2 , which has a source coupled to ground. This first n-channel transistor Q 2  is also configured for electrostatic discharge (ESD) protection, as illustrated in  FIG. 5B . As with standard transistors of this type, the first n-channel transistor Q 2  is comprised of a first conductive strip  50 , which, in this case, leads to the first conducting path  28  and, ultimately, to input bond pad  20 . (See  FIG. 5A .) A second conductive strip  52  leads to V ss  around, and a gate  54  is interposed between the first and second conductive strips  50  and  52 . Further, an n+ active area  56  is located between the gate  54  and the first conductive strip  50 . The n+ active area  56  is preferably in a vertical arrangement with the first conductive strip  50  and communicates with first conductive strip  50  via a series of contacts  58 . Unlike standard transistors, the n+ active area  56  is sufficiently large enough to create a relatively high active area resistance, generally around 1KΩ, thereby preventing ESD damage. 
   Returning to  FIG. 5A , a second conducting path  32  connects the probe bond pad  22  with a NOR gate  34 . The second conducting path  32  is also coupled to the drain of a second n-channel transistor Q 4 . A third conducting path  38  couples the Test Mode Enable bond pad  26  with a first inverter  40 . Between the Test Mode Enable bond pad  26  and the first inverter  40 . however, the third conducting path  38  is also coupled with the gate  54  of the first n-channel transistor Q 2  as well as with a low-bleed current device, known to those skilled in the art as a long L device  42 . The first inverter  40  has an input coupled to the third conducting path  38  and an output coupled to the gate of the second n-channel transistor Q 4 . The NOR gate  34  has a first input  44 , which receives an enabling signal for the operations circuit  14 . The NOR gate  34  also has a second input coupled to the second conducting path  32 , and an output. Finally, the testing circuit  24  contains a second inverter  46 , which has an input coupled to the output of the NOR gate  34 . The output of the second inverter  46  is coupled with the operations circuit  14 . 
   During normal use of the operations circuit  14 , the Test Mode Enable bond pad  26  is not receiving an enabling signal from any testing device. Therefore, the long L device  42  serves to bleed to V ss  ground any remaining low current within the third conducting path  38 . The lack of current in the third conducting path  38  turns off the first n-channel transistor Q 2 . With the first n-channel transistor Q 2  off, the first conducting path  28  may freely transmit signals from the input bond pad  20  to the operations circuit  14 . In the schematic illustrated in  FIG. 5A , the signal transmitted by the input bond pad  20  is an external Row Address Strobe (XRAS*) signal. Further, operations circuit  14  is an input butter which accepts the industry standard input levels of the transmitted XRAS* signal and modifies them to internal V CC  power and V SS  ground levels. It is know that such a circuit may have different configurations. The operations circuit in  FIG. 5C  demonstrates an alternate configuration, wherein optional transistors have omitted, including those used for further tuning the XRAS* signal. 
   Returning to the third conducting path  38 , the lack of current in the path results in a logic 0 value transmitted to the first inverter  40 . It follows that the output of the first inverter  40  is at logic 1, which turns on the second n-channel transistor Q 4 . Once activated, the second n-channel transistor Q 4  bleeds current from the second conducting path  32 , thereby grounding any signals from probe bond pad  22 . 
   Because the second conducting path  32  is logic 0 during normal operations mode, the signal reaching the operation circuit  14  from the second inverter  46  will match the control logic signals received by the first input  44  of the NOR gate  34 . For example, given a logic 1 value received by the first input  44  and the logic 0 of the second output, the output of the NOR gate  34  will be a logic 0, which will be inverted by the second inverter  46  to logic 1. This logic 1 will serve as an input for the operation circuit  14 . If, on the other hand, the first input  44  receives a logic 0, the two logic 0 input for the NOR gate  34  result in a logic 1 input the which is inverted by the second inverter  46  to result in a logic 0 being input into the operations circuit  14 . 
   During a test mode of the operations circuit  14 , the Test Mode Enable bond pad  26  is driven with a sufficient voltage to overcome the bleeding effects of the long L device  42  and send a signal of logic 1 to the third conducting path  38 . This signal turns on the first n-channel transistor Q 2 , thereby grounding any input signal that would come from the input bond pad  20 . The logic 1 signal of the third conducting path  38  also goes through the first inverter  40 . The resulting logic 0 value turns off the second n-channel transistor Q 4  that had been grounding signals from the probe bond pad  22 . As a result, signals such as XRAS* that once issued from the input bond pad  20  may now be input using the more accessible probe bond pad  22 . The NOR gate  34  receives both a signal enabling the operations circuit  14  as well as transmissions from the probe bond pad  22 . The NOR gate  34  output is inverted by the second inverter  46 , and the result is entered into the operations circuit  14 . 
   In another embodiment illustrated in  FIGS. 6A and 6B , a second input buffer  48  may be used with the probe bond pad  22  in order to preserve a trip point equivalent to that of other input bond pads  15  (see  FIG. 2 ). In this embodiment, the second input buffer  48  has a configuration similar to that of the operations circuit  14  of  FIG. 5C . 
   In a third embodiment, shown in  FIG. 7 , the signals that passed through the NOR gate  34  and the second inverter  46  in earlier embodiments are instead coupled directly into the operations circuit  14  with the addition of one n-channel transistor Q 6  and one p-channel transistor Q 8 . This embodiment has the benefit of allowing multiple points of access for test signals, rather than requiring all of the test signals to be input at only one location. This is not the most preferred embodiment, however, as the additional transistors Q 6  and Q 8  require additional die space. 
   One of ordinary skill in the art can appreciate that, although specific embodiments of this invention have been described above for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For example, the testing circuit could be modified so that a single Test Mode Enable pad could enable a plurality of probe bond pads, while simultaneously grounding the corresponding input bond pads. It is also possible to configure the testing circuit to provide for probe bond pads for measuring the output of an operations circuit in the event the output bond pad is inaccessible. In addition, exemplary embodiments within the scope of the current invention are not limited to those involved with inaccessible or redundant bond pads. Rather, the current invention includes within its scope embodiments addressing components including, but not limited to, an access point; an input; a terminal; a pad in general, including one not limited to bonding; and a contact pad. Further, exemplary embodiments within the scope of the current invention are not limited to those involved with a long L device. Rather, the current invention includes within its scope embodiments addressing components and acts for electrically grounding, as well as others. Accordingly, the invention is not limited except as stated in the claims.

Technology Classification (CPC): 6