Patent Abstract:
An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to U.S. provisional patent application Ser. No. 61/286,338, filed Dec. 14, 2009, entitled “METHOD AND APPARATUS FOR CHARGE LEAKAGE COMPENSATION FOR CHARGE PUMP WITH LEAKY CAPACITIVE LOAD.” 
     
    
     FIELD OF TECHNOLOGY 
       [0002]    The present application generally relates to charge pumps and more particularly relates to compensation of charge leakage in charge pump circuitry for charge pumps having a leaky capacitive load. 
       BACKGROUND 
       [0003]    A phase lock loop (PLL) is an important apparatus that is used in numerous applications. A PLL receives a reference clock and generates accordingly an output clock that is phase locked with the reference clock. A phase lock loop typically comprises a controller and a controlled oscillator. The controlled oscillator outputs an output clock with a frequency controlled by a control signal generated by the controller. The output clock is usually divided down by a factor of N, where N is an integer, resulting in a divided-down clock. The controller issues the control signal based on detecting a phase difference between a reference clock and the divided-down clock. The frequency of the output clock is thus controlled in a closed-loop manner so as to minimize a phase difference between the reference clock and the divided-down clock. In a steady state, the output clock is thus phase locked with the reference clock. 
         [0004]    In a typical PLL, the controller comprises a phase detector and a filter. The phase detector receives the reference clock and the divided-down clock and outputs a detector output signal representing a phase difference between the reference clock and the divided-down clock. The filter receives and converts the detector output signal into the control signal to control the controlled oscillator. In a typical PLL, the phase detector comprises a PFD (phase/frequency detector) and a charge pump circuit, and the resultant detector output signal is a current-mode signal. The filter serves as a capacitive load for the charge pump circuit, and effectively filters and converts the current-mode detector output signal into a voltage-mode control signal to control the oscillator, which is a voltage-controlled oscillator (VCO). Modern phase lock loops are usually implemented in a CMOS (complementary metal-oxide semiconductor) integrated circuit. In a deep submicron CMOS integrated circuit, high-speed devices of short channel lengths are prone to charge leakage. In particular, the capacitive load is prone to charge leakage due to either using a leaky MOS transistor as capacitor or interfacing with leaky MOS transistors. The charge leakage at the capacitive load effectively introduces an error in the phase detection, which results in an error in the voltage-mode control signal and thus an error in the phase/frequency of the output clock. The error in the phase/frequency of the output clock is generally referred to as clock jitter. 
         [0005]    Accordingly, what is desired is a method to reduce the clock jitter due to charge leakage of the capacitive load of the charge pump. 
       SUMMARY OF THIS INVENTION 
       [0006]    An embodiment of the present invention is directed to an apparatus comprising: a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. 
         [0007]    Another embodiment of the invention is directed to a method for compensating charge leakage of a charge pump, the method comprising: receiving a phase signal representing a result of a phase detection; converting the phase signal into a current signal using the charge pump; transmitting the current signal into a capacitive load; detecting the current signal using a current sensor; injecting a compensation current into the capacitive load in accordance with a control voltage; and adapting the control voltage using a feedback network in accordance with an output of the current sensor. 
     
    
     
       DETAILED DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  shows a schematic diagram of a circuit in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The following detailed description refers to the accompanying drawings which show, by way of illustration, various embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense. 
         [0010]      FIG. 1  shows a schematic diagram of a circuit  100  in accordance with an embodiment of the invention. Circuit  100  comprises: a charge pump  110  for receiving a phase signal (comprising a first logical signal UP and a second logical signal DN) and outputting a current signal I OUT  at an internal node  105 ; a capacitive load  120  comprising a capacitor CL for receiving the current signal I OUT  and converting the current signal I OUT  into an output voltage VOUT at an output node  107 ; a current sensor  140  embodied by a resistor RS inserted between the internal node  105  and the output node  107  for sensing the current signal I OUT ; a compensation network  160  embodied by a PMOS transistor M 1  biased by a bias voltage VBP for injecting a compensation current I C  into the output node  107 ; and a feedback network  150  embodied by an operational amplifier  152  loaded with an integrating capacitor CI for generating the bias voltage VBP. Here, VDD denotes a first substantially fixed-potential node (usually at an output of a power supply), and VSS denotes a second substantially fixed-potential node (usually referred to as “ground”). 
         [0011]    For illustration purpose,  FIG. 1  further includes an equivalent circuit  130  (e.g., a fictitious shunt) comprising a load resistor RL at the output node  107  serving as an illustrative equivalent circuit to model the phenomenon of the charge leakage of the capacitive load  120 . Note that in a real circuit embodiment, it is futile (and even detrimental) to purposely insert a real shunt circuit like equivalent circuit  130  at the output node  107 . Certain principles of this invention are explained below. 
         [0012]    In a typical application to a phase lock loop, circuit  100  receives the phase signal (comprising the two logical signals UP and DN) as a timing detection result from a preceding phase detector (not shown in the FIGURE), and outputs the output voltage VOUT for controlling a succeeding voltage controlled oscillator (not shown in the FIGURE). A timing of an output clock of the voltage controlled oscillator is detected by comparing it with a reference timing (usually provided by a crystal oscillator) by the preceding phase detector. When a frequency of an output clock of the voltage controlled oscillator is too high, a timing of the output clock is often too early; this causes the second logical signal DN to be asserted more frequently, resulting in a decrease in the output voltage VOUT to decrease the frequency of the output clock. When the frequency of the output clock of the voltage controlled oscillator is too low, the timing of the output clock is often too late; this causes the first logical signal UP to be asserted more frequently, resulting in an increase in the output voltage VOUT to increase the frequency of the output clock. In this closed-loop manner, the output voltage VOUT is adjusted and settled into a value such that the frequency of the output clock is neither too high nor too low but just right. In the steady state, the output voltage VOUT must be settled, and therefore the following condition must be met: 
         [0000]                  I   OUT   +I   C   −I   L           =0  (1)
 
         [0013]    Here,                     denotes a statistical mean. Equation (1) provides that the mean net current following into the output node  107  must be zero, otherwise the output voltage VOUT cannot be settled. If the mean value of I OUT  is positive, the current sensor  140  senses a positive current more frequently, causing the feedback network  150  to gradually lower the bias voltage VBP, leading to an increase to the compensation current I C  and accordingly the output voltage VOUT; this leads to an increase to the frequency of the output clock and accordingly an earlier timing that results in the second logical signal DN being asserted more frequently and thus a reduction of the mean value of I OUT . If the mean value of I OUT  is negative, the current sensor  140  senses a negative current more frequently, causing the feedback network  150  to gradually elevate the bias voltage VBP, leading to a gradual decrease to the compensation current I C  and accordingly the output voltage VOUT; this leads to a decrease to the frequency of the output clock and accordingly a later timing that results in the first logical signal UP being asserted more frequently and thus an increase of the mean value of I OUT  (but a decrease in an absolute value of the mean value of I OUT  since it is negative). In either case, the phase lock loop reacts so as to reduce the absolute value of the mean value of I OUT . In the steady state, the mean value of I OUT  must be zero, otherwise the bias voltage VBP will either keep increasing or keep decreasing. By applying          I OUT           =0 to equation (1), one has 
         [0000]        I   C   −I   L =0  (2)
 
         [0014]    That is, the leakage current I L  is exactly compensated by the compensation current l C . In this manner, the detrimental effect of the leakage current is effectively alleviated. 
         [0015]    However, in practical design one must choose a sufficiently large capacitance value for the integrating capacitor CI, so that the bias voltage VBP is adjusted much slower than the phase lock loop adjusts the output voltage VOUT (otherwise the phase lock loop may encounter instability). 
         [0016]    Charge pump  110  comprises a current source I 1 , a current sink  12 , a first switch S 1 , and a second switch S 2 . When the first logical signal UP is asserted, the current source  11  injects current into the internal node  105 . When the second logical signal DN is asserted, the current sink  12  drains current from the internal node  105 . 
         [0017]    In an alternative embodiment (not shown in  FIG. 1 ), the capacitive load  120  comprises a serial connection of a resistor and a capacitor. 
         [0018]    In embodiment  100 , it is assumed that the capacitive load  120 , as a stand-alone circuit, is leaking toward VSS, and therefore the equivalent circuit  130  comprises a resistor shunt between the output of the capacitive load and VSS and consequently the compensation network  160  must inject current into the output of the capacitive load to compensate for the charge leakage. Depending on the actual embodiment of the capacitive load  120 , however, it is possible that the capacitive load  120 , as a stand-alone circuit, is leaking toward VDD. In this case, the equivalent circuit  130  must be a resistor shunt between the output of the capacitive load  120  and VDD and consequently the compensation network  160  must drain current from the output of the capacitive load  120 ; this can be fulfilled by changing the PMOS transistor M 1  into a NMOS transistor. Those of ordinary skills in the art would appreciate other implementation details not particularly described herein. 
         [0019]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations and variations of the embodiments discussed herein. Various embodiments use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description.

Technology Classification (CPC): 7