Patent Abstract:
Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1). Field of the Invention  
           [0002]    This invention relates generally to an electronic assembly, typically of the kind having a package substrate secured to a printed circuit board utilizing solder bumps.  
           [0003]    2). Discussion of Related Art  
           [0004]    Integrated circuits are often manufactured in and on semiconductor wafers which are subsequently cut into individual semiconductor chips. A chip is then mounted to a package substrate and electrically connected thereto. The package substrate is then mounted to a printed circuit board.  
           [0005]    Solder balls are usually located on the surface of the package substrate which is located against the printed circuit board. The combination is then heated and allowed to cool so that the solder balls form solder bumps which secure the package substrate structurally to the printed circuit board, in addition to electrically connecting the package substrate to the printed circuit board.  
           [0006]    Electronic signals can be provided through the solder bumps between the printed circuit board and the integrated circuit. Other ones of the solder bumps provide power and ground to the integrated circuit. It may occur that high currents flow through some of the solder bumps, in particular those providing power or ground to the integrated circuit. These high currents may cause damage to the solder bumps. The solder bumps providing power, ground and signal communication are also usually equally spaced from one another thus taking up similar amounts of space.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    The invention is described by way of examples with reference to the accompanying drawings wherein:  
         [0008]    [0008]FIG. 1 is a cross-sectional side view illustrating components of an electronic assembly according to an embodiment of the invention;  
         [0009]    [0009]FIG. 2 is a view similar to FIG. 1 after the components are brought together, heated and allowed to cool;  
         [0010]    [0010]FIG. 3 is a plan view illustrating the layout of solder bumps and vias of a printed circuit board of the electronic assembly;  
         [0011]    [0011]FIG. 4 is a side view illustrating more components of the electronic assembly; and  
         [0012]    [0012]FIG. 5 is a plan view of a printed circuit board according to another embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    [0013]FIG. 1 of the accompanying drawings illustrates components of an electronic assembly  10  before being secured to one another. The electronic assembly  10  includes a package substrate subassembly  12  and a printed circuit board subassembly  14 .  
         [0014]    The printed circuit board subassembly  14  includes a printed circuit board  16 , vias  18 , and contact pads  20 .  
         [0015]    The printed circuit board  16  includes a number of layers including a power plane  22 , a ground plane  24 , and other layers  26 . The power plane  22  is separated from a ground plane  24  by one of the layers  26 . Another one of the layers  26  is located on top of the power plane  22  and a further one of the layers  26  is located on a lower surface of the ground plane  24 . The power and ground planes  20  and  24  are thus separated from one another by one of the layers  26  and spaced from upper and lower surfaces of the printed circuit board  16  by other ones of the layers  26 .  
         [0016]    The vias  18  are located in the printed circuit board  16  and extend from the upper surface thereof to the lower surface thereof through the layers  22 ,  24 , and  26 . The vias  18  include power vias  18 A, ground vias  18 B and signal vias  18 C. The power vias  18 A have lower ends connected to the power plane  22 . The ground vias  18 B have lower ends connected to the ground plane  24 . The signal vias  18 C are disconnected from the power and ground planes  22  and  24 .  
         [0017]    The contact pads  20  include a power contact pad  20 A, a ground contact pad  20 B and signal contact pads  20 C. The power contact pad  20 A has a height measured in a direction from the bottom of the paper to the top of the paper, a width as measured into the paper, and a length as measured from the left to the right of the paper. The length is a multiple of the width. The power contact pad  20 A is located on all the power vias  18 A. Each one of the power vias  18 A is attached and connected to the power contact pad  20 A at a respective location along the length of the power contact pad  20 A. As such, the power vias  18 A connect the power contact pad  20 A in parallel to the power plane  22 . In another embodiment the vias may be located outside the contact pads in an arrangement commonly referred to as a “dogbone” configuration.  
         [0018]    The ground contact pad  20 B, similarly, has a height, a width, and a length which is a multiple of the width. The ground contact pad  20 B is located on all the ground vias  18 B so that each ground via  18 B has a respective upper end connected to the ground contact pad  20 B at a respective location along its length.  
         [0019]    Each signal contact pad  20 C is located on and connected to a respective one of the signal vias  16 C. Each signal contact pad  20 C is disconnected from every other contact pad  20 .  
         [0020]    The package substrate subassembly  12  includes a package substrate  30 , vias  32 , bond pads  34 , and solder balls  36 . The package substrate  30  is also a multi-layer substrate having a ground plane and a power plane. The vias include power vias  32 A, ground vias  32 B, and signal vias  32 C. Each one of the power vias  32 A has an upper end connected to a ground plane in the package substrate  30  and each one of the ground vias  32 B has an upper end connected to a ground plane in the package substrate  30 .  
         [0021]    The bond pads  34  include the power bond pads  34 A, ground bond pads  34 B, and signal bond pads  34 C, all located on a lower surface of the package substrate  30 . Each power bond pad  34 A is located on a respective lower end of a respective one of the power vias  32 A, each ground bond pad  34 B is located on a respective lower end of a respective ground via  32 B, and each signal bond pad  34 C is located on a respective lower end of a respective signal via  32 C.  
         [0022]    The solder balls  36  include power solder balls  36 A, ground solder balls  36 B, and signal solder balls  36 C. Each power solder ball  36 A is located on a respective lower surface of a respective one of the power bond pads  34 A, each ground solder ball  36 B is located on a respective lower surface of a respective ground bond pad  34 B, and each signal solder ball  36 C is located on a respective lower surface of respective signal bond pads  34 C.  
         [0023]    Each respective power via  32 A is aligned with one power bond pad  34 A, one power solder ball  36 A, and one power via  18 A. Center points of the power solder balls  36 A are spaced from one another by about 1 mm. A center point of the power solder ball  36 A on the right is spaced from a center point of the ground solder ball  36 B on the left by about 1.2 mm. Center points of the ground solder balls  36 B are spaced from one another by about 1 mm. A center point of the ground solder ball  36 B on the right is spaced from a center point of the signal solder ball  36 C on the left by about 1.2 mm. Center points of the signal solder balls  36 C are spaced from one another by about 1.2 mm. All the solder balls  36 A, B, and C have equal mass and size. Therefore, the combined mass of the power solder balls  36 A divided by the number of power vias  18 A equals the combined mass of the ground solder balls  36 B divided by the number of ground vias  18 B, and equals the combined mass of the signal solder balls  36 C divided by the number of signal vias  18 C.  
         [0024]    The package substrate subassembly  12  is lowered onto the printed circuit board subassembly  14  so that lower surfaces of the solder balls  36  contact upper surfaces of the contact pads  18 A. All the power solder balls  36 A contact the power contact pad  20 A, all the ground solder balls  36 B contact the ground contact pad  20 B, and each signal solder ball  36 C contacts a respective one of the signal contact pads  20 C.  
         [0025]    The combination of the package substrate assembly  12  and the printed circuit board subassembly  14  is then located in a reflow furnace. The solder balls  36  are heated to above their melting temperature so that they melt. The power solder balls  36 A combine when they melt due to their relative close spacing and the ground solder balls  36 B combine when they melt due to their relative close spacing. The power solder balls  36 A however do not combine with the ground solder balls  36 B. The signal solder balls  36 C remain disconnected from one another from the ground solder balls  36 B and from the power solder balls  36 A.  
         [0026]    The combination of the package substrate subassembly  12  and the printed circuit board subassembly  14  is then removed from the reflow furnace and allowed to cool so that the material of the melted solder balls again solidifies. The solidified material of the power solder balls  36 A is represented in FIG. 2 of power solder bumps  40 B, the combination of the ground solder balls  36 B is represented as a ground solder bump  40 B, and the melted and reflowed signal solder balls  36 C is represented by signal solder bumps  40 C.  
         [0027]    Each one of the power solder bumps  40 A has a height, a width, and a length with the width and length of the power solder bump  40 A correspond to the width and the length of the power contact pad  20 A. Similarly, the ground solder bump  40 B has a height, a width, and a length, the width and length corresponding to the width and length of the ground contact pad  20 B. As such, the power solder bump  40 B has a length which is a multiple of its width and the ground solder bump  40 B has a length which is a multiple of its width.  
         [0028]    Upper ends of the power vias  18 A are connected through the power contact pads  20 A to respective points of the power solder bump  40 A along its length and upper ends of the ground vias  18 B are connected to the ground contact pad  20 B to the ground solder bump  40 B at respective locations along its length. The power solder bump  40 A is thus connected in parallel through the power vias  18 A to the power plane  22  and the ground solder bump is connected in parallel through the ground vias  18 B to the ground plane  24 .  
         [0029]    An advantage of combining the power solder balls  36 A and combining the ground solder balls  36 B is that they can be located closer to one another. More space is so freed up for additional ones of the signal solder balls  36 C. Another advantage of combining the power solder balls  36 A and combining the ground solder balls  36 B is that potential high currents through individual ones of the balls  36 A or B can be distributed through the larger solder bumps  40 A or  40 B.  
         [0030]    [0030]FIG. 3 is a more accurate representation of the relative positioning of the power and ground solder bumps  40 A and  40 B. The power and solder bumps  40 A and  40 B are represented by rectangles. The signal solder bumps  40 C are represented by larger circles. The power ground and signal vias  18 A,  18 B, and  18 C are represented by the smaller circles.  
         [0031]    It can be seen that the power and ground solder bumps  40 A and  40 B are located in lines parallel to one another, directly adjacent one another with a respective ground solder bump  40 B located between two of the power solder bumps  40 A. A surface of one of the power solder bumps  40 A thus faces a respective surface of one of the ground solder bumps  40 B to form a plurality of capacitors. In the example illustrated, there are three power solder bumps  40 A and three ground solder bumps  40 D and five capacitors are created. The capacitors assist in reducing resistive and inductive time delay of power or ground signals. All the power and ground vias  18 A and  18 B are located over a rectangular area where there are none of the signal vias  18 C and all the signal vias are located around the rectangular area where all the power and ground vias  18 A and  18 B are located.  
         [0032]    [0032]FIG. 4 illustrates more components of the electronic assembly. In addition to the package substrate  30  and the printed circuit board  16 , the electronic assembly  10  further includes a semiconductor chip  50 . The semiconductor chip  50  has an integrated circuit of electronic components therein The semiconductor chip  50  is mounted on the package substrate  30  and electrically connected thereto. Electronic signals can be provided to and from the integrated circuit in the semiconductor die  50  and the printed circuit board  16  through the solder bumps  40  and the package substrate  30 .  
         [0033]    [0033]FIG. 5 illustrates another manner in which capacitors can be created with power and ground solder bumps. Similar reference numerals are used as in the embodiment of FIG. 3. A power solder bump  140  has a plurality of limbs  140 A-E. The limbs  140 A-D all lead off the limb  140 E. A ground bump  150  is provided having limbs  150 A-E. The limbs  150 A-D lead off the limb  150 E. The limbs  150 A-D are located between the limbs  140 A-D so that the limbs  140  are alternated by the limbs  150 A-D. It has been found that a larger capacitor can be created over a given surface area by “fanning” the limbs into one another as illustrated in FIG. 5.  
         [0034]    While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.

Technology Classification (CPC): 8