Patent Abstract:
The system and method of the present invention for reducing the clock skew sensitivity of a shift register provides a control circuit for generating a clock signal to the first cell of the shift register. The first cell of the shift register receives the clock signal at its input and delays the clock signal for a specified time before transmitting the clock signal to the last cell in the shift register. The clock signal is propagated from the first cell of the shift register to the last cell of the shift register in a first direction. A test data circuit line is coupled to the last cell of the shift register. A test data signal is transmitted by the test data circuit line to the last cell of the shift register and is propagated through the shift register in a second direction, wherein the second direction is in a direction opposite from the direction of the clock signal. Thus, the clock signal is propagated through the cells in the shift register against the flow of the test data signal through the shift register.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates generally to a clocking scheme for digital circuits, and more particularly, to a clocking scheme for reducing the clock skew sensitivity of a shift register. 
     BACKGROUND OF THE INVENTION 
     Shift registers are well known in the construction of digital circuits. A basic shift register structure comprises a series of flip flops having a common clock input where the output of one flip flop is coupled to the input of the next flip flop. Each flip flop in the shift register has setup time and hold time requirements which define a forbidden zone of the active clock edge, i.e. clock skew, to ensure the correct function of the shift register. In order for a shift register to function properly, the clock skew between a transmitting and a receiving flip flop in a shift register must be less than the intrinsic delay of the transmitting flip flop minus the hold time of the receiving flip flop. 
     One particular use of such shift registers is for boundary-scan testing, otherwise known as Joint Test Action Group (JTAG). Boundary-scan testing is a non-intrusive method for testing interconnects on printed circuit boards that is implemented at the integrated circuit level. Since its adoption by IEEE as Standard 1149.1, boundary-scan testing has been applied in high volume to high-end consumer products, telecommunication products, defense systems, peripherals, computers and avionics. Current JTAG implementations utilize boundary scan cells coupled to each other so that the cells function as a shift register, and thus are very sensitive to clock skew. A Test Access Port (TAP) controller generates all required control signals for the boundary scan cells including the clock signal. The conventional JTAG clocking scheme routes the JTAG clock as one signal net. However, boundary scan cells need to be placed close to the input or output cell to which it belongs and are therefore distributed along the sides of the die. This distribution causes long net delays which can result in a high skew on a clock net. 
     As the intrinsic delay in fast sub-micron technologies becomes smaller, it becomes more difficult to achieve the requirements for clock skew. As a result, the use of shift registers in digital circuits, such as for boundary-scan testing, becomes more difficult to implement and increases the effort required during layout resulting in many additional days to complete the layout. Moreover, in some cases it is impossible to achieve the minimum skew required for a secure shift operation of the shift registers. One typical example is a design with several hardmacros (i.e. logic functions with fixed layout, for example Random Access Memories (RAMs)). Ideally, hardmacros should be placed close to the Input/Output (I/O) region of the die in order to easily connect the power rings of the hardmacros to the power rings in the I/O area. This arrangement, however, interferes with the requirement that the boundary scan cells be placed close to the I/O region. For critical outputs (i.e. signals where the delay needs to be as small as possible) the boundary scan cell needs to be placed right next to the output buffer between the I/O area and the hardmacro. This configuration causes big skew on the clock skew since the layout tools can only control the clock skew effectively if there is no blocking area between the clock trunk (placed in the middle of the die) and the flip flop. Because the wire is too long, the skew needs to be balanced manually by slowing down the delay of the other flip flops using balance cells. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a system and method for a clocking scheme is implemented to reduce the clock skew sensitivity of a shift register. The system of the present invention advantageously transmits a clock signal through the cells in a shift register in a direction which is against the direction of the data flow of the shift registers. To ensure that the hold time of each cell of the shift register is adequate, a delay circuit is provided in each cell of the shift register to delay the clock signal before transmitting it to the next cell of the shift register. The clocking scheme of the present invention advantageously reduces the sensitivity of the shift register to clock skew and is easy and fast to implement in layout. 
     The system of the present invention comprises a control circuit, and a first cell and a last cell of the shift register. The control circuit generates a clock signal to the first cell of the shift register. The first cell of the shift register contains a delay circuit for delaying the clock signal before transmitting the clock signal to the next cell of the shift register. The clock signal is continuously delayed by each cell of the shift register as it is transmitted from the first cell to the last cell of the shift register and through the cells of the shift register. The shift register may contain any number of cells, where each cell contains a delay circuit for delaying the clock signal before transmitting it to the next cell in the register. At the same time that the clock signal is transmitted to the first cell of the shift register, a test data circuit line transmits data to the last cell in the shift register. The data is received by the last cell of the shift register and is transmitted through the cells of the shift register in a direction which is against the direction of the clock signal. The present invention also includes a method for reducing the clock skew sensitivity of a shift register. The method includes the steps of generating and transmitting a clocked signal to the first cell of a shift register in a first direction; receiving at the first cell the generated clock signal, delaying the clock signal in the first cell by means of a delay circuit, and transmitting the clock signal to the next cell of the shift register. The method also requires transmitting data to the last cell of a shift register in a second direction which is in the opposite direction of the first direction. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a shift register clocking system embodying the principles of the present invention. 
     FIG. 2 is a timing diagram of a clock signal and the data flow of a shift register clocking system in accordance with the present invention. 
     FIG. 3 is a block diagram of one embodiment of a shift register cell in accordance with the present invention. 
     FIGS. 4A-4C are block diagrams of other embodiments of boundary scan cells in accordance with the present invention. 
     FIG. 5 is a table summarizing the details of one embodiment implementing the present invention. 
     FIG. 6 is a table summarizing the results of using three different types of buffers in a boundary scan cell implementation embodying the principles of the present invention. 
     FIG. 7 is a block diagram of one embodiment of a clocking system for a plurality of shift registers in accordance with the present invention. 
     FIG. 8 is a timing diagram of a clock signal and the data flow of a plurality of shift registers in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a block diagram of a shift register clocking system  100  in accordance with the present invention. System  100  comprises a plurality of cells  102 , a control circuit  104 , a test data circuit input line  108 , and a non-inverting buffer  110 . A clock signal input line  112 , a clock signal output line  114 , a test data input line  116 , and a test data output line  118  are coupled to each cell  102 . Cells  102  may also include other input and output lines coupled to cell  102  which are not shown here for simplification purposes but would be evident to one skilled in the art when coupling individual cells as a shift register. Cells  102  are flip flops having an internal delay circuit for delaying the input clock signal from clock signal input line  112 . The operation and configuration of cell  102  is described below in more detail with reference to FIG.  3 . Cells  102  are coupled to one another as shown in FIG. 1 to form a shift register, and in a preferred embodiment of the present invention are boundary scan cells for a JTAG implementation. More specifically, system  100  comprises a first cell  102 A and a last cell  102 B. System  100  may also contain any number of intermediary cells  102  coupled to one another and to first cell  102 A and last cell  102 B to form a shift register as shown in FIG.  1 . Cells  102 A,  102 B, and intermediary cells  102  are coupled to each other such that the clock signal output line  114  of one cell  102  is coupled to the clock signal input line  112  of the next cell  102 , and the test data input line  116  of one cell  102  is coupled to the test data output line  118  of the next cell  102 . 
     Control circuit  104  is coupled through a clock signal generator line  120  to the clock signal input line  112  of the first cell  102 A. The control circuit  104  is also coupled through the test data output line  118  to the first cell  102 A. Control circuit  104  may be any type of conventional control circuit which generates control signals, including a clock signal, to first cell  102 A of the shift register. In a preferred embodiment of the present invention, control circuit  104  is a Test Access Port (TAP) controller for generating control signals for the boundary scan cells in a JTAG implementation. Because control circuit  104  only clocks first cell  102 A, the driving strength of the driving buffer can be reduced from a dedicated clock buffer to a normal non-inverting buffer. One advantage of this configuration is its flexibility and easy implementation. A dedicated clock buffer consists of large transistors which are only available in the I/O ring of the die thus requiring long routing to connect control circuit  104  to the buffer and to drive all  102  cells using big clock trunks. As a result, conventional systems require additional layout steps for implementation and results in wasted silicon area are on the die. Systems embodying the principles of the present invention, however, enable a shortened connection between control circuit  104  and first cell  102 A which can be routed automatically in layout. 
     In a preferred embodiment, the present invention is a JTAG implementation. In such an embodiment, test data input line  116  is coupled to the test data circuit input (TDI) pin of the JTAG. Test data circuit input line (TDI)  108  is coupled to a buffer  110  which in turn is coupled to test data input line  116  of last cell  102 B in the shift register. In a preferred embodiment, TDI  108  is the data input of the JTAG implementation for all values that need to be loaded either in the boundary scan cells or TAP controllers. Buffer  110 , which is a conventional buffer and preferably, a non-inverting buffer, is usually used to supply the required driving strength since the routing from TDI  108  to last cell  102 B may be quite long. 
     During operation of system  100 , the clock signal generated by control circuit  104  flows in a direction opposite to the direction of the data flow transmitted by TDI  108 . Control circuit  104  transmits a clock signal along clock signal generator line  120  to first cell  102 A. First cell  102 A receives the clock signal at clock signal input line  112 . First cell  102 A delays the clock signal for a specified amount of time and then transmits the clock signal along the clock signal output line  114  to last cell  102 B. If system  100  comprises a plurality of intermediary cells  102  coupled to  102 A and  102 B, then first cell  102 A delays the clock signal for a specified amount of time and then transmits the clock signal along clock signal output line  114  to the next intermediary cell  102  in the shift register. The signal is then propagated through intermediary cells  102  of the shift register until the clock signal reaches last cell  102 B in the shift register. At the same time that control circuit  104  transmits a clock signal along clock signal generator line  120  to first cell  102 A, TDI  108  transmits a test data signal along test data input line  116  to last cell  102 B of the shift register. Last cell  102 B of the shift register then transmits the test data signal along the test data output line  118  to first cell  102 A. If system  100  comprises a plurality of intermediary cells  102  coupled to  102 A and  102 B, then last cell  102 B transmits the test data signal along the test data output line  118  to the next intermediary cell  102  in the shift register. Next intermediary cell  102  receives the test signal data at test data input line  116  and transmits the test signal data along the test data output line  118  to the next intermediary cell  102 . The signal is then propagated through intermediary cells  102  of the shift register until the test data signal reaches first cell  102 A in the shift register. From first cell  102 A of the shift register, the test signal data is transmitted along test data output line  118  to control circuit  104 . FIG. 2 shows a timing diagram of the clock signal and test data signal for system  100  in accordance with the present invention. 
     FIG. 3 shows a block diagram of one embodiment of a cell  102  in accordance with the present invention. Cell  102  is preferably a boundary scan cell and comprises a flip flop  310  coupled through the clock signal input line  112  to a delay circuit  320 . The clock signal output line  114  is also coupled to the delay circuit  320 . Delay circuit  320  is directly inserted in each cell  102 . Cell  102  may include other input and output lines which are not shown but which would be obvious to one skilled in the art. In a preferred embodiment of the present invention, delay circuit  320  is a non-inverting buffer. The present invention ensures that the shift operation operates correctly as long as the intrinsic delay of delay circuit  320  for the clock signal is longer than the intrinsic delay of the flip flop  310  of the previous cell itself. FIGS. 4A-4C are other examples of cells  102  embodying the principles of the present invention. The cells  102  in FIGS. 4A-4C are conventional boundary scan cells with a delay circuit  320  inserted directly into each boundary scan cell. Each cell  102  also includes a clock signal input line  112 , a clock signal output line  114 , a test data input line  116 , and a test data output line  118 . Cells  102  in FIGS. 4A-4C also include other input and output lines coupled to cells  102  and/or within cells  102  which are not shown here for simplification purposes but would be evident to one skilled in the art. 
     In a preferred embodiment, the present invention is implemented in an existing design using LCB500K technology which already contains JTAG inserted by JTAG builder. Cells  102  are boundary scan cells and are preferably the boundary scan cells as illustrated in FIG.  4 A. Referring now to FIG. 5, a table summarizing the details of a preferred embodiment is shown. In such an embodiment, the die size is approximately 11.9 mm by 11.9 mm with 180 boundary scan cells, 50 inputs, 58 outputs and 52 bidirects. The embodiment represents an average size of a state-of-the-art design. In this particular embodiment, the number of boundary scan cells is smaller than the total number of inputs/outputs because not all inputs and output were included into JTAG. Referring now to FIG. 6, a table summarizing the performance of the preferred embodiment using three different buffers  320  to delay the clock signal. Version  1  uses a lclkbuf 1  buffer, version  2  uses a lclkbuf 3   a  buffer, and version  3  uses two serial inverters n 1   b.  The second column of FIG. 6 shows the delay on the JTAG clock measured from the first boundary scan cell clocked directly by the TAP controller to the last boundary scan cell at the end of the clock chain. The values inside brackets are based on pre-layout c-MDE delay calculation, and the values without brackets are based on actual layout information. The third column of FIG. 6 gives an approximate frequency for which the JTAG will still run. For this estimation, a 50% duty cycle of the external clock is assumed. The maximum frequency is determined by the delay of the JTAG clock along the clock chain and the control signals of the TAP controller derived from the negative clock edge of the external clock. For calculating the frequencies shown in FIG. 6, the path of the shift signal to the last boundary scan cell with the longest clock delay was taken. As seen in FIG. 6, the best results can be achieved by using lclkbuf 3   a  as the delay buffer for delay circuit  320  in cell  102 . 
     FIG. 7 shows another embodiment of a system  400  in accordance with the present invention. System  400  comprises a control circuit  402 , a first shift register  404 A, a last shift register  404 B, and a plurality of data lockup latches  406 . System  400  may also contain any number of intermediary shift registers  404  coupled to one another in between first shift register  404 A and last shift register  404 B to form a chain of shift registers as shown in FIG.  7 . Each shift register ( 404 A,  404 B, and  404 ) may comprise any number of cells  102  (not shown) coupled to each other as a shift register and includes at least a first cell  408  and a last cell  410 . Control circuit  402  may be any type of conventional control circuit which generates control signals to first shift register  404 A, last shift register  404 B including a clock signal, and any intermediary shift register  404  in system  400 . In a preferred embodiment of the present invention, control circuit  402  is a Test Access Port (TAP) controller for generating control signals for the boundary scan cells in a JTAG implementation. Data lockup latches  406  are conventional data lockup latches and are generally used to ensure correct capturing of data of the shift register if the clock of the receiving flip flop of the shift register is slower than the clock of the sending flip flop of the shift register. A data lockup latch in front of the data input of the receiving flip flop of the shift register ensure correct functionality by allowing data to pass only during a low clock signal. A test data circuit input line (TDI)  412  is coupled to the last cell  410  in the first shift register  404 A. A clock signal generator line  416  is coupled to each shift register  404 . More specifically, control circuit  402  is coupled through the clock signal generator line  416  to the first cell  408  of each shift register  404  and to each data lockup latch  406 . The data lockup latches  406  are coupled through the test data output lines  418  to the first cells  408  of each shift register  404  except for the first cell  408  of the last shift register  404 B. The data lockup latches  406  are also coupled through the test data input lines  420  to the last cells  410  of each shift register  404  except for the last cell  410  of the first shift register  404 A. 
     During operation, control circuit  402  generates and transmits a clock signal along the clock signal generator line  416  to the first cell  408  of each shift register  404 ,  404 A and  404 B. The clock signal is propagated through the cells  102  of the shift register from the first cell  408  to the last cell  410  of the shift register. At the same time that control circuit  402  generates and transmits a clock signal to the first cell  408  of each shift register  404 ,  404 A, and  404 B, TDI line  412  transmits a test data signal from a test circuit to the last cell  410  of the first shift register  404 A. The test data signal is propagated through the cells  102  of the first shift register  404 A and is transmitted from the first cell  408  along the test data output line  418  to the data lockup latch  406 . The test data signal is then transmitted from the data lockup latch  406  to the last cell  410  of the last shift register  404 B via test data input line  420 . If system  400  comprises a plurality of intermediary shift registers  404  coupled in between  404 A and  404 B as shown in FIG. 7, then the data lockup latch  406  transmits the test data signal received from the first cell  408  of first shift register  404 A to the last cell  410  of the next intermediary shift register  404  via test data input line  420 . The signal is then propagated through cells  102  of intermediary shift register  404  until the test data signal reaches first cell  408  of the intermediary shift register  404 . The test data signal is propagated through the shift registers  404  and data lockup latches  406  until the test data signal reaches the first cell  408  of last shift register  404 B. The test data signal is then transmitted from first cell  408  of last shift register  404 B to control circuit  402  via test data output line  418 . FIG. 8 shows a timing diagram of the test data signal and the clock signal of system  400  in accordance with the present invention. 
     It is to be understood that the specific mechanisms and techniques which have been described are merely illustrative of certain applications of the principles of the invention. Numerous modifications may be made to the system and methods described without departing from the true spirit and scope of the invention.

Technology Classification (CPC): 6