Patent Abstract:
A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of transistors and method of forming transistors; more specifically, it relates to transistors having stressed channel regions and method of fabricating transistors having stressed channel regions. 
     BACKGROUND OF THE INVENTION 
     In microelectronic technology there is an ongoing search for transistors with increased performance. While many methods exist for increasing transistor performance, new and improved transistor structures with even more performance and methods of fabricating transistor structures with even more performance than currently available are continually sought after. Accordingly, there continues to be an unsatisfied need for transistors with increased performance. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention is a method, comprising: (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack. 
     A second aspect of the present invention is a structure, comprising: a gate stack on a silicon layer of a substrate; two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1A through 1F  are cross-sectional drawings illustrating fabrication of a stressed transistor according to a first embodiment of the present invention; 
         FIGS. 2A through 2C  are cross-sectional drawings illustrating fabrication of a stressed transistor according to a second embodiment of the present invention; 
         FIGS. 3A through 3F  are cross-sectional drawings illustrating fabrication of a stressed transistor according to a third embodiment of the present invention; and 
         FIGS. 4A and 4B  are cross-sectional drawings illustrating alternative process steps applicable to all embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Stress is a measure of the average amount of force exerted per unit area. Stress is a measure of the intensity of the total internal forces acting within a body across imaginary internal surfaces, as a reaction to external applied forces and body forces. Strain is the geometrical expression of deformation caused by the action of stress on a physical body. 
     Silicon-Germanium (SiGe) has an increased crystal lattice spacing compared to silicon alone. By embedding SiGe regions on either side of silicon channel of a field effect transistor (FET) the channel region will be put in compressive stress. In p-channel field effect transistors (PFETs) the mobility of the majority carriers (holes) is greater than (and electron mobility is less) when the channel region is in compressive stress in the direction of current flow. Increasing the mobility of majority carriers increase the performance of the device in terms of both speed and gain. However, as the area of an embedded SiGe region increases (e.g., allowing increased SiGe surface deflection), the strain within the SiGe region decreases, thus reducing the stress on adjacent the silicon channel region. 
       FIGS. 1A through 1F  are cross-sectional drawings illustrating fabrication of a stressed transistor according to a first embodiment of the present invention. In  FIG. 1A , a silicon-on-insulator (SOI) substrate includes a single-crystal silicon layer  105  and a supporting substrate  110  (e.g., single-crystal silicon) separated by a buried oxide (BOX) layer  115 . In one example BOX layer  115  comprises silicon dioxide. Formed on silicon layer  105  are first and second gate stacks  120 A and  120 B. Gate stacks  120 A and  120 B each comprise a gate dielectric layer  125  on a top surface  127  of silicon layer  105 , a gate electrode a  130  on a top surface of gate dielectric layer  125  and a dielectric capping layer  135  on a top surface of gate electrode  130 . In one example, gate electrode  135  comprises polysilicon. In one example, capping layer  135  comprises silicon dioxide or silicon nitride. Formed on sidewalls of gate stacks  120 A and  120 B are dielectric sidewall spacers  140 . In one example, sidewall spacers  140  comprise silicon dioxide or silicon nitride. 
     In  FIG. 1B , a hardmask layer  145  is formed on exposed surfaces of silicon layer  105 , capping layer  135  and sidewall spacers  140 . In one example, hardmask layer  145  comprises silicon dioxide or silicon nitride. In one example, hardmask layer  145  is a conformal layer. 
     In  FIG. 1C , hardmask layer  145  is patterned to form openings  147  through the hardmask layer with regions of silicon layer  105  exposed in openings  147  so there are regions of silicon layer  105  not protected by hardmask layer  145 , gate stacks  120 A and  120 B and sidewall spacers  140 . Openings  147  are formed in a photolithographic process followed by a wet or dry etch. An example of a dry etch is a reactive ion etch (RIE). In  FIG. 1C , after patterning, hardmask layer  145  has been removed from sidewall spacers  140  and capping layer  135 . Depending upon the etch properties of the particular etch process and the materials of capping layer  135 , sidewall spacers and  140  hardmask layer  145 , it is possible for spacers formed from hardmask layer  145  to be formed on sidewall spacers  140  as illustrated in  FIG. 4A  and described infra. 
     A photolithographic process is one in which a photoresist layer is applied to a surface, the photoresist layer exposed to actinic radiation through a patterned photomask and the exposed photoresist layer developed to form a patterned photoresist layer. When the photoresist layer comprises positive photoresist, the developer dissolves the regions of the photoresist exposed to the actinic radiation and does not dissolve the regions where the patterned photomask blocked (or greatly attenuated the intensity of the radiation) from impinging on the photoresist layer. When the photoresist layer comprises negative photoresist, the developer does not dissolve the regions of the photoresist exposed to the actinic radiation and does dissolve the regions where the patterned photomask blocked (or greatly attenuated the intensity of the radiation) from impinging on the photoresist layer. After further processing (e.g., an etch or an ion implantation), the patterned photoresist is removed. The photoresist layer may optionally be baked at one or more of the following steps: prior to exposure to actinic radiation, between exposure to actinic radiation and development, after development. 
     In  FIG. 1D , an etch process has been performed to etch trenches  150  into silicon layer  105  wherever silicon layer  105  is exposed by openings  147 . In one example, the etch process comprises a wet etch, a plasma etch or a RIE. Gate electrode(s)  130  is protected by capping layer  135  and sidewall spacers  140  from the silicon etching process. In  FIG. 1D , the edges of trenches  150  are aligned to the edges of sidewall spacers  140  and openings  147  in hardmask layer  145 . Depending upon the chemistry of the etchant, the sidewalls of trenches  150  may extend under edges of sidewall spacers  140  and openings  147  in hardmask layer  145  as illustrated in  FIG. 4B  and described infra. 
     In  FIG. 1E , trenches  150  (see  FIG. 1D ) are filled with SiGe to formed SiGe regions  155  between silicon regions  160 . Portions of silicon region  160  under gate electrodes  130  will become the channel regions of FETs as illustrated in  FIG. 1F  and described infra. The SiGe is selectively grown (e.g., by epitaxial deposition) on silicon layer  105  but not on capping layer  135 , sidewall spacers  140  or hardmask layer  145 . In  FIG. 1E , SiGe regions  155  have a width W 1 , silicon regions  160  have a width W 2  and gate electrodes  130  have a width W 3 . Gate stacks  120 A and  120 B are pitched apart a distance P 1 . In one example W 1  is between about 20 nm and about 60 nm, W 2  is between about 20 nm and about 60 nm and W 3  is between about 20 nm and about 60 nm. W 1  may be equal to W 2 , less than W 2  or greater than W 2 . Silicon layer  105  has a thickness T 1  and SiGe regions extend a distance D 1  into silicon layer  105 . In one example, T 1  is between about 120 nm and about 160 nm. In one example, D 1  is between about 80 nm and about 100 nm. In one example, T 1  is greater than D 1 . In one example P 1  is between about 120 nm and about 200 nm. In  FIG. 1E , there are, by way of example, two silicon regions  160  and three SiGe regions  155  between first and second gate stacks  120 A and  120 B. There may be as few as one silicon region  160  between two SiGe regions  155  or more than two silicon regions  160  between corresponding numbers of SiGe regions  155 . It should be understood, that there may be as few as one silicon region  160  between two SiGe regions  155  or more than two silicon regions  160  between corresponding numbers of SiGe regions  155  on both sides of gate stacks  120 A and  120 B and that the number of silicon regions  160  and SiGe regions  155  need not be the same on opposite sides of either of gate stacks  120 A or  120 B. 
     In  FIG. 1F , hardmask layer  145  (see  FIG. 1E ) has been removed and source/drains  165  formed in silicon layer  105  (e.g., by ion implantation). Top surfaces of SiGe regions  155  are essentially coplanar with top surfaces of silicon regions  160 . Top surfaces of silicon regions  160  are exposed between adjacent SiGe regions in source/drains  165 . Source/drains  165  include silicon regions  160  and SiGe regions  155 . While illustrated in  FIG. 1F  as contained within source/drains  165 , SiGe regions  155  may extend through source/drains  165 . While illustrated in  FIG. 1F  as not contacting BOX layer  115 , source/drains  165  may abut BOX layer  115 . While illustrated in  FIG. 1F  as not contacting BOX layer  115 , SiGe regions  155  may abut BOX layer  115 . Gate stacks  120 A and  120 B may either be separate gates of two different FETs or two gate fingers of a multi-gate FET. SiGe regions  155  exert compressive stress on silicon regions  160 . In one example, silicon layer  105  is doped N-type and source/drains  165  are doped P-type. By reducing the surface area of SiGe regions  155  (because of intervening silicon regions  160 ), the ability for strain relief due to surface deformation is reduced and more stress is induced in the channel region of the FET than in an otherwise identical FET where there are no intervening silicon regions  160 . 
     While an SOI substrate has been illustrated in  FIGS. 1A through 1F , the first (and second and third) embodiments of the present invention may be practiced on other semiconductor substrates including conventional bulk silicon substrates (i.e., substrates consisting of solid single-crystal silicon). 
       FIGS. 2A through 2C  are cross-sectional drawings illustrating fabrication of a stressed transistor according to a second embodiment of the present invention. Prior to the steps illustrated in  FIG. 2A , the steps illustrated in  FIGS. 1A ,  1 B,  1 C and  1 D have been performed. In  FIG. 2A , hardmask layer  145  (see  FIG. 1D ) is removed. Gate electrode(s)  130  are still protected by capping layer  135  and sidewall spacers  140 . 
     In  FIG. 2B , trenches  150  (see  FIG. 2A ) are over filled with SiGe to form SiGe layer  170  having thin SiGe regions  175  over silicon regions  160  and thick SiGe regions  180  between silicon regions  160 , thick regions  180  also filling trenches  150  (see  FIG. 2A ). Thus portions of gate stacks  120 A and  120 B extend above and below a top surface of SiGe layer  170 . In  FIG. 2B , there are, by way of example, two silicon regions  160  between first and second gate stacks  120 A and  120 B. There may be as few as one silicon region  160  between two SiGe regions  180  or more than two silicon regions  160  between corresponding numbers of SiGe regions  180 . It should be understood, that there may be as few as one silicon region  160  between two SiGe regions  180  or more than two silicon regions  160  between corresponding numbers of SiGe regions  180  on both sides of gate stacks  120 A and  120 B and that the number of silicon regions  160  and SiGe regions  180  need not be the same on opposite sides of either of gate stacks  120 A or  120 B. SiGe regions  175  have a thickness T 2 . In one example T 2  is between about 10 nm and about 40 nm thick. Thus, at least portions of each of gate stacks  120 A and  120 B are embedded in SiGe layer  170 . 
     In  FIG. 2C , source/drains  185  are formed in silicon layer  105  (e.g., by ion implantation). Source/drains  185  include silicon regions  160  and SiGe layer  170 . While illustrated in  FIG. 2C  as contained within source/drains  185 , SiGe regions  180  may extend through source/drains  185 . While illustrated in  FIG. 2C  as not contacting BOX layer  115 , source/drains  185  may abut BOX layer  115 . While illustrated in  FIG. 2C  as not contacting BOX layer  115 , SiGe regions  180  may abut BOX layer  115 . Gate stacks  120 A and  120 B may either be separate gates of two different FETs or two gate fingers of a multi-gate FET. SiGe regions  180  exert compressive stress on silicon regions  160 . In one example, silicon layer  105  is doped N-type and source/drains  185  are doped P-type. 
       FIGS. 3A through 3F  are cross-sectional drawings illustrating fabrication of a stressed transistor according to a third embodiment of the present invention. Prior to the steps illustrated in  FIG. 3A , the step illustrated in  FIG. 1A  has been performed. In  FIG. 3A , a single-crystal epitaxial silicon layer  190  has been selectively grown (e.g., by epitaxial deposition) on exposed regions of silicon layer  105 , but not on capping layer  135  or sidewall spacers  140 . In  FIG. 3B , hardmask layer  145  is formed (as described supra with respect to  FIG. 1B ) on exposed surfaces of epitaxial silicon layer  190 , capping layer  135  and sidewall spacers  140 . In  FIG. 3C , openings  147  are formed in hardmask layer  145  (as described supra with respect to  FIG. 1C ). In  FIG. 3D , trenches  195  are formed (similarly as to trenches  150  of  FIG. 1D ) through epitaxial silicon layer  190  into silicon layer  105  wherever silicon layer  105  is not protected by hardmask layer  145 , gate stacks  120 A and  120 B and sidewall spacers  140 . In  FIG. 3E , trenches  195  (see  FIG. 3D ) are filled with SiGe to formed SiGe regions  200 . The SiGe is selectively grown (e.g., by epitaxial deposition) on silicon layers  105  and  190  but not on capping layer  135 , sidewall spacers  140  or hardmask layer  145  and hardmask layer  145  (see  FIG. 3D ) is removed. Thus, at least a portion of each of gate stacks  120 A and  120 B extends below a surface formed by SiGe regions  200  and remaining regions of epitaxial silicon layer  190 . In FIG.  3 E, there are, by way of example, two silicon regions  160  between first and second gate stacks  120 A and  120 B. There may be as few as one silicon region  160  between two SiGe regions  200  or more than two silicon regions  160  between corresponding numbers of SiGe regions  200 . It should be understood, that there may be as few as one silicon region  160  between two SiGe regions  200  or more than two silicon regions  160  between corresponding numbers of SiGe regions  200  on both sides of gate stacks  120 A and  120 B and that the number of silicon regions  160  and SiGe regions  200  need not be the same on opposite sides of either of gate stacks  120 A or  120 B. In  FIG. 3F , source/drains  205  formed in silicon layer  105  (e.g., by ion implantation). Source/drains  205  include regions of silicon layers  105  and  190  and SiGe regions  200 . While illustrated in  FIG. 3F  as contained within source/drains  205 , SiGe regions  200  may extend through source/drains  205 . While illustrated in  FIG. 3F  as not contacting BOX layer  115 , source/drains  205  may abut BOX layer  115 . While illustrated in  FIG. 3F  as not contacting BOX layer  115 , SiGe regions  200  may abut BOX layer  115 . Gate stacks  120 A and  120 B may either be separate gates of two different FETs or two fingers of a multi-gate FET. 
       FIGS. 4A and 4B  are cross-sectional drawings illustrating alternative process steps applicable to all embodiments of the present invention. In  FIG. 4A , after etching hardmask layer  145  to form openings  147 , sidewall spacers  145 A (remnants of the hardmask layer  145  on sidewall spacers  140 ) are formed on sidewall spacers  140 . In  FIG. 4B , trenches  155 A undercut hardmask layer  145  and sidewall spacers  140  because the etch has a small lateral etch rate. If spacers  145 A (see  FIG. 4A ) were formed, then in  FIG. 4B , trenches  155 A could extend under spacers  145 A and not under sidewall spacers  140  or could extend under both spacers  145 A and sidewall spacers  140 . 
     Thus, the embodiments of the present invention provide transistors with increased performance and methods of fabricating transistors with increased performance. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Technology Classification (CPC): 7