Patent Abstract:
Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.

Full Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to data transmission in a network comprising buses of different widths and particularly to systems on chip (SoCs) and networks on chip (NoCs). 
     2. Description of the Related Art 
     Systems on chip result from the integration into a same chip of several modules, which can comprise several processors, selected from a library of modules. The modules of a system on chip are not necessarily compatible between themselves particularly in terms of clock signal, communication protocol and interface bus width. 
     Generally, bridges that provide a communication protocol and/or bus width and/or clock frequency conversion are implemented to interconnect two interface buses that are not compatible between themselves. However, when the number of modules to be interconnected having incompatible interfaces is high, the number of bridges becomes excessive. Providing a high number of bridges indeed induces significant costs in terms of silicon surface, latency and energy consumption. 
     To facilitate the design of systems on chip and in particular the interconnection of the modules of such systems, networks have been developed. These networks, referred to as “networks on chip”, generally implement distributed communication means and are based on communication by packet switching and wormhole. Some of these networks comprise three types of communication components, i.e., network interfaces that provide the connection of a module with the network, routers that provide the transmission of packets between the network interfaces and other routers, and links between the routers and between the network interfaces and the routers. Each network interface particularly performs a protocol, and/or clock frequency, and/or data bus width conversion, between an interface bus of a module to which it is connected and a bus internal to the network. Furthermore, some modules have their own network, which is then linked to the network on chip. In addition, for the sake of improved optimization particularly of the chip surface area occupied by the system, it can be useful to provide different data bus widths according to the transmission rates of the modules to be interconnected. The result is that a data bus width is also capable of being converted in certain links between routers. As a result, several data bus width conversions may be applied to a message during the routing thereof between a transmitting module and a receiving module. 
     Two types of problem may arise during such a data bus width conversion. When converting a bus of a given width towards a bus with a smaller width, additional invalid data can be generated and transmitted into the network. It is true that a message transmitted by a data bus does not necessarily have a size corresponding to a whole number of times the width of the bus. The result is that one or more of the last words of the message transmitted by the data bus contain non-valid data. If this message is converted to be transmitted by a less wide data bus, the non-valid data transmitted may be alone in a word transmitted by the less wide data bus. This results in pointless consumption of bandwidth. 
     When converting towards a wider data bus, valid data can be placed on wrong data lines of the wider data bus. Such a conversion can therefore lead to errors in the reconstruction of messages transmitted by the network. 
     It is thus desirable to provide data bus width conversions so as to avoid these problems. It is also desirable to provide such conversions by implementing simple mechanisms and occupying as little surface as possible on the chip. 
     BRIEF SUMMARY 
     Some embodiments relate to a method of transmitting a message in a data path of a network, comprising buses of different widths, the method comprising steps of: transmitting a message onto an input bus of an input interface module of the network, the message being received by the interface module, divided into flits corresponding to the width of the input bus, and transmitting the message received onto an output bus of the interface module towards a receiving interface module, the message transmitted onto the output bus being divided into flits having a size corresponding to the width of the output bus of the input interface module. According to one embodiment, the method comprises steps of: generating a validity indicator for each elementary flit constituting each flit received by the input interface module, each elementary flit having a size corresponding to or smaller than the smallest bus width of the network, each validity indicator indicating whether or not the corresponding elementary flit is valid, transmitting to the receiving interface module, each validity indicator generated, in association with the corresponding elementary flit, and the receiving interface module receiving flits constituting the message and the associated validity indicators, and rejecting a flit received if each elementary flit of the flit is associated with a validity indicator in the invalid state. 
     According to one embodiment, the method comprises the application of a circular permutation to the elementary flits FLT 1  of a flit of a message received by the receiving interface module, according to a target address of the message received, when the size of the message received is less than half the width of an output bus of the receiving interface module. 
     According to one embodiment, the validity indicators are generated by the input interface module according to the size of the message, to the width of the input bus via which the message is received and to a target address of the message. 
     According to one embodiment, the method comprises, in the input interface module, and/or in the receiving interface module, steps of storing the flits received in a first buffer memory, and of storing the validity indicators generated or received in a second buffer memory. 
     According to one embodiment, the message has a size less than or equal to that of an elementary flit, and is received in a flit comprising several elementary flits, the target address of the message being used to determine the position of the elementary flit containing the message in the received flit, the validity indicators of the elementary flits of the received flit being determined according to this position. 
     According to one embodiment, the message has a size less than or equal to half a received flit comprising several elementary flits, the target address of the message being used to determine the position of each elementary flit containing a portion of the message in the received flit, the validity indicators of the elementary flits of the received flit being determined according to this position. 
     According to one embodiment, the method comprises steps of: receiving by a link module of the network situated in the data path, flits constituting the message, and validity indicators associated with the flits received, dividing the message received into flits corresponding to the width of an output bus of the link module, and transmitting to the receiving interface module each flit obtained in the division step, if each elementary flit contained in the flit is associated with a validity indicator in the invalid state, each flit transmitted by the link module being transmitted in association with the validity indicator of each elementary flit contained in the flit. 
     According to one embodiment, the method comprises, in the link module, steps of storing the flits received in a first buffer memory, and of storing the validity indicators received in a second buffer memory. 
     Some embodiments also relate to a system comprising master modules and slave modules, each master and slave module being linked to a network through an interface module, the interface modules being configured to implement the method as defined above. 
     According to one embodiment, the system comprises link modules located in the network on data paths and configured to: receive flits constituting a message, and the validity indicators associated with the flits received, divide the message received into flits corresponding to the width of an output bus of the link module, and transmit onto the output bus each flit obtained in the division step, if each elementary flit contained in the flit is associated with a validity indicator in the invalid state, each flit transmitted being transmitted by the link module in association with the validity indicator of each elementary flit contained in the flit. 
     According to one embodiment, each link module comprises a first buffer memory for storing the flits received, and a second buffer memory for storing validity indicators received. 
     According to one embodiment, each bus of the network is associated with a transmission line for transmitting validity indicators per elementary flit contained in each flit likely to be transmitted by the bus. 
     According to one embodiment, the network comprises routing modules to route messages to a receiving module, according to a target address of the message. 
     Some embodiments also relate to a system on chip, comprising a system as defined above. 
     According to one embodiment, the system on chip comprises at least two of the bus types belonging to a set comprising STBus, AMBA, AXI, AHB, APB, CoreConnect, and Wishbone. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments are described with reference to the following drawings, wherein like labels refer to like parts throughout the various views unless otherwise specified. One or more embodiments are described hereinafter with reference to the accompanying drawings in which: 
         FIG. 1  schematically represents a system on chip comprising a network on chip, only a portion of the network providing the transmission of requests being represented, 
         FIG. 2  schematically represents components implemented in a data transmission path between two modules of the system on chip according to one embodiment, 
         FIG. 3  schematically represents a network interface module according to one embodiment, 
         FIGS. 4A to 4I  schematically represent different embodiments of a sending portion of a network interface module according to the bus widths upstream and downstream of the network interface module, 
         FIGS. 5A to 5I  schematically represent different embodiments of a conversion module of a link module of the network according to the bus widths upstream and downstream of the link module, 
         FIGS. 6A to 6I  schematically represent different embodiments of a receiving portion of a network interface module according to the bus widths upstream and downstream of the network interface module, 
         FIGS. 7 and 8  represent tables of values of validity bits implemented by the network interface modules according to a number of words to be transferred in the network and to a target address of the words to be transferred according to one embodiment, 
         FIGS. 9A and 9B and 10A to 10D  schematically represent switch matrices of data transferred in the network, implemented by the network interface modules. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  represents a system on chip SS comprising master modules IN 1  to IN 5  and slave modules TG 1  to TG 6  interconnected by a network on chip NT. The master modules IN 1 -IN 5  send requests to the slave modules TG 1 -TG 6 , and each slave module sends a response to a request received, to the master module sending this request. The requests and responses are transmitted by the network NT. For more clarity, only a portion of the bus NT providing the transmission of the requests is shown, the network NT comprising a portion (not shown) providing the transmission of the responses. The portion of the network providing the transmission of the responses can be symmetrical to the one providing the transmission of the requests or different. 
     The network NT provides the data transmission based on packet switching for example. The network NT comprises interface modules NI 1  to NI 5  and NI 11  to NI 16 , routers RTR 1  to RTR 3  and link modules ALK 1 , ALK 2  between the interface modules and the routers and between the routers. Each module IN 1 -IN 5 , TG 1 -TG 6  is linked to the network NT through an interface module NI 1 -NI 5  and NI 11 -NI 16 . 
     Below, “data bus” or “bus” indifferently designates by convention a data transmission link outside the network, connected to an interface module NI 1 -NI 5  and NI 11 -NI 16 , or a data transmission link inside the network. 
     Upon sending to the network NT, each interface module NI 1 -NI 5 , NI 11 -NI 16  performs a communication protocol conversion between the protocol used by the module IN 1 -IN 5 , TG 1 -TG 6  to which it is connected and the network, and possibly a clock frequency and/or bus width conversion, as well as an encapsulation of the data to be transmitted. Upon receiving from the network NT, each interface module NI 1 -NI 5 , NI 11 -NI 16  performs a communication protocol conversion between the protocol used by the module IN 1 -IN 5 , TG 1 -TG 6  to which it is connected and the network, an extraction of the data received, and possibly a clock frequency and/or bus width conversion. The network NT comprises routers RTR 1 , RTR 2 , RTR 3  to route the data sent by the interface modules NI 1 -NI 5 , NI 11 -NI 16  to the receiving interface modules, and link modules ALK 1 , ALK 2  to particularly perform bus width conversions. The routers RTR 1 -RTR 3  each comprise several input/output ports, and select a port to route a message received, according to message destination information found in the message heading. 
     In the example in  FIG. 1 , the router RTR 1  is connected to the interface modules NI 1 , NI 2 , NI 11  and NI 12 , and is linked to the router RTR 2  through the link module ALK 1 . The router RTR 2  is connected to the interface modules NI 3 , NI 13  and NI 14 , and to the router RTR 3 . The router RTR 3  is connected to the interface modules NI 4 , NI 5  and NI 16  and is linked to the interface module NI 15  through the link module ALK 2 . 
     The data are transmitted in the network NT encapsulated in messages comprising a heading and possibly end-of-message data. The messages are themselves divided into flow control units referred to as “flits”, comprising a number of bits corresponding to the width of the bus. The messages are transmitted in the network NT in accordance with the wormhole routing mode whereby a data transmission path is kept open between a transmitting module and a receiving module until all the flits making up a message have been transmitted, the first flit of the message containing message routing data enabling each router RTR 1 -RTR 3  to determine to which module (interface module or router) of the network NT the message must be transmitted. 
     The network NT can implement the “Spidergon” topology developed by the Applicant, or a derived architecture. The connection buses for connecting the interface modules NI 1 -NI 5 , NI 11 -NI 16  to the master and slave modules IN 1 -IN 5 , TG 1 -TG 6  can implement protocols such as the STBus protocol developed by the Applicant, the AMBA-type protocols such as ACE, AXI, AHB, APB developed by the company ARM, or the CoreConnect protocol developed by the company IBM, or even the Wishbone protocol developed in “open source”. 
       FIG. 2  represents a data transmission path for transmitting data between a master module INn sending a request or a slave module TGm sending a response to a request, and a slave module TGp receiving the request or a master module INq receiving the response to the request. The data transmission path comprises a transmitting interface module NIj, a link module ALK, and a receiving interface module NIk. The modules NIj and NIk can be any interface module NI 1 -NI 5 , NI 11 -NI 16 . The module ALK can be located in one of the link modules ALK 1 , ALK 2 . 
     The data transmission path comprises in the module NIj an encoding module ENC, a data buffer memory B 1 , for example of FIFO-type (First In, First out), and a decoding module DF. The module ENC is configured to break down into flits a message to be transmitted DT, by taking into account the respective widths of the input IB 1  and output OB 1  buses of the module NIj, and the communication protocols respectively implemented upstream by the module INn/TGm and downstream of the module NIj. The size of the flits generated by the module ENC corresponds to the width of the output bus OB 1  of the module INj. The flits generated comprise one or more elementary flits the size of which corresponds to the width of the least wide bus of the system SS. For example, the system SS comprises buses of 32, 64 and 128 bits. The elementary flits thus comprise 32 bits, and the flits generated by the module ENC comprise one, two or four elementary flits. The memory B 1  is provided for storing several of the flits generated by the module ENC. The module DF is configured to read the flits in the memory B 1  and to send them onto the output bus OB 1  of the module NIj. 
     According to one embodiment, the module NIj comprises a validity bit buffer memory EB 1 , for example of FIFO-type. The memory EB 1  is organized and designed for storing one validity bit per elementary flit constituting the flits stored in the memory B 1 . Each of the bits stored in the memory EB 1  indicates whether or not the corresponding elementary flit in the memory B 1  is valid. The module DF is configured to transfer a flit onto the output bus OB 1  of the module NIj only if the flit comprises at least one valid elementary flit as indicated by the validity bits in the memory EB 1  corresponding to the elementary flits constituting the flit. The module DF is also configured to send the validity bits read in the memory EB 1  onto an output of the module NIj. 
     The data transmission path comprises in the module ALK a buffer memory B 2 , a loading module LD 1  to load the memory B 2  with flits received via an input bus IB 2 , and a reading module DF 1  to read the flits in the memory B 2 . The memory B 2 , which can also be of FIFO-type, receives from the module LD 1  the flits of a message transmitted by the network NT and received via the input bus IB 2  of the module ALK. The module DF 1  is configured to transmit the flits read in the memory B 2  into the network via an output bus OB 2  of the module ALK. 
     According to one embodiment, the module ALK comprises a buffer memory EB 2 , for example of FIFO-type, to store validity bits of elementary flits stored in the memory B 2 , transmitted by the network NT. The module LD 1  comprises an input for receiving the validity bits corresponding to the elementary flits received. The module LD 1  is configured to load the validity bits received into the memory EB 2 . Each of the bits stored in the memory EB 2  indicates whether or not the corresponding elementary flit in the memory B 2  contains a valid datum. The module DF 1  is configured to read the memories B 2  and EB 2  and to transmit into the network NT only the flits read in the memory B 2 , which contain at least one valid elementary flit, as indicated by the corresponding validity bit in the memory EB 2 . The module DF 1  is also configured to transmit into the network the read validity bits corresponding to the elementary flits transmitted. 
     The data transmission path comprises in the module NIk a buffer memory B 3 , a loading module LD for loading the memory B 3  and a decoding module DEC. The memory B 3 , which can also be of FIFO-type, is loaded with the flits of a message received from the network by the module LD via an input bus IB 3  of the module NIk. The module DEC is configured to transmit the flits read in the memory B 3  onto an output bus OB 3  of the module NIk towards the module TGp, INq receiving the message. The module DEC performs, as applicable, a communication protocol, and/or clock frequency, and/or data bus width conversion. 
     According to one embodiment, the module NIk comprises a buffer memory EB 3  to store validity bits of the elementary flits stored in the memory B 3 . The module LD comprises an input for receiving the validity bits corresponding to the elementary flits received and is configured to load the validity bits received into the memory EB 3 . The module DEC is configured to transmit towards the receiving module TGp, INq only the flits read in the memory B 3 , which contain at least one valid elementary flit, i.e., corresponding to a validity bit in the memory EB 3  in the valid state. The module DEC can also be configured to perform the loading of each valid elementary flit onto a correct portion of the output bus OB 3 . 
     It shall be noted that the module ALK may not be necessary and may thus be omitted in the transmission path represented in  FIG. 2 . 
       FIG. 3  represents an interface module NI such as the module NIj or NIk. The module NI comprises a data send circuit comprising the elements of the module NIj represented in  FIG. 2  and a data receive circuit comprising the elements of the module NIk in  FIG. 2 . 
       FIGS. 4A to 4I, 5A to 5I and 6A to 6I  particularly represent bus width conversion circuits. 
       FIGS. 4A to 4I  represent in greater detail different embodiments of data send circuits of the interface module NIj, depending on the width of each of the input IB 1  and output OB 1  buses of the module NIj.  FIG. 4A  shows the case in which the data input IB 1  and output OB 1  buses of the module NIj have a width corresponding to the size of an elementary flit, for example 32 bits. The module NIj comprises an encoding module ENC 1 , buffer memories for data B 11  and validity bits EB 11  and a reading module DF 11 . The module ENC 1  comprises an addressing module BW 11  for simultaneously (i.e., concurrently) addressing the buffer memories B 11  and EB 11 , and a validity bit generating module EBC 1 , which writes in the memory EB 11  at a position selected by the module BW 11 . The memory B 11  is designed for storing a few elementary flits and can be addressed by word having the size of an elementary flit. The memory EB 11  is provided for storing validity bits supplied by the module EBC 1 , and which can for example be addressed individually. The memory EB 11  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 11 . The module BW 11  is configured to successively select each free 32-bit location in the memory B 11  and each free 1-bit location in the memory EB 11 . The module ENC 1  loads each 32-bit flit FLT 1  of a message DT 1  to be sent, into the memory B 11  at a position selected by the module BW 11 . When a flit FLT 1  is loaded into the memory B 11 , the module EBC 1  generates a validity bit BE 1  in the valid state (for example on 1) that is loaded into the memory EB 11  at a corresponding position selected by the module BW 11 . The module DF 11  comprises an addressing module BR 11 , which simultaneously addresses the memories B 11  and EB 11  to successively transfer each flit FLT 1  in the memory B 11  to the output of the module NIj, if the flit is associated in the memory EB 11  with a validity bit BE 1  in the valid state. Each bit BE 1  read in the memory EB 11  and corresponding to a valid flit is also supplied at the output of the module DF 11 . 
       FIG. 4B  shows the case in which the input bus IB 1  of the module NIj has a width corresponding to the size of an elementary flit, for example 32 bits, and the output bus OB 1  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module NIj comprises an encoding module ENC 3 , buffer memories for data B 12  and for validity bits EB 12  and a reading module DF 12 . The encoding module ENC 3  comprises an addressing module BW 13  for simultaneously addressing the memories B 12  and EB 12 , and the validity bit generating module EBC 1  ( FIG. 4A ), which writes in the memory EB 12 . The encoding module ENC 3  also comprises demultiplexers D 13 , ED 13  controlled by the module BW 13 . The demultiplexer D 13  is controlled by the module BW 13  to be able to load a 32-bit flit FLT 1  of a message DT 1  to be transmitted into each 32-bit location in the memory B 12 . The demultiplexer ED 13  is controlled by the module BW 13  to be able to load a 1-bit validity bit BE 1  supplied by the module EBC 1  into each 1-bit location in the memory EB 12 . The buffer memory B 12  is designed for storing a few flits FLT 2  and may be addressed for example by 64-bit word by the module BW 13 . The buffer memory EB 12  is provided for storing a few validity bits, which may for example be addressed in pairs by the module BW 13 . The memory EB 12  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 12 . The module BW 13  is configured to successively select, using the multiplexers D 13  and ED 13 , each free 32-bit location in the memory B 12  and each free 1-bit location in the memory EB 12 . The module ENC 3  loads each 32-bit flit FLT 1  of the message DT 1  to be sent, into the memory B 12  at a position selected by the module BW 13  and a 32-bit location selected by the demultiplexer D 13 . When a flit is loaded into the memory B 12 , the module EBC 1  generates a validity bit BE 1  in the valid state that is loaded into the memory EB 12  at a corresponding position, selected by the module BW 13 , and a 1-bit location selected by the demultiplexer ED 13 . The 1-bit locations not selected in the memory EB 12  are put to the invalid state (for example on 0). The module DF 12  comprises an addressing module BR 12 , which simultaneously addresses each 64-bit location in the memory B 12  and each corresponding bit-pair location BE 2  in the memory EB 12  to transfer a 64-bit flit FLT 2  to the output of the module NIj, if this flit is associated with a pair of validity bits BE 2 , which are not simultaneously in the invalid state. Each pair of bits BE 2  corresponding to a flit transferred to the output of the module NIj, is also supplied at the output of the module DF 12 . 
       FIG. 4C  shows the case in which the input bus IB 1  of the module NIj has a width corresponding to the size of an elementary flit, for example 32 bits, and in which the output bus OB 1  has a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module NIj comprises an encoding module ENC 5 , buffer memories for data B 14  and for validity bits EB 14  and a reading module DF 14 . The module ENC 5  comprises an addressing module BW 15  and the validity bit generating module EBC 1  ( FIG. 4A ). The module BW 15  addresses the memories B 14  and EB 14 , and the validity bit generating module EBC 1 , which writes in the memory EB 14 . The module ENC 5  also comprises demultiplexers D 15 , ED 15  controlled by the module BW 15 . The demultiplexer D 15  is used to store a 32-bit flit FLT 1  of a message DT 1  to be transmitted in each 32-bit location of the memory B 14 . The demultiplexer ED 15  is used to store a 1-bit validity bit BE 1  supplied by the module EBC 1  in each 1-bit location of the memory EB 14 . The buffer memory B 14  is designed for storing a few 128-bit words and can be addressed for example by 128-bit word by the module BW 15 . The buffer memory EB 14  is provided for storing a few validity bits, which can for example be addressed by groups of 4 bits by the module BW 15 . The memory EB 14  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 14 . The module BW 15  is configured to successively select, using the demultiplexers D 15  and ED 15 , each free 32-bit location in the memory B 14  and each free 1-bit location in the memory EB 14 . The module ENC 5  loads each 32-bit flit FLT 1  of the message DT 1  to be sent in the memory B 14  at a location selected by the module BW 15 . When a flit is loaded into the memory B 14 , the module EBC 1  generates a validity bit BE 1  in the valid state that is loaded into the memory EB 14  at a corresponding position, selected by the module BW 15 . The 1-bit locations not selected in the memory EB 14  are put to the invalid state. The module DF 14  comprises an addressing module BR 14 , which successively addresses each 128-bit location in the memory B 14  and each 4-bit location BE 4  in the memory EB 14  corresponding to the location addressed in the memory B 14 , to transfer a 128-bit flit FLT 4  to the output of the module NIj, if this flit is associated with a group of four validity bits BE 4 , which are not simultaneously in the invalid state. Each group of four bits BE 4  corresponding to a flit transferred to the output of the module NIj, is also supplied at the output of the module DF 14 . 
       FIG. 4D  shows the case in which the input bus IB 1  of the module NIj has a width corresponding to the size of two elementary flits, i.e., for example 64 bits, and in which the output bus OB 1  has a width corresponding to the size of an elementary flit, i.e., for example 32 bits. The module NIj comprises an encoding module ENC 2 , the buffer memories for data B 12  and validity bits EB 12  ( FIG. 4B ) and a reading module DF 13 . The encoding module ENC 2  comprises an addressing module BW 12  for addressing the memories B 12  and EB 12 , and a module for generating pairs of validity bits EBC 2 , which writes in the memory EB 12 . The module BW 12  is configured to successively select each free 64-bit location in the memory B 12  and each corresponding 2-bit location in the memory EB 12 . The module ENC 2  loads each 64-bit flit FLT 2  of a message DT 2  to be sent, into the memory B 12  at a position selected by the module BW 12 . When a flit is loaded into the memory B 12 , the module EBC 2  generates a pair of validity bits BE 2 , comprising at least one bit in the valid state. Each pair of validity bits generated BE 2  is loaded into the memory EB 12  at a corresponding position selected by the module BW 12 . The module DF 13  comprises an addressing module BR 13  and multiplexers X 13 , EX 13  controlled by the module BR 13 . The module BR 13  successively addresses each 64-bit location of the memory B 12  and each pair of validity bits stored in the memory EB 12 , and controls the multiplexers X 13 , EX 13  to transfer to the output of the module NIj, a 32-bit flit FLT 1  selected in the 64-bit flit FLT 2  addressed by the module BR 13 , if this flit is associated with a validity bit BE 1  selected by the multiplexer EX 13 , in the valid state. On the contrary, if the validity bit of the flit FLT 1  addressed in the memory B 12  and selected by the multiplexer X 13  is zero, i.e., if the flit is invalid, the flit is not transmitted and is removed from the memory B 12 . Each bit BE 1  corresponding to a flit transferred to the output of the module NIj, is also supplied at the output of the module DF 13 . 
       FIG. 4E  shows the case in which the input IB 1  and output OB 1  buses of the module NIj have a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module NIj comprises the encoding module ENC 2  ( FIG. 4D ), the buffer memories for data B 12  and for validity bits EB 12  ( FIG. 4B ), and the reading module DF 12  ( FIG. 4B ). 
       FIG. 4F  shows the case in which the input bus IB 1  of the module NIj has a width corresponding to the size of two elementary flits, i.e., for example 64 bits, and in which the output bus OB 1  has a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module NIj comprises an encoding module ENC 6 , the buffer memories for data B 14  and for validity bits EB 14  ( FIG. 4C ) and the reading module DF 14  ( FIG. 4C ). The encoding module ENC 6  comprises an addressing module BW 16  for addressing the memories B 14  and EB 14 , and the validity bit generating module EBC 2  ( FIG. 4D ), which writes in the validity bit buffer memory EB 14 . The module ENC 6  also comprises demultiplexers D 16 , ED 16  controlled by the module BW 16 . The demultiplexer D 16  is controlled by the module BW 16  to be able to load a 64-bit flit FLT 2  of a message DT 2  to be transmitted into each 64-bit location of the memory B 14 . The demultiplexer ED 16  is controlled by the module BW 16  to be able to load two validity bits BE 2  supplied by the module EBC 2  into each 2-bit location of the memory EB 14 . The module BW 16  is configured to successively select, using the demultiplexers D 16  and ED 16 , each free 64-bit location in the memory B 14  and each free 2-bit location in the memory EB 14 . The module ENC 6  loads each 64-bit flit FLT 2  of the message DT 2  to be sent into the memory B 14  at a position selected by the module BW 16  and by the demultiplexer D 16  controlled by the module BW 16 . When a 64-bit flit FLT 2  is loaded into the memory B 14 , the module EBC 2  generates a pair of validity bits BE 2  in the valid state. The pair of validity bits generated is loaded into the memory EB 14  at a corresponding position, selected by the module BW 16 . The 2-bit locations not selected in the memory EB 14  are put to the invalid state. 
       FIG. 4G  shows the case in which the input bus IB 1  of the module NIj has a width corresponding to the size of four elementary flits, i.e., for example 128 bits, and in which the output bus OB 1  has a width corresponding to the size of an elementary flit, i.e., for example 32 bits. The module NIj comprises an encoding module ENC 4 , the buffer memories for data B 14  and for validity bits EB 14  ( FIG. 4C ) and a reading module DF 15 . The encoding module ENC 4  comprises an addressing module BW 14  for addressing the memories B 14  and EB 14 , and a validity bit generating module EBC 4 , which writes in the memory EB 14 . The module BW 14  is configured to successively select each free 128-bit location in the memory B 14  and each corresponding 4-bit location in the memory EB 14 . The module ENC 4  loads each 128-bit flit FLT 4  of a message DT 4  to be sent into the memory B 14  at a position selected by the module BW 14 . When a 128-bit flit FLT 4  is loaded into the memory B 14 , the module EBC 4  generates a group of four validity bits BE 4  comprising at least one bit in the valid state. The group of validity bits generated is loaded into the memory EB 14  at a position selected by the module BW 14 . The module DF 15  comprises an addressing module BR 15  and multiplexers X 15 , EX 15  controlled by the module BR 15 . The addressing module BR 15  successively addresses each 128-bit location in the memory B 14  and each 4-bit location BE 4  in the memory EB 14 , and controls the multiplexers X 15 , EX 15  to transfer a 32-bit flit FLT 1  selected in the 128-bit flit FLT 4  addressed by the module BR 15 , to the output of the module NIj, if this flit corresponds to a validity bit BE 1  selected by the multiplexer EX 15  in the valid state. On the contrary, if the flit FLT 1  addressed in the memory B 14  and selected by the multiplexer X 15  is invalid, the flit is not transmitted and is removed from the memory B 14 . Each bit BE 1  corresponding to a flit transferred to the output of the module NIj, is also transferred to the output of the module NIj. 
       FIG. 4H  shows the case in which the input bus IB 1  of the module NIj has a width corresponding to the size of four elementary flits, i.e., for example 128 bits, and in which the output bus OB 1  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module NIj comprises the encoding module ENC 4  ( FIG. 4G ), the buffer memories for data B 14  and for validity bits EB 14  ( FIG. 4C ), and a reading module DF 16 . The module DF 16  comprises an addressing module BR 16  and multiplexers X 16 , EX 16  controlled by the module BR 16 . The addressing module BR 16  successively addresses each 128-bit location in the memory B 14  and each corresponding 4-bit location BE 4  in the memory EB 14 , and controls the multiplexers X 16 , EX 16  to transfer a 64-bit flit FLT 2  selected in the 128-bit flit FLT 4  addressed by the module BR 16 , to the output of the module NIj, if this flit is associated with a pair of validity bits BE 2  selected in the memory EB 14  by the multiplexer EX 16 , at least one bit of which is in the valid state. On the contrary, if the flit FLT 2  addressed in the memory B 14  and selected by the multiplexer X 16  is invalid, it is not transmitted and is removed from the memory B 14 . Each pair of bits BE 2  corresponding to a flit transferred to the output of the module NIj, is also transferred to the output of the module NIj. 
       FIG. 4I  shows the case in which the input IB 1  and output OB 1  buses of the module NIj have a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module NIj comprises the encoding module ENC 4  ( FIG. 4G ), the buffer memories for data B 14  and for validity bits EB 14  ( FIG. 4C ), and the reading module DF 14  ( FIG. 4C ). 
     The interface modules NIj in  FIGS. 4A, 4E and 4I  do not perform any bus width conversion towards a different link width (local size conversion), but can perform a communication protocol and/or clock frequency conversion. 
       FIGS. 5A to 5I  represent in greater detail different embodiments of data transmission circuits of the link module ALK, depending on the width of the input IB 2  and output OB 2  buses of the module ALK.  FIG. 5A  shows the case in which the input IB 2  and output OB 2  buses of the module ALK have a width corresponding to the size of an elementary flit, i.e., for example 32 bits. The module ALK comprises a loading module LD 21 , buffer memories for data B 21  and for validity bits EB 21  and a reading module DF 21 . The module LD 21  comprises an addressing module BW 21  for addressing the buffer memories B 21  and EB 21 . The buffer memory B 21  is designed for storing a few 32-bit words and can be addressed by 32-bit word. The buffer memory EB 21  is provided for storing a few validity bits BE 1  received by the module LD 21 , which can for example be addressed individually. The memory EB 21  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 21 . The module BW 21  is configured to successively select each free 32-bit location in the memory B 21  and each corresponding 1-bit location in the memory EB 21 . The module LD 21  loads each 32-bit flit FLT 1  received into the memory B 21  at a position selected by the module BW 21 . When a flit FLT 1  is loaded into the memory B 21 , the corresponding validity bit BE 1  is loaded into the memory EB 21  at a corresponding position selected by the module BW 21 . The module DF 21  comprises an addressing module BR 21 , which successively addresses each location in the memories B 21  and EB 21  to transfer a flit FLT 1  to the output of the module ALK, if this flit is associated in the memory EB 21  with a validity bit BE 1  in the valid state. Each bit BE 1  read in the memory EB 21  and corresponding to a valid flit, is also supplied at the output of the module DF 21 . 
       FIG. 5B  shows the case in which the input bus IB 2  of the module ALK has a width corresponding to the size of an elementary flit, i.e., for example 32 bits, and in which the output bus OB 2  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module ALK comprises a loading module LD 23 , buffer memories for data B 22  and for validity bits EB 22  and a reading module DF 22 . The encoding module LD 23  comprises an addressing module BW 23  for addressing the memories B 22  and EB 22 . The module LD 23  also comprises demultiplexers D 23 , ED 23  controlled by the module BW 23 . The demultiplexer D 23  is used to store a 32-bit flit FLT 1  received by the module LD 23  in each 32-bit location of the memory B 22 . The demultiplexer ED 23  is used to store a 1-bit validity bit BE 1  received by the module LD 23  in each 1-bit location of the memory EB 22 . The buffer memory B 22  is designed for storing a few 64-bit words and can be addressed for example by 64-bit word. The buffer memory EB 22  is provided for storing a few bits, which can for example be addressed in pairs. The memory EB 22  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 22 . The module BW 23  is configured to successively select, using the multiplexers D 23  and ED 23 , each free 32-bit location in the memory B 22  and each corresponding 1-bit location in the memory EB 22 . The module LD 23  loads each 32-bit flit FLT 1  received into the memory B 22  at a position selected by the module BW 23 . When a flit is loaded into the memory B 22 , a validity bit BE 1  is loaded into the memory EB 22  at a corresponding position, selected by the module BW 23 . The 1-bit locations not selected in the memory EB 22  are put to the invalid state. The module DF 22  comprises an addressing module BR 22 , which successively addresses each 64-bit location in the memory B 22  and each 2-bit location BE 2  in the memory EB 22  to transfer a 64-bit flit FLT 2  to the output of the module ALK, if this flit is associated with a pair of validity bits BE 2 , which are not simultaneously in the invalid state. Each pair of bits BE 2  read in the memory EB 22  and corresponding to a flit transferred to the output of the module NIj, is also supplied at the output of the module DF 22 . 
       FIG. 5C  shows the case in which the input bus IB 2  of the module ALK has a width corresponding to the size of an elementary flit, i.e., for example 32 bits, and in which the output bus OB 2  has a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module ALK comprises a loading module LD 25 , buffer memories for data B 24  and for validity bits EB 24  and a reading module DF 24 . The module LD 25  comprises an addressing module BW 25 . The module BW 25  addresses the memories B 24  and EB 24 . The module LD 25  also comprises demultiplexers D 25 , ED 25  controlled by the module BW 25 . The demultiplexer D 25  is used to store a 32-bit flit FLT 1  received by the module LD 25  in each 32-bit location of the memory B 24 . The demultiplexer ED 25  is used to store a validity bit BE 1  received by the module LD 25  in each 1-bit location of the memory EB 24 . The buffer memory B 24  is designed for storing a few 128-bit words and can be addressed for example by 128-bit word. The buffer memory EB 24  is provided for storing a few bits, which can for example be addressed by groups of 4 bits. The memory EB 24  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 24 . The module BW 25  is configured to successively select, using the multiplexers D 25  and ED 25 , each free 32-bit location in the memory B 24  and each corresponding 1-bit location in the memory EB 24 . The module LD 25  loads each 32-bit flit FLT 1  received into the memory B 24  at a position selected by the module BW 25 . When a flit is loaded into the memory B 14 , a corresponding validity bit BE 1  received is loaded into the memory EB 24  at a corresponding position, selected by the module BW 25 . The 1-bit locations not selected in the memory EB 24  are put to the invalid state. The module DF 24  comprises an addressing module BR 24 , which successively addresses each 128-bit location in the memory B 24  and each 4-bit location BE 4  in the memory EB 24  to transfer a 128-bit flit FLT 4  to the output of the module ALK, if this flit is associated with a group of four validity bits BE 4 , which are not simultaneously in the invalid state. Each group of four bits BE 4  read in the memory EB 24  and corresponding to a flit transferred to the output of the module ALK, is also supplied at the output of the module DF 24 . 
       FIG. 5D  shows the case in which the input bus IB 2  of the module ALK has a width corresponding to the size of two elementary flits, i.e., for example 64 bits, and in which the output bus OB 2  has a width corresponding to the size of an elementary flit, i.e., for example 32 bits. The module ALK comprises a loading module LD 22 , the buffer memories for data B 22  and for validity bits EB 22  ( FIG. 5B ) and a reading module DF 23 . The module LD 22  comprises an addressing module BW 22  for addressing the memories B 22  and EB 22 . The module BW 22  is configured to successively select each free 64-bit location in the memory B 22  and each corresponding 2-bit location in the memory EB 22 . The module LD 22  loads each 64-bit flit FLT 2  received by the module LD 22 , into the memory B 22  at a position selected by the module BW 22 . When a flit is loaded into the memory B 22 , a pair of validity bits BE 2  received by the module LD 22  is loaded into the memory EB 22  at a corresponding position selected by the module BW 22 . The module DF 23  comprises an addressing module BR 23  and multiplexers X 23 , EX 23 . The module BR 23  successively addresses each 64-bit location in the memory B 22  and each pair of validity bits stored in the memory EB 22 , and controls the multiplexers X 23 , EX 23  to transfer to the output of the module ALK, a 32-bit flit FLT 1  selected in the 64-bit flit FLT 2  addressed by the module BR 23 , if this flit is associated with a validity bit BE 1  selected in the memory EB 22  by the multiplexer EX 23  in the valid state. On the contrary, if the flit FLT 1  addressed in the memory B 22  and selected by the multiplexer X 23  is invalid, it is not transmitted and is removed from the memory B 22 . Each bit BE 1  read in the memory EB 22  and corresponding to a flit FLT 1  transferred to the output of the module ALK, is also supplied at the output of the module DF 23 . 
       FIG. 5E  shows the case in which the input IB 2  and output OB 2  buses of the module ALK have a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module ALK comprises the loading module LD 22  ( FIG. 5D ), the buffer memories for data B 22  and for validity bits EB 22  ( FIG. 5B ), and the reading module DF 22  ( FIG. 5C ). 
       FIG. 5F  shows the case in which the input bus IB 2  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits, and in which the output bus OB 2  has a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module ALK comprises a loading module LD 26 , the buffer memories for data B 24  and for validity bits EB 24  ( FIG. 5C ) and the reading module DF 24  ( FIG. 5C ). The module LD 26  comprises an addressing module BW 26  for addressing the memories B 24  and EB 24 . The module LD 26  also comprises demultiplexers D 26 , ED 26  controlled by the module BW 26 . The demultiplexer D 26  is used to store a 64-bit flit FLT 2  received by the module LD 26  in each 64-bit location of the memory B 24 . The demultiplexer ED 26  is used to store a pair of validity bits BE 2  received by the module LD 26  in each 2-bit location of the memory EB 24 . The module BW 26  is configured to successively select, using the demultiplexers D 26  and ED 26 , each free 64-bit location in the memory B 24  and each free 2-bit location in the memory EB 24 . The module LD 26  loads each 64-bit flit FLT 2  received into the memory B 24  at a position selected by the module BW 26  and by the demultiplexer D 26  controlled by the module BW 26 . When a 64-bit flit FLT 2  is loaded into the memory B 24 , a pair of validity bits BE 2  received by the module LD 26  is loaded into the memory EB 24  at a corresponding position, selected by the module BW 26 . The 2-bit locations not selected in the memory EB 24  are put to the invalid state. 
       FIG. 5G  shows the case in which the input bus IB 2  of the module ALK has a width corresponding to the size of four elementary flits, i.e., for example 128 bits, and in which the output bus OB 2  has a width corresponding to the size of one elementary flit, i.e., for example 32 bits. The module ALK comprises a loading module LD 24 , the buffer memories for data B 24  and for validity bits EB 24  ( FIG. 5C ) and a reading module DF 25 . The module LD 24  comprises an addressing module BW 24  for addressing the memories B 24  and EB 24 . The module BW 24  is configured to successively select each free 128-bit location in the memory B 24  and each corresponding 4-bit location in the memory EB 24 . The module LD 24  loads each 128-bit flit FLT 4  received into the memory B 24  at a position selected by the module BW 24 . When a 128-bit flit FLT 4  is loaded into the memory B 24 , the module LD 24  loads a group of four validity bits BE 4  received at a corresponding position, selected by the module BW 24  in the memory EB 24 . The module DF 25  comprises an addressing module BR 25  and multiplexers X 25 , EX 25  controlled by the module BW 25 . The addressing module BR 25  successively addresses each 128-bit location in the memory B 24  and each 4-bit location BE 4  in the memory EB 24 , and controls the multiplexers X 25 , EX 25  to transfer a 32-bit flit FLT 1  selected in the 128-bit flit FLT 4  addressed by the module BR 25 , to the output of the module ALK, if this flit is associated with a validity bit BE 1  in the valid state, selected by the multiplexer EX 25  in the 4-bit location addressed by the module BR 25  in the memory EB 24 . On the contrary, if the flit FLT 1  addressed in the memory B 24  and selected by the multiplexer X 25  is invalid, it is not transmitted and is removed from the memory B 24 . Each bit BE 1  read in the memory EB 24  and corresponding to a valid flit, is also transferred to the output of the module ALK. 
       FIG. 5H  shows the case in which the input bus IB 2  of the module ALK has a width corresponding to the size of four elementary flits, i.e., for example 128 bits, and in which the output bus OB 2  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module ALK comprises the loading module LD 24  ( FIG. 5G ), the buffer memories for data B 24  and for validity bits EB 24  ( FIG. 5C ) and a reading module DF 26 . The module DF 26  comprises an addressing module BR 26  and multiplexers X 26 , EX 26  controlled by the module BW 26 . The addressing module BR 16  successively addresses each 128-bit location in the memory B 14  and each corresponding 4-bit location BE 4  in the memory EB 24 , and controls the multiplexers X 26 , EX 26  to transfer a 64-bit flit FLT 2  selected in the 128-bit flit FLT 4  addressed by the module BR 26 , to the output of the module ALK, if this flit is associated with a pair of validity bits BE 2  selected by the multiplexer EX 26  at least one bit of which is in the valid state. On the contrary, if the flit FLT 2  addressed in the memory B 24  and selected by the multiplexer X 26  is invalid, it is not transmitted and is removed from the memory B 24 . Each pair of bits BE 2  read in the memory EB 24  and corresponding to a flit transferred to the output of the module NIj, is also transferred to the output of the module ALK. 
       FIG. 5I  shows the case in which the input IB 2  and output OB 2  buses of the module ALK have a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module ALK comprises the loading module LD 24  ( FIG. 5G ), the buffer memories for data B 24  and for validity bits EB 24  ( FIG. 5C ), and the reading module DF 24  ( FIG. 5C ). 
     The link modules ALK in  FIGS. 5A, 5E and 5I  do not perform any bus width conversion, but may perform a clock frequency conversion, and/or repeat the data transmitted when the link length on which the conversion module is located is too long. 
       FIGS. 6A to 6I  represent in greater detail different embodiments of data receive circuits of the interface module NIk, depending on the width of the input IB 3  and output OB 3  buses of the module NIk.  FIG. 6A  shows the case in which the input IB 3  and output OB 3  buses of the module NIk have a width corresponding to the size of one elementary flit, i.e., for example 32 bits. The module NIk comprises a loading module LD 31 , buffer memories for data B 31  and for validity bits EB 31  and a decoding module DEC 1 . The module LD 31  comprises an addressing module BW 31  for addressing the buffer memories B 31  and EB 31 . The buffer memory B 31  is designed for storing a few 32-bit words and can be addressed by 32-bit word. The buffer memory EB 31  is provided for storing a few validity bits BE 1  received by the module LD 31  and which can for example be addressed individually. The memory EB 31  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 31 . The module BW 31  is configured to successively select each free 32-bit location in the memory B 31  and each corresponding 1-bit location in the memory EB 31 . The module LD 31  loads each 32-bit flit FLT 1  received into the memory B 31  at a position selected by the module BW 31 . When a flit is loaded into the memory B 31 , the corresponding validity bit BE 1  received is loaded into the memory EB 31  at a corresponding position selected by the module BW 31 . The module DEC 1  comprises an addressing module BR 31 , which successively addresses each location in the memories B 31  and EB 31  to transfer a flit FLT 1  to the output of the module NIk, if this flit is associated with a validity bit BE 1  in the valid state. 
       FIG. 6B  shows the case in which the input bus IB 3  of the module NIk has a width corresponding to the size of one elementary flit, i.e., for example 32 bits, and in which the output bus OB 3  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module NIk comprises a loading module LD 33 , buffer memories for data B 32  and for validity bits EB 32  and a decoding module DEC 2 . The encoding module LD 33  comprises an addressing module BW 33  for addressing the memories B 32  and EB 32 . The module LD 33  also comprises demultiplexers D 33 , ED 33  controlled by the module BW 33 . The demultiplexer D 33  is used to store a 32-bit flit received by the module LD 33  in each 32-bit location of the memory B 32 . The demultiplexer ED 33  is used to store a 1-bit validity bit BE 1  received by the module LD 33  in each 1-bit location of the memory EB 32 . The buffer memory B 32  is designed for storing a few 64-bit words and can be addressed for example by 64-bit word. The buffer memory EB 32  is provided for storing a few bits, which can for example be addressed in pairs. The memory EB 32  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 32 . The module BW 33  is configured to successively select, using the demultiplexers D 33  and ED 33 , each free 32-bit location in the memory B 32  and each corresponding 1-bit location in the memory EB 32 . The module LD 33  loads each 32-bit flit FLT 1  received into the memory B 32  at a position selected by the module BW 33 . When a flit is loaded into the memory B 32 , a validity bit BE 1  is loaded into the memory EB 32  at a corresponding position, selected by the module BW 33 . The 1-bit locations not selected in the memory EB 32  are put to the invalid state. The module DEC 2  comprises an addressing module BR 32 , and a switch matrix BLM 2 . The module BR 32  successively addresses each 64-bit location in the memory B 32  and each 2-bit location BE 2  in the memory EB 32  to transfer a 64-bit flit FLT 2  to the output of the module NIk, if this flit is associated with a pair of validity bits BE 2 , which are not simultaneously in the invalid state. The matrix BLM 2  receives the flits FLT 2  at output of the memory B 32  and inverts if necessary the 32-bit elementary flits in the flits FLT 2 . 
       FIG. 6C  shows the case in which the input bus IB 3  of the module NIk has a width corresponding to the size of one elementary flit, i.e., for example 32 bits, and in which the output bus OB 3  has a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module NIk comprises a loading module LD 35 , buffer memories for data B 34  and for validity bits EB 34  and a decoding module DEC 4 . The module LD 35  comprises an addressing module BW 35 . The module BW 35  addresses the memories B 34  and EB 34 . The module LD 35  also comprises demultiplexers D 35 , ED 35  controlled by the module BW 35 . The demultiplexer D 35  is used to store a 32-bit flit FLT 1  received by the module LD 35  in each 32-bit location of the memory B 34 . The demultiplexer ED 35  is used to store a validity bit BE 1  received by the module LD 35  in each 1-bit location of the memory EB 34 . The buffer memory B 34  is designed for storing a few 128-bit words and can be addressed for example by 128-bit word. The buffer memory EB 34  is provided for storing a few bits, which can for example be addressed by groups of 4 bits. The memory EB 34  is designed for storing one validity bit per elementary flit likely to be stored in the memory B 34 . The module BW 35  is configured to successively select, using the multiplexers D 35  and ED 35 , each free 32-bit location in the memory B 34  and each corresponding 1-bit location in the memory EB 34 . The module LD 35  loads each 32-bit flit FLT 1  received into the memory B 34  at a position selected by the module BW 35 . When a flit is loaded into the memory B 14 , a corresponding validity bit BE 1  received is loaded into the memory EB 34  at a corresponding position, selected by the module BW 35 . The 1-bit locations not selected in the memory EB 34  are put to the invalid state. The module DEC 4  comprises an addressing module BR 34 , and a switch matrix BLM 4 . The module BR 34  successively addresses each 128-bit location in the memory B 34  and each 4-bit location BE 4  in the memory EB 34  to transfer a 128-bit flit FLT 4  to the output of the module NIk, if this flit is associated with a group of four validity bits BE 4 , which are not all in the invalid state. The matrix BLM 4  receives the flits FLT 4  at output of the memory B 34  and redistributes if necessary the 32-bit elementary flits in the flits FLT 4 . 
       FIG. 6D  shows the case in which the input bus IB 3  of the module NIk has a width corresponding to the size of two elementary flits, i.e., for example 64 bits, and in which the output bus OB 3  has a width corresponding to the size of one elementary flit, i.e., for example 32 bits. The module NIk comprises a loading module LD 32 , the buffer memories for data B 32  and for validity bits EB 32  ( FIG. 6B ) and a decoding module DEC 3 . The module LD 32  comprises an addressing module BW 32  for addressing the memories B 32  and EB 32 . The module BW 32  is configured to successively select each free 64-bit location in the memory B 32  and each corresponding bit-pair location in the memory EB 32 . The module LD 32  loads each 64-bit flit FLT 2  received by the module LD 32 , into the memory B 32  at a position selected by the module BW 32 . When a flit is loaded into the memory B 32 , a pair of validity bits BE 2  received by the module LD 32  is loaded into the memory EB 32  at a corresponding position selected by the module BW 32 . The module DEC 3  comprises an addressing module BR 13  and multiplexers X 33 , EX 33 . The module BR 33  successively addresses each 64-bit location in the memory B 32  and each corresponding pair of validity bits stored in the memory EB 32 , and controls the multiplexers X 33 , EX 33  to transfer to the output of the module NIk, a 32-bit flit FLT 1  selected in the 64-bit flit FLT 2  addressed by the module BR 33 , if this flit is associated with a validity bit BE 1  selected by the multiplexer EX 33  in the valid state. On the contrary, if the flit FLT 1  addressed in the memory B 32  and selected by the multiplexer X 33  is invalid, it is not transmitted and is removed from the memory B 32 . 
       FIG. 6E  shows the case in which the input IB 3  and output OB 3  buses of the module NIk have a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module NIk comprises the loading module LD 32  ( FIG. 6D ), the buffer memories for data B 32  and for validity bits EB 32  ( FIG. 6B ), and the reading module DEC 2  ( FIG. 6B ). 
       FIG. 6F  shows the case in which the input bus IB 3  of the module NIk has a width corresponding to the size of two elementary flits, i.e., for example 64 bits, and in which the output bus OB 3  has a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module NIk comprises a loading module LD 36 , the buffer memories for data B 34  and for validity bits EB 34  ( FIG. 6C ) and the decoding module DEC 4  ( FIG. 6C ). The module LD 36  comprises an addressing module BW 36  for addressing the memories B 34  and EB 34 . The module LD 36  also comprises demultiplexers D 36 , ED 36  controlled by the module BW 36 . The demultiplexer D 36  is used to store a 64-bit flit FLT 2  received by the module LD 36  in each 64-bit location of the memory B 34 . The demultiplexer ED 36  is used to store two validity bits BE 2  received by the module LD 36  in each 2-bit location of the memory EB 34 . The module BW 36  is configured to successively select, using the demultiplexers D 36  and ED 36 , each free 64-bit location in the memory B 34  and each corresponding 2-bit location in the memory EB 34 . The module LD 36  loads each 64-bit flit FLT 2  received into the memory B 34  at a position selected by the module BW 36  and by the demultiplexer D 36  controlled by the module BW 36 . When a 64-bit flit FLT 2  is loaded into the memory B 34 , a pair of validity bits BE 2  received by the module LD 36  is loaded into the memory EB 34  at a corresponding position, selected by the module BW 36 . The 2-bit locations not selected in the memory EB 34  are put to the invalid state. 
       FIG. 6G  shows the case in which the input bus IB 3  of the module NIk has a width corresponding to the size of four elementary flits, i.e., for example 128 bits, and in which the output bus OB 3  has a width corresponding to the size of one elementary flit, i.e., for example 32 bits. The module NIk comprises a loading module LD 34 , the buffer memories for data B 34  and for validity bits EB 34  ( FIG. 6C ) and a decoding module DEC 5 . The module LD 34  comprises an addressing module BW 34  for addressing the memories B 34  and EB 34 . The module BW 34  is configured to successively select each free 128-bit location in the memory B 34  and each corresponding 4-bit location in the memory EB 34 . The module LD 34  loads each 128-bit flit FLT 4  received into the memory B 34  at a position selected by the module BW 34 . When a 128-bit flit FLT 4  is loaded into the memory B 34 , the module LD 34  loads a group of four validity bits BE 4  received at a corresponding position, selected by the module BW 34 . The module DEC 5  comprises an addressing module BR 35  and multiplexers X 35 , EX 35  controlled by the module BW 35 . The addressing module BR 35  successively addresses each 128-bit location in the memory B 34  and each 4-bit location BE 4  in the memory EB 34 , and controls the multiplexers X 35 , EX 35  to transfer a 32-bit flit FLT 1  selected in the 128-bit flit FLT 4  addressed by the module BR 35 , to the output of the module NIk, if this flit is associated with a validity bit BE 1  selected by the multiplexer EX 35  in the valid state. On the contrary, if the flit FLT 1  addressed in the memory B 34  and selected by the multiplexer X 35  is invalid, it is not transmitted and is removed from the memory B 34 . 
       FIG. 6H  shows the case in which the input bus IB 3  of the module NIk has a width corresponding to the size of four elementary flits, i.e., for example 128 bits, and in which the output bus OB 3  has a width corresponding to the size of two elementary flits, i.e., for example 64 bits. The module NIk comprises the loading module LD 34  (FIG.  6 G), the buffer memories for data B 34  and for validity bits EB 34  ( FIG. 6C ) and a decoding module DEC 6 . The module DEC 6  comprises an addressing module BR 36 , multiplexers X 36 , EX 36  controlled by the module BW 36  and the matrix BLM 2 . The addressing module BR 36  successively addresses each 128-bit location in the memory B 14  and each 4-bit location BE 4  in the memory EB 34 , and controls the multiplexers X 36 , EX 36  to transfer a 64-bit flit FLT 2  selected in the 128-bit flit FLT 4  addressed by the module BR 36 , to the output of the module NIk, if this flit is associated with a pair of validity bits BE 2  selected by the multiplexer EX 36  at least one bit of which is in the valid state. On the contrary, if the flit FLT 2  addressed in the memory B 34  and selected by the multiplexer X 36  is invalid, it is not transmitted and is removed from the memory B 34 . The matrix BLM 2  receives the flits FLT 2  at output of the multiplexer X 36  and inverts if necessary the 32-bit elementary flits in the flits FLT 2 . 
       FIG. 6I  shows the case in which the input IB 3  and output OB 3  buses of the module NIk have a width corresponding to the size of four elementary flits, i.e., for example 128 bits. The module NIk comprises the loading module LD 34  ( FIG. 6G ), the buffer memories for data B 34  and for validity bits EB 34  ( FIG. 6C ), and the decoding module DEC 4  ( FIG. 6C ). 
     The interface modules NIk in  FIGS. 6A, 6E and 6I  do not locally perform any bus width conversion, but may perform a communication protocol and/or clock frequency conversion. 
     It goes without saying that the multiplexers X 13 , EX 13  ( FIG. 4D ), X 15 , EX 15  ( FIG. 4G ), X 16 , EX 16  ( FIG. 4H ), X 23 , EX 23  ( FIG. 5D ), X 25 , EX 25  ( FIG. 5G ), X 26 , EX 26  ( FIG. 5H ), X 33 , EX 33  ( FIG. 6D ), X 35 , EX 35  ( FIG. 6G ), X 36 , EX 36  ( FIG. 6H ), can be placed, not downstream, but upstream from the buffer memories B 12 , EB 12 , B 14 , EB 14 , B 22 , EB 22 , B 24 , EB 24 , B 32 , EB 32 , B 34 , EB 34 . In this case, the buffer memories B 12 , EB 12 , B 22 , EB 22 , B 32 , EB 32  can be replaced with the memories B 11 , EB 11 , B 21 , EB 21 , B 31 , EB 31 , and the memories B 14 , EB 14 , B 24 , EB 24 , B 34 , EB 34 , replaced with the memories B 12 , EB 12 , B 22 , EB 22 , B 32 , EB 32 . 
       FIG. 7  represents a table indicating the value of the pairs of validity bits BE 2 , implemented by the module EBC 2  ( FIGS. 4D and 4F ) when the output bus of the interface module has a width corresponding to the size of two elementary flits. In this table, the value of the pairs BE 2  depends on the third least significant bit ADD[ 2 ] of a target address ADD of the message to be transmitted DT 2 , and on a number of words NBB making up the message DT 2 , each address value enabling one word to be located. For request messages, the necessary address bits ADD[ 2 , 3 ] and the number NBB appear in heading data of the message. For response messages, the address ADD and the number NBB come from the module sending the response, or are found in registers of the interface module NIk connected to the module sending the response message. One word corresponds for example to one byte. If the number NBB is equal to 1, 2 or 4, i.e., if the message has a size smaller than or equal to that of one elementary flit (32 bits), the pair BE 2  is equal to “01” if the bit ADD[ 2 ] is equal to 0 and “10” if the bit ADD[ 2 ] is equal to 1. When the pair BE 2  is equal to “01”, this means that the corresponding flit FLT 2  comprises a valid elementary flit in first position and an invalid elementary flit in second position. When the pair BE 2  is equal to “10”, this means that the corresponding flit FLT 2  comprises an invalid elementary flit in first position and a valid elementary flit in second position. If the number NBB is greater than or equal to 8, i.e., if the message has a size greater than that of an elementary flit, the pair BE 2  is equal to “11” irrespective of the value of the bit ADD[ 2 ], which means that the corresponding flit FLT 2  comprises two valid elementary flits. 
       FIG. 8  represents a table indicating the value of the groups of four validity bits BE 4 , implemented by the module EBC 4  ( FIGS. 4G to 4I ) when the output bus of the interface module NIj has the width corresponding to four elementary flits. In this table, the value of the groups of four validity bits BE 4  depends on the fourth and third least significant bits ADD[ 3 , 2 ] of the target address ADD of the message to be transmitted DT 4  and on the number of words NBB making up the message DT 4 . If the number NBB is equal to 1, 2 or 4 (the message has a size smaller than or equal to that of an elementary flit, i.e., 32 bits), the group BE 4  is equal to “0001” if the bits ADD[ 3 , 2 ] are equal to “00”, “0010” if the bits ADD[ 3 , 2 ] are equal to “01”, “0100” if the bits ADD[ 3 , 2 ] are equal to “10”, and “1000” if the bits ADD[ 3 , 2 ] are equal to “11”. When the group BE 4  is equal to “0001”, this means that the corresponding flit FLT 4  comprises one valid elementary flit in first position and three invalid elementary flits in second, third and fourth positions. When the group BE 4  is equal to “0010”, this means that the corresponding flit FLT 4  comprises an invalid elementary flit in first position, a valid elementary flit in second position and invalid elementary flits in third and fourth positions. More generally, each bit on 0 of the group BE 4  indicates that the corresponding elementary flit of the flit FLT 4  is invalid, and each bit on 1 of the group BE 4  indicates that the corresponding elementary flit is valid. If the number NBB is equal to 8 (the message has the size of two elementary flits, i.e., 64 bits), the group BE 4  is equal to “0011” if the bit ADD[ 3 ] is equal to 0 and “1100” if the bit ADD[ 3 ] is equal to 1. If the number NBB is greater than or equal to 16 (the message has a size greater than or equal to that of four elementary flits, i.e., 128 bits), the group BE 4  is equal to “1111” indicating that all the elementary flits of the corresponding flit FLT are valid. 
     The switch matrices BLM 2 , BLM 4  can apply to a received flit a circular permutation of the elementary flits constituting the flit when the size NBB of the message received is smaller than or equal to half the size of a flit transmitted by the output bus of the module NIk.  FIGS. 9A, 9B  represent the configuration of the switch matrix BLM 2  ( FIGS. 6B, 6E, 6H ) when the output bus of the interface module NIk has a width corresponding to the size of two elementary flits. The configuration of the matrix BLM 2  depends on the number of words NBB making up the message DT 2 , and on the value of the third least significant bit ADD[ 2 ] of the target address ADD of the message to be transmitted DT 2 .  FIG. 9A  shows the cases in which the bit ADD[ 2 ] is equal to 0, and in which the bit ADD[ 2 ] is equal to 1 when the number NBB in the message DT 2  is greater than or equal to 8. In these cases, the matrix BLM 2  does not change the order of the two elementary flits constituting the flit FLT 2 . 
       FIG. 9B  shows the case in which the bit ADD[ 2 ] is equal to 1 when the number NBB in the message DT 2  is lower than or equal to 4 (the message received occupies at the most a single elementary flit and thus at the most half a flit transmitted by the output bus). In this case, the matrix BLM 2  performs an inversion of the two elementary flits constituting the flit FLT 2 . Such an inversion is equivalent to a circular permutation of one elementary flit rank. 
       FIGS. 10A, 10B, 10C and 10D  represent the configuration of the switch matrix BLM 4  ( FIGS. 6C, 6F, 6I ) when the output bus of the interface module NIk has a width corresponding to the size of four elementary flits. The configuration of the matrix BLM 4  depends on the fourth and third least significant bits ADD[ 3 , 2 ] of the target address ADD of the message to be transmitted DT 4 , when the number NBB in the message DT 4  is lower than or equal to 8.  FIG. 10A  shows the cases in which the bits ADD[ 3 , 2 ] are equal to “00” when the number NBB is lower than or equal to 8, in which the bits ADD[ 3 , 2 ] are equal to “01” when the number NBB is equal to 8, and in which the number NBB is greater than 8. In these cases, the matrix BLM 4  does not redistribute the four elementary flits constituting the flit FLT 4 . 
       FIG. 10B  shows the case in which the bits ADD[ 3 , 2 ] are equal to “01” when the number NBB is lower than or equal to 4. Therefore, the message received occupies at the most a single elementary flit and thus at the most one quarter of a flit transmitted by the output bus. In this case, the matrix BLM 4  performs a circular permutation of the elementary flits constituting the flit FLT 4  by increasing by one their respective ranks (from 1 to 4) in the flit FLT 4 , the last elementary flit  1  changing to the first position. 
       FIG. 10C  shows the cases in which the bits ADD[ 3 , 2 ] are equal to “10” when the number NBB is lower than or equal to 8 and in which the bits ADD[ 3 , 2 ] are equal to “11” when the number NBB is equal to 8. Therefore, the message received occupies at the most two elementary flits and thus at the most half a flit transmitted by the output bus. In these cases, the matrix BLM 4  performs an inversion of the two pairs ( 1 ,  2 ), ( 3 ,  4 ) of consecutive elementary flits constituting the flit FLT 4  (circular permutation of two ranks of elementary flits). 
       FIG. 10D  shows the case in which the bits ADD[ 3 , 2 ] are equal to “11” when the number NBB is lower than or equal to 4. Therefore, the message occupies at the most a single elementary flit and thus at the most one quarter of a flit transmitted by the output bus. In this case, the matrix BLM 4  performs a circular permutation of the elementary flits constituting the flit FLT 4 , by decreasing by one their respective ranks (from 1 to 4) in the flit FLT 4 , the first elementary flit  4  changing to the last position. 
     It shall be noted that in  FIGS. 7 to 10D , the bits of the target address ADD used depend on the different widths of the links and the buses of the network NT. If a link or a bus having other widths is implemented in the network NT, other bits of the address ADD can be used to determine the values of the validity bits and the configurations of the switch matrices. 
     As a result of these provisions, the non-valid elementary flits can be identified by the validity bits BE 1 , BE 2 , BE 4 , and thus, may not be transmitted unnecessarily in the case of a conversion of a bus having a certain width towards a less wide bus. Furthermore, upon a conversion from a bus having a certain width towards a wider bus, the switch matrices enable the valid elementary flits to be correctly placed onto the lines of the wider bus, taking into account the target address of the data transmitted. 
     The implementation of these provisions can be carried out with the addition of small buffer memories used to store the validity bits BE 1 , BE 2 , BE 4 , and adding to each bus of the network only one transmission line per elementary flit making up each flit transmitted by the bus. Furthermore, the logic circuits generating or using the validity bits implement simple mechanisms and thus occupy very little space on a chip into which a system implementing these provisions is integrated. 
     It will be understood by those skilled in the art that various alternative embodiments and various applications of the present invention are possible. In particular, the invention is not limited to 32-bit elementary flits and width conversions between buses of widths corresponding to one, two or four elementary flits. The claims attached can be applied to other sizes of elementary flits and to any other bus widths that are multiples of a same bus width corresponding to the size of one elementary flit. Embodiments apply to systems on chip and may also apply to any system comprising a data transmission network made up of buses of different widths. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Technology Classification (CPC): 7