Patent Abstract:
A method for testing operation of a preamplifier circuit includes generating a first symbol, converting the first symbol into a write signal, transmitting the write signal to a write signal input of the preamplifier circuit, and looping the write signal back to a read signal output of the preamplifier circuit.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 10/722,079, filed Nov. 25, 2003. The disclosure of the above application is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to data storage devices, and more particularly to preamplifiers and read channel circuits in data storage devices. 
     BACKGROUND OF THE INVENTION 
     Referring now to  FIG. 1 , an exemplary data storage device  10  is shown. A buffer  18  stores data that is associated the control of a hard disk drive. The buffer  18  may employ SDRAM or other types of low latency memory. A processor  22  performs processing that is related to the operation of the hard disk drive. A hard disk controller (HDC)  26  communicates with the buffer  18 , the processor  22 , a host  24 , a spindle/voice coil motor (VCM) driver  30 , and/or a read/write channel circuit  34 . 
     During a write operation, the read/write channel circuit or read channel circuit  34  encodes the data to be written onto the storage medium. The read/write channel circuit  34  processes the signal for reliability and may include, for example error correction coding (ECC), run length limited coding (RLL), and the like. During read operations, the read/write channel circuit  34  converts an analog output from the medium to a digital signal. The converted signal is then detected and decoded by known techniques to recover the data written on the hard disk drive. 
     One or more hard drive platters  52  include a magnetic coating that stores magnetic fields. The platters  52  are rotated by a spindle motor that is schematically shown at  54 . Generally the spindle motor  54  rotates the hard drive platter  52  at a fixed speed during the read/write operations. One or more read/write arms  58  move relative to the platters  52  to read and/or write data to/from the hard drive platters  52 . The spindle/VCM driver  30  controls the spindle motor  54 , which rotates the platter  52 . The spindle/VCM driver  30  also generates control signals that position the read/write arm  58 , for example using a voice coil actuator, a stepper motor or any other suitable actuator. 
     A read/write device  59  is located near a distal end of the read/write arm  58 . The read/write device  59  includes a write element such as an inductor that generates a magnetic field. The read/write device  59  also includes a read element (such as a magneto-resistive (MR) element) that senses the magnetic fields on the platter  52 . A preamplifier (preamp) circuit  60  amplifies analog read/write signals. When reading data, the preamp circuit  60  amplifies low level signals from the read element and outputs the amplified signal to the read/write channel circuit  34 . While writing data, a write current that flows through the write element of the read/write device  59  is switched to produce a magnetic field having a positive or negative polarity. The positive or negative polarity is stored by the hard drive platter  52  and is used to represent data. 
     Referring now to  FIG. 2 , the read channel circuit  34  outputs write signals w dx  and w dy  to the preamp circuit  60  when writing data. The preamp circuit  60  amplifies the write signals using a write amplifier  90 . The amplified write signals are output to the read/write device  59 . When reading data, the preamp circuit  60  receives signals from the read/write device  59 , amplifies the signals using a read amplifier  92  and outputs amplified read signals r dx  and r dy  to the read channel circuit  34 . In current data storage device architectures, there is no way to test whether the preamp circuit  60  is operating properly. Therefore, it is difficult to diagnose malfunctions in the preamp circuit  60 . 
     SUMMARY OF THE INVENTION 
     A data storage device preamp circuit according to the present invention includes a write amplifier having an input and an output. A read amplifier has an input and an output. A loopback circuit selectively connects the output of the write amplifier to the output of the read amplifier. 
     In other features, the write amplifier amplifies a write signal from a read channel circuit and outputs the amplified write signal to a read/write device. The read amplifier amplifies a read signal that is received from the read/write device and outputs the amplified read signal to the read channel circuit. 
     In still other features, the loopback circuit includes at least one of a switch and a multiplexer that selectively connects the output of the write amplifier to the output of the read amplifier. 
     In still other features, a trigger controls the switch and/or the multiplexer. Alternatively, the switch and/or the multiplexer is controlled by a write enable signal from the read channel circuit. 
     A read channel circuit for a data storage device according to the present invention includes a first counter that generates a first count of an attribute of a write signal that is output by the read channel circuit. A second counter generates a second count of the attribute of a looped-back write signal that is received by the read channel circuit. 
     In other features, a comparator compares a difference between the first count and the second count to a threshold and outputs a first state when the difference is less than the threshold and a second state when the difference is not less than the threshold. The read channel circuit generates a write enable signal that is output to a preamp circuit to enable a loopback mode of the preamp circuit. The attribute can be a rising edge, a falling edge and a pulse. 
     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a functional block diagram of an exemplary data storage device according to the prior art; 
         FIG. 2  is a functional block diagram of a read channel circuit and preamp circuit according to the prior art; 
         FIG. 3A  is a functional block diagram of a first exemplary read channel circuit and a preamp circuit with switched loopback according to the present invention; 
         FIG. 3B  is a functional block diagram of a first exemplary read channel circuit and a preamp circuit with multiplexed loopback according to the present invention; 
         FIG. 4  is a functional block diagram of a second exemplary read channel circuit and preamp circuit with loopback according to the present invention; 
         FIG. 5  is a functional block diagram of a third exemplary read channel circuit and preamp circuit with loopback according to the present invention; 
         FIG. 6  is a functional block diagram of a fourth exemplary read channel circuit and preamp circuit with loopback according to the present invention; 
         FIG. 7  is a functional block diagram of a read channel circuit that includes a data generator, a delay element and a comparator and preamp circuit with loopback according to the present invention; and 
         FIG. 8  is a functional block diagram of a hard drive controller that includes a data generator, a delay element and a comparator, a read channel circuit and preamp circuit with loopback according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
     Referring now to  FIG. 3A , a functional block diagram of a read channel circuit  100  and a preamp circuit  102  according to the present invention is shown. The read channel circuit  100  includes a first counter  104  that counts an attribute of the write signal w ax  and w ay . An output of the first counter  104  is input to a comparator  106 , which has a threshold Th. A second counter  108  counts the selected attribute of the read signal r ax  and r ay  that is received from the preamp circuit  102 . For example, the counters  104  and  108  can count a rising edge, a falling edge, a pulse and/or any other attribute of the write signal and the looped-back write signal. The counted attributes allow a comparison to be made between the write signal and the looped-back write signal, which indicates the operability of the preamp circuit  102 . 
     The preamp circuit  102  includes a write amplifier  114  that is located in the write path. The write amplifier  114  amplifies the write signal w ax  and w dy  and outputs the amplified write signal to the read/write device  59 . The preamp circuit  102  also includes a read amplifier  116  that receives read signals from the read/write device  59 , amplifies the read signals to generate the read signals r dx  and r dy , and outputs the amplified read signals to the read channel circuit  100 . 
     The preamp circuit  102  provides a loopback mode during which the write amplifier  114  of the preamp circuit  102  is tested. In  FIG. 3A , a switch  120  connects an output of the write amplifier  114  to an output of the read amplifier  116 . When the switch  120  is used, the read amplifier  116  is optionally turned off during the loopback mode to reduce noise in the system due to signals from the read/write head  59 . Turning off the read amplifier  116  may be accomplished by turning off or disconnecting a supply voltage, disconnecting the input of the read amplifier  116  from the read/write head and/or grounding the inputs of the read amplifier  116 . 
     As can be appreciated, other devices such as a multiplexer can be used by the loopback circuit. Referring now to  FIG. 3B , a multiplexer  121  is used to connect the output of the write amplifier  114  to the read channel  100 . The multiplexer  121  also disconnects the output of the write amplifier  116  at the same time, which reduces noise. 
     Referring now to  FIGS. 3A and 3B , a write enable signal (W) is generated by the read channel circuit  100  during a write operation. In one embodiment, the write enable signal controls the switch  120  or the multiplexer  121 . The output of the write amplifier  114  is looped back by the switch  120  or the multiplexer  121  to the read channel circuit  100 . In other words, the switch  120  or the multiplexer  121  connects the output of the write amplifier  114  to the read signal input of the read channel  100 . When the write enable signal is not asserted (e.g. during a read operation), the output of the write amplifier  114  is not looped back by the switch  120  or the multiplexer  121  to the read channel circuit  100 . 
     The first counter  104  generates a first count of the selected attribute of the write signal. The first count is output to the comparator  106 . The second counter  108  receives the amplified write signal that is looped back through the write amplifier  114 . The second counter  108  generates a second count of the attribute for the looped-back write signal. The second count is output to the comparator  106 . The comparator  106  compares a difference between the first and second counts to a threshold (Th). 
     If the difference between the first and second counts are less than or equal to the threshold, the comparator  106  outputs a first state. If the difference between the first and second counts are not less than or equal to the threshold, the comparator  106  outputs a second state. The first state corresponds to an operational preamplifier circuit. The second state corresponds to a non-operational preamplifier circuit. Faults and/or flags can optionally be generated when the comparator outputs the second state. As can be appreciated, testing of the preamp circuit  102  can be performed when the write enable signal is present. In addition, the testing can be performed at other intervals. For example, testing can be performed when the write enable signal is present during startup, periodically, randomly, during all write operations, in response to a particular event or events, or in any other suitable manner. 
     Referring now to  FIG. 4 , a functional block diagram of a second exemplary read channel circuit  100  and preamp circuit  102  according to the present invention are shown. In  FIG. 4 , both the write amplifier  114  and the read amplifier  116  are tested at the same time. When the write enable signal is present, the output of the write amplifier  114  is connected by a multiplexer  129  through an optional attenuator circuit  130  to an input of the read amplifier  116 . The attenuator circuit  130  attenuates the output of the write amplifier  114  if needed to prevent damage to the read amplifier  116 . The multiplexer  129  disconnects the input of the read amplifier  116  from the read/write head  59 . 
     Referring now to  FIGS. 5 and 6 , functional block diagrams of third and fourth exemplary read channel circuits  100  and preamp circuits  102  are shown. The read channel circuits  100  and preamp circuits  102  in  FIGS. 5 and 6  are similar to those shown in  FIGS. 3 and 4 , respectively. However, instead of using the write enable signal to initiate the test, the preamp circuit  110  includes a trigger  140  that automatically triggers the loopback mode periodically when the write enable signal is present. For example, the trigger  140  can be triggered during startup when the write enable signal is present. The test enable signal that is generated by the trigger  140  remains high for a predetermined period during which the testing of the write amplifier  114  is performed. After the test is complete, the test enable signal goes low until the next startup. When the switch  120  is used in  FIG. 5 , the read amplifier  116  is optionally turned off during the loopback mode to reduce noise in the system due to signals from the read/write head  59 . Turning off the read amplifier  116  may be accomplished by turning off or disconnecting a supply voltage, disconnecting the input of the read amplifier  116  from the read/write head and/or grounding the inputs of the read amplifier  116 . 
     Referring now to  FIG. 7 , the read channel (RC) circuit  100  includes a RC encoding circuit  150  in the write path and a RC decoding circuit  152  in the read path. The read channel circuit  100  includes a data generator  160  that generates a test symbol that is encoded and transmitted as a write signal to the preamp circuit  102 . The write signal is amplified by the write amplifier  114  and looped back by the switch  120  during the loopback mode to the RC decoding circuit  152 . The RC decoding circuit  152  decodes the write signal and outputs a received symbol to a comparator  164 . As can be appreciated, a multiplexer may also be used. 
     The comparator  164  compares the received symbol to a delayed test signal. A delay element  166  can be used to delay the test symbol for an appropriate amount of time. As can be appreciated, a latch, a buffer or any other suitable device can alternatively be used to store the test symbol until the received symbol is received at the comparator  164 . If the received symbol and test symbol match, the comparator  164  outputs a first state. If the symbols do not match, the comparator  164  outputs a second state. The first state corresponds to an operational preamplifier circuit. The second state corresponds to a non-operational preamplifier circuit. Faults and/or flags can optionally be generated when the comparator outputs the second state. When the switch  120  is used in  FIG. 7 , the read amplifier  116  is optionally turned off during the loopback mode to reduce noise in the system due to signals from the read/write head  59 . Turning off the read amplifier  116  may be accomplished by turning off or disconnecting a supply voltage, disconnecting the input of the read amplifier  116  from the read/write head and/or grounding the inputs of the read amplifier  116 . 
     Referring now to  FIG. 8 , a hard drive control (HDC) circuit  170  includes a HDC write processing circuit  172  in the write path and a HDC read processing circuit  174  in the read path. The data generator  160  generates a test symbol that is output by the HDC  170 , encoded by the read channel circuit  100  and transmitted to the preamp circuit  102 . The write signal is amplified by the write amplifier  114  and looped back by the switch  120  during the loopback mode to the read channel circuit  100  where decoding occurs. The received symbol is output to the comparator  164  in the HDC  170 . As can be appreciated, a multiplexer can also be used. 
     The comparator  164  compares the received symbol to a delayed test signal. The delay element  166  can be used to delay the test symbol for an appropriate amount of time. As can be appreciated, a latch, a buffer or any other suitable device can alternatively be used to store the test symbol until the appropriate time. If the symbols match, the comparator  164  outputs a first state. If the symbols do not match, the comparator  164  outputs a second state. The first state corresponds to an operational preamplifier circuit. The second state corresponds to a non-operational preamplifier circuit. Faults and/or flags can optionally be generated when the comparator outputs the second state. 
     The data generator, delay, and comparator components can be located anywhere on the read/write path, integrated with any device located on the read/write path, located in a host, and/or located in any other suitable device. Skilled artisans will appreciate that the embodiments in  FIGS. 5-8  may also be implemented using a multiplexer in a manner similar to  FIGS. 3B and 4 . When the switch  120  is used in  FIG. 3A ,  5  and  7 , the read amplifier  116  is optionally turned off during the loopback mode to reduce noise in the system due to signals from the read/write head  59 . In one implementation, the signal that is used to initial the loopback mode can also be used to shut down the read amplifier  116 . Alternately, the signal that is used to initiate the loopback mode can be used to trigger the additional switches and/or multiplexers that are used to turn off the read amplifier  116 . 
     While the present invention has been described in conjunction with hard drives, skilled artisans will appreciate that the foregoing invention has application to any data storage device including hard disk drives, compact disk (CD) drives (write and/or read/write), digital video disk (DVD) drives (read and/or read/write), optical drives, and/or any other type of data storage device. 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

Technology Classification (CPC): 6