Patent Abstract:
A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.

Full Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor transistors and more particularly to semiconductor transistors having high-K gate dielectric layers and metal gate electrodes. 
       BACKGROUND OF THE INVENTION 
       [0002]    A typical semiconductor transistor having high-K gate dielectric layer and metal gate electrode usually has poor gate dielectric quality at bottom corners of the gate electrode. Therefore, there is a need for a structure (and a method for forming the same) in which the gate dielectric quality at bottom corners of the gate electrode has a higher quality than that of the prior art. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a semiconductor structure, comprising a semiconductor substrate which includes a channel region; a first source/drain region on the semiconductor substrate; a second source/drain region on the semiconductor substrate, wherein the channel region is disposed between the first and second source/drain regions; a final gate dielectric region, wherein the final gate dielectric region comprises a first dielectric material, wherein the final gate dielectric region is in direct physical contact with the channel region via an interfacing surface, and wherein the interfacing surface defines a reference direction perpendicular to the interfacing surface and pointing from the final gate dielectric region toward the channel region; a final gate electrode region, wherein the final gate dielectric region is disposed between and in direct physical contact with the channel region and the final gate electrode region, and wherein the final gate electrode region comprises an electrically conductive material; and a first gate dielectric corner region, wherein the first gate dielectric corner region comprises a second dielectric material that is different from the first dielectric material, wherein the first gate dielectric corner region is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, wherein the first gate dielectric corner region is not in direct physical contact with the final gate electrode region, and wherein the first gate dielectric corner region overlaps the final gate electrode region in the reference direction. 
         [0004]    The present invention provides a structure (and a method for forming the same) in which the gate dielectric quality at bottom corners of the gate electrode has a higher quality than that of the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIGS. 1A-1M  show cross-section views used to illustrate a fabrication process of a semiconductor structure, in accordance with embodiments of the present invention. 
           [0006]      FIGS. 2A-2L  show cross-section views used to illustrate a fabrication process of another semiconductor structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0007]      FIGS. 1A-1M  show cross-section views used to illustrate a fabrication process of a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process of the semiconductor structure  100  can start with a silicon substrate  110 . 
         [0008]    Next, in one embodiment, a temporary gate dielectric layer  112  is formed on top of the silicon substrate  110 . The temporary gate dielectric layer  112  can comprise silicon dioxide. If silicon dioxide is used, the temporary gate dielectric layer  112  can be formed by thermally oxidizing the top surface  118  of the silicon substrate  110  resulting in the temporary gate dielectric layer  112 . 
         [0009]    Next, in one embodiment, a temporary gate electrode layer  120  is formed on top of the temporary gate dielectric layer  112 . The temporary gate electrode layer  120  can comprise poly-silicon. The temporary gate electrode layer  120  can be formed by CVD (Chemical Vapor Deposition) of poly-silicon on top of the temporary gate dielectric layer  112  resulting in the temporary gate electrode layer  120 . 
         [0010]    Next, in one embodiment, a cap layer  125  is formed on top of the temporary gate electrode layer  120 . The cap layer  125  can comprise silicon dioxide. The cap layer  125  can be formed by CVD of silicon dioxide on top of the temporary gate electrode layer  120  resulting in the cap layer  125 . 
         [0011]    Next, in one embodiment, the cap layer  125  and the temporary gate electrode layer  120  are patterned resulting in the cap region  125  and the temporary gate electrode region  120  of  FIG. 1B . More specifically, the cap layer  125  and the temporary gate electrode layer  120  can be patterned by anisotropically and selectively etching in a direction defined by an arrow  115  (hereafter can be referred to as the direction  115 ) resulting the cap region  125  and the temporary gate electrode region  120  of  FIG. 1B . The direction  115  is perpendicular to the top surface  118  of the silicon substrate  110  and points from the temporary gate dielectric layer  112  toward the silicon substrate  110 . 
         [0012]    Next, with reference to  FIG. 1B , in one embodiment, a thermal oxidization of the exposed surfaces of the structure  100  of  FIG. 1B  is performed resulting in dielectric regions  130   a  and  130   b  of  FIG. 1C  on side walls of the temporary gate electrode region  120 . Also as a result of this thermal oxidization step, most of the portions of the temporary gate dielectric layer  112  of  FIG. 1B  increase in thickness in the direction  115  resulting in the temporary gate dielectric layer  112 ′. More specifically, the closer to the surrounding ambient a portion of the temporary gate dielectric layer  112  of  FIG. 1B  is, the thicker in the direction  115  this portion is. For instance, with reference to  FIG. 1C , for the portions of the temporary gate dielectric layer  112 ′ sandwiched between the temporary gate electrode region  120  and the silicon substrate  110 , the closer to the center point C a portion is, the thinner in the direction  115  this portion is. 
         [0013]    The temporary gate dielectric layer  112 ′ comprises bird&#39;s beaks  112   a  and  112   b  at bottom corners of the temporary gate electrode region  120 . The dielectric regions  130   a  and  130   b  and the temporary gate dielectric layer  112 ′ can comprise silicon dioxide. 
         [0014]    Next, with reference to  FIG. 1D , in one embodiment, extension regions  114   a  and  114   b  are formed in the silicon substrate  110 . The extension regions  114   a  and  114   b  can be formed using a conventional ion implantation process. 
         [0015]    Next, with reference to  FIG. 1E , in one embodiment, a spacer layer  140  is formed on top of the structure  100  of  FIG. 1D . The spacer layer  140  can comprise silicon nitride. The spacer layer  140  can be formed by CVD of silicon nitride on top of the structure  100  of  FIG. 1D  resulting in the spacer layer  140 . 
         [0016]    Next, in one embodiment, the spacer layer  140  and the temporary gate dielectric layer  112 ′ are anisotropically etched in the direction  115  until the top surface  118  of the silicon substrate  110  is exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1F . After the etching of the spacer layer  140  and the temporary gate dielectric layer  112  is performed, with reference to  FIG. 1F , what remain of the spacer layer  140  are spacer regions  140   a  and  140   b , whereas what remains of the temporary gate dielectric layer  112  is the temporary gate dielectric region  112 ″ which includes the bird&#39;s beaks  112   a  and  112   b.    
         [0017]    Next, with reference to  FIG. 1F , in one embodiment, source/drain regions  116   a  and  116   b  are formed in the silicon substrate  110 . The source/drain regions  116   a  and  116   b  can be formed using a conventional ion implantation process. 
         [0018]    Next, with reference to  FIG. 1G , in one embodiment, silicide regions  150   a  and  150   b  are formed on the source/drain regions  116   a  and  116   b , respectively. More specifically, the silicide regions  150   a  and  150   b  can be formed by (i) depositing a metal layer (not shown) on top of the structure  100  of  FIG. 1F , then (ii) heating the structure  100  resulting in the metal chemically reacting with silicon of the source/drain regions  116   a  and  116   b , and then (iii) removing unreacted metal resulting in the silicide regions  150   a  and  150   b . If the metal used is nickel, then the silicide regions  150   a  and  150   b  comprise nickel silicide. 
         [0019]    Next, with reference to  FIG. 1H , in one embodiment, a silicon nitride layer  160  and a BPSG (boro-phospho-silicate glass) layer  170  are formed in turn on top of the structure  100  of  FIG. 1G . More specifically, the silicon nitride layer  160  and the BPSG layer  170  can be formed by (i) depositing silicon nitride on top of the structure  100  of  FIG. 1G  resulting in the silicon nitride layer  160  and then (ii) depositing BPSG on top of the silicon nitride layer  160  resulting in the BPSG layer  170 . 
         [0020]    Next, in one embodiment, a CMP (Chemical Mechanical Polishing) process is performed on top of the structure  100  of  FIG. 1H  until the top surface  122  of the temporary gate electrode region  120  is exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1I . After the CMP process is performed, what remain of the BPSG layer  170  are BPSG regions  170   a  and  170   b , and what remain of the silicon nitride layer  160  are silicon nitride regions  160   a  and  160   b.    
         [0021]    Next, with reference to  FIG. 1I , in one embodiment, the temporary gate electrode region  120  is removed resulting in a trench  124  of  FIG. 1J . The temporary gate electrode region  120  can be removed using a wet etching process. 
         [0022]    Next, with reference to  FIG. 1J , silicon dioxide on side walls and bottom walls of the trench  124  is removed (by using a wet etching process, for example) resulting in the top surface  118  of the silicon substrate  110  being exposed to the surrounding ambient, as shown in  FIG. 1K . After the removal, what remain of the temporary gate dielectric region  112 ″ are the bird&#39;s beaks  112   a  and  112   b.    
         [0023]    Next, with reference to  FIG. 1L , in one embodiment, a final gate dielectric layer  180  and a final gate electrode layer  190  are formed in turn on top of the structure  100  of  FIG. 1K . The final gate dielectric layer  180  can comprise a high-K dielectric material, wherein K is dielectric constant and K is greater than 4. For example, the final gate dielectric layer  180  comprises hafnium silicon oxynitride (HfSiON). The final gate electrode layer  190  can comprise a metal such as tantalum nitride (TaN). The final gate dielectric layer  180  and the final gate electrode layer  190  can be formed by (i) CVD or ALD (Atomic Layer Deposition) of the hafnium silicon oxynitride on top of the structure  100  of  FIG. 1K  resulting in the final gate dielectric layer  180  and then (ii) CVD or ALD of tantalum nitride on top of the final gate dielectric layer  180  such that the trench  124  is completely filed with tantalum nitride resulting in the final gate electrode layer  190 . 
         [0024]    Next, in one embodiment, a CMP process is performed on top of the structure  100  of  FIG. 1L  until the top surface  170 ′ of the BPSG regions  170   a  and  170   b  is exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1M . After the CMP process is performed, what remain of the final gate dielectric layer  180  and the final gate electrode layer  190  are the final gate dielectric region  180  and the final gate electrode region  190 , respectively. In one embodiment, each of the bird&#39;s beaks  112   a  and  112   b  overlaps the final gate electrode region  190  in the direction  115 . A first region is said to overlap a second region in a reference direction if and only if there exits at least one point inside the first region such that a straight line going through that point and being parallel to the reference direction would intersect the second region. 
         [0025]    Next, in one embodiment, interconnect layers (not shown) are formed on top of the structure  100  to provide electrical access to the source/drain regions  116   a  and  116   b  and the final gate electrode region  190 . 
         [0026]    With reference to  FIG. 1M , the structure  100  shows a transistor having the final gate electrode region  190 , the final gate dielectric region  180 , the source/drain regions  116   a  and  116   b  and the channel  119 . The presence of the bird&#39;s beaks  112   a  and  112   b  at corners of the final gate electrode region  190  increases the distances between the final gate electrode region  190  and the source/drain regions  116   a  and  116   b  and thereby helps reduce leakage currents between the final gate electrode region  190  and the source/drain regions  116   a  and  116   b  during the operation of the transistor. 
         [0027]      FIGS. 2A-2L  show cross-section views used to illustrate a fabrication process of a semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 2A , the fabrication process of the semiconductor structure  200  can start with the structure  200  of  FIG. 2A . The structure  200  is similar to the structure  100  of  FIG. 1B . The formation of the structure  200  is similar to the formation of  FIG. 1B . 
         [0028]    Next, in one embodiment, the structure  200  is annealed in ammonia (NH 3 ) or ammonia plasma resulting in silicon dioxide of the cap region  225  and exposed portions of the temporary gate dielectric layer  112  being converted to SiON, as shown in  FIG. 2B . More specifically, with reference to  FIG. 2B , dielectric regions  230   a  and  230   b  of the temporary gate dielectric layer  112  now comprise SiON, whereas the temporary gate dielectric region  212  still comprises silicon dioxide. The cap region  225  now comprises SiON. In one embodiment, the annealing of the structure  200  is performed such that the dielectric regions  230   a  and  230   b  undercut the temporary gate electrode region  120 . As a result, both the dielectric regions  230   a  and  230   b  overlap the temporary gate electrode region  120  in the direction  115 . 
         [0029]    Next, with reference to  FIG. 2C , in one embodiment, extension regions  114   a  and  114   b  are formed in the silicon substrate  110 . The extension regions  114   a  and  114   b  can be formed using a conventional ion implantation process. 
         [0030]    Next, with reference to  FIG. 2D , in one embodiment, a spacer layer  240  is formed on top of the structure  200  of  FIG. 2C . The spacer layer  240  can comprise silicon nitride. The spacer layer  240  can be formed by CVD of silicon nitride on top of the structure  200  of  FIG. 2C  resulting in the spacer layer  240 . 
         [0031]    Next, in one embodiment, the spacer layer  240  and the dielectric regions  230   a  and  230   b  are anisotropically etched in the direction  115  until the top surface  118  of the silicon substrate  110  is exposed to the surrounding ambient resulting in the structure  100  of  FIG. 2E . After the etching of the spacer layer  240  and the dielectric regions  230   a  and  230   b  is performed, with reference to  FIG. 2E , what remain of the spacer layer  240  are spacer regions  240   a  and  240   b , whereas what remain of the dielectric regions  230   a  and  230   b  are gate dielectric corner regions  230   a  and  230   b.    
         [0032]    Next, with reference to  FIG. 2F , in one embodiment, source/drain regions  116   a  and  116   b  are formed in the silicon substrate  110 . The source/drain regions  116   a  and  116   b  can be formed using a conventional ion implantation process. 
         [0033]    Next, in one embodiment, silicide regions  250   a  and  250   b  are formed on the source/drain regions  116   a  and  116   b , respectively. More specifically, the silicide regions  250   a  and  250   b  can be formed in a manner similar to the manner in which the silicide regions  150   a  and  150   b  are formed on the source/drain regions  116   a  and  116   b  of the structure  100  of  FIG. 1G . 
         [0034]    Next, with reference to  FIG. 2G , in one embodiment, a silicon nitride layer  260  and a BPSG layer  270  are formed in turn on top of the structure  200  of  FIG. 2F . More specifically, the silicon nitride layer  260  and the BPSG layer  270  can be formed by (i) depositing silicon nitride on top of the structure  200  of  FIG. 2F  resulting in the silicon nitride layer  260  and then (ii) depositing BPSG on top of the silicon nitride layer  260  resulting in the BPSG layer  270 . 
         [0035]    Next, in one embodiment, a CMP process is performed on top of the structure  200  of  FIG. 2G  until the top surface  122  of the temporary gate electrode region  120  is exposed to the surrounding ambient resulting in the structure  200  of  FIG. 2H . After the CMP process is performed, what remain of the BPSG layer  270  are BPSG regions  270   a  and  270   b , and what remain of the silicon nitride layer  260  are silicon nitride regions  260   a  and  260   b.    
         [0036]    Next, with reference to  FIG. 2H , in one embodiment, the temporary gate electrode region  120  is removed resulting in a trench  224  of  FIG. 2I . The temporary gate electrode region  120  can be removed using a wet etching process. 
         [0037]    Next, with reference to  FIG. 2I , in one embodiment, the temporary gate dielectric region  212  is removed resulting in the top surface  118  of the silicon substrate  110  being exposed to the surrounding ambient, as shown in  FIG. 2J . The temporary gate dielectric region  212  can be removed by a conventional wet etching process. 
         [0038]    Next, with reference to  FIG. 2K , in one embodiment, a final gate dielectric layer  280  and a final gate electrode layer  290  are formed in turn on top of the structure  200  of  FIG. 2J . The final gate dielectric layer  280  can comprise a high-K dielectric material. For example, the final gate dielectric layer  280  comprises hafnium silicon oxynitride (HfSiON). The final gate electrode layer  290  can comprise a metal such as tantalum nitride (TaN). The final gate dielectric layer  280  and the final gate electrode layer  290  can be formed by (i) CVD or ALD (Atomic Layer Deposition) of the hafnium silicon oxynitride on top of the structure  200  of  FIG. 2K  resulting in the final gate dielectric layer  280  and then (ii) CVD or ALD of tantalum nitride on top of the final gate dielectric layer  280  such that the trench  224  is completely filed with tantalum nitride resulting in the final gate electrode layer  290 . 
         [0039]    Next, in one embodiment, a CMP process is performed on top of the structure  200  of  FIG. 2K  until the top surface  270 ′ of the BPSG regions  270   a  and  270   b  is exposed to the surrounding ambient resulting in the structure  200  of  FIG. 2L . After the CMP process is performed, what remain of the final gate dielectric layer  280  and the final gate electrode layer  290  are the final gate dielectric region  280  and the final gate electrode region  290 , respectively. In one embodiment, each of the gate dielectric corner regions  230   a  and  230   b  overlaps the final gate electrode region  290  in the direction  115 . 
         [0040]    Next, in one embodiment, interconnect layers (not shown) are formed on top of the structure  200  to provide electrical access to the source/drain regions  116   a  and  116   b  and the final gate electrode region  290 . 
         [0041]    With reference to  FIG. 2L , the structure  200  shows a transistor having the final gate electrode region  290 , the final gate dielectric region  280 , the source/drain regions  116   a  and  116   b  and the channel  119 . The presence of the gate dielectric corner regions  230   a  and  230   b  at corners of the final gate electrode region  290  increases the distances between the final gate electrode region  290  and the source/drain regions  116   a  and  116   b  and thereby helps reduce leakage currents between the final gate electrode region  290  and the source/drain regions  116   a  and  116   b  during the operation of the transistor. 
         [0042]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Classification (CPC): 7