Patent Abstract:
Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.

Full Description:
REFERENCE TO RELATED APPLICATION  
       [0001]     This application is related to U.S. Pat. No. 6,657,894, issued 2 Dec. 2003, entitled “Apparatus and Method for Programming Virtual Ground Nonvolatile Memory Cell Array Without Disturbing Adjacent Cells.” 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present technology relates to nonvolatile memory cells, and in particular to nonvolatile memory cells subject to the program disturb effect.  
         [0004]     2. Description of Related Art  
         [0005]     The program operation of a nonvolatile memory cell is complicated by the program disturb effect. Programming refers to adding charge to, or removing charge from, selected memory cells of a memory array, unlike the indiscriminate erase operation which resets typically an entire sector of memory cells to the same charge storage state. The invention encompasses both products and methods where programming refers to making the net charge stored in the charge trapping structure more negative or more positive, and products and methods where erasing refers to making the net charge stored in the charge trapping structure more negative or more positive. In the program disturb effect, programming of a selected cell leads to unwanted programming of unselected memory cells adjacent to the selected cell. In particular, the program disturb effect leads to unwanted programming of memory cells that are: 1) located in columns adjacent to the column including the selected cell and 2) connected to the selected row line (the word line providing a gate voltage to the selected cell). The integrity of the memory array is adversely affected by these problems.  
         [0006]     A prior approach of addressing the read disturb effect alleviated the conditions giving rise to the unwanted programming of unselected memory cells. Unselected memory cells are programmed because of an unwanted voltage difference across the bit lines connected to the unselected memory cells which are in the column adjacent to the column including the selected cell. For example, if a bit line voltage is raised to program a memory cell positioned on one side of the bit line, the program disturb effect tends to program the adjacent memory cell on the other side of the bit line as well. The unwanted programming of unselected memory cells is prevented by decreasing the magnitude of the unwanted voltage difference across the bit lines connected to the unselected memory cells which are in the column adjacent to the column including the selected cell. For example, of the two bit lines that are used for accessing the column adjacent to the column including the memory cell selected to be programmed, when a program voltage is applied to one of those two bit lines to program the selected memory cell, the voltage of the other bit line is changed to decrease the unwanted voltage difference.  
         [0007]     This prevention mechanism masks the underlying tendency towards the program disturb effect, but does not prevent the underlying tendency leading to the program disturb effect. Because the program disturb effect is an intrinsic effect of many programming mechanisms, it would be advantageous to somehow take advantage of the program disturb effect, rather than simply applying voltages to other bit lines for the sole purpose of counteracting the voltage conditions that give rise to the program disturb effect.  
       SUMMARY OF THE INVENTION  
       [0008]     Various embodiments of the present invention are directed to a nonvolatile memory and a method for programming the memory. Rather than applying voltage settings to the bit lines only to counteract the program disturb effect, various embodiments take advantage of the program disturb effect to program nonvolatile memory in units of at least two memory cells.  
         [0009]     A common architecture of a nonvolatile memory array arranges the memory cells in row and columns. Each of the memory cells includes a body; two current terminals in the body, a bottom dielectric, a charge trapping structure having parts corresponding to the each current terminal (and each part having a charge storage state), a top dielectric.  
         [0010]     Word lines control access to the row of the nonvolatile memory array. Each word line provides a gate voltage to the top dielectric of the memory cells in a particular row of memory cells. Bit lines access the columns of memory cells via the current terminals of the memory cells.  
         [0011]     At least three particular bit lines access memory cells are arranged with respect to the memory cells in at least two columns of the memory array as follows. A first bit line accesses a first current terminal of memory cells in the first column and the second column. A second bit line accesses a second current terminal of memory cells in the first column. A third bit line accesses the second current terminal of memory cells in is the second column. In this fashion, the first current terminals of adjacent memory cells in neighboring columns are accessed by a same bit line, and the second current terminals of these adjacent memory cells in neighboring columns are accessed by different bit lines.  
         [0012]     In one embodiment, the program command is to add charge to a memory cell in the first column and to a memory cell in the second column. A voltage is applied to the word line that supplies the gate voltage to at least the memory cell in the first column and to the memory cell in the second column. The gate voltage is sufficient to move energetic charge from the body of memory cells across the bottom dielectric into the charge trapping structure. For example, if energetic charge had been induced in the body of a memory cell by current mechanisms (for example, such as CHISEL, CHE, Fowler-Nordheim tunneling, band-to-band hot hole tunneling) then the gate voltage is sufficient to move this energetic charge. A voltage is applied to the first bit line, which accesses memory cells in at least the first column and second column to be programmed. This voltage is sufficient to induce the energetic charge (for example, via CHISEL, CHE, Fowler-Nordheim tunneling, band-to-band hot hole tunneling) in the bodies of memory cells that have at least a sufficient voltage difference between their current terminals. Finally, a voltage setting is applied to the second and third bit lines, which are the remaining bit lines that access memory cells in at least the first column and second column to be programmed. The voltage setting can cause the same voltage to be applied to the second and third bit lines for simplicity, or different voltages on the second and third bit lines for flexibility. This voltage setting causes at least a sufficient voltage difference between the current terminals of memory cells in at least the first column and the second column to induce the energetic charge (for example, via CHISEL, CHE, Fowler-Nordheim tunneling, band-to-band hot hole tunneling) in the bodies of memory cells in the memory cells. Because of this sufficient voltage difference and the successful inducement of energetic charge in the bodies of the memory cells, the gate voltage and the voltage applied to the first bit line add charge to the memory cells.  
         [0013]     In another embodiment, the program command is to not add charge to a memory cell in the first column and to a memory cell in the second column. Rather than applying voltage setting to the second and third bit lines that causes at least a sufficient voltage difference between the current terminals of memory cells in at least the first column and the second column to induce the energetic charge in the bodies of memory cells, the voltage setting causes an insufficient voltage difference between the current terminals of memory cells in the first column and the second column that fails to induce the energetic charge in the bodies of the memory cells. Because of this insufficient voltage difference and the failure to induce energetic charge in the bodies of the memory cells, the gate voltage and the voltage applied to the first bit line do not add charge to the memory cells.  
         [0014]     In another embodiment, the voltage setting is applied to the second and third bit lines depending on the program command as follows:  
         [0015]     A) if the program command is to add charge to the charge trapping structure of the memory cells in the first and second columns, applying the voltage setting to the second and third bit lines to cause at least the sufficient voltage difference between the current terminals of the memory cells to induce the energetic charge in the bodies of the first and second columns of memory cells;  
         [0016]     B) if the program command is to not add charge to the charge trapping structure of the memory cells in the first and second columns, applying the voltage setting to the second and third bit lines to cause an insufficient voltage difference between the current terminals failing to induce the energetic charge in the bodies of the first and second columns of memory cells;  
         [0017]     C) if the program command is to add charge to the charge trapping structure of at least one memory cell in the first column and not add charge to the charge trapping structure of at least one memory cell in the second column, applying the voltage setting to the second and third bit lines to cause: 1) at least the sufficient voltage difference between the current terminals of the first column of memory cells to induce the energetic charge in the bodies of the first column of memory cells and 2) the insufficient voltage difference between the current terminals of the second column of memory cells failing to induce the energetic charge in the bodies of the second column of memory cells; and  
         [0018]     D) if the program command is to not add charge to the charge trapping structure of at least one memory cell in the first column and add charge to the charge trapping structure of at least one memory cell in the second column, applying the voltage setting to the second and third bit lines to cause: 1) the insufficient voltage difference between the current terminals of the first column of memory cells failing to induce the energetic charge in the bodies of the first column of memory cells and 2) at least the sufficient voltage difference between the current terminals of the second column of memory cells to induce the energetic charge in the bodies of the second column of memory cells.  
         [0019]     Various embodiments cover the methods of programming the memory cell and the integrated circuit with the nonvolatile memory array.  
         [0020]     The invention covers not only the programming of just two memory cells at a time, but three or more as well. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]      FIG. 1  is a simplified diagram of a portion of an array of nonvolatile memory cells showing the addition of charge to neighboring cells.  
         [0022]      FIG. 2  is a simplified diagram of a portion of an array of nonvolatile memory cells not showing an addition of charge to neighboring cells.  
         [0023]      FIG. 3  is a simplified diagram of a portion of an array of nonvolatile memory cells that implements a decoded program instruction to add or not add charge to neighboring cells.  
         [0024]      FIG. 4  is a more detailed diagram of neighboring nonvolatile memory cells showing the addition of charge to the neighboring cells.  
         [0025]      FIG. 5  is a more detailed diagram of neighboring nonvolatile memory cells not showing the addition of charge to the neighboring cells.  
         [0026]      FIG. 6  is a simplified block diagram of a nonvolatile memory array with multi-cell programming according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0027]      FIG. 1  is a simplified diagram of a portion of an array of nonvolatile memory cells. Word line WL N−1    110  supplies a gate voltage of 0 V to the row of nonvolatile memory cells  120  and  121 . Word line WL N    112  supplies a gate voltage of −5 V to the row of nonvolatile memory cells  122  and  123 . Word line WL N+1    114  supplies a gate voltage of 0 V to the row of nonvolatile memory cells  124  and  125 . Bit line BL M    131  supplies a voltage of 5 V to a first current terminal of the first column of memory cells  120 ,  122 , and  124 , and to a first current terminal of the second column of memory cells  121 ,  123 , and  125 . Bit line BL M+1    132  supplies a voltage of 0 V to a second current terminal of the first column of memory cells  120 ,  122 , and  124 . Bit line BL M−1    130  supplies a voltage of 0 V to a second current terminal of the second column of memory cells  121 ,  123 , and  125 . The charge storage state of the charge storage structure of nonvolatile memory cells  122  and  123  are programmed. The charge storage state of the charge storage structure of nonvolatile memory cells  120 ,  121 ,  124 , and  126  are not programmed because of gate voltage that is insufficient to move energetic charge in the bodies of the nonvolatile memory cells across the bottom dielectric into the charge trapping structure. The charge trapping structure of each of the nonvolatile memory cells  120 ,  121 ,  122 ,  123 ,  124 , and  125  has parts corresponding to the different current terminals. In nonvolatile memory cells  122  and  123 , the charge is added to the charge trapping structure via band-to-band hot holes. More specifically, the charge trapping structure by the bit line BL M    131  has charge added. This type of programming has the advantage of speed, by simultaneously programming nonvolatile memory cells  122  and  123 .  
         [0028]      FIG. 2  is a simplified diagram of a portion of an array of nonvolatile memory cells. In  FIG. 2 , bit line BL M+1    132  supplies a voltage of 3 V to a second current terminal of the first column of memory cells  120 ,  122 , and  124 . Bit line BL M−1    130  supplies a voltage of 3 V to a second current terminal of the second column of memory cells  121 ,  123 , and  125 . Despite the gate voltage that is insufficient to move energetic charge in the bodies of the nonvolatile memory cells  122  and  123  across the bottom dielectric into the charge trapping structure, nonvolatile memory cells  122  and  123  are not programmed. Nonvolatile memory cells  122  and  123  are not programmed because the voltage difference between bit line BL M+1    132  and bit line BL M    131  is too small for the column of nonvolatile memory cells  120 ,  122 , and  124 ; and the voltage difference between bit line BL M−1    130  and bit line BL M    131  is too small for the column of nonvolatile memory cells  121 ,  123 , and  125 . The voltage difference between the bit line pairs is insufficient to induce energetic charge to the bodies of the memory cells. This type of programming has the advantage of maintaining a bias on bit line BL M    131  that is sufficient to induce energetic charge in the body of a nonvolatile memory cell if the other bit line of the memory cell is grounded, but programs neither nonvolatile memory cell  122  nor nonvolatile memory cell  123 .  
         [0029]      FIG. 3  is a simplified diagram of a portion of an array of nonvolatile memory cells. Word line WL N−1    110  supplies a gate voltage of V N−1  to the row of nonvolatile memory cells  120  and  121 . Word line WL N    112  supplies a gate voltage of V N  to the row of nonvolatile memory cells  122  and  123 . Word line WL N+1    114  supplies a gate voltage of V N+1  to the row of nonvolatile memory cells  124  and  125 . Bit line BL M    131  supplies a voltage of V M  to a first current terminal of the first column of memory cells  120 ,  122 , and  124 , and to a first current terminal of the second column of memory cells  121 ,  123 , and  125 . Bit line BL M+1    132  supplies a voltage of V M+1  to a second current terminal of the first column of memory cells  120 ,  122 , and  124 . Bit line BL M−1    130  supplies a voltage of V M−1  to a second current terminal of the second column of memory cells  121 ,  123 , and  125 .  
         [0030]     The nonvolatile memory array of  FIG. 3  applies the voltages and voltage settings for the voltages V N−1 , V N , V N+1 , V M+1 , V M , V M−1  as follows:  
                                                           Add charge to charge   Add charge to charge trapping                               trapping structure part   structure part of cell 123 by       of cell 122 by bit line   other bit line       BL M     BL M+1 /BL M−1     V M+1     V M     V M−1     V N−1     V N     V N+1                     Yes   Yes   0 V   5 V   0 V   0 V   −5 V   0 V       Yes   No   0 V   5 V   3 V   0 V   −5 V   0 V       No   Yes   3 V   5 V   0 V   0 V   −5 V   0 V       No   No   3 V   5 V   3 V   0 V   −5 V   0 V               0 V   0 V   0 V   0 V   −5 V   0 V                  
 
         [0031]      FIG. 4  is a simplified diagram of two charge trapping memory cells sharing a word line and a bit line, showing a program operation being performed on the part of the charge trapping structure of each nonvolatile cell by the shared bit line. The p-doped substrate region  490  or  491  includes n+ doped current terminals  450 ,  460 , and  470 . n+ doped current terminal  460  is the first current terminal of both memory cells. The remainder of the first memory cell includes a bottom dielectric structure  440  on the substrate, a charge trapping structure  430  on the bottom dielectric structure  440  (bottom oxide), a top dielectric structure  420  (top oxide) on the charge trapping structure  430 , and a gate  410  on the oxide structure  420 . The remainder of the second memory cell includes a bottom dielectric structure  441  on the substrate, a charge trapping structure  431  on the bottom dielectric structure  441  (bottom oxide), a top dielectric structure  421  (top oxide) on the charge trapping structure  431 , and a gate  410  on the oxide structure  421 . The gate  410  is actually a word line providing a gate voltage to the oxide structure  420  of the first memory cell and the oxide structure  420  of the second memory cell. Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al 2 O 3 . Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al 2 O 3 , HfO 2 , and others. The charge trapping structure may be a discontinuous set of pockets or particles of charge trapping material, or a continuous layer as shown in the drawing.  
         [0032]     The memory cell for PHINES-like cells has, for example, a bottom oxide with a thickness ranging from 2 nanometers to 10 nanometers, a charge trapping layer with a thickness ranging from 2 nanometers to 10 nanometers, and a top oxide with a thickness ranging from 2 nanometers to 15 nanometers.  
         [0033]     In some embodiments, the gate comprises a material having a work function greater than the intrinsic work function of n-type silicon, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including for example greater than about 5 eV. Representative gate materials include p-type poly, TiN, Pt, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to Ru, Ir, Ni, and Co, metal alloys including but not limited to Ru—Ti and Ni-T, metal nitrides, and metal oxides including but not limited to RuO2. High work function gate materials result in higher injection barriers for electron tunneling than that of the typical n-type polysilicon gate. The injection barrier for n-type polysilicon gates with silicon dioxide as the top dielectric is around 3.15 eV. Thus, embodiments of the present technology use materials for the gate and for the top dielectric having an injection barrier higher than about 3.15 eV, such as higher than about 3.4 eV, and preferably higher than about 4 eV. For p-type polysilicon gates with silicon dioxide top dielectrics, the injection barrier is about 4.25 eV, and the resulting threshold of a converged cell is reduced about 2 volts relative to a cell having an n-type polysilicon gate with a silicon dioxide top dielectric.  
         [0034]     In the diagram of  FIG. 4 , the charge trapping structure part of each cell by the current terminal  460  of each memory cell has been programmed, for example via band-to-band hot hole injection of holes  435  and  436  into the charge trapping structures  430  and  431 , respectively. Other program and erase techniques can be used in operation algorithms applied to the PHINES-type memory cell, as described for example in U.S. Pat. No. 6,690,601. Other memory cells and other operation algorithms might also be used.  
         [0035]      FIG. 5  is a simplified diagram of two charge trapping memory cells sharing a word line and a bit line. The voltage setting is changed in that neither of the memory cells is programmed. Even with a bias on bit line  460  that is sufficient to induce energetic charge in the bodies  490  and  491  of the nonvolatile memory cells with a corresponding voltage on the other bit line, the other bit line  450  and  470  has a voltage which causes an insufficient voltage difference between the bit line pairs that fails to induce energetic charge in the bodies  490  and  491  of the nonvolatile memory cells.  
         [0036]      FIG. 6  is a simplified block diagram of an integrated circuit according to an embodiment. The integrated circuit  660  includes a memory array  600  implemented using charge trapping memory cells, on a semiconductor substrate. A row decoder  601  is coupled to a plurality of word lines  602  arranged along rows in the memory array  600 . A column decoder  603  is coupled to a plurality of bit lines  604  arranged along columns in the memory array  600 . Addresses are supplied on bus  670  to column decoder  603  and row decoder  601 . Sense amplifiers and data-in structures in block  606  are coupled to the column decoder  603  via data bus  607 . Data is supplied via the data-in line  611  from input/output ports on the integrated circuit  660 , or from other data sources internal or external to the integrated circuit  660 , to the data-in structures in block  606 . Data is supplied via the data-out line  610  from the sense amplifiers in block  606  to input/output ports on the integrated circuit  660 , or to other data destinations internal or external to the integrated circuit  660 . A bias arrangement state machine  609  controls the application of bias arrangement supply voltages  608 , such as for the erase verify and program verify voltages, and the arrangements for programming multiple selected cells, erasing, and reading the memory cells.  
         [0037]     While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. What is claimed is:

Technology Classification (CPC): 6