Patent Abstract:
A method and system for converting a plurality of input signals being indicative of a signal to be converted to a digital output including: setting a plurality of codes each being indicative of a corresponding reference level; and, for each one of the codes, converting the one code to a first analog signal, and summing the first analog signal with a first of the input signals to provide a first summed signal; complementing the one code to provide a complemented code, converting the complemented code to a second analog signal; summing the second analog signal with a second of the input signals to provide a second summed signal corresponding to the first summed signal. The corresponding first and second summed signals are compared to provide a comparison signal. At least a portion of the digital output is set according to the comparison signal.

Full Description:
FIELD OF INVENTION  
         [0001]    The present invention relates to analog-to-digital converters in general, and to differential analog-to-digital converters in particular.  
         BACKGROUND OF INVENTION  
         [0002]    The usefulness of Analog-to-Digital Converters (ADCs) is well known. One type of ADC is known as a Successive Approximation (SSA) ADC. An SSA ADC uses a Digital-to-Analog Converter (DAC) in a feedback loop, in combination with a comparator and Successive Approximation Register (SAR). An SSA ADC first sets a Most Significant Bit (MSB) using the SAR. The comparator then compares the analog input to be converted with the DAC feedback to determine whether the input is larger or smaller than ½ the full scale reference voltage. If the input voltage is greater than ½ the reference voltage the MSB is left unchanged, otherwise it is reset to the opposite state. The analog input voltage is then reduced by the compared ½reference voltage and compared with ½ 2 , or ¼, the reference voltage to set the next MSB. The process is continued until a desired Least Significant Bit (LSB) is set.  
           [0003]    Traditional SSA ADCs are undesirably prone to introducing errors though, due to the inclusion of both a comparator and DAC. To address this shortcoming, differential SSA ADCs have been proposed wherein two differential inputs are provided. However, many conventional Differential SSA ADCs are relatively costly and complicated in nature. It is an object of the present invention to provide a simplfied differential SSA ADC.  
         SUMMARY OF INVENTION  
         [0004]    A method for converting a plurality of input signals being indicative of a signal to be converted to a digital output including: setting a plurality of codes each being indicative of a corresponding reference level; and, for each one of the codes, converting the one code to a first analog signal, and summing the first analog signal with a first of the input signals to provide a first summed signal; complementing the one code to provide a complemented code, converting the complemented code to a second analog signal, and summing the second analog signal with a second of the input signals to provide a second summed signal corresponding to the first summed signal; comparing the corresponding first and second summed signals to provide a comparison signal; and, setting at least a portion of the digital output according to the comparison signal. 
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0005]    [0005]FIG. 1 illustrates a block diagram for a differential input analog-to-digital converter according to one aspect of the invention;  
         [0006]    [0006]FIG. 2 illustrates a block diagram of a differential input analog-to-digital converter according to another aspect of the invention;  
         [0007]    [0007]FIG. 3 illustrates a block diagram of a successive approximation analog-to-digital converter according to yet another aspect of the present invention;  
         [0008]    [0008]FIG. 4 illustrates a block diagram of a successive approximation analog-to-digital converter according to yet another aspect of the present invention;  
         [0009]    [0009]FIG. 5 illustrates a block diagram of a successive approximation analog-to-digital converter according to yet another aspect of the present invention;  
         [0010]    [0010]FIG. 6 illustrates a block diagram of a successive approximation analog-to-digital converter according to yet another aspect of the present invention;  
         [0011]    [0011]FIGS. 7A and 7B illustrate diagrams of circuits suitable for use as the digital-to-analog converter DA 1  of FIG. 6 according to an aspect of the present invention;  
         [0012]    [0012]FIGS. 8A and 8B illustrate diagrams of circuits suitable for use as the digital-to-analog converter DA 2  of FIG. 6 according to an aspect of the present invention;  
         [0013]    [0013]FIGS. 9A and 9B illustrate diagrams of alternative circuits suitable for use as the digital-to-analog converter DA 2  of FIG. 6 according to another aspect of the present invention;  
         [0014]    [0014]FIG. 10A illustrates a diagram of circuit suitable for use as the digital-to-analog converter DA 3  of FIG. 6 according to an aspect of the present invention;  
         [0015]    [0015]FIG. 10B illustrates a diagram of a circuit suitable for use as the digital-to-analog converter DA 4  of FIG. 6 according to an aspect of the present invention; and,  
         [0016]    [0016]FIG. 11 illustrates a diagram of a circuit suitable for use as the resistor ladder of FIG. 6 according to an aspect of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0017]    In a single input Analog-to-Digital Converter (ADC), a comparator compares an input signal (V in ) and a Digital-to-Analog Converter (DAC) output indicative of a reference level to decode digital outputs. In an N-bit Successive Approximation ADC (SSA), the comparator firstly compares V in  with a first fixed voltage, such as ½ the Full Scale voltage (FS), to determine a first Most Significant Bit (MSB) to be output a (N-1) , secondly compares V in −½(a (N-1) )FS with ¼ FS to determine a second MSB a (N-2) , and so on until comparing V in −½ (N-1) (a (N-1) )FS, where I is from 1 to (N-1), to decide a Least Significant Bit (LSB) a (0) .  
         [0018]    For differential SSA ADC&#39;s, two input signals are provided, V in+  and V in− . The relationship between these inputs is characterized by V in− =FS−V in+ . If the full scale value is normalized for sake of discussion, then V in− =1−V in+ . In the case of analog-to-digital conversion, each input signal subtracts with a digital-to-analog feedback signal to enable the comparator to determine the decoded digital output. Assuming DA (+)  is a digital-to-analog feedback signal corresponding to the V in+  input and DA (−)  is a digital-to-analog feedback signal corresponding to the V in−  input, the inputs to the comparator take the form of V in+ −DA (+)  and V in− −DA (−) . The present invention takes advantage of the following determined relationship between DA (+)  and DA (−) .  
         [0019]    Referring now to the Figures, like references identify like elements of the invention. FIG. 1 illustrates a block diagram of a differential input SSA ADC  5  according to one aspect of the invention. Generally, the ADC  5  includes: a comparator  10  including a (+) input  12 , (−) input  14  and output  16 ; a (+) input  20  for receiving V in+  and a (−) input  30  for receiving V in− . Coupled to the output  16  is a Successive Approximation Register (SAR)  40 . Coupled to an output of the SAR  40  are digital outputs  50  and Digital-to-Analog Converters (DACs)  60 ,  70 . A (+) summing circuit or summer  80  includes a (+) input  82 , a (−) input  84  and an output  86 . The input  82  is coupled to input  20 , while input  84  is coupled to output of DAC  60  and output  86  is coupled to comparator  10  input  12 . A (−) summing circuit or summer  90  includes a (+) input  92 , a (−) input  94  and an output  96 . The input  92  is coupled to input  30 , while input  94  is coupled to an output of DAC  70  and output  96  is coupled to comparator  10  input  14 . The DAC  60  produces the DA (+)  signal while the DAC  70  produces the DA (−)  signal. Hence, comparator  10  input  12  receives V in+ −DA (+)  and comparator  10  input  14  receives V in− −DA (−) . DA (+)  and DA (−)  normalized with digital codes and voltage amplitude such that in the analog domain they do not exceed 1 in normal operation.  
         [0020]    The ADC  5  receives the differential signals V in+  and V in−  at the inputs  20 ,  30 , i.e.  
           V   in+ − DA   (+)   =−[V   in−   −DA   (−) ]  (1)  
         [0021]    By substituting: V in+ +V in− =1 into Eq.  1 , due to normalization, DA (−) =[1−DA (+) ]=[FS−DA (+) ] in the analog domain, or,  
           DA   (−) =2&#39;s complement of  DA   (+) , in the digital domain.  (2)  
         [0022]    In the digital domain, for an N-bit ADC,  
                       DA     (   +   )       =                    a     (     N   -   1     )            1   2       +       a     (     N   -   2     )            1   4       +       a     (     N   -   3     )            1   8       +   …   +         a     (   1   )            (     1   2     )         N   -   1       +                                    a     (   0   )            (     1   2     )       N     ,                  
        or                   
            1   =       [       1   2     +     1   4     +     1   8     +     1   16     +   …   +       (     1   2     )       N   -   1       +       (     1   2     )     N       ]     +       (     1   2     )     N         ,     
          where                   a     (   1   )                     can                 be                 0                 or                 1     ,   so                                     DA     (   -   )       =                1   -     DA     (   +   )                     =                1   -     {         a     (     N   -   1     )            1   2       +       a     (     N   -   2     )            1   4       +       a     (     N   -   3     )            1   8       +   …   +                                          a     (   1   )            (     1   2     )         N   -   1       +         a     (   0   )            (     1   2     )       N       }                 =                    [     1   -     a     (     N   -   1     )         ]          1   2       +       [     1   -     a     (     N   -   2     )         ]          1   4       +       [     1   -     a     (     N   -   3     )         ]          1   8       +   …   +                                  [     1   -     a     (   1   )         ]            (     1   2     )       N   -   1         +       [     1   -     a     (   0   )         ]            (     1   2     )     N       +       (     1   2     )     N                   =                  [inverse  of         DA     (   +   )       ]       +       (     1   2     )     N                     (   3   )                               
 
         [0023]    Thus, for a case as DA (+) =0000 0000 0000 0000, the lowest possible voltage in a 12-bit ADC, DA (−) =1111 1111 1111 1111+0000 0000 0000 0001=1 0000 0000 0000 0000, the highest full range voltage, remembering that the 2&#39;s complement of a binary number N=(1&#39;s complement of N)+1 LSB . And, for a case where DA (+) =1111 1111 1111 1111, the highest code which is one LSB below the full voltage range in a 12-bit ADC, DA (−) =0000 0000 0000 0001, one LSB above the lowest voltage.  
         [0024]    Thus in any N-bit ADC according to the present invention, using Eq. 2, the ADC circuit of FIG. 1 can be realized as is illustrated in FIG. 2 using a simple 2&#39;s complementary conversion circuit at the output of SAR  40  in combination with DAC  70  to provide the DA (−)  signal according to an aspect of the present invention. Referring now also to FIG. 2, there is shown a block diagram for a differential input SSA ADC  100  according to an aspect of the invention.  
         [0025]    Still referring to FIG. 2, there is shown the ADC of FIG. 1 now also illustrating a 2&#39;s complementary conversion circuit  110  coupled between the SAR  40  and DAC  70 . Thus, DA (−)  which is the 2&#39;s complement of DA (+) , is provided as an input to the DAC  70 . The 2&#39;s complementary circuit  110  has a carry out bit as the MSB, i.e. is has (N+1) bits.  
         [0026]    The relationship between DA (+)  and DA (−)  in Eq. 2 is valid for differential ADC&#39;s using different types of digital-to-analog conversion schemes. According to another aspect of the present invention, the digital codes supplied at the output of the SAR  40  are decomposed into groups of DACs and then summed through a network of ratio capacitors and resistor ladders to achieve a correct weighting for the individual components and analog voltage level. Referring now also to FIG. 3, there is shown a 10-bit SSA ADC  200  block diagram according to an aspect of the present invention. Like elements to those described with reference to the previous figures will not be again described. The ADC  200  illustrated therein uses pseudo differential inputs V IN 20 and V   INR    30 ′, where V IN    20  is a real analog input signal to be converted and V INR    30 ′ is a DC or zero value at the lowest analog input voltage.  
         [0027]    Referring still to FIG. 3, the DAC  60  is decomposed into four (4) smaller DACs  62 : DA 1 , DA 2 , DA 3  and DA 4 . DA 1  processes four bits, DA 2  processes four bits plus one offset bit, DA 3  processes 1 bit and DA 4  processes 1 bit according to another aspect of the invention. Further, adder  210  is interposed between SAR  40  and digital outputs  50 .  
         [0028]    Referring now to FIG. 4, there is shown a 10-bit SSA ADC  220  according to another aspect of the present invention. Again, like elements to those described with reference to the previous figures will not be again described. Separate decoding circuits  62  and  72 ″ are provided for the differential inputs  20 ,  30 , respectively. DA (+)  is again decomposed into four DACs  62 : DA 1(+) , DA 2(+) , DA 3(+)  and DA 4(+) , analogously to the SSA  200  of FIG. 3. DA (−)  is also decomposed into four DACs  72 : DA 1(−) , DA 2(−) , DA 3(−)  and DA 4(−) . Again, DA (−)  is the  2 &#39;s complementary input of DA (+) (See EQ.2).  
         [0029]    Still referring to FIG. 4, an offset bit D 4S  is added to DA (+) , such that DA′ (+) =DA (+) +D 4S . Equation (2) remains applicable, such that DA′ (−) =1−DA′ (+) =1−[DA (+) +D 4S ]=[1−DA (+) ]−D 4S . DA 1(+)  is a four bit decoder, DA 2(+)  is a five bit decoder, while DA 3(+)  and DA 4(+)  are one bit decoders. DA 1(+)  receives the four MSBs: D 9 , D 8 , D 7 , D 6  output from SAR  40 . DA 2(+)  receives the next four MSBs: D 5 , D 4 , D 3 , D 2  and the offset bit D 4S  output from SAR  40 . DA 3(+)  receives the second LSB D 1 , while DA 4(+)  receives the LSB D 0  output from SAR  40 . DA 1(−)  is a 5 bit decoder, DA 2(−)  is a 4 bit decoder, while DA 3(−)  and DA 4(−)  are one bit decoders. DA 1(−)  receives the four MSBs: D 9 , D 8 , D 7 , D 6  and bit D 10  output from SAR  40 . DA 2(−)  receives the next four MSBs: D 5 , D 4 , D 3 , D 2  output from SAR  40 . DA 3(−)  receives the second LSB D 1 , while DA 4(−)  receives the LSB D 0  output from SAR  40 . Adder  210  serves to account for offset bit D 4S  being parsed from the output of SAR  40 .  
         [0030]    Referring now to FIG. 5, there is shown an SSA ADC  230  according to yet another aspect of the present invention. Again, like elements to those described with reference to the previous figures will not be again described. A single decoder circuit is used therein for driving the DA (+)  and DA (−)  DACs  62 ,  72 . Basically, the DA (+)  DAC is decomposed into four DACs  62 : DA 1(+) , DA 2(+) , DA 3(+)  and DA 4(+)    62 ′. In mathematical expression this yields:  
           DA   (+) =( a   9   ,a   8   ,a   7   ,a   6 ,0,0,0,0,0,0)+(0,0,0,0 , a   5   ,a   4   ,a   3   ,a   2 ,0,0)+(0,0,0,0,0,0,0,0, a   1 ,0)+(0,0,0,0,0,0,0,0,0 , a   0 )  
         = GP   1(+)   +GP   2(+)   +GP   3(+)   +GP   4(+)    
         [0031]    The 2&#39;s complement of DA (+)  is DA (−)  (See EQ.2), and DA (−)   =1−DA   (+) . Hence,  
           DA(−)=( 1 −a   9 ,1 −a   8 ,1 −a   7 ,1 −a   6 ,0,0,0,0,0,0)+(0,0,0,0,1−a 5 ,1 −a   4 ,1 −a   3 ,1 −a   2 ,0,0)+(0,0,0,0,0,0,0,0,1 −a   1 ,0)+(0,0,0,0,0,0,0,0,0,1 −a   0 )+(0,0,0,0,0,0,0,0,0,1)  (4)  
         = GP   1(−)   +GP   2(−)   +GP   3(−)   +GP   4(−)    
         [0032]    Where a 0 =0, GP 4(−) =(0,0,0,0,0,0,0,0,1,0). So, GP 4(31 )  has a range of (0,0,0,0,0,0,0,0,0,1) to (0,0,0,0,0,0,0,0,1,0). In the DA 4  decoder, the a 0  =0 selects V=0 for DA 4(+)  and V=V 4 (1,0) for DA 4(−) . Further, a 0 =1 selects V=V 4 (0,1) for DA 4 (+) and DA 4 (−). Thus, the same decoder can be used for both DA 4 (+) and DA 4 (−). It should be noted that V 4 (1,0) is twice the value of V 4 (0,1), and V 4 (0,0) is 0V. Further, in this case V 4 (0,1) is {fraction (1/1024)} the full voltage range of the ADC.  
         [0033]    Where a 0 =0 and a 1 =0, GP 3(−) =(0,0,0,0,0,0,0,1,0,0). Where a 0 =0, a 1 =1, GP 3(−) =(0,0,0,0,0,0,0,0,1,0). Accordingly, GP 3(−)  ranges from (0,0,0,0,0,0,0,0,1,0) to (0,0,0,0,0,0,0,1,0,0). In the DA 3  decoder, the a 1 =0 selects V=0 for DA 3(+)  and V=V 3 (1,0) for DA 3(−) ; while a 1 =1 selects V=V 3 (0,1) for DA 3(+)  and DA 3(−) . Thus, a same decoder can be used for both DA 3(+)  and DA 3 (−). V 3 (1,0) is twice V 3 (0,1), and V 3 (0,0) is 0V and V 3 (0,1) is {fraction (1/512)} the full voltage range of the ADC.  
         [0034]    Where a 0 =a 1 =0, and a 2 =a 3 =a 4 =a 5 =0, GP 2(−) =(0,0,0,1,0,0,0,0,0,0). Where a 0 =0, a 1 =0, and a 2 =a 3 =a 4 =a 5 =1, GP 2(−)=( 0,0,0,0,0,0,0,1,0,0). Hence, GP 2(−)  ranges from (0,0,0,0,0,0,0,1,0,0) to (0,0,0,1,0,0,0,0,0,0). As DA 2  is a four bit decoder, at a 2 =a 3 =a 4 =a 5 =0, the decoded output selects V=0 for DA 2(+)  and V=V 2 (1,0,0,0,0) for DA 2(−) . While at a 2 =a 3 =a 4 =a 5 =1, the decoded output selects V=V 2 (1,1,1,1) for DA 2 (+) and V=V 2 (0,0,0,1) for DA 2(−) . Thus, a same decoder can be used for both DA 2(+)  and DA 2(−) . V 2 (1,0,0,0,0) is 16 times the value of V 2 (0,0,0,1). V 2 (1,1,1,1) is 15 times the value of V 2 (0,0,0,1), and V 2 (0,0,0,0) is 0V. V 2 (0,0,0,1) is {fraction (1/256)} the full scale voltage range of the ADC.  
         [0035]    It should be noted that when an offset bit a 4S  is added into DA 2(+) , the carry bit from this summation does not change the original DA 1(+) , So, the new DA 2′(+)  has the same maximum value of (1,0,0,1,1) if a 4S =(0,1,0,0). The new range of new DA 2′(+)  in this particular case is (1,0,1,0,0) instead of (1,0,0,0,0). Hence,  
           DA   2′(−) =[(1,0,1,0,0)− DA   2(+)   −a   4S ] 
         =[(1,0,0,0,0)− DA   2(+) ]+(0,0,0,0)− a   4S   
         = DA   2(−) +(0,1,0,0)− a   4S ,  
         [0036]    where  a   4S  is a simplified expression for (0 ,a   4S , 0,0).  
         [0037]    Thus, where a 4S =(0,1,0,0), DA 2′(−) =DA 2(−) , DA 2′(+) =DA 2(+) +(0,1,0,0). And, where a 4S =(0,0,0,0), DA 2′(−) =DA 2(−) +(0,1,0,0), and DA 2′(+) =DA 2(+) . Thus, a decoding circuit used in connection with DA 2(+)  with an offset bit can be used for DA 2′(+)  and DA 2′(−)  as well. In this case, the decoded output of (0,0,0,0) in DA 2′(+)  selects V=0, and selects V=V 2 (1,0,1,0,0) in DA 2′(−) . The decoded output of (1,0,0,1,1) selects V=V 2 (1,0,0,1,1) for DA 2′(+)  and selects V=V 2 (0,0,0,1) for DA 2′(−) . V 2 (1,0,1,0,0) is 20 times the value of V 2 (0,0,0,1). V 2 (1,0,0,1,1) is 19 times the value of V 2 (0,0,0,1) and V 2 (0,0,0,0) is 0V. V 2 (0,0,0,1) is {fraction (1/256)} the full scale voltage range of the ADC.  
         [0038]    Where a0=a1=a2=a3=a4=a5=0, and a6=a7=a8=a9=0, GP1(−)=(1,1,1,1,1,1,1,1,1,1)+(0,0,0,0,0,0,0,0,0,1)=(1,0,0,0,0,0,0,0,0,0,0), an 11-bit code. Where a0=a1=a2=a3=a4=a5=0 and a6=a7=a8=a9=1, GP1(−)=(0,0,0,1,0,0,0,0,0,0). Accordingly, Gp1(−) ranges from (0,0,0,1,0,0,0,0,0,0) to (1,0,0,0,0,0,0,0,0,0,0). DA 1  uses a four-bit decoder, where a6=a7=a8=a9=0 the decoded output selects V=0 for DA 1 (+) and V=V 1 (1,0,0,0,0) for DA 1 (−). Where a6=a7=a8=a9=1, the decoded output selects V=V 1 (1,1,1,1) for DA 1 (+) and V=V 1 (0,0,0,1) for DA 1 (−). Thus, a same decoder can be used for both DA 1 (+) and DA 1 (−). V 1 (1,0,0,0,0) is {fraction (1/16)} the full scale voltage range of the ADC.  
         [0039]    Referring now also to FIG. 6, there is shown a 10-bit SSA ADC  250  according to yet another aspect of the present invention. Again, the ADC  250  generally includes comparator  10 , (+) differential analog input  20 , (−)differential analog input  30 , SAR  40 , adder  210  and digital outputs  50 . In response to the comparator  10 , SAR  40  provides a 10-bit digital code, having an MSB D 9 , LSB D 0  and offset bit D 4S . Digital-to-analog conversion is performed by four DACs  62 : DA 1 , DA 2, DA   3 and DA   4 . DA 1(+)  provides DA 1(+)  and DA 1(−)  using the four MSBs supplied by the SAR  40 , i.e. D 9 , D 8 , D 7  and D 6 . DA 2  provides DA 2(+)  and DA 2(−)  using the next four MSBs supplied by the SAR  40 , i.e. D 5 , D 4 , D 3  and D 2 , and the offset bit D 4S . DA 3  and DA 4  provide DA 3(+) , DA 3(−)  and DA 4(+)  and DA 4(−)  using the two LSBs supplied by the SAR  40 , i.e. D 1 , D 0 . A resistor ladder  260  is provided and uses a reference voltage V LHF  and span voltage V RHF  to supply a plurality of voltages Va (0-16)  and Vb (0-20)  as will be described in greater detail with regard to FIG. 11. Still referring to FIG. 6, capacitors  252  serve to appropriately weight DA 1(+) , DA 2(+) , DA 3(+) , DA 4(+) , DA 1(−) , DA 2(−) , DA 3(−)  and DA 4(−)  as they are supplied to the comparator  10 . In the illustrated 10-bit SSA ADC of FIG. 6, if the capacitors  252  corresponding to DA 3(+) , DA 4(+) , DA 3(−)  and DA 4(−)  have a given capacitance C, the capacitors  252  corresponding to DA 2(+)  and DA 2(−)  should each have a capacitance fours time the given value, or 4C while the capacitors  252  corresponding to DA 1(+)  and DA 1(−)  should each have a capacitance eight times the given value of 8C.  
         [0040]    Referring now to FIG. 7A also, there is shown a circuit  255  for generating DA (1+) . Generally, the circuit  255  includes a 4-to-16 decoder  270  which receives the four MSBs provided by the SAR  40  (FIG. 6), i.e. D 9 , D 8 , D 7  and D 6  and provides 16 pairs of outputs, T (0-15) , TN (0-15)  in response thereto. The circuit  255  further includes a plurality of switches  256  responsive to the pairs of signals T and TN output from the 4-16 decoder  270  to supply corresponding ones of supplied voltages Va 0 -Va 16  as DA 1(+) . The following Table-1 illustrates which of the voltages Va (0-15)  are provided responsively to T (0-15)  and TN (0-15)  by the switches  256 .  
                                           TABLE 1                           DA 1(+)              Va (0-15)     T (0-15)     TN (0-15)                      0   0   0       1   1   1       2   2   2       3   3   3       4   4   4       5   5   5       6   6   6       7   7   7       8   8   8       9   9   9       10   10   10       11   11   11       12   12   12       13   13   13       14   14   14       15   15   15                  
 
         [0041]    Thus, a first switch  256 ′, uses signals T (0)  and TN (0)  to selectively supply voltage Va (0)  as DA 1(+) .  
         [0042]    Referring now also to FIG. 7B, there is shown a circuit  280  for generating signal DA 1(−) . The circuit  280  includes a plurality of switches  285  also responsive to the pairs of signals T and TN output from the 4-16 decoder  270  (FIG. 7A) to supply corresponding ones of voltages Va 0 -Va 16  as DA 1(−) . The following Table-2 illustrates which of voltages Va (0-15)  are provided responsively to T (0-15)  and TN (0-15)  by the switches  285 .  
                                           TABLE 2                           DA 1(−)              Va (0-15)     T (0-15)     TN (0-15)                      1   15   15       2   14   14       3   13   13       4   12   12       5   11   11       6   10   10       7   9   9       8   8   8       9   7   7       10   6   6       11   5   5       12   4   4       13   3   3       14   2   2       15   1   1       16   0   0                  
 
         [0043]    Thus one of the switches  280 ′, uses signals T (0)  and TN (0)  to selectively supply voltage Va (16)  as signal DA 1(−) .  
         [0044]    Referring now to FIG. 8A, there is shown a circuit  290  for generating DA 2(+) . Generally, circuit  290  includes a 5-to-20 decoder  300  which receives the four next MSBs provided by the SAR  40  (FIG. 6), i.e. D 5 , D 4 , D 3  and D 2 , as well as the offset bit D 4S , and provides 20 pairs of outputs, T (0-19) , TN (0-19) . The circuit  290  includes a plurality of switches  295  responsive to these pairs of signals T and TN output from the 5-20 decoder  300  to supply corresponding ones of voltages Vb 0 -Vb 19  as DA 2(+) . The following Table-3 illustrates which of voltages Vb (0-20) , are provided responsively to T (0—19)  and TN (0-19)  by the switches  295 .  
                                           TABLE 3                           DA 2(+)              Vb (0-19)     T (0-19)     TN (0-19)                      0   0   0       1   1   1       2   2   2       3   3   3       4   4   4       5   5   5       6   6   6       7   7   7       8   8   8       9   9   9       10   10   10       11   11   11       12   12   12       13   13   13       14   14   14       15   15   15       16   16   16       17   17   17       18   18   18       19   19   19                  
 
         [0045]    Thus, a first switch  295 ′ uses signals T (0)  and TN (0)  to selectively supply voltage Vb (0)  as DA 2(′) .  
         [0046]    Referring now to FIG. 8B, there is shown a circuit  310  for generating DA 2(−) . Generally, the circuit  310  includes a plurality of switches  315  responsive to these pairs of signals T and TN output from the 5-20 decoder  300  to supply corresponding ones of voltages Vb 0 -Vb 20  as DA 2(−) . The following Table-4 illustrates which of voltages Vb (0-19)  are provided as DA 2(−)  responsively to T (0-19 )  and TN (0-19)  by the switches  315 .  
                                           TABLE 4                           DA 2(−)              Vb (0-20)     T (0-19)     TN (0-19)                      1   19   19       2   18   18       3   17   17       4   16   16       5   15   15       6   14   14       7   13   13       8   12   12       9   11   11       10   10   10       11   9   9       12   8   8       13   7   7       14   6   6       15   5   5       16   4   4       17   3   3       18   2   2       19   1   1       20   0   0                  
 
         [0047]    Thus, a switch  315 ′ uses signals T (0)  and TN (0)  to selectively supply voltage Vb (20) .  
         [0048]    Referring now to FIGS. 9A and 9B, therein is illustrated circuits  290 ′ and  310 ′ according to another aspect of the present invention. Therein a 5-20 decoder  300 ′ is used to provide signals T (0−19)  in response to input of the next four MSBs, i.e. D 5 , D 4 , D 3  and D 2 , and the offset bit D 4S . A plurality of transistors  296  are used to selectively provide voltages Vb( 0-19)  as DA 2(+)  and DA 2(−)  in response to T (0-20) . The following Tables 5 and 6 show which ones of signals T (0-20)  are used to selectively activate the transistors  296  to provide DA 2(+)  and DA 2(−) , respectively.  
                                           TABLE 5                           DA 2(+)                  Vb (0-19)     T (0-19)                              1   1           2   2           3   3           4   4           5   5           6   6           7   7           8   8           9   9           10   10           11   11           12   12           13   13           14   14           15   15           16   16           17   17           18   18           19   19                      
 
         [0049]    [0049]                                           TABLE 6                           DA 2(−)                  Vb (0-19)     T (0-19)                              1   19           2   18           3   17           4   16           5   15           6   14           7   13           8   12           9   11           10   10           11   9           12   8           13   7           14   6           15   5           16   4           17   3           18   2           19   1           20   0                        
         [0050]    Referring now to FIG. 10A, there is shown a circuit  320  for providing DA 3(+)  and DA 3(−) . Still referring to FIG. 10A, the circuit  320  receives bit D 1  via an input. The input is coupled to an inverter  321  and a first input of a NOR gate  322 . The inverter  321  outputs to a first input of a second NOR gate  323 . The output of the NOR gate  322  is provided as a second input for NOR gate  323 . Likewise, the output of NOR gate  323  is provided as a second input for NOR gate  322 . In other words, the NOR gates  322 ,  323  are cross-coupled similarly as for a conventional S-R latch. The output of NOR gate  322  is also coupled to a gate input for a transistor  324  and a gate input for a transistor  326 . The output of NOR gate  323  is coupled to a gate input of a transistor  325  and a gate input of a transistor  327 . The transistor  324  is provided on a source input with Vb (0)  and transistor  325  is provided on a source input with Vb (2) . The drains of transistors  324  and  325  are coupled to a common node to provide DA 3(+) . Accordingly, Vb (0)  and Vb (2)  are selectively provided as DA 3(+)  dependently upon D 1 . Similarly, transistor  326  is provided on a source input with Vb (4)  and transistor  327  is provided on a source input with Vb (2) . The drains of transistors  326  and  327  are coupled to a common node to provide DA 3(−) . Accordingly, Vb (4)  and Vb (2)  are selectively provided as DA 3(−)  dependently upon D 1 .  
         [0051]    Referring now to FIG. 10B, there is shown a circuit  330  for providing DA 4(+)  and DA 4(31 ) . Still referring to FIG. 10B, the circuit  330  receives D 0  via an input. The input is coupled to an inverter  331  and a first input of a NOR gate  332 . The inverter  331  outputs to a first input of a second NOR gate  333 . The output of the NOR gate  332  is provided as a second input for NOR gate  333 . Likewise, the output of NOR gate  333  is provided as a second input for NOR gate  332 . In other words, the NOR gates  332 ,  333  are cross-coupled similarly as for a conventional S-R latch. The output of NOR gate  332  is coupled to a gate input for a transistor  334  and a gate input for a transistor  336 . The output of NOR gate  333  is coupled to a gate input of a transistor  335  and a gate input of a transistor  337 . The transistor  334  is provided on a source input with Vb (0)  and transistor  335  is provided on a source input with Vb (1) . The drains of transistors  334  and  335  are coupled to a common node to provide DA 4(+) . Accordingly, Vb (0)  and Vb (1)  are selectively provided as DA 4(+)  dependently upon D 0 . Similarly, transistor  336  is provided on a source input with Vb (2)  and transistor  337  is provided on a source input with Vb (1) . The drains of transistors  336  and  337  are coupled to a common node to provide DA 4(−) . Accordingly, Vb (2)  and Vb (1)  are selectively provided as DA 4(−)  dependently upon D 0 .  
         [0052]    Referring finally to FIG. 11, there is shown the resistor ladder  260  discussed with regard to FIG. 6. The resistor ladder  260  provides the voltages Va (0-16)  and Vb (0-20)  as have been discussed. The resistor ladder  260  includes two serially-connected resistor ladders  261 ,  262 . These ladders  261 ,  262  are cross-connected to reduce resistivity non-unifornity due to fabrication, for example. Each resistor ladder  261 ,  262 , is divided into 16 main sections Va (0-16)  by resistors  263 . Between Va 0  and Va 1 , each ladder is subdivided into 8 sections Vb (0-8) . Between Va 1  and Va 2 , each ladder is subdivided into another 8 sections Vb (9-16) . Between Va 2  and Va 3 , each ladder is subdivided into another 5 sections Vb (17-20) . Each Vb section is {fraction (1/128)} of the full range for the analog signal input to an ADC utilizing the ladder  260 . The resistors that make up the ladder  260  are preferably all about the same value, for example 1k ohm, within a degree of accuracy of about 1 ohm, for example.  
         [0053]    Although the invention has been described and pictured in a preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form, has been made only by way of example, and that numerous changes in the details of construction and combination and arrangement of parts may be made without departing from the spirit and scope of the invention as hereinafter claimed. It is intended that the patent shall cover by suitable expression in the appended claims, whatever features of patentable novelty exist in the invention disclosed.

Technology Classification (CPC): 7