Patent Abstract:
An exemplary interface circuit with an electrostatic discharge (ESD) protection circuit includes an interface and an ESD protection circuit. The interface includes at least two pins. The ESD protection circuit includes at least a first polarity signal enable circuit, a second polarity signal enable circuit, and an ESD circuit. The at least two pins are grounded via the at least first polarity signal enable circuit, the second polarity signal enable circuit, and share the same ESD circuit.

Full Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to electrostatic discharge (ESD) protection, and particularly to an interface circuit with an ESD protection circuit. 
         [0003]    2. Description of Related Art 
         [0004]    ESD protection is generally important in electrical device design to prevent or minimize damage to the device not from static electricity. ESD protection circuits are particularly important in interface circuitry. 
         [0005]    Referring to  FIG. 3 , a typical interface circuit  1  includes an interface  11  and two ESD protection circuits  12 . The interface  11  includes a first pin  110  and a second pin  111 . The two pins  110 ,  111  are grounded via the two ESD protection circuits  12 , respectively. 
         [0006]    The ESD protection circuit  12  includes a first diode  121 , a second diode  122 , a first Zener diode  123 , and a second Zener diode  124 . A positive electrode of the first diode  121  is connected to the positive electrode of the first Zener diode  123 . The second pin  111  is connected to a negative electrode of the first diode  121  and is grounded via the series connected first diode  121  and the first Zener diode  123 . The second pin  111  is also connected to a negative electrode of the second Zener diode  124  and is grounded via the series connected second Zener diode  124  and the second diode  122 . 
         [0007]    In the interface circuit  1 , each pin needs an ESD protection circuit  12 , and each ESD protection circuit  12  includes two diodes and two Zener diodes. The Zener diode is expensive, and costs of the interface circuit  1  are increased, especially where many Zener diodes are needed. 
         [0008]    What is needed, therefore, is an interface circuit with an ESD protection circuit that can overcome the described limitations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a circuit diagram of a first embodiment of an interface circuit with an ESD protection circuit according to the present disclosure. 
           [0010]      FIG. 2  is a circuit diagram of a second embodiment of an interface circuit with an ESD protection circuit according to the present disclosure. 
           [0011]      FIG. 3  is a circuit diagram of a conventional interface circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Reference will now be made to the drawings to describe various embodiments of the present disclosure in detail. 
         [0013]    Referring to  FIG. 1 , an interface circuit with an electrostatic discharge (ESD) protection circuit  2  includes an interface  21  and an ESD protection circuit  22 . The interface  21  includes a first pin  210  and a second pin  211 . The interface  21  may be high definition multimedia interface (HDMI), video graphic array (VGA), digital visual interface (DVI), and/or USB interface. 
         [0014]    The ESD protection circuit  22  includes a first polarity signal enable circuit  23 , a second polarity signal enable circuit  25 , and an ESD circuit  24 . The first pin  210  is grounded via the series connected first polarity signal enable circuit  23  and the ESD circuit  24 . The second pin  211  is grounded via the series connected second polarity signal enable circuit  25  and the ESD circuit  24 . 
         [0015]    The first polarity signal enable circuit  23  includes a first positive polarity signal enable circuit  231  and a first negative polarity signal enable circuit  232 . The second polarity signal enable circuit  25  includes a second positive polarity signal enable circuit  251  and a second negative polarity signal enable circuit  252 . The ESD circuit  24  includes a positive ESD circuit  241  and a negative ESD circuit  242 . In this disclosure, the first positive polarity signal enable circuit  231  includes a first diode  221 . The first negative polarity signal enable circuit  232  includes a third diode  223 . The second positive polarity signal enable circuit  251  includes a second diode  222 . The second negative polarity signal enable circuit  252  includes a fourth diode  224 . The positive ESD circuit  241  includes a first Zener diode  225 , and the negative ESD circuit  242  includes a second Zener diode  226 . 
         [0016]    A positive electrode of the first diode  221  and a negative electrode of the third diode  223  are both connected to the second pin  211 . A positive electrode of the second diode  222  and a negative electrode of the fourth diode  224  are both connected to the first pin  210 . A negative electrode of the first diode  221  and a negative electrode of the second diode  222  are both connected to a negative electrode of the first Zener diode  225 . A positive electrode of the third diode  223  and a positive electrode of the fourth diode  224  are both connected to a positive electrode of the second Zener diode  226 . A positive electrode of the first Zener diode  225  and a negative electrode of the second Zener diode  226  are both grounded. 
         [0017]    A breakdown voltage of the first Zener diode  225  and the second Zener diode  226  is substantially higher than a normal working voltage of the first and the second pins  210 ,  211 . With this parameter, the first and the second pins  210 ,  211  are prevented from being grounded when the first and the second pins  210 ,  211  are working normally. 
         [0018]    In operation, positive electrostatic pulses of the first pin  210  are guided to ground via the second diode  222  and the first Zener diode  225 . Negative electrostatic pulses of the first pin  210  are guided to ground via the fourth diode  224  and the second Zener diode  226 . Positive electrostatic pulses of the second pin  211  are guided to ground via the first diode  221  and the first Zener diode  225 . Negative electrostatic pulses of the second pin  211  are guided to ground via the third diode  223  and the second Zener diode  226 . 
         [0019]    Unlike the conventional interface circuit, in the interface circuit  2 , the first and the second pins  210 ,  211  are grounded via the first polarity signal enable circuit  23 , the second polarity signal enable circuit  25 , and the ESD circuit  24 . The ESD circuit  24  is shared by the first and the second pins  210 ,  211 . Therefore, the number of required Zener diodes is few, keeping the cost low. 
         [0020]      FIG. 2  shows a second embodiment of an interface circuit  3 , differing from interface circuit  2  of the first embodiment only in the inclusion of an interface  31  including a first pin  310 , a second pin  311 , and a third pin  312 . Correspondingly, an ESD protection circuit  32  of the interface circuit  3  includes a first polarity signal enable circuit (not labeled), a second polarity signal enable circuit (not labeled), a third polarity signal enable circuit (not labeled), and a shared ESD circuit (not labeled). The interface circuit  3  has advantages similar to those of the interface circuit  2 . Furthermore, if an interface of an interface circuit has more pins, the interface circuit is more economical. 
         [0021]    Further and/or alternative embodiments are described as follows. In the first embodiment, one of the four diodes  221 ,  222 ,  223 ,  224  may be grounded via a third Zener diode rather than the ESD circuit  24 . For example, the first diode  221  may not be grounded via the first Zener diode  225 , but rather via a third Zener diode. In another embodiment, the first pin  210  is grounded via only the second diode  222  and the first Zener diode  225 , and the second pin  211  is grounded via only the first diode  221  and the first Zener diode  225 . That is, each of the first polarity signal enable circuit  23  and the second polarity signal enable circuit  25  includes only one diode, and the ESD circuit  24  includes only one Zener diode. The first polarity signal enable circuit  23  and the second polarity signal enable circuit  25  share the Zener diode. 
         [0022]    It is to be understood that even though numerous characteristics and advantages of the present embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Technology Classification (CPC): 7