Patent Abstract:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to determine frequency of occurrence information for a range of gray levels from luminance data of an input signal. The second circuit may be configured to selectively adjust enhancement for at least one portion of the range of grey levels based upon the frequency of occurrence information.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates to image and video processing generally and, more particularly, to a method and/or apparatus for adaptive video enhancement gain control. 
     BACKGROUND OF THE INVENTION 
     Video enhancement techniques are used to make video appear sharper. One type of video enhancement technique involves enhancing edges or high frequency elements of the video. Conventional edge enhancement uses a high pass filter (HPF) or band pass filter (BPF) and an adder with filtering gain control. The conventional technique for enhancing edges is based on the Mach band effect. Edge enhancement is achieved by increasing the simultaneous contrast of the edge. The variation of the simultaneous contrast needs to be clamped into a limited range to avoid undershoot or overshoot (i.e., for an 8 bit unsigned quantization system, the limits are 0 and 255). 
     Referring to  FIG. 1 , a graph  10  is shown illustrating an example of over emphasized artifacts that can occur with the conventional enhancement technique. An input signal, captured from a monochrome image with a quantization range of zero to ten, can have a black region having a range from zero to less than two, a visible (or perceivable) region having a range from two to eight and a white region having a range from greater than eight to ten. From a perceptual view, the pixels located in the black region or the white region are not distinguishable. 
     An enhanced output signal (i.e., mixed original and a gain controlled output of a HPF or BPF) can have overshoot and undershoot conditions (i.e., pixel values greater than 10 or less than 0, respectively). The overshoot and undershoot conditions can be corrected by clamping circuitry. However, some pixels that were in the black region or the white region in the input signal (i.e., pixels 2, 4, 16 and 18) can be shifted into the visible region (i.e., the range from two to eight) after enhancement. The pixels with values shifted into the visible range cause artifacts (i.e., noise in the black and white regions). In general terms, the enhancement can cause white flakes in the black region and grey flakes in the white region. 
     To reduce the over emphasized artifacts a filtering gain control scheme is used. However, the artifacts will be highlighted if the gain control is not set properly. Unfortunately, a proper setting of the filtering gain is very difficult because the HPF or the BPF operates based on the frequency component of the video and ignores the amplitude component of the video. 
     Referring to  FIGS. 2(A-C) , graphs are shown illustrating characteristics of a high pass filter. Input signals presented to a high pass filter can have different DC (direct current) values (illustrated in  FIG. 2A ). However, the output of the high pass filter is related to frequency response and phase relationship and independent of the DC value of the input (as illustrated in  FIG. 2B ). The outputs of the high pass filter can be identical for the input signals with different DC values ( FIG. 2C ). 
     The conventional techniques have disadvantages of emphasizing pixels that human vision can not distinguish and causing artifacts. The filtering gain adjustment is based on frequency domain response (filter output) only and ignores the time domain characteristic of the input signal (i.e., the DC value). 
     It would be desirable to have a method and/or apparatus for adaptively controlling the filtering gain to avoid artifacts. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to determine frequency of occurrence information for a range of gray levels from luminance data of an input signal. The second circuit may be configured to selectively adjust enhancement for at least one portion of the range of grey levels based upon the frequency of occurrence information. 
     The objects, features and advantages of the present invention include providing a method and/or apparatus for adaptive video enhancement gain control that may (i) provide a filtering gain that emphasizes only pixels in a perceptual luminance range (PLR), (ii) reduce over emphasized artifacts, (iii) implement a perceptual luminance range histogram (PLRH), (iv) use the PLRH to provide an energy distribution of the perceptual luminance range, (v) set reference limits to avoid artifacts, (vi) implement a hysteretic filter to reduce artifacts caused by abrupt histogram change, (vii) adaptively control filtering gain to achieve a sharper result for different applications, (viii) provide a Gaussian curve gain distribution built into a look-up table (LUT), (ix) achieve luminance equalization adaptively and without causing color distortion, and/or (x) achieve a variable peaking gain by simply modifying the shape of the Gaussian curve in the LUT. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a graph illustrating an example of an enhanced version of an input signal obtained using a conventional edge enhancement technique; 
         FIGS. 2(A-C)  are graphs illustrating high pass filter characteristics; 
         FIG. 3  is block diagram illustrating a circuit in accordance with a preferred embodiment of the present invention; 
         FIG. 4  is a more detailed block diagram illustrating an example of a PLRH block of  FIG. 3 ; 
         FIG. 5  is a more detailed block diagram illustrating an example of a WPHF block of  FIG. 3 ; 
         FIG. 6  is a function diagram illustrating an example of a weight processor and hysteretic filter blocks of  FIG. 5 ; 
         FIG. 7  is a diagram illustrating an example of a Gaussian curve gain distribution in accordance with the present invention; 
         FIG. 8  is a more detailed block diagram illustrating an example of an output circuit of  FIG. 3 ; 
         FIG. 9  is a graph illustrating an example of an enhanced version of the input signal of  FIG. 1  obtained using an enhancement technique in accordance with the present invention; and 
         FIGS. 10(A-B)  are histograms illustrating an example of dynamic contrast in accordance with a preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention generally focuses on a human visual aspect of edge enhancement. The present invention generally uses a perceptual luminance range (PLR) instead of a whole quantized range to implement a PLR histogram (PLRH). For example, while the whole quantized range may be, in one example, from 0 to 255 (8-bit), the PLR may range, in one example, from about 64 to about 192. The PLR may be implemented with a range that may be adjusted (programmable). The PLRH is a histogram of the perceptual luminance range that generally provides an energy distribution of an image. Using the PLRH, a weight processor and hysteretic filter (WPHF) may be configured to assign a perceptual filtering gain based on a predetermined Gaussian curve gain distribution. In one example, the Gaussian curve gain distribution may be implemented in (built into) a look-up table (LUT). The LUT may be used to adaptively adjust the filtering gain. 
     Referring to  FIG. 3 , a block diagram is shown illustrating a circuit  100  in accordance with a preferred embodiment of the present invention. In one example, the circuit  100  may be implemented as a video enhancement circuit (or block). The circuit  100  may have an input  102  that may receive a signal (e.g., INPUT) and an output  104  that may present a signal (e.g., OUTPUT). The signal INPUT may comprise a video signal. The signal OUTPUT may comprise an edge enhanced version of the signal INPUT. In one example, the signals INPUT and OUTPUT may comprise a luminance (Y) component of the respective video signals. The circuit  100  may be configured to generate the signal OUTPUT in response to the signal INPUT using adaptive gain control. 
     In one example, the circuit  100  may comprise a circuit (or block)  106  and a circuit (or block)  108 . In one example, the circuit  106  may be implemented as an adaptive video enhancement gain control system. The circuit  108  may be implemented as a video enhancement output circuit. The circuit  106  may have an input  110  that may receive the signal INPUT and an output  112  that may present a signal (e.g., CONTROL). The signal CONTROL may be implemented as a control signal. The signal CONTROL may be configured to adaptively control a filtering gain of the circuit  108 . The circuit  106  may be configured to generate the signal CONTROL in response to the signal INPUT. The circuit  108  may have an input  114  that may receive the signal INPUT, an input  116  that may receive the signal CONTROL and an output that may present the signal OUTPUT. The circuit  108  may be configured to generate the signal OUTPUT in response to the signals INPUT and CONTROL. 
     In one example, the circuit  106  may comprise a circuit (or block)  120 , a circuit (or block)  122  and a circuit (or block)  124 . The circuit  120  may be implemented, in one example, as a perceptual luminance range histogram (PLRH) generating circuit. The circuit  122  may be implemented, in one example, as a weight processor and hysteretic filter (WPHF) block. The circuit  124  may be implemented, in one example, as a look-up table (LUT). The circuit  120  may have an input that may receive the signal INPUT and an output that may present a number of signals (e.g., B 0  . . . Bn). In one example, the signals B 0  . . . Bn may represent individual bin (or slot) values of the perceptual luminance range histogram. The circuit  122  may have an input that may receive the signals B 0  . . . Bn and an output that may present a signal (e.g., MEAN). The signal MEAN may be configured to indicate a center value or mean of a distribution curve for the values of the perceptual luminance range histogram. For a Gaussian curve (e.g., a normal distribution curve) the curve function may be expressed by Equation 1 below:
 
 F ( x )=1 /σ×sqr (2π)×( e   −0.5((x−μ)/σ)2)   Eq. 1
 
where the value μ represents the mean of x and the variable σ represents the standard deviation of x.
 
     The circuit  124  may have an input that may receive the signal MEAN and an output that may present the signal CONTROL. The circuit  124  may be configured to generate the signal CONTROL in response to the signal MEAN. In one example, the circuit  124  may contain entries representing samples of a predetermined distribution curve (e.g., a Gaussian curve). For example, the entries stored in the circuit  124  may be determined using Equation 1 above. In one example, the circuit  124  may be configured to set a center value of the distribution curve in response to the signal MEAN. In one example, the preloaded samples in the circuit  124  may be determined for a gain curve for a particular standard deviation (e.g., σi). In another example, the preloaded samples may be determined for a number of different gain distribution curves for a number of different standard deviations (e.g., σ 1 -σn). 
     In one example, the circuit  108  may comprise a circuit (or block)  130 , a circuit (or block)  132 , a circuit (or block)  134  and a circuit (or block)  136 . The circuit  130  may be implemented, in one example, as either a high pass filter (HPF) or a band pass filter (BPF). The circuit  132  may be implemented, in one example, as a delay circuit. The circuit  134  may be implemented, in one example, as a gain control circuit. The circuit  136  may be implemented, in one example, as an adder circuit. 
     The circuit  130  may have an input that may receive the signal INPUT and an output that may present a signal (e.g., F_INPUT) to a first input of the circuit  134 . The circuit  134  may have a second input that may receive the signal CONTROL and an output that may present a signal (e.g., F_GAIN) to a first input of the circuit  136 . The circuit  132  may have an input that may receive the signal INPUT and an output that may present a signal (e.g., D_INPUT) to a second input of the circuit  136 . The circuit  136  may have an output that may present the signal OUTPUT. The circuits  130 - 136  may be implemented using conventional techniques. 
     The signal INPUT may be fed through a HPF/BPF (e.g., the circuit  130 ) and a delay device (e.g., the circuit  132 ) that is configured to compensate for a delay of the HPF/BPF. The signal F_INPUT may be used to select a multiplier for a gain of the circuit  134  to generate the signal F_GAIN. The signal F_GAIN may be summed with the signal D_INPUT by the circuit  136 . An output of the circuit  136  may present the enhanced result as the signal OUTPUT. 
     Referring to  FIG. 4 , a more detailed block diagram is shown illustrating an example of a PLRH generating circuit  120  in accordance with a preferred embodiment of the present invention. In one example, the circuit  120  may comprise a plurality of circuits (or blocks)  140   a - 140   n  and a plurality of circuits (or blocks)  142   a - 142   n . The circuits  140   a - 140   n  may be implemented, in one example, as range selector circuits. In one example, the circuits  140   a - 140   n  may be configured to determine whether an input signal falls within a range between predetermined limits. The circuits  142   a - 142   n  may be implemented as counter circuits. In one example, the circuits  142   a - 142   n  may comprise 16-bit counter circuits. 
     Each of the circuits  140   a - 140   n  may have a first input that may receive the signal INPUT, a second input that may receive a signal (e.g., LL 0 -LLn, respectively) and a third input that may receive a signal (e.g., UL 0 -ULn, respectively). The signals LL 0 -LLn may be implemented as lower limit values for respective bins (or slots) of the PLRH. The signals UL 0 -ULn may be implemented as upper limit values for respective bins (or slots) of the PLRH. Each of the circuit  140   a - 140   n  may be configured to generate an output indicating when a value of the signal INPUT is within the respective range set by the respective signals LL 0 -LLn and UL 0 -ULn. 
     Each of the circuits  142   a - 142   n  may have a first input that may receive an output of a corresponding one of the circuits  140   a - 140   n  and a second input that may receive a signal (e.g., VS). In one example, the signal VS may be configured to reset the circuits  142   a - 142   n . In one example, the signal VS may comprise a vertical sync signal of a video stream. Each of the circuits  142   a - 142   n  may have an output representing a slot (or bin) value of the perceptual luminance range histogram. For example, the circuit  142   a  may have an output that may present a signal (e.g., B 0 ) representing a value of a first bin  0 . The circuit  142   b  may have an output that may present a signal (e.g., B 1 ) representing a value for a second bin  1 . The circuit  142   c  may have an output that may present a signal (e.g., B 2 ) representing a value for a third bin  2 . The circuit  142   n  may have an output that may represent a signal (e.g., Bn) representing a value for an nth bin n. The PLRH may provide the energy distribution of the signal INPUT in the form of a histogram of the PLR. The depth and number of bins may be programmable to fit different applications. The output of the circuit  120  may be normalized. The PLRH generally provides a precise way to present the energy distribution of the signal INPUT. 
     Referring to  FIG. 5 , a more detailed block diagram is shown illustrating an example of a weight processor and hysteretic filter (WPHF) circuit  122  in accordance with a preferred embodiment of the present invention. In one example, the circuit  122  may comprise a circuit (or block)  150  and a circuit (or block)  152 . The circuit  150  may be implemented as a weight processor circuit. The circuit  152  may be implemented as a hysteretic filter circuit. In one example, the circuit  152  may be implemented as a low pass filter (LPF). Each of the signals B 0  . . . Bn may be presented to a respective input of the circuit  150 . The circuit  150  may have an output that may present a signal to an input of the circuit  152 . The circuit  152  may have an output that may present the signal MEAN. 
     In one example, the circuit  150  may comprise a number of registers  154   a - 154   n , a number of multiplier circuits (or blocks)  156   a - 156   n  and an adder circuit (or block)  158 . Each of the registers  154   a - 154   n  may contain a respective weighting factor or weight (e.g., W 0 -Wn). Each of the weights W 0 -Wn may be applied to (e.g., multiplied with) a corresponding one of the signals B 0 -Bn received from the circuit  120 . In one example, each of the weights W 0 -Wn may be programmable. 
     Each of the multiplier circuits  156   a - 156   n  may have a first input that may receive a respective one or the signals B 0 -Bn from the circuit  120  and a second input that may receive a respective one of the weights W 0 -Wn from a corresponding one of the registers  154   a - 154   n . Each of the multiplier circuits  156   a - 156   n  may have any output that may present a signal to a corresponding input of the adder circuit  158 . The adder circuit  158  may have an output that may present a signal to an input of the hysteretic filter  152 . 
     Referring to  FIGS. 6(   a - b ), a function diagram is shown further illustrating an example of the operation of the circuit  122  of  FIG. 5 . The circuit  122  generally performs a weight processor function  150  and a hysteretic filtering function  152  (illustrated in  FIG. 6(   a )). The weight processor  150  may be configured to manipulate normalized histogram data by multiplying each of the signals B 0 -Bn by a respective one of the programmable weight values W 0 -Wn. The manipulated data (signed) may be summed by the adder  158  and the output of the adder  158  fed into the hysteretic filter  152 . The weight processor  150  may be further configured to provide a value or parameter (e.g., μ). In one example, the parameter μ may provide mean-like deviation information that may be used by the LUT  124 . In one example, the hysteretic filter  152  may be implemented as a low pass filter (LPF). The LPF may be configured to smooth the accumulated weight and avoid artifacts due to abrupt changes in the PLRH received from the circuit  120 . 
     Referring to  FIG. 7 , a graph is shown illustrating a Gaussian curve shaped gain distribution in accordance with the present invention. In one example, the LUT  124  may be implemented as a Gaussian curve shaped gain distribution table. The output of the circuit  122  generally provides information for determining a position and a shape of the Gaussian curve gain distribution. For example, the circuit  122  may be configured to provide a parameter (e.g., σ) and the parameter μ. The parameter σ may be used to determine a peak (or center) amplitude of the Gaussian curve gain distribution. For example, the value σ may be used to select among a plurality of predetermined Gaussian curve gain distributions. The parameter μ may be used to determine the position of the center of the Gaussian curve gain distribution. For example, the center of the Gaussian curve may be shifted right when μ&gt;0 and shifted left when μ&lt;0. 
     In general, the center of the Gaussian curve provides the maximum gain. Since the center of the Gaussian curve provides the maximum gain, the present invention may also provide a kind of luminance equalization effect, without generating color distortion. The feature of dynamic luminance equalization of the PLR is generally based on adaptive parameter selection and the Gaussian curve distribution look-up table (LUT)  124 . By selecting different values of σ, a different peak of the Gaussian curve may be obtained. The samples of the Gaussian curve and variations of the parameters μ and σ generally determine the size of the LUT  124 . 
     Referring to  FIG. 8 , a more detailed block diagram is shown illustrating an example of an edge enhancement output circuit (or block)  108  and LUT  124  in accordance with a preferred embodiment of the present invention. In one example, the circuit  124  may comprise a circuit (or block)  160  and a circuit (or block)  162 . The circuit  160  may comprise a number (e.g., an integer N) of Gaussian curve registers. The circuit  162  may comprise a selector (or multiplexer) circuit. In one example, the circuit  162  may be configured to select a center point of a gain curve. For example, the circuit  162  may be configured to select a number (e.g., an integer M) of values from the number of Gaussian curve registers  160 . The selected values may be presented to the circuit  108  as the signal CONTROL. In one example, the integer M may be less than the integer N. 
     The circuit  134  may comprise a circuit (or block)  164  and a circuit (or block)  166 . The circuit  164  may be implemented as a slot selector (or multiplexer) circuit. The circuit  166  may be implemented as a peaking gain multiplier circuit. The circuit  164  may have a number (e.g., M) of first inputs, corresponding to the outputs of the circuit  124 , that may receive the signal CONTROL. 
     The circuit  164  may have a second input that may receive the signal INPUT and an output that may present a signal to first input of the circuit  166 . The circuit  166  may have a second input that may receive the signal F_INPUT and an output that may present the signal F_GAIN. The circuit  166  may be configured to generate the signal F_GAIN in response to the signal F_INPUT and the output of the circuit  164 . 
     Referring to  FIG. 9 , a graph is shown illustrating enhancement using a technique in accordance with the present invention. In general, the settings and definitions, such as black and white range, HPF coefficients and input signal used to generate the enhanced output signal illustrated in  FIG. 9  are the same as used in  FIG. 1 . In general, the present invention provides better quality enhancement than conventional techniques. The artifacts shown in  FIG. 1  are reduced or eliminated and may be ignored. The present invention generally does not scarify the enhancement in the PLR. For example, the present invention generally avoids shifting a sample from the white region (e.g., having a value greater than 8 to 10) into the PLR (e.g., values ranging from 2 to 8) which produces an artifact (noise) that looks like a grey scratch on a white board. 
     The artifacts shown in  FIG. 1  can be amplified by an interpolation processes, such as de-interlacing and horizontal or vertical scaling. Since the present invention may avoid generation of the artifacts and enhance the sharpness of an input signal, the present invention may be useful for iDTV and HDTV applications. 
     Referring to  FIGS. 10(   a - b ), histograms are shown illustrating an example of dynamic contrast in accordance with a preferred embodiment of the present invention.  FIG. 10   a  generally illustrates the original histogram of the signal INPUT.  FIG. 10   b  generally illustrates a normalized histogram generated in accordance with the present invention. The histogram of  FIG. 10   b  generally has a more even energy distribution than the histogram of  FIG. 10   a . Although the present invention generally does not equalize the PLR, the present invention generally has an advantage of not causing chrominance distortion (artifacts) because the invention may apply, in one example, a finite impulse response (FIR) filter gain based upon a Gaussian curve. The center of the Gaussian curve is generally determined based upon the perceptual luminance range histogram. By applying a filter gain based upon a Gaussian curve centered according to the perceptual luminance range histogram equalization may be achieved. 
     The present invention generally provides advantages over conventional enhancement techniques that may include, but are not limited to, (i) providing a filtering gain that emphasizes only pixels in the PLR, (ii) reducing over emphasized artifacts using adaptive gain control, (iii) providing a PLRH describing an energy distribution of the PLR that can be used to set reference limits to avoid the artifacts, (iv) providing a hysteretic filter that may reduce a “breath scream” artifact that may be caused by abrupt histogram changes, (v) providing a LUT, or similar device, that may be configured to adaptively control the filtering gain to achieve a sharper result for different applications, (vi) providing a Gaussian curve gain distribution built into a LUT and adjusted to adaptively achieve luminance equalization without color distortion, and/or (vii) providing a peaking gain that may be varied by simply modifying the shape of the Gaussian curve in the LUT. 
     The functions illustrated by the diagram of  FIGS. 3-8  may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
     The present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Technology Classification (CPC): 6