Patent Abstract:
A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Full Description:
[0001]    The present application claims priority to Provisional Application No. 60/912,399, filed Apr. 17, 2007 and is herein incorporated by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates generally to programmable devices, and more particularly to a programmable interconnect matrix. 
       BACKGROUND 
       [0003]    Field-programmable gate arrays (FPGAs) and Programmable Logic Devices (PLDs) have been used in data communication and telecommunication systems. Conventional PLDs and FPGAs consist of an array of programmable elements, with the elements programmed to implement a fixed function or equation. Some currently-available Complex PLD (CPLD) products comprise arrays of logic cells. Conventional PLD devices have several drawbacks, such as limited speed and limited data processing capabilities. 
         [0004]    In developing complex integrated circuits, there is often a need for additional peripheral units, such as operational and instrument amplifiers, filters, timers, digital logic circuits, analog to digital and digital to analog converters, etc. As a general rule, implementation of these extra peripherals create additional difficulties: extra space for new components, additional attention during production of a printed circuit board, and increased power consumption. All of these factors can significantly affect the price and development cycle of the project. 
         [0005]    The introduction of the Programmable System on Chip (PSoC) features digital and analog programmable blocks, which allow the implementation of a large number of peripherals. A programmable interconnect allows analog and digital blocks to be combined to form a wide variety of functional modules. The digital blocks consist of smaller programmable blocks and are configured to provide different digital functions. The analog blocks are used for development of analog elements, such as analog filters, comparators, inverting amplifiers, as well as analog to digital and digital to analog converters. Current PSoC architectures provide only a coarse grained programmability where only a few fixed functions are available with only a small number of connection options. 
       SUMMARY 
       [0006]    A programmable interconnect matrix includes horizontal channels that programmably couple different groups of one or more digital blocks together. The interconnect matrix can include segmentation elements that programmably interconnect different horizontal channels together. The segmentation elements can include horizontal segmentation switches that programmably couple together the horizontal channels for different groups of digital blocks in a same row. Vertical segmentation switches can programmably couple together the horizontal channels for different groups of digital blocks in different rows. 
         [0007]    Vertical channels can programmably connect the horizontal channels in different rows. The horizontal channels provide more connectivity between the digital blocks located in the same rows than connectivity provided by the vertical channels connecting the digital blocks in different rows. Two digital blocks in a same digital block pair can be tightly coupled together to common routes in a same associated horizontal channel and different digital block pairs can be less tightly coupled together through the segmentation elements. 
         [0008]    Programmable switches are configured to connect different selectable signals from the digital bocks to their associated horizontal channels. Programmable tri-state buffers in the segmentation elements can be configured to selectively couple together and drive signals between different horizontal channels. 
         [0009]    A Random Access Memory (RAM) can be configured to programmably control how the different digital blocks are coupled together through the interconnection matrix. Undedicated Inputs and Outputs (I/Os) can be programmably coupled to different selectable signals in different selectable digital blocks through different selectable routes in the interconnection matrix. The undedicated Inputs and Outputs refer to the connections on the Integrated Circuit (IC) to external signals. 
         [0010]    A micro-controller system is programmably coupled to the different digital blocks through the interconnect matrix and is programmably coupled to the different programmable Inputs/Outputs (I/Os) through the interconnect matrix. The micro-controller system can include a micro-controller, an interrupt controller, and Direct Memory Access (DMA) controller. Interrupt requests can be programmably coupled between the interrupt controller and different selectable digital blocks or different selectable I/Os through the interconnect matrix. DMA requests can also be programmably coupled between the DMA controller and different selectable digital blocks or different selectable I/Os through the interconnect matrix. In one embodiment, the micro-controller, digital blocks, I/Os, and interconnect are all located in a same integrated circuit. 
         [0011]    In one embodiment, the digital blocks comprise a first group of uncommitted logic elements that are programmable into different logic functions and also include a second group of structural logic elements that together form a programmable arithmetic sequencer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a schematic block diagram illustrating an example PSoC architecture that includes a Universal Digital Block (UDB) array. 
           [0013]      FIG. 2  is a schematic block showing an interconnect matrix in the UDB array. 
           [0014]      FIG. 3  is a schematic block diagram showing how a pair of UDBs are tightly coupled to a horizontal routing channel. 
           [0015]      FIG. 4  is a schematic block diagram showing programmable switches that connect the UDBs in  FIG. 3  to the horizontal routing channel. 
           [0016]      FIG. 5  is a schematic block diagram showing segmentation elements in the interconnect matrix. 
           [0017]      FIG. 6  is a schematic block diagram showing different programmable switches in the segmentation elements of  FIG. 5  in more detail. 
           [0018]      FIG. 7  is a schematic block diagram that shows how the interconnect matrix of  FIG. 2  can connect different interconnect paths to a micro-controller system. 
           [0019]      FIG. 8  is a schematic diagram that shows one of the UDBs in more detail. 
           [0020]      FIG. 9  is a schematic diagram that shows a datapath in the UDB of  FIG. 8  in more detail. 
       
    
    
     INTRODUCTION 
       [0021]    A new programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O. 
       DETAILED DESCRIPTION 
       [0022]      FIG. 1  is a high level view of a Universal Digital Block (UDB) array  110  contained within a Programmable System on a Chip (PSoC) Integrated Circuit (IC)  100 . The UDB array  110  includes a programmable interconnect matrix  130  that connects together the different UDBs  120 . The individual UDBs  120  each include a collection of uncommitted logic in the form of Programmable Logic Devices (PLDs) and structural dedicated logic elements that form a datapath  210  shown in more detail in  FIGS. 8 and 9 . 
       UDB Array 
       [0023]    The UDB array  110  is arranged into UDB pairs  122  that each include two UDBs  120  that can be tightly coupled to a shared horizontal routing channel  132 . The UDB pairs  122  can also be programmably connected to the horizontal routing channels  132  of other UDB pairs  122  either in the same horizontal row or in different rows through vertical routing channels  134 . The horizontal and vertical routing channels and other switching elements are all collectively referred to as the interconnect matrix  130 . 
         [0024]    A Digital System Interconnect (DSI) routing interface  112  connects a micro-controller system  170  and other fixed function peripherals  105  to the UDB array  110 . The micro-controller system  170  includes a micro-controller  102 , an interrupt controller  106 , and a Direct Memory Access (DMA) controller  108 . The other peripherals  105  can be any digital or analog functional element in PSoC  100 . The DSI  112  is an extension of the interconnect matrix  130  at the top and bottom of the UDB array  110 . 
         [0025]      FIG. 2  shows the interconnect matrix  130  in more detail and includes horizontal routing channels  132  that programmably connect with one or more associated Universal Digital Blocks (UDB)  120 . In this example, pairs  122  of UDBs  120  are tightly coupled together through their associated horizontal routing channel  132 . However, more than two UDBs  120  can be tightly coupled together through the same horizontal routing channel  132 . 
         [0026]    The interconnect matrix  130  also includes Horizontal/Vertical (H/V) segmentation elements  125  that programmably interconnect the different horizontal routing channels  132  together. The segmentation elements  125  couple together the horizontal routing channels  132  for the different digital block pairs  122  in the same rows. The segmentation elements  125  also programmably couple together the horizontal routing channels  132  for digital block pairs  122  in different rows through vertical routing channels  134 . 
         [0027]      FIG. 3  shows one of the UDB pairs  122  in more detail. The UDBs  120 A and  120 B each contain several different functional blocks that in one embodiment include two Programmable Logic Devices (PLDs)  200 , a data path  210 , status and control  204 , and clock and reset control  202 . The operations of these different functional elements are described in more detail below in  FIGS. 8 and 9 . 
         [0028]    The two UDBs  120 A and  120 B in UDB pair  122  are tightly coupled together to common routes in the same associated horizontal routing channel  132 . Tight coupling refers to the UDB I/O signals  127  in the upper UDB  120 A and the corresponding signals  128  in the lower UDB  120 B all being directly connected to the same associated horizontal routing channel  132 . This tight coupling provides high performance signaling between the two UDBs  120 A and  120 B. For example, relatively short connections  127  and  128  can be programmably established between the upper UDB  120 A and the lower UDB  120 B. 
         [0029]    In one embodiment, the horizontal routing channels  132  can also have a larger number of routes and connections to the UDBs  120 A and  120 B than the vertical routing channels  134  shown in  FIG. 2 . This allows the horizontal routing channels  132  to provide more interconnectivity both between the UDBs  120 A and  120 B in UDB pair  122  and also provides more interconnectivity between different UDB pairs  122  in the same rows of interconnect matrix  130 . 
         [0030]    Thus, the interconnect matrix  130  in  FIGS. 1 and 2  more effectively uses chip space by providing more traces and connectivity for the shorter/higher performance horizontal routing channels  132  than the relatively longer/lower performance vertical routing channels  134 . 
         [0031]      FIG. 4  shows switching elements  145  that connect the different I/O signals  127  and  128  for the UDBs  120 A and  120 B in  FIG. 3  to the horizontal routing channel  132 . In this example, an output  127 A from the upper UDB  120 A in the UDB pair  122  drives an input  128 A in the lower UDB  120 B. A buffer  138  is connected to the UDB output  127 A and a buffer  140  is connected to the UDB input  128 A. The output  127 A and input  128 A are connected to vertical wires  146  and  148 , respectively, that intersect the horizontal routing channel wire  132 A with a regular pattern. 
         [0032]    At the switch points, RAM bits operate RAM cells  136  and  138  which in turn control Complementary Metal Oxide Semi-conductor (CMOS) transmission gate switches  142  and  144 , respectively. The switches  142  and  144  when activated connect the UDB output  127 A and the UDB input  128 A to horizontal routing channel wire  132 A. 
         [0033]    The RAM cells  136  and  137  are programmably selectable by the micro-controller  102  ( FIG. 1 ) by writing values into a configuration RAM  410  ( FIG. 7 ). This allows the micro-controller  102  to selectively activate or deactivate any of the gate switches  142  and  144  and connect any I/O  127  or  128  from either of the two universal digital blocks  120 A and  120 B to different wires in the horizontal channel  132 . 
         [0034]      FIG. 5  shows the interconnect matrix  130  previously shown in  FIGS. 1 and 2  in further detail. The segmentation elements  125  can include different combinations of horizontal segmentation switches  152  and vertical segmentation switches  154 . The horizontal segmentation switches  152  programmably couple together adjacent horizontal routing channels  132  located in the same row. The vertical segmentation switches  152  programmably couple together horizontal routing channels  132  located vertically in adjacent rows via vertical routing channels  134 . 
         [0035]    In addition to the segmentation elements  125 , the interconnect matrix  130  includes the switching elements  145  previously shown in  FIG. 4  that programmably connect the upper and lower UDBs  120 A and  120 B with their associated horizontal routing channels  132 . 
         [0036]    Referring to  FIGS. 5 and 6 , the segmentation elements  125  comprise arrays of horizontal segmentation switches  152  that are coupled in-between different horizontal routing channels  132  and vertical segmentation switches  154  coupled in-between the vertical routing channels  134 . Each segmentation switch  152  and  154  is controlled by two bits  162 A and  162 B from the configuration RAM  410  ( FIG. 7 ). The two bits  162 A and  162 B together control a tri-state buffer  164 . 
         [0037]    When bit  162 A is set, the buffer  164 A drives one of the horizontal or vertical channel lines  166  from left to right. When bit  162 B is set, the buffer  164 B drives the same horizontal or vertical channel line  166  from right to left. If neither bit  162 A or bit  162 B is set, the buffers  164 A and  164 B drive line  166  to a high impedance state. 
       Configuration and Programmability 
       [0038]    Any combination of the switching elements  145 , horizontal segmentation switches  152 , and vertical segmentation switches  154  can be programmably configured to connect together almost any combination of external I/O pins  104  ( FIG. 1 ), UDBs  120 , and micro-controller system elements  170 , fixed peripherals  105 , and UDBs  120  ( FIG. 1 ). 
         [0039]      FIG. 7  shows different examples of how different types of interconnect paths can be programmed through the interconnect matrix  130 . A Random Access Memory (RAM) or a set of configuration registers  410  are directly readable and writeable by the micro-controller  102 . The configuration registers  410  are shown as a stand-alone RAM in  FIG. 7  for illustrative purposes. However, it should be understood that certain configuration registers  410  can be located within the individual UDBs  120  while other configuration registers can be stand-alone registers that are accessed by multiple different functional elements. 
         [0040]    A first set of bits in RAM section  412  are associated with the RAM cells  136  and  137  shown in  FIG. 4  that control connections between the inputs and output of UDB and their associated horizontal routing channels  132 . A second set of bits in RAM section  414  control how the horizontal segmentation switches  152  in  FIGS. 5 and 6  connect the horizontal routing channels  132  in the same rows together and other bits in RAM section  414  control how the vertical segmentation switches  154  connect together the horizontal routing channels  132  in different rows. 
         [0041]    Pursuant to the micro-controller  102  programming RAM  410 , the interconnect matrix  130  is configured with a first interconnect path  176  that connects a UDB  120 C to the interrupt controller  106 . The UDB  120 C can then send interrupt requests to the DMA controller  108  over interconnect path  176 . A second interconnect path  178  is established between a peripheral (not shown) in the PSoC chip  100  ( FIG. 1 ) and the DMA controller  108 . The peripheral sends DMA requests to the DMA controller  108  over the interconnect path  178  established over the interconnect matrix  130 . 
         [0042]    A third interconnect path  180  is also configured by the micro-controller  102  by loading bits into RAM sections  412  and  414 . The DMA controller  108  uses the interconnect path  180  to send a DMA terminate signal to UDB  120 D. A fourth interconnect path  182  is programmably configured between one of the PSoC I/O pins  104  and a fixed digital peripheral, such as the micro-controller  102 . The interconnect path  182  is used to send I/O signals between the micro-controller  102  and the I/O pin  104 . 
         [0043]    Interconnect paths  176 - 182  are of course just a few examples of the many different interconnect configurations that can be simultaneously provided by the interconnect matrix  130 . This example also shows how different I/O pins  104 , UDBs  120 , and other peripherals can be connected to the same interrupt line on the interrupt controller  106  or connected to the same DMA line on the DMA controller  108 . 
         [0044]    Typically, interrupt requests received by an interrupt controller and DMA requests received by a DMA controller can only be connected to one dedicated pin. The interconnect matrix  130  allows any variety of different selectable functional elements or I/O pins to be connected to the same input or output for the interrupt controller  106  or DMA controller  108  according to the programming of RAM  410  by micro-controller  102 . 
         [0045]    The programmability of the interconnect matrix  130  also allows any number, or all, of the I/O pins  104  to be undedicated and completely programmable to connect to any functional element in PSoC  100 . For example, the pin  104  can operate as an input pin for any selectable functional element in  FIG. 7 . In another interconnect matrix configuration, the same pin  104  can operate as an output pin when connected to a first peripheral and operate as an output pin when connected to a different peripheral. 
       Universal Digital Block 
       [0046]      FIG. 8  is a top-level block diagram for one of the UDBs  120 . The major blocks include a pair of Programmable Logic Devices (PLDs)  200 . The PLDs  200  take inputs from the routing channel  130  and form registered or combinational sum-of-products logic to implement state machines, control for datapath operations, conditioning inputs and driving outputs. 
         [0047]    The PLD blocks  200  implement state machines, perform input or output data conditioning, and create look-up tables. The PLDs  200  can also be configured to perform arithmetic functions, sequence datapath  210 , and generate status. PLDs are generally known to those skilled in the art and are therefore not described in further detail. 
         [0048]    The datapath block  210  contains highly structured dedicated logic that implements a dynamically programmable ALU, comparators, and condition generation. A status and control block  204  allows micro-controller firmware to interact and synchronize with the UDB  120  by writing to control inputs and reading status outputs. 
         [0049]    A clock and reset control block  202  provides global clock selection, enabling, and reset selection. The clock and reset block  202  selects a clock for each of the PLD blocks  200 , the datapath block  210 , and status and control block  204  from available global system clocks or a bus clock. The clock and reset block  202  also supplies dynamic and firmware resets to the UDBs  120 . 
         [0050]    Routing channel  130  connects to UDB I/O through a programmable switch matrix and provides connections between the different UDBs in  FIG. 7 . A system bus interface  140  maps all registers and RAMs in the UDBs  120  into a system address space and are accessible by the micro-controller  102 . 
         [0051]    The PLDs  200  and the datapath  210  have chaining signals  212  and  214 , respectively, that enable neighboring UDBs  120  to be linked to create higher precision functions. The PLD carry chain signals  212  are routed from the previous adjacent UDB  120  in the chain, and routed through each macrocell in both of the PLDs  200 . The carry out is then routed to the next UDB  120  in the chain. A similar connectivity is provided by the datapath chain  214  between datapath blocks  210  in adjacent UDBs  120 . 
         [0052]    Referring to  FIG. 9 , each UDB  120  comprises a combination of user defined control bits that are loaded by the micro-controller  102  into control registers  250 . The control registers  250  can be part of the control blocks  202  and  204  described above in  FIG. 8 . The control registers  250  feed uncommitted programmable logic  200 . The same control blocks  202  and  204  described above in  FIG. 8  also include associated status registers  256  that allow the micro-controller  102  to selectably read different internal states for structural arithmetic elements  254  within the datapath  210 . 
         [0053]    The datapath  210  comprises highly structured logic elements  254  that include a dynamically programmable ALU  304 , conditional comparators  310 , accumulators  302 , and data buffers  300 . The ALU  304  is configured to perform instructions on accumulators  302 , and to update the sequence controlled by a sequence memory. The conditional comparators  310  can operate in parallel with the ALU  304 . The datapath  210  is further optimized to implement typical embedded functions, such as timers, counters, etc. 
         [0054]    The combination of uncommitted PLDs  200  with a dedicated datapath module  210  allow the UDBs  120  to provide embedded digital functions with more efficient higher speed processing. The dedicated structural arithmetic elements  254  more efficiently implement arithmetic sequencer operations, as well as other datapath functions. Since the datapath  210  is structural, fewer gates are needed to implement the structural elements  254  and fewer interconnections are needed to connect the structural elements  254  together into an arithmetic sequencer. Implementing the same datapath  210  with PLDs could require additional combinational logic and additional interconnections. 
         [0055]    The structured logic in the datapath  210  is also highly programmable to provide a wide variety of different dynamically selectable arithmetic functions. Thus, the datapath  210  not only conserves space on the integrated circuit  100  ( FIG. 1 ) but also is more accessible and programmable than other structured arithmetic sequencers. 
         [0056]    The functional configurability of the datapath  210  is provided through the control registers  250  and allow the micro-controller  102  to arbitrarily write into a system state and selectively control different arithmetic functions. The status registers  256  allow the micro-controller  102  to also identify different states associated with different configured arithmetic operations. 
         [0057]    The flexible connectivity scheme provided by the routing channel  130  selectively interconnects the different functional element  250 ,  200 ,  254 , and  256  together as well as programmably connecting these functional element to other UDBs, I/O connections, and peripherals. Thus, the combination of uncommitted logic  200 , structural logic  254 , and programmable routing channel  130  provides more functionality, flexibility, and more efficiently uses less integrated circuit space. 
         [0058]    The interconnect matrix  130  also requires little or no dedicated UDB block routing. All data, state, control, signaling, etc, can be routed through the interconnect matrix  130  in the UDB array  110 . The array routing is efficient because there is little or no difference between a local UDB net and a net that spans the UDB array. Horizontal and vertical segmentation allow the array to be partitioned for increased efficiency and random access to the RAM  410  allow high speed configuration or on the fly reconfigurability. 
         [0059]    The system described above can use dedicated processor systems, micro controllers, programmable logic devices, or microprocessors that perform some or all of the operations. Some of the operations described above can be implemented in software and other operations can be implemented in hardware. 
         [0060]    For the sake of convenience, the operations are described as various interconnected functional blocks or distinct software modules. This is not necessary, however, and there can be cases where these functional blocks or modules are equivalently aggregated into a single logic device, program or operation with unclear boundaries. In any event, the functional blocks and software modules or features of the flexible interface can be implemented by themselves, or in combination with other operations in either hardware or software. 
         [0061]    Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. Claim is made to all modifications and variation coming within the spirit and scope of the following claims.

Technology Classification (CPC): 7