Patent Abstract:
IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.

Full Description:
BACKGROUND  
       [0001]     The invention relates to an IC with built-in self-test and a design method thereof, and in particular to an IC with built-in self-test and a design method thereof employed in a sigma-delta analog-to-digital converter (&#39;SD-ADC), degrading difficulty in designing the circuit and preventing performance degradation of the circuit caused by thermal noise.  
         [0002]     Analog/mixed-signal testing requires a signal source generator and an analog response analyzer, which can be realized by many analog instruments/meters or by a mixed-signal automatic testing equipment externally. The testing always suffers from the I/O signal degradation or the noise effects on the analog stimulus and measurement. Any attempt to realize an on-chip analog/mixed-signal testing requires characterization and quantification of the signal source generator and the analog response analyzer first, which could be prohibitively expensive. The cost to test the analog portion of a mixed-signal device can be as high as 50% of the total cost.  
         [0003]     Over sampling analog-to-digital and digital-to analog converters (ADC and DAC) have become popular for high-resolution medium-to-low-speed applications. The use of shaped quantization noise applied to over sampling signals is commonly referred to as a sigma-delta (σΔ) modulation. The main advantage of the sigma-delta modulation is its higher resolution, but testing thereof requires better resolution than itself. This modulation can provide a deadlock problem in the on-chip analog testing.  
         [0004]     A digital stimulus measurement technique (DSMT) has been suggested in the related art. See C. K. Ong, K. T. Chen, and L. C. Wang, “Self-testing Second-Order Delta-Sigma Modulator Using Digital Stimulus” In Proc. VLSI Test Symposium, pp. 237-46, April 2002 (hereafter referred to as “related art”). According to the prior art, the test stimulus is a digital bit-stream transformed from a sinusoid wave by a software modulator as shown in  FIG. 1 .  FIG. 2  is a system block diagram of the delta-sigma modulator in  FIG. 1 . In testing mode, an analog input signal X 2  is disconnected from the modulator (SD-ADC)  20  and the bit-stream Si 2  amplitude is reduced to maintain stability of the modulator  20 . The amplitude reduction is accomplished by a gain module  22  of a design-for-test (Dft) circuit  21  of which the gain is ¼. In the related art, reference voltages are selected by the bit-stream Si 2 . The selected reference voltage is reduced by the gain module  22  and is then used to test the modulator  20 .  
         [0005]     Since the modulator  20  is a switch-capacitor (SC) type, the Dft circuit  21  requires a small capacitor. The capacitor can cause thermal noise, reducing performance degradation of the modulator  20 . The analysis of thermal noise is described below.  
         [0006]     It is assumed that the maximum value of the capacitor is 10 p, the max peak-to-peak signal is 1, and the over sampling rate is 400. When the Dft circuit  21  is not applied in the modulator  20 , the analysis of thermal noise is represented by the following formula:  
             NoisePower   =       KT   C     =         1.38   ×     10     -   23       ×   300       2   ×     10     -   12           =     2.07   ⁢   nV                     SNR   =           10   ⁢           ⁢     log   ⁡     (     SignalPower     2.07   ⁢   n       )         +     10   ⁢           ⁢     log   ⁡     (   OSR   )           ≈     103.7   ⁢           ⁢   dB       =     17.3   ⁢           ⁢   bit                 
 
         [0007]     When the Dft circuit  21  is applied in the modulator and the minimum capacitance of the capacitor is 0.75 p, the analysis of thermal noise is represented by the following formula:  
             NoisePower   =     74.3   ⁢   nV                 SNR   =           10   ⁢           ⁢     log   ⁡     (     SignalPower     74.3   ⁢   n       )         +     10   ⁢           ⁢     log   ⁡     (   OSR   )           ≈     99.4   ⁢           ⁢   dB       =     16.5   ⁢           ⁢   bit                 
        wherein, SNR represents signal-to-noise ratio, k Boltzmann constant, T absolute temperature, and ORS over sampling rate.        
 
         [0009]     According to the above analysis, the Dft circuit  21  with the capacitor causes resolution degradation of the modulator  20 .  
         [0010]     When designing an analog integrated circuit, the circuit size and cost are limited, causing performance of internal components therein to be insufficient, thus capacitors are limited to a maximum value. Therefore, when maximum capacitance does not change, the Dft circuit  21  causes resolution degradation, that is, performance degradation. Moreover, the technique of the related art is limited to application in one specific circuit, thus, the technique suggested by the related art is not capable of utilizing various circuits correctly.  
       SUMMARY  
       [0011]     Accordingly, embodiments of the invention provide an IC with built-in self-test that ameliorates disadvantages of the related art.  
         [0012]     Accordingly, an embodiment of the invention provides an IC with built-in self-test, and the IC comprises a sigma-delta analog-to-digital converter (SD-ADC) and a test circuit.  
         [0013]     The SD-ADC has a first and a second input terminals, receives a first and a second reference voltage signals, and comprises a first-stage translation unit with a first-stage gain and a second-stage translation unit with a second-stage gain. The test circuit tests the SD-ADC and receives a first stimulus, and a gain of the test circuit is set to 1.  
         [0014]     In a testing mode, the test circuit respectively provides a third reference voltage signal and a fourth reference voltage signal to the first and the second input terminals according to the first stimulus and the SD-ADC outputs a first digital signal. The third and fourth reference voltage signals are inverse to each other. In an operating mode, the test circuit respectively provides a first and a second analog signals to the first and the second input terminals according to the first stimulus and the SD-ADC outputs a second digital signal.  
         [0015]     A detailed description is given in the following embodiments with reference to the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     Various aspects of embodiments of the invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0017]      FIG. 1  is flow chart of a digital stimulus measurement technique of the related art.  
         [0018]      FIG. 2  is a system block diagram of the delta-sigma modulator with a test circuit in  FIG. 1 .  
         [0019]      FIG. 3   a  is a block diagram of a conventional second-order SD-ADC.  
         [0020]      FIG. 3   b  shows circuit of the conventional second-order SD-ADC in  FIG. 3   a.    
         [0021]      FIG. 4  is a systemic block diagram of an IC with built-in self-test according to an embodiment of the invention.  
         [0022]      FIG. 5  shows a circuit of the IC with built-in self-test according to an embodiment of the invention.  
         [0023]      FIG. 6  is a diagram of simplifying the parameters of the IC with built-in self-test.  
         [0024]      FIGS. 7 and 8  show the effect on SNR by applying the variant second-stage gain a 52 .  
         [0025]      FIGS. 9 and 10  show simulation results of the ratio of the signal Vref 1 + to the signal Vin+ at some values of the first-stage gain a 51 .  
         [0026]      FIG. 11  is a spectrum diagram of the SD-ADC  52  tested by an analog stimulus.  
         [0027]      FIG. 12  is a spectrum diagram of the SD-ADC  52  tested by a digital stimulus.  
         [0028]      FIG. 13  is a flow chart of a design method for an IC with built-in self-test according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0029]      FIG. 3   a  is a block diagram of a conventional second-order sigma-delta analog-to-digital converter (SD-ADC). A feedback loop gain of a second-order SD-ADC  4  is set to be 1 to reduce the design complexity and the corresponding circuit is presented in  FIG. 3   b . A integrator  41  comprises a amplifier, two sampling capacitors and two integrating capacitors. The ratio of a capacitor C 42  to a capacitor C 41  and the ratio of a capacitor C 43  to a capacitor C 41  are chosen so as to realize a first-stage gain a 41  and a second-stage gain a 42  respectively. An embodiment of the invention provides a Dft circuit applied in the SD-ADC  4  of  FIG. 3   a.    
         [0030]     As above the described, when the capacitance becomes large, the resolution becomes high. If the capacitance is too large, however, circuit layout is difficult due to the size limitation. In order to achieve high OSR, the SD-ADC  4  is designed to have an appropriate capacitance to avoid the limitation related to thrust of switches and amplifiers within the circuit. In this embodiment of the invention, a signal frequency is set to be 22 k, a maximum capacitance 10 p, and OSR  400 , so that, SNR is equal to 17.3 bit.  
         [0031]      FIG. 4  is a systemic block diagram of an IC with built-in self-test according to an embodiment of the invention. The IC comprises a Dft circuit  51  and a second-order SD-ADC  52 . The SD-ADC  52  receives reference voltage signals Vref 1 + and Vref 1 − inverse to each other. In order to avoid performance degradation, a gain of the Dft circuit  51  is set to be 1. Referring to  FIG. 4 , in testing mode, the Dft circuit  51  receives a digital stimulus Si 5  to select reference voltage signals Vref 2 + and Vref 2 − and directly outputs them to the SD-ADC  52 . At the same time, quantization noise caused by the digital stimulus Si 5  is input to the SD-ADC  52 . The quantization noise is estimated by software simulation and then the measured SNR can be recovered. Therefore, the performance of the SD-ADC  52  is measured correctly.  
         [0032]      FIG. 5  shows a circuit of the IC with built-in self-test according to an embodiment of the invention. The circuit structure of the SD-ADC  52  is similar as that of the SD-ADC  4  in  FIG. 3   b . In the SD-ADC  52 , the ratio of a capacitor C 52  to a capacitor C 51  and the ratio of a capacitor C 53  to a capacitor C 51  correspond to a first-stage gain a 51  and a second-stage gain a 52  respectively. The Dft circuit  51  comprises an inverter  510  and switches  511  to  514 . The inverter  510  receives the digital stimulus Si 5  and outputs a signal Si 6  inverse to the digital stimulus Si 5 . The switches  511  and  512  are controlled by the digital stimulus Si 5  and the switches  513  and  514  are controlled by the signal Si 6 . Output terminals of the switches  511  and  513  are coupled to an input terminal In 50  of the SD-ADC  52  and output terminals of the switches  512  and  514  are coupled to an input terminal In 51  thereof. The switches  511  to  514  can be transistor switches.  
         [0033]     In operating mode, the switches  511  and  514  receive an analog input signal Vin+ and the switches  512  and  513  receive an analog input signal Vin− inverse to the analog input signal Vin+. A voltage level of the digital stimulus Si 5  is high and the inverter  510  outputs the signal Si 6  at low voltage level. Because the switches  511  and  512  are turned on and the switches  513  and  514  are turned off, the analog input signals Vin+ and Vin− are input to the input terminals In 50  and In 51  respectively. The SD-ADC  52  outputs a digital output signal Vout 50  according to the analog input signals Vin+ and Vin−.  
         [0034]     In testing mode, the switches  511  and  514  receive the reference voltage signal Vref 2 + and the switches  512  and  513  receive the reference voltage signal Vref 2 −. The digital stimulus Si 5  is a digital signal generated from a digital converter simulated by software. That is, the voltage level of the digital stimulus Si 5  is same as that of the digital output signal Vout 50 . When the voltage level of the digital stimulus Si 5  is high, that of the signal Si 6  low, so that, switches  511  and  512  are turned on and the switches  513  and  514  turned off. The reference voltage signals Vref 2 + and Vref 2 − are input to the input terminals In 50  and In 51  respectively. Similarly, when the voltage level of the digital stimulus Si 5  is low, that of the signal Si 6  high, so that, the switches  511  and  512  are turned off and the switches  513  and  514  turned on. The reference voltage signals Vref 2 − and Vref 2 + are input to the input terminals In 50  and In 51  respectively. As described above, each of the input terminals In 50  and In 51  receives the reference voltage signals Vref 2 + and Vref 2 − alternately. The SD-ADC  52  then outputs the digital output signal Vout 51  according to the reference voltage signals Vref 2 + and Vref 2 −.  
         [0035]     In an embodiment of the invention, there are many main parameters, such as, the first-stage gain a 51 , the second-stage gain a 52 , the reference voltage signals Vref 1 + and Vref 1 −, the analog input signals Vin+ and Vin− and the gain of the Dft circuit  51 . The reference voltage signals Vref 2 + and Vref 2 − are inverse to each other and so are the analog input signals Vin+ and Vin−. Through simulation, if the signals Vref 1 + and Vin+ are multiplied by two at the same time, the SNR of the SD-ADC  52  is not changed as shown in  FIG. 6 . Output swings of the integrators, however, are increased by two. In other words, when the ratio of the reference voltage signal Vref 1 + to the analog input signal Vin+ is fixed, SNR of the SD-ADC  52  is not changed. Thus, the number of variable parameters is reduced.  
         [0036]      FIGS. 7 and 8  show the effect of applying the variant second-stage gain a 52  on SNR. It is assumed that the reference voltage signal Vref 1 + is fixed and the gains a 51  and a 52  are variable. When the value of the first-stage gain a 51  is selected, the variant second-stage gain a 52  affects SNR slightly. Thus, the analysis of the variant second-stage gain a 52  is neglected and the dimension of the design parameters is reduced.  
         [0037]     In order to insert the Dft circuit  51  feasibly and easily, an embodiment of the invention provides a method for choosing the parameters. Taking a 16-bit circuit as an example, a ratio of the reference voltage signal Vref 1 + to the analog input signal Vin+ is defined as a new variable. After inserting the Dft circuit  51 , in order to keep stability, it has to fine the range of the ratio of the signal Vref 1 + to the signal Vin+ and the first-stage gain a 51 .  FIGS. 9 and 10  show simulation results of the ratio of the signal Vref 1 + to the signal Vin+ and the first-stage gain a 51 . When the gain of the Dft circuit  51  is 1 and the first-stage gain a 51  is between 0.2 and 0.45, the range of the ratio of the signal Vref 1 + to the signal Vin+ is shown in  FIG. 9 . When the gain of the Dft circuit  51  is 1 and the first-stage gain a 51  is between 0.46 and 0.55, the range of the ratio of the signal Vref 1 + to the signal Vin+ is shown in  FIG. 10 . The following formulas 2 and 3 are determined according to the closest curve and the errors between the formulas 2 and 3 and the real value are calculated with the formula 1.  
             error   =       ∑           ⁢         (     f   -     f   ^       )     2       f   2                   (     formula   ⁢           ⁢   1     )                         a   51     =       ⁢     0.2   ∼   0.45       ,           f   ^     min     ⁡     (   χ   )       ≤       vref1   +       vin   +       ≤         f   ^     max     ⁡     (   χ   )                           f   ^     min     ⁡     (   χ   )       =       ⁢   0.12                     f   ^     max     ⁡     (   χ   )       =       ⁢       1.5214   ×     10   3     ⁢     χ   4       -     2.1347   ×     10   3     ⁢     χ   3       ⁢           +                     ⁢       1.0454   ×     10   3     ⁢     χ   2       -     0.2078   ×     10   3     ⁢   χ     +   0.0161                 error   =       ⁢   0.019892                 (     formula   ⁢           ⁢   2     )                         a   51     =       ⁢     0.46   ∼   0.55       ,           f   ^     min     ⁡     (   χ   )       ≤       vref1   +       vref   +       ≤         f   ^     max     ⁡     (   χ   )                           f   ^     min     ⁡     (   χ   )       =       ⁢   0.12                     f   ^     max     ⁡     (   χ   )       =       ⁢         -   0.2735     ×     10   10     ⁢     χ   6       +     0.8261   ×     10   10     ⁢     χ   5       ⁢           -                     ⁢       1.0388   ×     10   10     ⁢     χ   4       +     0.6961   ×     10   10     ⁢     χ   3       -                     ⁢       0.2622   ×     10   10     ⁢     χ   2       +     0.0526   ×     10   10     ⁢   χ     -   0.0044                 error   =       ⁢       1.7178   ⁢           ⁢   e     -   007                   (     formula   ⁢           ⁢   3     )             
        wherein, f represents real SNR, {circumflex over (f)} min  a minimum simulate SNR, and {circumflex over (f)} max  a maximum simulate SNR.        
 
         [0039]     In a SC type SD-ADC, thermal noise seriously affects the performance thereof. The thermal noise can be determined by simulation with a Dft circuit. First, a Dft circuit  51  is applied in the SD-ADC  52  and the SD-ADC  52  is simulated based on the system of  FIG. 4 . The gain of the Dft circuit  51  is set to be 1, that is, the digital stimulus Si 5  with no amplitude decreased is applied to the SD-ADC  52 . Referring to the simulation result shown in Table 1, SNR of the SD-ADC  52  is 105.92 dB. The quantization noise referring to the digital stimulus Si 5  is calculated by software simulation and equal to 1.04 dB. The real SNR of 106.96 dB determined by adding 105.92 dB and 1.04 dB, as high as that of the original SD-ADC.  
         [0040]     Referring to the related art, a Dft circuit  21  is applied in a SD-ADC  20  and the second-order SD-ADC  20  is simulated based on the system of  FIG. 2 . The gain of the Dft circuit  21  is set to be ¼. The simulation result is shown in Table 2. Comparing the real SNR of this embodiment and the related art, the real SNR of this embodiment is almost equal to that of the original SD-ADC. Therefore, the SD-ADC  52  can be implemented without performance degradation.  
                                                             TABLE 1                                   SNR   Power   quantization   Real           (dB)   loss(dB)   noise(dB)   SNR(dB)                                        Original   106.97   0   0   106.97           SD-ADC           SD-ADC   105.92   0   1.04   106.96           52                      
 
         [0041]    
       
         
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                   
               
               
                   
                 SNR 
                 Power 
                 quantization 
                 Real 
               
               
                   
                 (dB) 
                 loss(dB) 
                 noise(dB) 
                 SNR(dB) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Original 
                 106.36 
                 0 
                 0 
                 106.36 
               
               
                   
                 SD-ADC 
               
               
                   
                 SD-ADC 
                 92.25 
                 12 
                 0 
                 104.25 
               
               
                   
                 20 
               
               
                   
                   
               
             
          
         
       
     
         [0042]      FIG. 11  is a spectrum diagram of the SD-ADC  52  tested by an analog stimulus.  FIG. 12  is a spectrum diagram of the SD-ADC  52  tested by a digital stimulus. Referring the spectrum diagrams in  FIGS. 11 and 12 , the built-in Dft circuit  51  can determine the performance of the IC according to this embodiment.  
         [0043]      FIG. 13  is a flow chart of a design method for an IC with built-in self-test according to an embodiment of the invention. Referring to  FIGS. 4 and 13 , a Dft circuit  51  is applied to the IC (step S 1 ). A testing mode is performed for a SD-ADC  52  (step S 2 ). It is judged whether the specification of the SD-ADC  52  conforms to a predetermined specification according to the test result (step S 3 ). When the specification of the SD-ADC  52  conforms to the predetermined specification, the Dft circuit  51  performs the testing mode (step S 4 ). When the specification of the SD-ADC  52  does not conform to the predetermined specification, the ratio of the reference voltage signal Vref 1 + t 0  to the analog input signal Vin+ is set to be a ratio parameter and the ratio parameter and the first stage gain a 51  are modified (step S 5 ). Noted that the predetermined specification serves for all requirements during the design flow.  
         [0044]     As the described above, the IC of the embodiment of the invention comprises a build-in Dft circuit and performs self-testing by a digital stimulus. Moreover, according to the design method of the embodiment of this invention, the design difficulty of the IC is reduced and the performance degradation caused by the thermal noise is prevented. The built-in Dft circuit is further applied in many IC with various specification.  
         [0045]     Finally, while embodiments of the invention have been described by way of example and in terms of the above, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 7