Patent Abstract:
A downconversion mixer includes a configurable gate or bulk bias voltage to allow calibration and correction of device offsets. Calibration may be performed on the configurable bias voltages to minimize IM2 distortion in the mixer. The techniques have minimal impact on voltage headroom, impose no requirement for a signal path to be phase-matched with a calibration path, and are particularly well-suited for passive mixers.

Full Description:
RELATED APPLICATIONS 
       [0001]    This application claims benefit of U.S. Provisional Application No. 60/972,719 titled “OFFSET CORRECTION FOR PASSIVE MIXERS,” filed Sep. 14, 2007, the entire disclosure of this application being considered part of the disclosure of this application. 
     
    
     TECHNICAL FIELD 
       [0002]    The disclosure relates to communications receivers and, more particularly, to offset correction techniques for mixers in communications receivers. 
       BACKGROUND 
       [0003]    In a digital communication system, a receiver receives a radio-frequency (RF) modulated signal from a transmitter. The receiver downconverts the received signal from RF to baseband, digitizes the baseband signal to generate samples, and digitally processes the samples to recover data sent by the transmitter. The receiver may use one or more downconversion mixers to downconvert the received signal from RF to baseband. 
         [0004]    An ideal mixer simply translates an input signal from one frequency to another without distortion. In integrated circuits, however, the mixer&#39;s performance may deviate from the ideal case due to mismatch between the transistors caused by, e.g., layout or process variations. Such mismatch may introduce distortion into the output of the mixer, leading to unwanted inter-modulation products. For example, in a mixer for a direct conversion receiver, second-order inter-modulation (IM2) products in particular may especially degrade the signal-to-noise ratio (SNR) at baseband. While symmetrical layout and differential signal processing can help reduce the effects of device mismatch, there may still be residual mismatch due to process limitations. 
         [0005]    Disclosed herein are techniques to provide for configurable parameters in a mixer to calibrate and correct for such mismatch, thereby minimizing mixer distortion. 
       SUMMARY 
       [0006]    An aspect of the present disclosure provides a receiver apparatus comprising a mixer operative to mix an input radio frequency (RF) signal with a local oscillator (LO) signal to generate a baseband signal, the mixer comprising first and second RF transistors to receive the input RF signal, the mixer further comprising first and second LO transistors to receive the LO signal, at least one of the transistors having a gate bias voltage that is variable in response to a configurable control signal. 
         [0007]    Another aspect of the disclosure provides a receiver apparatus comprising: a mixer operative to mix an input radio frequency (RF) signal with a local oscillator (LO) signal to generate a baseband signal, the mixer comprising first and second RF transistors to receive the input RF signal, the mixer further comprising first and second LO transistors to receive the LO signal, at least one of the transistors having a bulk bias voltage that is variable in response to a configurable control signal. 
         [0008]    Yet another aspect of the disclosure provides a method for downconverting a received signal, the method comprising providing a configurable control signal to a mixer, the control signal specifying a gate bias voltage of at least one transistor in said mixer; and downconverting said received signal by mixing said received signal with a local oscillator signal. 
         [0009]    Yet another aspect of the disclosure provides a method for downconverting a received signal, the method comprising providing a configurable control signal to a mixer, the control signal specifying a bulk bias voltage of at least one transistor in said mixer; and downconverting said received signal by mixing said received signal with a local oscillator signal. 
         [0010]    Yet another aspect of the disclosure provides a method for calibrating a mixer, the method comprising providing a signal input to the mixer; initializing at least one gate bias voltage of the mixer, and measuring an output characteristic of the mixer associated with the at least one initialized gate bias voltage; adjusting the at least one gate bias voltage of the mixer, and measuring the output characteristic of the mixer associated with the at least one adjusted gate bias voltage; based on the measured output characteristic of the mixer, determining a preferred setting for the at least one gate bias voltage of the mixer; and storing said preferred setting for use during operation of the mixer. 
         [0011]    Yet another aspect of the disclosure provides a method for calibrating first and second mixers in a receiver, the method comprising providing a signal input to the receiver; initializing at least one gate bias voltage of the first mixer, and measuring an output characteristic of the first mixer associated with the at least one initialized gate bias voltage; adjusting the at least one gate bias voltage of the first mixer, and measuring the output characteristic of the first mixer associated with the at least one adjusted gate bias voltage; based on the measured output characteristic of the first mixer, determining a preferred setting for the at least one gate bias voltage of the first mixer; and while setting the at least one gate bias voltage of the first mixer to the preferred setting, repeating the steps of adjusting, measuring and determining for the second mixer. 
         [0012]    Yet another aspect of the disclosure provides a method for calibrating a mixer, the method comprising providing a signal input to the mixer; initializing at least one bulk bias voltage of the mixer, and measuring an output characteristic of the mixer associated with the at least one initialized bulk bias voltage; adjusting the at least one bulk bias voltage of the mixer, and measuring the output characteristic of the mixer associated with the at least one adjusted bulk bias voltage; based on the measured output characteristic of the mixer, determining a preferred setting for the at least one bulk bias voltage of the mixer; and storing said preferred setting for use during operation of the mixer. 
         [0013]    Yet another aspect of the disclosure provides a method for calibrating first and second mixers in a receiver, the method comprising providing a signal input to the receiver; initializing at least one bulk bias voltage of the first mixer, and measuring an output characteristic of the first mixer associated with the at least one initialized bulk bias voltage; adjusting the at least one bulk bias voltage of the first mixer, and measuring the output characteristic of the first mixer associated with the at least one adjusted bulk bias voltage; based on the measured output characteristic of the first mixer, determining a preferred setting for the at least one bulk bias voltage of the first mixer; and while setting the at least one bulk bias voltage of the first mixer to the preferred setting, repeating the steps of adjusting, measuring and determining for the second mixer. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0014]      FIG. 1  shows a conventional circuit topology for a passive mixer. 
           [0015]      FIG. 2  depicts an embodiment wherein the DC gate bias voltages of the transistors are made configurable to correct for mismatch in transistors M 1 -M 4  of the mixer. 
           [0016]      FIG. 3  depicts a further embodiment wherein the bulk bias voltages, rather than the gate bias voltages, of the transistors are made configurable to correct for mismatch in transistors M 1 -M 4  of a mixer. 
           [0017]      FIG. 4  depicts a calibration mechanism for a receiver utilizing a mixer with configurable bias voltages as described herein. 
           [0018]      FIG. 5  depicts an embodiment of a method for calibrating a configurable mixer of the present disclosure to minimize second-order inter-modulation (IM2) products. 
           [0019]      FIG. 5A  depicts an alternative embodiment of a method for calibrating a configurable mixer of the present disclosure employing a potentially abbreviated number of steps compared to  FIG. 5 . 
           [0020]      FIG. 5B  depicts a hypothetical P |f1-f2|  vs. VC 1  relationship to illustrate the parameters cited above. 
           [0021]      FIG. 6  depicts one embodiment of a method that successively iterates an arbitrary number of times n to determine optimum control signals VC 1   best (n) and VC 2   best (n). 
           [0022]      FIG. 7  depicts an embodiment of a calibration mechanism for a radio having two mixers, e.g., a mixer for the in-phase (I) path and a mixer for the quadrature-phase (Q) path. 
           [0023]      FIG. 8  depicts an embodiment of a method for calibrating the I/Q mixers shown in  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    In accordance with the present disclosure, techniques are disclosed for calibrating and correcting offset in mixer devices. 
         [0025]      FIG. 1  shows a conventional circuit topology for a passive mixer. Note  FIG. 1  does not show the details of DC biasing and coupling. In  FIG. 1 , a first differential voltage V 1  (V 1 =V 1   P −V 1   N ) is mixed with a second differential voltage V 2  (V 2 =V 2   P −V 2   N ) to produce a differential current output IOUT (IOUT=IOUT P −IOUT N , wherein IOUT P  is defined as the current flowing out of terminal OUT P , and IOUT N  is the current flowing into terminal OUT N ). Assuming the transistors are matched, the output current may be approximated as: 
         [0000]    
       
         
           
             
               
                 
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         [0026]    where r ds  is the resistance between the drain (D) and source (S) (representatively labeled for transistor M 1  in  FIG. 1 ), μC OX  represents the transistor device parameter, W and L represent the width and length of each transistor, V T  represents the threshold voltage, and K represents a constant term. See, e.g., Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” (1998), page 341. 
         [0027]    In actual integrated circuits, device mismatch may introduce non-linear distortion into the output of the mixer, causing deviation of the mixer&#39;s input-output characteristics from the ideal scenario of Eq (1). To address the effects of mismatch, one or more bias voltages of transistors M 1 -M 4  may be adjusted according to the present disclosure. 
         [0028]      FIG. 2  depicts an embodiment wherein the DC gate bias voltages of the transistors are made configurable to correct for mismatch in transistors M 1 -M 4  of the mixer. Voltages VG M1 , VG M2 , VG M3 , and VG M4  represent the gate bias voltages of each of transistors M 1 -M 4 , respectively. The bias voltages may be coupled to the transistor gates by resistors R 1 -R 4 , which may nominally have the same resistances. By introducing intentional offsets in the gate bias voltages, mismatch between transistors M 1 -M 4  as well as resistors R 1 -R 4  can be corrected. In  FIG. 2 , capacitors C 1   P1 , C 1   N1 , C 1   P2 , C 1   N2 , C 2   P , and C 2   N  serve to couple only the AC components of the signals V 1  and V 2  to the mixer. 
         [0029]    Note that  FIG. 2  shows the bulk bias voltage VB to be constant for all transistors. However, the bulk bias voltages may also be made configurable in alternative embodiments described later herein. 
         [0030]    In an embodiment, the bias voltages VG M1 , VG M2 , VG M3 , and VG M4  may be directly set by externally supplied control signals VC 1 -VC 4  as follows: 
         [0000]      VG M1 =VC1,   Equations (2) 
         [0000]      VG M2 =VC2, 
         [0000]      VG M3 =VC3, and 
         [0000]      VG M4 =VC4. 
         [0000]    Thus VC 1 -VC 4  allow for four degrees of freedom in configuring the four gate bias voltages. 
         [0031]    In alternative embodiments, to simplify calibration, the degrees of freedom may be reduced by making some of the bias voltages non-configurable. In an embodiment, VG M1  and VG M3  can be made non-configurable, e.g., tied to on-chip voltage references, while VG M2  and VG M4  can be made independently configurable by control signals VC 1  and VC 2 . While this decreases the degrees of freedom in the configuration to two, it also allows for simpler calibration due to the fewer number of parameters. 
         [0032]    In another embodiment, the gate bias voltages may be specified as follows: 
         [0000]        VG   M2   =VG   M1   +VC 1, and   Equations (3) 
         [0000]        VG   M4   =VG   M3   +VC 2; 
         [0000]    where VG M1  and VG M3  are non-configurable, and VC 1  and VC 2  can be characterized as the configurable bias offset voltages between the transistors in each differential pair. 
         [0033]    In yet another embodiment, two out of the four gate bias voltages may be specified as follows: 
         [0000]        VG   M1   =VG   M1     —     nom   +VC 1, and   Equations (4) 
         [0000]        VG   M3   =VG   M3     —     nom   +VC 2; 
         [0000]    where VG M1     —     nom  and VG M3     —     nom  represent nominal values for VG M1  and VG M3 , respectively. The remaining gate bias voltages VG M2  and VG M4  may be made non-configurable and set at nominal voltages. 
         [0034]    In yet another embodiment, to simplify calibration even further, only one of the four gate bias voltages need be made configurable. 
         [0035]    In general, the bias voltages may be specified by the control signal or signals directly as in Equations (2), or indirectly by any linear or non-linear relationship, such as the relationships shown in Equations (3) and (4). 
         [0036]      FIG. 3  depicts a further embodiment wherein the bulk, rather than the gate, bias voltages of the transistors are made configurable to correct for mismatch in transistors M 1 -M 4  of a mixer. Voltages VB M1 , VB M2 , VB M3 , and VB M4  represent the bulk bias voltages of each of transistors M 1 -M 4 , respectively. By introducing intentional offsets in the bulk bias voltages, mismatch between transistors M 1 -M 4  can be corrected. Note that  FIG. 3  shows the gate bias voltage VG to be non-configurable for all transistors. However, the gate bias voltages may also be made configurable according to the embodiments previously described herein. 
         [0037]    Similar to the description for the gate bias voltages, control signals VC 1 -VC 4  may be used to control the bulk bias voltages in four degrees of freedom. The bulk bias voltages may also be configurable in fewer than four degrees of freedom to simplify calibration, as previously described for the gate bias voltages. The control signals may be related to the bulk bias voltages directly or indirectly by any predetermined transformation. 
         [0038]      FIG. 4  depicts a calibration mechanism for a receiver utilizing a mixer with configurable bias voltages as described herein. During normal operation, an antenna  400  is connected to a duplexer  402  via an antenna connector  401 . The duplexer  402  allows the antenna  400  to be shared between a transmit path (TX)  450  and a receive path (RX)  451 . During a calibration phase, the antenna connector  401  can be supplied with a signal Vs. In an embodiment, the antenna  400  is disconnected from the antenna connector  401  when Vs is supplied to the antenna connector  401 . In another embodiment (not shown), Vs can be supplied directly to the antenna  400  while connected to the antenna connector  401 , e.g., in the form of electromagnetic radiation. The signal Vs is input to a low-noise amplifier (LNA)  404 . In yet another embodiment (not shown), Vs can be supplied from the TX  450 . 
         [0039]    The output of the LNA is input to a mixer  406 , which may support the configurable gate or bulk bias voltages previously described. The mixer  406  mixes the LNA output with a local oscillator LO (not shown) to generate a mixed signal. In an embodiment, the LO output corresponds to the differential signal V 1  in  FIGS. 2  or  3 , and the LNA output corresponds to the differential signal V 2 . In another embodiment, the LO output and LNA output may be reversed. The output of the mixer  406  is provided to a baseband processor  408 . An output from the baseband processor  408  is supplied to a digital signal processor (DSP)  410 . 
         [0040]    Based on the output of the baseband processor  408 , the DSP  410  outputs digital signals  414 . In an embodiment, the digital signals  414  may comprise digital representations of the control signals VC 1 -VC 4 , or any subset of the control signals previously described herein. The digital signals  414  may be derived according to a calibration method to minimize IM2 products, to be described later herein, or the signals  414  may be derived according to any other method for any other purpose, e.g., minimizing other non-IM2 distortion. The digital signals  414  may be converted to analog voltages  416  by the digital-to-analog converter (DAC)  412 . The analog voltages  416  may be used to configure the bias voltages of the mixer  406  as described previously herein. 
         [0041]    The ranges over which control signals VC 1  and VC 2  are adjusted may be determined according to the mapping between the control signals and the specific bias voltage or voltages to be configured. In an embodiment, VC 1  and VC 2  adjust the offset between the gate bias voltages of the transistors in a differential pair, e.g., according to Equations (3). VC 1  may then be configured to range from a minimum of −V max     —     offset  to a maximum of +V max     —     offset , where V max     —     offset  is a parameter related to the full scale range of VC 1 . VC 2  can have a range identical to or different from that of VC 1 . 
         [0042]    To specify a range that goes from a negative voltage offset to a positive voltage offset, the DAC  412  may support signed digital representations of the control signals. In an embodiment, VC 1  can be represented by an eight-bit value programmed by the DSP  410  into an eight-bit register in the DAC  412 . In an embodiment, bits &lt; 7 : 6 &gt; of the register can be a code indicating the V max     —     offset  used to determine the full scale range of VC 1 , and bits &lt; 5 : 0 &gt; can specify the signed magnitude of the control signal VC 1 , with bit &lt; 5 &gt; being the sign bit. In an embodiment, the mapping of bits &lt; 7 : 6 &gt; to V max     —     offset  can be as follows: 
         [0000]                                TABLE I                       Bits &lt;7:6&gt;   V max     —     offset  [mV]                           00   37           01   19           10   10           11   62                        
Other digital control signals, e.g., VC 2 -VC 4  (if available), may be similarly represented if available.
 
         [0043]    Note the mechanism shown in  FIG. 4  is meant to illustrate only one embodiment of a calibration mechanism for the configurable mixers disclosed herein. Alternative embodiments may employ fewer or more functional blocks than shown in  FIG. 4 . In an embodiment, the digital signals  414  may be generated and supplied directly by the baseband processor  408 . In an alternative embodiment, they may be generated and supplied by modules not shown, e.g., by a microprocessor. 
         [0044]    Note that the DAC  412  depicted in  FIG. 4  may support any number of digital control inputs  414 , and output one or more analog voltages  416  associated with each digital control input. 
         [0045]      FIG. 5  depicts an embodiment of a method for calibrating a configurable mixer of the present disclosure to minimize second-order inter-modulation (IM2) products. The steps in  FIG. 5  are described with reference to the calibration mechanism shown in  FIG. 4 . However, the method of  FIG. 5  is equally applicable to calibration mechanisms other than the one shown in  FIG. 4 . For example, the method of  FIG. 5  does not necessarily require an antenna  400  or elements other than the mixer  406  in the underlying calibration mechanism. For example, the method of  FIG. 5  may utilize a microprocessor or other computing device in place of the DSP. 
         [0046]    In the method of  FIG. 5 , the mixer is configurable in two degrees of freedom via control signals VC 1  and VC 2 . However, the method can readily be extended to calibrate the mixer with fewer or more degrees of freedom in accordance with the principles disclosed previously herein. VC 1  and VC 2  may be used to set, for example, the gate bias voltages VG M1  and VG M3  as labeled in  FIG. 2 , or the bulk bias voltages VB M1  and VB M3  as labeled in  FIG. 3 . 
         [0047]    Referring to  FIG. 5 , at step  500 , the calibration mechanism of  FIG. 4  may be instructed to receive on a channel near the center of the frequency band of interest, such as 869-894 MHz corresponding to the cellular band, or 1930-1990 MHz corresponding to the personal communications service (PCS) band. This can be done by setting the frequency of the LO (not shown in  FIG. 4 ) to the frequency of the desired channel. The control signals VC 1  and VC 2  are both initially set to the minimum values within their respective ranges. At step  502 , a signal with two frequency tones, f 1  and f 2 , is supplied to the input of the LNA as input voltage Vs. In an embodiment, the tones f 1  and f 2  lie outside the channel of interest. In an embodiment of a direct conversion receiver for the W-CDMA standard, f 1  and f 2  differ by 200 kHz, such that their IM2 product lies within a baseband channel having a 1.92 MHz bandwidth. 
         [0048]    In the presence of second-order distortion in the mixer, the output of the mixer will contain a tone at the difference frequency |f 1 -f 2 |. At step  504 , the baseband  408  measures the power P |f1-f2|  of the tone present at the difference frequency |f 1 -f 2 |, and supplies the value of P |f1-f2  to the DSP. At step  506 , the DSP records the value of P |f1-f2|  with the associated value of VC 1 . At step  508 , the DSP determines whether the value of VC 1  has been increased to the maximum value within its range. If not, then the DSP increments VC 1  by a step size at step  510 , and returns to step  504 . If VC 1  has reached the maximum allowed value of VC 1 , then DSP proceeds to step  512 . At step  512 , the DSP analyzes the recorded values of P |f1-f2|  for all swept values of VC 1 , and determines the value of VC 1  associated with the lowest measured P|f 1 -f 2 |. This value of VC 1  may be referred to as VC 1   best . Also in step  512 , the value of VC 1  may be set at VC 1   best  for the remaining steps of  FIG. 5 . 
         [0049]      FIG. 5B  depicts a hypothetical P ″f1-f2|  vs. VC 1  relationship to illustrate the parameters cited above. Note  FIG. 5B  is provided for illustrative purposes only, and is not meant to limit the disclosed techniques to devices or parameters having any particular transfer characteristics. 
         [0050]    Note the method of  FIG. 5  may be designed to optimize for parameters other than or in addition to IM2 by simply replacing the checking for minimum P f1-f2|  with checking for a desired characteristic or characteristics of some other parameter or parameters. 
         [0051]    Returning to  FIG. 5 , VC 2  is next swept over a predetermined range while VC 1  is held constant at VC 1   best . In particular, step  514  initially commences with VC 2  set to the minimum value within its allowable range. At step  514 , the baseband again measures the power present at the difference frequency, and supplies the measured power value P |f1-f2|  to the DSP. At step  516 , the DSP records the measured P |f1-f2  with the associated value of VC 2 . At step  518 , the DSP determines whether the value of VC 2  has been increased to the maximum within its range. If not, the DSP increments VC 2  at step  520  and returns to step  514 . If VC 2  has reached the maximum allowed value of VC 2 , then the DSP proceeds to step  522 . At step  522 , the DSP analyzes the recorded values of P |f1-f2|  for all swept values of VC 2 , and determines the value of VC 2  associated with the lowest measured P |f1-f2 . This value of VC 2  may be referred to as VC 2   best . Once VC 2   best  is determined, the radio may exit calibration mode, and commence (or resume) normal operation. In an embodiment, during normal operation, the control signals VC 1   best  and VC 2   best  may be continuously supplied to the DAC to configure the bias voltages of the mixer as previously described herein. 
         [0052]    In an embodiment, VC 1  and VC 2  can each be incremented by a step size equal to the minimum resolution of the DAC during calibration. For example, in an embodiment wherein bits &lt; 5 : 0 &gt; of the DAC register specify the signed magnitude of VC 1 , the step size can be the voltage difference associated with the least-significant bit of bits &lt; 5 : 0 &gt;. 
         [0053]    In an alternative embodiment, to speed up calibration, the step size may be larger than the minimum resolution of the DAC. In this embodiment, the setting for VC 1   best  corresponding to the lowest IM2 product for the mixer may not be present in the recorded values of VC 1  vs. P |f1-f2| , as the best setting may have been “skipped” due to the larger step size. In this case, VC 1   best  may be determined by averaging the two values of VC 1  corresponding to the lowest and second-lowest values of P |f1-f2| . Alternatively, a predetermined offset may be added to the determined VC 1   best  to derive the actual control input supplied to the mixer. 
         [0054]      FIG. 5A  depicts an alternative embodiment of a method for calibrating a configurable mixer of the present disclosure employing a potentially abbreviated number of steps compared to  FIG. 5 . Steps in  FIG. 5A  correspond to similarly labeled steps in  FIG. 5 , with noted differences in steps  508 A and  51   8 A. In the embodiment of  FIG. 5A , rather than checking for whether the value of VC 1  has been increased to a maximum at a step  508 , the method at a step  508 A checks whether the currently measured value of P ″f1-f2|  is more than the previously measured value of P |f1-f2| . If so, the method advances to the calibration of VC 2 , without sweeping through the remaining values of VC 1 . The value of VC 1  corresponding to the P |f1-f2  measured prior to the detected increase can be taken as VC 1   best . A similar check can be performed for VC 2  at step  518 A. This embodiment effectively treats the local minimum for the measured P |f1-f2|  as the global minimum. This may speed up the calibration, as the desired values for VC 1  and VC 2  may be determined without sweeping through the entire range of either parameter. 
         [0055]    Note the methods depicted in  FIGS. 5 and 5A  can be readily applied to calibrate mixers having more or less than two configurable degrees of freedom by, for example, providing more or fewer steps than are shown. For example, in an embodiment, wherein only one control signal VC 1  is used to configure a mixer, the method of  FIG. 5  may be terminated after step  512 . In another embodiment, four control signals VC 1 -VC 4  may be determined by adding steps beyond  522  for determining VC 3  and VC 4 , while holding the previously optimized degrees of freedom constant at their determined optimum values. 
         [0056]    Note the calibration described in  FIGS. 5 and 5A  may be performed whenever the signal input Vs is known. In an embodiment, calibration can be done at the factory, when a chip is tested prior to shipping. In an embodiment, calibration can be done during normal operation as follows. Where full duplexing is supported (i.e., simultaneous transmission and reception by a single radio), TX  450  may transmit Vs, which is coupled to RX  451  through the residual coupling of the duplexer  402 . Note TX  450  may transmit Vs at a suitably high power level to overcome attenuation between the transmit path and receive path introduced by, for example, the duplexer  402  and/or TX/RX filters (not shown). 
         [0057]    In an embodiment, steps in addition to those shown in  FIG. 5  may be provided to further optimize IM2 for the mixer.  FIG. 6  depicts one embodiment of a method that successively iterates an arbitrary number of times n to determine optimum control signals VC 1   best (n) and VC 2   best (n). At step  600 , n is initialized to zero, and VC 1  and VC 2  may be initialized to the minimum voltages in their respective ranges VC 1   min  and VC 2   min . At step  602 , VC 2  is held constant, while VC 1  is swept over its range to locate a best setting VC 1   best (1). In an embodiment, the sweep can be done according to the method shown in either  FIG. 5  or  5 A. In other embodiments, other methods for determining VC 1   best  may be applied. At step  604 , VC 1  is held constant at VC 1   best (1), and VC 2  is swept over its range to locate a best setting VC 2   best (1). At step  606 , n is iterated by 1 to n=1, and steps  602 - 604  may be repeated (i.e., looped). 
         [0058]    Note the method shown in  FIG. 6  may generally be terminated at any arbitrary point in the loop. In an embodiment, the method is terminated when n reaches 1, i.e., only one iteration of the loop is run. In another embodiment, the method is terminated after step  702  with n=1, i.e., one-and-a-half iterations of the loop are run. In another embodiment, the method is terminated when the measured value of P |f1-f2|  for a newly determined VC 1   best (n) or VC 2   best (n) differs from the measured value of P |f1-f2|  for a previous VC 1   best (n−1) or VC 2   best (n−1), respectively, by an amount less than a predetermined threshold. 
         [0059]    Note the method depicted in  FIG. 6  can be readily applied to calibrate mixers having more than two configurable degrees of freedom by, for example, adding additional steps within the loop shown. 
         [0060]      FIG. 7  depicts an embodiment of a calibration mechanism for a radio having two mixers, e.g., a mixer for the in-phase (I) path and a mixer for the quadrature-phase (Q) path.  FIG. 7  shows an antenna  700  coupled to a duplexer  702  via antenna connector  701 . The LNA  704  output is provided to both an I mixer  706 A and a Q mixer  706 B. Each mixer can be made configurable according to the embodiments disclosed herein. The outputs of the mixers  706 A and  706 B are provided to the baseband  708 , and the baseband  708  provides signals to the DSP  710 . The DSP  710  generates digital signals VCI and VCQ  714 . VCI may comprise one or more control signals to configure the I mixer  706 A according to the present disclosure, and VCQ may likewise comprise one or more control signals to configure the Q mixer  706 B. Digital signals  714  are supplied to the DAC  712 , which converts the digital signals  714  to two sets of analog voltages  716 A and  716 B. Analog voltages  716 A are used to configure the I mixer  706 A, while analog voltages  716 B are used to configure the I mixer  706 B according to the techniques previously disclosed herein. 
         [0061]      FIG. 8  depicts an embodiment of a method for calibrating the I/Q mixers shown in  FIG. 7 . At step  800 , VCI and VCQ are initialized. At step  802 , an input signal Vs containing two tones is supplied to the LNA  704  in  FIG. 7 . At step  804 , best control signal or signals VCI best  are determined for the I mixer  706 A. Step  804  may utilize a method previously disclosed herein, or any other method, for deriving VCI best . At step  806 , best control signal or signals VCQ best  are determined for the Q mixer  706 B, while VCI is held at VCI best . 
         [0062]    In an embodiment, the method of  FIG. 8  may be further augmented by having step  806  loop back to step  804 , and determining a new value for VCI best  while holding VCQ fixed at VCQ best . This may be done an arbitrary number of times to obtain an optimal configuration for the control signals. 
         [0063]    Note the techniques of the present disclosure need not be limited to passive mixers. Active mixers such as those employing Gilbert multipliers may also employ the techniques disclosed. The appropriate modifications will be clear to those of ordinary skill in the art, and are contemplated to be within the scope of the present disclosure. 
         [0064]    Based on the teachings described herein, it should be apparent that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, the techniques may be realized using digital hardware, analog hardware or a combination thereof. If implemented in software, the techniques may be realized at least in part by a computer-program product that includes a computer readable medium on which one or more instructions or code is stored. 
         [0065]    By way of example, and not limitation, such computer-readable media can comprise RAM, such as synchronous dynamic random access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), ROM, electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. 
         [0066]    The instructions or code associated with a computer-readable medium of the computer program product may be executed by a computer, e.g., by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. 
         [0067]    A number of aspects and examples have been described. However, various modifications to these examples are possible, and the principles presented herein may be applied to other aspects as well. These and other aspects are within the scope of the following claims.

Technology Classification (CPC): 7