Patent Abstract:
A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal. In another embodiment, the initialization flag detection system includes a plurality of latches receiving the flag signals at their data inputs. The latches are clocked by respective strobe signals corresponding to the command clock signal, but having phases that differ from each other. The outputs of the latches are applied to a logic circuit, such as a NAND gate. Finally, in another embodiment of the invention, the bits of the command packet are sampled along with the flag signal and compared to the samples of the flag signal to detect when a command packet having a predetermined pattern does not correspond to a flag signal having a predetermined pattern.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 09/141,476, filed Aug. 27, 1998 is now U.S. Pat. No. 6,167,495. 
    
    
     TECHNICAL FIELD 
     The present invention relates to packetized dynamic random access memory devices, and more particularly, to a method in apparatus for detecting a signal indicating the start of an initialization procedure that adjusts the timing of an internal clock signal used to strobe the initialization signal and a command packet. 
     BACKGROUND OF THE INVENTION 
     Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices. 
     Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of the computer system, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 200 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components. 
     Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 200 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices. 
     System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory. 
     A solution to this operating speed disparity has been proposed in the form of a computer architecture known as “SyncLink.” In the SyncLink architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus. 
     An example of a computer system  10  using the SyncLink architecture is shown in FIG.  1 . The computer system  10  includes a processor  12  having a processor bus  14  coupled to three packetized dynamic random access memory or SyncLink DRAM (“SLDRAM”) devices  16   a-c  through a memory controller  18 . The computer system  10  also includes one or more input devices  20 , such as a keypad or a mouse, coupled to the processor  12  through the processor bus  14 , a bus bridge  22 , and an expansion bus  24 , such as an Industry Standard Architecture (“ISA”) bus or a Peripheral Component Interconnect (“PCI”) bus. The input devices  20  allow an operator or an electronic device to input data to the computer system  10 . One or more output devices  30  are coupled to the processor  12  to display or otherwise output data generated by the processor  12 . The output devices  30  are coupled to the processor  12  through the expansion bus  24 , bus bridge  22  and processor bus  14 . Examples of output devices  24  include printers and a video display units. One or more data storage devices  38  are coupled to the processor  12  through the processor bus  14 , bus bridge  22 , and expansion bus  24  to store data in or retrieve data from storage media (not shown). Examples of storage devices  38  and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives. 
     In operation, the processor  12  communicates with the memory devices  16   a-c  via the memory controller  18 . The memory controller  18  sends the memory devices  16   a-c  command packets that contain both control and address information. Data is coupled between the processor  12  and the memory devices  16   a-c  through the memory controller  18  and the processor bus  14 . Although all the memory devices  16   a-c  are coupled to the same conductors of the memory controller  18 , only one memory device  16   a-c  at a time reads or writes data, thus avoiding bus contention. Bus contention is avoided by each of the memory devices  16   a-c  having a unique identifier, and the command packet containing an identifying code that selects only one of these components. 
     The computer system  10  also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices  16   a-c  also receive a command clock signal to provide internal timing signals, a data clock signal clocking data into the memory device  16 , and a FLAG signal signifying the start of a command packet. 
     One of the memory devices  16   a  is shown in block diagram form in FIG.  2 . The memory device  16   a  includes a clock generator circuit  40  that receives a command clock signal CMDCLK and generates an internal clock signal ICLK and a large number of other clock and timing signals to control the timing of various operations in the memory device  16 . The memory device  16  also includes a command buffer  46  and an address capture circuit  48 , which receive the internal clock signal ICLK, a command packet CA 0 -CA 9  on a 10-bit command bus  50 , and a FLAG signal on line  52 . The memory controller (not shown) or other device normally transmits the command packet CA 0 -CA 9  to the memory device  16   a  in synchronism with the command clock signal CMDCLK. As explained above, the command packet, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence, as described in greater detail below. The command buffer  46  receives the command packet from the bus  50 , and compares at least a portion of the command packet to identifying data from an ID register  56  to determine if the command packet is directed to the memory device  16   a  or some other memory device  16   b, c.  If the command buffer  46  determines that the command packet is directed to the memory device  16   a,  it then provides the command words to a command decoder and sequencer  60 . The command decoder and sequencer  60  generates a large number of internal control signals to control the operation of the memory device  16   a  during a memory transfer. 
     The address capture circuit  48  also receives the command words from the command bus  50  and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer  64 , which generates a corresponding 3-bit bank address on bus  66 , a 10-bit row address on bus  68 , and a 7-bit column address on bus  70 . The column address and row address are processed by column and row address paths  73 ,  75  as will be described below. 
     One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM  16   a  shown in FIG. 2 largely avoids this problem by using a plurality of memory banks  80 , in this case eight memory banks  80   a-h.  After a memory read from one bank  80   a,  the bank  80   a  can be precharged while the remaining banks  80   b-h  are being accessed. Each of the memory banks  80   a-h  receive a row address from a respective row latch/decoder/driver  82   a-h.  All of the row latch/decoder/drivers  82   a-h  receive the same row address from a predecoder  84  which, in turn, receives a row address from either a row address register  86 , redundant row circuit  87 , or a refresh counter  88 , as determined by a multiplexer  90 . However, only one of the row latch/decoder/drivers  82   a-h  is active at any one time, as determined by bank control logic  94  as a function of a bank address from a bank address register  96 . 
     The column address on bus  70  is applied to a column latch/decoder  100 , which supplies I/O gating signals to an I/O gating circuit  102 . The I/O gating circuit  102  interfaces with columns of the memory banks  80   a-h  through sense amplifiers  104 . Data is coupled to or from the memory banks  80   a-h  through the sense amplifiers  104  and the I/O gating circuit  102  and a data path subsystem  108 , which includes a read data path  110  and a write data path  112 . The read data path  110  includes a read latch  120  that stores data from the I/O gating circuit  102 . In the memory device  16   a  shown in FIG. 2, 64 bits of data are stored in the read latch  120 . The read latch then provides four 16-bit data words to an output multiplexer  122  that sequentially supplies each of the 16-bit data words to a read FIFO buffer  124 . Successive 16-bit data words are clocked into the read FIFO buffer  124  by a clock signal RCLK generated by the clock generator  40 . The 16-bit words are then clocked out of the read FIFO buffer  124  by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit  126 . The read FIFO buffer  124  sequentially applies the 16-bit words to a driver circuit  128  in synchronism with the delayed RCLK signal. The driver circuit, in turn, applies the 16-bit data words to a data bus  130 . The driver circuit  128  also applies the delayed RCLK signal to a clock line  132  as the DCLK signal. The programmable delay circuit  126  is programmed during initialization of the memory device so that the read data as received by the controller (not shown) processor, or other device has the optimum phase relative to DCLK signal at the controller, processor or other device for the DCLK signal to clock the read data into the memory controller (not shown), processor, or other device. 
     The write data path  112  includes a receiver buffer  140  coupled to the data bus  130 . The receiver buffer  140  sequentially applies 16-bit words from the data bus  130  to four input registers  142 , each of which is selectively enabled by a signal from a clock generator circuit  144 . The clock generator circuit generates these enable signals responsive to the data clock DCLK, which, for write operations, is applied to the memory device  16   a  on line  132  from the memory controller, processor, or other device. As with the command clock signal CMDCLK and command packet CA 0 -CA 9 , the memory controller or other device (not shown) normally transmits the data to the memory device  16   a  in synchronism with the data clock signal DCLK. The clock generator  144  is programmed during initialization to adjust the timing of the clock signal applied to the input register  142  relative to the DCLK signal so that the input registers can capture the write data at the proper times. Thus, the input registers  142  sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer  148 . The data are clocked into the write FIFO buffer  148  by a clock signal from the clock generator  144 , and the data are clocked out of the write FIFO buffer  148  by an internal write clock WCLK signal. The WCLK signal is generated by the clock generator  40 . The 64-bit write data are applied to a write latch and driver  150 . The write latch and driver  150  applies the 64-bit write data to one of the memory banks  80   a-h  through the I/O gating circuit  102  and the sense amplifiers  104 . 
     Portions of the command buffer  46  is illustrated in greater detail in FIG.  3 . With reference to FIG. 3, a command packet CA consisting of a plurality of packet words is applied to a shift register  202  via the command bus  50 . The width of the bus  204  corresponds to the width of the shift register  202 , and the number of packet words in the command packet corresponds to the number of stages of the shift register  202 . In the embodiment shown in FIG. 3, the shift register  202  has four stages, each of which is 10 bits wide. Thus, the shift register  202  sequentially receives four 10-bit packet words CA&lt; 0 : 9 &gt;. Each of the four packet words is shifted into the shift register  202 , and from one shift register stage to the next, responsive to each transition of the internal clock signal ICLK. 
     Coincident with the start of each command packet during normal operation of the memory device  16   a,  the FLAG signal transitions high for one-half of the period of the internal clock signal ICLK. The flag signal FLAG, which is coupled to the memory device  16   a  via the flag line  52 , is also applied to the shift register  202 . In normal operation, the high FLAG signal is shifted through each of the four stages of the shift register  202  responsive to each transition of the ICLK signal. As a result, the F&lt; 0 &gt; bit of the shift register  202  transitions high on the transition of the ICLK signal following the FLAG signal transitioning high. On the next transition of the ICLK signal, the F&lt; 0 &gt; bit transitions low and the F&lt; 1 &gt; bit transitions high, on the next transition of the ICLK signal the F&lt; 1 &gt; bit transitions low and the F&lt; 2 &gt; bit transitions high, etc. Thus, in normal operation, only one F&lt; 3 : 0 &gt; bit is high at a time. 
     When four packet words have been shifted into the shift register  202 , an F&lt; 3 &gt; signal is generated at the output of the shift register  202 . The F&lt; 3 &gt; signal then loads the 40 bit contents of the shift register  202  into a storage register  208 . In the embodiment shown in FIG. 3 in which four 10-bit packet words are shifted into the shift register  202 , the storage register  208  receives and stores a 40-bit command word in addition to shifting the FLAG signal through the shift register  202 . However, in the more general case, the shift register  202  has N+1 stages, each of which has a width of M bits, and the storage register  208  loads an M*N bit command word. After the storage register  208  has been loaded, it continuously outputs the M*N bit command word Y&lt; 39 : 0 &gt;. 
     As further shown in FIG. 3, the internal clock signal ICLK is generated from the command clock signal CMDCLK by the clock generator  40 . The phase of the internal clock signal ICLK relative to the phase of the command clock signal CMDCLK controlled by and the phases of the DCLK and WCLK signals are controlled by respective values of PHASE bits, which are generated by a logic circuit (not shown in FIG.  3 ). The values of PHASE are determined during initialization, as described above and in greater detail in U.S. patent application Ser. No. 08/890,055 to Baker et al., which is incorporated herein by reference. 
     It will be understood that necessary portions of the command buffer and clock generator circuit  200  have been omitted from FIG. 3 in the interests of brevity since they are somewhat peripheral to the claimed invention. For example, the command buffer  48  will contain circuitry for allowing the command buffer to determine if a command packet is directed to it, circuitry for pipelining command words output from the storage register  208 , circuitry for generating lower level command signals from the command word, etc. 
     The relevant portions of the clock generator circuit  40  and the command buffer  46  are shown in greater detail in the block diagram of FIG.  4 . As shown in FIG. 4, a timing control circuit  206  includes a clock circuit  220  that receives a clock signal CLK and its quadrature CLK 90  from a conventional quadrature circuit  222  responsive to the internal clock signal ICLK. The internal clock signal ICLK is generated by the clock control circuit  40  from the command clock signal CMDCLK, as explained above with reference to FIG.  3 . The CLK and CLK 90  signals are applied to a NOR gate  232 , which outputs a high whenever ICLK and ICLK 90  are both low. The output of the NOR gate  232  is applied through a first inverter  234  to generate a CLK 1  signal and then through a second inverter  236  to generate a CLK 1 * signal (the “*” symbol after a signal name is used throughout to designate the compliment of the signal). 
     The CLK 90  and CLK signals are also applied to a NAND gate  240 . which outputs a low whenever both CLK and CLK 90  are high. The output of the NAND gate  240  is coupled through an inverter  242  to generate a CLK 0  signal and then through a second inverter  244  to generate a CLK 0 * signal. These CLK 0 , CLK 0 *, CLK 1 , and CLK 1 * signals correspond to the ICLK signal described with reference to FIG.  3 . 
     The clock generator circuit  40  also includes a pair of shift register circuits  246 ,  248  that are part of the shift register  202 . The shift register circuits  246 ,  248  are connected in series with each other to form an 8-stage shift register. The shift register circuit  246  receives the FLAG signal, and the FLAG signal is then sequentially shifted through the four stages of the shift register circuit  246  and the four stages of the shift register circuit  248  responsive to the CLK 0 , CLK 0 *, CLK 1 , and CLK 1 * signals. As mentioned above, the FLAG signal is shifted through two stages of the shift register circuits  246 ,  248  each cycle of the CLK signals. Thus, when FLAG goes high, two successive F&lt; 0 : 7 &gt; outputs of the shift register circuits  246 ,  248  sequentially go high each clock cycle. 
     The shift register  202  shown in FIG. 4 also includes ten separate shift register circuits  250   a-j,  each of which receives a respective bit CA 0 -CA 9  of the incoming 10-bit packet word coupled through respective buffers  251   a-j.  Each of the shift register circuits  250   a-j  includes four shift register stages. Thus, after four clock cycles, four packet word bits CA have been shifted into each shift register circuit  250 , and all four of these bits are available as a 4-bit word B&lt; 0 : 3 &gt;. Thus, the ten shift register circuits  250   a-j  collectively store and then output the 40-bit command word C&lt; 0 : 39 &gt;. 
     The storage register  208  also receives the CLK and CLK  90  signals. However, bits B&lt; 0 : 3 &gt; for the four packet words stored in the shift register  202  are not latched into the storage register  208  until the F&lt; 3 &gt; signal is generated, as explained above. The F&lt; 3 &gt; signal is generated four transitions of the CLK signal after receipt of the FLAG signal, i.e., after four command packets have been shifted into the shift register  202 . The storage register then stores and continuously outputs the 40-bit command word Y&lt; 0 : 39 &gt;. The command word Y&lt; 0 : 39 &gt; is used to control the operation of a memory device containing the command buffer  46  and clock generator circuit  40 . 
     The structure and operation of the command buffer  46  are described in greater detail in U.S. patent application Ser. No. 08/994,461 to Manning, which is incorporated herein by reference. 
     It is important that the clock signals generated from the ICLK signal be applied to the shift registers  250   a-j  at the proper time so that packet words CA 0 - 9  on the command bus  50  are latched when valid packet words are present on the command bus  50 . Similarly, it is important that the clock signals generated from the ICLK signal be applied to the shift registers  246 ,  248  at the proper time so that the FLAG signal on the flag line  52  are latched when a valid FLAG signal is present on the flag line  52 . If the ICLK signal does not latch the FLAG signal at the proper time, the memory device  16   a  will fail to recognize the start of a command packet or it may fail to do so at the proper time. At higher operating speeds, it can become very difficult to ensure that the ICLK signal has the proper timing to accurately latch the command packet and the FLAG signal. 
     Even if the timing at which the CMDCLK signal, the command packet CA, and the FLAG signal are applied to the memory device  16   a  could be precisely controlled, it would be difficult to precisely control or predict the propagation delay of these signals within the memory device  16   a.  For example, internal signals require time to propagate to various circuitry in the memory device  16   a.  Differences in the signal path lengths can cause differences in the times at which signals reach the circuitry. Differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry. These differences in arrival times can become significant at high operating speeds, and eventually limit the operating speed of memory devices. 
     The difficulty in clocking the packet words CA 0 - 9  and the FLAG signal into the shift registers at the proper time can be explained with reference to FIG. 5. A bit of a command packet or the FLAG signal is shown in the upper portion of FIG. 5 having a leading edge occurring at t 1  and a trailing edge occurring at t 5 . The internal clock signal is shown having a rising edge occurring at t 3 , which is midway between t 1  and t 5 . However, as explained above, a variety of factors can alter the relative timing of the packet words and the FLAG signal relative to the ICLK signal as those signals are coupled to the memory device  16   a  and propagate through the memory device  16   a  to the shift register  202 . As a result, the packet words CA 0 - 9  and the FLAG signal may have a phase relative to each other that varies considerably. The packet word CA 0 - 9  and the FLAG signal may be applied to the shift registered  202  at a time relative to the ICLK signal starting at t 0 , in which case it would terminate at time t 2 . The packet word CA 0 - 9  and the FLAG signal may also be applied to the shift registered  202  at a time relative to the ICLK signal starting at t 4 , in which case it would terminate after time t 5 . Under these circumstances, the transition of the ICLK must occur during the shaded portion of the packet word CA 0 - 9  and FLAG signal between t 2  and t 4 . It can therefore be seen that there is very little tolerance in the phase of the ICLK signal relative to the phases of the packet word CA 0 - 9  and the FLAG signal. 
     The command buffer  46  illustrated in FIGS. 3 and 4 is able to precisely control the timing of the ICLK signal because the clock control circuit  40  adaptively adjusts the phase of the ICLK signal relative to the CMDCLK signal so that the shift register  202  is clocked at the proper time. As explained in greater in the above-cited U.S. patent application Ser. No. 08/890,055 to Baker et al., during initialization of the memory device  16   a,  an initialization packet having a known data pattern is repetitively applied to the shift register  202  along with an initialization FLAG signal. As explained above, the initialization FLAG signal is a FLAG signal that is initially high for a duration that is twice the duration of the FLAG signal during normal operation. Thus, two adjacent FLAG bits, e.g., F&lt; 0 &gt; and F&lt; 1 &gt;, can both be logic “1”. In contrast, as mentioned above, only one FLAG bit can be logic “1” during normal operation of the memory device  16   a.  The NAND gate  212  (FIGS. 3 and 4) is used to detect the initialization FLAG signal by detecting when the F&lt; 0 &gt; and F&lt; 1 &gt; FLAG bits are both logic “1”. 
     As further described in the Baker et al. application, during the initialization process, a predetermined initialization packet and a predetermined pattern of FLAG bits are repetitively shifted into the shift register  202 . The packet words in the initialization packet and the FLAG bits are repetitively stored in the shift register  202  using different phases of the ICLK signal, as determined by an internal logic circuit (not shown). The bits of the packet words and the FLAG bits stored in the shift register  202  responsive to each phase of ICLK are then examined, and a determination is made of which phase of the ICLK signal was best able to capture the packet words and FLAG bits. The logic circuit then applies PHASE bits corresponding to the optimum phase of the ICLK signal to the clock generator  40 . Thereafter, the clock generator  40  delays the ICLK signal relative to the CMDCLK signal so that the transition of the ICLK signal occurs at the approximate center of the capture window between t 2  and t 4 , as illustrated in FIG.  5 . 
     As explained above, during normal operation of the memory device  16   a,  the FLAG signal transitions high for one bit, as illustrated in FIG.  6 . As further shown in FIG. 6, the ICLK signal has been adjusted during the initialization procedure explained above so that it transitions at the center of the FLAG bit. The high FLAG signal is clocked into the shift registered  202  thereby making the F&lt; 0 &gt; bit logic “1.” On each successive transition of the ICLK signal, the logic “1” is shifted through each successive stage of the shift register  202 , thereby sequentially making each of the F&lt; 1 &gt;-F&lt; 7 &gt; bits logic “1”. The logic level clocked into the shift register  202  is shown below each of the strobe arrows coincident with each transition of the ICLK signal. 
     The initialization FLAG signal is shown to being clocked into the shift register  202  in FIG.  7 . As mentioned above, the initialization FLAG signal is twice the width of the FLAG signal occurring during normal operation. The ICLK signal is shown in FIG. 7 with its transitions occurring at the 25% and 75% portions of the double—width FLAG signal. The FLAG signal as stored in the shift register  202  is thus “0” “1” “1” “0” “0” “0”, etc. so that at the second transition of ICLK, the F&lt; 0 &gt; and F&lt; 1 &gt; bits are both logic “1”, which is detected by the NAND gate  212 . 
     The ICLK signal is shown in FIGS. 6 and 7 as having a phase relative to the phase of the FLAG signal that allows the ICLK signal to accurately strobe the FLAG signal. Proper phasing of the ICLK signal is insured by the initialization procedure for normal operation, as illustrated in FIG.  6 . However, since the initialization FLAG signal shown in FIG. 7 is generated to signify the start of the initialization procedure, the initialization procedure has not yet occurred when the initialization FLAG signal is applied to the shift register  202 . Therefore, it is possible for the phase of the ICLK signal relative to the phase of the initialization FLAG signal to be as illustrated in FIG.  8 . Under these conditions, the transitions of the ICLK signal coincide with the transitions of the initialization FLAG signal so that the logic level clocked into the shift register  202  on those transitions of ICLK is indeterminate. However, the transition of ICLK occurring at the center of the initialization FLAG signal is properly registered as a logic “1”. The initialization FLAG signal as stored in the shift register  202  could thus be “110” to properly signify the start of the initialization procedure, but it could also be “010” to signify a normal FLAG signal or “111”, which signifies neither a normal FLAG signal nor an initialization FLAG signal. 
     The need to select the phase of the ICLK signal during the initialization procedure before the initialization FLAG signal signifying the start of the initialization procedure can be accurately detected creates an apparent inability to reliably initiate the initialization procedure. As a result, although the above—described initialization procedure is capable of insuring accurate synchronization of the ICLK signal to the packet words CA 0 - 9  and the FLAG signal, there is no apparent technique for reliably detecting the initialization FLAG signal in order to initiate the initialization procedure. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a method and apparatus for detecting an initialization flag signal in a packetized DRAM. The DRAM is adapted to receive a command packet, a command clock, and either the initialization flag signal or a normal flag signal, which are applied to a flag input terminal of the DRAM. The initialization flag signal is received prior to initialization of the DRAM, and the normal flag signal is received during normal operation of the DRAM. The normal flag signal has a duration that is substantially shorter than, preferably half, the duration of the initialization flag. In accordance with the inventive method and apparatus, the flag input terminal is sampled by a suitable device, such as a plurality of latches or a shift register. The flag input terminal is sampled at a rate that is sufficiently high than a plurality of samples, preferably at least 4, are taken during the duration of the initialization flag signal. The number of contiguous samples corresponding to a predetermined logic level, such as the logic level of the flag signals, is determined. A determination is then made whether the number of these contiguous samples were taken over duration that is longer than the duration of the normal flag signal. In another aspect of the invention, a command packet and a flag signal having predetermined patterns are applied to the DRAM. The bits of the command packet are then sampled along with the flag signal, and the samples of the flag signal are compared to the samples of each bit of the command packet. If the comparison indicates that the pattern of the flag signal does not correspond to the pattern of the command packet, an error signal is generated. The inventive method and apparatus may be included in a command buffer for the packetized DRAM, and the packetized DRAM incorporating the inventive method and apparatus may be used in a computer system. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a conventional computer system using a plurality of SyncLink packetized memory devices. 
     FIG. 2 is a block diagram of a conventional packetized DRAM used in the computer system of FIG.  1 . 
     FIG. 3 is a block diagram of a preferred embodiment of a portion of a command buffer and clock generator circuit in accordance with the invention that is usable in the packetized DRAM of FIG.  2 . 
     FIG. 4 is a more detailed block diagram of the portion of the command buffer and clock generator circuit shown in FIG.  3 . 
     FIG. 5 is a timing diagram illustrating a capture window corresponding to phases of the ICLK signal that are capable of accurately strobing packet words CA 0 - 9  and a FLAG signal into a shift register in the command buffer of FIGS. 3 and 4. 
     FIG. 6 is a timing diagram illustrating the ICLK signal strobing the FLAG signal into a shift register in the command buffer of FIGS. 3 and 4. 
     FIG. 7 is a timing diagram illustrating the ICLK signal having a first phase relative to the phase of an initialization FLAG signal strobing the initialization FLAG signal into a shift register in the command buffer of FIGS. 3 and 4. 
     FIG. 8 is a timing diagram illustrating the ICLK signal having a second phase relative to the phase of the initialization FLAG signal unsuccessfully attempting to strobe the initialization FLAG signal into a shift register in the command buffer of FIGS. 3 and 4. 
     FIG. 9 is a block diagram of the command buffer of FIG. 3 having an initialization FLAG Detector in accordance with one embodiment of the invention. 
     FIG. 10 is a timing diagram showing the operation of the command buffer of FIG. 9 upon receipt of an initialization FLAG signal having a first phase relationship with an internal clock signal. 
     FIG. 11 is a timing diagram showing the operation of the command buffer of FIG. 9 upon receipt of a normal FLAG signal having a first phase relationship with an internal clock signal. 
     FIG. 12 is a timing diagram showing the operation of the command buffer of FIG. 9 upon receipt of an initialization FLAG signal having a second phase relationship with an internal clock signal. 
     FIG. 13 is a timing diagram showing the operation of the command buffer of FIG. 9 upon receipt of a normal FLAG signal having a second phase relationship with an internal clock signal. 
     FIG. 14 is a block diagram of one embodiment of a Initialization Flag Detector that may be used in the command buffer of FIG.  9 . 
     FIG. 15 is a timing diagram showing the operation of the Initialization Flag Detector of FIG. 14 upon receipt of an initialization FLAG signal. 
     FIG. 16 is a timing diagram showing the operation of the Initialization Flag Detector of FIG. 14 upon receipt of a normal FLAG signal. 
     FIG. 17 is a block diagram of another embodiment of a Initialization Flag Detector that may be used in the command buffer of FIG.  9 . 
     FIG. 18 is a timing diagram showing the operation of the Initialization Flag Detector of FIG. 17 upon receipt of an initialization FLAG signal. 
     FIG. 19 is a timing diagram showing the operation of the Initialization Flag Detector of FIG. 17 upon receipt of a normal FLAG signal. 
     FIG. 20 is a timing diagram showing a pattern of signals that can be applied to the FLAG line and command bus during initialization, and also showing the operation of an Error Detector Circuit shown in FIG.  21 . 
     FIG. 21 is a block diagram of one embodiment of an Error Detection Circuit that may be used in the command buffer of FIG.  9 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     One embodiment of a command buffer  300  in accordance with the invention is illustrated in FIG.  9 . The command buffer  300  includes the shift register  202 , the storage register  208  and the clock generator circuit  40  from the command buffer  48  of FIG.  3 . These components operate in the same manner as explained above unless otherwise noted. Therefore, their operation will not be repeated with reference to FIG.  9 . The command buffer  300  does not include the NAND gate  212  of FIG. 3 because the INIT* signal is instead generated by an Initialization Flag Detector  306 . 
     The Initialization Flag Detector  306  receives the FLAG signal and a flag clock signal FCLK. As explained further below, the FCLK signal has a frequency that is higher than the frequency of the internal clock signal ICLK. The FCLK signal is preferably generated from the ICLK signal and is preferably an integer of multiple of the ICLK signal. However, the FCLK signal may be generated independently of the ICLK signal as long as it has a frequency that is higher than the frequency of the ICLK signal. 
     The operation of the initialization applied detector  306  can best be explained with reference to FIG.  10 . As illustrated in FIG. 10, the FCLK signal has a frequency that is twice the frequency of the FCLK signal. Since the width of the initialization FLAG signal is equal to the period of the ICLK signal there are at least 4 transitions of the FLAG signal during every initialization FLAG signal. 
     The logic levels strobed by the FCLK signal in the Initialization Flag Detector  306  are indicated in the fourth line of FIG.  10 . As shown therein, the initialization FLAG signal results in 4 logic “1” samples being strobed. In contrast, as shown in FIG. 1, the normal FLAG signal results in only 1 logic “1” sample being strobed in the Initialization Flag Detector  306 , since the normal FLAG signal has one-half the duration of the initialization FLAG signal. By appropriate processing of these samples, the Initialization Flag Detector  306  is able to detect the initialization FLAG and distinguish it from the normal FLAG signal. Examples of circuitry for processing these samples will be described in detail below. The Initialization Flag Detector  306  also includes circuitry for generating the INIT* signal in response to detecting the initialization FLAG signal. 
     It appears from an examination of FIGS. 10 and 11 that sampling the FLAG signals at a frequency of twice the frequency of the ICLK signal would be sufficient to always allow the initialization FLAG signal to be distinguished from the normal FLAG signal. Although that will generally be the case, it is possible for incorrect results to be obtained by sampling the FLAG signals at twice the frequency of the ICLK signal, as illustrated in FIGS. 12 and 13. With reference to FIG. 12, when the transitions of the FCLK signal coincide with the transitions of the initialization FLAG signal, indeterminate logic levels may be strobed in the Initialization Flag Detector  306  during the transitions. Thus, the samples of the initialization FLAG signal strobed into the shift register  202  may be “ . . . 0111110 . . . ”, “ . . . 0011110 . . . ”, “ . . . 0111100 . . . ”, or, in the worst case, “ . . . 0011100 . . . ” in which only 3 logic “1” samples are obtained. 
     With reference to FIG. 13, when the transitions of the FCLK signal coincide with the transitions of the normal FLAG signal, indeterminate logic levels may also be strobed in the Initialization Flag Detector  306  during the transitions. Thus, the samples of the normal FLAG signal strobed into the shift register  202  may be “ . . . 00100 . . . ”, “ . . . 01100 . . . ”, “ . . . 00110 . . . ”, or, in the worst case, “ . . . 01110 . . . ”, in which there are also 3 logic “1” samples obtained. Under these circumstances, it would not be possible to distinguish between an initialization FLAG signal from which 3 logic “1” samples were obtained and a normal FLAG signal from which 3 logic “1” samples were obtained. Thus, detection errors are theoretically possible by sampling the FLAG signals at only twice the frequency of the ICLK signal. However, in practice, the Initialization Flag Detector  306  will generally operate consistently during the first and second coincident transitions of the FCLK signal and the FLAG signal. For example, if the sample obtained by the Initialization Flag Detector  306  coincident with the loading edge of the FLAG signal corresponds to the FLAG signal before that transition (and thus samples a logic “0”), the sample obtained by the Initialization Flag Detector  306  coincident with the trailing edge of the FLAG signal will also correspond to the FLAG signal before that transition (and thus sample a logic “1”). In practice, therefore, it will generally be acceptable to sample the FLAG signals at twice the frequency of the ICLK signal. 
     Although sampling at twice the frequency of the ICLK signal will usually not produce erroneous results, the potential problem described above can be eliminated by sampling using a higher frequency FCLK signal, as explained further below. Generally, the number of logic “1” samples produced by strobing the initialization FLAG signal with the FCLK signal will approach twice the number of logic “1” samples produced by strobing the FLAG signal with the FCLK signal as the frequency of the FCLK signal increases. More specifically, if N+1 strobe signals (i.e., transitions of FCLK) are applied to the initialization flag detector  306  during the initialization FLAG, the minimum number of logic “1” bits that can be detected is N+1−2=N−1 because two of the strobe signals may have occurred during the transition of the initialization FLAG signal. When the same frequency strobe signal is used to strobe the FLAG signal that occurs during normal use, the maximum number of logic “1” samples that can be generated is N/2+1, which assumes that two strobe signals applied to the initialization flag detector  306  during the transitions of the FLAG signal are registered as logic “1” samples. For the initialization flag detector  306  to be able to distinguish between the normal FLAG signal and the initialization FLAG signal, the number of samples strobed as logic “1” for the initialization FLAG signal must be greater than the number of samples strobed as logic “1” for the normal FLAG signal. Thus, the term N−1 must be greater than N/2+1, which can be solved for N as: N&gt;4. Therefore, for the initialization flag detector  306  to unambiguously distinguish between the normal FLAG signal and the initialization FLAG signal, there must be more than 5 (N+1) transitions of the FCLK signal during the initialization FLAG signal. This frequency of the FCLK signal corresponds to a frequency that is greater than twice the frequency of the ICLK signal. 
     There are several techniques that may be used by the Initialization Flag Detector  306  to distinguish the initialization FLAG signal from the normal FLAG signal. One embodiment of the Initialization Flag Detector  306 , which is illustrated in FIG. 14, samples at twice the frequency of the ICLK signal, as illustrated in FIG. 12 and 13. As explained above, at least 3 successive samples of the FLAG signals must be obtained at this frequency to distinguish the normal FLAG signal from the initialization FLAG signal. With reference to FIG. 14, an Initialization Flag Detector  308  includes a buffer  310  to which the FLAG signals (both normal and initialization) are applied. The buffer  310  applies the FLAG signals to data inputs D of a pair of two-stage shift registers  314 ,  316 . The shift registers  314 ,  316  each include a clock input adapted to receive a clock signal. On each transition of the clock signal applied to the clock input, the logic level at a signal applied to the D input to the each shift register  314 ,  316  is stored in the shift register  314 ,  316  and coupled to its S 0  output. At the same time, the logic level of the signal previously at the S 0  output is shifted to the S 1  output of each shift register  314 ,  316 . Since only three samples are required. one of the outputs of one of the shift registers  314 ,  316  need not be used. In the embodiment of FIG. 14, the S 1  output of the shift register  316  is not used. Thus, a conventional latch may be used instead of the shift register  316 . 
     The clock signals applied to the clock inputs of the shift registers  314 ,  316  are generated by the quadrature circuit  222  (FIG. 4) from the internal clock signal ICLK. Thus, the quadrature circuit  222  applies to the shift register  314  a clock signal CLK in phase with the ICLK signal and applies to the shift register  316  a clock signal CLK 90  leading or lagging the ICLK signal by 90 degrees. 
     The outputs of the latch are coupled to respective inputs of a NAND gate  320 , which generates the active low INIT* signal when 3 successive samples of the FLAG signal are logic “1”. 
     The operation of the Initialization Flag Detector  308  will now be explained with reference to FIGS. 15 and 16. As shown in FIG. 15, the CLK signal applied to the shift register  314  has the same frequency and phase as the ICLK signal, and the CLK 90  signal applied to the shift register  316  lags the CLK signal by 90 degrees. However, the CLK 90  signal may lead the CLK signal by 90 degrees, and the Initialization Flag Detector  308  will operate in the same manner. As shown in FIG. 15, the leading-edge of the FLAG signal occurs at time t 0 . On the next transition of the CLK signal at time t 2 , the high logic level of the FLAG signal is clock into the shift register  314 , thereby causing the S 0 A output of the shift register  314  to transition high. On the next transition of the CLK signal at time t 4 , the high at the SOA output of the shift register  314  is clocked to the S 1 A output of the shift register  314 . However, since the FLAG signal is still high at time t 4 , a high is also clocked into the first stage of the shift register  314  so that the logic level at the S 0 A output of the shift register  314  remains high. The FLAG signal then transitions low at time t 5 . On the next transition of the CLK signal at time t 7 , the low FLAG signal is clocked into the first stage of the shift register  314 , thereby causing the S 0 A output of the shift register  314  to transition low. The high from the first stage of the shift register  314  is clocked to the second stage of the shift register  314  at time t 7 , so that the S 1 A output of the shift register  314  remains high. Thereafter, on the next transition of the CLK signal at the time t 9 , the low stored in the first stage of the shift register  314  is clocked to the second stage of the shift register  314 , thereby causing the S 1 A output to transition low. 
     The shift register  316  operates in the same manner as the shift register  314  except that it is clocked by the CLK 90  signal rather than by the CLK signal, and only the S 0 B output of the shift register  316  is used. The S 0 B output transitions high at time t 3 , i.e., on the first transition of the CLK 90  signal after the FLAG signal goes high. The S 0 B output of the shift register  316  subsequently translations low at time t 6 , i.e., on the first transition of the CLK 90  signal after the FLAG signal goes low. 
     It is apparent from an examination of FIG. 15 that, between time, t 4  and time t 6 , all of the outputs of the shift registers  314 ,  316  are high. The NAND gate  320  to which the outputs of the shift registers  314 ,  316  are applied then outputs an active low INIT* signal. 
     The operation of the Initialization Flag Detector  308  responsive to a normal FLAG signal will now be explained with reference to FIG.  16 . On the first transition of the CLK signal after the FLAG signal goes high, the S 0 A output of the shift register  314  transitions high. Thereafter, on the next transition of the CLK signal, the high in the first stage of the shift register  314  is shifted to the second stage of the shift register, thereby causing the S 1 A output of the shift register  314  to go high. However, since the FLAG signal has transitioned low prior to that time, a low is then shifted into the first stage of the shift register  314 , thereby causing its S 0 A output to transition low. For this reason, the S 0 A and S 1 A outputs of the shift register  314  are never a both high at the same time. The NAND gate  320  cannot, therefore, generate an active low INIT* signal even though the S 0 B output of the shift register  316  transitions high at the same time that the S 0 A output of the shift register  314  is high. The Initialization Flag Detector is thus able to distinguish between a normal FLAG signal and an initialization FLAG signal. 
     The Initialization Flag Detector  308  of FIG. 14 can be modified as desired to accommodate specific design goals. For example, a greater number of the samples may be taken during each FLAG signal by coupling the FLAG signal to additional shift registers (not shown) which receive respective clock signals having incrementally increasing phases between the CLK signal and the CLK 90  signal. The FLAG signal may also be sampled at a faster rate by applying a clock signal having a frequency that is higher than the frequency of the ICLK signal to one or more shift registers having a larger number of stages. For example, a single 16-stage shift register clocked at eight times the frequency of the ICLK signal would store 16 samples during each initialization FLAG signal. These 16 samples would then be applied to a logic circuit performing an AND function to generate the INIT* signal. Other variations can also be used. 
     Another embodiment of an Initialization Flag Detector  330  for sampling the FLAG signals at a rate sufficient to distinguish the initialization FLAG signal from the normal FLAG signal is illustrated in FIG.  17 . The Initialization Flag Detector  330  includes a plurality of single-bit latches  332   a - 332   n  that receive the FLAG signals through a buffer  334 . The latches  332   a - 332   n  are clocked by respective strobe signals STROBE  0 -STROBE N. As explained below, the strobe signals STROBE  0 -STROBE N incrementally increase in phase relative to the internal clock signal ICLK from the STROBE  0  signal to the STROBE N signal. The outputs of the latches  332   a - 332   n  are applied to respective inputs of a NAND gate  340 . The NAND gate  340  outputs an active low INIT* signal when all of its inputs are high. 
     The strobe signals STROBE  0 -STROBE N are generated from the ICLK signal in a conventional manner by a clock phase shifter  346 . 
     The operation of the Initialization Flag Detector  330  will now the explained with reference to FIG.  18 . As shown in the first line of FIG. 18, after the start of the initialization FLAG signal, the rising edge of each of the strobe signals STROBE  0 -STROBE N clock a high into the respective latch  332   a - 332   n  starting with latch  332   d  and ending with latch  332   c.  Thus, during the period between when the output of the latch  332   c  goes high and the output of the latch  332   d  goes low, the outputs of all of the latches  332   a - 332   n  will all be high. The NAND gate  340  then generates the active low INIT* signal during this period to signify the detection of the initialization FLAG signal. 
     The operation of the Initialization Flag Detector  330  responsive to a normal FLAG signal is illustrated in FIG.  19 . The first strobe signal occurring after the FLAG signal transitions high is again the STROBE  3  signal thereby, causing the output of the latch  332   d  to go high before the output of the other latches. As with the initialization FLAG signal, the last strobe signal to occur after the FLAG signal transitions high is the STROBE  2  signal, thereby causing the output of the latch  332   c  to go high after the outputs of all the other latches have transitioned high. However, because the normal FLAG signal has only half the duration of the initialization FLAG signal, the FLAG signal is high during only one transition of each strobe signal STROBE  0 -STROBE N. As a result, by the time the high FLAG signal is clocked into the latch  332   c,  the FLAG signal is transitioning low, and this low is then clocked to the output of the latch  332   d.  The outputs of the latches  332   a - 332   n  are all high during the period between the output of the latch  332   c  going high and the output of the latch the  332   c  going low. However, this period is too short in duration for the NAND gate  340  to transition low. As a result, the INIT* signal at the output of the NAND gate  340  remains inactive high. Therefore, the Initialization Flag Detector  330  does not generate an active low INIT* signal in response to the normal FLAG signal. 
     Various modifications of an Initialization Flag Detector using latches are possible. For example, the latches  332  may be of the type that are clocked on either the rising edge or the falling edge (but not both edges) of the strobe signals, and the latches may store the strobed FLAG signal until they are subsequently reset by external circuitry (not shown). Under these circumstances, some of the latches will not be clocked when the normal FLAG signal is high. For example, using the timing relationships shown in FIG. 19, the latches  332   a-c  will not be clocked when the FLAG signal is high if the latches are clocked on the rising edge of their respective strobe signal. In contrast, all of the latches will be clocked when the initialization FLAG signal is high as can be seen with reference to FIG. 18, again assuming the latches are clocked on a rising edge of their respective strobe signals. Other variations, such as varying the number of latches and strobe signals used, are, of course, possible. 
     Sampling the FLAG signal at a rate sufficiently high that at least two samples are obtained when the FLAG signal is high can also be used for other purposes during initialization of the memory device. For example, during initialization, a predetermined pattern of signals are applied to the FLAG input line  52  (FIG. 2) and the command the bus  50 . As described in greater detail in the application to Baker et al., Ser. No. 08/890,055, the memory device  16  attempts to capture this pattern of data for the purpose of configuring the memory device for optimum performance. However, it is difficult to sample the FLAG signal and packet words at the proper time during initialization because the phase of the ICLK signal, which clocks the FLAG signal and packet words, is not determined until completion of the initialization procedure. The FLAG signal and command packets can nevertheless be detected during initialization using the “oversampling” techniques described above for use in the Initialization Flag Detector. 
     One pattern of the FLAG signal and packet words that can be used during initialization is illustrated in FIG.  20 . As shown therein, the FLAG signal alternates between low and high logic levels, the even bits of the packet word are driven with the same logic level as the FLAG signal, and the odd bits of the packet word are driven with the complementary logic level of the FLAG signal. 
     One embodiment of an Error Detection Circuit  360  using the above-described oversampling technique is illustrated in FIG.  21 . The Error Detection Circuit  360  may be used in the command buffer of FIG. 9, and the resulting command buffer may be used in the memory device  16  of FIG.  2 . The components of the Error Detection Circuit  360  are primarily the same components used in the Initialization Flag Detector  330  of FIG. 17, and these components have therefore been provided with the same reference numerals. Since these components operate in the same manner as described above, a description of their operation will not be repeated in the interest of brevity. The only additional components used in the Error Detection Circuit  360  are 10 buffers  310 , 10 latches  362   a - 362   j,  which are the same as the latches  332   a - 332   n,  comparitors  364   a - 360   j,  and 5 inverters  366   a - 366   e.  The latches  362   a - 362   j  each receive a respective bit of the packet word through a respective buffer  310 , and the comparitors  364   a - 364   j  receive the output of the latch  332   a  at one input and the output of a respective latch  362   a - 362   j  at their other input. The output of the latches  362  for the odd bits of the packet word are coupled to their respective comparitors  364  through respective inverters  366   a - 366   e.    
     Returning now, to FIG. 20, the operation of the Error Detection Circuit  360  will now be explained. If the FLAG signal and all 10 bits of the packet word are properly detected in the memory device  16   a,  the signals provided to each of the comparitors  364  will be the same. However, if either the FLAG signal or any of the 10 bits of the packet word are improperly detected in the memory device  16   a,  then its corresponding comparitor  364  will generate an ERROR signal. This ERROR signal is detected by other circuitry (not shown) that receives the outputs of all of the comparitors  364 . The comparitors  364  may be implemented by various circuitry, such as by exclusive OR gates (not shown). 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Technology Classification (CPC): 6