Patent Abstract:
A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package substrate. One embodiment discloses at least one redistribution layer (RDL) is prepared and the RDL is wrapped by a molding compound. The molding compound wraps four lateral sides and bottom side of the RDL. A top side of the RDL is made for a chip to mount and a bottom side of the RDL is planted a plurality of solder balls so that the bottom side of the chip package is adaptive to mount onto a system board in a later process.

Full Description:
BACKGROUND 
     Technical Field 
     The present invention relates to a package substrate for chip/chips package, especially relates to a package substrate having molding compound wrapped four lateral sides and bottom side to stiffen the high density package substrate. 
     Description of Related Art 
       FIG. 1  Shows a Prior Art. 
       FIG. 1  shows a prior art package substrate for chip package. US20120146209A1 disclosed a chip package which has a through-holed interposer  21 , a redistribution-layer  213  disposed on a top side of the interposer  21 . A molding layer  22  is formed to embed the through-holed interposer  21 . The molding layer  22  has an exposed first surface  22   a  and a second surface  22   b . A built-up structure  24  is formed on the second surface  22   b  of the molding layer  22 . The built-up structure  24  comprises a dielectric layer  240  and a wiring layer  241 , such that the conductive vias  242  are formed in the dielectric layer  240  for electrically connecting the wiring layer  241  to the conductive through metal  210 . A solder mask layer  25  is formed on the outermost dielectric layer  240  to expose conductive pads  243 . The through-holed interposer  21  is made of glass or ceramic such as Al2O3 and AlN, wherein the ceramic has a CTE of about 3 ppm/° C. that is close to silicon. A chip  27  is flip-chip electrically connected to the electrode pads  211  of the redistribution-layer  213  through a plurality of solder bumps  271 , an underfill  270  is used to fill the space between the electrode pads  211  and the chip  27 , and a plurality of solder balls  26  are mounted on the conductive pads  243  for the package to electrically coupled to an outside print circuit board (not shown). 
     The prior art package substrate is mainly stiffened by the glass/ceramic interposer  21 . However, semiconductor package technology moves faster and faster, a thinner thickness package substrate without having a glass/ceramic interposer is developed, a different stiffening structure has to be conceived for a high density package substrate used for chip or chips package. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a prior art. 
         FIGS. 2A ˜ 2 B show a first embodiment according to the present invention. 
         FIGS. 3A ˜ 3 B show a second embodiment according to the present invention. 
         FIGS. 4A ˜ 4 B show a third embodiment according to the present invention. 
         FIGS. 5A ˜ 5 B show a fourth embodiment according to the present invention. 
         FIGS. 6A ˜ 6 B show a fifth embodiment according to the present invention. 
         FIGS. 7A ˜ 7 B show a sixth embodiment according to the present invention. 
         FIGS. 8A ˜ 8 B show a seven embodiment according to the present invention. 
         FIGS. 9A ˜ 9 B show an eighth embodiment according to the present invention. 
         FIGS. 10A ˜ 10 B show a top view of  FIGS. 9A ˜ 9 B. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A molding compound wrapped thin film high package substrate is disclosed. The package substrate has a top side for chip mount and a bottom side for mounting the chip package onto a system board. The molding compound wrapped the package substrate at least four lateral side and a bottom side to stiffen the thin film package substrate. 
       FIGS. 2A ˜ 2 B Show a First Embodiment According to the Present Invention. 
       FIG. 2A  shows a first package substrate according to the present invention. 
       FIG. 2A  shows a redistribution layer (RDL) which has a redistribution circuitry  31  embedded in a dielectric layer  31 D; the redistribution circuitry  31  has a plurality of top metal pads  31 T and a plurality of bottom metal pads  31 B; the redistribution circuitry  31  fans out downwards so that a density of the bottom metal pads  31 B is lower than a density of the top metal pads  31 T. A plurality of top openings  321  are formed on a top side of the dielectric layer  31 D; each top opening  321  exposes a top surface of a corresponding top metal pad  31 T. A molding compound  35  wraps four lateral sides and bottom side of the dielectric layer  31 D; and a plurality of bottom openings  351  are formed on a bottom side of the molding compound  35 ; each opening  351  exposes a bottom side of a corresponding bottom metal pad  31 B. 
       FIG. 2B  shows a chip package using the package substrate of  FIG. 2A . 
       FIG. 2B  shows at least one chip  36  is exemplarily configured on a top side of the redistribution circuitry  31  and electrically coupled to the top metal pads  31 T of the redistribution circuitry  31 . A plurality of solder balls  37  are configured on a bottom side of the redistribution circuitry  31 , each solder ball  37  is configured on a bottom side of a corresponding bottom metal pad  31 B. 
       FIGS. 3A ˜ 3 B Show a Second Embodiment According to the Present Invention. 
       FIG. 3A  shows a modified structure of  FIG. 2A . 
       FIG. 3A  is similar to  FIG. 2A . However,  FIG. 3A  has a plurality of metal pillars  33  formed on a bottom side of the redistribution circuitry  31 .  FIG. 3A  shows a redistribution layer (RDL) which has a redistribution circuitry  31  embedded in a dielectric layer  31 D; wherein the redistribution circuitry  31  has a plurality of top metal pads  31 T and a plurality of bottom metal pads  31 B; the redistribution circuitry  31  fans out downwards so that a density of the bottom metal pads  31 B is lower than a density of the top metal pads  31 T. A plurality of metal pillars  33  are formed on a bottom side of the redistribution circuitry  31 , each metal pillar  33  is configured on a bottom side of a corresponding bottom metal pad  31 B. A plurality of top openings  321  are formed on a top side of the dielectric layer  31 D; each top opening  321  exposes a top surface of a corresponding top metal pad  31 T. A molding compound  35  wraps four lateral sides and bottom side of the dielectric layer  31 D; and a plurality of bottom openings  351  are formed on a bottom side of the molding compound  35 ; each opening  351  exposes a bottom side of a corresponding bottom metal pad  31 B. 
       FIG. 3B  shows a chip package using the package substrate of  FIG. 3A . 
       FIG. 3B  shows at least one chip  36  is exemplarily configured on a top side of the redistribution circuitry  31  and electrically coupled to the top metal pads  31 T of the redistribution circuitry  31 . A plurality of solder balls  37  are configured on a bottom side of the redistribution circuitry  31 , each solder ball  37  is configured on a bottom side of a corresponding metal pillar  33 . 
       FIGS. 4A ˜ 4 B Show a Third Embodiment According to the Present Invention. 
       FIG. 4A  shows a modified structure of  FIG. 3A .  FIG. 4A  shows a package substrate which has a redistribution layer RDL. The RDL comprises a left redistribution circuitry  41  and a right redistribution circuitry  411 , both redistribution circuitry  41 ,  411  are embedded in a dielectric layer  41 D. The left redistribution circuitry  41  has a plurality of top metal pads  41 T and a plurality bottom metal pads  41 B; the left redistribution circuitry  41  fans out downwards so that a density of the bottom metal pads  41 B is lower that a density of the top metal pads  41 T. The right redistribution circuitry  411  is similar to the first redistribution circuitry  41 . The right redistribution circuitry  411  has a plurality of top metal pads and a plurality of bottom metal pads; the right redistribution circuitry  411  fans out downwards so that a density of the bottom metal pads is lower that a density of the top metal pads. A plurality of top openings  421  are formed on a top side of the dielectric layer  41 D; each top opening  421  exposes a top surface of a corresponding top metal pad  41 T. A plurality of metal pillars  43  are formed on a bottom side of the redistribution circuitry  41 , each metal pillar  43  is configured on a bottom side of a corresponding bottom metal pad  41 B. A molding compound  45  wraps four lateral sides and bottom side of the dielectric layer  41 D; the molding compound  45  also wraps the plurality of metal pillars  43 ; and a plurality of bottom openings  451  are formed on a bottom side of the molding compound  45 ; each opening  451  exposes a bottom side of a corresponding metal pillar  43 . A lateral communication circuitry  412  is configured between the left redistribution circuitry  41  and the right redistribution circuitry  411 ; the lateral communication circuitry  412  has a plurality of left top metal pads  412 T and a plurality of right top metal pads  413 T exposed on a top side of the dielectric layer  41 D. 
       FIG. 4B  shows a chip package using the package substrate of  FIG. 4A . 
       FIG. 4B  shows at least one left chip  461  is exemplarily configured on a top side the left redistribution circuitry  41  and electrically coupled to the top metal pads  41 T of the left redistribution circuitry  41 ; and at least one right chip  462  is exemplarily configured on a top side of the right redistribution circuitry  411  and electrically coupled to the top metal pad  41 T of the right redistribution circuitry  411 . A plurality of solder balls  47  are configured on a bottom side of the redistribution circuitry  41 ,  411 , each solder ball  47  is configured on a bottom side of a corresponding metal pillar  43 . The lateral communication circuitry  412  communicates the first chip  461  and the second chip  462 . 
       FIGS. 5A ˜ 5 B Show a Fourth Embodiment According to the Present Invention. 
       FIG. 5A  shows a modified structure of  FIG. 4A . 
       FIG. 5A  shows a cavity  48  is formed on a bottom side of the dielectric layer  41 D, and enclosed by the molding compound  45 ; and a plurality of openings  452  are formed on a bottom side of the dielectric layer  41 D within the cavity  48 , each opening  452  exposes a bottom side of a corresponding bottom metal pad  41 B within the cavity  48 . 
       FIG. 5B  shows a chip package using the package substrate of  FIG. 5A . 
       FIG. 5B  shows two chips  481 ,  482  are exemplarily shown to be electrically coupled to the bottom metal pads  41 B within the cavity  48 . A plurality of solder balls  47  are configured on a bottom side of the redistribution circuitry  41 ,  411 , each solder ball  47  is configured on a bottom side of a corresponding metal pillar  43 . 
       FIGS. 6A ˜ 6 B Show a Fifth Embodiment According to the Present Invention. 
       FIG. 6A  shows a package substrate according to the presentation invention. 
       FIG. 6A  shows a package substrate which has a first redistribution layer RDL 1 . The RDL 1  is built according to a first design rule. The RDL 1  has a first redistribution circuitry  51  embedded in a first dielectric layer  51 D; the first redistribution circuitry  51  has a plurality of first top metal pads  51 T and a plurality of first bottom metal pads  51 B. The package substrate has a second redistribution layer RDL 2  which is configured on a bottom side of the first redistribution layer RDL 1 . 
     The RDL 2  is built according to a second design rule and has a second redistribution circuitry  52  embedded in a second dielectric layer  52 D; the second redistribution circuitry  52  has a plurality of second top metal pads  52 T and a plurality of second bottom metal pads  52 B; each second top metal pad  52 T is electrically coupled to a corresponding first bottom metal pad  51 B; the first redistribution circuitry  51  fans out downwards so that a density of the first bottom metal pads  51 B is lower than a density of the first top metal pads  51 T; the second redistribution circuitry  52  fans out downwards so that a density of the second bottom metal pads  52 B is lower than a density of the second top metal pads  52 T. The second design rule has a lower circuitry density than the first design rule has. A plurality of top openings  521  are configured on a top side of the first dielectric layer  51 D; each top opening  521  exposes a top surface of a corresponding first top metal pad  51 T; a molding compound  55  wraps four lateral sides and a bottom side of, at least, the second dielectric layer  52 D; and a plurality of bottom openings  551  are formed on a bottom side of the molding compound  55 ; each opening  551  exposes a bottom side of a corresponding second bottom metal pad  52 B. 
       FIG. 6B  shows a chip package using the package substrate of  FIG. 6A . 
       FIG. 6B  shows at least one chip  56  is exemplarily shown to be electrically coupled to the first top metal pads  51 T. A plurality of solder balls  57  are configured on a bottom side of the second redistribution circuitry  52 , each solder ball  57  is configured on a bottom side of a corresponding second metal pad  52 B. 
       FIGS. 7A ˜ 7 B Show a Sixth Embodiment According to the Present Invention. 
       FIG. 7A  shows a package substrate according to the present invention.  FIG. 7A  shows a package substrate which has a first redistribution layer RDL 1 . The RDL 1  is built according to a first design rule; the RDL 1  has a first redistribution circuitry  51  embedded in a first dielectric layer  5 D; the first redistribution circuitry  51  has a plurality of first top metal pads  51 T and a plurality of first bottom metal pads  51 B. The package substrate also has a second redistribution layer RDL 2  which is configured on a bottom side of the first redistribution layer RDL 1 ; the RDL 2  is built according to a second design rule; the RDL 2  has a second redistribution circuitry  52  embedded in a second dielectric layer  52 D; the second redistribution circuitry  52  has a plurality of second top metal pads  52 T and a plurality of second bottom metal pads  52 B; each second top metal pad  52 T is electrically coupled to a corresponding first bottom metal pad  51 B. The first redistribution circuitry  51  fans out downwards so that a density of the first bottom metal pads  51 B is lower than a density of the first top metal pads  51 T; the second redistribution circuitry  52  fans out downwards so that a density of the second bottom metal pads  52 B is lower than a density of the second top metal pads  52 T. The second design rule has a lower circuitry density than the first design rule has. A plurality of metal pillars  53  are formed on a bottom side of the second redistribution circuitry  52 , each metal pillar  53  is configured on a bottom side of a corresponding bottom metal pad  52 B; a plurality of top openings  521  are configured on a top side of the first dielectric layer  51 D; each top opening  521  exposes a top surface of a corresponding first top metal pad  51 T; a molding compound  55  wraps four lateral sides and a bottom side of, at least, the second dielectric layer  52 D; and a plurality of bottom openings  551  are formed on a bottom side of the molding compound  55 ; each opening  551  exposes a bottom side of a corresponding metal pillar  53 . 
       FIG. 7B  shows a chip package using the package substrate of  FIG. 7A . 
       FIG. 7B  shows at least one chip  56  is exemplarily shown to be electrically coupled to the first top metal pads  51 T; a plurality of solder balls  57  are configured on a bottom side of the second redistribution circuitry  52 , each solder ball  57  is configured on a bottom side of a corresponding metal pillar  53 . 
       FIGS. 8A ˜ 8 B Show a Seven Embodiment According to the Present Invention. 
       FIG. 8A  shows a package substrate according to the present invention.  FIG. 8A  shows a package substrate which has a first redistribution layer RDL 1 , the RDL 1  is built according to a first design rule; the RDL 1  has a first redistribution circuitry  61 ,  611  embedded in a first dielectric layer  61 D; the first redistribution circuitry  61 ,  611  has a plurality of first top metal pads  61 T and a plurality of first bottom metal pads  61 B. 
     The package substrate also has a second redistribution layer RDL 2  which is built according to a second design rule. The RDL 2  is configured on a bottom side of the first redistribution layer RDL 1 . The RDL 2  has a second redistribution circuitry  62 ,  622  embedded in a second dielectric layer  62 D; the second redistribution circuitry  62 ,  622  has a plurality of second top metal pads  62 T and a plurality of second bottom metal pads  62 B. The second design rule has a lower circuitry density than the first design rule has. The first redistribution circuitry  61 ,  611  further comprises: a first left redistribution circuitry  61 , embedded in the first dielectric layer  61 D, having a plurality of first left top metal pads  61 T and a plurality of first left bottom metal pads  61 B; a first right redistribution circuitry  611 , embedded in the first dielectric layer  61 D, having a plurality of first right top metal pads and a plurality of first right bottom metal pads. 
     The second redistribution circuitry  62 ,  622  further comprises: a second left redistribution circuitry  62 , embedded in a second dielectric layer  62 D, has a plurality of second left top metal pads  62 T and a plurality of second left bottom metal pads  62 B; a second right redistribution circuitry  622 , embedded in the second dielectric layer  62 D, having a plurality of second right top metal pads  62 T and a plurality of second right bottom metal pads  62 B; each second left top metal pad  62 T is electrically coupled to a corresponding first left bottom metal pad  61 B; each second right top metal pad  62 T is electrically coupled to a corresponding first right bottom metal pad  61 B. The first left redistribution circuitry  61  fans out downwards so that a density of the first left bottom metal pads  61 B is lower than a density of the first left top metal pads  61 T. The first right redistribution circuitry  611  fans out downwards so that a density of the first right bottom metal pads is lower than a density of the first right top metal pads; the second left redistribution circuitry  62  fans out downwards so that a density of the second left bottom metal pads  62 B is lower than a density of the second left top metal pads  62 T; the second right redistribution circuitry  622  fans out downwards so that a density of the second right bottom metal pads is lower than a density of the second right top metal pads. A plurality of top openings  621  configured on a top side of the first dielectric layer  61 D; each top opening  621  exposes a top surface of a corresponding first top metal pad  61 T; a plurality of metal pillars  63  are formed on a bottom side of the second redistribution circuitry  62 , each metal pillar  63  is configured on a bottom side of a corresponding second bottom metal pad  62 B; and a molding compound  65  wraps four lateral sides and bottom side of, at least, the second dielectric layer  62 D; the molding compound  65  also wraps the plurality of metal pillars  63 ; and a plurality of bottom openings  651  are formed on a bottom side of the molding compound  65 ; each opening  651  exposes a bottom side of a corresponding metal pillar  63 . A lateral communication circuitry  612 , built according to the first design rule, is configured between the first left redistribution circuitry  61  and the first right redistribution circuitry  611 ; the lateral communication circuitry  612  has a plurality of left top metal pads  612 T and a plurality of right top metal pads  613 T exposed on a top side of the first dielectric layer  61 D. 
       FIG. 8B  shows a chip package using the package substrate of  FIG. 8A . 
       FIG. 8B  shows two chips  661 ,  662  configured on a top of the first redistribution circuitry and on a top of the lateral communication circuitry  612 . The chip  661  is exemplarily shown to be electrically coupled to the left top metal pads  612 T of the lateral communication circuitry  612 ; and the right chip  662  is exemplarily shown to be electrically coupled to the right top metal pads  613 T of the lateral communication circuitry  612 ; the left chip  661  and the right chip  662  are able to communicate with each other through the lateral communication circuitry  612 . A plurality of solder balls  67  are configured on a bottom side of the second redistribution circuitry  62 , each solder ball  67  is configured on a bottom side of a corresponding metal pillar  63 . 
       FIGS. 9A ˜ 9 B Show an Eighth Embodiment According to the Present Invention. 
       FIG. 9A  is a modified structure of  FIG. 8A . 
       FIG. 9A  shows a cavity  68  is formed on a bottom side of the second dielectric layer  62 D, and enclosed by the molding compound  65 ; and a plurality of openings  652  are formed on a bottom side of the second dielectric layer  62 D within the cavity  68 , each opening  652  exposes a bottom side of a corresponding second metal pads  62 B within the cavity  68 . 
       FIG. 9B  shows a chip package using the package substrate of  FIG. 9A . 
       FIG. 9B  shows chips  681 ,  682  are exemplarily shown to be electrically coupled to the second bottom metal pads  62 B within the cavity  68 . A plurality of solder balls  67  are configured on a bottom side of the second redistribution circuitry  62 , each solder ball  67  is configured on a bottom side of a corresponding metal pillar  63 . 
       FIGS. 10A ˜ 10 B Show a Top View of  FIGS. 9A ˜ 9 B. 
       FIG. 10A  shows a top view of  FIG. 9A .  FIG. 10A  shows the molding compound  65  wraps four sides of the first dielectric layer  61 D and the lateral communication circuitry  612  is embedded in the first dielectric layer  61 D. 
       FIG. 10B  shows a top view of  FIG. 9B .  FIG. 10B  shows the chips  664 ,  662  configured on the top surface of the first dielectric layer  61 D. The embedded lateral communication circuitry  612  communicates between the chip  661  and chip  662 . 
     While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims. 
     NUMERICAL SYSTEM 
     
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 31 redistribution circuitry 
               
               
                   
                 31B bottom metal pad 
               
               
                   
                 31D dielectric layer 
               
               
                   
                 31T top metal pad 
               
               
                   
                 321 opening 
               
               
                   
                 33 metal pillar 
               
               
                   
                 35 molding compound 
               
               
                   
                 351 opening 
               
               
                   
                 36 chip 
               
               
                   
                 37 solder ball 
               
               
                   
                 38 cavity 
               
               
                   
                 381, 382 chip 
               
               
                   
                 41 left redistribution circuitry 
               
               
                   
                 411 right redistribution circuitry 
               
               
                   
                 412 lateral communication circuitry 
               
               
                   
                 412T, 413T top metal pad 
               
               
                   
                 41B bottom metal pad 
               
               
                   
                 41D dielectric layer 
               
               
                   
                 41T top metal pad 
               
               
                   
                 421 opening 
               
               
                   
                 43 metal pillar 
               
               
                   
                 45 molding compound 
               
               
                   
                 451 opening 
               
               
                   
                 452 opening 
               
               
                   
                 461, 462 chip 
               
               
                   
                 47 solder ball 
               
               
                   
                 48 cavity 
               
               
                   
                 481, 482 chip 
               
               
                   
                 51 redistribution circuitry 
               
               
                   
                 51B bottom metal pad 
               
               
                   
                 51D dielectric layer 
               
               
                   
                 51T top metal pad 
               
               
                   
                 52 redistribution circuitry 
               
               
                   
                 521 opening 
               
               
                   
                 52B bottom metal pad 
               
               
                   
                 52D dielectric layer 
               
               
                   
                 52T top metal pad 
               
               
                   
                 53 metal pillar 
               
               
                   
                 55 molding compound 
               
               
                   
                 551 opening 
               
               
                   
                 56 chip 
               
               
                   
                 57 solder ball 
               
               
                   
                 61 redistribution circuitry 
               
               
                   
                 611 redistribution circuity 
               
               
                   
                 612 lateral communication circuitry 
               
               
                   
                 612T top metal pad 
               
               
                   
                 613T top metal pad 
               
               
                   
                 61B bottom metal pad 
               
               
                   
                 61D dielectric layer 
               
               
                   
                 61T top metal pad 
               
               
                   
                 62 redistribution circuitry 
               
               
                   
                 621 opening 
               
               
                   
                 622 redistribution circuitry 
               
               
                   
                 62B bottom metal pad 
               
               
                   
                 62D dielectric layer 
               
               
                   
                 62T top metal pad 
               
               
                   
                 63 metal pillar 
               
               
                   
                 65 molding compound 
               
               
                   
                 651 opening 
               
               
                   
                 652 opening 
               
               
                   
                 66 chip 
               
               
                   
                 661, 662 chip 
               
               
                   
                 67 solder ball 
               
               
                   
                 68 cavity 
               
               
                   
                 681, 682 chip

Technology Classification (CPC): 7