Patent Abstract:
Improved decision directed adaptation and decision feedback equalizers are provided in a block coded digital communication system. The performance of a receiver is significantly improved by allowing the decision feedback equalizer to perform time-tracking and residual frequency offset compensation during the data portion of a frame. This is accomplished by capitalizing on the inherent correlation among the chips of a code word in a block coded digital communication system to identify certain instances where more reliable symbol estimates can be derived from a sliced chip without introduction the delay inherent in decoding. As the more reliable symbol estimates are fed back into the chip slicer, the total efficiency of the decision feedback equalizer is improved and the more reliable symbol estimates can be used to replace older content in the feedback filter to further improve the accuracy of the modified slicer input and further decrease the effects of error propagation by the decision feedback equalizer.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 10/602,508, filed on Jun. 24, 2003, now pending, which is herein incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates generally to the field of wireless communications and more particularly relates to block coded digital communication systems. 
         [0004]    2. Related Art 
         [0005]    Conventional block coded digital communication systems typically split a frame into known training symbols and known data symbols. Although the symbols are known, i.e., included in a predefined finite alphabet, the particular data symbols in any given frame are unknown to the receiver. 
         [0006]    During the training portion of a frame, it is well known to run tracking loops based on an error signal generated from the training data. For example, a time tracking loop or phase locked loop may be employed. Alternatively, or in combination, a least mean square (“LMS”) equalizer updating procedure may also be used. These loops or procedures serve to provide critical information to the receiver of a wireless communication device. 
         [0007]    In these conventional block coded digital communication systems, it is often necessary to continue adapting the loops during the data portion of the frame, for example to compensate for a fading signal or timing error. A common method of such continuous adaptation is to employ decision-directed (“DD”) adaptation. This scheme requires that the receiver estimate what symbols are received in the data stream. Typically, a slicer is employed to obtain tentative decisions for the transmitted data symbols and to determine the noise associated with the slicer decision. The final decisions for the transmitted data symbols are based on the decoder output. 
         [0008]    A problem associated with this scheme is the delay that is inherent in channel decoding. Because the symbols are encoded, the efficiency of the process is either reduced by decoding the symbols or reduced by the higher error rate that is inherent with slicer decisions as opposed to decisions from the decoder output. 
         [0009]    Furthermore, implementing a decision feedback equalizer (“DFE”) at the receiver to remove intersymbol interference (“ISI”) exacerbates this problem because the input to the feedback filter (“FBF”) comprises the higher error rate slicer decisions. Thus, when the sliced symbols that are put into the FBF are in error, which is more likely when they are encoded, then the DFE propagates the error and increases the likelihood of subsequent slicer errors and thereby diminishes performance.  FIG. 1  is an example graph diagram illustrating conventional slicer errors when unmodified symbol estimates are used as slicer input. 
         [0010]    Therefore, what is needed is a method for improving slicer input and the corresponding feedback filter contents in block coded communications to overcome these significant problems found in the conventional systems as described above. 
       SUMMARY 
       [0011]    Methods for improved decision directed adaptation and decision feedback equalizers are presented. In a block coded digital communication system the performance of a receiver is significantly improved by allowing decision directed adaptation through a decision feedback equalizer to perform time-tracking and residual frequency offset compensation during the data portion of a frame. Additionally, DFE error propagation is decreased by modifying the contents of the feedback filter to include more reliable symbol estimates. 
         [0012]    As an encoded stream of symbols is received in a block coded digital communication system, a slicer is employed by a decision feedback equalizer to slice chips of a code word from the encoded stream and pass them to a feedback filter. Based on the inherent correlation among the chips of a code word, certain instances of more reliable symbol estimates are derived from the sliced chips. 
         [0013]    As the more reliable symbol estimates are fed back into the chip slicer, the total efficiency of the decision feedback equalizer is improved. Moreover, the more reliable symbol estimates are used to replace older content in the feedback filter to further improve the accuracy of the modified slicer input and decrease the effects of DFE error propagation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The details of the present invention, both as to its structure and operation, may be gleaned in part by study of the accompanying drawings, in which like reference numerals refer to like parts, and in which: 
           [0015]      FIG. 1  is an example graph diagram illustrating conventional slicer errors when unmodified symbol estimates are used as slicer input; 
           [0016]      FIG. 2  is a block diagram illustrating an example decision feedback equalizer according to an embodiment of the present invention; 
           [0017]      FIG. 3  is an example graph diagram illustrating a reduced amount of slicer errors based on modified symbol estimates according to an embodiment of the present invention; 
           [0018]      FIG. 4  is a block diagram illustrating an example chip slicer and feedback filter contents in a decision feedback equalizer according to an embodiment of the present invention; 
           [0019]      FIG. 5  is a table diagram illustrating improved feedback filter contents according to an embodiment of the present invention; 
           [0020]      FIG. 6A  is an example pseudo code listing for creating more accurate sliced chips for least mean square and feed back filter tracking according to an embodiment of the present invention; 
           [0021]      FIG. 6B  is an example pseudo code listing for using more accurate sliced chips for better least mean square updating of a decision feedback equalizer, feed forward filter, and feed back filter according to an embodiment of the present invention; and 
           [0022]      FIG. 6C  is an example pseudo code listing for using the more accurate sliced chips for improved feed back filter contents according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Certain embodiments as disclosed herein provide for improved decision directed adaptation employed by a receiver in a block coded digital communication system. For example, one method as disclosed herein allows for the inherent correlation between the chips of a code word to be exploited to derive more reliable symbol estimates. These more reliable symbol estimates are then passed through a feedback filter to improve the accuracy of future input to the chip slicer. Additionally, the more reliable symbol estimates replace earlier symbol estimates in a feedback filter to further improve the total efficiency of the decision feedback equalizer. 
         [0024]    After reading this description it will become apparent to one skilled in the art how to implement the invention in various alternative embodiments and alternative applications. However, although various embodiments of the present invention will be described herein, it is understood that these embodiments are presented by way of example only, and not limitation. As such, this detailed description of various alternative embodiments should not be construed to limit the scope or breadth of the present invention as set forth in the appended claims. 
         [0025]      FIG. 2  is a block diagram illustrating an example decision feedback equalizer (“DFE”)  10  according to an embodiment of the present invention. In the illustrated embodiment, the DFE  10  comprises an antenna  20 , a preprocessor  30 , a feed forward filter  40 , a chip combiner  50 , a chip slicer  60 , and a feed back filter  70 . 
         [0026]    The antenna  20  can be any of a variety of antennas configured for wireless communications in a block coded digital communication system, as will be understood by one having skill in the art. Similarly, the preprocessor  30  preferably carries out signal processing tasks and provides the feed forward filter  40  with baseband samples (i.e., digital input), as will also be understood by one having skill in the art. The feed forward filter  40  preferably processes the baseband samples and sends the digital data stream to the chip slicer  60 , in combination with any signal added or subtracted by the chip combiner  50 . In one embodiment, the feed back filter  70  can be a finite impulse response (“FIR”) filter that processes the previous slicer  60  outputs to subtract out postcursor inter symbol interference (“ISI”) from the current input to the slicer  60 . 
         [0027]    In one embodiment, the length of the feedback filter  70  is not related to the length of the codewords. For example, the coefficients for the feed forward filter  40  and the feedback filter  70  can be selected based on the minimum mean square error (“MMSE”) criterion using either adaptive techniques or based on computations involving a channel estimate. 
         [0028]    The chip slicer  60  is preferably configured to extract a portion of the data stream that corresponds to a single chip of a code word. Each sliced chip is preferably provided to the feed back filter  70 , where the sliced chips are processed to determine any noise associated with the slicer decision. The feed back filter  70  advantageously feeds the noise component back into the chip slicer  60  by way of the chip combiner  50 . In this fashion, the noise component can be subtracted from next incoming signal from the feed forward filter  40  before it is fed into the slicer  60 . 
         [0029]    For example, in block coded digital communications, a stream of digital data is sent over the airwaves in analog form and received by the antenna  20 . The analog waves are interpreted by the preprocessor  30  and converted to digital form. The digital signal comprises a frame that is divided into two portions, a training portion and a data portion. Within the data portion of the frame are a series of binary digits (i.e., ones and zeroes) that are encoded symbols which represent the data payload. These symbols can be broken down into a plurality of code words and each code word can be further broken down into a plurality of chips. For example, a complementary code keying (“CCK”) code word, as specified for the IEEE 802.11b 5.5 Mb/s data rate, is eight (8) chips long. 
         [0030]    When an encoded symbol is sent to the chip slicer  60 , the chip slicer  60  preferably identifies a subset of the symbol that represents a single chip. The correct identification of a chip is very important because if a chip is not correctly identified, then DFE error propagation will result, where the incorrectly sliced chips fed into the feedback filter  70  can result in an output from the feedback filter  70  that incorrectly accounts for interference and therefore causes further errors in slicer decisions made by the chip slicer  60 . 
         [0031]    Thus, in the training portion of the frame, it is well known to provide information relating to the identification of chips. However, when signal strength fades, for example, the information provided in the training portion of the frame may become obsolete during processing of the data portion of the frame. To account for such variations in the signal during the data portion of the frame, the chip slicer  60  sends the sliced chips to the feed back filter  70  in order to more accurately slice the next incoming chip. 
         [0032]    Advantageously, the construction of code words introduces a certain correlation between the various chips that comprise a code word. For example, a CCK code word is eight (8) chips long and includes the following structure: 
         [0000]      CCKchip(3)=CCKchip(1) 
         [0000]      CCKchip(4)=−CCKchip(2) 
         [0000]      CCKchip(5)=−CCKchip(7) 
         [0000]      CCKchip(6)=CCKchip(8) 
         [0033]    Knowledge of this structure allows the use of decision directed adaptation during the data portion of the frame in order to continuously calibrate the slicing of chips by the chip slicer  60 . Thus, the symbol estimates created by the chip slicer  60  can be improved in fifty percent (50%) of the estimates according to: 
         [0000]      Improved_Estimate(3)=Estimate(3)+Estimate(1) 
         [0000]      Improved_Estimate(4)=Estimate(4)−Estimate(2) 
         [0000]      Improved_Estimate(7)=Estimate(7)−Estimate(5) 
         [0000]      Improved_Estimate(8)=Estimate(8)+Estimate(6) 
         [0034]    With the improved estimates from the slicer  60 , an improved noise component can be fed back into the slicer  60  fifty percent (50%) of the time, resulting in significantly improved results and decreased DFE error propagation. Accordingly,  FIG. 3  is an example graph diagram illustrating a reduced amount of slicer errors based on improved symbol estimates according to an embodiment of the present invention. 
         [0035]      FIG. 4  is a block diagram illustrating an example chip slicer  62  and feedback filter contents  72  in a decision feedback equalizer  12  according to an embodiment of the present invention. In the illustrated embodiment, the DFE  12  comprises a signal combiner  52 , a chip slicer  62 , and feed back filter  72 . The feed back filter  72  comprises a series of tap contents that each contain decisions from the slicer  62 . Each set of tap contents is shown as “Tc” in  FIG. 4 . Advantageously, the DFE  12  can be switched so that the tap contents in the feed back filter  72  are updated only during the data portion of a frame. 
         [0036]    For certain block coded digital communication systems, for example, the IEEE 802.11b 5.5 Mb/s data rate system that uses CCK code words, the effects of DFE error propagation can be reduced by improving the reliability of slicer decisions that are stored in the tap contents of the feed back filter  72 . In one embodiment, chips  3 ,  4 ,  7 , and  8  of each CCK code word are known to contain more reliable information. Thus, these slicer decisions can be selectively fed back into the slicer  62  to improve the reliability of future slicer decisions. 
         [0037]    Additionally, once the slicer  62  has provided more reliable information, this information can be stored in the tap contents of the feed back filter  72  and the known correlation between the chips in the code word can be exploited to modify the older tap contents in the feed back filter  72  based on the more reliable information. For example, after slicing each of the chips  3 ,  4 ,  7 , and  8  and placing them into the first tap contents of the feed back filter  72 , the tap contents of the feed back filter  72  that is two chips old can be replaced with a more reliable value by modifying the third tap contents of the feed back filter  72 . The tap contents are appropriately mixed and combined to create the new estimate to be fed to the chip slicer  62 . Advantageously, after startup this ensures that the contents of feed back filter  72  taps  3  and higher will reflect the increased accuracy of the modified slicer input and thereby decrease DFE error propagation. 
         [0038]    For example, as k loops from 1 to 8 to represent the CCK chip index of the frame chip index n, the DFE may implement: 
         [0039]    If k=3, y ˜ [n−3]=y ˜ [n−1]. 
         [0040]    If k=4, y ˜ [n−3]=−y ˜ [n−1]. 
         [0041]    If k=7, y ˜ [n−3]=−y ˜ [n−1]. 
         [0042]    If k=8, y ˜ [n−3]=y ˜ [n−1]. 
         [0043]    Thus, as k loops from 1 to 8, the sample that is two chips old is modified pursuant to the correlation properties of the CCK code words as previously described in the CCKchip equations. After several chips have been processed, the majority of the tap contents in feed back filter  72  will advantageously be based on the more accurate slicer input. 
         [0044]    Accordingly,  FIG. 5  is a table diagram illustrating improved feedback filter contents according to an embodiment of the present invention. In the illustrated embodiment, the third and higher feed back filter tap contents reflect the improved accuracy of the chip estimates pursuant to the correlation between chips in the 8 chip CCK code words as previously described. Additionally, in the illustrated table, each row corresponds to a particular time index with time moving from top to bottom. Thus, the contents of feed back filter tap  9  are not modified until after the ninth row. 
         [0045]      FIGS. 6A-6C  are example code sections in pseudo code that illustrate methods for improving slicer output, using the improved slicer output in various filters, and storing the improved slicer output in a feedback filter to decrease the effects of DFE error propagation. Specifically,  FIG. 6A  is an example pseudo code listing for creating more accurate sliced chips for least mean square and feed back filter tracking according to an embodiment of the present invention. Moreover,  FIG. 6B  is an example pseudo code listing for using more accurate sliced chips for better least mean square updating of a decision feedback equalizer, feed forward filter, and feed back filter according to an embodiment of the present invention. Furthermore,  FIG. 6C  is an example pseudo code listing for using the more accurate sliced chips for improved feed back filter contents according to an embodiment of the present invention. 
         [0046]    While the particular embodiment herein shown and described in detail is fully capable of attaining the above described objects of this invention, it is to be understood that the description and drawings presented herein represent a presently preferred embodiment of the invention and are therefore representative of the subject matter which is broadly contemplated by the present invention. It is further understood that the scope of the present invention fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present invention is accordingly limited by nothing other than the appended claims.

Technology Classification (CPC): 7