Patent Abstract:
A signal processing circuit is connected between a first external circuit and a second external circuit. The signal processing circuit includes a signal input module and a signal processing module. The signal input module receives signal from the first external circuit. The processing module processes the signals received from the signal input module.

Full Description:
FIELD 
       [0001]    The subject matter herein generally relates to a signal processing circuit. 
       BACKGROUND 
       [0002]    Time delay circuits are used to protect circuits of a server or a computer from inrush current. However, the time delay circuits may delay a power off signal when the circuits stop operating, which will make data in the circuits disorderly or lost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figure. 
           [0004]      FIG. 1  is a block diagram of an embodiment of a signal processing circuit. 
           [0005]      FIG. 2  is a block diagram of a signal processing module of the signal processing circuit of  FIG. 1 . 
           [0006]      FIG. 3  is a circuit diagram of an embodiment of a signal processing circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0007]    Numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. 
         [0008]    Several definitions that apply throughout this disclosure will now be presented. 
         [0009]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0010]      FIG. 1  shows an embodiment of a signal processing circuit  100 . The signal processing circuit  100  can comprise a signal input module  101  and a signal processing module  102 . The signal input module  101  is coupled to a first external circuit  10  to receive a first signal or a second signal. The signal processing module  102  is configured to process the first signal and the second signal and outputs a signal processed to a second external circuit  20 . 
         [0011]      FIG. 2  and  FIG. 3  illustrate an embodiment of the signal processing circuit  100 . The signal processing module  102  can comprise a time delay circuit  1021 , an anti-interference circuit  1022 , and an anti-delay unit  1023 . The time delay circuit  1021  is configured to delay the first signal and the second signal. The anti-interference circuit  1022  is configured to reduce interference to the first signal and the second signal. The anti-delay unit  1023  is configured to eliminate the time delay of the first signal and the second signal. The first signal is output to the second external circuit  20  through the time delay circuit  1021 . The second signal is output to the second external circuit  20  through the time delay circuit  1021  and the anti-delay unit  1023  in that order. 
         [0012]    In the embodiment, the time delay circuit  1021  can comprise a resistor R 5  and a capacitor C 1 . The anti-interference circuit  1022  can comprise a Schmitt trigger U 1 . The anti-delay unit  1023  can comprise a diode D 1 . 
         [0013]    The signal processing module  101  can comprise a first signal input PG 1 , a second signal input PG 2 , a third signal input PG 3 , and resistors R 1 -R 4 . The first signal input PG 1  is coupled to a power terminal V 1  through the resistor R 1  and the resistor R 4  in that order. The second signal input PG 2  is coupled to the power terminal V 1  through the resistor R 2  and the resistor R 4  in that order. The third signal input PG 3  is coupled to the power terminal V 1  through the resistor R 3  and the resistor R 4  in that order. The power terminal V 1  is configured to supply an auxiliary voltage. 
         [0014]    The signal processing module  102  can comprise resistors R 5 -R 8 , the capacitor C 1 , a capacitor C 2 , the Schmitt trigger U 1 , the diode D 1 , and a reset signal terminal PERST. A first terminal of the resistor R 5  is coupled to the power terminal V 1  through the resistor R 4 . A second terminal of the resistor R 5  is coupled to the power terminal V 1  through the resistor R 6 . The second terminal of the resistor R 5  is also coupled to ground through the capacitor C 1 . The diode D 1  and the resistor R 5  are coupled in parallel. An anode of the diode D 1  is coupled to the second terminal of the resistor R 5 . A cathode of the diode D 1  is coupled to the first terminal of the resistor R 5 . The resistor R 1  is coupled to the capacitor C 1  through the cathode of the diode D 1  and the anode of the diode D 1  in that order. The second terminal of the resistor R 5  is coupled to an input  1  of the Schmitt trigger U 1 . An output  2  of the Schmitt trigger U 1  is coupled to a signal terminal S 1  of the second external circuit  20 . A power terminal  3  of the Schmitt trigger U 1  is coupled to the power terminal V 1 . A ground terminal  4  of the Schmitt trigger U 1  is grounded. The reset signal terminal PERST is coupled to the signal terminal S 1  through the resistor R 8 . The signal terminal S 1  of the second external circuit  20  is coupled to the power terminal V 1  through the resistor R 7 . The diode D 1  can be a Schottky diode. In other embodiments, the anti-delay unit  1023  can be other electronic elements which control the capacitor C 1  to discharge rapidly according to the second signal, such as a bipolar junction transistor or a field effect transistor. 
         [0015]    In the embodiment, the first external circuit  10 , the second external circuit  20 , and the signal processing circuit  100  are applied in an electronic device. The first external circuit  10  is configured to output a first signal or a second signal. The second external circuit  20  is configured to enable the electronic device to operate. When the signal terminal S 1  of the second external circuit  20  is at a high level, the electronic device is turned on. When the signal terminal S 1  of the second external circuit  20  is at a low level, the electronic device is turned off. The reset signal terminal PERST is configured to input a signal to reset the electronic device. 
         [0016]    In the embodiment, the first signal is at high level, such as logic 1. The second signal is at a low level, such as logic 0. The first to third signal inputs PG 1 -PG 3  are configured to output the first signal or the second signal synchronously. 
         [0017]    In other embodiments, the signal input module  101  can comprise at least one signal input. The signal input module  101  receives the first signal or the second signal through the at least one signal input. 
         [0018]    When the signal from the first to third signal inputs PG 1 -PG 3  turns into high level, the time delay circuit  1021  delays the signal, and the Schmitt trigger U 1  outputs the signal delayed to the signal terminal S 1  of the second external circuit  20 . A first terminal of the capacitor C 1  coupled to the Schmitt trigger U 1  is at a high level. The electronic device is turned on. 
         [0019]    When the signal from the first to third signal inputs PG 1 -PG 3  turns into low level, the capacitor C 1  discharges rapidly through the diode D 1 . The first terminal of the capacitor C 1  turns into low level. The input  1  of the Schmitt trigger U 1  turns into low level and the signal terminal S 1  turns into low level. The electronic device is turned off 
         [0020]    While the disclosure has been described by way of example and in terms of the embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 7