Patent Abstract:
A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal. The power switch is responsive to the control input to change between the on condition and the off condition to thereby adjust the output current of the DC/DC converter.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/151,971, filed Sep.  1, 1999. More than one reissue application has been filed for U.S. Pat. No. 6,181,120. Specifically, application Ser. No. 10/375,914 was filed on Feb. 26, 2003 as a continuation of the present application, Ser. No. 10/045,169.   
    
    
     FIELD OF THE INVENTION 
     The present invention relates to DC/DC converters. 
     BACKGROUND OF THE INVENTION 
     As the complexity and clock speed of CPUs continue to rise, greater demands are placed on the power supplies (DC/DC converters) that supply the operating voltage to the CPUs. Typically, the operating voltage of CPUs is specified with a relatively tight tolerance to ensure proper operation of the CPU. The tight tolerances on CPU operating voltages are being further narrowed as CPU clock and CPU bus speeds increase, and CPU operating voltages decrease. The decrease in permissible tolerances on CPU operating voltages has resulted in a corresponding increase in the regulation specifications of power supplies that supply operating voltages to CPUs. 
     The current drawn by a CPU generally undergoes frequent variation and rapid changes of substantial magnitude. For example, the current a CPU draws from a power supply may change by as much as 10-75 Amps per microsecond. These frequently varying and rapidly changing demands for substantial amounts of current are referred to as load transients. These extreme load transients cause a corresponding voltage transient on voltage output of the power supply, thereby making it very difficult for a power supply to comply with tight power supply regulation specifications. Many power supplies incorporate very large capacitors to reduce the effect of these large and rapid load transients, and thereby lessen the resultant corresponding voltage transients on the output voltage of the power supply to an acceptable level. However, the use of large capacitors adds significantly to the cost, size and weight of the power supply. 
     In order to reduce the number and size of capacitors needed to lessen the effect of a given load transient on power supply output voltage, a technique known as “droop” is employed. Normally, power supplies are designed to have an output voltage that is essentially independent of the load current. However, in applications where a power supply will be required to comply with tight regulation specifications in a high-load-transient environment, there is an advantage in carefully controlling and/or adjusting the output impedance of the power supply to thereby cause the power supply output voltage to decrease by a predetermined amount in response to an increase in current demanded by or being supplied to the load. 
     In conventional current-mode DC/DC converters, the duty cycle of the DC/DC converter is modulated by a negative-feedback voltage loop to maintain the desired output voltage. The feedback voltage loop has a DC voltage gain which determines the amount of “droop” in the output impedance of the power supply. The DC voltage gain of the feedback loop is, therefore, designed to be relatively low in order to achieve a relatively small amount of droop and thereby maintain a substantial degree of voltage regulation to comply with the tight tolerances placed upon the operating voltage supplied to the CPU. 
     The low DC gain in the feedback loop, however, results in any variations or offsets in the voltages within the DC/DC converter being reflected in a corresponding error in the output voltage of the converter. The only known solution to this problem is to design precise circuitry using components having tight tolerances in order to achieve low-offset voltages and/or precise internal voltages within the DC/DC converter. The inclusion of such precise circuitry adds substantially to the cost and complexity of the converter. 
     Therefore, what is needed in the art is a converter that maintains voltage regulation in a high-load-transient environment. 
     Furthermore, what is needed in the art is a converter which does not depend upon large capacitors to maintain voltage regulation in a high-load transient environment, and is therefore less expensive to build, smaller in size and lighter in weight. 
     Moreover, what is needed in the art is a converter which achieves voltage regulation in a high-load transient environment without the use of precision circuitry, and is therefore less complex and less expensive to build. 
     SUMMARY OF THE INVENTION 
     The present invention provides a DC/DC converter having a controlled output impedance and which provides for a controlled droop in the output voltage in response to load transients. 
     The invention comprises, in one form thereof, a DC/DC converter having an output voltage and sourcing an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal. The power switch is responsive to the control input to change between the on condition and the off condition to thereby adjust the output current of the DC/DC converter. 
     An advantage of the present invention is that droop in the output voltage of the converter in response to a load transient is controlled and reduced. 
     Another advantage of the present invention is that the need for a plurality of large capacitors to maintain regulation of the output voltage in a high-load transient environment is eliminated, and therefore the present invention is less expensive to manufacture, is of a lighter weight and smaller in size than conventional DC/DC converters. 
     A further advantage of the present invention is that it is essentially immune to errors in internal reference and offset voltages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above-mentioned and other features and advantages of this invention, and the manner of attaining them, will become apparent and be better understood by reference to the following description of one embodiment of the invention in conjunction with the accompanying drawings, wherein: 
         FIG. 1A  includes a pair of graphs illustrating how conventional converters droop when a load is applied and then removed. 
         FIG. 1B  includes a pair of graphs that show how the present invention improves droop when a load is applied and then removed; 
         FIG. 2  is a schematic of a conventional converter; 
         FIG. 3  is a schematic of one embodiment of a current mode DC/DC converter with controlled output impedance of the present invention; and 
         FIGS. 4A and 4B  show examples of the summing circuit of FIG.  3 ; 
     
    
    
     Corresponding reference characters indicate corresponding parts throughout the several views. The exemplification set out herein illustrates one preferred embodiment of the invention, in one form, and such exemplification is not to be construed as limiting the scope of the invention in any manner. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings, and particularly to  FIG. 1A , the effect of a load transient upon the output voltage of a conventional converter is illustrated. The targeted no-load output voltage of the converter is V TARGET1 . The actual no-load output voltage of the converter is V 1A . In the case of  FIG. 1A , V TARGET1  is intentionally set equal to V 1A . A load current transient occurs at time T 1A , which results in a contemporaneous and corresponding droop in the converter output voltage to a level below V TARGET1 . As the demand for load current reduces at time T 1A +1, a contemporaneous and corresponding spike in the converter output voltage to a level above V TARGET1  is observed. 
     Referring now to  FIG. 1B , the effect of the same load current transient as shown in  FIG. 1A  is illustrated on a converter having a targeted no-load output voltage of V TARGET2 . However, in the case of  FIG. 1B , the actual no-load output voltage of the converter V 1B  is intentionally set to be a predetermined amount greater than V TARGET2 . By intentionally setting V 1B  a predetermined amount greater than V TARGET2 , the load transient at time T 1B  results in a smaller-magnitude droop in the converter output voltage. More particularly, the droop in output voltage in  FIG. 1B  is only one-half the magnitude of the droop in converter output voltage observed in FIG.  1 A. Thus, for a given load transient and a fixed amount of converter output capacitance, a designer can reduce by one-half the amount of droop in the output voltage of the converter by setting the actual no-load output voltage of the converter to be a predetermined amount greater than the targeted no-load output voltage. Alternatively, the amount of converter output capacitance can be dramatically reduced while maintaining a given amount of droop in the converter output voltage in response to the same given load transient by setting the actual no-load output voltage of the converter to be a predetermined amount greater than the targeted no-load voltage. 
     Referring now to  FIG. 2 , the operation of conventional current-mode DC/DC converter  10  is described. A constant-frequency signal CLK sets SR-Latch  12  and turns on power switch  14  once per every cycle of the constant-frequency signal CLK. Power switch  14  remains on for a fraction of the cycle of the CLK signal (known as the “Duty Cycle”) as determined by the output of comparator  16 . During the “off-time” of power switch  14 , diode  18  conducts current flowing through inductor  20  to load  22 . In an alternate configuration, diode  18  is replaced by a second power switch (not shown), which is controlled in a complementary fashion to power switch  14 . Such a configuration is known as Synchronous Rectification. 
     As will be described in more detail hereinafter, the duty cycle of DC/DC converter  10  is modulated by a negative-feedback voltage loop to maintain the desired output voltage V OUT  across load  22 . In a current-mode converter (as in FIG.  2 ), output voltage regulation is achieved in an indirect fashion by controlling a sensed current. The current through power switch  14  is sensed, and therefore controlled, by current sensor  24 , and signal V ISENSE , which is proportional to the current sensed by current sensor  24 , is issued. However, it is to be understood that either the current through inductor  20  or the current through diode  18  can be sensed instead. 
     To achieve output voltage regulation, output voltage V OUT  is sensed and divided down by the voltage divider formed by R 1  and R 2  to produce the voltage V FB  at node  26 . Error Amp  28  amplifies the difference between V FB  and the voltage reference V REF  at node  30  and produces the error voltage V ERROR  at node  32 . Thus, error amp  28  adjusts the V ERROR  voltage at node  30  as needed to achieve a power switch  14  duty cycle that forces V FB  at node  26  to be equal to V REF . Subtraction circuit  35  subtracts V ISENSE  from V ERROR . Because the current sensed by current sensor  24  is subtracted from V ERROR  in the form of V ISENSE , error amp  28  also adjusts V ERROR  at node  32  in accordance with V ISENSE  to produce the needed duty cycle. This results in an effective control, or programming, of the current sensed by current sensor  24 . Depending on the gain of the signal conditioning block  36 , the V ERROR  signal at node  32  can be proportional to the intra-cycle peaks of the sensed current (known as Peak Current Control) or the V ERROR  signal may be proportional to the average value of the sensed current (known as Average Current Control). 
     To implement either Peak Current or Average Current Control, it is necessary to add frequency compensation to the voltage feedback loop to achieve stability. Frequency compensation is accomplished by C COMP  and R 1 . C COMP  and R 1  add a high-frequency pole into the feedback loop that cancels a zero that is due to the Equivalent Series Resistance (ESR) of the output capacitor C L . Depending on the details of the circuit values, this compensating pole is sometimes not needed. The feedback resistor R FB  is adjusted to control the DC gain of error amplifier  28 , and thereby provide the desired amount of droop in the output voltage V OUT  of converter  10 . Since the voltage V ERROR  at node  32  is proportional to V ISENSE , which represents the current sensed by current sensor  24  and which is proportional to load current I OUT , a reduction in DC gain will cause the output voltage V OUT  to vary with the load current I OUT . In this manner, a controlled droop in the output impedance of converter  10  is achieved. For example, the voltage V ISENSE  may vary by 2V as the load current I OUT  varies from 0 to 10 Amps. If the ratio of R FB  to R 1 , is equal to 10 (ten), the voltage V OUT  will decrease by 0.1V as the load current is increased from 0 to 10 Amps (hence, “Droop”). 
     The fundamental problem with the method of converter  10  in achieving and controlling droop resides in the low DC gain of the voltage feedback loop. This low gain is used to provide the drooping characteristic, but it also has an undesirable side-effect. As a result of this low DC gain, any variations in the V RAMP  signal or DC offsets in current sensor  24  or comparator  16  will be reflected in a corresponding error in the voltage V OUT . For example, if the average value of the voltage V RAMP  has tolerance of ±200 mV, and the ratio of R FB  to R 1  is equal to 20, an additional error term of ±10 mV on the voltage V OUT  will result. The only known solution to this problem is to design precise circuitry in order to achieve low-offset voltages and/or a precise V RAMP  voltage. The inclusion of such precise circuitry adds substantially to the cost and complexity of a DC/DC converter. 
     Referring now to  FIG. 3 , there is illustrated one embodiment of an improved current-mode DC/DC converter  100  of the present invention. DC/DC converter  10  includes SR latch  112  having a constant-frequency signal CLK which sets latch  112  which, in turn, turns on power switch  114 . Power switch  114 , although shown schematically as a conventional switch, is a transistor-based switch having one or more power transistors configured to source current in response to an input signal, which is the output of latch  112 . Switch  114  remains in the on state for a fraction of the period of the CLK signal, which is known as the duty cycle, as determined by comparator  116 . The current flowing through load  122  is sensed by current sensor  124 , which issues signal V ISENSE . The duty cycle of power switch  114  is modulated by a negative voltage feedback loop. Voltage V FE  at node  126  is input to error amplifier  128 . Summing circuit  129  sums voltages V ISENSE  and V OUT . This summed voltage is then divided by a voltage divider formed by R1 and R2, thereby creating voltage V FE  at node  126 . Thus, V ISENSE  is a component of V FB . Error amplifier  128  compares V FB  with V REF , thereby creating V ERROR . Comparator  116  compares V ERROR  with V RAMP . The output of comparator  116  periodically resets latch  112  to thereby determine the duty cycle of power switch  114 . Error amplifier  128  includes, in its negative voltage feedback path R COMP  and C COMP , which provide for the frequency compensation of V FB . The gain of error amplifier  128  is determined by the ratio of R COMP  to R 1 . 
     The most fundamental feature of DC/DC converter  100  is that current sensor  124  is electrically connected to the output voltage feedback loop. More particularly, V ISENESE  is divided by the voltage divider formed by R 1  and R 2 , and this divided portion forms part of V FB . However, it is to be understood that the current through inductor  120  or the current through diode  118  can be sensed and similarly connected to the output voltage feedback loop, rather than the current through power switch  114 . V ISENESE  is connected to the voltage feedback loop without first being frequency compensated by error amplifier  128 , as in conventional DC/DC converter  10  of FIG.  2 . The principle advantage of not performing frequency compensation upon signal V ISENESE  prior to the connection thereof with the output voltage feedback signal is that the gain of error amp  128  is thereby permitted to be arbitrarily high at DC (note the absence of RF), thus providing DC/DC converter  100  excellent output voltage accuracy that is essentially immune to variations in the V RAMP  voltage and offset voltages, etc. 
     To understand how DC/DC converter  100  creates the desired drooping output voltage characteristic, first consider the operation of DC/DC converter  100  under a no-load condition with I OUT =0. In this case, V ISENSE =0, and the output voltage V OUT  of converter  100 , under this no-load condition, is given by Vref (R 1 +R 2 )/R 2 . Note that R 1  and R 2  here are intentionally chosen so that the no-load output voltage of converter  100  is a predetermined amount greater than the desired target voltage. At full load, when I OUT =I MAX , V ISENSE  will equal V ISENSE, MAX , and thus we have V OUT =[V REF (R 1 +R 2 )/R 2 ]−V ISENSE,MAX . Thus, as the current through load  122  increases from zero to full load current, output voltage V OUT  decreases, or droops, by V ISENSE,MAX  Volts. 
     Note especially that the same frequency compensation provided by R COMP  and C COMP  is applied to both the V FB  voltage signal and the V ISENSE  current signal. In this way, average current mode control is implemented without the need for a separate signal conditioning block (Gc(s) in FIG.  2 ). This is another advantage of DC/DC converter  100 . Average current mode control and accurate droop are achieved using a single amplifier. The frequency compensation in DC/DC converter  10  introduces a pole at very low frequency, which is set by the characteristics of error amp  128 , and a zero which is set by R COMP  and C COMP . For the voltage feedback loop, a high DC gain is provided, which makes the output voltage of DC/DC converter  100  essentially immune from errors in V RAMP  and offset voltage errors. Likewise, in regards to current, the high DC gain and averaging characteristic of the frequency compensation provide excellent response to the average value of the sensed current. Because of the current-mode control, the two poles associated with the LC filter formed by inductor  120  and load capacitor  121  are split, with one pole moving to a relatively high frequency and the other pole moving to a relatively low frequency. The zero is placed before the crossover of the frequency compensation loop, which effectively cancels the effect of the low-frequency pole associated with the LC filter formed by inductor  120  and load capacitor  121 . The high frequency gain of error amp  128  is determined by the ratio R COMP /R 1 . This ratio is adjusted to provide suitable high frequency current gain (and the associated pole-splitting of the LC filter poles). The high-frequency pole associated with the LC filter formed by inductor  120  and load capacitor  121  is used to compensate for the zero associated with the ESR of load capacitor  121 . In this manner, a response that is essentially a single-pole response having excellent phase margin is achieved. 
     Referring now to  FIGS. 4A and 4B , two practical circuits are illustrated for the summing of V OUT  and V ISENSE . In  FIG. 4A , error amplifier  128  is configured as a summing amplifier to sum voltages V OUT  and V ISENSE . R 3  has been added between current sensor  124  and node  126 . Note that, in the configuration of  FIG. 4A , it is necessary to divide the voltage V REF  by a factor of two to obtain the correct output voltage V ERROR . In  FIG. 4B , the sensed current signal is summed into the V FB  node  126  as a current. This is a particularly useful approach, because it allows the voltage V REF  to be used directly, rather than being divided by two, and also allows the magnitude of the droop to be easily adjusted by varying the value of R 1 . 
     While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the present invention using the general principles disclosed herein. Further, this application is intended to cover such departures from the present disclosure as come within the known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.

Technology Classification (CPC): 7