Patent Abstract:
A photo detector device configured for use with a display device, the photo detector device comprising a photosensitive transistor formed on a substrate of the display device, the photosensitive transistor being capable of detecting an optical signal and converting the optical signal into a current signal, and a converter formed on the substrate of the display device, the converter being capable of receiving the current signal on a first conductive line and converting the current signal into a voltage signal, the converter comprising a first resistive device coupled between the first conductive line and a reference voltage line, and a first capacitive device coupled in parallel with the first resistive device between the first conductive line and the reference voltage line.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. patent application Ser. No. 11/534,680, filed Sep. 25, 2006. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to an image sensor, and more particularly, to a photo detector device capable of detecting an image input from a stylus, pen, torch or a shadow. 
     With the rapid development in the high-tech industry, pen tablets have been widely applicable to Personal Digital Assistants (PDAs), Personal Computers (PCs) and other electrical appliances used in our daily life. Generally, a pen tablet includes one of a resistor-type, electromagnetic inductance-type, capacitor-type and optoelectronic-type writing panel. As an example of a conventional optoelectronic-type pen tablet, an optical signal may be converted into electrical charges, which in turn may be stored in a capacitor of a detector array including capacitors, optoelectronic components and switch transistors before it is subsequently read. The capacitors may require additional areas and therefore adversely reduce the aperture ratio of the panel. Furthermore, the charges generated by a background light source and an input signal may be stored in the capacitor, adversely resulting in a relatively narrow dynamic range. It may therefore be desirable to have a photo detector device that is able to convert an optical signal into a photocurrent, thereby eliminating the storing capacitors used in the conventional panels. It may also be desirable to have a photo detector device of which the photosensitive transistors and associated circuits may be fabricated simultaneously with the thin film transistors of a liquid crystal display (LCD) device. 
     BRIEF SUMMARY OF THE INVENTION 
     Examples of the invention may provide a photo detector device configured for use with a display device, the photo detector device comprising a photosensitive transistor formed on a substrate of the display device, the photosensitive transistor being capable of detecting an optical signal and converting the optical signal into a current signal, and a converter formed on the substrate of the display device, the converter being capable of receiving the current signal on a first conductive line and converting the current signal into a voltage signal, the converter comprising a first resistive device coupled between the first conductive line and a reference voltage line, and a first capacitive device coupled in parallel with the first resistive device between the first conductive line and the reference voltage line. 
     Examples of the invention may also provide a photo detector device configured for use with a display device, the photo detector device comprising a plurality of first conductive lines extending in parallel with each other, a plurality of second conductive lines extending in parallel with each other and being orthogonal to the plurality of first conductive lines, an array of photosensitive transistors formed on a substrate of the display device, each of the photosensitive transistors being disposed near one of the plurality of first conductive lines and one of the plurality of the second conductive lines and being capable of detecting an optical signal and converting the optical signal into a current signal, and an array of converters formed on the substrate of the display device, each of the converters being capable of receiving the current signal on one of the first conductive lines, converting the current signal into a voltage signal, and comprising a first resistive device coupled between the first conductive line and a reference voltage line, and a first capacitive device coupled in parallel with the first resistive device between the first conductive line and the reference voltage line. 
     Some examples of the invention may also provide a photo detector device configured for use with a display device, the photo detector device comprising a photosensitive transistor formed on a substrate of the display device, the photosensitive transistor being capable of detecting an optical signal and converting the optical signal into a current signal, a switching transistor formed on the substrate of the display device, the switching transistor being capable of driving the photosensitive transistor and being disposed near an intersection of a first conductive line and a second conductive line, the first conductive line and the second conductive line being orthogonal to one another, and a converter formed on the substrate of the display device, the converter being capable of receiving the current signal on the first conductive line and converting the current signal into a voltage signal, the converter comprising a first resistive device coupled between the first conductive line and a reference voltage line, and a first capacitive device coupled in parallel with the first resistive device between the first conductive line and the reference voltage line. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings examples consistent with the invention. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
       In the drawings: 
         FIG. 1A  is a schematic circuit diagram of a photo detector array consistent with an example of the present invention; 
         FIG. 1B  is an enlarged circuit diagram of a photosensitive transistor of the photo detector array illustrated in  FIG. 1A ; 
         FIG. 1C  is an enlarged circuit diagram of a first amplifier module of the photo detector array illustrated in  FIG. 1A ; 
         FIG. 1D  is an enlarged circuit diagram of a second amplifier module of the photo detector array illustrated in  FIG. 1A ; 
         FIG. 1E  is an enlarged circuit diagram of a third amplifier module of the photo detector array illustrated in  FIG. 1A ; 
         FIG. 2A  is a schematic diagram of a photo detector array consistent with another example of the present invention; 
         FIG. 2B  is an enlarged circuit diagram of a photosensitive transistor and a switching transistor of the photo detector array illustrated in  FIG. 2A ; 
         FIG. 2C  is a schematic cross-sectional diagram of a photo detector array incorporated in a thin film transistor liquid crystal display panel consistent with an example of the present invention; 
         FIGS. 3A and 3B  are respectively a cross-sectional view and a top view of a photo detector device consistent with examples of the present invention; 
         FIG. 3C  is a top view of a conventional photo detector device; 
         FIGS. 4A and 4B  are respectively a cross-sectional view and a top view of a photo detector device consistent with examples of the present invention; 
         FIG. 4C  is a top view of another conventional photo detector device; 
         FIG. 5  is a schematic diagram of a photo detector array consistent with still another example of the present invention; 
         FIG. 6A  is a schematic diagram of a photo detector array consistent with yet another example of the present invention; 
         FIG. 6B  is a block diagram of an exemplary readout circuit of the photo detector array illustrated in  FIG. 6A ; 
         FIGS. 6C to 6F  are block diagrams of exemplary current-to-voltage converters of the photo detector array illustrated in  FIG. 6A ; 
         FIG. 7A  is a cross-sectional view of portions of a photo detector array consistent with an example of the present invention; 
         FIG. 7B  is a top view of a layout diagram of the photo detector array illustrated in  FIG. 7A ; 
         FIG. 8A  is a cross-sectional view of portions of a photo detector array consistent with another example of the present invention; and 
         FIG. 8B  is a top view of a layout diagram of the photo detector array illustrated in  FIG. 8A . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 1A  is a schematic circuit diagram of a photo detector array  10  consistent with an example of the present invention. Referring to  FIG. 1A , the photo detector array  10  may include a photosensitive transistor array  14 , and a first amplifier module  11 , a second amplifier module  12  and a third amplifier module  13 . The photosensitive transistor array  14  may include a plurality of photosensitive transistors  14 - 1  formed in rows and columns. A representative photosensitive transistor  14 - 1  is disposed near an intersection of one of a plurality of gate lines  14 -G and one of a plurality of data lines  14 -D orthogonal to the gate lines  14 -G. Each of the plurality of data lines  14 -D is electrically connected to the first amplifier module  11 , which in turn is electrically connected to the second amplifier module  12  and the third amplifier module  13  connected in parallel with the second amplifier module  12 . The photo detector array  10  may further include a first detector  15 - 1  and a second detector  15 - 2 , which are electrically connected to the second amplifier module  12  and the third amplifier module  13 , respectively. 
       FIG. 1B  is an enlarged circuit diagram of the photosensitive transistor  14 - 1  of the photo detector array  10  illustrated in  FIG. 1A . The photosensitive transistor  14 - 1  may function to detect light and serve as a switch. Referring to  FIG. 1B , the photosensitive transistor  14 - 1  may include a first electrode  141 , a second electrode  142  and a gate electrode  143 . The first electrode  141 , which serves as a drain of the photosensitive transistor  14 - 1 , is connected to the gate line  14 -G. The second electrode  142 , which serves as a source of the photosensitive transistor  14 - 1 , is connected to the data line  14 -D. The gate electrode  143  is connected to the gate line  14 -G and thus is short-circuited to the first electrode  141 , which may advantageously prevent parasitic capacitance from accumulation therebetween. In the absence of an input optical signal provided from, for example, a light source such as a stylus or torch, a pressure source such as a force applied from an ordinary pen or fingertip, or even the shadow of an object, only the background light may be detected by the photosensitive transistor  14 - 1  if the gate line  14 -G is selected. The background light is converted to a photo current I B , which is generally a relatively small current. In the presence of an input optical signal, the photosensitive transistor  14 - 1  generates a current I if the gate line  14 -G is selected. The current I includes an image current I M  due to the input optical signal and the photo current I B  due to the background light. The current I is provided to the first amplifier module  11 . 
       FIG. 1C  is an enlarged circuit diagram of the first amplifier module  11  of the photo detector array  10  illustrated in  FIG. 1A . Referring to  FIG. 1C , the first amplifier module  11  may include a first variable resistor  111 , a second variable resistor  112 , a capacitor  113 , an operational amplifier  114  and a resistor  115 . The first amplifier module  11  may function to obtain the image current I M  out of the current I by removing the photo current I B . The resistance of the first variable resistor  111  may vary as the photo current I B  varies. Specifically, the resistance of the first variable resistor  111  may be automatically adjusted in response to the variation in the background light intensity so as to provide differential signal compensation. Therefore, the photo current I B  may be cancelled in the operational amplifier  114  due to a differential amplifier circuit function. As a result, interference caused by the background light may be minimized, which may enhance the system sensitivity and expand the dynamic range of the photo detector array  10 . 
     In the absence of an input optical signal, the first variable resistor  111  may maintain an output voltage of the first amplifier module  11  at a stable level. That is, the gain of the first amplifier module  11  may be designed with a substantially large value (but not infinite) such that the signal response is sensitive enough to determine whether an input optical signal is light or shadow. In one example consistent with the present invention, when an output value is smaller than the level, it is determined that an input optical signal is provided by a light stylus or a light pen. Furthermore, when an output value is greater than the level, it is determined that an input optical signal is provided by a shadow. In another example, when an output value is greater than the level, it is determined that an input optical signal is provided by a light stylus. Furthermore, when an output value is smaller than the level, it is determined that an input optical signal is provided by a shadow. In still another example, the stable level may include a gray scale value “128”, given 8 bits per pixel. A relatively white-color optical input signal has a gray scale value ranging from 128 to 255, while a relatively black-color optical input signal has a gray scale value ranging from 0 to 128. The compensation process may thus compensate for the variation in the background light and the differences of optoelectronic characteristics of the plurality of photosensitive transistors  14 - 1  as well. Consequently, the output voltage of each of the plurality of photosensitive transistors  14 - 1  of the photo detector array  10  may be maintained at a stable level in the absence of an input optical signal. Therefore, a light stylus may be used as an entry tool. Similarly, the shadow of finger, chopstick or ordinary pen may also serve as an entry tool. In one example, an input optical signal having a diameter of approximately 3 millimeter or greater may be detectable by the photo detector array  10 . 
       FIG. 1D  is an enlarged circuit diagram of the second amplifier module  12  of the photo detector array  10  illustrated in  FIG. 1A . Referring to  FIG. 1D , the second amplifier module  12  may include a first resistor  121 , a second resistor  122 , a capacitor  123  and an operational amplifier  124 . The second resistor  122  and the capacitor  123  form a low pass filter. The second amplifier module  12  may function to process a direct-current (dc) component of a signal provided by the first amplifier module  11 . Specifically, the second amplifier module  12  filters out or attenuates frequencies higher than the cutoff frequency of the low pass filter, thereby reducing the high-frequency noise in the dc component. The dc component is generated by an optical input through, for example, a general stylus, pen, torch, finger or chopstick. In one example consistent with the present invention, the photo detector array  10  may include an analog-to-digital converter electrically connected to the second amplifier module  12  at a subsequent stage to further process the dc component. 
       FIG. 1E  is an enlarged circuit diagram of the third amplifier module  13  of the photo detector array  10  illustrated in  FIG. 1A . Referring to  FIG. 1E , the third amplifier module  13  may include a first resistor  131 , a second resistor  132 , a first capacitor  133 , a second capacitor  135  and an operational amplifier  134 . The third amplifier module  13  may serve as a band pass filter, and process an alternating-current (ac) component of a signal provided by the first amplifier module  11 . The ac component is generated by an optical input through, for example, a dedicated light stylus or light pen having a specific output specification such as frequency. The third amplifier module  13  is able to detect a modulated optical signal from the dedicated light stylus, which converts a force applied therethrough on a panel into a frequency. In one example consistent with the present invention, the photo detector array  10  may include a phase-locked-loop (“PLL”) circuit (not shown) electrically connected to the third amplifier module  13  at a subsequent stage to convert the frequency of the dedicated light stylus into a voltage signal. 
     Referring back to  FIG. 1A , each of the first detector  15 - 1  and the second detector  15 - 2  may include a diode (not numbered) and a low pass filter (not numbered) connected in parallel with the diode. The second detector  15 - 2  may be able to detect the amplitude of the signal from the third amplifier module  13 . 
       FIG. 2A  is a schematic diagram of a photo detector array  20  consistent with another example of the present invention. Referring to  FIG. 2A , the photo detector array  20  may be similar to the photo detector array  10  illustrated in  FIG. 1A  except, for example, a photosensitive transistor array  24  replaces the photosensitive transistor array  14 . The photosensitive transistor array  24  may include a plurality of photosensitive transistors  24 - 1  and a plurality of switching transistors  24 - 2  formed in rows and columns. A representative photosensitive transistor  24 - 1  and a representative switching transistor  24 - 2  are disposed near an intersection of one of a plurality of gate lines  24 -G and one of a plurality of data lines  24 -D orthogonal to the gate lines  24 -G. 
       FIG. 2B  is an enlarged circuit diagram of the photosensitive transistor  24 - 1  and the switching transistor  24 - 2  of the photo detector array  20  illustrated in  FIG. 2B . Referring to  FIG. 2B , the photosensitive transistor  24 - 1  may include a first electrode  241 , a second electrode  242  and a gate electrode  243 , which serve as a drain, source and gate of the photosensitive transistor  24 - 1 , respectively. The first electrode  241  and the gate electrode  243  are short-circuited to prevent parasitic capacitance from accumulation therebetween. The switching transistor  24 - 2  may include a first electrode  242 , a second electrode  244  and a gate electrode  245 , which serve as a drain, source and gate of the switching transistor  24 - 2 , respectively. The gate electrode  245  is connected to the gate line  24 -G, and the second electrode  244  is connected to the data line  24 -D. 
     In the absence of an input optical signal provided from, for example, a stylus, an ordinary pen, a torch, a fingertip or even the shadow of an object, only the background light may be detected by the photosensitive transistor  24 - 1  if the gate line  24 -G is selected, which turns on the switching transistor  24 - 2  and the photosensitive transistor  24 - 1 . The background light may be converted to a photo current I B . In the presence of an input optical signal, the photosensitive transistor  24 - 1  generates a current I if the gate line  24 -G is selected. The current I includes an image current I M  due to the input optical signal and the photo current I B  due to the background light. The current I is provided to the first amplifier module  11 . 
       FIG. 2C  is a schematic cross-sectional diagram of the photo detector array  24  incorporated in a thin film transistor liquid crystal display panel  21  consistent with an example of the present invention. Referring to  FIG. 2C , the panel  21  may include a pair of polarizers  201 ,  202 , a pair of glass substrates  203 ,  204 , a pair of alignment films  205 ,  206 , a color filter film  207 , a common electrode  208 , a liquid crystal cell  209 , a backlight unit  210  and a thin film transistor (“TFT”) layer  211 . The photo detector array  24  may be formed in the TFT layer  211 . In one example consistent with the present invention, the gate lines  24 -G illustrated in  FIG. 2B  serve as a portion of gate lines for switching transistors in the TFT layer  211 . 
       FIGS. 3A and 3B  are respectively a cross-sectional view and a top view of a photo detector device  30  consistent with examples of the present invention. Referring to  FIG. 3A , the photo detector device  30  may include a substrate  31 , a gate electrode “G” over the substrate  31 , an insulating layer  32  over the gate electrode G, a semiconductor layer  33  over the insulating layer  32 , and a first source electrode “S 1 ”, a drain electrode “D” and a second source electrode “S 2 ” over the semiconductor layer  33 . To avoid accumulation of parasitic capacitance, the drain electrode D and the gate electrode G may be coupled to one another as illustrated in  FIG. 1A . In the present example, the gate electrode G is aligned with the first source electrode S 1  and the second source electrode S 2 . In other examples, the gate electrode G may cross over a portion of the first source electrode S 1  or the entire first source electrode S 1 . Similarly, the gate electrode G may cross over a portion of the second source electrode S 2  or the entire second source electrode S 2 . Referring to  FIG. 3B , the photo detector device  30  may include two channel widths “W” and therefore two folds of channel width-to-length ratio, i.e., 2 (W/L), L being the channel length, in five unit areas, each of which is substantially equal to a source or drain electrode area. 
       FIG. 3C  is a top view of a conventional photo detector device  31 . To achieve the same two folds of channel width-to-length ratio, a total number of six unit areas are required in the conventional photo detector device  31 , including a first channel width defined by a first set of source, drain and gate electrodes S′, D′ and G′, respectively, and a second channel width defined by a second set of source, drain and gate electrodes S″, D″ and G″, respectively. By comparison, the photo detector device  30  illustrated in  FIG. 3A  or  3 B is more area effective than the conventional photo detector device  31 . 
       FIGS. 4A and 4B  are respectively a cross-sectional view and a top view of a photo detector device  40  consistent with examples of the present invention. Referring to  FIG. 4A , the photo detector device  40  may include a substrate  41 , a first gate electrode “G 1 ” and a second gate electrode “G 2 ” over the substrate  41 , an insulating layer  42  over the gate electrodes G 1  and G 2 , a semiconductor layer  43  over the insulating layer  42 , and a first source electrode “S 1 ”, a first drain electrode D 1 , a second drain electrode D 2  and a second source electrode S 2  over the semiconductor layer  43 . The first gate electrode G 1  and the second gate electrodes G 2  are the gates of a photosensitive transistor and a switching transistor, respectively. To avoid accumulation of parasitic capacitance, the first drain electrode D 1  and the first gate electrode G 1  may be coupled to one another as illustrated in  FIG. 2A . The first gate electrode G 1  may overlap the first source electrode S 1  or the second drain electrode D 2  or both. The second gate electrode G 2  is aligned with the second source electrode S 2  and the second drain electrode D 2 . In other examples, however, the second gate electrode G 2  may cross over a portion of the second source electrode S 2  or the entire second source electrode S 2 . Similarly, the second gate electrode G 2  may cross over a portion of the second drain electrode D 2  or the entire second drain electrode D 2 . Referring to  FIG. 4B , the photo detector device  40  includes two channel widths “W” and therefore two folds of channel width-to-length ratio, i.e., 2 (W/L), in seven unit areas. 
       FIG. 4C  is a top view of another conventional photo detector device  41 . To achieve the same two folds of channel width-to-length ratio, a total number of eight unit areas are required in the conventional photo detector device  41 , including a first channel width defined by a first set of source, drain and gate electrodes S′, D′ and G′, respectively, and a second channel width defined by a second set of source, drain and gate electrodes S″, D″ and G″, respectively. A third transistor including S′, G″′ and S″′ serves as a switching transistor. By comparison, the photo detector device  40  illustrated in  FIG. 4A  or  4 B is more area effective than the conventional photo detector device  41 . 
       FIG. 5  is a schematic diagram of a photo detector array  50  consistent with still another example of the present invention. Referring to  FIG. 5 , the photo detector array  50  may be similar to the photo detector array  20  illustrated in  FIG. 2A  except, for example, a photosensitive transistor array  54  replaces photosensitive transistor array  24 . The photosensitive transistor array  54  may include a plurality of photosensitive transistors  54 - 1  and a plurality of switching transistors  54 - 2  formed in rows and columns. A representative photosensitive transistor  54 - 1  and a representative switching transistor  54 - 2  are disposed near an intersection of one of a plurality of gate lines  24 -G and one of a plurality of data lines  24 -D orthogonal to the gate lines  24 -G. The switching transistor  54 - 2  may include a gate (not numbered) coupled to one gate line  24 -G, a drain (not numbered) coupled to the V DD , and a source (not numbered). Skilled persons in the art will understand that the drain and source of a transistor may be exchangeable, depending on the voltage levels to which they are connected. The photosensitive transistor  54 - 1  may include a drain (not numbered) coupled to the source of the switching transistor  54 - 2 , a source (not numbered) coupled to one data line  24 -D, and a gate (not numbered) coupled to its drain. 
       FIG. 6A  is a schematic diagram of a photo detector array  60  consistent with yet another example of the present invention. Referring to  FIG. 6A , the photo detector array  60  may include a photosensitive transistor array  64 , a plurality of current-to-voltage converters  61 - 1  to  61 -N, N being a natural number, and a readout circuit  62 . The photosensitive transistor array  64  may include one of the photosensitive transistor arrays  14 ,  24  and  54  illustrated in  FIGS. 1A ,  2 A and  5 , respectively. As shown here, photosensitive transistor array  64  comprises the photosensitive transistor array  54  of  FIG. 5 . Each of the current-to-voltage converters  61 - 1  to  61 -N may include a circuit capable of performing current to voltage transformation for a corresponding one of photo currents I 1  to I N . The circuit may include a resistor-capacitor network, and may further include a rectifier. The readout circuit  62  may be configured to calculate the coordinates of an optical source that causes a photo current. The circuit structure and functions of the converters  61 - 1  to  61 -N and the readout circuit  62  will be discussed below. 
       FIG. 6B  is a block diagram of an exemplary readout circuit of the photo detector array  60  illustrated in  FIG. 6A . Referring to  FIG. 6B , the readout circuit  62  may include an N-to-1 multiplexer  62 - 1 , an amplifier circuit  62 - 2 , an analog-to-digital converter (ADC)  62 - 3 , a micro computer unit (MCU)  62 - 4  and a timing generator  62 - 5 . The multiplexer  62 - 1  may provide a voltage signal from the converters  61 - 1  to  61 -N to the amplifier circuit  62 - 2  in a sequential order. The voltage signal may be amplified in the amplifier circuit  62 - 2  and then sampled in the ADC  62 - 3 . The MCU  62 - 4  may determine the coordinates of an optical source that causes a photo current based on a digital output from the ADC  62 - 3 . The timing generator  62 - 5  is able to synchronize the operations of the multiplexer  62 - 1 , ADC  62 - 3  and MCU  62 - 4  based on synchronous signals used in the photosensitive transistor array  64  for gate synchronization. The readout circuit  62  in one example may be formed in integrated circuits, which may facilitate the fabrication of the photo detector array  60 . The photosensitive transistor array  64  and the current-to-voltage converters  61 - 1  may be formed on the same panel of an LCD with the thin film transistors of the LCD at the sacrifice of approximately 10% of aperture ratio. 
       FIGS. 6C to 6F  are block diagrams of exemplary current-to-voltage converters of the photo detector array  60  illustrated in  FIG. 6A . Referring to  FIG. 6C , in one example, a current-to voltage converter  61 -J, J being one of 1 to N, may include a first resistor labeled R 1 , a second resistor R 2 , a first capacitor C 1 , a second capacitor C 2  and a diode DO. The first resistor R 1  may include a gate and a drain, both of which are coupled to one data line  24 -D, and a source coupled to a reference voltage rail such as a ground rail GND. The first capacitor C 1  is coupled between the one data line  24 -D and the ground rail GND. The diode DO may include a gate and a drain, both of which are coupled to the one data line  24 -D, and a source coupled to the readout circuit  62 . The second resistor R 2  may include a gate and a drain, both of which are coupled to the source of the diode DO, and a source coupled to the ground rail GND. The second capacitor C 2  is coupled between the source of the diode DO and the ground rail GND. 
     The first and second resistors R 1  and R 2  may include a structure similar to that of a thin film transistor (TFT) of a liquid crystal display (LCD) device, and may be fabricated simultaneously with the TFTs of the LCD device in substantially the same process for fabricating the TFTs of the LCD. The first and second capacitors C 1  and C 2  may include a structure similar to that of a pixel capacitor of the TFT LCD, and may be fabricated simultaneously with the pixel capacitors of the TFT LCD. The diode DO, which may serve as a rectifier, includes a transistor structure similar to that of the TFT of the LCD device, and may be fabricated simultaneously with the TFTs of the LCD. 
     Referring to  FIG. 6D , in another example, a current-to-voltage converter  61 -K, K being one of 1 to N, may include a third resistor R 3  and a third capacitor C 3 . The third resistors R 3  may include a gate and a drain, both of which are coupled to one data line  24 -D and the readout circuit  62 , and a source coupled to the ground rail GND. The third capacitor C 3  includes one terminal coupled to the one data line  24 -D and the readout circuit  62 , and the other terminal coupled to the ground rail GND. 
     Referring to  FIG. 6E , in still another example, a current-to-voltage converter  61 -L, L being one of 1 to N, may be similar to the current-to-voltage converter  61  -J illustrated in  FIG. 6C  except that, for example, resistors R′ 1  and R′ 2  replace resistors R 1 , and R 2 . Unlike the transistor structure of the resistors R 1  and R 2  illustrated in  FIG. 6C , each of the resistors R′ 1  and R′ 2  may include a thin film of semiconductor material defined between electrodes. The resistors R′ 1  and R′ 2  may have a structure similar to that of a semiconductor channel in a TFT, and may be fabricated simultaneously with the TFTs of the LCD. 
     Referring to  FIG. 6F , in yet another example, a current-to-voltage converter  61 -M, M being one of 1 to N, may be similar to the current-to-voltage converter  61 -K illustrated in  FIG. 6D  except that, for example, resistor R′ 3  replaces resistor R 3 . Unlike the transistor structure of the resistor R 3  illustrated in  FIG. 6D , the resistor R′ 3  may include a thin film of semiconductor material defined between electrodes. The resistor R′ 3  may have a structure similar to that of a semiconductor channel in a TFT, and may be fabricated simultaneously with the TFTs of the LCD. 
       FIG. 7A  is a cross-sectional view of portions of a photo detector array  70  consistent with an example of the present invention. Referring to  FIG. 7A , the photo detector array  70  may include the photosensitive transistor  24 - 1  and switching transistor  24 - 2  illustrated in  FIG. 2A , and the third resistor R 3  and third capacitor C 3  illustrated in  FIG. 6D . The photosensitive transistor  24 - 1 , switching transistor  24 - 2 , third resistor R 3  and third capacitor C 3  may be formed on a same substrate  71  in substantially the same processes for fabricating a switching TFT array  79  (illustrated in  FIG. 7B ) of a display. The processes may include forming a patterned metal layer  72  over the substrate  71 , which may eventually serve as gates for the transistors  24 - 1 ,  24 - 2  and  79 , and a bottom electrode for the third capacitor C 3 . Next, an insulating layer  73  such as a silicon nitride layer, a silicon layer  74 , either amorphous or polycrystalline, and a patterned dielectric layer  75  may be sequentially formed over the patterned metal layer  72 . Next, a semiconductor layer  76  such as a doped amorphous silicon layer may be formed over the silicon layer  74  and the patterned dielectric layer  75 . The semiconductor layer  76  may be etched to expose portions of the patterned dielectric layer  75  and the semiconductor layer  76 . Next, a metal layer  77  may be formed over the semiconductor layer  76 , which may fill the exposed portions of the semiconductor layer  76  to form source and drain contacts. The metal layer  77  may serve as a top electrode for the third capacitor C 3 . Furthermore, third resistor R 3  may include a transistor structure similar to that of the photosensitive transistor  24 - 1 . 
       FIG. 7B  is a top view of a layout diagram of the photo detector array  70  illustrated in  FIG. 7A . Referring to  FIG. 7B , vias  78  may be formed to electrically couple the drain and gate of the photosensitive transistor  24 - 1 . In the present example, the switching transistor  24 - 2  and the switching TFT  79  have a gate common to one another. In other examples, however, the switching transistor  24 - 2  may have a gate separated from that of the switching TFT  79 . Skilled persons in the art will understand that a voltage provided by the current-to-voltage converter such as the converter  61 -K to the readout circuit may be adjusted by changing the parameters such as the drain voltage of the photosensitive transistor  24 - 1 , the dimensions each of the photosensitive transistor  24 - 1 , switching transistor  24 - 2 , third resistor R 3  and third capacitor C 3  such as the channel length, channel width and gate oxide thickness thereof. 
       FIG. 8A  is a cross-sectional view of portions of a photo detector array  80  consistent with another example of the present invention. Referring to  FIG. 8A , the photo detector array  80  may be similar to the photo detector array  70  illustrated in  FIG. 7A  except that, for example, the resistor R′ 3  replaces resistor R 3 . The resistor R′ 3  may include a diffused resistor formed by the amorphous silicon layer  74  defined between related source and drain contacts.  FIG. 8B  illustrates a top view of a layout diagram of the photo detector array  80  with an RC network including the resistor R′ 3  and the capacitor C 3 . 
     It will be appreciated by those skilled in the art that changes could be made to one or more of the examples described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular examples disclosed, but it is intended to cover modifications within the scope of the present invention as defined by the appended claims. 
     Further, in describing certain illustrative examples of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.

Technology Classification (CPC): 7