Patent Abstract:
A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal.

Full Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
   This application is based on and claims priority from Korean Patent Application No. 10-2008-0012208, filed on Feb. 11, 2008, the disclosure of which is incorporated herein in its entirety by reference. 
   BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present disclosure relates to a level shifting circuit, and more particularly, to a level shifting circuit capable of maintaining a duty rate irrespective of a voltage change and capable of fixing its output to a specific voltage level. 
   2. Discussion of the Related Art 
   Mobile devices guarantee proper performance during an extended period of time using a limited battery. A variety of methods have been introduced in order to guarantee such performance one of which is to use different voltages in different block units. In this case, a high voltage is applied to a block requiring a high performance, and a low voltage is applied to a block requiring a low performance. 
   Since blocks use different voltages, a leakage current increases due to a voltage difference between interfaces of different blocks or when a problem occurs in a circuit operation. 
   To address these problems, a level shifter is used. The level shifter changes a level of a received voltage. The level shifter is disposed between blocks that use different voltages, thereby preventing the leakage current or circuit malfunction that may occur in blocks using different voltages. 
   SUMMARY OF THE INVENTION 
   Embodiments of the present invention seek to provide a level shifting circuit capable of maintaining a duty rate irrespective of a voltage change. 
   Further, embodiments of the present invention seek to provide a level shifting circuit that fixes an output to a specific voltage level for a specific mode. 
   Furthermore, embodiments of the present invention seek to provide a level shifting circuit that blocks parts of signal transfer units from an operation voltage or a ground for a specific mode. 
   A level shifting circuit, according to an exemplary embodiment of the present invention, comprises a first level shifting unit comprising a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal. 
   The first and second operation control units may connect some of the signal transfer units of the first and second level shifting units to ground, or to a first voltage or to a second voltage in response to a level of the clamping signal. 
   Each of the first and second operation control units may comprise a gate receiving the clamping signal; a first end connected to a signal transfer unit; and a second end connected to the ground, the first voltage, or the second voltage. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Exemplary embodiments of the present invention will become apparent by reference to the following detailed description taken in conjunction with the attached drawings, wherein: 
       FIG. 1  is a block diagram of a level shifting circuit according to an exemplary embodiment of the present invention; 
       FIG. 2  is a circuit diagram of the level shifting circuit shown in  FIG. 1  according to an exemplary embodiment of the present invention; 
       FIG. 3  is a circuit diagram of the level shifting circuit shown in  FIG. 1  according to an exemplary embodiment of the present invention; and 
       FIG. 4  is a circuit diagram of a level shifting circuit according to an exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements across various figures. 
     FIG. 1  is a block diagram of a level shifting circuit according to an exemplary embodiment of the present invention. Referring to  FIG. 1 , the level shifting circuit comprises a first level shifting unit  110 , a first operation control unit  130 , a second level shifting unit  120 , a second operation control unit  140 , a signal output unit  190 , and a clamping unit  170 . 
   The first level shifting unit  110  and the second level shifting unit  120  comprises a plurality of signal transfer units that transit-delay a signal. For example, each of the first level shifting unit  110  and the second level shifting unit  120  may comprise four signal transfer units. The first level shifting unit  110  and the second level shifting unit  120  receive a logic signal input through IN. Each of the first operation control unit  130  and the second operation control unit  140  is connected to the first level shifting unit  110  and the second level shifting unit  120 , respectively, so that each of the first operation control unit  130  and the second operation control unit  140  inactivates some of the signal transfer units. 
   Each signal transfer unit comprises a plurality of signal transfer stages. When a signal input into each signal transfer unit transits from a logic high level to a logic low level, and from a logic low level to a logic high level, the signal passes through different signal transfer stages. Therefore, a transition delay time of the first level shifting unit  110  and the second level shifting unit  120 , when the signal transits from a logic high level to a logic low level, and when the signal transits from a logic low level to a logic high level are different from each other. 
   When the voltage level supplied to the signal transfer unit changes, the transition delay time of the signal transfer stages included in the signal transfer unit changes so that the transition delay time of the first level shifting unit  110  and the second level shifting unit  120 , when the signal transits from a logic high level to a logic low level may change, and when the signal transits from a logic low level to a logic high level may change. 
   In the present embodiment, although levels of supplied operation voltages VDDA and VDDB change, a signal transfer path is selected so that the transition delay time of the first level shifting unit  110  and the second level shifting unit  120  when the signal transits from the logic high level to the logic low level, and when the signal transits from the logic low level to the logic high level change by the same amount of time. Therefore, a duty rate of output signals of the first level shifting unit  110  and the second level shifting unit  120  may not change. 
   Referring to  FIG. 1 , the first level shifting unit  110  and the second level shifting unit  120  are connected in parallel. An average signal of output signals of the first level shifting unit  110  and the second level shifting unit  120  is output to output ends of the first level shifting unit  110  and the second level shifting unit  120 . The signal transfer path is selected so that the transition delay time of the average signal when the signal transits from a logic high level to a logic low level, and the transition delay time of the average signal when the signal transits from a logic low level to a logic high level change by the same amount of time. 
   The signal output unit  190  is connected to the output ends of the first level shifting unit  110  and the second level shifting unit  120 , transit-delays the average signal of the output ends, and generates an output signal OUT. 
   The clamping unit  170  fixes the output ends of the first level shifting unit  110  and the second level shifting unit  120  to a previously determined voltage level in response to a clamping signal CLAMP. Although the previously determined voltage level is the second voltage VDDB in an exemplary embodiment, it may be another voltage level. 
   The first operation control unit  130  inactivates some of the signal transfer units  112 ,  114 ,  116 , and  118  of the first level shifting unit  110  in response to the clamping signal CLAMP. The second operation control unit  140  inactivates some of the signal transfer units  122 ,  124 ,  126 , and  128  of the second level shifting unit  120  in response to the clamping signal CLAMP. To this end, some of the signal transfer units  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126 , and  128  are blocked from ground, so that some signal transfer units can be inactivated. 
   For example, a first sub control unit  132  is connected between the second signal transfer unit  114  and ground, so that the second transfer unit  114  is connected to ground or is blocked from ground by the first sub control unit  132 . Likewise, the second through fifth sub control units  134 ,  142 ,  144 , and  146  connect the fourth, fifth, seventh, and eighth signal transfer units  118 ,  122 ,  126 , and  128 , respectively, to ground or are blocked from ground. 
     FIG. 2  is a circuit diagram of the level shifting circuit shown in  FIG. 1  according to an exemplary embodiment of the present invention. Referring to  FIG. 2 , the clamping unit  170  may comprise a transistor PX 0 . For example, the transistor PX 0  may comprise a gate receiving the clamping signal CLAMP, a first end connected to the second voltage VDDB, and a second end connected to an output end of the first level shifting unit  110  and the second level shifting unit  120 . The first and second ends may be a source and drain, respectively. Alternatively, the first and second ends may be a drain and source, respectively. 
   When the clamping signal CLAMP has a logic low level, the transistor PX 0  is turned on so that the output ends of the first level shifting unit  110  and the second level shifting unit  120  are fixed to the second voltage VDDB irrespective of the average output signal of the first level shifting unit  110  and the second level shifting unit  120 . However, when the clamping signal has a logic high level, the transistor PX 0  is turned off so that the average signal of the output signals of the first level shifting unit  110  and the second level shifting unit  120  is output to the output ends of the first level shifting unit  110  and the second level shifting unit  120 . 
   Each sub control unit  132 ,  134 ,  142 ,  144 , and  146  may comprise respective transistors NX 2  through NX 6 . For example, the transistor NX 2  may comprise a gate receiving the clamping signal CLAMP, a first end connected to the signal transfer unit  114 , and a second end connected to ground. 
   When the clamping signal CLAMP has a logic high level, the transistor NX 2  is turned on so that the signal transfer unit  114  is connected to ground and performs a signal transit delay operation. However, when the clamping signal CLAMP has a logic low level, the transistor NX 2  is turned off and the signal transfer unit  114  is blocked from ground and does not operate. As such, a logic level of the clamping signal CLAMP is adjusted in order to determine whether to operate the signal transfer unit  114 . If it is not necessary to operate the signal transfer unit  114 , a leakage current of the signal transfer unit  114  can be prevented. 
   The first through fourth signal transfer units  112 ,  114 ,  116 , and  118  included in the first level shifting unit  110  are used to transit-delay a signal, and may be inverters or differential amplifiers. For example, the first, third, and fourth signal transfer units  112 ,  116 , and  118  may be inverters, and the second signal transfer unit  114  may be a differential amplifier. The fourth signal transfer unit  118  may perform a pull-up/pull-down function. Likewise, for example, the sixth through eighth signal transfer units  124 ,  126 , and  128  may be inverters, and the fifth signal transfer unit  112  may be a differential amplifier. The seventh signal transfer unit  126  may perform the pull-up/pull-down function. Each signal transfer unit may be a signal transit delay unit other than an inverter and a differential amplifier. 
   Each signal transfer unit comprises a plurality of signal transfer stages. For example, the first signal transfer unit  112  may comprise a PMOS transistor P 10  and an NMOS transistor N 10 . When an input signal IN transits from a logic high level to a logic low level, the input signal IN passes through the PMOS transistor P 10 . When the input signal IN transits from a logic low level to a logic high level, the input signal IN passes through the NMOS transistor N 10 . 
   A pass time (transit delay time) of the PMOS transistor P 10  and the NMOS transistor N 10  changes according to a level of the first voltage VDDA supplied to the first signal transfer unit  112 . A gate-source voltage of the PMOS transistor P 10  and the NMOS transistor N 10  changes according to the level of the first voltage VDDA. When the gate-source voltage is high, the pass time of the PMOS transistor P 10  and the NMOS transistor N 10  decreases, whereas when the gate-source voltage is low, the pass time of the PMOS transistor P 10  and the NMOS transistor N 10  increases. 
   A transit delay time of the first signal transfer unit  112  changes according to the logic level of the input signal IN and the level of the first voltage VDDA. Likewise, a transit delay time of the signal transfer units  114 ,  116 ,  118 ,  122 ,  124 ,  126 , and  128  changes according to the logic level of the input signal IN and the level of the supplied voltages VDDA and VDDB, and thus a transit delay time of the first and second level shifting units  110  and  120  changes. 
   In an embodiment of the present invention, although levels of supplied operation voltages VDDA and VDDB change, transistors are selected wherein the transition delay time of the first level shifting unit  110  and the second level shifting unit  120  when the signal transits from a logic high level to a logic low level, and when the signal transits from a logic low level to a logic high level change by the same amount of time. 
   Hereinafter, an operation where the first voltage VDDA is lower than the second voltage VDDB will now be described. 
   When the input signal IN transits from a first voltage VDDA level (logic high level) to a ground voltage level (logic low level), the transistors P 10 , N 20 , and N 21  of the first level shifting unit  110  and transistors P 31 , N 41 , and P 43  of the second level shifting unit  120  are turned on. Therefore, the input signal IN passes through the transistors P 10 , N 20 , and P 21  of the first level shifting unit  110 , and passes through the transistors P 31 , N 41 , and P 43  of the second level shifting unit  120 . 
   In this case, since the first voltage VDDA is lower than the second voltage VDDB, the gate-source voltage of the transistor P 10  is lower than that of the transistor P 21 . Therefore, a pass time of the transistor P 10  is longer than that of the transistor P 21 . Likewise, the pass time of the transistor N 20  included in the first level shifting unit  110  is longer than that of the transistor P 21 . The pass time of the transistors P 31  and N 41  included in the second level shifting unit  120  is long and the pass time of the transistor P 43  is short. Hereinafter, a long pass time of a transistor is indicated by “L”, and a short pass time is indicated by “S”. 
   Therefore, the total pass time of the first level shifting unit  110  is “L(P 10 )+L(N 20 )+S(P 21 )=2L1S”. The total pass time of the second level shifting unit  120  is “L(P 31 )+L(N 41 )+S(P 43 )=2L1S”. Thus, an average pass time of the first and second level shifting units  110  and  120  is “2L1S”. 
   When the input signal IN transitions from a ground voltage level (logic low level) to a logic high level (first voltage VDDA level), the transistors N 10 , P 11 , and N 21  of the first level shifting unit  110  and transistors P 40 , P 41 , and N 43  of the second level shifting unit  120  are turned on. Therefore, the input signal IN passes through the transistors N 10 , P 11 , and N 21  of the first level shifting unit  110 , and passes through the transistors P 40 , P 41 , and N 43  of the second level shifting unit  120 . 
   In this case, since the first voltage VDDA is lower than the second voltage VDDB, the pass time of the transistors N 10 , P 11 , and N 21  included in the first level shifting unit  110  is long. The pass time of the transistor N 40  included in the second level shifting unit  120  is long and the pass time of the transistors P 41  and N 43  is short. 
   Therefore, the total pass time of the first level shifting unit  110  is “L(N 10 )+L(P 11 )+L(N 21 )=3L”. The total pass time of the second level shifting unit  120  is “L(N 40 )+L(P 41 )+S(N 43 )=1L2S”. Thus, an average pass time of the first and second level shifting units  110  and  120  is “2L1S”. 
   Hereinafter, an operation where the first voltage VDDA is higher than the second voltage VDDB will now be described. 
   When the input signal IN transitions from a logic high level to a logic low level, since the first voltage VDDA is higher than the second voltage VDDB, the pass time of the transistors P 10  and N 20  included in the first level shifting unit  110  is short and the pass time of the transistor P 21  is long. The pass time of the transistors P 31  and N 41  included in the second level shifting unit  120  is short and the pass time of the transistor P 43  is long. 
   Therefore, the total pass time of the first level shifting unit  110  is “S(P 10 )+S(N 20 )+L(P 21 )=1L2S”. The total pass time of the second level shifting unit  120  is “S(P 31 )+S(N 41 )+L(P 43 )=1L2S”. Thus, the average pass time of the first and second level shifting units  110  and  120  is “1L2S”. 
   When the input signal IN transitions from a logic low level to a logic high level (first voltage VDDA level), since the first voltage VDDA is higher than the second voltage VDDB, the pass time of the transistors N 10 , P 11 , and N 21  included in the first level shifting unit  110  is short. The pass time of the transistor N 40  included in the second level shifting unit  120  is short and the pass time of the transistors P 41  and N 43  is long. 
   Therefore, the total pass time of the first level shifting unit  110  is “S(N 10 )+S(P 11 )+S(N 21 )=3S”. The total pass time of the second level shifting unit  120  is “S(N 40 )+L(P 41 )+L(N 43 )=2L1S”. Thus, an average pass time of the first and second level shifting units  110  and  120  is “1L2S”. 
   During a level change in the first and second voltages VDDA and VDDB, when the logic level of the input signal IN transitions, the average pass time of the first and second level shifting units  110  and  120  transitions between 2L1S and 1L2S. In more detail, the transition delay time of the average signal when the signal transitions from a logic high level to a logic low level, and the transition delay time of the average signal when the signal transitions from a logic low level to a logic high level changes by the same amount of time. Therefore, a duty rate of the output signals OUT of the first level shifting unit  110  and the second level shifting unit  120  remains unchanged. 
     FIG. 3  is a circuit diagram of the level shifting circuit shown in  FIG. 1  according to an exemplary embodiment of the present invention. In comparison with  FIGS. 2 and 3 , the level shifting circuit shown in  FIG. 2  comprises a transistor NX 1 , whereas the level shifting circuit shown in  FIG. 3  comprises a transistor PX 4 . Since the construction of the level shifting circuit shown in  FIG. 3  corresponds to that of the level shifting circuit shown in  FIG. 2 , the detailed description thereof will not be repeated. 
     FIG. 4  is a circuit diagram of a level shifting circuit according to an exemplary embodiment of the present invention. Referring to  FIG. 4 , first and second level shifting units  110  and  120  correspond to the first and second level shifting units  110  and  120 , and thus the detailed description thereof will not be repeated. 
   A clamping unit  170  that comprises an NMOS transistor NX 0  differs from the clamping unit  170  shown in  FIG. 2 . The transistor NX 0  may comprise a gate receiving a clamping signal CLAMP, a first end connected to ground, and a second end connected to output ends of the first and second level shifting units  110  and  120 . 
   When the clamping signal CLAMP has a logic high level, the transistor NX 0  is turned on, and the output ends of the first and second level shifting units  110  and  120  are fixed to a ground voltage irrespective of an average output signal of the first and second level shifting units  110  and  120 . Meanwhile, if the clamping signal CLAMP has a logic low level, the transistor NX 0  is turned off, and the average output signal of the first and second level shifting units  110  and  120  is output to the output ends of the first and second level shifting units  110  and  120 . 
   First and second operation control units  130  and  140  that comprise PMOS transistors PX 1  through PX 6  are distinguished from the first and second control units  130  and  140  shown in  FIG. 2 . For example, the transistor PX 1  may comprise a gate receiving a clamping signal CLAMP, a first end connected to a signal transfer unit  118 , and a second end connected to a second voltage VDDB. 
   When the clamping signal CLAMP has a logic low level, the transistor PX 1  is turned on so that the signal transfer unit  118  is connected to the second voltage VDDB and performs a signal transit delay operation. However, when the clamping signal CLAMP has a logic high level, the transistor PX 1  is turned off and the signal transfer unit  118  is blocked from the second voltage VDDB and does not operate. Therefore, a logic level of the clamping signal CLAMP is adjusted in order to determine whether to operate the signal transfer unit  118 . If it is not necessary to operate the signal transfer unit  118 , a leakage current of the signal transfer unit  118  can be prevented. 
   The level shifting circuit shown in  FIG. 2  may not comprise signal transfer units  118  and  126  and sub control units  134  and  144 . In this case, the first level shifting unit  110  may comprise a first inverter receiving an input signal and operating based on a first voltage, a first differential amplifier connected to an output end of the first inverter and operating based on a second voltage, and a second inverter in parallel to the first differential amplifier and connected to an output end of the first inverter and operating based on the first voltage. The first control unit may comprise a first sub control unit connected between the first differential amplifier and ground. The clamping unit may be connected between an output end of the first differential amplifier and the second voltage. The second level shifting unit may comprise a second differential amplifier receiving the input signal and operating based on the second voltage, a third inverter receiving the input signal, connected in parallel to the second differential amplifier, and operating based on the first voltage, and a fourth inverter connected to an output end of the second differential amplifier. The second operation control unit may comprise a second sub control unit connected between the second differential amplifier and ground and a third sub control unit connected between the third inverter and ground. The clamping unit may be connected between an output end of the fourth inverter and the second voltage. 
   The level shifting circuit according to exemplary embodiments of the present invention is capable of maintaining a duty rate irrespective of a voltage change, and is capable of fixing an output to a specific voltage level for a specific mode. 
   Further, parts of signal transfer units are blocked from an operation voltage or a ground for a specific mode, thereby preventing a leakage current. 
   Although exemplary embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.

Technology Classification (CPC): 7