Patent Abstract:
The present invention discloses a level shift device which comprises: a level shift circuit for receiving an input with a first voltage level and generating a first signal and a second signal with a second voltage level; and an output circuit which generates an output according to the first signal and the second signal.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a level shift device, and in particular to a level shift device capable of providing about the same positive and negative duty cycles, and a method for the same. 
         [0003]    2. Description of the Related Art 
         [0004]    To reduce power consumption, it is a trend to decrease the operational voltage within a circuit chip to, e.g., 1.2V or lower, but the communication between circuit chips operates in a higher voltage such as 3.3V. For this reason, a level shift device is required as an input/output interface circuit to shift the operational level within a circuit chip to a higher level for inter-chip communication.  FIG. 1  shows the basic structure of a conventional level shift circuit  10 , which comprises two PMOS transistors M 1  and M 2 , and two NMOS transistors M 3  and M 4 . Assuming the function of the circuit is to convert the voltage level from 1.2V to 3.3V, the input IN in the shown circuit may thus be an operational voltage of 1.2V (the first operational voltage), and the voltage supplied from the voltage source VP 2  may be 3.3V (the second operational voltage). 
         [0005]    Referring to  FIGS. 1 and 2 , the conventional level shift circuit operates as follows. At time T 0 , the initial state of the circuit, the input IN is at the low level of the first operational voltage (e.g., 0V), while the inverted input INB is at the high level of the first operational voltage (e.g., 1.2V). Because the inverted input INB is at the high level, the NMOS transistor M 4  is ON, whereby the node B is grounded through the NMOS transistor M 4  and is at the low level of 0V. The voltage level of the node B is exactly the voltage level of the output OUT, which is thus also at the low level of 0V (the low level of the second operational voltage). Because the node B is low, the PMOS transistor M 1  is ON, whereby the voltage VP 2  reaches the node A through the PMOS transistor M 1  so that the node A is at a high level equivalent to VP 2  (the high level of the second operational voltage, such as 3.3V). Because the node A is high, the PMOS transistor M 2  is OFF; the voltage VP 2  does not affect the voltage level at the output OUT. 
         [0006]    When it is desired for the circuit to generate a high voltage level output, as shown at time T 1  in  FIG. 2 , the input IN switches from low to high, whereby the NMOS transistor M 3  turns ON so that the node A is grounded through NMOS transistor M 3 . However, during the transition state, the PMOS transistor M 1  is still partially conductive, and therefore the voltage VP 2  still affects the node A; the voltage at the node A does not reach low instantly, but rather drops slowly. The PMOS transistor M 2  is controlled by the node A and thus gradually turns ON until time T 2 . At time T 2 , the PMOS transistor M 2  fully turns ON, and from this time on the voltage VP 2  completely passes through the PMOS transistor M 2  and reaches the node B so that the output OUT is pulled high to a level equivalent to VP 2 . In the meantime, since the node B is high, the PMOS transistor M 1  fully turns OFF to stabilize node A at the low level of 0V. 
         [0007]      FIG. 2  shows ideal waveforms under an assumption that the PMOS and NMOS transistors in each of the PMOS-NMOS transistor pairs M 1  and M 3 , M 2  and M 4  have about the same driving strength. However, to ensure that the NMOS transistors M 3  and M 4  can over-drive the PMOS transistors M 1  and M 2  during the transition from low level to high level, in particular to cope with the situation where the NMOS transistors are in their worst case and the PMOS transistors are in their best case, the width of the NMOS transistors are typically made longer to increase their driving strength. Hence the driving strength of the PMOS transistor M 1  is weaker than that of the NMOS transistor M 3 , and the driving strength of the PMOS transistor M 2  is weaker than that of the NMOS transistor M 4 , resulting in the waveforms shown in  FIG. 3 , wherein the output signal of the level shift device is far slower in switching from low to high than from high to low, as referring to the time points T 2 , T 3 , T 4  and T 5 . 
         [0008]    Referring to  FIG. 4 , when the switching time from low to high and the time from high to low are not comparable, the positive (high level) and negative duty cycles (low level) are not equal to each other (TL&gt;TH, in other words, the rising and falling time of a signal are different). If such a level shift device is used in a product wherein both the rising and falling edges of a signal are meaningful, such as a DDR DRAM or other similar products, the uneven positive and negative duty cycles will significantly impact the accuracy of the clock, data, data strobe and other signals. To ensure the accuracy of such the signals, the processing time of the signals such as the set-up time and the hold time has to be prolonged, degrading the performance of the product. 
         [0009]    In view of the above, a level shift device providing about the same positive and negative duty cycles is desired. 
       SUMMARY OF THE INVENTION 
       [0010]    A first objective of the present invention is to provide a level shift device capable of providing about the same positive and negative duty cycles. 
         [0011]    A second objective of the present invention is to provide a level shift method. 
         [0012]    To achieve the foregoing objectives, according to an aspect of the present invention, a level shift device comprises: a first level shift circuit for converting an input signal with a first voltage level to a first signal and a second signal with a second voltage level, wherein the first voltage level is different from the second voltage level, and the first signal and the second signal are substantially opposite in phase, and an output stage circuit for generating an output signal according to the relationship between the first signal and the second signal. 
         [0013]    In the above-mentioned level shift device, the output stage circuit for example can be a comparator or a second level shift circuit. 
         [0014]    According to another aspect of the present invention, a level shift method comprises: receiving an input signal with a first voltage level; converting the input signal to a first signal and a second signal with a second voltage level, wherein the first voltage level is different from the second voltage level, and the first signal and the second signal are substantially opposite in phase, and generating an output signal according to the relationship between the first signal and the second signal. 
         [0015]    Preferably, in the above-mentioned circuit and method, the output signal is high when the voltage level of the signal with the second voltage level is higher than the voltage level of the inverted signal of the second operational voltage, and the output signal is low when the voltage level of the inverted signal of the second operational voltage is higher than the voltage level of the signal of the second operational voltage. 
         [0016]    For better understanding the objects, characteristics, and effects of the present invention, the present invention will be described below in detail by illustrative embodiments with reference to the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a circuit diagram schematically showing a conventional level shift circuit. 
           [0018]      FIG. 2  is a time diagram showing the voltage level transition at the critical nodes in the conventional level shift circuit shown in  FIG. 1 . 
           [0019]      FIGS. 3 and 4  explain the drawback in the prior art. 
           [0020]      FIG. 5  is a circuit diagram schematically showing a level shift device according to a first preferred embodiment of the present invention. 
           [0021]      FIG. 6  is a time diagram showing the voltage level transition at the critical nodes in the level shift device shown in  FIG. 5 . 
           [0022]      FIG. 7  is a circuit diagram schematically showing a level shift device according to a second preferred embodiment of the present invention. 
           [0023]      FIG. 8  is a time diagram showing the voltage level transition at the critical nodes in the level shift device shown in  FIG. 7 . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0024]    For purpose of simplicity, in all of the following embodiments, it is assumed that the first operational voltage has a high level of 1.2V and low level of 0V, and the second operational voltage VP 2  has a high level of 3.3V and a low level of 0V. The input and output signals are, e.g., clock signals. However, the present invention should not be limited as such, but may be applied to level shift between any two voltage levels and any other forms of signals. 
         [0025]      FIG. 5  schematically shows a first preferred embodiment according to the present invention. As shown in the figure, the level shift device  100  comprises a pair of PMOS transistors M 1  and M 2 , and a pair of NMOS transistors M 3  and M 4  (the PMOS and NMOS pairs constituting a basic level shift circuit  20 ). In addition to the above, the level shift device  100  according to this embodiment further comprises an output stage circuit which determines the level of the output OUT according to the difference between the voltages at the nodes A and B. The voltage signal at the node B is an inverted signal of that at the node A; there is 180° phase difference between the signals at the nodes A and B. There are various ways to embody the output stage circuit; in this embodiment, the output stage circuit is a comparator  30 . 
         [0026]    Referring to  FIG. 6  in conjunction with  FIG. 5 , when the input IN switches from low (0V) to high (1.2V), the voltage at the node A rapidly drops, and the voltage at the node B slowly increases. However, the output OUT of the overall circuit is not from the node B, but from the output of the comparator  30  which compares the voltages at the node A and node B; thus, the output OUT does not switch to high (3.3V) until the voltage at the node B is higher than that at the node A, as referring to time T 1 . 
         [0027]    Likely, when the input IN switches from high to low, the output OUT does not switch to low until the voltage at the node B is lower than that at the node A, as referring to time T 2 . 
         [0028]    Thus, as seen from  FIG. 6 , the positive and negative duty cycles of the output OUT are the same, i.e., TH=TL, achieving the objectives of the present invention. 
         [0029]    One important feature of the present invention is that the output OUT of the overall circuit is generated according to the relationship between the voltages at the node A and node B. This can be embodied by many other ways than the comparator  30  described above. 
         [0030]      FIG. 7  schematically shows a second preferred embodiment according to the present invention. As shown in the figure, the level shift device  200  further comprises another level shift circuit  40  which includes a pair of PMOS transistors M 5  and M 6 , and a pair of NMOS transistors M 7  and M 8 . In the level shift circuit  40 , the NMOS transistors M 7  and M 8  have the same width as that of the PMOS transistors M 5  and M 6 . The level shift circuit  40  in this embodiment may be deemed as an equal-level shift circuit because its first operational voltage (the gate voltage of the transistors M 7  and M 8 ) is the same as its second operational voltage (its output), which are both 3.3V in this embodiment. 
         [0031]    Referring to  FIG. 8  in conjunction with  FIG. 7 , when the input IN switches from low to high, the voltage at the node A rapidly drops, while the voltage at the node B slowly increases. Correspondingly, the NMOS transistor M 7  rapidly turns OFF but the NMOS transistor M 8  slowly turns ON. Thus, the gate voltage of the PMOS transistor M 5  drops slowly, and the output OUT of the overall circuit does not change state immediately. Only until the voltage at the node B is higher than that at the node A that the output OUT switches state to high, as referring to time T 1 . 
         [0032]    Likely, when the input IN switches from high to low, the output OUT does not switch to low until the voltage at the node B is lower than that at the node A, as referring to time T 2 . 
         [0033]    Thus, as seen from  FIG. 8 , the positive and negative duty cycles of the output OUT are the same, i.e., TH=TL, achieving the objectives of the present invention. 
         [0034]    The features, characteristics and effects of the present invention have been described with reference to its preferred embodiments, for illustrating the spirit of the invention and not for limiting the scope of the invention. Various other substitutions and modifications will occur to those skilled in the art, without departing from the spirit of the present invention. For example, there are various ways to determine the overall output OUT according to the relationship between the voltages at the node A and node B, and these variations should all belong to the scope of the present invention. As another example, in each of the described embodiments, the level shift device is for converting a low voltage level to a high voltage level, but the present invention may be applied to a level shift circuit for high-to-low level shift as well. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.

Technology Classification (CPC): 7