Patent Abstract:
Improved DC cancellation in zero-IF receivers for eliminating the DC offset that otherwise would be caused by the AC voltage on a coupling capacitor at the time of switching from AC coupling to DC coupling. The coupling capacitor normally is connected first as a high pass filter to block any DC component, and then directly coupled as a direct or DC coupler. However any AC component of voltage on the coupling capacitor at the moment of switching normally remains as a DC offset. In accordance with the invention, the component of AC voltage on a coupling capacitor is tracked, and when switched to DC coupling, the component of AC voltage on the capacitor at the time of switching is held and subtracted from the signal path, thereby canceling the DC offset component that otherwise would be caused. Alternate embodiments are disclosed, including embodiments for accelerating capacitance charging for speed-up of the method.

Full Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to the field of wireless communication. 
   2. Prior Art 
   Zero-IF receivers for wireless communication use AC coupling in the I and Q base band signal paths to block the unwanted DC levels due to local oscillator (LO) leakage and circuit implementation. After adjusting the receiver gain, the AC coupling is switched to DC coupling in order to improve the signal to noise ratio (S/N). In doing this, a large DC step may be observed in the I and Q signal paths due to the series capacitor retaining some signal dependent charge existing at the moment of switching. This can result in clipping of the I and Q A/D inputs and also in impairment of the S/N. 
   A prior art circuit for DC cancellation is shown in  FIG. 1   a.  V DC  is the unwanted DC offset that is blocked by C 1  when the switch S 1  is in the AC position. The R 1 C 1  time constant implements a high-pass filter (AC coupling) with a 3 dB corner frequency 
             f   HP     =       1     2   ⁢   π   ⁢           ⁢     R   1     ⁢     C   1         .           
If the wanted signal has a frequency component V AC  at a much lower frequency f 1 &lt;&lt;f HP , then C 1  will charge up close to the instantaneous value of that frequency component in V AC  and the AC voltage across C 1 , i.e., V C     1AC   , will follow that frequency component in V AC . When the switch S 1  is opened (DC position) for implementing DC coupling, the instantaneous voltage across C 1  will be V DC +V C     1AC    (t=0), assuming the switching is done at time t=0. The V DC  component of voltage across the capacitor C 1  is the desired blocking of the unwanted DC offsets. However the output V OUT  will now have a DC kick equal to V C     1AC    (t=0), which in the worst case will be nearly as large as the amplitude of V AC  at f 1 .
 
   The applicable waveforms are shown in  FIGS. 1   b  through  1   f    FIG. 1   b  shows the wanted input signal V AC ,  FIG. 1   c  a representative DC offset level V DC , and  FIG. 1   d,  the input voltage V IN  to the high pass filter (R 1 ,C 1 ), which is the sum of the wanted input signal V AC  and the representative DC offset level V DC . Assuming the wanted signal V IN  is at a frequency of f 1 &lt;&lt;f HP , the voltage V C1ac  across the capacitor C 1  prior to switching switch S 1  ( FIG. 1   a ) to the DC position will substantially follow the wanted signal V IN , as shown in  FIG. 1   e.  At the moment of switching (t=0), that signal may have an amplitude anywhere within its maximum amplitude.  FIG. 1   e  illustrates an arbitrary value at the time of switching that is V step  above the V DC  level. This unwanted DC step of V step =V C     1AC    (t=0) then is coupled to the next functional element in the signal path, as shown in  FIG. 1   f.    

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1   a  illustrates a prior art circuit for DC cancellation in a zero-IF receiver for wireless communication. 
       FIG. 1   b  illustrates a waveform for a wanted signal V AC . 
       FIG. 1   c  illustrates an unwanted DC offset V DC . 
       FIG. 1   d  illustrates the combination of signals of  FIGS. 1   b  and  1   c.    
       FIG. 1   e  illustrates the switching to DC coupling at time T=0 when there is an arbitrary part of the signal voltage V IN  on the coupling capacitor C 1  of  FIG. 1 . 
       FIG. 1   f  illustrates the output voltage having a zero average value before t=0, and an average value of V step  after t=0. 
       FIG. 2  is a diagram illustrating an embodiment of the present invention. 
       FIG. 3  illustrates a fast settling circuit for high pass filters that may be used with the present invention. 
       FIGS. 4   a  through  4   c  illustrate a conventional low pass filter and a fast settling low pass filter circuit for low pass filters that may be used with the present invention. 
       FIG. 5  illustrates in a single Figure, details of a preferred embodiment of the present invention. 
       FIG. 6  is a block diagram of an exemplary wireless transceiver incorporating the present invention. 
       FIG. 7  is an exemplary logic flow diagram for an embodiment of the present invention intended for use in IEEE 802.11a/g WLAN, IEEE802.16, Cellular Phone and Korean WiBro products. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   An embodiment of the present invention DC cancellation circuit shown in  FIG. 2  removes the unwanted DC kick of V step  that was present in the prior art. According to this invention, the voltage across C 1  is measured, and the component of this voltage that corresponds to V step  is subtracted at the output. Initially the switches S 1  and S 2  are in the AC positions, and the Sample/Hold switch is closed. The voltage across the capacitor C 1  is monitored by the summing point A 1 . As before, this voltage may be expressed as V DC +V C     1AC   . However the unwanted V step  is simply the value of V C     1AC    at time t=0. Therefore in order to separate the V step  component from the V DC  component, the voltage across C 1  is low-pas filtered in low pass filter F 1  and then subtracted at summing point A 2  from the instantaneous voltage that is across C 1  to provide the voltage V C     1AC    to the Sample/Hold capacitor C SH  tracking that voltage. The combination of the low pass filter F 1  and the summing point A 2  acts as a high pass filter. 
   At t=0, the coupling changes from AC to DC. Switches S 1  and S 2  change from the AC to the DC positions and the Sample/Hold switch is opened. The Sample/Hold capacitor C SH  now holds the output of summing point A 2  that existed at t=0, which is the voltage V C     1AC    at T=0 or V step . This value is coupled through switch S 2  to summing point A 3 , and finally subtracted at the output Vout by summing point A 3 . Thus the voltage V step  occurring on switching from AC to DC has also been stored and subtracted from the output Vout, thereby substantially eliminating the effect of V step  from the output V vout.    
   In order to speed up the DC settling of the I and Q receiver base band paths after switching to the receive mode or after changing the front-end RF gain (which produces large changes in V DC ), the resistor R 1  of  FIG. 2  may be momentarily made very small as shown in  FIG. 3 , where a shunt resistor R 2  may be momentarily placed in parallel with resistor R 1  through switch S 3 . By doing this, capacitor C 1  charges to V DC  very quickly with a time constant of approximately R 2 C 1 , which is much smaller than the regular time constant R 1 C 1  of the high pass filter. 
   This feature may also be implemented in the low pass filter F 1  of  FIG. 2 . In particular, the low pass filter F 1 , schematically shown in  FIG. 4   a,  may be implemented as the RC filter R 3 C 3  of  FIG. 4   b,  though preferably, with the addition of switch S 4  and resistor R 4  of  FIG. 4   c,  where R 4 &lt;&lt;R 3  of  FIG. 4   b,  switch S 4  may be momentarily closed at time t=0 to implement fast charging in the low pass filter F 1 . 
     FIG. 5  shows the coupling capacitor circuit of  FIG. 2  incorporating the fast charging circuits previously described. 
   An example of a wireless transceiver incorporating an embodiment of the present invention is shown in  FIG. 6 . This Figure illustrates a bridge switch for switching between two antennas, though a single antennae may be used as desired. For the transmitter side, the I(n) and Q(n) signals to be transmitted are converted to analog form in the D/A converters, filtered in the filters AF 1  and AF 2 , mixed in mixers M 3  and M 4  with an RF carrier generated by a voltage controlled oscillator (VCO) controlled through a phase locked loop (PLL), summed, and amplified by variable gain amplifier TXVGA and power amplifier PA, and finally low pass filtered (LPF) for coupling to an antennae. 
   For the receiver side, a received signal from an antennae is coupled to a band pass filter BPF, through a variable gain low noise amplifier LNA and mixed with the local oscillator frequency in mixers M 1  and M 2  to directly convert the received RF signal to I and Q base band channel signals. The base band signals are filtered in channel filters CF 1  and CF 2 , dynamically AC and DC coupled by blocks AC 1  through AC 4 , amplified by variable gain amplifiers VGA 1  and VGA 2  , and then converted to the digital signals I(n) and Q(n) by the A/D converters. The channel filters CF 1  and CF 2  may be fixed filters, or alternatively, may be programmable filters. In this embodiment, the blocks AC 1 , AC 2 , AC 3  and AC 4  implement the DC cancellation of the present invention, and preferably are generally in accordance with  FIG. 5 . 
   Now referring to  FIG. 6 , a flow chart showing an exemplary sequence of operations for the receiver portion of a wireless transceiver such as that shown in  FIG. 5  may be seen. For purpose of specificity, this exemplary sequence of operations is for products conforming to the IEEE 802.11a/g WLAN standards. When the receiver is first turned on, the receiver is set at maximum gain, that is, the gains of the low noise amplifier LNA and of the variable gain amplifiers VGA 1  and VGA 2  are set at a maximum. Typically the DC offset V DC  will equal the wanted signal V AC  plus approximately 40 dB. On receiver power turn on, switches S 1  and S 2  ( FIGS. 2 and 5 ) will be in the AC position and switches S 3  and S 4  ( FIGS. 3 ,  4  and  5 ) will be closed for fast charging of the respective capacitors. The Sample/Hold switch ( FIGS. 2 and 5 ) will be closed, putting the Sample/Hold circuit in the track mode, wherein the voltage on the capacitor C SH  will track the voltage V C     1AC   . 
   The switches are left in the stated positions for 112 nanoseconds to allow the capacitors C 1  ( FIGS. 3 and 5 ) and C 3  ( FIGS. 4 and 5 ) to charge to V DC . This time period is approximately seven times the applicable RC time constants, assuming RC time constant is approximately 16 nanoseconds, or the high pass corner frequency F HP  is 10 megahertz. At the end of the 112 nanosecond delay, switches S 3  and S 4  are opened to put the receiver in the normal AC coupled mode, wherein the receiver is ready for signal acquisition. When the switches S 3  and S 4  are open, the low pass filter corner frequency F LP  equals 112 KHz and the high pass filter corner frequency is 600 KHz. Also by this time, the DC offset output to the A/D converters will be approximately equal to V AC −20 dB. 
   Now the inphase and quadrature channel values are read, typically through the output of the A/D converters, and the gain of the receiver is adjusted. In that regard, such adjustment may be by way of adjusting the gain of the low noise amplifier LNA or the variable gain amplifiers VGA 1  and VGA 2 , or a combination of the two, normally in accordance with a predetermined regimen. If the low noise amplifier LNA gain has changed, the DC offset in the output can change by as much as 30 dB. Consequently, in accordance with the sequence being described, switches S 3  and S 4  ( FIGS. 3 ,  4  and  5 ) are turned on for 350 nanoseconds for fast charging of the respective capacitors, after which switches S 3  and S 4  are turned off and the inphase and quadrature values are again measured and gain adjusted, if required. If the gain of the low noise amplifier LNA is adjusted again, this loop again repeats. If it was not adjusted or changed, but the gain of the variable gain amplifiers VGA 1  and VGA 2  was changed, the inphase and quadrature values are again read and further gain adjustments are made, if necessary. Because the variable gain amplifiers VGA 1  and VGA 2  do not inject significant DC offset in the system, fast DC offset zeroing is not again required after their gain has been changed. 
   In order to adequately read the inphase and quadrature values for gain control purposes, once no further changes in the gain of the low noise amplifier LNA or in the variable gain amplifiers VGA 1  and VGA 2  are made, a delay of approximately 4 microseconds is imposed, which delay represents the remaining time available in the short sequence of the OFDM packet heading of the IEEE 802.11 specification. The 4 microsecond delay is required for the output of F 1  to settle to V DC , so that a more accurate AC component estimate is available at A 2  output at t=0. Thereafter, the sample/hold switch is opened to hold the voltage equal to V step  on the capacitor C SH  and switches S 1  and S 2  are changed to the DC position. With switch S 2  in the DC position, the DC voltage V step  that happened to exist on capacitor C 1  ( FIG. 2 ) is subtracted from the output Vout, completing the gain adjustment and DC cancellation. 
   In the above embodiment, gain adjustments are made based on the I and Q value read at the output of the A/D converters. Alternatively or in addition, an RSSI (received signal strength indicator) circuit may be used. Such circuits normally monitor the analog signal strength prior to the A/D converters and provide an output responsive to the log of the signal level. Such circuits are not as accurate as using the output of the A/D converters, though could be used, or alternatively, could be used for course gain correction, with the output of the A/D converters being used for the final gain corrections. 
   Thus in accordance with the present invention, DC components appearing at the input to a coupling capacitor are blocked as in the prior art. However in addition, the instantaneous AC component that may appear across the coupling capacitor at the time of switching to DC coupling is sensed, held and subtracted from the signal path, eliminating the additional DC offset component that would otherwise be imposed by that AC component. Embodiments of the invention disclosed herein subtract the voltage component from the signal path after the point of sensing the voltage across the coupling capacitor, though this is not a limitation of the invention, as the correction could be made at a point in the signal path prior to the point of sensing the voltage across the coupling capacitor, provide care was taken to not subtract the corrective value prior to decoupling the sample and hold capacitor from the signal path. Also embodiments of the present invention hereinbefore described have been described with respect to the IEEE 802.11a/g WLAN standards. However the invention is applicable to other direct conversion wireless applications also. By way of example, for CDMA cell phones using FDD (frequency division duplexing), the receiver gain is controlled from the base station in a closed loop, with an update rate of less than 1 kHz, i.e. an update interval of less than 1000 μsec. Every time the receiver gain is to be changed, the I and Q receive paths are switched to the AC-coupling mode hereinbefore described just before the actual gain change is done. For WCDMA, the AC coupling can be 100-200 kHz (−3 dB corner) to enable fast settling of gain and DC offsets (that are due to gain changes). About 10-20 μsec after gain is changed, the I and Q paths are switched back to DC coupling. The 10-20 μsec is sufficient to bring the output of F 1  ( FIG. 2 ) to the new input DC condition, in order to produce a more accurate signal estimate at A 2  output for sampling by C SH . Fast charging can also be enabled momentarily in the beginning of the 10-20 μsec interval, for both C 1  and C 3 . The 10-20 μsec AC coupling of 100-200 kHz every 1000 μsec does not significantly hurt the speech quality of WCDMA. By removing the DC step of the prior art, it actually improves the speech quality. Thus while certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Technology Classification (CPC): 7