Patent Abstract:
A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages that can be used to determine the state of the memory cell. By integrating the read current to obtain a measurement voltage, rather than directly comparing the read current to a reference current, the sensing system can use lower supply voltages than conventional sensing systems. In addition, because the measurement voltages are generated by integrating the read current over time, sensing operations are less sensitive to supply voltage fluctuations and the accuracy. Also, for memory cells that exhibit small read currents, the accuracy of sensing operations can be increased by increasing the period of integration.

Full Description:
FIELD OF THE INVENTION 
     This invention relates generally to semiconductor memories, and more particularly to a high-speed sensing system for low voltage memories. 
     BACKGROUND OF THE INVENTION 
     Various types of memory devices, such as random access memory (RAM), read-only memory (ROM) and non-volatile memory (NVM), are known in the art. A memory device includes an array of memory cells and peripheral supporting systems for managing, programming and data retrieval operations. 
     Each of the memory cells in a memory device can be configured to provide an electrical output signal during a read operation. A sense amplifier is coupled to receive the electrical output signal, and in response, provide a data output signal representative of the logic state of the data stored by the memory cell. 
     In general, sense amplifiers determine the logical value stored in a memory cell by comparing the electrical output signal (i.e., voltage or current) provided by the cell with a threshold value (i.e., voltage or current). If the electrical output signal exceeds the threshold value, the sense amplifier provides a data output signal having a first logic value (e.g., logic “1”), thereby indicating that the memory cell is in a first logic state (e.g., an erased state). Conversely, if the electrical output signal is less than the threshold value, the sense amplifier provides a data output signal having a second logic value (e.g., logic “0”), thereby indicating that the memory cell is in a second logic state (e.g., a programmed state). 
     The threshold value is typically set at a level that is between the expected electrical output signal for a programmed state of a memory cell and the expected electrical output signal for an erased state of a memory cell. It is desirable to set the threshold value at a level that is sufficiently far from both expected levels, so that noise on the electrical output signal will not cause false results. 
     FIG. 1 is a block diagram of a conventional memory device  100 , which includes memory array  110 , reference memory array  112 , clamping circuits  120 - 121 , sense amplifier first stages  130 - 131 , and sense amplifier second stage  140 . Memory array  110  and reference memory array  112  each include a plurality of non-volatile memory cells arranged in rows and columns. For example, memory array  100  includes non-volatile memory cell  111 , and reference memory array  112  includes non-volatile memory cell  113 . Clamping circuit  120  includes PMOS transistors P 1 -P 2 , NMOS transistor N 1  and comparator C 1 , which are connected as illustrated. Similarly, clamping circuit  121  includes PMOS transistors P 7 -P 8 , NMOS transistor N 2 , and comparator C 2 , which are connected as illustrated. Clamping circuits  120  and  121  cause the charging operation to be performed in a staged manner to improve the efficiency of the sensing operation. Sense amplifier first stage  130  includes PMOS transistor P 3  and NMOS transistor N 4 . Sense amplifier first stage  131  includes PMOS transistor P 6  and NMOS transistor N 3 . Sense amplifier second stage  140  includes PMOS transistors P 4 -P 5 , and current comparator circuit  141 . 
     To read (or “sense”) the state of a memory cell in memory array  110 , the word line and bit lines associated with the memory cell are selected. For example, to read memory cell  111 , a read voltage is applied to word line W 1  by a row decoder, while bit line B N  is coupled to a system bit line BL by a column decoder, and bit line B N+1  is grounded. A corresponding reference memory cell  113  in reference array  112  is configured in a similar manner. Thus, a read voltage is applied to word line W 1  by a row decoder, while bit line B M  is coupled to a reference bit line BL_REF by a column decoder, and bit line B M+1  is grounded. System bit line BL and reference bit line BL_REF exhibit capacitances C BL  and C REF     —     BL , respectively. 
     Sense amplifier first stage  130  and clamping circuit  120  apply a sense voltage on system bit line BL, thereby causing a read current I BL  to flow through memory cell  111 . The magnitude of the read current I BL  is determined by the logic state of memory cell  111  (i.e., programmed or erased). This read current I BL  is mirrored to PMOS transistor P 4  of sense amplifier second stage  140 . 
     Similarly, sense amplifier first stage  131  and clamping circuit  121  apply the sense voltage on reference bit line BL_REF, thereby causing a read current I BL     —     REF  to flow through reference memory cell  113 . The magnitude of the read current I BL     —     REF  is determined by the logic state of reference memory cell  113 . Reference memory cell  113  is programmed such that the magnitude of the read current I BL     —     REF  is less than the magnitude of the read current I BL  when memory cell  111  is programmed, and greater than the magnitude of the read current I BL  when memory cell  111  is erased. The read current I BL     —     REF  is mirrored to PMOS transistor P 5  of sense amplifier second stage  140 . 
     After the read currents I BL  and I BL     —     REF  have had time to develop, the enable signal EN is activated, thereby causing comparator circuit  141  to detect the difference between these read currents. In response, comparator circuit  141  provides an output data signal D OUT , representative of the data stored in memory cell  111 . 
     Memory device  100  is described in more detail in commonly owned, co-pending U.S. patent application Ser. No. 09/935,013, “Structure and Method for High Speed Sensing of Memory Arrays”, by Alexander Kushnarenko and Oleg Dadashev [TSL-103]. 
     Memory device  100  will not operate properly unless the V DD  supply voltage is greater than a minimum voltage V DD     —     MIN , which is defined as follows. 
     
       
           V   DD     —     MIN   =V   DIODE     —     MAX   +V   BL     —     MIN   +V   P1/P8   +V   P2/P7   (1) 
       
     
     In Equation (1), V DIODE     —     MAX  is the maximum voltage drop across PMOS transistor P 3  or PMOS transistor P 6 , V BL     —     MIN  is the minimum acceptable bit line voltage for the non-volatile memory technology, V P1/P8  is the drain-to-source voltage drop of PMOS transistor P 1  (or PMOS transistor P 8 ), and V P2/P7  is equal to the drain-to-source voltage drop on PMOS transistor P 2  (or PMOS transistor P 7 ). 
     For example, if V DIODE     —     MAX  is equal to 1.0 Volt, V BL     —     MIN  is equal to 1.8 Volts, and V P1/P8  and V P2/P7  are equal to 0.05 Volts, then the minimum supply voltage V DD     —     MIN  is equal to 2.9 Volts (1.8V+1V+0.05V+0.05V). In such a case, memory device  100  would not be usable in applications that use a V DD  supply voltage lower than 2.9 Volts. 
     In addition, sense amplifier first stages  130  and  131  are sensitive to noise in the V DD  supply voltage. If, during a read operation, the V DD  supply voltage rises to an increased voltage of V DD     —     OVERSHOOT , then the voltages V SA1  and V SA2  on the drains of PMOS transistors P 3  and P 6  rise to a level approximately equal to V DD     —     OVERSHOOT  minus a diode voltage drop. If the V DD  supply voltage then falls to a reduced voltage of V DD     —     UNDERSHOOT , then transistors P 3  and P 6  may be turned off. At this time, sense amplifier first stages  130  and  131  cannot operate until the voltages V SA1  and V SA2  are discharged by the cell currents I BL  and I BL     —     REF . If the cell current I BL  is low, then sense amplifier first stage  130  will remain turned off until the end of the read operation, thereby causing the read operation to fail. 
     Accordingly, it is desirable to provide a sensing system that can accommodate low supply voltages and tolerate supply voltage fluctuations. 
     SUMMARY OF THE INVENTION 
     The present invention provides a system and method for sensing the state of a memory cell by integrating current differences between a read current produced by the memory cell and a reference current produced by a reference memory cell. The integration process generates differential measurement voltages that can be compared to determine the state of the memory cell relative to the state of the reference memory cell. By performing a sensing operation in this manner, low supply voltages can be accommodated and sensitivity to supply voltage noise can be minimized. 
     According to an embodiment of the invention, a sensing system for sensing the state of a memory cell includes a sense amplifier first stage for detecting the read current of the memory cell and the reference current of the reference memory cell. The sense amplifier first stage generates differential voltages by integrating over time two measurement currents—the first measurement current being a function of the reference current minus the read current, and the second measurement current being a function of the read current minus the reference current. The resulting differential voltages can then be compared to determine the state of the memory cell relative to the reference memory cell. Because the differential voltages are the result of cumulative current measurements over time, rather than a read current or voltage value at a particular moment in time, sensing operations performed using the sense amplifier first stage can be much less sensitive to supply voltage levels and/or fluctuations than sensing operations using conventional sensing systems. 
     According to an embodiment of the invention, the sense amplifier first stage includes a first current source and a second current source producing equal constant currents. A portion of the constant current from the first current source provides the read current for the memory cell, while a portion of the constant current from the second current source provides the reference current for the reference memory cell. Half of the remainder of the constant current from the first current source is subtracted from half of the remainder of the constant current from the second current source to define a first measurement current. Since the constant currents from the first and second current sources are equal, this first measurement current is half of the difference between the reference current and the read current (i.e., the reference current minus the read current). Concurrently, half of the remainder of the constant current from the first current source is subtracted from half of the remainder of the constant current from the second current source to define a second measurement current. Once again, since the constant currents from the first and second current sources are equal, the second measurement current is half of the difference between the read current and the reference current (i.e., the read current minus the reference current). 
     The first measurement current can then be integrated to produce a first measurement voltage, and the second measurement current can be integrated to produce a second measurement voltage. Because the first and second measurement voltages are based upon the positive and negative differences between the read current and the reference current, the two measurement voltages will be substantially similar if the states of the memory cell and the reference memory cell (as indicated by the read current and the reference current) are the same, while the measurement voltages will diverge if the two states are different. Note that this divergence will increase as the period of integration for the measurement voltages increases. Once the measurement voltages have been generated, a comparator can be used to compare the two and determine the state of the memory cell relative to the reference memory cell. According to an embodiment of the invention, a fast comparator can be used to improve the speed of the sensing operation. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional memory device. 
     FIG. 2 is a circuit diagram of a memory system in accordance with one embodiment of the present invention. 
     FIG. 3 is a block diagram of a sense amplifier first stage, in accordance with one embodiment of the present invention. 
     FIG. 4 is a circuit diagram of the sense amplifier first stage of FIG. 3 in accordance with one embodiment of the present invention. 
     FIG. 5A is a circuit diagram of the sense amplifier first stage of FIG. 3 in accordance with another embodiment of the present invention. 
     FIG. 5B is a circuit diagram of the sense amplifier first stage of FIG. 3 in accordance with yet another embodiment of the present invention. 
     FIG. 6 is a circuit diagram of a sense amplifier second stage in accordance with one embodiment of the present invention. 
     FIG. 7 is a waveform diagram illustrating various signals associated with the operation of the sense amplifier first and second stages during a read operation. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 is a circuit diagram of a memory system  200  in accordance with one embodiment of the present invention. Because certain elements of memory system  200  are similar to certain elements of memory system  100  (FIG.  1 ), similar elements in FIGS. 1 and 2 are labeled with similar reference numbers. Thus, memory system  200  includes, memory array  110 , non-volatile memory cell  111 , reference memory array  112 , reference memory cell  113 , clamping circuits  120 - 121 , and bit lines BL and BL_REF (which exhibit bit line capacitances C BL  and C BL     —     REF ). 
     Although memory array  110  and reference memory array  112  are illustrated as arrays having two rows and six columns, it is understood that memory array  110  and reference memory array  112  can have other dimensions in other embodiments. It is also understood that row and column decoding circuitry is not illustrated in memory array  110  or reference memory array  112  for purposes of clarity. According to another embodiment of the invention, the reference memory array  112  can be replaced with a single non-volatile memory cell, (e.g., non-volatile memory cell  113 ), which provides a known reference logic state for use in sensing operations for all the memory cells in memory array  110 . In this embodiment, the silicon area required for memory system  200  can be significantly reduced. 
     Memory system  200  additionally includes sense amplifier first stage  201  and sense amplifier second stage  202 . Sense amplifier first stage  201  is coupled to bit lines BL and BL_REF. As described in more detail below, sense amplifier first stage  201  provides the read current I CELL  and the reference read current I REF     —     CELL  to bit lines BL and BL_REF, respectively. Sense amplifier first stage  201  is also coupled to receive an active-low sense initialization signal SEN#. 
     Sense amplifier first stage  201  provides differential output voltages V OUT1  and V OUT2  to sense amplifier second stage  202 . Second amplifier stage  202  is also coupled to receive an active-high enable signal, LAT. As described in more detail below, sense amplifier second stage  202  provides an output data value SA OUT  in response to the output voltages V OUT1  and V OUT2  when the enable signal LAT is activated high. 
     Returning to FIG. 2, memory cell  111  is selected for a read operation by applying a word line read voltage (e.g., 3-5 Volts) to word line W 1  of array  110 , coupling bit line B N  to system bit line BL through a column decoder (not shown), and coupling bit line B N+1  to a ground supply voltage. At the same time, reference memory cell  113  is also selected by applying the word line read voltage to word line W 1  of array  112 , coupling bit line B M  to reference bit line BL_REF through a column decoder (not shown), and coupling bit line B M+1  to a ground supply voltage. 
     Unlike conventional sense amplifiers, sense amplifier first stage  201  does not compare a read voltage or read current (i.e., I CELL ) introduced by the selected memory cell  111  directly against a reference voltage or current. Instead, sense amplifier first stage  201  performs a current integration operation based on positive and negative differentials between the read current I CELL  and the reference current I REF . This integration operation (described in more detail below) results in the generation of differential output voltages V OUT1  and V OUT2 . The longer the integration period, the larger the difference between differential output voltages V OUT1  and V OUT2 . After a desired integration period, the enable signal LAT is activated, thereby instructing sense amplifier second stage  202  to sample the differential output voltages V OUT1  and V OUT2 , and in response, generate a sense amplifier output SA OUT  (which indicates the state of the memory cell being sensed). 
     FIG. 3 is a block diagram of sense amplifier first stage  201 , in accordance with one embodiment of the present invention. Sense amplifier first stage  201  includes constant current sources  301 - 302 , current divider circuits  303 - 304 , current subtraction circuits  305 - 306 , output nodes  307 - 308  and initialization circuit  310 . Initialization circuit  310  is configured to receive the SEN# signal. At the beginning of a sensing operation, the SEN# signal is activated low, thereby causing initialization circuit to equalize (reset) the charge on current subtraction circuits  305 - 306  and output nodes  307 - 308 . 
     During a sensing operation, constant current sources  301  and  302  each provide a constant current I 0 . This constant current I 0  is greater than the expected read current I CELL  (and the reference read current I REF ). A portion of the constant current I 0  provided by current source  301  flows to the memory cell being sensed (e.g., memory cell  111 ) as the read current I CELL . The remaining portion of constant current I 0  provided by current source  301  (i.e., I 0 −I CELL ) flows to current divider circuit  303 . 
     Similarly, a portion of the constant current I 0  provided by current source  302  flows to the reference memory cell (e.g., reference memory cell  113 ) as the reference read current I REF . The remaining portion of constant current I 0  provided by current source  301  (i.e., I 0 −I REF ) flows to current divider circuit  303 . 
     Current dividers  303  and  304  each divide the received currents in half. Thus, current divider  303  divides the received current of I 0 −I CELL  into two equal currents of (I 0 −I CELL )/2. Similarly, current divider  304  divides the received current of I 0 −I REF  into two equal currents of (I 0 −I REF )/2. 
     Current subtraction circuit  305  is configured to subtract the current (I 0 −I REF )/2 provided by current divider  304  from the current (I 0 −I CELL )/2 provided by current divider  303 , thereby providing an output current equal to (I REF −I CELL )/2. Similarly, current subtraction circuit  306  is configured to subtract the current (I 0 −I CELL )/2 provided by current divider  303  from the current (I 0 −I REF )/2 provided by current divider  304 , thereby providing an output current equal to (I CELL −I REF )/2. 
     Output node  307  is configured to receive the output current (I REF −I CELL )/2 provided by current subtraction circuit  305 . Output node  307 , which is coupled to the gate of a transistor in sense amplifier second stage  202 , exhibits a capacitance C OUT1 . As a result, the output voltage V OUT1  is developed on output node  307 . This output voltage V OUT1  can be defined as follows, where V 0  is equal to the initial voltage on output node  307  before the sensing operation is started. 
     
       
           V   OUT1 ( t )=(∫ I   OUT1 ( t ) dt )/ C   OUT1   =V   0   +I   OUT1   *t/C   OUT1   (2) 
       
     
     Similarly, output node  308  is configured to receive the output current (I CELL −I REF )/2 provided by current subtraction circuit  306 . Output node  308 , which is coupled to the gate of a transistor in sense amplifier second stage  202 , exhibits a capacitance C OUT2 . As a result, the output voltage V OUT2  is developed on output node  308 . This output voltage V OUT2  can be defined as follows, where V 0  is equal to the initial voltage on output node  308  before the sensing operation is started. 
       V   OUT2 ( t )=(∫ I   OUT2 ( t ) dt )/ C   OUT2   =V   0   +I   OUT2   *t/C   OUT2   (3) 
     The difference between the output voltages V OUT1  and V OUT2  can be defined as follows. 
     
       
           V   OUT1 ( t )− V   OUT2 ( t )=( V   0   +I   OUT1   *t/C   OUT1 )−( V   0   +I   OUT2   *t/C   OUT2 )  (4) 
       
     
     In the described embodiment, sense amplifier first stage  201  and sense amplifier second stage  202  are designed such that C OUT2  is equal to C OUT1 . Capacitances C OUT1  and C OUT2  can therefore be represented by the equivalent capacitance value C OUT . As a result, equation (4) can be simplified as follows. 
     
       
           V   OUT1 ( t )− V   OUT2 ( t )=( I   REF   −I   CELL )* t /2 C   OUT −( I   CELL   −I   REF )* t /2 C   OUT   (5) 
       
     
     
       
           V   OUT1 ( t )− V   OUT2 ( t )=(( I   REF   −I   CELL )* t −( I   CELL   −I   REF )* t )/2 C   OUT   (6) 
       
     
     
       
           V   OUT1 ( t )− V   OUT   2 ( t )=(2 I   REF   *t −2 I   CELL   *t )/2 C   OUT   (7) 
       
     
     
       
           V   OUT1 ( t )− V   OUT2 ( t )=( I   REF   −I   CELL )* t/C   OUT   (8) 
       
     
     The differential output signal represented by output voltages V OUT1 (t) and V OUT2 (t) is therefore a function of the differential input signal to sense amplifier first stage  201 , I REF −I CELL . The differential output signal represented by output voltages V OUT1 (t) and V OUT2 (t) therefore includes required information about the compared input signals. Sense amplifier first stage  201  integrates the differential input current (I REF −I CELL ), such that the differential output signal represented by output voltages V OUT1 (t) and V OUT2 (t) increases linearly with time. As a result, sense amplifier first stage  201  exhibits a relatively high sensitivity to differences between the input currents (I REF  and I CELL ), while exhibiting a relatively low sensitivity to noise in the V DD  supply voltage. 
     As described in more detail below, sense amplifier second stage  202  compares the differential output voltages V OUT1  and V OUT2 , and provides a data output signal SA OUT  which has a first state if V OUT1  is greater than V OUT2 , and a second logic state if V OUT1  is less than V OUT2 . 
     FIG. 4 is a circuit diagram of sense amplifier first stage  201  in accordance with one embodiment of the present invention. Sense amplifier first stage  201  includes PMOS transistors  401 - 406  and NMOS transistors  411 - 417 . PMOS transistors  401  and  402  form constant current sources  301  and  302 , respectively. The source and bulk regions of PMOS transistors  401  and  402  are coupled to the V DD  voltage supply terminal. The gates of PMOS transistors  401  and  402  are coupled to receive a first bias voltage V BIAS1 . The first bias voltage V BIAS1  is selected such that the constant current I 0  flows through each of PMOS transistors  401  and  402 . The drain of PMOS transistor  401  is coupled to the memory cell being read and current divider circuit  303 . As described above, current divider circuit  303  receives a current equal to (I 0 −I CELL ). The drain of PMOS transistor  402  is coupled to the reference memory cell and current divider circuit  304 . As described above, current divider circuit  304  receives a current equal to (I 0 −I REF ). 
     PMOS transistors  403 - 404  are identical transistors configured to form current divider circuit  303 . The source and bulk regions of PMOS transistors  403  and  404  are coupled to receive the current, (I 0 −I CELL ). The gates of PMOS transistors  403  and  404  are coupled to receive a second bias voltage V BIAS2 . As a result, half of the current (I 0 −I CELL ) flows through each of PMOS transistors  403  and  404  (i.e., (I 0 −I CELL )/2 flows through each of PMOS transistors  403  and  404 ). The drains of PMOS transistors  403  and  404  are coupled to the drains of NMOS transistors  411  and  412 , respectively. 
     Similarly, PMOS transistors  405 - 406  are identical transistors configured to form current divider circuit  304 . The source and bulk regions of PMOS transistors  405  and  406  are coupled to receive the current, (I 0 −I REF ). The gates of PMOS transistors  405  and  406  are coupled to receive a third bias voltage V BIAS3 . As a result, half of the current (I 0 −I REF ) flows through each of PMOS transistors  405  and  406  (i.e., (I 0 −I REF )/2 flows through each of PMOS transistors  405  and  406 ). The drains of PMOS transistors  405  and  406  are coupled to the drains of NMOS transistors  413  and  414 , respectively. 
     NMOS transistors  411  and  413  are configured to form current subtraction circuit  305 . The sources of NMOS transistors  411  and  413  are coupled to the ground supply terminal. The gates of NMOS transistors  411  and  413  are commonly connected to the drain of NMOS transistor  413 , thereby forming a current mirror circuit, whereby the current through NMOS transistor  413  is mirrored to NMOS transistor  411 . Thus, the current of (I 0 −I REF )/2 flowing through NMOS transistor  413  is mirrored to NMOS transistor  411 . As a result, the current flowing to output terminal  307  is necessarily equal to ((I 0 −I CELL )/2−(I 0 −I REF )/2), or (I CELL −I REF )/2. This current charges output terminal  307  to the output voltage V OUT1  as described above. 
     Similarly, NMOS transistors  412  and  414  are configured to form current subtraction circuit  306 . The sources of NMOS transistors  412  and  414  are coupled to the ground supply terminal. The gates of NMOS transistors  412  and  414  are commonly connected to the drain of NMOS transistor  412 , thereby forming a current mirror circuit, whereby the current through NMOS transistor  412  is mirrored to NMOS transistor  414 . Thus, the current of (I 0 −I CELL )/2 flowing through NMOS transistor  412  is mirrored to NMOS transistor  414 . As a result, the current flowing to output terminal  308  is necessarily equal to ((I 0 −I REF )/2−(I 0 −I CELL )/2), or (I REF −I CELL )/2. This current charges output terminal  308  to the output voltage V OUT2  as described above. 
     NMOS transistors  415 - 417  are configured to form initialization circuit  310 . NMOS transistors  415 - 417  are connected in series between output terminals  307  and  308 . The source of transistor  416  is coupled to the gates of NMOS transistors  412  and  414 . The drain of NMOS transistor  416  is coupled to the gates of NMOS transistors  411  and  413 . The gates of NMOS transistors  412  are coupled to receive the SEN# signal. When the SEN# signal is de-activated high (V DD ), NMOS transistors  415 - 417  are turned on, thereby equalizing the voltages on output terminals  307 - 308 , the gates of transistors  411 - 414  and the drains of transistors  412 - 413 . When sensing begins, the SEN# signal is activated low (0 Volts), such that NMOS transistors  415 - 417  are turned off, and the differential output voltages V OUT1  and V OUT2  develop on output terminals  307  and  308  in the manner described above. 
     In accordance with one embodiment of the present invention, the second and third bias voltages V BIAS2  and V BIAS3  are the same voltage, which is provided by an external bias voltage supply. 
     In accordance with another embodiment of the present invention, the second bias voltage V BIAS2  is provided by the drain of PMOS transistor  405 , and the third bias voltage V BIAS3  is provided by the drain of PMOS transistor  404 . FIG. 5A is a circuit diagram illustrating this embodiment of the present invention. 
     In accordance with another embodiment of the present invention, the second bias voltage V BIAS2  is provided by the drain of PMOS transistor  404 , and the third bias voltage V BIAS3  is provided by the drain of PMOS transistor  405 . FIG. 5B is a circuit diagram illustrating this embodiment of the present invention. Advantageously, the embodiments illustrated by FIGS. 5A and 5B do not require an additional voltage supply. 
     FIG. 6 is a circuit diagram of sense amplifier second stage  202  in accordance with one embodiment of the present invention. Sense amplifier second stage  202  includes NMOS transistors  601 - 607 , PMOS transistors  611 - 615 , inverter  619  and NOR gates  621 - 622 . 
     NMOS transistors  601  and  602  form a differential input pair, with the gate of NMOS transistor  601  coupled to receive the output voltage V OUT1  from output terminal  307  of sense amplifier first stage  201 , and the gate of NMOS transistor  602  coupled to receive the output voltage V OUT2  from the output terminal  308  of sense amplifier first stage  201 . The gate terminals of NMOS transistors  601  and  602  contribute to the capacitances C OUT1  and C OUT2  of output terminals  307  and  308 , respectively. NMOS transistor  603  is coupled between the sources of NMOS transistors  601 - 602  and the ground supply terminal. A fourth bias voltage V BIAS4  is applied to the gate of NMOS transistor  603 , thereby providing a current source to the differential pair formed by NMOS transistors  601 - 602 . The voltages on the drains of NMOS transistors  601  and  602  are labeled as voltages V A  and V B , respectively. 
     PMOS transistors  611 - 615 , NMOS transistors  604 - 607  and inverter  619  are configured to form a CMOS latch circuit  610 . More specifically, the drains of transistors  601  and  602  are connected to the drains of p-type transistors  612  and  611 , respectively. PMOS transistor  611 , PMOS transistor  614  and NMOS transistor  605  are connected in series between the VDD voltage supply terminal and the ground supply terminal. PMOS transistor  612 , PMOS transistor  615  and NMOS transistor  606  are also connected in series between the VDD voltage supply terminal and the ground supply terminal. PMOS transistors  611  and  612  are cross-coupled, such that the gate of transistor  611  is coupled to the drain of transistor  611 , and the gate of transistor  612  is coupled to the drain of transistor  611 . NMOS transistors  605  and  606  are also cross-coupled, such that the gate of transistor  605  is coupled to the drain of transistor  606 , and the gate of transistor  606  is coupled to the drain of transistor  605 . 
     PMOS transistor  613  is connected across the drains of PMOS transistors  611  and  612 , with the gate of PMOS transistor  613  being coupled to receive the enable signal LAT. The enable signal LAT is inverted by inverter  619  and then applied to the gates of PMOS transistors  614 - 615  and NMOS transistors  604  and  607 . NMOS transistor  604  is connected between the drain of NMOS transistor  605  and the ground supply terminal. Similarly, NMOS transistor  607  is coupled between the drain of NMOS transistor  606  and the ground supply terminal. 
     NOR gates  621  and  622  are configured to form a data latch  620 . More specifically, one input terminal of NOR gate  621  is coupled to the drain of NMOS transistor  605 , and the other input terminal of NOR gate  621  is coupled to the output terminal of NOR gate  622 . Similarly, one input terminal of NOR gate  622  is coupled to the drain of NMOS transistor  606 , and the other input terminal of NOR gate  622  is coupled to the output terminal of NOR gate  621 . The output terminal of NOR gate  621  provides the output signal SA OUT . 
     The CMOS latch circuit  610  is turned off (i.e., the LAT signal is de-activated low) when there is no sensing operation being performed. At this time, transistors  604 ,  607  and  613  are turned on, and transistors  614 - 615  are turned off. Under these conditions, turned-on transistor  613  equalizes the voltages V A  and V B  on the drains of differential pair transistors  601  and  602 . In addition, turned-on transistors provide logic low voltages to the input terminals of NOR gates  621 - 622 . As a result, data latch  620  continues to provide the previously stored output value SA OUT . The voltages provided to the input terminals of NOR gates  621  and  622  are labeled as voltages V C  and V D , respectively. 
     During a sensing operation, the LAT signal is activated high, thereby turning off transistors  604 ,  607  and  613 , and turning on transistors  614 - 615 . Under these conditions, CMOS latch circuit  610  is enabled, and operates as follows. As described above, one of the output voltages V OUT1 , V OUT2  will be higher than the other. For example, the output voltage V OUT2  may be higher than the output voltage V OUT1 . In this case, transistor  602  will have a higher conductance than transistor  601 , such that voltage V B  is less than voltage V A . In response, transistors  612  and  605  will turn on, and transistors  611  and  606  will turn off, thereby pulling down the voltage V C  to a logic low value, and pulling up the voltage V D  to a logic high value. As a result, NOR gate  622  provides a logic low value to NOR gate  621 , and NOR gate  621  provides a logic high output value SA OUT . 
     Conversely, if the output voltage V OUT1  is higher than the output voltage V OUT2 , transistor  601  will have a higher conductance than transistor  602 , such that voltage V A  is less than voltage V B . In response, transistors  611  and  606  will turn on, and transistors  612  and  605  will turn off, thereby pulling down the voltage V D  to a logic low value, and pulling up the voltage V C  to a logic high value. As a result, NOR gate  621  provides a logic high output value SA OUT , and NOR gate  622  provides a logic low output value. 
     FIG. 7 is a waveform diagram illustrating the SEN#, LAT, V OUT1 /V OUT   2  and SA OUT  signals during a sensing operation. Prior to time T 1 , the SEN# signal is de-activated high, such that equalization circuit  310  is enabled. Under these conditions, the differential output voltage signals V OUT1  and V OUT2  have the same voltage. Data output latch  620  stores the previously read data value SA OUT , which happens to be a logic “1” value in the present example. 
     At time T 1 , the SEN# signal is activated low, thereby disabling equalization circuit  310  in sense amplifier first stage  201 . At this time, the output currents (I CELL −I REF )/2 and (I REF −I CELL )/2 begin to charge output terminals  307  and  308  to output voltages V OUT1  and V OUT2 , respectively. These output terminals  307  and  308  charge linearly with respect to time. 
     At time T 2 , the enable signal LAT is activated high, thereby enabling sense amplifier second stage  202 . In the described example, the output voltage V OUT1  is greater than the output voltage V OUT2 . As a result, the output signal SA OUT  transitions from a logic “1” value to a logic “0” value between time T 2  and time T 3 . 
     At time T 3 , the enable signal LAT is de-activated low, thereby disabling sense amplifier second stage  202 . At this time, the logic “0” output signal SAOUT is stored in data latch  620 . 
     At time T 4 , the SEN# signal is de-activated high, thereby enabling equalization circuit  310 , and causing the output voltage V OUT1  and V OUT2  on output terminals  307  and  308  to be equalized. At this time sense amplifier stages  201 - 202  are ready to begin the next sensing operation. 
     The various embodiments of the structures and methods of this invention that are described above are illustrative only of the principles of this invention and are not intended to limit the scope of the invention to the particular embodiments described. For example, although the present invention has been described with reference to a memory array including NVM cells, the present invention is equally applicable to other types of memory cell arrays. Also, while various specific implementations of the invention have been illustrated using p-type or n-type devices, implementations using alternative device types will be readily apparent. Thus, the invention is limited only by the following claims and their equivalents.

Technology Classification (CPC): 6