Patent Abstract:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Full Description:
This application is a divisional of U.S. patent application Ser. No. 10/932,296 filed Sep. 2, 2004, now U.S. Pat. No. 7,300,857 issued Nov. 27, 2007, which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to imager and memory wafers, and more particularly to through-wafer interconnects and blind vias for imager and memory devices. 
     BACKGROUND OF THE INVENTION 
     As depicted in  FIG. 1 , a conventional bond pad structure  100  is built on a silicon substrate  110  covered by an oxide layer  120 . The bond pad  130  is embedded within a passivation layer  140 . A conductive gold wire ( 160 ) ball ( 150 ) bond is formed and attached on a central upper surface of the bond pad  130 . 
     A disadvantage of direct bond pad connection on the top side of the die, as depicted in  FIG. 1 , includes the fact that they sometimes require a wire bond  160  to be electrically connected to a lead frame or other structure for final die packaging. Another method that involves flip chip packaging at the wafer level involves a re-distribution layer (RDL) that allows the bond pad pitch to be routed to a more useable pitch in order to attach a solder ball directly on the top side of the die. Both of these packaging approaches involve contacting the bond pads on the top side of the die. As a result, this limits the ability to stack memory and imager devices. Furthermore, the ability to attach the cover glass on imager wafers at the wafer level is limited due to the requirement to make contact to the bond pad on the top side of the wafer. Accordingly, it is desirable to develop a through-wafer interconnect to eliminate the need for wire bonding, to increase the volumetric circuit device density, to minimize the size of the die&#39;s packaging, to make memory devices stackable and to enable wafer level packaging (WLP) methods for imager wafers. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention addresses the shortcomings described above and provides in disclosed exemplary embodiments a through-wafer interconnect for imager, memory and other integrated circuit applications, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable to allow increased volumetric density and device functionality and enabling WLP for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which: 
         FIG. 1  depicts a conventional bond pad structure; 
         FIG. 2  depicts an initial portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 3  depicts a further portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 4  depicts a further portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 5  depicts a further portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 6  depicts a further portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 7  depicts a further portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 8  depicts a further portion of a process for manufacturing a through-wafer interconnect, in accordance with an exemplary embodiment of the invention; 
         FIG. 9  depicts an initial portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 10  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 11  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 12  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 13  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 14  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 15  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 16  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 17  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 18  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 19  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 20  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 21  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 22  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 23  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 24  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 25  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 26  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 27  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 28  depicts a further portion of a process for manufacturing a blind via, in accordance with an exemplary embodiment of the invention; 
         FIG. 29  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention; 
         FIG. 30  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention; 
         FIG. 31  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention; 
         FIG. 32  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention; 
         FIG. 33  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention; 
         FIG. 34  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention; and 
         FIG. 35  depicts a further portion of a process for manufacturing a blind via, in accordance with another exemplary embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or procedural changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention. 
       FIG. 2  depicts a portion of a semiconductor wafer  200  at a stage of a process for manufacturing a through-wafer interconnect for an integrated circuit device. A bond pad  240  is depicted as being formed over a silicon (Si) substrate  230  and within a passivation layer  220  or layers. Beneath the passivation layer  220  is a borophosphosilicate glass (BPSG) layer  225 . The bond pad  240  is depicted as being a monolithic structure, however, the bond pad  240  may take other forms including a multiple tiered structure. When the wafer  200  is an imager wafer, this portion of the process may be performed either prior to or after a color filter array (CFA)  720  and microlenses  710  (depicted in dotted lines) have been formed on the top surface of the wafer  200 . One advantage to forming the interconnect prior to forming the CFA  720  and lenses  710  is that the CFA and lenses may be somewhat delicate and sensitive to heat; thus, forming the interconnect prior to their formation may result in less risk to damaging the array. 
       FIG. 3  depicts a hole, or via,  300  formed in a center of the bond pad  240  from the passivation layer  220  down through the substrate  230 . The initial opening to create the hole  300  is formed by sequences of patterning and etching (either wet or dry) through the dielectric and metal layers. For instance, a dry etch may be performed to remove the top portion of passivation layer  220 . A dry etch may be performed through the metal  240 . A dry etch may be performed through the BPSG layer  225 . A wet etch may be performed to form the initial hole  300  in the bulk silicon and to form an initial dimple in the Si  230 . A laser drill process or deep silicon, dry etch process may then be conducted on the Si substrate  230 , followed by a wet clean process. Also depicted is the application of a dielectric  310  to line the walls of the hole  300  and to electrically insulate the subsequent conductive materials in the via from shorting to the bulk silicon substrate. The dielectric also covers the top of the bond pad  240  and the upper passivation layer  220 . The dielectric  310  may be low silane oxide (LSO) or any known method to deposit dielectric films using ALD, CVD, PECVD or other means commonly used in the art. 
       FIG. 4  depicts the interconnect structure with the dielectric  310  removed from the passivation layer  220  and the bond pad  240  by a spacer etch process (e.g., chemical mechanical polishing (CMP) or a dry vertical oxide etch). The dielectric  310  remains as a liner of the walls of the hole  300 . 
       FIG. 5  depicts a plating layer  410  of nickel on a seed material such as titanium nitride (TiN) or tungsten (W), or copper (Cu) on tantalum (Ta), or copper (Cu) on tungsten (W), or other conductive materials and other combinations of these materials, deposited on top of the dielectric  310  on the sidewalls of the via  300  and on top of a portion of the bond pad  240 . The seed material or materials are removed from the top passivation surface by CMP or photo/etch processing. This removal process does not remove the material in the via or on the bond pad. 
       FIG. 6  depicts the hole  300  as being filled with solder  510  utilizing plating or molten solder. It should be noted that other conductive materials (e.g., copper, nickel, conductive polymers, etc.) may be used to fill the hole  300  and/or conductive materials may also be plated to fill the hole. (e.g., nickel, copper, etc.). A dielectric layer  610  is then applied to the lower surface of the wafer  200 . 
     As depicted in  FIG. 7 , a CMP process may then be performed on the top surface  740  and the bottom surface  750 . Another variation of the process is to use a wet etch rather then CMP to etch away the protruding solder  510  or nickel plating  800  ( FIG. 8 ). It should be noted that the CMP process may not be necessary for memory device applications as the final surface topography may not be critical. For an imager wafer, the CFA  720  and lenses  710  are then formed on top of the upper flat surface  740 . Performing a planarization process after the solder  510  fill operation helps to provide a smooth surface in which to apply the CFA and microlens material. The smooth wafer surface prevents streaking and other imperfections which can affect the optical performance of the CFA and microlens structures. 
     In accordance with an exemplary embodiment of the invention, the via  510  electrically connects bond pad  240  with the top surface  740  of the wafer and the bottom surface  750  of the wafer resulting in a much more efficient package that is stackable for memory devices and that lends itself to wafer level packaging for imager devices. 
       FIG. 8  depicts another exemplary embodiment in which the nickel plating  800  is flush with the passivation layer  220 . In this embodiment, the top metal layer of the bond pad  240  is plated with nickel. In this manner, when the solder  510  filling the hole  300  is planarized by CMP, the nickel remains at the top-most portion of the through-wafer interconnect. 
     Turning to  FIG. 9 , an initial step in another exemplary process for forming a through-wafer interconnect with a blind via is depicted. An initial step in this exemplary process is to form a blind via that recesses only partially through a semiconductor substrate. A simplified illustration of a completed wafer is depicted as containing a silicon substrate  900  and a bond pad  920  provided near an upper surface which is surrounded by a passivation layer  910 . The passivation layer  910  is located above an insulation layer, such as BPSG layer  930 . As depicted in  FIG. 10 , the passivation layer is removed from an area over a portion of bond pad  920 , by a dry etch process up to the bond pad  920  leaving an opening  1000  in the passivation layer. 
     As depicted in  FIG. 11 , a wet or dry metal etch is performed through the bond pad  920  down to surface  1100  of the BPSG layer  930 .  FIG. 12  depicts a nickel plating  1200  formed on the bond pad  920 . An oxide etch is performed on the lower passivation layer and down to the top layer  1300  of the silicon substrate  900 , as depicted in  FIG. 13 .  FIG. 14  depicts the optional application of a polyimide coat  1400  to planarize and protect the frontside of the wafer from residual metals on the vertical surfaces of the wafer topography. These residual metals are formed when material is not sufficiently removed in previous CMP or wet or dry etch processing. 
     As depicted in  FIG. 15 , a resist coat  1500  is applied for performing a deep silicon etch. The results of the etch are depicted in  FIG. 16  in which a via  1600  approximately 150-300 micrometers deep has been etched. The deep silicon etch resist coat  1500  is then stripped, as depicted in  FIG. 17 .  FIG. 18  depicts the deposition of a dielectric material  1800  on the via  1600  sidewalls and other surfaces. The dielectric  1800  serves as an electrical insulation layer for the sidewalls. In  FIG. 19 , results of a spacer dry etch are depicted as having removed the dielectric from the surface  1400 , but maintaining the dielectric  1800  on the via sidewalls. 
     Turning to  FIG. 20 , a seed layer of conductive material is formed on the dielectric and on the metal bond pads through processes known in the art such as e.g., CVD, PECVD, PVD. In  FIG. 21 , the seed layer is covered with photoresist  2150  to protect the surface from subsequent plating steps. Electroless or electrolytic nickel plating  2000  is depicted on the sidewalls  2010  of the via  1600  and also on the top portion of the bond pad  920 . In the optional flow of using polyimide  1400 , the polyimide  1400  may be stripped from the surface of the passivation layer  910  ( FIG. 21 ). The via  1600  is filled with conductive material such as solder  2200  utilizing plating or molten solder as depicted in  FIG. 22 .  FIG. 23  depicts a thinned wafer  2300  having been processed by backgrind, CMP, wet etch, dry etch, or any other thinning method known in the art. 
       FIG. 24  depicts an optional tetramethylammonium hydroxide (TMAH) silicon etch that exposed the dielectric  2410  on the bottom side of the via and causes the via insulation and via fill material to slightly protrude out from the backside surface. Regardless of whether the TMAH etch is performed, a dielectric deposition is applied to passivate the backside  2500  of the wafer, as illustrated in  FIG. 25 . With the via protruding in the manner described, CMP or a wet etch may be performed across the entire backside of the wafer in order to remove the insulating material covering the solder while maintaining a passivation layer over bulk silicon regions of the backside of the wafer. 
     As an alternate embodiment to CMP exposure of the solder on the backside of the wafer, turning to  FIG. 26 , a resist  2600  is applied to the backside of the wafer and in  FIG. 27 , the lower level of passivation is removed by applying a photo pattern and performing a wet oxide etch or dry spacer etch to expose the lower layer of solder  2700 . The resist is stripped and a solder ball  2800  may be attached to the bottom of the via  1600 , as depicted in  FIG. 28 . Alternatively, a solder ball  2800  could be attached to the top of the via  1600 , or a solder ball  2800  could be attached to both the top and the bottom, or not attached at all. 
     As depicted in  FIG. 28 , a through-wafer interconnect  2830  is formed in which the interconnect  2830  extends from a topside surface  2810  of the wafer where it is electrically connected to a bond pad  920 , to a bottomside surface  2820  of the wafer and in which a solder ball  2800  is attached and electrically connected to the bottomside surface of the interconnect  2830 . As a result, the interconnect  2830  is actually part of the structure of the device or circuit included within the wafer and is more reliable, due to shorter connections and fewer parts, enabling a subsequent packaging size of the die to be greatly reduced and allowing die to be stacked with no wire bonding. 
     Turning to  FIGS. 29-35 , a second exemplary process for forming a blind via is depicted. The beginning of the second exemplary process is identical to the portions of the first exemplary process depicted above in connection with  FIGS. 9-22  The process continues at  FIG. 29 , as described below. 
       FIG. 29  depicts a carrier  3500  bonded to the upper layer of the wafer with a carrier bonding adhesive  3520  and the wafer is thinned to surface  3510  though any thinning process known in the art. The carrier material could be a substrate such as silicon, glass, silicon nitride, aluminum nitride, or any other material suitable for use as a carrier substrate. The adhesive can be photoresist, photo-definable epoxy, an adhesive tape medium, UV releasable tape, etc. A TMAH silicon etch may be optionally performed to expose the via  3610  at the bottom of the via and cause it to slightly protrude from the surface, as depicted in  FIG. 30 . 
       FIG. 31  depicts a dielectric deposition  3700  to passivate the backside of the wafer and  FIG. 32  depicts a resist and pattern  3810  applied to the backside of the wafer to prepare for an etch process on the backside. A wet passivation etch or dry spacer etch is performed to remove the backside passivation  3700  from the solder via  3900 , as depicted at  FIG. 33 . This may also be accomplished with a light CMP or grind operation which leaves passivation material over the bulk silicon while allowing the solder to be exposed on the backside of the filled via.  FIG. 34  depicts the removal of the resist  3810  and the application of solder ball  4010 .  FIG. 35  depicts removal of the carrier  3500 . 
     Here again, a through-wafer interconnect  4100  is formed in which the interconnect  4100  extends from a topside surface  4110  of the wafer, where it is electrically connected to a bond pad  920 , to a bottomside surface  4120  of the wafer and in which a solder ball  4010  is attached and electrically connected to the interconnect  4100 . The interconnect is part of the structure of the device or circuit included within a die and is more reliable, due to fewer connections and external parts, enabling a subsequent packaging size of a die to be greatly reduced. 
     In accordance with exemplary embodiments of the invention, packaging solutions are described which eliminate wire bonding to bond pads. As a result, die performance and reliability are enhanced. Furthermore, these processes result in much smaller die packages which may be stacked and which lend themselves to WLP. Packaging costs are also significantly reduced as a result. 
     While the invention has been described in detail in connection with preferred embodiments known at the time, it should be readily understood that the invention is not limited to the disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. For example, although the processes are described in a specific order, some of the process steps may be performed in an order different than that described above. Further, while the processes are described in connection with imager and memory wafers, the invention is not limited to such applications. The invention may be practiced with other types of wafers as well as any device that would benefit from such a through-wafer interconnect. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.

Technology Classification (CPC): 7