Patent Abstract:
An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Full Description:
TECHNICAL FIELD 
       [0001]    The invention relates generally to a comparator and, more particularly, to a sense amplifier based comparator. 
       BACKGROUND 
       [0002]    Comparators are non-linear circuits that are generally used to detect the sign differences between two or more signals and have been used to resolve signals in a variety of applications, such as memory and analog-to-digital converters (ADCs). As an example, a sense amplifier  50  (which can, for example, function as a comparator for memory applications) is shown in  FIG. 1 . Specifically, this sense amplifier  50  is a CMOS circuit that functions as a regenerative, clocked comparator. It generally comprises cross-coupled PMOS and NMOS transistors Q 2  to Q 5 , a differential input pair of NMOS transistors Q 7  and Q 8 , and a clock circuit (which generally includes PMOS transistors Q 1  and Q 6  and NMOS transistor Q 9 ). When the clock signal CLK is logic low or “0,” output terminals R and S can be precharged to the voltage on supply rail VDD and, when the clock signal CLK is logic high or “1,” the output values at terminals R and S are resolved based on the input values at input terminals INM and INP. If the voltage on input terminal INP is greater than the voltage on terminal INM, the terminals S and R resolve as “1” and “0,” respectively, and, conversely, when voltage on input terminal on INP is less than the voltage on terminal INM, the terminals S and R resolve as “0” and “1,” respectively. Additionally, transistor Q 9  couples and decouples the differential pair Q 7  and Q 8  to ground (supply rail) based on the clock signal CLK. 
         [0003]    A property used to describe the behavior of the sense amplifier  50  is its “time constant,” which indicates dependency of the propagation delay (or “clock to Q delay”) on the amplitude of the inputs. Typically, with a smaller the magnitude in the difference in voltage between terminals INM and INP, there is a longer delay to resolve the values on terminals R and S. This relationship between can be expressed as follows: 
         [0000]        T   PROP =max( t   FIXED   , t   FIXED −τ*1 n ( |V   IN |)),   (1)
 
         [0000]    where T PROP  is the propagation delay, t FIXED  is a fixed comparator delay related to (for example) process variation, temperature, and voltage on supply rail VDD, τ is a time constant, and |V IN | is the magnitude of the difference in voltage between terminals INM and INP (which is typically a differential signal). Usually, equation (1) holds for signals on the order of 100 mV or less, and, once the difference is sufficiently large, the propagation delay T PROP  saturates to the fixed comparator delay t FIXED . Thus, for some applications, it is desirable to reduce this propagation delay T PROP  to more quickly resolve comparison results for low amplitude signals. 
         [0004]    Some examples of conventional systems are: U.S. Pat. No. 4,274,013; U.S. Pat. No. 4,604,533; U.S. Pat. No. 5,627,789; U.S. Pat. No. 5,901,088; U.S. Pat. No. 7,688,125; and Payandehnia et al., “A 4 mW 3-tap 10 Gb/s Decision Feedback Equalizer,” 2011  IEEE  54 th International Midwest Symposium on Circuits and Systems  (MWSCAS), Sep. 23, 2011, pp. 1-4. 
       SUMMARY 
       [0005]    An embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a CMOS sense amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first output circuit having a first load capacitance; a second output circuit having a second load capacitance; and an isolation circuit that is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and that is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier, wherein the isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier. 
         [0006]    In accordance with an embodiment of the present invention, the first and second output circuits further comprise first and second inverters, respectively. 
         [0007]    In accordance with an embodiment of the present invention, the CMOS sense amplifier is controlled by a clock signal, and wherein the isolation circuit further comprises: a precharge circuit that is coupled to the first and second inverters and that is controlled by the clock signal; and a first isolation element that is coupled between the first output terminal of the CMOS sense amplifier and the first inverter; and a second isolation element that is coupled between the second output terminal of the CMOS sense amplifier and the second inverter. 
         [0008]    In accordance with an embodiment of the present invention, the precharge circuit further comprises: a first MOS transistor that is coupled to the first inverter at its drain; and a second MOS transistor that is coupled to the second inverter at its drain. 
         [0009]    In accordance with an embodiment of the present invention, the first and second isolation elements further comprise first and second resistors, respectively. 
         [0010]    In accordance with an embodiment of the present invention, the clock signal further comprises a first clock signal, and wherein the first and second isolation elements further comprise first and second switches, respectively, that are controlled by a second clock signal, and wherein there is a non-overlapping period between activation of the CMOS sense amplifier by the clock signal and activation of the first and second switches by the second clock signal. 
         [0011]    In accordance with an embodiment of the present invention, the sense amplifier further comprises: a clocking circuit that is configured to receive the first clock signal; a differential input pair of transistors that is configured to receive an differential input signal; a first pair of cross-coupled transistors that is coupled to the differential input pair of transistors; and a second pair of cross-coupled transistors that is coupled to the first pair of cross-coupled transistors. 
         [0012]    In accordance with an embodiment of the present invention, an apparatus is provided. The apparatus comprises: an analog front end (AFE); an analog-to-digital converter (ADC) that is coupled to the AFE, wherein the AFE has a plurality of slicers, and wherein each slicer includes: a CMOS sense amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first output circuit having a first load capacitance; a second output circuit having a second load capacitance; an isolation circuit that is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and that is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier, wherein the isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier; and a decision feedback equalizer (DFE) that is coupled to the ADC. 
         [0013]    In accordance with an embodiment of the present invention, an apparatus is provided. The apparatus comprises a serializer; a transmitter that is coupled to the serializer; a communication medium that is coupled to the transmitter; a receiver having: an AFE; an ADC that is coupled to the AFE, wherein the ADC has a plurality of slicers, and wherein each slicer includes: a sense amplifier having: a first supply rail; a second supply rail; a first output terminal; a second output terminal; a pair of cross-coupled PMOS transistors that are each coupled to the first and second output terminals and to the first supply rail; a pair of cross-coupled NMOS transistors that are each coupled to the first and second output terminals; a differential input pair of NMOS transistors that are each coupled to the communication channel and the pair of cross-coupled NMOS transistors; a first clocking NMOS transistor that is coupled between the first supply rail and the first output terminal and that is configured to receive a clock signal; a second clocking NMOS transistor that is coupled between the first supply rail and the second output terminal and that is configured to receive the clock signal; and a third clocking NMOS transistor that is coupled between the differential input pair of NMOS transistors and the second supply rail and that is configured to receive the clock signal; a first output circuit having a first load capacitance; a second output circuit having a second load capacitance; an isolation circuit that is coupled between the first output terminal of the sense amplifier and the first output circuit and that is coupled between the second output terminal of the sense amplifier and the second output terminal of the sense amplifier, wherein the isolation circuit isolates the first and second load capacitances from the sense amplifier; and a DFE that is coupled to the ADC; and a deserializer that is coupled to the DFE. 
         [0014]    In accordance with an embodiment of the present invention, the isolation circuit further comprises: a precharge circuit that is coupled to the first and second inverters and that is controlled by the clock signal; and a first isolation element that is coupled between the first output terminal of the sense amplifier and the first inverter; and a second isolation element that is coupled between the second output terminal of the sense amplifier and the second inverter. 
         [0015]    In accordance with an embodiment of the present invention, the precharge circuit further comprises: a first precharge PMOS transistor that is coupled to the first inverter at its drain; and a second precharge PMOS transistor that is coupled to the second inverter at its drain. 
         [0016]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0018]      FIG. 1  is a diagram of an example of a conventional CMOS sense amplifier; 
           [0019]      FIG. 2  is a diagram of an example of a system in accordance with an embodiment of the present invention; 
           [0020]      FIG. 3  is a diagram of an example of at least a portion of the ADC of  FIG. 2 ; 
           [0021]      FIGS. 4 and 5  are diagrams of examples of a slicer of  FIG. 3 ; and 
           [0022]      FIG. 6  is an example of a timing diagram for the slicer of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0024]    As mentioned above, it is desirable in some applications to reduce the propagation delay T PROP . This can be accomplished through adjustment of time constant τ. An example of such an application would be a sense amplifier based slicer in a serializer/deserializer (SERDES) system  100 , which can be seen in  FIGS. 2 and 3 . In operation, the serializer  102  converts parallelized streams of data into a serial data stream. This serialized data is then transmitted by transmitter  104  over channel  106  (which is generally a communication medium, like a twisted pair) to receiver  108 . The analog front end (AFE)  112  of receiver  108  is then able to recover the signal from the channel  106 , which is then digitized by ADC  114  (which generally employs slicers  202 - 1  to  202 -N and which can be several ADCs). The DFE  116  then filters and equalizes the digitized signal (i.e., compensates for inter-symbol interference or ISI), and the deserializer  110  parallelizes the output from the DFE  116 . Within this system  100 , it is the slicers  202 - 1  to  202 -N, which use a sense amplifier based comparator that can benefit from adjustment of time constant τ. 
         [0025]    Turning back to  FIG. 1 , the time constant τ is related to capacitance. Specifically, this time constant τ is proportional to a load capacitance C LOAD  divided by the transconductance g m  of the transistors Q 2  through Q 5  (i.e., τ α C LOAD /g m ). This load capacitance C LOAD  is typically the sum of the intrinsic or internal capacitance C INT  of sense amplifier  50  and an external capacitance C EXT  on terminals R and S. To reduce the time constant τ, the load capacitance C LOAD  should be reduced, while increasing the transconductance g m . Increasing the transconductance g m  would mean that the transistors Q 1  to Q 9  should be increased in size, but the increase in size is limited as internal capacitance C INT  is proportional to the sizes of transistors Q 1  to Q 9 . Thus, merely increasing the sizes of transistors Q 1  to Q 9  would not achieve the desired effect, so the slicers  202 - 1  to  202 -N employ sense amplifier based comparators where the external capacitance C EXT  is decoupled or isolated from the internal capacitance C INT  so that load capacitance C LOAD  is approximately equal to the internal capacitance C INT . 
         [0026]    An example of such a slicer  202 - 1  to  202 -N (which is labeled  202 -A) can be seen in  FIG. 4 . As shown in this example, the external capacitance C EXT  results from the loading of the output circuits (which are generally comprised of inverters  206  and  208  in this example). An isolation circuit  204 -A is coupled between terminals R and S and inverters  206  and  208 . This isolation circuit  204 -A is generally comprised of a precharge circuit (i.e., PMOS transistors Q 10  and Q 11 ) and resistors R 1  and R 2 . The precharge circuit (which is controlled by clock signal CLK) is generally used to precharge the external capacitance C EXT  provided by inverters  206  and  208 , and the resistors R 1  and R 2  (which function as isolation elements) isolate the external capacitance C EXT  from the internal capacitance C INT . Additionally, because transistors Q 10  and Q 11  provide the precharging for the external capacitance C EXT , transistors Q 1  and Q 6  can be reduced in drive strength (i.e., size), which reduces the internal capacitance C INT  and further reduces time constant τ. 
         [0027]    In  FIG. 5 , another example of a slicer  202 - 1  to  202 -N (which is labeled  202 -B) is shown. Slicer  202 -B is similar to the slicer  202 -A, except that isolation circuit  204 -A has been replaced with isolation circuit  204 -B. In isolation circuit  204 -B, switches SW 1  and SW 2  are employed as the isolation elements. These switches SW 1  and SW 2  are controlled by clock signal CLK′. As shown in  FIG. 6 , clock signal CLK′ is generated such that there is a non-overlapping period between activation of the sense amplifier  50  by the clock signal CLK and activation of switches SW 1  and SW 2  by the clock signal CLK′. During these non-overlapping periods, the external capacitance CEXT is isolated, allowing the time constant τ to be set by the internal capacitance C INT . It is at a point later (once the sense amplifier  50  has resolved the values on terminals R and S) that the output circuits (i.e., inverters  206  and  208 ) are coupled to the terminals R and S. 
         [0028]    As a result of implementing these slicers  202 - 1  to  202 -N, several advantages can be realized. First, the shortened propagation delay allows the slicers  202 - 1  to  202 -N to operate at a higher speed (i.e., clock frequency CLK is higher). Second, comparator metastability can be reduced, and, third, the bit error rate (BER) of ADC  114  and the overall transceiver system is improved. 
         [0029]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Technology Classification (CPC): 7