Patent Abstract:
A device for amplifying a signal includes a first amplifier which amplifies an input signal with reference to a reference voltage level to generate an amplified signal, a limiter circuit which limits an upper end of the amplified signal to a level twice as high as the reference voltage level so as to output a limited amplified signal, a second amplifier which amplifies the limited amplified signal with reference to an average of the limited amplified signal, and a comparator which compares an output of said second amplifier with the reference voltage level to output a result of the comparison.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to an amplifier, and particularly relates to an amplifier which can substantially avoid a duty-ratio error. 
     2. Description of the Related Art 
     As technology makes further progress in size reduction and lowering of power consumption of communication equipment, there is an increasing demand for circuits used in communication equipment to operate with low voltages. An IF (intermediate frequency) amplifier unit, which is generally provided at a stage prior to an FM demodulation unit, is required to provide a sufficient gain and a small waveform distortion under low-voltage conditions. 
     FIG. 1 is a circuit diagram of a related-art IF amplifier unit. 
     The IF amplifier unit of FIG. 1 includes amplifiers A 1  and A 2 , a comparator C 1 , and resistors R 1  through R 5 . 
     The amplifier A 1  receives an input signal via resistor R 1  at one input node when the input signal is supplied to an input terminal, and receives a reference voltage VSG at the other input node. The amplifier A 1  amplifies the input signal with reference to the reference voltage VSG. The input node of the amplifier A 1  that is connected to the resistor R 1  is connected to an output node of the amplifier A 1  via the resistor R 2 . 
     The signal amplified by the amplifier A 1  takes two different routes to be input to the amplifier A 2 , one being through the resistor R 3  and the other being through the resistor R 4 . The amplifier A 2  serves to cancel an offset of the input signal relative to the reference voltage VSG. The input node of the amplifier A 2  that is connected to the resistor R 3  is connected to the output node of the amplifier A 2  via the resistor R 5 . The other input node of the amplifier A 2  that is connected to the resistor R 4  is connected to the ground via a capacitor. 
     A signal output from the amplifier A 2  is supplied to the comparator C 1 . The comparator C 1  receives the reference voltage VSG in addition to the signal from the amplifier A 2 , and compares the signal with the reference voltage VSG to output a result of the comparison at its output node. 
     The IF amplifier unit of FIG. 1 exhibits problems when the input signal supplied to the input terminal exceeds a certain threshold voltage level. 
     FIGS. 2A through 2C are illustrative drawings of waveforms for explaining problems that arise when an input signal exceeds a threshold voltage level. 
     FIG. 2A shows an input signal together with a power voltage level and a ground voltage level where the input signal is supplied to the input terminal. As long as the input signal stays below a threshold voltage level, no problem is observed. 
     When the input signal exceeds the threshold voltage level, however, a signal output from the amplifier A 1  behaves as shown in FIG.  2 B. As shown in FIG. 2B, the output signal of the amplifier A 1  has an average voltage level V 2  that is different from the reference voltage VSG. This is because clamping occurs when the input signal to the input terminal exceeds the threshold voltage level. When the signal as shown in FIG. 2B is supplied to the amplifier A 2 , an output signal of the amplifier A 2  behaves as shown in FIG.  2 C. 
     Operating with reference to the reference voltage VSG, the comparator C 1  produces an output signal that suffers a phase displacement amounting to a temporal displacement dT in comparison with an output signal that would be obtained when a difference between the average voltage level V 2  and the reference voltage VSG is insignificant. This phase displacement leads to an error in a duty ratio. 
     Accordingly, there is a need for an IF amplifier which can reduce a difference between a reference voltage and an average voltage so as to suppress an error of a duty ratio. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide an amplifier which can satisfy the need described above. 
     It is another and more specific object of the present invention to provide an amplifier which can reduce a difference between a reference voltage and an average voltage so as to suppress an error of a duty ratio. 
     In order to achieve the above objects according to the present invention, a device for amplifying a signal includes a first amplifier which amplifies an input signal with reference to a reference voltage level to generate an amplified signal, a limiter circuit which limits an upper end of the amplified signal to a level twice as high as the reference voltage level so as to output a limited amplified signal, a second amplifier which amplifies the limited amplified signal with reference to an average of the limited amplified signal, and a comparator which compares an output of said second amplifier with the reference voltage level to output a result of the comparison. 
     In the amplifying device described above, the limiter circuit is situated between the first amplifier and the second amplifier so as to limit the amplified signal of the first amplifier to the level twice as high as the reference voltage level. This makes it possible to make an average voltage level of the signal input to the second amplifier substantially equal to the reference voltage level. That is, the limiter circuit serves to reduce a difference between the average voltage level and the reference voltage level. Such a reduction is useful in the communication technology since it prevents a displacement of signal phase. 
     According to one aspect of the present invention, the device as described above is such that the reference voltage level is lower than half of a power voltage level which drives the device. 
     In the configuration described above, use of the reference voltage level that is lower than half the power voltage level makes it possible to insure reliable operation even when the power voltage is lowered. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a related-art IF amplifier unit; 
     FIGS. 2A through 2C are illustrative drawings of waveforms for explaining problems that arise when an input signal exceeds a certain threshold voltage level; 
     FIG. 3 is a circuit diagram of an IF amplifier according to an embodiment of the present invention; 
     FIGS. 4A and 4B are illustrative drawing showing waveforms for explaining operation of a limiter circuit of FIG. 3; 
     FIG. 5 is a circuit diagram of the limiter circuit according to the embodiment of the present invention; and 
     FIG. 6 is a chart showing a relation between an output signal and an input signal of the limiter circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, embodiments of the present invention will be described with reference to the accompanying drawings. 
     FIG. 3 is a circuit diagram of an IF amplifier according to an embodiment of the present invention. 
     A configuration FIG. 3 has a limiter circuit  10  inserted at the output of the amplifier A 1  in addition to the configuration of FIG.  1 . The IF amplifier unit of FIG. 3 includes the amplifiers A 1  and A 2 , the comparator C 1 , the limiter circuit  10 , and the resistors R 1  through R 5 . 
     The amplifier A 1  receives an input signal via resistor R 1  at one input node when the input signal is supplied to an input terminal, and receives a reference voltage VSG at the other input node. The amplifier A 1  amplifies the input signal with reference to the reference voltage VSG. The input node of the amplifier A 1  that is connected to the resistor R 1  is connected to an output node of the amplifier A 1  via the resistor R 2 . 
     The signal amplified by the amplifier A 1  is supplied to the limiter circuit  10 . The limiter circuit  10  limits the signal supplied from the amplifier A 1 , and outputs a signal that is limited to a level that is twice the reference voltage VSG. The reason why such a signal limiting operation is carried out is that clamping occurs when the output signal of the amplifier A 1  exceeds the level twice the reference voltage VSG. 
     FIGS. 4A and 4B are illustrative drawing showing waveforms for explaining operation of the limiter circuit of FIG.  3 . 
     As shown in FIG. 4B, a signal output from the limiter circuit  10  is limited to the voltage level that is twice the reference voltage VSG, so that the average voltage level V 2  becomes substantially the same as the reference voltage VSG. 
     Even when the input signal supplied to the input terminal exceeds a threshold voltage level that makes the output signal of the amplifier A 1  clamped, the average voltage V 2  stays at the substantially the same level as the reference voltage VSG. 
     The signal amplified by the amplifier A 1  takes two different routes to be input to the amplifier A 2 , one being through the resistor R 3  and the other being through the resistor R 4 . The amplifier A 2  serves to cancel an offset of the input signal relative to the reference voltage VSG. The input node of the amplifier A 2  that is connected to the resistor R 3  is connected to the output node of the amplifier A 2  via the resistor R 5 . The other input node of the amplifier A 2  that is connected to the resistor R 4  is connected to the ground via a capacitor. 
     A signal output from the amplifier A 2  is supplied to the comparator C 1 . The comparator C 1  receives the reference voltage VSG in addition to the signal from the amplifier A 2 , and compares the signal with the reference voltage VSG to output a result of the comparison at its output node. 
     Since the average voltage level V 2  is substantially the same as the reference voltage VSG, the output signal of the comparator C 1  exhibits a duty-ratio error that is substantially reduced. 
     In the following, a description will be given with regard to a configuration of the limiter circuit  10 . 
     FIG. 5 is a circuit diagram of the limiter circuit  10  according to the embodiment of the present invention. 
     The limiter circuit  10  of FIG. 5 includes an amplifier A 3 , a transistor Tr 1 , an electric-current source I 1 , a resistor R 6 , and a resistor R 7 . 
     The amplifier A 3  has one input node thereof connected to the output node of the amplifier A 3  via the resistor R 6  and connected to the ground via the resistor R 7 . Here, the resistor R 6  and the resistor R 7  have an identical resistance. The amplifier A 3  has the other input node thereof receiving the reference voltage VSG. As a result, the amplifier A 3  outputs a voltage that is twice the reference voltage VSG. 
     The signal output from the amplifier A 3  is supplied to the transistor Tr 1 . The transistor Tr 1  outputs a signal from its output node such that the output signal varies in accordance with relationship between the signal supplied from the amplifier A 3  and a signal supplied from its input node. 
     FIG. 6 is a chart showing a relation between the output signal and the input signal of the limiter circuit  10 . 
     As shown in FIG. 6, the limiter circuit  10  produces an output signal that has the same voltage level as the input signal when the voltage level of the input signal is smaller than twice the reference voltage VSG. When the input signal has a voltage level greater than twice the reference voltage VSG, the limiter circuit  10  limits an output thereof to a level that is twice as high as the reference voltage VSG, thereby outputting a signal that is approximately equal to twice the reference voltage VSG. 
     In this manner, even when a signal input to the input terminal exceeds a threshold level to clamp a signal output from the amplifier A 1 , the average voltage V 2  becomes substantially equal to the reference voltage VSG because the limiter circuit places a cap at a voltage level twice as high as the reference voltage level VSG. Since the average voltage and the reference voltage VSG are substantially the same, an output from the comparator C 1  ends up having a substantially reduced duty ratio. 
     In the embodiment described above, the limiter circuit  10  has been described as a circuit having a configuration shown in FIG.  5 . It should be noted, however, that the limiter circuit  10  is not limited to this particular embodiment, and any circuit can be used in place of the circuit of FIG. 5 as long as such a circuit can limit a voltage level of a signal supplied from the amplifier A 1  to a level that is twice as high as the reference voltage VSG. 
     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese priority application No. 11-074473 filed on Mar. 18, 1999, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.

Technology Classification (CPC): 7