Patent Abstract:
A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Full Description:
[0001]    This U.S. patent application is a Continuation of U.S. patent application Ser. No. 12/874,397, filed on Sep. 2, 2010, which is a Division of U.S. patent application Ser. No. 12/029,574, filed on Feb. 12, 2008, and issued as U.S. Pat. No. 7,863,724 on Jan. 4, 2011. All of the above-referenced U.S. patent applications are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates generally to integrated circuit power supply distribution, and more particularly, to a methodology and substrate that has reduced power supply resistance from external power supply terminals to the die power supply connections. 
         [0004]    2. Description of the Related Art 
         [0005]    High-density interconnect schemes for processor packages, as well as other very-large-scale integrated (VLSI) circuits, typically use a large number of circuit layers to connect one or more dies to electrical terminals disposed on one or more surfaces of the package, as well as to interconnect multiple dies in multi-die packages. Power distribution in packages having bottom-side terminals and top side die mounting is typically performed by including multiple v cias connecting power supply terminals of the one or more dies to power supply planes that are disposed at metal layers at or near the bottom of the substrate. In packages having no power supply planes, power supply distribution is generally accomplished using vias extending from the die power supply terminals to the package terminals. 
         [0006]    When distributing power to dies such as those including one or more processors, a very low resistance path from the power supply terminals to the die is a requirement. Present-day VLSI integrated circuits such as processors, can require power supply currents in excess of 100 amperes and operate at power supply voltages of less than one volt. A net power supply path resistance of 0.005 milliohms will result in a power dissipation of 50 Watts under such conditions, which is 50% of the total power consumption. The resulting drop in voltage would require a 2 volt power supply to deliver 1 volt at the die. 
         [0007]    Therefore, large numbers of commonly-connected die terminals, vias and package terminals are included for each power supply connection (including return paths such as ground), to ensure that the overall resistance of each power supply path does not result in substantial power loss and voltage drop. The vias are typically placed under the die and/or near the edges of the die, to reduce the power supply path resistance. 
         [0008]    However, such power supply distribution consumes routing resources that could otherwise be utilized for routing signal paths, thereby increasing the size, weight, cost and complexity of the substrate and package. Further, inclusion of power supply vias near or under the die to decrease path resistance either requires placement of decoupling capacitors adjacent to the die, or placement of wide conductors extending to the decoupling capacitors further away from die, limiting critical signal routing resources near the edges of the die. Resources are further limited since manufacturing processes limit the number of layers a via can transit before requiring a “jog” or lateral displacement. The vias for power supplies are numerous and/or larger that signal vias in order to decrease resistance, and therefore the requirement to place power supply vias under or near the die drastically reduces the signal routing resources that would otherwise be available. 
         [0009]    Therefore, it is desirable to provide a substrate for an integrated circuit package, and a method for making a substrate for an integrated circuit package, that frees up routing resources in the vicinity of the die(s) by routing power supply connections from the die(s) to external terminals in regions away from the die(s). 
       BRIEF SUMMARY 
       [0010]    The objective of freeing routing resources in the vicinity of the die(s) of an integrated circuit package is achieved in an integrated circuit substrate, and methods for making the integrated circuit substrate. 
         [0011]    The substrate includes a pair of top metal layers separated by an insulating layer, that form power supply planes for supplying power supplies to a die. Power supply lands for connecting the power supplies to the die are disposed on a top metal plane, and include connected lands for a first power supply plane and isolated lands for a second power supply plane. Small-diameter blind vias are formed from the inner one of the top metal layers to the isolated lands. Large-diameter plated-through structures, e.g., plated-through holes, are formed near edges of the substrate and are electrically connected to a corresponding one of the top or inner metal layers. Power supply terminals are provided at the bottom of the substrate, which may be terminal lands connected by jogs to the bottoms of the plated-through structures, or may be extensions of a conductive pin inserted through the plated-through structures forming solderable power supply leads at the bottom of the substrate. 
         [0012]    A plurality of conductive vias may be formed around the plated-through structure, to decrease the resistance from the bottom of the plated-through structure to the top, as well as to form improve connections to the top and inner metal power supply planes. 
         [0013]    The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0014]    The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying Figures, wherein like reference numerals indicate like components, and: 
           [0015]      FIG. 1A  is a top view of an integrated circuit in accordance with an embodiment of the present invention. 
           [0016]      FIG. 1B  is a top view of an integrated circuit in accordance with another embodiment of the present invention. 
           [0017]      FIG. 2A  is a cross-sectional view of a portion of substrate  10 A of  FIG. 1A , in accordance with an embodiment of the present invention. 
           [0018]      FIG. 2B  is cross-sectional view of a substrate in accordance with another embodiment of the present invention. 
           [0019]      FIG. 2C  is cross-sectional view of a substrate in accordance with yet another embodiment of the present invention. 
           [0020]      FIGS. 3A-3F  are cross-sectional views illustrating steps in the manufacture of a substrate in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    The present invention concerns integrated circuit package substrates and methods of designing and making the substrates that provide improved power supply terminal coupling to the die. The resistance of the power supply connection paths is decreased by forming large-diameter plated-through holes near the edges of the substrate, and using them to provide power supply voltages to metal power plane layers at the top of the substrate. The large-diameter plated-through holes may be paste-filled or conductive pins may be inserted through the plated-through holes to further decrease resistance from the power supply terminals of the integrated circuit to the power planes. Power from the top of the large-diameter plated-through holes is transferred to the top metal power plane layer and the inner metal power plane layer(s) by the plated-through holes themselves, along with additional small diameter vias disposed around the central plated-through holes, which increase the effective area of contact to the metal power planes, as well as decreasing the overall resistance of the vertical structure. The power supply terminals may be directly provided by the conductive pins, by providing the conductive pins as solderable pins extending below the bottom surface of the substrate. Power supply connections to the die are made by lands formed on the top metal power supply plane and lands that are not connected to the top metal power supply are fed by small-diameter blind vias from the metal layer beneath that forms the other supply plane. While the illustrated embodiment depicted herein is directed toward substrates and integrated circuits having two power supply planes, additional power supply planes may be added beneath the top two power supply planes and additional plated-through structures added to supply their corresponding power supply voltages. 
         [0022]    Referring now to  FIG. 1A , a top view of an integrated circuit in accordance with an embodiment of the present invention is shown. A die  14 A is mounted on a substrate  10 A. Electrical connections to the die are made from a plurality of lands including power supply lands  16 A,  16 B, generally by bond wires (not shown) extending from the plurality of lands to terminals of the die. Power supply land  16 A illustrates a “connected” land, that includes metal stubs extending to the power plane forming the bulk of the metal layer on which the plurality of lands are formed, which lies beneath the top soldermask SMT. Power supply land  16 B illustrates an “isolated” land, which is connected to the other metal power supply plane layer by a small-diameter conductive blind via. Signal lands  15  are also isolated lands and are also connected by vias to signal layers disposed underneath the power plane layers. Locating the power planes at the top of the stack forming substrate  10 A reduces resistance of power supply connections substantially, as the length of small-diameter vias required to connect from power supply terminals of die  14 A to the power planes is shortened substantially. Away from die  14 A, near the edges of substrate  10 A large-diameter plated-through structures  12 A,  12 B are formed to connect power supply terminals at the bottom side of substrate  10 A to the top metal power planes. Plated-through structure  12 A illustrates a connected plated-through structure, which has a top end formed on or partially within the top metal power plane layer and is electrically connected thereto. Plated-through structure  12 B illustrates an isolated plated-through structure, which has a top end formed on or partially within the inner metal power plane layer and is electrically connected thereto. In the exemplary embodiment, a plurality of conductive small-diameter vias  13  are disposed around a central plated-through hole  11  in a circular pattern. Small-diameter vias  13  improve the connection between plated-through hole  11  and the metal power planes, and assist in lowering the overall resistance from the bottom end of plated-through structure  12 A to the top end. Since the area of contact of the corresponding metal power plane layer with plated-through hole  11  and small-diameter vias  13  is the product of the thickness of the metal power plane layer with the sum of the circumference of each of plated-through hole  11  and small-diameter vias  13 , inclusion of small-diameter vias  13  decreases the resistance from the tops of plated-through structures  12 A, 12 B to their corresponding metal power planes. Additional decoupling capacitor lands  17 A,  17 B, of which one exemplary pair is shown, are disposed atop substrate  10 A, and similar to power supply lands  16 A,  16 B include connected decoupling capacitor land  17 A connected to the top power supply plane, and isolated decoupling capacitor land  17 B connected to the inner power supply plane by a small-diameter conductive blind via. 
         [0023]    Referring now to  FIG. 1B , a top view of an integrated circuit in accordance with another embodiment of the invention is shown. The integrated circuit of  FIG. 1B  is similar to the integrated circuit of  FIG. 1A , and therefore only differences between them will be described below. A die  14 B is mounted on a substrate  10 B over the die interconnect structure, and is mounted to a plurality of lands by solder bumps or posts. The plurality of lands includes power supply lands  18 A, 18 B which includes connected power supply lands  18 A and isolated power supply lands  18 B. Signal lands  15 A are also provided under die  14 B. 
         [0024]    Referring now to  FIG. 2A , a cross-section of substrate  10 A of  FIG. 1A , which is also illustrative of substrate  10 B of  FIG. 1B , is shown in accordance with an embodiment of the invention. Top metal layer TM 1  forms the top power supply plane and is connected to plated-through structure  12 B at ends of small-diameter vias  13  and plated-through hole  11 . Plated-through structure  12 A is similarly connected to inner metal layer TM 2 , which forms the inner power supply plane. Top metal layer TM 1  and inner metal layer TM 2  are adjacent, but separated by an insulating layer IL 1 , and effectively form a capacitor that can provide improved decoupling of power supply voltages connected to metal layers TM 1  and TM 2 . A number of signal layers and interposed insulating layers are included in an inner section  21  of substrate  10 A and are laminated beneath inner metal layer TM 2  and a bottom metal layer BM separated from the last metal layer in inner section  21  by another insulating layer IL 2 . Bottom metal layer BM includes terminal lands  24 C and jogs that connect terminal lands  24 C to plated-through structures  12 A and  12 B. A bottom soldermask SMB includes voids for attachment of solderballs or contact by “fuzz buttons” to lands  24 C. 
         [0025]    Atop substrate  10 A, decoupling capacitor lands  17 A,  17 B and die power supply lands  16 A,  16 B are formed in top metal layer TM 1 , and include a plated surface for die-attach. Solder mask SMT has voids above lands  16 A,  16 B,  17 A,  17 B, as well as above plated-through structures  12 A,  12 B. As mentioned above, isolated lands  16 B, 17 B are connected by corresponding small-diameter blind vias  25 A,  25 B to inner metal power supply layer TM 2 . Connected lands  16 A,  17 A are connected directly to other portions of top metal layer TM 1  by stubs formed between relief regions included around the lands. 
         [0026]    Referring now to  FIG. 2B , a cross-section of a substrate  10 C, is shown in accordance with another embodiment of the present invention. Substrate  10 C is similar to substrate  10 A as illustrated in  FIG. 2A  and therefore only differences between them will be described below. Substrate  10 C includes conductive pins  28  inserted through plated-through structures  12 A and  12 B, which are attached by solder  29  or other electromechanical attachment to pads in bottom metal layer BM that connected to terminal lands  24 C. Conductive pins  28  can also be soldered or otherwise bonded to the top ends plated-through structures  12 A and  12 B to further improve electrical connection. 
         [0027]    Referring now to  FIG. 2C , a cross-section of a substrate  10 D, is shown in accordance with another embodiment of the present invention. Substrate  10 D is similar to substrate  10 C as illustrated in  FIG. 2B  and therefore only differences between them will be described below. Substrate  10 D includes longer conductive pins  28 A inserted through plated-through structures  12 A and  12 B, which are attached by solder  29  to pads on a circuit board PWB, thereby providing the power supply terminals directly, freeing up area that would otherwise be required by terminal lands such as terminal lands  24 C of  FIG. 2B . Inner section  21 A therefore is not required to include power supply lands. Conductive pins  28 A can also be soldered or otherwise bonded to the top ends plated-through structures  12 A and  12 B to further improve electrical connection. 
         [0028]    Referring now to  FIGS. 3A-3F , a method of making an integrated circuit substrate and an integrated circuit in accordance with an embodiment of the invention is shown. Referring to  FIG. 3A , layers of metal and insulator are laminated together by a plating, die-cut. paste screening or other suitable process, where the layers include top metal layer TM 1 , insulating layer IL 1 , inner metal layer TM 2 , inner section  21 , insulating layer IL 2  and bottom metal layer BM having structures as described above to form substrate step  30 A. Next, as shown in  FIG. 3B , soldermasks SMT and SMB are applied to substrate step  30 A to form substrate step  30 B. Soldermasks SMT and SMB may alternatively be applied later in the fabrication process. Through holes  20  and via holes  20 A are drilled through substrate step  30 B and blind via cavities  20 B are also formed, if they have not been formed previous to lamination, resulting in substrate step  30 C as shown in  FIG. 3C . Since blind via cavities  20 B are only required to transit one circuit layer and one insulating layer, they may be formed during the formation of substrate step  30 A, or previously if the layers are die-cut or otherwise formed prior to lamination. 
         [0029]    Next, referring to  FIG. 3D , holes  20  ( FIG. 3C ) are plated and via holes  20 A ( FIG. 3C ) are filled by plating or pasting, forming plated-through structure  12 B. Also, blind via cavities  20 B ( FIG. 3C ) are filled, resulting in substrate step  30 D. Then, as shown in  FIG. 3E , lands  17 A,  17 B,  16 A and  16 B are plated with a material compatible with the die-attach and capacitor-attach processes. Terminal lands  24 C are also plated, forming substrate  30 E. Finally, decoupling capacitor C, die  14 B and solder balls  32  are attached to substrate  30 E, and conductive pins  28 A are inserted and attached with solder  29  to form an integrated circuit  40  of  FIG. 3F . Substrate  30 E of  FIGS. 3E  and  FIG. 3F  corresponds generally to substrate  10 B of  FIG. 2B . Fabrication of substrates and integrated circuits such as those illustrated in  FIG. 2A  and  FIG. 2C  are similar, and is understood with reference to  FIGS. 3A-3F  and the description above, with insertion of longer conductive pins  28  substituted for conductive pins  28 A and fabrication of terminal lands  24 C omitted for fabrication of substrate  10 C of  FIG. 2C , or omission of conductive pins altogether for the fabrication of substrate  10 A of  FIG. 2A . 
         [0030]    While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention.

Technology Classification (CPC): 8