Patent Abstract:
A non-volatile memory unit includes memory units for providing a data current corresponding to stored data; a first load unit having a first end; a second load unit having a second end; and a sensing unit. The first load unit and the second load unit can receive current input to build voltages respectively at the first end and the second end. When the memory unit provides the data current, the second load unit is enabled such that the data current inputs into the first load unit and the second load unit; then the second load is disabled after a predetermined time such that the data current inputs into the first load unit only, and the sensing unit generates a data signal for data-acquisition according to a voltage difference between the voltage at the first end and a reference voltage.

Full Description:
BACKGROUND OF INVENTION 
     1. Field of the Invention 
     The present invention relates to non-volatile memory, and more particularly, to a non-volatile memory that utilizes extra devices to accelerate transient state transitions, and disables extra load units to maintain the sensitivity of operating margins when reading data. 
     2. Description of the Prior Art 
     The growth of the so-called information age has led to the storage of mass quantities of information in digital form. Memory storage devices are thus an important topic of research and develop. Flash memory has become prevalent, allowing the access of data at speeds comparable to those of other forms of electronic memory, while storing digital data in a non-volatile manner without requiring any moving parts. Flash memory has thus become one of the most important types of non-volatile storage devices. 
     Please refer to FIG. 1, which is a circuit diagram of a prior art flash memory  10 . The flash memory  10  is biased by DC current V dd , and has a plurality of memory units  11 A and  11 B, two on-load isolating units  12 A and  12 B, a sensor unit SA 1 , two p-type MOS transistors Ta 1  and Ta 3  for load units, and a p-type MOS Ta 7  for reference units. In memory units  11 A and  11 B, MOS transistors Ma 1  and Ma 2  have floating gates to store data. The gates of MOS transistors Ma 1 , Ma 2 , TA 1  and TA 2  are controlled by the controlling voltage V ma1 , V ma2 , V d1  and V d2  respectively to determine whether the MOS is on or off. The MOS transistor TA 1  of the memory unit  11 A is also electrically connected to one end of the MOS transistor Ma 1 ; the other end serves as a data end, and is electrically connected with on-load isolating at the node Na 5 . Similarly, an end of MOS transistor TA 2  of the memory  11 B is electrically connected with the node Na 5 , and serves as a data end of the memory unit  11 B. On-load isolating units  12 A and  12 B utilize inverters Iva 1 , Iva 2  and p-type MOS transistors Ta 5 , Ta 6 , respectively. The p-type MOS transistors serve as a loading unit, connecting to provide negative feedback, of which the source electrode is connected to the node Na 1  with the load unit  12 A, and the drain electrode is grounded. The source electrode of the MOS transistor Ta 3 , serving as a third end, connects with the on-load isolating unit  12 B at the node Na 3 , and its drain electrode is grounded. The sensor unit SA 1  is a differential sensing amplifier, comprising a first comparing end N 1 a and a second comparing end N 2 a, which are connected respectively to the nodes Na 1  and Na 3 ; the sensor unit SA 1  compares the first comparing end N 1 a to the second comparing end N 2 a, and then generate a data signal V rp1 . The MOS transistor Ta 7  with a floating gate electrode serves as a reference unit, of which its gate electrode is controlled by the controlling-voltage V ca ; one of the other two electrodes is connected to the power V dd , and the other is connected to the node Na 6  with the on-load isolating unit  12 B. 
     The principle of operation for storing data into flash memory is to store each bit to one of the memory units that contains transistors with floating gates. Programming a bit into a memory unit, represented by a binary “0” or a binary “1” is performed by injecting differing amounts of electric charge. The floating-gate electrode is injected with a different amount of electric charge, which changes the threshold voltage. Even when under the same condition of voltage bias, the different amount of electric charge in the floating-gate results in a different conductance of the MOS transistor, and thus different amounts of data current. Accordingly, it is possible to read out the data stored in the floating-gates of all the memory units. As shown in the FIG. 1, when the memory  10  is to read the binary data stored in the memory unit  11 A, the memory  10  controls the controlling-voltage V ma1  to bias and turn on the MOS transistor Ma 1  from the gate electrode, and the MOS transistor Ma 1  then generates a data current If 1 . The memory  10  also turns on the MOS transistor TA 1  by a high-voltage level V d1  , so that the data current I f1  can flow through the MOS transistor TA 1  via the node Na 5 . Of course, the MOS transistor TA 2  of the memory unit  11 B is turned off by the controlling-voltage V d2 , which prevents the memory  11 B from outputting data current I f1  to the node Na 5 , and thus prevents interfere when reading the data from the memory unit  11 A. The on-load insolating unit  12 A transmits data current I f1  to the node Na 1 , and injects the current I f1  into the MOS transistor Ta 1 , which is the load unit. With the MOS transistor Ta 1  current-biased by this data current I f1 , the MOS transistor Ta 1  establishes a corresponding voltage at the node Na 1 . When the MOS transistor Ta 1  is turned on, the controlling-voltage V ca  turns on the MOS transistor Ta 7 , which also serves as a reference unit, making the MOS transistor Ta 7  generate a reference current I r1 , and injecting the current I r1  into the MOS transistor Ta 3 . Serving as the load unit, after the MOS transistor Ta 3  is biased with this reference current I r1 , the MOS transistor Ta 3  generates a corresponding voltage at the node Na 3 . The sensor unit SA 1  compares the voltage at Na 1  with the voltage at Na 3  through the first comparing end N 1 a and the second comparing end N 2 a, and generate a corresponding data signal V rp1 , which reads out the data in the memory unit  11 A. 
     The process of reading data is further illustrated in FIG.  2 . Please refer to FIG.  2  and FIG.  3 . FIG. 2 is a graph of voltage versus time at first comparing end N 1 a and the second comparing end N 2 a when the memory  10  is in process of reading data; the X-axis represents time, and the Y-axis represents the voltage; the curves V(N 1 a)H and V (N 1 a)L represent voltage at the first comparing end N 1 a varying with time, whereas the curve V(N 2 a) represents the voltage at the second comparing end N 2 a. Before the timing point ta 0 , the memory  10  has not yet read the data, and the first and the second comparing ends, N 1 a and N 2 a, are charged to high-voltage levels. When the time reaches ta 0 , the MOS transistors Ma 1  and Ta 7  generate current, and pull down the voltages of the first comparing end Na 1  and the second comparing end Na 2 . As mentioned above, differing amounts of electric charge stored in the floating gate of the MOS transistor Ma 1  in the memory unit  11 A results in a different data current I f1 . When the data current I f1  is greater (indicating a lower threshold voltage), the voltage of the first comparing end N 1 a will have the shape of V(N 1 a)H, and eventually falls to a higher steady-state voltage V aH ; on the other hand, when the data current I f2  is smaller, the voltage of the first comparing end N 1 a will follow curve V(N 1 a)L, and eventually falls to a lower steady-state voltage V aL . Similarly, the voltage of the second comparing end N 2 a falls to a steady-state voltage V aR . During the interval between ta 0  and ta 2 , the inverters Iva 1  and Iva 2  in the on-load isolating units  12 A and  12 B respectively and adequately bias the MOS transistors Ta 5  and Ta 6 , which lightens the load-effect occurring at the nodes Na 1  and Na 3  to accelerate the speed at which a steady-state is reached. When the voltages of the two comparing-ends N 1 a, N 2 a have reached their respective steady-state voltages, the sensor-unit SA 1  determines what data is stored in the memory  11 A by detecting the voltage difference between the two comparing ends N 1 a, n 2 a. When the voltage of the first comparing end N 1 a is greater than that of the second comparing end N 2 a, the electric charge stored in the MOS transistor Ma 1  corresponds to a greater data current. The sensor unit SA 1  thus decides if the data stored in the memory unit  11 A is a binary “0” or a binary “1”, and accordingly generates a data signal V rp1 . 
     It&#39;s common to utilize many memory units in an ordinary flash memory, and connect them to the node Na 1  through relatively long metal paths. A large capacitance is consequently formed at the node Na 1 . Decreasing the voltage of the node Na 1  to a steady state merely by way of the data current of a memory unit is quite slow. One drawback of the prior art memory  10  is that the process of reading data is easily affected by transient states, or discharging. As shown in FIG. 2, if the sensor unit SA 1  incorrectly compares the voltages at the timing-point ta 1 , regardless of the data current flowing out of the memory unit  11 A is great or small, the sensor unit SA 1  will erroneously decide that data is stored in the memory unit  11 A, since the voltage of the first comparing end N 1 a is definitely greater than that of the second comparing end N 2 a. 
     Please refer to FIG. 3, which is circuit diagram of a prior art memory  20 . For the sake of convenience, item numbers marked in FIG. 3 that are the same as those in the FIG. 1 correspond to devices or nodes having the same functionality. The most obvious difference between the memory  20  and the memory  10  is that the memory  20  utilizes an additional equalizing unit  24 . Between the first comparing end N 1 a and the second comparing end N 2 a of the memory  20  there is a p-type MOS transistor Tta, an n-type MOS transistor Ttb and an inverter Ivb 3 . The p-type MOS transistor Tta and the n-type MOS transistor Ttb form a transmission gate, where V eq0  controls the transmission gate with the inverter Ivb 3 . When the transmission gate is on, the nodes Na 1  and Na 3  are shorted, otherwise, they are opened. 
     Please refer to FIG. 4A, which is a graph of voltage versus time between the first comparing end N 1 a and the second comparing end N 2 a when the memory  20  is reading data. The X-axis of FIG. 4A is time, and the Y-axis is voltage. The curves V (N 1 a)L and V(N 1 a)H show how differing data currents result in different voltages at the first comparing end N 1 a. The curve V(N 2 b) illustrates the voltage of the second comparing end N 2 a. Continuing with the example depicted in FIG. 2, it is also assumed that the memory unit  11 A of the memory  20  provides a data current I f1 . Differing from the memory unit  10 , however, is that at the timing point ta 0 , when the memory  20  controls the memory unit  11 A to generate the data current I f1  and the MOS transistor Ta 7  to generate the data current I r1 , the memory  20  also controls the voltage Veq 0  to turn on the transmission gate in the equalizing unit  24  to short the nodes Na 1  and Na 3 . Therefore, the voltages of the first and the second comparing ends N 1 a and N 2 a are equal, and their voltages changing at the same rate. As shown in FIG. 2, the curves V(N 1 b)H, V(N 1 b)L and V(N 2 b) overlap between the timing points ta 0  and tb 1 . When the timing point tb 1  is reached, the controlling voltage Veq 0  changes to turn off the transmission gate, and the nodes Na 1  and Na 3  are no longer shorted through the equalizing unit  24 ; their reach their respective steady state values. At the time point tb 2 , the sensor unit SA 1  determines the data stored in the memory unit  11 A by the voltage difference between the first and the second comparing end N 1 a and N 2 a. In short, the memory  20  causes the voltages of the first and the second comparing ends N 1 a and N 2 a to be the same by controlling the equalizing unit  24 . This prevents the memory unit  20  from incorrectly determining the data during the transient states. 
     The sensor unit SA 1  of memory  20  determines the data stored in the memory unit  11 A according to the steady-state-voltages of V aH , V aL  and the reference voltage V aR  (please refer to FIG.  2  and FIG.  4 A). As the differences between these voltages is greater, the SA 1  is able to determine and read the data more clearly, and the margin for reading the data is increased as well. The steady-state-voltages V aH  and V aL  are affected by the following factors: inconsistencies in the semiconductor manufacturing process that makes memory units that are not perfectly identical, noise interference when a read operation is in process, and changes to electrical characteristics because of repeated programming and erasing. If these factor are taken into consideration in advance to increase the operating margin by enlarging the voltage difference between V aH , V aL  and V aR , then even when the above factors occur and result in voltage-drifting between V aH  and V aL  during operation of the memory, the memory is still able to correctly read the data. Since the steady-state-voltages V aH  and V aL  are established by the data current injecting into the MOS transistor Ta 1  (as shown in FIG.  1  and FIG.  3 ), it is possible to change the characteristics of the MOS transistor TA 1  when designing the memory so as to enlarge the voltage difference between V aH  and V aL . Generally speaking, if the MOS transistor Ta 1  has a smaller aspect ratio (W/L ratio) under the condition of a fixed data current, then the voltage difference between V aH  and V aL  will be larger. Please refer to FIG. 4B, which is a graph of current versus voltage between the currents of source and drain electrodes and the voltage across the MOS transistor Ta 1 . If MOS transistor Ta 1  has a smaller aspect ratio, its current-voltage curve is as shown by IV 1 ; if MOS transistor Ta 1  has a larger aspect ratio, its current-voltage curvature is as shown in IV 2 . As mentioned above, the supplied current will be different if the data stored in the memory unit is different. The two currents I f1  (H) and I f1  (L) shown in FIG. 4B illustrate that the memory unit can provide two current levels, and when they are injected into the MOS transistor Ta 1 , they establish two levels of steady-state-voltages V aH  and V aL . As shown in the curve IV 1 , if the aspect ratio of the MOS transistor Ta 1  is smaller, the voltage difference DV 1  between the two corresponding steady-state-voltages is larger, as well as the operating margin. On the other hand, as the curve IV 2  illustrates, when the aspect ratio of MOS transistor Ta 1  is lower, the operating margin DV 2  is narrower. 
     However, it is known in the prior art that decreasing the aspect ratio of the MOS transistor Ta 1  also decreases the current-driving ability the MOS transistor. The period of transient states is thus lengthened. Consequently, the period from when the memory unit begins to supply data current and pulls down the voltage of the first comparing end, to the voltage reaching steady state and thus able to be read data, is increased. This decreases the efficiency data accessing. The prior art memory units  10  and  20  are all undermined by their inability to give consideration to both the operating margins and the reading speed. 
     SUMMARY OF INVENTION 
     It is therefore a primary objective of the claimed invention to provide a memory using a two-stage sensing amplifier with an additional load unit to increase the operating margin while maintain a good reading speed, enabling the memory in the claimed invention to read data both quickly and correctly. 
     In the prior art, to read data in the memory unit, it is required to first establish a voltage by injecting the data current generated from the memory unit into the load unit, and then the sensor unit determines the data condition according to the voltages. In the claimed invention, an enabled and a disabled load unit are added. 
     During the transient state of reading data from the memory unit, the load unit is enabled to enhance the current-driving ability and decrease the period of the transient state. When the transient state is finished, the load unit is disabled and a smaller aspect ratio load unit is instead used for establishing a final steady-state-voltage to achieve a better operating margin for the claimed invention. 
    
    
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a schematic diagram of a first prior art circuitry. 
     FIG. 2 is a graph of voltage versus time when the memory of FIG. 1 is reading data. 
     FIG. 3 is a schematic diagram of a second prior art circuit. 
     FIG. 4A is a graph of voltage versus time when the memory of FIG. 3 is reading data. 
     FIG. 4B is a graph of the relationship between the voltage and current of a load unit in FIG.  3 . 
     FIG. 5 is a schematic diagram of a memory circuit of the present invention. 
     FIG. 6 is a graph of voltage versus time when the memory showed of FIG. 5 is reading data. 
     FIG. 7 is a circuit schematic diagram of a sensor unit for an operation in the present invention memory circuit. 
     FIG. 8 is a circuit schematic diagram of a memory for an operation in the present invention. 
    
    
     DETAILED DESCRIPTION 
     Please refer to FIG. 5, which is a circuit schematic diagram of a memory  30  in according to the present invention. The memory  30  is DC biased by a voltage V dd , and utilizes a plurality of memory units  31 A and  31 B, on-load isolation units  32 A and  32 B, a MOS transistor Ml as a first load unit, a second load unit  36 A, a sensor unit SA, an equalizing unit  34 , a MOS transistor M 3  as a third load unit, a fourth load unit  36 B and a MOS transistor as a reference unit M 7 . The memory units  31 A and  31 B respectively store data into the MOS transistors Mm 1  and Mm 2  with floating gates. 
     The MOS transistors MA 1  and MA 2  control data accessing to the memory unit  31 A and  31 B, respectively. The gates of the MOS transistors Mm 1  and Mm 2  are controlled by the voltage biases Vm 1  and Vm 2 , respectively. The gates of the MOS transistors MA 1  and MA 2  are controlled by the voltage biases V A1  and V A2 , respectively. In the memory unit  31 A, the three electrodes of the MOS transistor MA 1 , besides the gate electrode, are connected respectively to the MOS transistor Mm 1  or the outputting data current end of the memory unit  31 A and connected to the node N 5  through the node Nd 1  and the on-load isolating unit  32 A. Similarly, one of the electrodes of the MOS transistor MA 2  connects to the MOS transistor Mm 2  and the other connects to the output end of the memory unit  31 B and the node N 5  through the node Nd 2 . The on-load isolating units  32 A and  32 B respectively control the gate electrodes of the MOS transistor M 5  and M 6  by inverters Iv 1  and Iv 2 . The gate of the MOS transistor M 7 , which serves as the reference unit, is controlled by the controlling voltage V c , and one of the electrodes is connected to the power V dd , and the other serves as a reference end, connecting to the on-load isolating unit  32 B at the node N 6 , to output the reference current I r  generated by the MOS transistor M 7 . The sensor unit SA is itself a differential sensor amplifier, having a first comparing end N 1 A and a second comparing unit N 2 c to generate a data signal V r  according to the voltage difference between the two comparing ends. The equalizing unit  34  forms a transmission gate with two MOS transistors Mta and Mtb, and controls the transmission gate by a controlling voltage V eq  and an inverter Iv 3 . When the transmission gate is on, it shorts the node N 1  to the node N 3 . On the other hand, when the transmission gate in the equalizing unit is off, the node N 1  and the node N 3  are not shorted. The MOS transistor M 1  serves as a first load unit, is diode-connected with two ends, with one of them connected to the sensor unit at the node N 11  and the other connected to ground G. Based on a similar implementation, the MOS transistor M 3  serves as the third load unit, is connected to the sensor unit SA at the node of N 3  on one side, and is grounded on the other side. 
     The main difference between the present invention and the prior art is that in addition to the first and the third load units in the present invention, a second load unit  36 A and a fourth load unit  36 B are utilized in this invention. The second load unit  36 A comprises MOS transistors Msa and M 2 . The MOS transistor Msa is a switching transistor, and the controlling voltage V eq  controls its gate electrode as well. The other two electrodes are connected to the MOS transistor Msa and to the sensor unit SA at the node of N 2 . The MOS transistor M 2  is diode-connected to be a load unit, and its source electrode is connected to the MOS transistor Msa. The fourth load unit  36 B utilizes MOS transistors Msb and M 4 . The MOS transistor Msb serves as a switching transistor, with its gate electrode controlled by the controlling voltage V eq , and the other ends connected to the diode-connected MOS transistor M 4  and to the sensor unit SA at the node N 4 . The MOS transistor M 4  is also a load unit, with its source electrode connected to the MOS transistor Msb. When the switch transistor Msa in the second load unit  36 A is turned on by the controlling voltage V eq , current is injected into the load transistor M 2  through the MOS transistor Msa, and the MOS M 2  establishes a voltage at the node N 2 . The second load unit  36 A is then enabled. If the controlling voltage V eq  turns off the switch transistor, the second load unit  36 A is disabled and the node N 2  isn&#39;t used for receiving current, and the node N 2  shows a high-impedance characteristic. The operations of the fourth load unit  36 B are similarly decided. 
     As in the prior art memory, the memory  30  stores electric charge corresponding to digital data in the floating gate. Under the same biases, a data current is different according to the different quantity of electric charge stored in the floating gate. According to the voltage that the data current has established on the load units, the sensor unit SA can read out the data stored in the memory unit. For example, when the memory  30  is about to read the data stored in the memory unit  31 A, the memory  30  turns on the MOS transistors Mm 1  and MA 1  in the memory unit  31 A by the controlling voltages Vm 1  and VA 1 , respectively. The MOS transistor Mm 1  generates a data current I f  according to the quantity of electric charge stored in the floating gate, and the current I f  is injected into the node N 5  through the turned-on transistor MA 1 . Meanwhile, the memory  30  turns off the MOS transistor MA 2  in the memory unit  31 B by way of the controlling voltage V A2 , so as to prevent interference while accesses the memory unit  31 A. 
     Please refer to FIG.  6  and FIG.  5 . FIG. 6 is a graph of voltage versus time for the first comparing end N 1 c and the second comparing end N 2 c when a read operation is in process. The X-axis represents the time domain, and the Y-axis represents voltage. The curves V(N 1 c)H and V(N 1 c)L represent the voltage of the first comparing end, and the curve V(N 2 c) represents the voltage of the second comparing end. Before the time point t 0 , when the read process has not yet begun, the first and second comparing ends N 1 c and N 2 c are charged to a high voltage level. At time t 0 , the memory unit  31 A begins to provide a data current I f , and the controlling voltage V c  turns on the MOS transistor M 7  to provide a reference current I r . At the same time, the controlling voltage V eq  turns on the transmission gate of the equalizing unit  34 , and thus shorts the node N 1  and N 3 . The MOS transistors Msa and Msb are also controlled by the controlling voltage V eq , and so are turned on to enable the second and the fourth on-load isolating units  36 A and  38 B. The controlling current flows into the load transistors M 2  and M 1 , through the load units  32 A and  32 B, and through the nodes N 1  and N 2 L. This is equivalent to adding discharging paths to accelerate the speed of lowering the voltages of the first and the second comparing ends N 1 c and N 2 c to a steady state, and the time region T 1  from time point t 0  to time point t 1  in FIG. 6 illustrates this condition. In the time region T 1 , the inverters Iv 1  and Iv 2  of the on-load isolating units  32 A and  32 B change the biases of the transistors M 5  and M 6 , which increases the equivalent impedances between the source and the drain electrodes of the two transistors MS, M 6 , and accelerates the transient state condition. At time point t 1 , the controlling voltage V eq  changes to turn off the transmission gate of the equalizing unit  34 , and the switch transistors Msa and Msb of the second and the fourth load units are simultaneously turned off to disable the two load units  36 A,  36 B. The data current I f  is thus no longer injected into the second load unit  36 A, but instead injects into the MOS transistor M 1  in the first load unit and establishes a steady-state-voltage V H  or V L  according to the level of the data current I f . Similarly, the reference current I r  is stopped from injecting into the fourth load unit  36 B, and instead only injects into the MOS transistor M 3  in the third load unit to establish a steady-state-reference-voltage V R . At the time point t 2 , the sensor unit SA determines the data stored into the memory unit  31 A according to the voltage difference between the first comparing end N 1 c and the second comparing end N 2 c and generates a corresponding data signal V r . 
     To sum up, the purpose of this invention is to provide two load units  36 A and  36 B during the transient state when reading data, and to thus shrink the time needed for transient state transitions. At the time when the steady-state is almost reached, the second and the fourth load units  36 A and  38 B are disabled, which then establishes a steady-state-voltage at the first comparing end N 1 c by way of the original load unit transistor M 1 . In operation, the MOS transistor M 1  of this invention is a low aspect ratio transistor, and the load unit M 2  is a higher aspect ratio transistor. Within the time region T 1 , the transistor m 2  provides a lower impedance discharging path (compared to the transistor M 1 ), and in combination with the discharging path provided by the transistor M 1 , makes the voltage of the first comparing end N 1 c decrease rapidly, and so reduces the period required for the transient state. At time point t 1 , time region T 2  is entered in which the second load unit  36 A is disabled so as to no longer drain current, and the. steady-state-voltage VH or V L  is completely established by way of the transistor M 1  according to the data current I f . As discussed above, a transistor with a lower aspect ratio generates a larger range for the steady-state-voltage, which enlarges the operating margin. Therefore, the present invention has the advantages of both accelerating the read process, and providing better operating margins. If the load transistor M 2  for the memory  30  of the present invention is the same as the load transistor Ta 1  of the prior art memory  20 , and similarly if the memory units and on-load isolating circuits are the same, then the curve V(N 1 b)L in FIG. 6 represents one of the voltage versus time curves of the first comparing end N 1 b of the memory  20 . It is clear that the transient state period in the present invention is shorter, and that the operating margin is significantly increased. 
     Please refer to FIG. 7, which is a circuit schematic diagram of a sensor unit SA in the memory  30  for a read operation in the present invention. In this operation, MOS transistors Q 1  and Q 2  are taken as a differential output pair, MOS transistors Q 3  and Q 4  are dynamic loads, and the MOS transistor Q 5  is a current source for bias, controlled by the controlling voltage V i . 
     Please refer to FIG. 8, which is a circuit schematic diagram of a memory  40  of a read operation in the present invention. Memory  40  utilizes memory units  41 A and  41 B, on-load isolating units  42 A and  42 B, an equalizing unit. 44 , a sensor unit SAb, MOS transistor QL 1  and QL 3  as a first and a third load unit, respectively; a second unit  46 A; a fourth unit  46 B, and a MOS transistor QL 7  as a reference unit. The controlling voltage Veq 2  controls the equalizing unit  44  and the second load unit  46 A and the fourth load unit  46 B. The main difference between the memory  30  and the memory  40  is that the memory  30  takes memory units as current sources and load units as current sinks. The memory  40  takes memory units as current sinks and load units as current sources. When the memory  40  is in the process of reading data, the memory  40  discharges the two ends of the sensor unit SAb to a low-voltage-level and charges them by the load units to a high-voltage-level. During the transient state that occurs while charging, the equalizing unit conducts so as to short the two comparing ends, and enables the second and the fourth load units to provide a low-impedance-path and so shrink the period of the transient state. Finally, the second and the fourth load units are disabled, since the equalizing unit  44  is switched off, and the load units transistors QL 1  and QL 3  instead establish the steady-state-voltage, allowing the sensor unit SAb to determine the data stored in the memory unit and output a corresponding data signal V r . The advantages of the memory  40  are identical to those indicated in the memory  30 . The spirit of the invention can be utilized in other types of non-volatile memory, or MOS devices with ONO gate electrodes. That is, all the transistors mentioned above can be other types of non-volatile memory, rather than simply transistors with floating gate electrodes. In addition, the p-type load transistors M 1  to M 4  can be n-type and diode-connected transistors; equally, the n-type transistors QL 1  and QL 3  in FIG.  8  and the load transistors of the load units  46 A and  46 B can be converted to p-type and diode-connected MOS devices, as shown in FIG.  5 . 
     In the prior art memory, only one load unit is implemented to provide a discharging path, preventing the prior art from simultaneously giving consideration to both reading speed and operating margins. In contrast, the memory of the present invention dynamically enables extra load units to speed up the discharging process. When a transient state is near completion, the extra load units are disabled and a lower aspect ratio transistor takes over to serve as the load unit to achieve the steady-state-voltage. A better operating margin is thereby achieved. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 6