Patent Abstract:
An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a divisional of application Ser. No. 11/499,381, filed Aug. 4, 2006, which is incorporated herein by reference in its entirety. 

   FIELD OF THE INVENTION 
   This invention relates to semiconductor chip fabrication and in particular to methods of fabricating and electrically isolating bipolar, CMOS and DMOS transistors and passive components in a semiconductor chip monolithically at high densities without the need for high temperature fabrication processing steps, and to provide ESD protection for such devices. 
   BACKGROUND OF THE INVENTION 
   In the fabrication of integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip, especially when these components operate at different voltages. Such complete electrical isolation is necessary to integrate certain types of transistors including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors including power DMOS transistors. Complete isolation is also needed to allow CMOS control circuitry to float to potentials well above the substrate potential during operation. Moreover, complete isolation allows the design of novel Electro-Static Discharge (ESD) protection devices. 
   Ability to survive an ESD event is one of the key requirements for ICs. A common method for providing such ESD protection is to include one or more ESD clamp devices that are connected across the external pins of an IC. More generally, the ESD devices are connected between the input terminals of, and thus in parallel with, the circuitry that is to be protected. These clamp devices are generally designed to break down at a voltage below that which would cause damage to the internal circuitry of the IC, thus absorbing the ESD energy and protecting the IC circuitry. The most commonly used ESD clamp devices are simple diodes, NPN bipolar transistors, and grounded-gate NMOS (GGNMOS) transistors, which are designed to operate in the bipolar snapback mode. 
     FIGS. 1A-1C  show two prior art ESD clamp devices. GGNMOS device  100  in  FIG. 1A  comprises a NMOS transistor  101  with drain (D) connected to input pad  102  and source (S) connected to ground pad  103 . The NMOS gate (G) is connected to source through a gate resistor  104 , with a value typically in the range of 1 kohm-100 kohm, and the NMOS body (B) is connected to source through internal body resistance  105  that is optimized to allow the GGNMOS to snapback due to parasitic NPN bipolar action at a reasonably low drain voltage. NPN ESD clamp device  110  in  FIG. 1B  comprises an NPN transistor  111  with collector (C) connected to input pad  112  and emitter (E) connected to ground pad  113 . The NPN base (B) is connected to emitter through internal base resistance  114  to allow the NPN to snapback due to BVcer at a reasonably low collector voltage. 
     FIG. 2  shows a cross-section schematic of prior art GGNMOS device  100  from  FIG. 1A . In this conventional, non-isolated CMOS process, P-well region  201 , which serves as the body of the NMOS, is formed in P-type substrate  202 . Therefore the body of this prior art GGNMOS is always connected to the substrate potential (“ground”). The device also includes N+ drain region  203 , N+ source regions  204 A and  204 B, P+ contact region  205 , lightly-doped drain (LDD) regions  206 , gate  207 , gate oxide  208 , sidewall spacers  209 , field oxide  210 , inter-level dielectric (ILD)  211 , and metal layer  212 . 
     FIG. 3  shows a cross-section schematic of prior art NPN ESD clamp device  110  from  FIG. 1B . In this conventional, non-isolated CMOS process, P-well region  301 , which serves as the base of the NPN, is formed in P-type substrate  302 . Therefore the body of this prior art NPN ESD clamp is always connected to the substrate potential (“ground”). The device also includes N+collector region  303 , N+ emitter regions  304 A and  304 B, P+ contact region  305 , field oxide  310 , ILD  311 , and metal layer  312 . 
   The breakdown or trigger voltage of ESD clamp devices is typically limited to less than 20V by the vertical breakdown of various junctions in a given process. ESD devices with higher trigger voltages generally rely on a lateral breakdown mechanism that is prone to current crowding, making it difficult to design large structures that effectively distribute the ESD energy. The use of series connected or “stacked” ESD clamp devices would allow the trigger voltages of a several ESD clamp devices to be added to achieve higher total trigger voltage, but this requires complete isolation of the ESD clamp devices. 
   Fabrication of conventional CMOS in P-type substrate material does not facilitate complete isolation of its devices since every P-type well forming the body (back-gate) of NMOS transistors is shorted to the substrate potential, typically the most negative on-chip potential. One method for achieving complete isolation is epitaxial junction-isolation, which employs an N-type epitaxial layer grown atop a P-type silicon substrate and separated into electrically isolated tubs by a deep P-type isolation diffusion—one requiring high temperature processes to implement. High temperature processing causes a redistribution of dopant atoms in the substrate and epitaxial layers, causing unwanted tradeoffs and compromises in the manufacturing of dissimilar devices fabricated using one common process. Moreover, the high-temperature diffusions and epitaxy employed in epi-JI processes are generally incompatible with the large wafer diameters and advanced low-temperature processing equipment common in submicron CMOS fabs. 
   What is needed is a process for integrating various IC devices with ESD protection devices that allows for the formation of stacked devices, yet eliminates the need for high temperature processing and epitaxy. Ideally, such a manufacturing process should employ “as-implanted” dopant profiles—ones where the final dopant profiles remain substantially unaltered from their original implanted profiles by any subsequent wafer processing steps. Moreover, the process should be constructed in a modular architecture where devices may be added or omitted and the corresponding process steps added or removed to the integrated flow without changing the other devices available in the process&#39;s device arsenal. 
   SUMMARY OF THE INVENTION 
   The clamping devices of this invention are formed within an isolated region of a substrate of a first conductivity type. The isolated region is bounded on the bottom by a deep implanted floor layer of a second conductivity type opposite to the first conductivity type and on the sides by one or more implanted wells of the second conductivity type that extend downward from the surface of the semiconductor material and merge with the deep implanted layer. In many embodiments the isolated region is bounded on the side by a single well that is formed in the shape of a closed figure—for example, a circle, rectangle or other polygon or some other shape. 
   A variety of ESD protection devices may be formed within the isolated region. For example, in one embodiment a bipolar transistor is formed in the isolated region, with its base connected to its emitter through a resistance such that a two-terminal device is formed. In another embodiment, a grounded-gate MOS device is formed with both its body region and its gate connected to its drain through respective resistances. 
   In yet another group of embodiments, a clamping diode is formed in the isolated region. The isolated device is formed in a P-type substrate and the floor isolation layer and the well(s) that surround the isolated region laterally are N-type. An N+ cathode region is formed at the surface of the isolated region and a P anode region is formed beneath the N+ cathode region. The P anode region may be formed by a succession of chained implants with the deeper implants having a higher doping concentration than the shallower implants. Alternatively, the anode and cathode may be formed by a series of parallel N-type and P-type regions within the isolated region. 
   The doped regions that constitute the isolation structure and the doped regions that constitute the ESD protection device are preferably formed by single or multiple implants with essentially no thermal processes that would result in the diffusion of the dopants. These doped regions therefore remain in an essentially “as-implanted” configuration. The process flow is modular in the sense that, with a few exceptions, the implants may be performed in virtually any order, and it is possible to eliminate one or more process steps in the fabrication of a given IC, depending on which set of devices are required. 
   The ESD protection devices are connected between the input terminals of the circuitry that is to be protected. Since the ESD protection devices are isolated from the substrate, they can be series connected or “stacked” such that the trigger voltages of a several ESD clamp devices are added together to achieve a higher effective trigger voltage in order to provide protection for high voltage circuits. 

   
     DESCRIPTION OF FIGURES 
       FIGS. 1A-1C  are schematic circuit diagrams of prior art ESD protection devices. 
       FIG. 2  is a cross-sectional view of a prior art GGNMOS ESD clamp device. 
       FIG. 3  is a cross-sectional view of a prior art NPN ESD clamp device. 
       FIGS. 4A-4D  are schematic circuit diagrams of stacked ESD protection devices. 
       FIG. 5  is a cross-sectional view of an isolated NPN ESD clamp device. 
       FIG. 6  is a cross-sectional view of an isolated GGNMOS ESD clamp device. 
       FIGS. 7A-7C  are cross-sectional views of an isolated ESD clamp diodes. 
       FIG. 8  is a cross-sectional view of a stacked ESD clamp structure. 
   

   DESCRIPTION OF THE INVENTION 
   An all low-temperature fabrication method using as-implanted junction isolation structures employs high-energy and chain implants with dopant implanted through contoured oxides to achieve fully-isolated bipolar, CMOS and DMOS devices without the need for isolation diffusions, epitaxy or high temperature processes. The low-temperature wafer fabrication methods and isolated device structures were previously described in pending U.S. application Ser. No. 11/298,075 and in U.S. Pat. Nos. 6,855,985, 6,900,091 and 6,943,426 to R. K. Williams et al., each of which is incorporated herein by reference. 
   The inventive matter in this application is related to these patents and applications but concentrates on the design and integration of isolated and stackable ESD protection structures. 
   The low-temperature fabrication of the high-voltage devices described in this application are compatible with the modular low-temperature fabrication methods described in the aforementioned applications, but are not necessarily limited to modular process architectures. 
   While specific embodiments of this invention have been described, it should be understood that these embodiments are illustrative only and not limiting. Many additional or alternative embodiments in accordance with the broad principles of this invention will be apparent to those of skill in the art. 
   Wafer Fabrication 
   Except as specifically stated, wafer fabrication of the devices described herein utilizes the same process sequence that is described in the above referenced patents. A brief summary of the basic process flow includes 
   Field oxide formation 
   High-energy implanted deep drift layer (ND) formation 
   High-energy implanted floor isolation (DN) formation 
   1 st  chain-implanted non-Gaussian N-well (NW 1 /NW 1 B) formation 
   1 st  chain-implanted non-Gaussian P-well (PW 1 /PW 1 B) formation 
   2 nd  chain-implanted non-Gaussian N-well (NW 2 /NW 2 B) formation 
   2 nd  chain-implanted non-Gaussian P-well (PW 2 /PW 2 B) formation 
   Dual gate oxide and gate electrode formation 
   N-base implant 
   P-base implant 
   1 st  N-LDD implant (NLDD 1 ) 
   1 st  P-LDD implant (PLDD 1 ) 
   2 nd  N-LDD implant (NLDD 2 ) 
   2 nd  P-LDD implant (PLDD 2 ) 
   ESD implant 
   Sidewall spacer formation 
   N+ implant 
   P+ implant 
   Rapid thermal anneal (RTA) implant activation 
   Multilayer metal interconnect process 
   Passivation 
   Since the process as described utilizes “as-implanted” dopant profiles with little or no dopant redistribution, implants may be performed in virtually any order except that it is preferred that the P-well and N-well implantation precede gate formation, the trench gate formation precede DMOS body implantation, N-LDD and P-LDD implants follow gate formation but precede sidewall spacer formation, and N+ and P+ implants follow sidewall spacer formation. This process flow is designed to be modular, so it is possible to eliminate one or more process steps in the fabrication of a given IC, depending on which set of devices are required for that IC design. 
   By way of example, the table below summarizes a preferred embodiment and a preferred range of conditions for the implants described in this application: 
   
     
       
             
             
             
           
         
             
                 
             
             
               Implant 
               Preferred Embodiment 
                 
             
             
               (Species) 
               (Energy, Dose) 
               Preferred Range (Energy, Dose) 
             
             
                 
             
           
           
             
               DN (P + ) 
               E = 2.0 MeV, Q = 2E13 cm −2   
               E = 1.0 MeV to 3.0 keV, Q = 1E12 to 1E14 cm −2   
             
             
               ND deep drift 
               E = 800 keV, Q = 2E12 cm −2   
               E = 400 keV to 1.2 MeV, Q = 5E11 to 5E12 cm −2   
             
             
               (P + ) 
               E = 600 keV, Q = 2E12 cm −2   
               E = 300 keV to 900 keV, Q = 5E11 to 5E12 cm −2   
             
             
               P-body (B + ) 
               E = 120 keV, Q = 2E12 cm −2   
               E = 60 keV to 180 keV, Q = 5E11 to 5E12 cm −2   
             
             
                 
               E = 80 keV, Q = 4E12 cm −2   
               E = 40 keV to 120 keV, Q = 1E12 to 1E13 cm −2   
             
             
               1st P-well + 
               E = 240 keV, Q = 1E13 cm −2   
               E = 120 keV to 360 keV, Q = 5E12 to 5E13 cm −2   
             
             
               (B + ) 
               E = 120 keV, Q = 6E12 cm −2   
               E = 60 keV to 180 keV, Q = 1E12 to 1E13 cm −2   
             
             
               1st N-well + 
               E = 460 keV, Q = 5E12 cm −2   
               E = 230 keV to 690 keV, Q = 1E12 to 1E13 cm −2   
             
             
               (P + ) 
               E = 160 keV, Q = 1E12 cm −2   
               E = 80 keV to 240 keV, Q = 5E11 to 5E12 cm −2   
             
             
               2nd P-well + 
               E = 460 keV, Q = 1E13 cm −2   
               E = 230 keV to 690 keV, Q = 5E12 to 5E13 cm −2   
             
             
               (B + ) 
               E = 160 keV, Q = 1E12 cm −2   
               E = 80 keV to 240 keV, Q = 5E11 to 5E12 cm −2   
             
             
               2nd N-well + 
               E = 950 keV, Q = 1E13 cm −2   
               E = 500 keV to 1.5 MeV, Q = 5E12 to 5E13 cm −2   
             
             
               (P + ) 
               E = 260 keV, Q = 1E12 cm −2   
               E = 130 keV to 390 keV, Q = 5E11 to 5E12 cm −2   
             
             
               N-base (P + ) 
               E = 300 keV, Q = 2E12 cm −2   
               E = 150 keV to 450 keV, Q = 5E11 to 5E12 cm −2   
             
             
                 
               E = 120 keV, Q = 9E12 cm −2   
               E = 60 keV to 180 keV, Q = 5E12 to 5E13 cm −2   
             
             
               P-base (B + ) 
               E = 240 keV, Q = 6E12 cm −2   
               E = 120 keV to 360 keV, Q = 1E12 to 1E13 cm −2   
             
             
                 
               E = 100 keV, Q = 6E12 cm −2   
               E = 50 keV to 150 keV, Q = 1E12 to 1E13 cm −2   
             
             
               NLDD1 (P + ) 
               E = 80 keV, Q = 2E13 cm −2   
               E = 40 keV to 160 keV, Q = 5E12 to 5E13 cm −2   
             
             
               PLDD1 (BF 2   + ) 
               E = 80 keV, Q = 2E12 cm −2   
               E = 40 keV to 160 keV, Q = 5E11 to 5E12 cm −2   
             
             
               NLDD2 (P + ) 
               E = 80 keV, Q = 6E12 cm −2   
               E = 40 keV to 160 keV, Q = 1E12 to 1E13 cm −2   
             
             
               PLDD2 (BF 2   + ) 
               E = 100 keV, Q = 3E12 cm −2   
               E = 50 keV to 150 keV, Q = 1E12 to 1E13 cm −2   
             
             
               NESD (P + ) 
               E = 40 keV, Q = 1E15 cm −2   
               E = 20 keV to 150 keV, Q = 1E14 to 5E15 cm −2   
             
             
               N+ (As + ) 
               E = 30 keV, Q = 5E15 cm −2   
               E = 20 keV to 60 keV, Q = 1E15 to 1E16 cm −2   
             
             
               P+ (BF 2   + ) 
               E = 30 keV, Q = 3E15 cm −2   
               E = 20 keV to 60 keV, Q = 1E15 to 1E16 cm −2   
             
             
                 
             
           
        
       
     
   
   Using this process architecture, a number of unique ESD protection devices may be fabricated and integrated into an IC in a modular fashion. These new ESD devices include isolated diodes, GGNMOS, and NPN devices. An important feature of these devices is the complete isolation provided by a high-energy implanted floor isolation layer (DN). Since these devices are isolated from the substrate, they can be series connected or “stacked” such that the trigger voltages of a several ESD clamp devices are added together to achieve a higher effective trigger voltage in order to provide protection for high voltage circuits. Stacking two devices that each have a 16V trigger voltage, for example, yields a combined trigger voltage of 32V, which may be suitable for protection of 30V circuitry. Formation of such stacked devices is simply not possible using prior art non-isolated CMOS processes, and while it is theoretically possible using epitaxial junction isolation techniques, the size of the ESD clamps would be prohibitive. Thus, the ESD devices of this invention are unique in their combination of isolation and cost-effectiveness. 
     FIGS. 4A-4D  show a circuit schematic of stacked ESD clamp structures  400 A- 400 D, respectively, each comprising a top ESD clamp  401  and a bottom ESD clamp  402  connected in series between an input pad  403  and a ground pad  404  and in parallel with a circuit  410  that is to be protected. Bottom ESD clamp  402  may be non-isolated (having a common terminal connected to the substrate) or isolated from the substrate. It may comprise any of several possible ESD clamp devices, including a GGNMOS as shown in  FIG. 4A , an NPN ESD clamp as shown in  FIGS. 4B and 4D , an ESD clamp diode as shown in  FIG. 4C , or other related devices. Top ESD clamp  401  is isolated from the substrate such that it can float to a high voltage and thus be stacked in series with bottom ESD clamp  402 . Top ESD clamp  401  may comprise any of several possible ESD clamp devices, including a GGNMOS, as shown in  FIG. 4A , an NPN ESD clamp as shown in  FIG. 4B , an ESD clamp diode as shown in  FIGS. 4C and 4D , or other related devices. The top and bottom ESD clamp devices may the same type, or different types of devices may be used for the top and bottom clamps, respectively. For example, an NPN ESD clamp may be used on the bottom and an isolated ESD clamp diode on the top, as shown in stacked ESD clamp structure  400 D in  FIG. 4D . 
     FIG. 5  shows a cross-sectional view of an isolated NPN ESD clamp  500 . An N+ collector  503  is separated from N+ emitters  504 A and  504 B by a significant distance, for example 10-100 um, to provide some ballasting resistance to distribute the ESD current uniformly. P+ base contacts  505 A and  505 B are spaced from the emitters  504 A and  504 B by a significant distance, for example 10-100 um, to provide some resistance between the base  501  and emitters  504 A and  504 B, which lowers the bipolar snapback voltage and allows easier triggering during an ESD event. An optional ESD implant  516  may be included adjacent the collector  503  to provide a lower trigger voltage (breakdown of the collector-base junction) for improved ESD protection. A trigger voltage of 16V, for example, may be used to provide protection of the 12V CMOS devices having a typical junction breakdown of 20V. The NPN ESD clamp  500  shown in  FIG. 5  also includes DN floor isolation layer  513  and N-type sidewall isolation regions  514 A and  514 B to provide complete isolation of the ESD clamp  500  from P-type substrate  502 . Active regions are separated by field oxide layer  510  and contacted by metallization layer  512  through contact holes in ILD  511 . Isolation (ISO) electrodes are connected to DN layer  513  via N+ contacts  515 A and  515 B. Depending on the bias conditions of the input pad, the ISO electrodes may be tied to the same potential as the collector  503 , the same potential as the base  501 , or some other potential defined in the IC. 
   Clamp  500  may be an annular device, with collector  503  at the center and each of emitters  504 A,  504 B, P+ base contacts  505 A,  505 B, and isolation regions  514 A,  514 B in an annular shape surrounding collector  503 . Note: As used herein, the term “annular” refers to a geometrical figure having an open center region whether the shape is circular, rectangular, hexagonal or some other shape. 
     FIG. 6  shows a cross-sectional view of an isolated GGNMOS ESD clamp  600 . P-well region  601 , which serves as the body of the NMOS  600 , is isolated from P-type substrate  202  by DN floor isolation layer  613  and N-type sidewall isolation regions  614 A and  614 B. The device also includes N+ drain region  603 , N+ source regions  604 A and  604 B, P+ body contact regions  605 A and  605 B, LDD regions  606 , gate  607 , gate oxide layer  608 , sidewall spacers  609 , field oxide layer  610 , ILD  611 , and metallization layer  612 . The metallization contact to N+ drain  603  is separated from the edges of gate  607  by a significant distance, for example 1-10 microns, to provide some ballasting resistance to distribute the ESD current uniformly among multi-fingered GGNMOS clamp devices. P+ body contacts  605 A and  605 B are spaced from the source regions  604 A and  604 B by a significant distance, for example 1-10 microns, to provide some resistance between the source regions  604 A and  604 B and the body  601 , which lowers the bipolar snapback voltage and allows easier triggering during an ESD event. An optional ESD implant  616  may be included adjacent the drain region to provide a lower trigger voltage (breakdown of the drain-body junction) for improved ESD protection. A trigger voltage of 9V, for example, may be used to provide protection of the 5V CMOS devices having a typical junction breakdown of 12V. Active regions are separated by field oxide layer  610  and contacted by metallization layer  612  through contact holes in ILD  611 . Isolation (ISO) electrodes are connected to DN  613  via N+ contact regions  615 A and  615 B. Depending on the bias conditions of the input pad, the ISO electrodes may be tied to the same potential as the drain  603 , the same potential as the body  601 , or some other potential defined in the IC. 
   Like device  500 , device  600  may be annular, with gate  607 , source regions  604 A,  604 B, body contacts  605 A,  605 B, and sidewall isolation regions  614 A,  614 B surrounding drain region  603 . 
     FIG. 7A  shows a cross-sectional view of an isolated ESD clamp diode  1100  comprising P-type region  1103  that is isolated from P-type substrate  1101  by high-energy implanted DN floor isolation layer  1102  and sidewall isolation N-wells  1105 A and  1105 B, which may be annular. N+ cathode  1106  extends across the semiconductor surface between LOCOS oxide regions  1108  and forms electrical contact with the floor isolation layer  1102  through its overlap onto N-wells  1105 A and  1105 B. The N+ cathode (K)  1106 , is contacted through ILD  1109  and electrically connected by metal layer  1111  through an optional barrier metal layer  1110 . P-body or P-base anode  1104  is contained within isolated P-type region  1103  and contacted by a P+ region (not shown) within the isolated P-type region  1103 . The contact is preferably formed in the dimension into the page, by interrupting the N+ cathode  1106  to insert the P+ region. Contact to non-isolated P-type substrate  1101  is facilitated by P+ regions  1107 A and  1107 B, which in a preferred embodiment form a ring circumscribing the diode  1100 . 
     FIG. 7B  shows a cross-sectional view of an isolated ESD clamp diode  1120  comprising P-type region  1131  that is isolated from P-type substrate  1121  by high-energy implanted DN floor isolation layer  1122  and sidewall isolation N-wells  1123 A and  1123 B, which may be annular. N+ cathode  1125  extends across the semiconductor surface between LOCOS oxide regions  1129  and forms electrical contact with the floor isolation layer  1122  through its overlap onto N-wells  1123 A and  1123 B. The N+ cathode (K)  1125 , is contacted through ILD  1130  and electrically connected by metal layer  1128  through optional barrier metal layer  1127 . P-well anode  1124  is contained within isolated P-type region  1131  and contacted by a P+ region (not shown) within the isolated P-type region  1131 . The contact is preferably formed in the dimension into the page, by interrupting the N+ cathode  1125  to insert the P+ region. Contact to non-isolated P-type substrate  1121  is facilitated by P+ regions  1126 A and  1126 B, which in a preferred embodiment form a ring circumscribing the diode  1120 . 
   Unlike a conventional diffused well which has its peak concentration near the surface and a monotonically decreasing concentration with increasing depth, P-well  1124  may be formed by a high energy ion implantation of boron, for example, and preferably by a boron chain-implant comprising a series of boron implants varying in dose and energy. The chain implant, while it may comprise any number of implants, is graphically represented in the drawing by two regions—a surface layer PW 1 , and a subsurface layer PW 1 B, formed by ion implantation through a single mask and without the use of epitaxy. In a preferred embodiment the deeper layer PW 1 B is more highly concentrated than the surface layer PW 1 . 
     FIG. 7C  shows a cross-section of an isolated ESD clamp diode  1140  comprising multiple parallel N-well to P-well junctions all contained in an isolated P-type region. Isolated P-wells  1144 A and  1144 B are contacted by P+ regions  1146 D and  1446 C, and N-wells  1143 A,  1143 B and  1143 C are contacted by N+ regions  1145 A,  1145 B, and  1145 C. The resulting diodes are isolated from P-type substrate  1141  by high energy implanted DN floor isolation layer  1142  and N-wells  1143 A and  1143 C. The device is circumscribed by LOCOS field oxide layer  1149  and P+ substrate ring  1146 A and  1146 B. The active areas are contacted through ILD  1150  by metal layer  1148  through optional barrier metal layer  1147 . 
   Unlike a conventional diffused wells which have peak concentrations near the surface and a monotonically decreasing concentration with increasing depth, the P-wells  1144 A and  1144 B, along with N-wells  1143 A,  1143 B and  1143 C, are formed by high energy ion implantation, and preferably by a chain-implant comprising a series of implants varying in dose and energy. While the chain implants may comprise any number of implant steps, they are graphically represented in the drawing by two regions—surface layers PW 1  and NW 1 , and a subsurface layers PW 1 B and NW 1 B. In a preferred embodiment the deeper layers NW 1 B and PW 1 B are more highly concentrated than the surface layers NW 1  and PW 1 , causing the breakdown of the Zener diodes to occur at a location well below the surface. 
   The various features shown in the isolated ESD clamp examples of  FIGS. 7A-7C  are illustrative of structures that are compatible with the disclosed process and capable of providing cost-effective, stacked ESD protection devices. It is well within the scope of this invention to combine the features from different figures to arrive at the best termination structure for a given implementation. For example, it is possible to add metal interconnect layers above the single metal layer shown, to substitute the LOCOS field oxide layers with alternative field dielectric schemes such as deposited and/or recessed field oxides. 
     FIG. 8  shows a cross-sectional view of a stacked ESD clamp structure comprising a top ESD clamp  801  and a bottom ESD clamp  802  connected in series. Electrical connections are illustrated schematically, showing the ESD clamps connected between an input pad  803  and a ground pad  804 . Bottom ESD clamp  802  is non-isolated (has a common terminal connected to substrate  805 ), while top ESD clamp  801  is isolated from substrate  805  by DN floor isolation layer  806  and N-type sidewall isolation regions  807 A and  807 B. 
   While specific embodiments of this invention have been described, these embodiments are illustrative only and not limiting. Persons of skill in the art will readily see that numerous alternative embodiments are possible in accordance with the broad principles of this invention.

Technology Classification (CPC): 7