Patent Abstract:
The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.

Full Description:
BACKGROUND OF THE RELATED ART  
         [0001]    Since the introduction of the first personal computer (“PC”), technological advances to make PCs more useful have continued at an amazing rate. Microprocessors that control PCs have become faster and faster, with operational speeds eclipsing the gigahertz (one billion operations per second) and continuing well beyond.  
           [0002]    Productivity has also increased tremendously because of the explosion in development of software applications. In the early days of the PC, people who could write their own programs were practically the only ones who could make productive use of their computers. Today, there are thousands of software applications ranging from games to word processors and from voice recognition to web browsers.  
           [0003]    Not surprisingly, the increasing complexity of computers and software applications has presented technologists with some challenging obstacles along the way. One such obstacle is the continual increase in the amount of computing power needed to run increasingly large and complex software applications. Increased computing power is also needed to enable networked computer systems to provide services such as file and printer sharing to larger numbers of users in a cost effective manner.  
           [0004]    One way to increase computing power has been to design computer systems that are capable of processing data faster. Computers may use clock signals to synchronize the processing of data. Bits of data in the form of electrical signals that represent “0s” and “1s” (logical lows and highs) may be clocked into integrated circuit devices, which may process the 0s and 1s to do useful work. Data signals may be passed through a data buffer circuit before being latched and stored in a device known as a register, which may also be known as a latch or flip-flop. A clock signal, which may be an electrical signal in the form of a square wave, may be used to latch data bits into the register. Registers are incorporated into an integrated circuit device to receive data bits and hold them for further processing by the internal workings of the integrated circuit device. The registers may be designed to receive a new data bit with each rising edge (or falling edge) of the clock signal. A rising edge of the clock occurs when the clock signal transitions from a relatively low level to a relatively high level. A falling clock edge occurs when the clock signal transitions from a relatively high level to a relatively low level.  
           [0005]    If the speed of the clock is increased, data is processed at a faster rate, with a corresponding increase in computing power. For example, if data bits are being clocked into data buffers for further processing on each rising edge of a system clock, twice as much data may be clocked into the registers if the clock rate is doubled. A potential problem may arise, however, because, as clock speed increases, there is less time during each clock cycle to perform work.  
           [0006]    One problem faced by designers of input buffer circuits as clock speeds increase is insufficient data setup time. Setup time refers to the length of time that a data signal should be stable to guarantee that it will be clocked into an input register by the relevant edge of a clock signal. Setup time is potentially a problem because electrical data signals transition rapidly and may take time to settle after a transition (for example a transition from a logical “0” to a logical “1” and vice versa). As clock speeds get faster, the time in which data signals have to stabilize or settle gets shorter. If a data signal is not stable when the relevant clock edge latches the signal into a register, the signal may be incorrectly interpreted. For example, a logical “0” may be mistakenly latched into the register as a logical “1” or vice versa. If data is incorrectly latched into a register, the performance of the computer system is degraded.  
           [0007]    Another factor that may affect the clocking of data into a register is the synchronization of the clock signal across multiple data inputs. In many integrated circuit devices, multiple data bits may be clocked in parallel into their respective registers by a single clock signal. Many factors may introduce small variations into the synchronization of the clock signal with respect to when each of the multiple data bits is latched into its register. One factor may be a difference in length that the clock signal has to travel to actuate the registers of different data inputs. Another factor may be that the registers that receive the data have differing voltages at which they are actuated by the clock signal. These differences may result from variations in integrated circuit processing or temperature, among others. A system that may reduce the effects of these variations may be desirable.  
         SUMMARY  
         [0008]    The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.  
           [0009]    Another embodiment is a computer system having at least one integrated circuit that includes a buffer circuit. The buffer circuit receives a data signal, a first clock signal and a second clock signal. The buffer circuit comprises circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.  
           [0010]    Yet another embodiment is a method of operating a buffer circuit that receives a data signal, a first clock signal and a second clock signal. The method comprises receiving a data signal, storing a first latched data signal using a first clock signal, storing a second latched data signal using a second clock signal, selecting the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    Advantages of the invention may become apparent upon reading the following detailed description and upon reference to the drawings in which:  
         [0012]    [0012]FIG. 1 is a block diagram illustrating a computer system in which embodiments of the present invention may be employed;  
         [0013]    [0013]FIG. 2 is a block diagram of an embodiment of a single-ended input buffer circuit in which the embodiments of the present invention may be employed;  
         [0014]    [0014]FIG. 3 is a block diagram of an input buffer circuit according to embodiments of the present invention; and  
         [0015]    [0015]FIG. 4 is a process flow diagram according to embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]    [0016]FIG. 1 is a block diagram illustrating a computer system in which embodiments of the present invention may be employed. A computer system is generally indicated by the numeral  100  and may comprise a processor complex  102  (which may include a plurality of central processing units (“CPUs”)). The computer system  100  may also include core logic  104  (or north bridge), system random access memory (“RAM”)  106 , a video graphics controller(s)  110 , a video display(s)  112 , a PCI/SCSI bus adapter  114 , a PCI/EISA/ISA bridge  116 , and a PCI/ATA controller  118 . Single or multilevel cache memory (not illustrated) may also be included in the computer system  100  according to the current art of microprocessor computer systems. Integrated circuit components that make up the processor complex  102 , the core logic  104 , the RAM  106 , for example, may include a plurality of data buffers and registers that are adapted to receive data via a clock or strobe signal.  
         [0017]    The processor complex  102  may be connected to the core logic  104  through a host bus  103 . The system RAM  106  is connected to the core logic  104  through a memory bus  105 . The video graphics controller(s)  110  is connected to the core logic  104  through an AGP bus  107  (or other bus for transporting video data). The PCI/SCSI bus adapter  114 , PCI/EISA/LPC bridge  116 , and PCI/ATA controller  1   18  is connected to the core logic  104  through a primary PCI bus  109 . Those of ordinary skill in the art will appreciate that a PCI-X bus or Infiniband bus is substituted for the primary PCI bus  109 .  
         [0018]    Also connected to the PCI bus  109  may be a network interface card (“NIC”)  122  and a PCI/PCI bridge  124 . Some of the PCI devices such as the NIC  122  and PCI/PCI bridge  124  may plug into PCI connectors on the computer system  100  motherboard (not illustrated). The PCI/PCI bridge  124  may provide an additional PCI bus  117 .  
         [0019]    Hard disk  130  and tape drive  132  may be connected to the PCI/SCSI bus adapter  114  through a SCSI bus  111 . The NIC  122  may be connected to a local area network  119 . The PCI/EISA/LPC bridge  116  may connect over an EISA or LPC bus  113  to a non-volatile random access memory (NVRAM)  142 , modem  120 , and input-output controller  126 . The NVRAM  142  may store the system BIOS and/or other programming and may include flash memory. Additionally, the NVRAM may be contained in a programmable logic array (“PAL”) or any other type of programmable non-volatile storage. The modem  120  may connect to a telephone line  121 . The input-output controller  126  may interface with a keyboard  146 , CD-ROM drive  144 , mouse  148 , floppy disk drive (“FDD”)  150 , serial/parallel ports  152 , and/or a real time clock (“RTC”)  154 .  
         [0020]    Many of the devices shown in FIG. 1 may be implemented as integrated circuit devices that employ buffer circuits according to embodiments of the present invention. The operation of buffer circuits is explained with reference to FIG. 2.  
         [0021]    [0021]FIG. 2 is a block diagram of an embodiment of a single-ended input buffer circuit in which embodiments of the present invention may be employed. The buffer circuit is generally identified by the reference numeral  200 . Single ended data signaling is typically used to minimize the number of wires and pins required for data transfer, with a concomitant reduction in the associated design cost.  
         [0022]    The buffer circuit  200  comprises a single-ended data buffer  202 , which is adapted to receive a data signal D 0 , and a single-ended data buffer  206 , which is adapted to receive a data signal D 1 . The data signal D 0  that may be delivered to the input buffer  202  is illustrated as a waveform  204 , which is shown as transitioning from a logical low level to a logical high level. The data signal D 1  that may be delivered to the input buffer  206  is illustrated as a waveform  208 , which is shown as transitioning from a logical high level to a logical low level. To correctly operate, the data buffers  202 ,  206  utilize data signals  204 ,  208  which are stable for a setup time, shown as tSU, prior to being latched. The imposition of the setup time tSU helps to ensure that the data presented to the data buffers  202 ,  206  is correctly received.  
         [0023]    A single-ended clock buffer  210  is adapted to receive a clock signal  212 , which may be a square wave. The clock buffer  210  is adapted to deliver the clock signal  212  to a register  214  and a register  216 . Transparent latches may be used instead of the registers  214 ,  216  depending on design considerations. The buffer circuit  200  may employ single-pumped, rising-clock-edge triggered signaling, double-pumped clock signaling designs, or any other appropriate clocking technology.  
         [0024]    For illustrative purposes, the clock signal  212  is used to clock data into the registers  214  and  216  on a rising edge, as illustrated by the clock signal  212 . The rising edge of the clock signal  212  is synchronized to occur after the end of the setup time tSU. This synchronization may help to ensure the valid data is clocked into the registers  214  and  216 . Data that is presented to the D input of the registers  214 ,  216  may be latched on the rising edge of the clock signal  212  and delivered to the Q output of the registers  214 ,  216  where it is retrieved for further processing by the internal workings of an integrated circuit device.  
         [0025]    The data buffers  202 ,  206  may have a threshold voltage, which is the voltage level at which the buffer recognizes the transition from a logical low to a logical high and vice versa. Variation in the threshold voltage may negatively impact setup time for the data signals  204 ,  208 . For example, if an input buffer has a higher-than-nominal threshold voltage, the buffer may tend to recognize a rising edge later (with respect to a buffer with a nominal threshold voltage). Similarly, the input buffer with the higher-than-nominal threshold voltage may also tend to recognize falling edges earlier as compared to an input buffer with a lower than nominal threshold voltage. Such variations in threshold voltages may open up timing ambiguity if a buffer recognizes such transitions in the data, and thus reduce setup timing margin. If the buffer has a single-ended clock buffer, the problem may be compounded by similar ambiguity in the timing of the clock or strobe. In such a case, embodiments of the present invention may be employed to advantage.  
         [0026]    [0026]FIG. 3 is a block diagram of an input buffer circuit according to embodiments of the present invention. The buffer circuit, which is generally identified by the reference numeral  300 , provides relatively improved clock timing. The buffer circuit  300  comprises a single-ended data buffer  302 , which is adapted to receive a data signal D 0 , and a single-ended data buffer  306 , which is adapted to receive a data signal D 1 . The data signal D 0  delivered to the input buffer  302  is illustrated as a waveform  304 , which is shown as transitioning from a logical low level to a logical high level. The data signal D 1  to the input buffer  306  is illustrated as a waveform  308 , which is shown as transitioning from a logical high level to a logical low level. To operate correctly, the data buffers  302 ,  306  employ data signals  304 ,  308  which are stable for a setup time, shown as tSU, prior to being latched. The imposition of the setup time tSU helps to ensure that the data presented to the data buffers  302 ,  306  is correctly received.  
         [0027]    The input buffer  302  delivers the data signal D 0  as an input to a pair of registers  328  and  330  via a signal path  318 . The input buffer  306  delivers the data signal D 1  as an input to a pair of registers  332  and  334  via a signal path  320 . As set forth below, the buffer circuit  300  is designed to select the output of the register pair for each data signal that will provide the most synchronized timing. In other words, the buffer circuit  300  selects the output of the registers  328  or  330  for further processing depending on which of the registers  328  or  330  will provide the best timing for the data signal D 0 . The data value stored by the register  328  may be referred to as a first latched signal and the data value stored by the register  330  may be referred to as a second latched signal. Similarly, the buffer circuit  300  selects the output of the registers  332  or  334  for further processing depending on which of the registers  332  or  334  will provide the best timing for the data signal D 1 . The data value stored by the register  332  may be referred to as a first latched signal and the data value stored by the register  334  may be referred to as a second latched signal.  
         [0028]    In the embodiment of FIG. 3, a single-ended clock buffer  310  is adapted to receive a clock high (CLK_H) signal  312 , which may be a square wave. For illustrative purposes, the clock high signal  312  is shown as transitioning from a low state to a high state. The clock buffer  310  may be adapted to deliver the clock high signal  312  to the register  328  and the register  332  via a signal path  322 . Transparent latches may be used instead of the registers  328 ,  332  depending on design considerations. The buffer circuit  300  may employ single-pumped, rising-clock-edge triggered signaling, double-pumped clock signaling designs, or any other appropriate clocking technology.  
         [0029]    A single-ended clock buffer  314  is adapted to receive a clock low (CLK_L) signal  316 , which may be a square wave. For illustrative purposes, the clock low signal  316  is shown as transitioning from a high state to a low state. The clock buffer  314  is adapted to deliver the clock low signal  316  to the register  330  and the register  334  via a signal path  324 . As illustrated in FIG. 3, the output of the clock buffer  314  is negated prior to being delivered as the clock signal to the registers  330 ,  334 . Transparent latches may be used instead of the registers  330 ,  334  depending on design considerations.  
         [0030]    The output of the clock buffers  310 ,  314  is delivered as inputs to a logic component  326 , which may be an OR gate. The clock low signal is negated before being delivered as the input to the logic component  326 . The output of the logic component  326  is used as a clock signal for a register  340  and a register  342  via a signal path  327 . The data input to the register  340  is provided as the output of a multiplexor  336 , and the data outputs of the registers  328 ,  330  are provided as inputs to the multiplexor  336 . The output of the register  340  is used to select which of the inputs of the multiplexor  336  is delivered as the input of the register  340  and also provided as the data to the internal workings of an integrated circuit component via a data path  344 . The output of the register  342  is used to select which of the inputs of the multiplexor  338  is delivered as the input of the register  342  and also provided as the data to the internal workings of an integrated circuit component via a data path  346 .  
         [0031]    The buffer circuit  300  exploits the fact that multiple receiving buffers implemented on the same IC wafer tend to have well-matched voltage activation thresholds. This may be true because buffers on the same integrated circuit device may share a common process, voltage, and temperature characteristics.  
         [0032]    In a system that employs single-ended clocking and enforces a setup time prior to an active edge transition of the clock or strobe, there may be two different scenarios. Either (1) the data transition and clock/strobe transition are both in the same direction (i.e. both rising or both falling), or (2) the data transition and clock/strobe transition are in opposite directions (i.e. one transition is rising and the other transition is falling). In case 1, uncertainty in the voltage thresholds of the data buffers tends to cancel each other out. For example, if the threshold voltage levels are lower than nominal and both signals are rising, then both the clock/strobe and data may tend to be recognized early, but their relative timing is not altered.  
         [0033]    The “canceling out” effect described with respect to case 1 may be effective if the edge rates of the data signals and clock/strobe signals are well matched to each other. Thus, the buffer circuit  300  may be well suited for use in connection with data busses on which the device sourcing the data also sources the clock or strobe. Performance may also be improved in cases in which the data signaling circuitry and clock circuitry has similar pad designs, topology, termination schemes, and board routing constraints.  
         [0034]    In case 2, uncertainty in the voltage thresholds of the data buffers tends to cause one signal transition to be recognized relatively early with respect to the other transition. For example, if the voltage threshold levels are lower than nominal with the data transition falling and the clock/strobe transition is rising, the data transition may be recognized late, while the clock/strobe transition may be recognized relatively early. This combination may reduce the amount of setup time at the input to an input buffer, potentially causing a timing violation and/or data corruption.  
         [0035]    The buffer circuit may reduce or eliminate the timing error that results from case 2 by helping to ensure that, if a given data bit transitions during any particular clock cycle, the data buffer that subsequently samples that data bit is clocked from a single-ended clock/strobe signal that is switching in the same direction as the transition in the data bit. In cases where a data bit does not transition in a given clock cycle, the polarity of the clock/strobe signal that samples it is immaterial.  
         [0036]    In the buffer circuit  300 , the data signals D 0  ( 304 ) and D 1  ( 308 ) may be received, respectively, by the input buffers  302  and  308 . The data signals are then each clocked into two different registers, one of which is controlled by the clock high signal  312  and the other of which is controlled by the clock low signal  316 . As shown in FIG. 3, the data signal D 0  ( 304 ) is clocked into the register  328  by the clock high signal  312  via the signal path  322 . The data signal D 0  ( 304 ) is also clocked into the register  330  by the clock low signal  316  via the signal path  324 . Similarly, the data signal D 1  ( 308 ) is clocked into the register  332  by the clock high signal  312  via the signal path  322 . The data signal D 1  ( 308 ) is also clocked into the register  334  by the clock low signal  316  via the signal path  324 . Thus, each of the data signals D 0  and D 1  is clocked into a first register by a rising edge clock transition (clock high signal  312 ) and into a second register by a falling edge clock transition (clock low signal  316 ).  
         [0037]    If the logical value of a data signal (e.g. the data signals D 0  or D 1 ) does not transition between two successive active clock edges (i.e., the value of the data signal stays at the same logical level for two clock active edge transitions instead of either transitioning from a logical low to a logical high or vice versa), then it may be immaterial for timing purposes whether the data is sampled by the clock signal with a falling edge transition (clock low signal  316 ) or a rising edge transition (clock high signal  312 ). This is true because the data signal being sampled has virtually an entire clock cycle of setup time since it does not transition in the interim. In such a case, the setup time tSU is easily met.  
         [0038]    If the logical value of one of the data signals does transition (e.g. from a logical low to a logical high or vice versa) in a given clock cycle, the data may be sampled by two registers close to simultaneously. One register may sample the data based on the rising clock high signal  312 , and the other register may sample the data based on the falling clock low signal  316 . Whichever of the clock signals switches the same direction as the data (i.e. high to low or low-to-high) is deemed to be more reliable. The data sampled by the other clock signal may be untrustworthy and possibly metastable. The buffer circuit  300  helps to ensure that the data sample that is actually sampled by the associated integrated circuit is the data that is sampled by the clock signal that transitions in the same direction as the data in cases where the data has transitioned since the previous active clock edge.  
         [0039]    The multiplexor  336  receives both data samples of the data signal D 0    304  via the registers  328  and  330 . The register  328  delivers the sample that is obtained on the rising edge of the clock high signal  312  and the register  330  delivers the sample that is obtained on the falling edge of the clock low signal  316 . Similarly, the multiplexor  338  receives both data samples of the data signal D 1    308  via the registers  332  and  334 . The register  332  delivers the sample that is obtained on the rising edge of the clock high signal  312  and the register  334  delivers the sample that is obtained on the falling edge of the clock low signal  316 .  
         [0040]    The register  340  controls which data sample is selected from the multiplexor  336  and the register  342  controls which data sample is selected from the multiplexor  338 . The buffer circuit  300  is designed in such a way that the registers  340  and  342  select the multiplexor input that corresponds to the data that is sampled by the clock signal that transitions in the same direction as the corresponding data signal. To accomplish this, the register  340  and the register  342  store the data from the corresponding clock cycle for comparison. Specifically, the register  340  stores the data symbol or value that the data signal D 0  represented at the previous active clock transition and the register  342  stores the data symbol or value that the data signal D 1  represented at the previous active clock transition. Moreover, the registers  340  and  342  comprise circuitry that stores a value corresponding to the respective data signals in a previous clock cycle. Those stored values are then used to select between the first latched signal and the second latched signal for each data input.  
         [0041]    The Q output of the register  340 , which may correspond to the data symbol or value from the previous active clock transition, selects the input of the multiplexor  336  that corresponds to the data sample clocked by the rising clock edge of the clock high signal  312  if the data symbol or value of the data signal Do  304  transitioned from a logical low level to a logical high level. The Q output of the register  340  selects the input of the multiplexor  336  that corresponds to the data sample clocked by the falling clock edge of the clock low signal  316  if the data symbol or value of the data signal D 0    304  transitioned from a logical high level to a logical low level. If the data symbol or value of the data signal D 0    304  does not transition between active clock edges, the multiplexor output selected by the register  340  is irrelevant for timing purposes. The output of the multiplexor  336  may be delivered to the internal workings of an integrated circuit device for further processing via a signal path  344 .  
         [0042]    The Q output of the register  342 , which may correspond to the data symbol or value from the previous active clock transition, selects the input of the multiplexor  338  that corresponds to the data sample clocked by the rising clock edge of the clock high signal  312  if the data symbol or value of the data signal D 1    308  transitioned from a logical low level to a logical high level. The output of the register  342  selects the input of the multiplexor  338  that corresponds to the data sample clocked by the falling clock edge of the clock low signal  316  if the data symbol or value of the data signal D 1    308  transitioned from a logical high level to a logical low level. If the data symbol or value of the data signal D 1    308  does not transition between active clock edges, the multiplexor output selected by the register  342  is irrelevant for timing purposes. The output of the multiplexor  338  may be delivered to the internal workings of an integrated circuit device for further processing via a signal path  346 .  
         [0043]    The logic component  326  may help to ensure correct operation of the buffer circuit  300 . A possible design consideration is meeting a hold time at the input of the register  340  and the register  342 . Skew between the rising clock high signal  312  and the falling clock low signal  316  could potentially cause hold time violations at the input of the register  340  or the register  342 , if those registers were clocked by the clock high signal  312  or the clock low signal  316 . The logic component  326 , which receives both the clock high signal  312  and the negation of the clock low signal  316 , helps to ensure that the registers  340  and  342  recognize only the earlier of the two clock signals.  
         [0044]    Ideally, the drivers and terminators driving a bus are symmetrical, with rising and falling edges having the same clock-to-output delay and slew rate. In practice there are several factors that may tend to make rising and falling edges have unequal timings and edge rates. Some of those factors may include:  
         [0045]    1. Difficulty sizing positive field effect transistors (“PFETs”) and negative field effect transistors (“NFETs”)for identical drive characteristics.  
         [0046]    2. Asymmetries in termination (e.g., in busses requiring pull-ups).  
         [0047]    3. Asymmetries in ground/power pin counts in driving chip.  
         [0048]    4. Asymmetrical ground bounce because more lines switch one way than the other in any given clock cycle.  
         [0049]    Each of these factors may tend to give rising and falling edges unequal delays and edge rates. Each of these factors may also tend to effect multiple simultaneously same-direction switching signals identically. By sampling rising data lines with rising clock/strobes, and falling data lines with falling clock/strobes, the buffer circuit  300  may also reduce the setup time margin degradation associated with each of these effects.  
         [0050]    [0050]FIG. 4 is a process flow diagram according to embodiments of the present techniques. The process is generally referred to by the reference numeral  400 . At block  402 , the process begins. At block  404 , a data signal is received by an input buffer circuit such as the buffer circuit  300  (FIG. 3).  
         [0051]    The data signal is clocked by two separate clock signals as set forth at block  406 . The first and second clock signals may transition in opposite directions, as do the clock high signal  312  and the clock low signal  316  (FIG. 3). If the data signal transitioned in the same direction as the first clock signal (block  410 ), then the data is latched by the first clock signal, as shown at block  416 . If the data signal transitioned in the same direction as the second clock signal (block  412 ), then the data is latched by the second clock signal, as shown at block  414 . If the data signal does not transition (i.e. the data remains at the same value for successive clock cycles), the data signal may be latched by either the first or second clock signal without significantly impacting timing synchronization (block  408 ). At block  418 , the process ends.

Technology Classification (CPC): 7