Patent Abstract:
Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PET data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PET data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Full Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation and claims the benefit of the filing date of an application entitled, “Kernel Memory Locking for Systems that. Allow Over-Commitment Memory” Ser. No. 13/299,463, filed Nov. 18, 2011, assigned to the assignee of the present application, and herein incorporated by reference. 
     
    
     FIELD OF DISCLOSURE 
       [0002]    The claimed subject matter relates generally to computing systems and, more specifically, to techniques for the allocation of real memory in conjunction with memory paging. 
       SUMMARY 
       [0003]    Provided are techniques for the controlling of memory paging, in systems that allow over-commitment of real-memory. Over two decades ago, kernel memory has been configured as pageable so that particular operating systems (OSs), such the AIX OS published by the IBM Corporation of Armonk, N.Y., could work in small memory systems. In such systems, kernel data structures may be paged out to a paging space on a secondary computer-readable storage medium (CRSM) in a manner similar to the paging of user-space data. 
         [0004]    In a system in which there is a single logical partition (LPAR) some kernel data structures may he pinned, or locked, in memory. In a simple kernel locking system, a least recently used (LRU) deamon cannot page out selected, or “pinned,” kernel memory. Some kernel locking, systems employ “klock” pages, or kernel locked pages, which may include pages of some kernel extensions or kernel pages/kernel data/kernel stack. pages. In Wok page systems, user memory is paged out first and kernel memory is only paged out in the event there is no available user memory. One advantage of klock paging systems is that the chance of a server crash due to a memory fault is reduced. 
         [0005]    In systems that permit multiple LPARs, Active Memory Sharing (AMS) relay be implemented. To handle a potential over commitment of memory, a hypervisor creates logical memory for each LPAR. When using logical memory, a system&#39;s real memory may become over committed. For example, in a system with twenty Gigabytes (20 GB) of memory, that may be three (3) LPARs, each with an allocation of eight (8) GB for a total of twenty-four (24) GB. In the event a hypervisor detects a need for memory, the hypervisor may page a particular LPAR&#39;s logical memory to a CRSM designated for the particular LPAR. In such a scenario, kernel locking may not he effective. 
         [0006]    Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a first data structure associated with to first page of the logical memory, wherein the first data structure comprises a first field indicating that the corresponding first page is a klock page; generating a second data structure corresponding to the first data structure and associated with a second page of the logical memory, wherein the second data structure comprises a field corresponding to the first field indicating that the second page is a non-klock page; allocating, by a hypervisor, physical memory corresponding to the first page and the second page; and prioritizing, by the hypervisor, the physical memory corresponding to the first page and the second page with respect to the klock/non-klock fields in the first and second data structures. 
         [0007]    This summary is not intended as a comprehensive description of the claimed subject matter hut, rather, is intended to provide a brief overview of some of the functionality associated therewith. Other systems, methods, functionality, features and advantages of the claimed subject matter will he or will become apparent to one with skill in the art upon examination of the following figures and detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    A better understanding of the claimed subject matter can be obtained when the following, detailed description of the disclosed embodiments is considered in conjunction with the following figures, in which: 
           [0009]      FIG. 1  is a block diagram of a computing system architecture that may implement the claimed subject matter. 
           [0010]      FIG. 2  is a block diagram of memory elements, first introduced in  FIG. 1 , in more detail. 
           [0011]      FIG. 3  is one example of a software page frame table (S/W PFT) data structure that may he used in one embodiment of the claimed subject matter. 
           [0012]      FIG. 4  is a flowchart showing one example of a Setup Memory process in accordance with the claimed subject matter. 
           [0013]      FIG. 5  is a flowchart showing an example of an Access Page process in accordance with the claimed subject matter. 
           [0014]      FIG. 6  is a flowchart showing additional aspects of Access Page process first introduced in  FIG. 5 . 
           [0015]      FIG. 7  is a flowchart of showing one example of a Swap Memory process in accordance with the claimed subject matter. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally he referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. 
         [0017]    Any combination of one or more computer readable medium(s) may he utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. 
         [0018]    A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may he any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. 
         [0019]    Program code embodied on a. computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. 
         [0020]    Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user&#39;s computer, partly on the user&#39;s computer, as a stand-alone software package, partly on the user&#39;s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user&#39;s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). 
         [0021]    Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can he implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
         [0022]    These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. 
         [0023]    The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational actions to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
         [0024]    As the Inventors herein have realized, one disadvantage of pageable kernel memory is that performance may be inhibited in systems that enough memory to prevent memory paging. Another disadvantage of kernel paging is an inflated need for paging space because paging space used for kernel paging is typically not freed up for other uses. Another disadvantage is an inherent time latency required to resolve kernel page faults. Time latency may be a problem for some real-time processes such as a heart heat daemon. 
         [0025]    Turning now in the figures,  FIG. 1  is a block diagram of one example of a computing system architecture  100  that may incorporate the claimed subject matter. A computing system  102  includes a central processing unit (CPU)  104 , coupled to a monitor  106 , a keyboard  108  and a pointing device, or “mouse,”  110 , which together facilitate human interaction with computing system  100  and client system  102 . Also included in client system  102  and attached to CPU  104  are computer-readable storage mediums (CRSMs), specifically a CRSM_ 0   120 , a CRSM_ 1   121 , CRSM_ 2   122  and a CRSM_ 3   123 . Each of CRSMs  120 - 123  may either be incorporated into client system  102  i.e. an internal device, or attached externally to CPU  104  by means of various, commonly available connection devices such as but not limited to, a universal serial bus (USB) port (not shown). 
         [0026]    CRSM_ 0   120  is illustrated storing as number of logical partitions, or LPARs, i.e. a LPAR_ 1   111 , a LPAR_ 2   112  and a LPAR_ 3   113 , a logical memory  114 , a hypervisor (HYPR)  116  and a shared memory pool (SMP), or real memory,  118 . As should be familiar to one with skill in the relevant arts, each of LPAR  111 - 113  may implement a different operating system (OS) such that multiple OSs (not shown) are able to run concurrently on computing system  102 . The implementation and coordination of LPARs  111 - 113 , logical memory  114 . HYPR  116  and SMP  118  are explained in more detail below in conjunction with  FIGS. 2-7 . 
         [0027]    Computing system  102  is also coupled to the Internet  130 , which is in turn coupled to two (2) servers, i.e. a server  132  and a server  134 . Although in this example, computing system  102  and servers  132  and  134  are communicatively coupled via the Internet  130 , they could also be coupled through any number of communication mediums such as, but not limited to, a local area network (LAN) (not shown). Servers  132  and  134  are used as examples of resources that mat he available to computing system  102  and may include, but are not limited to, email servers and storage servers. It should he noted that a typical computing system would typically include many addition elements, but for the sake of simplicity only a few are shown. 
         [0028]      FIG. 2  is a block diagram of memory elements, first introduced in FIG,  1 , in more detail. Like  FIG. 1 , included in  FIG. 2  are LPARs  111 - 113 , logical memory  114 , shared memory pool  118  and CRSMs  120 - 123 . in this example, LPAR_ 1   121  is mapped to a section, i.e. LPAR_ 1  logical memory (LM)  131 , of logical memory  114  that includes a block of free system memory, i.e. Free_ 1   141 , an area of kernel data, i.e. klock_ 1   151 , and an area of locked data, i.e. a pinned_ 1   161 . Memory such as free —    1   141  is able to be employed by LPAR_ 1   111  for data that may be freely paged in and out of, in this example. CRSM_ 1   121 . Klock_ 1   151  is data that LPAR 1 — 111  has indicated should preferably not be paged in and out of memory such as CRSM  121 . Pinned_ 1   151  is typically stored kernel memory that may not be paged in and out of memory such as CRSM  121  because of adverse impacts upon some processes such as, but not limited to, heartbeat and other real time processes. 
         [0029]    Like LAPR  111 , LPAR_ 2   112  is mapped to a section, i.e. LPAR_ 2  LM  132  of logical memory  114 , i.e. a free_ 2   142 , a klock_ 2   152  and as pinned_ 2   162 , which serve the same functions for LPAR 1   112  as free_ 1   141 , klock_ 1   151  and pinned_ 1   161  server for LAPR_ 1   111 . in a similar fashion, LPAR_ 3   113  is mapped to a section, i.e. LPAR_ 3  LM  133 , of logical memory  114 , i.e. a free_ 3   143 , a klock_ 3   153  and a pinned_ 3   163 . In this example, each of LPAR_ 1  LM  131 , LAPR_ 2  LM  132  and LPAR_ 3  LM  133  are eight megabytes (8 MB) in size for a total of twenty-four megabytes (24 MB) of memory for logical memory  114 . 
         [0030]    In this example, LPAR LMs  131 - 133  are mapped to physical memory, or shared memory pool  118 . LPAR_ 1   131  is mapped to LPAR_ 1  PM  171 , LPAR_ 2  LM  132  is mapped to LPAR_ 2  PM  172  and LPAR_ 2  LM  133  is mapped to LPAR_ 3  PM  173 . LPAR_ 1  PM  171  is four megabytes (4 MB) in size, LPAR_ 2  PM  172  is eight megabytes 8 MB) in size and LPAR_ 3  PM  173  is eight megabytes (1 MB) in size for a total of twenty megabytes (20 MB) of memory for shared memory pool  118 . Since LPAR_ 2   112  and LPAR_ 3   113 , each with 8 MB of logical memory  114 , are mapped to a total of 16 MB of physical memory  118 , there is no need to page memory into either CRSM_ 2   122  or CRSM_ 3   123 , respectively. However, since LPAR_ 1   111 , with 8 MB of logical memory, is mapped to only 4 MB of physical memory  118 , i.e. LPAR_ 1  PM  171 , there is a likelihood that memory may need to he paged in and out of CRSM_ 1   121 . 
         [0031]    Also illustrated in  FIG. 2  are an operating system (OS) page table  176  and a hypervisor (HYPR) page table  178 . OS page table  176  stores information for controlling the mapping of LPAR_ 1   111 , LPAR_ 2   112  and LPAR_ 2   113  to LPAR_ 1  LM  131 , LPAR_ 2  LM  132  and LPAR_ 3  LM  133 , respectively. HYPR page table  178  stored information for controlling the mapping of LPAR_ 1  LM  131 , LPAR_ 2  LM  132  and LPAR_ 2  LM  133  to LPAR_ 1  PM  171 , LPAR_ 2  PM  172  and LPAR_ 3  PM  173 , respectively. 
         [0032]    A virtual input/output server (MS)  180  controls memory tasks for hypervisor  114  ( FIG. 1 ). A dotted line to and from VIOS  180  indicated that VIOS  180  may use virtual memory devices that are implemented as physical devices such as CRSMs  121 - 123 . it should be understood that the memory mappings shown in  FIG. 2  are for illustrative purposes only and that one with skill in the relevant arts will appreciate that many different mappings are possible. 
         [0033]      FIG. 3  is one example of a software page frame table data structure (S/W PET)  200  that may he used in one embodiment of the claimed subject matter. S/W PET  200  is named “struct_pft_swbits”  202 . S/W PET  200  includes six (6) one bit elements, specifically an unsigned bit  205 , entitled “unsigned_inuse,” an unsigned bit  206 , entitled “unsigned_pageout,” an unsigned bit  207 , entitled “unsigned_pagein,” an unsigned bit  208 , entitled “unsigned_free,” an unsigned bit  209 , entitled “unsigned_slist” and an unsigned bit  210 , entitled “unsigned_klock.” Each of data elements  205 - 210  are defined as initialized to a value of ‘1’. A comment  204  indicates that a first four bits  205 - 208  of S/W PET  200  store information related the states of a data frame to which data S/W PET  200  is associated. The use of data elements  205 - 209  should be familiar to those with skill in the relevant arts. The use of unsigned_klock  210  is explained in more detail below in conjunction with FIGS,  4 - 7 . 
         [0034]      FIG. 4  is a flowchart showing one example of a Setup Memory process  300  in accordance with the claimed subject matter. In this example, logic associated with process  300  is stored in CRSM_ 0   120  ( FIG. 1 ) and executed on one or more processors (not shown) of computing system  102  ( FIG. 1 ) in conjunction with a logical partition such as LPARs  111 - 113  ( FIGS. 1 and 2 ). In his description, LPAR ——   1   111  is used as an example. 
         [0035]    Process  300  starts in a “Begin Setup Memory” block  302  and proceeds immediately to an “Determine Memory Requirements” block  304 . During processing associated with block  304 , LPAR_ 1   111  determines the amount of memory required, which in this example is represented by LPAR_ 1  LM  131  and is 8 GB. As should he understood by one with skill in the relevant arts, the memory determined to be required during processing associated with block  304  is made up of a number of frames, or pages, with the specific number dependent upon the size of the needed memory. During processing associated with an “Initialize S/W PFT” block  306 , a S/W PWT (see  200 ,  FIG. 3 ) is initialized for each frame of memory determined to be needed. Although most fields in each S/W PWT should be familiar to one with skill in the relevant arts, unsigned klock  210  ( FIG. 3 ) is novel and is set according to the locking status of the corresponding frame requested. For example, if the requested frame is intended to be a kernel page unsigned_klock is set to a value of 1 and, otherwise set to a value of ‘0’. In this example, all kernel pages are implicitly klock pages. 
         [0036]    During processing associated with a “Transmit Request to Hypervisor (HYPR)” block  308 , a memory request, with the corresponding S/W PFT structures are transmitted to HYPR  116 . LPAR_ 1   111  then waits for an acknowledgment from HYPR  116  during processing associated with a “Ack Received?” block  310 . If during processing associated with block  310 , an acknowledgment is received from HYPR  116 , control proceeds to a “Return Success” block  312  in which LPAR_ 1111  is notified of a successful allocation of memory, which in this example would be LPAR_ 1   131  ( FIG. 2 ), mapped to LPAR_ 1  PM  171  ( FIG. 2 ). It should be noted that each frame of LPAR_ 1   131  is associated with a S/W PFT with the field unsigned block  210  set to a value of 1 if the frame is one in Klock_ 151  ( FIG. 2 ). 
         [0037]    If during processing associated with block  310 , a determination is made that an acknowledgement from HYPR  116  has not been received, either because of an explicit failure message from HYPR  116  or because of a timeout, control proceeds to a “Throw Exception” block  314 . During processing associated with block  314 , appropriate measures are taken to deal with a memory allocation issue, including notifying LPAR_ 111  of the failure. Finally, control proceeds to an “End Setup Memory” block  319  during which process  300  is complete. 
         [0038]      FIG. 5  is a flowchart showing an example of an Access Page process  350  in accordance with the claimed subject matter. Like process  300 , in this example, logic associated with process  350  is stored. in CRSM_ 0   120  ( FIG. 1 ) and executed on one or more processors (not shown) of computing system  102  ( FIG. 1 ). 
         [0039]    Process  350  starts in a “Begin Access Page” block  352  and proceeds immediately to a “Receive Page Request” block  354 . In this example, during processing associated with block  354 . LPAR _ 1   111  ( FIGS. 1 and 2 ) receives a request for a particular page in memory. During processing associated with a “Page in LPAR logical memory (LM)?” block  356 , a determination is made as to whether or not the page requested During processing associated with block  354  is located in LPAR_ 1  LM  131 . If not, during processing associated with a “Page in VIOS Paging Space for Partition (PSP)?” block  358 . a determination is made as to whether or not the requested page is located in a PSP controlled by VIOS  180  ( FIG. 2 ), or in other words, in a CRSM corresponding to the LAPR, i.e. CRSM_ 1   121  ( FIGS. 1 and 2 ) corresponding to LPAR_ 1   111 , If a determination is made that the requested page is not in PSP controlled by VIOS  180 , a page fault is signaled during processing associated with a “Page Fault” block  360 . 
         [0040]    During processing associated with a “Page in LPAR Swap Space?” block  364 , a determination is made as to whether or not the requested page is located in the swap space of LPAR_ 1   111 , which in this example is CRSM_ 0   120 . if the page requested during processing associated with block  354  is determined to be located in LPAR_ 1  LM  131  during processing associated with block  356 , in PSP controlled by VIOS  180  during processing associated with block  358  or in LPAR swap space during processing associated with block  364 , control proceeds to an “Access Page” block  366  during which the requested page is access, or retrieved from the corresponding memory. During processing associated with an “Access Successful?” block  368 , a determination is made as to whether or not the access of the requested page during processing associated with block  366  was successful.  11  so, control proceeds to a transition point A (see  FIG. 6 ). If not, control proceeds to a “Throw Exception” block  370  and then to transition point A. During processing associated with block  370 , appropriate actions are taken to indicate to LPAR_ 1   111  that the page was not able to be accessed. 
         [0041]    If the page is not located in LPAR swap space during processing associated with block  364 , control proceeds to a “Free AMS Memory?” block  372 . During processing associated with block  372 , a determination is made as to whether or not there is memory available in shared memory pool  118  ( FIG. 2 ). If not control proceeds to a Transition Point. B (see  FIG. 6 ). If so, control proceeds to a “Get Page” block  374 . During processing associated with block  374 , the page of memory requested during processing associated with block  354  is loaded into the available space in shared memory pool  118 . During processing associated with an “Access Page” block  376  the page loaded during processing with block  374  is accessed. Control proceeds to Access Successful? block  368  and processing continues as describe above. Processing continues via either Transition Point A or B as described below in conjunction with  FIG. 6 . 
         [0042]      FIG. 6  is a flowchart showing further processing  380  associated with Access Page process  350  ( FIG. 5 ). Process  380  is entered via either Transition Point A or B (see  FIG. 5 ). Via. Transition point B. control proceeds to a “Within Logical Memory (EM) Limit?” block  382 . During processing associated with block  382 , it determination is made as to whether or not the memory requested during processing associated with block  354  (see  FIG. 5 ) is within the limits of LPAR_LM  131  ( FIG. 2 ) of LPAR_ 1   111  ( FIGS. 1 and 2 ), which in this example is eight Gigabytes (8 GB). If so, control proceeds to a. “Swap Out Pages From AMS” block  384 . During processing associated with block  384 , pages from LPAR_ 1  PM  171  ( FIGS. 1 and 2 ) are swapped out to CRSM_ 1   121  ( FIGS. 1 and 2 ). Pages are swapped out in accordance with the disclosed technology (see  FIG. 7 ). i.e. non-klock pages are swapped before any klock pages. The claimed technology provides this feature with respect to HYPR  116  ( FIG. 1 ), a feature that is not provided by the prior art. 
         [0043]    If during processing associated with block  382 , a determination is made that the memory requested is not within the limits of LPAR_ 1  LM  131 , control proceeds to a “Swap Pages From LM) block  386 . During processing associated with block  386 , pages are swapped from LPAR_ 1  LM  131  to clear space for the pages requested during processing associated with block  354 . Finally, control proceeds to an “End Access Page” block  389  during which process  380 , and process  350 , are complete. 
         [0044]      FIG. 7  is a flowchart of showing one example of a Swap Memory process  400  in accordance with the claimed subject matter. Like processes  300  and  350 , in this example, logic associated with process  400  is stored in CRSM_ 0   120  ( FIG. 1 ) and executed on one or more processors (not shown) of computing system  102  ( FIG. 1 ). Unlike processes  300  and  350 , which are executed in conjunction with LPAR  121 - 123 , process  400  is executed in conjunction with HYPR  116  ( FIGS. 1 and 2 ). In the example. LPAR_ 1   111  is requesting a particular page of memory from HYPR  116 . 
         [0045]    The following example may he best understood in light of the following scenario. Assume that LPAR_ 2   112  ( FIGS. 1 and 2 ) and LPAR_ 3   113  start operating such that sixteen gigabytes (16 GB) of logical memory is mapped to 16 GB of real memory, i.e. LAPR_ 2  LM  132  ( FIG. 2 ) is mapped to LPAR_ 2  PM  172  ( FIG. 2 ) and LAPR_ 3  LM  133  ( FIG. 2 ) is mapped to LPAR_ 3  PM  173 . Since shared memory pool  118  contains twenty gigabytes (20 GB), there is plenty of memory to cater to the memory requirements of LPAR_ 2   112  and LPAR_ 3   113 . Now assume that both LPAR_ 2   112  and LPAR_ 3   113  are under stress so that they are actually using all 16 GB. 
         [0046]    If LPAR_ 1   111  is now activated with a. requirement of 4 GB of memory, there is no issue because shared memory pool  118  has 4 GB of unallocated memory remaining. in other words, if LPAR_ 1   111  only needs 4 GB of memory, LPAR_ 1   111  may function without memory issues. However, if LPAR_ 1   111  is also put under stress such that 8 GB of memory is required, then 8 GB of logical memory  114  must he mapped to 4 GB of shared memory pool  118 . If 1 GB of LPAR_ 1  LM  131  is pinned, i.e. Pinned_ 1   161  ( FIG. 2 ), then 7 GB of logical memory  114  must be mapped to 3 GB of real memory  118 . 
         [0047]    Assuming that real memory  118  currently has eight hundred megabytes (800 MB) allocated for klock_ 1   151  and 2.2 GB allocated for free_ 1   141 , the remaining 4 GB. or 200 MB of klock_ 1   151  and 3.2 GB of free_ 1   141  would reside in paging space of a page space partition on CRSM_ 1   121 , controlled by HYPR page table  178  ( FIG. 2 ). If 500 MB of user pages and 500 MB of kernel pages are referred to continuously, then HYPR  116  does page ins and page outs operations for the existing 800 MB kernel pages and the 2.2 GB of user pages to the page space partition on CRSM_ 1   121 . In such a case kernel pages may be paged onto CRSM_ 1   121  with may result in a delay when the pages are accessed. Some applications such as real time processes and heartbeat daemons may crash as a result. 
         [0048]    In contrast to current technology, when implemented in accordance with the disclosed technology, only the 2.2 GB of user pages are paged in and out and the 500 MB of kernel data is not paged out unless there are no user pages that may be paged. In this manner, application such as, but not limited to, real time processes and heartbeat daemons are able to execute more predictably and with fewer faults than the same processes may execute under current system. 
         [0049]    Process  400  starts in a “Begin Swap Memory” block  402  and proceeds immediately to an “A MS Memory Available?” block  404 . During processing associated with block  404 , a determination is made as to whether or not AMS memory is available to load the page requested during processing associated with block  354  ( FIG. 5 ). If so, control proceeds to a “Use AMS Memory” block  406 , and the available AMS memory, which in this example would be Free_ 1   141  ( FIG. 2 ) is utilized. If not, control proceeds to a Non-Klock (NK Memory Available?” block  408 . During processing associated with block  408 , a determination is made as to whether or not non-klock memory. which in the example is memory associated with LPAR_ 1  PM  141  but not associated with either klock_ 1   151  or pinned_ 161 . if so, during processing associated with a “Page Out non-klock (NK) Memory” block  410  the memory not associated with either klock_ 1   151  or pinned 1  — 1   161  is swapped to CRSM_ 1   121 . If, during processing associated with block  408 , a determination is made that NK memory is not available, control proceeds to a “Page Out Klock Memory” block  412 . During processing associated with block  412 , memory in LPAR_ 1  PM  141  associated with klock_ 1   151  is swapped to CRSM_ 1   121 . 
         [0050]    During processing associated with a “Page In” block  412 , the page requested during processing associated with block  354  is copied into the space created during processing associated with block  410  or  412 . During processing associated with a More Memory Needed?” block  416 , a determination is made as to whether or not all the pages requested have been paged in. If not, control returns to NK Memory Available? block  404  and processing, continues as described above. in this manner, HYPR  116  is able to ensure that all non-klock memory is utilized before any klock memory is needed. Finally, control proceeds to an “End Swap Memory” block  419  during which process  400  is complete. 
         [0051]    The terminology used herein is fur the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0052]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
         [0053]    The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can he implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Technology Classification (CPC): 6