Patent Abstract:
In a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the siring layer. The plating layer is terminated within the interposer substrate

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a package for mounting a semiconductor device (chip) and a solder bump, and its manufacturing method.  
           [0003]    2. Description of the Related Art  
           [0004]    Generally, when a semiconductor chip and solder bumps are mounted on terminals of a package by soldering or the like, it is impossible to mount the semiconductor chip and the solder bumps directly on the terminals, because the terminals are not made of rust proof material. Therefore, it is essential to electroplate Au or Ni/Au on the terminals before the semiconductor chip and the solder bumps are mounted.  
           [0005]    In a prior art method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal (see: JP-A-5-95025 &amp; JP-A-8-288422). This will be explained later in detail.  
           [0006]    In the above-described prior art method, however, the plating layer is finally left. Therefore, when the operation frequency of this semiconductor chip is higher, the amount of signals reflected by the plating layer is increased. Also, the parasitic capacitance of the plating layer adversely affects signals from the semiconductor chip to the solder bump and vice versa.  
         SUMMARY OF THE INVENTION  
         [0007]    It is an object of the present invention to provide a package and its manufacturing method capable of decreasing the amount of reflected signals and reducing the parasitic capacitance by plating layers.  
           [0008]    According to the present invention, in a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the wiring layer. The plating layer is terminated within the interposer substrate.  
           [0009]    Also, in a method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal or the wiring layer and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal. Finally, the plating layer is terminated within the package. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0011]    [0011]FIGS. 1A through 1I are cross-sectional views for explaining a prior art method for manufacturing a BGA type semiconductor device;  
         [0012]    [0012]FIG. 2 is a plan view illustrating the interposer substrate of FIG. 1A;  
         [0013]    [0013]FIG. 3 is a plan view illustrating the pattern layer of FIG. 1B;  
         [0014]    [0014]FIG. 4 is a plan view illustrating the Au plating layers of FIG. 1H;  
         [0015]    [0015]FIG. 5A is a plan view illustrating the BGA type semiconductor device obtained by the method as illustrated in FIGS. 1A through 1I;  
         [0016]    [0016]FIGS. 5B and 5C are side views of the device of FIG. 5A;  
         [0017]    [0017]FIGS. 6A through 6J are cross-sectional views for explaining a first embodiment of the method for manufacturing a BGA type semiconductor device according to the present invention;  
         [0018]    [0018]FIG. 7 is a plan view illustrating the pattern layer of FIG. 6B;  
         [0019]    [0019]FIG. 8 is a plan view illustrating the Au plating layers of FIG. 6H;  
         [0020]    [0020]FIG. 9 is a plan view illustrating the Au plating layers of FIG. 6J;  
         [0021]    [0021]FIG. 10A is a plan view illustrating the BGA type semiconductor device obtained by the method as illustrated in FIGS. 6A through 6J;  
         [0022]    [0022]FIGS. 10B and 10C are side views of the device of FIG. 10A;  
         [0023]    [0023]FIGS. 11, 12 and  13  are plan views illustrating modifications of FIGS. 7, 8 and  9 , respectively;  
         [0024]    [0024]FIGS. 14, 15 and  16  are plan views illustrating other modifications of FIGS. 7, 8 and  9 , respectively;  
         [0025]    [0025]FIGS. 17A through 17J are cross-sectional views for explaining a second embodiment of the method for manufacturing a BGA type semiconductor device according to the present invention;  
         [0026]    [0026]FIG. 18 is a plan view illustrating the pattern layer of FIG. 17B;  
         [0027]    [0027]FIG. 19 is a plan view illustrating the Au plating layers of FIG. 17H;  
         [0028]    [0028]FIG. 20 is a plan view illustrating the Au plating layer of FIG. 17J;  
         [0029]    [0029]FIGS. 21, 22 and  23  are plan views illustrating modifications of FIGS. 18, 19 and  20 , respectively; and  
         [0030]    [0030]FIGS. 24, 25 and  26  are plan views illustrating other modifications of FIGS. 18, 19 and  20 , respectively. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]    Before the description of the preferred embodiments, a prior art method for manufacturing a ball grid array (BGA) type semiconductor device will be explained with reference to FIGS. 1A through 1I.  
         [0032]    Initially, an interposer substrate  101  made of polyamide as illustrated in FIG. 2 is prepared. Note that a dotted area PA designates a package area, and CA designates a current supply area.  
         [0033]    Next, referring to FIG. 1A, an adhesive layer  102  is coated on a back surface of the interposer substrate  101 . Then, a copper foil layer  103  is formed on a front surface of the interposer substrate  101 .  
         [0034]    Next, referring to FIG. 1B, the copper foil layer  103  is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 3. Each pattern of the pattern layer is constructed by wiring layers  103   a , terminals  103   b  for mounting solder balls (outer bumps) and plating layers  103   c.    
         [0035]    Next, referring to FIG. 1C, a solder resist layer  104  is coated on the entire front surface.  
         [0036]    Next, referring to FIG. 1D, openings  104   a  and  104   b  are perforated in the solder resist layer  104 . The opening  104   a  is used for forming an innerhole INH (see FIG. 1E), and the opening  104   b  exposes the terminal  103   b.    
         [0037]    Next, referring to FIG. 1E, an innerhole INH is perforated in the adhesive layer  102  and the interposer substrate  101  by a laser trimming process or the like. Note that the innerhole INH does not penetrate the wiring layer  103   a.  Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of the interposer substrate  101 .  
         [0038]    Next, referring to FIG. 1F, a plating mask layer  105  made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer ( 103   a ,  103   b ,  103   c ) from the current supply area CA of FIG. 2 while the interposer substrate  101  is dipped into a plating solution. As a result, a bump (plug layer)  106  is buried in the innerhole INH.  
         [0039]    Next, referring to FIG. 1G, the plating mask layer  105  is removed.  
         [0040]    Next, referring to FIG. 1H, an Au electroplating process is carried out by supplying a current to the pattern layer ( 103   a ,  103   b ,  103   c ) from the current supply area CA of FIG. 2 while the interposer substrate  101  is dipped into an Au plating solution. As a result, as illustrated in FIG. 4, an Au plating layer  107   a  is formed on the terminal  103   b  on the front surface of the interposer substrate  101 , and an Au plating layer  107   b  is formed on the plug layer  106  on the back surface of the interposer substrate  101 . Then, the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2.  
         [0041]    Finally, referring to FIG. 1I, a terminal of a flip-chip type semiconductor chip  2  is mounted on the back surface of the interposer substrate  101  by using an ultrasonic pushing tool. Then, the semiconductor chip  2  is molded by resin. Also, a solder ball  3  is provided on the front surface of the interposer substrate  101 .  
         [0042]    After that, a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices as illustrated in FIGS. 5A, 5B and  5 C, where FIGS. 5B and 5C are side views of FIG. 5A.  
         [0043]    In the BGA type semiconductor device obtained by the method as illustrated in FIGS. 1A through 1I, however, the plating layer  103   c  is left. Therefore, when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layer  103   c  is increased. Also, the parasitic capacitance of the plating layer  103   c  adversely affects signals from the semiconductor chip  2  to the solder bump  3  and vice versa.  
         [0044]    A first embodiment of the method for manufacturing a BGA type semiconductor device will be explained next with reference to FIGS. 6A through 6J.  
         [0045]    Initially, in the same way as in the prior art, an interposer substrate  11  made of polyimide as illustrated in FIG. 2 is prepared.  
         [0046]    Next, referring to FIG. 6A, in the same way as in FIG. 1A, an adhesive layer  12  is coated on a back surface of the interposer substrate  11 . Then, a copper foil layer  13  is formed on a front surface of the interposer substrate  11 .  
         [0047]    Next, referring to FIG. 6B, in a similar way to those of FIG. 1B, the copper foil layer  13  is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 7. Each pattern of the pattern layer is constructed by wiring layers  13   a , terminals  13   b  for mounting solder balls (outer bumps), plating layers  13   c , and a ground plate  13   d . Note that the ground plate  13   d  is connected to the plating layers  13   c . Also, the terminals  13   b  marked by “G” are ground terminals, the terminals  13   b  marked by “V cc ” are power supply terminals, and the terminals  13   b  marked by “S” are signal input/output terminals.  
         [0048]    Next, referring to FIG. 6C, in the same way as in FIG. 1C, a solder resist layer  14  is coated on the entire front surface.  
         [0049]    Next, referring to FIG. 6D, in the same way as in FIG. 1D, openings  14   a  and  14   b  are perforated in the solder resist layer  14 . The opening  14   a  is used for forming an innerhole INH (see FIG. 6E), and the opening  14   b  exposes the terminal  13   b.    
         [0050]    Next, referring to FIG. 6E, in the same way as in FIG. 1E, an innerhole INH is perforated in the adhesive layer  12  and the interposer substrate  11  by a laser trimming process or the like. Note that the innerhole INH does not penetrate the wiring layer  13   a . Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of the interposer substrate  11 .  
         [0051]    Next, referring to FIG. 6F, in the same way as in FIG. 1F, a plating mask layer  15  made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer ( 13   a ,  13   b ,  13   c ,  13   d ) from the current supply area CA of FIG. 2 while the interposer substrate  11  is dipped into a plating solution. As a result, a bump  16  is buried in the innerhole INH.  
         [0052]    Next, referring to FIG. 6G, in the same way as in FIG. 1G, the plating mask layer  15  is removed.  
         [0053]    Next, referring to FIG. 6H, in the same way as in FIG. 1H, an Au electroplating process is carried out by supplying a current to the pattern layer ( 13   a ,  13   b ,  13   c ,  13   d ) from the current supply area CA of FIG. 2 while the interposer substrate  11  is dipped into an Au plating solution. As a result, as illustrated in FIG. 8, an Au plating layer  17   a  is formed on the terminal  13   b  on the front surface of the interposer substrate  11 , and an Au plating layer  17   b  is formed on the plug layer  16  on the back surface of the interposer substrate  11 . Then, the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2.  
         [0054]    Next, referring to FIG. 9 as well as FIG. 6I, throughholes TH are perforated in the interposer substrate  11 , the adhesive layer  12  and the solder resist layer  14  by using metal molds. As a result, the plating layers  13   c  connected to the power supply terminals V cc  and the signal input/output terminals S are terminated at the throughholes TH. In this case, these plating layers  13   c  serve as stubs. On the other hand, the plating layers  13   c  connected to the ground terminals G remains and is still connected to the plate ground layer  13   d.    
         [0055]    Finally, referring to FIG. 6J, in the same way as in FIG. 1I, a terminal of a flip-chip type semiconductor chip  2  is mounted on the back surface of the interposer substrate  11  by using an ultrasonic pushing tool. Then, the semiconductor chip  2  is molded by resin. Also, a solder ball  3  is provided on the front surface of the interposer substrate  11 .  
         [0056]    After that, a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices as illustrated in FIGS. 10A, 10B and  10 C, where FIGS. 10B and 10C are side views of FIG. 10A.  
         [0057]    In the BGA type semiconductor device obtained by the method as illustrated in FIGS. 6A through 6J, the plating layers  13   c  connected to the power supply terminal V cc  and the signal input/output terminals S are terminated at the throughholes TH. Therefore, even when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layers  13   c  is decreased. Also, since the parasitic capacitance of the plating layers  13   c  is decreased, signals from the semiconductor chip  2  to the solder bump  3  and vice versa are hardly affected thereby.  
         [0058]    Also, in the first embodiment, since the ground plate  13   d  covers a large area of the package, the noise at the signal input/output terminals S can be remarkably suppressed.  
         [0059]    Further, in the first embodiment, if the terminals  13   b  are signal input/output terminals S, a length L of each of the pattern layers  13  between the bump  16  and the throughhole TH should be as small as possible to decrease the capacitance, thus enabling a high speed operation. Also, a length L1 of each of the remaining plating layers  13   c  connected to the signal input/output terminals S should be as small as possible to decrease the amount of reflected signals. Further, the length L of each of the pattern layers  13  connected to the signal input/output terminals S are equalized to homogenize the capacitance thereof, which is helpful in a high speed operation.  
         [0060]    The first embodiment can be modified as illustrated in FIGS. 11, 12 and  13 , which correspond to FIGS. 7, 8 and  9 , respectively. That is, the ground plate  13   d  of FIGS. 7, 8 and  9  is replaced by wiring layers  13   e . Even in this modification, the same effect except for the noise characteristics by the ground plate  13   d  can be expected.  
         [0061]    The first embodiment can be also modified as illustrated in FIGS. 14, 15 and  16 , which correspond to FIGS. 7, 8 and  9 , respectively. That is, the ground plate  13   d  of FIGS. 7, 8 and  9  is replaced by plating layers  13   f . The plating layers  13   f  are used in the Au electroplating process, and the plating layers  13   f  as well as the plating layers  13   c  are terminated by forming a throughhole TH. In FIGS. 14, 15 and  16 , note that each of the terminals  13   b  provided in the periphery of the package PA can be any of a ground terminal G, a power supply terminal V cc  and a signal input/output terminal S, while each of the terminals  13   b  provided at the center of the package PA can be a signal input/output terminal S or a power supply terminal G. Even in this modification, the same effect except for the noise characteristics by the ground plate  13   d  can be expected.  
         [0062]    A second embodiment of the method for manufacturing a BGA type semiconductor device will be explained next with reference to FIGS. 17A through 17J.  
         [0063]    Initially, in the same way as in the prior art, an interposer substrate  21  made of polyimide as illustrated in FIG. 2 is prepared.  
         [0064]    Next, referring to FIG. 17A, in the same way as in FIG. 1A, an adhesive layer  22  is coated on a back surface of the interposer substrate  21 . Then, a copper foil layer  23  is formed on a front surface of the interposer substrate  21 .  
         [0065]    Next, referring to FIG. 17B, in a similar way to those of FIG. 1B, the copper foil layer  23  is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 18. Each pattern of the pattern layer is constructed by wiring layers  23   a , terminals  23   b  for mounting solder balls (outer bumps), plating layers  23   c , and a ground plate  23   d . Note that the ground plate  23   d  is connected to the plating layers  23   c . Also, the terminals  23   b  marked by “S” are signal input/output terminals. Further, since the ground plate  23   d  surrounds the pattern layer ( 23   a ,  23   b ,  23   c ) so that the pattern layer is shielded by the ground plate  23   d , the inductance of the package can be decreased.  
         [0066]    Next, referring to FIG. 17C, in the same way as in FIG. 1C, a solder resist layer  24  is coated on the entire front surface.  
         [0067]    Next, referring to FIG. 17D, in the same way as in FIG. 1D, openings  24   a  and  24   b  are perforated in the solder resist layer  24 . The opening  24   a  is used for forming an innerhole INH (see FIG. 17E), and the opening  24   b  exposes the terminal  23   b.    
         [0068]    Next, referring to FIG. 17E, in the same way as in FIG. 1E, an innerhole INH is perforated in the adhesive layer  22  and the interposer substrate  21  by a laser trimming process or the like. Note that the innerhole INH does not penetrate the wiring layer  23   a . Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of the interposer substrate  21 .  
         [0069]    Next, referring to FIG. 17F, in the same way as in FIG. 1F, a plating mask layer  25  made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer ( 23   a ,  23   b ,  23   c ,  23   d ) from the current supply area CA of FIG. 2 while the interposer substrate  21  is dipped into a plating solution. As a result, a bump  26  is buried in the innerhole INH.  
         [0070]    Next, referring to FIG. 17G, in the same way as in FIG. 1G, the plating mask layer  25  is removed.  
         [0071]    Next, referring to FIG. 17H, in the same way as in FIG. 1H, an Au electroplating process is carried out by supplying a current to the pattern layer ( 23   a ,  23   b ,  23   c ,  23   d ) from the current supply area CA of FIG. 2 while the interposer substrate  21  is dipped into an Au plating solution. As a result, as illustrated in FIG. 19, an Au plating layer  27   a  is formed on the terminal  23   b  on the front surface of the interposer substrate  21 , and an Au plating layer  27   b  is formed on the plug layer  26  on the back surface of the interposer substrate  21 . Then, the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2.  
         [0072]    Next, referring to FIG. 20 as well as FIG. 17I, a part of the plating layer  27   c  on the side of the terminals S is removed by a laser trimming process or a photolithography and etching process. Note that a part of the solder resist layer  24  is also removed. As a result, the plating layer  23   c  connected to the signal input/output terminal S is terminated at a location indicated by X. In this case, the plating layer  23   c  serves as a stub.  
         [0073]    Finally, referring to FIG. 17J, in the same way as in FIG. 1I, a terminal of a flip-chip type semiconductor chip  2  is mounted on the back surface of the interposer substrate  21  by using an ultrasonic pushing tool. Then, the semiconductor chip  2  is molded by resin. Also, a solder ball  3  is provided on the front surface of the interposer substrate  21 .  
         [0074]    After that, a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices.  
         [0075]    In the BGA type semiconductor device obtained by the method as illustrated in FIGS. 17A through 17J, the plating layers  23   c  connected to the signal input/output terminal S is terminated at the location X. Therefore, even when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layers  23   c  is decreased. Also, since the parasitic capacitance of the plating layers  23   c  is decreased, signals from the semiconductor chip  2  to the solder bump  3  and vice versa are hardly affected thereby.  
         [0076]    Also, in the second embodiment, since the ground plate  23   d  covers a large area of the package, the noise at the signal input/output terminals S can be remarkably suppressed.  
         [0077]    Further, in the second embodiment, a length L of the pattern layers  23  between the bump  26  and the location X should be as small as possible to decrease the capacitance, thus enabling a high speed operation. Also, a length L1 of each of the remaining plating layers  23   c  should be as small as possible to decrease the amount of reflected signals.  
         [0078]    The second embodiment can be modified as illustrated in FIGS. 21, 22 and  23 , which correspond to FIGS. 18, 19 and  20 , respectively. That is, the plating layer  23   c  is connected between the ground plate  23   d  and a portion of the wiring layer  23   a  where the bump  26  will be provided.  
         [0079]    The second embodiment can be also modified as illustrated in FIGS. 24, 25 and  26 , which correspond to FIGS. 18, 19 and  20 , respectively. That is, the plating layer  23   c  is connected between the ground plate  23   d  and a center portion of the wiring layer  23   a.    
         [0080]    Even in the modifications, the same effect can be expected. In addition, the length L of the pattern layers  23  are equalized to homogenize the capacitance thereof, which is helpful in a high speed operation.  
         [0081]    In the above-described embodiments, although the interposer substrate is made of single polyamide, the present invention can be applied to an interposer substrate made of other material or multi-structured materials. Additionally, the present invention can be applied to other packages than a BGA type package, such as a land grid array (LGA) type package.  
         [0082]    As explained hereinabove, according to the present invention, since plating layers for supplying currents during an electroplating operation are finally terminated, even when the operation frequency of a semiconductor device is higher, the amount of signals reflected by the plating layers can be decreased. Also, since the parasitic capacitance of the plating layers is decreased, signals from the semiconductor device to its solder bumps and vice versa are hardly affected thereby.

Technology Classification (CPC): 7