Patent Abstract:
Methods for compensation of imbalance between I (In-phase) and Q (Quadrature) signal paths ( 12   a,    12   b,    605   a,    605   b ) in a quadrature receiver ( 8 ) and a quadrature transmitter ( 600 ) are disclosed. In the receiver case, the imbalance is compensated for by means of post-distortion in the digital domain. In the transmitter case, the imbalance is compensated for by means of pre-distortion in the digital domain. The methods can be carried out with a relatively low computational complexity. Signal-processing devices ( 30, 610 ) for carrying out the methods are disclosed as well. The same basic internal structure may be used for the signal-processing device ( 30 ) in the receiver case as for the signal processing device ( 610 ) in the transmitter case.

Full Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to methods and apparatuses for compensation of imbalance between I (In-phase) and Q (Quadrature) signal paths in a quadrature receiver and a quadrature transmitter. 
       BACKGROUND 
       [0002]    Mismatch, or imbalance, between an in-phase (I) and a quadrature (Q) signal path in a quadrature receiver circuit limits the achievable image attenuation, which results in a distorted signal. Likewise, imbalance between an I and a Q signal path in a quadrature transmitter circuit also poses a limitation on the achievable image attenuation. 
         [0003]    Various techniques have been developed for compensation of such imbalance in order to mitigate the effects of the imbalance and provide improved image attenuation. For example, the article L. Antilla et al, “Circularity-based I/Q imbalance compensation in wideband direct-conversion receivers”,  IEEE Transactions on Vehicular Technology,  vol. 57, no. 4, pp. 2099-2113, July 2008, discloses compensation of I/Q imbalance in quadrature receivers. In the following, this article is referred to as the Antilla receiver paper. Furthermore, the article L. Antilla et al, “Frequency-selective I/Q mismatch calibration of wideband direct-conversion transmitters”,  IEEE Transactions on Circuits and Systems—II: Express Briefs,  vol. 55, no. 4, pp. 359-363, April 2008, discloses compensation of I/Q imbalance in quadrature transmitters. In the following, this article is referred to as the Antilla transmitter paper 
         [0004]      FIG. 1  illustrates a block diagram of a basic compensation circuit  1  utilized in both of the articles mentioned above. A complex-valued signal o 1 (n) is an input signal to the compensation circuit  1  and another complex-valued signal o 2 (n) is output from the compensation circuit  1 . In the case of a receiver circuit, o 1 (n) is a signal, representing received data, having unbalanced I and Q components that is processed by the compensation circuit  1  to generate the signal o 2 (n) with (ideally) restored balance between the I and Q components. In the case of a transmitter circuit, o 1 (n) is a signal, representing data to be transmitted, having balanced I and Q components, which is processed by the compensation circuit  1  to generate the signal o 2 (n) with imbalance between the I and Q components that compensates for the imbalance in the I and Q signal paths of the transmitter such that the transmitted radio-frequency (RF) signal (ideally) has balanced I and Q components. In either case, the signal o 1 (n) is input to a block  2  that generates the complex conjugate o* 1 (n) of o 1 (n), which is filtered by a filter  3  having the frequency response W(e jω ). The output signal of the filter  3  is added to the signal o 1 (n) in the adder unit  4  to generate the signal o 2 (n). 
         [0005]    It is desirable to provide efficient compensation of imbalance between I and Q signal paths of a quadrature receiver or a quadrature transmitter at a relatively low computational complexity, e.g. in order provide a relatively small overhead in terms of required circuit area and/or power consumption for performing the compensation. 
       SUMMARY 
       [0006]    An object of the present invention is to provide means for compensation of imbalance between an in-phase (I) and a quadrature (Q) signal path of a quadrature receiver with a relatively low computational complexity. Another object of the present invention is to provide means for compensation of imbalance between an I and a Q signal path of a quadrature transmitter with a relatively low computational complexity. 
         [0007]    According to a first aspect, there is provided a method for compensating an imbalance between an I and a Q signal path of a quadrature receiver adapted to generate a real-valued uncompensated digital I component a(n) and a real-valued uncompensated digital Q component b(n), together forming an uncompensated complex digital signal x(n)=a(n)+jb(n), wherein j denotes the imaginary unit and n is a sequence index. The method comprises generating a complex compensation signal by filtering one of a(n) and jb(n) with a compensation filter having a complex-valued impulse response. Furthermore, the method comprises generating a first compensated complex digital signal as the sum of x(n) and the complex compensation signal. 
         [0008]    The method may further comprise adaptively generating filter parameters of the compensation filter. 
         [0009]    The impulse response of the compensation filter may be on the form: h Δ (n)+jφδ(n)+jφh Δ (n)+(e jφ −1−jφ)·(δ(n)+h Δ (n)), wherein δ(n) is the unit pulse, φ is a real-valued parameter and h Δ (n) is a real-valued sequence. Adaptively generating filter parameters of the compensation filter may comprise adaptively generating the real-valued parameter φ and the real-valued sequence h Δ (n). 
         [0010]    Adaptively generating filter parameters of the compensation filter may comprise, for each of a number of iterations, where each iteration is identified by an iteration index i, generating filter parameters for attaining an impulse response f (i) (n), wherein f (i) (n) is a default impulse response for the first iteration, wherein i=1, and f (i) (n) is based on f (i−1) (n) and Δ (i−1) (n) for i&gt;1, and Δ (i−1) (n) is an estimated impulse-response error of a preceding iteration. Furthermore, for each iteration, adaptively generating said filter parameters may comprise generating the complex compensation signal, denoted e (i) (n), as e (i) (n)=f (i) (n)*w(n), wherein * denotes the convolution operator and w(n) denotes said one of a(n) and jb(n). Moreover, for each iteration, adaptively generating said filter parameters may comprise generating the first compensated complex digital signal, denoted v (i) (n), as v (i) (n)=x(n)+e (i) (n). In addition, for each iteration, adaptively generating said filter parameters may comprise generating filter parameters determining Δ (i) (n) by minimizing a cost function based on u (i) (n)=v (i) (n)+Δ (i) (n)*w(n). 
         [0011]    Said cost function may e.g. a linear cost function. Furthermore, said cost function may be based on a properness measure of u (i) (n). 
         [0012]    Each iteration may further comprise generating a second compensated complex digital signal y (i) (n)=v (i) (n)+Δ (i) (n)*w(n) based on the generated Δ (i) (n). 
         [0013]    The method may further comprise determining whether a condition for ending said iterations is fulfilled. Moreover, the method may comprise, if said condition is fulfilled, ending said iterations and continuing compensating said imbalance between the I and the Q signal path based on filter parameters generated in the last iteration. 
         [0014]    The impulse response f (i) (n) may be on the form: f (i) (n)=h Δ   (i) (n)+jφ (k) δ(n)+jφ (i) h Δ   (i) (n)+(e jφ     (i)   −1−jφ (i) )·(δ(n)+h Δ   (i) (n)), wherein δ(n) is the unit pulse, φ (i)  is a real-valued parameter and h Δ   (i) (n) is a real-valued sequence. 
         [0015]    Furthermore, Δ (i) (n) may be on the form: Δ (i) (n)=Δ h   (i) (n)+jΔ φ   (i)  for n belonging to a finite set of integers and Δ (i) (n)=0 outside said finite set of integers, wherein Δ φ   (i)  is a real-valued parameter and Δ h   (i) (n) is a real-valued sequence. 
         [0016]    Generating filter parameters determining Δ (i) (n) may comprise generating the real-valued parameter Δ φ   (i)  and the real-valued sequence Δ h   (i) (n). 
         [0017]    Generating filter parameters for attaining the impulse response f (i) (n) may comprise generating the real-valued sequence h Δ   (i) (n) as h Δ   (i) (n)=h Δ   (i−1) (n)+Δ h   (i−1) (n) and the real-valued parameter φ (i)  as φ (i) =φ (i−1) +Δ φ   (i−1)  for i&gt;1. 
         [0018]    According to a second aspect, there is provided a method for compensating an imbalance between an I and a Q signal path of a quadrature receiver adapted to generate a real-valued uncompensated digital I component a(n) and a real-valued uncompensated digital Q component b(n), together forming an uncompensated complex digital signal x(n)=a(n)+jb(n), wherein j denotes the imaginary unit and n is a sequence index. The method comprises for each of a number of iterations, where each iteration is identified by an iteration index i, generating sample values of a finite-length real-valued impulse response g Δ   (i) (n) that can adopt nonzero values for n in a finite set K, wherein g  Δ   (i) (n) is a default impulse response for the first iteration, wherein i=1, and g Δ   (i) (n) is given by g Δ   (i) (n)=g Δ   (i−1) (n)+Δ g   (i−1) (n) for i&gt;1, and Δ g   (i−1) (n) is an estimated impulse-response error of a preceding iteration. Furthermore, for each iteration, the method comprises generating a real-valued phase parameter φ (i)  as a default value for the first iteration, where i=1, and as φ (i) =φ (i−1) +Δ φ   (i−1)  for i&gt;1, wherein Δ φ   (i−1)  is an estimated phase-parameter error of the preceding iteration. Moreover, for each iteration, the method comprises generating a first compensated complex digital signal, denoted v (i) (n), as 
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         [0000]    wherein * denotes the convolution operator, and either w 1 (n)=ja(n) and w 2 (n)=jb(n) or w 1 (n)=b(n) and w 2 (n)=a(n). In addition, for each iteration, the method comprises generating the estimated impulse response error Δ g   (i) (n) and the estimated phase-parameter error Δ φ   (i)  by minimizing a cost function based on 
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         [0019]    Said cost function may be a linear cost function. Furthermore, said cost function may be based on a properness measure of u (i) (n). 
         [0020]    Each iteration may further comprise generating a second compensated complex digital signal 
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         [0000]    based on the generated Δ g   (i) (n) and Δ φ   (i) . 
         [0021]    The method may further comprise determining whether a condition for ending said iterations is fulfilled. Furthermore, the method may comprise, if said condition is fulfilled, ending said iterations and continuing compensating said imbalance between the I and the Q signal path based on filter parameters generated in the last iteration. 
         [0022]    According to a third aspect, there is provided a signal-processing device for compensating an imbalance between an I and a Q, signal path of a quadrature receiver, wherein the quadrature receiver is adapted to generate a real-valued uncompensated digital I component a(n) and a real-valued uncompensated digital Q component b(n), together forming an uncompensated complex digital signal x(n)=a(n)+jb(n), wherein j denotes the imaginary unit and n is a sequence index, wherein the signal-processing device ( 30 ) is adapted to receive the uncompensated digital signal x(n) and compensate said imbalance by performing the method according to the first or the second aspect. 
         [0023]    According to a fourth aspect, there is provided a quadrature receiver. The quadrature receiver comprises an I and a Q signal path for generating a real-valued uncompensated digital I component a(n) and a real-valued uncompensated digital Q component b(n), together forming an uncompensated complex digital signal x(n)=a(n)+jb(n), wherein j denotes the imaginary unit and n is a sequence index. Furthermore, the quadrature receiver comprises a signal-processing device according to the third aspect for compensating an imbalance between the I and the Q signal path. 
         [0024]    According to a fifth aspect, there is provided a method for compensating an imbalance between an I and a Q signal path of a quadrature transmitter arranged to transmit a radio-frequency signal r a (t) representing an uncompensated complex-valued digital signal z(n)=c(n)+jd(n), wherein j denotes the imaginary unit, n is a sequence index, c(n) is an uncompensated digital I component, and d(n) is an uncompensated digital Q component, by generating a compensated complex-valued digital signal having a compensated digital I component, which is provided to the I signal path and a compensated digital Q component, which is provided to the Q signal path. The method comprises generating a complex compensation signal by filtering one of c(n) and jd(n) with a compensation filter having a complex-valued impulse response. Furthermore, the method comprises generating a first compensated complex digital signal as the sum of z(n) and the complex compensation signal. 
         [0025]    The method may further comprise adaptively generating filter parameters of the compensation filter. 
         [0026]    The impulse response of the compensation filter may be on the form: h Δ (n)+jφδ(n)+jφh Δ (n)+(e jφ −1−jφ)·(δ(n)+h Δ (n)), wherein δ(n) is the unit pulse, φ is a real-valued parameter and h Δ (n) is a real-valued sequence. Adaptively generating filter parameters of the compensation filter may comprise adaptively generating the real-valued parameter φ and the real-valued sequence h Δ (n). 
         [0027]    Adaptively generating filter parameters of the compensation filter may comprise, for each of a number of iterations, where each iteration is identified by an iteration index i, generating filter parameters for attaining an impulse response f (i) (n), wherein f (i) (n) is a default impulse response for the first iteration, wherein i=1, and f (i) (n) is based on f (i−1) (n) and Δ (i−1) (n) for i&gt;1, and Δ (i−10 (n) is an estimated impulse-response error of a preceding iteration. Furthermore, for each iteration, adaptively generating said filter parameters may comprise generating the complex compensation signal, denoted e (i) (n), as e (i) (n)=f (i) (n)*w(n), wherein * denotes the convolution operator and w(n) denotes said one of c(n) and jd(n). Moreover, for each iteration, adaptively generating said filter parameters may comprise generating the first compensated complex digital signal, denoted v (i) (n), as v (i) (n)=x(n)+e (i) (n). In addition, for each iteration, adaptively generating said filter parameters may comprise generating filter parameters determining Δ (i) (n) by minimizing a cost function based on a real-valued signal r BB (n), which is obtained from real downconversion of the signal r a (t). 
         [0028]    Said cost function may be a linear cost function. Furthermore, the method may comprise generating a signal q BB (n) corresponding to a signal that would have resulted from real downconversion of a radio-frequency signal generated by inputting the signal z(t) to a quadrature transmitter having no imbalance between the I and Q signal paths. The cost function may be based on a difference between r BB (n) and q BB (n). For example, the cost function is based on an L 2  noun or L ∞  norm of said difference. 
         [0029]    Each iteration may further comprise generating a second compensated complex digital signal y (i) (n)=v (i) (n)+Δ (i) (n)*w(n) based on the generated Δ (i) (n). 
         [0030]    The method may comprise determining whether a condition for ending said iterations is fulfilled. Furthermore, the method may comprise, if said condition is fulfilled, ending said iterations and continuing compensating said imbalance between the I and the Q signal path based on filter parameters generated in the last iteration. 
         [0031]    The impulse response f (i) (n) may be on the form: f (i) (n)=h Δ   (i) (n)+jφ (k) δ(n)+jφ (i) h Δ   (i) (n)+(e jφ     (i)   −1−jφ (i) )·(δ(n)+h Δ   (i) (n)), wherein δ(n) is the unit pulse, φ (i)  is a real-valued parameter h Δ   (i) (n) is a real-valued sequence. 
         [0032]    Furthermore, Δ (i) (n) may be on the form: Δ (i) (n)=Δ h   (i) (n)+jΔ φ   (i)  for n belonging to a finite set of integers and Δ (i) (n)=0 outside said finite set of integers, wherein Δ φ   (i)  is a real-valued parameter and Δ h   (i) (n) is a real-valued sequence. Generating filter parameters determining Δ (i) (n) may comprise generating the real-valued parameter Δ φ   (i)  and the real-valued sequence Δ h   (i) (n). 
         [0033]    Generating filter parameters for attaining the impulse response f (i) (n) may comprise generating the real-valued sequence h Δ   (i) (n) as h Δ   (i) (n)=h Δ   (i−1) (n)+Δ h   (i−1) (n) and the real-valued parameter φ (i)  as φ (i) =φ (i−1) +Δ φ   (i−1)  for i&gt;1. 
         [0034]    According to a sixth aspect, there is provided a signal-processing device for compensating an imbalance between an I and a Q signal path of a quadrature transmitter for transmitting a radio-frequency signal r a (t) representing an uncompensated complex-valued digital signal z(n)=c(n)+jd(n), wherein j denotes the imaginary unit, n is a sequence index, c(n) is an uncompensated digital I component, and d(n) is an uncompensated digital Q component. The signal processing device is adapted to receive the uncompensated complex-valued digital signal z(n) and generate a compensated digital I component, to be provided to the I signal path and a compensated digital Q component, to be provided to the Q signal path by performing the method according to the fifth aspect for compensating said imbalance. 
         [0035]    According to a seventh aspect, there is provided a quadrature transmitter for transmitting a radio-frequency signal r a (t) representing an uncompensated complex-valued digital signal z(n)=c(n)+jd(n). The quadrature transmitter comprises an I and a Q signal path arranged to receive a compensated digital I component and a compensated digital Q component, respectively, for generating the radio-frequency signal r a (t). Moreover, the quadrature transmitter comprises a signal-processing device according to the sixth aspect for compensating an imbalance between the I and the Q signal path. 
         [0036]    According to an eighth aspect, there is provided an electronic apparatus comprising the quadrature receiver according to the fourth aspect and/or the quadrature transmitter according to the seventh aspect. The electronic apparatus may e.g. be, but is not limited to, a mobile communication terminal or a radio base station. 
         [0037]    According to a ninth aspect, there is provided a computer program product comprising computer program code means for executing the method according to the first, second, or fifth aspect when said computer program code means are run by an electronic device having computer capabilities. 
         [0038]    According to a tenth aspect, there is provided a computer readable medium having stored thereon a computer program product comprising computer program code means for executing the method according to the first, second, or fifth aspect when said computer program code means are run by an electronic device having computer capabilities. 
         [0039]    According to an eleventh aspect, there is provided a hardware-description entity comprising computer-interpretable hardware-description code describing the signal-processing device according to the third or the sixth aspect and enabling computer-aided fabrication thereof as an application-specific hardware unit, through configuration of a configurable hardware unit, or a combination thereof. 
         [0040]    It is an advantage of embodiments of the present invention that imbalance between an I and a Q signal path of a quadrature receiver or transmitter can be compensated at a relatively low overhead in terms of required computational resources. This, in turn, means that the required circuit area and/or power consumption for performing the compensation can be kept relatively low. 
         [0041]    It should be emphasized that the term “comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0042]    Further objects, features and advantages of embodiments of the invention will appear from the following detailed description, reference being made to the accompanying drawings, in which: 
           [0043]      FIG. 1  is a block diagram of a known circuit for compensating I/Q imbalance; 
           [0044]      FIG. 2  is a block diagram of a quadrature receiver according to an embodiment of the present invention; 
           [0045]      FIG. 3  is a block diagram of a model of a quadrature receiver circuit; 
           [0046]      FIGS. 4-7  are block diagrams of a signal-processing device according to embodiments of the present invention; 
           [0047]      FIGS. 8-10  are flow charts for methods according to embodiments of the present invention; 
           [0048]      FIG. 11  is a block diagram of a signal-processing device according to an embodiment of the present invention; 
           [0049]      FIG. 12  is a flow chart for a method according to an embodiment of the present invention; 
           [0050]      FIG. 13  is a block diagram of a quadrature transmitter according to an embodiment of the present invention; 
           [0051]      FIG. 14  is a block diagram of a model of a quadrature transmitter circuit; 
           [0052]      FIG. 15  schematically illustrates an electronic apparatus according to an embodiment of the present invention; and 
           [0053]      FIG. 16  schematically illustrates a computer-readable medium and a programmable hardware unit. 
       
    
    
     DETAILED DESCRIPTION 
       [0054]      FIG. 2  is a block diagram of a quadrature receiver  8  according to an embodiment of the present invention. The quadrature receiver  8  is adapted to receive a continuous-time analog radio-frequency (RF) signal r a (t) on an input port  10 . In the following, the subscript “a” is used together with signals and impulse responses to indicate that the signal/impulse response is an analog continuous-time signal/impulse response, t is used as a time variable indicating continuous time, and n is used as a sequence index indicating discrete time. Furthermore, reference is made in the following to discrete-time signals/impulse responses that corresponds to continuous-time signals/impulse responses and vice versa. The term “corresponds” should in these contexts be interpreted as follows in this specification. In the case of a discrete-time signal s(n) that corresponds to a continuous-time signal s a (t), s(n)=s a (nT), where T is the sample period. It is assumed that the signal s a (t) is properly bandlimited to allow sampling without (significant) aliasing in accordance with the Nyquist sampling theorem. That is, it is assumed that the signal s a (t) has no (or in practice, only negligible) spectral content at frequencies above a frequency f BW &lt;1/(2T). In the case of a discrete-time impulse response g(n) that corresponds to a continuous-time impulse response g a (t), the discrete-time Fourier transform G(e jωt ) of g(n), defined by G(e jωt )=Σ n=−∞   ∞ g(n)e −jωnT , is equal to the continuous-time Fourier transform G a (jω) of g a (t), defined by 
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         [0000]    for a relevant angular frequency band, such as 0≦ω&lt;π/T or a subset thereof. 
         [0055]    According to the embodiment illustrated in  FIG. 2 , the quadrature receiver  8  comprises an in-phase (I) signal path  12   a  and a quadrature (Q) signal path  12   b.  The I signal path  12   a  comprises a mixer  14   a,  and the Q signal path  12   b  comprises a mixer  14   b.  Both mixers  14   a  and  14   b  are adapted to receive the RF signal r a (t) on an input port. Furthermore, the quadrature receiver comprises a local oscillator (LO) unit  17 , which is adapted to generate LO signals to the mixers  14   a  and  14   b.  Ideally, the LO signals supplied to the mixers  14   a  and  14   b  are provided in quadrature, i.e., ideally, there is a 90° (or π/2 radians) mutual phase shift between the LO signals. The mixers  14   a  and  14   b  are arranged to perform frequency down conversion of a signal frequency band of interest of the RF signal r a (t) to a lower frequency range. In the following, the quadrature receiver  8  is assumed to be a direct conversion receiver, which is adapted to down convert said frequency band to a base band, i.e. to a frequency band around 0 Hz. In other words, the LO frequency f 0  is a frequency band within said frequency band of interest. However, embodiments of the present invention is applicable to quadrature receivers that are adapted to down convert the signal frequency band of interest to other frequency bands as well. 
         [0056]    According to the embodiment illustrated in  FIG. 2 , the quadrature receiver  8  further comprises a filter  20   a  and a filter  20   b  in the I signal path  12   a  and the Q signal path  12   b,  respectively. The filters  20   a  and  20   b  are arranged to suppress unwanted frequency components output from the mixers  14   a  and  14   b.  In  FIG. 2 , the filters  20   a  and  20   b  are illustrated as low-pass (LP) filters. However, in other embodiments, where the quadrature receiver  8  is not a direct conversion receiver, the filters  20   a  and  20   b  may instead be band-pass (BP) filters. 
         [0057]    Moreover, in the embodiment illustrated in  FIG. 2 , the quadrature receiver  8  comprises an analog-to-digital converter (ADC)  25   a  and an ADC  25   b  in the I signal path  12   a  and the Q signal path  12   b,  respectively. The ADC  25   a  is adapted to convert the output signal from the filter  20   a  to a digital representation for generating a real-valued uncompensated digital I component, in the following denoted a(n). Similarly, the ADC  25   b  is adapted to convert the output signal from the filter  20   b  to a digital representation for generating a real-valued uncompensated digital Q component, in the following denoted b(n). The real-valued signals a(n) and b(n) together form an uncompensated complex digital signal x(n)=a(n)+jb(n), wherein j denotes the imaginary unit. 
         [0058]    A problem with frequency down conversion using mixers is that a frequency component of the input signal to the mixer located at a frequency f 0 +f 1  and another frequency component of the input signal to the mixer located at a frequency f 0 −f 1  are mapped onto the same frequency f 1  in the output signal from the mixer. By means of a quadrature receiver configuration, wherein a complex-valued signal representation is used, it is possible to suppress one of the components (normally referred to as the image component), say the one at f 0 −f 1 , and essentially maintain only the desired component, say the one at f 0 +f 1 . This is normally referred to as image rejection or image attenuation. In order to have a high degree of image attenuation, the I and Q signal paths need to be well balanced, i.e. the mutual phase difference between the LO signals of the I and Q signal paths needs to be close to 90° and the transfer functions of the I and Q signal paths need to be approximately equal. A mismatch, or imbalance, between the I and the Q signal path limits the achievable image attenuation. Such imbalance is normally due to temperature variations, manufacturing inaccuracies, and other non-idealities of the physical components in the I and Q signal paths of the quadrature receiver. Without use of compensation techniques, the achievable image attenuation is normally around 30-50 dB. Considering that the image component in some situations may well be 50-100 dB stronger than the desired component, such image attenuation may be insufficient. 
         [0059]    To compensate for the problems with insufficient image attenuation, the quadrature receiver  8  in the embodiment illustrated in  FIG. 2  comprises a signal-processing device  30 , which is adapted to compensate for imbalance between the I signal path  12   a  and the Q signal path  12   b  of the quadrature receiver  8 . The signal-processing device  30  is adapted to receive the uncompensated digital signal x(n) and compensate said imbalance by performing a signal processing method, which is further described below in the context of various embodiments. Thereby, the resulting overall I/Q imbalance of the quadrature receiver  8  can be reduced compared with if the signal-processing device  30  had not been present. 
         [0060]    In the embodiment illustrated in  FIG. 2 , the signal-processing device  30  is adapted to receive the signal a(n) on an input port  32   a  and the signal b(n) on an input port  32   d.  Furthermore, the signal-processing device  30  is adapted to output a compensated digital I component on an output port  34   a  and a compensated digital Q component on an output port  34   b.  In the embodiment illustrated in  FIG. 2 , the signals a(n) and b(n) are the output signals from the ADCs  25   a  and  25   b.  However, in other embodiments, one or more intervening components (not shown) for generating the signals a(n) and b(n) based on the output signals from the ADCs  25   a  and  25   b  may be connected between the ADCs  25   a  and  25   b  and the signal-processing device  30 . Nonlimiting examples of such intervening components may e.g. be filters or components for performing sample-rate conversion, such as interpolation or decimation. 
         [0061]      FIG. 3  is a block diagram of a model of the quadrature receiver  8  in  FIG. 2 , but without the signal-processing device  30 . The mixers  14   a  and  14   b,  and the LO  17  ( FIG. 2 ) are modeled with the multipliers  40   a  and  40   b  multiplying the signal r a (t) by cos(ω 0 t+ω 1 ) and −sin(ω 0 t+φ 2 ), respectively, where ω 0  is 2πf 0 . With balanced I and Q signal path, φ 1 =φ 2 . A difference between φ 1  and φ 2  results in an imbalance between the I and Q signal paths. 
         [0062]    The filters  20   a  and  20   b  ( FIG. 2 ) are modeled with the blocks  45   a  and  45   b,  respectively, having impulse responses h a1 (t) and h a2 (t), as indicated in  FIG. 3 . Furthermore, the ADCs  25   a  and  25   b  are modeled with ideal sample switches  50   a  and  50   b,  respectively, arranged to sample the output signals from the blocks  45   a  and  45   b  at time instants t=nT, where T denotes the sample period, as illustrated in  FIG. 3 . Any gain mismatch between and (linear) dynamic behavior of the ADCs  25   a  and  25   b  are lumped into the blocks  45   a  and  45   b  in the model of  FIG. 3 . 
         [0063]    An assumption used in derivations presented below is that the RF signal r a (t) is on the form r a (t)=z a (t)e jω     0     t +z* a (t)e −jω     0     t , where z a (t) is the corresponding analog representation of the discrete-time baseband signal z(n)=z a (nT)=c(n)+jd(n), which represents data transmitted by a transmitter, where c(n) and d(n) are both real-valued signals. A purpose of the quadrature receiver  8  is to enable recovery of said data. The signal x(n) can then be written on the form 
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         [0064]    Above, h 1 (n) and h 2 (n) are discrete-time impulse responses corresponding to continuous-time impulse responses h a1 (t) and h a2 (t). 
         [0065]    An equivalent representation is given by 
         [0000]        x ( n )= g   1 ( n )* p ( n )± g   2 ( n )* p *( n ),   (Eq. 4)
 
         [0000]    where the sign ± represents either + or − in different cases. In a case referred to below as case 1, ± represents +, and in a case referred to below as case 2, ± represents −. In Eq. 4, 
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         [0066]    According to case 1: 
         [0000]        p ( n )= e   −jφ     1     h   1 ( n )* z ( n ),   (Eq. 7)
 
         [0000]        h ( n )* h   1 ( n )= h   2 ( n ),   (Eq. 8)
 
         [0000]      and 
         [0000]      φ=φ 2 −φ 1 .   (Eq. 9)
 
         [0067]    According to case 2: 
         [0000]        p ( n )= e   −jφ     2     h   2 ( n )* z ( n ),   (Eq. 10)
 
         [0000]        h ( n )* h   2 ( n )= h   1 ( n ),   (Eq. 11)
 
         [0000]      and 
         [0000]      φ=φ 1 −φ 2 .   (Eq. 12)
 
         [0068]    For both case 1 and case 2, the signal p(n) is a linearly distorted version of z(n), from which z(n) can be recovered by means of a linear equalizer. Such a linear equalizer is normally included in a receiver. Hence, the signal-processing device  30  can be adapted to recover p(n) instead of z(n), which can instead be recovered from p(n) by means of said equalizer. The real and imaginary part of p(n) are in the following denoted ã(n) and {tilde over (b)}(n), respectively. Hence, p(n)=ã(n)+j{tilde over (b)}(n), where ã(n) and {tilde over (b)}(n) are real-valued signals. 
         [0069]    For case 1, we have: 
         [0000]        x ( n )= ã ( n )+ j (cos(φ) h ( n )* {tilde over (b)} ( n )−sin(φ) h ( n )* ã ( n ))   (Eq. 13)
 
         [0070]    Similarly, for case 2, we have: 
         [0000]        x ( n )=(cos(φ) h ( n )* ã ( n )−sin(φ) h ( n )* {tilde over (b)} ( n ))+ j{tilde over (b)} ( n )   (Eq. 14).
 
         [0071]    It can be observed from Eq. 13 and Eq. 14 that the real and imaginary parts of p(n) experience different transfer function, which results in image distortion in the signal x(n). Furthermore, it can be observed that in case 1, a(n)=ã(n) (i.e. the real parts of x(n) and p(n) are equal), and in case 2, b(n)={tilde over (b)}(n) (i.e. the imaginary parts of x(n) and p(n) are equal). This is utilized below in the derivation of resource-efficient circuitry and methods for compensating the I/Q imbalance. 
         [0072]    In  FIGS. 4-7 , referred to below, labels and reference signs included within square brackets relate to embodiments of a corresponding signal processing device for compensating I/Q imbalance in a quadrature transmitter. 
         [0073]      FIG. 4  is a block diagram of the signal-processing device  30  according to an embodiment of the present invention. According to the embodiment, the signal-processing device  30  comprises a compensation filter  60 . The compensation filter  60  is arranged to receive an input signal having only a real or an imaginary component, not both. Furthermore, the compensation filter  60  has a complex-valued impulse response, and is therefore arranged to output a complex-valued output signal (i.e. a signal having both a real and an imaginary component), which is a compensation signal for compensation of I/Q imbalance. In the embodiment of  FIG. 1 , the signal-processing device  30  has an input port  32  and an output port  34 . The input port  32  is a compound input port representing both input ports  32   a  and  32   b  in  FIG. 2 . Similarly, the output port  34  is a compound output port representing both output ports  34   a  and  34   b  in  FIG. 2 . Furthermore, according to the embodiment illustrated in  FIG. 4 , the signal-processing device  30  comprises an adder unit  65  adapted to generate a complex compensated digital signal y(n) as the sum of x(n) and the output signal of the compensation filter  60 . The signal y(n) is output on the output port  34 . With reference to  FIG. 2 , the real part of y(n) (or compensated digital I component) is output on the output port  34   a,  and the imaginary part of y(n) (or compensated digital Q component) is output on the output port  34   b.    
         [0074]    For case 1, the compensation filter  60  is arranged to receive the real part a(n) of x(n) as an input signal. For case 2, the compensation filter  60  is arranged to receive the imaginary part b(n) of x(n), multiplied by j, as an input signal. Hence, although such a connection is not explicitly shown in  FIG. 4 , the compensation filter  60  may be operatively connected to the input port  32  for receiving its input signal. For case 1, the selection of f(n) as 
         [0000]        f ( n )= e   jφ   h ( n )−δ( n )   (Eq. 15)
 
         [0000]      results in 
         [0000]        y ( n )=cos(φ) h ( n )* p ( n )=cos(φ 2 −φ 1 ) e   −jφ     1     h   2 ( n )* z ( n )   (Eq. 16).
 
         [0075]    Hence, y(n) is a linear function of z(n), from which z(n) can be recovered by means of a linear equalizer. Similarly, for case 2, the selection of f(n) as 
         [0000]        f ( n )= e   −jφ   h ( n )−δ( n )   (Eq. 17)
 
         [0000]      results in 
         [0000]        y ( n )=cos(φ) h ( n )* p ( n )=cos(φ 1 −φ 2 ) e   −jφ     2     h   1 ( n )* z ( n )   (Eq. 18).
 
         [0000]    Hence, also for case 2, y(n) is a linear function of z(n), from which z(n) can be recovered by means of a linear equalizer. 
         [0076]    It is an advantage of the embodiment illustrated in  FIG. 4  that the same performance in terms of image rejection can be achieved as for the compensation circuit illustrated in  FIG. 1  at a lower computational complexity, because only the real or imaginary part of x(n) is input to the compensation filter  60  in the embodiment of  FIG. 4 , whereas the filter  3  in the compensation circuit of  FIG. 1  requires a complex-valued input signal. Hence, for a given performance in tennis of image attenuation, the embodiment illustrated in  FIG. 4  can be implemented using a smaller amount of computational resources than the compensation circuit of  FIG. 1 . This, in turn, can be utilized to implement the embodiment of  FIG. 4  with a lower power consumption and/or smaller circuit area than the compensation circuit of  FIG. 1 . 
         [0077]    In order to facilitate efficient compensation of I/Q imbalance, filter parameters of the compensation filter  60  may be generated and updated adaptively. The methods disclosed in the Antilla receiver paper referred to in the “Background” section can e.g. be utilized for this purpose. Further approaches for adaptively generating filter parameters of compensation filters are disclosed below in the context of certain embodiments. 
         [0078]    Further simplifications of the compensation filter  60  are possible, which allows for a further reduction of the required computational complexity, as is disclosed below. For case 1, f(n) can be rewritten as 
         [0000]        f ( n )= h   Δ ( n )+ j φδ( n )+ jφh   Δ ( n )+( e   jφ −1− j φ)·(δ( n )+ h   Δ ( n ))   (Eq. 19)
 
         [0000]    where h Δ (n)=h(n)−δ(n). A block diagram of an embodiment of the signal-processing device  30  that utilizes the expression of Eq. 19 for obtaining a computational-efficient implementation is illustrated in  FIG. 5 . In this embodiment, the signal-processing device comprises a filter unit  70  adapted to receive the real-valued signal a(n) as an input signal. The filter unit  70  has the impulse response h  Δ (n). Furthermore, the signal-processing device  30  comprises an adder unit  75  adapted to generate the sum of a(n) and the output signal of the filter unit  70 . In addition, the signal-processing device  30  comprises a multiplication unit  80  adapted to multiply the sum generated by the adder unit  75  by the complex valued coefficient e jφ  and output the generated product. Moreover, the signal-processing device  30  comprises an adder unit  85  adapted to generate the sum of said product output from the multiplication unit  80  and −a(n). This sum corresponds to the complex-valued compensation signal output from the compensation filter  60  in the embodiment illustrated in  FIG. 4 . The adder circuit  85  is further adapted to add said sum and the signal x(n) to form the compensated digital signal y(n). In a comparison between  FIGS. 4 and 5 , the function of the compensation filter  60  ( FIG. 4 ) is performed by the filter unit  70 , multiplication unit  80 , and the adder units  75  and  85  ( FIG. 5 ), whereas the function of the adder unit  65  ( FIG. 4 ) is performed by the adder unit  85  ( FIG. 4 ). 
         [0079]    The impulse responses f(n) and h Δ (n) have the same lengths. However, f(n) has complex-valued samples, whereas h Δ (n) has only real-valued samples. In the following, it is assumed that the lengths of f(n) and h Δ (n) are finite and equal to N (i.e. finite-length impulse response (FIR) filters are used for the compensation). If the compensation filter  60  in the embodiment of  FIG. 4  is implemented as an FIR filter of length N with a “brute force” approach (e.g. as a standard or transposed direct form FIR filter), N multiplications with complex-valued coefficients are required for each sample, which corresponds to 2N multiplications with real-valued coefficients. With the same “brute force” approach used for implementing the filter unit  70  in  FIG. 5 , N multiplications with real-valued coefficients are required in the filter unit  70  for each sample. In addition, one multiplication with a complex-valued coefficient is required in the multiplication unit  80  for each sample, which corresponds to two multiplications with real-valued coefficients, resulting in a total of N+2 multiplications with real valued coefficients for each sample in the signal-processing device  30 , which is approximately 50% of the number of multiplications for the case where the compensation filter  60  of  FIG. 4  is implemented with a “brute force” approach. This can be utilized to further reduce the power consumption and/or the required circuit area. In addition, the adaptive generation of filter parameters is simplified, as only N real-valued filter coefficients for the filter unit  70  and the real-valued parameter φ need to be generated, compared with N complex-valued coefficients, corresponding to 2N real-valued coefficients, which are to be adaptively generated in the case where the compensation filter  60  of  FIG. 4  is implemented with the “brute force” approach. 
         [0080]    Comparing Eq. 15 and Eq. 17, it is readily realized that the structure of the signal-processing device  30  in  FIG. 5  can be utilized also in case 2, replacing a(n) with jb(n). This is illustrated in  FIG. 5  with the label “case 2: jb(n)”. Although the parameter φ enters with different signs in Eq. 15 and Eq. 17, this difference can be compensated for in the generation of the filter parameters by generating φ with different signs in the two cases (corresponding to a variable substitution where −φ is replaced with φ in Eq. 17). Such compensation is taken care of automatically in an adaptive parameter-generation scheme. 
         [0081]    Adaptive generation of filter parameters in the signal-processing device  30  according to an embodiment of the present invention is described below with reference to  FIG. 6 .  FIG. 6  is a block diagram of an embodiment of the signal-processing device  30 . According to this embodiment, the signal-processing device  30  comprises a compensation filter  160   a,  which essentially corresponds to the compensation filter  60  of  FIG. 4 . The compensation filter  160   a  is arranged to receive an input signal having only a real or an imaginary component, not both. Furthermore, the compensation filter  160   a  has a complex-valued impulse response, and is therefore arranged to output a complex-valued output signal, which is a compensation signal for compensation of I/Q imbalance. Just as for the compensation filter  60  in  FIG. 4 , the compensation filter  160   a  is arranged to receive a(n) in case 1 and jb(n) in case 2, as is illustrated in  FIG. 6 . 
         [0082]    Filter parameters of the filter unit  160   a  are adaptively generated in a number of iterations. Each iteration is below identified by an iteration index i. For the i:th iteration, filter parameters for attaining an impulse response f (i) (n) are generated. In the first iteration, f (i) (n) may be a default impulse response for the first iteration (i.e. for i=1). The default impulse response may e.g. be f (1) (n)=δ(n). For the following iterations (i.e. for i&gt;1), f (i) (n) is based on f (i−1) (n) and Δ (i−1) (n), and Δ (i−1) (n) is an estimated impulse-response error of a preceding iteration. How f (i) (n) can be based on f (i−1) (n) and Δ (i−1) (n) is described in more detail in the context of specific embodiments below. Furthermore, the complex compensation signal, which is denoted e (i) (n) in the following, is generated on an output port of the compensation filter  160   a  as e (i) (n)=f (i) (n)*w(n), wherein w(n) denotes a(n) in case 1 and jb(n) in case 2. A first compensated complex digital signal, denoted v (i) (n), is generated as v (i) (n)=x(n)+e (i) (n) in an adder unit  165   a of the signal-processing device  30 .    
         [0083]    In addition, filter parameters determining the estimated impulse response error Δ (i) (n) are generated, which can be used in the (i+1):th iteration for determining f (i) (n). For example, the filter parameters determining Δ (i) (n) may be generated based on the expression u (i) (n)=v (i) (n)+Δ (i) (n)*w(n), using an optimization technique aiming at making the I/Q imbalance of u (i) (n) lesser than that of v (i) (n). For example, the filter parameters determining Δ (i) (n) may be generated by minimizing a cost function that is based on u (i) (n). 
         [0084]    Assuming that the underlying signal z(t) is proper, as it is defined in the Antilla receiver paper referred to above, i.e. that 
         [0000]        E[z ( t ) z ( t −τ)]=0 for all τ,   (Eq. 20)
 
         [0000]    where E[·] denotes the expectation value operator, the compensated signal output from the signal-processing device  30  should also be proper if the I/Q imbalance is perfectly compensated. 
         [0085]    In such a case, the cost function based on u (i) (n) may be based on a properness measure of u (i) (n). Such a properness measure P(Δ (i) (n), k) may e.g. be defined as 
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         [0000]    where L is a suitably chosen interval. The length of L may e.g. be chosen based on computer simulations and/or measurements in order to obtain a desired accuracy for a given application. Furthermore, the cost function based on P(Δ (i) (n), k) may e.g. be defined as 
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         [0000]    where Re and Im denotes the real and imaginary parts, respectively, and K is a suitably chosen interval. The length of K may e.g. be chosen based on computer simulations and/or measurements in order to obtain a desired accuracy for a given application. As a general rule of thumb, the length of K should typically be at least of the same order as the length of Δ (i) (n). 
         [0086]    The cost function C(Δ (i) (n)) can be seen as a function of the filter parameters determining Δ (i) (n). In the following discussion, the number of filter parameters determining Δ (i) (n) is denoted M. C(Δ (i) (n)), as defined by Eq. 22, is generally a nonlinear cost function of the filter parameters determining Δ (i) (n) (depending, of course, on how Δ (i) (n) depends on the filter parameters). Another cost function {tilde over (C)}(Δ (i) (n)) may be derived from the nonlinear cost function C(Δ (i) (n)) (defined by Eq. 22, or as a nonlinear cost function of the filter parameters in any other suitable way) by linearizing C(Δ (i) (n)) with respect to the filter parameters, e.g. around the point Δ (i) (n)=0 for all n. Thereby, a linear cost function {tilde over (C)}(Δ (i) (n)) in the M filter parameters is obtained. For example, a set of linear equations may be derived by linearizing (Re(P(Δ (i) (n), k))) 2  and (Im(P(Δ (i) (n), k))) 2 , with respect to the M filter parameters, for each k ∈ K and setting the resulting linear equations equal to zero. Although the filter parameter values solving this linearized cost function does not exactly correspond to the minimum of C(Δ (i) (n)), the solution to the linearized cost function will normally, for each iteration, successively approach a solution, or region of solutions, close to the optimum solution. An advantage of this approach is that it requires less computational resources than directly minimizing the nonlinear cost function C(Δ (i) (n)). 
         [0087]    As indicated in  FIG. 6 , the signal-processing device  30  may be further arranged to generate a second compensated complex digital signal y (i) (n)=v (i) (n)+Δ (i) (n)*w(n) based on the generated filter parameters determining Δ (i) (n) (wherein, again, w(n) denotes a(n) in case 1 and jb(n) in case 2). For this purpose, the signal-processing device  30  may comprise a filter unit  160   b,  having the impulse response Δ (i) (n), and an adder unit  165   b  as indicated in  FIG. 6 . This second compensated digital signal y (i) (n) may be the signal which is output on the output port  34 . In other embodiments, the signal v (i) (n) may instead be output on the output port  34 . In such embodiments, the filter unit  160   b  and the adder unit  165   b  may be omitted. 
         [0088]    In an embodiment, the compensation filter  160   a  is an FIR filter, wherein the length of each of the impulse responses f (i) (n) and Δ (i) (n) are N. Furthermore, the filter parameters for attaining the impulse response f (i) (n) are the N real parts and the N imaginary parts of the samples of f (i) (n). Similarly, the filter parameters determining Δ (i) (n) are the N real parts and the N imaginary parts of the samples of Δ (i) (n). Hence, in this embodiment, M=2N. Moreover, in this embodiment, f (i) (n) is generated based on f (i−1) (n) and Δ (i−1) (n) as f (i) (n)=f (i−1) (n)+Δ (i−1) (n). 
         [0089]      FIG. 7  is a block diagram of another embodiment of the signal-processing device  30 , corresponding to the embodiment illustrated in  FIG. 5 , which also illustrates adaptive generation of filter parameters. In this embodiment, the impulse response f (i) (n) is on the form 
         [0000]        f   (i) ( n )= h   Δ   (i) ( n )+ jφ   (k) δ( n )+ jφ   (i)   h   Δ   (i) ( n )+( e   jφ     (i)   −1− jφ   (i) )·(δ( n )+ h   Δ   (i) ( n ))   (Eq. 23)
 
         [0000]    where φ (i)  is a real-valued parameter and h Δ   (i) (n) is a real-valued sequence. This form of f (i) (n) is motivated by Eq. 19. 
         [0090]    In the embodiment illustrated in  FIG. 7 , the signal-processing device  30  comprises a filter unit  170 , which essentially corresponds to the filter unit  70  in  FIG. 5 . The filter unit  170  has the impulse response h Δ   (i) (n). Furthermore, the signal-processing device  30  comprises an adder unit  175  adapted to generate the sum of w(n) (which, as above, is used to denote a(n) for case 1 and jb(n) for case 2) and the output signal of the filter unit  170 . The adder unit  175  essentially corresponds to the adder unit  75  in  FIG. 5 . In addition, the signal-processing device  30  comprises a multiplication unit  180   a  adapted to multiply the sum generated by the adder unit  175  by the complex valued coefficient e jφ     (i)    and output the generated product. The multiplication unit  180   a  essentially corresponds to the multiplication unit  80  in  FIG. 5 . Moreover, the signal-processing device  30  comprises an adder unit  185   a  adapted to generate the sum of said product output from the multiplication unit  180   a  and −w(n). The adder unit  185   a  essentially corresponds to the adder unit  85  in  FIG. 5 . The output signal of the adder unit  185   a  is a first compensated complex digital signal, denoted v (i) (n). 
         [0091]    For the embodiment illustrated in  FIG. 7 , the adaptive generation of filter parameters may be performed in the same general way as described in the context of  FIG. 6 . The filter parameters determining Δ (i) (n) may be a real-valued parameter Δ φ   (i)  and a real-valued sequence Δ h   (i) (n), having the same length as the real-valued sequence h Δ   (i) (n). The filter parameters to be generated for attaining the impulse response f (i) (n) may be the real-valued sequence h Δ   (i) (n), which can be generated as 
         [0000]        h   Δ   (i) ( n )= h   Δ   (i−1) ( n )+Δ h   (i−1) ( n ),   (Eq. 24)
 
         [0000]    and the real-valued parameter φ (i) , which can be generated as 
         [0000]      φ (i) =φ (i−1) +Δ φ   (i−1) .   (Eq. 25)
 
         [0092]    In the following, it embodiments where the filter unit  170   a  is an FIR filter is considered. Hence, the impulse response h  Δ   (i) (n) has finite length which is denoted N in conformity with the example above in connection with  FIG. 6 . The estimated impulse response error Δ (i) (n) may be on the form 
         [0000]      Δ (i) ( n )=Δ h   (i) ( n )+ jΔ   φ   (i)    (Eq. 26)
 
         [0000]    for n belonging to a finite set of integers and Δ (i) (n)=0 outside said finite set of integers. Said finite set of integers is the interval of length N for which h Δ   (i) (n) can adopt nonzero values. The expression given by Eq. 26 is a first-order approximation of f (i+1) (n)−f (i) (n) with f (i) (n) given by Eq. 23 and φ (i)  and h Δ   (i) (n) given by Eq. 24 and Eq. 25, respectively. For this situation, the number M of filter parameters for attaining the impulse response f (i) (n) is N+1, namely the N real-valued samples of h Δ   (i) (n) and the real-valued parameter φ (i) . For N&gt;1, this is less than for the example presented above with reference to  FIG. 6 , wherein M=2N, whereby adaptive generation of filter parameters can be performed using less computational resources, which is an advantage. 
         [0093]    As indicated in  FIG. 7 , the signal-processing device  30  may be further arranged to generate a second compensated complex digital signal y (i) (n)=v (i) (n)+Δ (i) (n)*w(n) based on the generated filter parameters determining Δ (i) (n). For this purpose, the signal-processing device  30  may comprise a filter unit  170   b,  having an impulse response equal to the real part of Eq 26, a filter unit  180   b  having an impulse response equal to j multiplied by the imaginary part of Eq. 26, and adder units  185   b  and  185   c  as indicated in  FIG. 7 . As for the embodiment illustrated in  FIG. 6 , this second compensated digital signal y (i) (n) may be the signal which is output on the output port  34 . In other embodiments, the signal v (i) (n) may instead be output on the output port  34 . In such embodiments, the filter units  170   b  and  180   b  and the adder units  185   b  and  185   c  may be omitted. 
         [0094]    In a comparison between the block diagrams in  FIG. 7  and the more general block diagram of  FIG. 6 , the function of the compensation filter  160   a  ( FIG. 6 ) is performed by the filter unit  170   a,  the multiplication unit  180   a,  and the adder units  175  and  185   a  ( FIG. 7 ). Furthermore, the function of the adder unit  165   a  ( FIG. 6 ) is performed by the adder unit  185   a  ( FIG. 7 ). Moreover, the function of the filter unit  160   b  ( FIG. 6 ) is performed by the filter units  170   b  and  180   b  and the adder unit  185   b  ( FIG. 7 ), and the function of the adder unit  165   b  ( FIG. 6 ) is performed by the adder unit  185   c.    
         [0095]      FIG. 8  is a flow chart of a method for compensating an imbalance between the I signal path  12   a  and the Q signal path  12   b  of the quadrature receiver  8  ( FIG. 2 ) according to an embodiment of the present invention. The method may e.g. be performed by the signal-processing device  30  ( FIGS. 2-7 ). According to the embodiment, the method is started in step  200 . In step  205 , the uncompensated complex digital signal x(n)=a(n)+jb(n) is received, e.g. on the input port  32  ( FIGS. 3-7 ) or ports  32   a  and  32   b  ( FIG. 2 ) of the signal-processing device  30 . In step  210 , the complex compensation signal is generated by filtering one of a(n) (case 1) and jb(n) (case 2) with a compensation filter having a complex-valued impulse response. Step  210  may e.g. be performed by the compensation filter  60  ( FIG. 4 ), the elements  70 - 85  ( FIG. 5 ) described above as performing the function of the compensation filter  60  ( FIG. 4 ), the compensation filter  160   a  ( FIG. 6 ), or the elements  170   a,    175 ,  180   a,  and  185   a  ( FIG. 7 ) described above as performing the function of the compensation filter  160   a  ( FIG. 6 ). Furthermore, in step  215 , a first compensated complex digital signal is generated as the sum of x(n) and the complex compensation signal. Said first compensated complex digital signal may be the signal y(n) in  FIGS. 4 and 5 , or the signal v (i) (n) in  FIGS. 6 and 7 . The method is ended in step  220 . 
         [0096]    The method may further comprise adaptively generating filter parameters of the compensation filter. Adaptively generating filter parameters of the compensation filter may e.g. comprise adaptively generating the complex-valued samples of the impulse response f(n) or adaptively generating the real-valued samples of the impulse response h Δ (n) and the real-valued parameter φ as described above with reference to  FIGS. 4 and 5 . 
         [0097]      FIG. 9  is a flow chart indicating how adaptive generation of filter parameters can be performed according to an embodiment of the present invention, which is e.g. applicable to the embodiments of the signal-processing device  30  illustrated in  FIGS. 6 and 7 . The flow chart in  FIG. 9  illustrates one iteration of the iterative process described above with reference to  FIGS. 6 and 7 . The iteration is started in step  300 . In step  305 , filter parameters for attaining the impulse response f (i) (n), wherein f (i) (n) is a default impulse response for the first iteration, wherein i=1, and f (i) (n) is based on f (i−1) (n) and Δ (i−1) (n) for i&gt;1. Furthermore, in step  310 , the complex compensation signal, denoted e (i) (n), is generated as e (i) (n)=f (i) (n)*w(n), wherein w(n) denotes a(n) (case 1) or jb(n) (case 2). Moreover, in step  315 , the first compensated complex digital signal v (i) (n) is generated as v (i) (n)=x(n)+e (i) (n). In addition, the filter parameters determining Δ (i) (n) are generated in step  320  by minimizing a cost function based on u (i) (n)=v (i) (n)+Δ (i) (n)*w(n). The iteration is ended in step  320 . In some embodiments, the iteration may also comprise generating a second compensated complex digital signal y (i) (n)=v (i) (n)+Δ (i) (n)*w(n) based on the generated Δ (i) (n) as described in the context of  FIGS. 6-7 . 
         [0098]    As described above with reference to  FIG. 7 , the cost function may be based on a properness measure of u (i) (n). Furthermore, as is also described in the context of  FIG. 7 , the cost function may be a linear cost function, such as a cost function obtained by linearization of a nonlinear cost function based on u (i) (n). 
         [0099]    The impulse responses f (i) (n) and Δ (i) (n) may e.g. have any of the forms described above in the context of  FIGS. 6 and 7  above. Furthermore, the steps  305  and  320  may e.g. comprise generating filter parameters in any of the ways described above with reference to  FIGS. 6 and 7 . 
         [0100]    In some embodiments, the iterations for adaptively generating filter parameters may be continually executed as long as the signal-processing device  30  is in operation. In other embodiments, the iterations may be terminated, or ended, when a certain stop condition for ending the iterations is fulfilled. Such a condition may e.g. be that the maximum value (over all n) of |Δ (i) (n)| is below a threshold value. The threshold value may e.g. be selected based on a system specification, computer simulations and/or measurements, e.g. to achieve certain degree of image rejection required by the system specification or to fulfill some other criterion of system specification. 
         [0101]    Such operation is illustrated by the flow chart in  FIG. 10 . In Step  400 , the operation is started. In step  405 , it is determining whether the stop condition is fulfilled. If the stop condition is not fulfilled, the filter parameter generation is iterated once more in step  410 . Step  410  may e.g. be performed in accordance with the flow chart in  FIG. 9 . If the stop condition is fulfilled, the iterations are ended and compensation of the imbalance between the I signal path  12   a  and the Q signal path  12   b  based on filter parameters generated in the last iteration is continued in step  415 . 
         [0102]    A slight modification of the block diagram of the signal processing device  30  in  FIG. 6 , resulting in essentially the same function, except for a phase shift, at a computational complexity that is comparable to that of the block diagram of  FIG. 6  is shown in  FIG. 11 . The embodiment illustrated in  FIG. 11  is motivated as follows. Setting, for case 1, 
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         [0000]    wherein, in both cases, g(n)*h(n)=δ(n), then y(n)=p(n) for both cases. That is, y(n) is a linear function of z(n), from which z(n) can be recovered by means of a linear equalizer. The definitions for h(n), p(n), and φ for the two cases are given by Eq. 7-Eq. 11. Setting 
         [0000]        g   Δ ( n )= g ( n )−δ( n ),   (Eq 29)
 
         [0000]    Eq. 27 can be rewritten as 
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         [0000]    It should be noted that g Δ (n) is a real-valued sequence. 
         [0103]    According to the embodiment illustrated in  FIG. 11 , the signal processing device  30  comprises a filter unit  500   a,  which is arranged to receive and filter a signal, which in the following is denoted w 2 (n). For case 1, w 2 (n)=jb(n), and for case 2, w 2 (n)=a(n) as indicated in  FIG. 11 . The filter unit  500   a  has a real-valued finite-length impulse response g Δ   (i) (n), which can adopt nonzero values for n in a finite set K. For example, the set K may be an interval of length N, whereby g Δ   (i) (n) has a finite length N. Furthermore, the signal processing device comprises an adder unit  505  arranged to generate the sum of the output signal of the filter unit  500   a  and w 2 (n). Moreover, the signal processing device  30  comprises a multiplication unit  510 , which is arranged to multiply the sum generated by the adder unit  505  by a factor 1/cos(φ (i) ), wherein φ (i)  is a real-valued parameter. 
         [0104]    According to the embodiment illustrated in  FIG. 11 , the signal processing device  30  further comprises a multiplier unit  520 , which is arranged to multiply a signal w 1 (n) by a factor tan(φ (i) ). In case 1, the signal w 1 (n)=ja(n), and in case 2, w 1 (n)=b(n), as is illustrated in  FIG. 11 . Furthermore, the signal processing device  30  comprises adder units  515   a  and  515   b  which are adapted to generate a first compensated complex digital signal v (i) (n) as 
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         [0105]    A comparison between Eq. 32 and Eq. 30-31 provides a motivation for the structure of the block diagram in  FIG. 11 . Similar to the adaptive generation of filter parameters described with reference to  FIGS. 6-7  and  9 , the parameter φ (i)  and sample values of a g Δ   (i) (n) are adaptively generated in a number of iterations. Each iteration is identified below by the iteration index i. For the first iteration, wherein i=1, g Δ   (i) (n) may be a default impulse response and φ (i)  may be assigned a default value, such as g Δ   (i) (n)=0 and φ (i) =0. For subsequent iterations, i.e. for i&gt;1, g Δ   (i) (n) is given by g Δ   (i) (n)=g Δ   (i−1) (n)+Δ g   (i−1) (n) and φ (i)  is given by φ (i) =φ (i−1) +Δ φ   (i−1) , wherein Δ g   (i−1) (n) is an estimated impulse-response error of a preceding iteration and Δ φ   (i−1)  is an estimated phase-parameter error of the preceding iteration. Similar to the adaptive generation of filter parameters described with reference to  FIGS. 6-7  and  9 , the estimated impulse response error Δ g   (i) (n) and the estimated phase-parameter error Δ φ   (i)  are generated by minimizing a cost function based on 
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                                 w 
                                 2 
                               
                                
                               
                                 ( 
                                 
                                   n 
                                   - 
                                   k 
                                 
                                 ) 
                               
                             
                           
                           + 
                           
                             
                               Δ 
                               ϕ 
                               
                                 ( 
                                 i 
                                 ) 
                               
                             
                              
                             
                               
                                 w 
                                 1 
                               
                                
                               
                                 ( 
                                 
                                   n 
                                   - 
                                   k 
                                 
                                 ) 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                      
                     33 
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    The cost function based on u (i) (n) given by Eq. 33 may be based on a properness measure of u (i) (n) in the same way as for the adaptive generation of filter parameters described above with reference to  FIGS. 6-7  and  9 . 
         [0106]    Similar to the embodiments of the signal processing device  30  illustrated in  FIGS. 6 and 7 , the signal processing device  30  according to the embodiment illustrated in  FIG. 11  may be further adapted to generate a second compensated complex digital signal 
         [0000]    
       
         
           
             
               
                 y 
                 
                   ( 
                   i 
                   ) 
                 
               
                
               
                 ( 
                 n 
                 ) 
               
             
             = 
             
               
                 
                   v 
                   
                     ( 
                     i 
                     ) 
                   
                 
                  
                 
                   ( 
                   n 
                   ) 
                 
               
               + 
               
                 
                   ∑ 
                   
                     k 
                     ∈ 
                     K 
                   
                 
                  
                 
                   ( 
                   
                     
                       
                         
                           Δ 
                           g 
                           
                             ( 
                             i 
                             ) 
                           
                         
                          
                         
                           ( 
                           k 
                           ) 
                         
                       
                        
                       
                         
                           w 
                           2 
                         
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                           ( 
                           
                             n 
                             - 
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                           ) 
                         
                       
                     
                     + 
                     
                       
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                         ϕ 
                         
                           ( 
                           i 
                           ) 
                         
                       
                        
                       
                         
                           w 
                           1 
                         
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                           ( 
                           
                             n 
                             - 
                             k 
                           
                           ) 
                         
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    based on the generated Δ g   (i) (n) and Δ φ   (i) . For this purpose, the signal processing device  30  may comprise a filter unit  500   b  adapted to generate the signal 
         [0000]    
       
         
           
             
               
                 ∑ 
                 
                   k 
                   ∈ 
                   K 
                 
               
                
               
                 
                   
                     Δ 
                     g 
                     
                       ( 
                       i 
                       ) 
                     
                   
                    
                   
                     ( 
                     k 
                     ) 
                   
                 
                  
                 
                   
                     w 
                     2 
                   
                    
                   
                     ( 
                     
                       n 
                       - 
                       k 
                     
                     ) 
                   
                 
               
             
             , 
           
         
       
     
         [0000]    a filter unit  520   b  adapted to generate the signal 
         [0000]    
       
         
           
             
               
                 ∑ 
                 
                   k 
                   ∈ 
                   K 
                 
               
                
               
                 
                   Δ 
                   g 
                   
                     ( 
                     i 
                     ) 
                   
                 
                  
                 
                   
                     w 
                     1 
                   
                    
                   
                     ( 
                     
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                       - 
                       k 
                     
                     ) 
                   
                 
               
             
             , 
           
         
       
     
         [0000]    and adder units  525   a  and  525   b  arranged for the generation of y (i) (n), as illustrated in  FIG. 11 . 
         [0107]    This second compensated digital signal y (i) (n) may be the signal which is output on the output port  34 . In other embodiments, the signal v (i) (n) may instead be output on the output port  34 . In such embodiments, the filter units  500   b  and  520   b  and the adder units  525   a  and  525   b  may be omitted. 
         [0108]      FIG. 12  is a flow chart indicating how adaptive generation of Δ g   (i) (n) and Δ φ   (i)  can be performed according to an embodiment of the present invention, which is applicable to the embodiment of the signal-processing device  30  illustrated in  FIG. 11 . Similar to the flow chart in  FIG. 9 , the flow chart in  FIG. 12  illustrates one iteration of the iterative process described above with reference to  FIG. 11 . The iteration is started in step  530 . In step  535 , sample values of the finite-length real-valued impulse response g Δ   (i) (n) and the real-valued phase parameter φ (i) . For the first iteration, wherein i=1, g Δ   (i) (n) is generated as a default impulse response. For i&gt;1, g Δ   (i) (n) is given by g Δ   (i) (n)=g Δ   (i−1) (n)+Δ g   (i−1) (n). Similarly, for the first iteration, wherein i=1, the real-valued phase parameter φ (i)  is generated as a default value. For i&gt;1, φ (i)  is generated as φ (i) =φ (i−1) +Δ φ   (i−1) . In step  540 , the first compensated complex digital signal v (i) (n) is generated according to Eq. 32. Moreover, in step  545 , the estimated impulse response error Δ g   (i) (n) and the estimated phase-parameter error Δ φ   (i)  by minimizing said cost function based on u (i) (n) as defined by Eq. 33. The iteration may also comprise generating said second compensated digital signal y (i) (n). 
         [0109]    In some embodiments, the iterations for adaptively generating Δ g   (i) (n) and Δ φ   (i)  may be continually executed as long as the signal-processing device  30  is in operation. In other embodiments, the iterations may be terminated, or ended, when a certain stop condition for ending the iterations is fulfilled. Such a condition may e.g. be that the maximum value (over all n) of |Δ g   (i) (n)| is below a first threshold value and |Δ φ   (i) | is above a second threshold value. The threshold values may e.g. be selected based on a system specification, computer simulations and/or measurements, e.g. to achieve certain degree of image rejection required by the system specification or to fulfill some other criterion of system specification. Such operation may e.g. be performed in accordance with the flow chart in  FIG. 10  described above, with step  410  performed in accordance with the flow chart in  FIG. 12 . 
         [0110]    According to some embodiments of the present invention, there is provided means for compensating an imbalance between an I and a Q signal path of a quadrature transmitter arranged to transmit a radio-frequency signal r a (t) representing an uncompensated complex-valued digital signal z(n)=c(n)+jd(n), wherein c(n) is an uncompensated digital I component and d(n) is an uncompensated digital Q component d(n). 
         [0111]      FIG. 13  is a block diagram of a quadrature transmitter  600  according to an embodiment of the present invention. According to the embodiment, the quadrature transmitter  600  comprises an I signal path  605   a  and a Q signal path  605   b.  Furthermore, the quadrature transmitter  600  comprises a signal-processing device  610  for compensating an imbalance between the I signal path  605   a  and the Q signal path  605   b.  The signal-processing device  610  has an input port  615   a  for receiving the real-valued signal c(n) and an input port  615   b  for receiving the real-valued signal d(n). The signal-processing device  610  is adapted to generate a compensated complex-valued digital input signal y(n)={tilde over (c)}(n)+j{tilde over (d)}(n) based on the signal z(n). The signal {tilde over (c)}(n) is a compensated digital I component, and the signal {tilde over (d)}(n) is a compensated digital Q component. The signal processing device  610  is adapted to supply {tilde over (c)}(n) to an input port of the I signal path  605   a  via an output port  620   a  of the signal processing device  610 , and to supply {tilde over (d)}(n) to an input port of the Q signal path  605   b  via an output port  620   b  of the signal processing device  610 . 
         [0112]    A difference between the arrangement of the signal processing device  610  in the quadrature transmitter  600  and the arrangement of the signal-processing device  30  in the quadrature receiver  8  ( FIG. 2 ) is that, in the quadrature transmitter  600 , the signal-processing device  610  is arranged to compensate for the I/Q imbalance by means of so called pre-distortion, whereas in the quadrature receiver  8 , the signal processing device  30  is arranged to compensate for the I/Q imbalance by means of so called post-distortion. 
         [0113]    Furthermore, according to the embodiment illustrated in  FIG. 13 , the quadrature transmitter  600  comprises a first digital-to-analog converter (DAC)  625   a  in the I signal path  605   a,  and a second DAC  625   b  in the Q signal path  605   b,  for converting {tilde over (c)}(n) and {tilde over (d)}(n), respectively, to corresponding analog representations. Furthermore, the quadrature transmitter  600  further comprises a filter  630   a  and a filter  630   b  in the I signal path  605   a  and the Q signal path  605   b,  respectively. The filters  630   a  and  630   b  are arranged to suppress unwanted frequency components output from the DACs  625   a  and  625   b.  In  FIG. 13 , the filters  630   a  and  630   b  are illustrated as LP filters. However, in other embodiments, depending on the signal band used, the filters  630   a  and  630   b  may instead be BP filters. 
         [0114]    Moreover, the I signal path  605   a  comprises a mixer  635   a,  and the Q signal path  605   b  comprises a mixer  635   b.  The mixers  635   a  and  635   b  are adapted to receive the output signal from the filter  630   a  and the output signal from the filter  630   b,  respectively, on an input port. Furthermore, the quadrature receiver comprises an LO unit  640 , which is adapted to generate LO signals, having a common frequency f 0 , to the mixers  635   a  and  635   b.  Ideally, the LO signals supplied to the mixers  635   a  and  635   b  are provided in quadrature, i.e., ideally, there is a 90° (or π/2 radians) mutual phase shift between the LO signals. The mixers  635   a  and  635   b  are arranged to perform frequency up conversion of their respective input signals to an RF signal frequency band. In addition, the quadrature transmitter  600  comprises an analog adder circuit  645  for generating an RF output signal r a (t) as the sum of the output signals from the mixers  635   a  and  635   b.  The RF signal r a (t) is output on an output port  650  of the quadrature transmitter  600 . 
         [0115]      FIG. 14  is a block diagram of a model of the quadrature transmitter  600 , except for the signal processing device  610 . The DACs  625   a  and  625   b  ( FIG. 13 ) are modeled with ideal DACs  655   a  and  655   b.  The filters  630   a  and  630   b  ( FIG. 13 ) are modeled with the blocks  660   a  and  660   b,  respectively, having impulse responses h a1 (t) and h a2 (t), as indicated in  FIG. 3 . Any gain mismatch between and (linear) dynamic behavior of the DACs  625   a  and  625   b  are lumped into the blocks  660   a  and  660   b  in the model of  FIG. 14 . 
         [0116]    The mixers  635   a  and  635   b,  and the LO  640  ( FIG. 13 ) are modeled with the multipliers  665   a  and  665   b  multiplying the output signals of the blocks  660   a  and  660   b  by 2 cos(ω 0 t+ω 1 ) and −2 sin(ω 0 t+ω 2 ), respectively, where ω 0  is 2πf 0 . With balanced I and Q signal path, φ 1 =φ 2 . The adder unit  645  ( FIG. 13 ) is modeled with the adder  670 . A difference between φ 1  and φ 2  results in an imbalance between the I and Q signal paths. Furthermore, a difference between h a1 (t) and h a2 (t) also contributes to the imbalance between the I and Q signal paths. 
         [0117]    In the following derivation, {tilde over (c)} a (t) and {tilde over (d)} a (t) denote the analog signals corresponding to {tilde over (c)}(n) and {tilde over (d)}(n), respectively. It can be shown that the signal r a (t) can be written on the form 
         [0000]        r   a ( t )=( c   1 ( t ) e   jφ     1     +d   1 ( t ) e   jφ     2   ) e   jω     0     t   +j ( c   1 ( t ) e   −jφ     1     −d   1 ( t ) e   −jω     0     t ,   (Eq. 34)
 
         [0000]    where c 1 (t)={tilde over (c)} a (t)*h 1 (t) and d 1 (t)={tilde over (d)} a (t)*h 2 (t). Furthermore, let x(n) denote an equivalent unbalanced discrete-time baseband signal. That is, x(n) denotes a complex-valued signal which, when input to a (hypothetical) perfectly balanced quadrature transmitter, would result in the output signal r a (t). It can be shown that x(n) can be written on the form 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       x 
                        
                       
                         ( 
                         n 
                         ) 
                       
                     
                     = 
                     
                       
                         
                           
                             g 
                             1 
                           
                            
                           
                             ( 
                             n 
                             ) 
                           
                         
                          
                         
                           y 
                            
                           
                             ( 
                             n 
                             ) 
                           
                         
                       
                       + 
                       
                         
                           
                             g 
                             2 
                           
                            
                           
                             ( 
                             n 
                             ) 
                           
                         
                          
                         
                           
                             y 
                             * 
                           
                            
                           
                             ( 
                             n 
                             ) 
                           
                         
                       
                     
                   
                   , 
                   
                     
 
                   
                    
                   wherein 
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                      
                     35 
                   
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         g 
                         1 
                       
                        
                       
                         ( 
                         n 
                         ) 
                       
                     
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                               1 
                             
                           
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                               1 
                             
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                               ( 
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                               ) 
                             
                           
                         
                         + 
                         
                           
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                               2 
                             
                           
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                               2 
                             
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                               ) 
                             
                           
                         
                       
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                   and 
                 
               
               
                 
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                     . 
                     
                         
                     
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                     36 
                   
                   ) 
                 
               
             
             
               
                 
                   
                     
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                       2 
                     
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                       ( 
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                              
                             
                               jϕ 
                               1 
                             
                           
                            
                           
                             
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                               1 
                             
                              
                             
                               ( 
                               n 
                               ) 
                             
                           
                         
                         - 
                         
                           
                              
                             
                               jϕ 
                               2 
                             
                           
                            
                           
                             
                               h 
                               2 
                             
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                               ( 
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                     . 
                   
                 
               
               
                 
                   ( 
                   
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                     . 
                     
                         
                     
                      
                     37 
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    In Eq. 36 and Eq. 37, h 1 (n) and h 2 (n) denote the discrete-time impulse responses corresponding to the continuous-time impulse responses h a1 (t) and h a2 (t), respectively. 
         [0118]    Similarly to the receiver case, two different cases, denoted case 1 and case 2, are considered in the transmitter case as well. According to case 1, generating y(n) according to 
         [0000]        y ( n )= z ( n )+ f ( n )* c ( n ),   (Eq. 38)
 
         [0000]    wherein f(n) is a complex-valued impulse response 
         [0000]        f ( n )= e   jφ   h ( n )−δ( n ),   (Eq. 39)
 
         [0000]        h ( n )* h   1 ( n )= h   2 ( n ),   (Eq. 40)
 
         [0000]      and 
         [0000]      φ=φ 2 −φ 1    (Eq. 41)
 
         [0000]      results in 
         [0000]        x ( n )= e   jφ     2     h   2 ( n ) z ( n ).   (Eq. 42)
 
         [0119]    Similarly, according to case 2, generating y(n) according to 
         [0000]        y ( n )= z ( n )+ f ( n )* jd ( n ),   (Eq. 43)
 
         [0000]    wherein f(n) is a complex-valued impulse response 
         [0000]        f ( n )= e   jφ   h ( n )−δ( n ),   (Eq. 44)
 
         [0000]        h ( n )* h   2 ( n )= h   1 ( n ),   (Eq. 45)
 
         [0000]      and 
         [0000]      φ=φ 1 −φ 2    (Eq. 46)
 
         [0000]      results in 
         [0000]        x ( n )= e   jφ     1     h   1 ( n ) z ( n ).   (Eq. 47)
 
         [0120]    As can be seen from Eq. 41 and 47, generating y(n) according to Eq. 38 or Eq. 44 results in an x(n) that is a linearly distorted version of z(n). Such linear distortion can e.g. be compensated for by a linear equalizer in a receiver arranged to receive the signal r a (t) transmitted from the quadrature transmitter  600 . 
         [0121]    From Eq. 38-Eq. 47, it can be deduced that the same structures that are used for the signal-processing device  30  in  FIGS. 4-7  in the receiver case can be utilized for the signal-processing device  610  in the transmitter case. The corresponding figures for the transmitter case can be obtained by 
         [0122]    replacing the input port  32  with a compound input port  615  comprising the input ports  615   a  and  615   b  of the signal processing device  610 ; 
         [0123]    replacing x(n) with z(n); 
         [0124]    replacing a(n) with c(n); 
         [0125]    replacing jb(n) with jd(n); and 
         [0126]    replacing the output port  34  with a compound output port  620  comprising the output ports  620   a  and  620   b  of the signal processing device  610 ; in  FIGS. 4-7 . The above replacements are indicated within square brackets in  FIGS. 4-7 .  FIGS. 4-7  are not described in any further detail for the transmitter case. 
         [0127]    Consequently, according to embodiments of the present invention, there is provided method for compensating the imbalance between the I and the Q signal path  605   a  and  605   b  of the quadrature transmitter  600 . Embodiments of the method are described below with reference to the flow charts in  FIGS. 8-10 , with suitable modifications to account for the differences between the transmitter and receiver cases. According to an embodiment of the method, with reference to  FIG. 8 , the method is started in step  200 . In step  205 , the uncompensated complex digital signal z(n)=c(n)+jd(n) is received, e.g. on the input ports  615   a  and  615   b  ( FIG. 13 ). Furthermore, in step  210 , a complex compensation signal is generated by filtering one of c(n) (case 1) and jd(n) (case 2) with a compensation filter having a complex-valued impulse response. Step  210  may e.g. be performed by the compensation filter  60  ( FIG. 4 ), the elements  70 - 85  ( FIG. 5 ) described above as performing the function of the compensation filter  60  ( FIG. 4 ), the compensation filter  160   a  ( FIG. 6 ), or the elements  170   a,    175 ,  180   a,  and  185   a  ( FIG. 7 ) described above as performing the function of the compensation filter  160   a  ( FIG. 6 ). Furthermore, in step  215 , a first compensated complex digital signal is generated as the sum of z(n) and the complex compensation signal. Said first compensated complex digital signal may be the signal y(n) in  FIGS. 4 and 5 , or the signal v (i) (n) in  FIGS. 6 and 7 . The method is ended in step  220 . 
         [0128]    The method may further comprise adaptively generating filter parameters of the compensation filter. Adaptively generating filter parameters of the compensation filter may e.g. comprise adaptively generating the complex-valued samples of the impulse response f(n) ( FIG. 4 ) or adaptively generating the real-valued samples of the impulse response h Δ (n) and the real-valued parameter φ ( FIG. 5 ). The adaptive generation of filter parameters may e.g. be performed using the general methods described in the Antilla transmitter paper referred to above in the “Background” section. 
         [0129]    For the embodiments of the signal processing device  610  illustrated in  FIGS. 6 and 7 , the adaptive generation of filter parameters may be performed in an iterative process similar to that described for the corresponding embodiments of the signal processing device  30 . However, a different cost function may be used. As in the Antilla transmitter paper, real down conversion (as opposed to quadrature (or complex) down conversion) of the signal r a (t), followed by analog-to-digital conversion, may be utilized to generate a real-valued signal r BB (n), which can be used as a basis for the cost function. For example, in addition to r BB (n), a signal q BB (n) may be generated, which corresponds to the signal that would have resulted from real downconversion of a radio-frequency signal generated by inputting the signal z(t) to a quadrature transmitter having no imbalance between the I and Q signal paths. The cost function may be based on a difference between r BB (n) and q BB (n). For example, the cost function may be based on an L 2  norm or L ∞  norm of said difference. Similar to the cost function in the receiver case, the cost function may be a linear cost function in the filter parameters to be estimated. For example, the linear cost function may be obtained as a linearization of a nonlinear cost function, such as said L 2  noun or L ∞  norm. 
         [0130]    According to an embodiment, an iteration of said iterative process may be performed in accordance with the flow chart shown in  FIG. 9  (showing one iteration). The iteration is started in step  300 . In step  305 , filter parameters for attaining the impulse response f (i) (n), wherein f (i) (n) is a default impulse response for the first iteration, wherein i=1, and f (i) (n) is based on f (i−1) (n) and Δ (i−1) (n) for i&gt;1. Furthermore, in step  310 , the complex compensation signal, denoted e (i) (n), is generated as e (i) (n)=f (i) (n)*w(n), wherein w(n) denotes c(n) (case 1) or jd(n) (case 2). Moreover, in step  315 , the first compensated complex digital signal v (i) (n) is generated as v (i) (n)=z(n)+e (i) (n). In addition, the filter parameters determining Δ (i) (n) are generated in step  320  by minimizing a cost function based on r BB (n). The iteration is ended in step  320 . In some embodiments, the iteration may also comprise generating a second compensated complex digital signal y (i) (n)=v (i) (n)+Δ (i) (n)*w(n) based on the generated Δ (i) (n) as described in the context of  FIGS. 6-7 . 
         [0131]    Similar to the receiver case, step  305  may comprise generating the samples of f (i) (n). Furthermore, step  320  may comprise generating the samples of Δ (i) (n). 
         [0132]    In some embodiments, the impulse response f (i) (n) may be on the form: f (i) (n)=h Δ   (i) (n)+jφ (k) δ(n)+jφ (i) h Δ   (i) (n)+(e jφ     (i)   −1−jφ (i) )·(δ(n)+h Δ   (i) (n)). Furthermore, Δ (i) (n) may be on the form Δ (i) (n)=Δ h   (i) (n)+jΔ φ   (i)  for n belonging to a finite set of integers, for which h Δ   (i) (n) can adopt nonzero values, and Δ (i) (n)=0 outside said finite set of integers. Δ φ   (i)  is a real-valued parameter and Δ h   (i) (n) is a real-valued sequence. Step  320  may comprises generating the real-valued parameter Δ φ   (i)  and the real-valued sequence Δ h   (i) (n). Furthermore, step  305  may comprise generating the real-valued sequence h Δ   (i) (n) as h Δ   (i) (n)=h Δ   (i−1) (n)+Δ h   (i−1) (n) and the real-valued parameter φ (i)  as φ (i) =φ (i−1) +Δ φ   (i−1)  for i&gt;1. 
         [0133]    In some embodiments, the iterations for adaptively generating filter parameters may be continually executed as long as the signal-processing device  610  is in operation. In other embodiments, the iterations may be terminated, or ended, when a certain stop condition for ending the iterations is fulfilled. Such a condition may e.g. be that the maximum value (over all n) of |Δ (i) (n)| is below a threshold value. The threshold value may e.g. be selected based on a system specification, computer simulations and/or measurements, e.g. to achieve certain degree of image rejection required by the system specification or to fulfill some other criterion of system specification. 
         [0134]    Similar to the receiver case, such operation is illustrated by the flow chart in  FIG. 10 . In Step  400 , the operation is started. In step  405 , it is determining whether the stop condition is fulfilled. If the stop condition is not fulfilled, the filter parameter generation is iterated once more in step  410 . Step  410  may e.g. be performed in accordance with the flow chart in  FIG. 9 . If the stop condition is fulfilled, the iterations are ended and compensation of the imbalance between the I signal path  605   a  and the Q signal path  605   b  based on filter parameters generated in the last iteration is continued in step  415 . 
         [0135]    According to embodiments of the present invention, an electronic apparatus may comprise the quadrature receiver  8  and/or the quadrature transmitter  600 . This is schematically illustrated in  FIG. 15 , showing an electronic apparatus  700  comprising the quadrature receiver  8  and the quadrature transmitter  600 . For example, the electronic apparatus may comprise a transceiver (not shown), which in turn comprises the quadrature receiver  8  and/or the quadrature transmitter  600 . The electronic apparatus may e.g. be, but is not limited to a mobile communication terminal or a radio base station. 
         [0136]    It is an advantage of embodiments of the present invention described herein that compensation of imbalance between I and Q signal paths of a quadrature receiver or a quadrature transmitter can be accomplished with the same performance, in terms of image attenuation, as for the compensation circuit  1  illustrated in  FIG. 1 , but at a lower computational complexity. The lower computational complexity in turn results in a smaller amount of required computational resources, compared with the compensation circuit illustrated in  FIG. 1 . This can be utilized to reduce the required circuit area and/or the power consumption, compared with the compensation circuit illustrated in  FIG. 1 . 
         [0137]    In some embodiments, the signal processing device  30  ( FIGS. 2-7  and  11 ) and/or the signal processing device  610  ( FIGS. 3-7  and  13 ) may be implemented as dedicated application-specific hardware units. Alternatively, said signal processing device  30  or  610 , or parts thereof, may be implemented with programmable and/or configurable hardware units, such as but not limited to one or more field-programmable gate arrays (FPGAs), processors, or microcontrollers. Hence, embodiments of the present invention may be embedded in a computer program product, which enables implementation of the method and functions described herein, e.g. the embodiments of the methods described with reference to  FIGS. 8-10  and  12 . Therefore, according to embodiments of the present invention, there is provided a computer program product, comprising instructions arranged to cause a programmable hardware unit with processing capabilities, such as the aforementioned one or more processors or micro controllers, to perform the steps of any of the embodiments of said methods. The computer program product may comprise program code which is stored on a computer readable medium  720 , as illustrated in  FIG. 16 , which can be loaded and executed by a programmable hardware unit  730  having processing capabilities, to cause it to perform the steps of any of the embodiments of said methods. The programmable hardware unit  730  having processing capabilities is preferably what normally is referred to as an embedded system of suitable format for integration within the signal processing device  30  or  610 . 
         [0138]    The signal processing device  30  ( FIGS. 2-7  and  11 ) and/or the signal processing device  610  ( FIGS. 3-7  and  13 ) may be fabricated by means of computer-aided fabrication. For example, in the case the signal processing device  30  or  610 , or parts thereof, is implemented as an application-specific hardware unit in an IC, lithography masks for the fabrication of the signal processing device  30  or  610  may be fabricated by means of computer-aided fabrication based on hardware-description code describing a physical circuit layout of the signal processing device  30  or  610 , such as but not limited to hardware-description code in the commonly used gdsII file format. Hardware description code describing a physical circuit layout may be computer generated, e.g. by means of synthesis and/or place-and-route computer program tools from another hardware-description code, such as but not limited to hardware-description code on a register-transfer level (RTL), or hardware description code in e.g. VHDL (VHSIC (Very-High-Speed Integrated Circuits) Hardware-Description Language), Verilog, or SystemC, or a combination thereof. Such hardware-description code may also be synthesized for configuring a configurable hardware unit, such as but not limited to an FPGA, to perform the functionality of the signal processing device  30  or  610 . Other hardware-description languages than those listed above exist and the listed languages should not be interpreted as exhaustive or as limiting the invention. 
         [0139]    Accordingly, in accordance with embodiments of the present invention, there is provided a hardware-description entity comprising computer-interpretable hardware-description code describing the signal processing device  30  or  610  and enabling computer-aided fabrication thereof as an application-specific hardware unit, through configuration of a configurable hardware unit, or a combination thereof. 
         [0140]    The hardware-description entity may comprise a file or a set of files comprising the hardware-description code. The file or set of files may e.g. be stored on a computer-readable medium, such as the computer-readable medium  720  ( FIG. 16 ). 
         [0141]    The present invention has been described above with reference to specific embodiments. However, other embodiments than the above described are possible within the scope of the invention. Different method steps than those described above, performing the method by hardware or software, may be provided within the scope of the invention. The different features and steps of the embodiments may be combined in other combinations than those described. The scope of the invention is only limited by the appended patent claims.

Technology Classification (CPC): 7