Patent Abstract:
A voltage ramp generator includes a capacitance and a charging circuit that permits generation of a charging current for the capacitance. The charging circuit for the capacitance includes a current generator having a resistance Rg 2.  The charging circuit for the capacitance includes components, such as resistance Re, that enables the capacitance charging current to be proportional to (Re/Rg 2 ) 2 . The voltage ramp generator is applicable to circuits for DC voltage converters operating in a current mode.

Full Description:
FIELD OF THE INVENTION 
   The present invention relates to a voltage ramp generator, and to a current ramp generator that converts the voltage ramp generator into the current ramp generator. The present invention has a particularly advantageous application for DC voltage converters operating in a current mode, for example. 
   BACKGROUND OF THE INVENTION 
   Circuits for DC voltage converters operating in a current mode include a regulation circuit that includes a current ramp generator necessary to stabilize the regulation circuit. It is therefore necessary for the current ramp generator to have only slight component and temperature variations. 
   A current ramp generator in accordance with the prior art is shown in  FIG. 1 . The current ramp generator is made up of a voltage ramp generator circuit and a circuit that enables the voltage ramp to be converted into a current ramp. The voltage ramp generator circuit is made up of a current generator Ig 1  and a capacitance C. The current Ig 1  charges the capacitance C in accordance with the equation: 
           Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t       =       1   C     ×   Ig1         
 
   where Vc is the voltage at the terminals of the capacitance C. 
   As is known to those skilled in the art, the current Ig 1  can be written as: 
       Ig1   =     K1   ×     Vg1   Rg1           
 
   where Vg 1  is a reference voltage such as a Bandgap voltage, for example, and Rg 1  is the resistance of the current generator, and K 1  is a proportionality coefficient. 
   The circuit permits the conversion of the voltage ramp into a current ramp, and is made up of an operational amplifier A, three transistors T 1 , T 2 , T 3  and a resistance Rs. The operational amplifier A includes a first input (e−), a second input (e+) and an output. The transistor T 1  is a N-type MOS transistor including a gate, a source and a drain, and the transistors T 2  and T 3  are P-type MOS transistors, each including a gate, a source and a drain. 
   The first input (e−) of the operational amplifier A is connected to the source of the transistor T 1 . The gate of which is connected to the output of the operational amplifier A, and the drain is connected to the drain of transistor T 2 . The second input (e+) of the operational amplifier A is connected to the first terminal of the capacitance C. The second terminal the capacitance C is connected to ground. The source of transistor T 1  is connected to the first terminal of the resistance Rs, and the second terminal of which is connected to ground. 
   The transistors T 2  and T 3  are assembled as a current mirror. The source of transistor T 2  is connected to a supply voltage V+. The drain and the gate of transistor T 2  are connected to one another and to the gate of transistor T 3 . The source of transistor T 3  is connected to the supply voltage V+, and the drain is connected to the circuit (not shown in the figure) which collects the current Is. Variation of the current Is is in relation to time which forms the current ramp. 
   In a known way, the variation of the current Is in relation to time is given by the equation: 
           Δ   ⁢           ⁢   Is       Δ   ⁢           ⁢   t       =       1   C     ×     Vg1   Rg1     ×   K1   ×     1   Rs           
 
   It follows that the variation of the gradient ΔIs/Δt depends directly on the variations of resistances Rg 1  and Rs and of the capacitance C. The resistances Rg 1  and Rs can have a spread on the order of ±20%. These spreads are then reflected in the current ramp on the order of ±40%. 
   Prior approaches for correcting the current ramp spreads include adjusting the resistance Rs. It is then necessary to use a sequence of tests to adjust the value of resistance Rs. Provision is thus made to use fuse type memory points to adjust the ramp of each circuit. This adjustment is a tedious operation. Furthermore, the design of the resistance Rs produced as a combination of fuses requires a relatively large area of the circuit. 
   In addition, resistances Rg 1  and Rs have temperature variations. These variations also have an impact on the current ramp. Since the adjustment of resistance Rs is only valid at the temperature at which it is carried out, the temperature dependence is not corrected. 
   BACKGROUND OF THE INVENTION 
   In view of the foregoing background, the present invention does not have the above described disadvantages. In effect, the invention relates to a voltage ramp generator comprising a capacitance and a charging circuit that permits the generation of a charging current for the capacitance. The charging circuit for the capacitance comprises a current generator of resistance Rg 2 . The charging circuit for the capacitance includes means that permit the charging current for the capacitance to be proportional to (Re/Rg 2 ) 2 , where Re is a resistance. 
   According to one particularly advantageous embodiment of the invention, the means that permit the charging current for the capacitance to be proportional to the quantity (Re/Rg 2 ) 2  comprises a degenerate current mirror. The term degenerate current mirror is used to mean a current mirror whose current ratio is not equal to the ratio of the surface areas of the MOS transistors that makes it up. 
   The invention also relates to a current ramp generator comprising a voltage ramp generator and a circuit that permits the conversion of the voltage ramp to a current ramp. The voltage ramp generator is a voltage ramp generator such as the one mentioned above. 
   According to the preferred embodiment of the invention, the components forming the voltage ramp generator and the current ramp generator are produced using CMOS technology The invention also relates to where the components are produced using a different technology, such as bipolar technology, for example. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other characteristics and advantages of the invention will become apparent on reading a description of a preferred embodiment of the invention made making reference to the appended figures among which: 
       FIG. 1  shows a current ramp generator according to the prior art, 
       FIG. 2  shows a voltage ramp generator according to the preferred embodiment of the present invention, and 
       FIG. 3  shows a current ramp generator according to the preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In all the figures, the same reference numbers designate the same components.  FIG. 2  represents a voltage ramp generator according to the preferred embodiment of the present invention. The voltage ramp generator circuit includes a current generator Ig 2 , a resistance Re, a capacitance C and two P-type MOS transistors T 4  and T 5  each comprising a gate, a drain and a source. 
   The transistor T 4  has its source connected to a first terminal of the resistance Re, the second terminal of which is connected to a supply voltage V+. The drain and the gate of transistor T 4  are connected to a first terminal of the current generator Ig 2 , the second terminal of which is connected to ground. The transistor T 5  has its gate connected to the gate of transistor T 4 , its source connected to the supply voltage V+ and its drain connected to a first terminal of the capacitance C. The second terminal of the capacitance C is connected to ground. 
   Preferably, the substrate effect is suppressed on transistors T 4  and T 5 , and the voltage threshold Vth 4  of transistor T 4  is equal to the voltage threshold Vth 5  of transistor T 5 . Current Ig 2  passes through the resistance Re. Therefore, it follows that:
 
 Re×Ig   2   +VGST   4   −Vth   4 = VGST   5 − Vth   5 ,
 
   where VGST 4  is the gate/source voltage of transistor T 4  and VGST 5  is the gate/source voltage of transistor T 5 . 
   According to the invention, the resistance Re is chosen in such a way that:
 
 Re×Ig   2 &gt;&gt; VGST   4 − Vth   4 ,
 
   It follows therefore:
 
 VGST   5 − Vth   5 ≈ Re×Ig   2 ,
 
   In CMOS technology, the current which passes through the transistor T 5  is written as: 
           I   T5     =         μ   ×   Cox     2     ×     W   L     ×       (       V   GST5     -   Vth5     )     2         ,       
 
where μ is the mobility of the carriers, Cox is the gate capacitance of the transistor T 5 , W is the channel width of transistor T 5 , L is the channel length of transistor T 5 .
 
   It follows, therefore, that: 
           I   T5     =         μ   ×   Cox     2     ×     W   L     ×       (     Re   ×   Ig2     )     2         ,       
 
The current Ig 2  can be written as: 
         Ig2   =     K2   ×     Vg2   Rg2         ,       
 
where Vg 2  is a reference voltage, Rg 2  is the resistance of the current generator and K2 is a proportionality coefficient.
 
   Preferably, the voltage Vg 2  is proportional to the quantity 
         k   ⁢     T   q       ,       
 
where k is the Boltzmann constant, T is absolute temperature and q is the charge of an electron.
 
   It follows, therefore, that: 
         I   T5     =         μ   ×   Cox     2     ×     W   L     ×       (     Re   Rg2     )     2     ×     K2   2     ×       Vg2   2     .           
 
   The current IT 5  is the current which charges the capacitance C. The equation which translates the charge of the capacitance C is written as: 
           Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t       =       1   C     ×       μ   ×   Cos     2     ×     W   L     ×       (     Re   Rg2     )     2     ×     K2   2     ×       Vg2   2     .           
 
   The presence of the resistance Re advantageously permits compensation for the variations of the resistance Rg 2 . The resistances Re and Rg 2  are chosen to be of the same type of technology, thereby allowing compensation for their spreads. 
   It is then possible, for example, to obtain a variation of the gradient 
         Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t         
 
on the order of ±25% for a variation of resistances Rg 2  and Re, each on the order of ±40% in total. The resistance Re is preferably chosen with a temperature variation coefficient of the same order of magnitude as that for the resistance Rg 2 . It is then possible to compensate for variations in temperature due to the resistance Rg 2 . Preferably, as has been previously mentioned, the voltage Vg 2  is proportional to the quantity 
       k   ⁢       T   q     .         
 
The mobility of the carriers varies proportionately to T −3/2 . It follows that the voltage ramp 
         Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t         
 
varies proportionately to T 1/2 .
 
     FIG. 3  shows a current ramp generator according to the preferred embodiment of the invention. The current ramp generator includes a voltage ramp generator circuit such as that described in  FIG. 2 , and a circuit that allows the voltage ramp to be converted into a current ramp. 
   The circuit allowing the conversion of the voltage ramp into a current ramp is made up of operational amplifier A, three transistors T 1 , T 2 , T 3  and a resistance Rs. The three transistors T 1 , T 2 , T 3  and the resistance Rs are connected as shown in  FIG. 1 . Similarly, the first input (e−) of the operational amplifier A is connected to the source of transistor T 1 , the gate of which is connected to the output of the operational amplifier. The second input (e+) of the operational amplifier A is connected to a first terminal of the capacitance C. The second terminal of the capacitance C is connected to ground. 
   Since Is is the current passing through transistor T 3 , the current ramp 
         Δ   ⁢           ⁢   Is       Δ   ⁢           ⁢   t         
 
is written as: 
             Δ   ⁢           ⁢   Is       Δ   ⁢           ⁢   t       =       1   Rs     ×       Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t           ,       
 
   where 
         Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t         
 
is the voltage ramp such as that calculated in the description of  FIG. 2 . Hence, all the advantages described for the voltage ramp generator circuit in  FIG. 2  are also advantages that relate to the current ramp generator according to the invention.
 
   As has already been previously mentioned, the voltage ramp 
         Δ   ⁢           ⁢   Vc       Δ   ⁢           ⁢   t         
 
varies with temperature according to T 1/2 .
 
   In accordance with the preferred embodiment of the invention, the resistance Rs is an implanted N-type resistance with a positive temperature variation coefficient that enables the temperature variation of the current ramp to vary according to T n , where n is less than 
         1   2     .       
 
To reduce the effect of component variations on the ramp, the capacitance C is the gate capacitance of a MOS transistor, the spread of which compensates for the spread of transistor T 5 .

Technology Classification (CPC): 7