Patent Abstract:
A display device includes a first substrate including an active area, a bending area, and a pad area; a plurality of pixels to display an image in the active area, each of the plurality of pixels including an organic light emitting diode (OLED); a signal line and a power line disposed on the first substrate, the signal line and the power ling being disposed on a same layer in the bending area, the bending area on the first substrate being configured to be bent flexibly; and a second substrate facing the active area and disposed on the first substrate.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Continuation of co-pending U.S. patent application Ser. No. 14/572,232 filed on Dec. 16, 2014, which claims the benefit under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2013-0169271 filed on Dec. 31, 2013, all of which are hereby expressly incorporated by reference into the present application. 
     
    
     BACKGROUND OF THE DISCLOSURE 
     Field of the Invention 
       [0002]    The present disclosure relates to a flexible display device, and particularly, to a flexible display device capable of preventing disconnection or short-circuiting of wires that may occur at a bending area during a bending process for a minimized bezel width, in an organic light-emitting diode display manufactured using a flexible substrate, and a method for fabricating the same. 
       Discussion of the Related Art 
       [0003]    Among flat panel display devices proposed to replace the conventional cathode ray tube, an organic light-emitting diode (OLED) display has a characteristic that a light-emitting diode provided at a display panel has high brightness and a low operation voltage. Such OLED display has advantages that a contrast ratio is large because it is a spontaneous light-emission type, and a very thin display can be implemented. The OLED display can easily implement moving images because a response time is several micro seconds (μs). Further, the OLED display has an unlimited viewing angle, and is stably operated even at a low temperature. 
         [0004]    In the OLED display device, display devices are formed on a substrate such as glass. Recently, a flexible organic light-emitting diode (OLED) display device, which is capable of maintaining a display function even when rolled (or bent) like paper due to its flexible material such as plastic or metal foil rather than a non-flexible substrate, has been developed. 
         [0005]      FIG. 1  is a planar view schematically illustrating a flexible organic light-emitting diode (OLED) display device in accordance with the conventional art, and  FIG. 2A  is an enlarged view of part ‘A’ in  FIG. 1 . 
         [0006]    Referring to  FIGS. 1 and 2A , the conventional flexible OLED display device  1  is formed on a flexible substrate  10  including an active area (A/A) and a non-active area (N/A). 
         [0007]    The active area (A/A) is a region where an image is substantially displayed. A plurality of pixels (P) are arranged in the active area (A/A), in the form of matrices. Each of the pixels (P) includes a switching transistor (ST 1 ), a driving transistor (DT), a sensing transistor (ST 2 ), a capacitor (C), and an organic light-emitting diode (OLED). 
         [0008]    The switching transistor (ST 1 ) of the pixel (P) is connected to a gate line (GL) and a data line (DL) which are formed in the active area (A/A) so as to cross each other. The driving transistor (DT) is connected to a driving voltage line  14   b  for supplying a driving voltage (VDD) to the pixel (P) in the active area (A/A). The sensing transistor (ST 2 ) is connected to a reference voltage line  14   a  for supplying a reference voltage (Vref) to the pixel (P) in the active area (A/A). 
         [0009]    The non-active area (N/A) is a region formed around the active area (A/A), and is covered by a bezel portion, etc. Driving circuitry for driving the pixels (P) in the active area (A/A) and wires may be formed in the non-active area (N/A). 
         [0010]    The driving circuitry includes a data driving portion  20 , a gate driving portion  13  and a light-emitting controller (not shown). The data driving portion  20  is mounted at a lower end non-active area (N/A) in the form of a chip. The gate driving portion  13  and the light-emitting controller are formed at one or more sides of the non-active area (N/A), in the form of a gate in panel (GIP). 
         [0011]    Wires include power lines  14   a - 14   c , and signal lines GSL, DSL. The power lines  14   a - 14   c  includes a driving voltage line  14   a , a reference voltage line  14   b  and a ground line  14   c . Also, the signal lines GSL, DSL include a gate signal line (GSL), a data signal line (DSL) and a light-emitting signal line (not shown). 
         [0012]    The driving voltage line  14   a  outputs a driving voltage (VDD) provided from the data driving portion  20  to the pixel (P) in the active area (A/A). The reference voltage line  14   b  outputs a reference voltage (Vref) provided from the data driving portion  20  to the pixel (P) in the active area (A/A). The ground line  14   c  outputs a ground voltage (GND) provided from the data driving portion  20  to the pixel (P) in the active area (A/A). 
         [0013]    The driving voltage line  14   a , the reference voltage line  14   b  and the ground line  14   c  include a region vertically extending from the data driving portion in the lower end non-active area (N/A), and a region formed in parallel to the data driving portion  20 . 
         [0014]    That is, the driving voltage line  14   a , the reference voltage line  14   b  and the ground line  14   c  are extending from the data driving portion  20  in a vertical direction, at a region adjacent to the data driving portion  20  in the lower end non-active area (N/A). The driving voltage line  14   a , the reference voltage line  14   b  and the ground line  14   c  are formed as bars, in parallel to the data driving portion  20 , at a region adjacent to the active area (A/A) in the lower end non-active area (N/A). 
         [0015]    The gate signal line (GSL) outputs a gate signal provided from the data driving portion  20  to the gate driving portion  13 . The data signal line (DSL) outputs a data signal provided from the data driving portion  20  to the data line (DL) in the active area (A/A). The light-emitting signal line outputs a light-emitting signal provided from the data driving portion  20  to the light-emitting controller. 
         [0016]    In accordance with one embodiment, these wires may be formed to cross each other at least once, in the lower end non-active area (N/A). Thus, the power lines  14   a - 14   c  and the signal lines GSL, DSL are formed on different layers, in order to prevent short-circuiting when the wires cross each other. 
         [0017]    In the conventional flexible OLED display device  1 , the lower end non-active area (N/A) is formed to have a larger width than the rest of the non-active area (N/A). A bending area (B/A) is formed in the lower end non-active area (N/A), and part of the lower end non-active area (N/A) is bent to a rear surface of the flexible OLED display device  1 . Under such configuration, the width of the lower end non-active area (N/A) can be reduced. 
         [0018]      FIG. 2B  is a cross-sectional view of the flexible OLED display device of  FIG. 1 , which illustrates a bent state. 
         [0019]    Referring to  FIG. 2B , reference numeral  11  denotes an organic light-emitting diode (OLED) formed in an active area (A/A), and reference numeral  12  denotes an encapsulation layer for encapsulating an OLED. 
         [0020]    Referring to  FIG. 2B , in the conventional flexible OLED display device  1 , the lower end non-active area (N/A) is bent based on a bending area (B/A), so that part of the lower end non-active area (N/A) can be positioned on a rear surface of the flexible OLED display device  1 . A curvature radius (R) of the bending area (B/A) is about 0.3 mm. 
         [0021]    As mentioned above with reference to  FIG. 2A , in the lower end non-active area (N/A) of the conventional flexible OLED display device  1 , wires are formed to cross each other. Thus, the power lines  14   a - 14   c  and the signal lines GSL, DSL are formed on different layers. 
         [0022]    However, because the wires are formed to cross each other even in the bending area (B/A), the wires may be disconnected from each other due to bending stress in the bending area (B/A). 
         [0023]      FIG. 3  is a cross-sectional view taken along line in  FIG. 2B . 
         [0024]    Referring to  FIG. 3 , the signal lines GSL, DSL and the power lines  14   a - 14   c  are formed on different layers to thus be insulated from each other. 
         [0025]    For instance, a gate signal line (GSL) and a data signal line (DSL) are formed on a flexible substrate  10  with a distance therebetween. A first insulating layer  15  is formed on the gate signal line (GSL) and the data signal line (DSL). 
         [0026]    A driving voltage line  14   a  and a ground line  14   c  are formed on the first insulating layer  15  with a predetermined gap therebetween. The driving voltage line  14   a  and the ground line  14   c  are formed to overlap the gate signal line (GSL) and the data signal line (DSL), respectively. A second insulating layer  16  is formed on the driving voltage line  14   a  and the ground line  14   c.    
         [0027]    When the bending area (B/A) is bent with more than a predetermined curvature radius, cracks/breaks may occur at wires due to bending stress as shown in  FIG. 3  (indicated by “a” and “b”). This may cause the wires to be disconnected from each other, or the insulating layer may be damaged to cause short-circuiting of the wires. 
         [0028]    Such disconnection or short-circuiting of the wires may cause a malfunction of the flexible OLED display device  1 . 
       SUMMARY OF THE DISCLOSURE 
       [0029]    Therefore, an aspect of the detailed description is to provide a flexible display device capable of preventing disconnection or short-circuiting of wires, by forming wires in a bending area of a non-active area, on the same layer so as not to cross each other, and a method for fabricating the same. 
         [0030]    To achieve these and other advantages and in accordance with the purpose of this specification, as embodied and broadly described herein, there is provided a flexible display device, including: a flexible substrate having an active area where pixels provided with organic light-emitting diodes have been formed, a non-active area formed around the active area, and a bending area formed at a lower part of the non-active area; a data driving portion mounted in the lower end non-active area; a plurality of power lines formed in the lower end non-active area, and configured to supply power signals provided from the data driving portion to the active area; and a plurality of signal lines formed in the lower end non-active area, and configured to supply driving signals provided from the data driving portion to the active area, wherein the plurality of power lines and the plurality of signal lines are formed in the bending area, on the same layer in parallel to each other. 
         [0031]    To achieve these and other advantages and in accordance with the purpose of this specification, as embodied and broadly described herein, there is also provided a method for fabricating a flexible display device, the method including: preparing a substrate having an active area, a non-active area, and a bending area formed at a lower part of the non-active area; forming a thin film transistor and an organic light-emitting diode on the active area of the substrate; and forming a plurality of power lines and a plurality of signal lines connected to the active area, on the lower end non-active area of the substrate, wherein the plurality of power lines and the plurality of signal lines are formed in the bending area on the same layer in parallel to each other. 
         [0032]    The present invention can have the following advantages. 
         [0033]    In the bending area of the non-active area, wires are formed on the same layer in parallel to each other, so as not to overlap or cross each other. As a result, disconnection or short-circuit of the wires, which occurs when the bending area is bent, can be prevented. Thus a malfunction of the flexible display device can be prevented. 
         [0034]    Further scope of applicability of the present application will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the disclosure, are given by way of illustration only, since various changes and modifications within the spirit and scope of the disclosure will become apparent to those skilled in the art from the detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0035]    The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments and together with the description serve to explain the principles of the disclosure. 
           [0036]    In the drawings: 
           [0037]      FIG. 1  is a planar view schematically illustrating a flexible organic light-emitting diode (OLED) display device in accordance with the related art; 
           [0038]      FIG. 2A  is an enlarged view of part ‘A’ in  FIG. 1 ; 
           [0039]      FIG. 2B  is a cross-sectional view of the flexible OLED display device of  FIG. 1 , which illustrates a bent state; 
           [0040]      FIG. 3  is a cross-sectional view taken along line in  FIG. 2B ; 
           [0041]      FIG. 4  is a planar view of a flexible OLED display device according to a first embodiment of the present invention; 
           [0042]      FIG. 5  is an equivalent circuit diagram for a single pixel in the flexible OLED display device of  FIG. 4 ; 
           [0043]      FIG. 6  is a cross-sectional view taken along line VIa≠VIa′ and VIb˜VIb′ in the flexible OLED device of  FIG. 4 ; 
           [0044]      FIGS. 7A to 7C  are views illustrating processes of fabricating a flexible OLED display device according to the first embodiment of the present invention; 
           [0045]      FIG. 8  is a planar view of a flexible OLED display device according to a second embodiment of the present invention; 
           [0046]      FIG. 9  is a cross-sectional view taken along line VII˜VII′ in the flexible OLED display device of  FIG. 8 ; 
           [0047]      FIG. 10  is a view illustrating a wire structure in a bending area in a flexible OLED display device according to the present invention; and 
           [0048]      FIG. 11  is a view illustrating various embodiments of  FIG. 10 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0049]    Description will now be given in detail of the exemplary embodiments of the present invention, with reference to the accompanying drawings. For the sake of brief description with reference to the drawings, the same or equivalent components will be provided with the same reference numbers, and description thereof will not be repeated. 
         [0050]    Hereinafter, a flexible display device and a method for fabricating the same according to the present invention will be explained in more detail. 
         [0051]      FIG. 4  is a planar view of a flexible organic light-emitting diode (OLED) display device according to a first embodiment of the present invention. 
         [0052]    Referring to  FIG. 4 , the flexible OLED display device  100  according to a first embodiment of the present invention may be formed on a flexible substrate  110  including an active area (display area) (A/A) and a non-active area (non-display area) (N/A). 
         [0053]    The active area (A/A) is a region where an image is substantially displayed. On the active area (A/A), a plurality of gate lines (GL) and a plurality of data lines (DL) may be formed to cross each other, thereby defining pixel regions. A plurality of sensing lines (SL) may be formed in parallel to the plurality of gate lines (GL). 
         [0054]    Power lines for supplying a driving voltage (VDD), a reference voltage (Vref) and a ground voltage (GND) to pixel regions, e.g., a driving voltage line  146   b , a reference voltage line  147   b  and a ground line  145   b  may be formed in the active area (A/A). 
         [0055]    A pixel (P) having a plurality of switching devices may be formed at the pixel region. The pixel (P) may operate by being connected to each of the gate line (GL), the data line (DL) and the sensing line (SL). 
         [0056]      FIG. 5  is an equivalent circuit diagram for a single pixel in the flexible OLED display device of  FIG. 4 . 
         [0057]    Referring to  FIGS. 4 and 5 , the pixel (P) in the active area (A/A) may have a structure where three switching devices (ST 1 , DT, ST 2 ), one capacitor (C) and one organic light emitting diode (OLED) are formed. However, the present invention is not limited to this configuration. That is, the pixel (P) may be formed to have various structures such as 2T1C, 4T1C, 5T1C and 6T1C. 
         [0058]    The switching devices (ST 1 , DT, ST 2 ) may include a switching transistor (ST 1 ), a driving transistor (DT) and a sensing transistor (ST 2 ). The switching device (ST 1 , DT, ST 2 ) may be thin film transistors (TFT), for example, formed of amorphous silicon or poly-crystalline silicon. 
         [0059]    The switching transistor (ST 1 ) of the pixel (P) may include a gate electrode connected to the gate line (GL) of the active area (A/A), a source electrode connected to the data line (DL), and a drain electrode connected to the driving transistor (DT). The switching transistor (ST 1 ) may output a data signal supplied from the data line (DL) to the driving transistor (DT), according to a gate signal supplied from the gate line (GL). 
         [0060]    The driving transistor (DT) of the pixel (P) may include a gate electrode connected to the drain electrode of the switching transistor (ST 1 ), a source electrode connected to an OLED, and a drain electrode connected to driving voltage lines  146   a ,  146   b  for supplying a driving voltage (VDD). The driving transistor (DT) may control the size of current applied to the OLED from the driving voltage (VDD), according to a data signal supplied from the switching transistor (ST 1 ). 
         [0061]    The capacitor (C) of the pixel (P) may be connected between the gate electrode of the driving transistor (DT) and the OLED. The capacitor (C) may store therein a voltage corresponding to a data signal supplied to the gate electrode of the driving transistor (DT). Also, the capacitor (C) may constantly maintain an ‘ON’ state of the driving transistor (DT) for a single frame, with the voltage stored therein. 
         [0062]    The sensing transistor (ST 2 ) of the pixel (P) may include a gate electrode connected to the sensing line (SL), a source electrode connected to the source electrode of the driving transistor (DT), and a drain electrode connected to reference voltage lines  147   a ,  147   b  for supplying a reference voltage (Vref). The sensing transistor (ST 2 ) may sense a threshold voltage (Vth) of the driving transistor (DT), thereby preventing a malfunction of the OLED. 
         [0063]    The switching transistor (ST 1 ) of the pixel (P) may be turned on by a gate signal supplied to the gate line (GL), and the capacitor (C) of the pixel (P) may be charged with charges by a data signal supplied to the data line (DL). The amount of current applied to the channel of the driving transistor (DT) may be determined according to a potential difference between a voltage charged at the capacitor (C) and the driving voltage (VDD). The amount of light emitted from the OLED may be determined based on such amount of current. As the OLED emits light, an image is displayed. 
         [0064]    The sensing transistor (ST 2 ) may be turned on earlier than the switching transistor (ST 1 ), according to a sensing signal supplied through the sensing line (SL). Under such configuration, electroluminescence of the OLED by the driving voltage (EVDD), which occurs before a data signal is charged at the capacitor (C) during an initial operation of the switching transistor (ST 1 ), can be prevented. 
         [0065]    Referring back to  FIG. 4 , the non-active area (N/A) of the flexible OLED display device  100  may be formed adjacent, for example, around the active area (A/A). Driving circuitry for driving the pixels (P) in the active area (A/A) and wires may be formed in the non-active area (N/A). 
         [0066]    The driving circuitry may include a data driving portion  230 , a gate driving portion  210  and a light-emitting controller  220 . 
         [0067]    The data driving portion  230  may be mounted at the non-active area (N/A) below the active area (A/A), in the form of a chip. The data driving portion  230  may generate a data signal by receiving a signal from an external printed circuit board (not shown). The generated data signals may be output to the plurality of data lines (DL) in the active area (A/A) through wires. 
         [0068]    The data driving portion  230  may output a gate signal and a light-emitting signal provided from external circuitry, to the gate driving portion  210  and the light-emitting controller  220  through wires, respectively. The data driving portion  230  may output power signals provided from external circuitry, e.g., power signals including a driving voltage (VDD), a reference voltage (Vref), a ground voltage (GND), etc., to driving voltage lines  146   a ,  146   b , reference voltage lines  147   a ,  147   b , and ground lines  145   a ,  145   b , respectively. 
         [0069]    The gate driving portion  210  may be formed at one side of the non-active area (N/A) outside the active area (A/A), in the form of a gate in panel (GIP). The gate driving portion  210  may sequentially output gate signals provided from the data driving portion  230  through wires (e.g., gate signal lines  141   a ), to the plurality of gate lines (GL) in the active area (A/A). 
         [0070]    The light-emitting controller  220  may be formed at another side of the non-active area (N/A) outside the active area (A/A), in the form of a gate in panel (GIP) so as to correspond to the gate driving portion  210 . The light-emitting controller  220  may sequentially output light-emitting signals provided from the data driving portion  230  through wires (e.g., light-emitting lines  141   c ), to the plurality of sensing lines (SL) in the active area (A/A). 
         [0071]    The wires may include power lines and signal lines formed between the data driving portion  230  and the active area (A/A). The power lines may include driving voltage lines  146   a ,  146   b , reference voltage lines  147   a ,  147   b , and ground lines  145   a ,  145   b . Also, the signal lines may include a gate signal line  141   a , a data signal line  141   b , and a light-emitting signal line  141   c.    
         [0072]    The power lines may supply power signals provided from the data driving portion  230 , to the active area (A/A). The signal lines may supply driving signals provided from the data driving portion  230 , e.g., a gate signal, a data signal and a light-emitting signal, to the active area (A/A), the gate driving portion  210  and the light-emitting controller  220 . 
         [0073]    The driving voltage lines  146   a ,  146   b  may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion  230  to the pixel (P) in the active area (A/A). 
         [0074]    The driving voltage lines  146   a ,  146   b  may include a first driving voltage line  146   a  and a second driving voltage line  146   b . The first driving voltage line  146   a  connected to the data driving portion  230 . The second driving voltage line  146   b  may be connected to the first driving voltage line  146   a  and formed as a bar in a direction parallel to the data driving portion  230 . The second driving voltage line  146   b  may be formed such that one side thereof is connected to the first driving voltage line  146   a , and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second driving voltage line  146   b  may output a driving voltage (VDD) provided through the first driving voltage line  146   a  to each pixel (P). 
         [0075]    The reference voltage lines  147   a ,  147   b  may be formed in the lower end non-active area (N/A), and may output a reference voltage (Vref) provided from the data driving portion  230  to the pixel (P) in the active area (A/A). 
         [0076]    The reference voltage lines  147   a ,  147   b  may include a first reference voltage line  147   a  and a second reference voltage line  147   b . The first reference voltage line  147   a  connected to the data driving portion  230 . The second reference voltage line  147   b  may be connected to the first reference voltage line  147   a  and formed as a bar in parallel to the second driving voltage line  146   b . The second reference voltage line  147   b  may be formed such that one side thereof is connected to the first reference voltage line  147   a , and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second reference voltage line  147   b  may output a reference voltage (Vref) provided through the first reference voltage line  147   a  to each pixel (P). 
         [0077]    The ground lines  145   a ,  145   b  may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion  230  to the pixel (P) in the active area (A/A). 
         [0078]    The ground lines  145   a ,  145   b  may include a first ground line  145   a  and a second ground line  145   b . The first ground line  145   a  connected to the data driving portion  230 . The second ground line  145   b  may be connected to the first ground line  145   a , and formed as a bar in parallel to the second driving voltage line  146   b  and the second reference voltage line  147   b . The second ground line  145   b  may be formed such that one side thereof is connected to the first ground line  145   a , and another side thereof is extending to the pixel (P) in the active area (A/A). By this configuration, the second ground line  145   b  may output a ground voltage (GND) provided through the first ground line  145   a  to each pixel (P). 
         [0079]    The gate signal line  141   a  may be formed between the data driving portion  230  and the gate driving portion  210  in the lower end non-active area (N/A). The gate signal line  141   a  may output a gate signal provided from the data driving portion  230  to the gate driving portion  210 . The gate signal may be output to the plurality of gate lines (GL) in the active area (A/A), through the gate driving portion  210 . 
         [0080]    The data signal line  141   b  may be formed in the lower end non-active area (N/A), between the data driving portion  230  and the data line (DL) in the active area (A/A). The data signal line  141   b  may output a data signal provided from the data driving portion  230  to the plurality of data lines (DL) in the active area (A/A). 
         [0081]    The light-emitting signal line  141   c  may be formed in the non-active area (N/A) between the data driving portion  230  and the light-emitting controller  220 . The light-emitting signal line  141   c  may output a light-emitting signal provided from the data driving portion  230 , to the light-emitting controller  220 . The light-emitting signal may be output to the plurality of sensing lines (SL) in the active area (A/A), by the light-emitting controller  220 . 
         [0082]    In the flexible OLED display device  100  according to this embodiment of the present invention, the lower end non-active area (N/A) may include a bending area (B/A). The bending area (B/A) may be a region which has a predetermined curvature when part of the lower end non-active area (N/A) is bent to the rear or front surface of the flexible OLED display device  100 . That is, the bending area (B/A) is a flexible portion including flexible materials that is provided between one end of the display device  100  and the other part of the device  100  and allows the one end to be bent or rotated around the bending area (B/A) toward the front or rear surface of the other part. In accordance with one embodiment, the lower end non-active area (N/A) may be bent around the bending area (B/A) toward the front or rear surface of the flexible OLED display device  100 . As an example, the lower end non-active area (N/A) may be attached to the rear surface of the flexible OLED display device  100  by the rotation around the bending area (B/A). Although  FIG. 4  shows only one bending area formed adjacent one end of the flexible OLED display device  100 , it will be readily appreciable to one skilled in the art that the bending area (B/A) may be formed adjacent any side of the flexible OLED display device  100  (e.g.  4  bending areas formed adjacent  4  sides of the flexible OLED display device  100  in rectangular shape). 
         [0083]    The lower end non-active area (N/A) may be divided into three regions by the bending area (B/A). For instance, the lower end non-active area (N/A) may be divided into a first area between the bending area (B/A) and the active area (A/A), the bending area (B/A), and a second area between the bending area (B/A) and an area where the data driving portion  230  has been mounted. 
         [0084]    The first area of the lower end non-active area (N/A) may be a region covered by a bezel portion, etc., together with the rest of the non-active area (N/A). Also, the second area may be a region that may be positioned on a rear surface of the flexible OLED display device  100 , by bending of the bending area (B/A). 
         [0085]    Power lines, which include the second driving voltage line  146   b , the second reference voltage line  147   b  and the second ground line  145   b , may be formed in the first area of the lower end non-active area (N/A). 
         [0086]    Signal lines, which include the gate signal line  141   a , the data signal line  141   b  and the light-emitting signal line  141   c , may be formed in the first area so as to cross the power lines. The signal lines and the power lines in the first area may be formed to overlap each other at different layers on the flexible substrate  110 . 
         [0087]    Power lines, which include the first driving voltage line  146   a , the first reference voltage line  147   a  and the first ground line  145   a , may be formed in the bending area (B/A) of the lower end non-active area (N/A). 
         [0088]    Signal lines, which include the gate signal line  141   a , the data signal line  141   b  and the light-emitting signal line  141   c , may be formed in the bending area (B/A) in parallel to the power lines so as not to cross the power lines. The signal lines and the power lines in the bending area (B/A) may be formed to be spaced from each other on the same layer on the flexible substrate  110 . 
         [0089]    The power lines, which include the first driving voltage line  146   a , the first reference voltage line  147   a  and the first ground line  145   a , may be formed in the second area of the lower end non-active area (N/A). 
         [0090]    The signal lines, which include the gate signal line  141   a , the data signal line  141   b  and the light-emitting signal line  141   c , may be formed in the second area in parallel to the power lines so as not to cross the power lines. The signal lines and the power lines may be formed to be extending from the data driving portion  230  in parallel to each other. In this case, the signal lines and the power lines may be formed to be in parallel to each other by being bent at least twice in the second area. The signal lines and the power lines in the second area may be formed to be spaced from each other on the same layer. 
         [0091]    As mentioned above, in the flexible OLED display device  100  according to this embodiment, wires are formed on the same layer in parallel to each other, in the bending area (B/A) of the lower end non-active area (N/A) where bending is performed. Accordingly, unlike in the conventional art, the occurrence of disconnection of the wires due to bending stress can be prevented. 
         [0092]    In the second area and the bending area (B/A) of the lower end non-active area (N/A), wires are formed on the same layer. However, in the first area, wires are formed on different layers. By such configuration, wires formed in the bending area (B/A) may be connected to wires formed on different layers in the first area, through holes (not shown). 
         [0093]      FIG. 6  is a cross-sectional view taken along line VIa˜VIa′ and VIb˜VIb′ in the flexible OLED device of  FIG. 4 . 
         [0094]    Referring to  FIGS. 4 and 6 , the flexible OLED display device  100  may include pixels (P) formed in the active area (A/A), and wires formed in the non-active area (N/A) (e.g., lower end non-active area (N/A)). The lower end non-active area (N/A) where wires have been formed may be the bending area (B/A). 
         [0095]    A thin film transistor (TFT) and an organic light emitting diode (OLED) may be formed on the flexible substrate  110  in the active area (A/A). 
         [0096]    For instance, a passivation layer  111  may be formed on the entire surface of the flexible substrate  110 . A semiconductor layer  121  formed of amorphous or poly-crystalline silicon may be formed on the passivation layer  111 . 
         [0097]    A gate insulating layer  113  may be formed on the semiconductor layer  121 , and a gate electrode  123  may be formed on the gate insulating layer  113  at a position corresponding to a predetermined region of the semiconductor layer  121 . 
         [0098]    An interlayer insulating layer  115  may be formed on the gate electrode  123 , and a source electrode  125   a  and a drain electrode  125   b  may be formed on the interlayer insulating layer  115 . 
         [0099]    The source electrode  125   a  and the drain electrode  125   b  may be connected to the semiconductor layer  121 , through contact holes (not shown) formed at the interlayer insulating layer  115  and the gate insulating layer  113 . 
         [0100]    The semiconductor layer  121 , the gate electrode  123 , the source electrode  125   a  and the drain electrode  125   b  may constitute a thin film transistor in the active area (A/A) of the flexible substrate  110 . The TFT may be, for example, a driving transistor of the flexible OLED display device  100 . However, the present invention is not limited to this example. 
         [0101]    A planarization layer  117  may be formed on the TFT. A first electrode  131 , connected to the drain electrode  125   b  through a contact hole (not shown), may be formed on the planarization layer  117 . 
         [0102]    A pixel defining layer  130 , through which part of the first electrode  131  is exposed to the outside, may be formed on the first electrode  131 . A light-emitting layer  133  may be formed on the pixel defining layer  130 . The light-emitting layer  133  may be formed on the first electrode  131  which has been exposed to the outside by the pixel defining layer  130 . A second electrode  135  may be formed on the light-emitting layer  133 . 
         [0103]    The first electrode  131 , the light-emitting layer  133  and the second electrode  135  may constitute an OLED in the active area (A/A) of the flexible substrate  110 . 
         [0104]    Signal lines and power lines may be formed on the flexible substrate  110  in the bending area (B/A). The signal lines may include the gate signal line  141   a  and the data signal line  141   b . The power lines may include the first ground line  145   a  and the first driving voltage line  146   a.    
         [0105]    For instance, the passivation layer  111  may be formed on the entire surface of the flexible substrate  110 . The gate signal line  141   a , the data signal line  141   b , the first ground line  145   a  and the first driving voltage line  146   a  may be formed commonly on the passivation layer  111 , such that they are spaced from each other with a predetermined distance therebetween, for example, in parallel to each other. 
         [0106]    In accordance with one embodiment, the signal lines and the power lines formed in the bending area (B/A) may be formed of the same metallic material as the source electrode  125   a  and the drain electrode  125   b  formed in the active area (A/A), at the same processing stage. 
         [0107]    Like in the active area (A/A), the planarization layer  117  may be formed as an insulating layer on the signal lines and the power lines formed in the bending area (B/A). 
         [0108]    As mentioned above, in the flexible OLED display device  100  according to one embodiment, wires may be formed on the same layer in the bending area (B/A), with the same metallic material. Accordingly, even if the planarization layer  117  is damaged by bending stress in the bending area (B/A), the wires in the bending area (B/A) are not disconnected or cracked. This can prevent a malfunction of the flexible OLED display device  100 . 
         [0109]      FIGS. 7A to 7C  are views illustrating processes of fabricating a flexible OLED display device according to the first embodiment of the present invention. 
         [0110]    A passivation layer  111  may be formed on the entire surface of a substrate divided into an active area (A/A) and a non-active area (N/A), e.g., a glass substrate  101 . The passivation layer  111  is provided so that thin film transistors, organic light-emitting diodes and wires can be prevented from being damaged during the process of detaching the glass substrate  101 , as described below in more detail. 
         [0111]    The non-active area (N/A) may include a bending area (B/A) formed below the active area (A/A), i.e., a bending area (B/A) of a lower end non-active area (N/A). 
         [0112]    Amorphous silicon or poly-crystalline silicon is deposited in the active area (A/A) on the glass substrate  101  where the passivation layer  111  has been formed. Then the amorphous silicon or the poly-crystalline silicon is selectively patterned, thereby forming a semiconductor layer  121 . The semiconductor layer  121  may include a source region and a drain region each including impurities, and a channel region including no impurities. 
         [0113]    A gate insulating layer  113  may be formed on the entire surface of the glass substrate  101  where the semiconductor layer  121  has been formed. The gate insulating layer  113  may be formed as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof. 
         [0114]    The gate insulating layer  113  may not be formed in the non-active area (N/A) of the glass substrate  101 . 
         [0115]    A gate electrode  123  may be formed on the gate insulating layer  113 , at a position corresponding to a channel region of the semiconductor layer  121 . The gate electrode  123  may be formed by depositing a metallic material such as molybdenum (Mo), aluminum (Al), chrome (Cr), titanium (Ti) and copper (Cu), or an alloy thereof, on the gate insulating layer  113 , and then by selectively patterning the metallic material or the alloy. 
         [0116]    An interlayer insulating layer  115  may be formed on the entire surface of the active area (A/A) of the glass substrate  101  where the gate electrode  123  has been formed. The interlayer insulating layer  115  may be formed as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof. 
         [0117]    Contact holes (not shown) may be formed by etching part of the interlayer insulating layer  115  and the gate insulating layer  113 , thereby exposing part of the semiconductor layer  121 , e.g., a source region and a drain region to the outside therethrough. 
         [0118]    A source electrode  125   a  and a drain electrode  125   b  may be formed on the interlayer insulating layer  115 . The source electrode  125   a  may be formed so as to be connected to the source region of the semiconductor layer  121  through the contact hole, and the drain electrode  125   b  may be formed so as to be connected to the drain region of the semiconductor layer  121  through the contact hole. 
         [0119]    The source electrode  125   a  and the drain electrode  125   b  may be formed by depositing a metallic material such as Ti, Al and Mo, or an alloy thereof such as Ti/Al/Ti and Mo/Al, on the interlayer insulating layer  115 , and then by selectively patterning the metallic material or the alloy. 
         [0120]    A thin film transistor (TFT) including the semiconductor layer  121 , the gate electrode  123 , the source electrode  125   a  and the drain electrode  125   b , which is, e.g., a driving transistor of the flexible OLED display device  100 , may be formed in the active area (A/A) of the glass substrate  101 . 
         [0121]    Wires, e.g., a gate signal line  141   a , a data signal line  141   b , a first ground line  145   a  and a first driving voltage line  146   a  may be formed on the passivation layer  111 , in the non-active area (N/A) of the glass substrate  101 . Such wires may be formed on the passivation layer  111  so as to be spaced from each other with a predetermined interval. 
         [0122]    The gate signal line  141   a , the data signal line  141   b , the first ground line  145   a  and the first driving voltage line  146   a  may be formed of the same metallic material as the source electrode  125   a  and the drain electrode  125   b , at the same processing stage. 
         [0123]    Referring to  FIG. 7B , a planarization layer  117  may be formed on the entire surface of the active area (A/A) where a thin film transistor has been formed, and the non-active area (N/A) where wires have been formed. 
         [0124]    The planarization layer  117  may be formed by a spin coating method, for example, the method for coating an organic material or an inorganic material such as polyimide, benzocyclobutene series resin and acrylate, in the form of a liquid phase, and then hardening the material. 
         [0125]    A contact hole (not shown) may be formed by etching part of the planarization layer  117  in the active area (A/A), thereby exposing the drain electrode  125   b  to the outside therethrough. 
         [0126]    A first electrode  131  may be formed on the planarization layer  117  in the active area (A/A). The first electrode  131  may be connected to the drain electrode  125   b  through the contact hole of the planarization layer  117 . 
         [0127]    The first electrode  131  may be formed of a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or ZnO (Zinc Oxide), which may form the anode of an OLED. 
         [0128]    A pixel defining layer  130  may be formed on the first electrode  131 . The pixel defining layer  130  may have an opening through which part of the first electrode  131  is exposed to the outside, and may define a pixel region. 
         [0129]    The pixel defining layer  130  may be formed by a spin coating method, for example, the method for coating an organic material or an inorganic material such as polyimide, benzocyclobutene series resin and acrylate, in the form of a liquid phase, and then hardening the material. 
         [0130]    Referring to  FIGS. 7B and 7C , a light-emitting layer  133  may be formed on the pixel defining layer  130 . The light-emitting layer  133  may be formed on the opening of the pixel defining layer  130 , i.e., may be formed on the first electrode  131  exposed to the outside by the pixel defining layer  130 . 
         [0131]    A second electrode  135  may be formed on the light-emitting layer  133 . The second electrode  135  may be formed of aluminum (Al), silver (Ag), magnesium (Mg), or an alloy thereof by deposition. 
         [0132]    An OLED including the first electrode  131 , the light-emitting layer  133  and the second electrode  135  may be formed on a TFT of the glass substrate  101  in the active area (A/A). 
         [0133]    When a TFT and an OLED have been formed in the active area (A/A) and wires have been formed in the non-active area (N/A), the glass substrate  101  may be detached from the passivation layer  111 . Then, a flexible substrate  110  may be attached to the passivation layer  111 . 
         [0134]    The flexible substrate  110  may have the same active area (A/A) and non-active area (N/A) as the glass substrate  101 . 
         [0135]    The flexible substrate  110  may be formed, for example, of one of polycarbon, polyimide, polyether sulfone (PES), polyarylate, polyethylene naphthalate (PEN) or poly ethyleneterephthalate (PET). 
         [0136]    The glass substrate  101  may be detached from the passivation layer  111  through irradiation of laser, etc., and the flexible substrate  110  may be attached to the passivation layer  111  by an adhesive tape such as an optically clear adhesive (OCA), with reference to  FIG. 7C . 
         [0137]      FIG. 8  is a planar view of a flexible OLED display device according to a second embodiment of the present invention. 
         [0138]    Referring to  FIG. 8 , the flexible OLED display device according to the second embodiment may be formed on a flexible substrate  110  having an active area (A/A) and a non-active area (N/A). 
         [0139]    The active area (A/A) is a region where an image is substantially displayed. On the active area (A/A), a plurality of gate lines (GL) and a plurality of data lines (DL) may be formed to cross each other, thereby defining pixel regions. A plurality of sensing lines (SL) may be formed in parallel to the plurality of gate lines (GL). 
         [0140]    Power lines for supplying a driving voltage (VDD), a reference voltage (Vref) and a ground voltage (GND) to pixel regions, e.g., a driving voltage line  146   b , a reference voltage line  147   b  and a ground line  145   b  may be formed in the active area (A/A). 
         [0141]    A pixel (P) having a plurality of switching devices may be formed at the pixel region. The pixel (P) may be the same pixel as described above with reference to  FIG. 5 . 
         [0142]    The non-active area (N/A) of the flexible OLED display device  200  may be formed around the active area (A/A), which may be defined by the dotted line. Driving circuitry for driving the pixels (P) in the active area (A/A) and wires may be formed in the non-active area (N/A). 
         [0143]    The driving circuitry may include a data driving portion  230 , a gate driving portion  210  and a light-emitting controller  220 . 
         [0144]    The data driving portion  230  may be mounted in the non-active area (N/A) positioned below the active area (A/A), i.e., the lower-end non-active area (N/A). The gate driving portion  210  and the light-emitting controller  220  may be formed in the non-active area (N/A), i.e., at two sides outside the active area (A/A), in the form of a gate in panel (GIP). 
         [0145]    The data driving portion  230  may generate a data signal by receiving a signal from an external circuit. The generated data signal may be output to the plurality of data lines (DL) in the active area (A/A) through wires. The gate driving portion  210  may output a gate signal provided from the data driving portion  230 , to the plurality of gate lines (GL) in the active area (A/A), through wires. The light-emitting controller  220  may output a light-emitting signal provided from the data driving portion  230 , to the plurality of sensing lines (SL) in the active area (A/A), through wires. 
         [0146]    Wires may include power lines including driving voltage lines  146   a ,  146   b , reference voltage lines  147   a ,  147   b , and ground lines  145   a ,  145   b , and signal lines including a gate signal line  141   a , a data signal line  141   b , and a light-emitting signal line  141   c.    
         [0147]    The driving voltage lines  146   a ,  146   b  may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion  230  to the pixel (P) in the active area (A/A). 
         [0148]    The driving voltage lines  146   a ,  146   b  may include a first driving voltage line  146   a  and a second driving voltage line  146   b . The first driving voltage line  146   a  connected to the data driving portion  230 . The second driving voltage line  146   b  may be connected to the first driving voltage line  146   a , and formed as a bar in a direction parallel to the data driving portion  230 . The second driving voltage line  146   b  may be formed such that one side thereof is connected to the first driving voltage line  146   a , and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second driving voltage line  146   b  may output a driving voltage (VDD) provided through the first driving voltage line  146   a  to each pixel (P). 
         [0149]    The reference voltage lines  147   a ,  147   b  may be formed in the lower end non-active area (N/A), and may output a reference voltage (Vref) provided from the data driving portion  230  to the pixel (P) in the active area (A/A). 
         [0150]    The reference voltage lines  147   a ,  147   b  may include a first reference voltage line  147   a  and a second reference voltage line  147   b . The first reference voltage line  147   a  connected to the data driving portion  230 . The second reference voltage line  147   b  may be connected to the first reference voltage line  147   a , and formed as a bar in parallel to the second driving voltage line  146   b . The second reference voltage line  147   b  may be formed such that one side thereof is connected to the first reference voltage line  147   a , and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second reference voltage line  147   b  may output a reference voltage (Vref) provided through the first reference voltage line  147   a  to each pixel (P). 
         [0151]    The ground lines  145   a ,  145   b  may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion  230  to the pixel (P) in the active area (A/A). 
         [0152]    The ground lines  145   a ,  145   b  may include a first ground line  145   a  and a second ground line  145   b . The first ground line  145   a  may be connected to the data driving portion  230 . Further, the second ground line  145   b  may be connected to the first ground line  145   a , and formed as a bar in a direction parallel to the second driving voltage line  146   b  and the second reference voltage line  147   b . The second ground line  145   b  may be formed such that one side thereof is connected to the first ground line  145   a , and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second ground line  145   b  may output a ground voltage (GND) provided through the first ground line  145   a  to each pixel (P). 
         [0153]    The gate signal line  141   a  may be formed in the lower end non-active area (N/A), between the data driving portion  230  and the gate driving portion  210 . The gate signal line  141   a  may output a gate signal provided from the data driving portion  230  to the gate driving portion  210 . The gate signal may be output to the plurality of gate lines (GL) in the active area (A/A), through the gate driving portion  210 . 
         [0154]    The data signal line  141   b  may be formed in the lower end non-active area (N/A), between the data driving portion  230  and the data line (DL) in the active area (A/A). The data signal lines  141   b  may output data signals provided from the data driving portion  230  to the plurality of data lines (DL) in the active area (A/A). 
         [0155]    The light-emitting signal line  141   c  may be formed in the non-active area (N/A), between the data driving portion  230  and the light-emitting controller  220 . The light-emitting signal line  141   c  may output a light-emitting signal provided from the data driving portion  230 , to the light-emitting controller  220 . The light-emitting signal may be output to the plurality of sensing lines (SL) in the active area (A/A), by the light-emitting controller  220 . 
         [0156]    In the flexible OLED display device  200  according to the second embodiment of the present invention, the lower end non-active area (N/A) may include a bending area (B/A). The bending area (B/A) may be a region which has a predetermined curvature when part of the lower end non-active area (N/A) is bent to the front or rear surface of the flexible OLED display device  200 . 
         [0157]    The lower end non-active area (N/A) may be divided, for example, into three regions by the bending area (B/A). For instance, the lower end non-active area (N/A) may be divided into a first area between the bending area (B/A) and the active area (A/A), the bending area (B/A), and a second area between the bending area (B/A) and an area where the data driving portion  230  has been mounted. 
         [0158]    The first area of the lower end non-active area (N/A) may be a region covered by a bezel portion, etc., together with the rest of the non-active area (N/A). Also, the second area may be a region positioned on the rear surface of the flexible OLED display device  200 , by bending of the bending area (B/A). 
         [0159]    The plurality of data signal lines  141   b  and the plurality of power lines may be formed in the first area. The plurality of power lines include the second driving voltage line  146   b , the second reference voltage line  147   b  and the second ground line  145   b . The plurality of data signal lines  141   b  may be connected to the plurality of data lines (DL) in the active area (A/A). The plurality of data signal lines  141   b  and the plurality of power lines may be formed in the first area in parallel with each other. 
         [0160]    In the bending area (B/A) of the lower end non-active area (N/A), the plurality of data signal lines  141   b  and the plurality of power lines formed in the first area, may be formed in parallel with each other. 
         [0161]    In the bending area (B/A) of the lower end non-active area (N/A), the plurality of lines extending from the power lines toward the active area (A/A), the plurality of data signal lines  141   b , the gate signal lines  141   a  and the light-emitting signal lines  141   c  may be formed so as to be spaced from each other on the same layer on the flexible substrate  110 . 
         [0162]    In the second area of the lower-end non-active area (N/A), signal lines including the gate signal lines  141   a , the data signal lines  141   b  and the light-emitting signal lines  141   c  may be formed to cross power lines. The power lines, which may have a bar shape, may include first and second driving voltage lines  146   a ,  146   b , first and second reference voltage lines  147   a ,  147   b , and first and second ground lines  145   a ,  145   b . The signal lines and the power lines in the second area may be formed to overlap each other on different layers on the flexible substrate  110 . 
         [0163]    The signal lines and the power lines may be formed to be in parallel to each other in the first area and the bending area (B/A), by being bent at least twice in the second area. 
         [0164]    That is, in the flexible OLED display device  200  according to the second embodiment, a plurality of signal lines and a plurality of power lines may be formed to cross each other in the second area positioned on the rear surface of the flexible OLED display device  200  when the bending area (B/A) of the lower end non-active area (N/A) is bent toward the rear surface of the device  200 . Thus, in the flexible OLED display device  200  according to the second embodiment, the width of the lower end non-active area (N/A) can be more reduced than in the conventional flexible OLED display device. As a result, the flexible OLED display device  200  according to the second embodiment can have a narrow bezel portion. 
         [0165]    As mentioned above, in the flexible OLED display device  200  according to the second embodiment, a plurality of signal lines and a plurality of power lines are formed on the same layer in parallel to each other, in the bending area (B/A) of the lower end non-active area (N/A). Accordingly, unlike in the conventional art, disconnection of the wires can be prevented even if an insulating layer is damaged due to bending stress. 
         [0166]    In the first area and the bending area (B/A) of the lower end non-active area (N/A), wires are formed on the same layer in accordance with one embodiment of the invention. However, in the second area, wires may be formed on different layers. Based on this configuration, wires formed on different layers in the second area may be connected to wires formed on the same layer in the bending area (B/A), through holes (not shown). 
         [0167]      FIG. 9  is a cross-sectional view taken along line in the flexible OLED display device of  FIG. 8 . 
         [0168]    Referring to  FIGS. 8 and 9 , in the bending area (B/A) of the lower end non-active area (N/A) of the flexible OLED display device  200 , a plurality of wires may be formed on the same layer in a spaced manner from each other. 
         [0169]    For instance, in the bending area (B/A), a passivation layer  111  is formed on a flexible substrate  110 . A gate signal line  141   a , a data signal line  141   b , a second ground line  145   b  and a second driving voltage line  146   b  may be formed on the passivation layer  111 , such that they are spaced from each other with predetermined distances, in parallel to each other. 
         [0170]    A first insulating layer  117   a  may be formed on the gate signal line  141   a , the data signal line  141   b , the second ground line  145   b  and the second driving voltage line  146   b.    
         [0171]    A plurality of wires may be formed to overlap each other on different layers, in the second area positioned on the rear surface of the flexible OLED display device  200  when the bending area (B/A) of the lower end non-active area (N/A) is bent. 
         [0172]    For instance, in the second area, a passivation layer  111  is formed on a flexible substrate  110 . A gate signal line  141   a  and a data signal line  141   b  may be formed on the passivation layer  111 , such that they are spaced from each other in parallel to each other. 
         [0173]    A first insulating layer  117   a  may be formed on the gate signal line  141   a  and the data signal line  141   b . A second ground line  145   b  and a second driving voltage line  146   b  may be formed on the first insulating layer  117   a , with a predetermined distance therebetween in parallel to each other. In this case, the second ground line  145   b  and the second driving voltage line  146   b  may be formed to overlap the gate signal line  141   a  and the data signal line  141   b.    
         [0174]    A second insulating layer  117   b  may be formed on the second ground line  145   b  and the second driving voltage line  146   b.    
         [0175]    In the flexible OLED display device  200  according to the second embodiment, the pixel region in the active area (A/A) has the same cross-sectional profile as the pixel region described above with reference to  FIG. 6 , of which description is not repeated. 
         [0176]    A plurality of wires formed in the non-active area (N/A) may be formed of the same metallic material as a source electrode (not shown) and a drain electrode (not shown) in the pixel region, at the same processing stage. The plurality of wires indicate power lines including the second ground line  145   b  and the second driving voltage line  146   b , and signal lines including the gate signal line  141   a  and the data signal line  141   b . For instance, the plurality of wires may be formed of a metallic material such as Ti, Al and Mo or an alloy thereof such as Ti/Al/Ti and Mo/Al. 
         [0177]      FIG. 10  is a view illustrating a wire structure in a bending area in a flexible OLED display device according to the present invention, and  FIG. 11  is a view illustrating various embodiments of  FIG. 10 . 
         [0178]    In this embodiment, the flexible OLED display device  100  of  FIG. 4  will be explained for convenience. However, this embodiment may be also applicable to the flexible OLED display device  200  of  FIG. 8 . 
         [0179]    Referring to  FIGS. 4 and 10 , in the flexible OLED display device  100 , wires may be formed to have a large width for prevention of disconnection thereof due to bending stress in the bending area (B/A) of the lower end non-active area (N/A). 
         [0180]    For instance, as shown in  FIG. 10 , the width (d 2 ) of wires in the bending area (B/A) of the lower end non-active area (N/A) may be greater than the width (d 1 ) of wires in the first area and the second area of the lower end non-active area (N/A). 
         [0181]    As shown in  FIG. 11 , wires are formed, in the bending area (B/A), with a shape such as a triangle, a diamond, a semi-circle and a circle. Thus, disconnection of the wires, due to bending stress occurring when the bending area (B/A) is bent, can be prevented. 
         [0182]    That is, in the flexible OLED display device  100 , disconnection of wires, which occurs when the bending area (B/A) is bent, can be prevented by various shape changes of the wires in the bending area (B/A). In order to prevent resistance increase of the wires due to the shape changes of the wires, the wires may be formed such that the width in the bending area (B/A) is larger than that in the other regions. As a result, disconnection of the wires, which occurs when the bending area (B/A) is bent, can be prevented. 
         [0183]    The aforementioned wires may be power lines including the first ground line  145   a  and the first driving voltage line  146   a , and signal lines including the gate signal line  141   a  and the data signal line  141   b.    
         [0184]    The foregoing embodiments and advantages are merely exemplary and are not to be considered as limiting the present disclosure. The present teachings can be readily applied to other types of apparatuses. This description is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. The features, structures, methods, and other characteristics of the exemplary embodiments described herein may be combined in various ways to obtain additional and/or alternative exemplary embodiments. 
         [0185]    As the present features may be embodied in several forms without departing from the characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be considered broadly within its scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the appended claims.

Technology Classification (CPC): 6