Patent Abstract:
A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs two pages into the at least one replay-protected memory block of the FLASH memory. The controller may perform a power restoration process based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to data storage devices, and in particular, relates to FLASH memory control methods. 
     2. Description of the Related Art 
     Flash memory is a general non-volatile storage device that is electrically erased and programmed. A NAND Flash, for example, is primarily used in memory cards, USB flash devices, solid-state drives, eMMCs (embedded MultiMediaCards), and so on. Generally, a storage array of a Flash memory (e.g. a NAND Flash) comprises a plurality of blocks. Each block comprises a plurality of pages. To release a block as a spare block, all pages of the entire block have to be erased at once. 
     For data security, some blocks of a FLASH memory are allocated to be replay-protected memory blocks (abbreviated to RPMBs). In comparison with the other blocks, the RPMBs are managed in a higher security level. Data management of the RPMBs is especially important. 
     BRIEF SUMMARY OF THE INVENTION 
     A data storage device and a FLASH memory control method are disclosed. 
     A data storage device in accordance with an exemplary embodiment of the invention comprises a FLASH memory and a controller. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. The controller is coupled to the FLASH memory. The controller manages at least one replay-protected memory block (RPMB) of the FLASH memory. The controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs two pages into the at least one replay-protected memory block of the FLASH memory. The controller may perform a power restoration process based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block. 
     In accordance with another exemplary embodiment of the invention, a FLASH memory control method is disclosed. According to the disclosed control method, at least one replay-protected memory block of a FLASH memory is managed. Further, a success flag and a write count are written into a system block of the FLASH memory after programming two pages into the at least one replay-protected memory block of the FLASH memory. A power restoration process for the FLASH memory may be performed based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a block diagram depicting a data storage device  100  in accordance with an exemplary embodiment of the invention; 
         FIG. 2  depicts how an RPMB data update issued from the host  106  is processed by the controller  104  when N is set to be 2; 
         FIG. 3  is a flowchart depicting how the update success flag RPMB_Update_Success and the write count RPMB_Write_Count are controlled during the RPMB data update procedure shown in  FIG. 2 ; and 
         FIG. 4  is a flowchart depicting a power restoration process with respect to the RPMB update procedure of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description shows several exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  is a block diagram depicting a data storage device  100  in accordance with an exemplary embodiment of the invention. The data storage device  100  comprises a FLASH memory  102  and a controller  104  coupled to the FLASH memory  102 . The controller  104  may operate the FLASH memory  102  according to commands issued from a host  106 . 
     The storage space of the FLASH memory  102  is divided into blocks and each block is further divided into pages. For simplicity, only the blocks relating to the replay-protected memory technique are shown in the figure. As shown, the FLASH memory  102  contains a partition RPMB_Partition of the replay-protected memory blocks RPMB — 1 to RPMB_N. An authentication key is required to access the replay-protected memory blocks RPMB — 1 to RPMB_N. The replay-protected memory blocks may be abbreviated as RPMBs. A host, e.g.  106 , may issue an RPMB data update command in a single frame or multiple frames, depending on the update data length. A MAC value evaluated from the authentication key is attached in the final frame to be verified by the controller  104 . The RPMB data update is allowed only when the MAC value is correct. When the MAC value is incorrect, the RPMB update command is ignored. 
     Note that a FAT block RPMB_FAT is allocated for data buffering. Update data issued from the host  106  is first buffered in the FAT block RPMB_FAT. When the FAT block RPMB_FAT is filled up, the FAT block RPMB_FAT is regarded as a replay-protected memory block and is classified into the partition RPMB_Partition. Meanwhile, another spare block of the FLASH memory  102  may be allocated to play the role of the FAT block RPMB_FAT. 
     According to the disclosure, the controller  104  allocates N pages of the FAT block RPMB_FAT of the FLASH memory  102  for each update of data of the replay-protected memory blocks no matter what update data length is issued. N depends on the amount of frames required for the host  106  to issue an update, of a longest data length, of the replay-protected memory blocks. In an exemplary embodiment, each frame transmits 256 bytes of RPMB data and 256 bytes of update information (e.g. a write count of 4 bytes, an update address of 2 bytes, an error detecting code of 2 bytes, a MAC value of 32 bytes and so on). When the update data length is 256 bytes, the host  106  issues the update of RPMB data in a single frame. When the update data length is 512 bytes, longer than the transmission capability (256 bytes) of a single frame, the host  106  issues the update of RPMB data in two frames. In a case wherein the longest update of RPMB data is 512 bytes, N is set to be 2. The controller  104  allocates 2 pages of the FAT block RPMB_FAT of the FLASH memory  102  for each update of data of the replay-protected memory blocks no matter what update data length is issued. When the host  106  just issues a data update of 256 bytes for the replay-protected memory blocks, the controller  104  fills up the allocated 2 pages with dummy data in addition to the 256 bytes of data issued by the host  106 . In this manner, each successful RPMB data update should result in N valid pages in the FAT block RPMB_FAT. 
     Further, RPMB information such as an update success flag RPMB_Update_Success suggested in the disclosure and a write count RPMB_Write_Count generally utilized in RPMB management may be recorded in a system block Sys_BLK of the FLASH memory  102 . In other exemplary embodiments, the system block is also a FAT block of the Flash memory. Note that the update success flag RPMB_Update_Success and the write count RPMB_Write_Count are recorded together within a single page. Every time the allocated N pages of the FAT block RPMB_FAT are all written with data, the controller  104  asserts an update success flag RPMB_Update_Success (e.g., asserted as a success flag) and updates a write count RPMB_WriteCount. The assertion of the update success flag RPMB_Update_Success is tied to the update of the write count RPMB_Write_Count. Thus, the update success flag RPMB_Update_Success is of high reliability. 
     The FAT block RPMB_FAT or/and the update success flag RPMB_Update_Success are checked by the controller  104  during a power restoration process, to recognize whether a power failure event happened before and if so, what time it happened. During the power restoration process, when the controller  104  observes that the amount of valid pages in the FAT block RPMB_FAT is a multiple of N and the update success flag RPMB_Update_Success has been asserted, the controller  120  accepts the data written in the last allocated N pages. 
     In some exemplary embodiments, the controller  102  keeps the update success flag RPMBUpdate_Success asserted until a start page of the next allocated N pages is written with data. During the power restoration process, when the controller  104  observes that the amount of valid pages in the FAT block RPMB_FAT is not a multiple of N, the controller  104  ignores the last update for the replay-protected memory blocks. Further, during the power restoration process, when the controller  104  observes that the update success flag RPMB_Update_Success has not been asserted, the controller  104  also ignores the last update for the replay-protected memory blocks. During the power restoration process, when the controller  104  observes that the amount of valid pages in the FAT block RPMB_FAT is a multiple of N and the update success flag RPMB_Update_Success has been asserted, the controller  104  confirms data synchronization within each update of the replay protect memory blocks. 
       FIG. 2  depicts how an RPMB data update issued from the host  106  is processed by the controller  104  when N is set to be 2. When the host  106  issues a shorter RPMB update data (e.g. 256 bytes) in a single frame, the controller  104  performs a first write process on the FLASH memory  102  to write the issued RPMB data  202  into the 1 st  allocated page in the FAT block RPMB_FAT and then performs a second write process on the FLASH memory  102  to write dummy data  204  into the 2 nd  allocated page in the FAT block RPMB_FAT. When the host  106  issues a longer RPMB update data (e.g. 512 bytes) in two frames, the controller  104  writes the RPMB data issued in the two different frames separately. As shown, the RPMB data  206  issued in the first frame is written into the 1 st  allocated page of the FAT block RPMB_FAT via a first write process and the RPMB data  208  issued in the second frame is written into the 2 nd  allocated page in the FAT block RPMB_FAT via a second write process. In this manner, each successful RPMB data update should result in 2 valid pages in the FAT block RPMB_FAT. 
       FIG. 3  is a flowchart depicting how the update success flag RPMB_Update_Success and the write count RPMB_Write_Count are controlled during the RPMB data update procedure shown in  FIG. 2 . In step S 302 , the first page allocated in the FAT block RPMB_FAT for the two-paged RPMB write is programmed. After the first write process S 302  is performed, the update success flag RPMB_Update_Success is refreshed to “Fail” (e.g., programming a fail flag) in step S 304 . The second write process S 306  is performed after step S 304 , by which the second page allocated in the FAT block RPMB_FAT for the two-paged RPMB write is programmed. After the second write process S 306  is performed, the update success flag RPMB_Update_Success is asserted as “Success” (e.g., programming a success flag) and the write count RPMB_Write_Count is updated (e.g. increased by 1). After the step S 308 , the RPMB data update procedure may be finished. As shown in  FIG. 3 , power fail events may occur at any time. A power fail event occurs before the first write process S 302  is a first sudden power off event SPO — 1. A power fail event occurs between the first write process S 302  and the update success flag RPMB_Update_Success control step S 304  is a second sudden power off event SPO — 2. A power fail event occurs between the update success flag RPMB_Update_Success control step S 304  and the second write process S 306  is a third sudden power off event SPO — 3. A power fail event occurs between the second write process S 306  and the update success flag RPMB_Update_Success and the write count RPMB_Write_Count control step S 308  is a forth sudden power off event SPO — 4. A power fail event occurs after the update success flag RPMB_Update_Success and the write count RPMB_Write_Count control step S 308  is a fifth sudden power off event SPO — 5. The different power fail events may be distinguished from each other based on the FAT block RPMB_FAT and/or the update success flag RPMB_Update_Success. 
       FIG. 4  is a flowchart depicting a power restoration process with respect to the RPMB update procedure of  FIG. 3 . In step S 402 , the FAT block RPMB_FAT is checked. As shown, the amount of programmed pages of the RPMB is checked. When there is an odd number of programmed pages in the FAT block RPMB_FAT, it means that the power failure event SPO — 2 or the power failure event SPO — 3 occurred before. Thus, step S 404  is performed and thereby the last programmed page of the FAT block RPMB_FAT is ignored. When it is determined in step S 402  that there is an even number of programmed pages in the FAT block RPMB_FAT and it is determined in step S 406  that the update success flag RPMB_Update_Success is “Fail”, it means that the power failure event SPO — 4 occurred before. Thus, step S 408  is performed and thereby the last programmed two pages of the FAT block RPMB_FAT are both ignored. When it is determined in step S 402  that there is an even number of programmed pages in the FAT block RPMB_FAT and it is determined in step S 406  that the update success flag RPMB_Update_Success is “Success”, it means that the power failure event SPO — 1 or the power failure event SPO — 5 occurred before. Because the data update had not happened yet when the power failure event SPO — 1 occurs and the data updated is finished when the power failure event SPO — 5 occurs, there is no data asynchronous problem due to the power failure events SPO — 1 and SPO — 5. Thus, data synchronization within each update of the replay protect memory blocks is confirmed and the step S 410  is performed to operate the FLASH memory without changing any page status of the FAT block RPMB_FAT. 
     In some exemplary embodiments, the controller  106  may include a computing unit and a read-only memory (ROM) stored with a ROM code. The ROM code may be coded according to the disclosure to be executed by the computing unit. The disclosed RPMB management, therefore, may be implemented by firmware. Further, any control method for a FLASH memory involving the disclosed RPMB management is also in the scope of the invention. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 6