Patent Abstract:
A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Full Description:
CLAIM OF PRIORITY 
     This application is a divisional of U.S. patent application Ser. No. 11/394,831 which was filed on Mar. 31, 2006 (now U.S. Pat. No. 7,692,295). 
    
    
     TECHNICAL FIELD 
     The invention relates to the field of microelectronics and more particularly, but not exclusively, to packaging wireless communications devices. 
     BACKGROUND 
     The evolution of integrated circuit designs has resulted in higher operating frequency, increased numbers of transistors, and physically smaller devices. This continuing trend has generated ever increasing area densities of integrated circuits and electrical connections. The trend has also resulted in higher packing densities of components on printed circuit boards and a constrained design space within which system designers may find suitable solutions. Physically smaller devices have also become increasingly mobile. 
     At the same time, wireless communication standards have proliferated as has the requirement that mobile devices remain networked. Consequently, many mobile devices include a radio transceiver capable of communicating according to one or more of a multitude of communication standards. Each different wireless communication standard serves a different type of network. For example, a personal area network (PAN), such as Blue Tooth (BT), wirelessly maintains device connectivity over a range of several feet. A separate wireless standard, such as IEEE 802.11a/b/g (Wi-Fi), maintains device connectivity over a local area network (LAN) that ranges from several feet to several tens of feet. 
     A typical radio transceiver includes several functional blocks spread among several integrated circuit packages. Further, separate packages often each contain an integrated circuit designed for a separate purpose and fabricated using a different process than that for the integrated circuit of neighboring packages. For example, one integrated circuit may be largely for processing an analog signal while another may largely be for computationally intense processing of a digital signal. The fabrication process of each integrated circuit usually depends on the desired functionality of the integrated circuit, for example, an analog circuit generally is formed from a process that differs from that used to fabricate a computationally intense digital circuit. Further, isolating the various circuits from one another to prevent electromagnetic interference may often be a goal of the designer. Thus, the various functional blocks of a typical radio transceiver are often spread among several die packaged separately. 
     Each package has a multitude of power, ground, and signal connections which affects package placement relative to one another. Generally, increasing the number of electrical connections on a package increases the area surrounding the package where trace routing density does not allow for placement of other packages. Thus, spreading functional blocks among several packages limits the diminishment in physical size of the radio transceiver, which in turn limits the physical size of the device in which the radio transceiver is integrated. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a block diagram of a prior art radio transceiver application. 
         FIG. 2  illustrates a block diagram of an exemplary single package radio transceiver application. 
         FIG. 3  illustrates a cross-sectional view of an exemplary single package radio transceiver. 
         FIG. 4  illustrates (1) an exemplary array of solder balls for coupling a single package radio transceiver to a printed circuit board and (2) an exemplary array of solder pads on a printed circuit board to which a single package radio transceiver may be coupled. 
         FIG. 5  illustrates an embodiment of a method of packaging a single package radio transceiver. 
         FIG. 6  illustrates a system schematic that incorporates an embodiment of a single package radio transceiver. 
     
    
    
     DETAILED DESCRIPTION 
     Herein disclosed are a package, a method of packaging, and a system including the package for an integrated, multi-die radio transceiver. 
     In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. Other embodiments may be utilized, and structural or logical changes may be made, without departing from the intended scope of the embodiments presented. It should also be noted that directions and references (e.g., up, down, top, bottom, primary side, backside, etc.) may be used to facilitate the discussion of the drawings and are not intended to restrict the application of the embodiments of this invention. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of the embodiments of the present invention is defined by the appended claims and their equivalents. 
     Description of a Radio Transceiver 
     Please refer to  FIG. 1  for a functional block diagram of a typical prior art radio transceiver application. 
     A typical radio transceiver usually includes several separate functional blocks, including a Front End Module (FEM)  106 , a Radio Frequency Integrated Circuit (RFIC)  108 , and a Base Band/Communication Processor  112 , that electrically couple to application specific circuitry  118 . The typical radio transceiver spreads the several functional blocks among different die and integrated circuit packages. The FEM  106  generally processes a radio frequency (RF) signal collected from an antenna  104 . The FEM  106  may include a low noise amplifier for small signal receiver gain larger than about 90 dB or a power amplifier for output power in excess of about 17 dBm or about 50 mW, and passive frequency selection circuits. The FEM  106  processes the RF signal before communicating a signal to the RFIC  108  for mixed signal processing. The RFIC  108  usually converts the RF signal from the FEM  106  to a digital signal and passes the digital signal to a Base Band/Communication Processor  112 . The Base Band/Communication Processor  112  generally communicates with application specific circuitry  118  that often includes an application processor  122  coupled to user interface peripherals  126  and a system memory  120 . In some instances, the Base Band/Communication Processor  112  is coupled to a memory  110  which may be on a separate die, or integrated into the die of the Base Band/Communication Processor  112 . Power consumption for the application processor may be managed by power management circuitry  124 . The RFIC  108  may also receive a signal input gathered from a Global Positioning System Receiver (GPS Receiver)  114 . 
     The FEM  106  and RFIC  108  are often on different die because of functional differences between the circuits that may not be easily achieved through the same die fabrication process. The Base Band/Communication Processor  112  may typically perform computationally intensive operations and therefore be fabricated using yet another process that differs from either of those used to fabricate the FEM  106  or the RFIC  108 . Further, the different die will often be packaged separately, although some prior art radio transceivers have integrated the FEM  106  and RFIC  108  within the same package, as indicated by the Prior Art Wireless Integration block  102 . Usually, the GPS Receiver  114  will also be packaged separately from other die. Further, the reference oscillator (crystal)  116  will generally be in a different package due to its sensitivity to temperature variance. 
     Current packages that integrate the FEM  106  and RFIC  108  use arrays use arrays of solder bumps on the individual die to couple the die to a package substrate. Further, the die are each disposed on the substrate in a substantially two-dimensional layout. A radio frequency transceiver integrated in a single package may address many shortcomings of present radio frequency transceivers. Because the different die will often be packaged separately, current system costs will often be higher than if the various die could be included in a single package. Further, because present systems continue to evolve to smaller form factors, a radio frequency transceiver integrated into a single package may help a system designer to achieve a desired overall system size that by itself being is smaller than a radio frequency transceiver spread among several packages. 
     Integration of a Radio Transceiver in a Single Package 
       FIG. 2  illustrates a functional block diagram of a system  200  using a radio frequency transceiver  202  wherein the radio frequency transceiver  202  is integrated into a single integrated circuit package, shown as  300  in  FIG. 3  and further described below. The radio frequency transceiver  202  includes an antenna  204 , an FEM (analog)  206 , an RFIC (mixed analog/digital)  208 , and a Base Band/Communication Processor (digital)  212 . The reference oscillator (crystal)  216  resides outside the integrated circuit package  300  because of its sensitivity to temperature and mechanical stress, both of which are often unavoidable during package assembly. Some embodiments of the radio frequency transceiver  202  also include a memory  210  coupled to the Base Band/Communication Processor  212 . Other embodiments of the radio frequency transceiver  202  may be capable of receiving input from other types of receivers, for example, a global positioning system receiver  214 . The signal collected by the alternative receiver  214  is transmitted to the RFIC  208 . The digital output of the Base Band/Communication Processor  212  couples to an application specific integrated circuit  218  that includes an application processor  222 . Further, the application processor  222  couples to a memory  220 , power management circuitry  224 , and any peripherals  226 . The peripherals  226  often include one or more of the following: an input/output interface, a user interface, an audio, a video, and an audio/video interface. 
     The application processor  222  often defines the standard used by the radio frequency transceiver  202 . Exemplary standards may include, by way of example and not limitation, a definition for a personal area network (PAN), such as Blue Tooth (BT), that wirelessly maintains device connectivity over a range of several feet, a local area network (LAN) that ranges from several feet to several tens of feet such as IEEE 802.11a/b/g (Wi-Fi), a metropolitan area network (MAN) such as (Wi-Max), and a wide area network (WAN), for example a cellular network. 
     An exemplary embodiment of a package  300  that integrates a radio frequency transceiver  202  is illustrated by  FIG. 3  and utilizes die stacking, or packaging in a third dimension, to alleviate many of the aforementioned problems, such as limited diminishment in size and increased packaging costs, associated with prior art two-dimensional layouts. The integrated radio frequency transceiver  202  in a single package  300  includes an antenna  204  formed by a copper stud  322  and a stack of a first die  306  and a second die  310  coupled to the package substrate  328 , to which is also coupled a third die  302 . 
     In the embodiment of  FIG. 3 , the third die  302  forms a front end module  206  and is coupled to the substrate  328  though solder bumps  304 . The third die may be formed substantially of gallium arsenide, silicon on sapphire, or silicon germanium. The second die  310  forms a Base Band/Communication Processor  210  and mechanically couples to the first die  306  that includes a radio frequency integrated circuit (RFIC)  208 . The first die  306  is electrically coupled to the substrate  328 , often through solder bumps  308 . For first die  306  sizes less than approximately 3.5 mm×3.5 mm underfill may often not be used. Larger first die  306  may utilize underfill. The second die  310  is electrically coupled to the substrate  328  through wire bonds  312 . One method of mechanically coupling the first die  306  and second die  310  includes using an interface bonding agent  314 , for example an epoxy. Many interface bonding agents  314  other than epoxy are known, e.g., RTV rubbers. The package  300  includes an antenna  204  formed of a copper stud  322  that couples to a package cover  334  that may act also as a heat spreader. Also included in the embodiment illustrated by  FIG. 3  is a fourth die  316  on which is formed memory  210 . The fourth die  316  couples to the circuitry of the second die  310  through a direct chip attach formed of solder bumps  318  and underfill  320 . Some embodiments of underfill  320  may include an adhesive tape or epoxy. Passive components  330  and  332 , such as inductor based components used for tuning, may be located at convenient locations on the substrate  328  if they are not included in the die  306  including the RFIC  208 . The passive components  330  and  332  may include high speed switching components formed on depleted CMOS devices, thereby enabling reconfigurable adaptive passive circuits. The package substrate  328  may have solder mask defined pads for surface mount components, and immersion gold plating may be used on the pads. 
     The embodiment of the package  300  shown includes an array of solder balls  326  that may be used to electrically and mechanically couple the package  300  to a printed circuit board (not shown). Some of the solder balls  326  may be arranged in groups  324  that will collapse and coalesce during reflow, and form a large area connection convenient for grounding the package  300 .  FIG. 4  illustrates a substrate  402  of a package  400  with an array of signal solder balls  404  and an array of ground solder balls  408 . The signal solder balls are distributed using a ball to ball pitch  406  that maintains the integrity of each solder ball  404 . The solder balls  408  used for grounding are distributed with a narrower pitch  410  such that on reflow the balls coalesce to form a larger area connection. The embodiment shown by  FIG. 4  includes solder balls  412  that may be used for power, ground, additional signals, or merely additional structural support without any electrical connectivity. A printed circuit board  414  may include arrays of exposed pads  416  and  418  similar to the arrays of solder balls. For example, the pitch  420  between exposed pads for the signals may be substantially similar to the pitch  406  for the signal solder balls  404 . Ground pads  418  may be a single large area of exposed metal, or an array of large exposed areas, similar to those shown. The substrate  414  may have outer metal layer thicknesses of approximately 35 μm and inner metal layer thickness ranging from approximately 60 μm to 150 μm. 
     A Single Package Radio Transceiver Assembly Method 
       FIG. 5  illustrates an exemplary method of integrating a multiple die in a single integrated circuit package. The method illustrated may be used to package a combination of die wherein some of the die forming the radio transceiver are stacked and form a three dimensional integration. For example, the method of  FIG. 5  includes soldering a first die to a package substrate having a layer of electrical traces and another layer of dielectric material  502 . A method similar to one illustrated by  FIG. 5  also includes mechanically coupling a second die to the first  504 . To achieve a functional die stack, wire bonds electrically couple the second die to the package substrate  506 . 
     As mentioned, the method illustrated by  FIG. 5  results in a substantially integrated radio frequency transceiver. The method illustrated by  FIG. 5  may be used to form a radio frequency transceiver capable of communicating according to any of a multitude of wireless standards that cover operation of networks ranging from personal area networks or local area networks to metropolitan area networks or wide area networks. Consequently,  FIG. 5  illustrates forming an antenna electrically coupled to the substrate  508  and soldering a third die to the substrate, wherein the antenna, first, second, and third die substantially form a radio transceiver  510 . The third die will often be substantially formed of gallium arsenide, silicon on sapphire, or silicon germanium, although other materials may often work as well. 
     In a radio frequency transceiver of the type whose assembly process is illustrated by  FIG. 5 , the second die substantially forms the often heavily computational, digital circuits of a base band communication processor. Some embodiments of a radio frequency transceiver couple memory to the digital circuits of the base band communication processor. Some of those embodiments may use a separate die for the memory and couple the memory die to the second die that substantially includes the digital circuits of the base band communications processor. A method of assembly, as illustrated by  FIG. 5 , may couple the memory die to the second die prior to mechanically coupling the second die to the first die  512 . 
     Further, radio frequency transceivers may often benefit from grounding through large area electrical ground connections. As described above, such connections may form when two or more solder balls collapse and coalesce during reflow and form an electrical connection with larger cross-sectional area than a single constituent solder ball  514 . 
     A System Embodiment that Includes a Single Package Radio Transceiver 
       FIG. 6  illustrates a schematic representation of one of many possible systems  60  that incorporate an embodiment of a single package radio transceiver  600 . In an embodiment, the package containing a radio frequency transceiver  600  may be an embodiment similar to that described in relation to  FIG. 3 . In another embodiment, the package  600  may also be coupled to a sub assembly that includes a microprocessor. In a further alternate embodiment, the integrated circuit package may be coupled to a subassembly that includes an application specific integrated circuit (ASIC). Integrated circuits found in chipsets (e.g., graphics, sound, and control chipsets) or memory may also be packaged in accordance with embodiments described in relation to a microprocessor and ASIC, above. 
     For an embodiment similar to that depicted in  FIG. 6 , the system  60  may also include a main memory  602 , a graphics processor  604 , a mass storage device  606 , and an input/output module  608  coupled to each other by way of a bus  610 , as shown. Examples of the memory  602  include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of the mass storage device  606  include but are not limited to a hard disk drive, a flash drive, a compact disk drive (CD), a digital versatile disk drive (DVD), and so forth. Examples of the input/output modules  608  include but are not limited to a keyboard, cursor control devices, a display, a network interface, and so forth. Examples of the bus  610  include but are not limited to a peripheral control interface (PCI) bus, PCI Express bus, Industry Standard Architecture (ISA) bus, and so forth. In various embodiments, the system  60  may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, an audio/video controller, a DVD player, a network router, a network switching device, a hand-held device, or a server. 
     Although specific embodiments have been illustrated and described herein for purposes of description of an embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve similar purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. For example, a processor and chipset may be integrated within a single package according to the package embodiments illustrated by the figures and described above, and claimed below. Alternatively, chipsets and memory may similarly be integrated, as may be graphics components and memory components. 
     Those with skill in the art will readily appreciate that the description above and claims below may be implemented using a very wide variety of embodiments. This detailed description is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Technology Classification (CPC): 7