Patent Abstract:
A single-inductor multiple-output (SIMO) power converter converts an input voltage into an output voltage and a biasing voltage. The SIMO power converter comprises an inductor and a primary power switch, and a control circuit. The inductor is configured for storing energy from the input voltage. The primary power switch has a control node and is connected between the inductor and the output voltage which powers an output load. The control circuit controls the primary power switch comprising an auxiliary power switch and a driver. The auxiliary power switch is connected between the inductor and the biasing voltage. The driver, powered by the biasing voltage, drives the control node. The biasing voltage determines a signal level at the control node. The primary power switch and the auxiliary power switch are controlled to distribute the energy stored in the inductor to the output voltage and the biasing voltage.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Taiwan Application Series Number 104102059 filed on Jan. 22, 2015, which is incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    The present disclosure relates generally to single-inductor multiple-output (SIMO) based DC-DC converters, more especially to SIMO based converters with adaptive gate biasing (AGB) technique for thermoelectric energy harvesting. 
         [0003]    Energy harvested from the environment can be used to develop battery-free electronics systems or prolong battery life. Among the different green energy sources from ambient environment such as light, motion, and heat, thermal power from human body is an efficient and reliable energy source for wearable applications. However, the output voltage of thermoelectric generators (TEGs) is typically less than 100 mV for a thermal difference of 2K depending on the temperature dependent output characteristics range of 10 mV/K to 50 mV/K. Moreover, considering the limited power budget of TEGs, the load system typically requires digital circuits operating in the near-threshold region to reduce power dissipation. Therefore, a power converter that can convert the harvested energy to a near-threshold output is required to realize an energy efficient system. However, designing a high efficiency low-V IN  low-V OUT  converter is challenging owing to the significant conduction losses (P CONDUCTION ) in power transistors. 
         [0004]    Numerous thermoelectric energy harvesting power converters have been proposed in the art for low V IN  and low power operation. However, the output stages of these power converters are greater than 0.9V. A two-stage topology with a cascaded auxiliary boost converter and a DC-DC buck converter has been proposed, as shown in  FIG. 1 . An auxiliary boost converter with an additional off-chip inductor L AUX  acts as a buffer, and the DC-DC buck converter maintains the V OUT  value at 1.8V. With this two-stage topology, the low V IN  and low V OUT  specifications can be realized because V OUT  can be regulated to any desired level. However, this structure in  FIG. 1  has low efficiency because of the two-stage conversion and high conversion ratio in the auxiliary boost converter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted. 
           [0006]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0007]      FIG. 1  shows a thermoelectric energy harvesting power converter in the art; 
           [0008]      FIG. 2  shows a single-stage power converter according to embodiments of the invention; 
           [0009]      FIG. 3  shows a conceptual block diagram of the AGB technique; 
           [0010]      FIG. 4A  shows the circuit schematic of the primary boost converter  20  in  FIG. 3 ; 
           [0011]      FIG. 4B  demonstrates the conversion efficiencies of converters with AGE, technique and without AGB technique respectively; 
           [0012]      FIG. 5  shows the primary boost converter and the biasing voltage generator  14  in  FIG. 3 ; 
           [0013]      FIG. 6  demonstrates the PWM generator in  FIG. 3 , including a latch comparator and a 7-bit DPWM (digital PWM) generator; 
           [0014]      FIG. 7  details the P OUT  detector and the level-shift module in  FIG. 3 ; 
           [0015]      FIGS. 8A and 8B  demonstrates the latch comparators PD 1  and PD 2 , respectively; 
           [0016]      FIG. 9  shows four different operation statuses PathA, PathB, PathC, and PathD for the SIMO of  FIG. 5 ; 
           [0017]      FIGS. 10A, 10B, 10C and 10D  show the inductor current waveforms when the SIMO of  FIG. 5  operates at the four statuses, respectively; and 
           [0018]      FIG. 11  shows the energy delivery mechanism of near-V TH  ERC and skipping modulation in response to skip signals S KIP1  and S KIP2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    An embodiment of the invention introduces a 100 mV V IN , 500 mV V OUT  high-efficiency SIMO-based boost converter for harvesting thermoelectric energy generated by thermoelectric generators.  FIG. 2  shows a single-stage power converter according to embodiments of the invention, which employs adaptive gate biasing (AGB) technique and near-threshold voltage (near-V TH ) energy redistribution control (ERC). To improve the conversion efficiency at low V OUT , two key techniques are used. (1) An AGB technique that provides dual load-dependent voltages (gate biasing voltages V AGB1  and V AGB2 ) for driving the power transistors of the primary boost converter. This technique improves the conversion efficiency by reducing P CONDUCTION  and switching loss (P SWITCHING ) at different load conditions and providing a self-calibration mechanism against V TH  variation. (2) A near-V TH  ERC mechanism that is powered by V OUT  and manages the power delivery strategy of output voltage V OUT , V AGB1 , and V AGB2 . One embodiment of the invention achieves a maximum efficiency of 83.4% at an output power (P OUT ) of 250 uW, and power efficiency greater than 80% over the output power range of 150 uW to 450 uW. In addition, the core controller is implemented using 7-bit delay-line based digital pulse width modulation (DPWM), which not only reduces the quiescent power to 0.48 uW but also ensures reliable digital operation with the near-V TH  power supply form output voltage V OUT . 
         [0020]      FIG. 3  shows a conceptual block diagram of the AGB technique. PWM generator  18  in the AGB circuit  10  provides digital PWM signal CK PWM  based on a clock signal CK, output voltage V OUT  and reference voltage V REF . The P OUT  detector  12 , powered by output voltage V OUT , senses the voltage difference between V X  and V SS  when M N1  is ON, and the voltage difference between V X  and V OUT  when M N2  is ON. As indicated in  FIG. 3 , V SS  is the voltage at a ground line and V X  is at the joint node between M N2  and M N1 . Outputs V GP1  and V GP2  of the P OUT  detector  12  control the biasing voltage generator  14  to generate gate biasing voltages V AGB1  and V AGB2  which perform as power sources for level-shift and driver module  16 . Based on the PWM signal CK PWM  and outputs of the P OUT  detector  12 , level-shifter and driver module  16  provides gate control signals V GN1  and V GN2 , whose signal levels are determined by gate biasing voltages V AGB1  and V AGB2  respectively. Therefore, this AGB technique can reduce P CONDUCTION  and P SWITCHING  by providing appropriate gate overdrive voltages. It also precludes output voltage V OUT  from a tradeoff between output load demand and the performance of the power converter and compensates for threshold voltage V TN  shift due to process or temperature variation. The operation principle and implementation of the AGB technique are described in detail below. 
         [0021]      FIG. 4A  shows the circuit schematic of the primary boost converter  20  in  FIG. 3 . This primary boost converter  20  includes an inductor L BOOST  N-type power transistors M N2  and M N2 , and the output capacitor C OUT . This primary boost converter  20  stores energy when the power transistor M N2  turns ON (M N2  turns OFF) to operate under status PhaseA. The stored energy is then delivered to output voltage V OUT  when the power transistor M N2  turns ON (M N2  turns OFF) to operate at status PhaseB. In one embodiment, because output voltage V OUT  is targeted to be 0.5V, in the near-V TH  region, an N-type power transistor M N2  is employed as the high-side power transistor. Compared with a P-type transistor, an N-type power transistor has higher mobility and superior area efficiency. In addition, only a positive voltage is required for driving an N-type power transistor whereas a voltage ranging from positive to negative potential is essential for a P-type transistor to effectively implement the AGB algorithm. Therefore, in one embodiment, no additional negative voltage converter is required and implemented, and the complexity of the circuit design is reduced. 
         [0022]    To simplify the analysis, it is assumed that the primary boost converter  20  operates under continuous conduction mode (CCM), and the inductor current ripple is negligible. In a steady state, P CONDUCTION  of power transistors M N2  and M N2  can be expressed as 
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         [0023]    where I L  is the average inductor current flowing through the inductor L BOOST , R DS1,ON  and P DS2,ON  are the on-resistances of power transistors M N1  and M N2r  respectively. Further, T is the clock period, and D is the duty cycle of the signal provided to the power transistor M N1  in a steady state. For a boost converter, the relation between I L  and the output load current I LOAD  can be expressed as 
         [0000]    
       
         
           
             
               
                 
                   
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         [0024]    Therefore, the correlation between P CONDUCTION  and I LOAD  can be derived as 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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         [0025]    Hence, if the duty cycle, operation frequency, fabrication process and transistor size of the power transistors are known, P CONDUCTION  is in proportion to the square of I LOAD  and increases dramatically as I LOAD  increases, as given by the equation (3). 
         [0026]    By detecting the voltage drop across the power transistors and adjusting the corresponding gate biasing voltages, the proposed AGB technique maintains the turn-on voltages V DS1,ON  and V DS2,ON  to be about constant. 
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         [0027]    Therefore, the total conduction loss can be derived from equations (3), (4), and (5) as 
         [0000]    
       
         
           
             
               
                 
                   
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                     CONDUCTION 
                   
                   = 
                   
                     
                       
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                         LOAD 
                       
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                   ( 
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         [0028]    If turn-on voltages V DS1,ON  and V DS2,ON  are constant, P CONDUCTION  is proportional only to I LOAD  in equation (6) instead of the square function in the conventional equation (3). Therefore, under heavy loads, the conversion efficiency can be improved by employing the AGB technique. 
         [0029]    On the other hand, under light-load conditions, P CONDUCTION  decreases due to the reduced I L  flowing through power transistors, and P SWITCHING  dominates the overall efficiency. The AGB technique detects the decreasing turn-on voltages V DS1,ON  and V DS2,ON , and the potentials of V AGB1  and V AGB2  are simultaneously reduced to maintain the turn-on voltages V DS1,ON  and V DS2,ON  across the power transistors M N1  and M N2 . Therefore, lower values of gate biasing voltages V AGB1  and V AGB2  decrease P SWITCHING  as given by 
         [0000]        P   SWITCHING   =f   CK   C   GATE1   V   AGB1   2   +f   CK   C   GATE2   V   AGB2   2   (7)
 
         [0030]    where f CK  is the operation frequency (=1/T), and C GATE1  and C GATE2  are the gate capacitances of the power transistors M N1  and M N2 , respectively. Because P SWITCHING  is proportional to the square of the gate biasing voltages, V AGB1  and V AGB2  power efficiency is predicted to be higher with the AGB technique under light load. Therefore, by applying the AGB technique, both light-load and heavy-load efficiencies can be improved, as shown in  FIG. 4B . The AGB technique automatically adjusts gate biasing voltages V AGB1  and V AGB2  according to I LOAD , so as to manipulate the on-resistances R DS1,ON  and R DS2,ON , thus resulting in significant suppression of losses under different load conditions. 
         [0031]    AGB circuit  10  in  FIG. 3  implements the AGB technique, providing a feedback mechanism to regulate or maintain both turn-on voltages V DS1,ON  and V DS2,ON  to be about constant, independent from the load condition. 
         [0032]      FIG. 5  shows the primary boost converter  20  and the biasing voltage generator  14  in  FIG. 3 , both composing a SIMO to simultaneously generate output voltage V OUT , and gate biasing voltages V AGB1  and V AGB2  Capacitors C 1  and C 2  are used to stabilize gate biasing voltages V AGB1  and V AGB2  Inductor L BOOST  N-type power transistors M N1  and M N2 , and P-type power transistor M P1  and M P2  are responsible for the energy stored and released in different time slots within a period T. Energy is delivered from input voltage V IN  via being stored in inductor L BOOST , and then distributed to the three output terminals through time-multiplexing control accompanied with skipping modulation, which precludes output voltage V OUT  from the crosstalk between gate biasing voltages V AGB1  and V AGB2  and will be discussed later. 
         [0033]      FIG. 6  demonstrates the PWM generator  18  in  FIG. 3 , including a latch comparator  22  and a 7-bit DPWM (digital PWM) generator  24 . The latch comparator  22  compares output voltage V OUT  with a reference voltage V REF , which is 0.5V for this embodiment, and controls the duty cycle of DPWM signal CK PWM  via the high-resolution DPWM unit  24 . For instance, if output voltage V OUT  is below reference voltage V REF  the duty cycle of DPWM signal CK PWM  increases stepwise by a fixed amount. Accordingly, in a steady state, output voltage V OUT  could be regulated at the reference voltage V REF  To reduce power consumption by DPWM unit  24  and the driver circuit, a clock frequency of 100 kHz is selected in this embodiment, as demonstrated by the reference clock signal CK in  FIG. 6 . 
         [0034]      FIG. 7  details the P OUT  detector  12  and level-shift and driver module  16  of  FIG. 3 . The P OUT  detector  12  has latch comparators PD 1  and PD 2 , and ERC unit  26 , while the level-shift and driver module  16  has level shifters  28  and  30 , and drivers  32  and  34 . 
         [0035]    The latch comparator PD 1  detects the voltage difference between V X  and V SS  during the ON time of the power transistor M N1 . In other words, it detects the turn-on voltage V DS1,ON , with which a predetermined value V OFFSET1  is compared to generate skip signal S KIP1  Similarly, the latch comparator PD 2  detects the voltage difference between V X  and output voltage V OUT , which is the turn-on voltage V DS2,ON  Turn-on voltage V DS2,ON  is compared with a predetermined value V OFFSET2  to generate skip signal S KIPS . When S KIP1  is “1” in logic, it means turn-on voltage V DS1,ON  is below or equal to the predetermined value V OFFSET1 . When S KIP1  is “0” in logic, turn-on voltage V DS1,ON  exceeds the predetermined value V OFFSET1 . Skip signal S KIP2  in logic “1” means the turn-on voltage V DS2,ON  is below or equal to the predetermined value V OFFSET2 , while that in logic “0” means the turn-on voltage V DS2,ON  exceeds the predetermined value V OFFSET2 . The latch comparators PD 1  and PD 2  are illustrated in  FIGS. 8A and 8B , respectively. The predetermined value V OFFSET1  is implemented using the intentionally mismatched PMOSFET input pair in  FIG. 8A , and the predetermined value V OFFSET2  is implemented using the intentionally mismatched NMOSFET input pair in  FIG. 8B . In  FIG. 7 , ERC unit  26  decides whether to pull low gate control signals V GP1  and V GP2  at corresponding time slots, depending on skip signals S KIP1  and S KIP2 . 
         [0036]      FIG. 9  shows four different operation statuses PathA, PathB, PathC, and PathD for the SIMO of  FIG. 5 .  FIGS. 10A, 10B, 10C and 10D  show the inductor current waveforms when the SIMO of  FIG. 5  operates at the four statuses, respectively. Under operation status PhaseA, power transistor M N1  turns ON and the energy is stored from input voltage V IN  in inductor L BOOST , and the duty cycle CK PWM  for this time slot is determined by the 7-bit DPWM unit  24 . Part of the energy accumulated in status PhaseA is then distributed to gate biasing voltage V AGB2  under the status PhaseD, via the turn-on of power transistor M P2 , where gate biasing voltage V AGB2  is the highest voltage in this system for this embodiment. Sequentially and similarly, the energy accumulated in status PhaseA is partially provided for gate biasing voltage V AGB1  under the status PhaseC, via the turn-on of power transistor M P1 . Finally, output voltage V OUT  receives the rest of the accumulated energy under status PhaseB to fulfill the output load. Even though the status sequence shown in  FIGS. 10A to 10D  is (PhaseA, PhaseD, PhaseC, PhaseB), this invention is not limited to, and a different status sequence is possibly employed in another embodiment. Statuses PhaseD and PhaseC are necessary for generating adaptive gate biasing voltages V AGB1  and V AGB2 ; however, they inevitably cause discontinuous conduction and disturbance for primary output voltage V OUT . To overcome this problem, the pulse width of the driving signals provided for power transistors M P1  and M P2  is limited to 100 ns to restrict the amount of power transferred to gate biasing voltages V AGB1  and V AGB2 . In other words, if any of power transistors M P1  and M P2  turns ON, the ON time will be always 100 ns. Additionally, status PhaseD is activated only when the turn-on voltage V DS2,ON  exceeds the predetermined value V OFFSET2  while status PhaseC is activated only when the turn-on voltages V DS1,ON  exceeds the predetermined value V OFFSET1 . 
         [0037]    The power consumed by gate biasing voltages V AGB1  and V AGB2  is typically less than one percent of that of the primary output voltage V OUT . Therefore, the ERC unit  26  in  FIG. 7  implements a skipping modulation mode to avoid large disparity in load conditions among V AGB1 , V AGB2  and V OUT .  FIG. 11  shows the energy delivery mechanism of near-V TH  ERC and skipping modulation in response to skip signals S KIP1  and S KIP2  Generally, three output terminals receive energy to maintain their voltage levels, as shown in mode IV when skip signals S KIP1  and S KIP2  are both “0” in logic. In the mode III when skip signals S KIP1  and S KIP2  are “0” and “1” respectively, the status PhaseD is skipped and gate biasing voltage V AGB2  does not receive energy. Similarly, In the mode II when skip signals S KIP1  and S KIP2  are “1” and “0” respectively, the status PhaseC is skipped and gate biasing voltage V AGB1  does not receive energy. When both the gate biasing voltages V AGB1  and V AGB2  are high enough to keep the turn-on voltages V DS1,ON  and V DS2,ON  below or equal to the predetermined values V OFFSET1  and V OFFSET2  respectively, P-type power transistors M P1  and M P2  are constantly kept OFF, and both the statuses PhaseC and PhaseD are skipped, as shown in the mode I. If the status PhaseC (PhaseD) is skipped, the gate biasing voltages V AGB1  (V AGB2 ) ramps down due to P SWITCHING , and the turn-on voltage V DS1,ON  (V DS2,ON ) in a subsequent switch cycle increases as a result. Therefore, by appropriate energy delivery management, the proposed near-V T  ERC and skipping modulation technique ensure that each of three voltages is sufficiently isolated and independent of the others to stabilize the entire power converter. 
         [0038]    It is shown by the mode IV in  FIG. 11  that the 100 nS after status PhaseA is for status PhaseD, the 100 nS after which is for status PhaseC, which is followed by status PhaseB. 
         [0039]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 7