Patent Abstract:
A structure. The structure includes a substrate. A first dielectric layer is on and in direct mechanical contact with the substrate. A first hard mask is on the first dielectric layer. A first and second trench is within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is on sidewalls of the first and second trenches. The first conformal liner is in direct physical contact with the substrate, the first dielectric layer, and the first hard mask A first conductive material that includes copper fills the first and second trenches. A planar surface of the first conductive material is coplanar with a top surface of the first conformal liner and a top surface of the first hard mask.

Full Description:
[0001]     This application is a Divisional of Ser. No. 10/906,552, filed Feb. 24, 2005. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates generally to semiconductor devices, and more particularly, to a method of forming low capacitance back end of the line (BEOL) wiring, and the structure so formed.  
         [0004]     2. Related Art  
         [0005]     When forming CMOS, BiCMOS, SiGe, and other similar devices, it is desirable to minimize capacitance. Likewise, there is a continuing desire in the industry to reduce device size. Therefore, there is a need in the industry for a method of forming a semiconductor device that addresses these and other issues.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides a method of forming a semiconductor device having a low wire capacitance and a high wire resistance, and the structure so formed, that solves the above-stated and other problems. The device comprises conductive wires having widths substantially smaller than the width of the printed and etched trench and/or via formed for the wire.  
         [0007]     A first aspect of the invention provides a method of forming a semiconductor device, comprising: providing a substrate; depositing a first dielectric layer; depositing a hard mask on the first dielectric layer; forming an at least one first feature within the first dielectric layer and the hard mask; depositing a conformal dielectric liner over the hard mask and within the at least one feature, wherein the liner occupies more than at least 2% of a volume of the at least one feature; depositing a conductive material over the liner; and planarizing a surface of the device to remove excess conductive material.  
         [0008]     A second aspect of the invention provides a method of forming a semiconductor device, comprising: providing a substrate; depositing a first dielectric layer; forming an at least one feature within the first dielectric layer; depositing a conformal dielectric liner over a surface of the device and within the at least one feature, wherein a thickness of the liner is at least approximately ⅓ a minimum width of the at least one feature; and metallizing the at least one feature.  
         [0009]     A third aspect of the invention provides a semiconductor device, comprising: a substrate; a first dielectric layer on a surface of the substrate; a hard mask on the first dielectric layer; at least one first feature within the first dielectric layer and the hard mask; a conformal dielectric liner over the hard mask and within the at least one feature, wherein the liner occupies more than at least 2% of a volume of the at least one feature; and a conductive material within the at least one feature.  
         [0010]     A fourth aspect of the present invention provides a method of forming a structure, and the structure so formed, comprising a dual damascene structure wherein a via of the dual damascene features may be formed having a width equal to, or up to ⅓ less than, a minimum trench width, and wherein a thickness of a conformal dielectric liner within the feature occupies more than at least approximately 2% of the feature volume.  
         [0011]     The foregoing and other features and advantages of the invention will be apparent from the following more particular description of the embodiments of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:  
         [0013]      FIG. 1  depicts a cross-sectional view of a device comprising a first dielectric layer, a first hard mask and a photoresist layer thereon, in accordance with embodiments of the present invention;  
         [0014]      FIG. 2  depicts the device of  FIG. 1  having trenches formed therein;  
         [0015]      FIG. 3  depicts the device of  FIG. 2  having a conformal liner thereon;  
         [0016]      FIG. 4  depicts the device of  FIG. 3  following an etch back process;  
         [0017]      FIG. 5  depicts the device of  FIG. 4  following metallization;  
         [0018]      FIG. 6  depicts the device of  FIG. 5  following planarization;  
         [0019]      FIG. 7  depicts the device of  FIG. 6  having a second dielectric layer, hardmask and photoresist layer;  
         [0020]      FIG. 8  depicts the device of  FIG. 7  having a plurality of trenches formed therein;  
         [0021]      FIG. 9  depicts the device of  FIG. 8  having a conformal liner thereon;  
         [0022]      FIG. 10  depicts the device of  FIG. 9  having a photoresist layer thereon;  
         [0023]      FIG. 11  depicts the device of  FIG. 10  following photoresist patterning;  
         [0024]      FIG. 12  depicts the device of  FIG. 11  having a plurality of narrow vias formed within the trenches;  
         [0025]      FIG. 13  depicts the device of  FIG. 12  following metallization;  
         [0026]      FIG. 14  depicts the device of  FIG. 13  following planarization;  
         [0027]      FIG. 15  depicts the device of  FIG. 11  having a plurality of wide vias formed within the trenches;  
         [0028]      FIG. 16  depicts the device of  FIG. 15  following metallization;  
         [0029]      FIG. 17  depicts the device of  FIG. 16  following planarization;  
         [0030]      FIG. 18  depicts the device of  FIG. 11  following photoresist patterning;  
         [0031]      FIG. 19  depicts the device of  FIG. 18  having a plurality of vias formed therein;  
         [0032]      FIG. 20  depicts the device of  FIG. 19  having a conformal liner deposited over the device;  
         [0033]      FIG. 21  depicts the device of  FIG. 20  having a plurality of layers deposited over the liner;  
         [0034]      FIG. 22  depicts the device of  FIG. 21  following photoresist patterning;  
         [0035]      FIG. 23  depicts the device of  FIG. 22  following etching;  
         [0036]      FIG. 24  depicts the device of  FIG. 23  following additional etching;  
         [0037]      FIG. 25  depicts the device of  FIG. 24  having trenches formed therein;  
         [0038]      FIG. 26  depicts the device of  FIG. 25  having a conformal liner deposited thereover;  
         [0039]      FIG. 27  depicts the device of  FIG. 26  following etching;  
         [0040]      FIG. 28  depicts the device of  FIG. 27  following metallization; and  
         [0041]      FIG. 29  depicts the device of  FIG. 28  following planarization. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0042]     Although certain embodiments of the present invention will be shown and described in detail, it should be understood that various changes and modifications might be made without departing from the scope of the appended claims. The scope of the present invention will in no way be limited to the number of constituting components, the materials thereof, the shapes thereof, the relative arrangement thereof, etc. Although the drawings are intended to illustrate the present invention, the drawings are not necessarily drawn to scale.  
         [0043]      FIG. 1  depicts a semiconductor device  10  having a substrate  12 , which may comprise conventional features (not shown), such as, a plurality of shallow trench isolations (STI), a MOS transistor and spacers, a vertical NPN transistor, a plurality of contacts damascened into a dielectric, etc., as is known in the art. The substrate  12  is preferably substantially planar, as shown in  FIG. 1 .  
         [0044]     In accordance with the present invention, a first dielectric layer  14  is deposited over a surface of the substrate  12 . The first dielectric layer  14  may comprise a dielectric material having a low dielectric constant (k), wherein “low k” is defined as a dielectric constant (k) below 3.0, or in the range of approximately 1.5-2.7, such as porous poly(areylene) ether (e.g., porous SiLK™ (Dow Chemical)), porous SiCOH, porous SiO 2 , teflon, amorphous carbon, etc. The first dielectric layer  14  may be deposited using chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), spin-on deposition, etc., to a thickness of approximately 150-200 nm.  
         [0045]     A hard mask  16  is then deposited over the first dielectric layer  14 . The hard mask  16  may comprise a dielectric material, such as SiC, SiCN, SiCOH, SiO 2 , Si 3 N 4 , etc. The hard mask  16  may be deposited using CVD, PECVD, etc., to a thickness of approximately 1-100 nm, e.g., 10 nm. The hard mask  16  protects the first dielectric layer  14  during subsequent processing, and is optional.  
         [0046]     A photoresist  18  is then applied over the hard mask  16 , as illustrated in  FIG. 1 . The photoresist  18  may be applied to a thickness in the range of approximately 50-3000 nm, e.g., 200 nm. The photoresist  18  may comprise a positive or negative photoresist  18  as desired. The photoresist  18  is patterned, and the first dielectric layer  14  and hard mask  16  are etched using standard back end of the line (BEOL) exposure and reactive ion etch (RIE) formation techniques to form trenches  20   a ,  20   b  ( FIG. 2 ). Narrower trenches  20   a  may be formed having an aspect ratio (height:width) in the range of approximately 2:1, and a minimum trench width  22   a  in the range of approximately 100-150 nm. Wider trenches  20   b  may be formed having any width, and a wide range of aspect ratios, e.g., an aspect ratio of approximately 1:2, 1:10, etc. The wider trenches  20   b  may also be formed with an optional “dummy fill” in the very large trenches  20   b  (e.g., a width greater than 2 microns) to reduce the patterned factor, as known in the art.  
         [0047]     During the standard BEOL formation process the photoresist  18  may be completely consumed during the RIE etch used in conjunction with a p-SiLK first dielectric layer  14 , as illustrated in  FIG. 2 . Alternatively, a multi-layer hard mask may be used (not shown), such as a first lower hard mask layer, (SiC), and a second upper hard mask layer, (SiO 2 ). When using the multi-layer hard mask set the SiO 2  is patterned and etched down to the SiC. The photoresist used to pattern the SiO 2  is removed. The SiO 2  is then used to pattern and etch the SiC. The remaining combination of SiO 2  and SiC are then used to pattern the underlying first dielectric layer  14 , as known in the art.  
         [0048]     As illustrated in  FIG. 3 , a conformal dielectric liner  24  is deposited over the surface of the device  10 . The liner  24  may comprise a dielectric material having a low dielectric constant (k), wherein “low k” is defined as a dielectric constant (k) preferably below 3.0, or in the range of approximately 1.4-4.5, such as SiCOH, SiO 2 , poly(areylene) ether (e.g., SiLK™ (Dow Chemical)), teflon, or other similarly used material. The liner  24  may be deposited using PECVD, CVD, or other similar deposition techniques. The liner  24  may have a thickness up to approximately ½ the width of the minimum trench width  22   a , and preferably ⅓ the width of the minimum trench width  22   a  ( FIG. 2 : 100-200 nm), i.e., a thickness in the range of approximately 30-50 nm. As a result, the liner  24  occupies more than at least 2% of a trench volume, e.g., at least 50%, or more, of the trench volume. The liner  24  must be prevented from “pinching off” (filling in the opening of the trenches  20   a ,  20   b ) which would prevent subsequent metallization of the trenches  20   a ,  20   b.    
         [0049]     A spacer etch back process is performed to remove a portion of the liner  24  from a base  31  of the trenches  20   a ,  20   b , while leaving the liner  24  on the sidewalls  33  of the trenches  20   a ,  20   b , as illustrated in  FIG. 4 .  
         [0050]     As illustrated in  FIG. 5 , a conductive liner  26 , a seed layer  28  and a conductive layer  30  are deposited during a standard metallization process. The conductive liner  26  may be deposited over the surface of the device  10  using sputtering techniques, such as plasma vapor deposition (PVD), ionized plasma vapor deposition (IPVD), self-ionized plasma (SIP), HCM, chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc. Likewise, the seed layer  28  may be deposited over the conductive liner  26  using similar sputtering techniques, i.e., PVD, IPVD, SIP, HCM, CVD, ALD, MOCVD, etc. The conductive liner  26  may comprise one or more refractory metals or alloys, such as Ta, TaN, TiN, W, WN, TaSiN, WSiN, or other similarly used material. The conductive liner  26  may have a thickness in the range of approximately 1-200 nm, e.g., 5 nm. The seed layer  28  may comprise a copper seed material, or other similarly used material for the subsequent electroplating deposition. The seed layer  28  may have a thickness in the range of approximately 1-200 nm, e.g., 20 nm. The conductive layer  30  may comprise copper, or other similarly used material. The conductive layer  30  may be formed having a thickness in the range of approximately 50 nm-5 microns, e.g., 200 nm. It should be noted that the conductive liner  26  and the seed layer  28  are not drawn to scale for purposes of illustration.  
         [0051]     Following deposition of the metallization, (the conductive liner  26 , the seed layer  28  and the conductive layer  30 ), a planarization process is performed to remove the excess metallization on the surface of the device  10 . A chemical mechanical polish (CMP) or other similarly used process may be used to planarize the surface of the device  10 . The planarization process is performed down to the conformal dielectric liner  24 , as illustrated in  FIG. 6 . Alternatively, the planarization process may be performed down to the hard mask  16  (not shown). A first metal wiring level  44 , having a plurality of electrically conductive wires  32   a ,  32   b  therein, in this example comprising a single damascene wiring structure, is produced following the planarization process.  
         [0052]     As illustrated in Table 1, infra, the present invention produces a device  10  having a capacitance far lower, and a wire resistance much higher, than that of similar devices formed using conventional formation methods.  
                                                                                 TABLE 1                           Comparison of Capacitance and wire Resistance measurements       normalized to the Conventional Device A.            BEOL device dielectric                   layer 14 liner 24       Line-to-Line   Capacitance       (wire dimensions)   Resistance   Capacitance   between wiring       (aspect ratio)   per micron   per micron   levels per micron                    Conventional Device            A. SiCO (k = 2.7)   1   1   1       (140 nm × 200 nm)       (1.4:1)            Present Invention            B. p-SiLK (k = 2.2)   5   0.4   0.7       SiCOH liner (k = 2.7)       (50 nm × 150 nm)       (3:1)       C. p-OSG (k = 1.6)   5   0.3   0.5       SiCOH liner (k = 2.7)       (50 nm × 150 nm)       (3:1)       D. p-OSG (k = 1.6)   20   0.15   0.3       SiCOH liner (k = 2.7)       (25 nm × 75 nm)       (3:1)                 (* The “p-” indicates that the dielectric is a porous dielectric. The “k” stands for dielectric constant.)             
 
         [0053]     As illustrated by examples B-D under the “Present Invention” in Table 1, using a low k dielectric material for the first dielectric layer  14 , in conjunction with a low k dielectric liner  24  reduces the overall capacitance of the device  10  and increases the wire resistance. In fact, the lower the dielectric constant (k) of the first dielectric layer  14  the more the capacitance of the device is reduced (compare example B with examples C and D) and the more the wire resistance is increased.  
         [0054]     As illustrated in  FIG. 6 , the wires  32   a ,  32   b  have a far smaller width  40   a ,  40   b  as compared to the trench widths  36   a ,  36   b , respectively, made available for wiring during patterning and etching. In fact, the wires  32   a ,  32   b  have a width  40   a ,  40   b  in the range of approximately ⅓-⅔ the widths  36   a ,  36   b  of the trenches  20   a ,  20   b , respectively. Typically this would be considered undesirable because it tends to increase wire resistance. The present invention, however, is not concerned with wire resistance, and may be used in conjunction with devices that are not affected by wire resistance, such as ultra low power CMOS devices, wherein the power consumption is determined primarily by the transistor driver resistance and the wire capacitance. By reducing the size (e.g., height  42  and width  40   a ,  40   b ) of the wires  32   a ,  32   b , the capacitance of the device  10  can be reduced even further, (compare examples C and D of Table 1). Therefore, it is possible in the present invention to pattern and etch the trenches  20   a ,  20   b  having an aspect ratio of 2:1, but end up with much narrower conductive wires  32   a ,  32   b  within the trenches  20   a ,  20   b  having an aspect ratio of 5:1.  
         [0055]     A dual damascene structure may also be formed in accordance with the present invention. As illustrated in  FIG. 7 , a second wiring level  45   a  may be formed on the first wiring level  44 , in this example comprising a dual damascene wiring structure. First, a capping layer  46  is deposited over the first metal wiring level  44 . The capping layer  46  may comprise SiCN, or other similarly used material. The capping layer  46  may be deposited using CVD, PECVD, etc., having a thickness in the range of approximately 5-100 nm, e.g., 20 nm. The purpose of the capping layer  46  is to prevent diffusion of copper from the conductive wire  32   a ,  32   b  formed in the first wiring level  44  into the dielectric layer  48  in the second wiring level  45   a . The capping layer  46  may also optionally be used as an etch stop layer during patterning and etching of the vias in the second wiring level  45 . Alternatively, the capping layer  46  could be replaced (not shown) by a selective conductive cap, such as electroless plated COWP; a damascene conductor, such as Ta; a dielectric, such as SiCN; or a substantially etched dielectric layer, as known in the art.  
         [0056]     A second dielectric layer  48  is deposited over the capping layer  46 . The second dielectric layer  48  may comprise a dielectric material having a low dielectric constant (k), wherein “low k” is defined as a dielectric constant (k) below 3.0, or in the range of approximately 1.5-2.7, such as porous poly(areylene) ether (e.g., porous SiLK™ (Dow Chemical)), porous SiCOH, porous SiO 2 , teflon, amorphous carbon, etc. The second dielectric layer  48  may be deposited using CVD, PECVD, spin-on deposition, etc., to a thickness of approximately 100-3000 nm, e.g., 400 nm.  
         [0057]     A hard mask  50  is then deposited over the second dielectric layer  48 . The hard mask  50  may comprise a dielectric material, such as SiC, SiCN, SiCOH, SiO 2 , Si 3 N 4 , etc. The hard mask  50  may be deposited using CVD, PECVD, etc., to a thickness of approximately 1-100 nm, e.g., 10 nm.  
         [0058]     A photoresist  52  is then applied over the hard mask  50 , as illustrated in  FIG. 7 . The photoresist  52  may be applied to a thickness in the range of approximately 50-3000 nm, e.g., 200 nm. The photoresist  52  may comprise a positive or negative photoresist  52  as desired. The photoresist  52  is then patterned and etched using standard BEOL exposure and RIE formation techniques to form trenches  54   a ,  54   b  ( FIG. 8 ). Narrower trenches  54   a  may be formed having an aspect ratio of approximately 2:1, and a minimum trench width  56   a  in the range of approximately 100-150 nm. Wider trenches  54   b  may be formed having any width, and a wide range of aspect ratios, e.g., an aspect ratio of approximately 1:2, 1:10, etc. As described supra, the photoresist  52  may be completely consumed during the standard BEOL formation processing when used in conjunction with a p-SiLK second dielectric layer  48 . Alternatively, a multi-layer hard mask may be used (not shown), as described supra.  
         [0059]     As illustrated in  FIG. 9 , a conformal dielectric liner  58  is deposited over the surface of the device  10 . The liner  58  may comprise a dielectric material having a low dielectric constant (k), wherein “low k” is defined as a dielectric constant (k) preferably below 3.0, or in the range of approximately 1.4-4.5, such as SiCOH, SiO 2 , poly(areylene) ether (e.g., SiLK™ (Dow Chemical)), teflon, or other similarly used material. The liner  58  may be deposited using PECVD, CVD, or other similar deposition techniques. The liner  58  may have a thickness up to approximately ½ the width of the minimum trench width  22   a , and preferably ⅓ the width of the minimum trench width  22   a  (100-150 nm), i.e., a thickness in the range of approximately 30-50 nm.  
         [0060]     A photoresist layer  60  is then applied over the liner  58 , as illustrated in  FIG. 10 . The photoresist  60  may be applied having a thickness in the range of approximately 50-3000 nm, e.g., 200 nm. The photoresist layer  60  over an optional anti-reflective layer (not shown) is then patterned using conventional positive or negative photolithography techniques, as illustrated in  FIG. 11 . A plurality of vias  62  may then be etched.  
         [0061]     The vias  62  may be formed having different widths as desired. For example, as illustrated in  FIGS. 12-14 , narrower vias  62   a  may be formed having a width  64   a  approximately ⅓ the minimum trench width  56   a , e.g., in the range of approximately 30-50 nm. The narrower vias  62   a  may be useful when forming devices having tighter device densities. Alternatively, wider vias  62   b  may be formed having a width  64   b  approximately the same size as the minimum trench width  56   a ), e.g., in the range of approximately 100-150 nm, as illustrated in  FIGS. 15-17 .  
         [0062]     To form either vias  62   a ,  62   b , the photoresist layer  60  is patterned, as known in the art ( FIG. 11 ). Multiple etch chemistries are employed to then etch down through the conformal liner  58 , the hard mask  50 , the second dielectric layer  48 , and the capping layer  46  to get down to the first wiring level  44  ( FIGS. 12 and 15 ), using a RIE process as know in the art. The etching process may be performed until substantially all of the photoresist  60  is consumed.  
         [0063]     As illustrated in  FIG. 12 , when forming the narrower vias  62   a , the etch removes only a portion  72  of the liner  58  on the sidewalls  68   a  of the trenches  54   a  having the minimum trench width  56   a . In contrast, when forming the wider vias  62   b , the etch removes the conformal liner  58  on the sidewalls  68   b  of the trenches  54   a  having the minimum trench width  56   a  ( FIG. 15 ).  
         [0064]     Following via  62   a ,  62   b  formation, a cleaning process is performed and the metallization is deposited. As illustrated in  FIGS. 13 and 16 , a conductive liner  74 , a seed layer  76  and a conductive layer  78  may be deposited as described supra in connection with the first wiring level  44 . Again, the conductive liner  74  and the seed layer  76  are not drawn to scale for purposes of illustration.  
         [0065]     Following deposition of the metallization, (the conductive liner  74 , the seed layer  76  and the conductive layer  78 ), a planarization process is performed to remove the excess metallization on the surface of the second wiring level  45   a . A CMP or other similarly used process may be used to planarize the surface of the second wiring level  45   a . The planarization process is performed down to the conformal liner  58 , as illustrated in  FIGS. 14 and 17 . Alternatively, the planarization process may be performed down to the hard mask  50  (not shown). Electrically conductive wires  80   a ,  80   b  are produced following planarization.  
         [0066]     The method for forming the second wiring level  45   a , described supra, was for a trench first, via second dual damascene feature formation. Alternatively, a second wiring level  45   b  may be formed using a via first, trench second dual damascene feature formation.  
         [0067]     For example, following the formation of the device  10  illustrated in  FIG. 7 , as described supra, including the capping layer  46 , the second dielectric layer  48 , the second hard mask  50  and the photoresist layer  52 , the photoresist layer  52  is patterned ( FIG. 18 ). The second dielectric layer  48  and the hard mask  50  are then etched using standard BEOL exposure and RIE formation techniques to form vias  100 , as illustrated in  FIG. 19 . The vias  100  may be formed having an aspect ratio of approximately 2:1, and a width  102  in the range of approximately 100-150 nm. As described supra, the photoresist  52  may be completely consumed during the standard BEOL formation processing when used in conjunction with a p-SiLK second dielectric layer  48 . Alternatively, a multi-layer hard mask may be used (not shown), as described supra.  
         [0068]     As illustrated in  FIG. 20 , a conformal dielectric liner  104  is deposited over the surface of the device  10 . The liner  104  may comprise a dielectric material having a low dielectric constant (k), wherein “low k” is defined as a dielectric constant (k) preferably below 3.0, or in the range of approximately 1.4-4.5, such as SiCOH, SiO 2 , poly(areylene) ether (e.g., SiLK™ (Dow Chemical)), teflon, or other similarly used material. The liner  104  may be deposited using PECVD, CVD, or other similar deposition techniques. The liner  104  may have a thickness in the range of approximately 10-50 nm.  
         [0069]     A gap filling organic anti-reflective coating (ARC)  106  is deposited over the surface of the device  10  filling the vias  100 , as illustrated in  FIG. 21 . The ARC  106  may be deposited having a thickness in the range of approximately 100-300 nm, e.g., 200 nm, and may comprise organic or inorganic materials, such as polymers, spin-on glass, etc. The ARC  106  may be deposited using spin-on, CVD, or other similarly used methods. The ARC  106  provides a planar surface for further processing.  
         [0070]     A third hard mask  108  is deposited over the ARC  106  using, a low temperature oxide deposited by PECVD at approximately 200° C. (so as not to damage the ARC  106 ), a spin-on oxide deposition with a low temperature cure (“low temperature” meaning a temperature below approximately 300° C.), etc. The third hard mask  108  may comprise a dielectric material, such as SiC, SiCN, SiCOH, SiO 2 , Si 3 N 4 , etc., and may be deposited to a thickness of approximately 1-100 nm, e.g., 10 nm.  
         [0071]     A photoresist layer  110  is then applied over the third hard mask  108 , as illustrated in  FIG. 21 . The photoresist  110  may be applied having a thickness in the range of approximately 5-3000 nm, e.g., 200 nm. An optional second ARC layer (not shown) may also be deposited over the photoresist layer  110  if desired. The photoresist layer  110  is then patterned using conventional positive or negative photolithography techniques, as illustrated in  FIG. 22 .  
         [0072]     Various etch chemistries are used to remove portions of the third hard mask  108  and the ARC  106 , as illustrated in  FIG. 23 . A portion of the ARC  106  remains within the vias  100  to prevent damage to the conductive material within the wires  32  of the first wiring level  44  during the subsequent etching process. A different etch chemistry is used to remove the liner  104  and the remaining hard mask  108 , as illustrated in  FIG. 24 . Another etch chemistry is used to remove a portion of the second dielectric layer  48 , thereby forming trenches  112  within the second wiring level  45   b , as illustrated in  FIG. 25 . As described supra, trenches  112   a ,  112   b  having different widths  114   a ,  114   b  may be formed.  
         [0073]     As illustrated in  FIG. 26 , the remaining ARC  106  within the base of the vias  100  is removed using an ARC removal etch process. A conformal dielectric liner  116  is then deposited over the surface of the device  10 . The liner  116  may comprise dielectric material having a low dielectric constant (k), wherein “low k” is defined as a dielectric constant (k) preferably below 3.0, or in the range of approximately 1.4-4.5, such as SiCOH, SiO 2 , poly(areylene) ether (e.g., SiLK™ (Dow Chemical)), teflon, or other similarly used material. The liner  116  may be deposited using PECVD, CVD, or other similar deposition techniques. The liner  116  may have a thickness up to approximately ½ the width of the minimum trench width  114   a , and preferably ⅓ the width of the minimum trench width  114   a  (100-150 nm), i.e., a thickness in the range of approximately 30-50 nm.  
         [0074]     Multiple etch chemistries are employed to then etch down through the conformal liners  116 ,  50  and the capping layer  46  within the base of the vias  100  to get down to the first wiring level  44 , as illustrated in  FIG. 27 .  
         [0075]     A cleaning process is then performed and the metallization is deposited, as described supra. As illustrated in  FIG. 28 , a conductive liner  120 , a seed layer  122  and a conductive layer  124  may be deposited as described supra in connection with the first wiring level  44 . Again, the conductive liner  120  and the seed layer  122  are not drawn to scale for purposes of illustration.  
         [0076]     Following deposition of the metallization, (the conductive liner  120 , the seed layer  122  and the conductive layer  124 ), a planarization process is performed to remove the excess metallization on the surface of the second wiring level  45   b , as illustrated in  FIG. 29 . A CMP or other similarly used process may be used to planarize the surface of the second wiring level  45   b . Electrically conductive dual damascene wires  126   a ,  126   b  are produced following planarization.

Technology Classification (CPC): 7