Patent Abstract:
Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.

Full Description:
BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates to FPGAs (Field-Programmable Gate Arrays), and more particularly, to testing of FPGAs embedded in an ASIC (Application-Specific Integrated Circuit). 
   2. Related Art 
   An FPGA (Field-Programmable Gate Array) and an ASIC (Application-Specific Integrated Circuit) can be combined to form a hybrid IC (integrated circuit) so that the hybrid IC can have the advantages of both the FPGA (design flexibility) and the ASIC (low power, high performance, and low test pin count). 
   Testing a standalone FPGA typically consists of exhaustively testing the logic blocks and interconnect resources of the FPGA through a series of structural tests. These structural tests configure the standalone FPGA in different ways and require access to all input/output (I/O) pins of the standalone FPGA. Similarly, testing the FPGA in the hybrid IC consists of essentially the same structural tests. The problem is how to access all I/O pins of the FPGA in the hybrid IC given the low test pin count of the hybrid IC. 
   Therefore, there is a need for a novel structure and testing method for a low test pin count, hybrid IC comprising an ASIC and multiple FPGAs. 
   SUMMARY OF THE INVENTION 
   The present invention provides a digital system, comprising (a) N macro circuits, N being a positive integer; (b) an application-specific integrated circuit (ASIC); and (c) a shift/interface system being coupled to the N macro circuits and the ASIC, wherein, in response to the N macro circuits and the ASIC being in normal operation, the shift/interface system electrically couples each macro circuit of the N macro circuits to the ASIC, wherein, in response to the N macro circuits being tested, the shift/interface system is further configured to scan-in macro circuit test data in series, then to feed the macro circuit test data to the N macro circuits, then to receive macro circuit response data from the N macro circuits, and then to scan-out the macro circuit response data in series, and wherein, in response to the ASIC being tested, the shift/interface system is further configured to scan-in ASIC test data in series, then to feed the ASIC test data to the ASIC, then to receive ASIC response data from the ASIC, and then to scan-out the ASIC response data in series. 
   The present invention also provides a system testing and operating method, comprising the steps of (a) providing a digital system including (i) N macro circuits, (ii) an application-specific integrated circuit (ASIC), and (iii) a shift/interface system being coupled to the N macro circuits and the ASIC; (b) in response to the N macro circuits and the ASIC being in normal operation, using the shift/interface system to electrically couple each macro circuit of the N macro circuits to the ASIC; (c) in response to the N macro circuits being tested, (i) scanning-in macro circuit test data in series into the shift/interface system, (ii) feeding the macro circuit test data from the shift/interface system to the N macro circuits, (iii) using the shift/interface system to receive macro circuit response data from the N macro circuits, and (iv) scanning-out the macro circuit response data in series from the shift/interface system; and (d) in response to the ASIC being tested, (i) scanning-in ASIC test data in series into the shift/interface system, (ii) feeding the ASIC test data from the shift/interface system to the ASIC, (iii) using the shift/interface system to receive ASIC response data from the ASIC, and (iv) scanning-out the ASIC response data in series from the shift/interface system. 
   The present invention also provides a system testing method, comprising the steps of (a) providing a digital system including (i) a macro circuit, (ii) an application-specific integrated circuit (ASIC), and (iii) a shift/interface system being coupled to the macro circuit and the ASIC, and (iv) a multiple-input signature register (MISR) including K MISR stages, K being a positive integer, the K MISR stages being coupled together, being coupled to K output pins of the macro circuit, and being coupled to K shift/interface circuits of the shift/interface system, wherein the K shift/interface circuits are coupled together; (b) scanning-in macro circuit test data in series into the shift/interface system; (c) transmitting the macro circuit test data from the shift/interface system to the macro circuit in parallel; (d) using the macro circuit to process the macro circuit test data into macro circuit response data and to present the macro circuit response data at the K output pins of the macro circuit; (e) transmitting the macro circuit response data from the K output pins of the macro circuit to the K MISR stages; (f) using the MISR to process the macro circuit response data into a macro circuit response signature and send the macro circuit response signature to the K shift/interface circuits; and (g) scanning the macro circuit response signature out of the K shift/interface circuits in series. 
   The present invention provides a novel structure and testing method for a low test pin count, hybrid IC comprising an ASIC and multiple FPGAs. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  illustrates a testing system comprising an IC (integrated circuit) and a tester, the IC comprising a shift/interface system, in accordance with embodiments of the present invention. 
       FIG. 1B  illustrates a method for operating the testing system of  FIG. 1A . 
       FIGS. 2A-2E  illustrate embodiments of shift/interface circuits of the shift/interface system of  FIG. 1A , in accordance with embodiments of the present invention. 
       FIG. 3  illustrates one embodiment of a shift/store unit that can be used in the shift/interface circuits of  FIGS. 2A-2E , in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1A  illustrates a testing system  100  comprising an IC (integrated circuit)  110  and a tester  120 , in accordance with embodiments of the present invention. In one embodiment, illustratively, the IC  110  can comprise FPGAs (Field-Programmable Gate Arrays)  130   a  and  130   b , MISRs (Multiple-Input Signature Registers)  140   a  and  140   b , a shift/interface system  150 , and an ASIC (Application-Specific Integrated Circuit)  160 . In general, the IC  110  can comprise M FPGAs similar to the FPGAs  130   a  and  130   b , and M MISRs similar to the MISRs  140   a  and  140   b  (M is positive integer). 
   The FPGA  130   a  is coupled to the shift/interface system  150  via connections  133   a  and to the MISR  140   a  via connections  135   a . The MISR  140   a  is coupled to the shift/interface system  150  via connections  145   a . Similarly, the FPGA  130   b  is coupled to the shift/interface system  150  via connections  133   b  and to the MISR  140   b  via connections  135   b . The MISR  140   b  is coupled to the shift/interface system  150  via connections  145   b . The shift/interface system  150  is coupled to the ASIC  160  via connections  155  and to the tester  120  via connections  157 . The ASIC  160  is coupled to the tester  120  via connections  165 . 
   In one embodiment, during the normal operation of the IC  110  (i.e., the ASIC  160  and the FPGAs  130   a  and  130   b  are in normal operation), the shift/interface system  150  can be configured to (a) electrically couple the FPGAs  130   a  to the ASIC  160  via the connections  133   a  and  155  and (b) electrically couple the FPGAs  130   b  to the ASIC  160  via the connections  133   b  and  155 . In other words, during the normal operation of the IC  110 , the shift/interface system  150  is transparent to the FPGAs  130   a  and  130   b  and the ASIC  160 . 
   In one embodiment, a structural test  180  ( FIG. 1B ) of the FPGAs  130   a  and  130   b  can be carried out as follows. With reference to  FIGS. 1A and 1B , illustratively, in step  182 , the tester  120  can place the FPGAs  130   a  and  130   b  in a safe (i.e., shut-off) state by sending a stability signal to both the FPGAs  130   a  and  130   b . As a result, random signals on the inputs (not shown) of the FPGAs  130   a  and  130   b  would not place the FPGAs  130   a  and  130   b  into an unknown or unstable state. In one embodiment, the tester  120  can send the stability signal to both the FPGAs  130   a  and  130   b  through the connections  157 , the shift/interface system  150 , and then the connections  133   a  and  133   b , respectively. 
   Next, in step  184 , with the FPGAs  130   a  and  130   b  being placed in the safe state, in one embodiment, the tester  120  can make a first data shift of a first bitstream comprising first FPGA test data and second FPGA test data into the shift/interface system  150  via connection  157 . The first data shift is carried out such that, at the end of the first data shift, the first FPGA test data is applied to the input pins of the FPGA  130   a  via the connections  133   a , and the second FPGA test data is applied to the input pins of the FPGA  130   b  via the connections  133   b.    
   Next, in step  186 , in one embodiment, the tester  120  can send an operation signal to the FPGAs  130   a  and  130   b  so as to place the FPGAs  130   a  and  130   b  in an operation state. In one embodiment, the tester  120  can send the operation signal to the FPGAs  130   a  and  130   b  by deactivating the stability signal. 
   Next, in step  188 , in one embodiment, the tester  120  can send configuration signals to the FPGAs  130   a  and  130   b  so as to configure the FPGAs  130   a  and  130   b  to operate on the first and second FPGA test data, respectively. In one embodiment, the tester  120  can send the configuration signals to the FPGAs  130   a  and  130   b  through the connections  157 , the shift/interface system  150 , and then the connections  133   a  and  133   b , respectively. 
   Next, in step  190 , in one embodiment, the FPGA  130   a  can send a first reset signal to the MISR  140   a  via the connections  135   a  so as to reset the MISR  140   a . In one embodiment, the FPGA  130   b  can send a second reset signal to the MISR  140   b  via the connections  135   b  so as to reset the MISR  140   b.    
   Next, in step  192 , in one embodiment, the FPGAs  130   a  and  130   b  and the MISRs  140   a  and  140   b  are clocked N times (N can be selected based on the design of the FPGAs  130   a  and  130   b ). In one embodiment, the FPGAs  130   a  and  130   b  and the MISRs  140   a  and  140   b  can be clocked by the same clock signal. 
   In one embodiment, for each of the N clocks, the FPGA  130   a  generates a different FPGA response to both the MISR  140   a  (via connections  135   a ) and the shift/interface system  150  (via connections  133   a ). At the shift/interface system  150 , the current FPGA response overrides and replaces the previous FPGA response. But, at the MISR  140   a , the current FPGA response is combined with all previous FPGA responses from the FPGA  130   a  such that after the N clocks, the MISR  140   a  combines all the N FPGA responses from the FPGA  130   a  into a first response signature. In one embodiment, after the N clocks, the FPGA  130   a  can also send its configuration status from its configuration status outputs to the shift/interface system  150  via connections  133   a.    
   Similarly, for each of the N clocks, the FPGA  130   b  generates a different FPGA response to both the MISR  140   b  (via connections  135   b ) and the shift/interface system  150  (via connections  133   b ). At the shift/interface system  150 , the current FPGA response overrides and replaces the previous FPGA response. But, at the MISR  140   b , the current FPGA response is combined with all previous responses such that after the N clocks, the MISR  140   b  combines all the N responses from the FPGA  130   b  into a second response signature. In one embodiment, after the N clocks, the FPGA  130   b  can also send its configuration status from its configuration status outputs to the shift/interface system  150  via connections  133   b.    
   Next, in step  194 , in one embodiment, the tester  120  can send the stability signal to both the FPGAs  130   a  and  130   b  to place the FPGAs  130   a  and  130   b  in the safe state. 
   Next, in step  196 , in one embodiment, the shift/interface system  150  can make a second data shift of a second bitstream comprising the first and second response signatures and the configuration status of the FPGA  130   a  and  130   b  out of the shift/interface system  150  to the tester  120  via connections  157 . 
   Next, in one embodiment, one or more structural test of the FPGAs  130   a  and  130   b  similar to the structural test  180  described supra can be performed. 
     FIGS. 2A-2E , respectively, illustrate five shift/interface circuits  151   a ,  151   b ,  151   c ,  151   d , and  151   e  representative of five different types of shift/interface circuits of the shift/interface system  150  of  FIG. 1A  (hereafter also referred to as types  151   a ,  151   b ,  151   c ,  151   d , and  151   e ), in accordance with embodiments of the present invention. Hereafter, a shift/interface circuit of any of the five types above can be referred to as the shift/interface circuit  151 . 
   In one embodiment, the shift/interface system  150  of  FIG. 1A  can comprise one chain of multiple shift/interface circuits  151  each of which can be of any one of the five types  151   a ,  151   b ,  151   c ,  151   d , and  151   e  ( FIGS. 2A ,  2 B,  2 C,  2 D, and  2 E, respectively). For example, one shift/interface circuit  151  in the chain can be of type  151   a  ( FIG. 2A ), while the next shift/interface circuit  151  in the chain can be of type  151   c  ( FIG. 2C ). 
   In one embodiment, the chain can have none, one, or more shift/interface circuits  151  of each type of the five types  151   a ,  151   b ,  151   c ,  151   d , and  151   e  ( FIGS. 2A ,  2 B,  2 C,  2 D, and  2 E, respectively). 
   In one embodiment, the shift/interface circuits  151  of a same type are arranged electrically next to each other in the chain. For example, all shift/interface circuits  151  of type  151   a  ( FIG. 2A ) of the chain can be placed electrically next to each other in the chain (two shift/interface circuits  151  are electrically next to each other in the chain if an output of one of the two shift/interface circuits  151  is electrically and directly coupled to an input of the other). 
   In one embodiment, each shift/interface circuits  151  in the chain, regardless of type, comprises a shift/store unit  210  and a multiplexer (i.e., MUX)  220  ( FIGS. 2A-2E ). In one embodiment, the shift/store unit  210  can function as a one-bit shift register. That is, in a store mode, the shift/store unit  210  can store a bit applied to its DI input and place the bit on its SO output. In a shift mode, for each shift, the shift/store unit  210  can shift its stored bit at its SO output to the next shift/store unit and receive a bit through its SI input from the immediately preceding shift/store unit. 
   In one embodiment, the SI input of the shift/store unit  210  of each shift/interface circuit  151  in the chain is electrically and directly coupled to the SO output of the shift/store unit  210  of the previous shift/interface circuit  151  in the chain. Exception is for the first shift/interface circuit  151  in the chain whose SI input (i.e., the SI input of its shift/store unit  210 ) is electrically coupled to the tester  120  via connections  157 . Exception is also for the last shift/interface circuit  151  in the chain whose SO output (i.e., the SO output of its shift/store unit  210 ) is also electrically coupled to the tester  120  via connections  157 . 
   The following discussion will show how each type of the five types  151   a ,  151   b ,  151   c ,  151   d , and  151   e  ( FIGS. 2A ,  2 B,  2 C,  2 D, and  2 E, respectively) helps in the structural test  180  ( FIG. 1B ). 
     FIG. 2A  illustrates the shift/interface circuit  151   a  (i.e., a shift/interface circuit  151  of type  151   a ) that can be used in the shift/interface system  150  of  FIG. 1A , in accordance with embodiments of the present invention. With reference to  FIGS. 1A and 2A , for type  151   a , in one embodiment, the MUX  220  can have its first and second inputs electrically coupled to an output of the ASIC  160  (via connection  155   a , a part of connections  155  of  FIG. 1A ) and the SO output of the shift/store unit  210 , respectively. The MUX  220  can have its output electrically coupled to an input of the FPGA  130   a  (via connection  136   a , a part of connections  133   a  of  FIG. 1A ) and to the DI input of the shift/store unit  210 . The MUX  220  can have its control input receiving a Test-FPGA signal from the tester  120  via connection  157   a , a part of connections  157  of  FIG. 1A . In short, the output of the ASIC  160  is coupled to the input of the FPGA  130   a  via the shift/interface circuit  151  of type  151   a.    
   In one embodiment, assume that the FPGA  130   a  has P functional data inputs that need to be directly coupled one-to-one to P functional data outputs of the ASIC  160  during the normal operation of the IC  110  of  FIG. 1A  (P is a positive integer). As a result, P shift/interface circuits  151  of type  151   a  can be used in the chain to couple the P functional data outputs of the ASIC  160  to the P functional data inputs of the FPGA  130   a.    
   During the normal operation of the IC  110 , with reference to  FIGS. 1A and 2A , the tester  120  can pull the Test-FPGA signal low (i.e.,  0 ) to cause the P MUXes  220  of the P shift/interface circuits  151  of type  151   a  to electrically couple the P functional data outputs of the ASIC  160  to the P functional data inputs of the FPGA  130   a . In other words, during the normal operation of the IC  110 , the shift/interface system  150  is transparent to the FPGA  130   a  and the ASIC  160  as far as the functional data is concerned. 
   During the structural test  180  ( FIG. 1B ) of the FPGA  130   a , in step  184 , in one embodiment, after the first data shift, the P shift/store units  210  of the P shift/interface circuits  151  of type  151   a  of the chain should contain the first FPGA test data. Then, with the Test-FPGA signal pulled high by the tester  120 , the P MUXes  220  of the P shift/interface circuits  151  of type  151   a  apply the first FPGA test data (at the P SO outputs of the P shift/store units  210 ) to the P functional data inputs of the FPGA  130   a.    
   During the testing of the ASIC  160 , the tester  120  can pull the Test-FPGA signal low (i.e., 0) to electrically couple the P outputs of the ASIC  160  to the P DI inputs of the P shift/interface circuits  151  of type  151   a . As a result, signals on the P outputs of the ASIC  160  can be stored in the P shift/interface circuits  151  of type  151   a  and can be later shifted out to the tester  120  for analysis. 
   In one embodiment, multiple shift/interface circuits  151  of type  151   a  can also be used to couple functional data outputs of the ASIC  160  to functional data inputs of the FPGA  130   b  in a manner similar to that for the FPGA  130   a . In one embodiment, the testing of the FPGAs  130   a  and  130   b  can be carried out simultaneously in a similar manner. 
     FIG. 2B  illustrates the shift/interface circuit  151   b  (i.e., a shift/interface circuit  151  of type  151   b ) that can be used in the shift/interface system  150  of  FIG. 1A , in accordance with embodiments of the present invention. With reference to  FIGS. 1A and 2B , for type  151   b , in one embodiment, the MUX  220  can have its first and second inputs electrically coupled to an output of the ASIC  160  (via connection  155   b , a part of connections  155  of  FIG. 1A ) and an output of the tester  120 , respectively. The MUX  220  can have its output electrically coupled to the input DI of the shift/store unit  210  and an input of the FPGA  130   a  via connection  136   b , a part of connections  133   a  of  FIG. 1A . The MUX  220  can have its control input receiving the Test-FPGA signal from the tester  120 . In short, the output of the ASIC  160  is coupled to the input of the FPGA  130   a  via the shift/interface circuit  151  of type  151   b.    
   In one embodiment, assume that the FPGA  130   a  has Q configuration inputs that need to be directly coupled one-to-one to Q configuration outputs of the ASIC  160  during the normal operation of the IC  110  of  FIG. 1A  (Q is a positive integer). As a result, Q shift/interface circuits  151  of type  151   b  can be used in the chain to couple the Q configuration outputs of the ASIC  160  to the Q configuration inputs of the FPGA  130   a.    
   During the normal operation of the IC  110 , with reference to  FIGS. 1A and 2B , the tester  120  can pull the Test-FPGA signal low (i.e.,  0 ) to cause the Q MUXes  220  of the Q shift/interface circuits  151  of type  151   b  to electrically couple the Q configuration outputs of the ASIC  160  to the Q configuration inputs of the FPGA  130   a . In other words, during the normal operation of the IC  110 , the shift/interface system  150  is transparent to the FPGA  130   a  and the ASIC  160  as far as the configuration data is concerned. 
   During the structural test  180  ( FIG. 1B ) of the FPGA  130   a , in step  188 , in one embodiment, with the Test-FPGA signal being high, the Q MUXes  220  of the Q shift/interface circuits  151  of type  151   b  can apply the Q configuration signal bits from the tester  120  to the Q configuration inputs of the FPGA  130   a . During the structural test  180  ( FIG. 1B ), the tester  120  can change the configuration signal bits sent to the FPGA  130   a.    
   During the testing of the ASIC  160 , the tester  120  can pull the Test-FPGA signal low (i.e.,  0 ) to electrically couple the Q outputs of the ASIC  160  to the Q DI inputs of the Q shift/interface circuits  151  of type  151   b . As a result, signals on the Q outputs of the ASIC  160  can be stored in the Q shift/interface circuits  151  of type  151   b  and can be later shifted out to the tester  120  for analysis. 
   In one embodiment, multiple shift/interface circuits  151  of type  151   b  can also be used to couple configuration outputs of the ASIC  160  to configuration inputs of the FPGA  130   b  in a manner similar to that for the FPGA  130   a . In one embodiment, the testing of the FPGAs  130   a  and  130   b  can be carried out simultaneously in a similar manner. 
     FIG. 2C  illustrates the shift/interface circuit  151   c  (i.e., a shift/interface circuit  151  of type  151   c ) that can be used in the shift/interface system  150  of  FIG. 1A , in accordance with embodiments of the present invention. With reference to  FIGS. 1A and 2C , for type  151   c , in one embodiment, the MUX  220  can have its first and second inputs electrically coupled to an output of the FPGA  130   a  (via connection  136   c , a part of connections  133   a  of  FIG. 1A ) and the SO output of the shift/store unit  210 , respectively. The MUX  220  can have its output electrically coupled to an input of the ASIC  160  (via connection  155   c , a part of connections  155  of  FIG. 1A ) and to the DI input of the shift/store unit  210 . In one embodiment, the MUX  220  can have its output further electrically coupled directly to the tester  120  via a connection (not shown). As a result, the tester  120  can continuously monitor the output of the FPGA  130   a  as long as the MUX  220  selects the output of the FPGA  130   a . The MUX  220  can have its control input receiving a Test-ASIC signal from the tester  120  via connection  157   c , a part of connections  157  of  FIG. 1A . In short, the output of the FPGA  130   a  is coupled to the input of the ASIC  160  via the shift/interface circuit  151  of type  151   c.    
   In one embodiment, assume that the FPGA  130   a  has R configuration status outputs that need to be directly coupled one-to-one to R configuration status inputs of the ASIC  160  during the normal operation of the IC  110  of  FIG. 1A  (R is a positive integer). Assume further that the FPGA  130   a  has S functional data outputs that need to be electrically coupled one-to-one to S functional data inputs of the ASIC  160  during the normal operation of the IC  110  of  FIG. 1A  (S is a positive integer). As a result, R shift/interface circuits  151  of type  151   c  can be used in the chain to couple the R configuration status outputs of the FPGA  130   a  to the R configuration status inputs of the ASIC  160 . Also, S shift/interface circuits  151  of type  151   c  can be used in the chain to couple the S functional data outputs of the FPGA  130   a  to the S functional data inputs of the ASIC  160 . 
   During the normal operation of the IC  110 , with reference to  FIGS. 1A and 2C , the tester  120  can pull the Test-ASIC signal low (i.e.,  0 ) to cause the R+S MUXes  220  of the R+S shift/interface circuits  151  of type  151   c  to electrically couple the R configuration status outputs and S functional data outputs of the FPGA  130   a  to the R configuration status inputs and S functional data inputs of the ASIC  160 , respectively. In other words, during the normal operation of the IC  110 , the shift/interface system  150  is transparent to the FPGA  130   a  and the ASIC  160  as far as the FPGA configuration status data and the FPGA functional output data are concerned. 
   During the structural test  180  ( FIG. 1B ) of the FPGA  130   a , in step  192 , in one embodiment, the tester  120  can pull the Test-ASIC signal low (i.e.,  0 ) to cause the R+S MUXes  220  of the R+S shift/interface circuits  151  of type  151   c  to electrically couple the R configuration status outputs and S functional data outputs of the FPGA  130   a  to the R+S DI inputs of the R+S shift/store units  210  of the R+S shift/interface circuits  151  of type  151   c . As a result, configuration status data from the FPGA  130   a  can be transmitted to and stored in the R shift/interface circuits  151  of type  151   c  of the chain and can be later shifted out to the tester  120  for analysis (as part of the second bitstream). Similarly, the FPGA responses at the S functional data outputs of the FPGA  130   a  can be transmitted to the S shift/interface circuits  151  of type  151   c  of the chain, and the last FPGA response of the FPGA  130   a  can be later shifted out to the tester  120  for analysis (as part of the second bitstream). 
   During the testing of the ASIC  160 , the tester  120  can pull the Test-ASIC signal high (i.e.,  1 ) to electrically couple the R+S inputs of the ASIC  160  to the R+S SO outputs of the R+S shift/interface circuits  151  of type  151   c . As a result, ASIC test data can be shifted into the shift/interface system  150  from the tester  120  (in one embodiment, as part of the first bitstream) and then applied to the R+S inputs of the ASIC  160  via the R+S MUXes  220  of the R+S shift/interface circuits  151  of type  151   c.    
   In one embodiment, multiple shift/interface circuits  151  of type  151   c  can also be used to couple configuration status outputs and functional data outputs of the FPGA  130   b  ( FIG. 1A ) to configuration status inputs and functional data inputs of the ASIC  160 , respectively, in a manner similar to that for the FPGA  130   a . In one embodiment, the testing of the FPGAs  130   a  and  130   b  can be carried out simultaneously in a similar manner. 
     FIG. 2D  illustrates the shift/interface circuit  151   d  (i.e., a shift/interface circuit  151  of type  151   d ) that can be used in the shift/interface system  150  of  FIG. 1A  and a MISR stage  142  that can be used in the MISR  140   a  of  FIG. 1A , in accordance with embodiments of the present invention. 
   In one embodiment, S MISR stages (not shown) like the MISR stage  142  (or in short, the S MISR stages  142 ) can be coupled together in daisy chain to form the MISR  140   a  of  FIG. 1A . In one embodiment, the S MISR stages  142  can be coupled one-to-one to the S functional data outputs (described above) of the FPGA  130   a  and also coupled one-to-one to S shift/interface circuits  151  of type  151   d.    
   In one embodiment, the shift/interface circuit  151   d  has a structure similar to the shift/interface circuit  151   c  ( FIG. 2C ), except that in the shift/interface circuit  151   d , the first input of the MUX  220  is coupled to an output of the associated MISR stage  142  (via connection  137 ) and the output of the MUX  220  is not coupled to the ASIC  160 . 
   During the structural test  180  ( FIG. 1B ) of the FPGA  130   a , in step  192 , in one embodiment, FPGA responses on the S functional data outputs of the FPGA  130   a  can be transmitted via connection  136   d  to the S associated MISR stages  142  to be processed into the first FPGA response signature. More specifically, when a current FPGA response at the S functional data outputs of the FPGA  130   a  is transmitted to the S associated MISR stages  142 , the S MISR stages  142  combine the current FPGA response with the previous FPGA response signature to form a current FPGA response signature. At the end, the first FPGA response signature is created at the S outputs of the S MISR stages  142 . With the Test-ASIC signal pulled low (i.e.,  0 ) by the tester  120 , the S MUXes  220  of the S shift/interface circuits  151  of type  151   d  apply the first FPGA response signature from the S MISR stages  142  to the S DI inputs of the S shift/interface circuits  151  of type  151   d . In step  196  ( FIG. 1  B), the first FPGA response signature is shifted out to the tester  120  for analysis (as part of the second bitstream). 
   In one embodiment, T more MISR stages  142  (T being a positive integer) can be added to the end of the chain of the S MISR stages  142  so as to reduce the chance of response signature alias. As a result, T more shift/interface circuits  151  of type  151   d  corresponding to the T additional MISR stages  142  can be added to the chain. The first FPGA response signature therefore has S+T bits instead of S bits. 
   In one embodiment, multiple shift/interface circuits  151  of type  151   d  and multiple MISR stages  142  can also be coupled to functional data outputs of the FPGA  130   b  in a manner similar to that for the FPGA  130   a . In one embodiment, the testing of the FPGAs  130   a  and  130   b  can be carried out simultaneously in a similar manner with respect to FPGA response signature formation. 
     FIG. 2E  illustrates the shift/interface circuit  151   e  (i.e., a shift/interface circuit  151  of type  151   e ) that can be used in the shift/interface system  150  of  FIG. 1  A, in accordance with embodiments of the present invention. With reference to  FIGS. 1A and 2E , for type  151   e , in one embodiment, the MUX  220  can have its first and second inputs electrically coupled to an output of the ASIC  160  and an output of the tester  120  (via connection  157   e   2 , apart of the connections  157  of  FIG. 1A ), respectively. The output of the ASIC  160  is also electrically coupled to the DI input of the shift/store unit  220 . The MUX  220  can have its output electrically coupled to an input of the FPGA  130   a  via connection  136   e . The MUX  220  can have its control input receiving a Test-Enable signal from the tester  120  via connection  157   e   1 , a part of connections  157  of  FIG. 1A . In one embodiment, the input of the FPGA  130   a  can be a stability input of the FPGA  130   a  for receiving the stability signal from the tester  120 . 
   During the normal operation of the IC  110 , with reference to  FIGS. 1A and 2E , the tester  120  can pull the Test-Enable signal low (i.e., 0) to cause the MUX  220  of the shift/interface circuit  151   e  to electrically couple the output of the ASIC  160  to the stability input of the FPGA  130   a.    
   During the structural test  180  ( FIG. 1B ) of the FPGA  130   a , in steps  182  and  194  in one embodiment, the tester  120  can pull the Test-Enable signal high and also assert the stability signal on the connection  157   e   2 . As a result, the asserted stability signal is transmitted to the stability input of the FPGA  130   a  via the MUX  220  of the shift/interface circuit  151   e . Therefore, the FPGA  130   a  is placed in the stable state. In one embodiment, in step  186  of the structural test  180  ( FIG. 1B ), the tester  120  can pull the Test-Enable signal high and also deactivate the stability signal on the connection  157   e   2 . As a result, the FPGA  130   a  is placed in the operation state. 
   During the testing of the ASIC  160 , the shift/store unit  220  can store the bit from the output of the ASIC  160 . Later, the stored bit can be shifted out to the tester  120  for analysis. 
   In one embodiment, another shift/interface circuit  151  of type  151   e  can also be used for a stability input of the FPGA  130   b  in a manner similar to that for the FPGA  130   a . In one embodiment, the testing of the FPGAs  130   a  and  130   b  can be carried out simultaneously in a similar manner. 
     FIG. 3  illustrates one embodiment of the shift/store unit  210  that can be used in the shift/interface circuits  151   a ,  151   b ,  151   c ,  151   d , and  151   e  of  FIGS. 2A-2E , respectively, in accordance with embodiments of the present invention. In one embodiment, the shift/store unit  210  can comprise latches  310  and  320 . The latch  310  can have four inputs I, A, C, and D and one output L 1 , whereas the latch  320  has two inputs B and E and one output L 2 . 
   The inputs SI and DI of the shift/store unit  210  can be electrically coupled to inputs I and D of the latch  310 , respectively. The output L 1  of the latch  310  is electrically coupled to input E of the latch  320 . The output L 2  of the latch  320  is electrically coupled to the output SO of the shift/store unit  210 . The inputs A, B, and C can be control inputs which can be electrically coupled to the tester  120  via connections  157  ( FIG. 1A ). 
   In one embodiment, for the latch  310 , if A=1 (i.e., logic high) and C=0 (i.e., logic low), then the output L 1  is electrically coupled to input I (i.e., L 1 =I). If A=0 and C=1, then L 1 =D. If A=C=0, then L 1  remains at its current state. The case A=C=1 is not allowed. In one embodiment, for the latch  320 , if B=1, then L 2 =E. If B=0, L 2  is electrically decoupled from E. 
   In the embodiments described above, all the shift/interface circuits  151  ( FIGS. 2A-2E ) of the shift/interface system  150  ( FIG. 1A ) are coupled together in a single chain. Alternatively, the shift/interface circuits  151  can be coupled together in multiple chains each of which can start from and end at the tester  120 . In one embodiment, latches in the ASIC  160  ( FIG. 1A ) can also be included in the chain(s) of the shift/interface circuits  151 . 
   In the embodiments described above, with reference to  FIG. 1A , the FPGAs  130   a  and  130   b  are shown separate from the ASIC  160 . Alternatively, the FPGAs  130   a  and  130   b  can be embedded in the ASIC  160 . 
   In the embodiments described above, with reference to  FIG. 1A , the FPGAs  130   a  and  130   b  are used for illustration. In general, the present invention is applicable to any macro circuits (not just FPGAs). A macro circuit is itself an integrated circuit (IC). A macro circuit can be integrated in another integrated circuit. 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Classification (CPC): 6