Patent Abstract:
A bias circuit for a magneto-resistive head having a bias current output circuit for flowing a bias current through a magneto-resistive head, and a feedback circuit for controlling the bias current from a bias current output circuit by detecting voltage variation across the magneto-resistive head so as a voltage across the magneto-resistive head to be a predetermined value, comprises a regulating circuit for regulating an operation of the bias current output circuit in the bias current output circuit, a control circuit for the regulating circuit for controlling the regulating circuit to be in a predetermined condition, and a switching circuit for switching a read/write condition for activating the control circuit for the regulating circuit in a non-read condition of the magneto-resistive head. The regulating circuit includes an oscillation suppressing capacitor; and the control circuit for the regulating circuit is a charging circuit for the oscillation suppressing capacitor.

Full Description:
CROSS REFERENCE TO RELATED APPLICATION  
         [0001]    This application claims priority from Japanese Priority Document No. 2002-169419, filed on Jun. 11, 2002 with the Japanese Patent Office, which document is hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention is related to a bias circuit for a read MR (Magneto-Resistive) head applied to a magnetic recording and/or reproducing apparatus such as a HDD (Hard Disk Drive) or the like.  
           [0004]    2. Description of the Related Art  
           [0005]    Conventionally, in a magnetic recording and/or reproducing apparatus such as a Hard Disk Drive for recording necessary data by magnetizing a magnetic layer formed on a rotating recording disk, a Magneto-Resistive head (MR head) is usually used to read out recorded data in case of reading the recorded data.  
           [0006]    Such a MR head is positioned opposite to the recording disk, and is possible to carry out the reading of the recorded data by outputting a change of magnets in the magnetic layer of the recording disk as a change of resistive value of the MR head.  
           [0007]    In this case, it is necessary to flow a bias current through the MR head using a bias circuit in advance, and the Voltage bias system which controls a voltage applied to the MR head is well-known as a bias system as one of such bias circuit.  
           [0008]    As shown in FIG. 3, a bias circuit a of the Voltage bias system is comprised of a bias current output circuit  100  for outputting the bias current flowing through the MR head Rmr, and a feedback circuit  200  for controlling the output bias current from the bias current output circuit  100 , so that a voltage across the MR head Rmr is controlled to be a predetermined value by detecting the voltage variation across the MR head Rmr through which the bias current is flowing.  
           [0009]    In the magnetic recording and/or reproducing apparatus having the MR head Rmr connected to the bias circuit a, not only the read MR head Rmr but a write inductive head  400  are provided in a head body  300  which is positioned opposite to a recording disk as shown FIG. 4, and it is so configured to operate either one of the MR head Rmr or the inductive head  400 .  
           [0010]    Here-in-after, a mode where a playback of the recorded data is carried out from the recording disk by operating the MR head Rmr is called as a read (reproducing) mode, and a mode where a writing of the data is carried out to the recording disk by operating the inductive head  400  is called as a write (recording) mode.  
           [0011]    The head body  300  is positioned opposite to the recording disk as mentioned above, and accordingly, the MR head Rmr and the bias circuit a are connected to each other by using a flexible printed circuit board  500 , the inductive head  400  is connected to the recording data amplifier circuit  600 , and the head body  300  is isolated from an amplifier circuit  700  which includes aforementioned bias circuit a and the recording data amplifier circuit  600 .  
           [0012]    The flexible printed circuit board  500  has a bare essential substrate area in order to make the magnetic recording and/or reproducing apparatus as small and light-weighted as possible. Further a read signal wiring  800  for connecting the MR head Rmr and the bias circuit a, and a write signal wiring  900  for connecting the inductive head  400  and the recording data amplifier circuit  600  are positioned extremely close to each other.  
           [0013]    For this purpose, when a writing signal flows through the write signal wiring  900  in the write mode, some cross-talk is, sometimes, generated in the read signal wiring  800  due to the writing signal, and there occurs a variation in the bias current flowing through the MR head Rmr due to the cross-talk. Accordingly, when the mode is changed from the write mode to the read mode, a recovery time is required for the bias current to be a predetermined bias current value for the read mode, so that, it takes a time to start the reading operation. Therefore in the write mode, it was usual to stop the flow of the bias current through the MR head Rmr by halting the operation of the bias circuit a.  
           [0014]    Namely, in a change-over switch SW provided in the bias circuit a in FIG. 3, the change-over switch SW was made ON in the read mode, and the change-over switch SW was made OFF in the write mode.  
           [0015]    In FIG. 4, a reference sign  710  designates a control signal line for transmitting control signals for transmitting the read mode for a read signal and for transmitting the write mode for a write signal to the bias circuit a, a read data amplifier  720  for amplifying the read data outputted from the bias circuit a, and further to the recording data amplifier circuit  600 . In this case, it is so configured that the control signal line  710  transmits the write signal when not in the read mode, and that the control signal line  710  transmits the read signal when not in the write mode.  
           [0016]    However, when the operation of the bias circuit a was halted, following problems occurred.  
           [0017]    Namely, when the operation of the bias circuit a is halted by setting the change-over switch SW to be OFF, there occur changes in an electrical state of the regulating circuit  110  provided in the bias current output circuit  100  that is prepared in order for the bias current output circuit  100  of the bias circuit a to operate in stable. Therefore, when the mode is changed from the write mode to the read mode, there requires a recovery time which is necessary for the regulating circuit  110  to comeback to a predetermined electrical state. Accordingly, it becomes difficult to carry out a stable conduction of the bias current during the recovery time, so that it is not able to start reading of the recorded data immediately after the mode is changed from the write mode to the read mode.  
           [0018]    Here, the regulating circuit  110  includes an oscillation suppressing capacitor C 1  provided in the bias current output circuit  100  for the purpose of suppressing the oscillation of the circuit and noise elimination, and the oscillation suppressing capacitor is configured by one oscillation suppressing capacitor C 1  in FIG. 3.  
           [0019]    If the operation of the bias circuit a is halted in the write mode, the power supply to the regulating circuit  110  is also halted, and thereby, there occurs voltage variation at the oscillation suppressing capacitor C 1  of the regulating circuit  110 , and the change-over switch SW is made ON, because the read signal is transmitted to the bias circuit a in this condition. Then, charging and discharging of the oscillation suppressing capacitor C 1  in the regulating circuit  110  occur at first, so that it becomes difficult to carry out a stable conduction of the bias current until the oscillation suppressing capacitor C 1  becomes to have a predetermined voltage.  
           [0020]    Particularly, it is able to increase a noise reducing effect to use a capacitor having as large capacity as possible as the oscillation suppressing capacitor C 1 , so that there is a problem that it takes a long time for the voltage of the oscillation suppressing capacitor C 1  to comeback to the predetermined voltage.  
         SUMMARY OF THE INVENTION  
         [0021]    In order to solve the above problems, a bias circuit for MR head of this invention includes a bias current output circuit for outputting a bias current flowing through the MR head, and a feedback circuit for controlling a bias current output from a bias current output circuit so that a voltage across the MR head is controlled to be a predetermined value by detecting the voltage across the MR head through which the bias current is flowing. Further, the bias circuit for MR head is so configured in which the bias current output circuit includes a regulating circuit for stably operating the bias current output circuit, and a control circuit for the regulating circuit for controlling the regulating circuit to be a predetermined state, and the control circuit for the regulating circuit is started to operate when not in the read mode of the MR head.  
           [0022]    Further the regulating circuit is a circuit equipped with an oscillation suppressing capacitor and the control circuit for the regulating circuit is characterized to be the charging circuit for the oscillation suppressing capacitor.  
           [0023]    Namely, when the MR head is in the read mode, the regulating circuit in the bias current output circuit is activated by activating the bias current output circuit, and on the contrary, when the MR head is made not in the read mode, namely made in the write mode, the regulating circuit is activated by activating the control circuit for regulating circuit so that the regulating circuit is always controlled and maintained to be a predetermined state.  
           [0024]    Accordingly, the bias current output circuit can start the playback of the data by the MR head immediately after the mode is changed from the write mode to the read mode, because a read current is anytime ready for flowing, and therefore, the twitching time from the write mode to the read mode is able to be shortened.  
           [0025]    Further, as a result, the recording disk of the magnetic recording and/or reproducing apparatus does not require a waiting interval corresponding to the recovery time of the regulating circuit, and it is able to carry out the recording of the data during the waiting interval so that it is also able to improve the recording density in the magnetic recording and/or reproducing apparatus.  
           [0026]    In addition, the regulating circuit is a circuit having an oscillation suppressing capacitor, and the control circuit for the regulating circuit is able to simplify the construction of the bias current output circuit without complexity, and also is able to operate it stably when it is to be the charging circuit for the oscillation suppressing capacitor. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]    In the accompanying drawings:  
         [0028]    [0028]FIG. 1 is a circuit diagram of a bias circuit for a MR head of the present invention in a read mode;  
         [0029]    [0029]FIG. 2 is a circuit diagram of a bias circuit for a MR head of the present invention in a write mode;  
         [0030]    [0030]FIG. 3 is a circuit diagram of a conventional bias circuit for a MR head; and  
         [0031]    [0031]FIG. 4 is a chart for explaining a configuration of a peripheral circuit in the conventional bias circuit for a MR head. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]    Here-in-after, one embodiment of the present invention is described with reference to the accompanying drawings. FIG. 1 is a circuit diagram of a bias circuit for a MR head A, and is a circuit diagram illustrating the bias circuit for the MR head A particularly in a read mode. FIG. 2 is the bias circuit for MR head A in a write mode.  
         [0033]    The bias circuit for MR head A is configured with a bias current output circuit  1  for outputting a bias current Ib flowing through the MR head Rmr, and a feedback circuit  2  which detects a voltage variation across the MR head Rmr by a voltage-current converting circuit gm, outputs a detecting result as a current, and controls the voltage across the MR head Rmr to be a predetermined value by controlling the bias current output circuit  1  based on the detected current.  
         [0034]    The bias current output circuit  1  is a current mirror circuit, and is configured to include a first PNP transistor P 1  and a third PNP transistor P 3 , where emitters of the first PNP transistor P 1  and the third PNP transistor P 3  are connected to an upper-side voltage source V CC  through resistors R 1 , R 3 , respectively, and bases thereof are connected to each other.  
         [0035]    In the bias current output circuit  1  of the present embodiment, a collector of the first PNP transistor P 1  is connected to the MR head Rmr, and flows the bias current Ib through the MR head Rmr. A collector of the third PNP transistor P 3  is connected to a base of the first NPN transistor Q 1 , an emitter of the first NPN transistor Q 1  is connected to a base of the second PNP transistor P 2 , and an emitter of the second PNP transistor P 2  is not only connected to a base of the third PNP transistor P 3  but also to the upper-side voltage source Vcc through a resistor R 2 .  
         [0036]    By the way, an emitter of the first NPN transistor Q 1  and a base of the second PNP transistor P 2  are connected to a second current source  12  by way of a second change-over switch SW 2 .  
         [0037]    An operation control of the bias current output circuit  1  is carried out by the forth NPN transistor Q 4  a collector of which is connected to the base of the first NPN transistor Q 1 . Further, a collector of the forth NPN transistor Q 4  is connected to a first oscillation suppressing capacitor C 1  one terminal of which is connected to the upper-side voltage source V CC , and is configured to prevent oscillation of the bias current output circuit  1  by the first oscillation suppressing capacitor C 1 , and to eliminate noise. In the present embodiment, the regulating circuit  3  is configured with a single first oscillation suppressing capacitor C 1 . An emitter of the forth NPN transistor Q 4  is connected to the lower-side voltage source V EE  by way of a resister R 8 .  
         [0038]    Further in the bias current output circuit  1 , there is provided a control circuit  4  for regulating circuit to be operated by switching of a second change-over switch SW 2  not in the read mode of the MR head Rmr, namely in the write mode.  
         [0039]    The control circuit  4  for the regulating circuit is served as a dummy current mirror circuit, and is configured to include a sixth PNP transistor P 6 , a fifth NPN transistor Q 5 , and a fifth PNP transistor P 5 . In this case, a collector of the sixth PNP transistor P 6  is connected to the collector of the forth NPN transistor Q 4 , a base of the fifth NPN transistor Q 5  is connected to a collector of the sixth PNP transistor P 6 , a collector of the fifth NPN transistor Q 5  is connected to the upper-side voltage source V CC , an emitter thereof is connected to a second current source I 2  by way of the second change-over switch SW 2 . In addition, a base of the fifth PNP transistor P 5  is connected to the emitter of the fifth NPN transistor Q 5 , and an emitter of the fifth PNP transistor P 5  is not only connected to the upper-side voltage source V CC  through a resistor R 9  but also to the base of the the sixth PNP transistor P 6 .  
         [0040]    An operation control of the forth NPN transistor Q 4  is carried out at the feedback circuit  2 , and the feedback circuit  2  is configured as follows.  
         [0041]    Namely, the feedback circuit  2  comprises a reference voltage source V 1  for applying a reference voltage to the MR head Rmr, a voltage-current converting circuit gm for detecting voltage variation across the MR head Rmr to which the reference voltage, a seventh PNP transistor P 7  serving as a switch for operating the feedback circuit  2  based on the output from the voltage-current converting circuit gm, a forth PNP transistor P 4  serving as a switch for operating the bias current output circuit  1 , and a second NPN transistor Q 2  for controlling the flow of the bias current Ib to the MR head Rmr by connecting an emitter of the seventh PNP transistor P 7 .  
         [0042]    A pair of registers R 4  and R 5  are connected to both end terminals of the MR head Rmr for setting a center point of the MR head Rmr to be the ground potential. Further an emitter of the second NPN transistor Q 2  is connected to the lower-side voltage source V EE  through a resistor R 6 .  
         [0043]    A second capacitor C 2  one of terminals of which is connected to the lower-side voltage source V EE  is connected to a base of the seventh PNP transistor P 7 , and a cutoff frequency of the feedback circuit  2  is determined by the second capacitor C 2 .  
         [0044]    An emitter of the seventh PNP transistor P 7  a base of which is connected to output of the voltage-current converting circuit gm is connected to the first current source I 1  by way of the first change-over switch SW 1 . A collector of the seventh PNP transistor P 7  is connected to the lower-side voltage source V EE .  
         [0045]    Further, an emitter of the forth PNP transistor P 4  a base of which is connected to an output of the voltage-current converting circuit gm is connected not only to a third current source I 3  but also to a base of the forth NPN transistor Q 4 , and is configured to carry out the operation control for the bias current output circuit  1 . A collector of the forth PNP transistor P 4  is connected to the lower-side voltage source V EE .  
         [0046]    In the read mode, namely when the first change-over switch SW 1  is ON state, and provided that R 1 =R 3 , and R 6 =R 8 , the transistors P 1  and P 3  have the same characteristics, and the transistors Q 2  and Q 4  have the same characteristics, and when the voltage Vmr of the MR head Rmr is less than the voltage V 1  of the reference voltage source V 1 , −terminal voltage of the voltage-current converting circuit gm is expressed as follows 
         (+terminal voltage of he voltage-current converting circuit gm)&lt;(−terminal voltage of the voltage-current converting circuit gm) 
         [0047]    Wherein the voltage of the −terminal voltage of the voltage-current converting circuit gm is ‘(+terminal voltage of he voltage-current converting circuit gm)+Vmr−V 1 ‘, and Vmr&lt;V 1 .  
         [0048]    In this case, in the feedback circuit  2 , in connection with the increase of the output current of the voltage-current converting circuit gm, the base potential of the seventh PNP transistor P 7  and the base potential of the forth PNP transistor P 4  are increased.  
         [0049]    In connection with the increase in the base potential of the forth PNP transistor P 4 , the base potential of the forth PNP transistor P 4  increases, and the bias current Ib outputted from the bias current output circuit  1  is increased, and in addition, in connection with the rise in the base potential of the seventh PNP transistor P 7 , the base potential of the second NPN transistor Q 2  is increased, and also the bias current Ib flowing through the MR head Rmr is increased.  
         [0050]    As a result, the voltage Vmr of the MR head Rmr increases, and when the voltage Vmr of the MR head Rmr becomes equal to the voltage V 1  of the reference voltage source V 1 , a feedback for stopping the output of the control current from the voltage-current converting circuit gm is activated.  
         [0051]    Further in the read mode, the base potential of the forth NPN transistor Q 4  becomes Vc 2 +Vbe, provided that the potential of the second capacitor C 2  is Vc 2 , so that the forth NPN transistor Q 4  always keeps its ON state, and the charging is carried out to the first oscillation suppressing capacitor C 1  which is the regulating circuit  3 .  
         [0052]    On the contrary in the write mode, namely in the mode where the first change-over switch SW 1  is OFF state and the second change-over switch SW 2  connects the second current source  12  and the control circuit  4  for regulating circuit, a base potential of the forth NPN transistor Q 4  becomes Vc 2 +Vbe, and accordingly, the forth NPN transistor Q 4  becomes ON state, so that the charging is carried out to the first oscillation suppressing capacitor C 1  which is the regulating circuit  3 .  
         [0053]    The charging to the first oscillation suppressing capacitor C 1  is carried out, regardless of the read mode or the write mode, by setting the forth NPN transistor Q 4  to be ON state, the potential across the first oscillation suppressing capacitor C 1  is not changed when the mode is changed from the write mode to the read mode. Accordingly, it becomes possible to start the playback immediately after the mode is changed by flowing a predetermined bias current Ib through the MR head Rmr, and it is able to shorten the switching time from the write mode to the read mode.  
         [0054]    In this case, in the present invention, the control circuit  4  for regulating circuit serves as a charging circuit for the first oscillation suppressing capacitor C 1  by carrying out the charging of the first oscillation suppressing capacitor C 1  in connection with the operation of the control circuit  4  for regulating circuit.  
         [0055]    In the present embodiment, the regulating circuit  3  comprises of a single first oscillation suppressing capacitor C 1 , but the invention is not limited to this single first oscillation suppressing capacitor C 1 , and the regulating circuit  3  may comprises of a combination of necessary elements.

Technology Classification (CPC): 6