Patent Abstract:
A method of transferring data between a first electrical component ( 16 ) and a second electrical component ( 18 ), which are both coupled to a common oscillator ( 62 ) that oscillates at a first frequency, the first electrical component ( 16 ) generating a first bit stream having a second frequency that is a fraction of the first frequency and having a first number of bits, generating an indicator signal having a third frequency that is a fraction of the first frequency and that is indicative of a type of data represented by the first bit stream, and coupling the first bit stream and the indicator signal to the second electrical component. The second electrical component ( 18 ) sampling the first bit stream and the indicator signal at a fourth frequency that is substantially identical to the second frequency, thereby recovering the first bit stream generated by the first electrical component ( 16 ) and determining the type of data contained in the first bit stream.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates in general to a method and apparatus for transferring digital information between electrical components and, in particular, to a method and apparatus for transferring digital information between electrical components without the use of a dedicated data clock or data over sampling. 
     BACKGROUND OF THE INVENTION 
     Presently, it is known for two or more electronic devices to exchange information or data using a serial data stream. Known methods of data transfer include a serial peripheral interface (SPI) that uses a dedicated data clock, data and enable signals to transfer serial data. Such interfaces are typically used in applications requiring data to be transferred from one electronic device or component to another electronic device or component. 
     One particular application in which data is transferred between electrical components is found in integrated circuit architectures used in wireless products that have a radio frequency integrated circuit (RF IC) and a baseband integrated circuit (BB IC). The RF IC receives and downconverts RF signals to baseband data signals that are coupled to the BB IC for further processing. The BB IC, among its various functions, may process the baseband data signals to develop a digital error or frequency control signal that is coupled to the RF IC. The RF IC may use the frequency control signal to correct and control its receive frequency synchronization. Additionally, the BB IC may generate a digital audio signal that may represent audio, such as voice, which is coupled to the RF IC for subsequent broadcast. 
     The use of an SPI to transfer the baseband data signals, the digital frequency control signal and the digital audio signal between the RF IC and the BB IC may require as many as nine dedicated pins on the integrated circuit chip (three pins for each signal to be transferred) and, therefore, may add cost and complexity to both the RF IC and the BB IC. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating a digital interface between a radio frequency integrated circuit (RF IC) and a baseband integrated circuit (BB IC). 
     FIG. 2 is a signal diagram illustrating the timing of various signals that may be used to couple data between the RF IC and the BB IC shown in FIG.  1 . 
     FIG. 3 is a block diagram of the clock synchronizers shown in FIG. 1 
     FIG. 4 is a model of a state machine employed by the clock synchronizer of FIGS.  1  and  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, a personal communication device  10 , such as a cellular telephone or the like, may generally include an antenna  12 , front end circuitry  14 , a radio frequency integrated circuit (RF IC)  16 , a baseband integrated circuit (BB IC)  18 , receive (RX) audio circuitry  20  and transmit (TX) audio circuitry  22 . The antenna  12  may receive an RF signal broadcast from a transmitter, such as a cellular base station (not shown), and may couple the RF signal to the front end circuitry  14 . The front end circuitry may process the RF signal and couple the processed RF signal to the RF IC  16 , wherein the processed RF signal may be fed to mixers  30  and  32 , which may be fed with local oscillator signals that may be 90° out of phase with respect to one another, due to a phase shifter  34 . The mixer  30  may generate a quadrature component of the RF signal and couple the quadrature component to a low pass filter  40 . Similarly, the mixer  32  may generate an in-phase component of the RF signal and couple the in-phase component to a low pass filter  42 . After the quadrature and the in-phase components are filtered by the low pass filters  40 ,  42 , the in-phase and quadrature components may be each coupled to 10 bit analog to digital converters  44 ,  46 . The output of the 10 bit analog to digital converter  44  is a 10 bit digital signal representative of the quadrature component of the RF signal. Similarly, the output of the 10 bit analog to digital converter  46  is a 10 bit digital signal representative of the in-phase component of the RF signal. The bit streams from the 10 bit analog to digital converters  44 ,  46  may be coupled to a serializer  48 . 
     The serializer  48  may also receive a Sync signal and a clock signal, both of which may be used to control the output of the serializer  48 . The clock signal may be generated by a divider  60  that is coupled to an oscillator  61 . In one embodiment, the oscillator  61  may be separate from the RF IC  16  and may have a frequency of 7.68 megahertz (MHz). Alternatively, the oscillator  61  may be integrated with the RC IC  16 . Either way, the divider  60  may divide the oscillator frequency by a factor of six to generate a clock signal having a frequency of 1.28 MHz. The Sync signal may be generated by an I/Q Sync generator  62  that may divide the clock signal from the divider  60  by a factor of twenty to produce a 64 kilohertz (KHz) Sync signal. More detail regarding the timing of the clock and Sync signals will be described hereinafter in conjunction with FIG.  2 . 
     Upon receiving the bit streams from the 10 bit analog to digital converters  44 ,  46  and the clock and Sync signals, the serializer  48  may generate an output bit stream having both the quadrature and the in-phase bits from the 10 bit analog to digital converters  44 ,  46  therein. The output bit stream from the serializer  48  may be coupled to the BB IC  18 , where it may be received and processed in a manner described in detail below. 
     In addition to the output bit stream from the serializer  48 , the oscillator  61  output may be coupled to the BB IC  18 . A buffer  64  in the RF IC  16  may receive the Sync signal from the I/Q Sync generator  62  and may generate a Sync&#39; signal that is also coupled to the baseband IC  18 . The Sync signal, which is generated by the I/Q Sync generator  62 , is a synchronization signal that is local only to the RF IC  16  and is used by the serializer  48  to transmit information from the RF IC  16  to the BB IC  18 . The Sync&#39; signal may also be coupled to the baseband IC  18 . Due to circuit board capacitance or inductance and a finite output impedance of the buffer  64 , the Sync&#39; signal may be slightly skewed with respect to the Sync signal. The Sync&#39; signal and the oscillator signal may both be coupled to a clock synchronizer  66 , which generates an Sclock-RF signal representative of a synchronized clock in the RF IC  16 . The clock synchronizer  66  may be a divider that divides the oscillator signal by a factor of six, wherein the clock synchronizer  66  may be reset by the Sync&#39; signal so that a negative edge of the Sclock-RF signal coincides with a state transition of the Sync&#39; signal. Accordingly, the Sclock-RF signal may have substantially the same frequency as the clock signal (e.g., if the oscillator  61  frequency is 7.68 MHz, the clock signal will be 1.28 MHz) and may be synchronized with the Sync&#39; signal. The RF IC  16  uses the Sync&#39; signal and the Sclock-RF signal to receive information from the BB IC  18 . 
     The BB IC  18  may also contain a clock synchronizer  70  that may receive the oscillator signal and the Sync&#39; signal from the RF IC  16  and may generate an Sclock-BB signal representative of a synchronized clock on the BB IC  18 . Like the clock synchronizer  66 , the clock synchronizer  70  may divide the oscillator signal by a factor of six and may be reset at every transition of the Sync&#39; signal. The clock synchronizer  70  maintains the timing of the Sclock-BB signal because the periodic reset caused by the Sync&#39; signal also resets the clock synchronizer  66  and thereby synchronizes the Sclock-BB signal with the Sclock-RF signal. Sclock-BB and Sclock-RF are then used to maintain alignment of data words that are transmitted between the RF IC  16  and the BB IC  18 . 
     The clock signals (e.g., the clock, the Sclock-BB and the Sclock-RF) are represented in FIG. 2 by a clock signal  76 . The clock signal  76  has a rising edge  78 , a high state  80 , a falling edge  82  and a low state  84 . As shown in FIG. 2, in one embodiment the clock signal  76  may have a period of 781.25 nanoseconds (ns), which corresponds to a clock frequency of 1.28 MHz. The synchronization signals (e.g., the Sync signal and the Sync&#39; signal) are represented in FIG. 2 by a synchronization signal  90 , having a rising edge  92 , a high state  94 , a falling edge  96  and a low state  98 . The sychronization signal  90  changes states (from low to high or from high to low) every time  10  falling edges  82  of the clock signal  76  occur. Accordingly, the synchronization signal  90  has a period of 15.625 microseconds (μs), which corresponds to a frequency of 64 KHz. 
     Also shown in FIG. 2 is a data signal timing diagram  100  that represents the timing of the output bit stream generated by the serializer  48  of the RF IC  16  and received by the BB IC  18 . For example, returning to FIG. 1, the output bit stream that is coupled from the serializer  48  to the BB IC  18  may contain alternating sequences of in-phase information and quadrature information, wherein each sequence contains ten bits. The in-phase information may be clocked out of the serializer  48  while the synchronization signal  90  is high, and the quadrature information may be clocked out of the serializer  48  while the synchronization signal is low. In other alternative embodiments, the in-phase information may be clocked out of the serializer  48  while the synchronization signal  90  is low and the quadrature information may be clocked out of the serializer  48  while the synchronization signal  90  is high. 
     The BB IC  18  includes an I/Q to phase converter  110  that receives the output bit stream from the serializer  48 , the Sync&#39; signal and the Sclock-BB signal. As shown in the data signal timing diagram  100  of FIG. 2, the I/Q to phase converter  110  clocks in data from the serializer  48  on every rising edge  78  of the clock signal  76 . As the I/Q to phase converter  110  clocks in the data bit by bit, the I/Q to phase converter  110  knows whether the clocked bits represent in-phase information or quadrature information based on the state of the Sync&#39; signal represented in FIG. 2 by the synchronization signal  90 . For example, when the synchronization signal  90  is in the high state  94 , the I/Q to phase converter  110  may interpret the output data received from the serializer  48  as in-phase data. Conversely, when the synchronization signal  90  is in the low state  98 , the I/Q to phase converter  110  may interpret the output data received from the serializer  48  as quadrature information. Because the I/Q to phase converter  110 , which may be thought of as a data receiver, is synchronized with the serializer  48 , the I/Q to phase converter  110  can receive an output bit stream without the use of a dedicated data clock and without over sampling the output bit stream. 
     As the I/Q to phase converter  110  receives the data from the serializer  48 , it converts the data from in-phase and quadrature format to differential phase format and couples the differential phase formatted information to a demodulator  120 . The demodulator  120  may produce an audio signal that may be coupled to the RX audio circuitry  20  to produce an analog audio signal that may be coupled to, for example, an earpiece speaker. The demodulator  120  may also produce a signal representative of a baseband offset frequency between the personal communication device  10  and a base station (not shown) with which the personal communication device  10  is communicating. 
     The signal representative of the baseband offset frequency may be coupled from the demodulator  120  to a serializer  130 , which operates in substantially the same manner as the serializer  48  of the RF IC  16 . The serializer  130  clocks 10 bit data words to the RF IC  16 . The 10 bit data words are representative of the frequency control signal (referred to hereinafter as a 10 bit frequency control signal) and are clocked at a rate determined by the Sclock-BB signal. A data signal timing diagram  140 , shown in FIG. 2, illustrates the timing at which the 10 bit frequency control signal from the serializer  130  may be clocked. Specifically, on the first rising edge  78  of the clock signal  76  that occurs after the rising edge  92  of the sychronization signal  90 , a new data bit  142  may be set. The new data bit  142  informs the RF IC  16  as to whether it should expect information from the BB IC  18 . For example, if the new data bit  142  is a logical one, the RF IC  16  may be programmed to expect more data that will be clocked from the serializer  130  on subsequent clock pulses. Conversely, if the new data bit  142  is a logical zero, the RF IC  16  may be programmed to ignore any subsequent “data” that may appear to follow. When the new data bit  142  is set, 10 bits of information will be clocked from the serializer  130  on the next 10 rising edges  78  of the clock signal  76 . The data bits following the next data bit  142  may be arranged from least significant bit to most significant bit, or may be arranged from most significant bit to least significant bit. 
     As data is output from the serializer  130 , it is received by a multi-accumulator fractional-N modulator, which may also be referred to as a fractional-N synthesizer (frac-N synth)  150 . As will be appreciated by those having ordinary skill in the art, the frac-N synth  150  receives serial data that is used to program a rapidly tuning synthesizer. The frac-N Synth  150  has sufficient bandwidth so that it can be programmed to the baseband signal without introducing distortion. The frac-N synth  150  is clocked by the Sclock-RF signal and the Sync&#39; signal and receives the 10 bit frequency control from the serializer  130  of the BB IC  18 . Because the Sclock-RF signal is synchronized by the Sync&#39; signal, which is the same signal used to synchronize the Sclock-BB signal that is used to clock the serializer  130 , the frac-N synth  150  is sufficiently synchronized to the serializer  130  to receive the 10 bit frequency control signal without the use of a dedicated data clock and without oversampling the 10 bit frequency control signal. 
     The frac-N synth  150  receives the 10 bit frequency control signal and, based on that signal, reprograms its output frequency. The output signal from the frac-N synth  150  is coupled to a low pass filter  160 , which filters the output signal and couples the filtered signal to a second local oscillator (LO)  162 . Although, the low pass filter  160  and the LO  162  are shown in FIG. 1 as being separate from the RF IC  16 , those having ordinary skill in the relevant art will readily appreciate that the low pass filter  162  and the LO  162  could be integrated into the RF IC  16 . The filtered output signal from the low pass filter  162  provides frequency correction to the LO  162  to keep the LO  162  oscillating at the proper frequency and phase. The output of the LO  162  may be coupled to the mixer  32  and further coupled to the mixer  30  through the phase shifter  34 . As described above, the mixers  30 ,  32  operate on the processed RF signal from the front end  14  to produce in-phase and quadrature components on the processed RF signal. 
     The BB IC  18  also includes a serializer  170  that is clocked by the Sclock-BB signal and that receives a digital audio signal from the TX audio circuitry  22 . The serializer  170  may couple the digital audio signal to the RF IC  16  in serial 9 bit words (referred to hereinafter as a 9 bit digital audio signal). Referring to a data signal timing diagram  172  shown in FIG. 2, on the first rising edge  78  of the clock signal  76  after a rising edge  92  of the synchronization signal  90 , the serializer  170  may clock a filler bit  174  to the RF IC  16 . In some applications the filler bit  174  provides no useful information to the RF IC  16  and is just used as a filler because the digital audio signal is only 9 bits long and 10 bits may be clocked out of the serializer  170  on each half cycle of the synchronization signal  90 . In other applications, the filler bit  174  may be used to carry useful information. The 9 bits following the filler bit  174  form the 9 bit digital audio signal, which transfers audio to the RF IC  16  so that the RF IC  16  may modulate the audio onto a carrier signal for broadcast. In some applications, the 9 bit digital audio signal may have its bits arranged from least significant to most significant. In other applications, the bits of the 9 bit digital audio signal may be arranged from most significant to least significant. 
     Because the 9 bit digital audio signal may need to be coupled to the RF IC  16  more frequently than the 10 bit frequency control signal, a second 9 bit word of digital audio is coupled from the serializer  170  to the RF IC  16  following the falling edge  96  of the synchronization signal  90 . A filler bit  176 , which may be followed by 9 digital audio bits, is clocked out of the serializer  170  on the first rising edge  78  of the clock signal  76  following the falling edge  96  of the synchronization signal  90 . Again, the 9 digital audio bits may be arranged from least significant to most significant or from most significant to least significant. Additionally, the filler bit  176  may or may not provide useful information to the RF IC  16 . 
     A frac-N synth  186  disposed within the RF IC  16  receives the 9 bit digital audio signal from the serializer  170 . Like the frac-N synth  150 , the frac-N synth  186  is clocked by the Sclock-RF signal and the Sync&#39; signal. Because the Sclock-RF signal is synchronized by the Sync&#39; signal, which is the same signal used to synchronize the Sclock-BB signal that is used to clock the serializer  170 , the frac-N synth  186  is sufficiently synchronized to the serializer  170  to receive the 9 bit digital audio signal without the use of a dedicated data clock and without the need to oversample the 9 bit digital audio signal. The frac-N synth  186 , upon receiving the 9 bit digital audio signal, changes its output frequency to create a frequency modulated signal representative of the information in the 9 bit digital audio signal. The analog signal may be coupled to transmitter (TX) circuitry  190 , which may be separate from or integrated with the RF IC  16 . The TX circuitry  190  may include an upconverter or a mixer and/or various other components known to those having ordinary skill in the art. The frequency modulated signal from the TX circuitry  190  is coupled to the antenna  12 , which broadcasts the signal. 
     Turning now to FIG. 3, the clock synchronizer  66 ,  70  may include an inverter gate  200 , a first D flip-flop  204 , a second flip-flop  206 , an AND gate  208  and a state machine  210 . The output of the oscillator  61 , which may be 7.68 MHz, may be coupled to the inverter gate  200  and the state machine  210 . The output of the inverter gate  200  has the same frequency as the input to the inverter gate  200 , except that the output of the inverter gate  200  is 180° out of phase with the input to the inverter gate  200 . The output of the inverter gate  200  clocks the D flip-flops  204 ,  206  at every negative edge of the output from the oscillator  61 . The Sync&#39; signal is coupled to the first D flip-flop  204 . The non-inverting output (Q) of the first D flip-flop  204  is coupled to the input (D) of the second D flip-flop  206  and is further coupled to the AND gate  208 . The inverting output ({overscore (Q)}) of the second D flip-flop  206  is also coupled to the AND gate  208 . The output of the AND gate  208 , which is referred to herein as the Pos signal, is an edge detect of the Sync&#39; signal running off the negative edge of the oscillator  61 . For example, when two consecutive states of the Sync&#39; signal are the same, the output of the AND gate  208  is a logical zero and when two consecutive states of the Sync&#39; signal are different, the output of the AND gate  208  is a logical one. 
     The state machine  210 , which receives inputs from the oscillator  61  and the AND gate  208 , can change the state of its output (Sclock) on each pulse of the oscillator  61 , wherein the state of the output Sclock signal is dependent on the state of the Pos signal provided to the state machine  210 . Further detail regarding the implementation and operation of the state machine  210  is given with respect to FIG. 4 below. 
     The state machine  210  may be implemented using combinational logic, application specific hardware or any other suitable electrical technology known to those having ordinary skill in the art. A register transfer language (RTL) such as VERILOG may be used to model the operation of the state machine  210  and to automatically produce the appropriate hardware to carry out the model. As shown in FIG. 4, the state machine model has seven states represented by seven circles labeled  0 - 6 , each state having an associated Sclock output that is produced at each pulse of the oscillator  61  (FIG. 1) and the state of which is determined by the Pos signal (FIG.  3 ). For example, states  0 - 3  have an Sclock output equal to 0 and states  4 - 6  have an Sclock output equal to 1. 
     The state machine  210  may begin operation in the 0 state and may remain in the 0 state so long as the Pos signal is equal to 1. However, when the Pos signal goes low (becomes equal to 0), the state machine  210  may transition from state  0  to state  2  as indicated by an arrow from state  0  to state  2  that is labeled “Pos=0.” As can be seen from FIG. 4, as long as the Pos signal is equal to 0, the state machine  210  will traverse from state  0  to state  2 , to state  3  and so on until the machine  210  reaches state  6 , wherein if the Pos signal is still equivalent to 0, the state machine  210  transitions from state  6  to state  1 . Accordingly, as long as the Pos signal is equal to 0, the state machine  210  repeatedly traverses from state  1  to state  6  through states  2 - 5  and back to state  1  again. When the Pos signal is equal to  1 , the state machine  210  will transition from whichever state it is currently in, to state  0 , which may be referred to as the reset state. 
     During operation of the clock synchronizer  66 ,  70 , when the input to the second D flip-flop  206  and the output of the second D flip-flop  206  are both a logical  1 , the AND gate  208  generates a Pos signal equal to 1, which resets the state machine  210  to state  0 . When the state machine is at state  0 , Sclock equals 0. Therefore, each time the clock synchronizer  66 ,  70  detects an edge on the Sync&#39; signal, the clock synchronizer  66 ,  70  creates a negative edge Sclock signal thereby synchronizing the Sclock signal with the Sync&#39; signal. As shown in FIG. 4, states  1 ,  2  and  3  have an associated Sclock signal equal to 0 in states  4 ,  5  and  6  have an associated Sclock signal equal to 1. Accordingly, during periods of time, when no edges of the Sync&#39; signal are detected, the state machine  210  repeatedly traverses from state  1  to state  6 , thereby tracing out a 50% duty cycle signal having a frequency that is one-sixth of the oscillator frequency. During such operation, states  1 ,  2  and  3  represent the low state of the Sclock signal and states  4 ,  5  and  6  represent the high state of the Sclock signal. 
     The foregoing description is one embodiment of a device constructed in accordance with the teachings of the present invention. Consequently, it will be understood by those of ordinary skill in the art, that the teachings of the present invention may be carried out in software resident on a processor such as a digital signal processor or by dedicated hardware that is designed to carry out the various functions disclosed herein. Accordingly, the foregoing description has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Technology Classification (CPC): 7