Patent Abstract:
Disclosed is a printed circuit board (PCB) and a method of fabricating the same. A contact portion is formed on an internal layer of the multi-layered PCB. A groove is formed so as to expose the contact portion of the internal layer. A chip package is mounted on the PCB while being flip-chip bonded to the exposed contact portion of the internal layer.

Full Description:
INCORPORATION BY REFERENCE 
       [0001]    The present application is a divisional of U.S. patent application Ser. No. 11/128,852, filed May 13, 2005, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2004-74872 filed on Sep. 18, 2004. The contents of both applications are incorporated herein by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates, in general, to a printed circuit board (PCB) and a method of fabricating the same and, more particularly, to a PCB and a method of fabricating the same, in which a contact portion is formed on an internal layer of the multi-layered PCB, a groove is formed so as to expose the contact portion of the internal layer, and a chip package is mounted on the PCB while being flip-chip bonded to the exposed contact portion of the internal layer. 
         [0004]    2. Description of the Prior Art 
         [0005]    A semiconductor package is exemplified by a resin seal package, a tape carrier package (TCP), a glass seal package, and a metal seal package. Furthermore, the semiconductor package is classified into a TH-type, in which a hole is formed through a PCB and a pin is inserted into the hole, and a surface mounting technology (SMT) type, in which it is mounted on a surface of a PCB, according to a mounting method thereof. 
         [0006]    The TH-type is the typical integrated circuit (IC) package which has been used for the longest time, and representative examples include a dual inline package (DIP), in which a plurality of pins protrude from both sides of the package in a straight line, and a pin grid array (PGA), in which pins are arranged on the underside of a large hexahedron. 
         [0007]    The SMT-type is a package having a structure in which, when a packaged chip is electrically connected to a substrate, the electric connection is achieved on the substrate unlike the TH-type, in which the pin is inserted into the hole and soldered. 
         [0008]    Compared to the TH-type, the SMT-type is advantageous in that, assuming that chips having the same size are employed, the mounting area is reduced because of the small size, it is thin and lightweight, and operation speed improves with an increase in frequency because of a low parasitic capacitance or inductance. 
         [0009]    Other advantages are that it is unnecessary to form a hole, a soldering region and a pitch can be reduced, it is possible to achieve highly dense wiring and mounting, and the cost of fabricating a PCB can be reduced. However, the SMT-type is disadvantageous in that it is difficult to inspect the appearance of a soldered part. 
         [0010]    Representative examples of the SMT-type package include a quad flat package (QFP), a plastic leaded chip carrier (PLCC), a ceramic leaded chip carrier (CLCC), and a ball grid array (BGA). 
         [0011]    Meanwhile, there are some limits with respect to the size and thickness of a PCB in the course of mounting many parts on the PCB. Recently, demand for slim mobile devices which are handy to carry is growing, and thus, it is necessary to arrange integrated and passive components in a space having a restricted area and height on a surface of the PCB. 
         [0012]    A thin chip may be fabricated to satisfy such a necessity. In this case, however, handling problems and signal interference problems between layers may occur. 
         [0013]    In other words, multiple layers of integrated circuit chips are integrated in one conventional integrated circuit chip package. At this time, the integrated circuit chip must be very thin in order to insert many layers of chips into a package having a restricted thickness. However, since the integrated circuit chip is very thin, it is difficult to handle the chip and signal interference problems between the integrated circuit chips occur. 
         [0014]    Meanwhile, a technology of embedding an integrated circuit chip in a PCB has been suggested to compensate for insufficient space. 
         [0015]    With respect to the above technology, Japanese Pat. Laid-Open Publication No. 11-274734 discloses an electronic circuit device which is provided with a circuit substrate that acts as a core, electronic parts mounted on the circuit substrate, an insulating layer formed on the circuit substrate, and a circuit formed on the insulating layer. 
         [0016]      FIG. 1  is a sectional view of a conventional PCB having a chip mounted thereon. 
         [0017]    Referring to  FIG. 1 , in the conventional PCB having the chip mounted thereon, a circuit substrate  10  is used as a core, and circuit patterns  12 ,  18  are formed on upper and lower sides of the circuit substrate. 
         [0018]    A through hole  13  is formed through the circuit substrate  10  to connect external and internal circuits to each other. A chip  16  is flip-chip bonded to the circuit substrate  10  and thus mounted on it. A welding bump  17  formed on a pad of the integrated circuit chip  16  is connected to a land  18  on the circuit substrate  10 . 
         [0019]    Additionally, a plurality of insulating layers  22  is laminated on the circuit substrate  10 , and a circuit pattern  25  is formed on each of the insulating layers  22 . 
         [0020]    At this stage, an integrated circuit chip  29  is mounted on an external surface of the outermost layer  22  of the insulating layers  22 , and connected to a wire pattern on the surface of the outermost insulating layer  22 . 
         [0021]    However, in the conventional technology of embedding the integrated circuit chip in the PCB, it is difficult to form a passage for emitting heat, and thus, it is hard to apply the technology to an integrated circuit chip which generates a lot of heat. 
         [0022]    Furthermore, since it is necessary to control occurrence of dust during the fabrication of the PCB to be the same level as that during the fabrication of a semiconductor, undesirably, clean room facilities must be newly installed or the level of dust must be tightly controlled. 
       SUMMARY OF THE INVENTION 
       [0023]    Therefore, the present invention has been made keeping in mind the above disadvantages occurring in the prior arts, and an object of the present invention is to provide a PCB and a method of fabricating the same. In the method, a contact portion, on which a chip package is to be mounted, is formed in the PCB, the lamination of layers is conducted so that the contact portion formed on an internal layer of a substrate is exposed, and the chip package is flip-chip bonded to the contact portion of the internal layer, thereby mounting the thick chip package in a space having a restricted height on a surface of the substrate. 
         [0024]    The above object can be accomplished by providing a PCB having a chip package mounted thereon, which comprises a substrate having a plurality of electric contact portions formed on an upper side thereof and acting as a core. The chip package is mounted on the substrate and has bumps connected to the electric contact portions. An insulating layer is laminated on the substrate and has a hole in which the chip package is to be mounted. 
         [0025]    Furthermore, the present invention provides a method of fabricating a PCB having a chip package mounted thereon. The method includes the steps of forming a first etching resistor to form an electric contact portion on an upper side of a first circuit layer on one side of a substrate; applying a first photosensitive substance on the first circuit layer of the substrate to form a first circuit pattern on the first circuit layer, and removing the first photosensitive substance; laminating an insulating layer and a second circuit layer on the substrate, and forming a hole through a portion of the insulating layer, in which the chip package is to be mounted; applying a second photosensitive substance to form a second circuit pattern on the second circuit layer, and forming the electric contact portion on the exposed first circuit layer of the substrate, on which the first etching resistor is formed; and mounting the chip package so that the chip package is connected to the electric contact portion formed on an exposed internal layer of the substrate. 
         [0026]    Furthermore, the present invention provides a method of fabricating a PCB having a chip package mounted thereon. The method includes the steps of laminating an insulating layer and a first circuit layer on an upper side of a second circuit layer on one side of a substrate, on which a first circuit pattern is formed; removing portions of the insulating layer and the first circuit layer laminated on the substrate, which have a position corresponding to an area in which the chip package is to be mounted; applying a photosensitive substance on internal and external layers so that the photosensitive substance adheres closely to the internal and external layers, and forming a second circuit pattern on the photosensitive substance to form an electric contact portion and to form a third circuit pattern on the external layer; conducting an etching process using the second circuit pattern, formed on the photosensitive substance, to form the third circuit pattern on the external layer and to form the electric contact portion on the internal layer; and mounting the chip package so that the chip package is connected to the electric contact portion formed on the exposed second circuit layer of the substrate. 
         [0027]    Furthermore, the present invention provides a method of fabricating a PCB having a chip package mounted thereon. The method includes the steps of forming a first circuit pattern, which includes an electric contact portion, to be connected to the chip package, on a first circuit layer of a substrate; laminating an insulating layer and a second circuit layer on an upper side of the first circuit layer on one side of the substrate, on which the first circuit pattern is formed; removing portions of the insulating layer and the second circuit layer laminated on the substrate, which have a position corresponding to an area in which the chip package is to be mounted; and mounting the chip package so that the chip package is connected to the electric contact portion formed on the exposed first circuit layer of the substrate. 
         [0028]    Furthermore, the present invention provides a method of fabricating a PCB having a chip package mounted thereon. The method includes the steps of forming a first circuit pattern, which includes an electric contact portion, to be connected to the chip package, on a first circuit layer of a substrate; surrounding the electric contact portion using an etching resistor; laminating an insulating layer, through which a hole is formed so as to mount the chip package therein while the chip package being connected to the electric contact portion, and laminating a second circuit layer on the insulating layer; laminating a photosensitive substance on the second circuit layer, forming a second circuit pattern, of which a portion, having a position corresponding to the hole, is removed, on the photosensitive substance, and etching the resulting substrate to form a third circuit pattern on the second circuit layer; and mounting the chip package so that the chip package is connected to the electric contact portion formed on the exposed first circuit layer of the substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]    The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0030]      FIG. 1  is a sectional view of a conventional PCB having a chip mounted thereon; 
           [0031]      FIG. 2  is a sectional view of a PCB having a chip package mounted thereon according to an embodiment of the present invention; 
           [0032]      FIGS. 3   a  to  3   p  are sectional views illustrating the fabrication of the PCB having the chip package mounted thereon according to an embodiment of the present invention; 
           [0033]      FIGS. 4   a  to  4   q  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to a further embodiment of the present invention; 
           [0034]      FIGS. 5   a  to  5   k  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention; 
           [0035]      FIGS. 6   a  to  6   l  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to a further embodiment of the present invention; 
           [0036]      FIGS. 7   a  to  7   l  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention; 
           [0037]      FIGS. 8   a  to  8   m  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to a further embodiment of the present invention; and 
           [0038]      FIGS. 9   a  to  9   d  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0039]    Hereinafter, a detailed description will be given of the present invention with reference to  FIGS. 2 to 9   d.    
         [0040]      FIG. 2  is a sectional view of a PCB having a chip package mounted thereon according to an embodiment of the present invention. 
         [0041]    Referring to  FIG. 2 , the PCB having the chip package mounted thereon according to an embodiment of the present invention comprises a copper clad laminate  210  acting as a core, a plurality of insulating layers  231 ,  233  laminated on the copper clad laminate  210 , a plurality of circuit layers  232 ,  234 , solder resist films  240 ,  241  applied on the external circuit layers  232 ,  234  and an exposed internal circuit layer  212 , a chip package  250 , and a conductive material  242  interposed between bumps  251  of the chip package  250  and contact portions of the internal circuit layer  212 . 
         [0042]    The copper clad laminate  210  is made of an insulating material, and comprises an insulating layer  211  having a predetermined thickness, and copper foil layers  212 ,  213  positioned on both sides of the insulating layer  211  and having circuit patterns. 
         [0043]    In this respect, the contact portions, to which the bumps  251  of the chip package  250  are capable of being flip-chip bonded, are formed on the copper foil layer  212  on one side of the insulating layer  211 . The contact portions are electrically connected to other portions  213  through holes  214 . 
         [0044]    Additionally, a groove, which corresponds in size to the chip package  250 , is formed on the insulating layer  231  laminated on an upper side of the copper clad laminate  211  so that the chip package  250  is flip-chip bonded to the contact portions formed in the internal circuit layer  212 . Furthermore, the contact portions of the internal circuit layer  212  are exposed. 
         [0045]    The chip package  250  is flip-chip bonded through the groove to the contact portions using the bumps  251  attached thereto, thereby being mounted on the PCB. 
         [0046]    At this stage, the electric conductive material  242  may be applied so as to improve the adhesion strength between the bumps  251  of the chip package  250  and the contact portions. 
         [0047]    Furthermore, the solder resist may be applied on the external circuit layers  232  and the exposed internal circuit layer  212 . 
         [0048]    As well, as shown in  FIG. 2 , a side wall connection is feasible by use of a lead frame, and thus, it is possible to assure many channels for signal connection. 
         [0049]      FIGS. 3   a  to  3   p  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to an embodiment of the present invention. 
         [0050]    Referring to  FIG. 3   a , a circuit substrate  310  acting as a core is provided. The circuit substrate  310  is made of an insulating material, and comprises an insulating layer  311 , having a predetermined thickness, and copper foil layers  312 ,  313  positioned on upper and lower sides of the insulating layer  311 . Furthermore, a plurality of through holes  314  is formed through the circuit substrate  310  to connect circuits on both sides of the circuit substrate to each other. 
         [0051]    With reference to  FIGS. 3   b  and  3   c , photosensitive substances  321 ,  322  are applied on the copper foil layers  312 ,  313  of the circuit substrate  310 . Subsequently, the upper photosensitive substance  321  is selectively removed through exposure and development processes to expose a portion of the copper foil layer  312  which is not to be removed, thereby forming a portion on which the chip package is to be mounted. Such a photolithography process may be classified into a photographic process and a screen printing process. Employing an art work film having a circuit pattern printed thereon, the photographic process is divided into a dry film (D/F) process using a dry film as a photosensitive material, and a photosensitive liquid process using photosensitive liquid. 
         [0052]    Referring to  FIG. 3   d , an etching resistor  323 , which is capable of being used as a resistor during a copper etching process using gold or nickel, is applied on the exposed portion of the copper foil layer so as to prevent the copper foil layer from being etched when the copper etching process is conducted using gold or nickel, thereby providing an electric connection to the chip package to be mounted. At this time, it is preferable to form the etching resistor  323  through a plating process. 
         [0053]    Referring to  FIG. 3   e , the photosensitive substances  321 ,  322  are removed from both sides of the copper foil layers  312 ,  313  using a stripping process, and photosensitive substances  324 ,  325  are further applied to form a circuit as shown in  FIG. 3   f.    
         [0054]    At this time, a portion of the photosensitive substances  324 ,  325  corresponding in position to an area in which the chip package is to be mounted is not etched. However, the remaining portion, under which the copper foil layer is to be etched, is exposed and developed to expose a portion of the copper foil layer to be etched, as shown in  FIG. 3   g.    
         [0055]    As shown in  FIG. 3   h , after a circuit pattern of the copper foil is formed using circuit patterns of the photosensitive substances  324 ,  325  as an etching resist, the photosensitive substances  324 ,  325  as the etching resist are stripped to complete the formation of the circuit pattern of the copper foil. At this time, the etching resistor  323  must not be removed. 
         [0056]    Next, after an etching process is conducted as shown in  FIG. 3   i  to form a circuit on an internal layer, the photosensitive substances  324 ,  325  are removed through a stripping process, and a plurality of insulating layers  331 ,  333  and circuit layers  332 ,  334  are further laminated. 
         [0057]    As shown in  FIG. 3   j , in order to remove a portion of the insulating layer  331 , corresponding in position to an area in which the chip package is to be mounted, the copper foil positioned on that portion of the insulating layer  331  is removed through a process using a laser or a plasma. 
         [0058]    Subsequently, after a portion of the copper foil, corresponding in position to an area in which the chip package is to be mounted, is removed as shown in  FIG. 3   k , a portion of the insulating layer  331 , also corresponding in position to the area in which the chip package is to be mounted, is removed through a process, using a laser or a plasma, capable of removing the insulating layer  331 . At this time, if necessary, it is preferable to control the removal of the insulating layer so as to prevent the resulting substrate from being excessively removed. Additionally, it is preferable that a material of the insulating layer, which is to be removed, be different from that of the insulating layer, which must not be removed, so as to prevent the insulating layer, which must not be removed, from being etched. 
         [0059]    As shown in  FIG. 31 , photosensitive materials  335 ,  336  are applied to form circuits on the outermost layers  332 ,  334 . 
         [0060]    As shown in  FIG. 3   m , the photosensitive materials  335 ,  336  are exposed and developed to form circuit patterns thereon. At this time, a portion of the photosensitive materials  335 ,  336 , corresponding in position to an area in which the chip package is to be mounted, is removed so that an exposed copper foil portion of the internal layer  312 , corresponding in position to an area in which the chip package is to be mounted, is removed by a copper etching process. 
         [0061]    As shown in  FIG. 3   n , wire patterns are formed on the external circuit layers  332 ,  334  and the exposed internal copper foil layer  312  using the circuit patterns of the photosensitive materials  335 ,  336  and the etching resistor  323  as an etching resist. In other words, circuits are formed on a surface of the resulting substrate and the copper foils  312 ,  332 ,  334  of the internal layer through the etching process. 
         [0062]    As shown in  FIG. 3   o , after the photosensitive materials  335 ,  336  are completely removed through a stripping process, the chip package is mounted on the surface of the internal layer of the substrate. In the case where the etching resistor  323  formed on the internal layer must be removed, the removal may be conducted through an etching resistor stripping process as shown in  FIG. 3   p . However, if the etching resistor is formed by gold plating, it is preferable that the etching resistor be not removed. 
         [0063]      FIGS. 4   a  to  4   q  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention. 
         [0064]    Referring to  FIG. 4   a , a circuit substrate  410  acting as a core is provided. The circuit substrate  410  is made of an insulating material, and comprises an insulating layer  411 , having a predetermined thickness, and copper foil layers  412 ,  413  positioned on upper and lower sides of the insulating layer  411 . Furthermore, a plurality of through holes  414  is formed through the circuit substrate  410  to connect circuits on both sides of the circuit substrate to each other. 
         [0065]    With reference to  FIGS. 4   b  and  4   c , photosensitive substances  421 ,  422  are applied on the copper foil layers  412 ,  413  of the circuit substrate  410 . Subsequently, the photosensitive substances  421 ,  422  are selectively removed through exposure and development processes to expose a portion of the upper copper foil layer  412 , which is not to be removed, thereby forming a portion on which the chip package is to be mounted. 
         [0066]    Referring to  FIG. 4   d , an etching resistor  423 , which is capable of being used as a resistor during a copper etching process using gold or nickel, is applied on the exposed portion of the copper foil layer so as to prevent the copper foil layer from being etched when the copper etching process is conducted using gold or nickel, thereby providing an electric connection to the chip package to be mounted. At this time, it is preferable to form the etching resistor  423  through a plating process. 
         [0067]    Referring to  FIG. 4   e , the photosensitive substances  421 ,  422  are removed from both sides of the copper foil layers  412 ,  413  using a stripping process, and photosensitive substances  424 ,  425  are further applied to form a circuit as shown in  FIG. 4   f.    
         [0068]    At this stage, a portion of the photosensitive substances  424 ,  425 , corresponding in position to an area in which the chip package is to be mounted, is not etched. However, the remaining portion, under which the copper foil layer is to be etched, is exposed and developed to expose a portion of the copper foil layer to be etched, as shown in  FIG. 4   g.    
         [0069]    As shown in  FIG. 4   h , after a circuit pattern of the copper foil is formed using circuit patterns of the photosensitive substances  424 ,  425  as an etching resist, the photosensitive substances  424 ,  425  as the etching resist are stripped to complete the formation of the circuit pattern of the copper foil. 
         [0070]    Next, after an etching process is conducted as shown in  FIG. 4   i  to form a circuit on an internal layer, the photosensitive substances  424 ,  425  are removed through a stripping process, and a plurality of insulating layers  431 ,  433  and circuit layers  432 ,  434  are further formed. 
         [0071]    As shown in  FIG. 4   j , in order to remove a portion of the insulating layer  431  corresponding in position to an area in which the chip package is to be mounted, a portion of the copper foil, which is positioned on such portion of the insulating layer  431 , is removed through a process using a laser or a plasma. 
         [0072]    Subsequently, after a portion of the copper foil, corresponding in position to an area in which the chip package is to be mounted, is removed as shown in  FIG. 4   k , a portion of the insulating layer  431 , corresponding in position to an area in which the chip package is to be mounted, is removed through a process, using a laser or a plasma, capable of removing the insulating layer  431 . At this stage, if necessary, it is preferable to control the removal of the insulating layer so as to prevent the resulting substrate from being excessively removed. Additionally, it is preferable that the material of the insulating layer, which is to be removed, be different from that of the insulating layer, which must not be removed, so as to prevent the insulating layer, which must not be removed, from being etched. 
         [0073]    As shown in  FIG. 41 , photosensitive materials  435 ,  436  are applied to form circuits on the outermost layers  432 ,  434 . 
         [0074]    As shown in  FIG. 4   m , the photosensitive materials  435 ,  436  are exposed and developed to form circuit patterns thereon. At this stage, a portion of the photosensitive materials  435 ,  436 , corresponding in position to an area in which the chip package is to be mounted, is not removed. 
         [0075]    As shown in  FIG. 4   n , etching resistors  437 ,  438  are applied on the circuit patterns formed on the photosensitive materials  435 ,  436  using exposure and development processes. At this stage, it is preferable that the application of the etching resistors  437 ,  438  be conducted by a plating process. 
         [0076]    As shown in  FIG. 4   o , the photosensitive materials  435 ,  436  are removed so as to form wire patterns on the copper foil using the circuit patterns of the etching resistors  437 ,  438  as an etching resist. 
         [0077]    As shown in  FIG. 4   p , after the photosensitive materials  435 ,  436  are removed through a stripping process, circuits are formed on a surface of the resulting substrate and the copper foils  412 ,  413 ,  432 ,  434  of the internal layer through an etching process employing the etching resistors  437 ,  438  as the etching resist. 
         [0078]    As shown in  FIG. 4   q , after the etching resistors  437 ,  438  are completely removed through a stripping process, the chip package is mounted on the surface of the internal layer of the substrate. In case that the etching resistor  423  formed on the internal layer must be removed as shown in  FIG. 4   q , the removal may be conducted through an etching resistor stripping process. However, if the etching resistor is formed by a gold plating, it is preferable that the etching resistor not be removed. 
         [0079]      FIGS. 5   a  to  5   k  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention. 
         [0080]    Referring to  FIG. 5   a , a circuit substrate  510  acting as a core is provided. The circuit substrate  510  is made of an insulating material, and comprises an insulating layer  511 , having a predetermined thickness, and copper foil layers  512 ,  513  positioned on upper and lower sides of the insulating layer  511 . Furthermore, a plurality of through holes  514  is formed through the circuit substrate  510  to connect circuits on both sides of the circuit substrate to each other. 
         [0081]    With reference to  FIGS. 5   b  and  5   c , photosensitive substances  521 ,  522  are applied on the copper foil layers  512 ,  513  of the circuit substrate  510 . Subsequently, circuit patterns are formed on a portion of the photosensitive substances  521 ,  522 , corresponding in position to an area in which the chip package is not mounted, through a photolithography process, and another circuit patterns are formed on the copper foil layers  512 ,  513  using the photosensitive substances  521 ,  522  as an etching resist. 
         [0082]    As shown in  FIG. 5   d , the photosensitive substances  521 ,  522  are removed through a stripping process, and a plurality of insulating layers  531 ,  533  and circuit layers  532 ,  534  are further formed as shown in  FIG. 5   e.    
         [0083]    As shown in  FIG. 5   f , in order to remove a portion of the insulating layer  531 , corresponding in position to an area in which the chip package is to be mounted, photosensitive substances  535 ,  536  are applied on the outermost layers  532 ,  534 . 
         [0084]    As shown in  FIG. 5   g , in order to remove a portion of the insulating layer  531 , corresponding in position to an area in which the chip package is to be mounted, the photosensitive substance  535  is exposed and developed to be removed at a portion thereof, corresponding in position to the area in which the chip package is to be mounted. Subsequently, an etching process is conducted to remove a portion of the copper foil layer  532  of the outermost layer, corresponding in position to the area in which the chip package is to be mounted. 
         [0085]    After the function of the photosensitive substance  531  is completed, the photosensitive substance is removed by a stripping process as shown in  FIG. 5   h . Subsequently, a portion of the insulating layer  531 , corresponding in position to an area in which the chip package is to be mounted, is removed through a process, using a laser or a plasma, capable of removing the insulating layer  531 . Furthermore, photosensitive materials  537 ,  538  are applied on a surface of the resulting substrate to form circuits on external layers. 
         [0086]    As shown in  FIG. 5   i , circuits are formed on the photosensitive materials  537 ,  538  through exposure and development processes. At this time, in the exposure process, a portion of the photosensitive materials  537 ,  538 , corresponding in position to an area in which the copper foil must not be removed, may be hardened using radiation that travels very straight, such as UV radiation, X-rays, or a laser. 
         [0087]    As well, as shown in  FIG. 5   j , the copper foil  532  on a surface of the resulting substrate, and the copper foil  512  of the internal layer, on which the chip package is to be mounted, are simultaneously etched through an etching process employing the photosensitive materials  537 ,  538  as an etching resist. 
         [0088]    As shown in  FIG. 5   k , after the photosensitive materials are completely removed through a stripping process, the chip package is mounted on a surface of the internal layer of the substrate. 
         [0089]      FIGS. 6   a  to  6   l  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention. 
         [0090]    Referring to  FIG. 6   a , a circuit substrate  610  acting as a core is provided. The circuit substrate  610  is made of an insulating material, and comprises an insulating layer  611 , having a predetermined thickness, and copper foil layers  612 ,  613  positioned on upper and lower sides of the insulating layer  611 . Furthermore, a plurality of through holes  614  is formed through the circuit substrate  610  to connect circuits on both sides of the circuit substrate to each other. 
         [0091]    With reference to  FIGS. 6   b  to  6   d , photosensitive substances  621 ,  622  are applied on the copper foil layers  612 ,  613  of the circuit substrate  610 . Subsequently, circuit patterns are formed on the photosensitive substances  621 ,  622  through a photolithography process, and other circuit patterns are then formed on the copper foil layers  612 ,  613  using the photosensitive substances  621 ,  622  as an etching resist. Thereby, the circuit patterns are formed on a portion of the internal layers  612 ,  613 , corresponding in position to an area in which the chip package is to be mounted, and another portion of the internal layers. 
         [0092]    As shown in  FIG. 6   e , the photosensitive substances  621 ,  622  are removed through a stripping process, and a plurality of insulating layers  631 ,  633  and circuit layers  632 ,  634  is further formed as shown in  FIG. 6   f.    
         [0093]    As shown in  FIG. 6   g , in order to remove a portion of the insulating layer  631 , corresponding in position to an area in which the chip package is to be mounted, photosensitive substances  635 ,  636  are applied on the outermost layers  632 ,  634 . 
         [0094]    As shown in  FIG. 6   h , in order to remove a portion of the insulating layer  631 , corresponding in position to an area in which the chip package is to be mounted, the photosensitive substance  635  is exposed and developed to be removed at a portion thereof, corresponding in position to the area in which the chip package is to be mounted. Subsequently, an etching process is conducted to remove a portion of the copper foil layer  632  of the outermost layer, corresponding in position to the area in which the chip package is to be mounted. 
         [0095]    After the function of the photosensitive substance  635  is completed, the photosensitive substance is removed through a stripping process as shown in  FIG. 6   i . Subsequently, as shown in  FIG. 6   j , a portion of the insulating layer  631 , corresponding in position to an area in which the chip package is to be mounted, is removed through a process capable of removing the insulating layer  631  using a laser or a plasma. 
         [0096]    As shown in  FIG. 6   k , photosensitive materials  637 ,  638  are applied on a surface of the resulting substrate, and exposure and development processes are then conducted to form circuit patterns on external layers. Since the circuit pattern is already formed on the internal layer  612 , on which the chip package is to be mounted, the circuit patterns are formed on a portion of the external layers, on which the chip package is not to be mounted. At this time, in the exposure process, a portion of the photosensitive materials  637 ,  638 , corresponding in position to an area in which the copper foil must not be removed, may be hardened using radiation that travels very straight, such as UV radiation, X-rays, or a laser. 
         [0097]    As shown in  FIG. 6   l , after the copper foil  632  on a surface of the resulting substrate is etched through an etching process employing the photosensitive materials  637 ,  638  as an etching resist, and the photosensitive materials are completely removed through a stripping process, the chip package is mounted on a surface of the internal layer of the substrate. 
         [0098]      FIGS. 7   a  to  7   l  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention. 
         [0099]    Referring to  FIG. 7   a , a circuit substrate  710  acting as a core is provided. The circuit substrate  710  is made of an insulating material, and comprises an insulating layer  711 , having a predetermined thickness, and copper foil layers  712 ,  713  positioned on upper and lower sides of the insulating layer  711 . Furthermore, a plurality of through holes  714  is formed through the circuit substrate  710  to connect circuits on both sides of the circuit substrate to each other. 
         [0100]    With reference to  FIGS. 7   b  to  7   d , photosensitive substances  721 ,  722  are applied on the copper foil layers  712 ,  713  of the circuit substrate  710 . Subsequently, circuit patterns are formed on the photosensitive substances  721 ,  722  through a photolithography process, and other circuit patterns are then formed on the copper foil layers  712 ,  713  using the photosensitive substances  721 ,  722  as an etching resist. Thereby, the circuit patterns are formed on a portion of the internal layers  712 ,  713 , corresponding in position to an area in which the chip package is to be mounted, and another portion of the internal layers. 
         [0101]    As shown in  FIG. 7   e , the photosensitive substances  721 ,  722  are removed through a stripping process. 
         [0102]    As shown in  FIG. 7   f , photosensitive substances  723 ,  724  are applied to achieve the selective application of an etching resistor  725 . 
         [0103]    As shown in  FIG. 7   g , the photosensitive substance  723  is exposed and developed to expose a portion on which the etching resistor  725  is to be applied. 
         [0104]    As shown in  FIG. 7   h , after the etching resistor  725  is applied, the photosensitive substances  723 ,  724  are removed through a stripping process. At this stage, it is preferable that the application of the etching resistor  725  be conducted using a plating process. 
         [0105]    As shown in  FIG. 7   i , a plurality of insulating layers  726 ,  728  and circuit layers  727 ,  729  are further formed. In this regard, a portion of the insulating layer  726 , in which the chip package is to be mounted, is already removed, and a portion of the copper foil layer  727 , corresponding in position to that portion of the insulating layer, remains. Accordingly, it is unnecessary to etch that portion of the insulating layer  726  to mount the chip package in the insulating layer. 
         [0106]    As shown in  FIG. 7   j , photosensitive substances  730 ,  731  are applied on the outermost layers  727 ,  729  to form a circuit pattern on the outermost layer  727 . 
         [0107]    As shown in  FIG. 7   k , the photosensitive substance  730  is exposed and developed to be removed at a portion thereof, which corresponds in position to the circuit pattern of the outermost layer  727 , so as to form the circuit pattern on the outermost layer  727 . At this stage, a portion of the photosensitive substance  730 , corresponding in position to an area in which the chip package is to be mounted, is completely removed. 
         [0108]    Furthermore, an etching process is conducted using the photosensitive substance  730  as an etching resist to remove a portion of the copper foil layer  727  of the outermost layer, corresponding in position to the circuit pattern of the photosensitive substance  730 . 
         [0109]    After the function of the photosensitive substance  730  is completed, the photosensitive substance is removed through a stripping process as shown in  FIG. 7   l . Thereby, it is possible to mount the chip package on a surface of the internal layer of the substrate. 
         [0110]      FIGS. 8   a  to  8   m  are sectional views illustrating the fabrication of a PCB having a chip package mounted thereon according to another embodiment of the present invention. 
         [0111]    Referring to  FIG. 8   a , a circuit substrate  810  acting as a core is provided. The circuit substrate  810  is made of an insulating material, and comprises an insulating layer  811 , having a predetermined thickness, and copper foil layers  812 ,  813  positioned on upper and lower sides of the insulating layer  811 . Furthermore, a plurality of through holes  814  is formed through the circuit substrate  810  to connect circuits on both sides of the circuit substrate to each other. 
         [0112]    With reference to  FIGS. 8   b  to  8   d , photosensitive substances  821 ,  822  are applied on the copper foil layers  812 ,  813  of the circuit substrate  810 . Subsequently, circuit patterns are formed on the photosensitive substances  821 ,  822  through a photolithography process, and other circuit patterns are then formed on the copper foil layers  812 ,  813  using the photosensitive substances  821 ,  822  as an etching resist. Thereby, the circuit patterns are formed on a portion of the internal layers  812 ,  813 , corresponding in position to an area in which the chip package is to be mounted, and another portion of the internal layers. 
         [0113]    As shown in  FIG. 8   e , the photosensitive substances  821 ,  822  are removed through a stripping process. 
         [0114]    As shown in  FIG. 8   f , photosensitive substances  823 ,  824  are applied to achieve the selective application of an etching resistor  825 . 
         [0115]    As shown in  FIG. 8   g , the photosensitive substance  823  is exposed and developed to expose a portion on which the etching resistor  825  is to be applied. 
         [0116]    As shown in  FIG. 8   h , after the etching resistor  825  is applied, the photosensitive substances  823 ,  824  are removed through a stripping process. At this stage, it is preferable that the application of the etching resistor  825  be conducted using a plating process. 
         [0117]    As shown in  FIG. 8   i , a plurality of insulating layers  826 ,  827  is further laminated. In this regard, a portion of the insulating layer  826 , in which the chip package is to be mounted, is already removed. Accordingly, it is unnecessary to etch that portion of the insulating layer  826  to mount the chip package in the insulating layer. 
         [0118]    As shown in  FIG. 8   j , electroless and electrolytic copper plating processes are conducted to form plating layers  828 ,  829 . 
         [0119]    As shown in  FIG. 8   k , photosensitive substances  830 ,  831  are applied on the outermost layers  828 ,  829  to form circuit patterns on the plating layers  828 ,  829 . 
         [0120]    As shown in  FIG. 81 , the photosensitive substance  830  is exposed and developed to be removed at a portion thereof, which corresponds in position to the circuit patterns of the plating layers, so as to form the circuit patterns on the plating layers  828 ,  829 . At this time, a portion of the photosensitive substance  830 , corresponding in position to an area in which the chip package is to be mounted, is completely removed. 
         [0121]    Furthermore, an etching process is conducted using the photosensitive substance  830  as an etching resist to remove a portion of the copper foil layer  828  of the outermost layer, corresponding in position to the circuit pattern of the photosensitive substance  830 . 
         [0122]    After the function of the photosensitive substance  830  is completed, the photosensitive substance is removed through a stripping process as shown in  FIG. 8   m . Thereby, it is possible to mount the chip package on a surface of the internal layer of the substrate. 
         [0123]    Meanwhile, a process of  FIGS. 9   a  to  9   d  may be further conducted in all the above embodiments of the present invention. 
         [0124]      FIGS. 9   a  to  9   c  are sectional views illustrating the fabrication of a PCB having an integrated circuit chip mounted thereon according to yet another embodiment of the present invention. 
         [0125]    Referring to  FIG. 9   a , a solder resist ink  940  is applied to an entire side of a PCB from which a portion of an insulating layer  931 , in which a chip package is to be mounted, is removed according to the procedures of the preceding embodiments. 
         [0126]    With reference to  FIG. 9   b , a solder resist layer  940 , formed by the solder resist ink applied to the PCB, is removed at a portion thereof, which corresponds in position to solders  951  of the chip package or shown in  FIG. 9   d.    
         [0127]    As shown in  FIG. 9   c , an electric conductive material or a nonconductive material  942  may be applied on a copper foil layer  912  partially exposed by removing a portion of the solder resist layer  940  of the PCB so as to prevent oxidation of the copper foil layer and to improve adhesion strength between parts to be mounted on the PCB and the copper foil layer. At this stage, it is preferable that the application of the material be conducted through gold plating. 
         [0128]    As shown in  FIG. 9   d , the chip package  950  is mounted using a flip chip on the PCB. 
         [0129]    The fabrication of a PCB of the present invention has been described in an illustrative manner, and it is to be understood that the terminology used is intended to be in the nature of description rather than of limitation. Many modifications and variations of the present invention are possible in light of the above teachings. Therefore, it is to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described. 
         [0130]    As described above, the present invention is advantageous in that since a finished chip package is mounted on a PCB, the required degree of cleanliness is reduced, eliminating the necessity for additional devices and costs. 
         [0131]    Another advantage of the present invention is that since it is possible to position a chip closer to an electric power source layer, the occurrence of noise caused by interference can be reduced. 
         [0132]    Still another advantage of the present invention is that connection is feasible through side walls of the package as well as through the bottom of the package because of the use of a lead frame, and thus, it is possible to provide many channels for signal connection.

Technology Classification (CPC): 8