Patent Abstract:
A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates to a dual resistance heater for phase change devices and to the manufacturing method thereof. In particular, the invention relates to a heater for phase change memory devices.  
         [0003]     2. Description of the Related Art  
         [0004]     Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element utilizes a phase change material that is electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. The state of the phase change materials is also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event, as that value represents a phase or physical state of the material (e.g., crystalline or amorphous). The state is unaffected by removing electrical power.  
         [0005]     Turning to  FIG. 1 , an embodiment of a memory  100  is illustrated. Memory  100  includes a n×n array of memory cells  111 - 119 , wherein memory cells  111 - 119  each include a select device  120  and a memory element  130 .  
         [0006]     Memory elements  130  comprise a phase change material, thus memory  100  may be referred to as a phase change memory. A phase change material is a material having electrical properties (e.g., resistance, capacitance, etc.) that may be changed through the application of energy such as, for example, heat, light, voltage potential, or electrical current. Examples of a phase change material include a chalcogenide material.  
         [0007]     A chalcogenide alloy may be used in a memory element or in an electronic switch. A chalcogenide material is a material that includes at least one element from column VI of the periodic table or is a material that includes one or more of the chalcogenic elements, e.g., any of the elements of tellurium, sulfur, or selenium.  
         [0008]     Memory  100  includes column lines  141 - 143  and row lines  151 - 153  to select a particular memory cell of the array during a write or read operation. Column lines  141 - 143  and row lines  151 - 153  may also be referred to as address lines since these lines may be used to address memory cells  111 - 119  during programming or reading. Column lines  141 - 143  may also be referred to as bit lines and row lines  151 - 153  may also be referred to as word lines.  
         [0009]     Memory elements  130  are connected to row lines  151 - 153  and are coupled to column lines  141 - 143  via select device  120 . While one select device  120  is depicted, more select devices may also be used. Therefore, when a particular memory cell (e.g., memory cell  115 ) is selected, voltage potentials may be applied to the memory cell&#39;s associated column line (e.g.,  142 ) and row line (e.g.,  152 ) to apply a voltage potential across the memory cell.  
         [0010]     Series connected select device  120  is used to access memory element  130  during programming or reading of memory element  130 . The select device  120  is an ovonic threshold switch that is made of a chalcogenide alloy that does not exhibit an amorphous to crystalline phase change and which undergoes rapid, electric field initiated change in electrical conductivity that persists only so long as a holding voltage is present. Select device  120  operates as a switch that is either “off” or “on” depending on the amount of voltage potential applied across the memory cell, and more particularly whether the current through the select device exceeds its threshold current or voltage, which then triggers the device into the on state. The off state is a substantially electrically nonconductive state and the on state is a substantially conductive state, with less resistance than the off state. In the on state, the voltage across the select device is equal to its holding voltage V H  plus IxRon, where Ron is the dynamic resistance from V H . For example, select device  120  has a threshold voltage and, if a voltage potential less than the threshold voltage of a select device  120  is applied across select device  120 , then the select device  120  remains “off” or in a relatively high resistive state so that little or no electrical current passes through the memory cell and most of the voltage drop from selected row to selected column is across the select device. Alternatively, if a voltage potential greater than the threshold voltage of select device  120  is applied across select device  120 , then the select device  120  “turns on,” i.e., operates in a relatively low resistive state so that electrical current passes through the memory cell. In other words, select device  120  is in a substantially electrically nonconductive state if less than a predetermined voltage potential, e.g., the threshold voltage, is applied across select device  120 . Select device  120  is in a substantially conductive state if greater than the predetermined voltage potential is applied across select device  120 . Select device  120  may also be referred to as an access device, an isolation device, or a switch.  
         [0011]     Here, each select device  120  comprises a switching material such as, for example, a chalcogenide alloy, and may be referred to as an ovonic threshold switch, or simply an ovonic switch. The switching material of select device  120  is a material in a substantially amorphous state positioned between two electrodes that may be repeatedly and reversibly switched between a higher resistance “off” state (e.g., greater than about ten megaOhms) and a relatively lower resistance “on” state (e.g., about one thousand Ohms in series with V H ) by application of a predetermined electrical current or voltage potential. Here, each select device  120  is a two terminal device that has a current-voltage (I-V) characteristic similar to a phase change memory element that is in the amorphous state. However, unlike a phase change memory element, the switching material of select device  120  does not change phase. That is, the switching material of select device  120  is not a programmable material, and, as a result, select device  120  is not a memory device capable of storing information. For example, the switching material of select device  120  remains permanently amorphous and the I-V characteristic remains the same throughout the operating life. A representative example of I-V characteristics of select device  120  is shown in  FIG. 2 .  
         [0012]     In  FIG. 2 , in the low voltage or low electric field mode, i.e., where the voltage applied across select device  120  is less than a threshold voltage (labeled V TH ), select device  120  is “off” or nonconducting, and exhibits a relatively high resistance, e.g., greater than about 10 megaOhms. Select device  120  remains in the off state until a sufficient voltage, e.g., V TH , is applied, or a sufficient current is applied, e.g., I TH , that switches select device  120  to a conductive, relatively low resistance on state. After a voltage potential greater than about V TH  is applied across select device  120 , the voltage potential across select device  120  drops (“snapback”) to a holding voltage potential, labeled V H . Snapback refers to the voltage difference between V TH  and V H  of a select device.  
         [0013]     In the on state, the voltage potential across select device  120  remains close to the holding voltage V H  as current passing through select device  120  is increased. Select device  120  remains on until the current through select device  120  drops below a holding current, labeled I H . Below this value, select device  120  turns off and returns to a relatively high resistance, nonconductive off state until the VTH and ITH are exceeded again.  
         [0014]     In known phase change memory cells, there is the problem that relatively high levels of currents are required to switch the phase change material of the memory elements.  
         [0015]     Another disadvantage of known change memory cells resides in the poor adhesion of the chalcogenide material to the underlying heater, resulting in some instances in a delamination of patterned electrode stacks.  
         [0016]     The same problem affects all devices including a phase change material layer overlying a resistive heater.  
       BRIEF SUMMARY OF THE INVENTION  
       [0017]     In one embodiment, the present invention provides a device including a phase change layer that requires less current for causing switching of the phase change layer. In particular, the device comprises a phase change material region and a heater, the heater having a surface region in contact with said phase change material region, wherein the surface region has a higher resistance than that of another portion of said heater.  
         [0018]     In another embodiment, a method for manufacturing a phase change device is described, the method comprising forming a heater and increasing the resistance of a surface of the heater by ion implantation of silicon or oxygen ion. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)  
       [0019]     For the understanding of the present invention, preferred embodiments are now described, purely as a non-limitative example, with reference to the enclosed drawings, wherein:  
         [0020]      FIG. 1  is a schematic diagram illustrating a phase change memory;  
         [0021]      FIG. 2  is a diagram illustrating a current-voltage characteristic of an access device of the phase change memory of  FIG. 1 ;  
         [0022]      FIG. 3  is an enlarged cross-sectional view of one embodiment of the present invention;  
         [0023]      FIGS. 4-13  are enlarged cross-sectional views of the embodiment shown in  FIG. 3  at subsequent stages of manufacture in accordance with one embodiment of the present invention;  
         [0024]      FIG. 14  is a schematic system depiction of one embodiment of the present invention;  
         [0025]      FIGS. 15-21  are enlarged cross-sectional views of another embodiment of the present invention at subsequent stages of manufacture. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Referring to  FIG. 3 , a phase change memory cell, such as a cell  111 - 119  in  FIG. 1 , is formed in a substrate  10 . Over the substrate  10  various interconnections and transistor features are formed. An interlayer dielectric  12  separates those features from the features provided above the interlayer dielectric  12 . A conductor  14  extends above the interlayer dielectric  12  and act as a row line  151 - 153  ( FIG. 1 ). At the top, a conductor  36  extends generally transversely to the electrode  14  and acts as a column line  141 - 143  ( FIG. 1 ).  
         [0027]     A dielectric layer  16  has a pore formed therein and the pore accommodates a spacer  22 , a lance heater  24 , and a phase change memory material  28  which, together with the heater  24 , form a phase change memory element  130  ( FIG. 1 ). A region  26  of the heater  24  has a higher resistance than the region  27 . Thus, the heater  24  is a dual resistance heater made up of the region  26  and the region  27 , each region having a different resistance, although both regions may be formed of the same starting material. The region  27  has a lower resistance, so it creates a lower voltage drop, reducing the power consumed by the heater  24  and, thus, the cell as a whole.  
         [0028]     An ovonic threshold device  120  ( FIG. 1 ) is formed above the phase change memory material  28  and acts as a selection or threshold device for the underlying memory element  130 . The ovonic threshold device  120  is formed in a dielectric layer  18 , e.g., of nitride, and in a dielectric layer  20 , e.g., oxide. The threshold device  120  includes a lower electrode  30 , an upper electrode  34 , a surrounding dielectric layer  38 , and a switching material  32 . The switching material  32  may, like the memory material  28 , be a chalcogenide. However, generally, the switching material  32  does not change phase.  
         [0029]     The formation of the cell shown in  FIG. 3  begins with the formation of a contact or lance opening  17  in the dielectric  16 , as shown in  FIG. 4 . The dielectric  16  is, e.g., of oxide.  
         [0030]     Next, as shown in  FIG. 5 , a sidewall spacer  22  is formed in the opening  17 . The sidewall spacer  22  may be formed by conventional techniques, including the deposition of a layer of nitride followed by anisotropic etching.  
         [0031]     Then,  FIG. 6 , a heater  24  is deposited to fill the opening  17 . The heater  24  may, for example, be titanium nitride.  
         [0032]     The heater  24  is recessed to create the recess  25  shown in  FIG. 7 . The heater  24  is planarized prior to being recessed. The recess  25  may be created by dry or wet etching processes known as dip backs or etch backs. Thereafter, the exposed structure is subjected to an ion implantation indicated as A in  FIG. 7 . E.g., the ion implantation may be an implantation of silicon at 20 keV and 10 15  atoms per square centimeter.  
         [0033]     A result of the implant is to convert at least an upper region  26  of the heater  24  into a higher resistance state. For example, where the heater  24  is titanium nitride, the upper region  26 , shown in  FIG. 8 , becomes titanium silicon nitride as a result of an implant followed by an effective anneal while the remaining region  27  remains titanium nitride. The titanium silicon nitride in the region  26  has a higher resistance than the underlying material in the region  27 .  
         [0034]     Thus,  FIG. 8 , the upper region  26  of the heater  24  has a higher resistance than the region  27 . Preferably, the upper region  26  is a very small portion of the overall heater  24 . In other words, the heater  24  is much bigger in thickness and volume than the region  26 , the region  26  only constituting a few surface layers.  
         [0035]     As another alternative, the resistance of the region  26  may be increased by an oxygen plasma treatment. In such case, the arrows A represent oxygen plasma which reacts with the heater  24  to form an oxide thereof. That oxide, in the region  26 , has higher resistance than the underlying region  27  of the heater  24 .  
         [0036]     In the case of an implant to increase the resistance of the region  26 , a separate anneal step may not be necessary. For example, ensuing steps that involve temperature processing of 250° C. may be sufficient to activate the implanted species.  
         [0037]     As shown in  FIG. 9 , a chalcogenide material  28  is then deposited into the pore  17  with the heater  24 . The memory material  28  acts as the phase change memory material for the cell. The implantation of  FIG. 7  also improves adhesion of dielectric layers, such as spacer  22  and layer  16 , to the material  28 . The memory material  28  is then planarized as shown in  FIG. 10 .  
         [0038]     In  FIG. 11 , the ovonic threshold switch  120  ( FIG. 1 ) is then formed over the memory element  130 . An electrode  30  is deposited, followed by the deposition of a chalcogenide material  32  that does not change phase, in turn followed by an upper electrode  34 . The sandwich of the upper electrode  34 , chalcogenide material  32 , and lower electrode  30  is then patterned as indicated in  FIG. 12 .  
         [0039]     The patterned structure is covered with a passivation layer  18  as shown in  FIG. 13 . The passivation layer  18  may, for example, be a nitride. Thus, the passivation layer  18  covers the underlying portion of the dielectric  16  and the threshold device  120 .  
         [0040]     Thereafter, a dielectric  20  is deposited as shown in  FIG. 3 . The dielectric  20  is trenched and an upper electrode  36  is formed in the trench. The upper electrode may act as a column line  141 - 143  ( FIG. 1 ).  
         [0041]     Memory material  28  is a phase change, programmable material capable of being programmed into one of at least two memory states by applying a current to memory material  28  to alter the phase of memory material  28  between a substantially crystalline state and a substantially amorphous state, wherein a resistance of memory material  28  in the substantially amorphous state is greater than the resistance of memory material  28  in the substantially crystalline state.  
         [0042]     Programming of memory material  28  to alter the state or phase of the material is accomplished by applying voltage potentials to the conductors  14  and  36 , thereby generating a voltage potential across select device  120  and memory element  130 . When the voltage potential is greater than the threshold voltage of select device  120  and memory element  130 , then an electrical current flows through memory material  28  in response to the applied voltage potential, and results in heating of memory material  28 .  
         [0043]     This heating alters the memory state or phase of memory material  28 . Altering the phase or state of memory material  28  alters the electrical characteristic of memory material  28 , e.g., the resistance of the material is altered by altering the phase of the memory material  28 . Memory material  28  is referred to as a programmable resistive material.  
         [0044]     In the “reset” state, memory material  28  is in an amorphous or semi-amorphous state and in the “set” state, memory material  28  is in a crystalline or semi-crystalline state. The resistance of memory material  28  in the amorphous or semi-amorphous state is greater than the resistance of memory material  28  in the crystalline or semi-crystalline state. It is to be appreciated that the association of reset and set with amorphous and crystalline states, respectively, is a convention and that at least an opposite convention may be adopted.  
         [0045]     Using electrical current, memory material  28  is heated to a relatively higher temperature to amorphosize memory material  28  and “reset” memory material  28  (e.g., program memory material  28  to a logic “0” value). Heating the volume of memory material  28  to a relatively lower crystallization temperature crystallizes memory material  28  and “sets” memory material  28  (e.g., program memory material  28  to a logic “1” value). Various resistances of memory material  28  may be achieved to store information by varying the amount of current flow and duration through the volume of memory material  28 .  
         [0046]     The composition of switching material  32  may comprise a Si concentration of about 14%, a Te concentration of about 39%, an As concentration of about 37%, a Ge concentration of about 9%, and an In concentration of about 1%. In another example, the composition of switching material  32  may comprise a Si concentration of about 14%, a Te concentration of about 39%, an As concentration of about 37%, a Ge concentration of about 9%, and a P concentration of about 1%. In these examples, the percentages are atomic percentages which total 100% of the atoms of the constituent elements.  
         [0047]     In another embodiment, a composition for switching material  32  includes an alloy of arsenic (As), tellurium (Te), sulfur (S), germanium (Ge), selenium (Se), and antimony (Sb) with respective atomic percentages of 10%, 21%, 2%, 15%, 50%, and 2%.  
         [0048]     In other embodiments, switching material  32  includes Si, Te, As, Ge, sulfur (S), and selenium (Se). As an example, the composition of switching material  32  comprises a Si concentration of about 5%, a Te concentration of about 34%, an As concentration of about 28%, a Ge concentration of about 11%, a S concentration of about 21%, and a Se concentration of about 1%.  
         [0049]     The switching material  32  is a thin film material having a thickness ranging from about 20 Å to about 2000 Å. In one embodiment, the thickness of the material  32  ranges from about 100 Å to about 1000 Å. In another embodiment, the thickness of the material  32  is about 300 Å.  
         [0050]     Suitable materials for electrodes  30  and  34  include a thin film of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), carbon (C), silicon carbide (SiC), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), polycrystalline silicon, tantalum nitride (TaN), some combination of these films, or other suitable conductors or resistive conductors compatible with switching material  32 .  
         [0051]     Turning to  FIG. 14 , a portion of a system  500  in accordance with an embodiment of the present invention is described. System  500  may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System  500  may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect.  
         [0052]     System  500  includes a controller  510 , an input/output (I/O) device  520  (e.g., a keypad, display), a memory  530 , and a wireless interface  540  coupled to each other via a bus  550 .  
         [0053]     Controller  510  may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory  530  may be used to store messages transmitted to or by system  500 . Memory  530  may also optionally be used to store instructions that are executed by controller  510  during the operation of system  500 , and may be used to store user data. Memory  530  may be provided by one or more different types of memory. For example, memory  530  may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory  100  discussed herein.  
         [0054]     I/O device  520  may be used by a user to generate a message. System  500  may use wireless interface  540  to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface  540  may include an antenna or a wireless transceiver.  
         [0055]     In accordance with another embodiment of the present invention, the dielectric region surrounding the heater is treated to improve the adhesion properties thereof.  
         [0056]     According to this embodiment, as shown in  FIG. 15 , a second dielectric layer  40  is formed over the dielectric layer  16  and the stack of the dielectric layer  16  and the second dielectric layer  40  is etched to form an opening  42  defining a contact opening structure. The remaining structure of  FIG. 15  is similar to the structure previously described in connection with  FIG. 4 .  
         [0057]     Next,  FIG. 16 , the opening  42  is covered with a sidewall spacer  45 , using known techniques. The spacer  45  is e.g., of nitride.  
         [0058]     Then, as shown in  FIG. 17 , the heater  24  is deposited to completely fill the remaining opening  42  and to cover the top of the second dielectric layer  40 . This structure is then planarized in a timed polish so as to remove a portion of the second dielectric layer  40 , and to polish away the flared region  41  of the spacer  45 , as shown in  FIG. 18 .  
         [0059]     Thereafter, a silicon implant is accomplished as indicated at B in  FIG. 19 . The implant converts the top portion  40   a  of the second dielectric layer  40  to silicon nitride. The implant conditions are the same as those described previously in connection with  FIG. 7 .  
         [0060]     Silicon-implanted nitride has good adhesion to overlying layers including chalcogenide containing layers. Thus, the silicon-implanted nitride layer  40   a  acts as a glue or adhesion layer.  
         [0061]     Moreover, the implanted region  24   b  of the heater  24  is converted to titanium silicon nitride, which has higher resistivity than the non-implanted titanium nitride region  27 . Annealed silicon-implanted titanium nitride, or titanium silicon nitride has a very high adhesion to overlying layers including chalcogenide containing layers.  
         [0062]     Thus, a dual resistance heater  24  is formed at the same time that the top portion  40   a  of the second dielectric layer  40  is modified to make it an effective glue layer. In this embodiment, the top portion  40   a  of the second dielectric layer  40  is substantially planar. In other words, it does not extend into the opening  42  that includes the heater  24 .  
         [0063]     Next, as shown in  FIG. 20 , a chalcogenide layer  46  is deposited, followed by an upper electrode  48 . Then, referring to  FIG. 21 , the upper electrode  48  and the chalcogenide layer  46  are patterned.  
         [0064]     Finally, it is clear that numerous variations and modifications may be made to method and the contact region, the phase change memory cell and process described and illustrated herein, all falling within the scope of the invention as defined in the attached claims.  
         [0065]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.

Technology Classification (CPC): 7