Patent Abstract:
The adjustable lock-in circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable lock-in circuits provide an adjustable initial loop condition closer to the expected loop condition according to a targeted lock-in time. In addition, the initial loop condition is varied by changing the reference voltage level.

Full Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to the field of fast-locking phase-locked loops and more particularly to adjustable lock-in circuit for phase-locked loops.  
       BACKGROUND ART  
       [0002]     Phase-looked loop is a vitally important device. Phase-looked loop is analog and mixed signal building block used extensively in communication, networks, digital systems, consumer electronics, computers, and any other fields that require frequency synthesizing, clock recovery, and synchronization.  
         [0003]     Prior Art  FIG. 1  illustrates a block diagram of a basic architecture of two types of conventional phase-locked loops, which are a conventional phase-locked loop  110  and a conventional fast-locking phase-locked loop  120 . The conventional phase-locked loop  110  typically consists of a phase-frequency detector (or phase detector), a charge-pump, a low-pass filter, and a voltage-controlled oscillator in a loop. Phase-locked loops without any frequency divider in a loop are considered here for simplicity. The phase-frequency detector (or phase detector) is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output signal of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector (or phase detector). Therefore, change in the low-pass filter&#39;s output voltage drives the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.  
         [0004]     In the conventional phase-locked loop  110  of Prior Art  FIG. 1 , lock-in time is defined as the time that is required to attain lock from an initial loop condition. Assuming that the phase-locked loop bandwidth is fixed, the lock-in time is proportional to the difference between the input signal frequency and the initial voltage-controlled oscillator&#39;s frequency as follows:  
           (       ω   in     -     ω   osc       )     2       ω   0   3         
 
 where ω in  is the input signal frequency, ω osc  is the initial voltage-controlled oscillator&#39;s frequency, and ω 0  is the loop bandwidth. The loop bandwidth must be wide enough to obtain a fast lock-in time. But most systems require a fast lock-in time without regard to the input signal frequency, bandwidth, and output phase jitter due to external noise. However, the conventional phase-locked loop  110  shown in Prior Art  FIG. 1  has suffered from slow locking and harmonic locking. Thus, time and power are unnecessarily consumed until the phase-locked loops become locked. In addition, it has taken a vast amount of time to simulate and verify the conventional phase-locked loop  110  before fabrication since the simulation time of phase-locked loop circuits is absolutely proportional to time that is required the phase-locked loops to be locked. This long simulation adds additional cost and serious bottleneck to better design time to market. For these reasons, the conventional phase-locked loop  110  of Prior Art  FIG. 1  is very inefficient to implement in an integrated circuit (IC) or system-on-chip (SOC). 
 
         [0005]     To overcome the drawbacks of the conventional phase-locked loop  110  of Prior Art  FIG. 1 , a conventional fast-locking phase-locked loop  120  of Prior Art  FIG. 1  is illustrated. The conventional fast-locking phase-locked loop  120  consists of a digital phase-frequency detector, a proportional-integral controller  122 , a 10-bit digital-to-analog converter  124 , and a voltage-controlled oscillator. Unfortunately, the conventional fast-locking phase-locked loop is costly, complicated, and inefficient to implement in system-on-chip (SOC) or integrated circuit (IC) because additional proportional-integral controller  122  and the 10-bit digital-to-analog converter  124  take much more chip area, consume much more power, and make the stability analysis very difficult. The complexity increases the number of blocks that need to be designed and verified. The conventional fast-locking phase-locked loop  120  might improve the lock-in time, but definitely results in bad time-to-market, higher cost, larger chip area, much more power consumption, and longer design time.  
         [0006]     Thus, what is desperately needed is a highly cost-effective fast-locking phase-locked loop that can be highly efficiently implemented with a drastic improvement in a very fast lock-in time, lock-in time controllability, adjustable initial condition, performance, cost, chip area, power consumption, stand-by time, and fast design time for much better time-to-market. At the same time, serious harmonic locking problem has to be resolved. The present invention satisfies these needs by providing adjustable lock-in circuits.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention provides five types of the adjustable lock-in circuits for phaselocked loops. The adjustable lock-in circuits simultaneously enable any phase-locked loop to be locked according to a targeted lock-in time. In addition, the output voltage level is varied by changing the reference voltage level. The basic architecture of the adjustable lock-in circuits consists of a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the output voltage reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled.  
         [0008]     Consequently, all adjustable lock-in circuits provide a significant reduction in the difference between the initial loop condition and the locked condition in order to overcome serious drawbacks simultaneously. The lock-in time controllability enables all of the phase-locked loops on the chip to be locked according to schedule. In addition, the present invention has five different embodiments which achieve a drastic improvement in a very fast lock-in time, lock-in time controllability, adjustable initial condition, performance, cost, chip area, power consumption, stand-by time, and design time.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The accompanying drawings, which are incorporated in and form a part of this specification, illustrate five embodiments of the invention and, together with the description, serve to explain the principles of the invention:  
         [0010]     Prior Art  FIG. 1  illustrates a block diagram of two types of conventional phase-locked loops.  
         [0011]      FIG. 2  illustrates a block diagram of two types of adjustable lock-in circuits for phase-locked loops in accordance with the present invention.  
         [0012]      FIG. 3  illustrates a circuit diagram of a basic adjustable lock-in circuit according to the present invention.  
         [0013]      FIG. 4  illustrates a circuit diagram of an adjustable lock-in circuit in accordance with the present invention.  
         [0014]      FIG. 5  illustrates a circuit diagram of a dual adjustable lock-in circuit according to the present invention.  
         [0015]      FIG. 6  illustrates a circuit diagram of a p-type adjustable lock-in circuit in accordance with the present invention.  
         [0016]      FIG. 7  illustrates a circuit diagram of a p-type dual adjustable lock-in circuit according to the present invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]     In the following detailed description of the present invention, five types of the adjustable lock-in circuits, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, CMOS digital gates, components, and metal-oxide-semiconductor field-effect transistor (MOSFET) device physics have not been described in detail so as not to unnecessarily obscure aspects of the present invention.  
         [0018]      FIG. 2  illustrates a block diagram of two types of the adjustable lock-in circuits for phase-locked loops in accordance with the present invention. One type of the adjustable lock-in circuit is applied for phase-locked loops including a filter  216  connected between V C  and ground, as seen in the phase-locked loop  210  shown in  FIG. 2 . The other type of the adjustable lock-in circuit called “p-type adjustable lock-in circuit” is applied for phase-locked loops including a filter  226  connected between V DD  and V C , as seen in the phase-locked loop  220  shown in  FIG. 2 . To reduce the difference between the initial loop condition and the locked condition, the outputs of the adjustable lock-in circuit  214  and the p-type adjustable lock-in circuit  224  are coupled to the outputs of the filter  216  and the filter  226 , respectively, as shown in  FIG. 2 . The phase-locked loop  210  excluding the adjustable lock-in circuit  214  represents all types of phase-locked loops including a filter  216  connected between V C  and ground without regard to the types of phase-locked loops because the applications of the adjustable lock-in circuit  214  are independent of architectures and types of phase-locked loops. The phase-locked loop  220  excluding the p-type adjustable lock-in circuit  224  represents all types of phase-locked loops including a filter  226  connected between V DD  and V C  without regard to the types of phase-locked loops because the applications of the p-type adjustable lock-in circuit  224  are independent of architectures and types of phase-locked loops. The filters  216  and  226  are low-pass filters. If these filters are multiple-order low-pass filters, then they will be approximated to the first-order filter with neglecting resistor in the filter for simplicity.  
         [0019]      FIG. 3  illustrates a basic adjustable lock-in circuit according to the present invention. This basic adjustable lock-in circuit  300  does not have power-down mode in order to show the fundamental concept of the invention clearly. The basic adjustable lock-in circuit  300  is a feedback circuit that consists of a lower-voltage sensing comparator  302 , a higher-voltage sensing comparator  304 , two reference voltages, two stacked PMOS transistors  306  and  308 , two stacked NMOS transistors  326  and  328 , and a feedback line  310 . The gate terminal of a PMOS transistor  308  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  326  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.).  
         [0020]     It is assumed that the output of the basic adjustable lock-in circuit  300  is at ground. Since the lower-voltage sensing comparator  302  initially senses a voltage less than the lower reference voltage, the output voltage of the lower-voltage sensing comparator  302  is low enough to turn on the PMOS transistor  306 . At the same time, the output voltage of the higher-voltage sensing comparator  304  is low enough to turn off the NMOS transistor  328 . Thus, the PMOS transistor  306  provides a current (i.e., I p ) to the output until the output voltage (i.e., V C ) goes up to the lower reference voltage. The time to reach the expected voltage level at the filter connected between V C  and ground is as follows:  
         Δ   ⁢           ⁢   t     =         V   REFL     ⁢     C   P         I   P           
 
 where V REFL  is the lower reference voltage and C P  is the value of the capacitor in the filter. Thus, the lock-in time of the phaselocked loops including the filter connected between V C  and ground is approximately given by  
             (       ω   in     -     ω   REFL       )     2       ω   0   3       +         V   REFL     ⁢     C   P         I   P           
 
 where ω in  is the input signal frequency, ω REFL  is the voltage-controlled oscillator&#39;s frequency for V C =V REFL , and ω 0  is the loop bandwidth. This lock-in time is varied by the current I P  depending on the size of the PMOS transistor  306 . 
 
         [0021]     Now it is differently assumed that the output of the basic adjustable lock-in circuit  300  is at power supply. Since the higher-voltage sensing comparator  304  initially senses a voltage greater than the higher reference voltage, the output voltage of the higher-voltage sensing comparator  304  is high enough to turn on the NMOS transistor  328 . At the same time, the output voltage of the lower-voltage sensing comparator  302  is high enough to turn off the PMOS transistor  306 . Thus, the NMOS transistor  328  provides a current (i.e., I N ) to the output until the output voltage (i.e., V C ) goes down to the higher reference voltage. The time to reach the expected voltage level at the filter connected between V C  and power supply is as follows:  
         Δ   ⁢           ⁢   t     =         (       V   DD     -     V     REFH   )         )     ⁢     C   P         I   N           
 
 where V REFH  is the higher reference voltage and C P  is the value of the capacitor in the filter. Thus, the lock-in time of the phase-locked loops including the filter connected between V C  and power supply is approximately given by  
             (       ω   in     -     ω   REFH       )     2       ω   0   3       +         (       V   DD     -     V   REFH       )     ⁢     C   P         I   N           
 
 where ω in  is the input signal frequency, ω REFH  is the voltage-controlled oscillator&#39;s frequency for V C =V REFH , and ω 0  is the loop bandwidth. This lock-in time is varied by the current I N  depending on the size of the NMOS transistor  328 . 
 
         [0022]     In design of the basic adjustable lock-in circuit of  FIG. 3 , it is also desirable to use a value for the lower reference voltage, V REFL , less than V′ C  and a value for the higher reference voltage, V REFH , greater than V′ C . V′ C  is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal&#39;s frequency.  
         [0023]      FIG. 4  illustrates an adjustable lock-in circuit  400  according to the present invention. A power-down input voltage, V PD , is defined as the input voltage for power-down mode. The power-down enable system is in power-down mode when V PD  is V DD  and it is in normal mode when V PD  is zero. The adjustable lock-in circuit  400  is a feedback circuit that consists of a lower-voltage sensing comparator  402 , a reference voltage, two stacked PMOS transistors  406  and  408 , two stacked NMOS transistors  426  and  428 , a feedback line  410 , and a power-down NMOS transistor  442 . In addition, the gate terminal of a PMOS transistor  408  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  426  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Furthermore, the gate terminal of a NMOS transistor  428  is shorted and thus no current flows into the drains of the NMOS transistors  426  and  428 .  
         [0024]     The circuit mode changes from power-down mode to normal mode in  FIG. 4 . Since the lower-voltage sensing comparator  402  initially senses a voltage less than the lower reference voltage, the output voltage of the lower-voltage sensing comparator  402  is low enough to turn on the PMOS transistor  406 . The PMOS transistor  406  generates a current (i.e., I P ) to the output until the output voltage (i.e., V C ) goes up to the lower reference voltage. Furthermore, the lock-in time of the phase-locked loops including the filter connected between V C  and ground is approximately given by  
             (       ω   in     -     ω   REFL       )     2       ω   0   3       +         V   REFL     ⁢     C   P         I   P           
 
 where ω in  is the input signal frequency, ω REFL  is the voltage-controlled oscillator&#39;s frequency for V C =V REFL , and ω 0  is the loop bandwidth. Also, V REFL  is the lower voltage reference and C P  is the value of the capacitor in the filter. The lock-in time is varied by the current I P  depending on the size of the PMOS transistor  406 . 
 
         [0025]     In design of the adjustable lock-in circuit of  FIG. 4 , it is also desirable to use a value for the lower reference voltage, V REFL , less than V′ C . V′ C  is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal&#39;s frequency. The adjustable lock-in circuit  400  is used for all types of phase-locked loops including the filter connected between V C  and ground.  
         [0026]     Since the power-down NMOS transistor  442  is on during power-down mode, it provides an output pull-down path to ground. Thus, V C  of the adjustable lock-in circuit  400  is zero so that no current flows into the circuits during power-down mode.  
         [0027]      FIG. 5  illustrates a dual adjustable lock-in circuit  500  in accordance with the present invention. The dual adjustable lock-in circuit  500  is a modification of the circuit described in  FIG. 4 . The gate terminal of a PMOS transistor  508  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  526  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Furthermore, compared to  FIG. 4 , the first difference to note is that the higher-voltage sensing comparator  504  is added into  FIG. 5  in order to provide the higher-voltage sensing function. The second difference to note is that the output of the higher-voltage sensing comparator  504  is connected to the gate terminal of a NMOS transistor  528 . Therefore, the dual adjustable lock-in circuit  500  is able to sense the lower-voltage as well as the higher-voltage while the adjustable lock-in circuit  400  is able to sense only the lower-voltage.  
         [0028]     No current flows into the drains of the NMOS transistors  526  and  528  assuming V C &lt;V REFH  where V REFH  is the higher reference voltage for the higher-voltage sensing comparator  504 . If V C  is greater than V REFH , the gate voltage of the NMOS transistor  528  is V DD . As a result, a current flows into the drains of the NMOS transistors  526  and  528  until V C  goes down to V REFH .  
         [0029]     In design of the dual adjustable lock-in circuit of  FIG. 5 , it is also desirable to use a value for the lower reference voltage (i.e., V REFL ) less than V′ C  and a value for the higher reference voltage (i.e., V REFH ) greater than V′ C . V′ C  is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal&#39;s frequency. The dual adjustable lock-in circuit  500  is used for all types of phase-locked loops including the filter connected between V C  and ground. Zero dc volt at V C  ensures that no current flows into the circuits during power-down mode.  
         [0030]      FIG. 6  illustrates a p-type adjustable lock-in circuit  600  according to the present invention. The power-down input voltage, V PD , is defined as the input voltage for the p-type power-down mode as well as for the power-down mode. The p-type power-down enable system is in power-down mode when V PD  is V DD  and it is in normal mode when V PD  is zero. The p-type adjustable lock-in circuit  600  is a feedback circuit that consists of a higher-voltage sensing comparator  604 , a reference voltage, two stacked PMOS transistors  606  and  608 , two stacked NMOS transistors  626  and  628 , a feedback line  610 , a power-down inverter  614 , and a power-down PMOS transistor  642 . In addition, the gate terminal of a PMOS transistor  608  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  626  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Furthermore, since the PMOS transistor  606  is turned off, no current flows out of the drains of the PMOS transistors  606  and  608 .  
         [0031]     The circuit mode changes from p-type power-down mode to normal mode in  FIG. 6 . Since the higher-voltage sensing comparator  604  initially senses a voltage greater than the higher reference voltage (i.e., V REFH ), the output voltage of the higher-voltage sensing comparator  604  is high enough to turn on the NMOS transistor  628 . The NMOS transistor  628  generates a current (i.e., I N ) to the output until the output voltage (i.e., V C ) goes down to the higher reference voltage (i.e., V REFH ). Thus, the lock-in time of the phase-locked loops including the filter connected between V C  and power supply is approximately given by  
             (       ω   in     -     ω   REFH       )     2       ω   0   3       +         (       V   DD     -     V   REFH       )     ⁢     C   P         I   N           
 
 where ω in  is the input signal frequency, ω REFH  is the voltage-controlled oscillator&#39;s frequency for V C =V REFH , and ω 0  is the loop bandwidth. Also, C P  is the value of the capacitor in the filter and V REFH  is the higher reference voltage. The lock-in time is varied by the current I N  depending on the size of the NMOS transistor  628 . 
 
         [0032]     In design of the p-type adjustable lock-in circuit of  FIG. 6 , it is also desirable to use a value for the higher reference voltage (i.e., V REFH ) greater than V′ C . V′ C  is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal&#39;s frequency. The p-type adjustable lock-in circuit  600  is used for all types of phase-locked loops including the filter connected between V C  and power supply.  
         [0033]     The output voltage of the power-down inverter  614 , V PDB , is zero during power-down mode. As a result, the power-down PMOS transistor  642  is turned on and thus provides an output pull-up path to V DD . Therefore, V C  of the p-type adjustable lock-in circuit  600  is V DD  so that no current flows into the circuits during power-down mode. On the contrary, it was stated earlier that V C  must be zero when power-down mode occurs in  FIG. 4  and  FIG. 5 .  
         [0034]      FIG. 7  illustrates a p-type dual adjustable lock-in circuit  700  in accordance with the present invention. The p-type dual adjustable lock-in circuit  700  is a modification of the circuit described in  FIG. 6 . The gate terminal of a PMOS transistor  708  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  726  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Compared to  FIG. 6 , the first difference to note here is that the lower-voltage sensing comparator  702  is added into  FIG. 7  in order to sense the lower-voltage. The second difference to note here is that the output of the lower-voltage sensing comparator  702  is connected to the gate terminal of the PMOS transistor  706 . The p-type dual adjustable lock-in circuit  700  is able to sense the lower-voltage as well as the higher voltage while the p-type adjustable lock-in circuit  600  is able to sense only the higher voltage.  
         [0035]     No current flows out of the drains of the PMOS transistors  706  and  708  if V C  is greater than the lower reference voltage (i.e., V REFL ). If V C  is less than V REFL , the PMOS transistor  706  is turned on until V C  goes up to V REFL .  
         [0036]     In design of the p-type dual adjustable lock-in circuit of  FIG. 7 , it is also desirable to use a value for the higher reference voltage (i.e., V REFH ) greater than V′ C  and a value for the lower reference voltage (i.e., V REFL ) less than V′ C . V′ C  is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal&#39;s frequency. The p-type dual adjustable lock-in circuit  700  is used for all types of phase-locked loops including the filter connected between V C  and power supply. V C =V DD  in the p-type dual adjustable lock-in circuit  700  ensures that no current flows into the circuits during power-down mode.  
         [0037]     In summary, the five adjustable lock-in circuits of the present invention simply control how fast the phase-locked loops become locked from an adjustable initial condition. Also, they provide a solution for harmonic locking problem. Furthermore, three adjustable lock-in circuits  300 ,  500 , and  700  are highly effective for LC oscillator which has a very narrow tuning range. In addition, the initial loop condition is varied by changing the value of reference voltage. The reference voltage is programmable to provide any expected voltage level for different applications. Two approaches for realizing the programmable reference voltages are as follows: 1. The reference voltages are outputs of any digital-to-analog converter whose digital data inputs are programmed. 2. The reference voltages are based on selecting taps of a segmented resistor string by a digital circuit that is coupled to the segmented resistor string. The digital circuit consists of the switch (e.g., multiplexer, transmission-gate, MOS transistor) network that is connected in a tree-like decoder or it consists of a decoder and switches. The digital inputs of the digital circuit are programmed. Furthermore, the CMOS process variations usually must be considered so that the proper value of the reference voltage is chosen for all the adjustable lock-in circuits  300 ,  400 ,  500 ,  600 , and  700 . Each bulk of two stacked PMOS transistors can be connected to its own N-well to obtain better immunity from substrate noise in all adjustable lock-in circuits. The balance between PMOS output resistance and NMOS output resistance must be considered to obtain high output resistance.  
         [0038]     The adjustable lock-in circuit  214  shown in  FIG. 2  represents the basic adjustable lock-in circuit  300 , the adjustable lock-in circuit  400 , and the dual adjustable lock-in circuit  500 , as shown in  FIG. 3 ,  FIG. 4 , and  FIG. 5 , respectively. Also, the p-type adjustable lock-in circuit  224  shown in  FIG. 2  represents the basic adjustable lock-in circuit  300 , the p-type adjustable lock-in circuit  600  and the p-type dual adjustable lock-in circuit  700 , as shown in  FIG. 3 ,  FIG. 6 , and  FIG. 7 , respectively. It is noted that SPICE is used for the simulation of phase-locked loops. The conventional phase-locked loop  110  and the phase-locked loop  210  including the basic adjustable lock-in circuit  300  of the invention are simulated using the same components. As a result, the total simulation time of the conventional phase-locked loop  110  is 20 hours and that of the phase-locked loop  210  is 1.9 hours. This improvement can be accomplished by simply inserting a proper one of the five adjustable lock-in circuits into any conventional phase-locked loop, and the simulation time can be reduced by a factor of 10. So far, it should be noted that the same time step has been used for the SPICE simulation in order to accurately measure and compare the simulation time of all circuits.  
         [0039]     All the adjustable lock-in circuits of the present invention are very efficient to implement in system-on-chip (SOC) or integrated circuit (IC). The present invention provides five different embodiments which achieve a drastic improvement in a very fast lock-in time, lock-in time controllability, adjustable initial condition, performance, time-to-market, power consumption, stand-by time, cost, chip area, and design time. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as being limited by such embodiments, but rather construed according to the claims below.

Technology Classification (CPC): 8