Patent Abstract:
The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Full Description:
RELATED APPLICATION INFORMATION 
     The present application is a continuation application of U.S. application Ser. No. 10/163,785, filed Jun. 5, 2002, now U.S. Pat. No. 6,671,212, issued on Dec. 30, 2003, entitled, “Method and Apparatus For Data Inversion in Memory Device”, and Ser. No. 10/681,014 filed Oct. 7, 2003, now U.S. Pat. No. 6,826,095, issued on Nov. 30, 2004 the disclosures of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of data writing and reading. 
     2. Background Art 
     Digital data is stored in memory devices as ones and zeros. Data is transferred into and out of a memory device via a conductive path called a “pin”. Data is written into the memory as a string of high and low signals that represent the ones and zeros. Each time there is a transition between the low and high signals, the efficiency of the memory device is reduced. However, because data is somewhat random, there is no easy way to control the data to reduce the number of transitions. This problem can be understood by a review of writing to and from memory devices. 
       FIG. 1  is a block diagram of a data source and a data receiver. The data source  100  communicates with the data receiver  102  via a bus  101 . Data is transferred in blocks of 8 bits called “bytes”. Each byte is sent to the data receiver  102  in parallel as 8 data signals on 8 lines with each signal line being high or low depending on the data being transmitted. For example, if a data value of one is sent, the bus line is at a high state. If the next signal sent is a zero, the bus line must be brought down to a low state to represent the new data. Then, if the succeeding signal is a one, the bus line must be again brought up to the high value. These changes of state are known as data transitions and require time and energy to achieve. Consider the following scenario, representing four bytes of data that are written to the data receiver  102 . 
     
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Data Byte 
                 # of Transitions 
               
               
                   
                   
               
             
             
               
                   
                 00000000 
                 — 
               
               
                   
                 11111111 
                 8 
               
               
                   
                 10001000 
                 6 
               
               
                   
                 01110111 
                 6 
               
               
                   
                   
               
             
          
         
       
     
     The total number of data transitions in the 24 bits of bytes  2 ,  3 , and  4  in the above example is 20, or 83%. (Note that this assumes that each line of the bus was in a low state when the original byte is sent). This results in time and power penalties in the operation of the data transfer system. 
     Data Inversion Scheme 
     The prior art has provided a scheme to reduce the number of data transitions in writing to a memory device known as “data inversion”. In the data inversion scheme, the number of data transitions between one byte and the next is determined and analyzed. If the number of transitions is greater than four, the data of the byte to be sent is inverted. In this way the number of transitions is made to be less than four. This scheme sets a bound of four on the greatest number of transitions that can occur from byte to byte, for a maximum of 50% transitions. The operation of the data inversion scheme is illustrated by reference to the table below. 
     
       
         
               
               
               
               
             
           
               
                   
               
               
                 Data Byte 
                 Invert? 
                 Data Byte Actually Sent 
                 # of Transitions 
               
               
                   
               
             
             
               
                 00000000 
                 — 
                 00000000 
                 — 
               
               
                 11111111 
                 Yes 
                 00000000 
                 0 
               
               
                 10001000 
                 No 
                 10001000 
                 2 
               
               
                 01110111 
                 Yes 
                 10001000 
                 0 
               
               
                   
               
             
          
         
       
     
     After the first byte is sent, the next byte is examined to see how many transitions there would be if the byte was sent without inversion. Here, where the byte changes from all zeros to all ones, there would be 8 transitions. Since 8 is greater than four, the byte is inverted, becoming all zeros. When this byte is sent, there are no data transitions, since each line of the bus was already in the low state. Examining the next byte, it is compared to the actual byte sent (in this case the inverted byte) to determine the number of possible transitions. Without inversion, there will be two transitions, which is less than four, so the byte is sent without inversion. Comparing the next byte (01110111) to the byte that had been sent reveals 8 transitions if it is sent without inversion. Therefore the byte is inverted (to 10001000) and is sent with no transitions. Sending the same data using the inversion scheme results in only 2 transitions out of 24 bytes, or 8.3%. This improvement results in better and faster data transfer operation. 
     A disadvantage of the data inversion scheme is that it requires an extra bits to be sent with the data byte so that the data can be properly used or stored at the data receiver, as well as extra bits when data is read from the receiver. These extra bits require additional wiring for the bus, data sender and receiver, adding to the expense and complexity of a system. 
     SUMMARY OF THE INVENTION 
     The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during reading operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a data source and a data receiver. 
         FIG. 2  is a diagram of an implementation for writing data to a device. 
         FIG. 3  illustrates read circuitry for the DRAM of the present invention. 
         FIG. 4  is an example of a DIM generator. 
         FIG. 5  is a flow diagram that illustrates the operation of the invention during a burst read operation. 
         FIG. 6  is a block diagram of the invention used with a microprocessor interface. 
         FIG. 7A  is a block diagrma of an alternate embodiment of a read block of the present invention. 
         FIG. 7B  is an alternate embodiment of a write block of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is a method and apparatus for reading and writing data. In the following description, numerous specific details are set forth to provide a more thorough description of embodiments of the invention. It is apparent, however, to one skilled in the art, that the invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the invention. 
     Currently there has not been provided an efficient scheme for using data inversion in a dynamic random access memory (DRAM) system. One of the advantage of using DRAMs in a system is the low cost of DRAMs and the commodity nature of such memory devices. A DRAM communicates with other devices via “pins” that extend from the DRAM package. If a DRAM using a data inversion scheme requires extra pins for the inversion information, the DRAM might not be usable in many applications where the geography is for DRAMS having fewer pins. Similarly, the expense of building and selling a DRAM with an extra pin could make it commercially unviable. 
     The present invention takes advantage of an existing pin called the data mask (DM) pin that is associated with the data pins of a DRAM. The DM pin is typically used on data input but not on data output. The invention takes advantage of the DM pin on data output to provide a signal indicating the presence or absence of data inversion when the data is being outputted by the DRAM. 
     In the DRAM of the preferred embodiment of the invention, there are 32 data bits DQ 0  to DQ 31  divided into four bytes each DQ 0 -DQ 7 , DQ 8 -DQ 15 , DQ  16 -D Q  23 , and DQ  24 -DQ 31 . Each of the data bytes has an associated data mask pin DM 0 -DM 3  that is used during write operations to mask the data input as appropriate. When any of DM 1  to DM 3  are high, the data input at the same timing are masked. 
     Write Operations 
     Write operations to the DRAM must include an indication of whether the incoming data is inverted or not inverted. A data inversion mask (DIM) bit is included with the data to be written so that the DRAM can store the data in its true state. One implementation for accomplishing this is illustrated in  FIG. 2 . Incoming data is provided as input  201  to an exclusive OR gate  203 , along with DIM bit  202 . When the DIM bit is high, the data coming in has been inverted so it is re-inverted via XOR gate  203  before being stored in the data array  204 . 
     Read Operations 
       FIG. 3  illustrates read circuitry for the DRAM of the present invention. Each byte of data has an associated DM pin. For example, data byte D[ 7 : 0 ] is associated with DM 0 , byte D[ 15 : 8 ] is associated with DM 1 , byte [ 23 : 16 ] is associated with DM 2 , and byte D[ 31 : 24 ] is associated with DM 3 . During read operations, the data is provided from array  300  directly to the data output pins and to a DIM generator such as generators  301 . 1  through  301 . 4 . The DIM generator determines of the data should be inverted or not to reduce data transitions during the read operation. The output of the DIM generator is outputted on the DM pin associated with the data byte. 
     An example of a DIM generator is illustrated in  FIG. 4 . A last data register  401  stores the most recently sent byte (as it was actually sent, inverted or non inverted). A new data register  402  stores the current data byte to be sent. The outputs of registers  401  and  402  are provided to comparator  403 . If the number of transitions is greater than 4 bits, the comparator  403  outputs a high signal to be output on the DM pin with the data byte. 
     Burst Operation 
     Often reads are done from a DRAM in a burst mode.  FIG. 5  is a flow diagram that illustrates the operation of the invention during a burst read operation. At block  500  the burst read begins. At block  510  the previous data register and the DM signal are set to low. At block  520  the present data and previous data are compared to determine the number of transitions that will occur when sending the present data. At decision block  530  the number of transitions is checked to see if it is greater than 4. If yes, the data is inverted and the DM is inverted at block  540 . If the result at decision block  530  is no, the data is not inverted and the previous DM value is maintained at block  550 . 
     After either of block  540  or  550 , a determination is made at decision block  560  as to whether the burst operation has ended. If yes, the process ends at block  570 . If no, the present data is stored in the prior data register, the new data byte is obtained, and the process returns to block  520 . 
     Pin Advantages 
     The present invention has the advantage of providing the ability to provide data inversion for a DRAM without the need for excessive increased pin count, especially for read operations. By using the a pin that is normally unused during read operations, i.e. the DM pin, the invention permits byte reads using data inversion with no additional pins for the read operation. 
     Termination 
     As described above with respect to the burst read example, an assumption was made that the bus was in a low state when the burst read operation began. This is not required and the invention is not limited to such a scheme or assumption. The termination of the bus can be any one of a number of ways as described below. 
     A. Pulled Low—In one embodiment of the invention, the bus is gradually pulled low after reads. One method of accomplishing this is described in a co-pending patent application entitled Self-Termination Scheme in a Double Data Rate Synchronous Dynamic Random Access Memory Device, assigned to the assignee of the present invention, and filed on Jun. 5, 2002, Ser. No. 10,164,044. In this scheme, NMOS transistors are coupled to the bus lines and gradually pull them to ground over some period of time. When this scheme is used, a read operation is assumed to begin with all lines low and the number of transitions for the first byte of data is determined based on this assumption. 
     B. Pulled High—In another embodiment, the bus can be pulled high be a PMOS termination scheme so that over time, after activity on the bus, all lines are pulled to a high state. The assumption in this scheme is that all lines are high at the beginning of a read operation and therefore the number of transitions for the first byte is determined with respect to an all high state. 
     C. Midpoint Termination—In an alternative embodiment, the bus lines are pulled to a midlevel condition over time. When this scheme is used, the first byte in a read operation is sent non-inverted since there will be no difference in pulling the bus lines high or low from the midlevel state. 
     D. Unterminated Unlatched—In this embodiment, the bus lines are not terminated at all and a first data byte is always sent unterminated. This results in lost efficiency for the first byte, since it may be possible to have greater than four transitions for the first byte. 
     E. Unterminated Latched—This embodiment leaves the bus lines in the same state as the most recent byte on the bus and latches that value. For a subsequent operation, the previous byte register contains the latched value and the first byte is compared to that latched value to determine the number of transitions. 
     Processor Interface Logic Application 
     Although described in connection with a DRAM, the present invention has other applications as well. For instance, the scheme can be used in connection with a microprocessor interface logic to allow a data inversion scheme to be used. An example of such an embodiment is illustrated in  FIG. 6 . 
     A DRAM  601  includes, for example first and second data banks  601 A and  601 B each having an output bus  602 A and  602 B along with associated DIM signals  603 A and  603 B (note that the DIM signals could be provided on DM pins). The outputs of the DRAM are provided to memory controller  604 . Within the memory controller  604  the data outputs  602 A and  602 B of the DRAM are combined in a 16 bit bus  605  to microprocessor  608 . The DIM signals  603 A and  603 B are coupled as inputs to an XOR gate  606  to produce an output signal  607  to microprocessor  608 . 
     Power Optimization 
     An embodiment of a read block of the present invention is illustrated in  FIG. 7A . This embodiment provides DC power optimization when the I/O is open drain (i.e. the bus is terminated to a logical 1). Referring to  FIG. 7A , read data  701  (8 bits) is coupled to flip-flop  702 , comparator  703 , and NOR gate  704 . A load signal  705  is coupled to the enable input of flip-flop  702 . The output of flip-flop  702  is coupled to one input of OR gate  706  along with DC optimizing signal  707 . The DC optimizing signal is a logical 1 which is OR&#39;ed into the previous data field of the comparator block  703 . This OR&#39;ing guarantees that the output of the comparator will have more than half of its values being a logical 1, saving DC power. The comparator  703  compares the present data field with the previous data field to see if there are more than 4 bits with different values. If so, the output (DIM) is a logical 1 and is provided to NOR gate  704  and appropriate inversion of the data is provided. 
     If the bus is terminated to a logical 0, then the DC optimizing signal can be a logical 0 as well, so that more than half of the outputs are biased to 0, also saving power. 
     Referring now to  FIG. 7B , a block diagram of a write block is shown. Write data  710  (e.g. 32 bits) is provided to flip-flop  711  and a DIM signal  712  is provided to flip-flop  713 . Both flip-flops are clocked with Write clock signal  714 . The outputs are coupled as inputs to NOR gate  715  to produce the data to be written into the memory array. 
     The present invention has been described in terms of the transmission of data but has equal application to any digital signals including address or command signals. 
     Thus, a method and apparatus for data inversion in memory devices has been described.

Technology Classification (CPC): 6