Patent Abstract:
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation of application Ser. No. 10/435,335, filed May 8, 2003, now U.S. Pat. No. 6,838,768, issued Jan. 4, 2005, which is a continuation of application Ser. No. 10/137,755, filed May 2, 2002, now U.S. Pat. No. 6,563,217, issued May 13, 2003, which is a continuation of application Ser. No. 09/343,746, filed Jun. 30, 1999, now U.S. Pat. No. 6,414,391 B1, issued Jul. 2, 2002, which claims the benefit of U.S. Provisional Application No. 60/091,285 filed Jun. 30, 1998. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages may be stacked on flexible or rigid substrates.  
         [0004]     2. State of the Art  
         [0005]     Chip-on-board technology generally consists of three types of techniques for attaching a semiconductor device to a printed circuit board, such as flip chip attachment, wire bonding, and tape automated bonding techniques.  
         [0006]     Flip chip attachment consists of attaching a semiconductor device, generally having a ball grid array (BGA), a slightly larger than integrated circuit carrier (SLICC), or a pin grid array (PGA) to a printed circuit board. With the BGA or SLICC, the solder ball arrangement on the semiconductor device must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connections are made. The semiconductor device is bonded to the printed circuit board by refluxing the solder balls. With the PGA, the pin arrangement of the semiconductor device must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the semiconductor device is generally bonded by soldering the pins into place. An underfill encapsulant is generally disposed between the semiconductor device and the printed circuit board to prevent contamination. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J-leads are soldered to pads on the surface of the circuit board. However, the lead and pad locations must coincide, as with the other types of flip-chip techniques.  
         [0007]     Wire bonding and tape automated bonding (TAB) attachment generally begin with attaching a semiconductor device to the surface of a printed circuit board with an appropriate adhesive. In wire bonding, a plurality of bond wires is attached, one at a time, from each bond pad of the semiconductor device to a corresponding lead on the printed circuit board. The bond wires are generally attached through one of three industry-standard wire bonding techniques, such as ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld, thermocompression bonding—using a combination of pressure and elevated temperature to form a weld, and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The semiconductor device may be oriented having either the active surface up or the active surface down (with the bond pads thereon either up or down with respect to the printed circuit board) for wire bonding, although active surface up is the most common. With TAB, metal tape leads are attached between the bond pads on the semiconductor device and the leads on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.  
         [0008]     Although such methods are effective for bonding semiconductor devices to printed circuit boards, the terminal arrangements of the devices and the connection arrangements of the boards must be designed to accommodate one another. Thus, it may be impossible to electrically connect a particular semiconductor device to a printed circuit board for which the semiconductor device terminal arrangements were not designed to match the board&#39;s connection arrangement. With either wire bond or TAB attachment, the semiconductor device bond pad arrangement may not correspond to the lead ends on the circuit board, making attachment difficult due to the need for overlong wires and the potential for inter-wire contact and shorting. With flip chip attachment, if the printed circuit board connection arrangement is not a mirror-image of the solder ball or pin arrangement of the semiconductor device, electrically connecting the flip chip to the printed circuit board is impossible.  
         [0009]     Ball grid array (BGA) semiconductor device packages are well known in the art. A BGA package typically comprises a substrate, such as a printed circuit board, with a semiconductor device, such as a dynamic random access memory device, mounted on the top side of the substrate. The semiconductor device has a plurality of bond pads on the active surface thereof electrically connected to a series of metal traces on the top surface or top side of the printed circuit board. The connection between the bond pads and the metal traces is provided by wire bonds electrically and mechanically connecting the semiconductor device and the printed circuit board. The series of metal traces on the printed circuit board is connected, in turn, to a second series of metal traces on the bottom surface or bottom side of the printed circuit board using a series of vias extending therethrough. The second series of metal traces each terminate with a connection contact pad where a conductive element is attached. The conductive elements can be solder balls or conductive filled epoxy. The conductive elements are arranged in an array pattern and the semiconductor device and wire bonds are encapsulated with a molding compound.  
         [0010]     As semiconductor device and grid array densities increase, the desire in packaging semiconductor devices has been to reduce the overall height or profile of the semiconductor package. The use of BGAs has allowed for this reduction of profile as well as increased package density. Density has been increased by using lead frames, such as lead-over-chip type lead frames, in an effort to increase the semiconductor device density as well as allow stacking of the semiconductor devices one on top another.  
         [0011]     One example of a lead chip design in a BGA package is shown in U.S. Pat. No. 5,668,405. A semiconductor device is disclosed having a lead frame attached to the semiconductor device. Through holes are provided that allow for solder bumps to connect via the lead frame to the semiconductor device. Such a mounting arrangement requires several steps for attaching the semiconductor device to the lead frame, then providing sealing resin, and subsequently adding a base film and forming through holes in the base film. A cover resin is added before solder bumps are added in the through holes to connect to the lead frame. This particular structure lacks the ability to stack semiconductor devices one on top another.  
         [0012]     U.S. Pat. No. 5,677,566, commonly assigned to the assignee of the present invention, illustrates a semiconductor device package that includes discrete conductive leads with electrical contact bond pads on a semiconductor device. The lead assembly is encapsulated with a typical encapsulating material and electrode bumps are formed through the encapsulating material to contact the conductive leads. The electrode bumps protrude from the encapsulating material for connection to an external circuit. The semiconductor device has the bond pads located in the center of the active surface of the device, thus allowing the conductive leads to be more readily protected once encapsulated in the encapsulating material. However, the assembly illustrated in the &#39;566 patent lacks the ability to stack one semiconductor device on top another.  
         [0013]     U.S. Pat. No. 5,625,221 illustrates a semiconductor device package assembly that has recessed edge portions that extend along at least one edge portion of the assembly in an attempt to form a stacked package of semiconductor devices. An upper surface lead is exposed therefrom and a top recess portion is disposed on a top surface of the assembly. A bottom recess portion is disposed on the bottom surface of the assembly such that when the assembly is used in fabricating a three-dimensional integrated circuit module, the recess edge portion accommodates leads belonging to an upper semiconductor assembly to provide electrical interconnection therebetween. However, the assembly requires long lead wires from the semiconductor chip to the outer edges. These lead wires add harmful inductance and unnecessary signal delay and can form a weak link in the electrical interconnection between the semiconductor device and the outer edges. Further, the assembly profile is a sum of the height of the semiconductor devices, the printed circuit boards to which they are bonded, the conductive elements, such as the solder balls, and the encapsulant that must cover the semiconductor devices and any wire bonds used to connect the devices to the printed circuit boards. Reducing such a package profile is difficult because of the geometries required in having the bond pads on the semiconductor device along the outer periphery with extended lead wires reaching from the semiconductor device to the outer edges.  
         [0014]     U.S. Pat. Nos. 5,266,912 and 5,400,003 illustrate another stacked arrangement of semiconductor devices on a substrate interconnected by pins. However, the height of the stacked package is limited by the length of the pin connections between the individual multi-chip modules or printed circuit boards.  
         [0015]     Another problem which arises in stacking semiconductor devices mounted on printed circuit boards is that it is difficult to provide a flat, smooth surface on which to mount the printed circuit board. Accordingly, flexible boards have been developed to allow both lighter-weight structures and greater adaptability at conforming to nonuniform surfaces. However, the use of such flexible circuit boards has resulted in other problems, such as the problem in joining several flexible boards while maintaining the proper interconnection between the respective boards. Further, in some applications, such as protecting semiconductor devices mounted on a bottom surface of a flexible substrate from touching the top of another flexible circuit board, the use of a rigid member or assembly is required to support the stacked flexible circuit boards. This sacrifices the flexibility that is present in the flexible circuit boards that allows their compliance with a non-planar surface.  
         [0016]     U.S. Pat. No. 5,440,171 illustrates semiconductor devices mounted on flexible, stackable circuit boards to form semiconductor modules. A basic structure unit is illustrated comprising a flexible circuit board made from a polyamide film with circuit lines formed on both sides, typically using copper foil. A supporting frame is provided and bonded to the flexible circuit board with a heat-resistant resin, such as a polyamide resin. Electrical connections are possible between the flexible circuit board and the support frame. Conductive through holes are provided so that electrical continuity exists between a semiconductor device mounted upon the flexible circuit board and either at least one other semiconductor device mounted on another flexible circuit board stacked within the module assembly or an outside source upon which the entire basic structure unit is mounted. The semiconductor devices are electrically connected to electrodes on the support frame. Although the semiconductor device is mounted on a flexible circuit board that is stackable in an arrangement, the support frame attaching the stackable circuit boards one to another is made from a rigid material that does not allow for any bending. One type of frame material is ceramic, such as silicon nitride. Silicon nitride is used for its high thermal conductivity for heat radiation or dissipation when the semiconductor device has a high power consumption. Since the support frame is made from rigid and non-flexible material, the semiconductor device package assembly needs to be mounted on a substantially planar surface, thereby preventing the assembly from being molded on surfaces that are not uniformly planar or smooth.  
         [0017]     Additionally, when stacking semiconductor devices using flexible or rigid substrates, as the operation speed of the semiconductor device increases it is desirable to match the impedance of the various circuits to which the semiconductor devices are connected, to try to keep the circuit response time the same for each circuit. Since in stacked arrangements the circuit length for each semiconductor device will vary, attention must be given to keeping the circuit impedance substantially the same.  
         [0018]     Accordingly, what is needed is a ball grid array package that allows for the stacking of packages where printed circuit board substrates or flexible substrates may be used as desired and which allows for the matching of the impedance for the different circuits as required.  
       BRIEF SUMMARY OF THE INVENTION  
       [0019]     The present invention comprises ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. Additionally, the present invention comprises an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0020]      FIG. 1  is a view of a semiconductor package for use in the present invention;  
         [0021]      FIG. 2  is a cross sectional view of a semiconductor package for use in the present invention;  
         [0022]      FIG. 3  is a bottom view of a semiconductor package for use in the present invention;  
         [0023]      FIG. 4  is a side view of a first embodiment of the present invention using semiconductor packages in a stacked package arrangement on each side of a substrate;  
         [0024]      FIG. 5  is a side view of a second embodiment of the present invention using semiconductor packages stacked in a package arrangement on one side of a substrate wherein resistors and a bus bar arrangement are used to match the impedance of the circuits;  
         [0025]      FIG. 6  is a side view of a third embodiment of the present invention using semiconductor packages stacked in a package arrangement on both sides of a substrate wherein resistors and bus bars are used to match the circuit impedance of the stacked packages;  
         [0026]      FIG. 7  is a top view of a fourth embodiment of the semiconductor package of the present invention using a flexible substrate for the mounting of a semiconductor device thereon;  
         [0027]      FIG. 8A  is a side view of the fourth embodiment of the semiconductor package of the present invention of  FIG. 7  shown in cross section using a flexible substrate for the mounting of a semiconductor device thereon;  
         [0028]      FIG. 8B  is an enlarged view of a portion of the flexible substrate of the semiconductor package of  FIG. 8A ;  
         [0029]      FIG. 9  is a side view of a fifth embodiment of the semiconductor package of the present invention using a plurality of stacked semiconductor packages using a flexible substrate for the mounting of a semiconductor device thereon; and  
         [0030]      FIG. 10  is a side view of a sixth embodiment of the semiconductor package of the present invention using a plurality of stacked semiconductor packages using a flexible substrate for the mounting of a semiconductor device thereon. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0031]     Referring to drawing  FIG. 1 , a wire bond style/flip chip assembly  100  is illustrated. An adapter board  18  is shown having a semiconductor device  12  located on the upper surface  20  thereof with the lower surface of the adapter board  18  having a plurality of solder balls  22  located thereon in rows for connection purposes.  
         [0032]     Referring to drawing  FIG. 2 , the wire bond style/flip chip assembly  100  is illustrated in cross section. The semiconductor device  12  has a plurality of bond pads  38  arranged in two rows on the active surface  14  thereof. The semiconductor device  12  is secured to the adapter board  18  by a suitable adhesive  40 . The adapter board  18  is formed having at least one longitudinally extending aperture  42  therethrough and a plurality of connection pads  39  located on the bottom surface thereof. A plurality of circuits or circuit traces  23  of adapter board  18  connects connection pads  39  to a desired solder ball(s)  22 . Wires  34  extend between the bond pads  38  of the semiconductor device  12  and the connection pads  39  of the adapter board  18 , the wires being bonded to the pads  38  and  39  through the use of a suitable wire bonder well known in the industry. After the connections using wires  34  have been made through aperture  42  in adapter board  18 , a suitable encapsulant material  44  is applied to the aperture  42  to cover the wires  34 , the bond pads  38  on the semiconductor device  12 , and the connection pads  39  on the adapter board  18 .  
         [0033]     Referring to drawing  FIG. 3 , an adapter board  18  is illustrated from the bottom thereof. As illustrated, the encapsulant material  44  covers the aperture  42  in the adapter board  18 . The solder balls  22  are illustrated in a plurality of rows. The semiconductor device  12  is shown in dashed lines as well as adhesive  40  connecting the semiconductor device  12  to the upper surface of the adapter board  18 .  
         [0034]     Referring to drawing  FIG. 4 , a plurality of wire bond style/flip chip assemblies  100  is illustrated connected to a substrate  50  in a stacked arrangement, each assembly  100  having two rows of solder balls  22  thereon. Each assembly  100  is connected to another assembly  100  through circuits  52  in boards  18  and connected to circuits  54  in substrate  50 . The substrate  50  may be any suitable substrate, such as a printed circuit board, FR-4 board or the like, which is structurally and electrically capable of connecting a plurality of assemblies  100  thereto. Any desired number of assemblies  100  may be connected to the substrate  50  on both or only one side thereof. The substrate  50  may have connection pads  56  thereon connected to circuits  54  for connection to other circuits or components. Although one stack of assemblies  100  has been illustrated on each side of the substrate  50 , any number may be used on each side or one side of the substrate  50 .  
         [0035]     Referring to drawing  FIG. 5 , a plurality of wire bond style/flip chip assemblies  100  is illustrated installed on a substrate  60  having suitable circuits therein in a first stack  62  and a second stack  64 , the assemblies  100  being interconnected using solder balls  22 . The substrate  60  may be any suitable substrate, such as a printed circuit board, FR-4 board, or the like, capable of supporting the stacks  62  and  64  of assemblies  100 . In the arrangement, the stacked assemblies  100  are serially connected by means of the solder balls  22  using a jumper board  70  which includes bus lines therein and acts as a heat sink for the stacks  62  and  64 . The jumper board  70  may be any suitable board, such as a printed circuit board, FR-4 board, or the like. Included on the substrate  60  is a plurality of resistors  66  which is used to balance the impedance of the circuits of the serially connected assemblies  100  in the stacks  62  and  64 . The assemblies  100  are serially connected to a resistor  66  through the circuits in the substrate  60  and jumper board  70  as illustrated by the arrows  72 . In this manner, the impedance of the various circuits in the assemblies  100  in the stacks  62  and  64  may be matched so that the response of the stacked assemblies  100  will not substantially vary.  
         [0036]     Referring to drawing  FIG. 6 , a plurality of wire bond style/flip chip assemblies  100  is illustrated installed on both sides of substrate  60  having suitable circuits therein in first stacks  62  and a second stacks  64 , the assemblies  100  being interconnected using solder balls  22 . The substrate  60  may be any suitable substrate, such as a printed circuit board, FR-4 board, or the like, capable of supporting the stacks  62  and  64  of assemblies  100 . In the arrangement, the stacked assemblies  100  are serially connected by means of the solder balls  22  using jumper boards  70  which include bus lines therein and act as heat sinks for the stacks  62  and  64 . The jumper boards  70  may be any suitable board, such as a printed circuit board, FR-4 board, or the like. Included on the substrate  60  is a plurality of resistors  66  which is used to balance the impedance of the circuits of the serially connected assemblies  100  in the stacks  62  and  64 . The assemblies  100  are serially connected to a resistor  66  through the circuits in the substrate  60  and jumper board  70  as illustrated by the arrows  72 . In this manner, the impedance of the various circuits in the assemblies  100  in the stacks  62  and  64  may be matched so that the response of the stacked assemblies  100  will not substantially vary.  
         [0037]     Referring to drawing  FIG. 7 , a bottom view of an assembly  200  of a flexible substrate  202  is illustrated having a plurality of conductors  204  formed thereon connected by bonds  206  through apertures  212  in substrate  202  to bond pads  208  of semiconductor device  210 . The flexible substrate  202  may be any suitable type material, such as polyamide tape, and have a plurality of desired conductors  204  formed thereon, such as copper type conductors. The substrate  202  may include alignment apertures  214  therein, if desired. The substrate  202  further includes apertures  216  therein for the connection of the conductors  204  to other conductors  204  on adjacent stacked substrates. The apertures  216  have a size sufficient to allow a solder ball having a diameter of at least twice the thickness of the substrate  202  to be used therein. A gold ball type bond  206  may be used to connect the conductors  204  to the bond pads  208  of the semiconductor device  210 .  
         [0038]     Referring to drawing  FIG. 8A , the assembly  200  is shown in cross section, the flexible substrate  202  having the semiconductor device  210  mounted on the upper surface thereof with bonds  206  to the bond pads  208  of the semiconductor device  210  and conductors  204  of the substrate  202 .  
         [0039]     Referring to drawing  FIG. 8B , a portion of the flexible substrate  202  is illustrated having aperture  216  therein having a solder ball  220  contained therein for connection to an adjacent substrate  202 .  
         [0040]     Referring to drawing  FIG. 9 , a plurality of stacked assemblies  200  is illustrated being vertically stacked with the flexible substrates  202  extending therebetween and connections between the conductors  204  (not shown) of each flexible substrate  202  being made through apertures  216  in the substrates  202  by means of melted solder balls  220  extending therebetween in the apertures  216 . Since polyamide tape is used as the substrate  202 , the substrate is flexible and readily bends and complies to the vertically stacked arrangement of a plurality of assemblies  200 . As illustrated, a stacked arrangement of assemblies  200  is made on one side of the bottom substrate  202 . The assemblies  200  are aligned through the use of the alignment apertures  214  (not shown) in the flexible substrates  202  forming the stacked arrangement. If desired, a mechanical connection may be made to the melted solder balls  220  in the apertures  216  to connect the conductors  204  to the appropriate bond pad of the semiconductor device  210 .  
         [0041]     Each assembly  200  may be fabricated individually or in strip form and subsequently singulated.  
         [0042]     Referring to drawing  FIG. 10 , a vertical stack of assemblies  200  is illustrated where the assemblies  200  are stacked on both sides of the bottom substrate  202  with interconnections between the conductors  204  on the substrates  202  being made by melted solder balls  220  extending within apertures  216  of the substrates  202 . The assemblies  200  are aligned through the use of the alignment apertures  214  (not shown) in the flexible substrates  202  forming the stacked arrangement. If desired, a mechanical connection may be made to the melted solder balls  220  in the apertures  216  to connect the conductors  204  to the appropriate bond pad of the semiconductor device  210 .  
         [0043]     Having thus described the invention, it will be understood that changes, revisions, additions, and deletions may be made to the invention which will come within the scope of the invention. Such may be required by the design of the semiconductor device and its attachment to the substrates and/or to adjacent assemblies of semiconductor devices.

Technology Classification (CPC): 7