Patent Abstract:
A retaining ring structure of a carrier head designed for use in a chemical mechanical polishing system (CMP) is provided. The retaining ring includes a retaining ring support and a sacrificial retaining ring, which is designed to confine a substrate to be polished. The included sacrificial retaining ring has an upper surface and a contact surface. The upper surface of the sacrificial retaining ring is configured to be attached to the retaining ring support, such that the retaining ring support holds the sacrificial retaining ring. Preferably, the contact surface of the sacrificial retaining ring is configured to be substantially planer with a top surface of the substrate being polished. In a preferred example, the sacrificial retaining ring can include a plurality of capillary tubes and is constructed from a material having substantially the same characteristics as the surface of the substrate to be polished.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to chemical mechanical polishing (CMP) systems and techniques for improving the performance and effectiveness of CMP operations. Specifically, the present invention relates to a substrate carrier having an active sacrificial retaining ring. 
     2. Description of the Related Art 
     In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level and/or associated dielectric layer, there is a need to planarize the metal and/or dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization. 
     In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to polish, buff, and scrub one or both sides of a wafer. Slurry is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface. 
     In a typical CMP system, a wafer is mounted on a carrier, which rotates in a direction of rotation. The CMP process is achieved when the exposed surface of the rotating wafer is applied with force against a polishing pad, which moves or rotates in a polishing pad direction. Some CMP processes require that a significant force be used at the time the rotating wafer is being polished by the polishing pad. 
     Normally, the polishing pads used in the CMP systems are composed of porous or fibrous materials. Depending on the type of the polishing pad used, slurry composed of an aqueous solution containing different types of dispersed abrasive particles such as SiO 2  and/or Al 2 O 3  may be applied to the polishing pad, thereby creating an abrasive chemical solution between the polishing pad and the wafer. 
     FIG. 1A depicts a cross-sectional view of an exemplary prior art CMP system. The CMP system of FIG. 1A depicts a carrier head  100  engaging a wafer  102  utilizing a retaining ring  101 . The carrier head  100  is applied against the polishing pad surface  103   a  of a polishing pad  103  with a force F. As shown, the top surface of the retaining ring  101  is positioned above the front surface of the wafer  102 . Thus, while the front surface of the wafer  102  is in contact with the polishing pad surface  103   a , the surface of the retaining ring  101  is configured not to come into contact with the polishing pad surface  103   a.    
     Several problems may be encountered while using a typical prior art CMP system. One recurring problem is called “edge-effect” caused by the CMP system polishing the edge of the wafer  102  at a different rate than other regions, thereby creating a non-uniform profile on the surface of the wafer  102 . The problems associated with edge-effect can be divided into two distinct categories of the “pad rebound effect” and “edge burn-off effect.” FIG. 1B is an enlarged illustration of the pad rebound effect associated with the prior art. The pad rebound effect occurs when the polishing pad surface  103   a  initially comes into contact with the edge of the wafer  102  causing the polishing pad surface  103  to bounce off the wafer  102 . As the moving polishing pad surface  103   a  shifts under the surface of the wafer  102 , the edge of the wafer  102  cuts into the polishing pad  103  at the edge contact zone  104   c , causing the polishing pad  103   a  to bounce off the wafer  102 , thereby creating a wave on the polishing pad  103 . 
     Ideally, the polishing pad  103  is configured to be applied to the wafer  102  at a specific uniform pressure. However, the waves created on the polishing pad  103  create a series of low-pressure regions such as an edge non-contact zone  104   a  and a non-contact zone  104   a , wherein the removal rate is lower than the average removal rate. Thus, the regions of the wafer  102  which came into contact with the polishing pad surface  103   a  such as the edge contact zone  104   c  and a contact zone  104   b , are polished more than the other regions. As a result, the CMP processed wafer will tend to show a non-uniform profile. 
     Further illustrated in FIG. 1B is the edge “burn-off.” As the polishing pad surface  103   a  comes into contact with the sharper edge of the wafer  102  at the edge contact zone  104   c , the edge of the wafer  102  cuts into the polishing pad  103 , thereby creating an area defined as a “hot spot,” wherein the pressure exerted by the polishing pad  103  is higher than the average polishing pressure. Thus, the polishing pad surface  103   a  excessively polishes the edge of the wafer  102  and the area around the edge contact zone  104  (i.e., the hot spots). The excessive polishing of the edge of the wafer  102  occurs because a considerable amount of pressure is exerted on the edge of the wafer  102  as a result of the polishing pad surface  103   a  applying pressure on a small contact area defined as the edge contact zone  104   c . As a consequence of the burn-off effect, a substantially high removal rate is exhibited at the area within about 1 millimeter to about 3 millimeters of the edge of the wafer  102 . Moreover, depending on the polisher and the hardware construction, a substantially low removal rate is detected within the edge non-contact zone  104   a ′, an area between about 3 millimeters to about 20 millimeters of the edge of the wafer  102 . Accordingly, as a cumulative result of the edge-effects, an area of about 1 millimeter to about 20 millimeters of the edge of the resulting post CMP wafers sometimes could be rendered unusable, thereby wasting silicon device area. 
     Although, occasionally, an air bearing has been implemented in an attempt to compensate for the different levels of pressure applied by the polishing pad  103 , air bearings have almost never been able to completely compensate for the difference in the pressure levels. Particularly, at the edge contact zone  104   c , the edge non-contact zone  104   a ′, the contact zone  104   b , and the non-contact zone  104   a  the use of air bearings do not completely compensate for the difference in the exerted pressure, as the air can easily escape. 
     A common problem associated with the pad rebound effect and the edge burn off effect is the non-uniformity of the wafer  102  caused by the lack of uniform distribution of slurry between the polishing pad surface  103   a  and the surface of the wafer  102 . As the edge of the wafer  102  cuts into the polishing pad surface  103   a , it causes the slurry to be squeezed out of the polishing pad  103 , thereby preventing the polishing pad surface  103   a  from performing a thorough polishing operation on the edge of the wafer  102 . Thus, to accomplish a proper polishing operation, additional slurry must be supplied to the polishing interface. Consequently, a significant amount of slurry is wasted as a result of the combined effects of the pad rebound effect and edge burn-off effect. 
     In view of the foregoing, a need therefore exists in the art for a chemical mechanical polishing system that substantially eliminates damaging edge-effects and their associated removal rate non-uniformities while efficiently facilitates slurry distribution. 
     SUMMARY OF THE INVENTION 
     Broadly speaking, the present invention fills these needs by providing a system, which yields a substantially uniform removal rate throughout the surface of a wafer. In a preferred embodiment, the CMP system is designed to implement an active retaining ring configured to have a sacrificial component, which simulates the pattern of the substrate being polished by utilizing a plurality of collimated holes. As the sacrificial component is being polished together with the wafer, the edge of the polishing interface is thus virtually extended to the outside of the substrate being polished, thereby eliminating the aforementioned edge-effects, pad rebound effects, and edge bum-off effects. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below. 
     In one embodiment, a retaining ring structure of a carrier head for use in a chemical mechanical polishing system (CMP) is disclosed. The retaining ring structure includes a retaining ring support and a sacrificial retaining ring designed to confine a substrate to be polished. The sacrificial retaining ring also has an upper surface and a contact surface. The upper surface of the sacrificial retaining ring is configured to be attached to the retaining ring support, such that the retaining ring support holds the sacrificial retaining ring. The contact surface of the sacrificial retaining ring is configured to be substantially planer with a top surface of the substrate being polished. 
     In another embodiment, a wafer holding and application apparatus for use in chemical mechanical polishing (CMP) applications is disclosed. The apparatus includes a carrier head and a retaining ring support, which is designed to be attached to the carrier head. Also included in the apparatus is a sacrificial retaining ring, which is attached to the retaining ring support. The sacrificial retaining ring is designed to confine a wafer at a desired location when the carrier head applies the wafer to a polishing surface. The retaining ring support is defined from a material that approximates the wafer. A contact surface of the sacrificial retaining ring is positioned approximately planar with a to be polished surface of the wafer. 
     In yet another embodiment, a method for making a carrier head to be used in chemical mechanical polishing (CMP) of a wafer is disclosed. The method includes generating a retaining ring support and attaching the retaining ring support to the carrier head. Also included in the method is generating a plurality of capillary tube array units each having a contact surface. The method further includes attaching each of the plurality of capillary tube array units around the retaining ring support such that the plurality of capillary tube array units define a sacrificial retaining ring designed to contain the wafer having a surface to be polished. In addition, the surface of the wafer to be polished and the contact surface of each of the plurality of capillary tube array units are defined at about a same planar position. 
     The advantages of the present invention are numerous. Primarily, in contrast to prior art CMP systems, the contact surface of the sacrificial retaining ring is positioned substantially on a same horizontal plane as the top surface of the wafer, thereby virtually extending the polishing interface to the outside of the surface of the wafer. As such, the present invention eliminates the negative effects of the edge-effects, pad rebound effects, and edge burn-off effect. In addition, the construction of the sacrificial retaining ring out of plurality of capillary tube array units having plurality of capillary tubes facilitates the uniform distribution of slurry to the polishing interface so as to achieve a substantially uniform material removal through out the surface of the wafer. 
     Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements. 
     FIG. 1A is an illustration of the prior art CMP system. 
     FIG. 1B is an illustration of the pad rebound effect and edge burn-off effect associated with the prior art. 
     FIG. 2 depicts the non-uniform removal rate of materials from a polishing interface, in accordance with one embodiment of the present invention. 
     FIG. 3A is an exploded cross-sectional view of a CMP carrier head engaging a retaining ring support holding a sacrificial retaining ring, in accordance with another embodiment of the present invention. 
     FIG. 3B-1 is an enlarged cross-sectional view of a polishing pad surface being applied to a wafer and a sacrificial retaining ring without introducing additional slurry, in accordance with yet another embodiment of the present invention. 
     FIG. 3B-2 is an enlarged cross-sectional view of a polishing pad surface being applied to a wafer and a sacrificial retaining ring utilizing a slurry guide inlet to supply additional slurry to the sacrificial retaining ring via a slurry distribution manifold, in accordance with yet another embodiment of the present invention. 
     FIG. 4A depicts the structure of a retaining ring and the relative position of a sacrificial retaining ring with respect to the retaining ring support, in accordance with et another embodiment of the present invention. 
     FIG. 4B depicts the relative positions of multiple capillary tube array units with respect to each other as well as a wafer, in accordance with yet another embodiment of the present invention. 
     FIG. 4C is a three-dimensional view of a capillary tube array unit, in accordance with yet another embodiment of the present invention. 
     FIG. 5A depicts the retaining ring support holding the capillary tube array units utilizing a contiguous ring finger, in accordance with yet another embodiment of the present invention. 
     FIG. 5B depicts the sacrificial retaining ring being mounted on the retaining ring support utilizing microscrews, in accordance with yet another embodiment of the present invention. 
     FIG. 5C depicts a sacrificial retaining ring being affixed to a retaining ring support utilizing glue, in accordance with yet another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An invention for a CMP system, which substantially eliminates the aforementioned edge-effects, pad rebound effects, and edge burn-off effects is disclosed. In preferred embodiments, the CMP system implements an active retaining ring having a sacrificial component, which simulates the patterned surface of the wafer while relocating the line of contact of the polishing pad and the wafer, outside of the wafer surface and onto the outer edge of the sacrificial component of the retaining ring. Preferably, in one implementation, the sacrificial component is constructed from glass (e.g., Silicon dioxide (SiO 2 ), Borosilicate, Soda Lime, etc.) and contains a plurality of capillary tubes, which assist in simulating the patterns on the surface of the wafer and/or facilitate uniform distribution of slurry to the polishing interface. 
     In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be understood, however, to one skilled in the art, that the present invention may be practiced without some or all of these details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention. 
     Graph  150  of FIG. 2 depicts the non-uniform removal rate of materials from a polishing interface, in accordance with the present invention. A removal rate axis  152  of the graph  150  illustrates the fluctuation of the removal rates of materials at different points of the polishing area axis  154 . In accordance with one embodiment of the present invention, the CMP system starts the polishing operation at an edge of a sacrificial retaining ring (SRR)  176  so as to achieve a removal rate of  172 . Thereafter, as a result of the edge-effect, pad rebound effect, and burn-off effect, a maximum removal rate  174  is achieved at a point  158 , which corresponds to a point  178  located on the Sacrificial Retaining Ring (SRR)  201   a . Then, the graph descends, depicting a point  160 , which corresponds to the CMP machine polishing a point  180  located on the SRR  201   a  having a removal rate of  168 . Subsequently, a substantially lower removal rate of  166  is achieved for the point  182  positioned within the bounce back region of the polishing area axis  154  still located within the SRR  201   a  corresponding to a point  162  of the graph. Then, at a point  164  of the graph, a substantially uniform removal rate of  170  is achieved. As depicted, the point  164  corresponds to a position  184  of the polishing area axis, representing approximately the end of the SRR  201   a  and approximately the beginning of the true edge of a wafer  202 . Thus, as illustrated, the non-uniform removal rate caused by the edge-effect, pad rebound effect, and edge burn-off effect has been substantially eliminated by virtually extending the edge of the polishing interface to outside of the wafer  202 . 
     FIG. 3A is an exploded cross-sectional view of a CMP carrier head  200  engaging a retaining ring support (RRS)  201 b holding a sacrificial retaining ring (SRR)  201   a . Also shown are a plurality of vacuums  206  feed through in a carrier film  204  engaging a wafer  202 . The surface of the carrier film  204  may include approximately about  4  to  12  vacuum holes  206 . The vacuums  206  are configured to retain the wafer  202  via carrier film  204 , when the carrier head  200  is no longer in contact with the surface of the polishing pad  103   a . As depicted, the top surface of the wafer  202  as well as the contact surface of the SRR  201   a  are being applied to a polishing pad surface  203   a  of a polishing pad  203 . Specifically shown is the planer relationship of the top surface of the wafer  202  and the contact surface of the SRR  201   a , revealing the active sacrificial characteristic of the SRR  201   a.    
     In one preferred implementation, the SRR  201   a  is constructed from materials having similar characteristics to those of the material of the substrate being polished. Thus, in this embodiment, as it is the silicon wafer  202  that is being polished, the SRR  201   a  is constructed from a material having similar characteristics as silicon (Si) or the films that are typically present on the surface of the wafer  202  (i.e., glass, dielectrics, metals, etc.). More specifically, the chosen material is preferred to be of a material, which friction with the polishing pad surface  203   a  does not introduce any additional defects or contamination to the polishing interface of the SRR  201   a  and the wafer  202 . Accordingly, the concurrent polishing of the glass SRR  201   a  and the wafer  202  relocates the line of contact of the polishing interface and the polishing pad surface  203   a  outside of the wafer  202  and to the edge of the glass SRR  201   a  so as to eliminate the aforementioned shortcomings of edge-effects, edge burn-off effects, and pad rebound effects. 
     FIG. 3B-1 is an enlarged cross-sectional view of a polishing pad surface  203   a  being applied to a top surface of a wafer  202  and a top surface of a sacrificial retaining ring (SRR)  201   a  without introducing slurry through capillary tubes  208  of capillary tube array units  201   a    40   (e.g., through collimated hole structures). As depicted, the top surface of the wafer  202  and the contact surface of the sacrificial retaining ring  201   a  are positioned substantially on a same horizontal plane so that the sacrificial retaining ring  201   a  can be polished together with the wafer  202 . As shown, the SRR  201   a  contains a plurality of capillary tubes  208 , which in this embodiment, extend from the contact surface of the SRR  201   a  to a bottom surface of the SRR  201   a . The capillary tubes  208  are configured to simulate the pattern of the surface of the substrate being polished (i.e., the wafer  202 ). Preferably, the diameters of the capillary tubes  208  may vary so as to simulate different types of patterned surfaces of the wafer  202  or different processes so that optimum polishing performance can be achieved. 
     In the embodiment of FIG. 3B-2 slurry is supplied to a slurry distribution manifold  210  through a slurry guide inlet  212  and is subsequently provided to a sacrificial retaining ring  201   a . It must be appreciated that although in this embodiment only one slurry guide inlet  212  is depicted, any number of slurry guide inlets  212  may be utilized to introduce slurry to the CMP system. Furthermore, the slurry guide inlets  212  may be made from any material and be in any shape or form (i.e., tubes, channels, etc.). 
     In one implementation, initially, slurry is supplied to the slurry distribution manifold  210  via a slurry guide inlet  212 . Thereafter, slurry distribution manifold  210  provides slurry to the capillary tubes  208  substantially evenly, which in turn, guide slurry to the polishing interface. As a result, slurry usage is minimized by uniformly injecting sufficient quantity of slurry into the polishing pad surface  203   a  at the point of use. Consequently, the polishing pad surface  203   a  is saturated with slurry. Thus, as the polishing pad surface  203   a  moves across the wafer  202 , sufficient quantity of slurry will be present at the edge of the wafer  202 , the center of the wafer  202 , and the low-pressure regions. 
     The significance of the capillary tubes  208  in facilitating the saturation of the polishing pad  203  with slurry becomes apparent at the instances when the polishing pad surface  203   a  is polishing the center of the wafer  202 . Conventionally, due to insufficient presence of slurry at the center of the wafer  202 , the removal rate of materials may decrease as the polishing pad surface  203   a  moves away from the edge of the wafer  202  and approaches the center of the wafer  202 . However, in this embodiment, the SRR  201   a  saturates the polishing pad surface  203   a  by uniformly distributing slurry to the polishing pad surface  203   a . As such, while the surface of the polishing pad  203   a  approaches the center of the wafer  202 , the polishing pad surface  203   a  contains substantially sufficient quantity of slurry so that the removal rate remains substantially flat from the edge of the wafer  202  to the center of the wafer  202 . 
     The structure of a retaining ring  201  and the relative position of a sacrificial retaining ring  201   a  with respect to the retaining ring support  201   b  is shown in FIG.  4 A. As depicted, the retaining ring support  201   b  is a contiguous ring which diameter is substantially equivalent to the diameter of the wafer  202 . In one embodiment, the retaining ring support  201   b  can be constructed from metal (i.e., Stainless Steal, Aluminum, or any other kind of alloy) or plastic. The retaining ring support  201   b  is configured to support the sacrificial retaining ring  201   a , which consists of a plurality of capillary tube array units  201   a ′. Although in this embodiment, the sacrificial retaining ring  201   a  is configured to be constructed from a plurality of capillary tube array units  201   a ′, it should be appreciated that similar to the retaining ring support  201   b , the sacrificial retaining ring  201   a  may be a contiguous ring. However, in this embodiment, in an attempt to simplify manufacturability, a plurality of capillary tube array units  201   a ′ have been utilized. Exemplary structures, such as capillary tube array units  201   a ′, can be custom ordered from Collimated Holes, Inc., of Campbell, Calif. 
     In one preferred implementation, the capillary tube array units  201   a ′ are configured to be placed on top of the retaining ring support  201   b . The capillary tube array units  201   a ′ are placed on top of the RRS  201   b  and adjacent to one another so as to ideally create a ring substantially in the size of the wafer  202 . The capillary tube array units  201   a ′ may be placed adjacent to one another in a manner so as to create an empty slot  214 . Alternatively, the capillary tube array units  201   a ′ may be placed next to one another so that no space exists between the two adjacent capillary tube array units  201   a ′. In a preferred embodiment, each capillary tube array unit  201   a ′ contains a plurality of capillary tubes  208  and is constructed from a material which has similar characteristic to those of the wafer  202  (i.e., Silicon) or the films typically present on the wafer  202 . Most importantly, the capillary tube array units  201   a ′ should preferably be constructed from a material that will not contaminate or introduce additional defects to the surface of the post-CMP wafer  202 . Thus, the capillary tube array units containing capillary tubes  208  are configured to simulate the patterned surface of the wafer  202  so as to extend the negative effects of the edge effects, edge burn-off effects, and pad rebound effects out of the surface of the wafer  202 , thereby achieving a less than a 3-millimeter wafer edge exclusion. 
     The three-dimensional FIG. 4B depicts the relative positions of multiple capillary tube array units  201   a ′ with respect to each other as well as a wafer  202 . In this embodiment, the capillary tube array units  201   a ′ are configured to be placed adjacent to each other in a manner so as to leave an empty space defined as a slot  214 . In a preferred implementation, slurry can be supplied to the polishing interface via the capillary tubes  208  as well as the slots  214  thus ensuring the presence of sufficient uniform quantity of slurry through out the surface of the wafer  202 . 
     The three-dimensional view of a capillary tube array unit  201   a ′ is depicted in FIG.  4 C. As shown, a capillary array unit length  201   a′   L  of the capillary tube array unit  201   a ′ is configured to have an approximate linear range of about 4 millimeters to about 37 millimeters, and a preferred linear length of about 12 millimeters. Similarly, a capillary tube array unit width  201   a ′ w  of the capillary tube array unit  201   a ′ is configured to have an approximate range of about 4 millimeters to about 37 millimeters, and a preferred width of about 12 millimeters. As illustrated, the capillary tubes  208  (e.g., holes) cover about fifty percent (50%) of a top surface of a capillary tube array unit  201   a ′. The approximate capillary tube diameter  208   a  of the capillary tube  208  ranges from about 10 micrometers to about 200 micrometers. The preferred inside diameter of the capillary tube  208  is preferably 50 micrometers. Likewise, a capillary tube height  208   b  approximately ranges millimeters, and a preferred capillary tube height  208   b  of about 6 millimeters. However, it should be appreciated that the diameter size and the height of the capillary tube  208  may vary depending on each particular process so that optimum polishing operation is achieved. 
     FIG. 5A is an illustration of one of several different mounting methods that can be used to place the sacrificial retaining ring  201   a  on the retaining ring support  201   b . As shown, the retaining ring support  201   b  secures all the individual capillary tube array units  201   a ′ together utilizing a contiguous ring finger  216 . In the embodiment of FIG. 5B, a sacrificial retaining ring  201   a  is held down to a retaining ring support  201   b  utilizing a fastener (e.g., a microscrews). Alternatively, in a different implementation, as depicted in FIG. 5C, a sacrificial retaining ring  201   a  is affixed to a retaining ring support  201   b  utilizing an adhesive substance (e.g., Epoxy glue). 
     Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. For instance, the embodiments are applicable to any substrate, such as, storage media disks, semiconductor wafers (e.g., 200 mm wafers, 300 mm wafers, etc.), and any other type of substrate requiring polishing, planarization, buffing, or other suitable preparation operations. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Technology Classification (CPC): 1