Patent Abstract:
An embodiment of the present invention is directed to a low power voltage reference circuit. The circuit includes a first circuit for generating a PTAT voltage without using an operational amplifier. The circuit also includes a second circuit for generating the reference voltage. The first and the second circuit do not utilize a resistor.

Full Description:
CLAIM OF PRIORITY UNDER 35 U.S.C. §119 
     The present Application for Patent claims priority to Indian Patent Application No. 395/CHE/2006 filed Mar. 7, 2006, and assigned to the assignee hereof and hereby expressly incorporated by reference herein. 
     The present Application for Patent claims priority to U.S. Provisional Application No. 60/793,489 entitled “A RESISTOR-LESS BANDGAP REFERENCE FOR MICRO-POWER MEMORIES and LOW-POWER LOW VOLTAGE MOSFET BASED VOLTAGE REFERENCE” filed Apr. 19, 2006, and assigned to the assignee hereof and hereby expressly incorporated by reference herein. 
    
    
     BACKGROUND 
     Conventionally, obtaining a sub-100 nA micro-power voltage reference for micro-power wide voltage range memory applications required very large matched resistors to achieve a low current, bipolar junction transistors (BJT), and an amplifier to generate a proportional to absolute temperature (PTAT) voltage.  FIG. 1  illustrates a circuit schematic for a conventional band-gap voltage reference circuit  100 . The large resistors (R 1  and R 2 ) are not generally suitable as micro-power components. Furthermore, the use of BJTs  102 - 106  and resistors R 1 -R 2  introduces BJT mismatch and resistor mismatch. 
     One purpose of a band gap voltage reference is to balance the negative temperature coefficient of a P-N junction with the thermal voltage (V T , where V T =KT/q). In  FIG. 1 , the reference voltage V bg  can be expressed as follows:
 
 V   bg   =V   eb106   +K   1   *V   T .  (1)
 
The amplifier  108  generates a PTAT voltage across resistor  110  by equalizing nodes A and B. The current through resistor  110  can be expressed as follows:
 
                         I   =       Δ   ⁢           ⁢     V     R   ⁢           ⁢   1           R   ⁢           ⁢   1                   =         V     eb   ⁢           ⁢   102       -     V     eb   ⁢           ⁢   104           R   ⁢           ⁢   1                     =           V   T     ⁢     ln   ⁡     (     I   /     I   S       )         -       V   T     ⁢     ln   ⁡     (     I       I   S     *     K   2         )             R   ⁢           ⁢   1         ,               =         V   T     ⁢     ln   ⁡     (     K   2     )           R   ⁢           ⁢   1                     (   2   )               
where the m-factor K 2  is equal to 8. V bg  can alternatively be expressed as:
 
 V   bg   =V   eb106   +I*R 2.  (3)
 
Upon substituting the expression of I from Equation 2 into Equation 3:
 
 V   bg   =V   eb106   +R 2 /R 1*ln(8)* V   T   (4)
 
Thus, it should be clear from Equation 4 that
 
 K   1   =R 2 /R 1*ln( K   2 )  (5)
 
Thus, establishing a band-gap reference voltage in the conventional art depended heavily on the values of R 1  and R 2 .
 
     Beta multiplier voltage references have been developed in the past that do not require the use of a BJT.  FIG. 2  is a circuit schematic for one such conventional circuit  200  for generating a beta multiplier voltage reference. When MOSFETS  202 - 208  operate in the sub-threshold region, the relationship between I DS  and V GS  depends strongly on Vt variations with respect to temperature. Thus I DS  at 90° C. would be greater than I DS  at 27° C. On the other hand, when MOSFETS  202 - 208  operate in the strong inversion region, the relationship between I DS  and V GS  depends strongly on Mobility (u n ) variations with respect to temperature. Thus I DS  at 90° C. would be less than I DS  at 27° C. 
       FIG. 3  is an I DS  vs. V GS  curve illustrating a MOSFET&#39;s transfer characteristic for two different temperatures. The principle behind beta multiplier voltage references is that there exists a temperature-insensitive value of V GS  for a given I DS . This point is denoted as point CP in  FIG. 3 . However, the temperature insensitivities of circuits such as circuit  200  strongly depend on MOSFET modeling and do not account for threshold voltage and mobility variations with respect to temperature or the variations in resistance. Consequently, these circuits require a significant amount of on-chip trimming. 
     SUMMARY 
     Accordingly, embodiments of the present invention eliminate the need for the resistors and the amplifier discussed above and also reduce the number of BJTs required for a voltage reference circuit. Embodiments also help to eliminate excessive dependence on MOSFET models so as to eliminate the need for on-chip trimming. 
     An embodiment of the present invention is directed to a low power voltage reference circuit. The circuit includes a first circuit for generating a PTAT voltage without use of an operational amplifier. The reference circuit also includes a second circuit for generating the reference voltage. The first and the second circuit are resistor-free, e.g., they do not use resistors. 
     Another embodiment of the present invention is directed to a circuit for generating a band-gap voltage reference including a first transistor coupled with a first output of a current reference circuit. The first transistor is operable to generate a bias current that is proportional to a reference current of the current reference circuit. The reference current is proportional to a temperature measurement. The novel circuit also includes a diode-connected transistor coupled with the first transistor and a second transistor coupled with said first transistor and said second transistor, wherein said reference voltage is generated at a drain of said diode-connected transistor. The reference voltage is generated at a drain of the diode-connected transistor. 
     This embodiment of the present invention is capable of achieving a band-gap reference of minimal variation (1.24V+/−20 mV, for instance) across a wafer in the temperature range of −45° C. to 95° C., for instance. The voltage reference is achieved with an ultra low sub-100 nA operating current. This embodiment is applicable for micro-power applications requiring low standby current, for example. 
     Another embodiment of the present invention is directed to a circuit for generating a low-power, low-voltage voltage reference including a PMOS transistor coupled with an output of a current reference circuit. The current reference circuit generates a reference current that is proportional to a temperature measurement. The novel circuit also includes a diode-connected transistor coupled with the PMOS transistor. The voltage reference is generated at a drain of said diode-connected transistor. 
     This embodiment has several benefits over conventional voltage reference circuits. For example, the circuit&#39;s dependency on MOSFET models has been minimized and depends on Vt modeling. The circuit also has low power requirements (≦300 nA of current, for instance). The circuit can also operate at low voltage (up to Vt+300 mV, for instance). Additionally, in one embodiment, the circuit&#39;s temperature coefficient is less than 200 ppm/° C. Furthermore, the reference may be adaptive with respect to process. 
     Thus, embodiments of the present invention are able to advantageously provide a reference voltage without using resistors or amplifiers. As a result, circuit area and operating current are reduced. Moreover, problems associated with resistor matching are eliminated. These advantages translate generally into lower cost and lower power consumption compared to conventional voltage reference circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of embodiments of the invention: 
         FIG. 1  shows a circuit schematic of a conventional band-gap voltage reference. 
         FIG. 2  shows a circuit schematic of a conventional beta multiplier voltage reference. 
         FIG. 3  is an I DS  vs. V GS  curve, illustrating a temperature insensitive point in a MOSFET&#39;s transfer characteristic. 
         FIG. 4  shows an exemplary circuit schematic of a resistor-less current reference, in accordance with an embodiment of the present invention. 
         FIG. 5  shows an exemplary circuit schematic of a resistor-less band-gap voltage reference, in accordance with an embodiment of the present invention. 
         FIG. 6  shows an exemplary circuit schematic of a low power, low voltage MOSFET based voltage reference, in accordance with an embodiment of the present invention. 
         FIG. 7  illustrates a schematic for a band-gap voltage reference circuit  420 A, in accordance with various embodiments of the present invention. 
         FIG. 8  illustrates a schematic for a voltage reference circuit  420 B, in accordance with various embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the claims. Furthermore, in the detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. 
       FIG. 4  illustrates a block diagram of a low power voltage reference circuit  400 , in accordance with various embodiments of the present invention. Circuit  400  may be well-suited for use in, for example, memory applications. In one embodiment, circuit  400  advantageously uses no resistors. As such, the problems associated with resistor mismatch of conventional designs are eliminated. Furthermore, circuit  400  has a smaller on-chip footprint than conventional circuits. 
     Circuit  400  includes a current reference circuit  410 . The current reference circuit  410 , which uses no resistors, is operable to generate a reference current. The current reference circuit  410  is also operable to generate a PTAT voltage (V ptat ) without using an operational amplifier. For example, in one embodiment, the current reference circuit  410  contains no operational amplifier. 
       FIG. 5  illustrates a block diagram of a current reference circuit  410 A, in accordance with various embodiments of the present invention, which may be used in circuit  400 . The current reference circuit  410 A includes a current mirror  510  for mirroring the reference current within the current reference circuit  410 A and to other circuits coupled with the current reference circuit  410 A. In one embodiment, the current reference circuit  410 A generates the output signal “bias_p,” which may be used by another circuit to mirror the reference current. The current reference circuit  410 A also includes a PTAT generator  520  coupled with the current mirror  510 . In one embodiment, the PTAT generator is operable to generate the PTAT voltage (V ptat ) without use of an operational amplifier. The PTAT generator may also be operable to generate the signal “bias_n,” which may be used to bias another circuit. The current reference circuit  410 A may also include a V-I converter  530  for converting a voltage signal to a current signal. In one embodiment, the V-I converter is coupled with the PTAT generator and is operable to convert V ptat  to a PTAT current (I ptat ). The reference current of the current reference circuit  410 A may then be based on I ptat . The current reference circuit  410 A may also include a bias circuit  540  for biasing the V-I converter  530 . 
       FIG. 6  illustrates a detailed schematic of a current reference circuit  410 B, in accordance with various embodiments of the present invention, which may be used in circuit  400 . In current reference circuit  410 B, transistors  610 ,  620 , and  630  act as a current mirror  510 A. Transistors  640  and  650  are coupled with transistors  610  and  620  respectively. In this configuration, transistors  640  and  650  operate in sub-threshold region and serve as a PTAT generator  520 A for generating the PTAT voltage V ptat , thereby eliminating the need for an amplifier. The current reference circuit  410 B also includes transistor  530 A, which is coupled with transistor  650 . As configured, transistor  530 A is operable to convert V ptat  to I ptat . In one embodiment, transistor  530 A is a MOSFET operating in the linear region and thus taking the place of a resistor. The current reference circuit  410 B may also include a transistor  540 A, which may be used to bias transistor  530 A. 
     Consequently, the reference current through the current reference circuit  410 B is:
 
 I= 8*β 530A *η 2   *V   T   2* ln 2 ( S )  (6)
 
Ignoring the constant terms in Equation 6, the relationship can be reduced to:
 
I∝β 530A *V T   2 .  (7)
 
Noting that β 530A ∝C OX *μ n , and μ n ∝T −1.6 , where T is Absolute Temperature, and V T ∝T, this relationship can be rewritten as:
 
I∝β 530A *V T   2 ∝C OX *T −1.6 *T 2 ∝C OX *T 0.4   (8)
 
     Thus, the current is nearly constant across the Transistor Process Voltage and Temperature. Therefore, this current can be used to advantageously bias a voltage reference stage  420  of the circuit  400 . 
     With reference again to  FIG. 4 , circuit  400  includes a voltage reference circuit  420  for generating a reference voltage V REF . Voltage reference circuit  420  advantageously uses no resistors. 
     In one embodiment, the reference voltage V REF  is a band-gap reference (e.g., V bg ).  FIG. 7  illustrates a schematic for a band-gap voltage reference circuit  420 A, in accordance with various embodiments of the present invention, which may be used by circuit  400 . Circuit  420 A includes a transistor  710 , which mirrors the current from circuit  410  (or circuit  410 A). The band-gap voltage reference circuit  420 A also includes a BJT  750 , which has an emitter voltage of V EB . Circuit  420 A also includes a diode-connected transistor  720 , which acts as a resistor. It should be appreciated that this configuration of transistor  720  therefore obviates the need for a resistor. The negative temperature variation due to the BJT  750  is cancelled by the positive temperature coefficient of the overdrive of transistor  720 . 
     In one embodiment, the band-gap voltage reference circuit  420 A also includes transistors  730  and  740 , which serve as a simple voltage follower and remove a V th  component of the drain voltage of transistor  720 . The reference voltage V bg  from  FIG. 7  can be expressed as:
 
 V   bg   =V   EB   +V   GS720   −V   GS730 .  (9)
 
Here, V GS720 =V t +√{square root over (2*4*I/β 720 )} and V GS730 ≈V t . On substituting these V GS  values into Equation 9,
 
 V   bg   =V   EB +√{square root over (2*4 *I/β   720 )}.  (10)
 
     In one embodiment, the transistors  710  and  720  of voltage reference circuit  420 A and transistor  530 A of current reference circuit  410 A are selected so that β 530A /β 720 =2 and K 3 =4. On substituting the I given in Equation 6 into Equation 10,
 
 V   bg   =V   EB   +η*V   T *ln(4)*√{square root over (2*2*4*8)} =V   EB +19.2 *V   T ≈1.24 V,   (11)
 
at room temperature. Thus, by appropriate selection of transistors  530 A and  720 , the β terms can be cancelled out. In one embodiment, transistors  640 ,  650 ,  530 A,  540 A, and  720 - 740  in  FIGS. 6-7  may be native NMOS transistors, which allows for lower supply voltage operation.
 
     Thus, this embodiment of the present invention is capable of achieving a band-gap reference of minimal variation (1.24V+/−20 mV) across a wafer in the temperature range of −45° C. to 95° C., for instance. The voltage reference is achieved with an ultra low sub-100 nA operating current. This embodiment is applicable for micro-power applications requiring low standby current, for example. 
       FIG. 8  illustrates a schematic for a voltage reference circuit  420 B, in accordance with various embodiments of the present invention, which may be used in circuit  400 . Voltage reference circuit  420 B is particularly useful in low power applications and low voltage applications. It should be appreciated that voltage reference circuit  420 B does not require a resistor or a BJT to generate the voltage reference V REF . For example, transistor  820  is diode-connected and therefore operates similar to a resistor. Moreover, because BJTs can become inaccurate at sub-nA currents (e.g., 10 nA), it is therefore advantageous to generate V REF  without using a BJT. In one embodiment, the current reference circuit  410 B of  FIG. 6  is connected to the voltage reference circuit  420 B of  FIG. 8  at the bias_p node. From  FIG. 8 , the reference voltage V REF  can be expressed as:
 
 V   REF   =V   t +√{square root over (2 *I/β   820 )}  (12)
 
Upon substituting I from Equation 4 into Equation 10,
 
 V   REF   =V   t +√{square root over (2*8*β 530A /β 820 *ln 2 ( S ))}* V   T   (13)
 
 V   REF   =V   t   +K   1   *V   T   (14)
 
     By changing the sizes of transistors  530 A and  820 , the value of K 1  can be manipulated to cancel out the V t  variations with respect to temperature. Assuming that V t  variation with respect to temperature is mainly with Bulk Fermi Potential (2φ F ) and mathematics, the following expression for V REF  can be derived:
 
 V   REF   =V   FB   +Q   B   /C   OX   +V   G0 +3 V   T0   (15)
 
Where V G0  represents the extrapolated silicon band-gap at T=0° K. and V T0  represents the thermal voltage at room temperature. It is appreciated that the expression for the reference voltage in Equation 15 is substantially independent of temperature. The temperature dependent term (2φ F ) in the threshold voltage (V t ) is cancelled with weighted PTAT voltage from the current reference circuit  410 B. V REF  is also substantially independent of external voltage because it is driven by the self-biased current reference  410 B. However, V REF  does depend on process (1/C OX ), which is adaptive. In other words, the circuit will produce a higher V REF  at slow PMOS and slow NMOS, and it will produce a lower V REF  at fast PMOS and fast NMOS.
 
     This embodiment has several benefits over conventional voltage reference circuits. For example, the circuit&#39;s dependency on MOSFET models has been minimized and depends on Vt modeling. The circuit also has low power requirements (≦300 nA of current). The circuit can also operate at low voltage (up to Vt+300 mV). Additionally, in one embodiment, the circuit&#39;s temperature coefficient is less than 200 ppm/° C. Furthermore, the reference may be adaptive with respect to process. 
     Thus, embodiments of the present invention are able to provide a reference voltage without using resistors or amplifiers. As a result, circuit area and operating current are reduced. Moreover, problems associated with resistor matching are eliminated. These advantages translate generally into lower cost and lower power consumption compared to conventional voltage reference circuits. 
     The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Technology Classification (CPC): 6