Patent Abstract:
A variable-gain current conveyor-based instrumentation amplifier without introducing distortion. An exemplary variable-gain instrumentation amplifier includes a first dual-output transconductance amplifier (DOTA) (i.e., current conveyor) that receives a first input voltage, a second DOTA that receives a second input voltage, a first resistive element connected between the first and second DOTA, an amplifier connected to the second DOTA at an inverting input, and a second resistive element that connects the second DOTA and the inverting input to an output of the amplifier. At least one of the resistive elements is a variable resistive element.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    CMOS transmission gate (T-gate) switches introduce distortion when used in an instrumentation amplifier (IA). A prior-art transmission gate circuit is shown in  FIG. 1 . Transistors MN 1  and MP 1  form the CMOS switch between pins “IN” and “OUT”. This switch is controlled by the “PGATE” and “NGATE” voltages, which are driven out of phase and rail to rail (0-5V) by two digital inverters. 
         [0002]    The off-resistance of this switch is essentially infinite (&gt;1000 meg). The on-resistance is typically between 50 and 5000 ohms, depending on design, and varies with process, supply voltage, and temperature (PVT). Furthermore, the on-resistance also varies with the voltage present at the “IN” and “OUT” terminals. The magnitude of this non-linear variation in resistance is typically significant, on the order of +/−10% of the nominal on-resistance over the full range of applied voltages in a given system. In amplifier circuits where low signal distortion is important, the effects of this non-linear on-resistance must always be mitigated. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a variable-gain current conveyor-based instrumentation amplifier without introducing transmission gate distortion. 
         [0004]    An exemplary variable-gain instrumentation amplifier includes a first current conveyor that receives a first input voltage, a second current conveyor that receives a second input voltage, a first resistive element connected between the first and second current conveyors, an amplifier connected to the second current conveyor at an inverting input, and a second resistive element that connects the second current conveyor and the inverting input to an output of the amplifier. At least one of the resistive elements is a variable resistive element. 
         [0005]    In one aspect of the invention, the current conveyors are dual-output trans conductance amplifiers (DOTAs). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings: 
           [0007]      FIG. 1  is a transmission gate circuit formed in accordance with the prior art; 
           [0008]      FIGS. 2 through 4  are conceptual circuits used to show some of the theory behind the present invention; and 
           [0009]      FIGS. 5-1  through  5 - 3 , and  6  through  8  show exemplary current-conveyor instrumentation amplifier circuits formed in accordance with various embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0010]      FIG. 2  illustrates an instrumentation amplifier (IA)  20 . For clarity, dual-output transconductance amplifier (DOTA) symbols  26 ,  28  are used to represent current conveyors. One of ordinary skill would understand how to apply current conveyors to the IA  20 . The gain of the IA  20  is defined by the following equation: 
         [0000]        A   V   =V   OUT /( V   1 - V   2 )= R   2   /R   1   (1)
 
         [0011]    As shown in  FIG. 3 , a IA  40  includes an additional resistor, R 3 , between resistor R 1  and the DOTA  26 . The voltage gain remains the same, A v  =R 2 /R 1 , because there is no significant current flowing through the resistor R 3 , especially when using CMOS amplifiers, and no voltage is developed across the resistor R 3 . 
         [0012]    Also in the IA  40 , a resistor R 4  is added between the resistor R 1  and the DOTA  26 . The gain remains the same for small values of the resistor R 4 . In this case, the same current that flows through the resistor R 1  also flows through the resistor R 4  but the voltage that develops across the resistor R 4  does not affect overall gain until the DOTA  26  saturates. For positive input voltages (V 1 -V 2 &gt;0), this happens when the sum of the voltages across the resistors R 4  and R 1  is greater than the voltage across the resistor R 2 . Because the same current, I, flows through all three resistors, this is equivalent to saying that the sum of the resistors R 4  and R 1  must be less than the value of resistor R 2  to avoid amplifier saturation. In other words: 
         [0000]        R   4   +R   1   &lt;R   2 ,  (2)
 
         [0000]    where it is assumed that all amplifiers are connected to the same power supply voltages, all amplifiers have the same saturation characteristics, and one of the inputs is at the ground potential (either V 1 =0 or V 2 =0, the worst case). This is equivalent to the condition: 
         [0000]        R   4   &lt;R   2   −R   1   (3)
 
         [0013]    Because A v =R 2 /R 1 , equation (3) is equivalent to equation (4) by substitution. 
         [0000]        R   4   &lt;R   1 ( A   v −1)  (4)
 
         [0014]    In most practical systems, the desired voltage gain is greater than unity and reasonable values of the resistor R 4  will not have any effect on the gain of the IA circuit  40 . In the same way, resistor R 5  does not affect IA voltage gain and small values of resistor R 6  (R 6 &lt;R 2 −R 1 ) do not affect gain, either. 
         [0015]    In a similar manner,  FIG. 4  is a IA  60  that includes vestigial resistors R 7  and R 8  that are added to the negative input of the amplifier  24  without affecting the voltage gain of the IA  60  (A v =R 2 /R 1 ). In the IA  60 , reasonable values of the resistor R 7  do not affect the gain because there is no current flowing through the resistor R 7  and the voltage across the resistor R 7  is insignificant (zero for CMOS amplifiers). However, if the value of the resistor R 7  is very large, it may affect high-frequency AC performance. 
         [0016]    The gain of the IA  60  is also not affected by the value of the resistor R 6 , even though there is current flowing through the resistor R 8 , as long as the value is small enough to prevent saturation of the DOTA  26  output. Given the assumption that both amplifiers  26  and  24  are connected to the same power supply, have the same saturation characteristics, and that the node common to the resistors R 2 , R 7 , and R 8  is at zero volts (a virtual ground), then this condition is met when the voltage across the resistor R 8  is less than or equal to the voltage across the resistor R 2 . Because the same current, I, flows through both the resistors R 2  and R 8 , the gain of the IA  60  will not be affected by the value of the resistor R 8 , as long as the value of the resistor R 8  is less than or equal to the value of the resistor R 2 . 
         [0000]      R 8 ≦R 2   (5)
 
         [0017]    In one embodiment, as shown in  FIG. 5-1 , the gain of IA  120  is changed using a three-terminal potentiometer  124 . A potentiometer  122  is positioned between two DOTAs  126 ,  128  that receive two different input voltages (V 1 , V 2 ). The output of the second DOTA  128  is connected to the inverting input of a noninverting amplifier  30 . Functionally, all three circuits from  FIGS. 5-1  through  5 - 3  have the following gain. Current conveyors are shown in U.S. Pat. Nos. 8,081,030 and 7,893,759, which are hereby incorporated by reference. 
         [0000]        A   v   =R   2   /R   1A   (6)
 
         [0018]    The potentiometer  122  is modeled as a pair of resistors (R 1A +R 1B ) such that the sum of the pair is a constant resistance (R 1 =R 1A +R 1B ). When the wiper of the potentiometer  122  is at one extreme, the resistance between the wiper and the current-carrying end of the potentiometer  122  is a maximum of R 1  (R 1A =R 1  and R 1B =0). In this position, the gain of the IA  120  is equal to R 2 /R 1 . When the wiper is at the other extreme, where R 1A =0 and R 1B =R 1 , the gain of the IA is, in theory, R 2 /0 or infinity. As a practical matter, two effects will prevent the gain from actually going to infinity: (1) the open-loop gain of the input amplifiers and (2) the nonzero wiper contact resistance. Still, very high values of gain, on the order of 1000 or more are feasible. 
         [0019]    As shown in  FIG. 5-2 , an IA  140  is configured similarly to the IA  120 , except that the potentiometer  122  receives the wiper from the second DOTA  128 . 
         [0020]    As shown in  FIG. 5-3 , a IA  150  includes two potentiometers  152 ,  154 , each having a maximum resistance of one half of the maximum resistance of the potentiometer  122  ( FIGS. 5-1 ,  5 - 2 ). The IA  150  has the advantage that the values of the noncurrent-carrying resistor segments ½R 1B  may be matched if the two potentiometers  152 ,  154  are ganged together. In this case, whatever secondary effect these resistor segments have on the high-frequency AC response of the input amplifiers (i.e., DOTAs  126 ,  128 ) is equalized and the overall effect on bandwidth is minimized. 
         [0021]      FIG. 6  shows an IA  170  that includes an array  172  of six resistor segments that replace the resistor R 1  from the IAs shown in  FIGS. 2 through 4 . This resistor array  172  is connected to CMOS transmission gates SW 1A  thru SW 3B  or some other active switch. The array  172  of resistor segments and digitally controlled T-gates is implemented on an integrated circuit; whereas the potentiometer approach is not. While this approach is not continuous and limits the IA gain to certain discrete steps, arrays of hundreds or thousands of resistor segments are feasible. In one embodiment, a digital logic block controls the CMOS transmission gates. The digital logic block may, in turn, be controlled by a microprocessor and computer program based on user input. 
         [0022]    In the IA  170  there are three gain settings. Let A 1  denote the first gain setting (only switches SW 1A , SW 1B  are on) where A 1 =R 2 /R i . Then, the second gain setting, with only the switches SW 2A , SW 2B  conducting, is A 2 =R 2 /R 1 /2=2 A 1 . In a similar manner, the third gain setting, with only the switches SW 3A , SW 3B  on, is A 3 =R 2 /R 1 /4=4 A 1 . To summarize, these three gain settings are related, as shown in Table 1. In one embodiment, the IA  170  does not require an array of equal-value resistor segments. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Switch setting 
                 Relative gain 
               
               
                   
                   
               
             
             
               
                   
                 SW 1A , SW 1B   
                 A 1   
               
               
                   
                 SW 2A , SW 2B   
                 2 A 1   
               
               
                   
                 SW 3A , SW 3B   
                 4 A 1   
               
               
                   
                   
               
             
          
         
       
     
         [0023]    A significant consideration is the on-state resistance of the CMOS transmission gates  172  used as the switches shown in  FIG. 6 . The on-state resistance is not critical as long as it is less than R 2 −R 1A . This requirement is most difficult to meet (smallest resistance) for the switches SW 1A , SW 1B  and becomes progressively easier to meet for the switches SW 2A , SW 2B  and then SW 3A , SW 3B  which benefit from progressively larger values of gain. 
         [0024]    The transmission gates do not cause distortion in the IA  170  as long as the peak on-resistance is less than R 2 −R 1 . Transmission gates are not typically used in gain switching circuits where direct current flows through them because their on-resistance varies with the operating voltage. 
         [0025]    As shown in  FIG. 7 , an IA  200  includes a common three-terminal potentiometer  204  for changing the gain of the circuit  200 . The potentiometer  204  is located between the second DOTA  128  and the amplifier  130 . The gain of the IA  200  is given by equation (7) below where a first resistor segment R 2A  of the potentiometer  204  carries direct current and a second resistor segment R 2B  does not carry direct current. 
         [0000]      AV=R 2A /R 1   (7)
 
         [0026]    In one embodiment, the potentiometer  204  is set so that the first resistor segment R 2A =0 and the second resistor segment R 2B =R 2 . Thus, the gain of the IA  200  is zero: A v =0/R 1 =0. At the other extreme, the potentiometer  204  is set so that first resistor segment R 2A =R 2  (see  FIG. 2 ) and the second resistor segment R 2B =0. Thus, the gain of the IA  200  is the same as the nominal gain using fixed resistors: A v =R 2 /R 1 . As a practical matter, the gain of the IA  200  cannot go to exactly zero, due to the finite terminal resistance of the potentiometer  204 . However, the gain may easily be reduced by three or four orders of magnitude from the nominal gain. 
         [0027]    As shown in  FIG. 8 , an IA  240  includes an array  244  of three resistor segments and transmission gates, or other switches. Three possible gain settings are listed in Table 2 below where the nominal gain, A 1 , is R 2 /R 1 . 
         [0028]    The IA  240  allows: 
         [0000]    
       
         
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Switch setting 
                 Relative gain 
               
               
                   
                   
               
             
             
               
                   
                 SW 3   
                 A 1   
               
               
                   
                 SW 2   
                  1/2 A 1   
               
               
                   
                 SW 1   
                  1/4 A 1   
               
               
                   
                   
               
             
          
         
       
     
         [0029]    In one embodiment, the features shown in  FIGS. 5 through 8  may be combined to construct IA circuits whose gains may be varied over a very wide range of values: from zero to infinity with ideal components. Even with real components, the gain may be varied by at least six orders of magnitude. Furthermore, this may be accomplished with a high degree of gain accuracy and no amplifier distortion. 
         [0030]    While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.

Technology Classification (CPC): 7