Patent Abstract:
A method of fabricating a semiconductor device includes laminating a dielectric sheet on a substrate and forming a via opening in the dielectric sheet. The method further includes depositing a conductive material into the first via opening.

Full Description:
FIELD OF THE INVENTION  
         [0001]    The present invention is directed to integrated circuit processing. More particularly, the present invention is directed to the fabrication of interconnects on an integrated circuit.  
         BACKGROUND INFORMATION  
         [0002]    Modern integrated circuits use conductive interconnects to connect the individual devices on a chip or to send and/or receive signals external to the chip. Popular interconnect materials include copper, aluminum, copper alloys, and aluminum alloys. In order to accommodate desired interconnect densities, multiple layers of interconnects, referred to as “metallization layers” may be used.  
           [0003]    A typical method of forming an interconnect, particularly a copper interconnect, is a damascene process. A common conventional damascene process usually involves the following, as illustrated by FIG. 1:  
           [0004]    (1) Deposit an etch stop  120  on a substrate  110 .  
           [0005]    (2) Deposit a dielectric layer  130 . Because dielectric layer  130  will ultimately fill the space between interconnects within a particular layer, it may be referred to as an interlayer dielectric or ILD.  
           [0006]    (3) Form a trench  132  having via openings  134  in the dielectric layer  130  and etch stop  120  to an underlying layer, such as substrate  110 . For example, via openings  134  may expose the source, drain, or gate of a transistor. A hard mask  140  may be used to form the trench, but is not necessary. Structure  11  shows a partially fabricated interconnect layer after step 3.  
           [0007]    (4) Line the trench  132  and via opening  134  with a barrier layer of a refractory material, for example titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). The barrier layer serves to inhibit the diffusion of the interconnect material that will subsequently be introduced in the via and trench into the interlayer dielectric.  
           [0008]    (5) Deposit a suitable seed material on the wall or walls of trench  132  and via opening  134 . Suitable seed materials for the deposition of copper interconnect material include copper (Cu), nickel (Ni), and cobalt (Co).  
           [0009]    (6) Deposit an interconnect material  150 , such as copper, into the trench and via openings. Deposition methods include electroplating and physical deposition. Structure  12  shows a partially fabricated interconnect layer after step 6.  
           [0010]    (7) Planarize to remove any excess interconnect material and to form interconnect  160 . Structure  13  shows an interconnect layer after step 7.  
           [0011]    Steps 1 through 7 may be repeated multiple times to fabricate multiple layers of metallization. After the final layer of metallization is fabricated, a dielectric material may be deposited to isolate the structure.  
           [0012]    Although many different materials have been used as interconnect materials, copper has become a popular choice for various reasons. For example, copper has a low resistively and a high melting point compared to aluminum or aluminum alloys. Low resistively enables the use of thinner interconnects without sacrificing conductivity, and high melting point decreases susceptibility to migration during operation, which can lead to undesirable voids in the interconnect.  
           [0013]    As chip processing technology advances and the packing density of devices increases, it is desirable to similarly increase the density of interconnects. This may be achieved by reducing the interconnect metal pitch, and by increasing the number of metallization levels. However, reduced interconnect pitch and/or increased metallization levels may lead to problems such as increased capacitance between interconnects on the same plane, and between interconnects between layers. Increased parasitic capacitance can cause undesirable effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk.  
           [0014]    One way to reduce the unwanted capacitance between the interconnects is to increase the distance between them. However, increased spacing between interconnects has adverse consequences such as increased area requirements, and corresponding increases in manufacturing costs.  
           [0015]    Based on the foregoing, there is a need for a simplified fabrication method to form damascene interconnects and a method to reduce capacitance between interconnects. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 illustrates a common conventional damascene process.  
         [0017]    [0017]FIG. 2 illustrates a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.  
         [0018]    [0018]FIG. 3 illustrates a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0019]    One embodiment of the present invention utilizes a laminate sheet as an ILD when creating a damascene structure. The laminate sheet can avoid the need for a diffusion barrier between layers, and can be removed, leaving behind an air gap that functions as an improved dielectric. The use of a laminate sheet also simplifies the fabrication process.  
         [0020]    [0020]FIG. 2 illustrates a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.  
         [0021]    Structure  14  has a substrate layer  110 , and a preexisting interconnect layer that includes an etch stop diffusion barrier  220 , interconnects  231 ,  232 , and dielectric  230 . The preexisting layer may have been formed by prior art methods, or by the methods in accordance with the present invention.  
         [0022]    A diffusion barrier  221  is placed over the preexisting layer. In other embodiments, a diffusion barrier is not used and the new interconnect layer placed directly on top of the preexisting layer.  
         [0023]    A sheet of dielectric film  210  in the form of a low dielectric constant laminate sheet is laminated on diffusion barrier  221 . In one embodiment, roller bars  201 ,  202  laminate laminate sheet  210  on diffusion barrier  221 . In other embodiments, laminate sheet  210  may be laminated using a press operation. Laminate sheet  210  can be formed from a single ILD lamella, a multilayer lamella, or a composite material.  
         [0024]    Trenches  310 ,  311  having via openings are formed in laminate sheet  210 , as shown on structure  15 . Laminate sheet  210  is also trimmed and cured.  
         [0025]    Finally, a suitable seed material is placed on the walls of trenches  310 ,  311  and an interconnect material  320 ,  321 , such as copper, is deposited, as shown on structure  16 . Interconnect material  320 ,  321  may be polished or otherwise treated to form a conductive interconnect layer.  
         [0026]    The use of laminate sheet  210  to form structure  16  provides advantages over prior art that applies an ILD by the use of expensive film deposition such as chemical vapor deposition (“CVD”) or spin-on techniques.  
         [0027]    [0027]FIG. 3 illustrates a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. Structure  17  has substrate  110 , diffusion barrier  510 , and interconnects  520 ,  521  that are formed similar to interconnects  320 ,  321  except that the laminate sheet is removed after interconnects  520 ,  521  are formed.  
         [0028]    A laminate sheet  525  is laminated on interconnects  520 ,  521  by rollers  201 ,  202 , as shown on structure  18 . As shown, a diffusion barrier or etch stop is not used or needed between interconnects  520 ,  521  and laminate sheet  525 , because laminate sheet  525  prevents electro-migration. The elimination of a diffusion barrier has the desirable effect of lowing the dielectric constant between interconnects.  
         [0029]    Interconnects  620 ,  621  are formed in laminate sheet  525  through the use of a diffusion barrier  610 , as shown on structure  19 .  
         [0030]    Finally, laminate sheet  525  and diffusion barrier  610  is removed on structure  20 . As shown, structure  20  now includes two layers of interconnect devices  520 ,  521 ,  620 ,  621 , and a dielectric between interconnects that is formed of air. Therefore, parasitic capacitance between the interconnect devices is reduced compared to prior art devices having ILD layers.  
         [0031]    Additional metalization layers can be formed on structure  20  in a similar manner as previously described.  
         [0032]    In another embodiment, only the trench level portion of laminate sheet  525  (i.e., the portion above dotted line  570  of structure  19 ) is removed, while the via level portion (i.e., the portion below dotted line  570 ) is not removed. The portion of laminate sheet  525  that remains provides thermomechanical stability to the vias of interconnects  620 ,  621 . The removal of the trench level portion provides a low dielectric constant at the trench level.  
         [0033]    In another embodiment, a thin metal layer, or metal shunt, is deposited on interconnects  620 ,  621 . The metal shunt can also be added on top of all interconnects of a layered device. The metal shunt improves the electromigration performance of the device and can function as an etch stop layer. In one embodiment, the metal shunt is formed of cobalt and is deposited using an electroless plating method.  
         [0034]    As described, a multi-layer damascene interconnect can be manufactured using a removable laminated sheet. The use of a laminated sheet provides a simplified manufacturing procedure and an improved dielectric between interconnects.  
         [0035]    Several embodiments of the present invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.

Technology Classification (CPC): 7