Patent Abstract:
The level shifter comprises a coupling block, a PMOS switch, a first PMOS transistor and a second PMOS transistor. The coupling block receives a first signal and a second signal to generate a first control signal and a first reference voltage. The first signal and the second signal are of opposite phases. The PMOS switch is controlled by the first control signal to choose the first reference voltage or a second reference voltage to be a second control signal. The first PMOS transistor is controlled by the first control signal. The second PMOS transistor is controlled by the second control signal. The connection point between the second PMOS transistor and the first PMOS transistor outputs an output signal.

Full Description:
[0001]     This application claims the benefit of Taiwan application Ser. No. 94101920, filed Jan. 21, 2005, the subject matter of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention relates in general to a level shifter, and more particularly to a level shifter manufactured according to Low Temperature Poly-Silicon technology.  
         [0004]     2. Description of the Related Art  
         [0005]     The Low Temperature Poly-Silicon (LTPS) manufacturing technology of display is featured by integrating peripheral circuits and manufacturing directly on the glass substrate, so that signal transmission is sped up and a higher resolution is achieved. However, the LTPS technology is more complicated than amorphous silicon (a-Si) manufacturing process, hence resulting in a decrease in production efficiency and an increase in manufacturing costs. The key element of LTPS is more in terms of Complementary Metal-Oxide Semiconductor (CMOS). If the CMOS transistor is replaced by a P channel Metal-Oxide Semiconductor (PMOS) transistor, the number of masks used can be reduced and the manufacturing process can be further simplified.  
         [0006]     In order to integrate the circuits and reduce the costs, applying the circuits whose design incorporates PMOS transistors to the LTPS manufacturing technology has become a focus in today&#39;s design of display, and level shifter is one of the circuits used in the display. Referring to  FIG. 1 , a conventional level shifter is shown. An output signal Output is generated according to a voltage VDD (0 V), a VSB (−20 V), a VSS (−30 V), a VSA (−15 V), and an input signal Input. The oscillation of the input signal Input ranges from 0 to −10 V, while the oscillation of the output signal Output ranges from 0 to −20 V. For the oscillation of the output signal Output to range from 0 to −20 V, a voltage VSS of −30 V and a voltage VSA of −15 V are further added. However, adding an even negative voltage leads to additional power consumption, and is not as practical as expected.  
         [0007]     Referring to  FIG. 2 , another conventional level shifter is shown. The level shifter includes several transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , T 7 , T 8 , T 9  and T 10 , wherein each of the transistors T 1  to T 10  has a drain D, a source S, and a gate G. The level shifter of  FIG. 2 , which is divided into an input stage, a switch stage, and an output stage, generates voltages V 1 , V 2 , V 3  and V 4  to be applied onto the circuits of various stages according to voltages VSS and VDD, and the functions of input signals In 1  and In 2 . When functioning, the transistors T 7  and T 8  form a current path from the voltage VDD to the voltage VSS, and generates a static current, hence resulting in lasting power consumption. The transistors T 1  and T 2  as well as the transistors T 3  and T 4  also have the same problems.  
         [0008]     However, if the above level shifter is applied in a portable electronic product such as the display panel of a mobile phone, the disadvantage of power consumption will shorten battery duration, jeopardizing the competitive power of the electronic product.  
       SUMMARY OF THE INVENTION  
       [0009]     It is therefore an object of the invention to provide a level shifter manufactured according to Low Temperature Poly-Silicon (LTPS) manufacturing method. The level shifter includes a coupling block, a PMOS switch, a first PMOS transistor, and a second PMOS transistor. The coupling block receives a first signal and a second signal to generate a first control signal and a first reference voltage. The first signal and the second signal are inverted. The PMOS switch is controlled by the first control signal to choose the first reference voltage or a second reference voltage to be a second control signal. The first PMOS transistor is controlled by the first control signal. The second PMOS transistor is controlled by the second control signal. The connection point between the second PMOS switch and the first PMOS switch outputs an output signal whose level is obtained by shifting the level of the first signal.  
         [0010]     Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a conventional level shifter;  
         [0012]      FIG. 2  is another conventional level shifter;  
         [0013]      FIG. 3  is a circuit diagram of a level shifter according to a first embodiment of the invention;  
         [0014]      FIG. 4  is an example of a circuit diagram of the one-way conducting device;  
         [0015]      FIG. 5  is another example of a circuit diagram of the one-way conducting device  
         [0016]      FIG. 6  is a signal time sequence diagram of a level shifter according to a first embodiment of the invention;  
         [0017]      FIG. 7  is a circuit diagram of a level shifter according to a second embodiment of the invention; and  
         [0018]      FIG. 8  is a signal time sequence diagram of a level shifter according to a second embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     Referring to  FIG. 3 , a circuit diagram of a level shifter according to a first embodiment of the invention is shown. The present embodiment provides a level shifter  300  manufactured according to Low Temperature Poly-Silicon (LTPS) manufacturing method. The level shifter  300  includes a PMOS switch M 31 , a PMOS transistor M 32 , a PMOS transistor M 33  and a coupling block  310 . The gate of the PMOS switch M 31  receives a signal S 32 , while the drain of the PMOS switch M 31  provides a first reference voltage. The PMOS switch M 31  chooses the first reference voltage or a second reference voltage to be a signal S 33 , while the source of the PMOS switch M 31  receives the signal S 31  having the level of the first reference voltage. The gate of the PMOS transistor M 32  receives the signal S 32 , while the source of the PMOS switch M 32  receives the signal S 31 . The gate of the PMOS transistor M 33  is coupled to the drain of the PMOS switch M 31  and receives the signal S 33 , the drain of the PMOS transistor M 33  is coupled to a low voltage V 31 , while the source of the PMOS transistor M 33  is coupled to the drain of the PMOS transistor M 32  and generates an output signal X 3 . The coupling block  310 is for receiving the signals S 31  and S 32  to output the second reference voltage.  
         [0020]     The coupling block  310  includes a PMOS transistor M 34 , a PMOS transistor M 35 , a capacitor C 31 , a capacitor C 32  and a one-way conducting device  311 . The source of the PMOS transistor M 34  is coupled to a low voltage V 31 . The gate of the PMOS transistor M 35  is coupled to the drain of the PMOS transistor M 34 , the drain of the PMOS transistor M 35  is coupled to the gate of the PMOS transistor M 34 , while the source of the PMOS transistor M 35  is coupled to the low voltage V 31 . One end of the capacitor C 31  receives the signal S 31 , while another end of the capacitor C 31  is coupled to the drain of the PMOS transistor M 34 . One end of the capacitor C 32  receives the signal S 32 , while another end of the capacitor C 32  is coupled to the drain of the PMOS transistor M 35 . The input end of the one-way conducting device  311  is coupled to the drain of the PMOS transistor M 34 , while the output end of the one-way conducting device  311  is coupled to the drain of the PMOS transistor M 31  and generates the second reference voltage.  
         [0021]     The one-way conducting device  311  can be achieved as below. Referring to  FIG. 4 , an example of a circuit diagram of the one-way conducting device is shown. The one-way conducting device  311  includes N serially connected diodes D 1  to DN. The positive end of each diode D is coupled to the negative end of previous diode D, the positive end of the diode D 1  is the input end of the one-way conducting device  311 , and the negative end of the diode DN is the output end of the one-way conducting device  311 . Referring to  FIG. 5 , another example of a circuit diagram of the one-way conducting device is shown. The one-way conducting device  311  includes M serially connected PMOS transistors K 1  to KM. The drain of each PMOS transistor K is coupled to the gate of the PMOS transistor K as well as the source of the previous PMOS transistor K. The drain of the PMOS transistor K 1  is the input end of the one-way conducting device  311 . The source of the PMOS transistor KM is the output end of the one-way conducting device  311 . However, the number of diodes or PMOS transistors disposed in the one-way conducting device  311  does not necessarily to be in plural form. Any number of diodes or PMOS transistors that provides a reference voltage and one-way conductivity will do.  
         [0022]     In the present embodiment, the signal S 31 , a clock signal of 9 to 0 V, and the signal S 32 , a clock signal of 9 to 0 V, are inverted. The low voltage V 31  is −6 V. Referring to both  FIG. 3  and  FIG. 6  at the same time,  FIG. 6  is a signal time sequence diagram of a level shifter according to a first embodiment of the invention. Voltage VO 32  is the voltage at the drain of the PMOS transistor M 34 , and voltage VO 33  is the voltage at the drain of the PMOS transistor M 35 . The operations of the circuit inside the coupling block  310  are elaborated below. During time period t 1 , the signal S 31  is 9 V, while the signal S 32  is 0 V. Meanwhile, the voltage VO 32  and voltage VO 33  are at initial state and are hard to define, hence are assumed to be close to the low voltage V 31  which is −6 V.  
         [0023]     During time period t 2 , the signal S 31  is 0 V, and the signal S 32  is 9 V. Due to the coupling effect of the capacitor C 31 , the voltage drop is fixed. During time period t 1 , the voltage drop is equal to the difference between 9 V and −6 V which is 15 V due to the voltage VO 32  and the signal S 31 . During time period t 2 , the signal S 31  is reduced to 0 V and the voltage VO 32  is reduced to −15 V, so that the PMOS transistor M 35  is conducted and that the voltage VO 33  is equal to −6 V. During time period t 3 , the signal S 31  is 9 V, while the signal S 32  is 0 V. The voltage VO 33  is reduced to −15 V due to the coupling effect of the capacitor C 32 , so that the PMOS transistor M 34  is conducted and that the voltage VO 32  is −6 V. During time period t 4 ′, the voltage VO 32  is −15 V. Hence, the voltage VO 32  and the signal S 31  are in phase. When the signal S 31  is 9 V, the voltage VO 32  is −6 V; when the signal S 31  is 0 V, the voltage VO 32  is −15 V.  
         [0024]     The operations of the signal of the level shifter  300  are elaborated below. During time period t 1 , the signal S 31  is 9 V, while the signal S 32  is 0 V. The PMOS switches M 31  and M 32  are conducted, so that the signal S 33  and the output signal X 3  are 9 V, and that the PMOS transistor M 33  is not conducted. Since the PMOS transistor M 33  is not conducted, no current flows to the low voltage V 31  from the signal S 31  and the power consumption is thus reduced. During time period t 2 , the PMOS switches M 31  and M 32  are not conducted. Since the voltage VO 32  is −15V, the level of the voltage VO 32  outputted by the one-way conducting device  311  is equal to the previously defined second reference voltage, so that the signal S 33  is −15 V, the PMOS transistor M 33  is conducted, and that the output signal X 3  is −6 V. After time period t 2 , the oscillation of the signal S 33  ranges from −15 to 9 V. Hence, the oscillation of the output signal X 3  ranges from 9 V to −6 V and varies with the signals S 31  and S 32 .  
         [0025]     Referring to  FIG. 7 , a circuit diagram of a level shifter according to a second embodiment of the invention is shown. The present embodiment provides a level shifter  400  manufactured according to Low Temperature Poly-Silicon (LTPS) manufacturing method. The level shifter  400  includes a PMOS switch M 41 , a PMOS transistor M 42 , a PMOS transistor M 43  and a coupling block  410 . The gate of the PMOS switch M 41  receives a signal S 43 , the drain of the PMOS switch M 41  provides a third reference voltage, while the source of the PMOS switch M 41  is biased to a high voltage V 41 . The PMOS switch M 41  chooses the third reference voltage or a fourth reference voltage to be a signal S 44 . The gate of the PMOS transistor M 42  receives the signal S 43 , the source of the PMOS transistor M 42  is biased to the high voltage V 41 . The gate of the PMOS transistor M 43  receives the signal S 44 , the drain of the PMOS transistor M 43  is coupled to low voltage V 42 , the source of the PMOS transistor M 43  is coupled to the drain of the PMOS transistor M 42  and generates a signal X 4 . The coupling block  410  is for receiving signals S 41  and S 42  to generate the signal S 43  and provide the fourth reference voltage.  
         [0026]     The coupling block  410  includes several PMOS transistors M 44 , M 45 , M 46 , and M 47 , several capacitors C 41 , C 42 , C 43 , and C 44  and the one-way conducting device  311 . The source of the transistor M 44  is coupled to a low voltage V 42 . The gate of the PMOS transistor M 45  is coupled to the drain of the PMOS transistor M 44 , the drain of the PMOS transistor M 45  is coupled to the gate of the PMOS transistor M 44 , while the source of the PMOS transistor M 45  is coupled to the low voltage V 42 . One end of the capacitor C 41  receives a signal S 41 , while another end of the capacitor C 41  is coupled to the drain of the PMOS transistor M 44 . One end of the capacitor C 42  receives the signal S 42 , while another end of the capacitor C 42  is coupled to the drain of the PMOS transistor M 45 .  
         [0027]     The source of the PMOS transistor M 46  is biased to the high voltage V 41 . The gate of the PMOS transistor M 47  is coupled to the drain of PMOS transistor M 46 , the drain of the PMOS transistor M 47  is coupled to the gate of the PMOS transistor M 46 , while the source of the PMOS transistor M 47  is biased to the high voltage V 41 . One end point of the capacitor C 43  receives the signal S 42 , while another end point O 43  is coupled to the drain of the PMOS transistor M 46  to generate the signal S 43 . One end point of the capacitor C 44  receives the signal S 41 , while another end point O 44  of the capacitor C 44  is coupled to the drain of the PMOS transistor M 47 . The output end of the one-way conducting device  311  is coupled to the drain of the PMOS switch M 41  and provides the fourth reference voltage, while the input end of the one-way conducting device  311  is coupled to the drain of the PMOS transistor M 44 . The contents of the one-way conducting device  311  are disclosed in the first embodiment and are not repeated here.  
         [0028]     Referring to both  FIG. 7  and  FIG. 8  at the same time.  FIG. 8  is a signal time sequence diagram of a level shifter according to a second embodiment of the invention. The signals S 41 , a clock signal ranging between 5 and 0 V, and the signal S 42 , a clock signal ranging between from 5 and 0 V, are inverted. The high voltage V 41  is 9 V, while the low voltage V 42  is −6 V. The voltage VO 44  is the voltage at the drain of the PMOS transistor M 47 .  
         [0029]     The generation of the signal S 43  is elaborated below. During time period t 1 ′, the signal S 41  is 0 V, while the signal S 42  is 5 V. Meanwhile, the signal S 43  of the end point O 43  and the voltage VO 44  of the end point O 44 , being at initial state, are assumed to be close to the value of the high voltage V 41  which is 9 V. During time period t 2 ′, the signal S 41  is 5 V, while the signal S 42  is 0 V. During time period t 1 ′, the voltage drop is equal to the difference of 9 V and 5 V which is 4 V due to the signals S 43  and S 42  and the coupling effect of the capacitor C 43 . During time period t 2 ′, the signal S 42  is reduced to 0 V, and the signal S 43  is reduced to 4 V accordingly, so that the PMOS transistor M 47  is conducted, and that the voltage VO 44  is 9 V. During time period t 3 ′, the signal S 41  is 0 V, and the signal S 42  is 5 V. The voltage O 44  of the end point O 44 , is reduced to 4 V due to the coupling effect of the capacitor C 44 , so that the PMOS transistor M 46  is conducted, and that the signal S 43  is 9 V. During time period t 4 ′, the signal S 43  is 4 V. Hence the signal S 43  which is a clock signal and the signal S 42  are in phase. When the signal S 42  is 5 V, the signal S 43  is 9 V; when the signal S 42  is 0 V, the signal S 43  is 4 V.  
         [0030]     The signal S 44  is formed by the third reference voltage provided by the PMOS switch M 41  and the fourth reference voltage provided by the one-way conducting device  311 . According to the present embodiment, the third reference voltage is the high level voltage V 41  when the PMOS switch M 41  is conducted; the fourth reference voltage, which is provided by the one-way conducting device  311  when the PMOS switch M 41  is not conducted, is −10 V. The structure and the operations of the circuit formed by the PMOS transistors M 44 , M 45 , the capacitors C 41 , C 42  and the one-way conducting device  311  are the same with that of the coupling block  310  with the only difference being the level of the signal. Anyone who is skilled in the technology can obtain the fourth reference voltage of the circuit according to the previous embodiment and is not repeated here. The operations of the level shifter  400  are exemplified by the signal S 44  as below.  
         [0031]     The operations of the signal of the level shifter  400  are elaborated below. During time period t 1 ′, the signal S 43  is 9 V while the signal S 44  is −10 V, so that the PMOS switch M 41  and the PMOS transistor M 42  are not conducted, the PMOS transistor M 43  is conducted, and that the output signal X 4  is −6 V. During time period t 2 ′, the signal S 43  is 4 V while the signal S 44  is 9 V, so that the PMOS switch M 41  and the PMOS transistor M 42  are conducted, the PMOS transistor M 43  is conducted, and that the output signal X 4  is −6 V. Hence, the output signal X 4  whose oscillation ranges between 9 V and −6 V and the signal S 41  are in phase.  
         [0032]     According to the invention, the values of the signals S 31 , S 32 , S 41 , S 42 , the low voltage V 31 , the low voltage V 42  and the high voltage V 41  are not fixed, and any value will do as long as the above elements can be enabled to function as in the above embodiments. According to the design of the invention, whether the PMOS transistor is conducted or not does not generate static current, hence no power is wasted.  
         [0033]     The level shifter disclosed in above embodiment of the invention can be achieved according to the LTPS manufacturing method with the advantages that fewer masks are needed and that circuits are integrated to reduce the costs. Moreover, the design of the circuit avoids the power consumption of the stable current or when providing a higher or a lower voltage in response to the oscillation of the output signal, therefore improving the applicability of the product.  
         [0034]     While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Technology Classification (CPC): 6