Patent Abstract:
A transmitting/receiving system may include a transmission line, a transmitter circuit configured to transmit a clock to the transmission line and to adjust an amplitude of the clock in accordance with a logic level of data, and a receiver circuit configured to receive the clock transferred to the transmission line and to recover the data through detection of the amplitude of the clock.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2012-0132965, filed on Nov. 22, 2012, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a data transmitting/receiving technology. 
         [0004]    2. Description of the Related Art 
         [0005]    Various integrated circuit chips do not operate alone, but operate to send/receive data with peripheral chips. For example, memory chips, such as a DRAM and a flash memory, send/receive data with a memory controller, and a CPU also sends/receives data with various chips on a motherboard. 
         [0006]      FIG. 1  is a diagram illustrating a data transmitting method between a transmitter circuit  110  and a receiver circuit  120  in the related art. 
         [0007]    Referring to  FIG. 1 , the transmitter circuit  110  transmits data DATA1 and DATA2 to the receiver circuit  120  together with clocks CLK and CLKB. Then, the receiver circuit  120  receives the data DATA1 and DATA2 in synchronization with the clocks CLK and CLKB. In order to stably send/receive high-frequency (high-speed) data, clocks that are synchronized with the data are essential and most high-speed transmitting/receiving systems use the data transmitting method as illustrated in  FIG. 1 . 
         [0008]    Some transmitting system transmits data without clock and corresponding receiving system recovers a clock included in the data transmitted from the transmitting system using a clock data recovery circuit, which consumes a large amount of current and performs unstable operation, such as a clock generator. 
       SUMMARY 
       [0009]    Various embodiments of the present invention are directed to a technology that may transmit/receive a clock and data together through one line with less consumption of current and stable high-speed operation. 
         [0010]    In an embodiment, a transmitting/receiving system may include a transmission line, a transmitter circuit configured to transmit a clock to the transmission line and to adjust an amplitude of the clock in accordance with a logic level of data, and a receiver circuit configured to receive the clock transferred to the transmission line and to recover the data through detection of the amplitude of the clock. 
         [0011]    In an embodiment, a transmitter circuit may include a first driver configured to drive a clock on a transmission line, and a second driver configured to drive the clock on the transmission line, and to be activated if data is of a first level and to be inactivated if the data is of a second level. 
         [0012]    In an embodiment, a receiver circuit may include a clock receiving unit configured to recover a clock through detection of logic high and logic low of a signal received through a transmission line, and a data receiving unit configured to recover data through detection of an amplitude of the signal received through the transmission line. 
         [0013]    In another embodiment, a transmitting/receiving system may include a first transmission line, a second transmission line, a first transmitting unit configured to transmit a positive clock to the first transmission line and to adjust an amplitude of the positive clock in accordance with a logic level of first data, a second transmitting unit configured to transmit a negative clock to the second transmission line and to adjust an amplitude of the negative clock in accordance with a logic level of second data, and a receiver circuit configured to receive the first clock and the second clock transferred to the first transmission line and the second transmission line, to recover the first data through detection of the amplitude of the received positive clock, and to recover the second data through detection of the amplitude of the received negative clock. 
         [0014]    In another embodiment, a receiver circuit may include a clock receiving unit configured to recover a first clock and a second clock through comparison of a signal received through a first transmission line with a signal received through a second transmission line, and a data receiving unit configured to recover first data through detection of an amplitude of the signal received through the first transmission line and to recover second data through detection of an amplitude of the signal received through the second transmission line. 
         [0015]    In another embodiment, a transmitting/receiving system may include a transmitter circuit configured to generate a clock whose peak amplitude varies in accordance with a logic level of data to be transmitted and to transmit the clock as a signal, and a receiver circuit configured to recover the clock based on a logical level of the signal received from the transmitter circuit and to recover the data based on a amplitude of the received signal. 
         [0016]    According to embodiments of the present invention, since the clock modulated by data is transmitted via one transmission line, the number of lines required to transmit the data may be reduced, and a stable high-speed operation may be achieved. 
         [0017]    Further, it is not necessary to use a clock data recovery circuit based on a clock generator that may involve complicated circuit and a large amount of current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a diagram illustrating a data transmitting method between a transmitter circuit  110  and a receiver circuit  120  in the related art. 
           [0019]      FIG. 2  is a diagram illustrating the configuration of a transmitting/receiving system in accordance with an embodiment of the present invention. 
           [0020]      FIG. 3  is a diagram illustrating the configuration of a transmitter circuit  210  shown in  FIG. 2  in accordance with an embodiment of the present invention. 
           [0021]      FIG. 4  is a diagram illustrating the configuration of a receiver circuit  220  shown in  FIG. 2  in accordance with an embodiment of the present invention. 
           [0022]      FIG. 5  is a diagram explaining operations of the transmitter circuit  210  and the receiver circuit  220  illustrated in  FIGS. 2 to 4 . 
           [0023]      FIG. 6  is a diagram illustrating the configuration of a transmitting/receiving system in accordance with another embodiment of the present invention. 
           [0024]      FIG. 7  is a diagram illustrating the configuration of a transmitter circuit  610  shown in  FIG. 6  in accordance with an embodiment of the present invention. 
           [0025]      FIG. 8  is a diagram illustrating the configuration of a receiver circuit  620  shown in  FIG. 6  in accordance with an embodiment of the present invention. 
           [0026]      FIG. 9  is a diagram explaining operations of the transmitter circuit  610  and the receiver circuit  620  illustrated in  FIGS. 6 to 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    Various exemplary embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, reference numerals correspond directly to the like numbered parts in the various figures and embodiments of the present invention. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence. 
         [0028]    The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. 
         [0029]      FIG. 2  is a diagram illustrating the configuration of a transmitting/receiving system in accordance with an embodiment of the present invention. 
         [0030]    Referring to  FIG. 2 , a transmitting/receiving system includes a transmitter circuit  210 , a receiver circuit  220 , and a transmission line LINE. The transmitter circuit  210  and the receiver circuit  220  may be arranged in different integrated circuit chips, or in the same chip, which may vary according to a design. 
         [0031]    The transmitter circuit  210  transmits a clock CLK to the receiver circuit  220  through the transmission line LINE. Amplitude of the clock CLK transmitted by the transmitter circuit  210  depends on a value of data DATA. The transmitter circuit  210  transmits the clock CLK with relatively greater amplitude when the data DATA to be transmitted is “1”. On the other hand, the transmitter circuit  210  transmits the clock CLK with relatively smaller amplitude when the data DATA to be transmitted is “0”. That is, the transmitter circuit  210  transmits the clock CLK, of which the amplitude varies depending on the value of the data DATA to be transmitted. 
         [0032]    The receiver circuit  220  receives a signal or the clock CLK transmitted from the transmitter  210  via the transmission line LINE, and if the logic level of the received signal is “1”, the receiver circuit  220  identifies the received signal as the clock CLK, which has a value of “1”, while if the logic level of the received signal is “0”, the receiver circuit  220  identifies the received signal as the clock CLK, which has a value of “0”. Further, the receiver circuit  220  identifies the data DATA sent from the transmitter  210  as “0” or “1” based on the amplitude of the received signal. 
         [0033]      FIG. 3  is a diagram illustrating the configuration of a transmitter circuit  210  shown in  FIG. 2  in accordance with an embodiment of the present invention. 
         [0034]    Referring to  FIG. 3 , the transmitter circuit  210  includes a first driver  310  and a second driver  320 . 
         [0035]    The first driver  310  receives and drives the clock CLK on the transmission line LINE. A first pull-up voltage V_PU1 for pull-up driving of the transmission line LINE and a first pull-down voltage V_PD1 for pull-down driving of the transmission line LINE are supplied to the first driver  310 . 
         [0036]    The second driver  320  also drives the clock CLK on the transmission line LINE. However, the second driver  320  is activated when the data DATA to be transmitted has a value of “1”, and is inactivated when the data DATA to be transmitted has a value of “0”. That is, the second driver  320  drives the clock CLK on the transmission line LINE if the data DATA to be transmitted has the value of “1”, but does not drive the clock CLK on the transmission line LINE if the data DATA to be transmitted has the value of “0”. A second pull-up voltage V_PU2 for pull-up driving of the transmission line LINE and a second pull-down voltage V_PD2 for pull-down driving of the transmission line LINE are supplied to the second driver  320 . The second pull-up voltage V_PU2 is higher than the first pull-up voltage V_PU1, and the second pull-down voltage V_PD2 is lower than the first pull-down voltage V_PD1. 
         [0037]    If the value of the data DATA input to the transmitter circuit  210  is “0”, only the first driver  310  drives the clock CLK on the transmission line LINE. On the other hand, if the value of the data DATA is “1”, the first driver  310  and the second driver  320  simultaneously drive the clock CLK on the transmission line LINE. Accordingly, the amplitude of the clock CLK driven on the transmission line LINE is changed depending on the value of the data DATA. 
         [0038]    Although  FIG. 3  illustrates that the pull-up voltages V_PU1 and V_PU2 and the pull-down voltages V_PD1 and V_PD2 that are supplied to the first driver  310  and the second driver  320  are different from each other, the same pull-up voltage and the same pull-down voltage (that is, V_PU1=V_PU2 and V_PD1=V_PD2) may be supplied to the first driver  310  and the second driver  320 . Even though the first driver  310  and the second driver  320  use the same pull-up voltage and the same pull-down voltage, the amplitude of the clock CLK driven on the transmission line LINE may be changed depending on the value of the data DATA because there is a difference in driving force on the clock CLK when only the first driver  310  drives the clock CLK and when both the first driver  310  and the second driver  320  drive the clock CLK. 
         [0039]      FIG. 4  is a diagram illustrating the configuration of a receiver circuit  220  shown in  FIG. 2  in accordance with an embodiment of the present invention. 
         [0040]    Referring to  FIG. 4 , the receiver circuit  220  includes a clock receiving unit  410  recovering the clock CLK and a data receiving unit  420  and  430  recovering the data DATA. The data receiving unit includes an even data receiving unit  420  and an odd data receiving unit  430 . 
         [0041]    The clock receiving unit  410  recovers the clock CLK through comparison of the signal transmitted from the transmitter  210  via the transmission line LINE with a first reference voltage VREF1. If the voltage level of the received signal is higher than the voltage level of the first reference voltage VREF1, the clock receiving unit  410  recovers the value of the clock CLK to “1”, and if the voltage level of the received signal is lower than the voltage level of the first reference voltage VREF1, the clock receiving unit  410  recovers the value of the clock CLK to “0”. Here, the first reference voltage VREF1 is a reference voltage for determining whether the logic level of the received signal is “1” or “0”. 
         [0042]    The even data receiving unit  420  recovers even data E_DATA from the received signal. The even data E_DATA is synchronized with a period of logic level “1” of the clock CLK. The even data receiving unit  420  recovers the even data E_DATA by comparing the level of the received signal with a level of a second reference voltage VREF2 and by sampling the result of comparison in synchronization with the clock CLK. The even data receiving unit  420  may include a differential buffer  421  and a latch  422 . The differential buffer  421  compares the received signal with the second reference voltage VREF2, and outputs a signal that has logical value of “1” if the received signal is higher than the second reference voltage VREF2, and outputs a signal that has logical value of “0” if the received signal is lower than the second reference voltage VREF2. Further, the latch  422  latches the output of the differential buffer  421  in synchronization with the level “1” of the clock CLK. The signal latched in the latch  422  becomes the even data E_DATA. Here, the second reference voltage VREF2 is a reference voltage that is higher than the first reference voltage VREF1. A value of the second reference voltage VREF2 is set between the relatively greater amplitude and the relatively smaller amplitude of the clock CLK that has logical level of “1”. As described above in connection with  FIG. 2 , the transmitter circuit  210  transmits the clock CLK with relatively greater amplitude when the data DATA to be transmitted is “1”, while with relatively smaller amplitude when the data DATA to be transmitted is “0”. 
         [0043]    The odd data receiving unit  430  recovers odd data O_DATA from the received signal. The odd data O_DATA is synchronized with a period of logic level “0” of the clock CLK. The odd data receiving unit  430  recovers the odd data O_DATA by comparing the level of the received signal with a level of a third reference voltage VREF3 and by sampling the result of comparison in synchronization with a reverse signal CLKB of the clock CLK. The odd data receiving unit  430  may include a differential buffer  431  and a latch  432 . The differential buffer  431  compares the received signal with the third reference voltage VREF3, and outputs a signal whose logical value is “1” if the received signal is lower than the third reference voltage VREF3 and outputs a signal whose logical value is “0” if the received signal is higher than the third reference voltage VREF3. Further, the latch  432  latches the output of the differential buffer  431  in synchronization with the level “1” of the signal CLKB, or level “0” of the clock CLK. The signal latched in the latch  432  becomes the odd data O_DATA. Here, the third reference voltage VREF3 is a reference voltage that is lower than the first reference voltage VREF1. An absolute value of the third reference voltage VREF3 is set between the relatively greater amplitude and the relatively smaller amplitude of the clock CLK that has a logical level of “1”. 
         [0044]      FIG. 5  is a diagram explaining operations of the transmitter circuit  210  and the receiver circuit  220  illustrated in  FIGS. 2 to 4 . 
         [0045]    The level of the signal transmitted from the transmitter circuit  210  is shown in (a) of  FIG. 5 , and the levels of the clock CLK and the data DATA recovered by the receiver circuit  220  are shown in (b) of  FIG. 5 . In (b) of  FIG. 5 , data indicated by “E” denotes the even data E_DATA recovered by the even data receiving unit  420 , and data indicated by “O” denotes the odd data O_DATA recovered by the odd data receiving unit  430 . 
         [0046]    Referring to  FIG. 5 , the transmitter circuit  210  adjusts the amplitude of the clock CLK in accordance with the level of the data DATA, and the receiver circuit  220  recovers the clock CLK using the logical value of the signal transmitted from the transmitter circuit  210  and recovers the data DATA using the amplitude of the signal transmitted from the transmitter circuit  210 . 
         [0047]      FIG. 6  is a diagram illustrating the configuration of a transmitting/receiving system in accordance with another embodiment of the present invention. With reference to  FIG. 6 , the transmitting/receiving system using clocks of differential type or clocks CLK and CLKB will be described. 
         [0048]    Referring to  FIG. 6 , the transmitting/receiving system includes a transmitter circuit  610  and a receiver circuit  620 . Transmitter circuit  610  and the receiver circuit  620  may be arranged in different integrated circuit chips, or in the same chip, which may vary according to a design. 
         [0049]    The transmitter circuit  610  transmits a positive clock CLK to the receiver circuit  620  through a first transmission line LINE1, and transmits a negative clock CLKB through a second transmission line LINE2. Amplitudes of the clocks CLK and CLKB to be transmitted depends on values of data DATA1 and DATA2, respectively. The transmitter circuit  610  transmits the positive clock CLK on the first transmission line LINE1 with relatively greater amplitude when the first data DATA1 to be transmitted is “1”. On the other hand, the transmitter circuit  610  transmits the positive clock CLK on the first transmission line LINE1 with relatively smaller amplitude when the first data DATA1 to be transmitted is “0”. Further, the transmitter circuit  610  transmits the negative clock CLKB on the second transmission line LINE2 with relatively greater amplitude when the second data DATA2 to be transmitted is “1”. On the other hand, the transmitter circuit  610  transmits the negative clock CLKB on the second transmission line LINE2 with relatively smaller amplitude when the second data DATA2 to be transmitted is “0”. That is, the transmitter circuit  610  transmits the clocks CLK and CLKB, of which the amplitudes are changed depending on the values of the data DATA1 and DATA2 to be transmitted on the transmission lines LINE1 and LINE2, respectively. 
         [0050]    The receiver circuit  620  receives signals or the clocks CLK and CLKB transmitted from the transmitter  610  via the transmission lines LINE1 and LINE2, and if the logic level of the signal of the first transmission line LINE1 is “1”, the receiver circuit  620  identifies the signal on the first transmission line LINE1 as the positive clock CLK of logical value “1”, while if the logic level of the signal of the first transmission line LINE1 is “0”, the receiver circuit  620  recognizes the signal on the first transmission line LINE1 as the positive clock CLK of logical value “0”. Further, the receiver circuit  620  identifies the first data DATA1 sent from the transmitter  210  as “0” or “1” based on the amplitude of the signal on the first transmission line LINE1. Further, if the logic level of the signal of the second transmission line LINE2 is “1”, the receiver circuit  620  recognizes the signal on the second transmission line LINE2 as the negative clock CLKB of logical value “1”, while if the logic level of the signal of the second transmission line LINE2 is “0”, the receiver circuit  620  recognizes the signal on the second transmission line LINE2 as the negative clock CLKB of logical value “0”. Further, the receiver circuit  620  recognizes the second data DATA2 sent from the transmitter  210  as “0” or “1” based on the amplitude of the signal on the second transmission line LINE2. 
         [0051]      FIG. 7  is a diagram illustrating the configuration of a transmitter circuit  610  in  FIG. 6  in accordance with another embodiment of the present invention. 
         [0052]    Referring to  FIG. 7 , the transmitter circuit  610  includes a first driver  710 , a second driver  720 , a third driver  730 , and a fourth driver  740 . 
         [0053]    The first driver  710  receives and drives the positive clock CLK on the first transmission line LINE1. A first pull-up voltage V_PU1 for pull-up driving of the first transmission line LINE1 and a first pull-down voltage V_PD1 for pull-down driving of the first transmission line LINE1 are supplied to the first driver  710 . 
         [0054]    The second driver  720  also drives the positive clock CLK on the first transmission line LINE1. However, the second driver  720  is activated when the first data DATA1 to be transmitted has a value of “1”, and is inactivated when the first data DATA1 to be transmitted has a value of “0”. That is, the second driver  720  drives the positive clock CLK on the first transmission line LINE1 if the first data DATA1 to be transmitted has the value of “1”, but does not drive the positive clock CLK on the first transmission line LINE1 if the first data DATA1 to be transmitted has the value of “0”. A second pull-up voltage V_PU2 for pull-up driving of the first transmission line LINE1 and a second pull-down voltage V_PD2 for pull-down driving of the first transmission line LINE1 are supplied to the second driver  720 . The second pull-up voltage V_PU2 is higher than the first pull-up voltage V_PU1, and the second pull-down voltage V_PD2 is lower than the first pull-down voltage V_PD1. 
         [0055]    The third driver  730  receives and drives the negative clock CLKB on the second transmission line LINE2. A first pull-up voltage V_PU1 for pull-up driving of the second transmission line LINE2 and a first pull-down voltage V_PD1 for pull-down driving of the second transmission line LINE2 are supplied to the third driver  730 . 
         [0056]    The fourth driver  740  also drives the negative clock CLKB on the second transmission line LINE2. However, the fourth driver  740  is activated when the second data DATA2 to be transmitted has a value of “1”, and is inactivated when the second data DATA2 to be transmitted has a value of “0”. That is, the fourth driver  740  drives the negative clock CLKB on the second transmission line LINE2 if the second data DATA2 to be transmitted has the value of “1”, but does not drive the negative clock CLKB on the second transmission line LINE2 if the second data DATA2 has the value of “0”. A second pull-up voltage V_PU2 for pull-up driving of the second transmission line LINE2 and a second pull-down voltage V_PD2 for pull-down driving of the second transmission line LINE2 are supplied to the fourth driver  740 . The second pull-up voltage V_PU2 is higher than the first pull-up voltage V_PU1, and the second pull-down voltage V_PD2 is lower than the first pull-down voltage V_PD1. 
         [0057]    The transmitter circuit  610  of  FIG. 7  is different from the transmitter circuit  210  of  FIG. 3  only on the point that two kinds of clocks CLK and CLKB are transmitted in accordance with two kinds of data DATA1 and DATA2, and operates in the same principle as the transmitter circuit  210  of  FIG. 3 . Accordingly, the same pull-up voltage and the same pull-down voltage may be supplied to the drivers  710  to  740  as described above with reference to  FIG. 3 . That is, it may be satisfied that V_PU1=V_PU2 and V_PD1=V_PD2. 
         [0058]    If the value of the first data DATA1 input to the transmitter circuit  610  is “0”, only the first driver  710  drives the positive clock CLK on the first transmission line LINE1. On the other hand, if the value of the first data DATA1 is “1”, the first driver  710  and the second driver  720  simultaneously drive the positive clock CLK on the first transmission line LINE1. Accordingly, the amplitude of the positive clock CLK driven on the first transmission line LINE1 may be changed depending on the value of the first data DATA1. 
         [0059]    If the value of the second data DATA2 input to the transmitter circuit  610  is “0”, only the third driver  730  drives the negative clock CLKB on the second transmission line LINE2, while if the value of the second data DATA2 is “1”, the third driver  730  and the fourth driver  740  simultaneously drive the negative clock CLKB on the second transmission line LINE2. Accordingly, the amplitude of the negative clock CLKB driven on the second transmission line LINE2 is changed depending on the value of the second data DATA2. 
         [0060]      FIG. 8  is a diagram illustrating the configuration of a receiver circuit  620  shown in  FIG. 6  in accordance with another embodiment of the present invention. 
         [0061]    Referring to  FIG. 8 , the receiver circuit  620  includes a clock receiving unit  810  recovering the clocks CLK and CLKB and data receiving units  820  to  850  recovering the data DATA1 and DATA2. The data receiving unit includes a first even data receiving unit  820 , a first odd data receiving unit  830 , a second even data receiving unit  840 , and a second odd data receiving unit  850 . 
         [0062]    The clock receiving unit  810  recovers the positive clock CLK and the negative clock CLKB through comparison of the level of the signal received through the first transmission line LINE1 with the level of the signal received through the second transmission line LINE2. If the signal of the first transmission line LINE1 is higher than the signal of the second transmission line LINE2, the clock receiving unit  810  outputs the positive clock CLK of logic value “1” and the negative clock CLKB of logic value “0”, and if the signal of the second transmission line LINE2 is higher than the signal of the first transmission line LINE1, the clock receiving unit  810  outputs the positive clock CLK of logic value “0” and the negative clock CLKB of logic value “1”. The clock receiving unit  810  may be a differential buffer with differential input-differential output. 
         [0063]    The first even data receiving unit  820  recovers first even data E_DATA1 from the signal received through the first transmission line LINE1. The first even data E_DATA1 is synchronized with a period of logic level “1” of the positive clock CLK. The first even data receiving unit  820  recovers the first even data E_DATA1 by comparing the level of the signal received through the first transmission line LINE1 with the level of the second reference voltage VREF2 and by sampling the result of comparison in synchronization with the positive clock CLK. The first even data receiving unit  820  may include a differential buffer  821  and a latch  822 . The differential buffer  821  compares the signal received through the first transmission line LINE1 with the second reference voltage VREF2, and outputs the signal whose logical value is “1” if the signal received through the first transmission line LINE1 is higher than the second reference voltage VREF2, and outputs the signal whose logical value is “0” if the signal received through the first transmission line LINE1 is lower than the second reference voltage VREF2. Further, the latch  822  latches the output of the differential buffer  821  in synchronization with the level “1” of the positive clock CLK. The signal latched in the latch  822  becomes the first even data E_DATA1. A value of the second reference voltage VREF2 is set between the relatively greater amplitude and the relatively smaller amplitude of the positive clock CLK whose logical level is “1”. As described above in connection with  FIG. 6 , the transmitter circuit  610  transmits the positive clock CLK with relatively greater amplitude when the first data DATA1 to be transmitted is “1”. On the other hand, the transmitter circuit  610  transmits the positive clock CLK with relatively smaller amplitude when the first data DATA1 to be transmitted is “0”. 
         [0064]    The first odd data receiving unit  830  recovers first odd data O_DATA1 from the signal received through the first transmission line LINE1. The first odd data O_DATA1 is synchronized with the period of logic level “1” of the negative clock CLKB. The first odd data receiving unit  830  recovers the first odd data O_DATA1 by comparing the level of the signal that is received through the first transmission line LINE1 with the level of the third reference voltage VREF3 and by sampling the result of comparison in synchronization with the negative clock CLKB. The first odd data receiving unit  830  may include a differential buffer  831  and a latch  832 . The differential buffer  831  compares the signal received through the first transmission line LINE1 with the third reference voltage VREF3, and outputs the signal that has a logical value of “1” if the signal received through the first transmission line LINE1 is lower than the third reference voltage VREF3 and outputs the signal that has a logical value of “0” if the signal received through the first transmission line LINE1 is higher than the third reference voltage VREF3. Further, the latch  832  latches the output of the differential buffer  831  in synchronization with the level “1” of the negative clock CLKB. The signal latched in the latch  832  becomes the first odd data O_DATA1. Here, the third reference voltage VREF3 is a reference voltage lower than the first reference voltage VREF1. An absolute value of the third reference voltage VREF3 is set between the relatively greater amplitude and the relatively smaller amplitude of the positive clock CLK or the negative clock CLKB whose logical level is “1”. 
         [0065]    The second even data receiving unit  840  recovers second even data E_DATA2 from the signal received through the second transmission line LINE2. The second even data E_DATA2 is synchronized with the period of logic level “1” of the positive clock CLK. The second even data receiving unit  840  recovers the second even data E_DATA2 by comparing the level of the signal received through the second transmission line LINE2 with the level of the third reference voltage VREF3 and by sampling the result of comparison in synchronization with the positive clock CLK. The second even data receiving unit  840  may include a differential buffer  841  and a latch  842 . The differential buffer  841  compares the signal received through the second transmission line LINE2 with the third reference voltage VREF3, and outputs the signal that has a logical value of “1” if the signal received through the second transmission line LINE2 is lower than the third reference voltage VREF3 and outputs the signal that has a logical value of “0” if the signal received through the second transmission line LINE2 is higher than the third reference voltage VREF3. Further, the latch  842  latches the output of the differential buffer  841  in synchronization with the level “1” of the positive clock CLK. The signal latched in the latch  842  becomes the second even data E_DATA2. 
         [0066]    The second odd data receiving unit  850  recovers second odd data O_DATA2 from the signal received through the second transmission line LINE2. The second odd data O_DATA2 is synchronized with the period of logic level “1” of the negative clock CLKB. The second odd data receiving unit  850  recovers the second odd data O_DATA2 by comparing the level of the signal that is received through the second transmission line LINE2 with the level of the second reference voltage VREF2 and by sampling the result of comparison in synchronization with the negative clock CLKB. The second odd data receiving unit  850  may include a differential buffer  851  and a latch  852 . The differential buffer  851  compares the signal received through the second transmission line LINE2 with the second reference voltage VREF2, and outputs the signal that has a logical value of “1” if the signal received through the second transmission line LINE2 is higher than the second reference voltage VREF2 and outputs the signal that has a logical value of “0” if the signal received through the second transmission line LINE2 is lower than the second reference voltage VREF2. Further, the latch  852  latches the output of the differential buffer  851  in synchronization with the level “1” of the negative clock CLKB. The signal latched in the latch  852  becomes the second odd data O_DATA2. 
         [0067]      FIG. 9  is a diagram explaining operations of the transmitter circuit  610  and the receiver circuit  620  illustrated in  FIGS. 6 to 8 . 
         [0068]    The levels of the signals on the transmission lines LINE1 and LINE2 are shown in (a) of  FIG. 9 , and the levels of the clocks CLK and CLKB and the data DATA1 and DATA2 that the receiver circuit  620  recovers using the signal levels of the transmission lines LINE1 and LINE2 are shown in (b) of  FIG. 9 . In (b) of  FIG. 9 , data indicated by “E” denotes the even data E_DATA1 and E_DATA2, and data indicated by “O” denotes the odd data O_DATA1 and O_DATA2. 
         [0069]    Referring to  FIG. 9 , the transmitter circuit  610  adjusts the amplitude of the positive clock CLK and negative clock CLKB in accordance with the level of the first data DATA1 and the second data DATA2, respectively, and the receiver circuit  620  recovers the positive clock CLK and the negative clock CLKB using the logical values of the signals transmitted from the transmitter circuit  610  and recovers the first data DATA1 and the second data DATA2 using the amplitudes of the signals transmitted from the transmitter circuit  610 . 
         [0070]    In the above-described embodiments, it is exemplified that the transmitter circuit increases the amplitude of the transmitted clock if the data is “1” and decreases the amplitude of the clock if the data is “0”. However, the reverse is also possible. 
         [0071]    Further, the scope of the present invention may expand to the case of more than 2 of the data to be transmitted. For example, it may be also possible that a plurality (for example, 8) of transmission lines are provided between the transmitter circuit and the receiver circuit. The above-described transmitting method according to the embodiment is used in the two transmission lines, and the same data transmitting method as in the related art is used in the 6 remaining transmission lines. 
         [0072]    Further, the signal value may be fixed to “0” on the transmission line in a period when there is no data to be transmitted, and the clock having constant amplitude may be transmitted to the transmission line according to data to be transmitted, where the clock functions as the data of logical value “1” or “0” as well as the clock itself. 
         [0073]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Technology Classification (CPC): 7