Patent Abstract:
Voltage generating apparatus includes a positive temperature coefficient current generating module, a negative temperature coefficient current generating module, a fine-tune current module and a voltage output module. The function of the positive temperature coefficient current generating module and the negative temperature coefficient current generating module, which take advantage of characteristics of MOS devices operated in the sub-threshold region, is to generate a stable current of positive temperature coefficient and a stable current of negative temperature coefficient, respectively. The current fine-tune module increases or decreases output current of the negative temperature coefficient current generating module. The voltage output module sums two output currents of the positive temperature coefficient current generating module and the negative temperature coefficient current generating module and transforms the total current into output voltage that is stable under temperature and process variation.

Full Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to a voltage generating apparatus, more particularly, to a voltage generating apparatus with a fine-tune current module. 
   2. Description of the Prior Art 
   Almost all analog or mixed-mode circuits need reference voltages to provide the bias voltage. The reference voltage can generate a constant and reproducible voltage even during process variation, change of ambient temperature, and supply voltage instability so that the circuits can operate with accurate DC bias. Therefore, a DC voltage generator is an important block in many circuits. 
   A well-known method of generating a stable reference voltage is to utilize the phenomenon of semiconductor bandgap in a reference circuit. The bandgap energy of a semiconductor will change predictably with ambient temperature, and bandgap reference circuits are designed according to this principle. The most popular method of generating bandgap voltage in the prior art is to connect the base and the collector of a BJT to form a diode-like structure, so the voltage difference (Vsub) between the base and the emitter of the BJT can be the bandgap voltage. 
   Please refer to  FIG. 1 .  FIG. 1  illustrates temperature variation versus Vsub in a diode-like device. As shown in  FIG. 1 , Vsub linearly decreases with rising temperature. If one can generate another voltage (like the compensation voltage in  FIG. 1 ) which linearly increases with rising temperature at the same rate as Vsub decreases, the summation of the two voltages results in a constant reference voltage that reduces variation due to temperature. 
   Please refer to  FIG. 2 .  FIG. 2  illustrates a reference voltage generator  200  implementing the bandgap voltage principle. The reference voltage generator  200  is a feedback control system that maintains two inputs of the amplifier  230  at similar levels. In the reference voltage generator  200 , the diodes D 1  and D 2  have different section areas corresponding to different current densities in order to adjust the slopes of the temperature coefficients of the two diodes, D 1  and D 2 . When the voltage generator  200  is operating, the voltage difference of VD 1  and VD 2  (Vdel) expresses a characteristic of a positive temperature coefficient (a positive slope in the temperature function), but the voltage VD 1  expresses a characteristic of a negative temperature coefficient, like the property of an ordinary semiconductor. Through the combination and arrangement of the diodes D 1 , D 2  and the amplifier  230 , the amplifier  230  will output a stable voltage regulated against temperature variation resulting from compensation of the voltage with the positive temperature coefficient, and the voltage with the negative temperature coefficient. However, in the modern IC industry, more mature CMOS technology achieves lower production costs. Thus, the reference voltage generator in  FIG. 1  implemented by BJTs has the disadvantage of higher price compared to some products. Moreover, the bandgap of silicon, being about 1.2V to 1.3V, cannot satisfy future trends in low power applications. 
   Due to lower costs and more mature technology, a voltage generator of another prior art is implemented by MOSFETs. In this case, the voltage is generated by operating a MOS device in the sub-threshold region. 
   When a MOS device is operating in the sub-threshold region, if the device is given a fixed drain current, the voltage difference between the gate and the source of the device will linearly decrease with an increase of ambient temperature. In other words, the voltage difference shows a negative temperature coefficient in this situation. Please refer to  FIG. 3 ;  FIG. 3  illustrates a voltage generator  300  utilizing the negative temperature coefficient of a MOS device according to the prior art. The voltage generator  300  has two parts. The first part includes MOS MM 1  to MOS MM 4 , and a resistor R 1 , wherein the MOS MM 1  is designed to operate in the sub-threshold region and the current IRR 1  through the resistor RR 1  relates to the voltage difference between the gate and the source of the MOS MM 1 . The second part includes MOS MM 5  to MOS MM 11  and the resistors RR 2 , RR 3  and RR 4 . The second part generates an output voltage VR by compensating the current IRR 1  of a negative temperature coefficient and a current of a positive temperature coefficient. The voltage generating method not only has lower production costs but also can generate a lower reference voltage to provide a small voltage bias for low power circuits. 
   However, the prior art in  FIG. 3  has the disadvantage that although the generated voltage is stable with respect to temperature variation, the actual voltage output of the circuit will deviate from the design value due to processing variation. Therefore, the voltage generators in the second prior art have different output voltages if implemented by different process corners. 
   SUMMARY OF INVENTION 
   It is therefore an objective of the claimed invention to provide a voltage generator in order to solve the abovementioned problems. 
   According to the claimed invention, a voltage generator comprises a positive temperature coefficient current generating module, wherein an output current of the positive temperature coefficient current generating module increases with a rising ambient temperature; a negative temperature coefficient current generating module, wherein an output current of the positive temperature coefficient current generating module decreases with rising ambient temperature; a current fine-tune module used for adjusting the output current of the negative temperature coefficient current generating module; and a voltage output module, connected to the positive temperature coefficient current generating module and the negative temperature coefficient current generating module for generating an output voltage according to the positive temperature coefficient current generating module and the negative temperature coefficient current generating module. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  illustrates temperature variation versus Vsub in a diode-like device. 
       FIG. 2  illustrates a reference voltage generator implementing the bandgap voltage principle. 
       FIG. 3  illustrates a voltage generator utilizing the negative temperature coefficient of a MOS device according to the prior art. 
       FIG. 4  illustrates function blocks of a voltage generator according to the present invention. 
       FIG. 5  illustrates one embodiment of the positive temperature coefficient current generating module. 
       FIG. 6  illustrates one embodiment of the negative temperature coefficient current generating module. 
       FIG. 7  illustrates a current fine-tune module. 
       FIG. 8  illustrates the voltage output module. 
       FIG. 9  illustrates a positive temperature coefficient current generating module. 
       FIG. 10  illustrates a negative temperature coefficient current generating module. 
       FIG. 11  illustrates the preferred embodiment of a voltage generator according to the present invention. 
       FIG. 12  illustrates another embodiment of the voltage generator according to the present invention. 
       FIG. 13  illustrates another embodiment of the voltage generator according to the present invention. 
       FIG. 14  illustrates another embodiment of the voltage generator according to the present invention. 
       FIG. 15  illustrates another embodiment of the voltage generator according to the present invention. 
       FIG. 16  illustrates another embodiment of the voltage generator according to the present invention. 
       FIG. 17  illustrates another embodiment of the voltage generator according to the present invention. 
       FIG. 18  illustrates another embodiment of the voltage generator according to the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 4 .  FIG. 4  illustrates function blocks of a voltage generator  10  according to the present invention. The voltage generator  10  comprises a positive temperature coefficient current generating module  11 , a negative temperature coefficient current generating module  12 , a current fine-tune module  13 , and a voltage output module  14 . The positive temperature coefficient current generating module  11  is used to generate a current of a positive temperature coefficient (a current of a positive temperature coefficient means that when the ambient temperature rises, the current will increase, wherein the increasing slope of the current is the positive temperature coefficient). The negative temperature coefficient current generating module  12  is used to generate a current of negative temperature coefficient (Similarly, a current of a negative temperature coefficient means that when the ambient temperature rises, the current will decrease, wherein the decreasing slope of the current is the negative temperature coefficient). The current fine-tune module  13  is used to adjust the output current of the negative temperature coefficient current generating module  12 . The voltage output module  14 , being connected to two temperature coefficient current generating modules, is used to generate an output voltage according to the output current of the two temperature coefficient current generating modules. 
     FIG. 5  illustrates one embodiment of the positive temperature coefficient current generating module  11 . In this embodiment, the positive temperature coefficient current generating module  11  comprises NMOS M 8  and M 9 , resistor R 2  and a current mirror Mir 6 . The drain and the gate of NMOS M 8  are connected to the gate of MOS M 9  and the source of NMOS M 8  is connected to ground. The source of NMOS M 9  is connected to ground through resistor R 2 . Both the drains of NMOS M 8  and NMOS M 9  are connected to current mirror Mir 6 . The current I A  through the drain of MOS M 9  is the current of the positive temperature coefficient. The current mirror Mir 6  comprises PMOS M 6  and M 7 . PMOS M 6  and M 7  not only help NMOS M 8  and NMOS M 9  operate in the sub-threshold region, but also generate a current that is some multiple of the current I A . In the circuit of  FIG. 5 , NMOS M 8  and M 9  are operated in the sub-threshold region so that the drain currents of NMOS M 8  and M 9  are stable and regulated against variation of the power supply. The magnitude of the current I A  relates to the ratio W/L of MOS M 8  and MOS M 9  (W and L are the width and the length of a MOS, respectively). The current I A  is also a function of the resistor R 2 . For example, if we define the W/L of NMOS M 8  and NMOS M 9  as P 8  and P 9  respectively. The output current I A  can be expressed in the following: 
         I   A     =         ϛV   T       R   2       ⁢     ln   ⁡     (       P   9       P   8       )                       wherein V T  is a coefficient proportional to the absolute temperature, and ζ is a ratio constant related to the characteristic of a MOS device operating in the sub-threshold region. From above we know that the current I A  is decided by the resistor R 2  and W/L of NMOS M 8  and M 9  and is proportional to the ambient absolute temperature. Therefore, the output current I A  is a current of a positive temperature coefficient.       
   Please refer to  FIG. 6 .  FIG. 6  illustrates one embodiment of the negative temperature coefficient current generating module  12 . The negative temperature coefficient current generating module  12  comprises an NMOS M 3 , a resistor R 1 , current mirrors Mir 1  and Mir 2 . The gate of NMOS M 3  is connected to one end of resistor R 1  and the other end of resistor R 1  is connected to ground. The source of NMOS M 3  is connected to ground and the drain of NMOS M 3  is connected to current mirror Mir 1 . The current mirror Mir 1 , comprising a PMOS M 1 , is used to mirror an outside reference current and inject a current output into NMOS M 3 . The injection current should be small enough to force NMOS M 3  to operate in the sub-threshold region, so the voltage VGS 3  between the gate and the source of NMOS M 3  is constant for a fixed temperature. The voltage VGS 3  is representative of a negative temperature coefficient and can generate a current of the negative temperature coefficient, i.e. the output current of the negative temperature coefficient current generating module when applied to the resistor R 1 . The current mirror Mir 2 , comprising a PMOS M 2 , can mirror the output current IR 1  to generate a current that is some multiple of the current IR 1 . In the preferred embodiment of the negative temperature coefficient current generating module  12 , the outside reference current that the current mirror Mir 1  mirrors is the output current I A  of the positive temperature coefficient current generating module  11 . The output current I A  is utilized to avoid the need for an extra circuit for generating a reference current. 
   Please refer to  FIG. 7 .  FIG. 7  illustrates a current fine-tune module  13 . The current fine-tune module comprises at least one fine-tune unit  18  and the adjusting ability of each fine-tune unit  18  is freely set. The fine-tune unit  18  comprises a current source and a switch. In the embodiment, the current fine-tune module  13  comprises three fine-tune units, the fine-tune unit CT 1 , the fine-tune unit CT 2 , and the fine-tune unit CT 3 . The current source of the fine-tune unit CT 1  is designed to be ‘K’ times the output current I A  (of the positive temperature coefficient current generating module), wherein K is a constant. The current source of the fine-tune unit CT 2  is designed as 2K times the output current I A  and the current source of the fine-tune unit CT 3  is designed as 4KI A . The current of the three fine-tune units is summed to form the output current I C  of the current fine-tune module. The switch of each fine-tune unit digitally controls the output current I C . Therefore, the current I C  of the embodiment ranges from 0 to 7KI A  in increments of 1KI A . Of course, the number of fine-tune units is not limited to three. If there are N fine-tune units, for example, the output current I C  of the current fine-tune module will range from 0 to (2 N −1)KI A  with in increments of 1I A . The current source of the embodiment is implemented by the current mirror of an NMOS device or a PMOS device, which mirror the output current I to generate a current of some multiple of the current I A . However, the current source can be implemented in other ways. 
   Please refer to  FIG. 8 .  FIG. 8  illustrates the voltage output module  14 . The voltage output module  14  comprises current mirrors Mir 10  and Mir 11  and a resistor R 3 . Current mirror Mir 10  comprises a PMOS M 10  and current mirror Mir 11  comprises a PMOS M 11 . The sources of PMOS M 10  and M 11  are connected to the power supply V DD , and the drains are connected to one end of the resistor R 3 , the node VR shown in  FIG. 8 . The other end of the resistor R 3  is connected to ground. The current mirrors Mir 10  and M 11  mirror the output currents of the positive temperature coefficient current generating module  11  and the negative temperature coefficient current generating module  12  respectively with some multiple, the two mirrored currents are summed and injected into the resistor R 3  to obtain the output voltage of the voltage output module  14  at the node VR. 
   Please refer to  FIG. 9 .  FIG. 9  illustrates a positive temperature coefficient current generating module  51 . The positive temperature coefficient current generating module  51  comprises PMOS M 108  and M 109 , a resistor R 102  and a current mirror Mir 106 . The source and the gate of PMOS M 108  and M 109  are connected together. The source of MOS  108  is connected to the power supply V DD . The source of MOS M 109  is connected to the power supply V DD  through resistor R 102 . The drains of MOS M 108  and MOS M 109  are connected to the current mirror Mir 106 . The current I A  through the drain of the PMOS M 109  is an output current of positive temperature coefficient. The current mirror Mir 106  comprises NMOS M 106  and M 107 . As mentioned before, NMOS M 106  and M 107  help PMOS M 108  and M 109  operate in the sub-threshold region and generate a current that is a multiple of the current I A . If we define the ratio W/L of MOS M 108  and M 109  as P 108  and P  109 , respectively, the output current I A  can be expressed by the following equation: 
         I   A     =         ϛV   T       R   2       ⁢     ln   ⁡     (       P   109       P   108       )             
 
   Please refer to  FIG. 10 .  FIG. 10  illustrates a negative temperature coefficient current generating module  52 . The negative temperature coefficient current generating module  52  comprises a PMOS M 103 , a resistor R 101 , current mirrors Mir 101  and Mir 102 . The gate of PMOS M 103  connects to one end of resistor R 101  and the other end of the resistor R 1  is connected to V DD . The source of PMOS M 103  is connected to ground and the drain of PMOS M 103  is connected to current mirror Mir 101 . Current mirror Mir 101 , comprising an NMOS M 101 , is used to mirror an outside reference current and inject an output current into PMOS M 103  to force PMOS M 103  to operate in the sub-threshold region. The current through resistor R 101  is representative of a negative temperature coefficient. The current mirror Mir 102  comprises an NMOS M 102 , na NMOS M 122 , and a PMOS M 132  to generate a current that is some multiple of the current IR 101 . 
   Please refer to  FIG. 11 .  FIG. 11  illustrates the preferred embodiment of a voltage generator according to the present invention. The voltage generator comprises a positive temperature coefficient current generating circuit  60 , a negative temperature coefficient current generating circuit  70 , a current fine-tune circuit  80 , and a voltage outputting circuit  90 . The positive temperature coefficient current generating circuit  60  comprises NMOS M 208  and M 209 , a resistor R 2  and a current mirror Mir 206 . The drain and gate of NMOS M 208  are connected to the gate of MOS M 209  and the source of NMOS M 208  is connected to ground. The source of NMOS M 209  is connected to ground through resistor R 202 . The drain current of NMOS M 209  passes through the current mirror Mir 206 , generating an output current I A  being representative of a positive temperature coefficient. Both NMOS M 208  and M 209  operate in the sub-threshold region so that the output current I A  from the drain of MOS M 203  is regulated against variation of the power supply. The current mirror Mir 206  comprises PMOS M 206 , M 207  and M 207 , and is used to mirror the output current I A  with some multiple to other blocks of the voltage generator. 
   The negative temperature coefficient current generating circuit  70  comprises an NMOS M 203 , a resistor R 201 , current mirrors Mir 201  and Mir 202 . The gate of NMOS M 203  connects to one end of the resistor R 201  and the other end of the resistor R 201  is connected to ground. The source of NMOS M 203  is also connected to ground. The current mirror Mir 201  mirrors the current I A  and injects it into the drain of NMOS M 203  to force NMOS M 203  to operate in the sub-threshold region. Therefore, the current through the resistor R 201  is a current representative of a negative temperature coefficient. The purpose of the current mirror Mir 202  is to mirror the output current of the negative temperature coefficient current generating circuit  70  to the voltage outputting circuit  90 . If the negative temperature coefficient current generating circuit  70  is not equipped with the current fine-tune circuit  80  to fine tune the output current, the current mirror Mir 202  would directly mirror the output current IR 1 . However, in the embodiment, the negative temperature coefficient current generating circuit  70  is combined with the current fine-tune circuit  80  to generate the output current I B  (as shown in  FIG. 6 ). Therefore, the current mirror Mir 202  mirrors the current I B . The current I B  relates to the current I C  and IR 1  in  FIG. 11  and will be explained in detail below. 
   The current fine-tune circuit  80  can comprise three fine-tune units. The first fine-tune unit comprises PMOS MP 1  as a switch, and PMOS MC 1  as a current source. The second fine-tune unit comprises PMOS MP 2  as a switch, and PMOS MC 2  as a current source. The third fine-tune unit comprises PMOS MP 3  as a switch, and PMOS MC 3  as a current source. PMOS MC 1 , MC 2 , and MC 3  act like current mirrors, mirroring the output current I A  of the positive temperature coefficient current generating circuit  60  with some multiple. Therefore, in the current fine-tune circuit  80 , the first fine-tune unit provides fine-tune current 1K I A , wherein K is the ratio of W/L of two MOS devices in the current mirror, such as the ratio of MOS M 207  W/L P 207  and MC 1  W/L P MC1 , 
       MC1     M   207         
 
   The second fine-tune unit provides the fine-tune current 2KI A , and the third fine-tune unit provides fine-tune current 4KI A . The three fine-tune currents are summed as an output current I C . Controlled digitally by the switches MP 1 , MP 2  and MP 3 . The current I c  can be tuned to 0, 1KI A , 2KI  A , 3KI A , 4KI A , . . . 7KI A . To describe in detail, suppose that W/L of PMOS M 207  in the positive temperature coefficient current generating circuit  60  is P  207 , and W/L of three current sources in the current fine-tune circuit are P C1 , P C2 , and P C3 , respectively. The current I C  can be expressed as follows: 
           I   C     =       (           P   C1       P   207       ⁢     ϕ   1       +         P   C2       P   207       ⁢     ϕ   2       +         P   C3       P   207       ⁢     ϕ   3         )     ⁢     I   A         ,     and   ⁢           ⁢     ϕ   1       ,     ϕ   2     ,     ϕ   3         
         are 1 or 0 that represents on or off condition of a switch. The negative temperature coefficient current generating circuit  70  combined with the current fine-tune circuit  80  is used to fine decrease the output current I B  of the negative temperature coefficient current generating circuit  70 , wherein the currents I B , I C  and IR 1  will satisfy the following relationship:
 
 I   B   =IR   201 − I   C  
       

   Therefore, the increase of the current I C  will decrease the output current I B  to achieve the function of fine-tuning. 
   The voltage outputting circuit  90  connected to the positive and the negative temperature coefficient current generating circuits  60 ,  70  comprises PMOS M 210 , PMOS M 211  and resistor R 203  and generates an output voltage VR according to the output currents of the positive and the negative temperature coefficient current generating circuits  60 ,  70 . PMOS M 210  and M 211  act like current mirrors, wherein PMOS M 211  mirrors the output current I A  of the positive temperature coefficient current generating circuit  60  and PMOS M 210  mirrors the output current I B  of the negative temperature coefficient current generating circuit  70 . Two mirrored currents are summed to form an output voltage VR through the resistor R 203 . Suppose that P represents W/L of a MOS device. Therefore, P 201  represents W/L of PMOS M 201  and P 209  represents W/L of PMOS M 209 , and vice versa. Set 
         N   =     (           P   C1       P   207       ⁢     ϕ   1       +         P   C2       P   207       ⁢     ϕ   2       +         P   C3       P   207       ⁢     ϕ   3         )       ,       
         wherein VGS 203  represents the voltage between the gate and the source of NMOS M 203 . We can obtain the expression of output voltage V: 
           V   R     =           P   211       P   202       ⁢       R   203       R   201       ⁢     V   GS203       +       (         P   210       P   207       -     N   ⁢       P   211       P   202           )     ⁢       R   203       R   202       ⁢     ςV   T     ⁢     ln   ⁡     (       P   209       P   208       )             ,       
   VR is determined by 
           P   210       P   207       *       
           R   203       R   202       ⁢           ⁢   and   ⁢           ⁢       P   211       P   202       *       
           R   203       R   201       ,       
   so VR is easier to design by controlling the coefficient involved in the multiplication of 
             P   210       P   207       ⁢           ⁢   and   ⁢           ⁢       R   203       R   202         ,       
   as well as the multiplication of 
           P   211       P   202       ⁢           ⁢   and   ⁢           ⁢         R   203       R   201       .         
       

   Because N 
         P   211       P   202         
         is the term for fine tuning, 
           P   210       P   207       &gt;&gt;     N   ⁢           ⁢         P   211       P   202       .           
       

   Please refer to  FIG. 12 .  FIG. 12  illustrates another embodiment of the voltage generator according to the present invention. The voltage generator comprises a positive temperature coefficient current generating circuit  160 , a negative temperature coefficient current generating circuit  170 , a current fine-tune circuit  180 , and a voltage outputting circuit  190 . In the embodiment, the principle of the current fine-tune circuit  180  is similar to the current fine-tune circuit  80  in  FIG. 11 . However, the current fine-tune circuit in  FIG. 11  is used to fine decrease the output current of the negative temperature coefficient current generating circuit, but this embodiment is to fine increase the output current of the negative temperature coefficient current generating circuit. The current fine-tune circuit comprises three fine-tune units that are composed of three switches MC 301 , MC 302  and MC 303  as well as three NMOS MP 301 , MP 302  and MP 303  serving as the current sources. The gates of MOS MP 301 , MP 302  and MP 303  are connected to the gate of NMOS M 309  of the positive temperature coefficient current generating circuit  160 , so NMOS MP 301 , MP 302 , MP 303  and NMOS M 309  form three sets of current mirrors which generate three current sources in the current fine-tune circuit  180  according to the drain current I A  of NMOS M 309 . Of course, the currents of the three fine-tune units can be designed as any multiple of a reference current. Finally, the currents of the three fine-tune units are summed to become the fine-tune current I C  for effecting fine increases in the output current I B  of the negative temperature coefficient current generating circuit  170 . The current I B  can be expressed in the following way:
 
 I   B   =IR   301 + I   C  
 
   Please refer to  FIG. 13 .  FIG. 13  illustrates another embodiment of the voltage generator according to the present invention. The voltage generator comprises a positive temperature coefficient current generating circuit  260 , a negative temperature coefficient current generating circuit  270 , a current fine-tune circuit  280 , and a voltage outputting circuit  290 . The positive temperature coefficient current generating circuit  260  comprises PMOS M 408 , PMOS M 409 , resistor R 402  and current mirror Mir 406 . The source and the gate of PMOS M 408  and M 409  are connected together. The source of MOS  408  is connected to the power supply V DD . The source of MOS M 109  is connected to the power supply V DD  through resistor R 402 . Both PMOS M 408  and M 409  operate in the sub-threshold region, the output current I A  of the positive temperature coefficient is generated by the drain of PMOS M 409 . The current mirror Mir 406  comprises NMOS M 406  and M 407 , which mirror the output current I A  to other blocks of the voltage generator. The negative temperature coefficient current generating circuit  270  comprises PMOS M 403 , resistor R 401 , and two current mirrors Mir 401  and Mir 402 . The gate of PMOS M 403  connects to one end of resistor R 401  and the other end of resistor R 401  is connected to the supply V DD . The source of NMOS M 403  is also connected to the power supply V DD . The current mirror Mir 401  mirrors the current I A  and injects it into the drain of PMOS M 403  to force PMOS M 403  to operate in the sub-threshold region. Therefore, the current through resistor R 401  is a current representative of a negative temperature coefficient. In addition, the current mirror Mir 402  comprises NMOS M 402 , NMOS M 422  and PMOS M 432 , and mirrors the output current of the negative temperature coefficient current generating circuit  270  to the voltage outputting circuit  290 . 
   The current fine-tune circuit  280  is similar to the current fine-tune circuit  180  in  FIG. 12 . In this embodiment, the current fine-tune circuit  280  is used to fine decrease the output current of the negative temperature coefficient current generating circuit  270  so that the output current I B  of the negative temperature coefficient current generating circuit  270 , and the output current I C  of the current fine-tune circuit  280 , satisfy the following relationship:
 
 I   B   =IR   401 − I   C  
 
   The voltage outputting circuit  290 , similar to the voltage outputting circuit  90  in  FIG. 11 , comprises a PMOS M 410 , a PMOS M 411  and a resistor R 403 . The gate of PMOS M 410  is connected to the gate of PMOS M 409  of the positive temperature coefficient current generating circuit  260 . The gate of PMOS M 411  connected to the gate of PMOS M 432  of the negative temperature coefficient current generating circuit  270  functions as a current mirror to mirror the output current I A  of the positive temperature coefficient current generating circuit  260 , and the output current I B  of the negative temperature coefficient current generating circuit  270 , to become two mirror currents and these two mirror currents are summed through resistor R 403  to generate the output voltage VR. 
   Please refer to  FIG. 14 .  FIG. 14  illustrates another embodiment of the voltage generator according to the present invention. The embodiment in  FIG. 14  is similar to the embodiment in  FIG. 13 , wherein the voltage generator comprises a positive temperature coefficient current generating circuit  360 , a negative temperature coefficient current generating circuit  370 , a current fine-tune circuit  380 , and a voltage outputting circuit  390 . However, in this embodiment, the current fine-tune circuit  380  is used to fine increase the output current of the negative temperature coefficient current generating circuit  370 , instead of fine decreasing the output current in the embodiment of  FIG. 13 . The structure and the principle of the current fine-tune circuit  380  is similar to the current fine-tune circuit  70  in  FIG. 11 . The output current I C  generated by the current fine-tune circuit  380  and the output current I B  generated by the negative temperature coefficient current generating circuit  370  have the following relationship:
 
 I   B   =IR   501 + I   C  
 
   Please refer to  FIG. 15 .  FIG. 15  illustrates another embodiment of the voltage generator according to the present invention. The embodiment in  FIG. 15  is similar to the embodiment in  FIG. 11 , wherein the voltage generator comprises a positive temperature coefficient current generating circuit  460 , a negative temperature coefficient current generating circuit  470 , a current fine-tune circuit  480 , and a voltage outputting circuit  490 . However, the positive temperature coefficient current generating circuits in  FIG. 15  and  FIG. 11  are different. The positive temperature coefficient current generating circuit  460  similar to the positive temperature coefficient current generating circuit  260  in  FIG. 13  comprises a PMOS M 508 , a PMOS M 509 , a resistor R 502 , and a current mirror Mir 506 . As shown in  FIG. 15 , The source and the gate of PMOS M 508  and M 509  are connected together. The source of MOS  508  is connected to the power supply V DD . The source of PMOS M 509  is connected to the power supply V DD  through resistor R 502 . Both the PMOS M 508  and M 509  operate in the sub-threshold region, the output current I A  of the positive temperature coefficient is generated by the drain of PMOS M 509 . The current mirror Mir 506  comprises NMOS M 506  and M 507 , which mirror the output current I A  with some multiple to other blocks of the voltage generator. 
   Please refer to  FIG. 16 .  FIG. 16  illustrates another embodiment of the voltage generator according to the present invention. The voltage generator comprises a positive temperature coefficient current generating circuit  560 , a negative temperature coefficient current generating circuit  570 , a current fine-tune circuit  580 , and a voltage outputting circuit  590 . The embodiment in  FIG. 16  is similar to that in  FIG. 15 , but the current fine-tune circuit  580  is different. In this embodiment, the principle of the current fine-tune circuit  580  is the same with the current fine-tune circuit  180  in  FIG. 12 , i.e. to fine increase the output current of the negative temperature coefficient current generating circuit. 
   Please refer to  FIG. 17 .  FIG. 17  illustrates another embodiment of the voltage generator according to the present invention. The voltage generator comprises a positive temperature coefficient current generating circuit  660 , a negative temperature coefficient current generating circuit  670 , a current fine-tune circuit  680 , and a voltage outputting circuit  690 . The embodiment in  FIG. 17  is similar to that in  FIG. 13 , but the positive temperature coefficient current generating circuit  660  is different. The positive temperature coefficient current generating circuit  660  in  FIG. 17  is the same as that in  FIG. 12 . 
   Please refer to  FIG. 18 .  FIG. 18  illustrates another embodiment of the voltage generator according to the present invention. The voltage generator comprises a positive temperature coefficient current generating circuit  760 , a negative temperature coefficient current generating circuit  770 , a current fine-tune circuit  780 , and a voltage outputting circuit  790 . This embodiment is similar to that in  FIG. 17 , but the current fine-tune circuit  780  is different. The principle of the current fine-tune circuit  780  is the same as the current fine-tune circuit  80  in  FIG. 11 , i.e. to fine increase the output current of the negative temperature coefficient current generating circuit. 
   In the prior art, diodes and an amplifier are specially arranged to compensate a current of a positive temperature coefficient and a current of a negative temperature coefficient so that the output of the amplifier obtains a reference voltage regulated against variation of the ambient temperature. However, the prior art cannot satisfy the demand for lower costs and lower voltage output power supplies in the modern electronics market. In another prior art, the characteristic of a MOS device operating in the sub-threshold region is utilized to implement a voltage generator, but the output reference voltage of the chip of the voltage generator often deviates from the designed value due to process variation. Compared to the prior art, the voltage generator of the present invention takes advantages of CMOS technology to generate a current of a positive temperature coefficient and a current of a negative temperature coefficient by operating MOS devices in the sub-threshold region. Moreover, a mechanism to fine-tune the current of the negative temperature coefficient is included. Therefore, the present invention has the advantages of low production cost, stable output voltage of a voltage generator regulated against process variation and changes in ambient temperature. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 8