Patent Abstract:
A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to integrated circuit (IC) devices, and particularly to a semiconductor device suitable for application in high-voltage operation and a method for fabricating the same. 
         [0003]    2. Description of the Related Art 
         [0004]    Recently, as fabrication techniques for semiconductor integrated circuits (ICs) develop, the demands on elements such as controllers, memory, low-voltage operation circuits and high-voltage operation circuits formed over a single chip are also increasing to form a single-chip system with increased integration. 
         [0005]    In a single-chip system, a high-voltage device such as an insulated gate bipolar transistor (IGBT) is usually used to improve the power conversion efficiency and reduce electricity loss. The IGBT has the advantages of, for example, high current gain, high operating voltage, and low on-state resistance, and is useful in high-voltage operation applications. 
         [0006]    However, with the ongoing trend of size reduction of the single-chip system, an IGBT is needed to comply with the trend of size reduction and maintain predetermined or increased current densities and on-state resistances. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    An exemplary semiconductor device comprises a semiconductor, first, second, and third isolations, a first doped well region, a first doped region, a second doped well region, second, third, and fourth doped regions, a first gate structure, and a second gate structure. The semiconductor layer has a first conductivity type. The first, second, and third isolations are formed separately over a portion of the semiconductor layer, thereby defining a first region between the first and second isolations, and a second region between the second and third isolations. The first doped well region is disposed in a portion of the semiconductor layer in the first region and has the first conductivity type. The first doped region is disposed in the first doped well region and has a second conductivity type opposite to the first conductivity type. The second doped well region is disposed in a portion of the semiconductor layer in the second region and has the second conductivity type and an asymmetric cross-sectional profile. The second, third, and fourth doped regions are proximately disposed in the second doped well region, wherein the second and fourth doped regions have dopants of the first conductivity type, and the third doped region has dopants of the second conductivity type. The first gate structure is disposed in a portion of the semiconductor layer in the second region to partially cover the second doped well region. A second gate structure is embedded in a portion of the semiconductor layer in the second region and penetrates a portion of the second doped well region. 
         [0008]    An exemplary method for fabricating a semiconductor device comprises providing a semiconductor layer, having dopants of a first conductivity type. A first doped well region and a second doped well region are formed in a portion of the semiconductor layer, wherein the first doped well region has dopants of the first conductivity type, and the second doped well region has dopants of a second conductivity type opposite to the first conductivity type and a symmetric cross-sectional profile. First, second and third isolations are formed over the semiconductor layer, wherein the first and second isolations partially cover a portion of the first doped well region and defines a first region between the first and second isolation, and the third isolation is adjacent to the second doped well region and defines a second region between the second and third isolations. A patterned mask layer having an opening therein is formed over the semiconductor layer, herein the opening exposes a portion of the second doped well region. A trench is funned through the portion of the second doped well region exposed by the opening and a first doped region in a portion of the second doped well region exposed by the trench and a portion of the semiconductor layer under the second doped well region, wherein the first doped region has dopants of the first conductivity type. The patterned mask layer is removed. A thermal diffusion process is performed to diffuse the dopants of the first conductivity type of the first doped region into the second doped well region adjacent thereto, and makes the symmetric cross-sectional profile into an asymmetric cross-sectional profile, wherein a bottom surface of a portion of the second doped web region adjacent to the trench is closer to a top surface of the semiconductor layer than other portions of the second doped well region. A first gate structure is formed over a portion of the semiconductor layer in the second region and a second gate structure in the trench, wherein the first gate structure partially covers the second isolation and the second doped web region. Second, third, fourth and fifth doped regions are formed, wherein the second doped region is formed in a portion of the first doped well region and has dopants of the second conductivity type, and the third and fifth doped regions are formed in a portion of the second doped well region and has dopants of the first conductivity type, and the fourth doped region is formed in a portion of the second doped well region and is between the third and fifth doped regions and has dopants of the second conductivity type. 
         [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  is schematic cross-sectional view showing a semiconductor device according to an embodiment of the invention; and 
           [0012]      FIGS. 2-9  are schematic cross-sectional views showing a method for fabricating a semiconductor device according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0014]      FIG. 1  is a schematic cross-sectional view showing an exemplary semiconductor device  10  comprising an insulated gate bipolar transistor (IGBT) known by the inventor. The semiconductor device  10  is suitable for high-voltage operation applications. 
         [0015]    Herein, the semiconductor device  10  is used as a comparative embodiment, and only one insulated gate bipolar transistor (IGBT) in the semiconductor device  10  is partially illustrated in  FIG. 1  to describe issues such as the driving current reduction of the semiconductor device  10  which happens currently with the trend of size reduction. 
         [0016]    As shown in  FIG. 1 , the semiconductor device  10  comprises a semiconductor-on-insulator (SOI) substrate  12 . The SOI substrate  12  comprises a bulk semiconductor layer  14 , and a buried insulating layer  16  and a semiconductor layer  18  sequentially stacked thereover. The bulk semiconductor layer  14  and the semiconductor layer  18  may comprise semiconductor materials such as silicon, and the buried insulating layer  16  may comprise insulating materials such as silicon dioxide. The semiconductor layer  18  may comprise dopants of a first conductivity type, for example n-type. In the semiconductor device  10 , a deep trench isolation  20  is formed in a portion of the semiconductor layer  18 , and the deep trench isolation  20  penetrates the semiconductor layer  18  and arrives the buried insulating layer  16 , thereby defining an active region (not shown) for disposing the IGBT. The deep trench isolation  20  may comprise insulating materials such as silicon dioxide. 
         [0017]    In addition, three isolations  22 ,  24  and  26  are formed separately over the semiconductor layer  18 , and a source region  28  and a drain region  30  are thus defined over the surface of the semiconductor layer  18 . Herein, the isolations  22 ,  24  and  26  are illustrated as field oxides (FOXs) formed over a portion over the surface of the semiconductor layer  18 . The source region  28  is a region substantially between the isolations  22  and  24 , and the drain region  30  is a region substantially between the isolations  24  and  26 . In addition, a gate structure  32  is further formed over the semiconductor layer  18 . The gate structure  32  is formed over a portion of the semiconductor layer  18  in the source region  28  and extends over a portion of the isolation  24  adjacent to the source region  28 . Herein, the gate structure  32  comprises a gate dielectric layer  34  and a gate electrode  36 . The gate dielectric layer  34  is only formed over the surface of the semiconductor layer  18 , and the gate electrode  36  is formed over the gate dielectric layer  34  and further extends to cover a portion of the isolation  24  adjacent thereto. 
         [0018]    Moreover, a doped well region  38  is formed in a portion of the semiconductor layer  18  in the drain region  30 , having dopants of the first conductivity type the same as that of the semiconductor layer  18 . The dopant concentration in the doped well region  38  is greater than that of the semiconductor layer  18 . A doped region  40  is further formed in the doped well region  38 , having dopants of a second conductivity type, for example p-type, opposite to the first conductivity type of the doped well region  38  and the semiconductor layer  18 . Herein, the dopant concentration in the doped region  40  is greater than the dopant concentration in the doped well region  38 . In addition, a doped well region  42  is formed in a portion of the semiconductor layer  18  in the source region  28 , having dopants of the second conductivity type, for example p-type, opposite to that of the semiconductor layer  18 . Two adjacent doped regions  46  and  44  are formed in the doped well region  42  and the doped regions  46  and  44  are surrounded by the doped well region  42 . The doped region  46  comprises dopants of the second conductivity type opposite to that of the semiconductor layer  18 , and the doped region  44  comprises dopants of the first conductivity type the same as that of the semiconductor layer  18 . Dopant concentrations of the doped regions  44  and  46  are greater than the dopant concentration of the doped well region  42 . Herein, the gate structure  32  covers a portion of the doped well region  42  and the doped region  44 . 
         [0019]    In one embodiment, the first conductivity type in the semiconductor device  10  is n-type and the second conductivity type in the semiconductor device  10  is p-type. Thus, the doped region  40  may function as an emitter of a PNP bipolar transistor, and the semiconductor layer  18  may function as a base of the PNP bipolar transistor, and the doped region  46  may function as a collector of the PNP bipolar transistor. In addition, the doped layer  40  may also function as a drain of an N-type high voltage metal-oxide-semiconductor (MOS) transistor, and the doped region  44  may function as a source of the N-type HV MOS transistor, and the gate structure  32  may function as a gate of the N-type HV MOS transistor. The portion of the gate structure  32  covering the doped region  42  may function as a channel of the N-type HV MOS transistor. 
         [0020]    During operation of the semiconductor device  10  comprising the IGBT shown in  FIG. 1 , a positive emitter voltage relative to the collector (i.e. the doped region  46 ) is applied to the doped region  40 , and a gate voltage greater than the threshold voltage of the N-type HV MOS transistor allows currents to pass through the N-type HV MOS transistor, thereby modulating the base currents which are connected to the collector and formed between the emitter and the collector. In addition, due to formation of the N-type HV MOS transistor, more base currents can be provided to the PNP bipolar transistor. Moreover, due to formation of the n-type semiconductor layer  18 , the voltage drop of the base currents in the base can be reduced. 
         [0021]    However, since the IGBT in the semiconductor device  10  comprise a planar type gate (i.e. the gate structure  32 ), aspects of electrical performances such as driving current and the on-state resistance thereof cannot be improved any further currently with the size reduction of the semiconductor device  10  and the region of the IGBT in the semiconductor device  10 . 
         [0022]    Accordingly, a semiconductor device comprising an insulated gate bipolar transistor IGBT) suitable for high-voltage operation applications and a method for fabricating the same are thus provided. The semiconductor device comprising the IGBT may maintain or improve electrical performance such as driving current and on-state resistance currently with the trend of size reduction. 
         [0023]      FIGS. 2-9  are schematic views showing an exemplary method for fabricating a semiconductor device  100  comprising an IGBT. Herein,  FIGS. 2-9  respectively show fabrication in an intermediate stage of the method for fabricating the semiconductor device  100 . 
         [0024]    In  FIG. 2 , a semiconductor substrate  102  is first provided. Herein, the semiconductor substrate  102  can be, for example, a semiconductor-on-insulator (SOI) substrate. The SOI substrate comprises a bulk semiconductor layer  104 , and a buried insulating layer  106  and a semiconductor layer  108  sequentially stacked over the hulk semiconductor layer  104 , The bulk semiconductor layer  104  and the semiconductor layer  108  may comprise semiconductor materials such as silicon, and the buried insulating layer  106  may comprise insulating materials such as silicon dioxide. The semiconductor layer  108  may comprise dopants of a first conductivity type, for example n-type. 
         [0025]    Next, implantation processes (not shown) such as ion implantation processes are performed using suitable implantation masks (not shown) to form a doped well region  112  in a portion of the semiconductor layer  108  in a source region  116  for defining an IGBT of the semiconductor device  100 , and a doped well region  110  in a portion of the semiconductor layer  108  in a drain region  114  for defining the IGBT of the semiconductor device  100 . Herein, the doped well region  112  has dopants of a second conductivity type, for example p-type, opposite to the first conductivity type of the semiconductor layer  108  and a symmetric cross-sectional profile, and the doped well region  110  as dopants of the first conductivity type the same with that of the semiconductor layer  108 . 
         [0026]    In  FIG. 3 , a deep trench isolation  118  and at least three isolations  120 .  122 , and  124  are next formed in and over the semiconductor layer  108 . Herein, the deep trench isolation  118  is formed in a portion of the semiconductor layer  108  adjacent to a side of the doped well region  112  and extends downward to reach the buried insulating layer  106 . The deep trench isolation  118  can be formed by etching a portion of the semiconductor layer  108  to first form a deep trench (not shown) exposing a portion of the buried insulating layer  106  and then filling the deep trench with insulating materials such as silicon dioxide. The isolations  120 ,  122 , and  124  can be formed by, for example, thermal oxidation by using suitable patterned masks, and thus are separately formed over various portions of the semiconductor layer  108 . Herein, the isolations  120 ,  122 , and  124  are field oxides of silicon dioxide which are formed by thermal oxidation. The isolation  120  is disposed over the semiconductor layer  108  between the doped well region  112  and the deep trench isolation  118 , and the isolations  122  and  124  are formed over the semiconductor layer  108  at opposite sides of the doped well region  110  and partially cover the doped well region  110 . 
         [0027]    In  FIG. 4 , a patterned mask layer  125  is next formed over the surface of the semiconductor layer  108  and covers the deep trench isolation  118  and the isolations  120 ,  122 , and  124 . An opening  126  is formed in the patterned mask layer  125  to expose a portion of the doped well region  112 . In one embodiment, the patterned mask layer  125  is a photoresist layer, and the opening  126  can thus he formed by processes such as photolithography and etching processes. Next, an ion implantation process  127  is performed, using the patterned mask layer  125  as an implantation mask, to implant dopants of the first conductivity type into a portion of the lower portion of the doped well region  112  exposed by the opening  126  and a portion of the semiconductor layer  108  thereunder, thereby forgoing a doped region  132 . Dosages and energies used in the ion implantation process  127  can be properly adjusted to control the location of the formed doped region  132 . 
         [0028]    In  FIG. 5 , an etching process (not shown) is performed next, using the patterned mask layer  125  as an etching mask, to remove the portion of the doped well region  112  exposed by the opening  126 , and form a trench  130  in the portion of the doped region exposed by the opening  126 . The trench  130  partially penetrates the doped well region  112  and exposes a top surface of the doped region  132 . In the above etching process, a portion of the doped region  132  (not shown) may be also etched and removed. 
         [0029]    In another embodiment, the sequence of the ion implantation process and the etching process performed in  FIGS. 4-5  may be reversed. As shown in  FIG. 6 , after forming the patterned mask layer  125  having the opening  126  over the semiconductor layer  108 , an etching process  128  is first performed, using the patterned mask layer  125  as an etching mask, to remove a portion of the doped well region  112  exposed by the opening  126 , and a trench  130  is formed in a portion of the doped well region  112  exposed by the opening  126 . The trench  130  partially penetrates the doped well region  112 . 
         [0030]    In  FIG. 7 , an ion implantation process (not shown) is performed, using the patterned mask layer  125  as an implant mask, to implant dopants of the first conductivity type to a portion of the doped well region  112  exposed by the trench  130  and a portion of the semiconductor layer  108  thereunder, thereby forming a doped region  132  under the trench  130  and a portion of the semiconductor layer  108  exposed by the trench  130 , and the trench  130  partially exposes the surface of the doped region  132 . 
         [0031]    In  FIG. 8 , after removal of the patterned mask layer  125  shown  FIGS. 4-7 , a thermal diffusion process (not shown), for example an annealing process, is then performed to diffuse the dopants of the first conductivity type in the doped region  132  into the adjacent doped well region  112  (see  FIGS. 5 and 7 ) and changes the symmetric cross-sectional profile of the doped well region  112 . The change to the cross-sectional profile is illustrated as the doped dwell region  112 ′ shown in  FIG. 8 . Herein, the doped dwell region  112 ′ no longer has a symmetric cross-sectional profile as that shown in  FIGS. 2-7  but an asymmetric cross-sectional profile. After the thermal diffusion process, the profile of the doped region  132  is also changed and identified with the reference number  132 ′ in  FIG. 8 . The diffused doped region  132 ′ covers a lower portion of the trench  130 . 
         [0032]    Next, two gate structures  140  and  150  are separately formed over the semiconductor layer  108 . The gate structure  140  is formed over the semiconductor layer  108  between the doped well region  112  and the isolation  122 , and the gate structure  150  is formed in the trench  130  and fills the same. Herein, the gate structures  140  and  150  respectively comprise a gate dielectric layer  134  and a gate electrode layer  136 . The gate dielectric layer  134  and a gate electrode layer  136  in gate structure  140  and  150  can be formed in the same processes, and the fabrication and materials thereof can be the same as those of the conventional gate dielectric layer and gate electrode layer, and are not described herein. 
         [0033]    In  FIG. 9 , through the usage of suitable imp an masks (not shown) and operations of several implantation processes such as ion implantation processes, a doped region  152  is formed in a portion of the doped dwell region  1110 , and a plurality of adjacent doped regions  154 ,  156 ,  158 , and  160  are formed in the doped well region  112 ′. Herein, the doped regions  152 ,  154 , and  158  have dopants of the second conductivity type opposite to the first conductivity type of the semiconductor layer  108 , and the doped regions  156  and  160  have dopants of the first conductivity type the same as that of the semiconductor layer  108 . The concentration of the doped regions  152 ,  154 ,  156 ,  158 , and  160  are greater than the doped well region  110  or  112 ′ adjacent thereto. 
         [0034]    As shown in  FIG. 9 , a method for fabricating the semiconductor device  100  comprising an IGBT device is substantially completed. Additional contacts, interconnects, and insulating layers can be sequentially formed in the sequential processes to form related connection circuits, and the fabrication of these components is not described here for simplicity. 
         [0035]    In one embodiment, the first conductivity type in the semiconductor device  100  shown in  FIG. 9  is n-type and the second conductivity type in the semiconductor device  100  is p-type. Thus, the doped region  152  may function as an emitter of a PNP bipolar transistor, and the semiconductor layer  108  may function as a base of the PNP bipolar transistor, and the doped region  158  may function as a collector of the PNP bipolar transistor. 
         [0036]    In addition, the doped region  152  may also function as a drain of an N-type high voltage metal-oxide-semiconductor (MOS) transistor comprising the gate structure  140 , and the doped region  160  may function as a source of the N-type HV MOS transistor comprising the gate structure  140 , and the gate structure  140  may function as a gate of the N-type HV MOS transistor. The portion of the gate structure  140  covering the doped region  112 ′ may function as a channel of the N-type HV MOS transistor. 
         [0037]    Moreover, another N-type metal-oxide-semiconductor (MOS) transistor is disposed in the semiconductor device  100 , comprising the gate structure  150 . The doped region  152  may also function as a drain of an N-type metal-oxide-semiconductor (MOS) transistor comprising the gate structure  150 , and the doped region  156  may function as a source of the N-type MOS transistor comprising the gate structure  150 , and the gate structure  150  may function as a gate of the N-type MOS transistor. The portion of the doped region  112 ′ covered by the gate structure  150  may function as a channel of the N-type MOS transistor, which is entitled as C 1  in  FIG. 9 . A bottom surface of the portion of the doped well region  112 ′ adjacent to the doped regions  156  and  154  is closer to the top surface of the semiconductor layer  108  than other portions of the doped well region  112 ′. Compared with another channel C 2  of an imaginary N-type MOS transistor comprising the gate structure  150  and the original doped well region  112  (illustrated with dotted line here, see  FIG. 2-7 ) which is not formed with the doped region  132 ′ and is not affected by diffusion of the doped region  132 ′, having the original cross-sectional profile, the asymmetric cross-sectional profile of the doped well region  112 ′ adjacent to the gate structure  150  caused due to formation and diffusion of the doped region  132 ′ may reduce the length of the channel C 1 , thereby improving driving currents of the N-type MOS transistor comprising the gate structure  150 . 
         [0038]    Moreover, during operation of the semiconductor device  100  comprising the IGBT shown in  FIG. 9 , a positive emitter voltage relative to the collector (i.e. the doped region  158 ) is applied to the doped region  152 , and a gate voltage greater than the threshold voltage of the N-type MOS transistor and the N-type HV MOS transistor of the semiconductor device  100  allows currents to pass through the N-type MOS transistor and the N-type HV MOS transistor, thereby modulating the base currents which are connected to the collector and firmed between the emitter and the collector. In addition, due to formation of the N-type MOS transistor and the N-type HV MOS transistor, more base currents can be provided to the PNP bipolar transistor. Moreover, due to fore ration of the n-type semiconductor layer  108 , voltage drop of the base currents in the base can be reduced. 
         [0039]    When compared with the semiconductor device  10  shown in  FIG. 1 , since an additional MOS device is provided in the semiconductor device  100  shown in  FIG. 9 , the semiconductor device  100  shown in  FIG. 9  may have improved electrical performance such as increased driving currents and on-state resistance than the semiconductor device  10  shown in  FIG. 1 . Therefore, the electrical performances such as driving current and on-state resistance of the elements in the semiconductor device  100  can he maintained or improved currently with the trend of size reduction of the semiconductor device  100  and the region of the IGBT in the semiconductor device  100 . Moreover, since the semiconductor device  100  shown in  FIG. 9  is formed over a SOI substrate and a deep trench isolation  118  is formed in a portion of the semiconductor layer  108  of the SOI substrate, noises affecting the semiconductor device  100  can be reduced and a latch-up effect in the semiconductor device  100  is thus prevented. 
         [0040]    The scope of the invention is not limited to the semiconductor device  100  shown in  FIG. 9 , and a plurality of IGBT can be provided and properly arranged in the semiconductor device. For the purpose of simplicity, fabrications and arrangements thereof are not described here. 
         [0041]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 7