Patent Abstract:
A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated circuit devices and, more specifically, to a flip-chip having an on-chip decoupling capacitor. 
     2. Description of Related Art 
     It is generally desirable to have a semiconductor package which is more efficient and has high decoupling capacitance/low inductance. It is known that the effective inductance can be lowered by connecting decoupling capacitors nearer to a circuit (i.e, the effective inductance is lower by reducing the lead length). Inductance is a function of path length, therefore the longer the current path, the higher the inductance. High inductance, which yields higher supply noise in semiconductor packages, reduces the performance of integrated circuits (ICs). Also, inductance between an IC and power supply can induce spurious voltage spikes in the power supply system, which can in turn cause timing problems in signal switching. 
     Decoupling capacitors are housed on semiconductor packages in order to lower the inductance through the package by reducing the lead length. Decoupling capacitors placed close to power consuming circuits are able to smooth out voltage variation with a stored charge on the decoupling capacitor. The stored charge either dissipates or is used as a local power supply to device inputs during signal switching stages, allowing the decoupling capacitor to negate the effects of voltage noise induced into the system by parasitic inductance. Off-chip decoupling capacitors, however, are not sufficient for very high speed microprocessor applications. Since the decoupling capacitors are located at a relatively long distance from the switching circuits, the time delay caused by the long inductance path makes the off-chip capacitors unusable with gigahertz switching circuits. 
     In order to sustain high frequency circuit operation, an ample amount of capacitive decoupling must be provided close to the switching circuits. Although it is possible to integrate chip capacitors within the chip&#39;s circuit elements, the capacitors compete for valuable die area that could be used for building additional circuits. Due to the limited area in which to build these capacitors, the overall capacitive decoupling that they provide is also limited. 
     SUMMARY OF THE INVENTION 
     A flip-chip package device having a decoupling capacitor electrically coupled to or through the backside of the chip is disclosed. The flip-chip package device includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and are connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to one or more of the plurality of electrical interconnects. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention is further described by way of example with reference to the accompanying drawings, wherein: 
     FIG. 1 is a sectioned side view of a flip-chip with a decoupling capacitor electrically coupled to the backside of the chip; and, 
     FIG. 2 is a sectioned side view of a flip-chip in another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A controlled collapse chip connection (C 4 ) packaged chip (or flip-chip) having a decoupling capacitor electrically coupled to or through the backside of the chip is described. In the following description, numerous specific details are set forth such as material types, processes, etc., in order to provide a thorough understanding of the present invention. However, it will be obvious to one of skill in the art that the invention may be practiced without these specific details. In other instances, well-known elements and processing techniques have not been shown in particular detail in order to avoid unnecessarily obscuring the present invention. 
     FIG. 1 illustrates a side view of a chip package  200  in one embodiment of the present invention. Package  200  includes a semiconductor chip  202  that is electrically coupled to a package substrate  250  via a plurality of raised bump/solder bump connections  220 . Chip  202  includes a semiconductor substrate  204  having a plurality of circuit elements  206  formed within the frontside surface  230  of the semiconductor substrate  204 . A routing (or conductive) region  210  is located above the frontside surface  230  of semiconductor substrate  204 . Routing region  210  generally includes multiple layers of conductive lines  212  and  214  that are electrically coupled to the circuit elements  206  by conductive vias  222 . 
     The conductive lines  212  and  214  of routing region  210  may be any one of or combination of several conductive materials such as cobalt, molybdenum, tungsten, titanium, aluminum, copper, doped silicon, doped polysilicon, or a metal silicide layer. Conductive lines  212  and  214  are typically deposited on and separated by dielectric layers. Although only two conductive layers are shown in FIG. 1, it is noted that conductive region  210  generally includes additional conductive layers. For the purpose of this discussion, conductive lines  212  typically comprise the metal one (M 1 ) layer of the chip and conductive lines  214  comprise the metal two (M 2 ) layer of the chip. Conductive layers such as M 1  and M 2  are often used to distribute, for example, power and ground to transistors. Note, however, that M 1  and M 2  are not of any specific order and may, respectively, be MX and MY, where MX represents a power grid structure and MY represents a ground plane or ground grid structure. Conductive region  210  also includes additional layers of signal lines, which are not shown in FIG.  1 . External power and ground connections to the chip  202  are made through a first set of electrical contact pads  251  located on the top-side surface  232  of conductive region  210 . Contact pads  251  are electrically coupled to conductive lines  212  and  214  by conductive vias  221 . 
     A decoupling capacitor  270  having electrodes  271   a  and  271   b  is embedded within the backside surface  205  of chip  202 . Preferably, the backside surface  272  of capacitor  270  is flush with the backside surface  205  of chip  202 . This configuration maximizes the surface area available for attaching a heatsink or other heat dissipating device to the backside of chip  202 . 
     The electrodes  271   a  and  271   b  of capacitor  270  are electrically coupled to conductive lines  212  and  214 , respectively. Electrically conductive vias  260  couple the capacitor electrodes  271   a  and  271   b  to conductive lines  212  and  214 . By electrically coupling the decoupling capacitor  270  to the power and ground planes through the backside of chip  202 , the inductance path length between the capacitor electrodes  271   a  and  271   b  and the switching circuit elements  206  is kept to a minimum. As a result, the inductance induced time delay is also kept to a minimum. In certain situations, the capacitor  270  may be electrically coupled directly to the circuit elements  206 . The direct connection allows the capacitor to supply the charge to critical circuit elements without the need to go through the power and ground grid, allowing the capacitor to function as a local reservoir and further reducing the inductive path and the inductance induced time delay. The short time delay associated with the backside decoupling capacitor  270  enhances the capacitor&#39;s ability to respond to voltage spikes. More particularly, the placement of capacitor  270  on or within the backside  205  of chip  202  enables the capacitor to respond to voltage spikes in very high speed switching circuits, such as gigahertz switching circuits. 
     With continuing reference to FIG. 1, semiconductor substrate  204  is typically made of silicon. Vias  260  are produced by etching or micromachining the backside  205  of substrate  204  and vapor depositing a conductive material within the via. The conductive material generally includes a conductive metal such as aluminum or copper. Other electrically conductive metals or materials may also be used. 
     In the embodiment of FIG. 1, capacitor  270  is located within a recess formed within the backside of chip substrate  204 . In an alternative embodiment, capacitor  270  is attached to the backside surface  205  of chip  202 . In such an embodiment, conductive vias  260  extend through the entire thickness of the substrate  204  to electrically couple electrodes  271   a  and  271   b  to power and ground planes  212  and  214 , respectively. 
     With reference to FIG. 2, a chip package  300  of another embodiment of the present invention is shown. Chip package  300  includes a flip-chip  202  having a decoupling capacitor  270  located within a recess in the backside  205  as shown in FIG.  1 . Chip package  300  includes an additional decoupling capacitor  280  which is located on the bottom surface  292  of the package substrate  250 . Lands  252  located on the top surface  290  of substrate  250  are electrically coupled to lands  282  located on the bottom surface  292  of substrate  250  by conductive vias  286 . The capacitor electrodes  281   a  and  281   b  are coupled to lands  282  by solder bump connections  284 . Other connecting structures, such as gold bump connections, may be used to couple the capacitor electrodes  281   a  and  281   b  to lands  282 . As shown in FIG. 2, electrodes  281   a  and  281   b  are electrically coupled to the ground plane  214  of chip  202 . Note that electrodes  281   a  and  281   b  may each be electrically coupled to the power plane  212  and/or the ground plane  214 . The placement of capacitor  280  on the bottom surface  292  of package substrate  250  greatly reduces the current path between the electrodes  281   a  and  281   b  and the power and ground planes of chip  202  as compared to conventional off-chip decoupling capacitors. 
     Vias  286  are produced by micromachining through holes in package substrate  250  and depositing a conductive material within the via. The conductive material generally includes copper. Other electrically conductive metals or materials may also be used. 
     In an alternative embodiment, the electrodes  281   a  and  281   b  of capacitor  280  are coupled to lands  252  located on the top surface  290  of package substrate  250  through a series of conductive layers and conductive vias located within the package substrate. 
     Whereas many alterations and modifications of the invention will no doubt be appreciated by one of ordinary skill in the art after having read the foregoing description, it is understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. Therefore, references to details of the individual embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as essential to the invention.

Technology Classification (CPC): 7