Patent Abstract:
Techniques are presented to reduce reversion leakage in charge pump circuits. The exemplary circuit is a charge pump of the voltage doubler type, where the output of each leg is supplied through a corresponding output transistor. An auxiliary charge pump is used to supply the gates of the output transistors in order to cancel the threshold voltage of these output transistors. To reduce reverse leakage back through the output transistors, in each leg of the charge pump a switch is connected between the gate of the output transistor and the output level of the leg so the these levels can be shorted when that particular is not supplying the pump&#39;s output.

Full Description:
FIELD OF THE INVENTION 
       [0001]    This invention pertains generally to the field of charge pumps and more particularly to improving their efficiency. 
       BACKGROUND 
       [0002]    Charge pumps use a switching process to provide a DC output voltage larger or lower than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock half cycle, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second clock cycle, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in  FIGS. 1   a  and  1   b . In  FIG. 1   a , the capacitor  5  is arranged in parallel with the input voltage V IN  to illustrate the charging half cycle. In  FIG. 1   b , the charged capacitor  5  is arranged in series with the input voltage to illustrate the transfer half cycle. As seen in  FIG. 1   b , the positive terminal of the charged capacitor  5  will thus be 2* V IN  with respect to ground. 
         [0003]    Charge pumps are used in many contexts. For example, they are used as peripheral circuits on flash and other non-volatile memories to generate many of the needed operating voltages, such as programming or erase voltages, from a lower power supply voltage. A number of charge pump designs, such as conventional Dickson-type pumps, are know in the art.  FIG. 2  shows a 2 stage, 2 branch version of a conventional Dickson type charge pump that receives Vcc as its input voltage on the left and generates from it an output voltage on the right. The top branch has a pair of capacitors  303  and  307  with top plates connected along the branch and bottom plates respectively connected to the non-overlapping clock signals CLK 1  and CLK 2 . The capacitors  303  and  307  are connected between the series of transistors  301 ,  305 , and  309 , which are all diode connected to keep the charge from flowing back to the left. The bottom branch is constructed of transistors  311 ,  315 , and  319  and capacitors  313  and  317  arranged in the same manner as the top branch, but with the clocks reversed so the two branches will alternately drive the output. 
         [0004]    V TH -cancellation pumps can be used to replace the traditional Dickson charge pumps with diode connected switches for better efficiency and strong IV characteristics, because the V TH -drop in each stage of a Dickson charge pump is offset by boosting the gate of the transfer switch to a higher voltage through an auxiliary pump. However this kind of architecture has an inherent reverse leakage issue when the pump is supposed to deliver very high currents, such as where a large capacitance is instantaneously connected to the output of the pump. The reverse leakage issue hampers pump recovery time and causes power loss. Consequently, such V TH -cancellation pumps could benefit from ways to reduce this revers leakage problem. 
       SUMMARY OF THE INVENTION 
       [0005]    According to a first set of aspects, a charge pump circuit generates an output voltage. The charge pump circuit includes an output generation section, an offset cancellation section, and first and second output transistors. The output generation section has a first leg receiving a first clock signal and providing a first output and has a second leg receiving a second clock signal and providing a second output, wherein the first and second clock signals are non-overlapping. The first and second outputs of the first and second output generation section&#39;s legs are respectively connected through the first and second output transistors to provide the output voltage. The offset cancellation section has a first leg providing a first offset cancellation output and has a second leg having a second offset cancellation output, where the first and second offset cancellation outputs of the output generation section are respectively connected to the control gate of the first and second output transistors. When the first and second offset cancellation outputs are high, the first and second outputs of the output generation section are respectively high; and when the first and second outputs of the output generation section are low, the first and second offset cancellation outputs are respectively low. The charge pump circuit also includes first and second shorting transistors. The first shorting transistor is connected between the first output of the output generation section and the control gate of the first output transistor and has a gate connected to the gate of the second output transistor. The second shorting transistor is connected between the second output of the output generation section and the control gate of the second output transistor and has a gate connected to the gate of the first output transistor. 
         [0006]    Another set of aspects concern a method of reducing leakage in a charge pump circuit. The method includes receiving an input voltage, receiving a first clock at a first branch of a first charge pump section and generating from it a first output from the input voltage, and receiving a second clock signal at a second branch of the first charge pump section and generating from it a second output from the input voltage. The first and second clock signals are non-overlapping. The method also includes receiving a third clock at a first branch of a second charge pump section and generating therefrom a third output from the input voltage and receiving a fourth clock signal at a second branch of the second charge pump section and generating therefrom a fourth output from the input voltage. The first and second charge pump sections have the same structure. The first clock signal is high when the third clock signal is high and the third clock signal is low when the first clock signal is low. The second clock signal is high when the fourth clock signal is high and the fourth clock signal is low when the second clock signal is low. The third and fourth outputs are applied to the control gates of first and second transistors, respectively, where the first and second transistors are respectively connected between the first and second outputs of the first charge pump section and the output of the charge pump circuit. The fourth and third outputs are applied to the control gates of third and fourth transistors, respectively, wherein the third transistor is connected between the first output and the third output and the fourth transistor is connected between the second output and the fourth output. 
         [0007]    Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The various aspects and features of the present invention may be better understood by examining the following figures, in which: 
           [0009]      FIG. 1   a  is a simplified circuit diagram of the charging half cycle in a generic charge pump. 
           [0010]      FIG. 1   b  is a simplified circuit diagram of the transfer half cycle in a generic charge pump. 
           [0011]      FIG. 2  shows a 2 stage, 2 branch version of a conventional Dickson type charge pump. 
           [0012]      FIG. 3A  is a schematic of a voltage double type of charge pump with V TH  cancellation. 
           [0013]      FIGS. 3B and 3C  illustrate a clock scheme and typical node voltages for the device of  FIG. 3A . 
           [0014]      FIG. 4  shows a recovery time profile, transient response and I-V curves 
           [0015]      FIGS. 5-7  show embodiments of V TH  cancellation charge pumps having reduced reverse leakage. 
           [0016]      FIGS. 8A and 8B  illustrate voltage and current levels for the circuits of  FIGS. 3A and 7 , respectively. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    A typical doubler-based charge pump stage is shown in  FIG. 3A , with a corresponding clock scheme shown in  FIG. 3B . Pump capacitors C 1    401  and C 2    403  get charged through switches M 3    405  and M 4    407 , respectively, to a voltage V IN  during phase Φ 2 /Φ 1  respectively. This voltage is then boosted by a voltage V DD  by using clocks, Φ 1 /Φ 2 , and passed on to V OUT  through switches M 1    409 / M 2    411  respectively. To minimize the drop across switches M 1    409  and M 2    411 , a higher voltage is used at nodes V G1 /V G2 , which are in turn obtained through a separate auxiliary pump using pump capacitors C B1    421 , C B2    422  and along with boosted clocks, Φ B1 /Φ B2  to boost V IN  by 2V DD . Typical node voltages are shown in  FIG. 3C . 
         [0018]    A common application of a charge pump is to supply a high-voltage bias to very large capacitive load, represented C L    433 . An example of this is when the charge pump is a peripheral element of a flash EEPROM memory circuit. This load is typically switched ON (here represented by closing a switch S 1   431 ) after the charge pump reaches steady state, causing a significant voltage drop on the output V OUT . The time taken for the charge pump to reach steady-state again is termed the recovery time. Voltage doubler-based architectures suffer from a slow recovery compared to the Dickson-type architectures due to a reverse-leakage phenomenon that is absent in Dickson-type architectures. 
         [0019]    To explain this phenomenon, consider a charge pump in steady-state. When switch M 1    409  is ON, consider a very large capacitor C L    433  connected suddenly to the node V OUT  using switch S 1    431 . The pump capacitor C 1    401  loses charge instantaneously to C L    433 , causing the voltage V OUT  to drop by some voltage, say V drop . This charge lost to the load should be replenished in the next phase from the supply V IN  through the switch M 3    405 , during which time the switch M 1    409  should be completely OFF. Since there is no discharge path for the auxiliary pump capacitor, C B1    421 , it loses no charge and V G1  still stays at V IN , whereas V 1  has dropped to V IN −V drop . For an appreciable drop, this switch, M 1    409 , starts conducting and enables an alternate current path from the output node back into the pump capacitor, C 1    401 . This slows down the voltage build-up on V OUT  as charge from C L    433  leaks back into the pump and the recovery time increases. Though the charge is not lost and goes back into the pump capacitor, switching losses in this reverse-leakage path attribute to increased power consumption during recovery. This is the reverse-leakage issue addressed in the following. A typical recovery profile for both types of charge pump is shown in  FIG. 4 . 
         [0020]    More information on prior art charge pumps, such as Dickson type pumps, and charge pumps generally, can be found, for example, in “Charge Pump Circuit Design” by Pan and Samaddar, McGraw-Hill, 2006, or “Charge Pumps: An Overview”, Pylarinos and Rogers, Department of Electrical and Computer Engineering University of Toronto, available on the webpage “www.eecg.toronto.edu/˜kphang/ece1371/chargepumps.pdf”. Further information on various other charge pump aspects and designs can be found in U.S. Pat. Nos. 5,436,587; 6,370,075; 6,556,465; 6,760,262; 6,922,096; 7,030,683; 7,554,311; 7,368,979; 7,795,952; 7,135,910; 7,973,592; and 7,969,235; US Patent Publication numbers 2009-0153230-A1; 2009-0153232-A1; 2009-0315616-A1; 2009-0322413-A1; 2009-0058506-Al; US- 2011 - 0148509 -A1; 2007-0126494-A1; 2007-0139099-A1; 2008-0307342 A1; and 2009-0058507 A1; and applications Ser. Nos. 12/973,641 and 12/973,493, both filed Dec. 20, 2010, and Ser. No. 13/228,605, filed Sep. 9, 2011. More detail on voltage cancellation pumps, including multi-stage arrangements, can be found in U.S. Pat. No. 7,969,235. 
         [0021]    The basic idea is to somehow short the nodes V 1  and V G1  when M 2    411  is ON, thereby guaranteeing that M 1    409  is turned OFF; but the circuit also needs to ensure that this new switch should be open when M 1    409  is intended to be ON, thereby preventing loss of charge from C B1    421  during intended operation. There are several embodiments described in the following to do this. 
         [0022]    A first embodiment uses the addition of weak diodes M 7    441 /M 8    443 between V G1 /V G2  and V 1 /V 2 , respectively, as shown in  FIG. 5 . Consider when the pump in steady-state and in the Φ 1  phase: When C L    433  is suddenly connected through the switch S 1    431 , V 1  drops suddenly but V G1  does not. When the pump shifts to phase Φ 2 , since the diode M 7    441  is forward-biased, V G1  and V 1  equalizes quickly until V 1 =V G1 −V TH  and hence M 1    409  is shut OFF thereby preventing reverse leakage. Since the diode is forward-biased during phase Φ 1  also, it has to be a weak diode. The drop in V G1  due to the forward-biased diode M 7    441  during phase Φ 1  is minute and even this small amount of charge lost by C B1    421  is gained back by C 1    401  and C L    433 . Hence, the drop in power efficiency is minimal. The recovery time now improves as the reverse-leakage path is cut off and there is more charge transferred from C 1    401  to C L    433 in each clock cycle. The power efficiency is also better as the dynamic losses due to the reverse-leakage path are absent. 
         [0023]    A second embodiment adds switches M′ 7    451 /M′ 8    453  between V G1 /V G2  and V 1 /V 2  respectively as shown in  FIG. 6 . fhe switches M′ 7    451 /M′ 8    453  are driven by the opposite phase clocks, V G2 /V G1  respectively. Consider the pump of  FIG. 6  in steady-state and in the Φ 1  phase: When C L    433  is suddenly connected through the switch S 1    431 , V 1  drops suddenly but V G1  does not. When the pump shifts to phase Φ 2 , the switch M′ 7    451  is turned ON strongly, as its gate-source voltage (V GS ) level is close to 2V DD , thereby shorting V 1  and V G1 . This causes the V GS  of M 1    409  to be ZERO and hence, the reverse leakage path is cut off Back in phase Φ 1 , V G2  drops by 2V DD  and the switch. M′ 7    451  is turned OFF completely, as long as the drop in voltage V 1  is not very drastic (&gt;V DD +V TH ). Hence, there is no drop in V G1  during phase Φ 1  and the driving capability of switch M 1    401  is unaltered. It is worth noting that there is no possibility for the switches M′ 7    451 /M′ 8    453  to turn ON accidentally as Φ B1 /Φ B2  are non-overlapping clocks by design. For designs working on the limit due to area constraints, a minute loss of driving capability in switches M 1    409 /M 2    411  cannot be tolerated and this new design will help in such cases. A disadvantage of this embodiment relative to that to be discussed next is that it takes some time to cut-off the reverse-leakage path due to the non-overlap time between the boosted clocks Φ B1 /Φ B2 . Hence, some degree of reverse leakage can occur. 
         [0024]    Another embodiment, shown in  FIG. 7 , uses depletion-type devices M″ 7    461 /M″ 8    463  instead of enhancement-type devices M′ 7    451 /M′ 8    453  of  FIG. 6  for the sorting switches. This causes these switches turn ON immediately after the removal of boosted clocks Φ B1 /Φ B2 , thereby cutting off the reverse-leakage path from the outset. M″ 7    461  is weakly ON when Φ B1  is removed and strongly ON when Φ B2  is applied. However, during phase Φ 1 , the switch M″ 7    461  starts conducting if the voltage drop exceeds a certain level (&gt;V DD −|V TH |). This can be preferable when the drop in voltage is not too much, i.e.; as long as C 1    401 /C 2    403  is comparable to C L    433 . 
         [0025]    A graphical depiction of the operation of the embodiment of  FIG. 7  is shown in  FIGS. 8A and 8B .  FIG. 8A  shows the voltage and current profiles for a typical doubler-type charge pump such as in  FIG. 3 , whereas  FIG. 8B  shows the voltage and current profiles for the modified charge pump of  FIG. 7 . The charge needed to be transferred to the output in both cases is ∫(I A1 +I A2 )*dt. As shown in  FIG. 8B , the negative components (reverse current) of I A1 /I A2  have been reduced greatly, thereby transferring more charge to the output every cycle and reducing the recovery-time. 
         [0026]    The embodiments described above address the reverse leakage issue in doubler-type charge pump architectures. Depending on the charge pump application and design constraints, the preferred embodiment can be chosen for the charge pump. Compared to previous charge pump circuits, the embodiments described here can provide a ramp-up time comparable to the Dickson-type charge pumps, similar I-V performance, and better power efficiency. Charge pump architectures are typically optimized keeping the steady-state performance in mind so as to reduce power consumption, area, or both. Doubler-type charge pump architectures with V TH -cancellation offer distinctly better performance than their Dickson-type architecture equivalents; but the dynamic performance of the pump (ramp-up, recovery-time) is adversely affected and can make it unsuitable for sensitive applications where the Dickson-type architecture may be chosen. The techniques presented here improve the dynamic performance of doubler-type charge pumps along with ensuring better power efficiency, making them comparable to the Dickson-type charge pumps and thereby providing high levels of both steady-state performance and dynamic performance in the same voltage doubler-type charge pump architecture. 
         [0027]    Although the invention has been described with reference to particular embodiments, the description is only an example of the invention&#39;s application and should not be taken as a limitation. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as encompassed by the following claims.

Technology Classification (CPC): 6