Patent Abstract:
Presented herein are system(s), method(s), and apparatus for displaying pictures on a display. In one embodiment, there is presented a method for outputting pictures. The method comprises receiving the plurality of fields for display in a particular order, where the plurality of fields are associated with the stream; detecting that a first field and a field adjacent to the first field have the same polarities; selecting between leading or lagging the fields after the first field; detecting that a second field and a field adjacent to the second field have the same polarities; selecting between leading and lagging the fields after the second field, based at least in part on the selection after the first field; detecting that a third field and a field adjacent to the third field have the same polarities; and selecting between leading and lagging the fields based at least in part on the selection after the second field.

Full Description:
RELATED APPLICATIONS 
     This application claim priority to “System, Method, and Apparatus for Displaying Pictures on an Interlaced Display”, Provisional Application for Patent, Application Ser. No. 60/727,983 filed Oct. 18, 2005 by MacInnis, which is incorporated herein by reference. 
    
    
     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     [Not Applicable] 
     MICROFICHE/COPYRIGHT REFERENCE 
     [Not Applicable] 
     BACKGROUND OF THE INVENTION 
     Video data can have a variety of formats. For example, motion pictures are typically filmed at 24 progressive frames per second. Other material can be filmed at 30 progressive frames per second, or 30 interlaced frames per second. 
     The display devices are also associated with a specific display rate and format. For example, display devices according to the National Television Standards Committee display 30 interlaced frames per second. 
     The source video content for display on a display device can include video that has a variety of different display rates. For example, the video can include a motion picture with commercials. 
     While the motion picture is filmed at 24 progressive frames per second, the display device displays 30 interlaced frames per second. Accordingly, the display device uses what is known as 3:2 pull down. In 3:2 pulldown, 24 progressive frames are separated into 48 fields. Since every four fields represent the display time of five fields, one of the four fields is repeated. For example, where the progressive frames include frames F 0 , F 1 , F 2 , F 3  . . . , the display order is T 0 , B 0 , T 1 , B 1 , T 1 , B 2 , T 2 , B 3 , T 3 , B 3 , . . . , where T# is the top field from frame F#, and B# is the bottom field from frame F#. 
     The motion picture can then be followed by a commercial that is filmed at 30 interlaced frames per second. The commercials are displayed without using 3:2 pull down. For interlaced frames, the top field and bottom field are captured at and represent different video times. Therefore, either top fields or bottom fields are to be displayed first. 
     When the last field for display from the motion picture movie has the same polarity as the first field from the commercial, the first field from the commercial is not aligned with the display device. 
     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings. 
     BRIEF SUMMARY OF THE INVENTION 
     Aspects of the present invention may be found in system(s), method(s), and apparatus for displaying pictures on an interlaced display, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
     These and other advantages and novel features of the present invention, as well as illustrated embodiments thereof will be more fully understood from the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is an illustration of a plurality of fields that can be displayed in accordance with an embodiment of the present invention; 
         FIG. 2  is a block diagram of an exemplary circuit in accordance with an embodiment of the present invention; 
         FIG. 3  is a flow chart for providing fields in accordance with an embodiment of the present invention; and 
         FIG. 4  is an illustration of a plurality of frames and fields that can displayed in accordance with an embodiment of the present invention; and 
         FIG. 5  is a block diagram of an exemplary circuit for displaying pictures in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to  FIG. 1 , there is illustrated a block diagram describing an exemplary video source in accordance with an embodiment of the present invention. The video source comprises a first plurality of fields  100   a ( 0  . . . m) for display, a second plurality of fields for display  100   b ( 0  . . . n), a third plurality of fields for display  100   c ( 0  . . . x), a fourth plurality of fields for display  100   d ( 0  . . . y), and a fifth plurality of fields  100   e ( 0  . . . z). 
     The plurality of fields for display  100   a ,  100   b ,  100   c ,  100   d , and  100   e  comprise top fields, e.g., fields  100   a ( 0 , 2 , 4 , . . . ),  100   b ( 0 , 2 , 4 , . . . ),  100   c ( 1 , 3 , 5  . . . ),  100   d ( 1 , 3 , 5  . . . )  100   e ( 0 , 2 , 4 , . . . ) and bottom fields, e.g., fields  100   a ( 1 , 3 , 5 , . . . ), fields  100   b ( 1 , 3 , 5 , . . . ), fields  100   c ( 0 , 2 , 4 , . . . ), fields  100   d ( 0 , 2 , 4 ), and fields  100   e ( 1 , 3 , 5 ). 
     Top fields  100   a ( 0 , 2 , 4 , . . . ) represent one set of alternating lines of pixels in a frame during a period of time 0−&gt;T a , 2T a −&gt;3T a , 4T a −&gt;5T a , . . . , while the bottom fields  100   a ( 1 , 3 , 5 , . . . ) represent the other set of alternating lines during alternating periods of time T a −&gt;2T a, 3T a −&gt;4T a , 5T a −&gt;6T a . . . . For example, a top field can include even numbered lines while a bottom field can include odd numbered lines. 
     An interlaced display displays interlaced video data by displaying one of the top or bottom fields followed by the other during alternating periods of time. The display simulates motion video when displaying the top fields  100   a ( 0 , 2 , 4 , . . . ) at times D−&gt;D+T a , D+2T a −&gt;D+3T a , D+4T a −&gt;D+5T a . . . , and the bottom fields  100   a ( 1 , 3 , 5 , . . . ) at times D+T a −&gt;D+2T a , D+3T a −&gt;D+4T a , D+5T a −&gt;D+6T a . . . . 
     After displaying field  100   a (m), display field  100   b ( 0 ) is the next field for display in the video source. However, if field  100   a (m) and field  100   b ( 0 ) are both top fields (this is known as having the same polarity), the field  100   b ( 0 ) will provide a top field at D+mT a  when a bottom field is expected. At time T m , the interlaced display may display the received top field as a bottom field and subsequent fields may also be displayed with inverted polarity. This tends to cause objectionable artifacts. 
     Similarly, if both field  100   b (n) and field  100   c ( 0 ) are bottom fields, or if both field  100   c (x) and field  100   d ( 0 ) are bottom fields, or if both  100   d (y) and  100   e ( 0 ) are top fields, fields  100   c ( 0 ),  100   d ( 0 ), or  100   e ( 0 ) will provide fields that are opposite in polarity to what is expected. 
     In the foregoing circumstance, interlaced display can lag or lead the fields  100 . Lagging the fields refers to delaying the display of fields  100   b  by at least one field period. The delay of the display of fields  100   b  is relative to an order of display that would occur, except for the opposing polarity of the field and the interlaced display. In cases, such as where 3:2 pulldown is used, the delay is relative to the 3:2 pulldown order. For example, the fields  100   b ( 0 , . . . n) can be displayed starting at D+(m+1)T a . If at time D+mT a , the interlaced display expects bottom fields, at time D+(m+1)T a , the interlaced display expects top fields. 
     During time D+mT a , the field  100   a (m) can be repeated with the opposite polarity. When a top field is displayed with opposite polarity, a vertical phase shift filter can be applied to the field to convert it from e.g. a top field to a bottom field, or vice versa. In another example, a field may be displayed as if it had the opposite polarity to its actual polarity, e.g. display a top field as a bottom field, or vice versa. Alternatively, the field  100   a (m−1) can be repeated. In another case, the field  100   b ( 0 ) can displayed with opposite polarity, as a bottom field, and repeated at D+(m+1)T a  as a top field. 
     Leading the fields refers to displaying at least one field from fields  100   b  ahead of time. The display of fields  100   b  ahead of time is relative to an order of display that would occur, except for the opposing polarity of the field and the interlaced display. The order of display that would occur, except for the opposing polarity of the field and the interlaced display is often explicitly indicated in a data structure that provides the fields  100  from the video source, or can be the order that the fields  100  are received. In cases, such as where 3:2 pulldown is used, the delay is relative to the 3:2 pulldown order. For example, field  100   b ( 0 ) can be skipped. Field  100   b ( 1 ), that is a bottom field, can be displayed starting at time D+(m+1)T a . Each of the remaining fields  100   b ( 2  . . . n) can then be displayed in order. 
     In the case of lagging the fields, the fields  100   b  can be shown one time period later, while in the case of leading the fields, the fields  100   b  can be shown one time period earlier. 
     If fields  100   b (n) and  100   c ( 0 ) are both bottom fields, when the interlaced display finishes displaying fields  100   b (n), the interlaced display is ready to display a top field. Similarly, if the fields  100   c (x) and  100   d ( 0 ) are both bottom fields, the display is ready to display a top field after field  100   c (x). If fields  100   d (y) and  100   e ( 0 ) are both top fields, the interlaced display is ready to display a bottom field after field  100   d (y). 
     If in every case, the decision is to lag the pictures, the lag will accumulate over time. Many decoding systems and display systems include a buffer for storing pictures before decoding or before display. If the lag accumulates beyond a certain threshold, the buffers may overflow. 
     Alternatively, if in every case, the decision is to lead the pictures, the lead will accumulate over time. If the lead accumulates over a certain threshold, fields may not be available for display. 
     According to certain aspects of the present invention, the decision to lag or lead, such as after displaying  100   d (y) can be based on at least one previous decision, the decisions made after displaying fields  100   a (m),  100   b (n), or  100   c (x). The decision to lag or lead, based on at least one previous decision, can be made in a manner to offset accumulated lags, with leads, and vice versa. In one embodiment, the decisions can alternate between leading and lagging. For example, where after displaying field  100   a (m), the decision is to lag, the decision after displaying field  100   b (n) can be to lead, after displaying fields  100   c (x), lag. 
     Referring now to  FIG. 2 , there is illustrated a block diagram of an exemplary circuit  200  for providing fields  100  for display on an interlaced display  220 . The circuit receives fields  100  from a video source and provides the fields  100  for display. The interlaced display  220  displays fields at time periods. The circuit  200  provides the fields  100  for display at approximately the time period that the interlaced display  220  displays the fields  100 . The circuit  200  may include a buffer  205  for buffering some of the fields  100 , a memory  210  for storing one or more indicators, and output port(s)  215  for providing fields to the interlaced display  220 , as will be set forth below. The circuit  200  can be hardwired, comprise logic or a state machine, or comprise a programmed processor. 
     The operation of the circuit  200  will now be described with reference to  FIG. 3 , which illustrates a flow diagram for displaying pictures in accordance with an embodiment of the present invention. At  305 , the circuit  200  makes a determination whether the next field for display in the buffer  205  has the same polarity as expected for the next output. If the polarity is the same as expected for the next output, the circuit  200  provides ( 310 ) the next picture to the display  220  via output port(s)  215 . 
     If at  305 , the polarity is different, the circuit  200  decides whether to lag or lead at  315 , based on previous decisions to lag or lead. In certain embodiments of the present invention, the decision to lead or lag at  315  can be set to be the opposite of the decision at the last iteration of  315 . The decision is then recorded at  320 , and carried out at  325 . 
     It is noted that the rate the fields  100  are captured can be different from the rate that the fields  100  are displayed. It is also noted that the video source can include progressive frames. For example, a motion picture that includes commercials often includes progressive frames that are captured at one rate, and fields that are captured at another rate. 
     Referring now to  FIG. 4 , there is illustrated a plurality of progressive frames  400   a  and interlaced frames  400   b  that are part of the transmission from a single stream. The progressive frames  400   a  can carry, for example, a motion picture, while the fields  400   b  can carry, for example commercials. The progressive frames  400   a  and fields  400   b  are commingled together. 
     The frames  400   a ( 0  . . . n), and  400   b ( 0  . . . x) correspond to time intervals 0−&gt;T a , T a −&gt;2T a , . . . , nT a −&gt;(n+1)T a  and 0−&gt;T b , T b −&gt;2T b , . . . , xT b −&gt;(x+1)T b . When displayed at corresponding times D+T a , . . . , D+nT a , D+nT a +T b , D+nT b +xT b , motion video is simulated. The amount of time that the first plurality of frames  400   a  and the second plurality  400   b  are displayed can be different. 
     The frames  400  can be displayed as interlaced video. When displayed as interlaced video, the display device displays top fields at particular time intervals, e.g., D−&gt;D+T c , D+2T c −&gt;D+3T c , . . . , while displaying bottom fields at particular time intervals, e.g., D+T c −&gt;D+2T c , D+3T c −&gt;D+4T c , . . . . 
     The format, and time periods T a , T b , and T c  can be different from each other, but are usually defined by standards. For example, for motion pictures, usually the frames are progressive at a rate of approximately 24 (23.976) per second. According to the National Television Standards Committee (NTSC) standard, the frames are interlaced having a rate of approximately 60 fields per second (59.94 fields/second), or 30 frames/second (29.97 frames/second). 
     It is common when a motion picture is broadcast with commercials, wherein-the motion picture frames  400  are captured at 24 frames per second while the commercials are captured at 60 fields per second. 
     In the case where 24 progressive frames/second are displayed on an interlaced display at 30 interlaced frames/sec., i.e. 60 fields/sec., a technique known as 3:2 pulldown is used. In 3:2 pulldown, the frames, e.g., top fields  400   a T( 0  . . . n) can be created from one set of alternating lines, while bottom fields  400   a B( 0  . . . n) can be created from the other. 
     The fields  400   a T and  400   a B are then displayed in the order,  400   a T( 0 ),  400   a B( 0 ),  400   a T( 1 ),  400   a B( 1 ),  400   a T( 1 ),  400   a B( 2 ),  400   a T( 2 ),  400   a B( 3 ),  400   a T( 3 ),  400   a B( 3 ), . . . , at each period T c . It is noted that one field from every second progressive frame is repeated. 
     The foregoing fields can then be renumbered  100 ( 0 ) . . .  100 ( 9 ). Due to the repetition of a field, the frames can either be displayed top field first or bottom field first. At the transition from displaying frames  400   a  to frames  400   b , the display may be ready to display a field with a different polarity than field  400   b ( 0 ). In the foregoing cases, a lag or a lead occurs. At the next transition, the opposite action is taken. 
     Referring now to  FIG. 5 , there is illustrated a block diagram of an exemplary circuit  500  in accordance with an embodiment of the present invention. Data is received and stored in a buffer  532 . The data can be received from either a communication channel or local memory, such as a hard disk or DVD. 
     The data output from the compressed data buffer  532  is then passed to a data transport processor  335 . The data transport processor  535  demultiplexes different data packets. At least some of the data packets carry compressed versions of the frames  400   a , and fields  400   b.    
     It is noted that in many implementations, the frames  400   a  and fields  400   b  may be compressed in accordance with a particular video compression standard, such as MPEG-2, or Advanced Video Coding (AVC, also known as H.264 or MPEG-4 Part 10). Additionally, it is noted that the foregoing video compression standards may reorder the fields/frames  400   a / 400   b  for encoding and decoding purposes. 
     A video decoder  545  receives and decompresses the compressed video data. While decompressing the video data, the decoded frames  400   a /fields  400   b  are stored in frame buffers  570  to await display by the display engine  550 . The display engine  550  scales the video, renders the graphics, and provides fields to the display device  580 . 
     Additionally, for motion picture progressive frames, frames  400   a , the decoder  545  effectuates 3:2 pulldown by indicating the fields  400   a T/ 400   a B that can be generated from the progressive frames  400   a . The foregoing results in a plurality of fields  100   a ( 0  . . . x). 
     After displaying field  100   a (x) , field  400   b ( 0 ) is displayed. After outputting a top field, the next field to output should be a bottom field. Where field  400   b ( 0 ) is a top field, a decision is made by the display manager  585  whether to lag or lead. 
     The display manager  585  also includes a control bit  592  that indicates the most recent decision to lead or lag at the previous transition point. The display manager  585  makes the opposite decision and toggles the control bit  592 . 
     The embodiments described herein may be implemented as a board level product, as a single chip, application specific integrated circuit (ASIC), or with varying levels of the system integrated with other portions of the system as separate components. Alternatively, if the processor is available as an ASIC core or logic block, then the commercially available processor can be implemented as part of an ASIC device wherein certain aspects of the present invention are implemented as firmware. 
     The degree of integration may primarily be determined by speed and cost considerations. Because of the sophisticated nature of modern processors, it is possible to utilize a commercially available processor, which may be implemented external to an ASIC implementation. 
     While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. 
     Additionally, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Technology Classification (CPC): 7