Patent Abstract:
A circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application Nos. 61/576,306, filed on Dec. 15, 2011 and 61/720,844, filed on Oct. 31, 2012. The entire disclosures of the applications referenced above are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The present disclosure relates to radio frequency (RF) transmitters, and more particularly to RF power detection circuit for RF transmitters. 
       BACKGROUND 
       [0003]    The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
         [0004]    Some radio frequency (RF) transmitters require accurate control of transmitted output power. For example, many RF transmitters need to comply with FCC regulations and wireless standards. Control of output power can be accomplished using an open loop or closed loop control system. In open loop control systems, the RF transmitter relies on accurate gain steps within the transmitter. In closed loop control systems, output power is measured and gain is adjusted accordingly. 
         [0005]    An RF power detection circuit is an integral part of any RF transmitter closed-loop power-control system. The RF power detection circuit measures absolute transmitted power. This measurement is preferably independent of variation in temperature, device characteristics due to process spread, and load/antenna impedance. 
         [0006]    Some RF power detection circuits assume a resistance value of an output load such as an antenna, measure output voltage and calculate output power based the output voltage squared divided by the resistance value. However, the resistance value of the load such as the antenna may vary during operation. For example, the resistance value of the antenna may be affected when the antenna is near or comes in contact with other objects. As can be appreciated, the RF power calculation will be adversely affected due to the difference between the actual resistance value of the antenna and the assumed resistance value. 
       SUMMARY 
       [0007]    A circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance. 
         [0008]    In other features, the mixer includes a Gilbert cell mixer. The bias circuit is configured to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature. The bias circuit includes a current source configured to generate the constant reference current, a bias resistance having the bias resistance and including one end in communication with the first current source, and a first transistor including a first terminal and a control terminal in communication with one end of the bias resistance. The bias signal is generated at a node between the bias resistance and the current source. 
         [0009]    A method of operating a circuit includes, using a mixer, multiplying a first differential input signal and a second differential input signal, wherein the mixer comprises a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. The method further includes generating the bias signal based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance. 
         [0010]    In other features, the mixer includes a Gilbert cell mixer. Generating the bias signal includes generating the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature. The bias signal is generated at a node between a bias resistance and a current source. 
         [0011]    Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]      FIG. 1  is a functional block diagram and electrical schematic of an example of an RF power detection circuit according to the prior art; 
           [0013]      FIG. 2  is a functional block diagram and electrical schematic of an example of a multiplier circuit; 
           [0014]      FIG. 3  is a functional block diagram and electrical schematic of an example of a bias circuit according to the present disclosure; 
           [0015]      FIG. 4  is a functional block diagram and electrical schematic of an example of a multiplier circuit including a bias circuit according to the present disclosure; 
           [0016]      FIG. 5  is a functional block diagram and electrical schematic of another example of a multiplier circuit including a bias circuit according to the present disclosure; and 
           [0017]      FIG. 6  is a functional block diagram and electrical schematic of another example of a multiplier circuit including a bias circuit according to the present disclosure. 
       
    
    
     DESCRIPTION 
       [0018]    Referring now to  FIG. 1 , part of an output circuit  10  of a prior art transmitter is shown. The output circuit  10  includes a power amplifier (PA)  20  that receives a radio frequency (RF) signal to be amplified and transmitted. The PA  20  outputs an amplified RF signal to a primary side of a transformer  24 . One end of a secondary side of the transformer  24  is connected to an antenna  26 , which may be arranged on a printed circuit board (PCB). Another end of the secondary side of the transformer  24  is connected to a reference potential such as ground. In this example, the antenna is the load, which has a load impedance. 
         [0019]    The output circuit  10  also includes an RF detection circuit  32  that detects an output power level of the PA  20 . The RF detection circuit  32  includes an amplifier  40  that receives and amplifies inputs to the PA  20  and outputs an amplified signal to first inputs of a multiplier circuit  42 . A voltage divider  44  is connected to outputs of the PA  20  (or to nodes  45 A and  45 B on the secondary side of the transformer  24 ) and outputs signals to second inputs of the multiplier circuit  42 . Outputs of the multiplier circuit  42  are connected to inputs of an amplifier  46 , which has first and second feedback resistances R FB  connected to respective inputs and outputs of the amplifier  46 . The amplifier  46  outputs a power detect voltage signal V PD , which is based on detected output power. 
         [0020]    The transmitted RF power is measured by multiplying the output voltage and current of the PA  20 . The result is independent of load/antenna impedance (R) or voltage standing wave ratio (VSWR). The output voltage of the PA  20  is sensed through the voltage divider  44  (k v *VPA). The output current of the PA  20  is replicated by using a scaled down replica PA (k I *I PA ). 
         [0021]    In  FIG. 2 , an example of the prior art multiplier circuit  42  is shown. The multiplier circuit  42  includes a mixer  50 , such as a Gilbert cell mixer, including transistors M 1 , M 2 , M 3 , and M 4 . First terminals of transistors M 1  and M 2  receive current I p . First terminals of transistors M 3  and M 4  receive current I n . Control terminals of transistors M 2  and M 3  receive a first bias signal V B  and the sensed output voltage V PA  (or V B −½V PA ). Control terminals of transistors M 1  and M 4  receive the bias signal V B  and the sensed output voltage V PA  (or V B +½ V PA ). A second terminal of transistor M 3  is connected to a second terminal of transistor M 1 . A second terminal of transistor M 2  is connected to a second terminal of transistor M 4 . 
         [0022]    The multiplier circuit  42  has a conversion gain G c . The mixer  50  performs V*I multiplication. Transistors M 1  thru M 4  are biased in the linear region. Current I p  divides into two parts, I p1  and I p2 . The ratio depends on the admittances of transistors M 1  and M 2  (gds 1  and gds 2 ). Similarly, current I n  is also divided into two parts, I n1  and I n2 , depending on gds 3  and gds 4 . While a virtual GND termination is assumed for ease of derivation, it is not necessary. 
         [0000]    
       
         
           
             
               I 
               
                 p 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   
                     g 
                     
                       ds 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   
                     
                       g 
                       
                         ds 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     + 
                     
                       g 
                       
                         ds 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                 
                 · 
                 
                   I 
                   p 
                 
               
               = 
               
                 
                   
                     ( 
                     
                       
                         V 
                         B 
                       
                       + 
                       
                         
                           1 
                           2 
                         
                          
                         
                           V 
                           PA 
                         
                       
                       - 
                       
                         V 
                         T 
                       
                     
                     ) 
                   
                   
                     2 
                      
                     
                       ( 
                       
                         
                           V 
                           B 
                         
                         - 
                         
                           V 
                           T 
                         
                       
                       ) 
                     
                   
                 
                 · 
                 
                   I 
                   p 
                 
               
             
           
         
       
       
         
           
             
               I 
               out 
             
             = 
             
               
                 
                   I 
                   op 
                 
                 - 
                 
                   I 
                   on 
                 
               
               = 
               
                 
                   
                     V 
                     PA 
                   
                   · 
                   
                     ( 
                     
                       
                         I 
                         p 
                       
                       - 
                       
                         I 
                         n 
                       
                     
                     ) 
                   
                 
                 
                   2 
                   · 
                   
                     ( 
                     
                       
                         V 
                         B 
                       
                       - 
                       
                         V 
                         T 
                       
                     
                     ) 
                   
                 
               
             
           
         
       
     
         [0023]    From  FIG. 1 , the output (voltage) of the power detection circuit is equal to: 
         [0000]        V   PD   =k   V   ·k   I   ·G   c ·( V   PA   ·I   PA )· R   FB  
 
         [0000]    From  FIG. 2 , the multiplier conversion gain G c  is: 
         [0000]    
       
         
           
             
               G 
               c 
             
             = 
             
               1 
               
                 2 
                  
                 
                   ( 
                   
                     
                       V 
                       B 
                     
                     - 
                     
                       V 
                       T 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    Therefore the output of the power detection circuit is equal to: 
         [0000]    
       
         
           
             
               V 
               PD 
             
             = 
             
               
                 
                   k 
                   V 
                 
                 · 
                 
                   k 
                   I 
                 
                 · 
                 
                   ( 
                   
                     
                       V 
                       PA 
                     
                     · 
                     
                       I 
                       PA 
                     
                   
                   ) 
                 
                 · 
                 
                   R 
                   FB 
                 
               
               
                 2 
                 · 
                 
                   ( 
                   
                     
                       V 
                       B 
                     
                     - 
                     
                       V 
                       T 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0024]    The value of the on-chip resistance R FB  depends on temperature and process variation (manufacturing). MOS threshold voltage V T  also depends on temperature and process variation (manufacturing). k v  and k I  (PA voltage and current division ratio) can be accomplished using a ratioed Gilbert cell, which is independent of temperature, process and load impedance. 
         [0025]    According to the present disclosure, (V B −V T ) is set equal to I ref *R bias . Resistors R FB  and R bias  can be implemented as scaled versions of each other, e.g. R FB =A*R bias . The ratio of resistances A remains constant and independent of process and temperature variation, therefore the output of the power detector is: 
         [0000]    
       
         
           
             
               V 
               PD 
             
             = 
             
               
                 
                   
                     k 
                     V 
                   
                   · 
                   
                     k 
                     I 
                   
                   · 
                   
                     ( 
                     
                       
                         V 
                         PA 
                       
                       · 
                       
                         I 
                         PA 
                       
                     
                     ) 
                   
                   · 
                   
                     R 
                     FB 
                   
                 
                 
                   2 
                   · 
                   
                     I 
                     ref 
                   
                   · 
                   
                     R 
                     bias 
                   
                 
               
               = 
               
                 
                   1 
                   
                     I 
                     ref 
                   
                 
                 · 
                 
                   
                     R 
                     FB 
                   
                   
                     R 
                     bias 
                   
                 
                 · 
                 
                   
                     
                       k 
                       V 
                     
                     · 
                     
                       k 
                       I 
                     
                   
                   2 
                 
                 · 
                 
                   ( 
                   
                     
                       V 
                       PA 
                     
                     · 
                     
                       I 
                       PA 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0026]    The constant reference current I ref  does not depend on process or temperature. The constant reference current I ref  is usually already available on-chip. The constant reference current I ref  can be generated by using a combination of a bandgap voltage and an external high-precision resistance. 
         [0027]    Referring now to  FIG. 3 , a bias circuit  100  for generating a bias voltage V B =V T +I ref *R bias  is shown. The bias circuit  100  includes a current source I ref  that is connected to one end of a bias resistance R bias . Another end of the resistance R bias  is connected to a first terminal and a control terminal of a transistor M 5 . A second terminal of the transistor M 5  is connected to a reference potential such as ground. Assuming: 
         [0000]        V   gs5   =V   T   +V   I ; 
         [0000]      If  V   dsat5   &lt;&lt;V   T ; 
         [0000]      Then  V   gs5   ≈V   T    
         [0028]    This can be done by biasing the transistor M 5  with a very low current density. The transistor M 5  is preferably a scaled version of transistors M 1 -M 4  for best matching. 
         [0029]    Referring now to  FIGS. 4 and 5 , an example of the multiplier circuit  200  according to the present disclosure is shown. In  FIG. 4 , the multiplier circuit  200  includes a mixer  206 , such as a Gilbert cell, with transistors M 1 , M 2 , M 3 , and M 4 . The sampled voltage V PA  is connected to first terminals of capacitances C 1  and C 2 . Second terminals of the capacitances C 1  and C 2  are connected to control terminals of transistors M 1 , M 2 , M 3 , and M 4  and to first terminals of resistances R 1  and R 2 . Second terminals of the resistances R 1  and R 2  provide a bias voltage V B  to the bias circuit  100 . First terminals of first and second transistors M 1  and M 2  and third and fourth transistors M 3  and M 4  are connected to I PA . A second terminal of transistor M 3  is connected to a second terminal of transistor M 1 . A second terminal of transistor M 2  is connected to a second terminal of transistor M 4 . 
         [0030]    An amplifier  220  has a non-inverting input connected to the second terminals of the transistors M 1  and M 3  and to one end of a first feedback resistance R FB . The amplifier  220  has an inverting input connected to the second terminals of the transistors M 2  and M 4  and to one end of a second feedback resistance R FB . An inverting output of the amplifier  220  is connected to another end of the first feedback resistance R FB  and to a first inverting input of an amplifier  230 . A non-inverting output of the amplifier  220  is connected to another end of the second feedback resistance R FB  and to a second inverting input of the amplifier  230 . In  FIG. 5 , a common mode input of the amplifier  230  is connected to a second terminal of the transistor M 5  and one end of a common mode feedback resistance R CMFB . 
         [0031]    Transistors M 1 -M 4  are biased with a constant voltage (V gs −V T ). The circuit accommodates a non-zero common-mode input voltage level. I ref *R CMFB  sets the common-mode voltage reference. A common-mode feedback amplifier sets V + =V − =V CMREF . Therefore, transistors M 1 -M 4  are still biased with (V gs −V T )=I ref *R bias . 
         [0032]    While the preceding discussion involved a power detector using a passive mixer, the present disclosure can also use an active mixer as well. The active mixer transistors may be biased with a constant overdrive voltage=I ref *R. As can be appreciated, while the foregoing description relates to RF detection circuits, the multiplier circuit can be used in other systems. Additionally, the input does not have to correspond to voltage and current delivered to a load. 
         [0033]    PA load impedance is unknown and can vary with the environment Z L =|Z|·e −jφ ). Knowing the value of load impedance is useful because PA output matching can be optimized to allow the PA to operate most efficiently. PA load impedance can be measured if we have the following two measurements: 
         [0000]    
       
      
       P 
       o 
       =V 
       PA 
       *I 
       PA  
      
     
         [0000]    
       
      
       V 
       sq 
       =V 
       PA 
       *V 
       PA 
       =V 
       PA 
       *I 
       PA 
       *|Z|*e 
       −jφ 
      
     
         [0034]    |Z| and φ can be solved using these two measurements. The voltage V sq  can be generated in multiple ways, one of which is shown in  FIG. 6 . 
         [0035]    Referring now to  FIG. 6 , the voltage V PA  is input to a transconductance amplifier  260 , which receives V PA . The transconductance amplifier  260  transforms a voltage input to a current output. The transconductance amplifier  260  generates an output current G m V PA , which is input to the first terminals of the transistors M 1  and M 2  and transistors M 3  and M 4  instead of I PA  as in  FIGS. 4 and 5 . 
         [0036]    The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure.

Technology Classification (CPC): 6