Patent Abstract:
Titanium nitride layers a less than 30 nm thickness are formed by physical vapor deposition and used as barrier layers for tungsten deposition. The titanium nitride layers are annealed in the presence of nitrogen or a nitrogen compound.

Full Description:
BACKGROUND  
         [0001]    The present invention relates to physical vapor deposition of titanium nitride.  
           [0002]    Titanium nitride has been used as a barrier and adhesion layer in fabrication of tungsten plugs in semiconductor integrated circuits. Tungsten plugs interconnect different conductive layers separated by a dielectric. Frequently used dielectrics are silicon dioxide and silicon nitride. Tungsten does not adhere well to silicon dioxide and silicon nitride, so titanium nitride has been used to promote adhesion. In addition, titanium nitride serves as a barrier layer preventing a chemical reaction between WF 6  (a compound from which the tungsten is deposited in a chemical vapor deposition process) and other materials present during tungsten deposition. See “Handbook of Semiconductor Manufacturing Technology” (2000), edited by Y. Nichi et al., pages 344-345.  
           [0003]    [0003]FIGS. 1, 2 illustrate a typical fabrication process. A dielectric layer  110  is deposited over a layer  120  which can be a metal or silicon layer. A via  130  is etched in the dielectric. A thin titanium layer  140  is deposited over dielectric  110  and into the via  130  to improve contact resistance (the titanium dissolves the native oxide on layer  120 ). Then titanium nitride layer  150  is deposited. Then tungsten  160  is deposited by chemical vapor deposition (CVD) from tungsten hexafluoride (WF 6 ). Tungsten  160  fills the via. Layers  160 ,  150 ,  140  are removed from the top surface of dielectric  110  (by chemical mechanical polishing or some other process). See FIG. 2. The via remains filled, so the top surface of the structure is planar. Then a metal layer  210  is deposited. The layers  160 ,  150 ,  140  in via  130  provide an electrical contact between the layers  210  and  120 .  
           [0004]    Titanium nitride  150  can be deposited by a number of techniques, including sputtering and chemical vapor deposition (CVD). Sputtering is less complex and costly (see “Handbook of Semiconductor Manufacturing Technology”, cited above, page 411), but the titanium nitride layers deposited by sputtering have a more pronounced columnar grain structure. FIG. 3 illustrates columnar monocrystalline grains 150 G in titanium nitride layer  150 . During deposition of tungsten  160 , the WF 6  molecules can diffuse between the TiN grains and react with titanium  140 . This reaction produces titanium fluoride TiF 3 . TiF 3  expands and causes failure of the TiN layer. The cracked TiN leads to a higher exposure of TiF 3  to WF 6 , which in turn leads to the formation of volatile TiF 4 . TiF 4  causes voids in the W film which are known as “volcanoes”. To avoid the volcanoes, the sputtered titanium nitride layers have been made as thick as 40 nm, and at any rate no thinner than 30 nm. In addition, the sputtered titanium nitride layers have been annealed in nitrogen atmosphere to increase the size of the TiN grains.  
         SUMMARY  
         [0005]    The inventor has discovered that under some conditions thinner annealed layers of sputtered titanium nitride unexpectedly provide better protection against the volcanoes than thicker layers. In some embodiments, fewer volcanoes have been observed with a TiN layer thickness of 20 nm than with 30 nm. In fact, no volcanoes have been observed in some structures formed with the 20 nm TiN layers. Why the thinner TiN layers provide better protection is not clear. Without limiting the invention to any particular theory, it is suggested that perhaps one reason is a lower stress in the thinner annealed layers and a higher density of the TiN grains.  
           [0006]    The invention is applicable to physical vapor deposition techniques other than sputtering. Additional features and embodiments of the invention are described below. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    FIGS.  1 - 3  are cross sectional views of prior art semiconductor structures in the process of fabrication.  
         [0008]    FIGS.  4 - 6  are cross sectional and perspective views of semiconductor structures in the process of fabrication according to one embodiment of the present invention. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0009]    [0009]FIG. 4 is a cross sectional and perspective view of a dual damascene semiconductor structure in the process of fabrication according to one embodiment of the present invention. Layer  120  is polysilicon formed by chemical vapor deposition (CVD) over a monocrystalline silicon wafer  410 . Before fabrication of layer  120 , the wafer  410  may have been processed to form devices such as MOS transistor  420 . The transistor&#39;s source/drain regions  430  were formed in substrate  410 , gate insulation  440  was formed over the substrate, and gate  450  was formed over the gate insulation. Other devices, including non-MOS devices, could be formed using known techniques. Layer  120  can also be part of substrate  410  (this embodiment is not shown in FIG. 4).  
         [0010]    In the embodiment of FIG. 4, dielectric  460  was deposited over the wafer. Then layer  120  was formed as described above, and was patterned by a plasma etch. An exemplary thickness of layer  120  is 150 nm.  
         [0011]    Dielectric layer  110  was deposited over the layer  120 . In some embodiments, dielectric  110  was a combination of two silicon dioxide layers. The first layer was PSG (phosphosilicate glass) deposited by chemical vapor deposition (CVD). The second layer was silicon dioxide deposited by CVD from TEOS. The combined thickness of the two layers was approximately 900 nm.  
         [0012]    Then a photoresist layer (not shown) was deposited and patterned photolithographically to define a via  464 . In some embodiments, the mask opening defining the via was round in top view, with a diameter of 0.18 μm. The via was formed in layer  110  with a plasma etch.  
         [0013]    The photoresist was removed, and another layer of photoresist (not shown) was deposited and patterned photolithographically to define a trench  470  in dielectric  110  for a tungsten interconnect. In some embodiments, the trench length was approximately 1 mm. The trench width was 0.22 μm. The trench was etched with a timed etch to a depth of approximately 250 nm. Via  464  was fully exposed at the bottom of the trench.  
         [0014]    Then the top surface of the structure was exposed to RF plasma in argon atmosphere for 10 seconds. The argon flow was 5 sccm (standard cubic centimeters per minute). The RF power was 315 W. This operation removed native oxide from layer  120 . Also, this operation smoothened (rounded) top edges  480  of trench  470  and via  464 . The rounded edges are desirable to reduce stress in titanium nitride  150  (FIG. 5) at these edges so as to reduce the risk of volcano formation. The RF plasma operation was performed in a system of type ENDURA available from Applied Materials of Santa Clara, Calif.  
         [0015]    Then titanium layer  140  (FIG. 5) was sputter deposited from a titanium target. The sputtering was performed at a temperature of 200° C. in argon atmosphere. The base pressure (the pressure before the argon flow was turned on) was 5×10 −7  torr. The DC power was 4000 W, the RF power was 2500 W. The wafer AC bias was 150 W. The titanium deposition was performed in a system of type ENDURA, in an ionized metal plasma (IMP) chamber of type Vectra, available from Applied Materials.  
         [0016]    The thickness of Ti layer  140  was varied. In one embodiment, the thickness was 10 nm. In another embodiment, the thickness was 36 nm.  
         [0017]    Then titanium nitride  150  was deposited by reactive sputtering from a titanium target in a nitrogen atmosphere. The base pressure (the pressure before the nitrogen flow was turned on) was 5×10 −7  torr. The nitrogen flow was 28 sccm (standard cubic centimeters per minute), the DC power was 4000 W, the RF power was 2500 W, the wafer bias was 150 W. The deposition temperature was 200° C. The deposition was performed in a system of type ENDURA, in an IMP chamber of type Vectra, available from Applied Materials.  
         [0018]    The thickness of the TiN layer  150  was 20 nm in one embodiment, 30 nm in another embodiment.  
         [0019]    Then the structure was heated to a temperature between 600° C. and 700° C. for 20 to 30 seconds in a nitrogen atmosphere. (This operation is referred to herein as Rapid Thermal Anneal, or RTA.) The base pressure was 100-120 torr, the nitrogen flow was 8 slm (standard liters per minute). The temperature was 620° C. in one embodiment, 670° C. in another embodiment. The anneal was performed in a system of type HEATPULSE 8800 available from AG Associates, Inc., of San Jose, Calif. The anneal is believed to have increased the lateral size of TiN grains 150 G (FIG. 3).  
         [0020]    Then tungsten layer  160  was deposited by CVD in two stages. At the first stage, the chemical reaction was:  
         2WF 6 +3SiH 4 →2W+3SiF 4 +6H 2    
         [0021]    This stage lasted 10 seconds. Then the silane (SiH 4 ) flow was turned off, and the hydrogen flow was turned on for the second stage. The chemical reaction was:  
         WF 6 (vapor)+3H 2  (vapor)→W(solid)+6HF(vapor).  
         [0022]    See S. Wolf, “Silicon Processing for the VLSI Era”, vol. 2 (1990), page 246, incorporated herein by reference. Both stages were performed in a system of type CONCEPT 1 available from Novellus Systems of San Jose, Calif. The silane flow was 20 sccm. The hydrogen flow was 12-15 slm (standard liters per minute). The WF 6  flow was 350 sccm. The pressure was 40 torr. The temperature was 400° C.  
         [0023]    Then the layers  160 ,  150 ,  140  were polished off the top of dielectric  110 . 2  by CMP. The resulting structure is shown in FIG. 6. Prior to CMP, the structure was examined for volcanoes using an optical microscope and SEM and STEM microscopes. The results are given in Table 1 below. The second column of Table 1 indicates the temperature of the Rapid Thermal Anneal, described above, performed after the deposition of TiN  150  before the deposition of tungsten  160 . In Embodiment No. 1, the anneal was omitted.  
                           TABLE 1                               Ti/TiN thickness:   Ti/TiN thickness:       Embodiment   RTA   10 nm/20 nm   36 nm/30 nm       No.   of TiN   Volcanoes observed?   Volcanoes observed?                   1.   None   Yes   Yes       2.   620° C.   No   Yes, but fewer than in                   Embodiment No. 1       3.   670° C.   No   No                  
 
         [0024]    These results show, unexpectedly, that the use of thinner Ti and TiN layers in combination with the RTA can provide a better protection against the volcanoes than thicker layers without the RTA. The thinner layers can eliminate the volcanoes at the lower RTA temperature of 620° C. Lower RTA temperatures are desirable to reduce impurity diffusion during the RTA, to prevent melting or softening of materials having low melting temperatures (e.g. aluminum), and reduce wafer warping.  
         [0025]    The invention is not limited to the particular materials, dimensions, structures, or fabrication processes described above. The invention is not limited to a thickness or composition of any particular layer, or the number, shape and size of vias  464  or trenches  470 . The trench length, for example, is 2 μm in some embodiments, and other lengths are possible. The invention is not limited to the particular gas flow rates, temperatures, or any other fabrication parameters or equipment. Some embodiments use nitrogen sources other than pure nitrogen for the RTA or titanium nitride deposition. For example, ammonia (NH 3 ) or H 2 /N 2  can be used. The invention is not limited to the Rapid Thermal Anneal or to any particular anneal temperature. Non-rapid anneals can be used. The anneal can be performed with plasma or with other heating techniques, known or to be invented. The invention is applicable to TiN sputtered from a TiN target. The invention is applicable to single damascene, dual damascene, and other structures, for example, to tungsten plugs formed in contact vias in non-damascene structures, and to tungsten features other than plugs. Titanium  140  is omitted in some embodiments. The invention is applicable to different tungsten CVD techniques, including tungsten deposition from WCl 6  rather than WF 6 . The invention is not limited by particular materials chosen for the layers  120 ,  110 ,  460 . Some embodiments involve non-silicon semiconductor materials. The invention is not limited to any particular sputtering process, and further is applicable to TiN deposited by physical vapor deposition techniques other than sputtering. For example, pulsed laser deposition and other evaporation techniques can be used. See “Handbook of Semiconductor Manufacturing Technology” (2000), cited above, pages 395-413, incorporated herein by reference. Layer  120  (FIG. 4) can be a metal layer, and can be part of the second, third, or higher metallization layers. The term “layer”, as used herein, may refer to a combination of two or more other layers. The invention is defined by the appended claims.

Technology Classification (CPC): 7