Patent Abstract:
A low voltage bandgap reference circuit based on a current summation technique where reference voltages with positive and negative temperature coefficients are generated by a first circuit. These reference voltages are coupled to amplifying circuits which generate reference voltages with equal and opposite temperature coefficients based on the ratio of resistors in these amplifying circuits, thereby producing a temperature independent reference voltage. The current from each of these amplifying circuits is then summed in a summing resistor, where the size of the resistor determines the magnitude of the temperature independent reference voltage.

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to temperature-stabilized reference voltage circuits, and more particularly to a sub-1-V bandgap reference circuit using a low supply voltage.  
         [0003]     2. Description of the Related Art  
         [0004]     Reference circuits are necessary in many applications ranging from memory, analog, mixed-mode to digital circuits. The demand for a low voltage reference is especially apparent in mobile battery-operated products. Low voltage operation is also a trend of process technology advancement. It is difficult to approach a stable operation in conventional bandgap reference (BGR) circuits when the supply voltage is under 1.5 V. As a result, the demand for a new bandgap reference circuit technique which is stable and operated at low supply voltages is inevitable.  
         [0000]     For a discussion of bandgap reference circuits with below 1.5 V power supply voltages refer to:  
         [0000]    
       
         
           
              H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,” in IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 670-673, May 1999, which describes a BGR circuit where V ref  has been converted from the sum of two currents; one is proportional to V f  and the other is proportional to V T , and  
              J. Doyle, Y. J. Lee, Y.-B. Kim, H. Wilsch, and F. Lombardi, “A CMOS Subbandgap Reference Circuit With 1-V Power Supply Voltage,” in IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, pp. 252-255, January 2004, where threshold voltage reduction and subthreshold operation techniques are used. Large ΔV BE  (100 mV) as well as a 90-dB operational amplifier are used to circumvent the amplifier offset.  
           
         
       
     
         [0007]     Shown in  FIG. 1   a  is one example of a conventional CMOS BGR circuit which is composed of a CMOS op-amp OA 1 , a current mirror comprising MP 1 , MP 2 , MP 3 , diode-wired transistors Q 1 , Q 2 , Q 3 , and resistors R 1 , R 2 , all implemented in the standard CMOS process. VDD and VSS are the power supply rails. The area ratio of Q 1 , Q 2 , Q 3  is Q 1 :Q 2 :Q 3 =1:M:1. Transistors MP 1 , MP 2 , MP 3  supply currents I 1 , I 2 , I 3 , respectively. The voltage V BE1  is seen at node BE 1 , voltage V N1  is seen at node N 1 , voltage V BE2  is seen at node VBE 2 , and voltage V BGR  is seen at output node BGR. 
 
 The current versus voltage relation of a general diode is expressed as:  
               I   D     =       I   S     ·     (       ⅇ       q   ·     V   D         k   ·   T         -   1     )               (   1   )             
 
 If  
           V   D     ⪢     kT   q       ,       
 
 then eq. (1) can be approximated as  
               I   D     ≅       I   S     ·     ⅇ       q   ·     V   D         k   ·   T                   (   2   )             
 
 solving for V D :  
               V   D     =             k   ·   T     q     ·   ln     ⁢           ⁢       I   D       I   S         =         V   T     ·   ln     ⁢           ⁢       I   D       I   S                   (   3   )             
 
 where 
 
 k is Boltzmann&#39;s constant (1.38×10 −23  J/K), 
 
 q is the electron charge (1.6×10 −19  C), 
 
 T is the absolute temperature (K), 
 
 V D  is the voltage across the diode, 
 
 I D  is the diode current, 
 
 I S  is the saturation current, and 
 
 V T  is the thermal voltage=(k·T)/q. 
 
 The PMOS transistor dimensions of MP 1 , MP 2 , and MP 3  are the same. Therefore the currents I 1 , I 2 , and I 3  have the same value because their gates are connected to a common node.  
                 (     W   L     )     MP1     =         (     W   L     )     MP2     =       (     W   L     )     MP3               (   4   )                 I   1     =       I   2     =       I   3     =   I               (   5   )             
 
 using (3) and (4), V BE1  and V N1  in  FIG. 1   a  can be expressed as:  
               V   BE1     =       V   T     ⁢           ⁢   ln   ⁢           ⁢     I     I   S                 (   6   )                 V   N1     =       I   ·   R1     +         V   T     ·   ln     ⁢           ⁢     I     M   ·     I   S                     (   7   )             
 
 where M is the area ratio between diodes Q 1  and Q 2  (Q 1 :Q 2 =1:M; thus M=Q 2 /Q 1 ) and where V BE1  is the base-emitter voltage drop of a bipolar transistor or the diode turn-on voltage. Because V BE1  and V N1  are a pair of input voltages for the op-amp, they are controlled to be the same voltage. 
 
 V   BE1   =V   N1   (8) 
 
 Using (6), (7), and (8), I is given by:  
             I   =         V   T     R1     ·   ln   ·   M             (   9   )             
 
 Using (9), the conventional BGR, the output voltage V BGR  becomes  
               V   BGR     =         I   ·   R2     +     V   BE1       =         R2   R1     ·     V   T     ·   ln   ·   M     +     V   BE1                 (     10   ⁢   a     )             
 
 Where V BE1  has a negative temperature coefficient of about −1.5 mV/K as shown in  FIG. 1   b , whereas V T  has a positive temperature coefficient of about +0.087 mV/K, so that V BGR  is determined by the resistance ratio of R 2 /R 1  and the area ratio of diode-wired transistors Q 1 , Q 2 .  FIG. 1   b  is a graph of the simulation results of the prior art bandgap circuit relating temperature in ° C. on the horizontal axis to voltage in Volt on the vertical axis for Curve V BE1  and Curve V BGR  (output voltage). Thus V BGR  is controlled to be about 1.25 V where the temperature dependence of V BGR  becomes negligibly small. As a result, the supplied voltage can not be lower than 1.25 V DS +V DS3 , which limits the low voltage design for CMOS circuits as shown in  FIG. 1   c , Curve  1 .  FIG. 1   c  is a graph of the simulation results of the prior art bandgap circuit relating the supply voltage V DD  in Volt on the horizontal axis versus the bandgap reference output voltage V BGR  in Volt on the vertical axis. 
 
         [0008]     A review of the prior art U.S. patents has yielded the following related patents: 
    U.S. Pat. No. 6,788,041 (Gheorghe et al.) discloses a bandgap reference circuit which when operating with a voltage source in the range from 1.0 to 1.2 volt provides a Vref output of about 242 and 245 mV, respectively, utilizing a PTAT current source.     U.S. Pat. No. 6,605,987 (Eberlein) teaches a temperature-stabilized reference voltage circuit using the current-mode technique, in which two partial currents are superimposed on each other and converted into the reference voltage. The circuit permits the implementation of low temperature-compensated output voltages below 1.0 V.     U.S. Pat. No. 6,529,066 (Guenot et al.) shows a bandgap circuit producing an output of 1.25 V and utilizing parasitic vertical PNP transistors operating at different current densities. A difference in the base-emitter voltages is developed across a resistor to produce a current with a positive temperature coefficient. When combined with another voltage with a negative temperature coefficient a bandgap reference voltage is produced.     U.S. Pat. No. 6,566,850 (Heinrich) describes a bandgap reference circuit, which includes a sensing circuit and a current injector circuit, that can transition quickly to a desired operational state by injecting bootstrap current into an internal node of the bandgap reference circuit. The bandgap reference circuit is effective with a low voltage power supply (e.g., 1-1.5 V).     U.S. Pat. No. 6,531,857 (Ju) presents a bandgap reference circuit which has a segmented resistor coupled across the emitter-base terminals of a PNP transistor to generate a V BE  current. The resistor sums this V BE  current with a PTAT current and generates a Vref voltage, where Vref can be less than V EB . V EB  typically is less than or equal to 0.7 V, resulting in a V DD  voltage of equal or larger than 0.85 V.     U.S. Pat. No. 6,489,835 (Yu et al.) discloses a bandgap reference circuit which operates with a voltage supply that can be less than 1 V and where only one non-zero current operating point is available. The bandgap reference circuit comprises a core circuit with an embedded current generator, and a bandgap reference generator with output V BG .     U.S. Pat. No. 6,281,743 (Doyle) describes a sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The generation of the reference signal includes generating first and second signals with negative and positive temperature coefficients, respectively. The first and second signals are then sampled and stored on first and second capacitors. A low impedance path between these capacitors yields the reference signal. Simulation shows a stable sub-bandgap reference output of 0.605 V using a supply voltage of only 1 V.     U.S. Patent Application Publication US 2004/0169549 A1 (Liu) presents a bandgap reference circuit comprising an op-amp, a plurality of MOS transistors coupled to the op-amp, a plurality of resistors and bipolar transistors coupled to the MOS transistors. Simulation and measurement results indicate that Vref, generated by the bandgap reference circuit, is within the range of 1.18 to 1.2 V from −40° C. to 120° C.     U.S. Patent Application Publication 2004/0155700 A1 (Gower et al.) teaches a bandgap reference voltage generator with low voltage operation comprising a first closed-loop circuit having a first current with a positive temperature coefficient, and a second closed-loop circuit having a second current with a negative temperature coefficient. The bandgap reference voltage generator includes a multitude of output stages where each output may be independently scaled to have either a zero, a positive or a negative temperature coefficient.    
 
         [0018]     A problem of many of the prior art circuits is that they tend not to be stable until the supply voltage is larger than 1.5 V or require additional components, such as capacitors which take considerable area, for stable operation at low supply voltages. Clearly a BGR circuit is desirable which can work down to sub-1-V supply voltages which is stable, simple to integrate, and has low cost.  
       SUMMARY OF THE INVENTION  
       [0019]     It is an object of at least one embodiment of the present invention to provide circuits and a method for a temperature independent voltage bandgap reference circuit which is capable of working down to sub-1-Volt.  
         [0020]     It is another object of the present invention to provide a circuit which utilizes standard CMOS processes.  
         [0021]     It is yet another object of the present invention to provide a bandgap reference circuit which is stable at supply voltages below 1.5 V.  
         [0022]     It is still another object of the present invention to allow adjustment of the positive and negative temperature coefficients.  
         [0023]     It is a further object of the present invention is to allow adjustment of the temperature coefficient to an arbitrarily selected value.  
         [0024]     It is yet a further object of the present invention is to provide for a fractional bandgap reference voltage.  
         [0025]     It is still a further object of the present invention is to provide a fractional bandgap reference voltage which, regardless of its chosen value, is temperature independent.  
         [0026]     These and many other objects have been achieved utilizing first a circuit which produces positive and negative reference voltages based on the area ratio of 1:M of two diode type devices or diode-connected transistors and the ratio of two resistive means. Secondly, these two reference voltages are driving a summing circuit, each using current sources and resistive means to generate a current which is dependent on the ratio of the positive reference voltage and a resistive means, and the ratio of the negative reference voltage and another resistive means. These currents are then summed using a final resistive means which produces the fractional temperature-independent sub-bandgap reference voltage. The magnitude of the fractional, temperature independent sub-bandgap reference voltage is determined by selecting a specific value for that final resistive means. The current sources of each summing circuit may have equal (W/L) ratios or, depending on the circuit implementation, the ratios of each of these current sources may be N:1 (where N is larger than or equal to 1) for one current source and P:1 (where P is larger than or equal to 1) for the other current source.  
         [0027]     These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]      FIG. 1   a  is a BGR circuit diagram of the related art.  
         [0029]      FIG. 1   b  is a graph of the BGR circuit of the related art comparing temperature versus reference voltage.  
         [0030]      FIG. 1   c  is a graph of the BGR circuit of the related art comparing supply voltage versus reference voltage.  
         [0031]      FIG. 2   a  is circuit diagram of a BGR circuit of a first preferred embodiment of the present invention.  
         [0032]      FIG. 2   b  is a graph of the BGR circuit of  FIG. 2   a  for voltage nodes relating temperature versus voltage.  
         [0033]      FIG. 2   c  is a graph of the BGR circuit of  FIG. 2   a  for the output reference voltage relating supply voltage versus voltage.  
         [0034]      FIG. 3  is a circuit diagram of a BGR circuit of a second preferred embodiment of the present invention.  
         [0035]      FIG. 4  is a circuit diagram of a BGR circuit of a third preferred embodiment of the present invention.  
         [0036]      FIG. 5  is a block diagram of the method of the present invention. 
     
    
       [0000]     Use of the same reference number in different figures indicates similar or like elements.  
       DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0037]     A new low voltage bandgap reference circuit (BGR) is proposed which will be described in detail below. The circuit uses current summation techniques to implement the temperature compensation and is capable of working down to sub-1-V using standard CMOS processes.  
       BGR Circuit  1   
       [0038]     Circuit  200  of  FIG. 2   a  illustrates a first preferred embodiment of the present invention.  FIG. 2   a  comprises a CMOS op-amp OA 1 , a current mirror with PMOS transistors MP 1 , MP 2 , MP 3 , diode-wired transistors Q 1 , Q 2 , and resistors R 1 , R 2 , all implemented in the standard CMOS process. VDD and VSS are the positive and negative power supply rails, respectively. Nodes BE 1  and N 1  are coupled to the minus and plus inputs of OA 1 , respectively. Nodes BE 1  (alternatively node BE 2 ) and POS are outputs which connect to inputs of op-amps OA 2 , OA 3 , respectively, described next. Resistor R 1  is coupled between node N 1  and Q 2 , resistor R 2  is coupled between node POS and VSS. The area ratio of Q 1  and Q 2  is Q 1 :Q 2 =1:M. Current source transistors MP 1 , MP 2 , MP 3  have the same (W/L) ratio and supply currents I 1 , I 2 , I 3 , respectively. The voltage V BE1  is seen at node BE 1 , voltage V N1  is seen at node N 1 , voltage V BE2  is seen at node BE 2 , voltage V POS  is seen at node POS, voltage V p  is seen at node P, voltage V N  is seen at node N, and voltage V REF  is seen at output node REF.  
         [0039]     PMOS transistor MP 4  and resistor Rn are serially coupled between VDD and VSS. The junction of MP 4  and Rn is node N. Inputs BE 1  (or alternately BE 2 ) and node N are coupled to the minus and plus inputs of OA 2 , respectively. The output of OA 2  couples to the gates of current source transistors MP 4  and MP 5 . PMOS transistor MP 5  and summing resistor Rc are serially coupled between VDD and VSS. The junction of MP 5  and Rc is output V REF . PMOS transistor MP 6  and resistor Rp are serially coupled between VDD and VSS. The junction of MP 6  and Rp is node P. Input POS and node P are coupled to the minus and plus inputs of OA 3 , respectively. The output of OA 3  couples to the gates of current source transistors MP 6  and MP 7 . Coupled in parallel to MP 5  is PMOS transistor MP 7 . Transistors MP 4 , MP 5 , MP 6 , MP 7  supply currents I 4 , I 5 , I 6 , I 7 , respectively. 
 
 As already stated above:  
           (     W   L     )     MP1     =         (     W   L     )     MP2     =         (     W   L     )     MP3     ⁢           ⁢   therefore   ⁢     :             
         I   1     =       I   2     =       I   3     =   I           
 
 using eq. (9)  
               V   Pos     =       I   ·   R2     =           V   T     R1     ·   ln   ·   M   ·   R2     =       R2   R1     ·     V   T     ·   ln   ·   M                 (     10   ⁢   b     )                   (     W   L     )     MP4     =           (     W   L     )     MP5     ⇒   14     =   15             (   11   )                   (     W   L     )     MP6     =           (     W   L     )     MP7     ⇒   16     =   17             (   12   )             
 
 Because V BE1  and V N  are a pair of input voltages for the op-amp, they would be controlled to be the same voltage:  
               V   BE1     =     V   N             (   13   )               I4   =         V   N     Rn     =       V   BE1     Rn               (   14   )             
 
 Because V POS  and V P  are a pair of input voltages for the op-amp, they would be controlled to be the same voltage.  
               V   POS     =     V   P             (   15   )               I6   =         V   P     Rp     =       V   POS     Rp               (   16   )             
 
 from (11) and (13)  
             I5   =       V   BE1     Rn             (   17   )             
 
 from (12) and (14)  
             I7   =       V   POS     Rp             (   18   )                 V   REF     =     Rc   ⁡     (     I5   +   I7     )               (   19   )             
 
 Using (17), (18), and (19)  
               V   REF     =         V   BE1     ·     (     Rc   Rn     )       +       V   POS     ·     (     Rc   Rp     )                 (   20   )             
 
 from (10b) we know that  
         V   POS     =       R2   R1     ·     V   T     ·   ln   ·   M         
 
 which has a positive temperature coefficient of about  
         (         +   0.087     ·     mV   /   K       ×     R2   R1     ×     ln   ·   M       )     .       
 
 After R 1 , R 2 , and M are determined, we can choose the ratio of Rn and Rp to obtain a V REF  whose temperature dependence becomes negligibly small as shown in the graph of  FIG. 2   b . We can therefore choose different values of Rc to obtain different V REF  voltages.  FIG. 2   b  is graph of the simulation results of the proposed bandgap circuit relating temperature in ° C. on the horizontal axis to voltage in mVolt on the vertical axis for Curves V BE1 , V POS , and the output voltage V REF . Curve V BE1  has a negative slope, Curve V POS  has a positive slope, resulting in Curve V REF  with a slope which is essentially zero throughout the temperature range of −40 to +125° C. 
 
 Once we have a temperature independent V REF  by choosing a suitable  
       Rn   Rp       
 
 ratio, selecting the different values of Rc would not destroy the temperature independent characteristic of V REF  but would just change the absolute value of V REF . Therefore we can choose a suitable value of Rc so that the voltage of V REF  is smaller than the external supply voltage. An example is shown in the graph of  FIG. 2   c , Curve  2 , which relates the supply voltage V DD  in Volt on the horizontal axis to voltage in mVolt on the vertical axis for the BGR circuit output voltage V REF . Curve  2  shows that V REF =0.6 V and that its value is almost a constant when V DD &gt;1.0 V. From the simulation results of  FIGS. 2   b  and  2   c , we find that the proposed first preferred embodiment of the BGR circuit can be applied to sub-1-V external voltage systems. 
 
       BGR Circuit  2   
       [0040]     With reference to circuit  300  of  FIG. 3 , we now discuss a second preferred embodiment of the present invention. The only changes in  FIG. 3  over  FIG. 2   a  are that (a) resistors Rn and Rp are replaced by resistors Rc so that there are three resistors Rc, all having the same value, and (b) the W/L ratios of MP 4  and MP 5 , and MP 6  and MP 7  are different. Elements previously discussed are indicated by like numerals and need not be described further.  
         [0000]     Note:  
         [0000]     MP 4 :MP 5 =N:1  
         [0041]     MP 6 :MP 7 =P:1 
                 (     W   L     )     MP4     =         N   ·       (     W   L     )     MP5       ⇒   I4     =     N   ·   I5               (   21   )                   (     W   L     )     MP6     =         P   ·       (     W   L     )     MP7       ⇒   I6     =     P   ·   I7               (   22   )             therefore                           V   REF     =         (     I5   +   I7     )     ·   Rc     =       [       (     I4   N     )     +     (     I6   P     )       ]     ·   Rc                                 V   REF     =         (         1   N     ·       V   N     Rc       +       1   P     ·       V   P     Rc         )     ·   Rc     =         V   N     N     +       V   P     P                                   V   REF     =         1   N     ⁢     V   BE1       +       1   P     ⁢     V   POS                 (   23   )             
 
 After R 1 , R 2 , and M are determined, we can choose the ratio of N and P to obtain a V REF  whose temperature dependence becomes negligibly small. 
 
       BGR Circuit  3   
       [0042]     With reference to circuit  400  of  FIG. 4 , we now discuss a third preferred embodiment of the present invention. The only changes in  FIG. 4  are that (a) resistor Rn is replaced by resistor Rc so that there are two resistors Rc both with the same value, and (b) the W/L ratios of MP 4  and MP 5  are different. Elements previously discussed are indicated by like numerals and need not be described further.  
         [0000]     Note:  
         [0043]     MP 4 :MP 5 =N:1 
                 (     W   L     )     MP4     =         N   ·       (     W   L     )     MP5       ⇒   I4     =     N   ·   I5               (   24   )                   (     W   L     )     MP6     =           (     W   L     )     MP7     ⇒   I6     =   I7             (   25   )             therefore                           V   REF     =         (     I5   +   I7     )     ⁢   Rc     =       (       I4   N     +   I6     )     ·   Rc                                 V   REF     =       (         1   N     ·       V   N     Rc       +       V   P     Rp       )     ·   Rc                               V   REF     =         1   N     ⁢     V   BE1       +       (     Rc   Rp     )     ·     V   POS                 (   26   )             
 
 After R 1 , R 2 , and M are determined, we can choose the ratio of  
         1   N     ⁢           ⁢   and   ⁢             ⁢             ⁢     Rc   Rp         
 
 to obtain a V REF  whose temperature dependence becomes negligibly small. 
 
         [0044]     We now describe the method of the invention with reference to  FIG. 5 : 
    Block  1  provides first and second reference voltages with positive and negative temperature coefficients, respectively.     Block  2  provides a first amplifying circuit with a first resistor and a first current source to generate a first current directly proportional to the first reference voltage and the reciprocal of the first resistor.     Block  3  provides a second amplifying circuit with a second resistor and a second current source to generate a second current directly proportional to the second reference voltage and the reciprocal of the second resistor.     Block  4  creates a bandgap reference voltage independent of temperature by choosing suitable values for the second and first resistor.     Block  5  generates the temperature independent bandgap reference voltage by summing the first and the second current in a third resistor.     Block  6  selects a fractional, temperature independent bandgap reference voltage by selecting a specific value for the third resistor.    
 
         [0051]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Technology Classification (CPC): 6