Patent Abstract:
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of internal read data buses. A first set of multiplexers selectively couple each of the internal write data buses to any of a plurality of banks of memory cells. Similarly, a second set of multiplexers selectively couple each of the banks of memory cells to any of the internal read data buses. Write data can be coupled to one of the banks concurrently with coupling read data from another of the banks. Also, write data may be concurrently coupled from respective write data buses to two different banks, and read data may be concurrently coupled from two different banks to respective read data buses.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates to memory systems, and more particularly, to systems and methods for coupling command, address and data signals between a memory controller and one or more memory devices. 
     BACKGROUND OF THE INVENTION 
     Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These DRAM devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The system memory is typically arranged in memory modules each having multiple memory devices, and the memory modules are coupled through a memory bus to the memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read or to which data or instructions are to be written. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory through the memory bus. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus. 
     A high data bandwidth is a desirable capability of memory systems. Generally, bandwidth limitations are not related to the memory controllers since the memory controllers sequence data to and from the system memory as fast as the memory devices allow. One approach to increasing bandwidth is to increase the speed of the memory data bus coupling the memory controller to the memory devices. However, memory devices have not been able to keep up with increases in the data bandwidth of memory controllers and memory data buses. In particular, the memory controller must schedule all memory commands to the memory devices in a manner that allows the memory devices to respond to the commands. Although these hardware limitations can be reduced to some degree through the design of the memory device, a compromise must be made because reducing the hardware limitations typically adds cost, power, and/or size to the memory devices, all of which are undesirable alternatives. While memory devices can rapidly handle “well-behaved” accesses at ever increasing rates, for example, sequel traffic to the same page of a memory device, it is much more difficult for the memory devices to resolve “badly-behaved traffic,” such as accesses to different pages of the memory device. As a result, the increase in memory data bus bandwidth does not result in a corresponding increase in the bandwidth of the memory system. 
     One approach to increasing the bandwidth of memory systems has been to use bank interleaving. In bank interleaving, two or more memory banks are accessed alternately so that preparations can be made to access data in one memory bank while data are being written to or read from another bank. The bandwidth of the memory system can be increased using this approach because it is not necessary to wait for memory access preparations like precharging to be completed before data can be coupled to or from the memory device. However, the memory bandwidth improvements that can be obtained with bank interleaving are limited by the inability to write to or read from multiple banks of memory at the same time. While preparations can be made to read from or write to a bank while data are being read from or written to another bank, it is not possible to actually couple the read data from or the write data to the bank until the access to the other bank has been completed. 
     An approach to increasing memory bandwidth that has some similarities to bank interleaving is memory device interleaving. In memory device interleaving, different memory devices are alternately accessed. As a result, preparations can be made to access one memory device while data is being read from or written to the other memory device. While memory device interleaving increases the memory bandwidth in a manner similar to the manner in which bank interleaving increases memory bandwidth, it suffers essentially the same limitations. In particular, it is not possible to actually couple the read data from or the write data to the memory device until the transfer of data to or from the other memory device has been completed. 
     In addition to the limited bandwidth of memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data cannot be output from the SDRAM device until a delay of several clock periods has occurred. Although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices. These latency issues generally cannot by alleviated to any significant extent by simply increasing the memory data bus bandwidth. 
     The memory latency problem is greatly exacerbated by read accesses alternating with write accesses, a situation known as “read/write turnarounds.” When a memory controller issues a read command to a memory device, the memory device must couple read data from a memory array to external data bus terminals of the memory device. The read data must then be coupled through a data bus portion of the memory bus from the memory device to the memory controller. It is only then that the memory controller can couple write data to the memory device through the data bus to initiate a write memory access. 
     Opening the page requires the coupling of memory command and a row address and a column address from the memory controller to the memory device. In response to the read address, the memory device must equilibrate the corresponding row, turn on access transistors for that row, and allow a sense amplifier for each column to sense the voltage that a respective memory cell couples to the sense amplifier. All of this can take a considerable period of time. For this reason, a read operations from a closed page and read/write turnarounds can prevent memory devices from even coming close to achieving the data bandwidths that are possible with high speed memory controllers and memory buses. 
     There is therefore a need for a memory device and memory system that allows a higher data bandwidth to be achieved. 
     SUMMARY OF THE INVENTION 
     A memory system is able to achieve a high bandwidth and low latency through the use of two separate data buses coupling a memory controller to one or more memory device. A downstream bus couples write data from the memory controller to each memory device, and an upstream bus couples read data from each memory device to the memory controller. As a result, read data can be coupled from each memory device to the memory controller at the same time that write data can be coupled from the memory controller to each memory device. The downstream memory bus may be used to couple memory commands and memory addresses to each memory device along with the write data. Each memory device may include dual internal write data buses that can concurrently transfer write data to different memory banks. Each memory device may also or alternatively include dual internal read data buses that can concurrently transfer read data to different memory banks. Furthermore, the write data buses may transfer write data to different banks at the same time that read data are being transferred to the read data buses from different banks. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a memory system according to one example of the present invention. 
         FIG. 2  is a block diagram of a memory system according to another example of the present invention. 
         FIG. 3  is a block diagram of a portion of a dynamic random access memory device that may be used in the memory systems of  FIGS. 1 and 2 . 
         FIG. 4  is a schematic diagram showing one example of a connection between a memory bank in the memory device of  FIG. 3  and dual write and read data buses. 
         FIG. 5  is a block diagram showing one example for obtaining command and address signals from a write data bus coupled to the memory device of  FIG. 3 . 
         FIG. 6  is a block diagram of a computer system using the memory system of  FIG. 1  or  2  or some other example of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     A memory system  10  according to one example of the invention is illustrated in  FIG. 1 . The memory system  10  includes a memory controller  14  coupled to the four dynamic random access memory (“DRAM”) devices  20 ,  22 ,  24 ,  26 . The memory controller  14  is coupled to each of the DRAM devices  20 – 26  by an 8-bit write data bus  30  and an 8-bit read data bus  32 . The memory controller  14  couples memory commands and memory addresses “downstream” to the DRAM devices  20 – 26  through either the write data bus  30 , a separate command/address bus (not shown) or separate command and address buses (not shown). If the memory commands and memory addresses are coupled through the downstream bus, the commands and addresses may be in the form of a packet, which, for write commands, may also include write data. 
     In operation, the memory controller  14  couples write data “downstream” to the DRAM devices  20 – 26  through the write data bus  30 , and the DRAM devices  20 – 26  couple read data “upstream” to the memory controller  14  through the read data bus  32 . The bandwidth of the write data bus  30  may be the same as the bandwidth of the read data bus  32 . Alternatively, the write data bus  30  and the read data bus  32  may have different bandwidths to accommodate different data rates through the buses  30 ,  32 . By using separate write and read data buses  30 ,  32 , respectively, the memory controller  14  can couple write data to the DRAM devices  20 – 26  at the same time that the memory devices  20 – 26  are coupling read to the memory controller  14 . 
     A memory system  40  according to another example of the invention is illustrated in  FIG. 2 . The memory system  40  of  FIG. 2  is substantially identical to the memory system  10  of  FIG. 1 . Therefore, in the interests of brevity, the components that are common to both memory systems  10 ,  40  have been provided with the same reference numerals, and a description of their structure and operation will not be repeated. The memory system  40  differs from the memory system  10  of  FIG. 1  by using synchronous DRAM (“SDRAM”) devices  20 ′– 26 ′ devices, which perform operations in synchronism with a clock signal. In the memory system  40  of  FIG. 2 , the memory controller  14  couples a write clock (“WCLK”) signal to the each of the SDRAM devices  20 ′– 26 ′ with each of the write data. The WCLK signal is used to capture the write data in the SDRAM device  20 ′– 26 ′ to which the write memory access is directed. In the memory system  40  of  FIG. 2 , the WCLK signal has transitions that occur substantially in the middle of when the corresponding write data are valid. Also, the SDRAM devices  20 ′– 26 ′ may be double data rate (“DDR”) devices in which write data is latched responsive to both the rising edge and the falling edge of the WCLK signal. However, other relationships between the phase and number of transitions of the WCLK signal and the write data may be used. 
     In a similar manner, each of the SDRAM devices  20 ′– 26 ′ couple a read clock (“RCLK”) signal to the memory controller  14  each time read data are coupled from the SDRAM device  20 ′– 26 ′ to the memory controller  14 . The RCLK signal is used by the memory controller  14  to capture the read data. In the memory system  40  of  FIG. 2 , the RCLK signal has transitions that occur at substantially the beginning and edge of the period when the corresponding read data are valid. Since the SDRAM devices  20 ′– 26 ′ are double data rate (“DDR”) devices, the read data is latched in the memory controller  14  responsive to both the rising edge and the falling edge of the RCLK signal. Again, the RCLK signal may have other relationships with the phase and number of transitions of the read data. 
     A portion of the SDRAM devices  20 ′– 26 ′ are shown in greater detail in  FIG. 3 . Each of the DRAM devices  20 ′– 26 ′ includes eight memory banks  44   a–h  each of which are coupled to a pair of internal write data buses  46   a,b  and a pair of internal read data buses  48   a,b . The write data buses  46   a,b  receive write data from a write buffer  50 , and the read data buses  48   a,b  couple read data to a read latch  52 . Write data is coupled to the write buffer  50  through a write data bus  54  and is latched into the buffer  50  by a clock signal coupled through line  56 . Memory commands and addresses are also coupled through the write data bus  54 , and they are stored in a command/address register  58 . 
     The read latch  52  outputs read data on an 8-bit read data bus  60  in synchronism with a clock signal that is also coupled from the read latch  52  on line  62 . The memory devices  20 ′– 26 ′ include a large number of other conventional memory device components, but these have been omitted from  FIG. 3  in the interest of brevity and clarity. 
     In operation, memory commands, such as write commands and read commands, as well as memory addresses are coupled through the write data bus  54 . The memory commands and addresses are stored in the command/address register  58 . The write data is also coupled through the write data bus  54  and stored in the write buffer  50 . In response to a read command coupled to the command/address register  58 , the memory devices  20 ′– 26 ′ output read data, which are coupled to the read latch  52 . The read latch  52  stores the read data until the read data bus  60  and memory controller  14  ( FIG. 1 ) are able to receive the read data. The read data are then clocked out of the read latch  52  through the read data bus  60 . The read memory accesses are preferably given priority over write memory accesses so that a number of write commands and associated addresses are stored in the command/address register  58  while the write data are accumulated in the write buffer  48 . When a sufficient number of write accesses have been accumulated, they can be processed sequentially without any intervening read accesses. As a result, the latency penalties inherent in read/write turnarounds are avoided. 
     The use of two write data buses  46   a,b  makes it possible to couple write data to one of the banks  44   a–h  concurrently with the coupling of write data to another one of the banks  44   a–h . Similarly, the use of two read data buses  48   a,b  makes it possible to couple read data from one of the banks  44   a–h  concurrently with the coupling of read data from another one of the banks  44   a–h . Furthermore, it is possible to couple write data to one of the banks  44   a–h  concurrently with the coupling of read data from another one of the banks  44   a–h . It is even possible to concurrently couple write data to two banks  44   a–h  at the same time that read data are being concurrently coupled from two different banks  44   a–h . Other combinations of data coupling will be apparent to one skilled in the art. As a result, as explained in greater detail below, bank interleaving may be accomplished concurrently in the memory devices  20 – 26 . Also, by allowing a read command to be coupled through the write data bus  54  and stored in the command/address register  58 , read commands can be coupled to the memory devices  20 – 26  during write or read operation. As a result, the latency for read operations is minimized. Otherwise, it would be necessary to wait for a write operation to be completed before a read command could be sent. 
     Each of the DRAM devices  20 – 26  is substantially identical to the SDRAM devices  20 ′– 26 ′ shown in  FIG. 3  except that a WCLK signal is not coupled to the write buffer  50  through the line  56 , and a RCLK signal is not coupled from the read latch  52  through the line  62 . 
     In one embodiment of the invention, the memory controller  14  ( FIG. 1 ) simply issues read and write memory commands and addresses to the memory devices  20 – 26  and  20 ′– 26 ′. The memory commands are stored in the command/address register  58  until the memory devices  20 – 26  and  20 ′– 26 ′ are able to process them. The commands are then processed by each of the memory devices  20 – 26  and  20 ′– 26 ′. The memory devices  20 – 26  and  20 ′– 26 ′ may also couple a read response or a write response to the memory controller  14  through the read data bus  60 . The read responses and write responses indicate to the memory controller  14  that processing of a corresponding memory request has been completed. The responses uniquely identify the memory request corresponding to the response so that it is not necessary for the memory controller  14  to keep track of the memory requests, and the memory requests may be processed out-of-order. In the case of a read response, the read response may also include the read data resulting from the corresponding read request. 
     One example of a circuit for coupling the banks  44   a–h  to the internal write data buses  46   a,b  and to the internal read data buses  48   a,b  is shown in  FIG. 4 . The internal write data buses  46   a,b  are coupled to respective inputs of a multiplexer  70   a . Although not shown in  FIG. 4 , one multiplexer  70   a–h  is provided for each of the banks  44   a–h , respectively, and all of the multiplexers  70   a–h  have their inputs coupled to both of the internal write data buses  46   a,b . Each of the multiplexers  70   a–h  has its output coupled to its respective bank  44   a–h  through a single respective bank write bus  72   a–h . The multiplexers  70   a–h  are operated by control signals (not shown in  FIG. 4 ) so that either of the internal write data buses  46   a,b  can be coupled to any of the banks  44   a–h.    
     The internal read data buses  48   a,b  are coupled to the banks  44   a–h  in a manner that is somewhat different from the manner in which the write data buses  46   a,b  are coupled to the banks  44   a–h . Each of two multiplexers  74   a,b  has its output coupled to a respective one of the internal read data buses  48   a,b . Corresponding inputs to the multiplexers  74   a,b  are coupled to each other and to a respective one of the banks  44   a–h  by a single respective bank read bus  78   a–h . Thus, a respective input to each of the multiplexers  74   a–b  is provided for each of the banks  44   a–h . The multiplexers  74   a–b  are operated by control signals (not shown in  FIG. 4 ) so that any of the banks  44   a–h  may be coupled to either of the internal read data buses  48   a,b.    
     A portion of the circuitry in the SDRAM devices  20 ′– 26 ′ shown in  FIG. 3  is shown in greater detail in  FIG. 5 . The write data bus  54  and the clock line  56  are coupled to respective inputs of a demultiplexer  80 , which routes the write data to a write buffer  84 , the memory commands to a command register  86 , and memory addresses to an address register  88 . The command register  86  includes control logic to decode memory commands and output corresponding control signals, some of which are shown in  FIG. 5 . The write buffer  84  stores write data for one or more write memory accesses, and then couples the write data to a DRAM array  90  at an appropriate time that is determined by control signals output from the control logic in the command register  86 . The DRAM array  90  includes the dual internal write data buses  46   a,b , the dual internal read data buses  48   a,b  and the banks  44   a–h  shown in  FIG. 3 . The DRAM array  90  also includes the multiplexers  70   a–h  and  74   a,b  shown in  FIG. 4 . Thus, the write data from the write buffer  84  is coupled to the banks  44   a –h. The write data for sequential write accesses are preferably coupled to different banks  44   a–h  so that the write data from both write accesses can be stored concurrently. 
     The address register  88  stored memory addresses that are coupled through the write data bus  56  along with a memory command and, in the case of a write request, write data. The address register  88  couples address bits corresponding to a bank address to bank control circuitry  92 , address bits corresponding to a row address to a row address latch  94 , and address bits corresponding to a column address to a column address counter  96 . The bank control circuitry  92  causes the write data or read data to be coupled to or from a selected one of the banks  44   a–h , and a row address stored in the latch  94  opens a corresponding row in the selected bank  44   a–h . The column address applied to the counter  96  sets the initial count of an internal counter, which is then output to the selected bank  44   a–h.    
     A computer system  100  using the memory system  10  of  FIG. 1 , the memory system  40  of  FIG. 2  or a memory system according to some other example of the present invention is shown in  FIG. 6 . The computer system  100  includes a processor  102  for performing various computing functions, such as executing specific software for performing specific calculations or tasks. The processor  102  includes a processor bus  104  that normally includes an address bus, a control bus, and a data bus. The processor bus is coupled to an expansion bus  108 , such as a peripheral component interconnect (“PCI”) bus, through a system controller  110 . The computer system  100  includes one or more input devices  114 , such as a keyboard or a mouse, coupled to the processor  102  through the expansion bus  108 , system controller  110  and processor bus  104  to allow an operator to interface with the computer system  100 . Typically, the computer system  100  also includes one or more output devices  116  coupled to the expansion bus  108 , such output devices typically being a printer or a video terminal. One or more mass data storage devices  118  are also typically coupled to the expansion bus  108  to store data or retrieve data from external storage media (not shown). Examples of typical mass data storage devices  118  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  102  is also typically coupled to a cache memory  126 , which is usually static random access memory (“SRAM”). As mentioned above, the computer system  100  also includes a memory system, such as the memory system  10  or  40 . Specifically, the system controller  110  includes the memory controller  14 , which, as explained above with reference to  FIGS. 1 and 2 , is coupled to several DRAM devices  20 – 26  or  20 ′– 26 ′. The memory controller  14  is coupled to each of the DRAM devices  20 – 26  or  20 ′– 26 ′ through the write data bus  30  and the read data bus  32  as well as a command bus  130  and an address bus  134 . 
     Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.

Technology Classification (CPC): 6