Patent Abstract:
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry. The operational amplifier contains two input circuits that are time multiplexed in a manner that allows capacitance to be discharged at one input circuit while the other input circuit is inputting signals into the amplifier. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Full Description:
FIELD OF THE INVENTION 
   Embodiments of the invention relate to pipelined analog-to-digital converters that share operational amplifiers between stages of the pipeline and signal processing circuitry that shares an operational amplifier between two signal processing channels. 
   BACKGROUND OF THE INVENTION 
   Analog-to-digital converters (ADCs) are useful components in any circuit or system that interfaces analog and digital circuitry and signals. One application in which analog-to-digital converters are particularly useful includes imaging devices such as CMOS and CCD imagers. Imagers typically convert light photons into analog image signals. These analog image signals are converted to digital signals, by an analog-to-digital converter, and then processed by an image processor or other processing circuitry. 
   There is a desire to increase the speed of the analog-to-digital conversion process in many applications such as e.g., imagers. As such, many applications use pipelined analog-to-digital converters, which typically operate faster than non-pipelined analog-to-digital converters.  FIG. 1  is an illustration of a conventional N-bit pipelined analog-to-digital converter  10 . The pipelined analog-to-digital converter  10  consists of multiple low resolution (e.g., 1.5 bits) stages  12   1 ,  12   2 , . . . ,  12   n ,  12   N-1 , each of which comprises an arithmetic unit  20  and a two-level decision circuit  40 . The pipelined analog-to-digital converter  10  further includes digital correction logic  14  for outputting an N-bit digital code representing an input analog signal. 
     FIG. 1  illustrates the components of the nth stage  12   n  in more detail. It should be appreciated that the other stages  12   1 ,  12   2 , . . . ,  12   N-1  contain the same circuitry as the nth stage  12   n . The arithmetic unit  20  comprises a switching block  22 , four additional switches  24 ,  26 ,  28 ,  30 , a sampling capacitor Cs, a feedback capacitor Cf, and an operational amplifier  32 . The decision circuit  40  includes two comparators  42 ,  44  and an encoder  46 . 
   In operation, the arithmetic unit  20  in the first stage  12   1  merely operates as a sample and hold circuit. In the other stages  12   2 , . . . ,  12   n ,  12   N-1 , the arithmetic unit  20  multiplies the incoming analog signal portion V RES(n-1) , often referred to as a “residue,” by a factor of two and subtracts from this product one of three voltages +V R , 0, −V R , based on the closed switch in the switching block  22 . The switches of block  22  are opened/closed based on the decision bits D n-1  from a prior stage (e.g., stage  12   n-1 ). The new residue is fed into the decision circuit  40 , where it is compared with two different reference voltages ¼VR, −¼V R . The encoder generates and outputs decision bits D n  for the stage  12   n . The decision bits for each of the stages  12   1 ,  12   2 , . . . ,  12   n , . . .  12   N-1  are processed by the digital correction logic  14 , which removes any redundancy and outputs the N-bit digital output code. 
   As can be seen in  FIG. 1 , the conventional pipelined analog-to-digital converter  10  requires one operational amplifier  32  for each stage  12   1 ,  12   2 , . . . ,  12   n , . . .  12   N-1  in the pipeline. The majority of the power of the pipelined analog-to-digital converter  10  is consumed by operational amplifiers  32 . Therefore, minimizing the power consumption of the operational amplifiers  32  is key to the design of low power pipelined analog-to-digital converters  10 . 
     FIG. 2  illustrates the timing diagram for two stages STAGE  1 , STAGE  2  of the  FIG. 1  pipelined analog-to-digital converter  10 . Non-overlapping clock signals PHI 1 , PHI 2  are used to control the switching circuitry contained within each stage STAGE  1 , STAGE  2  to configure how the sampling and feedback capacitors Cs, Cf and the operational amplifier  32  are connected. 
     FIG. 3  illustrates the operational amplifier configuration of the two stages STAGE  1 , STAGE  2  when the second clock signal PHI 2  is asserted (i.e., has a high level). As can be seen in  FIGS. 2 and 3 , the first stage STAGE  1  undergoes a sampling operation while the second stage STAGE  2  undergoes an amplifying operation. That is, the first stage&#39;s arithmetic unit  20   1  is configured such the analog input voltage Vin is sampled in the sampling capacitor Cs. The second stage&#39;s arithmetic unit  20   2  is configured in a manner such that the operational amplifier  32  amplifies the signal stored in the sampling capacitor Cs and outputs the amplified signal as Vout. 
     FIG. 4  illustrates the operational amplifier configuration of the two stages STAGE  1 , STAGE  2  when the first clock signal PHI 1  is asserted (i.e., has a high level). As can be seen in  FIGS. 2 and 4 , the first stage STAGE  1  undergoes the amplifying operation while the second stage STAGE  2  undergoes the sampling operation. That is, the first stage&#39;s arithmetic unit  20   1  is configured such the signal stored in the sampling capacitor Cs is amplified by the operational amplifier  32 . The second stage&#39;s arithmetic unit  20   2  is configured to sample the output from the first stage STAGE  1  and store it in the stage  2  STAGE  2  sampling capacitor Cs. 
   It can be seen from  FIGS. 3 and 4  that during the sampling operations, the operational amplifiers  32  performs no useful function; they just consume power. This occurs because the operational amplifiers  32  are placed into an open-loop configuration with their inputs and outputs connected to known voltage levels. To avoid wasting power during every sampling operation, some analog-to-digital converters share one operational amplifier  32  between two adjacent stages STAGE  1 , STAGE  2  as is shown in  FIGS. 5 and 6 . 
     FIGS. 5 and 6  illustrate a circuit  120  of a pipelined analog-to-digital converter in which arithmetic units  20   1 ,  20   2  of two pipeline stages STAGE  1 , STAGE  2  share one operational amplifier  32 . The amplifier  32  can be shared because the circuit  120  contains six switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6  that are controlled to connect the sampling and feedback capacitors Cs, Cf to the operational amplifier  32  inputs and outputs differently depending on the operation being performed. 
     FIG. 5  illustrates the circuit  120  when the second clock signal PHI 2  of  FIG. 2  is asserted. While the second clock signal PHI 2  is asserted, switch S 1  is closed to connect the analog input voltage Vin to the stage  1  arithmetic unit  20   1  sampling capacitor Cs. Switches S 5  and S 6  are closed in the second stage&#39;s arithmetic unit  20   2  such that the operational amplifier  32  amplifies, and outputs as Vout, a signal stored in the stage  2  arithmetic unit  20   2  sampling capacitor Cs. The other switches S 2 , S 3  and S 4  are left open. Thus, as can be seen in  FIGS. 2  and  5 , the first stage STAGE  1  undergoes a sampling operation while the second stage STAGE  2  undergoes an amplifying operation, but only one operational amplifier  32  is connected and used. 
     FIG. 6  illustrates the circuit  120  when the first clock signal PHI 1  of  FIG. 2  is asserted. While the first clock signal PHI 1  is asserted, switches S 1 , S 5  and S 6  are open, and switches S 2 , S 3  and S 4  are closed. As such, the first stage&#39;s arithmetic unit  20   1  is configured such that a signal stored in the first stage arithmetic unit  20   1  sampling capacitor Cs is amplified by the operational amplifier  32  and output as Vout. The second stage&#39;s arithmetic unit  20   2  is configured to sample and store an analog input Vin in the stage  2  STAGE  2  sampling capacitor Cs. As can be seen in  FIGS. 2 and 6 , the first stage STAGE  1  undergoes the amplifying operation while the second stage STAGE  2  undergoes the sampling operation. Again, only one operational amplifier  32  is connected and used during these operations. 
   By sharing an operational amplifier  32  between two adjacent stages STAGE  1 , STAGE  2 , the power consumption of the pipelined analog-to-digital converter  10  ( FIG. 1 ) can be reduced by half. However due to the finite DC gain A O  and input parasitic capacitance Cp of the operational amplifier  32  ( FIG. 7   b ), the previous output V O (k−1) adversely effects the present output V O (k), which is known in the art as the “memory effect.” The memory effect can cause a non-linearity in the operational amplifier  32  and thus, analog-to-digital converter output. 
   Briefly, the memory effect can be described using the following equations in reference to  FIG. 7   a . Ideally, during sampling, charge should be represented as Q=(Cf+Cs)×Vin. From charge conversion, at the amplifying phase, Q=Cf×(V O −V X )−Cp×V X −Cs×V X =(Cf+Cs)×Vin, where V X  is the input node voltage of the operational amplifier  32 . Because the amplifier has a finite gain A O , V O =−A O ×V X , which yields V X =−V O /A O . This means that Cf×(V O +V O /A O )+Cp×V O /A O +Cs×V O /A O =(Cf+Cs)×Vin. Therefore, V O =Vin×(Cf+Cs)/(Cf+(Cf+Cs+Cp)/A O ), which equals Vin×Gc. 
   In reality, however, there is charge associated with parasitic capacitance Cp (due to the memory effect). As such, at the sampling stage, as shown in  FIG. 7   b , Q=(Cf+Cs)×Vin(k)−Cp×Vin_err(k), where Vin_err(k) is the memory error associated with the parasitic capacitance Cp. Using just the error term, from charge conversion, V O (k)=−Vin_err(k)×Cp/(Cf+(Cf+Cs+Cp)/A O )˜=−Vin_err(k)×Cp/Cf, if A O  is large enough. For the first and second terms V O (k)=Vin(k)×Gc−Vin_err(k)×Cp/(Cf+(Cf+Cs+Cp)/A O ). Since Vin_err(k) comes from the previous output, Vin_err(k)=−V O (k−1)/A O =−Gc×Vin(k−1)/A O . Accordingly, V O (k)=Vin(k)×Gc+Vin(k−1)×Gc/A O ×Cp/(Cf+(Cf+Cs+Cp)/A O )=Vin(k)×Gc+Vin(k−1)×Gc×e, where e=1/A O ×Cp/(Cf+(Cf+Cs+Cp)/A O )˜1/A O ×Cp/Cf. It should be noted that the second order errors are neglected in the above calculations. 
   In addition, charge injection and kickback noise from the circuitry add to the memory effect error described above. Reducing the memory effect is a key element in designing a pipelined analog-to-digital converter that shares operational amplifiers between two pipeline stages. 
   Accordingly, there is a need and desire for a pipelined analog-to-digital converter that shares an operational amplifier between two pipeline stages, yet does not suffer from the memory effect and the problems associated with the memory effect. 
   It is known to divide signal processing circuitry into multiple channels. For example, imagers often include multiple readout channels where one channel processes a specific set of pixel signals and at least one other channel processes the remaining sets of pixel signals.  FIG. 7   c  illustrates a two channel processing circuit  150  designed to sample and hold analog input signals and convert the signals into digital signals. As shown in  FIG. 7   c , the first channel CHANNEL  1  comprises a sample and hold circuit  152   a  and multiple analog-to-digital pipeline stages  154   a ,  156   a . Similarly, the second channel CHANNEL  2  comprises a sample and hold circuit  152   b  and multiple analog-to-digital pipeline stages  154   b ,  156   b . The sample and hold circuits  152   a ,  152   b  share an operational amplifier  32 . The analog-to-digital pipeline stages  154   a ,  154   b  share an operational amplifier  32  as do the other analog-to-digital pipeline stages  156   a ,  156   b . 
   The devices of the two channels CHANNEL  1 , CHANNEL  2  share the operational amplifiers in a similar manner and with similar timing (e.g.,  FIG. 2 ) as the adjacent pipelined analog-to-digital converter stages share the operational amplifiers (as discussed above). That is, the channels switch in or out the amplifier based on the operation being performed in that portion of the channel. Thus, although the circuit  150  achieves the benefits of reducing the number of operational amplifiers, the circuit  150  also suffers from the memory effect. 
   Accordingly, there is a need and desire for sharing an operational amplifier between two channels of a signal processing circuit, yet does not suffer from the memory effect and the problems associated with the memory effect. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is an illustration of a conventional N-bit pipelined analog-to-digital converter. 
       FIG. 2  is a timing diagram for two stages of the  FIG. 1  pipelined analog-to-digital converter. 
       FIG. 3  illustrates the operational amplifier configuration of the two stages of the  FIG. 1  pipelined analog-to-digital converter in accordance with one timing of the  FIG. 2  timing diagram. 
       FIG. 4  illustrates the operational amplifier configuration of the two stages of the  FIG. 1  pipelined analog-to-digital converter in accordance with a second timing of the  FIG. 2  timing diagram. 
       FIG. 5  illustrates a first shared operational amplifier configuration of the two stages of the  FIG. 1  pipelined analog-to-digital converter in accordance with one timing of the  FIG. 2  timing diagram. 
       FIG. 6  illustrates a second shared operational amplifier configuration of the two stages of the  FIG. 1  pipelined analog-to-digital converter in accordance with a second timing of the  FIG. 2  timing diagram. 
       FIGS. 7   a  and  7   b  illustrate by comparison the memory effect that arises in the shared operational amplifier configuration of the two stages of the  FIG. 1  pipelined analog-to-digital converter. 
       FIG. 7   c  illustrates a two channel signal processing circuit that shares operational amplifiers between respective portions of the channels. 
       FIGS. 8   a  and  8   b  illustrate a portion of a conventional two-channel signal processing circuit that shares operational amplifiers between respective portions of the channels. 
       FIG. 9  illustrates a conventional folded cascode operational amplifier used in the circuits illustrated in  FIGS. 8   a  and  8   b.    
       FIG. 10  illustrates a folded cascode operational amplifier constructed in accordance with an embodiment. 
       FIGS. 11   a  and  11   b  illustrate a portion of a two-channel signal processing circuit that shares operational amplifiers between respective portions of the channels constructed in accordance with an embodiment. 
       FIG. 12  illustrates another folded cascode operational amplifier constructed in accordance with another embodiment. 
       FIGS. 13   a  and  13   b  illustrate a portion of another two-channel signal processing circuit that shares operational amplifiers between respective portions of the channels constructed in accordance with another embodiment. 
       FIGS. 14   a  and  14   b  illustrate a circuit portion of two stages of a pipelined analog-to-digital converter which share an operational amplifier constructed in accordance with an embodiment. 
       FIGS. 14   c  and  14   d  illustrate another circuit portion of two stages of a pipelined analog-to-digital converter which share an operational amplifier constructed in accordance with an embodiment. 
       FIGS. 14   e  and  14   f  illustrate a circuit portion of two stages of a pipelined analog-to-digital converter which share an operational amplifier constructed in accordance with another embodiment. 
       FIGS. 14   g  and  14   h  illustrate a circuit portion of two stages of a pipelined analog-to-digital converter which share an operational amplifier constructed in accordance with another embodiment. 
       FIG. 15  is a block diagram of a CMOS imager, which utilizes either the pipelined analog-to-digital converter or the shared channel processing circuitry constructed in accordance with an example embodiment. 
       FIG. 16  is a block diagram of a processing system utilizing the imaging system illustrated in  FIG. 15 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments described herein provide a pipelined analog-to-digital converter that shares an operational amplifier between two pipeline stages, yet does not suffer from the problems of prior art circuits. The embodiments also provide for the sharing of an operational amplifier between two channels of a signal processing circuit, yet does not suffer from the problems of prior art circuits. 
     FIGS. 8   a  and  8   b  illustrate a portion of a conventional two-channel signal processing circuit  150  that shares an operational amplifier  32  between respective portions of the channels  152   a ,  152   b . The first channel  152   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 15 , S 16 , S 17 , S 18 . The second channel  152   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , S 11 , S 12 , S 19 , S 20 , S 21 , S 22 , S 23 , S 24 . Between the two channels  152   a ,  152   b , is a conventional folded cascode operational amplifier  32  (described below in more detail with respect to  FIG. 9 ). 
     FIG. 8   a  illustrates the configuration for the two channels  152   a ,  152   b  when the first clock signal PHI 1  is asserted by the clock generator  148 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first channel  152   a  while switches S 11 , S 12 , S 19 , S 20 , S 21  and S 24  are closed in the second channel  152   b . This connects the first channel  152   a  to receive differential input signals Vinp, Vinn while the second channel  152   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 8   b  illustrates the configuration for the two channels  152   a ,  152   b  when the second clock signal PHI 2  is asserted. When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 15 , S 16 , S 17  and S 18  are closed in the first channel  152   a  while switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second channel  152   b . This connects the second channel  152   b  to receive differential input signals Vinp, Vinn while the first channel  152   a  amplifies signals previously stored in capacitors C 1 -C 4 . 
     FIG. 9  illustrates a conventional folded cascode operational amplifier  32  used in the circuit  150  illustrated in  FIGS. 8   a  and  8   b . The operational amplifier comprises six PMOS transistors P 1 , P 2 , P 3 , P 4 , P 5 , P 6  and seven NMOS transistors N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 . Transistors P 1 , P 2 , N 1 , N 2  are serially connected between a voltage source Vcc and a ground potential. Transistors P 5 , P 6 , N 5 , N 6  are serially connected between the voltage source Vcc and the ground potential. Transistors P 3  and N 3  are serially connected between the voltage source Vcc and a source/drain terminal of the seventh NMOS transistor N 7 . Transistors P 4  and N 4  are also serially connected between the voltage source Vcc and the same source/drain terminal of the seventh NMOS transistor N 7 . The connection between the first and second PMOS transistors P 1 , P 2  is connected to the connection between the third PMOS and third NMOS transistors P 3 , N 3 . Similarly, the connection between the fifth and sixth PMOS transistors P 5 , P 6  is connected to the connection between the fourth PMOS and fourth NMOS transistors P 4 , N 4 . 
   Input voltages Vinp, Vinn, described above, are respectively connected to the gates of the third and fourth NMOS transistors N 3 , N 4 . Output voltages Voutn, Voutp are respectively taken from output nodes ON, OP. The gates of transistors P 1 , P 3 , P 4 , and P 5  are connected to a first bias voltage biasp. The gates of transistors P 2  and P 6  are connected to a second bias voltage biaspc. The gates of transistors N 1  and N 5  are connected to a third bias voltage biasnc. The gates of transistors N 2  and N 6  are connected to a fourth bias voltage biasn. The seventh NMOS transistor N 7  has its gate connected to a bias control signal biasn_tail. The operational amplifier  32  is controlled by the bias voltages and generates the differential output voltages Voutn, Voutp based on the input voltages Vinn, Vinp. This type of operational amplifier typically offers high gain and fast settling times. 
   As stated above, the circuitry illustrated in  FIGS. 8   a ,  8   b  and  9  suffers from the memory effect. Co-pending U.S. patent application Ser. No. 11/211,566, also assigned to Micron Technology, Inc., provides one solution to the memory effect problem and is hereby incorporated by reference in its entirety. The solution of the &#39;566 application uses a discharge switch connected to an input of the operational amplifier and special timing to overcome the memory effect. The present application discloses other embodiments. Certain of these embodiments do not require a discharge switch or special timing. A first embodiment is now described with reference to  FIGS. 10 ,  11   a  and  11   b.    
     FIG. 10  illustrates a folded cascode operational amplifier  232  constructed in accordance with an embodiment. The illustrated amplifier  232  contains two input circuits  202 A,  202 B and amplifying circuitry, designated generally with reference numeral  234 . 
   The first input circuit  202 A contains two NMOS transistors N 30 , N 31  and two switches S 30 , S 31 . A source/drain terminal of transistor N 30  is connected to a source/drain terminal of transistor N 31 , which is also connected to node C within circuitry  234 . The other source/drain terminal of transistor N 30  is connected to node A within circuitry  234  through switch S 30  while the other source/drain terminal of transistor N 31  is connected to node B within circuitry  234  through switch S 31 . The gate of transistor N 30  is connected to a first input voltage Vinp. The gate of transistor N 31  is connected to a second input voltage Vinn. 
   The second input circuit  202 B contains two NMOS transistors N 32 , N 33  and two switches S 32 , S 33 . A source/drain terminal of transistor N 32  is connected to a source/drain terminal of transistor N 33 , which is also connected to node C within circuitry  234 . The other source/drain terminal of transistor N 32  is connected to node B within circuitry  234  through switch S 32  while the other source/drain terminal of transistor N 33  is connected to node A within circuitry  234  through switch S 33 . The gate of transistor N 33  is connected to receive the first input voltage Vinp. The gate of transistor N 33  is connected to receive the second input voltage Vinn. 
   Thus, each input circuit  202 A,  202 B is connected to receive differential input voltages Vinp, Vinn. As will be described below with reference to  FIGS. 11   a  and  11   b , each input circuit  202 A,  202 B can be connected to a respective channel of a two-channel processing system. In addition, as will be described below with reference to  FIGS. 14   a - 14   d , each input circuit  202 A,  202 B can be connected to a respective stage within a shared pipelined analog-to-digital converter. In operation, the two input circuits  202 A,  202 B are time-multiplexed to share components within the remaining circuitry  234  of the amplifier  232  (described below). 
   The remaining circuitry  234  of the illustrated amplifier  232  contains similar components as the conventional amplifier  32  ( FIG. 9 ) with the below noted exceptions. The third PMOS transistor P 3  is connected between node A and the voltage source Vcc. The fourth PMOS transistor P 4  is connected between node B and the voltage source Vcc. The seventh NMOS transistor N 7  is connected between the ground potential and node C. The operation of the operational amplifier  232  of the first embodiment is now described with reference to  FIGS. 11   a  and  11   b , which illustrate a portion of a two-channel signal processing circuit  250  that shares operational amplifiers  232  between respective portions of the channels  252   a ,  252   b . 
   The first channel  252   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 17 , and S 18  and includes the second input circuit  202 B of amplifier  232 . The second channel  252   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , S 11 , S 12 , S 21 , S 22 , S 23 , and S 24  and includes the first input circuit  202 A of amplifier  232 . Between the two channels  252   a ,  252   b , is the remaining circuitry  234  of the folded cascode operational amplifier  232 . 
     FIG. 11   a  illustrates the configuration for the two channels  252   a ,  252   b  when the first clock signal PHI 1  is generated and asserted by a clock generator  248 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first channel  252   a  while switches S 11 , S 12 , S 21  and S 24  are closed in the second channel  252   b . In addition, switches S 30  and S 31  are closed in the first input circuit  202 A. This configuration connects the first channel  252   a  to receive the differential input signals Vinp, Vinn while the second channel  252   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 11   b  illustrates the configuration for the two channels  252   a ,  252   b  when the second clock signal PHI 2  is generated and asserted by the clock generator  248 . When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 17  and S 18  are closed in the first channel  252   a , switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second channel  252   b  and switches S 32  and S 33  are closed in the second input circuit  202 B. This configuration connects the second channel  252   b  to receive differential input signals Vinp, Vinn while the first channel  252   a  amplifies signals previously stored in capacitors C 1 -C 4 . 
   Therefore, as can be seen from  FIGS. 11   a  and  11   b , during the sampling operations, the input nodes of the input circuits  202 A,  202 B are connected to the common mode voltage Vcm or to each other so that the differential voltage stored in the input circuits  202 A,  202 B are removed. This means that the circuitry  250 , using the operational amplifier  232 , uses the entire sampling period to remove the memory effect (i.e., discharges any parasitic capacitance in the input circuitry) and thus, does not sacrifice the settling time of the operational amplifier  232 . Moreover, the operation of the amplifier  232  and the circuitry  250  is exactly the same as, and uses the same timing, as the conventional circuitry. That is, the amplifier  232  and circuitry  250  operate in accordance with the timing diagram illustrated in  FIG. 2 . Therefore, no additional timing or operations are required, which means that the clock generator  248  may be a simple or conventional generator. 
   Accordingly, the advantages of the first operational amplifier  232  include: (1) reducing the residual error associated with parasitic capacitance; (2) using more of the sampling period to reduce the residual error; (3) achieving low power consumption without adversely impacting the settling time of the amplifier  232 ; and (4) limiting or not requiring timing changes or additional timing circuitry to implement. 
     FIG. 12  illustrates another folded cascode operational amplifier  332  constructed in accordance with another embodiment. The illustrated amplifier  332  contains two input circuits  302 A,  302 B and amplifying circuitry, designated generally with reference numeral  334 . 
   The first input circuit  302 A contains two NMOS transistors N 30 , N 31 , but only one switch S 40 . A source/drain terminal of transistor N 30  is connected to a source/drain terminal of transistor N 31 , which is also connected to node C within circuitry  334  through switch S 40 . The other source/drain terminal of transistor N 30  is connected to node A within circuitry  334  while the other source/drain terminal of transistor N 31  is connected to node B within circuitry  334 . The gate of transistor N 30  is connected to a first input voltage Vinp. The gate of transistor N 31  is connected to a second input voltage Vinn. 
   The second input circuit  302 B contains two NMOS transistors N 32 , N 33  and one switch S 41 . A source/drain terminal of transistor N 32  is connected to a source/drain terminal of transistor N 33 , which is also connected to node C within circuitry  334  through switch S 41 . The other source/drain terminal of transistor N 32  is connected to node B within circuitry  334  while the other source/drain terminal of transistor N 33  is connected to node A within circuitry  334 . The gate of transistor N 33  is connected to receive the first input voltage Vinp. The gate of transistor N 33  is connected to receive the second input voltage Vinn. 
   Thus, each input circuit  302 A,  302 B is connected to receive differential input voltages Vinp, Vinn. As will be described below with reference to  FIGS. 13   a  and  13   b , each input circuit  302 A,  302 B can be connected to a respective channel of a two-channel processing system. In addition, as will be described below with reference to  FIGS. 14   e - 14   h , each input circuit  302 A,  302 B can be connected to a respective stage within a shared pipelined analog-to-digital converter. In operation, the two input circuits  302 A,  302 B are time-multiplexed to share components within the remaining circuitry  334  of the amplifier  332  (described below). 
   The remaining circuitry  334  of the illustrated amplifier  332  contains the same components as the components contained in the first embodiment ( FIG. 10 ). The operation of the operational amplifier  332  of the second embodiment is now described with reference to  FIGS. 13   a  and  13   b , which illustrate a portion of a two-channel signal processing circuit  350  that shares operational amplifiers  332  between respective portions of the channels  352   a ,  352   b . 
   The first channel  352   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 17 , and S 18  and includes the second input circuit  302 B of amplifier  332 . The second channel  352   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , S 11 , S 12 , S 21 , S 22 , S 23 , and S 24  and includes the first input circuit  302 A of amplifier  332 . Between the two channels  352   a ,  352   b , is the remaining circuitry  334  of the folded cascode operational amplifier  332 . 
     FIG. 13   a  illustrates the configuration for the two channels  352   a ,  352   b  when the first clock signal PHI 1  is generated and asserted by a clock generator  348 . As with the first embodiment, the generator  348  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first channel  352   a  while switches S 11 , S 12 , S 21  and S 24  are closed in the second channel  352   b . In addition, switch S 40  is closed in the first input circuit  302 A. This configuration connects the first channel  352   a  to receive the differential input signals Vinp, Vinn while the second channel  352   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 13   b  illustrates the configuration for the two channels  352   a ,  352   b  when the second clock signal PHI 2  is generated and asserted by the clock generator  348 . When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 17  and S 18  are closed in the first channel  352   a , switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second channel  352   b  and switch S 41  is closed in the second input circuit  302 B. This configuration connects the second channel  352   b  to receive differential input signals Vinp, Vinn while the first channel  352   a  amplifies signals previously stored in capacitors C 1 -C 4 . As can be seen, since the generator  348  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 , the amplifier  332  and circuitry  350  achieve the same advantages as the first embodiment described above. 
     FIGS. 14   a  and  14   b  illustrate a circuit portion  420  of two stages  420   a ,  420   b  of a pipelined analog-to-digital converter which share an operational amplifier  232  constructed in accordance with an embodiment. The first stage  420   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 17  and S 18  and includes the second input circuit  202 B of amplifier  232 . The second stage  420   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , S 11 , S 12 , S 21 , S 22 , S 23 , and S 24  and includes the first input circuit  202 A of amplifier  232 . The connection between switches S 9  and S 10  is connected to output node OP while the connection between switches S 7  and S 8  is connected to output node ON. Between the two stages  420   a ,  420   b , is the remaining circuitry  234  of the folded cascode operational amplifier  232  described above. 
     FIG. 14   a  illustrates the configuration for the two stages  420   a ,  420   b  when the first clock signal PHI 1  is generated and asserted by a clock generator  448 . As with other embodiments, the generator  448  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first stage  420   a  while switches S 11 , S 12 , S 21  and S 24  are closed in the second stage  420   b . In addition, switches S 30  and S 31  are closed in the first input circuit  202 A. This configuration connects the first stage  420   a  to receive the differential input signals Vinp, Vinn while the second stage  420   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 14   b  illustrates the configuration for the two stages  420   a ,  420   b  when the second clock signal PHI 2  is generated and asserted by the clock generator  448 . When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 17  and S 18  are closed in the first stage  420   a , switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second stage  420   b  and switches S 32  and S 33  are closed in the second input circuit  202 B. This configuration connects the second stage  420   b  to receive differential input signals Vinp, Vinn while the first stage  420   a  amplifies signals previously stored in capacitors C 1 -C 4 . As can be seen, since the generator  448  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 , the amplifier  232  and circuitry  420  achieve the same advantages as the other embodiments described above. 
     FIGS. 14   c  and  14   d  illustrate a circuit portion  520  of two stages  520   a ,  520   b  of a pipelined analog-to-digital converter which share an operational amplifier  232  constructed in accordance with an embodiment. The first stage  520   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 17  and S 18  and includes the second input circuit  202 B of amplifier  232 . The second stage  520   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , S 11 , S 12 , S 21 , S 22 , S 23 , and S 24  and includes the first input circuit  202 A of amplifier  232 . In this embodiment, the connection between switches S 9  and S 10  is connected to output node ON while the connection between switches S 7  and S 8  is connected to output node OP. Between the two stages  520   a ,  520   b , is the remaining circuitry  234  of the folded cascode operational amplifier  232  described above. 
     FIG. 14   c  illustrates the configuration for the two stages  520   a ,  520   b  when the first clock signal PHI 1  is generated and asserted by a clock generator  548 . As with other embodiments, the generator  548  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first stage  520   a  while switches S 11 , S 12 , S 21  and S 24  are closed in the second stage  520   b . In addition, switches S 30  and S 31  are closed in the first input circuit  202 A. This configuration connects the first stage  520   a  to receive the differential input signals Vinp, Vinn while the second stage  520   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 14   d  illustrates the configuration for the two stages  520   a ,  520   b  when the second clock signal PHI 2  is generated and asserted by the clock generator  548 . When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 17  and S 18  are closed in the first stage  520   a , switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second stage  520   b  and switches S 32  and S 33  are closed in the second input circuit  202 B. This configuration connects the second stage  520   b  to receive differential input signals Vinp, Vinn while the first stage  520   a  amplifies signals previously stored in capacitors C 1 -C 4 . As can be seen, since the generator  548  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 , the amplifier  232  and circuitry  520  achieve the same advantages as the other embodiments described above. 
     FIGS. 14   e  and  14   f  illustrate a circuit portion  620  of two stages  620   a ,  620   b  of a pipelined analog-to-digital converter which share an operational amplifier  332  constructed in accordance with another embodiment. The first stage  620   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 17  and S 18  and includes the second input circuit  302 B of amplifier  332 . The second stage  620   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , S 11 , S 12 , S 21 , S 22 , S 23 , and S 24  and includes the first input circuit  302 A of amplifier  332 . The connection between switches S 9  and S 10  is connected to output node OP while the connection between switches S 7  and S 8  is connected to output node ON. Between the two stages  620   a ,  620   b , is the remaining circuitry  334  of the folded cascode operational amplifier  332  described above. 
     FIG. 14   e  illustrates the configuration for the two stages  620   a ,  620   b  when the first clock signal PHI 1  is generated and asserted by a clock generator  648 . As with other embodiments, the generator  648  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first stage  620   a  while switches S 11 , S 12 , S 21  and S 24  are closed in the second stage  620   b . In addition, switch S 40  is closed in the first input circuit  302 A. This configuration connects the first stage  620   a  to receive the differential input signals Vinp, Vinn while the second stage  620   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 14   f  illustrates the configuration for the two stages  620   a ,  620   b  when the second clock signal PHI 2  is generated and asserted by the clock generator  648 . When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 17  and S 18  are closed in the first stage  620   a , switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second stage  620   b  and switch S 41  is closed in the second input circuit  302 B. This configuration connects the second stage  620   b  to receive differential input signals Vinp, Vinn while the first stage  620   a  amplifies signals previously stored in capacitors C 1 -C 4 . As can be seen, since the generator  648  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 , the amplifier  332  and circuitry  620  achieve the same advantages as the other embodiments described above. 
     FIGS. 14   g  and  14   h  illustrate a circuit portion  720  of two stages  720   a ,  720   b  of a pipelined analog-to-digital converter which share an operational amplifier  332  constructed in accordance with an embodiment. The first stage  720   a  comprises four capacitors C 1 , C 2 , C 3 , C 4  and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 13 , S 14 , S 17  and S 18  and includes the second input circuit  302 B of amplifier  332 . The second stage  720   b  comprises four capacitors C 5 , C 6 , C 7 , C 8  and switches S 7 , S 8 , S 9 , S 10 , SI 1 , S 12 , S 21 , S 22 , S 23 , and S 24  and includes the first input circuit  302 A of amplifier  332 . In this embodiment, the connection between switches S 9  and S 10  is connected to output node ON while the connection between switches S 7  and S 8  is connected to output node OP. Between the two stages  720   a ,  720   b , is the remaining circuitry  334  of the folded cascode operational amplifier  332  described above. 
     FIG. 14   g  illustrates the configuration for the two stages  720   a ,  720   b  when the first clock signal PHI 1  is generated and asserted by a clock generator  748 . As with other embodiments, the generator  748  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 . When the first clock signal PHI 1  is asserted, switches S 1 , S 2 , S 5 , S 6 , S 13  and S 14  are closed in the first stage  720  while switches S 11 , S 12 , S 21  and S 24  are closed in the second stage  720   b . In addition, switch S 40  is closed in the first input circuit  302 A. This configuration connects the first stage  720   a  to receive the differential input signals Vinp, Vinn while the second stage  720   b  amplifies signals previously stored in capacitors C 5 , C 6 , C 7  and C 8 . Vcm is a common mode voltage used to place charge on (or read charge out of) the capacitors C 1 -C 8 . 
     FIG. 14   h  illustrates the configuration for the two stages  720   a ,  720   b  when the second clock signal PHI 2  is generated and asserted by the clock generator  748 . When the second clock signal PHI 2  is asserted, switches S 3 , S 4 , S 17  and S 18  are closed in the first stage  720   a , switches S 7 , S 8 , S 9 , S 10 , S 22  and S 23  are closed in the second stage  720   b  and switch S 41  is closed in the second input circuit  302 B. This connects the second stage  720   b  to receive differential input signals Vinp, Vinn while the first stage  720   a  amplifies signals previously stored in capacitors C 1 -C 4 . As can be seen, since the generator  748  generates the first and second clock signals PHI 1 , PHI 2  at the timing illustrated in  FIG. 2 , the amplifier  332  and circuitry  720  achieve the same advantages as the other embodiments described above. 
     FIG. 15  illustrates an exemplary imager  900  that may utilize the analog-to-digital converter or shared channel processing circuitry constructed in accordance with any of the embodiments described above. The imager  900  has a pixel array  905  comprising rows and columns of pixels. Row lines are selectively activated by a row driver  910  in response to row address decoder  920 . A column driver  960  and column address decoder  970  are also included in the imager  900 . The imager  900  is operated by the timing and control circuit  950 , which controls the address decoders  920 ,  970 . The control circuit  950  also controls the row and column driver circuitry  910 ,  960 . 
   A sample and hold circuit  961  associated with the column driver  960  reads a pixel reset signal Vrst and a pixel image signal Vsig for selected pixels. A differential signal (Vrst-Vsig) is amplified by differential programmable gain amplifier (PGA)  962  for each pixel and is digitized by the pipelined analog-to-digital converter  975 . The analog-to-digital converter  975  supplies the digitized pixel signals to an image processor  980 , which forms a digital image. Alternatively, the sample and hold circuit  961  and the analog-to-digital converter  975  may be connected in a shared two channel configuration such as the configuration illustrated in  FIGS. 7   c ,  11   a ,  11   b ,  13   a ,  13   b . Each channel would be responsible for a different set of pixel signals (e.g., one channel can process red and blue pixel signals, while the other channel processes green pixel signals). 
     FIG. 16  shows a system  1000 , a typical processor system modified to include an imaging device  1008  (such as the imaging device  900  illustrated in  FIG. 15 ) implementing an embodiment described herein. The processor system  1000  is exemplary of a system having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and data compression system. 
   System  1000 , for example a camera system, generally comprises a central processing unit (CPU)  1002 , such as a microprocessor, that communicates with an input/output (I/O) device  1006  over a bus  1020 . Imaging device  1008  also communicates with the CPU  1002  over the bus  1020 . The processor-based system  1000  also includes random access memory (RAM) 1004 , and can include removable memory  1014 , such as flash memory, which also communicate with the CPU  1002  over the bus  1020 . The imaging device  1008  may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor. 
   The processes and devices described above illustrate preferred methods and typical devices of many that could be used and produced. The above description and drawings illustrate embodiments, which achieve the objects, features, and advantages described herein. However, it is not intended that these embodiments be strictly limited to the above-described and illustrated embodiments. It should be appreciated that modifications, though presently unforeseeable, of these embodiments that comes within the scope of the following claims can be made.

Technology Classification (CPC): 7