Patent Abstract:
According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; annealing the second insulating film in a second processing chamber; and forming a second conductive layer on the second insulating film.

Full Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-15415, filed on Jan. 24, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a semiconductor device and a method of fabricating the same.  
         [0003]     Conventionally, a NAND flash memory has been developed as a nonvolatile semiconductor memory. A memory cell transistor of this NAND flash memory has a structure in which a floating gate electrode formed on a semiconductor substrate via a tunnel insulating film and a control gate electrode formed on this floating gate electrode via an inter-electrode insulating film are stacked.  
         [0004]     Recently, to decrease the cell size, a method of using an alumina (Al 2 O 3 ) film, instead of the conventional ONO film (a stacked film in which a silicon oxide film, silicon nitride film, and silicon oxide film are stacked), as an inter-electrode insulating film is proposed (reference 1).  
         [0005]     Since the alumina (Al 2 O 3 ) film is a high-dielectric-constant film having a relative dielectric constant higher than that of the ONO film, the area of the inter-electrode insulating film can be reduced. As a consequence, the cell size can be decreased.  
         [0006]     The NAND flash memory stores “1” data in the memory cell transistor by discharging electrons from the floating gate electrode to the semiconductor substrate, and stores “0” data in the memory cell transistor by injecting electrons into the floating gate electrode from the semiconductor substrate.  
         [0007]     Unfortunately, the density of a high-dielectric-constant film is low. Therefore, if a high-dielectric-constant film is used as the inter-electrode insulating film, electrons injected into the floating gate electrode from the semiconductor substrate by applying an electric field of a predetermined level between the control gate electrode and semiconductor substrate penetrate through the inter-electrode insulating film. This increases a leakage current flowing through the control gate electrode.  
         [0008]     To prevent this, therefore, it is necessary to suppress the leakage current by performing a predetermined heating process (annealing) for a high-dielectric-constant film deposited on a conductive layer serving as the floating gate electrode, thereby modifying the high-dielectric-constant film.  
         [0009]     The reference concerning the use of the alumina (Al 2 O 3 ) film as the inter-electrode insulating film is as follows. 
    Reference 1: Symposium on VLSI Technology Digest of Technical Papers, p. 117, 1997    
 
       SUMARY OF THE INVENTION  
       [0000]    
       
         
           
              According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:  
           
         
       
     
         [0012]     forming a first insulating film on a semiconductor substrate;  
         [0013]     forming a first conductive layer on the first insulating film;  
         [0014]     forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside;  
         [0015]     performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside;  
         [0016]     annealing the second insulating film in a second processing chamber; and  
         [0017]     forming a second conductive layer on the second insulating film.  
         [0018]     According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:  
         [0019]     loading a semiconductor substrate into a first processing chamber isolated from an outside, and forming an insulating film on a surface of the semiconductor substrate in the first processing chamber;  
         [0020]     performing a modification process on the insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside;  
         [0021]     annealing the insulating film in a second processing chamber; and  
         [0022]     forming a conductive layer on the insulating film. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIGS. 1A and 1B  are longitudinal sectional views each showing the sectional structure of elements in one step of a method of fabricating a NAND flash memory according to the first embodiment of the present invention;  
         [0024]      FIGS. 2A and 2B  are longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the NAND flash memory;  
         [0025]      FIGS. 3A and 3B  are longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the NAND flash memory;  
         [0026]      FIGS. 4A and 4B  are longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the NAND flash memory;  
         [0027]      FIGS. 5A and 5B  are longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the NAND flash memory;  
         [0028]      FIGS. 6A and 6B  are longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the NAND flash memory;  
         [0029]      FIG. 7  is a block diagram showing the arrangement of a batch type deposition/modification apparatus and annealing apparatus;  
         [0030]      FIGS. 8A and 8B  are longitudinal sectional views showing the sectional structure of a memory cell transistor according to the first embodiment of the present invention and that of a memory cell transistor of a comparative example;  
         [0031]      FIG. 9  is a longitudinal sectional view showing the sectional structure of a floating gate electrode and vicinity in the memory cell transistor of the comparative example;  
         [0032]      FIG. 10  is a longitudinal sectional view showing the sectional structure of the corner and vicinity at the upper end of the floating gate electrode in the memory cell transistor of the comparative example;  
         [0033]      FIG. 11  is a longitudinal sectional view showing the sectional structure of the floating gate electrode in the memory cell transistor;  
         [0034]      FIG. 12  is a longitudinal sectional view showing the sectional structure of the interface and vicinity between the floating gate electrode and an inter-electrode insulating film in the memory cell transistor of the comparative example;  
         [0035]      FIG. 13  is a block diagram showing the arrangement of a single-wafer deposition/modification apparatus and annealing apparatus;  
         [0036]      FIG. 14  is a longitudinal sectional view showing the sectional structure of elements in a predetermined step of a method of fabricating a MOSFET according to the second embodiment of the present invention;  
         [0037]      FIG. 15  is longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the MOSFET;  
         [0038]      FIG. 16  is longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the MOSFET;  
         [0039]      FIG. 17  is longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the MOSFET;  
         [0040]      FIG. 18  is longitudinal sectional views each showing the sectional structure of elements in one step of the method of fabricating the MOSFET; and  
         [0041]      FIGS. 19A and 19B  are longitudinal sectional views showing the sectional structure of the MOSFET according to the second embodiment of the present invention and that of a MOSFET of a comparative example.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0042]     Embodiments of the present invention will be described below with reference to the accompanying drawings.  
       (1) First Embodiment  
       [0043]      FIGS. 1A  to  6 B show a method of fabricating a memory cell transistor of a NAND flash memory according to the first embodiment of the present invention. Of  FIGS. 1A  to  5 B, each of  FIGS. 1A, 2A ,  3 A,  4 A, and  5 A is a longitudinal sectional view, cut along a bit line, of elements in a predetermined step, and each of  FIGS. 1B, 2B ,  3 B,  4 B, and  5 B is a longitudinal sectional view, cut along a word line, of elements in a predetermined step.  
         [0044]     First, as shown in  FIGS. 1A and 1B , a silicon oxynitride (SiON) film  20  about 10 nm thick serving as a tunnel insulating film is formed by thermal oxidation and thermal nitriding on a semiconductor substrate  10  into which a predetermined impurity is doped. After that, a phosphorous (P)-doped polysilicon layer  30  serving as a floating gate electrode is deposited by CVD (Chemical Vapor Deposition), and a mask material  40  is formed by coating. Note that any of various impurities such as arsenic (As) may also be doped, in place of phosphorus (P), into the polysilicon layer  30 .  
         [0045]     The mask material  40 , polysilicon layer  30 , and silicon oxynitride (SiON) film  20  are sequentially patterned by lithography and RIE (Reactive Ion Etching). In addition, the mask material  40  is used as a mask to etch the semiconductor substrate  10 , thereby forming an element isolation trench  50  about 100 nm deep from the surface of the semiconductor substrate  10 .  
         [0046]     As shown in  FIGS. 2A and 2B , a silicon oxide film  60  is deposited on all the surfaces of the semiconductor substrate  10  and mask material  40  so as to fill the element isolation trench  50 . After that, the silicon oxide film  60  is planarized by polishing its surface by CMP (Chemical Mechanical Polishing), thereby forming a silicon oxide film  60  as an element isolation insulating film.  
         [0047]     As shown in  FIGS. 3A and 3B , a predetermined amount of the surface portion of the silicon oxide film  60  is etched to be removed by using a dilute hydrofluoric acid solution to expose the side surfaces of the polysilicon layer  30  by about 50 nm. The exposed mask material  40  is then selectively removed.  
         [0048]     In addition, dilute hydrofluoric acid is used to remove a natural oxide film formed on the surface of the polysilicon layer  30 . After that, the semiconductor substrate  10  is loaded into a batch type deposition/modification apparatus  65  shown in  FIG. 7  which is a processing chamber having a single processing vessel and is called a furnace. In the deposition/modification apparatus  65 , an alumina (Al 2 O 3 ) film  70  serving as an inter-electrode insulating film is deposited on all the surfaces of the silicon oxide film  60  and polysilicon layer  30  at a temperature of 400° C. Note that the deposition/modification apparatus  65  has an exhausting mechanism and gas supply source (neither is shown), and can form a desired ambient by using them.  
         [0049]     In this embodiment, the alumina (Al 2 O 3 ) film  70  is deposited as an inter-electrode insulating film. However, it is also possible to deposit any of various high-dielectric-constant films having a relative dielectric constant of 4 or more. Examples are oxide films such as hafnia (HfO 2 ), zirconia (ZrO 2 ), hafnium silicate (HfSiO), and zirconium silicate (ZrSiO), and oxide films obtained by doping an impurity into these oxide films.  
         [0050]     When the alumina (Al 2 O 3 ) film  70  which is a high-dielectric-constant film is used as an inter-electrode insulating film as in this embodiment, it must be densified by high-temperature annealing in order to suppress a leakage current in it.  
         [0051]     Unfortunately, the deposition/modification apparatus  65  in which the alumina (Al 2 O 3 ) film  70  is deposited cannot perform this high-temperature annealing. Therefore, it is necessary to once remove the semiconductor substrate  10  from the deposition/modification apparatus  65 , load the semiconductor substrate  10  into an annealing apparatus  75  shown in  FIG. 7  which can perform high-temperature annealing, and densify the alumina (Al 2 O 3 ) film  70  by high-temperature annealing in the annealing apparatus  75 .  
         [0052]     If, however, the semiconductor substrate  10  is exposed to the atmosphere after being removed from the deposition/modification apparatus  65  and before being loaded into the annealing apparatus  75 , the alumina (Al 2 O 3 ) film  70  absorbs water.  
         [0053]     If the alumina (Al 2 O 3 ) film  70  which has absorbed water is annealed, a low-dielectric-constant silicon oxide film is formed in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . This poses the problem that the effective relative dielectric constant of the alumina (Al 2 O 3 ) film  70  lowers.  
         [0054]     In this embodiment, therefore, in the deposition/modification apparatus  65  in which the alumina (Al 2 O 3 ) film  70  is deposited, the alumina (Al 2 O 3 ) film  70  is annealed in a nitrogen ambient at a temperature of, e.g., 800° C. for 60 min, thereby modifying, e.g., densifying the alumina (Al 2 O 3 ) film  70  to such an extent that it does not absorb water when the semiconductor substrate  10  is exposed to the atmosphere.  
         [0055]     Note that the temperature of this annealing need only be, e.g., 600° C. to 900° C. which is higher than the temperature when the alumina (Al 2 O 3 ) film  70  is deposited. However, the temperature is desirably as high as possible because the densifying effect improves. Annealing may also be performed in an oxidizing ambient, and the annealing time may also be about 30 min.  
         [0056]     After that, the semiconductor substrate  10  is removed from the deposition/modification apparatus  65 , and loaded into the annealing apparatus  75  shown in  FIG. 7 . Although the semiconductor substrate  10  is exposed to the atmosphere during this transfer, it is possible to suppress the alumina (Al 2 O 3 ) film  70  from absorbing water, i.e., suppress moisture absorption by the alumina (Al 2 O 3 ) film  70 .  
         [0057]     In the annealing apparatus  75 , the alumina (Al 2 O 3 ) film  70  is annealed in an oxidizing ambient at, e.g., about 1,035° C. which is higher than the temperature of annealing for suppressing moisture absorption by the alumina (Al 2 O 3 ) film  70 , without performing any liquid chemical treatment for avoiding moisture absorption by the alumina (Al 2 O 3 ) film  70 , thereby densifying the alumina (Al 2 O 3 ) film  70  to such an extent that the leakage current in it can be suppressed. After that, the semiconductor substrate  10  is removed from the annealing apparatus  75 .  
         [0058]     Note that if a high-dielectric-constant film is deposited as a tunnel insulating film, the densifying process described above may also be applied to this tunnel insulating film.  
         [0059]     As shown in  FIGS. 4A and 4B , CVD is performed to deposit a conductive layer  80  about 100 nm thick which has a two-layered structure including, e.g., a polysilicon layer and tungsten (W) silicide layer, and which serves as a control gate electrode later, and to deposit a mask material  90 .  
         [0060]     The mask material  90 , conductive layer  80 , alumina (Al 2 O 3 ) film  70 , polysilicon layer  30 , and silicon oxynitride (SiON) film  20  are sequentially patterned by lithography and RIE, thereby forming a slit  100 . In this manner, a floating gate electrode made of the polysilicon layer  30  and a control gate electrode made of the conductive layer  80  are formed.  
         [0061]     As shown in  FIGS. 5A and 5B , a silicon oxide film  100  serving as an electrode sidewall insulating film is formed by thermal oxidation on the exposed surfaces of the semiconductor substrate  10 , silicon oxynitride (SiON) film  20 , polysilicon layer  30 , alumina (Al 2 O 3 ) film  70 , conductive layer  80 , and mask material  90 . After that, a source region  110 A and drain region  110 B are formed by ion implantation, and an interlayer dielectric film  120  is formed on the entire surface of the silicon oxide film  100  by CVD. Finally, interconnecting layers (not shown) and the like are formed to fabricate the memory cell transistor of the NAND flash memory.  
         [0062]      FIG. 6A  shows the longitudinal section when a NAND flash memory  200  in which memory cell transistors MC fabricated by the above method are arranged in a matrix is cut along a bit line BL.  FIG. 6B  shows the circuit diagram, which corresponds to the longitudinal section shown in  FIG. 6A , of the NAND flash memory  200 .  
         [0063]     In the NAND flash memory  200  as shown in  FIGS. 6A and 6B , the source regions  110 A and drain regions  110 B of a plurality of memory cell transistors MC are connected in series between two selection transistors (not shown), one of these selection transistors is connected to the bit line BL, and the other is connected to a source line (not shown). Also, a word line WL is connected to the control gate electrode made of the conductive layer  80  of each memory cell transistor MC.  
         [0064]     In this embodiment, the NAND flash memory  200  is fabricated as a flash memory. However, it is also possible to fabricate any of various flash memories having a structure in which a floating gate electrode and control gate electrode, e.g., NOR and AND are stacked. Furthermore, a structure including three or more stacked layers each made up of an insulating film and gate electrode may also be formed.  
         [0065]      FIG. 8A  shows the structure of the memory cell transistor MC of the NAND flash memory  200  according to this embodiment.  FIG. 8B  shows the structure of a memory cell transistor MC 10  as a comparative example. In the memory cell transistor MC 10 , an alumina (Al 2 O 3 ) film  70  is not densified after being deposited, but densified after being exposed to the atmosphere, thereby forming a low-dielectric-constant silicon oxide film  210  in the interface between a floating gate electrode made of a polysilicon layer  30  and an inter-electrode insulating film made of the alumina (Al 2 O 3 ) film  70 .  
         [0066]     The memory cell transistor MC 10  of the comparative example has the problem that the effective relative dielectric constant of the inter-electrode insulating film lowers, since the low-dielectric-constant silicon oxide film  210  is formed in the interface between the floating gate electrode made of the polysilicon layer  30  and the inter-electrode insulating film made of the alumina (Al 2 O 3 ) film  70 .  
         [0067]     By contrast, in this embodiment, in the deposition/modification apparatus  65 , the alumina (Al 2 O 3 ) film  70  is densified, after being deposited and before being exposed to the atmosphere, to such an extent that moisture absorption by the alumina (Al 2 O 3 ) film  70  can be suppressed. Accordingly, even when the alumina (Al 2 O 3 ) film  70  is densified in the annealing apparatus  75  to such an extent that the leakage current in the alumina (Al 2 O 3 ) film  70  can be suppressed, it is possible to prevent the formation of the low-dielectric-constant silicon oxide film  210  in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . This makes it possible to suppress the lowering of the effective relative dielectric constant of the alumina (Al 2 O 3 ) film  70  as a high-dielectric-constant film.  
         [0068]     Also, as shown in  FIG. 8B , if the low-dielectric-constant silicon oxide film  210  is formed in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70  as in the memory cell transistor MC 10  of the comparative example, the existence of the silicon oxide film  210  increases the leakage current (an arrow A 10  in  FIG. 8B ) in the alumina (Al 2 O 3 ) film  70  as an inter-electrode insulating film.  
         [0069]     That is, when an electric field of a predetermined level is applied between a conductive layer  80  as the control gate electrode and a semiconductor substrate  10  to inject electrons (an arrow A 20  in  FIG. 8B ) from the semiconductor substrate  10  into the polysilicon layer  30  as the floating gate electrode, these electrons injected into the polysilicon layer  30  penetrate through the silicon oxide film  210  and alumina (Al 2 O 3 ) film  70 , and increase the leakage current (the arrow A 10  in  FIG. 8B ) flowing through the conductive layer  80 .  
         [0070]     Conversely, in this embodiment as shown in  FIG. 8A , it is possible to prevent the formation of the low-dielectric-constant silicon oxide film  210  in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . Therefore, even when an electric field of a predetermined level is applied between the conductive layer  80  and semiconductor substrate  10  to inject electrons (an arrow A 30  in  FIG. 8A ) from the semiconductor substrate  10  into the polysilicon layer  30 , a leakage current in the alumina (Al 2 O 3 ) film  70  can be suppressed.  
         [0071]     Also, as shown in  FIG. 9 , in the memory cell transistor MC 10  of the comparative example, the silicon oxide film  210  is formed into an inverse U-shape along the interface between the polysilicon layer  30  as the floating gate electrode and the alumina (Al 2 O 3 ) film  70  as the inter-electrode insulating film.  
         [0072]     When a length W in the direction of the word line WL of the surface of the polysilicon layer  30  shortens by the film thickness of the silicon oxide film  210 , the surface area of the polysilicon layer  30  reduces. As a consequence, the capacitance of the capacitor between the conductive layer  80  and polysilicon layer  30  decreases.  
         [0073]     This causes the necessity of the higher voltage applied to the conductive layer  80  as the control gate electrode to inject electrons from the semiconductor substrate  10  into polysilicon layer  30  as the floating gate electrode, and then the larger electric filed is applied between the conductive layer  80  and polysilicon layer  30 .  
         [0074]     Recently, the dimension (i.e., the channel width) W in the direction of the word line WL of the surface of the polysilicon layer  30  is set to 100 nm or less, and desirably, 50 nm or less, by the decrease in cell size.  
         [0075]     Accordingly, when the silicon oxide film  210  is formed along the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 , the influence the silicon oxide film  210  has on the surface area of the polysilicon layer  30  increases, so the memory cell transistor characteristics largely change.  
         [0076]     On the contrary, in this embodiment, it is possible to prevent the formation of the silicon oxide film  210  along the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . This suppresses the change in memory cell transistor characteristics.  
         [0077]     Also, as shown in  FIG. 10 , when the silicon oxide film  210  is formed into an inverse U-shape along the interface between the polysilicon layer  30  as the floating gate electrode and the alumina (Al 2 O 3 ) film  70  as the inter-electrode insulating film as in the memory cell transistor MC 10  of the comparative example, a corner  30 A at the upper end of the polysilicon layer  30  is pointed because the oxidation rate is low in this portion.  
         [0078]     When, therefore, a high electric field is applied between the conductive layer  80  as the control gate electrode and the polysilicon layer  30  as the floating gate electrode, field concentration occurs in the corner  30 A at the upper end of the polysilicon layer  30  because the corner  30 A is pointed. This allows easy occurrence of insulation breakdown.  
         [0079]     By contrast, in this embodiment, it is possible to prevent the formation of the silicon oxide film  210  along the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . This prevents the occurrence of insulating breakdown caused by field concentration in the corner  30 A at the upper end of the polysilicon layer  30 .  
         [0080]     Furthermore, to prevent the formation of a depletion layer when an electric field is applied, the polysilicon layer  30  serving as the floating gate electrode is formed such that the impurity concentration of, e.g., phosphorus (P) doped is as high as, e.g., 1.0×10 20 /cm 3  or more.  
         [0081]     In this case, if the silicon oxide film  210  having a high impurity concentration is formed in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70  as in the memory cell transistor MC 10  of the comparative example, the leakage current in the alumina (Al 2 O 3 ) film  70  as an electrode insulating film increases compared to the case in which a silicon oxide film having a low impurity concentration is formed.  
         [0082]     In contrast to this, in this embodiment, it is possible to prevent the formation of the silicon oxide film  210  having a high impurity concentration in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . This suppresses the increase of the leakage current in the alumina (Al 2 O 3 ) film  70  as an electrode insulating film.  
         [0083]     Also, as shown in  FIG. 11 , the polysilicon layer  30  as the floating gate electrode is made of polysilicon having a plurality of single-crystal grains  30 B. Therefore, as shown in  FIG. 12 , when the silicon oxide film  210  is formed in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70  as in the memory cell transistor MC 10  of the comparative example, oxygen diffuses along a grain boundary  30 C. Consequently, a projecting portion  210 A which sharply projects along the grain boundary  30 C is formed on the silicon oxide film  210 .  
         [0084]     Accordingly, when an electric field is applied between the conductive layer  80  as the control gate electrode and the polysilicon layer  30  as the floating gate electrode, field concentration occurs in the projecting portion  210 A of the silicon oxide film  210 , and this increases the leakage current.  
         [0085]     On the contrary, in this embodiment, it is possible to prevent the formation of the silicon oxide film  210  in the interface between the polysilicon layer  30  and alumina (Al 2 O 3 ) film  70 . This suppresses the increase of the leakage current caused by field concentration near the grain boundary  30 C of the single-crystal grains  30 B.  
         [0086]     Note that the first embodiment described above is merely an example, and hence does not limit the present invention. For example, in the batch type deposition/modification apparatus  65  called a furnace, the alumina (Al 2 O 3 ) film  70  is deposited, and annealing is performed to suppress moisture absorption by the alumina (Al 2 O 3 ) film  70 . However, it is also possible to perform deposition of the alumina (Al 2 O 3 ) film  70  and annealing for suppressing moisture absorption in a single-wafer type deposition/modification apparatus  220  called a cluster chamber shown in  FIG. 13 .  
         [0087]     A transfer chamber  230  is placed near the central portion of the deposition/modification apparatus  220  as a processing chamber called a cluster chamber. A loading chamber  240 , an unloading chamber  250 , a deposition chamber  260  as a processing vessel, and an annealing chamber  270  as another processing vessel are arranged around the transfer chamber  230 .  
         [0088]     A transfer mechanism  280  which is an arm or the like is placed near the central portion of the transfer chamber  230 , and transfers the semiconductor substrate  10  between the chambers  240  to  270 . Also, the transfer chamber  230  has an exhausting mechanism and gas supply source (neither is shown), and a desired ambient is formed in the transfer chamber  230  by using them. In this manner, the semiconductor substrate  10  can be transferred to a desired chamber without being exposed to the atmosphere.  
         [0089]     That is, the transfer mechanism  280  of the transfer chamber  230  transfers the semiconductor substrate  10  loaded from the loading chamber  240  to the deposition chamber  260 , and an alumina (Al 2 O 3 ) film  70  is deposited in the deposition chamber  260 . After that, the semiconductor substrate  10  is transferred from the deposition chamber  260  to the annealing chamber  270  via the transfer chamber  230 . In the annealing chamber  270 , the alumina (Al 2 O 3 ) film  70  is densified by annealing to such an extent that moisture absorption by the alumina (Al 2 O 3 ) film  70  can be suppressed.  
         [0090]     Then, the semiconductor substrate  10  is transferred from the annealing chamber  270  to the unloading chamber  250  via the transfer chamber  230 , and thereby removed from the deposition/modification apparatus  220 . The semiconductor substrate  10  is loaded into an annealing apparatus  290  shown in  FIG. 13 . Although the semiconductor substrate  10  is exposed to the atmosphere during this transfer as in the above first embodiment, moisture absorption by the alumina (Al 2 O 3 ) film  70  can be suppressed.  
         [0091]     In the annealing apparatus  290 , the alumina (Al 2 O 3 ) film  70  is densified by annealing at a high temperature to such an extent that the leakage current in the alumina (Al 2 O 3 ) film  70  can be suppressed.  
       (2) Second Embodiment  
       [0092]     FIGS.  14  to  18  show a method of fabricating a MOSFET according to the second embodiment of the present invention. First, as shown in  FIG. 14 , element isolation insulating films  310 A and  310 B are formed on a semiconductor substrate  300 , and a natural oxide film formed on the semiconductor substrate  300  is removed by cleaning using dilute hydrofluoric acid.  
         [0093]     As shown in  FIG. 15 , the semiconductor substrate  300  is loaded into a batch type deposition/modification apparatus  65  shown in  FIG. 7  which is a processing chamber having a single processing vessel and is called a furnace. In the deposition/modification apparatus  65 , a hafnia (HfO 2 ) film  320  serving as a gate insulting film is deposited on the surface of the semiconductor substrate  300  at a temperature of 400° C. Note that the deposition/modification apparatus  65  has an exhausting mechanism and gas supply source (neither is shown), and can form a desired ambient by using them.  
         [0094]     In this embodiment, the hafnia (HfO 2 ) film  320  is deposited as a gate insulating film. However, it is also possible to deposit any of various high-dielectric-constant films having a relative dielectric constant of 4 or more. Examples are oxide films such as alumina (Al 2 O 3 ), zirconia (ZrO 2 ), hafnium silicate (HfSiO), and zirconium silicate (ZrSiO), and oxide films obtained by doping an impurity into these oxide films.  
         [0095]     As in the first embodiment, in the deposition/modification apparatus  65  in which the hafnia (HfO 2 ) film  320  is deposited, the hafnia (HfO 2 ) film  320  is densified by annealing in a nitrogen ambient at a temperature of, e.g., 800° C., to such an extent that the hafnia (HfO 2 ) film  320  does not absorb water when the semiconductor substrate  300  is exposed to the atmosphere.  
         [0096]     Note that, as in the first embodiment, the temperature of this annealing need only be, e.g., 600° C. to 900° C. which is higher than the temperature when the hafnia (HfO 2 ) film  320  is deposited. However, the temperature is desirably as high as possible because the densifying effect increases. Annealing may also be performed in an oxidizing ambient.  
         [0097]     After that, the semiconductor substrate  300  is removed from the deposition/modification apparatus  65 , and loaded into an annealing apparatus  75  shown in  FIG. 7 . Although the semiconductor substrate  300  is exposed to the atmosphere during this transfer, it is possible to suppress the hafnia (HfO 2 ) film  320  from absorbing water, i.e., suppress moisture absorption by the hafnia (HfO 2 ) film  320 .  
         [0098]     In the annealing apparatus  75 , the hafnia (HfO 2 ) film  320  is annealed in an oxidizing ambient at, e.g., about 1,000° C. which is higher than the temperature of annealing for suppressing moisture absorption by the hafnia (HfO 2 ) film  320 , without performing any liquid chemical treatment, thereby densifying the hafnia (HfO 2 ) film  320  to such an extent that the leakage current in the hafnia (HfO 2 ) film  320  can be suppressed. After that, the semiconductor substrate  300  is removed from the annealing apparatus  75 .  
         [0099]     As shown in  FIG. 16 , CVD is performed to deposit a polysilicon layer  330  serving as a gate electrode. As shown in  FIG. 17 , the polysilicon layer  330  and hafnia (HfO 2 ) film  320  are sequentially patterned by lithography and RIE, thereby forming a gate insulating film made of the hafnia (HfO 2 ) film  320 , and a gate electrode made of the polysilicon layer  330 . As shown in  FIG. 18 , a source region  340 A and drain region  340 B are formed by ion implantation. In this manner, a MOSFET  400  is fabricated.  
         [0100]      FIG. 19A  shows the structure of the MOSFET  400  according to this embodiment.  FIG. 19B  shows the structure of a MOSFET  500  as a comparative example. In the MOSFET  500 , a hafnia (HfO 2 ) film  320  is not densified after being deposited, but densified after being exposed to the atmosphere, thereby forming a low-dielectric-constant silicon oxide film  510  in the interface between a gate insulating film made of the hafnia (HfO 2 ) film  320  and a semiconductor substrate  300 .  
         [0101]     The MOSFET  500  of the comparative example has the problem that the effective relative dielectric constant of the gate insulating film lowers, since the low-dielectric-constant silicon oxide film  510  is formed in the interface between the gate insulating film made of the hafnia (HfO 2 ) film  320  and the semiconductor substrate  300 .  
         [0102]     By contrast, in this embodiment, as in the first embodiment, the hafnia (HfO 2 ) film  320  is densified in the deposition/modification apparatus  65 , after being deposited and before being exposed to the atmosphere, to such an extent that moisture absorption by the hafnia (HfO 2 ) film  320  can be suppressed. Accordingly, even when the hafnia (HfO 2 ) film  320  is densified in the annealing apparatus  75  to such an extent that the leakage current in the hafnia (HfO 2 ) film  320  can be suppressed, it is possible to prevent the formation of the low-dielectric-constant silicon oxide film  510  in the interface between the hafnia (HfO 2 ) film  320  and semiconductor substrate  300 . This makes it possible to suppress the lowering of the effective relative dielectric constant of the hafnia (HfO 2 ) film  320  as a high-dielectric-constant film.  
         [0103]     Also, as shown in  FIG. 19B , if the low-dielectric-constant silicon oxide film  510  is formed in the interface between the hafnia (HfO 2 ) film  320  and semiconductor substrate  300  as in the MOSFET  500  of the comparative example, the existence of the silicon oxide film  510  increases the leakage current (an arrow A 100  in  FIG. 19B ) in the hafnia (HfO 2 ) film  320  as a gate insulating film.  
         [0104]     That is, when an electric field of a predetermined level is applied between the polysilicon layer  330  as the gate electrode and the semiconductor substrate  300  to draw electrons toward the surface of the semiconductor substrate  300 , these drawn electrons penetrate through the silicon oxide film  510  and hafnia (HfO 2 ) film  320 , and increase the leakage current (the arrow A 100  in  FIG. 19B ) flowing through the polysilicon layer  330 .  
         [0105]     Conversely, in this embodiment as shown in  FIG. 19A , it is possible to prevent the formation of the low-dielectric-constant silicon oxide film  510  in the interface between the hafnia (HfO 2 ) film  320  and semiconductor substrate  300 . Therefore, the leakage current in the hafnia (HfO 2 ) film  320  can be suppressed.  
         [0106]     Note that the second embodiment described above is merely an example, and hence does not limit the present invention. For example, in the batch type deposition/modification apparatus  65  called a furnace, the hafnia (HfO 2 ) film  320  is deposited, and annealing is performed to suppress moisture absorption by the hafnia (HfO 2 ) film  320 . However, as in the other embodiment of the first embodiment, it is also possible to perform deposition of the hafnia (HfO 2 ) film  320  and annealing for suppressing moisture absorption in a single-wafer type deposition/modification apparatus  220  called a cluster chamber shown in  FIG. 13 .  
         [0107]     In this case, as in the other embodiment of the first embodiment, the semiconductor substrate  300  is removed from the deposition/modification apparatus  220  which is a processing chamber having a plurality of processing vessels, and loaded into an annealing apparatus  290  shown in  FIG. 13 . Although the semiconductor substrate  300  is exposed to the atmosphere during this transfer, moisture absorption by the hafnia (HfO 2 ) film  320  can be suppressed.  
         [0108]     In the annealing apparatus  290 , the hafnia (HfO 2 ) film  320  is densified by annealing at a high temperature to such an extent that the leakage current in the hafnia (HfO 2 ) film  320  can be suppressed.  
       (3) Other Embodiments  
       [0109]     Note that the first and second embodiments described above are merely examples, and hence do not limit the present invention. For example, oxygen radical processing may also be performed at a temperature of 400° C. as the modification process of suppressing moisture absorption by the alumina (Al 2 O 3 ) film  70  and hafnia (HfO 2 ) film  320 . In this case, although the temperature need only range from room temperature to 900° C., the temperature is desirably as high as possible because the modification effect improves.  
         [0110]     The oxygen radical is, e.g., neutral atomic oxygen or excited molecular oxygen, and is generated by changing a gas mixture, which is obtained by diluting oxygen gas to 1% to 100% with argon gas, into plasma by microwaves. The alumina (Al 2 O 3 ) film  70  and hafnia (HfO 2 ) film  320  are modified by oxygen radical processing which causes the alumina (Al 2 O 3 ) film  70  and hafnia (HfO 2 ) film  320  to absorb this oxygen radical.  
         [0111]     Note that this oxygen radical processing may also be performed in an ambient in which the oxygen radical and oxygen ion are mixed. It is also possible to dilute oxygen gas with any of various diluent gases such as helium, neon, krypton, and xenon. Furthermore, the ratio of oxygen gas may also be increased by reducing the amount diluted by the diluent gas, or the ratio of oxygen gas may also be set at  100 % without any dilution by the diluent gas.  
         [0112]     Although hydrogen gas may also be added to the gas mixture, the addition amount is preferably as low as 1% to 10%. The gas mixture may also be changed into plasma by a high frequency, NO gas, or N 2 O gas, instead of microwaves. The oxygen radical may also be generated by the reaction of oxygen gas with hydrogen gas.  
         [0113]     Nitrogen radical processing may also be performed by generating nitrogen radical by changing a gas mixture of nitrogen gas and a diluent gas or 100% nitrogen gas into plasma by the same method as for generating the oxygen radical. It is also possible to simultaneously perform the oxygen radical processing and nitrogen radical processing by simultaneously generating the oxygen radical and nitrogen radical by changing a gas mixture of oxygen gas and nitrogen gas into plasma.  
         [0114]     Furthermore, as the modification process of suppressing moisture absorption by the alumina (Al 2 O 3 ) film  70  and hafnia (HfO 2 ) film  320 , it is also possible to perform an ultraviolet radiation process of irradiating the alumina (Al 2 O 3 ) film  70  and hafnia (HfO 2 ) film  320  with ultraviolet light in a nitrogen ambient at room temperature.  
         [0115]     Note that a light radiation process of radiating any of various types of light such as visible light, infrared light, and white light may also be performed.  
         [0116]     In this case, a point light source is placed above the semiconductor substrates  10  and  300 , and the semiconductor substrates  10  and  300  are irradiated, by uniform intensity, with light emitted from this point light source by using a light reflecting plate. It is also possible to arrange a plurality of light sources over the semiconductor substrates  10  and  300 , and irradiate the semiconductor substrates  10  and  300 , by uniform intensity, with light emitted from these light sources.  
         [0117]     Although the temperature need only range from room temperature to 900° C., the temperature is desirably as high as possible because the modification effect improves. The light radiation process may also be performed in an oxygen ambient or in a vacuum, instead of a nitrogen ambient.  
         [0118]     As has been explained above, the semiconductor device fabrication method of each of the above embodiments can improve the reliability of the semiconductor device by suppressing the leakage current.

Technology Classification (CPC): 7