Patent Abstract:
A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefit of Taiwan application serial no. 96138177, filed on Oct. 12, 2007. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. More particularly, the present invention relates to a power MOSFET array structure located under a gate pad. 
         [0004]    2. Description of Related Art 
         [0005]    Power MOSFET can be used as high voltage device with current applicable operating voltage of up to higher than 4500 volts, and is mainly used as switching apparatus. Commonly, the MOSFET is of a planar structure, and each end point in the transistor is only several micrometers away from a chip surface. All the power devices are of a vertical structure, such that the devices can bear high voltage and high current at the same time. The bearable voltage of the power MOSFET depends on doping concentration and thickness of n-type epitaxy layer, and the current capable of passing through the power MOSFET depends on channel width of the device. The wider the channel is, the more current can be accommodated. Under fixed channel size, the current is directly proportional to channel density. Generally speaking, in the conventional art, the channel density is increased by means of reducing distance between basic devices. When volume of the transistor is reduced, not only the space is saved, but also the cost is reduced. Therefore, the industry urgently needs a method of reducing the volume of the power MOSFET array. 
         [0006]    The basic devices of the MOSFET array include a substrate, an epitaxy layer, a source region, gates, a source pad, and a gate pad etc. In the conventional art, the source pad is disposed above the power MOSFET array and is connected to the source region, and the gate pad is disposed beside the array and is connected to the gate. A space exists under the gate pad, and is useless. Therefore, the industry urgently needs a method of well utilizing the space under the gate pad, thereby reducing the volume of the array and increasing the device integration. 
       SUMMARY OF THE INVENTION 
       [0007]    Accordingly, the present invention is directed to provide a power MOSFET array structure, which is capable of disposing the power MOSFET array under the gate pad, so as to well utilize the space under the gate pad, and to increase device integration. 
         [0008]    The present invention is further directed to provide a power MOSFET array pair structure, which is capable of connecting the power MOSFET array disposed under the gate pad and the conventional power MOSFET array disposed under the source pad, so as to share the same gate pad and source pad, thereby saving the volume of the array pair, and increasing the device integration. 
         [0009]    The present invention provides a power MOSFET array structure. In the structure, a gate pad is disposed above the power MOSFET array. The power MOSFET array includes a substrate, an epitaxy layer, a plurality of gates, a source region, and a gate pad. The substrate serves as a drain, and the substrate has a device region. The epitaxy layer is disposed on the substrate, the plurality of gates is disposed on the epitaxy layer in the device region, and the gates are mutually electrically insulated. The source region is disposed on the epitaxy layer between the gates, in which the source region and the gates form the power MOSFET array. The gate pad is disposed above the power MOSFET array, and the gate pad is electrically connected to the gates. 
         [0010]    The present invention provides a power MOSFET array pair structure. Two power MOSFET arrays share the same gate pad and source pad through the connection of the circuit connection region. The power MOSFET array pair includes a substrate, an epitaxy layer, source regions, a gate region, a gate pad, and a source pad. The substrate has a first device region, a second device region, and a circuit connection region, a portion of the substrate in the first device region serves as a first drain, and a portion of the substrate in the second device region serves as a second drain. The epitaxy layer is disposed on the substrate. A plurality of first gates is disposed on the epitaxy layer of the first device region, in which the first gates are mutually electrically insulated. A first source region is disposed on the epitaxy layer between the first gates, and the first source region and the first gates form a first power MOSFET array. A plurality of second source regions is disposed on the epitaxy layer, in which the second source regions are mutually electrically insulated. A second gate is disposed on the epitaxy layer between the second source regions, and the second gate and the second source regions form a second power MOSFET array. The gate pad is disposed right above the first power MOSFET array, the gate pad is electrically connected to the first gates, and is electrically connected to the second gate in the second device region through the circuit connection region. The source pad is disposed right above the second power MOSFET array, in which the source pad is electrically connected to the second source regions, and is electrically connected to the first source in the first device region through the circuit connection region. 
         [0011]    In the present invention, the MOSFET array is disposed under the gate pad, so as to well utilize the originally idle space under the gate pad and to increase the device integration. By adopting the circuit connection region, the MOSFET array under the gate pad and the conventional MOSFET array disposed under the source pad form an array pair, so as to share the same gate pad and source pad, thereby reducing the volume of the array pair, such that the application scope of the power MOSFET array is broader. 
         [0012]    In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. 
         [0013]    It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
           [0015]      FIG. 1A  is a top view of the power MOSFET array according to an embodiment of the present invention. 
           [0016]      FIG. 1B  is a simplified sectional view of  FIG. 1A  along line I-I′. 
           [0017]      FIG. 2A  is a top view of the power MOSFET array pair according to an embodiment of the present invention. 
           [0018]      FIG. 2B  is a simplified sectional view of  FIG. 2A  along line II-II′. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0019]      FIG. 1A  is a top view of the power MOSFET array according to an embodiment of the present invention.  FIG. 1B  is a simplified sectional view of  FIG. 1A  along line I-I′. 
         [0020]    Referring to  FIGS. 1A and 1B , the power MOSFET array of the present invention includes a substrate  100 , an epitaxy layer  102 , a plurality of gates  104 , a plurality of source regions  106 , a gate pad  110 , and a source pad  120 . 
         [0021]    The substrate  100  has a device region  100   a , a circuit connection region  100   b , and a source pad region  100   c . The epitaxy layer  102  is disposed above the substrate  100 . In the power MOSFET array, the substrate  100  serves as a drain. Further, for example for an N type power MOSFET, the conductive type of the substrate  100  is, for example, N type, and the conductive type of the epitaxy layer  102  is P type. 
         [0022]    Referring to  FIGS. 1A and 1B , the plurality of gates  104  is disposed on the epitaxy layer  102  in the device region  100   a . The gates  104  disposed on the epitaxy layer  102  are mutually electrically insulated. A source region  106  is disposed on the epitaxy layer  102  between the gates  104 , and a portion of the source region  106  extends to the circuit connection region  100   b . The source region  106  and the gates  104  together form a power MOSFET array  114  (as shown in  FIG. 1A ). For example, for the N type power MOSFET, when the conductive type of the substrate  100  is, for example N type, and the conductive type of the epitaxy layer  102  is P type, the conductive type of the source region  106  is N type. 
         [0023]    An insulation layer  108  is further disposed above the substrate  100 , the insulation layer  108  covers the device region  100   a  and the circuit connection region  100   b , and the insulation layer  108  has a plurality of gate contact openings  112  in the device region  100   a , for respectively exposing the gates  104 . At the same time, the insulation layer  108  has a plurality of source contact openings  118  in the circuit connection region  100   b , for exposing the source regions  106 . In addition, the material of the insulation layer  108  is, for example, silica, silicon nitride, or silicon oxynitride etc. The gate pad  110  is disposed on the insulation layer above the device region  110   a  in the substrate  100 , and the gate pad  110  electrically contacts with the gates  104  respectively through the gate contact openings  112  in the insulation layer  108 . That is to say, the gate pad  110  is disposed above the power MOSFET array  114  and covers the power MOSFET array  114 . 
         [0024]    Next, the power MOSFET array  114  further includes a source pad  120  disposed above a region beyond the gate pad  110  of the substrate  100 , i.e., above the source pad region  100   c . The source pad  120  covers the source pad region  100   c  and covers a portion of the circuit connection region  100   b . Further, the source pad  120  is electrically connected to the source region  106  through the source contact openings  118  in the insulation layer  108  in the circuit connection region  100   b.    
         [0025]      FIG. 2A  is a top view of the power MOSFET array pair according to an embodiment of the present invention.  FIG. 2B  is a simplified sectional view of FIG.  2 A along line II-II′. 
         [0026]    Referring to  FIG. 2A , the power MOSFET array pair of the present invention is disposed on a substrate  200  and includes an epitaxy layer  202 , a plurality of first gates  204 , a first source  206 , a plurality of second sources  208 , a second gate  210 , a gate pad  222 , and a source pad  224 . The substrate  200  has a first device region  200   a , a second device region  200   b , and a circuit connection region  200   c . The circuit connection region  200   c  is disposed between the first device region  200   a  and the second device region  200   b . In addition, a portion of the substrate  200  in the first device region  200   a  serves as a first drain, and a portion of the substrate  200  in the second device region  200   b  serves as a second drain. 
         [0027]    Referring to  FIGS. 2A and 2B , the epitaxy layer  202  is disposed on the substrate  200 , and a portion of the epitaxy layer  202  in the first device region  200   a  has a plurality of first gates  204  electrically insulated with each other. A first source region  206  is disposed on the epitaxy layer  202  between the first gates. The first source region  206  is, for example, a portion of the epitaxy layer  202 , that is, a portion of the epitaxy layer  202  exposed by the first gates  204  is converted to a doped region of the first source region  206  by means of ion-implantation. In addition, the first source region  206  partially extends to the circuit connection region  200   c  between the first device region  200   a  and the second device region  200   b . It should be noted that the first source region  206  and the first gates  204  form a first power MOSFET array  220 . 
         [0028]    In the second device region  200   b , a plurality of second source regions  208  electrically insulated with each other is disposed on a portion of the epitaxy layer  202  with a same horizontal height as the first gates  204  and the first source region  206 . A second gate  210  is disposed on the exposed epitaxy layer  202  between the second source regions  208 . In addition, the second gate  210  partially extends to the circuit connection region  200   c  between the first device region  200   a  and the second device region  200   b . The second source regions  208  are, for example, a portion of the epitaxy layer  202 , that is, a plurality of doped regions serving as the second source regions  208  is formed in the epitaxy layer  202  by means of ion-implantation. It should be noted that the second source regions  208  and the second gate  210  form a second power MOSFET array  240 . 
         [0029]    An insulation layer  212  covers the substrate  200 , and the material of the insulation layer  212  is, for example, silica, silicon nitride, or silicon oxynitride etc. A portion of the insulation layer  212  in the first device region  200   a  covers the first source region  206 , and the insulation layer  212  has a plurality of first gate contact openings  212   a  in the first device region  200   a . The first gate contact openings  212   a  respectively expose the first gates  204 . In addition, in the second device region  200   b , the insulation layer  212  covers the second gate  210 , and in the second device region  200   b , the insulation layer  212  has a plurality of first source contact openings  212   b  respectively exposing the second source regions  208 . 
         [0030]    Further, in the circuit connection region  200   c , the insulation layer  212  has a plurality of second gate contact openings  212   c  and a plurality of second source contact openings  212   d , respectively exposing a portion of the second gate  210  and the first source region  206  in the circuit connection region  200   c.    
         [0031]    Next, referring to  FIGS. 2A and 2B , a gate pad  222  is disposed right above the first power MOSFET array  220 . The gate pad  222  is electrically connected to the first gates  204  in the first device region  200   a  through the first gate contact openings  212   a  in the insulation layer  212 . At the same time, the second gate  210  in the second device region  200   b  is electrically connected to the gate pad  222  through the second gate contact openings  212   c  of the insulation layer  212  in the circuit connection region  200   c.    
         [0032]    At the same time, a source pad  224  is disposed right above the second power MOSFET array  240 . The source pad  224  is electrically connected to the second source regions  208  disposed in the second device region  200   b  through the first source contact openings  212   b  in the insulation layer  212 . The first source  206  in the first device region  200   a  is electrically connected to the source pad  224  through the second source contact openings  212   d  of the insulation layer  212  in the circuit connection region  200   c.    
         [0033]    To sum up, in the present invention, the MOSFET array is disposed under the gate pad, the disposing quantity of the MOSFETs of unit area is improved, thereby increasing the device integration. In addition, by using the circuit connection region, the MOSFET array disposed under the gate pad is electrically connected to the source pad above the non-array. In other aspect, similarly through the circuit connection region, the MOSFET array disposed under the gate pad and the MOSFET array disposed under the source pad can form an array pair, so as to share the same gate pad and source pad. Accordingly, the volume of the array pair is reduced, the integration is improved, such that the application scope of the power MOSFET array becomes broader. 
         [0034]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Technology Classification (CPC): 7