Patent Abstract:
Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.

Full Description:
BACKGROUND 
     One useful aspect of semiconductor-on-insulator (SOI) structures is that they permit the use of high-voltage SOI devices, such as diodes, field effect transistors (FETs), thyristors, and bipolar transistors. Still higher voltages may be achieved by connecting a plurality of such devices in series. However, doing so increases the difference in voltage potential between the device and an underlying substrate. This difference increases in each downstream device in the series. As such, the type and number of high-voltage SOI devices that may be connected in series is ultimately limited by the difference in voltage potential between the terminal device and its underlying substrate. Too great a difference in voltage potential will result in degradation of the breakdown voltage (V br ) of the series device, making the device “leaky.” This can adversely impact the efficiency of the series device, sometimes to a degree that the series device fails. For example, in the case of five high-voltage (i.e., 30 V) diodes connected in series, the voltage at the terminal diode would theoretically be 150 V. However, at or near the terminal diode, this may result in too great a difference in voltage potential with the substrate, resulting in the voltage at the terminal diode being less than 150 V. 
       FIG. 1  shows an integrated circuit  100  including a substrate  10 , a buried oxide (BOX) layer  20 , and a semiconductor layer  30 . Within semiconductor layer  30  are a plurality of HV SOI devices, here shown as diodes  40 A- 40 D, connected in series. Diode  40 A comprises a p-doped portion  42 A and n-doped portion  44 A. For the sake of clarity, the p-doped portions and n-doped portions of diodes  40 B-D are not labeled, but are similar to p-doped portion  42 A and n-doped portion  44 A of diode  40 A. 
     As can be seen in  FIG. 1 , a difference in voltage potential  41 A between diode  40 A and substrate  10  is less than a difference in voltage potential  41 B between diode  40 B and substrate  10 . A difference in voltage potential  41 C between diode  40 C and substrate  10  is greater than difference in voltage potential  41 B, and a difference in voltage potential  41 D between diode  40 D (the terminal diode) and substrate  10  is greater still. As noted above, difference in voltage potential  41 D may be so great that the breakdown voltage degrades, resulting in voltage leakage. 
     SUMMARY 
     Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. 
     A first aspect of the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band. 
     A second aspect of the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; at least one high voltage (HV) device within the semiconductor layer; an n-doped band within the substrate and below the at least one HV device; and a contact extending from the semiconductor layer and through the BOX layer to the n-doped band. 
     A third aspect of the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a p-type substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a first high voltage (HV) device and a second HV device connected in series within the semiconductor layer; a first n-doped band within the substrate and below the first HV device; a second n-doped band within the substrate and below the second HV device; a first contact extending from the semiconductor layer and through the BOX layer to the first n-doped band; and a second contact extending from the semiconductor layer and through the BOX layer to the second n-doped band, wherein the first n-doped band and the second n-doped band are separated within the p-type substrate by a space, a portion of the first n-doped band extends laterally beyond an end of the first HV device, and a portion of the second n-doped band extends laterally beyond an end of the second HV device. 
     A fourth aspect of the invention provides a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; a semiconductor layer atop the BOX layer; a first doped band within the substrate; a second doped band within the substrate; a first contact extending from the semiconductor layer and through the BOX layer to the first doped band; and a second contact extending from the semiconductor layer and through the BOX layer to the second doped band. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which: 
         FIG. 1  shows a schematic cross-sectional view of an integrated circuit having a plurality of semiconductor-on-insulator (SOI) devices connected in series. 
         FIG. 2  shows a schematic cross-sectional view of an integrated circuit according to an embodiment of the invention. 
         FIG. 3  shows a schematic cross-sectional view of an integrated circuit according to an other embodiment of the invention. 
         FIG. 4  shows a schematic cross-sectional view of an integrated circuit according to yet another embodiment of the invention. 
         FIG. 5  shows a partial schematic cross-sectional view of an integrated circuit according to still another embodiment of the invention. 
         FIG. 6  shows a schematic cross-sectional view of an integrated circuit according to yet another embodiment of the invention. 
     
    
    
     It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings. 
     DETAILED DESCRIPTION 
       FIG. 2  shows an integrated circuit  200  according to an embodiment of the invention. As in  FIG. 1 , wafer  200  includes a substrate  110 , BOX layer  120 , semiconductor layer  130 , and a plurality of diodes  140 A- 140 D within semiconductor layer  130 . While shown herein as diodes, it should be understood that embodiments of the invention may employ one or more other devices, including but not limited to a field effect transistor (FET), a thyristor, and a bipolar transistor. Wafer  200  also includes a contact  150 A disposed adjacent diode  140 A and extending from semiconductor layer  130 , through BOX layer  120 , and contacting an n-doped band  152 A within substrate  110 . Again, for the sake of clarity, only the n-doped bands and contacts of diodes  140 B- 140 D necessary for illustration of the depicted embodiment of the invention are labeled in  FIG. 2 . 
     Substrate  110  and/or semiconductor layer  130  may include silicon (p-doped, n-doped, and/or undoped), high-resistivity silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 , where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition Zn A1 Cd A2 Se B1 Te B2 , where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). In some embodiments, the substrate  10  may include amorphous or polycrystalline silicon. 
     BOX layer  120  may include, for example, oxide, silicon oxide, silicon dioxide, silicon oxynitride, silicon nitride (Si 3 N 4 ), tantalum oxides, alumina, hafnium oxide (HfO 2 ), hafnium silicate (HfSi), plasma-enhanced chemical vapor deposition oxide, tetraethylorthosilicate (TEOS), nitrogen oxides, nitrided oxides, aluminum oxides, zirconium oxide (ZrO 2 ), zirconium silicate (ZrSiO x ), high K (K&gt;5) materials, and/or combinations thereof. 
     Contact  150 A may include any conductive material, including, but not limited to, polysilicon, tungsten, silicon, and/or combinations thereof. Other useful materials include, for example, aluminum, an aluminum-copper alloy, cobalt, cobalt silicide, copper, metal silicide, nickel, nickel silicide, a nitrided metal, palladium, platinum, a refractory metal, such as ruthenium, tantalum nitride, titanium, titanium aluminum nitride, titanium nitride, titanium silicide, a titanium-tungsten alloy, and/or combinations thereof. 
     Dopants useful in forming, for example, n-doped band  152 A include, but are not limited to, phosphorus, arsenic, antimony, sulphur, selenium, tin, silicon, and carbon. P-type dopants include, for example, but are not limited to: boron, indium, and gallium. 
     N-doped band  152 A shields diode  140 A, such that a difference in voltage potential  141 A between diode  140 A and substrate  110  is minimized. Thus, as can be seen in  FIG. 2 , difference in voltage potential  141 A is substantially the same as the differences in voltage potentials  141 B,  141 C, and  141 D between substrate  110  and diodes  140 B,  140 C, and  140 D, respectively. That is, in wafer  200 , differences in voltage potential do not increase along series-connected diodes as one approaches the terminal diode as they do in wafer  100  of  FIG. 1 . As such, embodiments of the invention permit the use of higher voltage devices and/or a larger number of devices connected in series, and therefore a higher total voltage, without degrading the breakdown voltage of the series-connected device or the loss of voltage through leakage. 
     The voltages of individual devices (e.g., diodes  140 A-D) as well as the total voltage of the series-connected devices will depend, for example, on their application and the number of devices so connected. In some embodiments, voltages of individual devices are between about 10 V and about 50 V and total voltages are between about 20 V and about 150 V. Such voltages are exemplary, however, and are not limiting of the scope of the various embodiments of the invention. 
     In some embodiments of the invention, an end  153 A of n-doped band  152 A extends laterally beyond an end  143 A of diode  140 A, providing an overlap portion  154 A. Such an arrangement helps control an electric field induced by diode  140  and ensures that substrate  110  does not act to gate diode  140 A. 
     Similarly, in some embodiments of the invention, a space  156 A remains between adjacent n-doped bands  152 A,  152 B. That is, a second end  155 A of n-doped band  152 A is separated within substrate  110  from a first end  153 B of n-doped band  152 B. Space  156 A is large enough to ensure that n-doped band  152 A and n-doped band  152 B do not act as a single shield, which would cause the depletion regions of each diode  140 A,  140 B to intersect, resulting in a single voltage potential for the two diodes  140 A,  140 B. 
       FIG. 3  shows an integrated circuit  300  according to another embodiment of the invention. Here, a plurality of deep diodes  240 A- 240 D are connected in series within a thick semiconductor layer  230 . Each deep diode (e.g.,  240 A) includes stacked p-doped regions  242 A,  246 A and stacked n-doped regions  244 A,  248 A, such that a shallow trench isolation  260 A and deep trench isolation  262 A are formed in semiconductor layer  230  adjacent each deep diode. Thick semiconductor layer  230  permits the incorporation of an internal isolation  247 A within deep diode  240 A. That is, internal isolation  247 A isolates p-doped region  246 A from n-doped region  248 A but does not extend through to BOX layer  220 . 
       FIG. 4  shows an integrated circuit  400  according to another embodiment of the invention, in which a p-doped band  352 A is used in an n-type substrate. The shielding properties of wafer  400  are similar, therefore, to those of wafer  200  in  FIG. 2 . 
       FIG. 5  shows an integrated circuit  500  according to yet another embodiment of the invention. In wafer  500 , a plurality of high-voltage n-type field effect transistors (n-FETs) are connected in series. (For the sake of clarity,  FIG. 5  shows only two n-FETs  440 A,  440 B, although any number of such devices may be connected in series, and only the features of n-FET  440 A are labeled.) Each n-FET  440 A,  440 B includes a polysilicon gate  480 A, polysilicon conductors  446 A,  448 A, a p-well  470 A, n-wells  442 A,  444 A, and a gate oxide formed from shallow trench isolation (STI)  460 A. In wafer  500 , n-doped band  452 A shields n-FET  440 A similarly to the shielding of diode  140 A in  FIG. 2 . 
       FIG. 6  shows an integrated circuit  600  according to still another embodiment of the invention. Wafer  600  is similar to wafer  200  of  FIG. 2 , but each n-doped band  652 A,  652 B,  652 C,  652 D is biased to a voltage V 1 , V 2 , V 3 , V 4 , respectively. Each voltage V 1 , V 2 , V 3 , V 4  is optimized to reduce voltage leakage or increase breakdown voltage (V br ) of its respective diode  640 A,  640 B,  640 C,  640 D. 
     The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.

Technology Classification (CPC): 7