Patent Abstract:
A system and a method for converting an analog signal to a digital signal are provided. The technique involves receiving a sampled analog signal, and selecting one of a plurality of segments of a segmented relation between DAC output values and desired ADC input values. Desired gain and offset values are applied to the DAC output values or to the sampled analog signal based upon the selected segment. The sampled analog signal is converted to a digital signal based upon the desired gain and offset values.

Full Description:
BACKGROUND 
   The invention relates generally to signal processing, and more particularly to systems and methods used in the transformation of image signals between the analog and digital domains to aid in image signal processing. 
   Signal processing is a valuable tool for various applications that involve data transmission, data storage, and the like. One aspect of signal processing, for certain applications, is to convert an analog signal into its digital equivalent to facilitate storage, transmission, workability, signal conditioning, noise filtering, and the like. For example, a digital X-ray panel may convert a scanned X-ray image into a digital format for subsequent processing, storage and image reconstruction. 
   Various signal processing techniques exist that provide transformation of image signals between the analog and digital domains. One such method for performing analog-to-digital (A/D) signal conversion utilizes a single digital-to-analog converter (DAC) for providing a base analog signal for comparison to an input analog signal that requires conversion. 
   Although such a method provides high accuracy, one disadvantage with A/D conversion using a single DAC is that the process is slow. This is because each input analog signal is converted individually into a digital equivalent by a dedicated channel, and all the channels are driven by the same DAC. The counter that provides a digital count to the DAC, therefore, has to run from the lowest count to the highest count before all channels perform conversion of each input analog signal into digital equivalents. 
   Attempts have been made to increase the speed of A/D conversion process. One method of increasing the speed is by increasing the number of DACs so that each channel has a dedicated DAC. However, such a method may not be cost effective in certain applications. For example, a digital X-ray panel using a single DAC for A/D conversion process has a speed of 30 frames per second (fps), which may not be suitable for applications requiring higher frame rate. The speed may be improved by increasing the number of DACs. However, due to the increase in cost and complexity of the additional circuitry, such a digital X-ray panel becomes prohibitively expensive and complex. 
   There is therefore a need for a system and method to improve the speed of A/D conversion process. 
   BRIEF DESCRIPTION 
   According to one aspect of the present technique, a system and a method for converting an analog signal to a digital signal are provided. The technique includes receiving a sampled analog signal, and selecting one of a plurality of segments of a segmented relation between DAC output values and desired ADC input values. Desired gain and offset values are applied to the DAC output values or to the sampled analog signal based upon the selected segment. The sampled analog signal is then converted to a digital signal based upon the desired gain and offset values. The system and method may be implemented in digital X-ray systems. 

   
     DRAWINGS 
     These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein: 
       FIG. 1  is a diagrammatic view of an exemplary digital X-ray system, in which signal conversion is implemented in accordance with aspects of the present technique; 
       FIG. 2  is a diagrammatic view of an exemplary digital X-ray panel of a type that may be used in a system such as that of  FIG. 1  for generating analog signals to be converted to digital signals in accordance with aspects of the present technique; 
       FIG. 3  is a diagrammatic view of an exemplary digital acquisition system for the digital X-ray panel shown in  FIG. 2 ; 
       FIG. 4  is a diagrammatic view of an exemplary system shown in  FIG. 3 , in accordance with aspects of the present techniques; 
       FIG. 5  is a graphical view of a path followed by the DAC output signal, illustrating a segmentation process in accordance with aspects of the present technique; 
       FIG. 6  is a diagrammatic view of an exemplary embodiment of the system shown in  FIG. 3  in accordance with aspects of the present technique; 
       FIG. 7  is a detailed diagrammatic view of the architecture of the system shown in  FIG. 6 ; 
       FIG. 8  is a diagrammatic view of an exemplary memory stack utilized in the digital acquisition system in accordance with aspects of the present technique; 
       FIG. 9  is a graphical illustration of the segmented linear-polynomial path followed by the DAC output signal in accordance with aspects of the present technique; and 
       FIG. 10  is a flowchart illustrating an exemplary digital signal conversion process in accordance with an exemplary embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   In the subsequent paragraphs, various aspects of a technique for signal conversion will be explained in detail. The various aspects of the present technique will be explained, by way of example only, with the aid of figures hereinafter. Referring generally to  FIG. 1 , the present technique for conversion of analog signals to digital signals will be described by reference to an exemplary digital X-ray system designated generally by numeral  10 . It should be borne in mind, however, that the technique may find application in a range of settings and systems, and that its use in the X-ray system shown is but one such application. 
   The digital X-ray system  10  of  FIG. 1  is operable to capture an X-ray projection of a portion of the body of a subject  12  under medical examination. However, as will be appreciated by those skilled in the art, the digital X-ray system  10  may also be utilized for non-destructive evaluation (NDE) of materials, such as castings, forgings, or pipelines, inspection of parts, parcels and baggage, and other such applications. The digital X-ray system  10  comprises an X-ray source  14  that is used to scan the subject  12 . The X-ray source  14  generates X-ray beams that penetrate through the subject  12 . In a typical medical application, the X-ray beams may be attenuated based on the texture of the organs, skin, lesions, muscle, bones and the like, in the various portions of the body of the subject  12 . The attenuated X-rays are captured by a digital X-ray panel  16 , as illustrated in  FIG. 1 , which comprises a plurality of photodiodes that form a pixel array. The projection thus formed, is read row-by-row or column-by-column by one or more data modules  18 , where each line of pixels may be enabled for scanning, by one or more scan modules  20 . Control circuitry  22  is used to control the operation of the data modules  18  and the scan modules  20 . 
     FIG. 2  is a diagrammatic view of an exemplary digital X-ray panel  16 . The digital X-ray panel  16  comprises a plurality of rows  24 , each of which contains a plurality of photodiodes defining the pixels  26  arranged contiguously to form a pixel matrix or a pixel array. During operation of the X-ray panel  16 , received X-ray radiation is converted to a lower energy form, and each of the photodiodes  26  has an initial charge that is depleted by an amount representative of the amount of X-ray radiation incident on the respective location of each photodiode  26 . The data modules  18  are operable to read the amount of charge from each of the photodiodes  26 . Each row  24  is scanned by the data modules  18  in conjunction with the scan modules  20  to read the amount of charge from all the pixels  26  in that row  24  (or column). The scan module  20  corresponding to a row  24  enables reading the pixels  26  in that row  24 . When the pixel  26  is enabled for reading, the data module  18  corresponding to that pixel  26  reads the charge stored on the photodiode or pixel  26  by recharging the photodiode. Having read the charge value from the plurality of photodiodes  26 , the data module  18  converts the charge value into a digital equivalent for further processing. 
   Turning now to  FIG. 3 , a diagrammatic view of an exemplary digital acquisition system  28  for the digital X-ray panel  16  of  FIG. 2  is illustrated. The digital acquisition system  28  comprises an analog readout chip (ARC)  30 , which comprises circuitry for reading the charge from (in practice the recharge to) the photodiodes  26  in the X-ray panel  16 . The ARC  30  processes and digitizes the charge from the photodiodes  26 . Detailed functionality of the ARC  30  will be explained later in the description. For facilitating digitization of the charge from the photodiodes  26 , a digital-to-analog converter (DAC)  32  may be utilized. Driven by a counter, the DAC  32  provides a DAC output signal for circuitry in the ARC  30  to compare the charge values read from the photodiodes  26 . The DAC output signal may define a linear portion and a polynomial portion, such as a linear portion, a quadratic portion, a cubic portion, and the like. The DAC output signal will be explained in further detail below. 
   In accordance with the present technique, the DAC output signal may be divided into segments to improve the speed of scanning an entire row  24  of pixels  26  and, consequently, the overall speed of digitizing the X-ray image. Therefore, a segment that comprises the location of charge value (input signal) may be desirably located. For locating a segment, segment-gain information may be required, which may be provided by a programming element  34 . Moreover, other programmable options, such as dynamic bandwidth control and the data readout may be set by the programming element  34 . A data logger  36  collects the digitized data from the ARC  30  and transmits the data to digital circuitry for image processing and reconstruction of a useful image. 
     FIG. 4  is a diagrammatic view of the exemplary ARC  30  shown in  FIG. 3 , in accordance with aspects of the present techniques. ARC  30  comprises a plurality of channels  38 , each being operable to read the charge value from a photodiode or pixel  26  and to provide the digital equivalent. The DAC  32  is common to all the channels  38 , so that the DAC  32  provides the DAC output signal to each of the channels  38 , which respectively compare the charge value with the common DAC output signal. An input signal  40 , comprising a charge value from a photodiode or pixel  26 , is provided to the channel  38 , as illustrated. Each channel comprises an integrator  42 , which integrates the input signal  40  (charge value Q in ) for conversion into an equivalent voltage value, V int , which is fed into a low-pass-filter  44  for reducing noise. Voltage signal outputted from the low-pass-filter  44 , V lpf , is fed into a double sampling amplifier  46 , which provides a desirable gain to V lpf . The output of the double sampling amplifier  46 , V dsa , is sampled and held in sample and hold (S/H) circuitry  48 . The double sampling amplifier  46  in conjunction with the low-pass-filter  44  provides correlated double sampling process to reduce offset and flicker noise. Integrator  42 , low-pass-filter  44 , and double sampling amplifier  46  together form an analog front-end. The analog front-end may therefore be decoupled from the rest of the channel  38  by the S/H circuit  48 . Pipelined conversion is thus achieved by the use of the S/H circuit  48 . 
   The output of the S/H circuit  48 , V sh , and the DAC output signal provided by the DAC  32  may be fed as input into a comparator  50  for comparison. The comparator  50  provides either a high or a low output based on the comparison of V sh  and the DAC output signal provided by the DAC  32 . The channel  38  also comprises a register  52 , which is provided with a counter value from a counter  54 . The counter value provided by counter  54  is proportional to the digital code provided to the DAC  32  for generating the DAC output signal. The output of the comparator  50  may be configured to freeze the counter value in the register  52  when the output of the S/H circuit  48  and the DAC output signal provided by the DAC  32  are equal. Because the counter value provided to DAC  32  and register  52  are proportional, the frozen counter value in the register  52  is representative of the digitized output of the input signal (charge value) of the corresponding pixel  26  read by channel  38 . 
   A state machine  56  may be utilized to synchronize the counter  54  and the count value provided to the DAC  32  at any instant. It may be noted that the integrator  42 , low-pass-filter  44 , double sampling amplifier  46 , S/H circuit  48 , comparator  50  and register  52  comprise a single channel  38  that reads a single photodiode or pixel  26 . In one embodiment, there are thirty-two different channels  38  hard-wired into a single ARC  30 . DAC  32  is common to the entire system. Counter  54 , and state machine  56 , however, are separate components, within the ARC  30  that are common to all thirty-two channels  38 . Each of the data modules  18 , described previously with reference to  FIG. 2 , may comprise eight analog readout chips  30 , and a single digital analog readout chip. Therefore, each data module  18  can read and digitize 256 pixels simultaneously. Thus, if a row of 1024 pixels  26  has to be read simultaneously, 4 (=1024/256) data modules  18  may be employed. Detailed operation of the ARC  30  will be explained below. 
   Referring now to  FIG. 5 , a graphical illustration  58  of a path followed by the DAC output signal is shown. The illustration  58  shows the output signal values, in counts, on the y-axis  60  plotted against ramp counter values on the x-axis  62 . The ramp counter value  62  is proportional to the digital code values that are fed into the DAC  32  for generating the DAC output signal that follows a linear-polynomial ramp  64 . Therefore, the DAC output signal increases in steps or counts. The linear-polynomial ramp  64  defined by the DAC output signal begins with a linear portion  66  until a desirable ramp counter value C. Beyond ramp counter value C, the ramp may advantageously define a polynomial portion  68  for improvement of signal-to-noise ratio of the digital output of the scanned X-ray image. 
   Quantum noise is the noise intrinsic to an X-ray image. The amount of quantum noise produced by an X-ray beam is equal to the square root of the number of X-rays incident on the detector  16 . Therefore, at high X-ray flux, the system may be prone to more quantum noise and relatively less electronic noise. Advantageously, quantization step can made proportional to the quantum noise, without any loss of information. In other words, when the signal is small, small steps may be employed, and when the signal is large, step size may be increased. 
   In one specific embodiment, the linear-polynomial ramp  64  may define a linear portion  66  followed by a quadratic portion  68 , and may be therefore termed as a linear-quadratic ramp. Furthermore, the polynomial portion  68  may define a cubic curve, or other polynomial curves that may be advantageously employed. The particular relationship between the input and output (count) values may follow other profiles and relations in other applications. Moreover, the segmentation of the relationship, as described below, may result in more or fewer segments than those described here, and will typically result in different offsets and gains (slopes) for each segment, also as described below. 
   Referring back to  FIG. 4 , the output of the S/H circuit  48  is provided to the comparator  50 . The value of the DAC output signal (initially zero) is checked against V sh . If the DAC output signal at that instant is not equal to the output of the S/H circuit  48 , the ramp counter value that provides counts to the DAC  32  and the register  52  is increased to the next count value. The linear-polynomial relationship (linear-quadratic, linear-cubic, etc.) between the ramp counter and the digital code may be appropriately implemented based on the applications. For example, for the linear portion, the ramp counter and the digital code to the DAC may be equal. Beyond a certain ramp counter value, e.g. C in  FIG. 5 , the relationship may be polynomial. The ramp counter in  FIG. 5  and the counter  54  in  FIG. 4  increment linearly. However, the digital code provided to the DAC  32  and the resulting analog signal will be linear-polynomial. When the DAC output signal becomes equal to V sh , the comparator  50  provides a signal that freezes the counter value residing in the register  52 . Therefore, the register  52  contains a digital value corresponding to the input signal from the respective channel (i.e., the charge value for the photodiode or pixel  26  of  FIG. 2  in the X-ray system implementation). By applying the relationship between the DAC digital code and the ramp counter value, an equivalent DAC digital code to the counter value yields the charge value stored on the photodiode  26 . 
   Those skilled in the art will appreciate that if the maximum possible value of the output of S/H circuit  48  is divided by a greater number of total counts (i.e. a finer comparison), the resolution of the digital output corresponding to the input signal will be increased. For example, if the maximum value attained by the output of S/H circuit  48  is 5 volts, and the total number of counts that may be provided to the DAC  32  is 1024, the step size of the ramp counter value will be 5/1024. However, if the total number of counts that may be provided to the DAC  32  is 2048, the step size of the ramp counter value will be 5/2048, which, being smaller, provides higher resolution. Also, for digitizing a signal in the higher range (e.g., 5 volts) at the S/H circuit  48 , about 2048 steps may have to be provided to the DAC  32 . Furthermore, if the signal to be digitized is greater (e.g., 10 volts), then to produce the desired resolution, more number of steps (ramp counter values) may be required. 
   In the X-ray system implementation described above, because the thirty-two different channels  38  are provided with the same DAC output signal that is used for comparison in each of the channels  38 , and given that these different channels  38  may have different charge values to be compared, the DAC  32  may provided for all the counts from minimum to the maximum count. The amount of time required for the whole image to be digitized is therefore limited by the time taken for the DAC  32  to traverse from the minimum to maximum count. Therefore, this may limit the frame rate of scanning the digital X-ray panel. However, by using the linear-polynomial ramp  64 , it will be understood that much fewer than 2048 steps may be needed to dynamically cover the range of 5 volts. 
   The graphical illustration  58  further shows a segmentation process for achieving a higher signal conversion rate. Segmentation may be achieved by using the generally linear portion  66 , and transforming it to generate portions of the polynomial portion  68 . In other words, counter values provided to the DAC  32  follow a linear ramp, until the ramp counter value C, hereinafter referred to as the base ramp  66 . The base ramp  66  is common to the entire ramp  64 . The remaining portions of the curve  64  may be generated within the ARC  30  on a channel-by-channel basis by applying gain and offset values to the base ramp  66 . 
   Moreover, while digitizing the input signal  40 , the ARC  30  may coarsely compare V sh  against ramp count values C, 2C, 3C, 4C, and 5C. If the comparator  50  on a given channel actuates (i.e., changes output state) on application of any of the above ramp count values, such actuation is indicative of V sh  lying in the segment ending that ramp count value. For example, at 2C if the comparator  50  does not actuate, and at 3C, the comparator  50  actuates indicating that V sh  is less than 3C, then the coarse A/D conversion registers that the output of S/H circuit  48  lies between the counts 2C and 3C, or in segment  72 . The base ramp  64  received by this particular channel  38  is manipulated by applying gain and offset values to recreate the segment  72 . Once a segment is identified as having the digital equivalent of the output of S/H circuit  48 , then a fine A/D conversion similar to that described previously with respect to linear-polynomial ramp  64 , may be performed. For example, the counts between 2C and 3C are compared against the output of S/H circuit  48 , such that the counts follow the path defined by segment  72 . Such an auto-ranging process enhances the speed of A/D conversion. It may be noted that any of the segment to be traced could be generated using a base ramp  66  and by adding an offset and multiplying by a gain value. This may be performed to achieve the desired linear portion in the corresponding segment, which has the desired starting value and slope. In general, then, a segment i can be described by the following equation:
 
V( i )=V offset ( i )+Gain( i )*V base  
     where, V(i) is the desired output voltage for comparison in segment i;   V base  is the base voltage of linear portion  66 ;   Gain(i) is the gain value, which is multiplied to base voltage V base  to transform V base  to the desired slope in segment i;   V offset (i) is the desired offset voltage that is added to Gain(i)*V base  to reach segment i.   

   It will be understood by those skilled in the art that the base ramp, which in the above example is the generally linear portion  66  of the linear-polynomial ramp  64 , may lie in any of the segments. In other words, if the generally linear portion  66  lies in the middle of the linear-polynomial ramp  64 , then the offset voltage V offset (i) corresponding to a segment i in the left of the base ramp would be negative. 
   Referring now to  FIG. 6 , a diagrammatic view of an exemplary embodiment of the ARC  30  of  FIG. 3  is illustrated. The charge value Q in    40  from the detector  16  is converted to a voltage by the integrator  42 . The output of the integrator  42  is fed to a low-pass-filter  44  and amplified by the double sampling amplifier  46 . A coarse A/D conversion is performed by block  80  to determine a suitable segment. After being processed by block  80 , the output comprises a digital equivalent of the segment information. This segment information may comprise one or more bits indicating the segment. The bits also form the exponent of the digital output of the charge value Q in    40 . Based on the segment information, appropriate gain Gain(i) and offset values V offset (i) may be selected by a gain/offset selector  82 . Once the gain and offset values are selected, appropriate gain values are provided, such as gain G int  to integrator  42 , gain G dsa  to double sampling amplifier  46 , gain G s  to S/H circuit  48 , and gain G p  to a fine A/D conversion block  84 . The gain/offset selector  82  therefore manipulates the base ramp  66  from the DAC  32  by applying gains G int , G dsa , G s , G p  and V offset (i) to generate the i th  segment. The offset voltage V offset  is generated by an offset multiplexer  86 . The signal gain of channel  38  may therefore be defined by G channel =G int *G dsa *G s . The transposed signal is then sampled and held by the S/H circuit  48  before being digitized by the fine A/D conversion block  84  to provide the mantissa. The segment offsets and references for both coarse and fine ADC are generated by time division multiplexing of the DAC, and, pipelining the charge value Q in    40  in the S/H circuit  48 . 
   The output of the fine A/D conversion block  84  comprises the mantissa of the digital value. Thus, the digitized signal corresponding to the charge value Q in    40  comprises the segment information from block  80  and the output of the fine A/D conversion block  84 . 
     FIG. 7  is a detailed diagrammatic view of the architecture of ARC  30 , shown in  FIG. 6 . The charge value Q in    40  from the detector  16  is fed to the integrator  42  comprising an integration capacitor  88  in a feedback loop of an amplifier  90 . In addition to storing the charge value Q in    40  temporarily, the integrator  42  may serve to convert the charge value Q in    40  into a voltage equivalent. It may be noted that the low noise integrator  42  is reset each time prior to reading a fresh charge value Q in    40  so as to remove any charge stored in the capacitor  88 . This voltage is fed into the low-pass-filter  44 , which comprises a tunable resistor R  92 , and tunable capacitors C b    94  and C ds    96 . Because resistor R  92 , and capacitors C b    94  and C ds    96  are tunable, the low-pass-filter  42  may be utilized to dynamically change the low-pass-filter bandwidth of the channel  38  during A/D conversion to obtain faster settling times and lower noise effective bandwidth. 
   The double sampling amplifier  46 , comprising an integration capacitor  98  in a feedback loop of an amplifier  100 , amplifies the output of the low-pass-filter  44 . The double sampling amplifier  46  may be a correlated double sampling amplifier, for removing any reset-offset pedestal, as well as any kTC and reset noise of the integrator  42 . 
   The output of double sampling amplifier  46  is sampled and held on a capacitor C sh    102 , in the S/H circuit  48 , at the input of the comparator  50 . Digitization is achieved by disabling the parallel load of the counter value provided to the register  52  when the linear-polynomial ramp  64  exceeds the value held on the sample and hold capacitor C sh    102 . The resulting conversion is transmitted via one of eight serial outputs (four channels per serial output) in a simultaneous fashion, thereby allowing transmission of digital data from all the thirty-two different channels  38  simultaneously. Pipelined conversion is facilitated by the S/H circuit  48 . Integration, conversion and transmission are pipelined in consecutive Sync cycles, which comprise the reading cycles. The dynamic range of the system may be further extended by providing a bank of integration capacitors  86 . 
   Because charge value Q in    40  is compared to the linear-polynomial ramp  64  during the fine ADC, therefore either the linear-polynomial ramp  64  or the charge value Q in    40  may be manipulated. Alternatively, both the linear-polynomial ramp  64  and the charge value Q in    40  may be manipulated. If the linear-polynomial ramp  64  is manipulated to generate a segment, which encompasses the charge value Q in    40 , then the gain of the linear-polynomial ramp  64  may be changed by changing G p  alone, and applying an offset V offset (i) to implement equation V(i)=V offset (i)+Gain(i)*V base . 
   The linear-polynomial ramp  64  can be created by alternatively using a switch selectable capacitor bank having capacitors C 1 , C 2 , and C 3  (not shown) instead of capacitor C dac    104  prior to the comparator  50 . Once the gain/offset selector  82 , selects the gain value Gain(i) and the offset value V offset , the offset value V offset  provided by the offset multiplexer  86  may be applied through a capacitor, C os    106 . However, changing only gain G p  of the linear-polynomial ramp  64  to generate the segment may cause C dac    104  to become extremely large for implementation of all gains. Advantageously, gain decomposition may be implemented for changing gain G p  of the linear-polynomial ramp  64 . The ramp based fine A/D conversion compares the charge in the capacitors C 1 -C 3 . Capacitor C 1  may be the same as C dac    104  in gain decomposition implementation and provides an amplified version of the base ramp  66 . Capacitor C 2 , which may be the same as C sh    102 , contains the sampled and held signal from the double sampling amplifier  46 . The offset V offset  is applied using C 3 , which may be the same as C os    106 . The voltage V X  at node  108  is given by: 
             V   X     =         G   *     V   ramp     *     C   1       +       V   offset     *     C   3       -       V   signal     *     C   2             C   1     +     C   2     +     C   3                     Therefore   ,     
     ⁢       V   X     =       G       C   1     +     C   2     +     C   3         *       [         V   ramp     *     C   1       +         V   offset     G     *     C   3       -         V   signal     *     C   2       G       ]     .               
When the voltage V X  at node  108  transitions from positive to negative, or vice-versa, comparator  50  trips (i.e., is actuated) because the charge in C 1  (=C dac ) exceeds the charge from C 2  (=C sh ) and C 3  (=C os ). The equation can be rewritten as decomposition of a single channel gain G channel  distributed into gains of integrator  42   
             (       A   int     =     1     G   int         )     ,         
double sampling amplifier  46   
             (       A   dsa     =     1     G   dsa         )     ,         
S/H circuit  48   
             (       A   s     =     1     G   s         )     ,         
and gain G p , as follows:
 
             V   X     =           A   int     *     A   dsa     *     A   s           C   1     +     C   2     +     C   3         *     [         G   p     *     V   ramp     *     C   1       +         V   offset         A   int     *     A   dsa     *     A   s         *     C   3       -         V   signal     *     C   2           A   int     *     A   dsa     *     A   s           ]             
where A int , A dsa , A s  are the attenuation factors applied to reduce the gain of integrator  42 , double sampling amplifier  44 , and sampling capacitor ratio C sh    102 , respectively. Consequently, the actual channel gain changes from the original
 
   
     
       
         
             
           
             
               
                 
                   
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   The gain values G int , G dsa , G s , and G p  may be implemented as switch selectable capacitor banks, C int    88 , C dsa    96 , C s    102 , and C dac    104 . The offset may be implemented by applying V offset  through capacitor C os    106  at either node  108  or  110 . By choosing node  110 , a single capacitor bank implementing the gain of the double sampling amplifier  46  manipulates both the signal and offset optimally. Therefore, the gain of the channel changes as a function of the signal, providing optimal signal-to-noise performance. 
   In one embodiment, the detector  16  may use an amorphous silicon field effect transistor (FET), as a switch to release the charge value Q in    40  from the detector  16 . The amorphous silicon FET may subject the detector  16  to transients, which may provide incorrect auto-ranging. Thus, in this architecture, G int  is set as a constant to overcome incorrect auto-ranging. The value of G int  may be application specific. Hence, without loss of generality, the total gain may be considered as G=A dsa *A s *A p . In other words, the total gain G will be dynamically distributed to A dsa , A s , and A p . Because double sampling amplifier  46  has the maximum impact on the noise performance in the back-end stages, to optimize noise performance, A dsa  may be minimized (i.e. G dsa  is maximized), and As may be minimized (i.e. G s  is maximized). If A dsa  is small, G p  may be minimized. If both A dsa  and A s  are minimum, then G p  will be maximized. 
   For example, in an exemplary application, G dsa  can be set to 1, 2, or 4; G s  to 1, 2, or 4; and G p  to 1 or 2. Given these conditions, to achieve a total DAC gain of G=4, then G dsa  may be set according in the following manner: A dsa  can be set 1, i.e. G dsa =4, which is the maximum gain of double sampling amplifier  46 . Thus, 
                 A   s     *     G   p       =       G     A   dsa       =       4   1     =   4         ,         
which will be distributed to A s  and G p . Because the maximum gain for G s  is 4, we set A dsa =2, i.e. G s =2. Moreover, because
 
               G   p     =       G       A   dsa     *     A   s         =       4     1   *   2       =   2         ,         
therefore, the final gain distribution for a total DAC gain of 4 is A dsa =1, A s =2, and G p =2. Alternatively, A dsa =2, A s =2, and G p =1, or, A dsa =4, A s =1, and G p =1. However, such alternatives may not achieve better signal-to-noise ratio because the signal gain is not maximized. Thus, each segment has properties of gain (G dsa , G s , G p ) and offset V offset  associated with it. These properties may be encoded and stored in a register file within the ARC  30 .
 
   An auto-ranging algorithm that may be followed is as below:
 
V os0 ≦V dsa &lt;V os1 , then V os =0 and G=1;
 
V os1 ≦V dsa &lt;V os2 , then V os =V os1  and G=G 1 ;
 
V os2 ≦V dsa &lt;V os3 , then V os =V os2  and G=G 2 ;
 
V os3 ≦V dsa &lt;V os4 , then V os =V os3  and G=G 3 ;
 
V osN-1 ≦V dsa &lt;V osN , then V os =V osN-1  and G=G N ;
 
   An alternate algorithm that maximizes SNR is as follows
 
V os0 ≦V dsa &lt;V os1 , then V os =0 and G channel =G max  
 
               V     os   ⁢           ⁢   1       ≤     V   dsa     &lt;     V     os   ⁢           ⁢   2         ,       then   ⁢           ⁢     V   os       =           V     os   ⁢           ⁢   1       ⁡     (       G   max       G   1       )       ⁢           ⁢   and   ⁢           ⁢     G   channel       =       G   max       G   1                           V     os   ⁢           ⁢   2       ≤     V   dsa     &lt;     V     os   ⁢           ⁢   3         ,       then   ⁢           ⁢     V   os       =           V     os   ⁢           ⁢   2       ⁡     (       G   max       G   2       )       ⁢           ⁢   and   ⁢           ⁢     G   channel       =       G   max       G   2                           V     os   ⁢           ⁢   3       ≤     V   dsa     &lt;     V     os   ⁢           ⁢   4         ,       then   ⁢           ⁢     V   os       =           V     os   ⁢           ⁢   3       ⁡     (       G   max       G   3       )       ⁢           ⁢   and   ⁢           ⁢     G   channel       =       G   max       G   3                           V       os   ⁢           ⁢   N     -   1       ≤     V   dsa     &lt;     V     os   ⁢           ⁢   N         ,       then   ⁢           ⁢     V   os       =         V       os   ⁢           ⁢   N     -   1       ⁢           ⁢   and   ⁢           ⁢     G   channel       =   1             
where G max =G int     Max   *G dsa     Max   *G s     Max   =G N . The original base ramp  66  is multiplied by G max  to span the entire power supply. It may be noted that the channel gain is selected after the comparator  50  at the output of the double sampling amplifier  46  has determined the segment.
 
   Gain distribution may be implemented in the architecture shown in  FIG. 7 . The DAC  32  is distributed to the double sampling amplifier  46  and sampling capacitor ratio during fine A/D conversion. The coarse ADC quantizes the output of double sampling amplifier  46  to determine signal range and then the gain/offset selector  82  applies appropriate offset V offset  to the input of double sampling amplifier  46  and gain to the following stages, including double sampling amplifier  46 . 
   Referring generally to  FIG. 8 , a diagrammatic view of an exemplary memory stack  112  utilized in the digital acquisition system is illustrated. The memory stack  112  comprises information stored in registers  114 , each having bit allocations for the various gain and offset values, such as, hints G int , G dsa , G s , and V offset . As illustrated, in register  114 , M1 bits may be allocated to G int , M2 bits may be allocated to G dsa , M3 bits may be allocated to G s , and M4 bits may be allocated to V offset . During the coarse A/D conversion, the segment is determined. Once the segment is determined, the gain/offset selector  82  selects the various gains and offset values noted above from the memory stack  112 . Thus, memory stack  112  serves as a look-up-table that stores the different gain &amp; offset combinations to be used in a given segment. It may be noted that in the memory stack  112 , there may be N registers, and therefore, the size of the memory stack  112  may be equal to N*(M1+M2+M3+M4) bits. Such implementation of the technique may be used to render the same basic system and hardware adaptable to a wide range of applications, systems, conversions and relationships between input signals and output signals (count values). 
   It may be noted that several DACs (equal to the number of segments) may be utilized to provide fine A/D conversion for each channel once the segment is identified. For example, if the DAC output signal is divided into six segments, then six DACs may be provided in common to all the thirty-two channels, such that each of the DACs is dedicated to a single segment. Moreover, in such case, the gain and offset values for the respective segments may be pre-defined for the segment, and the system will apply the same automatically while performing the fine A/D conversion. 
   Referring generally to  FIG. 9 , a graphical illustration  116  of the segmented linear-polynomial path followed by the DAC output signal is shown. As illustrated, after every C counts, the DAC output signal assumes a linear segment that conforms to the linear-polynomial path  64 . Non-optimal gain values provided during transformation of the base ramp  66  to the desired segment may result in dead bands. Similarly, variation in non-ideal implementation of offset value may result in dead bands. Such effects may provide erroneous digital output of the charge value Q in    40 . However, sufficient overlap  118  between segments may be provided to avoid dead zones caused by capacitor mismatches, offset errors, and other chip processing imperfections. 
     FIG. 10  is a flowchart illustrating the digital signal conversion process  120 . As illustrated in process  120 , a coarse A/D conversion is performed by the ARC  30  (block  122 ). The coarse A/D conversion may be utilized to determine the segment information (block  124 ). The segment information comprises the segment in which the digital equivalent of the input signal (e.g., charge value Q in )  40  lies. Once the segment is determined, the digital signal conversion process  120  proceeds with performing a fine A/D conversion to determine the digital equivalent of the input signal (e.g., charge value Q in )  40  (block  126 ). 
   The teachings of the present techniques may be implemented in systems where A/D conversion of a plurality of analog values is performed via a single DAC. Such systems may include digital X-ray systems, digital cameras, as well as other applications outside the imaging field. The teachings of the present techniques enable faster signal conversion. Moreover, advantages of the techniques include increased dynamic range with faster rates of conversion at lower power consumption, appropriate signal conditioning prior to conversion, optimized noise performance, and self test capability without reliance on external stimulus for providing precise amounts of charge to validate the system. Dynamically changing the bandwidth during a scan may allow obtain faster settling times and lower noise effective bandwidth. 
   While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.

Technology Classification (CPC): 7