Patent Abstract:
A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a liquid crystal display device and method for driving the same, and more particularly, to a liquid crystal display device capable of reducing image flicker and method for driving the same. 
     2. Description of the Prior Art 
     Liquid crystals display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) devices and been widely used in electronic products, such as notebook computers, personal digital assistants (PDAs), flat panel TVs, or mobile phones. In traditional LCD devices, a source driver and a gate driver are used for driving the pixels of the panel in order to display images. Since the source driver is more expensive than the gate driver, LCD devices adopting half source driver (HSD) structure have been developed in order to reduce the number of source drivers. In other words, for the same amount of pixels, the manufacturing cost can be reduced by halving the number of data lines receiving signals from the source driver and doubling the number of gate lines receiving signals from the gate driver. 
       FIG. 1  is a prior art LCD device  100  which adopts HSD structure. The LCD device  100  includes a timing controller  130 , a source driver  110 , a gate driver  120 , a plurality of data lines DL 1 -DL m , a plurality of gate lines GL 1 -GL n , and a pixel matrix. The pixel matrix includes a plurality of pixel units PX L  and PX R  each having a thin film transistor (TFT) switch, a liquid crystal capacitor C LC  and a storage capacitor C ST , and respectively coupled to a corresponding data line, a corresponding gate line and a common node. The timing controller  130  can generate control signals YOE and YV 1 C, input clock signals CK and CKB or an output enable signal OE for operating the source driver  110  and the gate driver  20 . The source driver  110  can generate data driving signals SD 1 -SD m  corresponding to display images. If the gate driver  120  is an external driving circuit, the gate driving signals SG 1 -SG n  for turning on the TFT switches are generated according to the control signals YOE and YV 1 C; if the gate driver  120  is fabricated using gate on array (GOA) technique, the gate driving signals SG 1 -SG n  are generated according to the input clock signals CK,CKB and the output enable signal OE. 
     When the TFT switch is turned off, the pixel electrode is not connected to any voltage source and thus has a floating level. Any voltage variation around the pixel electrode is coupled to the pixel electrode via its parasite capacitance, which in turn influences the voltages applied to the liquid crystal capacitor C LC  and the storage capacitor C ST . The feed-through voltage V FD  due to voltage variations caused by parasite capacitance can be represented by the following equation:
 
 V   FD   =[C   GD /( C   LC   +C   ST   +C   GD )]* ΔV   G   =K*ΔV   G  
 
     C GD  represents the parasite capacitance between the gate and the drain of the TFT switch. K represents the percentage of C GD  which contributes to the overall parasite capacitance. ΔV G  represents the gate voltage difference caused by a gate driving signal when turning off a corresponding TFT switch. The parasite capacitance is an inherent characteristic of the TFT switch. In order to effectively reduce image flicker, the gate voltage difference ΔV G  needs to be lowered first before adjusting the common voltage Vcom for compensating the feed-through voltage V FD . 
       FIGS. 2 and 3  are diagrams illustrating methods for driving the prior art LCD device  100 .  FIG. 2  shows the waveforms of the control signal YOE and the gate driving signals SG 1 -SG 4  when the gate driver  120  is an external circuit.  FIG. 3  shows the waveforms of the clock signals CK, CKB, O_CK, O_CKB, the output enable signal OE and the gate driving signals SG 1 -SG 4  when the gate driver  120  is fabricated using GOA technique. 
     In the driving method depicted in  FIG. 2 , the length of the enable period in the gate driving signals SG 1 -SG 4  is determined by the pulse width of the control signal YOE, and the length of the signal falling time in the gate driving signals SG 1 -SG 4  is determined by the signal falling start point of the control signals YOE and YV 1 C. In each period, the control signal YOE remains at high level for a constant length, and the waveform of the control signal YV 1 C starts to fall at the same point. Therefore, the gate driving signals SG 1 -SG 4  result in an identical gate voltage difference ΔV G ′ when turning off corresponding TFT switches. As previously stated, the feed-through voltage is proportional to the gate voltage difference. Since the gate voltage difference ΔV G ′ after voltage trimming is smaller than the gate voltage difference ΔV G  without voltage trimming, the effect of the feed-through voltage can be compensated. 
     In the driving method depicted in  FIG. 3 , the clock signals CK and CKB having opposite phases switch between high/low voltage levels based on a predetermined period which determines the length of the enable period in the gate driving signals SG 1 -SG 4 . When the output enable signal OE is at high level, the gate driver  120  outputs the clock signals CK and CKB for providing the corresponding clock signals O_CK and O_CKB. When the output enable signal OE is at low level, the gate driver  120  stops outputting the clock signals CK and CKB. Charge-sharing is then performed between the clock signals O_CK and O_CKB, thereby achieving voltage trimming at the signal falling edge. The gate driving signals SG 1 -SG 4  can thus be provided according to the clock signals O_CK and O_CKB after charge-sharing. In each period, the output enable signal OE remains at low level for a constant length T, the degree of voltage trimming in the gate driving signals SG 1 -SG 4  is identical. Therefore, the gate driving signals SG 1 -SG 4  result in an identical gate voltage difference ΔV G ′ when turning off corresponding TFT switches. As previously stated, the feed-through voltage is proportional to the gate voltage difference. Since the gate voltage difference ΔV G ′ after voltage trimming is smaller than the gate voltage difference ΔV G  without voltage trimming, the effect of the feed-through voltage can be compensated. 
     In the prior art LCD device  100 , the pixel units are disposed on both sides of each data line, wherein the pixel units PX L  disposed on the left side of the data lines are controlled by the gate driving signals SG 1 , SG 3 , . . . , SG n-1  transmitted from the odd-numbered gate lines, while the pixel units PX R  disposed on the right side of the data lines are controlled by the gate driving signals SG 2 , SG 4 , . . . , SG n  transmitted from the even-numbered gate lines. Normally adopting different designs, these two types of pixel units PX L  and PX R  have different C LC , C ST , C GS  or C GD , and the value of the feed-through voltage V FD  also varies. Even if the two types of pixel units PX L  and PX R  adopt the same design, the value of the feed-through voltage V FD  may also vary due to characteristic shift caused by manufacturing process deviations, For example, the process shift between the first metal layer M 1  and the second metal layer M 2  may result in different C GD  values of the pixel units PX L  and PX R . 
     In the driving methods depicted in  FIGS. 2 and 3 , the gate voltage difference of each pixel is lowered by the same degree. Since each pixel has different feed-through voltage, image flicker can not be effectively reduced by adjusting the common voltage Vcom. 
     SUMMARY OF THE INVENTION 
     The present invention provides an LCD device which improves image flicker, comprising a first gate line for transmitting a first gate driving signal; a second gate line adjacent and parallel to the first gate line for transmitting a second gate driving signal; a data line perpendicular to the first and second gate lines for transmitting data driving signals; a first pixel disposed at an intersection of the data line and the first gate line and on a first side of the data line, and for displaying images according to the first gate driving signal and a received data driving signal; a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line, and for displaying images according to the second gate driving signal and a received data driving signal; a trimming circuit for generating a trimming signal according to the parasite capacitances of the first and second pixels; and a gate driver for generating the first and second gate driving signals by adjusting a signal falling edge of a gate pulse signal according to the trimming signal, wherein a signal falling edge of the first gate driving signal falls from a high level to a first level, and a signal falling edge of the second gate driving signal falls from the high level to a second level. 
     The present invention also provides a method for driving an LCD device which comprises a data line, two adjacent first and second gate lines, a first pixel disposed at an intersection of the data line and the first gate line and on a first side of the data line, and a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line. The method comprises providing a gate pulse signal; generating a first gate driving signal by adjusting the gate pulse signal according to a parasite capacitance of the first pixel, wherein a signal falling edge of the first gate driving signal falls from a high level to a first level; generating a second gate driving signal by adjusting the gate pulse signal according to a parasite capacitance of the second pixel, wherein a signal falling edge of the second gate driving signal falls from the high level to a second level; and outputting the first and second gate driving signals to the first and second gate lines for driving the first and second pixels, respectively. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a prior art LCD device which adopts HSD structure. 
         FIGS. 2 and 3  are diagrams illustrating methods for driving the prior art LCD device. 
         FIGS. 4 and 5  are diagrams of LCD devices which adopt HSD structure according to the present invention. 
         FIG. 6  is a timing diagram illustrating a method for driving the LCD device according to a first embodiment of the present invention. 
         FIG. 7  is a diagram illustrating the trimming circuit capable of performing the driving method according to the first embodiment of the present invention. 
         FIG. 8  is a timing diagram illustrating a method for driving the LCD device according to a second embodiment of the present invention. 
         FIG. 9  is a diagram illustrating the trimming circuit capable of performing the driving method according to the second embodiment of the present invention. 
         FIG. 10  is a timing diagram illustrating a method for driving the LCD device according to a third embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 4 and 5  are diagrams of LCD devices  200  and  300  which adopt HSD structure according to the present invention. The LCD devices  200  and  300  each include a source driver  210 , a gate driver  220 , a timing controller  230 , a trimming circuit  240 , a plurality of data lines DL 1 -DL m , a plurality of gate lines GL 1 -GL n , and a pixel matrix. The pixel matrix of the LCD device  200  includes a plurality of pixel units PX L  and PX R , and the pixel matrix of the LCD device  300  includes a plurality of pixel units PX LU , PX LB , PX RU  and PX RB . Each of the pixel units includes a TFT switch, a liquid crystal capacitor C LC  and a storage capacitor C ST  respectively coupled to a corresponding data line, a corresponding gate line and a common node. The timing controller  230  can generate control signals YOE and YV 1 C, clock signals CK and CKB or an output enable signal OE for operating the source driver  210  and the gate driver  220 . The source driver  210  can generate data driving signals SD 1 -SD m  corresponding to display images. If the gate driver  220  is an external driving circuit, the trimming circuit  240  generates a trimming signal V TRIM  according to the control signal YV 1 C and the parasite capacitance of the pixel units, and the gate driver  220  then generates the gate driving signals SG 1 -SG n  for turning on the TFT switches according to the control signal YOE and the trimming signal V TRIM ; if the gate driver  220  is fabricated using GOA technique, the trimming circuit  240  generates a trimming signal V TRIM  according to the output enable signal OE and the parasite capacitance of the pixel units, and the gate driver  220  then generates the gate driving signals SG 1 -SG n  for turning on the TFT switches according to the clock signals CK, CKB and the trimming signal V TRIM . 
     In the LCD device  200  according to the present invention, the pixel units are disposed on both sides of each data line, wherein the first type of pixel units PX L  disposed on the left side of the data lines are controlled by the gate driving signals SG 1 , SG 3 , . . . , SG n-1  transmitted from the odd-numbered gate lines, while the second type of pixel units PX R  disposed on the right side of the data lines are controlled by the gate driving signals SG 2 , SG 4 , . . . , SG n  transmitted from the even-numbered gate lines. Normally adopting different designs, these two types of pixel units PX L  and PX R  have different C LC , C ST , C GS  or C GD /and the value of the feed-through voltage V FD  also varies. Even if the two types of pixel units PX L  and PX R  adopt the same design, the value of the feed-through voltage V FD  may also vary due to characteristic shift caused by manufacturing process deviations. 
     In the LCD device  300  according to the present invention, the pixel units are disposed on both sides of each data line, wherein the first type of pixel units PX LU  disposed on the left side of the data lines are controlled by the gate driving signals SG 1 , SG 5 , . . . , SG n-3  transmitted from the gate lines GL 1 , GL 5 , . . . , GL n-3 , the second type of pixel units PX RB  disposed on the right side of the data lines are controlled by the gate driving signals SG 2 , SG 6 , . . . , SG n-2  transmitted from the gate lines GL 2 , GL 6 , . . . , GL n-2 , the third type of pixel units PX RU  disposed on the right side of the data lines are controlled by the gate driving signals SG 3 , SG 7 , . . . , SG n-1  transmitted from the gate lines GL 3 , GL 7 , . . . , GL n-1 , the fourth type of pixel units PX LB  disposed on left side of the data lines are controlled by the gate driving signals SG 4 , SG 8 , . . . , SG n  transmitted from the gate lines GL 4 , GL 8 , . . . , GL n  (assuming n is a multiple of 4). Normally adopting different designs, these four types of pixel units PX LU , PX LB , PX RU  and PX RB  have different C LC , C ST , C GS  or C GD /and the value of the feed-through voltage V FD  also varies. Even if the four types of pixel units PX LU , PX LB , PX RU  and PX RB  adopt the same design, the value of the feed-through voltage V FD  may also vary due to characteristic shift caused by manufacturing process deviations. 
     In the present invention, the gate driving signals SG 1 -SG n  with trimmed signal falling edges are used for reducing the gate voltage differences. Meanwhile, the degree of voltage trimming is adjusted according to the parasite capacitance of the pixel units, so that the gate driving signals SG 1 -SG n  result in various gate voltage differences ΔV G1 -ΔV Gn  when turning off corresponding TFT switches. In the LCD device  300  for instance, the gate driving signals SG 1 -SG 4  with different trimmed signal falling edges are used for driving the four types of pixel units, thereby resulting in various gate voltage differences ΔV G1 -ΔV G4  when turning off corresponding TFT switches. The capacitance percentages K 1 -K 4  of the four types of the pixel units which influence the feed-through voltage differently can thus be compensated. Since the feed-through voltages V FD1 -ΔV FD4  of the four types of the pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced. 
       FIG. 6  is a timing diagram illustrating a method for driving the LCD device  200  or  300  when the gate driver  310  is an external driving circuit according to a first embodiment of the present invention.  FIG. 6  shows the waveforms of the control signal YOE and YV 1 C, the trimming signal V TRIM  and the gate driving signals SG 1 -SG 4 . In the driving method depicted in  FIG. 6 , the control signal YOE remains at high level for a constant length in each period, and the length of the enable period in the gate driving signals SG 1 -SG 4  is determined by the pulse width of the control signal YOE. The signal falling edge start points in each period of the control signal YV 1 C vary according to the parasite capacitances of the pixel units. The total lengths of the signal falling time T 1 -T 4  of the gate driving signals SG 1 -SG 4  are determined by the signal falling start points of the control signals YOE and YV 1 C in corresponding periods. The trimming circuit  340  first generates the trimming signal V TRIM  having distinct signal falling edge start points in corresponding periods according to the control signal YV 1 C and the capacitance percentages K 1 -K 4 . The gate driver  320  then generates the gate driving signals SG 1 -SG 4  having distinct trimmed signal falling edges in corresponding periods according to the control signal YOE and the trimming signal V TRIM . The gate driving signals SG 1 -SG 4  result in different gate voltage differences ΔV G1 -ΔV G4  when the control signal YOE switches from high level to low level. Assuming the relationship of the capacitance percentages is K 1 &lt;K 2 &lt;K 3 &lt;K 4 , then the relationship of the total lengths of the signal falling time is T 1 &lt;T 2 &lt;T 3 &lt;T 4 , and the relationship of the gate voltage differences is thus ΔV G1 &gt;ΔV G2 &gt;ΔV G3 &gt;ΔV G4 . As previously stated, the feed-through voltage is proportional to the multiple of the capacitance percentage and the gate voltage difference. When K 1 &lt;K 2 &lt;K 3 &lt;K 4 , the first embodiment of the present invention provides the gate driving signals SG 1 -SG 4  which result in gate voltage differences having the relationship of ΔV G1 &gt;ΔV G2 &gt;ΔV G3 &gt;ΔV G4 . Since the feed-through voltages of each type of pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced by adjusting the common voltage Vcom. 
       FIG. 7  is a diagram illustrating the trimming circuit  340  capable of performing the driving method according to the first embodiment of the present invention. The trimming circuit  340  in  FIG. 7 , including an inverter  70 , a level shifter  72 , a slope-adjusting circuit  74 , and transistor switches QP and QN, can generate the trimming signal V TRIM  according to the control signal YV 1 C. When the control signal YV 1 C is at high level, the transistor switch QP is turned on and the transistor switch QN is turned off, and the trimming signal V TRIM  is at a high level VGH. When the control signal YV 1 C is at low level, the transistor switch QP is turned off and the transistor switch QN is turned on, and the level of the trimming signal V TRIM  is pulled down to low level via the resistor R 1  of the slope-adjusting circuit  74 . Therefore in the embodiments of  FIGS. 6 and 7 , the trimming circuit  340  receives the control signal YV 1 C having distinct signal falling edge start points, and then provides the trimming signal V TRIM  having a slope at the signal falling edge. The slope-adjusting circuit  74  can be an impedance device, such as a resistor or a variable resistor. 
       FIG. 8  is a timing diagram illustrating a method for driving the LCD device  200  or  300  when the gate driver  310  is an external driving circuit according to a second embodiment of the present invention.  FIG. 8  shows the waveforms of the control signal YOE and YV 1 C, the trimming signal V TRIM  and the gate driving signals SG 1 -SG 4 . In the driving method depicted in  FIG. 8 , the control signal YOE remains at high level for a constant length in each period, and the length of the enable period in the gate driving signals SG 1 -SG 4  is determined by the pulse width of the control signal YOE. The signal falling edge start points in each period of the control signal YV 1 C vary according to the parasite capacitances of the pixel units. The waveform of the control signal YV 1 C starts to fall at the same point in each period, thereby resulting in an identical total length of the signal falling time T in the gate driving signals SG 1 -SG 4 . The slopes m 1 -m 4  of the signal falling edges in the gate driving signals SG 1 -SG 4  are determined by the trimming circuit  340 . The trimming circuit  340  first generates the trimming signal V TRIM  having distinct signal falling edge slopes in corresponding periods according to the control signal YV 1 C and the capacitance percentages K 1 -K 4 . The gate driver  320  then generates the gate driving signals SG 1 -SG 4  having distinct trimmed signal falling edges in corresponding periods according to the control signal YOE and the trimming signal V TRIM . The gate driving signals SG 1 -SG 4  result in different gate voltage differences ΔV G1 -ΔV G4  when the control signal YOE switches from high level to low level. Assuming the relationship of the capacitance percentages is K 1 &lt;K 2 &lt;K 3 &lt;K 4 , then the relationship of the signal falling edge slopes is m 1 &lt;m 2 &lt;m 3 &lt;m 4 , and the relationship of the gate voltage differences is thus ΔV G1 &gt;ΔV G2 &gt;ΔV G3 &gt;ΔV G4 . As previously stated, the feed-through voltage is proportional to the multiple of the capacitance percentage and the gate voltage difference. When K 1 &lt;K 2 &lt;K 3 &lt;K 4 , the second embodiment of the present invention provides the gate driving signals SG 1 -SG 4  which result in gate voltage differences having the relationship of ΔV G1 &gt;ΔV G2 &gt;ΔV G3 &gt;ΔV G4 . Since the feed-through voltages of each type of pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced by adjusting the common voltage Vcom. 
       FIG. 9  is a diagram illustrating the trimming circuit  340  capable of performing the driving method according to the second embodiment of the present invention. The trimming circuit  340  in  FIG. 9 , including an inverter  70 , a level shifter  72 , a slope-adjusting circuit  94 , and transistor switches QP and QN, can generate the trimming signal V TRIM  according to the control signal YV 1 C. When the control signal YV 1 C is at high level, the transistor switch QP is turned on and the transistor switch QN is turned off, and the trimming signal V TRIM  is at a high level VGH. When the control signal YV 1 C is at low level, the transistor switch QP is turned off and the transistor switch QN is turned on, and the level of the trimming signal V TRIM  is pulled down to low level via the resistor R 1  of the slope-adjusting circuit  94 . The slope-adjusting circuit  94 , including a resistor R 1 , a variable resistor R 2 , and switches S 1  and S 2 , can provide different equivalent resistances according to the capacitance percentages K 1 *K 4  and can pull down the level of the trimming signal V TRIM  using an adequate slope. Therefore in the embodiments of  FIGS. 8 and 9 , the trimming circuit  340  receives the control signal YV 1 C having identical signal falling edge start points, and then provides the trimming signal V TRIM  having distinct slopes at the signal falling edge using the slope-adjusting circuit  94 . 
       FIG. 10  is a timing diagram illustrating a method for driving the LCD device  200  or  300  when the gate driver  310  is fabricated using GOA technique according to a third embodiment of the present invention.  FIG. 10  shows the waveforms of the clock signals CK, CKB, O_CK and O_CKB, the output enable signal OE and the gate driving signals SG 1 -SG 4 . In the driving method depicted in  FIG. 8 , the clock signals CK and CKB having opposite phases switch between high/low voltage levels based on a predetermined period which determines the length of the enable period in the gate driving signals SG 1 -SG 4 . The trimming circuit  340  first generates a trimming signal OE TRIM  having distinct disable lengths (low level) T 1 -T 4  in corresponding periods according to the enable signal OE and the capacitance percentages K 1 -K 4 . The gate driver  320  then outputs the clock signals CK and CKB for providing the clock signals O_CK and O_CKB. When the trimming signal OE TRIM  is at high level, the gate driver  220  outputs the clock signals CK and CKB for providing the corresponding clock signals O_CK and O_CKB. When the trimming signal OE TRIM  is at low level, the gate driver  220  stops outputting the clock signals CK and CKB. Charge-sharing is then performed between the clock signals O_CK and O_CKB, thereby achieving voltage trimming at the signal falling edge. The gate driver  320  then generates the gate driving signals SG 1 -SG 4  having distinct trimmed signal falling edges in corresponding periods according to the clock signals OCK and O_CKB. 
     The gate driving signals SG 1 -SG 4  result in different gate voltage differences ΔV G1 -ΔV G4  when the corresponding clock signals O_CK and O_CKB switch from high level to low level. Assuming the relationship of the capacitance percentages is K 1 &lt;K 2 &lt;K 3 &lt;K 4 , then the relationship of the disable lengths is T 1 &lt;T 2 &lt;T 3 &lt;T 4 , and the relationship of the gate voltage differences is thus ΔV G1 &gt;ΔV G2 &gt;ΔV G3 &gt;ΔV G4 . As previously stated, the feed-through voltage is proportional to the multiple of the capacitance percentage and the gate voltage difference. When K 1 &lt;K 2 &lt;K 3 &lt;K 4 , the third embodiment of the present invention provides the gate driving signals SG 1 -SG 4  which result in gate voltage differences having the relationship of ΔV G1 &gt;ΔV G2 &gt;ΔV G3 &gt;ΔV G4 . Since the feed-through voltages of each type of pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced by adjusting the common voltage Vcom. 
     The present invention can adjust the total length or the slope of the signal falling edge in the gate driving signals SG 1 -SG 4  according to the capacitance percentages K 1 -K n  of the pixel units. Different parasite capacitances can be compensated by various voltage differences ΔV G1 -ΔV Gn  so that the feed-through voltages of each type of pixel units are substantially the same. The present invention can effectively reduce image flicker the by adjusting the common voltage Vcom, and thus provide better display quality. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Technology Classification (CPC): 6