Patent Abstract:
A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.

Full Description:
[0001]    This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application U.S. Patent Application Ser. No. 61/132,122, filed on Jun. 16, 2008, assigned to the same assignee as the present invention, and incorporated herein by reference in its entirety. 
         [0002]    This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application U.S. Patent Application Ser. No. 61/132,628, filed on Jun. 20, 2008, assigned to the same assignee as the present invention, and incorporated herein by reference in its entirety. 
       Related Patent Applications 
       [0003]    U.S. patent application Ser. No. 12/387,771, filed on May 7, 2009, assigned to the same assignee as the present invention. 
         [0004]    Attorney Docket AP08-005, U.S. patent application Ser. No. 12/455,337, filed on Jun. 1, 2009 assigned to the same assignee as the present invention. 
         [0005]    Attorney Docket AP08-006, U.S. patent application Ser. No. ______, filed on ______, assigned to the same assignee as the present invention. 
         [0006]    Attorney Docket AP08-008, U.S. patent application Ser. No. ______, assigned to the same assignee as the present invention. 
     
    
     BACKGROUND OF THE INVENTION  
       [0007]    1. Field of the Invention 
         [0008]    This invention relates generally to nonvolatile memory array structure and operation. More particularly, this invention relates to flash based EEPROM nonvolatile memory device structures, peripheral circuits for operating flash based EEPROM nonvolatile memory devices and methods for operation of flash based EEPROM nonvolatile memory devices. 
         [0009]    2. Description of Related Art 
         [0010]    Nonvolatile memory is well known in the art. The different types of nonvolatile memory include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the Flash Memory has become one of the more popular types of Nonvolatile Memory. All EEPROM, NOR and NAND flash are Electrically Erasable and Programmable Memory using a single low-voltage power supply VDD but only EEPROM offers an erase size in unit of bytes and page with  1  M program/erase cycles. 
         [0011]    The Flash Memory structures known in the art employ a charge retaining mechanism such as a charge storage phenomena and a charge trapping phenomena. The charge storage mechanism, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell determine that digital data stored. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiN x ). 
         [0012]    NOR flash provides a fast random-access, asynchronous read, but NAND flash offers a slow serial-access, synchronous read. NOR flash is the high pin-count memory chip with multiple external address and data pins, and control signal pins. One disadvantage of NOR flash is as the density being doubled, the number of its required external pin count would increase by one due to the adding of one more external address pin. In contrast, NAND has advantage of less pin-count than NOR with no address input pins. As density increases, NAND&#39;s pin count is always kept constant. Both today&#39;s NAND and NOR flash provide the advantage of in-system program and erase capabilities with 100K endurance cycles spec. NOR flash is used to store fast program code but NAND is used to store huge slow serial audio and video data storage. The size of the memory units that are erased in a NOR and NAND flash is presently around 1M bits in a giga-bit density memory device. Alternately, an EEPROM provides a unit of erase that is capable of storing a byte and a page, to permit alteration of small quantities of data or parameters. 
         [0013]    Up until 2008, the EEPROM designs were based on a semiconductor manufacturing process where the transistor devices had a drain-to-source breakdown voltage (BVDS) of approximately ±16V. In 2008, the semiconductor manufacturing processing moved to having feature sizes less than 0.13 μm. The current EEPROM design employ program and erase voltage levels of approximately +15.0V. The current EEPROM memory cell is designed having a polycrystalline silicon floating-gate placed over a tunneling oxide. A polycrystalline control gate is formed over an inter-polycrystalline silicon oxide layer above the floating gate. Low current Fowler-Nordheim channel erase operation is used to increase the threshold voltage Vt of the memory cell above the desired value of +2.0V to store a digital datum of a logical “1”. A low-current Fowler-Nordheim channel program operation is used to decrease threshold voltage Vt of the memory cell to a voltage level of approximately −2.0V to store digital datum of a logical “0”. 
         [0014]    The advantage of an EEPROM memory device is its high 1M program/erase cycles and its ability to be programmed in units of byte and page. However, a disadvantage of an EEPROM memory device is that the physical size of a memory cell is very large and not scalable. The averaged cell size is more than 80 λ 2  and because of the inability to be scaled the manufacturing technology is employing feature sizes of approximately 0.18μ. And as noted above, the EEPROM designs were based on a drain-to-source breakdown voltage (BVDS) of approximately ±16V. 
       SUMMARY OF THE INVENTION  
       [0015]    An object of this invention is to provide a method for operating an array of EEPROM connected flash nonvolatile memory cells at increments of a page and block while minimizing operational disturbances and providing bias operating conditions to prevent drain to source breakdown drain to source breakdown in peripheral devices. 
         [0016]    Another object of this invention is to provide a row decoder circuit for selecting nonvolatile memory cells of an array of EEPROM connected nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells of the array of the EEPROM connected nonvolatile memory cells while minimizing operational disturbances and preventing drain to source breakdown drain to source breakdown in peripheral devices. 
         [0017]    Further, another object of this invention is to provide a select gate decoder circuit for selecting and providing biasing conditions to selected nonvolatile memory cells of an array of EEPROM connected nonvolatile memory cells for reading, programming, verifying, and erasing the selected nonvolatile memory cells of the array of the EEPROM connected nonvolatile memory cells while minimizing operational disturbances and preventing drain to source breakdown drain to source breakdown of peripheral devices. 
         [0018]    To accomplish at least one of these objects, a nonvolatile memory device includes an array of nonvolatile memory cells arranged in rows and columns. The nonvolatile memory cells are connected into an EEPROM configuration where the nonvolatile memory cells located on each column are connected such that the drains of each of the nonvolatile memory cells are commonly connected to a bit line associated with each column. The nonvolatile memory cells on each row are commonly connected to a word line. The nonvolatile memory cells on two adjacent rows are commonly connected to a select gate control line. The array of nonvolatile memory cells is placed in an isolation well of a first impurity type. The array of the nonvolatile memory cells is divided into blocks and each block is divided into pages. Each page includes one row of the nonvolatile memory cells within each block of each block connected to a word line. 
         [0019]    The EEPROM configured nonvolatile memory cells each have a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The drain of the floating gate memory transistor is connected to the source of the floating gate select transistor and the drain of the floating gate select transistor is connected to the bit line that is commonly connected with one column of the EEPROM configured nonvolatile memory cells. The source of the floating gate memory transistor is connected to a source line that is commonly connected with the one row of the EEPROM configured nonvolatile memory cells. A gate of the floating gate select transistor is connected to the connected to a select gate control line associated with one row of the EEPROM configured memory cells for receiving a select gate control biasing voltages for selectively activating the floating gate select transistor to connect the floating gate memory transistor to the bit line for reading, programming, and erasing the floating gate memory cell. The gate of the floating gate memory cell is connected to the word line for receiving operational biasing voltages for reading, programming, and erasing the floating gate memory transistor. 
         [0020]    The nonvolatile memory device has a row decoder that has a first block selector that sets a block signal when a block address indicates that a block is selected. The row decoder further includes a word line selector circuit, which based on a row address provides the word lines with word line operational biasing voltage levels necessary for biasing the control gates of the EEPROM configured nonvolatile memory cells for reading, programming, verifying, and erasing. The row decoder has a voltage level shifter for shifting a voltage level of a block select signal to activate pass gates to transfer the operational biasing voltage levels to the word lines of the selected block for biasing the control gates of the EEPROM configured nonvolatile memory cells of the block for reading, programming, verifying, and erasing the selected nonvolatile memory cells. 
         [0021]    The nonvolatile memory device has a select gate decoder circuit is connected to each select gate control line within each block to transfer a necessary gate select biasing voltage for reading, programming, verifying, and erasing selected EEPROM configured nonvolatile memory cells to selected select gate control lines. The select gate decoder circuit has a second block selector circuit which activates for the selection of the block being addressed. The block selector circuit is connected to a select gate voltage level shifter that shifts the voltage level of the block selector signals for activating pass transistors to transfer select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor of each of the EEPROM configured nonvolatile memory cells of the selected block for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. 
         [0022]    The nonvolatile memory device has a column decoder in communication with bit lines for providing biasing voltages for reading, programming, verifying, and erasing selected EEPROM configured nonvolatile memory cells. The row decoder, select gate decoder, and column decoder provide inhibit biasing voltage levels to all the non-selected nonvolatile EEPROM configured nonvolatile memory cells to minimize disturbances resulting from the reading, programming, verifying, and erasing selected EEPROM configured nonvolatile memory cells. Further the row decoder, select gate decoder, and column decoder generate the word line biasing voltages, the select gate biasing voltage, bit line biasing voltages, and the inhibit biasing voltages such that an amplitude of the word line biasing voltages, the select gate biasing voltage, bit line biasing voltages, and the inhibit biasing voltages does not exceed a drain-to-source break down voltage of transistors forming the row decoder, select gate decoder, and column decoder. 
         [0023]    For reading a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a read reference biasing voltage level to the word line of the selected EEPROM configured nonvolatile memory cells. The row decoder further transfers read reference biasing voltage level to the word lines of the unselected EEPROM configured nonvolatile memory cells in the selected and unselected blocks. The column decoder transfers a first read biasing voltage to the drains of the selected EEPROM configured nonvolatile memory cells and the voltage level of the ground reference voltage source to the drains of the unselected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The first read biasing voltage has a voltage level of approximately +1.0V. The read reference biasing voltage level is approximately the voltage level of the power supply voltage source VDD, where voltage level of the power supply voltage source is either 1.8V or 3.0V. The bit lines are is pre-charged to the voltage level of the first read voltage of approximately the 1.0V. The pre-charged level of the first read voltage is discharged to approximately 0.0V when the memory cell has been programmed and has a threshold voltage level less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the first read level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary erased threshold voltage level of approximately +4.0V. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0024]    For erasing a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high positive erase voltage to the word line of the selected EEPROM configured nonvolatile memory cells and transfers the ground reference voltage level to the word lines of the unselected EEPROM configured nonvolatile memory cells of the selected block. The row decoders of the unselected blocks of EEPROM configured nonvolatile memory cells disconnect the word lines of the unselected EEPROM configured nonvolatile memory cells so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The select gate decoder transfers the very high negative erase voltage to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to an isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the select gate decoder. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −10.0V to approximately −8.0V. 
         [0025]    For verifying a page erase, a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage level to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the second read voltage is pre-charged to approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage level is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the second read voltage level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0026]    For erasing a selected block of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high positive erase voltage to all the word lines of the EEPROM configured nonvolatile memory cells of the selected block. The row decoders of the unselected blocks of EEPROM configured nonvolatile memory cells disconnect the word lines of the unselected EEPROM configured nonvolatile memory cells so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The select gate decoder transfers the very high negative erase voltage to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the very high negative erase voltage. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the select gate decoder. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. 
         [0027]    For verifying a block erase, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage level to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the second read voltage level is pre-charged to approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage level is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the second read voltage level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0028]    For erasing an entire chip containing the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high positive erase voltage to all the word lines of the EEPROM configured nonvolatile memory cells of the entire chip. The select gate decoder transfers the very high negative erase voltage to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the select gate decoder. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. 
         [0029]    For verifying erasing an entire chip, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage level to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the second read voltage is pre-charged to approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V. 
         [0030]    For programming a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high negative program voltage to the word line of the selected EEPROM configured nonvolatile memory cells. The row decoder transfers a second negative program inhibit voltage to the word lines of the unselected word lines is the selected block and the unselected blocks of the array of EEPROM configured nonvolatile memory cells. The column decoder transfers a high program select voltage level to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are to be programmed. The column decoder transfers a low program deselect voltage level to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are not to be programmed. The select gate decoder transfers a high positive activate control signal to the select gate control lines connected to the selected nonvolatile voltage cells and transfers a low deactivate select gate signal to the select gate control lines connected to the selected nonvolatile voltage cells to allow them to float. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The voltage level of the very high negative program voltage and the high positive program select voltage are less than the breakdown voltage level of transistors forming the row decoder. The voltage level of the high negative program voltage is from approximately −8.0V to approximately −10.0V. The high program select voltage is from approximately +8.0V to approximately +10.0V and the low program deselect voltage level is from approximately −2.0V to the voltage level of the ground reference voltage source (0.0V) to avoid programming of the unselected EEPROM configured nonvolatile memory cells. 
         [0031]    For verifying a page program, a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a voltage level of a upper boundary of programmed threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage level to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The upper boundary of an programmed threshold voltage level is approximately +1.0V for the single level cell program. The bit line is pre-charged to the voltage level of the second read voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage level is discharged to approximately 0.0V when the memory cell has been successfully programmed and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are not successfully programmed, the pre-charged level will be maintained when the threshold voltage of the programmed EEPROM configured nonvolatile memory cells is greater than the upper boundary of the programmed threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0032]    In other embodiments, a method for operating an array includes steps for providing the operating conditions for reading, page erasing, block erasing, chip erasing, page erase verifying, block erase verifying, chip erase verifying, page programming, and page program verifying of selected EEPROM configured nonvolatile memory cells of the array of EEPROM configured nonvolatile memory cells. For the step of reading a selected page of the array of EEPROM configured nonvolatile memory cells, a read reference biasing voltage level is transferred to the word line of the selected EEPROM configured nonvolatile memory cells. A read reference biasing voltage level is transferred to the word lines of the word lines of the unselected EEPROM configured nonvolatile memory cells in the selected and unselected blocks. A bit line read biasing voltage is transferred to the drains of the selected EEPROM configured nonvolatile memory cells and the voltage level of the ground reference voltage source is transferred to the drains of the unselected EEPROM configured nonvolatile memory cells. An activate select gate signal is transferred to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The bit line read biasing voltage has a voltage level of approximately +1.0V. The read biasing voltage level is approximately the voltage level of the power supply voltage source VDD, where power supply voltage source is either 1.8V or 3.0V. The voltage level of the bit lines is pre-charged to the first read voltage level. The pre-charged level of the first read voltage is discharged to approximately 0.0V when the memory cell has been successfully programmed and has a threshold voltage level is less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells are not successfully programmed, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the upper boundary of the programmed threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0033]    For the step of erasing a selected page of the array of EEPROM configured nonvolatile memory cells, a very high positive erase voltage is transferred to the word line of the selected EEPROM configured nonvolatile memory cells and the word lines of the unselected EEPROM configured nonvolatile memory cells of the selected block are set to the ground reference voltage level. The word lines of the unselected EEPROM configured nonvolatile memory cells are disconnected and allowed to float so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The very high negative erase voltage is applied to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to an isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −10.0V to approximately −8.0V. 
         [0034]    For the step of verifying a page erase, a selected page of the array of EEPROM configured nonvolatile memory cells, a voltage level of a lower boundary of an erased threshold voltage level is transferred to the word lines of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is applied to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and a deactivate select gate signal is applied to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the bit lines is pre-charged to second read voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor wherein the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0035]    For the step of erasing a selected block of the array of EEPROM configured nonvolatile memory cells, a very high positive erase voltage is applied to all the word lines of the EEPROM configured nonvolatile memory cells of the selected block. The word lines of the unselected EEPROM configured nonvolatile memory cells of the unselected blocks are disconnected so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The very high negative erase voltage is applied to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the very high negative erase voltage. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage is approximately the breakdown voltage level of transistors. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. 
         [0036]    For the step of verifying a block erase, a voltage level of a lower boundary of an erased threshold voltage level is applied to the word lines of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is applied to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the bit lines are pre-charged to the second read voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
         [0037]    For the step of erasing an entire chip containing the array of EEPROM configured nonvolatile memory cells, a very high positive erase voltage is applied to all the word lines of the EEPROM configured nonvolatile memory cells of the entire chip. The very high negative erase voltage is applied to the all the select gate control lines of the EEPROM configured nonvolatile memory cells of the entire chip. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage is less than approximately the breakdown voltage level of transistors. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. 
         [0038]    For the step verifying erasing an entire chip, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is transferred to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the bit lines is pre-charged to the second read voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V. 
         [0039]    For the step of programming a selected page of the array of EEPROM configured nonvolatile memory cells, a very high negative program voltage is applied to the word line of the selected EEPROM configured nonvolatile memory cells. A second negative program inhibit voltage is applied to the word lines of the unselected word lines is the selected block and the unselected blocks of the array of EEPROM configured nonvolatile memory cells. A high program select voltage level is applied to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are to be programmed. A low program deselect voltage level is applied to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are not to be programmed. A high positive activate control signal is transferred to the select gate control lines connected to the selected nonvolatile voltage cells and a low deactivate select gate signal is transferred to the select gate control lines connected to the unselected nonvolatile voltage cells to allow them to float. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The voltage level of the very high negative program voltage is less than the breakdown voltage level of transistors forming the row decoder. The voltage level of the high negative program voltage is from approximately −8.0V to approximately −10.0V. The high program select voltage is from approximately +8.0V to approximately +10.0V and the low program deselect voltage level is from approximately −2.0V to the voltage level of the ground reference voltage source (0.0V) to avoid programming of the unselected EEPROM configured nonvolatile memory cells. 
         [0040]    For the step of verifying a page program, a selected page of the array of EEPROM configured nonvolatile memory cells, a voltage level of an upper boundary of an programmed threshold voltage level is applied to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is transferred to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and a deactivate select gate signal is transferred to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The upper boundary of an programmed threshold voltage level is approximately +1.0V for the single level cell program. The voltage level of the bit lines is pre-charged to the second read voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read voltage is discharged to approximately 0.0V when the memory cell has been successfully programmed and has a threshold voltage level is less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells are not programmed, the pre-charged level will be maintained when the threshold voltage of the programmed EEPROM configured nonvolatile memory cells is greater than the upper boundary of the threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0041]      FIG. 1   a  is schematic diagram of an embodiment of a two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention. 
           [0042]      FIG. 1   b  is a top plan view of an embodiment of two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention. 
           [0043]      FIG. 1   c  is a cross sectional cross sectional view of an embodiment of two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention. 
           [0044]      FIG. 2   a  is a graph of the single threshold voltage distribution of a floating gate select transistor of a two floating-gate transistor EEPROM configured memory cell having a single threshold voltage level embodying the principles of the present invention. 
           [0045]      FIG. 2   b  is a graph of two threshold voltage distributions of two floating-gate transistor EEPROM configured memory cell having a single positive program level and a positive erase level. 
           [0046]      FIGS. 3   a - 3   d  are simplified schematic diagrams of an array of two floating-gate transistor EEPROM configured memory cells illustrating the bias conditions for reading, programming, page erasing and chip erasing of two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention. 
           [0047]      FIG. 4  is a block diagram of a nonvolatile memory device embodying the principles of the present invention. 
           [0048]      FIG. 5  is a schematic diagram illustrating an array of two floating-gate transistor EEPROM configured memory cells of  FIG. 4  embodying the principles of the present invention. 
           [0049]      FIG. 6   a  is a schematic diagram of a block row decoder of the nonvolatile memory device of  FIG. 4  embodying the principles of the present invention. 
           [0050]      FIG. 6   b  is a schematic diagram of select gate decoder of the nonvolatile memory device of  FIG. 4  embodying the principles of the present invention. 
           [0051]      FIG. 7  is a schematic diagram of a level shifter circuit of the block row decoders of  FIG. 6  embodying the principles of the present invention. 
           [0052]      FIG. 8  is flow chart for the method for operating the nonvolatile memory device of  FIG. 4 . 
           [0053]      FIG. 9  is flow chart for the method for erasing and erase verifying a page, block, or chip of the nonvolatile memory device of  FIG. 4 . 
           [0054]      FIG. 10  is flow chart for the method for programming and program verifying a page of the nonvolatile memory device of  FIG. 4 . 
           [0055]      FIG. 11  is a table illustrating the voltage conditions applied to the two floating-gate transistor EEPROM configured memory cells of  FIG. 5  incorporated in the nonvolatile memory device embodying the principles of the present invention. 
           [0056]      FIG. 12   a  is a table illustrating the voltage conditions applied to the row decoder of  FIG. 6  for the nonvolatile memory device for nonvolatile memory device embodying the principles of the present invention. 
           [0057]      FIG. 12   b  is a table illustrating the voltage conditions applied to the select gate decoder of  FIG. 6  for the nonvolatile memory device for nonvolatile memory device embodying the principles of the present invention. 
           [0058]      FIG. 13  is a plot of threshold voltage for the floating gate memory transistor in the two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention vs. program time for hot-hole injection. 
           [0059]      FIG. 14  is a timing diagram for erasing and erase verification of a block of the nonvolatile memory device of  FIG. 5 . 
           [0060]      FIG. 15  is a timing diagram for programming and program verification of a block of the nonvolatile memory device of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0061]      FIG. 1   a  is schematic diagram of an embodiment of a two floating-gate transistor EEPROM configured memory cell  5 .  FIG. 1   b  is a top plan view of an embodiment of two floating-gate transistor EEPROM configured memory cell  5 .  FIG. 1   c  is a cross sectional cross sectional view of an embodiment of two floating-gate transistor EEPROM configured memory cell  5 . The two floating-gate transistor EEPROM configured memory cell  5  is formed in the top surface of a P-type substrate  10 . An N-type material is diffused into the surface of the P-type substrate  10  to form a deep N-well  15 . A P-type material is then diffused into the surface of the deep N-well  15  to form a P-well  20  (commonly referred to as a triple P-well—TPW). The N-type material is then diffused into the surface of a P-type well TPW  20  to form the drain region (D)  31  of the NMOS floating-gate select transistor  30 , the source region of the floating gate select transistor  30  and the source/drain regions (S/D)  55 . The source/drain region  55  is the source region of the floating gate select transistor  30  and the drain region for the floating gate memory transistor  25 . A first polycrystalline silicon layer is formed above the bulk region of the P-type well  20  between the drain region  31  and the source/drain region  55  of the NMOS floating-gate select transistor  30  to form the floating gate  32 . The first polycrystalline layer is also formed above the bulk region between the source/drain region  55  and the source region  29  to form the floating gate  27  of the floating gate memory transistor  25 . A second polycrystalline silicon layer is formed over the floating gates  27  and  32  to create the control gates  28  and  33  of the floating gate memory transistor  25  and the floating-gate select transistor  30 . The source/drain regions  55  is formed between the adjacent second polycrystalline silicon layers of control gates  28  and  33  of the floating gate memory transistor  25  and the floating-gate select transistor  30 . The source region  29  of the floating gate memory transistor  25  is shown as a half source region in that the whole source region  29  is shared with the source region of an adjacent two floating-gate transistor EEPROM configured memory cell  5  in an array. The self-aligned source/drain regions  29  are commonly used in the floating gate memory transistor  25  to reduce the source line pitch. 
         [0062]    In an array, multiple two floating-gate transistor EEPROM configured memory cells  5  are arranged in a matrix of rows and columns. The control gates  28  of the floating gate memory transistor  25  is extended to form a word line  35  that connects to each of the floating gate memory transistor  25  on a row of the array. The control gate  33  of the NMOS floating-gate select transistor  30  is connected to receive the select gating signal  40  at the drain  31 . A P + -contact  21  connects a P-well TPW  20  to the P-well voltage source  70 , the N + -contact  16  is connected to the deep N-well voltage source  65 , and the P + -contact  11  is connected to the P-substrate voltage source  60 . In most embodiments P-substrate voltage source  60  is actually the ground reference voltage source. 
         [0063]      FIGS. 2   a  and  2   b  are graphs of threshold voltage levels of various embodiments of a two floating-gate transistor EEPROM configured memory cell with a floating gate memory transistor  25  and a floating-gate select transistor  30  of  FIG. 1   a .  FIG. 2   a  illustrates the voltage thresholds levels the NMOS floating-gate select transistor  30 . The floating-gate select transistor  30  has a positive threshold voltage that is nominally approximately +2.0V. The voltage level applied to the select gating signal  40  must be greater than the select gating voltage VSG (boosted) to insure that the floating-gate select transistor  30  will turn on. The select gating voltage VSG (boosted) is set to a voltage level that is approximately +2.0V greater than the positive threshold voltage Vt 1  of the floating-gate select transistor  30 . The select gating voltage VSG (boosted) will be discussed in more detail hereinafter for the read operation, the program operation, the program verify operation, the erase operation (page, block, and chip), and the erase verify operation. 
         [0064]      FIG. 2   b  illustrates the voltage thresholds levels for programming and erasing of the floating gate memory transistor  25 . There is a positive programmed threshold voltage level (Vt 1 ) representing a logical “0” datum and one positive erased threshold voltage level (Vt 0 ) representing a logical “1” datum. The programmed threshold voltage level (Vt 1 ) is established through a Fowler-Nordheim edge tunneling effect and the erased threshold voltage level (Vt 0 ) is established through a Fowler-Nordheim channel tunneling effect. An upper boundary of the threshold voltage Vt 0 H for programming of the floating gate memory transistor  25  with an voltage level of approximately +1.0 V to activate the Fowler-Nordheim edge tunneling effect. A lower boundary of the threshold voltage Vt 1 L for erasing the floating gate memory transistor is approximately +4.0V to activate the Fowler-Nordheim channel tunneling effect. 
         [0065]      FIGS. 3   a - 3   d  are simplified schematic diagrams of an array of a two floating-gate transistor EEPROM configured memory cells  110   a , . . . ,  110   m  illustrating the bias conditions for reading, programming, page erasing and chip erasing of two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention. The EEPROM configured memory cells  110   a , . . . ,  110   m  are arranged in rows and columns to form an array. The schematic diagrams of  FIGS. 3   a - 3   d  are simplified to show a single column of the array of EEPROM configured memory cells  110   a , . . . ,  110   m . Each of the EEPROM configured memory cells  110   a , . . . ,  110   m  has a floating gate select transistor  115   a , . . . ,  115   m  and a floating-gate memory transistor  120   a , . . . ,  120   m . The drains of the floating gate memory transistors  120   a , . . . ,  120   m  and the source of floating-gate select transistors  115   a , . . . ,  115   m  are connected together. The drains of the floating gate select transistors  115   a , . . . ,  115   m  on each column are commonly connected to the bit line  140 . The control gates of each of the floating gate memory transistors  120   a , . . . ,  120   m  on each row are commonly connected to one of a word lines  125   a , . . . ,  125   m  The sources of the floating-gate memory transistors  120   a , . . . ,  120   m  on each row of the array are commonly connected to the source lines  135   a , . . . ,  135   m . The gates of the floating-gate select transistors  115   a , . . . ,  115   m  are connected to the select gate lines  130   a , . . . ,  130   m . The array  100  of the EEPROM configured memory cells  110   a , . . . ,  110   m  are formed in a single P-type well TPW  105 . 
         [0066]    The word lines  125   a , . . . ,  125   m  are connected to a row decoder that decodes a block and row address and applies the appropriate voltages to the word lines  125   a , . . . ,  125   m  for reading, programming, and erasing selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . The select gate lines  130   a , . . . ,  130   m  are connected to a select gate decoder that decodes a block and row address and applies to the appropriate voltage levels to the source lines select gate lines  130   a , . . . ,  130   m  for reading, programming, and erasing selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . The bit line  140  is a pass gate and sense amplifier that decodes a column address and applies the appropriate biasing voltages for reading, programming, and erasing selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . The bit line  140  is representative of multiple bit lines in a much larger array of EEPROM configured memory cells  110   a , . . . ,  110   m . The P-type well TPW  105  and the source lines  135   a , . . . ,  135   m  are connected to be appropriately biased for reading, programming, and erasing selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . 
         [0067]      FIG. 3   a  illustrates the biasing voltages for reading data from selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . The word line  125   a , which is connected to the selected page having the selected EEPROM configured memory cell  110   a  containing the selected floating gate memory transistor  120   a , is set to the voltage level of the read voltage threshold VR or approximately the level of the power supply voltage source VDD. The power supply voltage source VDD is either 1.8V or 3.0V. The unselected word line  125 m, which is connected to the unselected page having the selected EEPROM configured memory cell  110   m  containing the unselected floating gate memory transistor  120   m , is set to the voltage level of the power supply voltage source VDD. The select gate line  130   a  connected to the selected floating-gate select transistor  115   a  is set to the voltage level select gating voltage VSG that is approximately +4.0V. The select gate line  130   m , which is connected to the unselected page having the selected EEPROM configured memory cell  110   m  containing the unselected floating gate memory transistor  115   m , is set to a first select gate inhibit biasing voltage that is approximately the voltage level of the ground reference voltage source. The bit line BL[ 0 ]  140  is set to the read biasing voltage level of approximately +1.0V. The P-type well TPW  105  and the source lines  135   a , . . . ,  135   m  are set to the voltage level of the ground reference voltage source (0.0). The bit line  140  is pre-charged to the voltage level of the first read voltage of approximately the 1.0V. The pre-charged level of the first read voltage is discharged to approximately 0.0V when the selected EEPROM configured memory cell  110   a  has been programmed and has a threshold voltage level less than the upper boundary of the programmed threshold voltage level. If the selected EEPROM configured memory cell  110   a  is erased, the pre-charged level will be maintained when the threshold voltage of the selected EEPROM configured memory cell  110   a  is greater than the lower boundary erased threshold voltage level of approximately +4.0V. If the selected floating gate memory transistor  120   a  is erased as a logical “1”, the selected NMOS floating gate memory transistor  120   a  will not turn on and a sense amplifier will detect the programmed level of the logical “1”. Alternately, if the selected floating gate memory transistor  120   a  is programmed with a logical “0”, the selected floating gate memory transistor  120   a  will turn on and a sense amplifier will detect the programmed level of the logical “0”. 
         [0068]      FIG. 3   b  illustrates the biasing voltages for programming data to selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . The word line  125   a , which is connected to the selected page having the selected EEPROM configured memory cell  110   a  containing the selected floating gate memory transistor  115   a , is set to the voltage level of a very high negative programming voltage level of from approximately −10.0V to approximately −8.0V. The unselected word line  125   m , which is connected to the unselected page containing the unselected floating gate memory transistor  120   m , is disconnected to be floating. The select gate line  130   a  connected to the selected floating gate memory transistor  120   a  is set to a voltage level of a very high positive voltage that is from approximately +8.0V to approximately +10.0V. The select gate line  130   m , which is connected to the unselected page having the unselected floating-gate select transistor  115   m , is set to a program inhibit voltage level that is approximately the voltage level of the ground reference voltage source. The P-type well TPW  105  and the source lines  135   a , . . . ,  135   m  are set to the voltage level of the ground reference voltage source (0.0). If the selected floating gate memory transistor  120   a  is to remain erased as a logical “1”, the bit line  140  connected to the selected NMOS floating gate memory transistor  120   a  will be set to a voltage level of the ground reference voltage source. Alternately, if the selected floating gate memory transistor  120   a  is to be programmed with a logical “0”, the bit line  140  connected to the selected floating gate memory transistor  120   a  is set to the program biasing drain voltage of approximately +5.0V. 
         [0069]      FIG. 3   c  illustrates the biasing voltages for erasing a page of data from selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . The word line  125   a , which is connected to the selected page having the selected EEPROM configured memory cell  110   a  containing the selected floating gate memory transistor  120   a , is set to the voltage level of a very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V. The unselected word line  125   m , which is connected to unselected pages of the selected block containing an unselected floating gate memory transistor  120   m , is set to the voltage level of approximately the ground reference voltage source. The unselected word line  125   m , which is connected to unselected pages of an unselected block containing an unselected floating gate memory transistor  120   m , is set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. The select gate lines  130   a , . . . ,  130   m  are connected are set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. The bit line  140 , the P-type well TPW  105 , and the source lines  135   a , . . . ,  135   m  are set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. 
         [0070]    The 20.0 V difference voltage difference of the very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V at the selected word line  125   a  and the very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V between the control gate of the selected floating gate memory transistor  120   a  and the P-type well TPW  105  induces the Fowler-Nordheim channel tunneling phenomena that attracts electrons into the floating-gate of the selected floating gate memory transistor  120   a  in the selected page. As a consequence, the threshold voltage of the selected floating gate memory transistor is increased. After about 500 μS, the threshold voltage would be increased to be greater than lower boundary of the erased threshold voltage level Vt 1 L of approximately 4.0V. The bias conditions as shown, prevent the floating gate memory transistors  120   m  in the unselected pages from being effected during the erase operation. After a page erase operation, an erase verification operation is executed to insure that the desired erased threshold voltage level Vt 1 L of approximately 4.0V is achieved. 
         [0071]      FIG. 3   d  illustrates the biasing voltages for erasing an entire chip of data from selected EEPROM configured memory cells  110   a , . . . ,  110   m  of the array  100 . All the word lines  125   a , . . . ,  125   m  of the chip containing the all the floating gate memory transistor  120   a , . . . ,  120   m  are selected and set to the voltage level of a very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V. The select gate lines  130   a , . . . ,  130   m  are connected are set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. The bit line  140 , the P-type well TPW  105 , and the source lines  135   a , . . . ,  135   m  are set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. 
         [0072]    As described, the 20.0 V difference voltage difference of the very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V at the selected word lines  125   a , . . . ,  125   m  and the very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V between the control gate of all the floating gate memory transistors  120   a , . . . ,  120   m  and the P-type well TPW  105  induces the Fowler-Nordheim channel tunneling phenomena that attracts electrons into the floating-gate of the selected floating gate memory transistors  120   a , . . . ,  120   m  in the chip. As a consequence, the threshold voltage of the floating gate memory transistors  120   a , . . . ,  120   m  is increased. After about 500 μS, the threshold voltage would be increased to be greater than lower boundary of the erased threshold voltage level Vt 1 L of approximately +4.0V. 
         [0073]      FIG. 4  is a block diagram of a nonvolatile memory device  200  embodying the principles of the present invention incorporating the various embodiments of EEPROM configured memory cells of the present invention. The EEPROM nonvolatile memory device  200  includes an array  205  of EEPROM configured memory cells arranged in a matrix of rows and columns. The array  205  is partitioned into a uniform number of blocks  210   a , . . . ,  210   m  and each block is divided into a uniform number of pages  215   a ,  215   b , . . . ,  215   n , and  216   a ,  216   b , . . . ,  216   n , For instance, a 1 Mb memory array device may be divided into 128 blocks. Each block then becomes 8 KB and may be divided into a number of pages such as 8 pages of 1 KB each. Further, the block is divided into pages. In this example, the page may have a size of 4 Kb such that one page is equivalent to one word line or row of the block or sub-array  215   a ,  215   b , . . . ,  215   n , and  216   a ,  216   b , . . . ,  216   n . Thus, each block  215   a ,  215   b , . . . ,  215   n , and  216   a ,  216   b , . . . ,  216   n  has 8 pages or word lines. 
         [0074]    The column address decoder  265  receives a column address  290 , decodes the column address  290 , and from the decoded column address  290  selects which columns of the array are being accessed. The data register and sense amplifier  260  activates the appropriate bit lines  270   a , . . . ,  270   k  for operating a selected block  210   a , . . . ,  210   m . The appropriate bit lines  270   a , . . . ,  270   k  are further connected to the column address decoder  265 . The data register and sense amplifier  260  receives the data signals through the bit lines  270   a , . . . ,  270   k  from the selected block  210   a , . . . ,  210   m  and senses and holds the data from the data signal for a read operation. In a program operation, the data is transferred from the data register and sense amplifier  260  through the bit lines  270   a , . . . ,  270   k  to the selected block  210   a , . . . ,  210   m . The data being read from or written (program and erase) to the array  205  of EEPROM configured memory cells is transferred to and from the data register and sense amplifier  260  through the column address decoder  265  from and to the data input/output bus  295 . 
         [0075]    Each block  215   a ,  215   b , . . . ,  215   n , and  216   a ,  216   b , . . . ,  216   n  of the array  205  of EEPROM configured memory cells is connected to a row decoder  220  through the word lines  275   a ,  275   b , . . . ,  275   n ,  276   a ,  276   b , . . . ,  276   n . Each block  210   a , . . . ,  210   m  is connected to a block row decoder  230   a , . . . ,  230   m  within the row decoder  220  for providing the appropriate voltage levels to a selected page or word line for reading and programming selected EEPROM configured memory cells. The row address  285  is transferred to each of the block row decoders  230   a ,  230   b , . . . ,  230   n  to select the page or word line and to provide the appropriate voltage levels for reading and programming the selected EEPROM configured memory cells. 
         [0076]    Each block  215   a ,  215   b , . . . ,  215   n , and  216   a ,  216   b , . . . ,  216   n  of the array  205  of EEPROM configured memory cells is connected to a select gate decoder  240  through the select gate lines  280   a ,  280   b , . . . ,  280   n  and  281   a ,  281   b , . . . ,  281   n . The select gate decoder  240  is formed of multiple blocks of select gate decoders  245   a , . . . ,  245   m . Each block  215   a ,  215   b , . . . ,  215   n , and  216   a ,  216   b , . . . ,  216   n  is connected with its own select gate line decoder  245   a , . . . ,  245   m  for providing the appropriate voltage levels to selected gate lines of a selected page for reading and programming selected EEPROM configured memory cells. The row address  285  is transferred to each of the block select gate line decoders  245   a ,  245   b , . . . ,  245   m  to select the select gate line of the selected page to provide the appropriate voltage levels for reading, programming, and erasing the selected EEPROM configured memory cells. 
         [0077]    Refer now to  FIG. 5  for a discussion of the structure of a block  210  of the array  205  of  FIG. 4 . The block  210  is exemplary of the all the blocks  210   a , . . . ,  210   m  of array  205 . The block  210  is placed in a common P-type well TPW  212  and contains all the EEPROM configured memory cells  5  of the block  210 . The EEPROM configured memory cells  5  are arranged in rows and columns to form the sub-array of the block  210 . Each of the EEPROM configured memory cells  5  are formed of a floating-gate memory transistor MC and a floating-gate select transistor MS. The floating-gate select transistor MS of the EEPROM configured memory cells  5  have their drains commonly connected to a bit line  270   a , . . . ,  270   k  associated with a column on which the EEPROM configured memory cells  5  are placed. The source of the floating-gate select transistor MS is commonly connected to the drain of the floating-gate memory transistor MC. The sources of the floating-gate memory transistors MC of adjacent pairs of rows of the EEPROM configured memory cells  5  are connected to one source line  135   a , . . . ,  135   m . The source lines  135   a , . . . ,  135   m  are connected externally to the array to receive the appropriate source biasing voltages for reading, programming, and erasing selected EEPROM configured memory cells  5 . The control gates of the floating-gate memory transistors MC are connected to the word lines  275   a , . . . ,  275   m . The word lines  275   a ,  . . . ,  275   m  are connected to the row decoder  220  of  FIG. 4 . The block  210  divided into pages  215   a , . . . ,  215   m . The page  215   a , . . . ,  215   m  being groupings of the EEPROM configured memory cells  5  having their control gates connected commonly to a word line (WL 0 ) of the word lines  275   a , . . . ,  275   m . The control gates of the floating-gate select transistors MS are connected to the select gate lines  280   a , . . . ,  280   m . The select gate lines  280   a , . . . ,  280   m  are commonly connected to the select gate decoder  240  of  FIG. 4  to received the activation signals to turn on the selected floating-gate select transistors MS for reading, programming, erasing and verifying selected floating-gate memory transistors MC. 
         [0078]      FIG. 6   a  is a schematic diagram of a representative row decoder  220  of the nonvolatile memory device of  FIG. 4 . Each row decoder  220  is partitioned into block decoders  230   a , . . . ,  230   m . The number of block decoders  230   a , . . . ,  230   m  in each row decoder  220  is equal to the number of blocks  210   a , . . . ,  210   m  of  FIG. 4 . the logic gate  310   a , . . . ,  310   m  (an AND gate in this embodiment) receives the block address  320  of the row address  285  of  FIG. 4 , decodes the block address  320  to select which of the block row decoders  230   a , . . . ,  230   m  is to be activated for reading, programming, or erasing. The output of the logic gate  310   a , . . . ,  310   m  is the block select signal RXD [ 0 ]  312   a , . . . , RXD [m]  312   m  that is the input to an input to the level shift circuit  315   a , . . . ,  315   m . The level shift circuit  315   a , . . . ,  315   m  receives the power supply voltage levels  325  that are used to shift the lower voltage logic level of the block select signal RXD [ 0 ]  312   a , . . . , RXD [m]  312   m  to the levels required for reading, programming, and erasing. The outputs of the level shift circuit  315   a , . . . ,  315   m  are the high voltage block select signals XD  330   a , . . . ,  330   m  and XDB  332   a , . . . ,  332   m  that are applied to the row decode circuit  340   a , . . . ,  340   m.    
         [0079]    The row decode circuits  340   a , . . . ,  340   m  provide the appropriate voltage levels for transfer to the rows of the word lines  275   a , . . . ,  275   m  of the selected block  210   a , . . . ,  210   m  of  FIG. 4 . The voltage levels applied to row decode circuit  340   a , . . . ,  340   m  are provided by the high voltage power supply voltage lines  335 . Each high voltage power supply voltage lines XT[0:1]  335  is associated with one of the word lines  275   a , . . . ,  275   m  and is set according to the operation (read, program, erase, or verify) to be executed and are discussed hereinafter. The row decode circuits  340   a , . . . ,  340   m  have the row pass devices formed of the high voltage PMOS transistors  341   a , . . . ,  341   m  and the high voltage NMOS transistors  342   a , . . . ,  342   m  connected pair-wise in parallel. The gates of the PMOS transistors  341   a , . . . ,  341   m  are each connected to one of the high voltage out of phase block select signals XDB  332   a , . . . ,  332   m . The gates of the NMOS transistors  342   a , . . . ,  342   m  are each connected to one of the in-phase block select signals XD  330   a , . . . ,  330   m . The sources of the PMOS transistors  341   a , . . . ,  341   m  and the drains of the NMOS transistors  342   a , . . . ,  342   m  are connected to the high voltage power supply voltage lines XT[0:1]  335  associated with one of the word lines  275   a , . . . ,  275   m . The drains of the PMOS transistors  341   a , . . . ,  341   m  and the sources of the NMOS transistors  342   a , . . . ,  342   m  are connected to the drain high voltage pass transistors  343   a , . . . ,  343   m  associated with one of the word lines  275   a , . . . ,  275   m . The drains of the PMOS transistors  341   a , . . . ,  341   m  and the sources of the NMOS transistors  342   a , . . . ,  342   m  are further connected to the drain of the NMOS transistors  343   a ,  . . . ,  343   m.  The gate of the NMOS transistors  343   a , . . . ,  343   m  is connected to the out of phase block select signals XDB  332   a , . . . ,  332   m  and the sources of the NMOS transistors  343   a , . . . ,  343   m  are connected to the ground reference voltage source (0.0). For the row decoders  230   a , . . . ,  230   m  of the unselected block  210   a , . . . ,  210   m , the level shift circuit  315   a , . . . ,  315   m  are deactivated and the out of phase block select signals XDB  332   a , . . . ,  332   m  are set to turn on the NMOS transistors  343   a , . . . ,  343   m  to set the drains of the NMOS transistors  343   a , . . . ,  343   m  to the voltage level of the ground reference voltage source (0.0). 
         [0080]    The high voltage pass transistors  351   a , . . . ,  351   m  form the PMOS high voltage isolators  350   a , . . . ,  350   m . The gates of the high voltage pass transistors  351   a ,  . . . ,  351   m  are connected together and to the isolation signal ISOB  366 . When activated, the high voltage pass transistors  351   a , . . . ,  351   m  connect the word lines  275   a , . . . ,  275   m  to the row decode circuits  340   a , . . . ,  340   m  through the word line biasing lines  345   a , . . . ,  345   m . When deactivated, the high voltage pass transistors  351   a , . . . ,  351   m  isolate the word lines  275   a , . . . ,  275   m  to the row decode circuits  340   a , . . . ,  340   m.    
         [0081]    The PMOS high voltage isolators  350   a , . . . ,  350   m  are each formed in an independent N-type well  352   a , . . . ,  352   m . The N-type well  352   a , . . . ,  352   m  for each of the N-type well  352   a , . . . ,  352   m  is connected to an N-type well switch  355   a , . . . ,  355   m  to individually charge or discharge the N-type wells  352   a , . . . ,  352   m . The N-type well switch  355   a , . . . ,  355   m  includes the PMOS transistors  356   a , . . . ,  356   m  and  357   a , . . . ,  357   m  and the NMOS transistor  358   a , . . . ,  358   m . The gates of the PMOS transistors  356   a , . . . ,  356   m  and the NMOS transistors  358   a , . . . ,  358   m  are connected to the out of phase block select signals XDB  332   a , . . . ,  332   m . The gates of the PMOS transistors  357   a , . . . ,  357   m  are connected to the out of phase read signal RDB  364 . The drains the PMOS transistors  356   a , . . . ,  356   m  and  357   a , . . . ,  357   m  and drains the NMOS transistors  358   a , . . . ,  358   m  are connected to the N-type wells  352   a , . . . ,  352   m . The sources of the PMOS transistors  356   a , . . . ,  356   m  and  357   a , . . . ,  357   m  are connected to the positive N-well biasing voltage source VP 1   362  and the sources of the NMOS transistors  358   a , . . . ,  358   m  are connected to the negative N-well biasing voltage source VM 1   360 . 
         [0082]      FIG. 6   b  is a schematic diagram of select gate decoder  240  of the nonvolatile memory device of  FIG. 4 . Each select gate decoder  240  is partitioned into a block select gate decoders  245   a ,  245   b , . . . ,  245   m . The number of block select gate decoders  245   a ,  245   b , . . . ,  245   m  in each select gate decoder  425  is equal to the number blocks  210   a , . . . ,  210   m  in the array  205  of  FIG. 4 . The logic gate  410   a , . . . ,  410   m  (an AND gate in this embodiment) receives the block address  420  of the row address  285  of  FIG. 4 , decodes the block address  420  to select which of the block select gate decoders  245   a , . . . ,  245   m  is to be activated for reading, programming, or erasing. The output of the logic gate  410   a , . . . ,  410   m  is the block select signal RXD [ 0 ]  412   a , . . . , RXD [m]  412   m  that is the input to an input to the level shift circuit  415   a , . . . ,  415   m . The level shift circuit  415   a , . . . ,  415   m  receives the power supply voltage levels  425  that are used to shift the lower voltage logic level of the block select signal RXD [ 0 ]  412   a , . . . , RXD [m]  412   m  to the levels required for reading, programming, and erasing. The outputs of the level shift circuit  415   a , . . . ,  415   m  are the high voltage block select signals XD  330   a , . . . ,  330   m  and XDB  432   a , . . . ,  432   m  that are applied to the row decode circuit  440   a , . . . ,  440   m.    
         [0083]    The row decode circuits  440   a , . . . ,  440   m  provide the appropriate voltage levels for transfer to the rows of the select gate lines  280   a , . . . ,  280   m  of the selected block  210   a , . . . ,  210   m  of  FIG. 4 . The voltage levels applied to row decode circuit  440   a ,  . . . ,  440   m  are provided by the high voltage power supply voltage lines  435 . Each high voltage power supply voltage lines  435  is associated with one of the select gate lines  280   a , . . . ,  280   m  and is set according to the operation (read, program, erase, or verify) to be executed and are discussed hereinafter. Each of the row decode circuits  440   a , . . . ,  440   m  have the row pass devices formed of the high voltage PMOS transistors  441   a , . . . ,  441   m  and the high voltage NMOS transistors  442   a , . . . ,  442   m  connected pair-wise in parallel. The gates of the PMOS transistors  441   a , . . . ,  441   m  are each connected to one of the high voltage out of phase block select signals XDB  432   a , . . . ,  432   m . The gates of the NMOS transistors  442   a , . . . ,  442   m  are each connected to one of the in-phase block select signals XD  330   a , . . . ,  330   m . The sources of the PMOS transistors  441   a , . . . ,  441   m  and the drains of the NMOS transistors  442   a , . . . ,  442   m  are connected to the high voltage power supply voltage line  435  associated with one of the select gate lines  280   a ,  . . . ,  280   m . The drains of the PMOS transistors  441   a , . . . ,  441   m  and the sources of the NMOS transistors  442   a , . . . ,  442   m  are connected to the drain high voltage pass transistors  443   a , . . . ,  443   m  associated with one of the select gate lines  280   a , . . . ,  280   m . The drains of the PMOS transistors  441   a , . . . ,  441   m  and the sources of the NMOS transistors  442   a , . . . ,  442   m  are further connected to the drain of the NMOS transistors  443   a , . . . ,  443   m . The gate of the NMOS transistors  443   a , . . . ,  443   m  is connected to the out of phase block select signals XDB  432   a , . . . ,  432   m  and the sources of the NMOS transistors  443   a , . . . ,  443   m  are connected to the ground reference voltage source (0.0). For the select gate decoders  245   a , . . . ,  245   m  of the unselected block  210   a , . . . ,  210   m , the level shift circuit  415   a , . . . ,  415   m  are deactivated and the out of phase block select signals XDB  432   a , . . . ,  432   m  are set to turn on the NMOS transistors  443   a , . . . ,  443   m  to set the drains of the NMOS transistors  443   a , . . . ,  443   m  to the voltage level of the ground reference voltage source (0.0). 
         [0084]    The high voltage pass transistors  451   a , . . . ,  451   m  form the PMOS high voltage isolators  450   a , . . . ,  450   m . The gates of the high voltage pass transistors  451   a ,  . . . ,  451   m  are connected together and to the isolation signal ISOB  366 . When activated, the high voltage pass transistors  451   a , . . . ,  451   m  connect the select gate lines  280   a , . . . ,  280   m  to the row decode circuits  440   a , . . . ,  440   m  through the select gate biasing lines  445   a , . . . ,  445   m . When deactivated, the high voltage pass transistors  451   a , . . . ,  451   m  isolate the select gate lines  280   a , . . . ,  280   m  to the row decode circuits  440   a , . . . ,  440   m.    
         [0085]    The PMOS high voltage isolators  450   a , . . . ,  450   m  are each formed in an independent N-type well  452   a , . . . ,  452   m . The N-type well  452   a , . . . ,  452   m  for each of the N-type well  452   a , . . . ,  452   m  is connected to an N-type well switch  455   a , . . . ,  455   m  to individually charge or discharge the N-type wells  452   a , . . . ,  452   m . The N-type well switches  455   a , . . . ,  455   m  include the PMOS transistors  456   a , . . . ,  456   m  and  457   a , . . . ,  457   m  and the NMOS transistors  458   a , . . . ,  458   m . The gates of the PMOS transistors  456   a , . . . ,  456   m  and the NMOS transistors  458   a , . . . ,  458   m  are connected to the out of phase block select signals XDB  432   a , . . . ,  432   m . The gates of the PMOS transistors  457   a , . . . ,  457   m  are connected to the out of phase read signal RDB  364 . The drains the PMOS transistors  456   a , . . . ,  456   m  and  457   a , . . . ,  457   m  and drains the NMOS transistors  458   a , . . . ,  458   m  are connected to the N-type wells  452   a , . . . ,  452   m . The sources of the PMOS transistors  456   a , . . . ,  456   m  and  457   a , . . . ,  457   m  are connected to the positive N-well biasing voltage source VP 1   362  and the sources of the NMOS transistors  458   a , . . . ,  458   m  are connected to the negative N-well biasing voltage source VM 1   360 . 
         [0086]      FIG. 7  is a schematic diagram of the level shifter circuits  315   a , . . . ,  315   m  and  415   a , . . . ,  415   m  respectively of the row decoder of  FIG. 6   a  and the select gate decoder of  FIG. 6   b . Referring now to  FIG. 7 , the level shifter circuit  515  has two sub-level-shifter circuits  570  and  580  to translate the low voltage level of the block select signal RXD  512  to a voltage level of a positive high voltage power source VPX  527 . The voltage translation maintains the drain to source breakdown voltage BVDSS that is less than ±10V such that special high voltage devices are not required for the circuitry of the nonvolatile memory device  200  of  FIG. 4 . The first level shift circuit  570  has pair of cross connected PMOS transistors  571  and  572  that have their sources and bulk regions connected to the positive high voltage power source VPX  527 . The drain of the PMOS transistor  571  is connected to the gate of the PMOS transistor  572  and the drain of the PMOS transistor  572  is connected to the gate of the PMOS transistor  571 . The drain of the PMOS transistors  571  is connected to the drain of the NMOS transistor  575  and the drain of the PMOS transistors  572  is connected to the drain of the NMOS transistor  577 . The gate of the NMOS transistor  575  is connected to receive the block select signal RXD  512 . The block select signal RXD  512  is connected to the input of the inverter  576 . The output of the inverter  576  is connected to the gate of the NMOS transistor  577 . The sources of the NMOS transistors  575  and  577  are connected to the ground reference voltage source (0.0). 
         [0087]    The output nodes  573  and  574  of the first level shift circuit  570  are the input nodes of the second level shift circuit  580 . The second level shift circuit  580  has a pair of PMOS transistors  581  and  582  that have their sources and bulk regions connected to the high voltage power supply VPX  527 . The drain of the PMOS transistor  581  is connected to the drain of the NMOS transistor  585  and the source of the PMOS transistor  583 . The drain of the PMOS transistor  582  is connected to the drain of the NMOS transistor  586  and the source of the PMOS transistor  584 . The output node  573  of the first level shift circuit  570  is connected to the gate of the PMOS transistor  581  and the output node  574  of the first level shift circuit  570  is connected to the gate of the PMOS transistor  582 . The sources of the NMOS transistors  585  and  586  are connected to the negative high voltage source VNX  526 . The drains of the PMOS transistors  583  and  584  are connected to the drain of the NMOS transistor  587 . The source of the NMOS transistor  587  is connected to the ground reference voltage source. The gate of the NMOS transistor  587  is connected to the negative power supply enable signal ENVNX  528 . The out-of-phase block select signal XDB  533  is at the junction of the connection of the drains of the PMOS transistors  581  and  583  and the NMOS transistor  585 . The in-phase block select signal XD  532  is at the junction of the connection of the drains of the PMOS transistor  582  and  584  and the NMOS transistor  586 . 
         [0088]    The first sub-level shifter circuit  570  receives the low voltage logic signal of the block select signal RXD  512  and generates the high voltage block select signal XD  532  and XDB  533 . The two sub-level-shifter circuits  570  and  580 , as designed, provide the positive and negative very high voltages and yet not exceed the drain-to-source breakdown voltage of the transistors of the two sub-level-shifter circuits  570  and  580 . The negative power supply enable signal ENVNX  528  selectively activates the NMOS transistor  587  to provide the appropriate ground reference voltage level to allow the in-phase block select signal XD  532  and the out-of-phase block select signal XDB  533  to be set to the voltage level of the negative high voltage source VNX  526  during a program and erase. 
         [0089]      FIG. 8  is flow chart for the method for operating the nonvolatile memory device  200  of  FIG. 4 .  FIG. 9  is flow chart of the method for erasing and erase verifying a page, block, or chip of the nonvolatile memory device  200  of  FIG. 4 .  FIG. 10  is flow chart of the method for programming and program verifying a page of the nonvolatile memory device  200  of  FIG. 4 . Refer now to  FIGS. 4-11 ,  12   a , and  12   b  for a discussion of the operating voltage levels required for the reading, programming, erasing, and verification of the nonvolatile memory device  200 . The method begins by determining (Box  600 ) if the operation is an erase. If the operation is an erase operation, the erase is determined (Box  605 ) to be a page, block, or chip erase. If the operation is to be a page erase, the page to be erased is selected (Box  610 ) and the page is erased (Box  620 ). The voltage levels for erasing a page of the array  205  of EEPROM configured memory cells  5  are shown in  FIG. 11  The word lines  275 U of the unselected blocks  410 U of the selected chips are set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V as coupled from the P-type well TPW  212 . The P-type well TPW  212  of the selected chip set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. The selected word line  275 S of the selected block is set to a very high positive erase voltage is from approximately +8.0V to approximately +10.0V. The unselected word line  275 SU in the selected block  410 S is set to the approximately the voltage level of the ground reference voltage source (0.0V). The selected bit line  270 S is set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. The selected and unselected select gate line  280 S are set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. 
         [0090]    To establish the page erase values as just described the row decoders  230   a ,  230   b , . . . ,  230   m  have voltage levels described in  FIG. 12   a  and the select gate decoders  245   a ,  245   b , . . . ,  245   m  have voltage levels described in  FIG. 12   b . The selected word line  275 S must be set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the unselected word lines  275 SU of the selected block are set to the approximately the voltage level of the ground reference voltage source (0.0V). The unselected word lines  275 U of the unselected blocks are coupled to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V coupled from the P-type well TPW  212 . The selected select gate line  280 S, unselected select gate lines  280 SU of the selected block, and unselected select gate lines  280 U of the unselected blocks must be set to the very high negative erase voltage is from approximately −10.0V to approximately −8.0V. To accomplish these levels as shown in  FIGS. 12   a  and  12   b , the row decoders  275   a ,  275   b , . . . ,  275   n  of the selected blocks  410 S have their selected high voltage power supply voltage line XT  335 S associated with the selected word line  275 S set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V to be fed through the row decode circuit  340   a , . . . ,  340   n  and the PMOS high voltage isolators  350   a , . . . ,  350   n  to the selected word line  275 . The unselected high voltage power supply voltage line  335 U associated with the selected word line  275 SU set to the voltage level of the ground reference voltage level to be fed through the row decode circuit  340   a , . . . ,  340   n  and the PMOS high voltage isolators  350   a , . . . ,  350   n  to the unselected word line  275 SU. The voltage level of the selected in-phase block select signals XD  330 S, indicating that a block  210 S is selected, is set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the out-of-phase block select signals XD  330 U, indicating that the unselected blocks  410 U are unselected, is set to approximately the voltage level of the ground reference voltage source (0.0V) to be coupled from the row decode circuit  340   a , . . . ,  340   n  through the PMOS high voltage isolators  350   a , . . . ,  350   m  such that the unselected word lines  275 U are coupled to the very high negative erase voltage that is from approximately −8.0V to approximately −10.0V from the P-type well TPW  212 . The N-type wells  352 S of the selected block  410 S is connected to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V to avoid voltage breakdown in the PMOS high voltage isolators  350   a , . . . ,  350   m  and the N-type well switch  355   a , . . . ,  355   m . The N-type wells  352 U of the selected block  410 U is connected to the voltage level of the ground reference voltage source (0.0V). 
         [0091]    To transfer the very high positive erase voltage present on the selected high voltage power supply voltage line XT  335 S to the selected word line  275 S, the PMOS high voltage isolators  350   a , . . . ,  350   m  are activated with the isolation signal ISOB  366  is set to the voltage level of the ground reference voltage source (0.0V). The out of phase read signal RDB  364 , positive high voltage power source VPX  327 , and the positive N-well biasing voltage source VP 1   362  are set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V to set the selected word line  275 S to the voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V. The high negative voltage source VNX  326 , negative power supply enable signal ENVNX  328  are set to the voltage level of the ground reference voltage source (0.0V) to set the unselected word lines  275 SU of the selected block  410 S to approximately the voltage level of the ground reference voltage source (0.0V). 
         [0092]    The select gate decoders  280   a ,  280   b , . . . ,  280   m  of the selected blocks  410 S have their selected high voltage power supply voltage line XT  435 S associated with the selected select gate line  280 S, the unselected high voltage power supply voltage line XT  435 U associated with the unselected select gate lines  280 SU of the selected block, and unselected select gate lines  280 U of the unselected blocks are set to the voltage level of the very high negative erase voltage to be fed through the row decode circuit  440   a , . . . ,  440   m  and the PMOS high voltage isolators  450   a , . . . ,  450   m  to the selected select gate line  280 S and unselected select gate lines  280 SU and  280 U. The voltage level of the selected in-phase block select signals XD  430 S and the voltage level of the out-of-phase block select signals XD  430 U are set to the very high negative erase voltage to be coupled from the row decode circuit  440   a , . . . ,  440   m  through the PMOS high voltage isolators  450   a , . . . ,  450   m  such that the selected select gate line  280 S and the unselected select gate lines  280 SU and  280 U are set to the very high negative erase voltage that is from approximately −8.0V to approximately −10.0V. The N-type wells  452 S of the selected block  410 S and the N-type wells  452 U of the selected blocks  410 U are connected to the voltage level of the ground reference voltage source (0.0V). 
         [0093]    To transfer the very high negative erase voltage present on the selected high voltage power supply voltage lines XT  435 S,  435 SU, and  435 U to the selected select gate line  280 S, the PMOS high voltage isolators  450   a , . . . ,  450   m  are activated with the isolation signal ISOB  466  is set to a very high negative select level of approximately −12V. The out of phase read signal RDB  464  is set to the very high positive erase voltage. The positive high voltage power source VPX  427  is set to the voltage level of the ground reference voltage source (0.0V) and the high negative voltage source VNX  426  is set to the very high negative erase voltage level. The negative power supply enable signal ENVNX  428  is set to the voltage level of the power supply voltage source VDD and set the selected gate lines  280 S and the unselected select gate lines  280 SU and  280 U of the selected and unselected blocks to very high negative erase voltage. 
         [0094]    Returning now to  FIG. 9 , after the completion of the page erase operation (Box  620 ), the page erase verify operation is executed (Box  625 ) to determine if the erase has been successfully accomplished. The voltage levels for the page erase verification for the array  205  of the EEPROM configured memory cells  5  are shown in  FIG. 11 . Referring to  FIG. 11 , the selected word line  275 S and the unselected word lines  275 SU of the selected blocks  410  S and the unselected word lines  275 U of the unselected blocks  410 U are set to the lower boundary of the threshold voltage Vt 1 L that is approximately +4.0V. The selected bit line  270 S is pre-charged to the second read voltage level that is approximately the voltage level of the power supply voltage source VDD less a threshold voltage Vt of an NMOS transistor. The pre-charged level of the second read voltage level is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level Vt 1 L. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the second read voltage level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level Vt 1 L. The selected select gate line  280 S is set to the high read select voltage HV″ that is approximately +5.0V and the unselected select gate lines are set a voltage level of the voltage level of the ground reference voltage source (0.0V). 
         [0095]    Referring to  FIG. 12   a  to discuss the voltage levels of the row decoders  230   a ,  230   b , . . . ,  230   m , the selected word line  275 S and the unselected word lines  275 SU and  275 U are set to the lower boundary of the erase threshold voltage level Vt 1 L by setting selected high voltage power supply voltage line XT  335 S and the unselected high voltage power supply voltage line XT  335 SU and  335 U to the voltage level of the lower boundary of the erase threshold voltage level Vt 1 L. The voltage level of the selected and unselected in-phase block select signals XD  330 S and  330 U, the positive high voltage power source VPX  327 , and the selected and unselected negative N-well biasing voltage lines NW  352   a  and NW  352 U are set to lower boundary of the erase threshold voltage Vt 1 L to pass the lower boundary of the erase threshold voltage level Vt 1 L to the selected word line  275 S. The out of phase read signal RDB  364 , the first high negative voltage source VNX  326 , and the negative power supply enable signal ENVNX  328  are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB  366  is set to a first negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the lower boundary of the erase threshold voltage level Vt 1 L from the selected and unselected high voltage power supply voltage line XT  335 S and XT  335 U to the selected word line  275 S and the unselected word lines  275 SU and  275 U. 
         [0096]    Returning to  FIG. 11 , the selected bit lines BL  270 S for the selected columns are pre-charged to the pre-charge voltage level of the power supply voltage source VDD less the threshold voltage Vt (VDD−Vt) for sensing the status of the selected floating-gate memory transistor MC of the EEPROM configured memory cells  5  on the activated columns. The pre-charge voltage level (VDD−Vt) will be discharged to 0V when any of the floating-gate memory transistors MC have not been successfully erased to the lower boundary of the threshold voltage level Vt 1 L of the floating-gate memory transistor MC is lower than the lower boundary of the erased threshold voltage level. If the floating-gate memory transistors MC are erased, the pre-charged level will be maintained when the threshold voltage of the floating-gate memory transistor MC is greater than the erased threshold voltage level Vt 1 L. The select gate lines  280 S for the selected block is set to the voltage level of the high read select voltage HV″ of approximately +5.0V to fully couple the pre-charged voltage level of second read voltage level that is the power supply voltage source VDD less the threshold voltage Vt (VDD−Vt) from the bit lines  270   a , . . . ,  270   k  to the drains of the selected floating-gate memory transistors MC. 
         [0097]    Referring to  FIG. 12   b  to discuss the voltage levels of the select gate decoders  245   a ,  245   b , . . . ,  245   m , the selected select gate line  280 S is set to the high read select voltage HV″ by setting selected high voltage power supply voltage line XT  435 S to the high read select voltage HV″. The unselected select gate lines  280 SU and  280 U are set to the voltage level of the ground reference voltage source (0.0V) by setting the unselected high voltage power supply voltage line XT  435 SU and  435 U to the voltage level of the ground reference voltage source (0.0V). The voltage level of the selected in-phase block select signals XD  430 S, selected and unselected negative N-well biasing voltage lines NW  452 S and NW  452 U, and the positive high voltage power source VPX  427  are set to the high read select voltage HV″. The unselected in-phase block select signals  430 U, negative high voltage power source VNX  426 , the out of phase read signal RDB  464 , and the negative power supply enable signal ENVNX  428  are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB  466  is set to a second negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the high read select voltage HV″ from the selected high voltage power supply voltage line XT  435 S to the selected select gate line  280 S. Further, the voltage levels, as described, fully pass voltage level of the ground reference voltage source (0.0V) from the unselected high voltage power supply voltage line XT  435 U to the unselected select gate lines  280 U. 
         [0098]    Returning to  FIG. 9 , if the page erase verify (Box  625 ) indicates the page erase (Box  620 ) is not successful, a loop counter is tested (Box  630 ) to assess that the maximum number of erasure trials is not exceeded. If the maximum number of erasure trials is not exceeded, the loop counter is incremented (Box  635 ) and the page erase operation (Box  620 ) is executed repetitively until the maximum number of erasure trials is exceeded and the nonvolatile memory device is declared as having failed (Box  640 ) or the erasure is a success and the nonvolatile memory device is declared as having successfully been erased (Box  645 ). 
         [0099]    Return now to  FIG. 9 . If the operation is not a page erase but is determined (Box  605 ) to be a block erase, the block to be erased is selected (Box  615 ) and the block is erased (Box  615 ). Referring now to  FIGS. 11 ,  12   a  and  12   b , the voltage levels for the block erase are identical to that of the page erase described above except that there are no unselected word lines  275 SU in the selected block  410 S. All the word lines  275 S are now selected for erasure and placed at the very high positive erase voltage level of from approximately +8.0V to approximately +10.0V to accomplish the block erase. 
         [0100]    Returning now to  FIG. 9 , after the completion of the block erase operation (Box  620 ), the block erase verify operation is executed (Box  625 ) to determine if the block erase has been successfully accomplished. The block erase verify operation (Box  625 ) is identical to the page erase verify. The selected and unselected word lines  275 S,  275 SU, and  275 U are set to a voltage level of the lower boundary of the erase threshold voltage Vt 1 L or approximately +4.0V for the single level cell program as shown in  FIG. 12   a.    
         [0101]    Returning to  FIG. 9 , if the block erase verify (Box  625 ) indicates that the block erase (Box  620 ) was not successful, a loop counter is tested (Box  630 ) to assess that the maximum number of erasure trials is not exceeded. If the maximum number of erasure trials is not exceeded, the loop counter is incremented (Box  635 ) and the block erase operation (Box  620 ) is executed repetitively until the maximum number of erasure trials is exceeded and the nonvolatile memory device is declared as having failed (Box  640 ) or the erasure is a success and the nonvolatile memory device is declared as having successfully been erased (Box  645 ). 
         [0102]    If the operation is to be a chip erase, the chip is erased (Box  625 ). Referring now to  FIGS. 11 ,  12   a  and  12   b , the voltage levels for the chip erase are identical to that of the page erase and block erase described above except that there are no unselected word lines  275 SU or  275 U. All the word lines  275 S are now selected for erasure and placed at the very high positive erase voltage level of from approximately +8.0V to approximately +10.0V to accomplish the chip erase. 
         [0103]    Returning now to  FIG. 9 , after the completion of the chip erase operation (Box  625 ), the chip erase verify operation is executed (Box  630 ) to determine if the block erase has been successfully accomplished. The chip erase verify (Box  625 ) is identical to the page erase verify. All the selected and unselected word lines  275 S,  275 SU, and  275 U are set to a voltage level of the lower boundary of the erase threshold voltage Vt 1 L. 
         [0104]    If the chip erase verify (Box  625 ) indicates that the block erase (Box  620 ) was not successful, a loop counter is tested (Box  630 ) to assess that the maximum number of erasure trials is not exceeded. If the maximum number of erasure trials is not exceeded, the loop counter is incremented (Box  635 ) and the chip erase (Box  620 ) operation is executed repetitively until the maximum number of erasure trials is exceeded and the nonvolatile memory device is declared as having failed (Box  640 ) or the erasure is a success and the nonvolatile memory device is declared as having successfully been erased (Box  645 ). 
         [0105]    Returning now to  FIG. 8 , if the operation is determined (Box  600 ) not to be an erase operation, the operation is determined (Box  650 ) if it is a program operation. If the operation is determined (Box  650 ) to be a page program operation (referring to FIG.  10 ), data is loaded (Box  655 ) to the data register and sense amplifier  260  and the page to be programmed is selected (Box  660 ) to be transferred to the bit line  270   a , . . . ,  270   k  through the activation of the data register and sense amplifier  260 . The floating-gate memory transistors MC of the selected page are then programmed with the voltage levels applied as shown in  FIG. 11 ,  12   a , and  12   b . Referring to  FIG. 11 , the unselected word lines  275 U of the unselected blocks  410 U because the unselected row decode circuits  340   a , . . . ,  340   m  are turned off and the unselected word lines  275 SU of the selected block  410 S are set to the voltage level of the ground level voltage source (0.0V). The selected word line  275 S is set to the high negative program voltage level that is from approximately −8.0V to approximately −10, which is somewhat less than the drain to source breakdown voltage BVDSS of the transistors of the row decoder  220  of  FIG. 4 . The selected bit lines BL  270 S for the columns that are to be programmed are set to the high program voltage is approximately +5.0V. The unselected bit lines BL  270 U (the program inhibited) for the columns that are to remain erased are set to a voltage level of approximately the ground reference voltage source (0.0V) or alternately disconnected and allowed to float. The selected select gate line  280 S connected to the selected page is set to the high program select voltage of approximately 10.0V. The unselected select gate lines  280 U are set to the voltage level of the ground reference voltage source (0.0V). The source lines of the array  205  of EEPROM configured memory cells  5 , and the P-type well TPW  212  in which the array  205  of EEPROM configured memory cells  5  are formed is set to the voltage level of the ground reference voltage source (0.0V). 
         [0106]    To establish the voltage levels as described for the programming in  FIG. 11 , the row decoder  220  has the voltage levels shown in  FIGS. 12   a  and the select gate decoder has the voltage levels shown in  FIG. 12   b . Referring to  FIG. 12   a , to have the selected word line  275 S set to a high negative program voltage level that is from approximately −8.0V to approximately −10.0V, the selected high voltage power supply voltage line XT  335 S associated with the selected word line  275 S set to the very high negative program voltage level. To have the unselected word lines  275 SU set to the voltage level of the ground reference voltage source (0.0V), the unselected high voltage power supply voltage line XT  335 SU associated with the unselected word lines  275 SU set to the voltage level of the ground reference voltage source (0.0V). To have the unselected word lines  275 U of the unselected blocks disconnected and floating the selected row decode circuit  340   a , . . . ,  340   m  are deactivated to disconnect the unselected word lines  275 U to be floating. The voltage level of the selected in-phase block select signals XD  330 S, indicating that a block  410 S is selected is set to approximately the voltage level of the ground reference voltage source (0.0V) such that the very high negative program voltage is coupled from the selected row decode circuit  340   a , . . . ,  340   n  through the PMOS high voltage isolator  350   a , . . . ,  350   m  to the selected word line  275 S. The voltage level of the out-of-phase block select signals XD  330 U, indicating that a block is unselected, is set to the very high negative program voltage to turn off all the voltages from the unselected high voltage power supply voltage line XT  335 U and XT 335 SU to the force unselected word line  275 SU and  275 U to be disconnected and allowed to float. The selected N-type well NW  352 S of the selected block and the N-type wells  352 U of the unselected blocks  410 U are connected to the voltage level of approximately the ground reference voltage source (0.0V). The isolation signal ISOB  366  is set to a very large program activation voltage level of approximately −12.0V to activate the PMOS high voltage isolators  350   a , . . . ,  350   m  to transfer the very high negative program voltage to the selected word lines  275 S and the voltage level of the ground reference voltage source (0.0V) to the unselected word lines  275  SU and disconnecting the unselected word lines  275 U such that they are floating. The out of phase read signal RDB  364  is set to the very high negative program voltage. The positive high voltage power source VPX  327  is set to the voltage level of the ground reference voltage source (0.0V) and the negative high voltage power source VNX  326  is set to the very high negative program voltage. To enable the passage of the very high negative program voltage from the negative high voltage power source VNX  326 , the negative power supply enable signal ENVNX  328  is set to the voltage level of the power supply voltage source VDD. 
         [0107]    Referring now to  FIG. 12   b , the selected select gate line  280 S is set to the very high positive program voltage that is from approximately +8.0V to approximately +10.0V. The unselected select gate lines  280 SU and  280 U are voltage level of the ground reference voltage source (0.0V). Further, the selected select gate lines  280 S is to be set to the voltage level of very high program voltage level of from approximately +8.0V to approximately +10.0V and the unselected select gate lines  280 S is to be set to the voltage level of approximately the ground reference voltage source (0.0V). To have the selected select gate line  280 S set to the very high program voltage level, the selected high voltage power supply voltage line XT  435 S associated with the selected select gate lines  280 S set to very high program voltage level. To have the unselected select gate lines  280 SU and  280 U set to the voltage level of the ground reference voltage source (0.0V), the unselected high voltage power supply voltage line XT  435 U associated with the unselected select gate lines  280 U set to the voltage level of the ground reference voltage source (0.0V). The voltage level of the selected in-phase block select signal XD  430 S, indicating that a block is selected is set to approximately the high program select voltage of approximately +10.0V. The voltage level of the unselected in-phase block select signals XD  430 S, indicating that a block is selected, are set to the voltage level of the ground reference voltage source (0.0V). The selected N-type well NS  452 S of the selected block and the N-type wells  452 U of the unselected blocks is set to the high program select voltage of approximately +10.0V. The isolation signal ISOB  466  is set to the voltage level of a negative pass gate activation voltage level of approximately −2.0V to activate the PMOS high voltage isolators  450   a , . . . ,  450   m  to transfer the very high positive program voltage to the selected select gate lines  280 S and the voltage level of the ground reference voltage source (0.0V) to the unselected select gate lines  280  SU and  280 U. The out of phase read signal RDB  464  is set to the voltage level of the ground reference voltage source and the positive high voltage power source VPX  427  is set to the very high positive program voltage that is from approximately +8.0V to approximately +10.0V. The negative high voltage power source VNX  426  is set to the very high negative program voltage. To enable the passage of the very high negative program voltage from the negative high voltage power source VNX  426 , the negative power supply enable signal ENVNX  428  is set to the voltage level of the ground reference voltage source. 
         [0108]    Returning now to  FIG. 10 , after the completion of the program operation (Box  665 ), the page program verify operation is executed (Box  670 ) to determine if the program has been successfully accomplished. If the program operation (Box  665 ) is not successful, a loop counter is tested (Box  675 ) to assess that the maximum number of program trials is not exceeded. If the maximum number of program trials is not exceeded, the loop counter is incremented (Box  680 ) and the page program operation (Box  665 ) is executed repetitively until the maximum number of program trials is exceeded and the nonvolatile memory device is declared as having failed (Box  685 ) or the programming is a success and the nonvolatile memory device is declared as having successfully been erased (Box  690 ). 
         [0109]    Referring to  FIG. 11 , the program verify operation (Box  670 ) is essentially the same as the erase verify (Box  630 ) of  FIG. 9  except the selected word line  275 S is set to the upper boundary of the threshold voltage level Vt 0 H to evaluate the programmed threshold voltage of the selected NMOS floating gate transistors Mc. 
         [0110]      FIG. 13  is a plot of threshold voltage for the floating gate memory transistor in the two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention vs. program time for hot hole injection. In the example illustrated the selected bit lines BL  270 S for the columns that are to be programmed are increased from the high program voltage that is approximately +5.0V to a voltage of approximately +6.0V to activate a Fowler-Nordheim hot-hole injection phenomena. It can be seen that the threshold voltage Vt of the floating-gate memory transistor MC of the EEPROM configured memory cells  5  are able to be programmed to a lower voltage level  700  of approximately +1.0V in approximately 300 μs. The setting of the selected bit lines BL  270 S for the columns that are to be programmed to the higher program voltage is approximately +6.0V allows the Fowler-Nordheim hot-hole injection phenomena or maintaining the high program voltage of approximately +5.0V allows a slower Fowler-Nordheim drain edge injection. The program current for each cell in these examples is approximately 1.0 nA. This permits a page program that is similar to that of a NAND flash nonvolatile memory page program operation. 
         [0111]    Returning now to  FIG. 8 , if the operation is determined (Box  650 ) not to be a program operation, the operation is a read operation and the read operation is executed (Box  695 ). The selected page is then read with the voltage levels applied as shown in  FIG. 11 ,  12   a , and  12   b . Referring to  FIG. 11 , the selected word line  275 S and the unselected word lines  275 SU of the selected blocks and the unselected word lines  275 U of the unselected blocks are set to the read voltage threshold VR that is approximately the level of the power supply voltage source VDD. The selected bit line  270 S is set to the first read voltage level of approximately +1.0V. The selected select gate line  280 S is set to the high read select voltage HV″ that is approximately +5.0V and the unselected select gate lines  280 S and  280 SU are set a voltage level of the voltage level of the ground reference voltage source (0.0V). 
         [0112]    Referring to  FIG. 12   a  to discuss the voltage levels of the row decoders  230   a ,  230   b , . . . ,  230   n , . . . ,  245   n , the selected word line  275 S and the unselected word lines  275 SU and  275 U are set to the read voltage threshold VR by setting selected high voltage power supply voltage line XT  335 S and the unselected high voltage power supply voltage line XT  335 SU and  335 U to the voltage level of the read voltage threshold VR. The voltage level of the selected and unselected in-phase block select signals XD  330 S and  330 U, the positive high voltage power source VPX  327 , and the selected and unselected negative N-well biasing voltage lines NW  352 S and NW  352 U are set to the voltage level of the power supply voltage source VDD to pass the read voltage threshold VR to the selected word line  275 S. The out of phase read signal RDB  364 , the first high negative voltage source VNX  326 , and the negative power supply enable signal ENVNX  328  are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB  366  is set to a first negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the read voltage threshold VR from the selected and unselected high voltage power supply voltage line XT  335 S and XT  335 U to the selected word line  275 S and the unselected word lines  275 SU and  275 U. 
         [0113]    Returning to  FIG. 11 , the selected bit lines BL  270 S for the selected columns are pre-charged to the first read voltage level of approximately +1.0V for sensing the status of the selected floating-gate memory transistor MC of the EEPROM configured memory cells  5  on the activated columns. The selected select gate lines  280 S for the selected block is set to the voltage level of the high read select voltage HV″ of approximately +5.0V to fully couple the read voltage threshold VR from the bit lines  270   a , . . . ,  270   k  to the selected floating-gate memory transistors MC. 
         [0114]    Referring to  FIG. 12   b  to discuss the voltage levels of the select gate decoders  245   a ,  245   b , . . . ,  245   m , the selected select gate line  280 S is set to the high read select voltage HV″ by setting selected high voltage power supply voltage line XT  435 S to the high read select voltage HV″. The unselected select gate lines  280 SU and  280 U are set to the voltage level of the ground reference voltage source (0.0V) by setting the unselected high voltage power supply voltage line XT  435 SU and  435 U to the voltage level of the ground reference voltage source (0.0V). The voltage level of the selected in-phase block select signals XD  430 S, selected and unselected negative N-well biasing voltage lines NW  452 n and NW  452 U, and the positive high voltage power source VPX  427  are set to the high read select voltage HV″. The unselected in-phase block select signals  430 U, negative high voltage power source VNX  426 , the out of phase read signal RDB  464 , and the negative power supply enable signal ENVNX  428  are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB  466  is set to a second negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the lower boundary of the high read select voltage HV″ from the selected high voltage power supply voltage line XT  435 S to the selected select gate line  280 S. Further, the voltage levels, as described, fully pass voltage level of the ground reference voltage source (0.0V) from the unselected high voltage power supply voltage line XT  435 U to the unselected select gate lines  280 U and  280 SU. 
         [0115]    Refer to  FIGS. 14 and 15  for a summary of the erase and program operations of the floating-gate memory transistor MC of the EEPROM configured memory cells  5  of  FIG. 5  within the EEPROM memory array  205  of  FIG. 4 .  FIG. 14  is a timing diagram for erasing and erase verification of a block of the nonvolatile memory device of  FIG. 5 . During the erase operation  620  between the time τ 0  and the time τ 1 . The voltage levels are as described above for  FIGS. 11 ,  12   a , and  12   b  to initiate an Fowler-Nordheim channel tunneling phenomena to inject more electrons to the floating-gate to increase the threshold voltage Vt of the floating-gate memory transistor MC of the EEPROM configured memory cells  5  to greater than the lower boundary of the threshold voltage Vt 1 L that is approximately +4.0V. 
         [0116]    The erase verify operation  625  has two segments a pre-charge period  626  and the verification period  627 . The pre-charge period  626  is between the time τ 1  and the time τ 2 . At this time, the selected bit line  270 S is pre-charged to the second read voltage level that is approximately the voltage level of the power supply voltage source VDD less a threshold voltage Vt of an NMOS transistor. In the verification time between the time τ 2  and the time τ 3 , the pre-charged level of the second read voltage level is discharged to approximately 0.0V when the memory cells have not been successfully erased and has a threshold voltage level that is less than the lower boundary of the erased threshold voltage level Vt 1 L. If the EEPROM configured nonvolatile memory cells  5  are erased, the second read voltage level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells  5  is greater than the lower boundary of the erased threshold voltage level Vt 1 L. The Y-pass gate and sense amplifier  260   b  of  FIG. 4  determines if the floating-gate memory transistor MC of the EEPROM configured memory cells  5  are erased and has achieved the threshold voltage level representing the datum of a logical “1”. If the floating-gate memory transistor MC of the EEPROM configured memory cells  5  is not erased, the data register and sense amplifier  260  of  FIG. 4  determines that the floating-gate memory transistor MC of the EEPROM configured memory cells  5  has not achieved the threshold voltage level representing a datum of logical “1”. The voltage levels as shown are established as described above for  FIGS. 11 ,  12   a , and  12   b.    
         [0117]      FIG. 15  is a timing diagram for programming and program verification of a block of the nonvolatile memory device of  FIG. 5 . During the program operation  665  between the time τ 0  and the time τ 1 . The voltage levels are as described above for  FIGS. 11 ,  12   a , and  12   b  to initiate an Fowler-Nordheim drain edge tunneling phenomena to extract electrons to the floating-gate to decrease the threshold voltage Vt of the floating-gate memory transistor MC of the selected EEPROM configured memory cells  5  on the selected bit lines  270 S to less than the upper boundary of the threshold voltage Vt 0 H that is approximately +1.0V. For the floating-gate memory transistor MC of the unselected EEPROM configured memory cells  5  on the unselected bit lines  270 U, the program inhibit voltage level that is the ground reference voltage source is applied to the unselected bit lines  270 U. 
         [0118]    The program verify operation  670  has two segments a pre-charge period  671  and the verification period  672 . The pre-charge period  671  is between the time τ 1  and the time τ 2 . At this time, the selected bit lines  270 S are pre-charged to approximately the voltage level of the power supply voltage source VDD less a threshold voltage Vt of an NMOS transistor. In the verification time between the time τ 2  and the time τ 3 , the pre-charged level of the second read voltage is discharged to approximately 0.0V when the memory cell has not been successfully programmed and has a threshold voltage level that is less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells  5  are not programmed, the pre-charged level will be maintained when the threshold voltage of the programmed EEPROM configured nonvolatile memory cells  5  is greater than the upper boundary of the programmed threshold voltage level. The data register and sense amplifier  260  of  FIG. 4  determines if the floating-gate memory transistor MC of the EEPROM configured memory cells  5  are programmed and has achieved the threshold voltage level representing the datum of a logical “0”. If the floating-gate memory transistor MC of the EEPROM configured memory cells  5  is not programmed, the data register and sense amplifier  260  of  FIG. 4  determines that the floating-gate memory transistor MC of the EEPROM configured memory cells  5  has not achieved the threshold voltage level representing a datum of logical “0”. The voltage levels as shown are established as described above for  FIGS. 11 ,  12   a , and  12   b.    
         [0119]    The description of the nonvolatile memory device  200  of  FIG. 4  incorporating EEPROM configured memory cells having a floating-gate memory transistor and a floating gate select transistor. In other embodiments, the EEPROM configured memory cells include charge trapping transistor formed with a layers of silicon, a first layer of silicon dioxide, silicon nitride, a second layer of silicon oxide and a layer of polycrystalline silicon commonly referred to as a SONOS charge trapping transistor to form a charge trapping memory transistor and a charge trapping select transistor within the EEPROM configured memory cells to embody the principles of this invention. Further, as shown in  FIG. 14 , other voltage levels may be used for reading, programming, erasing and verifying the EEPROM configured memory cells in other embodiments and still be in keeping with the principles of this invention. One key aspect of the principles of this invention is that the structure of the row decoder  220 , the select gate decoder  240 , and the data register and Sense Amplifier  260  of  FIG. 4  provide the operating voltages voltage levels that do not exceed the drain-to-source breakdown voltage of the transistors used to construct the row decoder  220 , the select gate decoder  240 , and the data register and Sense Amplifier  260  of  FIG. 4 . 
         [0120]    While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Technology Classification (CPC): 6