Patent Abstract:
A source driver of an LCD includes a first and second power sources, a first and second inversion units, a first and second charging switches, and a first and second discharging switches. The first charging switch is coupled to the first power source, a first end of the first inversion unit, and a second end of the second inversion unit. The second charging switch is coupled to the first power source, a first end of the second inversion unit, and a second end of the first inversion unit. The first discharging switch is coupled to the second power source, the second end of the first inversion unit, and the first end of the second inversion unit. The second discharging switch is coupled to the second power source, the second end of the second inversion unit, and the first end of the first inversion unit.

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to an integrated circuit capable of synchronizing multiple outputs, and more particularly, to a source driver of a display device capable of synchronizing multiple outputs.  
         [0003]     2. Description of the Prior Art  
         [0004]     [Liquid crystal display (LCD) devices are used in various devices such as personal computers or television screens due to their advantages of thinness, light weight, and low power consumption. Color liquid crystal display devices with an active matrix system in particular, which are advantageous for controlling image quality with high definition, have become dominant.  
         [0005]      FIG. 1  shows a diagram of a prior art liquid crystal display device  10  including an LCD panel  12 , a controller  14 , a plurality of gate drivers  16 , and a plurality of source drivers  20 - 2   n.  Though the details of the LCD panel  12  are not illustrated, the LCD panel  12  is constituted from a structure including a semiconductor substrate with transparent pixel electrodes and thin film transistors (TFTs) disposed thereon, an opposing substrate with one transparent electrode formed on an entire surface thereof, and a liquid crystal sealed between these two opposing substrates. Then, by controlling the TFTs, a predetermined voltage is applied to each pixel electrode, and the transmissivity or reflectivity of the liquid crystal is changed by a potential difference between each pixel electrode and the electrode on the opposing substrate. A scanning signal in a pulse form is sequentially transmitted to a scan line on the LCD panel  12  from a corresponding gate driver  16 . TFTs connected to the gate line to which a pulse is applied are all turned on. At this point, gray-scale voltages are supplied to the data lines of the LCD panel  12  from the respective source drivers  20 - 2   n  and applied to pixel electrodes through the turned-on TFTs. Then, when the TFTs connected to the gate line to which no pulse is applied any longer are turned off, potential differences between the pixel electrodes and the opposing substrate electrode are held for a period until subsequent gray-scale voltages are applied to the pixel electrodes. Then, by sequential pulse application, predetermined gray-scale voltages are applied to all pixel electrodes. By performing gray-scale voltage rewriting in each frame period, an image can be displayed.  
         [0006]      FIG. 2  shows a diagram of the source driver  20  of the liquid crystal display device  10  constituting an interface circuit for chip-to-chip data transfer. Since the source drivers  21  - 2   n  have the same structure as the source driver  20  shown in  FIG. 2 , corresponding illustrations and descriptions will be omitted. The source driver  20  includes an RSDS (reduced swing differential signaling) receiver  30 , a shift register  40 , a data capturing circuit  50 , a latch  60 , a level shifter  70 , a digital-to-analog conversion circuit (which will be hereinafter referred to as a D/A converter)  80 , and an output buffer  90 . Based on the input signal INV 1 , the RSDS receiver  30  generates the output signal OUT 1  and a data signals DATA to the shift register  40  and the data capturing circuit  50 , respectively. The latch  60  holds the data signals captured by the data capturing circuit  50  at the timing of the front edges of the latch signals STB, and then collective supplies the latched data signals to the level shifter  70  during each horizontal period. The level shifter  70  increases the voltage levels of the data signals DATA from the latch  60 , and then outputs the data signals to the D/A converter  80 . The D/A converter  80  supplies gray scale voltages corresponding to the logic values of the data signals to the output buffer  90 , which then outputs the gray-scale voltages at the timing of the rear edges of the latch signals STB. For the liquid crystal display device  10  to function efficiently, the output signals supplied by the RSDS receivers (referred to as  30 - 3   n  in  FIG. 3 ) of the source drivers  21 - 2   n  have to be synchronized.  
         [0007]     Since the input signals are generated by the controller  14 , different input signals encounter different resistance according the distances between the controller  14  and corresponding RSDS receivers.  FIG. 3  is a diagram showing an equivalent circuit of the RSDS receiver  30 - 3   n  of the source drivers  20 - 2   n.  In  FIG. 3 , VDD and VSS are power sources supplying power to the RSDS receivers  30 - 3   n  via a power line PL and a ground line GL, respectively.  11 - 1   n  are analog current sources. RD 1 -RDn are parasitic resistors of the power line PL, and RS 1 -RSn are parasitic resistors of the ground line GL. VD 1 -VDn and VS 1 -VSn represent the bias voltages of the RSDS receivers  30 - 3   n,  respectively. Usually the RSDS receivers  30 - 3   n  are disposed in a way such that the parasitic resistors RD 1 -RDn and RS 1 -RSn have the same resistance. The voltage difference established across each parasitic resistor when the liquid crystal display device  10  is operating is represented by A. The bias voltages VD 1 -VDn can be respectively represented by VDD-Δ, VDD- 2 *Δ, . . . , VDD-n*Δ, and the bias voltages VS 1 -VSn can be respectively represented by VSS+Δ, VSS+2*Δ, . . . , VSS+n*Δ. Since each RSDS receiver has different bias voltages, the output signals OUT 1 -OUTn cannot be outputted simultaneously. Therefore, the performance of the prior art liquid crystal display device  10  cannot be optimized.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention provides an integrated circuit capable of synchronizing multiple outputs comprising a first power source, a second power source, a first and second units for providing a plurality of output voltages at corresponding output ends, a first charging switch, a second charging switch, a first discharging switch, and a second discharging switch. The first charging switch includes a first end coupled to the first power source, a second end coupled to a first end of the first inversion unit, and a control end coupled to a second end of the second inversion unit. The second charging switch includes a first end coupled to the first power source, a second end coupled to a first end of the second inversion unit, and a control end coupled to a second end of the first inversion unit. The first discharging switch includes a first end coupled to the second power source, a second end coupled to the second end of the first inversion unit, and a control end coupled to the first end of the second inversion unit. The second discharging switch includes a first end coupled to the second power source, a second end coupled to the second end of the second inversion unit, and a control end coupled to the first end of the first inversion unit.  
         [0009]     The present invention also provides a circuit for synchronizing outputs of a first and a second output buffers, each of which has a first and second end for receiving bias voltages, the circuit comprising a first switch having a first end coupled to receive a first voltage, a second end coupled to the first end of the first output buffer, and a control end coupled to the second end of the second output buffer; a second switch having a first end coupled to receive the first voltage, a second end coupled to the first end of the second output buffer, and a control end coupled to the second end of the first output buffer; a third switch having a first end coupled to receive a second voltage, a second end coupled to the second end of the first output buffer, and a control end coupled to the first end of the second output buffer; and a fourth switch having a first end coupled to receive the second voltage, a second end coupled to the second end of the second output buffer, and a control end coupled to the first end of the first output buffer.  
         [0010]     The present invention also provides a circuit for synchronizing outputs of a first, second and third output buffers, each of which has a first and second end for receiving bias voltages, the circuit comprising a first switch having a first end coupled to receive a first voltage, a second end coupled to the first end of the first output buffer, and a control end coupled to the second end of the second output buffer; a second switch having a first end coupled to receive the first voltage, a second end coupled to the first end of the second output buffer, and a control end coupled to the second end of the first output buffer; a third switch having a first end coupled to receive a second voltage, a second end coupled to the second end of the first output buffer, and a control end coupled to the first end of the second output buffer; a fourth switch having a first end coupled to receive the second voltage, a second end coupled to the second end of the second output buffer, and a control end coupled to the first end of the first output buffer; a fifth switch having a first end coupled to receive the first voltage, a second end coupled to the first end of the third output buffer, and a control end coupled to the second end of the third output buffer; and a sixth switch having a first end coupled to receive the second voltage, a second end coupled to the second end of the third output buffer, and a control end coupled to the first end of the third output buffer.  
         [0011]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  shows a diagram of a prior art liquid crystal display device.  
         [0013]      FIG. 2  shows a diagram of a source driver in the liquid crystal display device in  FIG. 1 .  
         [0014]      FIG. 3  is a diagram showing an equivalent circuit of the RSDS receivers of the liquid crystal display device in  FIG. 1 .  
         [0015]      FIG. 4  is a diagram showing an RSDS receiver circuit according to a first embodiment of the present invention.  
         [0016]      FIG. 5  is a diagram showing an RSDS receiver circuit according to a second embodiment of the present invention.  
         [0017]      FIG. 6  is a diagram showing a CMOS inverter used for the RSDS receiver circuits in  FIGS. 4 and 5 .  
         [0018]      FIG. 7  is a diagram showing a CMOS inverter used for the RSDS receiver circuits in  FIGS. 4 and 5 . 
     
    
     DETAILED DESCRIPTION  
       [0019]     The present invention provides RSDS receiver circuits capable of synchronizing a plurality of outputs.  FIG. 4  is a diagram showing an RSDS receiver circuit  40  according to a first embodiment of the present invention. The first embodiment of the present invention can provide odd output signals simultaneously. For ease of explanation, the RSDS receiver circuit  40  in  FIG. 4  only provides three output signals OUT 1 -OUT 3 . The RSDS receiver circuit  40  includes power sources VDD and VSS, a power line PL, a ground line GL, inversion units U 1 -U 3  (output buffers), P-type metal-oxide semiconductor (PMOS) transistors MP 1 -MP 3 , N-type metal-oxide semiconductor (NMOS) transistors MN 1 -MN 3 , and analog current sources  11 - 13 . The power sources VDD and VSS provide bias voltages to the inversion units U 1 -U 3  via the power line PL and the ground line GL, respectively. RD 1 -RD 3  are parasitic resistors of the power line PL, and RS 1 -RS 3  are parasitic resistors of the ground line GL. Each of the analog current sources I 1 -I 3  is coupled between the power line PL and the ground line GL.  
         [0020]     The PMOS transistors MP 1 -MP 3  provide current paths for charging the inversion units U 1 -U 3 , and the NMOS transistors MN 1 -MN 3  provide current paths for discharging the inversion units U 1 -U 3 . Each of the PMOS transistors MP 1 -MP 3  includes a source coupled to the power line PL and a drain coupled to a first bias end of a corresponding inversion unit. Each of the NMOS transistors MN 1 -MN 3  includes a source coupled to the ground line GL and a drain coupled to a second bias end of a corresponding inversion unit. The gates of the PMOS transistors MP 1 -MP 3  are coupled to the drains of the NMOS transistors MN 3 -MN 1 , respectively. The gates of the NMOS transistors MN 1 -MN 3  are coupled to the drains of the PMOS transistors MP 3 -MP 1 , respectively.  
         [0021]     Usually the inversion units U 1 -U 3  are disposed in a way such that the parasitic resistors RD 1 -RD 3  and RS 1 -RS 3  have the same resistance. The voltage difference established across each parasitic resistor when the RSDS receiver circuit  40  is operating is represented by Δ. The source voltages Vs(MP 1 )-Vs(MP 3 ) of the PMOS transistors MP 1 -MP 3  and the source voltages Vs(MN 1 )-Vs(MN 3 ) of the NMOS transistors MN 1 -MN 3  can be represented by the following formulae: 
 
 Vs ( MP 1)= VDD−Δ;  
 
 Vs ( MP 2)= VDD− 2*Δ; 
 
 Vs ( MP 3)= VDD− 3*Δ; 
 
 Vs ( MN 1)= VSS+Δ;  
 
 Vs ( MN 2)= VSS+ 2*Δ; 
 
 Vs ( MN 3)= VSS+ 3*Δ; 
 
         [0022]     When the PMOS transistors MP 1 -MP 3  and the NMOS transistors MN 1 -MN 3  are turned on, the drain-to-source voltages of the transistors are very small and can thus be regarded as zero. Therefore, the drain voltages Vd(MP 1 )-Vd(MP 3 ) of the PMOS transistors MP 1 -MP 3  and the drain voltages Vd(MN 1 )-Vd(MN 3 ) of the NMOS transistors MN 1 -MN 3  can be represented by the following formulae: 
 
 Vd ( MP 1)≅ Vs ( MP 1); 
 
 Vd ( MP 2)≅ Vs ( MP 2); 
 
 Vd ( MP 3)≅ Vs ( MP 3); 
 
 Vd ( MN 1)≅ Vs ( MN 1); 
 
 Vd ( MN 2)≅ Vs ( MN 2); 
 
 Vd ( MN 3)≅ Vs ( MN 3); 
 
         [0023]     Since the gates of the PMOS transistors MP 1 -MP 3  are coupled to the drains of the NMOS transistors MN 3 -MN 1 , respectively, the absolute values of the gate-to-source voltages Vgs(MP 1 )-Vgs(MP 3 ) of the PMOS transistors MP 1 -MP 3  can be represented by the following formulae: 
 
 |Vgs ( MP 1)|=| Vs ( MN 3)− Vs ( MP 1)| ≅VDD−VSS− 4*Δ; 
 
| Vgs ( MP 2)|=| Vs ( MN 2)− Vs ( MP 2)| ≅VDD−VSS− 4*Δ; 
 
| Vgs ( MP 3)|= |Vs ( MN 1)− Vs ( MP 3)|≅ VDD−VSS− 4*Δ; 
 
         [0024]     Since the gates of the NMOS transistors MN 1 -MN 3  are coupled to the drains of the PMOS transistors MP 3 -MP 1 , respectively, the gate-to-source voltages Vgs(MN 1 )-Vgs(MN 3 ) of the NMOS transistors MN 1 -MN 3  can be represented by the following formulae: 
 
 Vgs ( MN 1)= Vs ( MP 3)− Vs ( MN 1)≅ VDD−VSS− 4*Δ; 
 
 Vgs ( MN 2)= Vs ( MP 2)− Vs ( MN 2)≅ VDD−VSS− 4*Δ; 
 
 Vgs ( MN 3)= Vs ( MP 1)− Vs ( MN 3)≅ VDD−VSS− 4*Δ; 
 
         [0025]     Since the absolute values of the gate-to-drain voltages of all transistors in the RSDS receiver circuit  40  are the same, the transistors can be turned on simultaneously. Therefore, the transistors provide the same driving ability for the inversion units U 1 -U 3 . By adjusting the sizes (W/L ratios), the NMOS and PMOS transistors can provide signals having the same rise and fall time, thereby synchronizing the output voltages OUT 1 -OUT 3  for subsequent signal sampling.  
         [0026]      FIG. 5  is a diagram showing an RSDS receiver circuit  50  according to a second embodiment of the present invention. The second embodiment of the present invention can provide even output voltages simultaneously. For ease of explanation, the RSDS receiver circuit  50  in  FIG. 5  only provides four output voltages OUT 1 -OUT 4 . The RSDS receiver circuit  50  includes power sources VDD and VSS, a power line PL, a ground line GL, inversion units U 1 -U 4 , PMOS transistors MP 1 -MP 4 , NMOS transistors MN 1 -MN 4 , and analog current sources I 1 -I 4 . The power sources VDD and VSS provide bias voltages to the inversion units U 1 -U 4  via the power line PL and the ground line GL, respectively. RD 1 -RD 4  are parasitic resistors of the power line PL, and RS 1 -RS 4  are parasitic resistors of the ground line GL. Each of the analog current sources I 1 -I 4  is coupled between the power line PL and the ground line GL.  
         [0027]     The PMOS transistors MP 1 -MP 4  provide current paths for charging the inversion units U 1 -U 4 , and the NMOS transistors MN 1 -MN 4  provide current paths for discharging the inversion units U 1 -U 4 . Each of the PMOS transistors MP 1 -MP 4  includes a source coupled to the power line PL and a drain coupled to a first bias end of a corresponding inversion unit. Each of the NMOS transistors MN 1 -MN 4  includes a source coupled to the ground line GL and a drain coupled to a second bias end of a corresponding inversion unit. The gates of the PMOS transistors MP 1 -MP 4  are coupled to the drains of the NMOS transistors MN 4 -MN 1 , respectively. The gates of the NMOS transistors MN 1 -MN 4  are coupled to the drains of the PMOS transistors MP 4 -MP 1 , respectively.  
         [0028]     Usually the inversion units U 1 -U 4  are disposed in a way such that the parasitic resistors RD 1 -RD 4  and RS 1 -RS 4  have the same resistance. The voltage difference establish across each parasitic resistor when the RSDS receiver circuit  50  is operating is represented by Δ. The source voltages Vs(MP 1 )-Vs(MP 4 ) of the PMOS transistors MP 1 -MP 4  and the source voltages Vs(MN 1 )-Vs(MN 4 ) of the NMOS transistors MN 1 -MN 4  can be represented by the following formulae: 
 
 Vs ( MP 1)= VDD−Δ;  
 
 Vs ( MP 2)= VDD− 2*Δ; 
 
 Vs ( MP 3)= VDD− 3*Δ; 
 
 Vs ( MP 4)= VDD− 4*Δ; 
 
 Vs ( MN 1)= VSS+Δ;  
 
 Vs ( MN 2)= VSS+ 2*Δ; 
 
 Vs ( MN 3)= VSS+ 3*Δ; 
 
 Vs ( MN 4)= VSS+ 4*Δ; 
 
         [0029]     When the PMOS transistors MP 1 -MP 4  and the NMOS transistors MN 1 -MN 4  are turned on, the drain-to-source voltages of the transistors are very small and can thus be regarded as zero. Therefore, the drain voltages Vd(MP 1 )-Vd(MP 4 ) of the PMOS transistors MP 1 -MP 4  and the drain voltages Vd(MN 1 )-Vd(MN 4 ) of the NMOS transistors MN 1 -MN 4  can be represented by the following formulae: 
 
 Vd ( MP 1)≅ Vs ( MP 1); 
 
 Vd ( MP 2)≅ Vs ( MP 2); 
 
 Vd ( MP 3)≅ Vs ( MP 3); 
 
 Vd ( MP 4)≅ Vs ( MP 4); 
 
 Vd ( MN 1)≅ Vs ( MN 1); 
 
 Vd ( MN 2)≅ Vs ( MN 2); 
 
 Vd ( MN 3)≅ Vs ( MN 3); 
 
 Vd ( MN 4)≅ Vs ( MN 4); 
 
         [0030]     Since the gates of the PMOS transistors MP 1 -MP 4  are coupled to the drains of the NMOS transistors MN 4 -MN 1 , respectively, the absolute values of the gate-to-source voltages Vgs(MP 1 )-Vgs(MP 4 ) of the PMOS transistors MP 1 -MP 4  can be represented by the following formulae: 
 
| Vgs ( MP 1)|=| Vs ( MN 4)− Vs ( MP 1)|≅ VDD−VSS− 5*Δ; 
 
| Vgs ( MP 2)|=| Vs ( MN 3)− Vs ( MP 2)|≅ VDD−VSS− 5*Δ; 
 
| Vgs ( MP 3)|= |Vs ( MN 2)− Vs ( MP 3)| ≅VDD−VSS− 5*Δ; 
 
| Vgs ( MP 4)|= |Vs ( MN 1)− Vs ( MP 4)| ≅VDD−VSS− 5*Δ; 
 
         [0031]     Since the gates of the NMOS transistors MN 1 -MN 4  are coupled to the drains of the PMOS transistors MP 4 -MP 1 , respectively, the gate-to-source voltages Vgs(MN 1 )-Vgs(MN 4 ) of the NMOS transistors MN 1 -MN 4  can be represented by the following formulae: 
 
 Vgs ( MN 1)= Vs ( MP 4)− Vs ( MN 1)≅ VDD−VSS− 5*Δ; 
 
 Vgs ( MN 2)= Vs ( MP 3)− Vs ( MN 2)≅ VDD−VSS− 5*Δ; 
 
 Vgs ( MN 3)= Vs ( MP 2)− Vs ( MN 3) ≅VDD−VSS− 5*Δ; 
 
 Vgs ( MN 4)= Vs ( MP 1)− Vs ( MN 4) ≅VDD−VSS− 5*Δ; 
 
         [0032]     Since the absolute values of the gate-to-source voltages of all transistors in the RSDS receiver circuit  50  are the same, the transistors can be turned on simultaneously. Therefore, the transistors provide the same driving ability for the inversion units U 1 -U 4 . By adjusting the sizes (W/L ratios), the NMOS and PMOS transistors can provide signals having the same rise and fall time, thereby synchronizing the output voltages OUT 1 -OUT 4  for subsequent signal sampling.  
         [0033]     The inversion units used in the RSDS receiver circuits  40  and  50  can include complimentary metal-oxide semiconductor (CMOS) inverters.  FIG. 6  is a diagram showing a CMOS inverter  60  used for the inversion units of the RSDS receiver circuits  40  and  50 . The CMOS inverter  60  includes a PMOS transistor MP and an NMOS transistor MN. The gate and the drain of the PMOS transistor MP are coupled to the gate and the drain of the NMOS transistor MN, respectively. When an input signal INV received at the gates of the transistors has a high level (logic 1), the NMOS transistor MN is turned on, and the PMOS transistor MP is turned off, thereby generating an output signal OUT having a low level (logic 0). When the input signal INV has a low level, the NMOS transistor MN is turned off, and the PMOS transistor MP is turned on, thereby generating an output signal OUT having a high level.  
         [0034]      FIG. 7  is a diagram showing another CMOS inverter  70  used for the inversion units of the RSDS receiver circuits  40  and  50 . The CMOS inverter  70  includes PMOS transistors MP 1 -MP 2  and NMOS transistors MN 1 -MN 2 . The gates of the PMOS transistors MP 1  and MP 2  are respectively coupled to INVp and INVN, and the gates of the NMOS transistors MN 1  and MN 2  are respectively coupled to INVN and INVp. The source of the NMOS transistor MN 1 , the drain of the NMOS transistor MN 2 , the drain of the PMOS transistor MP 1 , and the source of the PMOS transistor MP 2  are coupled together. Input signals INVn and INVP are supplied to the gates of the transistors, and a corresponding output signal OUT is generated based on the levels of the input signals INVn and INVP. The inverters shown in  FIGS. 6 and 7  are only two embodiments of the inversion units. Other types of inverters can also be adopted for the RSDS receivers of the present invention.  
         [0035]     In the RSDS receivers of the present inventions, a plurality of PMOS transistors are provided for charging the inversion units, and a plurality of NMOS transistors are provided for discharging the inversion units. The gates of the transistors are coupled, as illustrated in  FIGS. 4 and 5 , so as to compensate different voltage drops caused by the parasitic resistors of the power lines. By adjusting the W/L ratio, the NMOS and PMOS transistors can generate signals having the same rise and fall time, thereby synchronizing multiple output signals for subsequent signal sampling.  
         [0036]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 6