Patent Abstract:
The variable transconductance circuit includes: a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal; first and second MOS transistors for converting the current signal received to a square-root compressed voltage signal; and third and fourth MOS transistors for converting the square-root compressed voltage signal to a linear current signal. A bias current at the first and second MOS transistors and a bias current at the third and fourth MOS transistors are varied to control transconductance.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Divisional of U.S. application Ser. No. 11/481,861, filed Jul. 7, 2006, now U.S. Pat. No. 7,486,139, and claims priority under 35 U.S.C. §119 on Japanese Patent Application No. 2005-198623 filed in Japan on Jul. 7, 2005 and Japanese Patent Application No. 2006-110550 filed in Japan on Apr. 13, 2006, the entire contents of each of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a differential amplifier circuit, and more particularly, to a variable transconductance circuit formed on a semiconductor integrated circuit, and an optical disk device having such a variable transconductance circuit placed on a signal processing path. 
     A conventional transconductance circuit disclosed in Japanese Laid-Open Patent Publication No. 11-68477 will be described with reference to  FIG. 15 . 
     MOS transistors M 50  and M 51  constitute an input differential pair biased with a current Io. When a voltage signal Vi is input, MOS transistors M 56  and M 57  respectively drive gate voltages of MOS transistors M 52  and M 53  so that the gate-source voltages thereof are constant. At this time, the input voltage signal Vi is converted to a current ΔI 1  with a resistance R connected between the sources of the MOS transistors M 50  and M 51 , and the current ΔI 1  flows to the MOS transistors M 52  and M 53 . This relationship is represented by Expression (1) below. The current ΔI 1  is output from the drains of MOS transistors M 54  and M 55 . 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     Vi 
                     R 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     The output current ΔI 1  is input into the drains of MOS transistors M 58  and M 59 . The gate and drain of each of the MOS transistors M 58  and M 59  are connected to each other via a resistance Rg, and the gates thereof are common-connected. At this time, since the equal current flows to the MOS transistors M 58  and M 59 , the current ΔI 1  of Expression (1) flows to the resistances Rg, generating a voltage (V + -V − ) at both ends of the resistances Rg. With this voltage (V + -V − ), the gates of MOS transistors M 60  and M 61  are driven. A drain current difference ΔI 2  between the MOS transistors M 60  and M 61  at this time is represented by Expression (2): 
                           Δ   ⁢           ⁢   I   ⁢           ⁢   2     =       ⁢     k   ⁢           ⁢     β   ⁡     [         (       V   +     -   Vth     )     2     -       (       V   -     -   Vth     )     2       ]                       =       ⁢     4   ⁢           ⁢   k   ⁢         β   ·   Io       ·   Rg         ⁣       ·   Δ     ⁢           ⁢   I   ⁢           ⁢   1                 =       ⁢     4   ⁢           ⁢   k   ⁢         β   ·   Io       ·     Rg   R     ·   Vi                     (   2   )               
where β=charge mobility×capacity of gate oxide film/2, k=(transistor size of MOS transistors M 60  and M 61 )/(transistor size of MOS transistors M 58  and M 59 ), and Vth is a transistor threshold voltage.
 
     From Expression (2), the transconductance (gm) is represented by Expression (3): 
                   gm   =     4   ⁢   k   ⁢         β   ·   Io       ·     Rg   R                 (   3   )               
which indicates that gm is allowed to vary sequentially by varying Io.
 
     Gm is proportional to the square root of lo according to Expression (3). Therefore, to allow gm to vary up to 10 times its minimum value, it is necessary to vary Io up to 100 times its minimum value. In general, the gate-source voltage Vgs and the operating current Io of a MOS transistor have a relationship (Vgs-Vth) ∝√{square root over ( )}Io, in which if lo is increased by 100 times, Vgs-Vth will increase by 10 times. Since Vgs-Vth must be about 0.2 V at minimum to operate the MOS transistor in the saturation region, Vgs-Vth will be 2V at maximum. Low power supply voltage operation is therefore difficult, and also the 100-fold current variation will increase current consumption. Thus, wide-range gm variation and low power consumption are in a trade-off relationship. 
     To solve the problem described above, Japanese Laid-Open Patent Publication No. 2001-292051 discloses a configuration of connecting a plurality of transconductors in parallel to enable wide-range gm variation and low power supply voltage operation. However, this configuration still has problems in current consumption and on-board circuit area. 
     In optical disk devices such as DVDs, for example, a filter circuit used for signal processing must respond to a wide range of signals including a high-speed signal about 100 times as fast as the lowest-speed signal. Also, a variable gain amplifier, which normalizes a variation in signal amplitude caused by a medium and an optical pickup before performing signal processing, is required to provide a wide range of gains including a gain 10 to 20 times as large as the smallest gain. To achieve such a filter circuit and variable gain amplifier, a variable gm circuit serves as an important component. However, with a power supply voltage as low as just about 3V, the conventional variable gm circuit can only secure a variable range up to about five times the gm lowest value for one circuit. Therefore, a plurality of such variable gm circuits are connected in parallel or in series to achieve a filter circuit and variable gain amplifier. This causes the problems of increase in power consumption and on-board circuit area. 
     SUMMARY OF THE INVENTION 
     The variable transconductance circuit according to the present invention includes: a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal (Vi); first and second MOS transistors (M 1 , M 2 ) for converting the current signal received to a square-root compressed voltage signal; and third and fourth MOS transistors (M 3 , M 4 ) for converting the square-root compressed voltage signal to a linear current signal, wherein transconductance is controlled by varying a bias current (Ia) for the first and second MOS transistors (M 1 , M 2 ) and a bias current (Ia) for the third and fourth MOS transistors. Thus, by providing two control parameters (Ia, Ib), gm can be varied in a wide range. For example, a variation up to about 20 times its minimum value can be achieved with a power supply voltage as low as about 3 V. 
     Preferably, in the variable transconductance circuit described above, the voltage-current conversion circuit comprises: two operational amplifiers into which the input voltage signal (Vi) is input; and a resistance (R) interposed between outputs of the two operational amplifiers, each of the outputs of the two operational amplifiers serves as a source follower biased with a first current source ( 1 ) or a second current source ( 2 ), and the current signal is taken from a drain of the source follower, gates of the first and second MOS transistors (M 1 , M 2 ) are grounded with a predetermined bias voltage, and the current signal output from the voltage-current conversion circuit is input into sources of the first and second MOS transistors, sources of the third and fourth MOS transistors (M 3 , M 4 ) are common-connected, a third current source ( 3 ) is connected to the common-connected sources, and a gate of the third MOS transistor (M 3 ) is connected to a source of one of the first and second MOS transistors (M 1 , M 2 ) while a gate of the fourth MOS transistor (M 4 ) is connected to a source of the other first or second MOS transistor (M 1 , M 2 ), the variable transconductance circuit uses drains of the third and fourth MOS transistors (M 3 , M 4 ) as current outputs, and controls transconductance by varying the current (Ia) from the first and second current sources ( 1 ,  2 ) and the current (Ib) from the third current source ( 3 ). 
     Preferably, in the variable transconductance circuit described above, the voltage-current conversion circuit includes: fifth and sixth MOS transistors (M 5 , M 6 ) constituting an input differential pair into which the input voltage signal (Vi) is input; and a resistance (R) interposed between sources of the fifth and sixth MOS transistors (M 5 , M 6 ), each of the fifth and sixth MOS transistors (M 5 , M 6 ) is biased with a first current source ( 1 ) or a second current source ( 2 ) connected to a drain of the fifth or sixth MOS transistor, the source of the fifth MOS transistor (M 5 ) is connected to a drain of one of the first and second MOS transistors (M 1 , M 2 ) while the source of the sixth MOS transistor (M 6 ) is connected to a drain of the other first or second MOS transistor (M 1 , M 2 ), a gate voltage of each of the first and second MOS transistors (M 1 , M 2 ) is driven with a drain voltage of the fifth MOS transistor (M 5 ) or the sixth MOS transistor (M 6 ) whichever is connected to the drain of the first or second MOS transistor, sources of the third and fourth MOS transistors (M 3 , M 4 ) are common-connected, a third current source ( 3 ) is connected to the common-connected sources, and a gate voltage of the third MOS transistor (M 3 ) is driven with the drain voltage of one of the fifth and sixth MOS transistor (M 5 , M 6 ) while a gate voltage of the fourth MOS transistor (M 4 ) is driven with the drain voltage of the other fifth or sixth MOS transistor (M 5 , M 6 ), and the variable transconductance circuit uses drains of the third and fourth MOS transistors (M 3 , M 4 ) as current outputs, and controls transconductance by varying the current (Ia) from the first and second current sources ( 1 ,  2 ) and the current (Ib) from the third current source ( 3 ). 
     Preferably, in the variable transconductance circuit described above, each of the first and second MOS transistors (M 1 , M 2 ) or the third and fourth MOS transistors (M 3 , M 4 ) is composed of a plurality of MOS transistors connected in parallel, and transconductance is controlled by switching. With this configuration, a further wide range of transconductance variation (for example, up to about 100 times the minimum gm) can be achieved. 
     Preferably, the variable transconductance circuit described above further includes a transconductance control circuit for generating the bias currents (Ia, Ib), wherein the transconductance control circuit includes: a square circuit ( 20 ) comprising a trans-linear loop circuit including vertically-connected seventh and eighth MOS transistors (M 101 , M 102 ) with a gate and drain of each transistor being connected to each other, a ninth MOS transistor (M 103 ) of which gate is connected to the gate of the eighth MOS transistor (M 102 ), and a tenth MOS transistor (M 104 ) of which gate is connected to a source of the ninth MOS transistor (M 103 ), the square circuit comprising a supply means for increasing a current flowing through each of the ninth and tenth MOS transistors (M 103 , M 104 ) by several times and supplying the resultant current to the seventh and eighth MOS transistors (M 101 , M 102 ), the square circuit using a drain of the eighth MOS transistor (M 102 ) as a current input, and connecting one of the ninth and tenth MOS transistors (M 103 , M 104 ) to a fourth current source ( 13 ) while outputting a current flowing through the other ninth or tenth MOS transistor as a current mirror output, and the current mirror output serves as the bias current (Ia or Ib). With this configuration, transconductance control according to linearity or exponential can be achieved. 
     Preferably, in the variable transconductance circuit described above, the supply means includes a current mirror for increasing a current flowing through each of the ninth and tenth MOS transistors (M 103 , M 104 ) by several times and supplying the resultant current to the seventh and eighth MOS transistors (M 101 , M 102 ). 
     Preferably, in the variable transconductance circuit described above, the mirror ratio of the current mirror output is variable. With this configuration, transconductance control characteristics according to desired linearity or exponential can be achieved. 
     Preferably, in the variable transconductance circuit described above, the current value of the fourth current source is variable. With this configuration, transconductance control according to desired linearity or exponential can be achieved. 
     The optical disk device according to the present invention includes a filter including the variable transconductance circuit described above and a capacitance element or a variable gain amplifier including the variable transconductance circuit described above and a resistance element, placed on a signal processing path. 
     Effects of the variable gm circuit according to the present invention will be briefly described. 
     The first effect is that a variable gm circuit permitting a wide range of variation with a low power supply voltage can be attained in a small scale. The reason for this is that the current change amount required for varying gm can be reduced to enable a wide range of gm variation with one circuit. 
     The second effect is that high gm can be attained with low power consumption. The reason for this is that gm can be determined with the current ratio. 
     The variable transconductance circuit according to the present invention is applicable to filter circuits and variable gain amplifiers for optical disk devices such as DVDs, for example. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a variable transconductance circuit of Embodiment 1 of the present invention. 
         FIG. 2  shows a variable transconductance circuit of Embodiment 2 of the present invention. 
         FIG. 3  shows a variable transconductance circuit of Embodiment 3 of the present invention. 
         FIG. 4  shows an example of configuration of an operational amplifier shown in  FIG. 3 . 
         FIG. 5  shows an alteration to a square root expansion section  11  shown in  FIGS. 1  to  3 . 
         FIGS. 6A and 6B  show examples of a transconductance control circuit provided for any of the variable transconductance circuits of  FIGS. 1 to 3 . 
         FIG. 7  shows an example of configuration of a square circuit included in the transconductance control circuit of  FIG. 6B . 
         FIG. 8  shows another example of configuration of the square circuit included in the transconductance control circuit of  FIG. 6B . 
         FIG. 9  shows transconductance control characteristics. 
         FIG. 10  shows an example of connection between the variable conductance circuit of  FIG. 2  and the square circuits. 
         FIG. 11  shows an approximate error of the transconductance control characteristics. 
         FIG. 12  shows an example of configuration of an optical disk device. 
         FIG. 13  shows an example of configuration of a data signal generation circuit in  FIG. 12 . 
         FIGS. 14A and 14B  show examples of configurations of a variable gain amplifier and a low-pass filter, respectively, using the variable transconductance circuit according to the present invention. 
         FIG. 15  shows a conventional variable transconductance circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that the same or equivalent components are denoted by the same reference numerals. 
     Embodiment 1 
       FIG. 1  shows a variable transconductance circuit of Embodiment 1. In a linear voltage current conversion section, which is configured as described in the prior art, an input voltage signal Vi is converted to a current with an inter-source resistance R between MOS transistors M 5  and M 6 , to give a drain current for MOS transistors M 1  and M 2 . At this time, the gate voltage difference between the MOS transistors M 1  and M 2  is represented by expression (4): 
                     Δ   ⁢           ⁢   Vg     =       (           Ia   +     Vi   R         k   ⁢           ⁢     1   ·   β           -         Ia   -     Vi   R         k   ⁢           ⁢     1   ·   β             )     .             (   4   )               
where k 1 =gate width/gate length of MOS transistors M 1  and M 2  and β=charge mobility×capacity of gate oxide film/2.
 
     The gate voltages of the MOS transistors M 1  and M 2  are driven with the sources of MOS transistors M 7  and M 8  each constituting a source follower. If a substrate bias effect of the MOS transistors M 7  and M 8  is neglected, the above value ΔVg is equal to the gate voltage difference between the MOS transistors M 7  and M 8 , that is, the drain voltage difference between the MOS transistors M 5  and M 6 . The drain voltages of the MOS transistors M 5  and M 6  are respectively input into the gates of MOS transistors M 4  and M 3 . A current source  3  for supplying a current Ib is connected to the common-connected sources of the MOS transistors M 3  and M 4 . The drains of the MOS transistors M 3  and M 4  are connected to MOS transistors M 9  and M 10  of which gates are common-connected. When ΔVg is input, a current ΔIout output from the drains of the MOS transistors M 3  and M 4  is represented by expression (5): 
                     Δ   ⁢           ⁢   Iout     =     k   ⁢           ⁢     2   ·   β   ·   Δ     ⁢           ⁢     Vg   ·           2   ·   Ib       k   ⁢           ⁢     2   ·   β         -     Δ   ⁢           ⁢     Vg   2                       (   5   )               
where k 2  is the gate width/gate length of the MOS transistors M 3  and M 4 .
 
     Substitution of Expression (4) into Expression (5) yields Expression (6): 
                           Δ   ⁢           ⁢   Iout     =       ⁢         2     ·   k     ⁢           ⁢     3   ·     (         Ia   +     Vi   R         -       Ia   -     Vi   R           )     ·                       ⁢           I   ⁢           ⁢   b       k   ⁢           ⁢   3       -   Ia   +         Ia   2     -       (     Vi   R     )     2                         ≅       ⁢       Vi   R     ⁢           2   ·   k     ⁢           ⁢     3   ·   I     ⁢           ⁢   b     Ia       ⁢     (     First   ⁢     -     ⁢   order   ⁢           ⁢   approximation     )                     (   6   )               
where k 3 =k 2 /k 1 . From the above, gm is represented by Expression (7):
 
     
       
         
           
             
               
                 
                   gm 
                   = 
                   
                     
                       1 
                       R 
                     
                     ⁢ 
                     
                       
                         
                           
                             2 
                             · 
                             k 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             3 
                             · 
                             I 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           b 
                         
                         Ia 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     It is found from the above expression that by varying Ia and Ib up to 10 times their minimum values (Ia×1/10, Ib×10), gm is allowed to vary up to 10 times its minimum value. Therefore, gm is allowed to vary over a wide range with a current variation smaller than that in the prior art discussed with reference to Expression (3), that is, with a low power supply voltage. Also, since gm can be determined with the current ratio, it is advantageously possible to achieve high gm with a smaller operating current. 
     Embodiment 2 
       FIG. 2  shows a variable transconductance circuit of Embodiment 2. In the variable transconductance circuit of  FIG. 1 , the gate voltages of the MOS transistors M 4  and M 3  are automatically determined with the gate-source voltages of the MOS transistors M 1  and M 7  and the MOS transistors M 2  and M 8 , respectively. Therefore, to allow operation of the MOS transistors M 3  and M 4  in the saturation region, the output dynamic range is automatically determined, and this restricts the degree of design freedom. To solve this problem, in the variable transconductance circuit of  FIG. 2 , a level shift circuit  4  is interposed each between the gates of the MOS transistors M 1  and M 4  and between the gates of the MOS transistors M 2  and M 3 . By appropriately setting the DC level shift amount of each of the level shift circuits  4 , the degree of design freedom of the output dynamic range is improved. Alternatively, if the input impedance is sufficiently high, the level shift circuit  4  may be interposed each between the drain of the MOS transistor M 5  and the gate of the MOS transistor M 4  and between the drain of the MOS transistor M 6  and the gate of the MOS transistor M 3  in  FIG. 1 . 
     Embodiment 3 
     In the configurations in  FIGS. 1 and 2 , the MOS transistors M 1 , M 5  and M 7  or the MOS transistors M 2 , M 6  and M 8  constitute a negative feedback loop. The unity gain frequency f 0  of such a loop and Ia have the relationship of Expression (8) below, and thus the circuit frequency characteristic varies with gm.
 
f0∝√{square root over (Ia)}   (8)
 
       FIG. 3  shows a variable transconductance circuit of Embodiment 3 for solving the above problem. The MOS transistor M 5  and a current source  1  constitute an output source follower for an operational amplifier, and the MOS transistor M 6  and a current source  2  constitute another output source follower. The resistance R is connected between the outputs of the source followers. When the voltage signal Vi is input, the voltage difference of Vi also occurs at both ends of the resistance R, allowing flow of a signal current of Vi/R. This signal current, output from the drains of the MOS transistors M 5  and M 6 , is input into the MOS transistors M 1  and M 2  of which gates are grounded with Bias  1 . The gate-source voltage difference between the MOS transistors M 1  and M 2  at this time is as represented by Expression (4) above. Thus, the circuit of  FIG. 3  can obtain the transconductance represented by Expression (7) above like the circuit operation described in Embodiment 1. 
       FIG. 4  shows an example of configuration of the operational amplifier shown in  FIG. 3 . The unity gain frequency f 0  of the operational amplifier is as represented by Expression (9) below. As long as the frequency band of the source follower composed of the MOS transistor M 5  and the current source  1  is sufficiently high with respect to f 0 , the frequency characteristic of the transconductance circuit of  FIG. 3  will not vary even if gm is varied.
 
f0∝√{square root over (Id)}   (9)
 
     Note that in  FIGS. 1 ,  2  and  3 , the case that input transistors were N-channel transistors was described. It is however needless to mention that the channel conductivity type of the transistors may be reversed. 
     Also, in  FIGS. 1 ,  2  and  3 , the resistance R may be replaced with a MOS transistor operating in the linear region, and the gate voltage of the transistor may be varied together with Ia and Ib. This permits gm to be variable in a wider range. 
     Embodiment 4 
       FIG. 5  shows an alteration to a square root expansion section  11  shown in  FIGS. 1 to 3 . The gm of the variable transconductance circuits of  FIGS. 1 to 3  depends on the transistor size ratio k 3  of the MOS transistors M 1  and M 2  to the MOS transistors M 3  and M 4 , as is found from Expression (7). In  FIG. 5 , in place of each of the MOS transistors M 3  and M 4 , a plurality of MOS transistors are connected in parallel and switched with control signals φ 1  to φ 3 . This permits k 3  to vary, and thus gm can be made variable. Although the MOS transistors M 3  and M 4  were replaced in  FIG. 5 , each of the MOS transistors M 1  and M 2  may be replaced with parallel-connected MOS transistors. 
     Embodiment 5 
       FIGS. 6A and 6B  show examples of a transconductance control circuit  16  provided for any of the variable transconductance circuits of  FIGS. 1 to 3 , denoted by  111 . First, the operation of square circuits  20  included in the transconductance control circuit  16  of  FIG. 6B  will be described with reference to  FIG. 7 . 
     Referring to  FIG. 7 , Iin denotes a current input and cnt denotes a square current output. N-channel transistors M 101  to M 104  constitute a trans-linear loop circuit, while P-channel transistors M 107  to M 110  constitute a current mirror circuit. The current mirror circuit is connected to the drains of the MOS transistor M 103  driven with a current source  13  and the MOS transistor M 104  of which source is grounded. The current mirror circuit multiplies the currents flowing through the MOS transistors M 103  and M 104  by k 1  and k 2 , respectively, sums the multiplied currents, and supplies the resultant current to the MOS transistors M 101  and M 102 . A MOS transistor M 105  constitutes a current mirror circuit that multiplies the current from the MOS transistor M 107  by a and outputs the resultant current. Assuming that the transistor size ratios of the MOS transistors M 102 , M 103  and M 104  to the transistor size of the MOS transistor M 101  as the reference are n 2 , n 3  and n 4 , respectively, Expression (10) below is established among currents I 0 , I 1  and I 2  shown in  FIG. 7 . 
     
       
         
           
             
               
                 
                   
                     
                       
                         I 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         0 
                       
                     
                     + 
                     
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           0 
                         
                         
                           n 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                   = 
                   
                     
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         
                           n 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                     
                     + 
                     
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         
                           n 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     By squaring both terms of the above expression and substituting I 0 =Iin+k 1 ·I 1 +k 2 ·I 2  into this expression, Expression (11) below is obtained: 
                         (     1   +       1     n   ⁢           ⁢   2           )     2     ⁢     (             I   ⁢           ⁢   i   ⁢           ⁢   n     +     k   ⁢           ⁢     1   ·                     I   ⁢           ⁢   1     +     k   ⁢           ⁢     2   ·   I     ⁢           ⁢   2             )       =         I   ⁢           ⁢   1       n   ⁢           ⁢   3       +       I   ⁢           ⁢   2       n   ⁢           ⁢   4       +     2   ·         I   ⁢           ⁢     1   ·   I     ⁢           ⁢   2         n   ⁢           ⁢   3     ⁣       ·   n     ⁢           ⁢   4                       (   11   )               
By substituting Expression (12):
 
                       k   ⁢           ⁢   1     =     1     n   ⁢           ⁢     3   ·       (     1   +       1     n   ⁢           ⁢   2           )     2             ⁢     
     ⁢       k   ⁢           ⁢   2     =     1     n   ⁢           ⁢     4   ·       (     1   +       1     n   ⁢           ⁢   2           )     2                     (   12   )               
into Expression (11) above and arranging the result, Expression (13) below is given, in which I 2  has a square characteristic with respect to the input current Iin.
 
                     I   ⁢           ⁢   2     =         n   ⁢           ⁢     3   ·   n     ⁢           ⁢   4         4   ·   I     ⁢           ⁢   1       ⁢       (     1   +       1     n   ⁢           ⁢   2           )     4     ⁢   I   ⁢           ⁢   i   ⁢           ⁢     n   2               (   13   )               
Multiplying the above value by a gives the output current, and finally Expression (14) below is obtained.
 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       out 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     = 
                     
                       
                         I 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         out 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                       = 
                       
                         E 
                         · 
                         
                           Iin 
                           2 
                         
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   E 
                   = 
                   
                     
                       a 
                       · 
                       
                         
                           n 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             3 
                             · 
                             n 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                         
                           
                             4 
                             · 
                             I 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                     
                     ⁢ 
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               1 
                               
                                 n 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                         
                         ) 
                       
                       4 
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     From the above expression, it is found that since the circuit of  FIG. 7  does not include a device parameter β and has a square characteristic determined with the parameters a, n 2 , n 3  and n 4  and the current I 1  having relative precision, the circuit is advantageously less susceptible to fabrication variation. 
     The current output may be made as shown in  FIG. 8  depending on the polarity of the necessary output current. Alternatively, in the examples of  FIGS. 7 and 8 , the transistor M 104  may be driven with a constant current to allow the current I 1  to be output as current mirror output. If it is desired to change the square characteristic of the square circuits of  FIGS. 7 and 8 , this can be achieved by changing the transistor size ratio a or the current I 1 . 
     Next, control of the transconductance will be described with reference to  FIGS. 6A and 6B , in the case of a circuit in which transconductance varies exponentially with a control signal. 
     In  FIG. 6A , when a control signal x is changed to give Ia∝1+x and Ib∝1−x with a function generator  15 , the transconductance is represented by Expression (15) below from Expression (7) above. 
                   gm   ∝         1   -   x       1   +   x                 (   15   )               
This expression can be approximated to gm ∝ e x  in a specific range of x as shown in  FIG. 9 . Therefore, the transconductance can be varied exponentially.
 
     However, if the range of x is widened in an attempt of widening the variable width of gm, the approximation accuracy deteriorates. To solve this problem, in  FIG. 6B , the transconductance control circuit  16  is provided with the square circuits  20 .  FIG. 10  shows an example of connection of the square circuits  20  with the variable transconductance circuit  111  having the configuration of  FIG. 2 , for example. When the control signal x is changed to give Iin 1 ∝1+x and Iin 2 ∝1−x with the function generator  15 , Ia∝(1+x) 2  and Ib∝(1−x) 2  are given. From Expression (7) above, the transconductance is represented by Expression (16): 
                   gm   ∝       1   -   x       1   +   x               (   16   )               
This expression can be approximated to gm ∝ e 2x  in a specific range of x as shown in  FIG. 9 .  FIG. 11  shows an exponential approximation error between Expressions (15) and (16). By providing the square circuits  20 , the approximation accuracy can be enhanced even if the range of x is widened to widen the variable width of gm.
 
     Embodiment 5 
       FIG. 12  shows an optical disk device of Embodiment 5. The optical disk device includes a spindle motor  101 , an optical pickup  102 , an address signal generation circuit  103 , an address decoder  104 , a servo controller  105 , a servo error signal generation circuit  106 , a data signal generation circuit  107 , a decoder  108 , a CPU  109  and a laser power control circuit  110 . 
     Hereinafter, as one of applications of the variable gm circuit according to the present invention, application thereof to the data signal generation circuit  107  in  FIG. 12  will be described. Note however that the variable gm circuit according to the present invention is also applicable to the address signal generation circuit  103 , the servo error signal generation circuit  106  and the laser power control circuit  110 .  FIG. 13  shows an internal configuration of the data signal generation circuit  107 . 
     A data signal obtained from an optical disk  100  must be subjected to amplitude normalization and noise removal to improve the readability thereof. To accomplish this, a variable gain amplifier  1071  and a low-pass filter  1072  are provided on the signal processing path as shown in  FIG. 13 . The variable gain amplifier  1071  normalizes the signal amplitude with a gain switched in a gain control circuit  1074  in response to the signal amplitude value detected in a read channel circuit  1073 . The low-pass filter  1072  is allowed to change its cut-off frequency under the control of a pass band control circuit  1075  to attain invariably optimal noise removal in response to the medium type and speed of the optical disk  100 .  FIGS. 14A and 14B  show examples of the variable gain amplifier  1071  and the low-pass filter  1072 , respectively, made up of the variable gm circuit according to the present invention. As shown in  FIG. 14A , a resistance is connected to the variable gm circuit  111  to give the variable gain amplifier  1071 , in which the gain is determined with Gm×R. As shown in  FIG. 14B , a capacitance is connected to the variable gm circuit  111  to give the low-pass filter  1072 , in which the cut-off frequency Fc is determined with Gm/C. For simplification, the low-pass filter  1072  of  FIG. 14B  is of a first-order configuration. In actual optical disk devices, however, fifth- to seventh-order low-pass filters may be used. 
     While the present invention has been described in preferred embodiments, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.

Technology Classification (CPC): 7