Patent Abstract:
A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.

Full Description:
[0001]    This application is a divisional application claiming priority to Ser. No. 12/026,793, filed Feb. 6, 2008. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates generally to CMOS (Complementary Metal Oxide Semiconductor) devices and more particularly to CMOS devices having metal gate NFETs (n-channel field effect transistors) and poly-silicon gate PFETs (p-channel field effect transistors). 
       BACKGROUND OF THE INVENTION 
       [0003]    A conventional CMOS device includes an NFET and a PFET electrically coupled together in series. It is known that the operation of the CMOS device would be improved if the NFET has a metal gate electrode and the PFET has a poly gate electrode. Therefore, there is a need for a method for forming a CMOS device having a metal gate NFET and a poly-silicon gate PFET. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention provides a semiconductor structure fabrication method, comprising providing a structure which includes (a) a first semiconductor region and a second semiconductor region, (b) a first gate dielectric region on the first semiconductor region and a second gate dielectric region on the second semiconductor region, (c) a high-K dielectric region having a dielectric constant K on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; patterning the hard mask layer resulting in a first hard mask region and a second hard mask region; and etching the poly-silicon layer with the first and second hard mask regions as blocking masks until a second top surface of the electrically conductive layer and a third top surface of the second gate dielectric region are exposed to a surrounding ambient resulting in a first poly-silicon region and a second poly-silicon region, wherein the first poly-silicon region and the second poly-silicon region are exposed to a surrounding ambient. 
         [0005]    The present invention provides a method for forming a CMOS device having a metal gate NFET and a poly-silicon gate PFET. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIGS. 1A-1H  show cross-section views used to illustrate a fabrication process of a semiconductor structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0007]      FIGS. 1A-1H  show cross-section views used to illustrate a fabrication process of a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process of the semiconductor structure  100  starts with the semiconductor structure  100  of  FIG. 1A . The semiconductor structure  100  comprises a silicon substrate  110 , an STI (shallow trench isolation) region  112  in the silicon substrate  110 , gate dielectric regions  114   a  and  114   b  on top of the silicon substrate  110 , and a high-K dielectric region  118  on the gate dielectric region  114   a,  as shown in  FIG. 1A . The silicon substrate  110  comprises silicon regions  110   a  and  110   b,  wherein an nFET (n-channel field effect transistor) is to be formed on the silicon region  110   a  and a pFET (p-channel field effect transistor) is to be formed on the silicon region  110   b.  The gate dielectric regions  114   a  and  114   b  can be collectively referred to as a gate dielectric layer  114   a + 114   b.    
         [0008]    In one embodiment, the STI region  112  and the gate dielectric regions  114   a  and  114   b  comprise silicon dioxide. The high-K dielectric region  118  can comprise a high-K dielectric material, wherein K is dielectric constant. The high-K material has dielectric constant greater than 3.9 (which is dielectric constant of silicon dioxide). In one embodiment, the dielectric region  118  comprises hafnium oxide (K=25). 
         [0009]    In one embodiment, the structure  100  further comprises an electrically conductive region  120  on the high-K dielectric region  118 , an amorphous silicon region  130  on the electrically conductive region  120 , and a first poly-silicon region  140  on the gate dielectric region  114   b.  The structure  100  also comprises a second poly-silicon layer  150  on the amorphous silicon region  130  and the first poly-silicon region  140 , a hard mask layer  160  on top of the second poly-silicon region  150 , and photoresist regions  170   a  and  170   b  on the hard mask layer  160 . The second poly-silicon layer  150  comprises a doped poly-silicon region  152 . In one embodiment, the doped poly-silicon region  152  comprises n-type dopants. The electrically conductive region  120  can comprise titanium nitride. The hard mask layer  160  can comprise silicon nitride. 
         [0010]    In one embodiment, the entire photoresist region  170   a  overlaps the silicon region  110   a  in a direction defined by an arrow  175  (also called the direction  175 ). The arrow  175  is perpendicular to the top surface  110 ′ of the silicon substrate  110 . It is said that the entire photoresist region  170   a  overlaps the silicon region  110   a  in the direction  175  if, for any point of the photoresist region  170   a,  a straight line going through that point and being parallel to the direction  175  would intersect the silicon region  110   b.  In one embodiment, the entire photoresist region  170   b  overlaps the silicon region  110   b  in the direction  175 . 
         [0011]    In one embodiment, the structure  100  of  FIG. 1A  is formed using the processes described in the U.S. Pat. No. 6,902,969, which is hereby incorporated into this present application by reference. 
         [0012]    Next, after the structure  100  of  FIG. 1A  is formed, in one embodiment, the hard mask layer  160  and then the second poly-silicon layer  150  are etched resulting in the structure  100  of  FIG. 1B . More specifically, the hard mask layer  160  and the second poly-silicon layer  150  can be anisotropically etched in a direction opposite to the direction  175  with CxFy chemistry using the photoresist regions  170   a  and  170   b  as blocking masks. The hard mask layer  160  and the second poly-silicon layer  150  are etched until the doped poly-silicon region  152  is completely etched through. In other words, the top surface  150 ′ of the second poly-silicon  150  after the etching of the hard mask layer  160  and the second poly-silicon layer  150  is at the same level as or a lower level than the bottom surface  152 ′ of the doped poly-silicon region  152  in the direction  175 . It should be noted that, as shown in  FIG. 1B , the top surface  150 ′ of the second poly-silicon  150  is at the same level as the bottom surface  152 ′ of the doped poly-silicon region  152 . After the etching of the hard mask layer  160  and the second poly-silicon layer  150  is performed, the remaining portions of the hard mask layer  160  are hard mask regions  160   a  and  160   b,  as shown in  FIG. 1B . 
         [0013]    Next, with reference to  FIG. 1B , in one embodiment, the photoresist regions  170   a  and  170   b  are removed resulting in the structure  100  of  FIG. 1C . More specifically, the photoresist regions  170   a  and  170   b  can be removed using in-situ oxygen plasma etching process followed by a wet clean process. 
         [0014]    Next, with reference to  FIG. 1C , in one embodiment, the second poly-silicon layer  150 , the amorphous silicon region  130 , and the first poly-silicon region  140  are etched such that the top surfaces  120 ′ and  114   b ′ of the electrically conductive region  120  and the gate dielectric layer  114   b,  respectively, are exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1D . More specifically, the second poly-silicon layer  150 , the amorphous silicon region  130 , and the first poly-silicon region  140  can be anisotropically etched in the direction opposite to the direction  175  using the hard mask regions  160   a  and  160   b  as blocking masks. After the etching of the second poly-silicon layer  150 , the amorphous silicon region  130 , and the first poly-silicon region  140  is performed, the remaining portions of the second poly-silicon layer  150  directly beneath the hard mask regions  160   a  and  160   b  are poly-silicon regions  150   a  and  150   b,  respectively. As a result of the etching the second poly-silicon layer  150 , the amorphous silicon region  130 , and the first poly-silicon region  140 , the entire silicon region  150   a  and the entire amorphous silicon region  130  overlap the hard mask region  160   a,  whereas the entire silicon region  150   a  and the entire first poly-silicon region  140  overlap the hard mask region  160   b.    
         [0015]    Next, with reference to  FIG. 1E , in one embodiment, a photoresist region  180  is formed on top of the structure  100  of  FIG. 1D  such that the hard mask region  160   b,  the poly-silicon regions  150   b  and  140 , and the gate dielectric region  114   b  are covered by the photoresist region  180 , whereas the hard mask region  160   a,  the doped poly-silicon region  152 , the poly-silicon region  150   a,  the amorphous silicon region  130 , and the electrically conductive region  120  are not covered by the photoresist region  180 . In other words, the entire hard mask region  160   b,  the entire poly-silicon regions  150   b  and  140 , and the entire gate dielectric region  114   b  overlap the photoresist region  180  in the direction  175 , whereas the hard mask region  160   a,  the doped poly-silicon region  152 , the poly-silicon region  150   a,  the amorphous silicon region  130 , and the electrically conductive region  120  do not overlap the photoresist region  180  in the direction  175 . A first region is said to not overlap a second region in a reference direction if, for any point of the first region, a straight line going through that point and being parallel to the reference direction would not intersect the second region. 
         [0016]    Next, in one embodiment, the electrically conductive region  120  and the high-K dielectric region  118  are etched until the top surface  114   a ′ of the gate dielectric region  114   a  is exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1F . More specifically, the electrically conductive region  120  and the high-K dielectric region  118  can be anisotropically etched in the direction opposite to the direction  175  using the hard mask region  160   a  as a blocking mask. 
         [0017]    Next, with reference to  FIG. 1F , in one embodiment, the photoresist region  180  is removed resulting in the structure  100  of  FIG. 1G . More specifically, the photoresist region  180  can be removed by ex-situ nitrogen/hydrogen gas mix plasma etching process. 
         [0018]    Next, with reference to  FIG. 1G , in one embodiment, the hard mask regions  160   a  and  160   b  are removed resulting in the structure  100  of  FIG. 1H . More specifically, the hard mask regions  160   a  and  160   b  can be removed by a wet clean process. After that, the structure  100  can undergo a post high K metal gate etch wet clean. 
         [0019]    Next, with reference to  FIG. 1H , in one embodiment, source/drain regions (not shown) of the nFET are formed in the silicon region  110   a.  The source/drain regions of the nFET can be doped with n-type dopants. After that, source/drain regions (not shown) of the pFET are formed in the silicon region  110   b.  The source/drain regions of the pFET can be doped with p-type dopants. It should be noted that the nFET is a metal gate nFET because it has a metal gate electrode region  120  which comprises titanium nitride (a metal), whereas the pFET is a poly gate pFET because it has a poly gate electrode  140 + 150   b  which comprises poly-silicon. It should be noted that the nFET and pFET can be electrically connected to form a CMOS (Complementary Metal Oxide Semiconductor) device. 
         [0020]    In summary, described above is the fabrication process of the structure  100  which has an nFET and a pFET, wherein the nFET is a metal gate nFET and the pFET is a poly gate pFET. 
         [0021]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Classification (CPC): 7