Patent Abstract:
A system including a first graphics controller and an expansion slot for coupling a second graphics controller. The first graphics controller generates first graphic symbols based on data stored in the system memory in synchronism with clock signals received from a clock circuit. Similarly, the second graphics controller generates second graphic symbols based on data stored in the system memory in synchronism with clock signals received from the clock circuit. When the second graphics controller is not coupled to the expansion slot, the processor provides a graphics select signal. A clock steering circuit responds to the graphics select signal by applying the clock signals to the first graphics controller, while blocking the clock signals to the expansion slot. In the absence of the graphics select signal, the clock steering circuit applies the clock signals to the expansion slot for application to the second graphics controller, while blocking the clock signals to the first graphics controller.

Full Description:
FIELD 
     The present invention relates to dynamic clock distribution. 
     BACKGROUND 
     There exists a continuing need for an arrangement effecting selective enabling/disabling of an existing functional block and an expansion functional block within a system (e.g., on a motherboard), while reducing the liklihood of malfunctioning or degrading (e.g., overloading) of a system clock. Considering a graphics controller functional block as an example, some resellers of computer systems desire to provide their customers with a selection of graphics capabilities, and thus desire to provide computer systems capable of being fitted with different graphics controllers. However, manufacturers generally desire to provide a generic graphics controller as standard equipment, while leaving it to the resellers to add a customized one at the time of sale of the system, if desired. In addition, some users of computer systems may at some time after the purchase decide to upgrade or change the graphics controller by inserting one in an expansion slot on the computer. Having two graphics controllers coupled to the computer system clock circuit at the same time might create an undesirable clock circuit load, and might cause edge rate degradation of the clock signals. 
     In the past, a dual in-line package (DIP) switch, a jumper, or other hardware on the motherboard was used to activate the add-on graphics controller, while disabling the built-in one. This is a cumbersome process employing tedious intervention by the user, in contrast to easier “plug-and-play” additions to the computer system. 
     SUMMARY 
     The present invention is an arrangement for dynamic clock distribution with respect to functional blocks. A clock control circuit includes a source of a select signal for selecting between operation of a first functional block and a second functional block. A clock steering circuit receives clock signals from a clock signal source and in response to a first predetermined state of the select signal prevents clock signals from being applied to the first functional block while enabling clock signals to be applied to the second functional block. In response to a second predetermined state of the select signal, the clock steering circuit enables clock signals to be applied to the first functional block while preventing clock signals from being applied to the second functional block. 
    
    
     BRIEF DESCRIPION OF THE DRAWINGS 
     The follow present brief descriptions of the drawings, wherein: 
     FIG. 1 is a block diagram of an example computer system having a clock steering circuit with respect to two graphic controllers, in accordance with an embodiment of the present invention; 
     FIG. 2 is a schematic diagram of an example clock steering circuit suitable for use in the system of FIG. 1; 
     FIGS. 3 a - 3   d  are timing diagrams illustrative of the operation of the clock steering circuit of FIG. 2; 
     FIG. 4 is a chart illustrating an example method of determining whether a second graphics controller is coupled to the system in accordance with an embodiment of the present invention; and 
     FIG. 5 is a flowchart illustrating an example method in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     When appropriate, like reference numerals and characters are used to designate identical, corresponding or similar components in differing drawing figures. 
     FIG. 1 depicts the several components of an example system mounted on a motherboard  20 . These components include a processor  22 , a clock generator  24 , and a first bridge circuit  28  which are intercoupled by a bus  27  having a plurality of lines. This example system further includes a memory  26  which is also coupled to bridge circuit  28  by connection  29 . Bridge circuit  28  services a bus  32  capable of having a plurality of input/output devices disposed therealong and can be coupled to a second bridge circuit  30 . Second bridge circuit  30  is, for example, coupled by bus  31  to various expansion slots for other components, in well known manner. The system further includes input/output (I/O) devices  33  coupled to bus  31  through I/O port  35 . 
     A first (e.g., generic) graphics controller  36  is mounted on motherboard  20  and is coupled to first bridge circuit  28  by a bus  38  for receipt of graphics signals from processor  22 . An expansion slot  40  on motherboard  20  can be used to mount a second graphics controller  42 , which may be an optional or an upgrade controller, or a replacement, in the event of failure of first graphics controller  36 . Expansion slot  40  is also coupled by bus  38  to first bridge circuit  28  for receipt of graphics signals from processor  22 . 
     A clock steering circuit  44  may also be mounted on motherboard  20  and has a clock input port  45  which receives clock signals originating from clock circuit  24 , by way, for example, of first bridge circuit  28 . Clock steering circuit  44  also has a second input port  46  which receives graphic select signals, originating from the processor  22 , by way of second bridge circuit  30  and connection  34 . Clock steering circuit  44  is not limited to such inputs; for example, input port  45  may receive the clock signals directly from another programmable device, rather than from clock generator  24  through first bridge circuit  28 . Also, input port  46  may receive the graphics select signal from first bridge circuit  28 , rather than through the more complex route of bus  32 , second bridge circuit  30 , and bus  34 . 
     Clock steering circuit  44  has a first output port  47  which can provide clock signals on line  49  to first graphics controller  36  and a second output  48  coupled by line  51  to expansion slot  40  which can provide clock signals to second graphics controller  42 . Graphics controllers  36  and  42  in turn may be coupled to display  50  to provide graphical displays. 
     FIG. 2 depicts an example clock steering circuit suitable for use as clock steering circuit  44  in accordance with an embodiment of the present invention, although other suitable gating circuitry, known to those skilled in the art, could be utilized. FIGS. 3 a - 3   d  are timing diagrams illustrative of the operation of the circuit of FIG.  2 . Clock signals, illustrated in FIG. 3 a , are applied to input terminal  45  which is coupled to ground through capacitor  60  and is coupled by resister  62  to the signal input port of switching circuit  54  and the signal input port of switching circuit  56 . A graphics select signal, illustrated in FIG. 3 b , is applied from input terminal  46  through inverter  52  to the control input port of switching circuit  54  and also is applied directly from input terminal  46  to the control input port of switching circuit  56 . The signal output port of switching circuit  54  is coupled through resistor  68  to output terminal  47  which is coupled to first graphics controller  36 . The junction of resistor  68  and output terminal  47  is coupled to ground through the parallel combination of capacitor  72  and resistor  74 . In a similar manner, the signal output port of switching circuit  56  is coupled through resistor  76  to output terminal  48  which is coupled to expansion slot  40 , and the junction of resistor  76  and output terminal  48  is coupled to ground through the parallel combination of capacitor  78  and resistor  80 . Resistors  68 ,  74 ,  76 , and  80  and capacitors  72  and  78  have values selected to provide the desired slope or edge rate to the clock pulse output signals from switching circuits  54  and  56 , respectively, permitting timing of the edge rate to accommodate the characteristics of the particular switching circuits. These components may be omitted if the clock signal edge rate is otherwise controlled or is not of concern. 
     As illustrated in FIGS. 3 a - 3   d , in the absence of a graphics select signal (FIG. 3 b ) on input terminal  46 , switching circuit  54  blocks the clock signals (Pig.  3   a ) from output terminal  47  (FIG. 3 c ), while switching circuit  56  applies the clock signals through resistor  76  to output terminal  48  (FIG. 3 d ). This enables second graphics controller  42  to provide graphics signals to display  50 . When a graphics select signal (FIG. 3 b ) is applied to input terminal  46 , switching circuit  54  applies the clock signals (FIG. 3 a ) through resistor  68  and output terminal  47  (FIG. 3 c ) to first graphics controller  36 , while switching circuit  56  blocks the clock signals from output terminal  48  (FIG. 3 d ) and expansion slot  40 . This enables first graphics controller  36  to provide graphics signals to display  50 . 
     Each switching circuit  54  and  56  might be a field effect transistor (FET) switch, such as an SN74CBT3306 dual FET switch available from Texas Instruments, Inc., for example. If desired, the clock signals from input terminal  45  can be applied from resistor  62  to an additional output terminal  82  for application to other destinations. 
     Processor  22  performs processing functions utilizing data stored in memory  26  and applies results of those processing functions to other components, such as memory  26 , all with timing based on clock signals from clock circuit  24 . For example, with respect to the dynamic clock distribution, a program may be installed within memory  26  which queries the status of the system upon each system initialization to determine whether there is a graphics controller installed within expansion slot  40 . The query can be answered in a number of ways, such as via a keyboard, mouse, or other manual input signal from a user, but in a plug-and-play approach installation of second graphics controller  42  is automatically sensed by processor  22  directly from expansion slot  40 , e.g., by mechanical and/or optical sensing, or from second graphics controller  42 , e.g., by polling. Further, in a plug-and-play approach, processor  22  automatically (e.g., transparently) changes over the graphics select signal, and thus clock redistribution, when appropriate, without user intervention. 
     If there is no graphics controller in expansion slot  40  (e.g., at time T 0  in FIG.  3 ), then processor  22  senses this and causes a graphics select signal to be applied (FIG. 3 b , between times T 0  and T 1 ) through first bridge circuit  28 , bus  32  and second bridge circuit  30  to connection  34  which applies the signal to input port  46  of clock steering circuit  44 . This causes clock steering circuit  44  to apply clock signals (FIG. 3 c , between times T 0  and T 1 ) received from first bridge circuit  28  to first graphics controller  36  via output terminal  47  and connection  49 . Alternatively, if second graphics controller  42  is in expansion slot  40  (e.g., installed at time T 1  in FIG.  3 ), a graphics controller installed signal (not shown), for example from expansion slot  40  on bus  38 , is sensed by processor  22 , and no graphics select signal (e.g., FIG. 3 b , between times T 1  and Tn) is applied to clock steering circuit  44 . Instead, a reset signal (not shown) is applied to first graphics controller  36  on line  52  from second bridge circuit  30 . Accordingly, in response to the absence of the graphics select signal, clock steering circuit  44  applies clock signals (FIG. 3 d , between times T 1  and Tn) via output terminal  48  and connection  51  to expansion slot  40 , from which the signals are applied to second graphics controller  42 . Connection  49  from clock steering circuit  44  to first graphics controller  36  can thus be considered a first graphics controller connection, while connection  51  from clock steering circuit  44  to expansion slot  40  can be considered a second graphics controller connection. 
     FIG. 4 is an example flow chart illustrating this. Once the system is started in block C 0 , block C 1  determines whether a graphics controller is installed in expansion slot  40 . If not, then in block C 2  the graphics select signal is provided. If there is a graphics controller installed in expansion slot  40 , the graphics select signal is not provided, and the flow repeats block C 1  or ends. 
     FIG. 5 illustrates an example method in accordance with an embodiment of the present invention. Once the system is started in block S 0 , block S 1  determines whether the graphics select signal is present. If yes, then in block S 2  first graphics controller  36  is enabled by having clock signals applied to it. If block SI determines that the graphics select signal is not present, then in block S 3  second graphics controller  42  is enabled by having clock signals applied to it. 
     The described embodiments thus permit provision of two graphics controllers without an undesirable clock circuit load. Presence of a second graphics controller in expansion slot  40  results in processor  22  inhibiting the graphics select signal, resulting in that second graphics controller receiving clock signals, while the clock signals are blocked from the first graphics controller, thus providing a plug-and-play capability. 
     Although the present invention has been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art having the benefit of this specification which will fall within the spirit and scope of the principles of the invention. More particularly, reasonable variations and modifications are possible in the component parts and/or their arrangement within the scope of the foregoing disclosure, the drawings and the appended claims, without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses and/or environments will also be apparent to those skilled in the art. As possible modifications, the arrangement of the present invention may control enabling/disabling of the functional blocks, such as graphics controllers, by provision/non-provision of a parameter differing from the clock signal, e.g., application/non-application of power or ground to either part of or the whole of each functional block.

Technology Classification (CPC): 6