Patent Abstract:
A multiple die package is formed, which allows multiple die to be interconnected using internal leads or traces from a lead frame. A plurality of slots in the paddle area of the lead frame are created which define the internal signal traces. Then the outer portions of the die paddle area of the lead frame are removed or trimmed to isolate the internal traces from each other and form a plurality of individual internal leads. Multiple die, either stacked, in a planar array, or a combination of the two, are connected to selected internal leads, such as by wire bonding, to form the desired die-to-die interconnections for routing signals between die without interfering with normal wire bond fan-out. A tape can be adhered to the interior portion of the die paddle area prior to trimming to hold the internal traces in place and leave the ends of the traces exposed for wire bonding to the die. The internal traces also allow connections to be made within a single die by wire bonding selected bond pads from the die via one or more of the internal traces.

Full Description:
BACKGROUND 
     1. Field of Invention 
     The present invention relates to integrated circuit packaging, and more particularly to multiple die packaging. 
     2. Related Art 
     Semiconductor die or chip packages are used to protect the semiconductor device (e.g., an integrated circuit chip) and allow the chip to be electrically connected to external circuitry. The chip typically has a surface containing active circuit elements that can be accessed via conductors on the chip, such as bonding pads. The chip can be packaged using numerous packaging techniques, as is known in the art. The package can then be placed into a printed circuit board (PCB) to access the circuitry on the IC chip. 
     As the complexity of applications increases, a greater number of chips are needed on the PCB to implement the necessary functions. Conventional methods to increase the number of chips without increasing the package size is to stack multiple chips on the package, such as disclosed in U.S. Pat. No. 5,012,323 to Farnworth, U.S. Pat. No. 5,291,061 to Ball, U.S. Pat. No. 5,347,429 to Kohno et al., U.S. Pat. No. 5,780,925 to Cipolla et al., U.S. Pat. No. 5,793,108 to Nakanishi et al., and U.S. Pat. No. 5,898,220 to Ball. Although these disclose two or more stacked die each electrically connected to leads on the package or lead frame, none disclose the ability to connect the die together without connection to the external package leads, which limits the interconnection capability of signals between die, such as the wire bond fan-out of the package. 
     In order to increase signal routing capability, previous solutions included using higher cost laminate-based packages. Thus, it is desirable to have a stacked multiple-die package with high signal routing capability between die without the costs associated with laminate-based packages. 
     SUMMARY 
     In the present invention, a method and structure are provided that allow multiple stacked die to be connected through internal conductive traces in the lead frame or package for high signal routing capability between die. 
     According to the present invention, electrically isolated signal traces within the paddle area are created for die-to-die signal interconnection and held together using lead lock tape. These signal traces are completely internal to the package and not connected to the external leads. Die are then stacked, either over each other or on both sides of the paddle area, and interconnected via the internal traces. A bond wire is connected from a bond pad of a first die to an internal trace. Another bond wire is connected from a bond pad of a second die to the internal trace to provide a desired interconnection between the two die. 
     This invention takes advantage of the metal in the lead frame paddle area to create internal “inner” lead traces (ILTs) for signal routing for die-to-die interconnection in stacked die lead frame packages. The “inner” leads complement the existing “outer” leads normally associated with lead frame design, which are used to provide electrical connection between the die and peripheral circuitry. 
     In one set of embodiments, a first die is mounted over the ILTs, such as with die attach paste or adhesive film, and a second die is mounted over the first die, such as with die attach paste or film adhesive. The first die and ILT area are designed such that there must be sufficient separation between the ILT area and the first die to allow wire connection to the ILTs. There must also be sufficient separation between the first and second die to allow wire connection to the bond pads from the first die. 
     In another set of embodiments, a first die is mounted over one side of the ILTs, and a second die is mounted on the other side of the ILTs, either with the active side (having the bond pads) or the inactive “back” side facing the ILT paddle area. If the second die is mounted with the active side facing the ILT paddle area, there must be sufficient separation between the top of the die the bottom of the ILT paddle area to allow proper wire connection to bond pads on the second die. If the first die is at least the same size as the ILT paddle area, the separation between the first die and the ILTs must be adequate to allow bond wire connection to the ILTs. This set of embodiments also allows a second die with center bond pads to be connected to the first die. The bond pads of the second die, mounted with the active side facing the ILTs, are connected to center portions of the ILTs, while the bond pads of the first die are connected to outer portions of the ILTs to facilitate the desired signal routing. 
     In other embodiments, the present invention provides additional benefits, such as allowing a larger lower die to be connected to external fingers of a lead frame while allowing the smaller upper die to be connected to ILTs without bond wires crossing each other. The ILT paddle area leads can be designed such that the ILT fingers extend beyond the tips of the external fingers in a interleaved fashion, i.e., the ends of the external fingers are closer to the die than the ends of the ILTs. With this configuration, a larger bottom die mounted on the ILT paddle area can be wire bonded to the external fingers, while a smaller top die mounted over the larger die can be wire bonded to the ILTs without crossing the bond wires of the top and bottom die. 
     Using conventional wire bonding techniques, the equivalent of a “via” can also be formed. Wire bonds are used to provide the out-of-plane electrical connections between crossing ILT segments of a specific die-to-die signal path. This allows routing of crossed die-to-die signal paths, similar to the way “vias” are used in multi-layer laminate substrates. These wire bond “vias” also overcome the inherent limitation of one-dimensional, or single metal layer, routing limitations of a lead frame. 
     The present invention will be more fully understood when taken in light of the following detailed description taken together with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a top view of a lead frame package for use in one embodiment of the present invention; 
     FIG. 2 shows a lead frame package formed from the package of FIG. 1 according to one embodiment of the present invention; 
     FIGS. 3A and 3B are respective top and side views of a lead frame package with stacked die according to one embodiment; 
     FIGS. 4 and 5 are side views of additional embodiments of the package shown in FIGS. 3A and 3B, in which the first and second die are on the same side of the internal traces; 
     FIGS. 6,  7 , and  8  are side views of different embodiments of the present invention, in which the first and second die are mounted on opposite sides of the internal traces; 
     FIGS. 9A,  9 B, and  9 C show another embodiment of the present invention, in which wire bond vias are used to route crossed signal path ILT segments; and 
     FIGS. 10A,  10 B, and  10 C show an embodiment of the present invention for wire bonding die to internal and external traces traces using interleaved bond fingers. 
    
    
     Use of the same or similar reference numbers in different figures indicates same or like elements. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides a method and structure to allow inexpensive signal routing between stacked die in a lead frame by forming inexpensive interconnections between die using inner lead traces (ILTs) formed etching or stamping signal trace defining slots, then trimming the edge of the ILT paddle area to create electrically isolated traces. 
     FIG. 1 is a top view of an ILT lead frame package  10 , according to one embodiment, having a plurality of external lead fingers or outer lead traces (OLTs)  12  and an internal paddle area  14  containing slots  16  and traces  17 , where traces  17  are electrically connected. Lead frame package  10  is shown having slots  16  ending at three sides of the package. However, the lead frame package can be any suitable type, such as dual-sided or quad packages. 
     According to the present invention, the outer portions of paddle area  14  are removed or trimmed to create inner lead traces (ILTs) for die interconnection. In FIG. 1, dotted line  18  shows, for example, portions of paddle area  14  to be removed, such by trimming or cutting. Prior to removing the outer portions, a tape, such as a standard lead locking tape, is placed over an interior portion on either side of paddle area  14 , such as shown by dotted line  19 . The tape may also serve as a permanent plating mask for plating the tips of the ILTs. 
     FIG. 2 shows lead frame package  10  after removal of the outer portions of paddle area  14 . Traces  17  are no longer electrically connected to other traces. Instead, each resulting inner lead trace  20  is electrically isolated from other ILTs  20 . As shown in FIG. 2, ILTs  20  can carry signals to and from adjacent sides or to and from opposite sides of paddle area  14 . It should be noted that the package shown in FIG. 2 can be modified so that ILTs  20  can carry signals to and from the perimeter and the interior of paddle area  14  for die with center bond pads. To achieve this, an interior portion of paddle area  14  is removed, such that ILTs  20  have ends at the perimeter and interior of paddle area  14 . This is in contrast to package  10  of FIG. 2, in which ILTs  20  have ends only at the perimeter of the paddle area. Die can then be attached and stacked onto package  10 . Subsequent wire bonding electrically couples the die to OLTs  12  for connection to other circuitry, such as through a PCB. Wire bonding also electrically couples the stacked die to provide the desired signal routing or interconnections between the die. 
     FIGS. 3A and 3B are respective top and side views of lead frame package  10  with a first die  30  and a second die  31 . Note that these and other figures show only two die. However, as those skilled in the art will appreciate, more than two die can be used with the present invention. First die  30  is secured to an inner lead trace (ILT) tape  32 , such as a standard lead locking tape discussed above, by a non-conductive film or a less expensive die attach paste  33 . Note that tape  32  may also be placed on the bottom of ILT  20  with first die  30  secured directly to ILT  20  using non-conductive film or paste  33 . In this embodiment, first die  30  is smaller than the ILT area so that the ends of ILTs  20  are exposed for wire bonding. Second die  31  is mounted to first die  30 , such as with die attach paste  33 . In this embodiment, second die  31  is smaller than first die  30  to allow wire bonding to bond pads  34  on first die  30 . Thin conductive bond wires  35 , such as gold, can be connected between bond pads  36  of second die  31  and selected ones of ILTs  20 . Bond wires  35  can also be connected between bond pads  34  of first die  30  and the same selected ones of ILTs  20  to provide the desired die-to-die interconnection. In addition, bond wires  35  can be connected between bond pads  36  of second die  31  and OLTs  12 , ILTs  20 , or bond pads  34  of first die  30 , between bond pads  34  of first die  30  and OLTs  12  or ILTs  20 , and between OLTs  12  and ILTs  20 . Using various combinations of these connections paths allows desired die-to-OLT connections and die-to-die interconnections to be formed, after which, the package can be encased, such as in a mold compound  37 . 
     FIGS. 4 and 5 show some alternative embodiments to the package shown in FIGS. 3A and 3B, in which both die are stacked on one side of the ILTs. In FIG. 4, second die  31  is approximately the same size as first die  30 , although second die  31  can also be larger. In this embodiment, after first die  30  is mounted over ILTs  20 , such as by ILT tape  32  and die attach paste  33 , bond wires are attached to bond pads  34  of first die  30 . Second die  31  is then attached to first die  30  with a spacer  40 , such as a thick non-conductive adhesive or die attach tape or a solid spacer attached to the two die by adhesive. If a solid spacer is used, the solid spacer can be made of a conductive material, such as a metal, or a non-conductive material, such as a polymer or ceramic. Further, the adhesive between the solid spacer and the top or active side of the die is non-conductive, while the adhesive between the solid spacer and the bottom or inactive side of the die can be conductive or non-conductive, depending on the electrical function, such as described in commonly-owned U.S. patent application Ser. No. 09/828,396, entitled “Making Semiconductor Devices Having Stacked Dies With Biased Back Surfaces”, now U.S. Pat. No. 6,437,449, issued Aug. 20, 2002, which is incorporated by reference in its entirety. Spacer  40  should provide enough separation between first die  30  and second die  31  to allow clearance of bond wires  35  from bond pads  34 . 
     In FIG. 5, an exposed thermal pad  50  is attached underneath ILTs  20  by ILT tape  32  or adhesive. In this embodiment, ILT tape  32  may or may not also be attached to the other side of ILTs  20  (FIG. 5 shows no ILT tape  32 ). Thermal pad  50  is exposed to the exterior of the package to provide a solderable thermal path. In other embodiments, a heat slug or other similar element can be used instead of thermal pad  50 . 
     In other embodiments, shown in FIGS. 6,  7 , and  8 , first die  30  and second die  31  are on opposite sides of ILTs  20 , instead of on the same side, as discussed above. In FIG. 6, the side of second die  31  containing active circuitry and bond pads is attached to the side of ILTs  20  opposite first die  30 . Non-conductive die attach paste  33  or adhesive film secures second die  31  to ILTs  20 . Also note that ILT tape  32  may be placed on top, bottom, or both sides of ILTs  20 . As shown in FIG. 6, second die  31  is larger than the ILT area, which allows wire bonding to bond pads  36  of second die  31 . First die  30  can also be the same size as or larger than the ILT area. In this case, there must be sufficient separation between the ILT area and first die  30  to allow wire bonding to the ILTs. After bond wires  35  are connected to bond pads  36  of second die  31 , a spacer such as thick non-conductive paste or a solid spacer with adhesive, as discussed above, provides the desired separation and attachment between first die  30  and ILTs  20 . Other variations of the package shown in FIG. 6 include features discussed above, such as first die  30  being larger than the ILT area and having an exposed thermal pad or heat slug attached to second die  31 . 
     In FIG. 7, the inactive side of second die  31  is attached to ILTs  20 . Adhesive  33  attaching second die  31  to ILTs  20  can be conductive or non-conductive. When electrical backside contact to first die  30  or second die  31  is desired, ILT tape  32  between the corresponding die and ILT  20  has openings to the appropriate electrical conductors so that electrical contact to the die backside may be made through the conductive adhesive. This may be done with one or both die. The bond fingers of ILTs  20  are plated on both sides to allow wire bonding from both die. Again, other variations are possible, such as first die  30  being the same size as or larger than the ILT area and/or the package having an exposed thermal pad or heat slug. 
     In FIG. 8, second die  31  has center bond pads  80  in addition to outer bond pads  36 . The paddle area is formed, as discussed above, with ILTs  20  having terminals at both the perimeter and interior of the paddle area. Second die  31  is attached to ILTs  20 , such as described above. Bond wires  35  are attached to outer bond pads  36  and center bond pads  80  as required. First die  30  is then attached to ILTs  20 , again as discussed above, and wire bonded. 
     FIGS. 9A,  9 B, and  9 C show another embodiment of the present invention, which can be applied to any of the previous embodiments. This shows how crossed signal paths within the ILT can be used to route signals between die using wire bonds or allow signals to be routed within the same die, both of which are functionally similar to vias. FIG. 9A shows a package where these vias can be formed both at the interior of the paddle area at region  90  and at the exterior of the paddle area at region  91 . FIG. 9B shows a top view of ILTs  20  at interior region  90 . Dotted line  92  shows an opening in the ILT tape  32  to expose portions of ILTs  20  for connection. As seen, selected segments of ILTs  20  can be electrically connected by wires  93 , providing electrically isolated but crossed signal paths between die, or a die may be wire bonded to one or more of the ILTs  20  to provide the desired connection between different portions of the die. FIG. 9C shows a top view of ILTs  20  at exterior region  91 . The right of dotted line  94  are exposed portions of ILTs  20  not covered with the ILT tape  32 . Similar to FIG. 9B, selected segments of ILTs  20  are wire bonded together, thereby providing a desired interconnection between die or within a die. 
     FIGS. 10A,  10 B, and  10 C show an embodiment of the present invention that allows a smaller upper die to be wire bonded to internal lead traces and a larger lower die to be wire bonded to outer or external leads without crossing upper and lower bond wires. FIG. 10A shows a portion of a lead frame package having external leads  100  and internal leads  102 . Internal leads  102  are exposed above dotted line  104 , underneath which indicates the ILT tape  32 . As seen from FIG. 10A, external leads  100  and internal leads  102  are electrically connected at portions  106  prior to trimming to allow a conventional lead frame manufacturing process. FIG. 10B shows the portion of the lead frame of FIG. 10A after trimming away portions  106 , resulting in electrical isolation of interleaved external leads  100  and internal leads  102 . The ends of internal leads  102  extend beyond the ends of external leads  100 , which are now closer to the die. This allows a smaller upper die  110  to be wire bonded to the internal leads and a larger lower die  120  to be wire bonded to the external leads without crossing bond wires  125 , as shown in FIG.  10 C. 
     The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. For example, the above specification describes multiple die counted on a lead frame with lead fingers for connection to PCBs. However, other types of lead frames are also suitable for use with the present invention, such as micro lead frames, which have leads in the form of lands on the bottom surface of the package. Further, stacked-die packages are shown, although other types of arrangements are also suitable, such as multi-die single layer configurations or a combination of both. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.

Technology Classification (CPC): 7