Patent Abstract:
Semiconductor devices according to the present invention include a duty cycle correction circuit having a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Full Description:
RELATED APPLICATION  
         [0001]    This application claims the benefit of Korean Application No. 2000-46938, filed Aug. 14, 2000, the disclosure of which is hereby incorporated herein by reference.  
         FIELD OF THE INVENTION  
         [0002]    The present invention relates to semiconductor devices, and more particularly, to duty cycle correction circuits.  
         BACKGROUND OF THE INVENTION  
         [0003]    Recently, the speed of semiconductor memory devices, for example, dynamic random access memories (DRAMs), has increased to improve the performance of existing systems. However, increasing demand for improved systems may require DRAMs that can process even more data at even higher speeds. Accordingly, synchronous dynamic random access memories (SDRAMs) that operate in synchronization with system clocks have been developed for a high-speed operation, thus significantly increasing data transmission speeds.  
           [0004]    There are limitations on the amount of data that may be input to and/or output from a memory device per clock cycle of a system clock. To address these limitations, dual data rate (DDR) SDRAMs have been recently developed in order to further increase the transmission speed of data. DDR SDRAMS input and/or output data in synchronization with both the rising edge and the falling edge of a clock.  
           [0005]    Reliable data transmission is possible when the duty cycle of a clock signal is equivalent at 50%, which is ideal, in a DDR SDRAM or a direct rambus dynamic random access memory (RDRAM). Thus, when a signal having a duty cycle that is not equivalent, i.e. greater than or less than 50%, is provided as an input, the signal typically does not perform very well as an input signal. Duty cycle correction circuits have been developed to address this problem.  
           [0006]    A block diagram of a conventional duty cycle correction circuit is illustrated in FIG. 1. A duty cycle correction circuit includes a duty cycle corrector  10  and a detection circuit  13 . The duty cycle corrector  10  generates a pair of complementary input signals IN and INB, from which distortion is typically removed, in response to first and second complementary clock signals CLK and CLKB, having distortion resulting from nonequivalent duty cycles. The detection circuit  13  feeds back first and second detection signals DETECT and DETECTB obtained by detecting distortion in the duty cycles of the complementary pair of input signals IN and INB of the correction circuit  10  in response to the pair of complementary input signals IN and INB.  
           [0007]    Now referring to FIG. 2, a circuit diagram of a conventional detection circuit  13  of FIG. 1 will be discussed. When mismatching exists among diode-connected loads M 1  and M 4 , cross-coupled loads M 2  and M 3 , source coupled pairs M 5  and M 6 , and/or the respective transistors in the detection circuit  13 , increased distortion may occur in the duty cycles of the pair of complementary input signals IN and INB due to mismatching of the respective transistors, even though less distortion is present in the duty cycles of the complementary pair of clock signals CLK and CLKB.  
         SUMMARY OF THE INVENTION  
         [0008]    Semiconductor devices according to embodiments of the present invention include a duty cycle correction circuit having a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.  
           [0009]    In some embodiments of the present invention, the duty cycle corrector further generates a second input signal having a fourth duty cycle with a higher degree of equivalence than the third duty cycle in response to a second detection signal and a second control signal having a third duty cycle. The detection circuit, in other embodiments of the present invention, further generates the second detection signal in response to the second input signal.  
           [0010]    In further embodiments of the present invention, the duty cycle correction circuit includes a load matching circuit that is electrically coupled to the first and second current sources and matches a load of the bias circuit in response to the second input signal.  
           [0011]    In still further embodiments of the present invention, the first control signal is a true clock signal and the second control signal is a complementary clock signal. Furthermore, the first and second input signals are complementary signals and the first and second detection signals are complementary signals.  
           [0012]    In some embodiments of the present invention, the duty cycle correction circuit further includes a first output driver circuit that pulls the first detection signal up or down in response to the first input signal and a second output driver circuit that pulls a second detection signal up or down in response to a second input signal. The current generated by the current source is supplied to the first output driver circuit, the second output driver circuit and the bias circuit responsive to a bias voltage. The bias voltage may be a voltage at a first node during a period and is calculated according to the equation V NODB +V NODC −VDD−GND. V NODB  is the voltage at a second node, V NODC  is the voltage at a third node, VDD is a source voltage, and GND is a ground voltage. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 is a block diagram illustrating a conventional duty cycle correction circuit;  
         [0014]    [0014]FIG. 2 is a circuit diagram illustrating a conventional detection circuit of FIG. 1; and  
         [0015]    [0015]FIG. 3 is a circuit diagram illustrating a detection circuit according to embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Signal lines and signal thereon may be referred to by the same reference names. Like numbers refer to like elements throughout.  
         [0017]    Now referring to FIG. 3, a circuit diagram of a detection circuit  13 A according to embodiments of the present invention will be discussed. It will be understood that the detection circuit  13 A receives a pair of complementary input signals IN and INB that are generated by a duty cycle corrector, for example, duty cycle corrector  10 , in response to a pair of complementary clock signals CLK and CLKB. It will be further understood that although the inputs of the duty cycle corrector are described herein as a complementary pair of clock signals, the present invention is not limited to this configuration. For example, the inputs to the duty cycle corrector may be a complementary pair of control signals CNTL and CNTLB. The detection circuit  13 A includes a first output driver  31 , a bias circuit  33 , a current source  35 , a second output driver  39 , and a load matching circuit  37 .  
         [0018]    The first output driver  31  pulls a first detection signal DETECT up or down in response to a complementary input signal INB. The first output driver  31  may include a PMOS transistor M 3  and an NMOS transistor M 1  that are electrically connected as illustrated in FIG. 3. In particular, the drains of transistors M 3  and M 1  are connected together and the complementary input signal INB is applied to the gates of transistors M 3  and M 1 . Furthermore, the first detection signal DETECT is connected to the drain of the PMOS transistor M 3  and a first capacitor C 1  may be electrically connected between the first detection signal line DETECT and ground GND.  
         [0019]    The second output driver  39  pulls a second detection signal DETECTB up or down in response to an input signal IN. The second output driver  39  may include a PMOS transistor M 4  and an NMOS transistor M 2  that are electrically connected as illustrated in FIG. 3. In particular, the drains of transistors M 4  and M 2  are connected together and the input signal IN is applied to the gates of transistors M 4  and M 2 . Furthermore, the second detection signal DETECTB is electrically connected to the drain of the PMOS transistor M 4  and a second capacitor C 2  may be electrically connected between the second detection signal line DETECTB and ground GND.  
         [0020]    The current source  35  steers current to the first output driver  31 , the second output driver  39 , and the bias circuit  33 , in response to a bias voltage. The bias voltage is the voltage of a node NODA. The current source  35  may include first and second current source transistors, PMOS transistor M 11  and NMOS transistor M 9 , respectively. First and second current source transistors M 11  and M 9  are electrically connected as illustrated in FIG. 3.  
         [0021]    The detection circuit  13 A according to embodiments of the present invention has a structure, in which the source coupled pair of the NMOS transistors M 1  and M 2  and the source coupled pair of the PMOS transistors M 3  and M 4  are stacked. The current steering capability of the source coupled pairs is used in the structure to steer current to one side of the detection circuit  13 A. Thus, the degree of deterioration of the characteristics of a transistor in the detection circuit  13 A due to mismatching of the processes of the transistors M 1  and M 2  and/or M 3  and M 4  used for the source coupled pairs may be reduced.  
         [0022]    When the bias of the first and second current source transistors M 9  and M 11 , which operate as the current source  35 , is provided from outside of the duty cycle detection circuit the level of the first or second detection signal DETECT or DETECTB, which are a complementary pair of detection signals, is saturated to the source voltage VDD or the ground voltage GND. This is called the common mode problem. Accordingly, embodiments of the present invention include a self-bias circuit located within the detection circuit  13 A in order to reduce the distortion introduced by the common mode problem.  
         [0023]    A self-bias circuit  33  according to embodiments of the present invention includes a PMOS transistor M 7  and an NMOS transistor M 5  that are electrically connected as illustrated in FIG. 3. In particular, the drains of transistor the PMOS transistor M 7  and NMOS transistor M 5  are electrically connected together and the complementary input signal INB is applied to the gates of transistor the PMOS transistor M 7  and the NMOS transistor M 5 . The NMOS transistor M 5  and the PMOS transistor M 7 , which operate as the self-bias circuit  33 , dynamically determine the bias of the NMOS transistor M 9  and the PMOS transistor M 11  of the current source  35  according to the complementary input signal INB. Since the bias circuit  33  does not need to operate at high speed, the ratio of the width to the length (W/L) may be small.  
         [0024]    A load matching circuit  37  is provided to compensate for the mismatch of load caused by adding the self-bias circuit  33  to the detection circuit  13 A. The load matching circuit  37  includes a PMOS transistor M 8 , an NMOS transistor M 6 , a PMOS transistor M 12  and an NMOS transistor M 10  that are electrically connected as illustrated in FIG. 3. The characteristics of the NMOS transistor M 6  may be similar to the characteristics of the NMOS transistor M 5  of the self-bias circuit  33 . Similarly, the characteristics of the PMOS transistor M 8  may be similar to the characteristics of the PMOS transistor M 7  of the self-bias circuit  33 . Furthermore, the characteristics of the NMOS transistor M 10  may be similar to the characteristics of the NMOS transistor M 9  and the characteristics the PMOS transistor M 12  may be similar to the characteristics of the PMOS transistor M 11  of the current source  35 .  
         [0025]    The operation of the detection circuit  13 A according to embodiments of the present invention will now be described. Since the input signal IN and the complementary input signal INB are a pair of complementary input signals, operations will only be discussed with respect to the complementary input signal INB.  
         [0026]    When the complementary input signal INB is at the supply voltage VDD, transistors M 1  and M 5  are turned on and transistors M 3  and M 7  are turned off. This causes transistor M 5  to sink current from the first node NODA in an amount that is proportional to the difference between the source voltage VDD and the voltage V NODC  of the third node NODC, i e. VDD-V NODC . On the other hand, when the complementary input signal INB is at the ground voltage GND, transistors M 1  and M 5  are turned off and transistors M 3  and M 7  are turned on. This causes transistor M 7  to supply current to the first node NODA in an amount that is proportionate to the difference between the ground GND and the voltage V NODB  of the second node NODB, i.e V NODB -GND.  
         [0027]    Accordingly, net current, which is proportional to the equation: 
           T   INB-H ×( V   NODC.   −VDD )+ T   INB-L ×( V   NODB.   −GND )  (1) 
         [0028]    where T INB-H  equals a period that the complementary input signal INB is at a logic high level and where T INB-L  equals a period that the complementary input signal INB is at a logic low level, is supplied to the first node NODA every period. When the duty cycle correction circuit  10  is in a steady state, the duty cycle is corrected, i.e. the duty cycle is equivalent. Therefore, the period that the complementary input signal is at the logic high level is equal to the period that the complementary input signal is at the logic low level. Accordingly, a net current, which is proportionate to V NODB +V NODC −VDD−GND, is supplied to the first node NODA every period. The amount of the net current is positive when the values of V NODB  and V NODC  are high. Accordingly, when the values of V NODB  and V NODC  are high, the voltage of the first node NODA increases. Similarly, the amount of the net current is negative when the values of V NODB  and V NODC  are low, thus reducing the voltage of the first node NODA.  
         [0029]    If the current through current source transistor M 11  is larger than the current through current source transistor M 9 , the voltages V NODB  and V NODC  of nodes NODB and NODC, respectively, increase. Accordingly, the current through current source transistor M 11  is reduced and the current through current source transistor M 9  increases. However, when the current through current source transistor M 11  is smaller than the current through current source transistor M 9 , the voltages V NODB  and V NODC  of nodes NODB and NODC, respectively, are reduced. Accordingly, the current through current source transistor M 11  increases and the current through current source transistor M 9  is reduced. As a result, the detection circuit  13 A operates such that the amount of the current through transistor M 11  is typically the same as the amount of the current through transistor M 9 , thus reducing distortion caused by mismatched transistors and providing an equivalent duty cycle.  
         [0030]    As described above, a duty cycle correction circuit according to embodiments of the present invention may reduce the deterioration of the performance of the detection circuit caused by mismatched transistors and makes it is possible to correctly detect the duty cycle of the complementary input signals. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Technology Classification (CPC): 7