Patent Abstract:
A cable driver is disclosed which provides a substantially linear output signal corresponding to an input signal received by the cable driver on a transmission line. The cable driver includes a number of switches coupled by delay elements with cause the switches to operate in a sequential order in response to an input signal. Each of the switches couples an associated current source to an output port, producing a substantially linear output signal on a transmission line connected to the output port. The substantially linearity of the output signal increases the rate at which data may be transmitted over the transmission line, while permitting the rise and fall time of a specified portion of the output signal to be controlled to ensure that electro-magnetic interference is not produced.

Full Description:
FIELD OF THE INVENTION 
     This invention relates to the field of data communications. More particularly, the invention relates to cable drivers, line drivers, wave shaping of digital pulses and rise and fall control circuits. 
     BACKGROUND OF THE INVENTION 
     The transmission of digital data along a transmission line may be accomplished using a cable driver. The cable driver receives the signal to be transmitted and generates a corresponding signal on the transmission line. One objective in the design of cable drivers is to maximize the rate at which data may be transmitted (the “data rate”) on the transmission line. Among other limitations, the maximum data rate which may be transmitted will be limited by two considerations: 
     i. The cable driver should not generate excessive electromagnetic radiation, which may affect the operation of other devices near the cable driver. To avoid electromagnetic radiation, the 20% to 80% rise and fall time of the low to high and high to low transitions of the output signal of the cable driver must not be less than a specified minimum rise/fall time. In the case of some cable drivers used in the motion picture and television industries, the Society of Motion Picture and Television Engineering (SMPTE) has set out a minimum rise/fall time of 400 pico-seconds (See SMPTE Standard 259M: 10-Bit 4:2:2 Component and f SC  Composite Digital Signal Serial Digital Interface). 
     ii. The cable driver should minimize any jitter in its output signal by ensuring that the output signal is within a specified tolerance of its steady state level prior to the start of the next transition of the output signal. 
     Prior art cable drivers control the rise and fall times of the output signal with a resistor-capacitor circuit. Such circuits exhibit exponential low to high and high to low output transitions with the result that the output signal takes a relatively long time to settle within the specified tolerance to minimize jitter, while still having a sufficiently long 20% to 80% rise and fall time. Consequently, the data rate which can be transmitted by prior art cable drivers is limited. 
     BRIEF SUMMARY OF THE PRESENT INVENTION 
     The maximum data rate which can be transmitted may be increased by designing the cable driver to have linear low to high and high to low output transitions. 
     Accordingly, it is an objective of the present invention to provide an improved cable driver which has substantially linear low to high and high to low output transitions. 
     The primary feature of the improved cable driver is the ability to transmit data at higher data rates without increased jitter or electromagnetic radiation. In addition, the improved cable driver reduces the problems of ringing and overshoot in the output signal. 
     In one aspect, the improved cable driver comprises (a) an input port for receiving an input signal, comprising first and second input terminals; (b) an output port for transmitting an output signal on a transmission line, comprising first and second output terminals; (c) a first resistance and a second resistance for defining an output signal at said output port, said first resistance being coupled between a voltage source and said first output terminal and said second resistance being coupled between said voltage source and said second output terminal; (d) a plurality of switching stages, wherein each of said switching stages comprises a switch and a current source associated with said switch for producing a current, said current source being coupled to its associated switch and each of said switches being coupled to said output port; (e) a plurality of delay stages for providing a delay time, (f) one of said switching stages being coupled to said input port and the remaining switching stages being coupled in series, with a delay stage between at least some of successive pairs of said switching stages so that the rise and fall times of a selected portion of said output signal exceeds a selected duration. 
     In a second aspect, the improved cable driver comprises (a) an input port for receiving an input signal, comprising first and second input terminals; (b) an output port for transmitting an output signal on a transmission line, comprising first and second output terminals; (c) a first resistor and a second resistor for defining an output signal at said output terminal, said first resistor being coupled between a first voltage source and said first output terminal, and said second resistor being coupled between the first voltage source and said second output terminal, wherein the resistances of said first resistor and said second resistor are equal to the impedance of the transmission line; (d) a plurality of switching stages, wherein each of said switching stages comprises a switch and a current source associated with said switch for producing a current, said current source being coupled between its associated switch and a second voltage source, and each of said switches being coupled to said input port and being responsive to said input signal for coupling its associated current source to said first output terminal or said second output terminal and being capable of switching between said first output terminal and second output terminal with a specified switching time and wherein the switching time of each of said switches is equal; (e) a plurality of delay stages, such that the number of delay stages is one less than the number of switching stages, for providing a delay time, wherein each of said delay stages is coupled between a pair of said switches of said switching stages, for delaying the response of said switches to said input signal such that said switches operate in a sequential order and wherein the delay time of each of said delay stages is equal, and the delay time of said delay stages and the switching time of said switches are selected such that the output signal is substantially linear. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art cable driver. 
     FIGS. 2A &amp; 2B show the input and output signals of the prior art cable driver. 
     FIGS. 3A &amp; 3B show the jitter introduced into the output signal when the prior art cable driver receives a short input pulse. 
     FIG. 4 shows a low to high transition of the output signal of the prior art cable driver. 
     FIG. 5 shows the improved cable driver in block diagram form. 
     FIGS. 6A &amp; 6B and  7 A &amp;  7 B show the transition of switches which comprise the improved cable driver the output signal of the improved cable driver. 
     FIG. 8 shows the switching stage and delay stage of the improved cable driver. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Reference is first made to FIG. 1, which shows a prior art cable driver  20  for transmitting a digital signal over a transmission line. The prior art cable driver  20  comprises an input port  22 , a switch  24 , a current source  26 , resistors  28  and  30 , capacitors  32  and  34 , output stages  36  and  38  and an output port  44 . 
     Capacitor  32  and resistor  28  are connected in parallel between V CC  and node  42 . Capacitor  34  and resistor  30  are connected in parallel between V CC  and node  40 . Current source  26  is coupled between switch  24  and ground. Switch  24  is responsive to an input received at input port  22  and may couple current source  26  to node  42  through node H or to node  40  through node L. Output port  44  comprises output terminals  46  and  48 . 
     Output stage  36  comprises transistor Q 1 , and resistors  50  and  52 . Transistor Q 1  is connected as an emitter follower stage. The base of transistor Q 1  is connected to node  42 . The emitter of transistor Q 1  is coupled to ground through resistor  52  and to output terminal  46  through resistor  50 . The collector of transistor Q 1  is coupled to V CC . Output stage  38  is similarly comprised of a transistor Q 2  and two resistors  54  and  56 . The base of transistor Q 2  is connected to node  40 . The emitter of transistor Q 2  is coupled to ground through resistor  56  and to output terminal  48  through resistor  54 . The collector of transistor Q 2  is connected to V CC . 
     In use, the prior art cable driver  20  will be configured to produce a differential output signal V out  at output terminals  46  and  48 . The differential output signal is defined as the difference between the voltage at output terminal  48  (V 48 ) and the voltage at output terminal  46  (V 46 ): 
     
       
           V   out   =V   48   −V   46 . 
       
     
     The differential output signal V out  will be positive when V 48  is higher than V 46  and this condition will be referred to as a high output signal. Conversely, the differential output signal V out  will be negative when V 48  is lower than V 46  and this condition will be referred to as a low output signal. Although the description here is given with respect to a differential output signal, one skilled in the art will recognize that the individual components of the output signal V out  at terminals  46  and  48  may be used independently, for example, to drive a single ended cable. 
     The prior art cable driver  20  operates as follows. A differential input signal, V in , is received at input port  22 , which comprises input terminals  58  and  60 , and is directed to switch  24 . The differential input signal consists of two voltage signals, one of which is received at terminal  58  and the other of which is received at terminal  60 . V in  is defined as the voltage at terminal  60  (V 60 ) minus the voltage at terminal  58  (V 58 ): 
     
       
           V   in   =V   60   −V   58 . 
       
     
     V in  will be positive when V 60  is higher than V 58  (defined as V in =V IH ). This condition will be referred to as a high input signal. Conversely V in  will be negative when V 60  is lower than V 58  (defined as V in =V IL ) and this condition will be referred to as a low input signal. 
     Switch  24  is responsive to the differential input signal V in  and switches between nodes L and H depending on whether differential input signal V in  is low or high, respectively. When differential input signal V in  is high, switch  24  will connect current source  26  to node H and conversely, when differential input signal V in  is low, switch  24  will connect current source  26  to node L. 
     Assuming that differential input signal V in  is initially low, switch  24  will couple current source  26 , which has a current I 26 , to node  40 . Current I 26  will flow through resistor  30 , which has a resistance R 30 , and capacitor  34 . Capacitor  34  will be charged and the voltage at node  40  will fall to V CC −V 34 , where V 34  is the voltage across capacitor  34 . Capacitor  34  will charge until the voltage at node  40  falls to V CC −I 26 R 30 . The voltage at output terminal  48  will be V CC −I 26 R 30 −V BE2 , where V BE2  is the base-emitter voltage of transistor Q 2 . 
     Simultaneously, any charge on capacitor  32  will be discharged through resistor  28 , which has a resistance R 28 . When capacitor  32  is fully discharged, the voltage at node  42  will be V CC  and the voltage at output terminal  46  will be V CC −V BE1 , where V BE1  is the base emitter voltage of transistor Q 1 . Assuming that the base-emitter voltages of transistors Q 1  and Q 2  are the same and are equal to V BE  (i.e. V BE1 =V BE2 =V BE ), the low value of the differential output signal V out  will be                V   OL     =       V   48     -     V   46                   =       (       V   CC     -       I   26          R   30       -     V   BE       )     -     (       V   CC     -     V   BE       )                   =       -     I   26            R   30                                    
     When the differential input switches from low to high, switch  24  will couple current source  26  to node  42 . Current I 26  will now flow through resistor  28  and capacitor  32 , which was previously discharged. Capacitor  32  will charge and the voltage at output terminal  46  will fall to V CC −I 26 R 28 −V BE . Simultaneously, capacitor  34 , which was previously charged will discharge through resistor  30  and the voltage at output terminal  48  will rise to V CC −V BE . The high value of the differential output signal V out  will thus be                V   OH     =       V   48     -     V   46                   =       (       V   CC     -     V   BE       )     -     (       V   CC     -       I   26          R   28       -     V   BE       )                   =       I   26          R   28                                    
     When the differential input switches from high to low, the process described above will occur in reverse and the differential output signal will return to its initial value of −I 26 R 30 . 
     The specific output voltage levels will depend on the magnitude of current of current I 26  and the resistances R 28  and R 30 . If both resistors have the same value (as they generally will), the differential output voltage swing will be 2I 26 R, where R is the resistance of resistors  28  and  30 . 
     One skilled in the art will understand that emitter follower output stages  36  and  38  are required to match the output impedance of the transmission line to which the cable driver&#39;s output is directed. The impedance of a transmission line is generally resistive with very low reactance. The resistance of resistors  50  and  54  will normally be equal to the resistance of the transmission line. The use of the emitter follower output stages  36  and  38  introduces a potential problem of ringing and overshoot in the differential output signal appearing at output port  44 . The cable driver  20  will normally be integrated onto a single chip with a package. Emitter follower stages are typically inductive and combined with the parasitic capacitance of the cable driver&#39;s package, the output stage  36  or  38  may introduce resonance into the output. If this resonance is substantial, the overshoot and ringing introduced into the transmission line may exceed acceptable tolerances, depending on the particular installation of the prior art cable driver  20 . 
     Reference is now made to FIGS. 2A and 2B, which shows the input and output voltages of the prior art cable driver  20 , respectively. FIG. 2A shows differential input signal V in  received at input port  22  and FIG. 2B shows the differential output signal V out  generated by the prior art cable driver  20  at output port  32  in response to the differential input signal V in . 
     As shown, the differential output signal V out  rises and falls exponentially due to the presence of capacitors  32  and  34  in the prior art cable driver  20 . One skilled in the art will recognize that these capacitors in fact increase the rise and fall times of the differential output signal V out . However, these capacitors are required to ensure that the 20% to 80% rise and fall times are not less than the specified minimum time, and therefore ensure that electromagnetic radiation is not produced in the prior art cable device driver. The exponential rise and fall curve of the differential output signal limits the maximum bandwidth of the prior art cable driver  20 , as will be explained below. 
     As shown at point A on FIGS. 2A and 2B, when the differential input signal V in  does not remain high for a sufficiently long period, the differential output signal V out  does not approach its maximum output level. When the differential input signal V in  subsequently steps from high to low, the differential output signal begins to fall. The starting voltage level for the high to low transition of the output signal is lower than in the normal case, introducing pattern jitter into the differential output signal V out . The same effect is seen at point B when the differential input signal V in  has a short low input pulse. 
     Reference is next made to FIGS. 3A and 3B which show the effect of this pattern jitter more clearly, in the case of a short low input pulse. The dashed line in FIG. 3A shows a normal low input pulse in the differential input signal V in . The dashed line in FIG. 3B shows the corresponding differential output signal V out . Sufficient time has elapsed by the end of the normal low input pulse to permit the differential output signal V out  to reach its normal low level V OL . The solid line in FIG. 3B shows the differential output signal V out  when the differential input signal V in  has a short low input pulse, shown by the solid line in FIG. 3A, and the low to high transition occurs before the differential output signal V out  reaches V OL . In FIG. 3B, the difference between the dashed and solid lines is time jitter, as shown. 
     The degree of jitter may be calculated as follows. If the time at which the low pulse of the differential input signal V in  ends is time  0 , then the voltage of the output differential signal V out , in the normal case (dashed lines), may be written            V   out     =       V   OH     -       (       V   OH     -     V   OL       )          e       -   t         R   28          C   32                 ,                          
     where C 32  is the capacitance of capacitor  32  and t is time in seconds. To simplify the calculation of jitter, we make the following exemplary definitions: 
     V OH =1 volt 
     V OL =0 volts 
     R 28 =R 
     C 32 =C 
     Once skilled in the art will be capable of selecting appropriate components for the prior art cable driver  20  to produce these V OH  and V OL  voltages. 
     Thus, V out  may be written          V   out     =     1   -       e       -   t     RC       .                              
     The time at which V out  reaches any particular voltage Va may be written 
     
       
           t=−RC ln (1 −Va ) 
       
     
     Thus, the time t o  at which V out  reaches a voltage of 0.5V is 
     
       
           t   o   =−RC ln (0.5) 
       
     
     If the low to high transition of the input differential signal occurs when the differential output signal has a value of 0.02V (within 2% of its steady state value of 0V), V out  may be written          V   out     =     1   -     0.98          e       -   t     RC       .                                
     and the time at which V out  reaches any particular voltage Va may be written 
     
       
           t=−RC ln ((1 −Va )/0.98). 
       
     
     The time at which the differential output voltage V out  reaches a voltage of 0.5V is 
     
       
           t   1   =−RC ln (0.5/0.98) 
       
     
     The time jitter introduced by the 2% error may then be calculated as              Jitter   =       t   0     -     t   1                   =       -   RC                     ln        (   0.98   )                                      
     The 20% to 80% rise time of the differential output signal V out  may be written                t     20      –80       =       t     80      %       -     t     20      %                     =         -   RC                     ln        (   0.2   )         -     (       -   RC                     ln        (   0.8   )         )                   =       -   RC                     ln        (     0.2   /   0.8     )                     =       -   RC                     ln        (   0.25   )                                      
     The percentage effect of jitter resulting from a low to high transition which occurs when the output signal is settled to within 2% of it steady state value may be calculated as                %                 Jitter     =     Jitter   /     t     20      –80                     =       [       -   RC                     ln        (   0.98   )         ]     /     [       -   RC                     ln        (   0.25   )         ]                   =     1.46      %                                  
     This indicates that if the differential output voltage V out  does not settle to within 2% of its steady state value, a jitter of greater than 1.46% of the rise and fall time results. One skilled in the art will be able to show that this calculation holds true for an early high to low transition and for any arbitrary high and low voltage levels (V OH  and V OL ) for the differential output signal V out . 
     Reference is next made to FIG. 4, which shows the differential output signal V out , the 20% to 80% rise time of the differential output signal V out  for the prior art cable driver  20  (shown in FIG. 1) and the 2% settling time (i.e. the 98% rise time, t 98% ) of the differential output signal V out . Since the 20% to 80% rise time of the cable driver must exceed the specified minimum threshold, the maximum data rate which may be transmitted using the prior art cable driver  20  will be dependent on the ratio of the 20% to 80% rise time to the 2% settling time of the differential output signal V out . 
     The ratio of the 20% to 80% rise time of the differential output signal V out  to the 2% settling time of the differential output signal V out  may be calculated                  t     20      –80       /     t     98      %         =       [       -   RC                     ln        (   .25   )         ]     /     [       -   RC                     ln        (   0.02   )         ]                   =     35.4      %                                  
     If this ratio could be increased, the maximum data rate which may be transmitted on a transmission line could also be increased, without introducing any additional electromagnetic radiation and without increasing jitter. 
     Reference is next made to FIG. 5, which shows an improved cable driver  120 , according to the present invention. 
     The improved cable driver  120  comprises an input port  122 , an output port  144 , two resistors  128  and  130  and five switching stages SS 1 , SS 2 , SS 3 , SS 4  and SS 5  coupled in series by four delay stages, D 1 , D 2 , D 3  and D 4 . 
     Input port  122  comprises input terminals  158  and  160 . Output port  144  comprises output terminals  146  and  148 . Resistor  128 , which has resistance R 128 , is coupled between V CC  and node  148  and resistor  130 , which has resistance R 130 , is coupled between V CC  and node  146 . 
     Resistors  128  and  130  will be chosen to match the impedance of the transmission line to which the improved cable driver  120  is coupled. This eliminates the need for emitter follower output stages, so the associated problems of ringing and overshoot are avoided. 
     Switching stage SS 1  comprises a current source  162  and a switch  164 . Current source  162  is coupled between switch  164  and ground. Switch  164  is responsive to a differential input signal V in  received at input port  122  and may couple current source  162  to node H 1  or to node L 1 . Node H 1  is coupled to output terminal  148  and node L 1  is coupled to output terminal  146 . 
     Switching stages SS 2 , SS 3 , SS 4  and SS 5  each similarly comprise a current source  166 ,  170 ,  174  or  178 , respectively, and a switch  168 ,  172 ,  176  or  180 , respectively. These current sources and switches are coupled together and coupled to ground and to output terminals  148  and  146  in the same manner as current source  162  and switch  164 . 
     Delay stage D 1  is coupled to input port  122  at nodes  182  and  184  and provides a delayed signal V in−1  responsive to input signal V in  at nodes  198  and  200 . Switch  168  is coupled to nodes  198  and  200  and is responsive to signal V in−1  and may connect current source  166  to terminals H 2  or L 2 . Delay stages D 2 , D 3  and D 4  generate sequentially delayed signals V in−2 , V in−3  and V in−4  corresponding to V in  and V in−1 . They are similarly coupled between switches  168  and  172 ,  172  and  176  and  176  and  180  respectively such that each subsequent switch  172 ,  176  or  180  receives a signal corresponding to differential input signal V in−2 , V in−3 , V in−4  at a later time than the preceding switch. 
     As with the prior art cable driver  20 , the improved cable driver  120  will typically be configured to produce a differential output signal V out  at output terminals  146  and  148 . The differential output terminal is defined as the difference between the voltage at output terminal  148  (V 148 ) and the voltage at output terminal  146  (V 146 ): 
     
       
         
           V 
           out 
           =V 
           148 
           −V 
           146 
         
       
     
     The improved cable driver operates as follows. A differential input signal V in  is received at input terminals  158  and  160  and is directed to switch  164 . As with the prior art cable driver  20 , the differential input signal V in  is defined as the difference between the voltage received at terminal  160  (V 160 ) and the voltage received at terminal  158  (V 158 ): 
     
       
           V   in   =V   160   −V   158 . 
       
     
     Switch  164  is responsive to differential input signal V in . If V in  is high (i.e. V 160 &gt;V 158 ), switch  164  will couple current source  162  to node H 1  and conversely, if V in  is low (i.e. V 160 &lt;V 158 ), switch  164  will couple current source  162  to node L 1 . 
     Delay stage D 1  provides a delayed signal V in−1  corresponding to input signal V in  at nodes  198  and  200 . Switch  168  is responsive to signal V in−1 . If V in−1  is high, switch  168  will couple current source  166  to node H 2  and conversely, if V in−1  is low, switch  168  will couple current source  166  to node L 2 . In this manner, current sources  162  and  166  will be coupled to the same output terminal  146  or  148 . 
     Similarly switches  172 ,  176  and  180  are responsive to the delayed signals provided by delay stages D 2 , D 3  and D 4 , respectively, and will couple current sources  170 ,  174  and  178 , respectively, to the same output terminal  146  or  148  as current sources  162  and  166 . 
     At steady state, if V in  is low, all five current sources  162 ,  166 ,  170 ,  174  and  178  will be coupled to output terminal  148 . The voltage at terminal  148  (V 148 ) will be 
     
       
           V   148   =V   CC   −R   128 ( I   162   +I   166   +I   170   +I   174   +I   178 ). 
       
     
     The voltage at terminal  146  (V 146 ) will be V CC , and the differential output signal V out  will be                V   out     =       V   148     -     V   146                   =     -       R   128     (       I   162     +     I   166     +     I   170     +     I   174     +     I     178   )                         =     V   OL                                  
     If V in  is high, all five current sources  162 ,  166 ,  170 ,  174  and  178  will be coupled to output terminal  146  and the output voltage will be                V   out     =                  R   130          (       I   162     +     I   166     +     I   170     +     I   174     +     I   178       )                   =                V   OH                                  
     Assuming that the differential input signal V in  is initially high, differential output signal V out  will be equal to V OH . On the high to low transition of V in , switch  164  will switch current source  162  from terminal H 1  to L 1 . The voltage at terminal  146 , will rise to 
     
       
           V   146   =V   CC   −R   130 ( I   166   +I   170   +I   174   +I   178 ) 
       
     
     and the voltage at terminal  148  will fall to 
     
       
           V   148   =V   CC   −R   128 ( I   162 ). 
       
     
     The differential output voltage V out  will fall to                V   out     =       V   148     -     V   146                   =       -       R   128          (     I   162     )         +         R   130          (       I   166     +     I   170     +     I   174     +     I   178       )       .                                    
     Delay stage D 1  will, after its configured delay period, produce a high to low transition at terminals  198  and  200 . Switch  168  will then switch current source I 2  from terminal H 2  to terminal L 2  and the differential output voltage will fall to 
     
       
           V   out   =−R   128 ( I   162   +I   166 )+ R   130 ( I   170   +I   174   +I   178 ). 
       
     
     This process will continue until the delay periods of all four delay stages D 1 , D 2 , D 3  and D 4  have elapsed, all five switches  164 ,  168 ,  172 ,  176  and  180  have respectively coupled  162 ,  166 ,  170 ,  174  and  178  to output terminal  146  and V out  has fallen to V OL , as defined above. 
     Reference is next made to FIGS. 6A and 6B. FIG. 6A shows the transitions of switches  164 ,  168 ,  172 ,  176  and  180  from their respective H nodes to their respective L nodes in response to a high to low transition of the differential input signal. FIG. 6B shows the corresponding high to low transition of V out . Switches  164 ,  168 ,  172 ,  176  and  180  are non-ideal switches with a finite transition time. The transition time of switches  164 ,  168 ,  172 ,  176  and  180  and the delay times of delay stages D 1 , D 2 , D 3  and D 4  are preferentially chosen to ensure that the differential output signal V out  is substantially linear. At the same time, the 20% to 80% rise and fall times of the differential output signal V out  must exceed the specified minimum time. As shown in FIGS. 6A and 6B, if the transition time of the switching stages is too short, the output signal V out  will appear as a staircase signal with each step being separated by the delay of the respective delay stages D 1 , D 2 , D 3  and D 4 . Increasing the transition time of the switches  164 ,  168 ,  172 ,  176  and  180  will provide a smooth transition, improving the linearity of differential output signal V out , As shown in FIGS. 7A and 7B, which also shows the transitions of switches  164 ,  168 ,  172 ,  176  and  180  and the differential output signal V out , the differential output signal V out  may be made substantially linear by making appropriate choices in the design of the switching stages SS 1 , SS 2 , SS 3 , SS 4  and SS 5  and delay stages D 1 , D 2 , D 3  and D 4 . The design of these elements is described in detail below. As an example, a substantially linear differential output signal V out  may be achieved if the delay time between the corresponding signals V in , V in−1 , V in−2 , V in−3  and V in−4  is 70 ps and the transition time of the switches  164 ,  168 ,  172 ,  176  and  180  is 150 ps. This will provide a differential output signal with a transition time of approximately 220 ps. 
     When a low to high transition of V in  occurs subsequently, switches  164 ,  168 ,  172 ,  176  and  180  will couple their respective current sources  162 ,  166 ,  170 ,  174  and  178  to output terminal  148  and differential output signal will return to its initial high output level V OH . 
     Since the high to low and low to high transitions of the differential output signal V out  are substantially linear, the ratio of the 20% to 80% rise time of V out  to the 2% settling time (i.e. the 98% rise time) will be                  t     20      –80       /     t   98       =     0.6   /   0.98                 =   0.612               =     61.2        %   .                                    
     As described above, the 20% to 80% rise time or fall time of the differential output signal V out  must exceed a minimum time period. If both the prior art cable driver  20  and the improved cable driver  120  are (1) configured to operate with this minimum 20% to 80% minimum rise/fall time and (2) receive an input which allows them the meet the requirement that the differential output signal V out  must settle to with 2% of its steady state value (in order to reduce time jitter, as described above), the improved cable driver  120  will be capable of carrying a higher data rate than the prior art cable driver  20 . The ratio of the maximum data rate which may be carried by the improved cable driver  120  to the maximum data rate which may be carried by the prior art cable driver  20  may be calculated as follows: 
     
       
         61.2%/35.4% =1.73 
       
     
     Thus, the improved cable driver  120  is capable of carrying a data rate 1.73 times higher than the prior art cable driver  20 , without increasing the generation of electromagnetic radiation or increasing jitter in the differential output signal V out . One skilled in the art will recognize that if the particular application in which improved cable driver  120  requires that the jitter in the differential output signal V out  be less than 1.46%, as calculated above, the benefit of the invention will be commensurately greater. 
     Reference is next made to FIG. 8, which shows switching stage SS 1  and delay stage D 1  in detail. Switch  164  comprises a differential amplifier stage  220  and current source  162  comprises current mirror  222 . Current mirror  222  comprises transistor Q 5 , diode connected transistor Q 6  and reference current source  224 , which are connected in the well known current mirror configuration. The bases of transistors Q 5  and Q 6  are coupled together and the emitters of transistors Q 5  and Q 6  are connected to a voltage source −V EE . The collector of transistor Q 6  is coupled to V CC  through reference current source  224 . The current drawn by transistor Q 5  through differential amplifier stage  220  will depend on the current of current source  224  in known manner. Differential amplifier stage  220  comprises two transistors Q 3  and Q 4 , the emitters of which are connected together. The base of transistor Q 3  is coupled to input terminal  158  and the base of transistor Q 4  is coupled to input terminal  160 . The collector of transistor Q 3  comprises node L 1  and the collector of transistor Q 4  comprises node H 1 . The emitters of transistors Q 3  and Q 4  are coupled to the collector of transistor Q 5 . 
     The bases of transistors Q 3  and Q 4  are coupled to input terminals  158  and  160 , respectively and receive the differential input signal across their bases. One skilled in the art will be familiar with the operation of the differential amplifier stage  220  and the current mirror  222  and will understand the switching operation provided by the switching stage SS 1 . 
     Delay stage D 1  is comprised of a differential amplifier consisting of transistors Q 7  and Q 8 , resistors  226  and  228  and a current mirror comprising transistors Q 9 , diode connected transistor Q 10  and reference current source  230 . The emitters of transistors Q 7  and Q 8  are connected together and to the collector of transistor Q 9 . The base of transistor Q 9  is coupled the base of transistor Q 10 . The collector of transistor Q 10  is coupled to V CC  through reference current source  230 . The emitters of the transistors Q 9  and Q 10  are connected to −V EE . The collectors of transistors Q 7  and Q 8  are coupled to a voltage source V DD  through resistors  226  and  228 , respectively. Transistors Q 7  and Q 8  receive the differential input signal V in  across their bases, which are connected to input terminals  160  and  158  respectively. The collectors of transistors Q 7  and Q 8  are coupled to nodes  200  and  198  respectively. One skilled in the art will understand that the operation of Q 7  and Q 8  as a differential amplifier will produce signal V in−1  at nodes  198  and  200  (as discussed above) responsive to the differential input signal V in , but delayed in time. The length of the delay will depend on the current of current source Q 9 , which will depend on the current of reference current source  230  in known manner, the resistance of resistors  226  and  228  and other characteristics of the bipolar technology in which the cable driver circuit is realized. One skilled in the art will be capable of selecting appropriate components to ensure that the transitions of the differential output signal are substantially linear. 
     Although the invention has been described with reference to an embodiment with 5 rise/fall time stages and 4 delay stages, the number of rise/fall time stages and delay stages may be varied to meet the operational requirements of the particular context in which the improved cable driver  120  is used. In addition, by varying the number and configuration of the switching stages and the delay stages, a non-linear differential output signal V out  may be generated and in fact, any desired output wave form may be generated. 
     One skilled in the art will be capable of making the modifications necessary to use the improved cable driver  120  in these contexts and will recognize that these and other embodiments fall within the spirit and scope of the invention, as defined by the following claims.

Technology Classification (CPC): 7