Patent Abstract:
A shift register circuit comprising a plurality of stages dependently connected to an initial input signal or an output signal of a previous stage and connected to first and second clock signals which are mutually inverted. Each stage includes eight switching devices interconnected together with three capacitors and interfaced through eleven interface points. Some of the interface points are connected to the first and second clock signals according to whether the stage is an even numbered stage or an odd numbered stage. Other ones of the interface points are connectable to the first and second clock signals in alternative ways to reduce power consumption without changing an internal configuration of the stage.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of Korean Patent Application No. 2005-105697, filed on Nov. 4, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     Aspects of the present invention relate to a shift register circuit, and more particularly, to a shift register circuit provided in an organic electroluminescent display and sequentially outputting signals different in polarity.  
         [0004]     2. Description of the Related Art  
         [0005]     In general, an active matrix display such as an organic electroluminescent display is provided with a pixel array matrix in a region where data lines and scan lines intersect with each other.  
         [0006]     Here, the scan lines form horizontal lines (row lines) of a matrix pixel portion, through which predetermined signals are sequentially supplied by a shift register circuit provided in a scan driver.  
         [0007]     Such a shift register is widely classified into a dynamic shift register and a static shift register. The dynamic shift register needs a relatively small number of thin film transistors (TFT) per stage and has a simple structure, but the dynamic shift register has shortcomings that a frequency band for a clock is narrow and power consumption is relatively high.  
         [0008]     On the other hand, the static shift register needs a relatively large number of TFTs per stage, but it has advantages that the frequency band for the clock is wide and power consumption is relatively low.  
         [0009]     For a shift register to be mounted in the active matrix display such as the organic electroluminescent display, it is important to decrease the number of TFTs as long as functions of the shift register are not deteriorated. However, it is more important to secure high reliability and low power consumption in the circuit operation.  
         [0010]     Further, as the organic light emitting display has recently become larger having a large-sized panel, the scan driver to be mounted in the panel should include the shift register, thereby reducing the size, the weight and the production cost of the organic light emitting display. However, the conventional shift register includes a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor, so that it is difficult to mount it on the panel. Further, the conventional shift register including the PMOS transistor and the NMOS transistor consumes much power because a predetermined static current flows through the transistor while generating an output signal.  
       SUMMARY OF THE INVENTION  
       [0011]     Accordingly, an aspect of the present invention is to provide a 2-phase shift register circuit including a plurality of PMOS transistors and capacitors, in which a yield is enhanced, a production coat is reduced, and power consumption is lowered.  
         [0012]     According to an exemplary embodiment of the present invention, a shift register circuit includes n stages SRU 1  through SRUn. Each stage is dependently connected to an initial input signal IN or an output signal of a previous stage and connected to first and second clock signals CLK 1  and CLK 2 , each stage including: a first switching device SW 1  connected between a first power source VDD and an output terminal N 2 ; a second switching device SW 2  connected between the output terminal N 2  and a second power source VSS; a third switching device SW 3  connected between a first node N 1  and the output terminal N 2  and having a gate electrode connected to the gate electrode of the first switching device SW 1 ; a fourth switching device SW 4  connected between the first node N 1  and the second power source VSS and having a gate electrode connected to an output terminal of a conversion part; a fifth switching device SW 5  connected between a first input terminal and the gate electrode of the first switching device SW 1 ; a first capacitor C 1  connected between the output terminal N 2  and the first node N 1 ; and a second capacitor C 2  connected between the first power source VDD and the gate electrode of the first switching device SW 1 .  
         [0013]     Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:  
         [0015]      FIG. 1  is a block diagram of a shift register circuit according to an embodiment of the present invention;  
         [0016]      FIG. 2  is a circuit diagram of a stage (SRU) of the shift register circuit of  FIG. 1  according to a first embodiment of the present invention;  
         [0017]      FIGS. 3A-3G  are timing diagrams showing input/output signal waveforms of the shift register circuit shown in  FIG. 1 ;  
         [0018]      FIGS. 4A and 4B  are circuit diagrams of stages of the shift register circuit of  FIG. 1  according to second and third embodiments of the present invention; and  
         [0019]      FIG. 5  is a table comparatively showing the various interconnections of the stage circuits shown in  FIGS. 2, 4A  and  4 B. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0020]     Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.  
         [0021]      FIG. 1  is a block diagram of a shift register circuit according to an embodiment of the present invention.  
         [0022]     As shown in  FIG. 1 , the shift register circuit includes a plurality of stages (shift register units) SRU 1  through SRU(n). The 1 st  stage SRU 1  receives an initial input signal IN, and the output signals of the 1 st  through (n−1)th stages are supplied as input signals to the following stages thereof, respectively.  
         [0023]     Further, each stage SRU 1  through SRU(n) includes a first clock terminal CLKa and a second clock terminal CLKb which receive first and second clock signals CLK 1  and CLK 2  having phases inverted from each other. In the odd numbered stages, the first clock terminals CLKa receive the first clock signal CLK 1 , and the second clock terminals CLKb receive the second clock signal 2 . On the other hand, in the even numbered stages, the first clock terminals CLKa receive the second clock signal CLK 2 , and the second clock terminals CLKb receive the first clock signal CLK 1 .  
         [0024]     That is, the stages, which receive the initial input signal IN or the output voltages from the previous terminals and the first and second clock signals CLK 1  and CLK 2 , output predetermined signals through the respective output lines thereof in sequence.  
         [0025]     The shift register circuit according to the embodiment of the present invention employs the odd numbered stages to sequentially shift the signals having an inverted level with respect to the initial input signal, i.e., having an inverted polarity, and outputs the shifted signals P 1 , P 2 , . . . P(n−1), Pn; and employs the even numbered stages to sequentially shift the signals having the same phase with the initial input signal and outputs the shifted signals S 1 , S 2 , . . . S(n−1), Sn.  
         [0026]     Thus, the shift register circuit can either select the signals P 1 , P 2 , . . . P(n−1), Pn sequentially output from the odd numbered stages or the signals S 1 , S 2 , . . . S(n−1), Sn sequentially output from the even numbered stages.  
         [0027]     For example, when the shift register circuit is in general use, the signals S 1 , S 2 , . . . S(n−1), Sn output from the even numbered stages are selected.  
         [0028]     A predetermined capacitor C is, as shown in  FIG. 1 , may be provided in an output line of each stage SRU 1  through SRU(n).  
         [0029]      FIG. 2  is a circuit diagram of a stage (SRU) of the shift register circuit of  FIG. 1  according to a first embodiment of the present invention, and  FIGS. 3A-3G  are timing diagrams showing input/output signal waveforms of the shift register circuit shown in  FIG. 1 .  
         [0030]      FIG. 2  is a circuit diagram showing the 1 st  stage SRU 1  of the shift register circuit shown in  FIG. 1 . Here, the first and second clock signals CLK 1 , CLK 2 , respectively, and the initial input signal IN are input to the 1 st  stage SRU 1  of the shift register circuit. The CLK 1  and CLK 2  references shown in  FIG. 2  represent inputs to CLKa and CLKb, respectively, as shown in  FIG. 1 .  
         [0031]     Referring to  FIG. 2 , the stage SRU 1  of the shift register circuit shown in  FIG. 1  includes a first switching device SW 1  connected between a first power source VDD and an output terminal N 2 ; a second switching device SW 2  connected between the output terminal (OUT) N 2  and a second power source VSS; a third switching device SW 3  connected between a first node N 1  and the output terminal N 2  and having a gate electrode connected to a gate electrode of the first switching device SW 1 ; a fourth switching device SW 4  connected between the first node N 1  and the second power source VSS and having a gate electrode connected to an output terminal N 4  of a conversion part; a fifth switching device SW 5  connected between a first input terminal T 1  and the gate electrode of the first switching device SW 1 ; a first capacitor C 1  connected between the output terminal N 2  and the first node N 1 ; and a second capacitor C 2  connected between the first power source VDD and the gate electrode of the first switching device SW 1 .  
         [0032]     Here, the first power source VDD has a voltage level higher than that of the second power source VSS. Further, the first through fifth switching devices SW 1  through SW 5  may be implemented by PMOS transistors.  
         [0033]     The fifth switching device SW 5  has a first electrode connected to the first input terminal T 1  to receive the initial input signal IN and the gate electrode to receive the first clock signal CLK 1 .  
         [0034]     Further, the fourth switching device SW 4  has a first electrode connected to the first node N 1 , a second electrode connected to the second power source VSS, and the gate electrode connected to an output terminal N 4  of the conversion part.  
         [0035]     The conversion part includes a sixth switching device SW 6  connected between the first power source VDD and a third node N 3 ; a seventh switching device SW 7  connected between the third node N 3  and a second input terminal T 2 ; an eighth switching device SW 8  connected between the output terminal N 4  of the conversion part and a third input terminal T 3  and having a gate electrode connected to the third node N 3 ; and a third capacitor C 3  connected between the third node N 3  and the output terminal N 4  of the conversion part.  
         [0036]     Like the first input terminal T 1 , the gate electrode of the sixth switching device SW 6  receives the initial input signal IN.  
         [0037]     Further, a gate electrode of the seventh switching device SW 7  receives the second clock signal CLK 2 ; the second input terminal T 2  receives the second clock signal CLK 2 ; and the third input terminal T 3  receives the first clock signal CLK 1 .  
         [0038]     That is, the fourth switching device SW 4  is turned on/off by an output signal from terminal N 4  of the conversion part.  
         [0039]     Further, the first capacitor C 1  connected between the output terminal N 2  and the first node N 1  is also connected between the first electrode and the gate electrode of the second switching device SW 2 . Here, the first capacitor C 1  is charged with a voltage corresponding to whether the second switching device SW 2  is turned on or off.  
         [0040]     For example, when the second switching device SW 2  is turned on, the first capacitor C 1  stores a voltage to turn on the second switching device SW 2 . On the other hand, when the second switching device SW 2  is turned off. The first capacitor C 1  stores a voltage to turn off the second switching device SW 2 .  
         [0041]     Likewise, the second capacitor C 2  connected between the first power source VDD and the gate electrode of the first switching device SW 1  is also connected between the first electrode and the gate electrode of the first switching device SW 1 . Here, the second capacitor C 2  is charged with a voltage corresponding to whether the first switching device SW 1  is turned on or off.  
         [0042]     For example, when the first switching device SW 1  is turned on, the second capacitor C 2  stores a voltage to turn on the first switching device SW 1 . On the other hand, when the first switching device SW 1  is turned off, the second capacitor C 2  stores a voltage to turn off the first switching device SW 1 .  
         [0043]     Further, the third capacitor C 3  connected between the third node N 3  and the output terminal N 4  of the conversion part is also connected between the first electrode and the gate electrode of the eighth switching device SW 8 . Here, the third capacitor C 3  is charged with a voltage corresponding to whether the eighth switching device SW 8  is turned on or off.  
         [0044]     For example, when the eighth switching device SW 8  is turned on, the third capacitor C 3  stores a voltage to turn on the eighth switching device SW 8 . On the other hand, when the eighth switching device SW 8  is turned off, the third capacitor C 3  stores a voltage to turn off the eighth switching device SW 8 .  
         [0045]     Referring to  FIGS. 2 and 3 , the 1 st  stage SRU 1  of the shift register circuit operates as follows.  
         [0046]     In a first period T 1 , the first clock signal CLK 1  has a low level; the second clock signal CLK 2  has a high level; and the initial input signal has a high level.  
         [0047]     In this case, the sixth and seventh switching devices SW 6  and SW 7  are turned off, and the eighth switching device SW 8  is turned on by a voltage previously stored in the capacitor C 3 , thereby turning on the fourth switching device SW 4  having the gate electrode connected to the output terminal N 4  of the conversion part.  
         [0048]     Then, the fifth switching device SW 5  is turned on by the first clock signal CLK 1 , and thus the input signal IN having the high level is input to the gate electrode of the first switching device SW 1 , thereby turning off the first switching device SW 1 .  
         [0049]     Therefore, the second capacitor C 2  is charged with a voltage to turn on the first switching device SW 1  during the first period T 1 , i.e., a voltage corresponding to turning-off the first switching device SW 1 .  
         [0050]     Because the input signal IN has the high level, the third switching device SW 3  is also turned off. Further, the fourth switching device SW 4  turned on as described above allows the second power source VSS to apply a voltage to the gate electrode of the second switching device SW 2 . Then, the output corresponds to the second power source VSS connected to the second electrode of the second switching device SW 2 , i.e., has the low level.  
         [0051]     Thus, the first capacitor C 1  is charged with a voltage to turn on the second switching device SW 2  during the first period T 1 , i.e., a voltage corresponding to turning on the second switching device SW 2 .  
         [0052]     In a second period T 2 , the first clock signal CLK 1  has a high level; the second clock signal CLK 2  has a low level; and the initial input signal has a low level.  
         [0053]     In this case, the sixth and seventh switching devices SW 6  and SW 7  are turned on, and the eighth switching device SW 8  is also turned on as the second clock signal having the low level is applied to the gate electrode of the eighth switching unit SW 8  by the turned on seventh switching device SW 7 .  
         [0054]     Then, the capacitor C 3  is charged with a voltage to turn on the eighth switching device SW 8  during the second period T 2 , i.e., a voltage corresponding to turning-on the eighth switching device SW 8 .  
         [0055]     When the eighth switching device SW 8  is turned on, the first clock signal CLK 1  having the high level is output through the output terminal N 4  of the conversion part, thereby turning off the fourth switching device SW 4  having the gate electrode connected to the output terminal of the conversion part.  
         [0056]     Further, the fifth switching device SW 5  is turned off by the first clock signal CLK 1 , and thus the first and third switching devices SW 1  and SW 3  are turned off by the voltage previously stored in the second capacitor C 2 .  
         [0057]     As the fourth switching transistor SW 4  is turned off, the second switching device SW 2  is turned on by the voltage previously stored in the first capacitor C 1 , so that the output corresponds to the second power source VSS connected to the second electrode of the second switching device SW 2 , i.e., has the low level. As a result, the output in the first period T 1  is maintained in the second period T 2 .  
         [0058]     In a third period T 3 , the first clock signal CLK 1  has a low level; the second clock signal CLK 2  has a high level; and the initial input signal has a low level.  
         [0059]     In this case, the sixth switching device SW 6  is turned on and the seventh switching device SW 7  is turned off. Then, the voltage applied to the gate electrode of the eighth switching device SW 8  is boosted up to be equal to the first power source VDD supplied from the first electrode of the sixth switching device SW 6 . Thus, when the gate voltage of the eighth switching device SW 8  increases up to the first power source VDD, the voltage applied to the first electrode cannot decrease below the first power source VDD, so that the first power source VDD of the high level is output through the output terminal N 4  of the conversion part, thereby turning off the fourth switching device SW 4  having the gate electrode connected to the output terminal of the conversion part.  
         [0060]     Further, the fifth switching device SW 5  is turned on by the first clock signal CLK 1 , and thus the input signals having the low level are applied to the gate electrodes of the first and third switching devices SW 1  and SW 3 , thereby turning on the first and third switching devices SW 1  and SW 3 .  
         [0061]     Then, the second capacitor C 2  is charged with a voltage to turn on the first switching device SW 1  during the third period T 3 , i.e., a voltage corresponding to turning on the switching device SW 1 .  
         [0062]     Thus, when the first and second switching devices SW 1  and SW 3  are turned on, the first power source VDD having the high level is applied to the output terminal and the gate electrode of the second switching device SW 2 .  
         [0063]     On the other hand, the second switching device SW 2  is turned off, so that the first capacitor C 1  is charged with a voltage to turn off the second switching device SW 2  during the third period T 3 , i.e., a voltage corresponding to turning off the second switching device SW 2 , thereby outputting the first power source VDD of the high level.  
         [0064]     In a fourth period T 4 , the first clock signal CLK 1  has a high level; the second clock signal CLK 2  has a low level; and the initial input signal has a high level.  
         [0065]     In this case, the sixth switching device SW 6  is turned off and the seventh switching device SW 7  is turned on. Therefore, the second clock signal CLK 2  having the low level is input to the gate electrode of the eighth switching device SW 8 , so that the eighth switching device SW 8  is turned on, thereby outputting the first clock signal CLK 1  having the high level through the output terminal N 4  of the conversion part.  
         [0066]     Thus, the fourth switching transistor SW 4  having the gate electrode connected to the output terminal of the conversion part is turned off.  
         [0067]     Further, the fifth switching device SW 5  is turned off by the first clock signal CLK 1 , and the first and third switching devices SW 1  and SW 3  are turned on by the voltage previously stored in the second capacitor C 2 , i.e., the voltage previously stored during the third period T 3  and turning on the first switching device SW 1 .  
         [0068]     As the fourth switching device SW 4  is turned off, the second switching device SW 2  is turned off by the voltage previously stored in the first capacitor C 1  and turning off the second switching device SW 2 , thereby outputting the first power source VDD of the high level through the output terminal. As a result, the output in the third period T 3  is maintained in the fourth period T 4 .  
         [0069]     Meanwhile, the foregoing first through fourth periods T 1  through T 4  are repeated in sequence, thereby obtaining output waveforms as shown in  FIGS. 3A-3G .  
         [0070]     In each period, each stage of the shift register circuit shown in  FIG. 1  is operated so that the output signal has a level inverted with respect to the input signal IN when the first clock signal CLK 1  has the low level, but the level of the output signal in the previous period is maintained when the first clock signal CLK 1  has the high level.  
         [0071]     The remaining stages SRU 2  through SRU(n) are constructed the same as the stage SRU 1  shown in  FIG. 2 , however the connections of stages SRU 2  through SRU(n) differ from the connections of stage SRU 1  in the following respects. Each stage SRU 2  through SRU(n) receives an output of a previous stage as an input at the first input terminal T 1  and the gate of switching device SW 6  instead of the input signal IN. Odd numbered stages  3 ,  5 ,  7 , etc., receive the first clock signal CLK 1  and the second clock signal CLK 2  as shown in  FIG. 2  and even numbered stages,  2 ,  4 ,  6 , etc., receive the second clock signal CLK 2  where the first clock signal CLK 1  is shown in  FIG. 2  and receive the first clock signal CLK 1  where the second clock signal CLK 2  is shown in  FIG. 2 .  
         [0072]      FIGS. 4A and 4B  are circuit diagrams of stages SRU 1  through SRU(n) according to second and third embodiments of the present invention, respectively, in the shift register circuit of  FIG. 1 . Here, like elements having like numerals as elements shown in the stage of  FIG. 2  have a same function the elements shown in  FIG. 2 , and repetitive descriptions will be avoided.  
         [0073]     In the shift register circuit according to the first embodiment shown in  FIG. 2 , the sixth and seventh switching devices SW 6  and SW 7  may be turned on at the same time, so that power consumption increases.  
         [0074]     In the state that the sixth and seventh switching devices SW 6  and SW 7  are turned on at the same time, the first clock signal has the high level, so that the fourth switching device SW 4  is turned off, thereby having no effect on the final output.  
         [0075]     The embodiments illustrated in  FIGS. 4A and 4B  are provided for further reducing the power consumption of the shift register circuit shown in  FIG. 1 . The embodiments shown in  FIGS. 4A and 4B  have the same configuration as the first embodiment and differ in an arrangement of inputs to the circuit of each stage.  
         [0076]     According to the second embodiment as shown in  FIG. 4A , a source electrode of the eighth switching device SW 6  is connected to the second clock signal CLK 2  rather than to the first power source VDD as in the first embodiment shown in  FIG. 2 . According to the third embodiment as shown in  FIG. 4B , a drain electrode of the fourth switching device SW 4  is connected to the first clock signal CLK 1  rather than the second power source VSS as in the first embodiment shown in  FIG. 2 .  
         [0077]     Referring to  FIG. 4A  and  FIG. 2 , the operation of the second embodiment is as follows.  
         [0078]     In the first period T 1 , the sixth switching device SW 6  is turned off by the input voltage IN having a high level.  
         [0079]     In the second period T 2 , the sixth switching device SW 6  is turned on by the input voltage IN having a low level. Further, the seventh switching device SW 7  is turned on by the second clock signal CLK 2  having a low level supplied to a gate electrode of the seventh switching device SW 7  in the second period T 2 . Then, the sixth and seventh switching devices SW 6  and SW 7  are turned on, so that a low level voltage is applied to the gate electrode of the eighth switching device SW 8 . In this case, the eighth switching device SW 8  is turned on, so that a high level voltage is applied to the output terminal N 4  of the conversion part.  
         [0080]     According to the second embodiment, even though the sixth and seventh switching devices SW 6  and SW 7  are turned on at the same time in the second period T 2 , the sixth switching device SW 6  receives the second clock signal CLK 2  through the first electrode of the switching device SW 6 , thereby decreasing the power consumption. Comparatively, when the sixth and seventh switching devices SW 6  and SW 7  according to the first embodiment are turned on at the same time, the first power source VDD input to the first electrode of the sixth switching device SW 6  and the second clock signal CLK 2  input to the first electrode of the seventh switching device SW 7  are connected, so that power consumption is relatively high. On the other hand, according to the second embodiment, since the first electrode of the sixth switching device SW 6  receives the second clock signal CLK 2 , the power consumption is relatively low.  
         [0081]     In the third period T 3 , the sixth switching device SW 6  is turned on by the input voltage IN having the low level. As the sixth switching device SW 6  is turned on, the high level voltage is applied to the gate electrode of the eighth switching device SW 8 . Then, the voltage applied to the first electrode of the eighth switching device SW 8  is not dropped to less than the high level, so that the fourth switching device SW 4  is turned off.  
         [0082]     In the fourth period T 4 , the sixth switching device SW 6  is turned off by the input voltage having the high level.  
         [0083]     As described above, the circuit diagram according to the second embodiment of the present invention has a same structure as the circuit diagram of the first embodiment shown in  FIG. 2 . However, in operation, the circuit according to the second embodiment of the present invention has advantages that the power consumption is relatively low even though the sixth and seventh switching devices SW 6  and SW 7  are turned on at the same time.  
         [0084]     Referring now to  FIG. 4B  and  FIG. 2 , the operation of the third embodiment is as follows.  
         [0085]     In the first period T 1 , the fourth switching device SW 4  is turned on by an input voltage having a low level and supplied from the output terminal N 4  of the conversion part. At this time, the first clock signal CLK 1  having the low level is applied to the first electrode of the fourth switching device SW 4 . In this case, the low level voltage is applied to the gate electrode of the second switching device SW 2 , so that the second switching device SW 2  is turned on. In the second period T 2 , the third period T 3  and the fourth period T 4 , the conversion part supplies the high level voltage, so that the fourth switching device SW 4  is turned off.  
         [0086]     That is, the shift register circuit according to the third embodiment of the present invention is operated like that of the first embodiment shown in  FIG. 2 . Here, the shift register circuit according to the third embodiment employs the odd numbered stages to sequentially shift the signals having an inverted level, i.e., having the opposite polarity to the initial input signal and outputs the shifted signals P 1 , P 2 , . . . . . . , Pn; and employs the even numbered stages to sequentially shift the signals having the same phase with the initial input signal and outputs the shifted signals S 1 , S 2 , . . . . . . , Sn. Thus, in the case where the shift register circuit according to the third embodiment is used as a typical shift register circuit, the output lines of the odd numbered stages can be removed so as to select only the signals S 1 , S 2 , . . . . . . , Sn output through the even numbered stages.  
         [0087]     The stage circuits shown in  FIGS. 2, 4A  and  4 B may be viewed as a circuit having first through eleventh interface points and connectable in a variety of ways to achieve a same result in an operating shift register circuit. Various combinations of connections of the stage circuit are summarized in  FIG. 5 . In  FIG. 5 , IN 1  represents an initial input or an output of a previous even numbered stage and IN 2  represents an output of a previous odd numbered stage.  
         [0088]     The embodiments of the present invention provide a shift register circuit, which can improve a production yield thereof and decrease a production cost and a power consumption thereof.  
         [0089]     Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Technology Classification (CPC): 6