Patent Abstract:
The present disclosure relates to resource management of memory using information regarding the physical state of the memory device(s), and, more specifically, to attempting to reduce the heat dissipation of a memory device by managing the contents of the memory device.

Full Description:
BACKGROUND 
   1. Field 
   The present disclosure relates to resource management of memory using information regarding the physical state of the memory device(s), and, more specifically, to attempting to reduce the heat dissipation of a memory device by managing the contents of the memory device. 
   2. Background Information 
   Currently most electrical devices generate heat during operation. Memory devices generate heat when data is read from or written to the device. Typically the heat generated by such accesses is minimal. Usually, the data stored in each memory element is accessed so infrequently that any generated heat has the opportunity to dissipate before the next access generates additional heat. However, when a particular memory element is accessed frequently, the generated heat may build-up and become noticeable. This heat build-up may then cause undesirable effects. 
   Typically in modern processing systems very little thought is given to the heat generated and dissipated by the system memory devices. If any technique is used to manage the heat generated by these devices, if often occurs in one of two ways. 
   In one known technique, a heat sink or heat spreader is attached to the memory device. The heat spreader is typically a piece of metal or other thermally conductive material that facilitates the transfer of heat from the memory element to the ambient environment, typically air or fluid, if water-cooled. In some cases a fan or pump may be employed to provide circulation of the ambient environment. 
   In another technique, thermal monitoring may be used to determine when the memory element is overheating, or has otherwise reached a thermal limit. Upon reaching this limit, a system may typically throttle memory access, which decreases performance. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Subject matter is particularly pointed out and distinctly claimed in the concluding portions of the specification. The claimed subject matter, however, both as to organization and the method of operation, together with objects, features and advantages thereof, may be best understood by a reference to the following detailed description when read with the accompanying drawings in which: 
       FIG. 1  is a flowchart illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter; 
       FIG. 2  is a flowchart illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter; 
       FIG. 3  is a block diagram illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter; 
       FIG. 4  is a block diagram illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter; and 
       FIG. 5  is a block diagram illustrating an embodiment of an apparatus and a system that is capable of memory resource management in accordance with the claimed subject matter. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, numerous details are set forth in order to provide a thorough understanding of the present claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as to not obscure the claimed subject matter. 
   In this context, a “memory element” is any memory device of various size. The term includes the terms, such as, for example, “memory chip,” “memory module,” and “memory bank.” 
   In this context, “memory chip” is defined as an integrated chip comprising several memory locations. A memory chip is typically, but not limited to, being comprised of Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash memory, Read-Only Memory (ROM) or another form of memory. 
   In this context, “memory module” is defined as device comprising, typically, multiple memory chips arranged to facility access to the memory chips. A memory module is often, but not necessarily, a small circuit board carrying several memory chips. 
   In this context, “memory bank” is defined as a portion of a system that includes slots, or other connections, for memory modules. Typically memory banks are organized into units representing the minimum or maximum number of memory chips the system is designed to allow to operate in tandem. 
     FIG. 1  is a flowchart illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter. Block  110  illustrates that a condition of the memory may be detected. This condition may act as an indicator of an undesirable effect, such as, for example, in one embodiment excessive or over-heating of the memory element or, in another example, limited or reduced performance; however, other undesirable effects are contemplated and within the scope of the disclosed matter. It is contemplated that the condition may in one embodiment include such things as frequent access to the same area of memory, a signal from a thermal sensor, or information obtained about how a program intends to access a specific portion of memory; however, it is understood that these are merely a few non-limiting examples. 
   Block  120  illustrates that it may be determined how to reallocate the contents of the memory in order to at least in part ameliorate the undesirable effect. It is contemplated that, in one embodiment, the contents of the memory may be moved or copied from a comparatively large portion of memory to a plurality of comparatively smaller memory portions. It is contemplated that by spreading the contents of the memory portion from one memory element to multiple memory elements the undesirable effect may be reduced or avoided. 
   For example, in one embodiment, if the undesirable effect is excessive heat generation, by moving the contents of the memory portion to multiple memory elements, the heat generated by access to that memory portion will be spread across the multiple elements as opposed to concentrated at the single original memory element. 
   In another illustrative embodiment, if the undesirable effect is reduced performance, by moving the contents of the memory portion to multiple memory elements, the memory elements may be accessed in parallel or a quicker fashion and performance may be increased. However, these are merely two illustrative embodiments and other embodiments are contemplated and within the scope of the disclosed subject matter. 
   Blocks  133 ,  135 , &amp;  138  illustrate that, in one embodiment, an attempt may be made to minimize the number of levels of memory hierarchy that are affected by the reallocation. Block  133  illustrates that an attempt may be made to ameliorate the undesirable effect by merely reallocating the contents of the memory portion from one memory chip to multiple memory chips. Block  135  illustrates a similar concept but at the memory module level, i.e. reallocating the memory portion from one memory module to multiple memory modules. Block  138  illustrates a similar concept but at the memory bank level, i.e. reallocating the memory portion from one memory bank to multiple memory banks. It is understood that multiple reallocation techniques and preferences may be used and are within the scope of the disclosed subject matter. 
   Block  140  illustrates that the contents of the targeted memory portion may be reallocated amongst memory elements. In one embodiment, Block  150  illustrates that the contents of a sub-portion of the affected memory portion may be copied to a new location. Block  160  illustrates that this may occur until all desired sub-portions of the affected memory portion is copied. 
     FIG. 3  is a block diagram illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter.  FIG. 3  provides a graphical illustration of an embodiment the reallocation process. In memory state  300 , three memory elements  310 ,  320  &amp;  330  exist. Memory portion  340  is stored within memory element  320 . As described above and illustrated in  FIG. 1 , the memory portion  340  is detected as causing an undesirable effect. The memory portion is then reallocated across the three memory elements. 
   Memory state  350  illustrates that the contents of memory portion  340  have been moved from memory element  320 . The memory portion  340  has been sub-divided into three sub-portions  360 ,  370 , &amp;  380 . These three sub-portions have been moved to memory elements  310 ,  320 , &amp;  330 , respectively. It is contemplated that in one embodiment, the memory portions may have been copied from portion  340 , allowing portion  340  to be accessed while the copying operations took place, or in another embodiment, it is contemplated that normal access to portion  340  was halted and the portions were moved; however, other reallocation techniques are contemplated and within the scope of the disclosed matter. 
   It is also understood that while  FIG. 3  shows three sub-portions of roughly identical size, the sub-portions may be of any size. It is further understood that while  FIG. 3  shows the memory portion  340  reallocated across all available memory elements, the disclosed subject matter is not limited to reallocating across any specific number or percentage of memory elements. It is yet further understood that while sub-portion  370  does not appear to have moved from the same memory location as portion  340 , the invention is not limited to keeping any sub-portion in a specific location, or moving every sub-portion from the original location. 
   Returning to  FIG. 1 , Block  170  illustrates that in one embodiment, the virtual memory tables may be remapped to point to the new post-reallocation physical memory address. In many systems, the memory addresses provided to the processor or software are virtual addresses that map to the physical addresses of the memory elements. By remapping the virtual address of the original memory portion to the new memory portions, it is contemplated that the memory reallocation may appear as seamless to the rest of the system as possible. It is contemplated that in one embodiment the remapping action may take place during the reallocation action; such as, for example, the remapping may occur as part of, in parallel with, or substantially simultaneously with the reallocation. 
     FIG. 2  is a flowchart illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter.  FIG. 2  illustrates an embodiment where the technique of  FIG. 1  has been modified to include Redundant Arrays of Independent Devices (RAID). Typically RAID is used in the context of hard drives and other non-volatile memory devices, where it is also referred to by the terms “Redundant Arrays of Inexpensive Drives” or “Redundant Arrays of Independent Drives”. It endeavors to provide reliable storage at relatively reasonable costs. However, in this context, RAID may also be used to provide volatile memory storage. It is contemplated that a number of memory elements may be used to provide reliable volatile memory storage at relatively reasonable costs using substantially similar techniques or techniques derived from those used for non-volatile storage RAID. It is further contemplated that some embodiments of the disclosed subject matter may include substantially non-volatile memory elements, such as, for example, flash RAM. 
   Block  245  illustrates that the reallocation process may be carried out for each affect device in the memory RAID. It is contemplated that in one embodiment, the redundancy of the array may be affected while first one memory device is reallocated than another, and so forth. In one embodiment, the array may be inaccessible during the reallocation process. 
     FIG. 4  is a block diagram illustrating an embodiment of a memory resource management technique in accordance with the claimed subject matter. Memory state  400  includes memory devices  401  &amp;  402  arranged in what is known as a RAID 1 (a.k.a. data mirroring) configuration, although other RAID configurations are contemplated and within the scope of the invention. In this embodiment, memory device  402  acts as a backup of memory device  401 . The memory devices include memory portions  441  &amp;  442 , respectively. 
   Memory state  450  illustrates that, in one embodiment, memory device  402  may undergo reallocation first. Memory portion  442  may be moved or copied from memory element  422  to memory sub-portions  462 ,  472 , &amp;  482  on memory elements  412 ,  422 , &amp;  432 , respectively. During this time, it is contemplated that access to the array may be, for example, limited in the entirety, limited to read-only access for the array, or not restricted at all; however, these are merely a few non-limiting examples. 
   Memory state  490  illustrates that both memory devices have completed the reallocation process and are once again in-sync, as dictated by the RAID 1 standard. The memory portion  441  of memory device  401  has been reallocated to sub-portions  481 ,  471 , &amp;  461  on memory elements  431 ,  421 , &amp;  411 , respectively. It is contemplated that in one embodiment, if any access restrictions were placed upon the RAID system during the reallocation process those restrictions may be lifted when memory state  490  is reached. 
   It is contemplated that in one embodiment, the memory portions may have been copied from portions  441  &amp;  442 , allowing one or both portions to be accessed while the copying operations took place, or in another embodiment, it is contemplated that normal access to portions  441  &amp;  442  were halted and the portions were moved; however, other reallocation techniques are contemplated and within the scope of the disclosed matter. 
   It is also understood that while  FIG. 4  shows three sub-portions of roughly identical size, the sub-portions may be of any size. It is further understood that while  FIG. 4  shows the memory portions  441  &amp;  442  reallocated across all available memory elements, the disclosed subject matter is not limited to reallocating across any specific number or percentage of memory elements. It is yet further understood that while sub-portions  471  &amp;  472  do not appear to have moved from the same memory location as portions  441  &amp;  442 , respectively, the invention is not limited to keeping any sub-portion in a specific location, or moving every sub-portion from the original location. 
     FIG. 5  is a block diagram illustrating an embodiment of an apparatus  501  and a system  500  that is capable of memory resource management in accordance with the claimed subject matter. Apparatus  501 , in one embodiment, may include condition detector  510 , memory reallocator  520 , and memory  540 . Memory  540  may include a number of memory elements, illustrated by memory elements  541  and  549 . In one embodiment, the apparatus may be capable of performing one or both of the techniques illustrated by  FIGS. 1 &amp; 2 . 
   Condition Detector  510  may be capable of detecting that a condition exists in memory  540  that may result in an undesired effect, as illustrated by Block  110  of  FIG. 1 . Memory Reallocator  520  may then determine how to reallocate the contents of the memory in order to attempt to ameliorate the undesired effect, as illustrated by Blocks  120 ,  133 ,  135 , &amp;  138  of  FIG. 1 . The Memory Reallocator may then reallocate the memory according to that determination, as illustrated by Blocks  140 ,  150 , &amp;  160  of  FIG. 1  and Block  245  of  FIG. 2 . In one embodiment, the reallocation may occur as described above and illustrated in  FIGS. 1 ,  2 ,  3 , &amp;  4 . 
   In another embodiment, the apparatus may also include a Virtual Memory Map  530 . This map may be a table that facilitates the conversion of virtual memory addresses to physical memory addresses. It is contemplated that this Virtual Memory Map may, in one embodiment, be different from the system level virtual memory map. It is also contemplated that the system level memory map may map system level virtual memory addresses to apparatus level memory addresses, which are then in turned mapped to physical address by Virtual Memory Map  530 . It is contemplated that this double indirection may occur with or without the knowledge of the system. However, this is merely one embodiment, and other embodiments are within the scope of the disclosed subject matter. 
   System  500  may include apparatus  501 , a processor  590 , and a memory controller  580 . In one embodiment, the processor may be capable of processing instructions and/or data stored in memory  540 . In one embodiment, the memory controller may be capable of controlling the processor&#39;s access to the memory. In one embodiment, the Virtual Memory Map may be part of or integrated with apparatus  501 , memory controller  580 , processor  590 , or a substantially independent component of system  500 . 
   The techniques described herein are not limited to any particular hardware or software configuration; they may find applicability in any computing or processing environment. The techniques may be implemented in hardware, software, firmware or a combination thereof. The techniques may be implemented in programs executing on programmable machines such as mobile or stationary computers, personal digital assistants, and similar devices that each include a processor, a storage medium readable or accessible by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. Program code is applied to the data entered using the input device to perform the functions described and to generate output information. The output information may be applied to one or more output devices. 
   Each program may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. However, programs may be implemented in assembly or machine language, if desired. In any case, the language may be compiled or interpreted. 
   Each such program may be stored on a storage medium or device, e.g. compact disk read only memory (CD-ROM), digital versatile disk (DVD), hard disk, firmware, non-volatile memory, magnetic disk or similar medium or device, that is readable by a general or special purpose programmable machine for configuring and operating the machine when the storage medium or device is read by the computer to perform the procedures described herein. The system may also be considered to be implemented as a machine-readable or accessible storage medium, configured with a program, where the storage medium so configured causes a machine to operate in a specific manner. Other embodiments are within the scope of the following claims. 
   While certain features of the claimed subject matter have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the claimed subject matter.

Technology Classification (CPC): 6