Patent Abstract:
One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones.

Full Description:
RELATED APPLICATIONS 
     The present application is related to concurrently filed and commonly assigned U.S. patent application Ser. No. 10/679,786, entitled “SYSTEMS AND METHODS FOR SYNCHRONIZING MULTIPLE VARIABLE FREQUENCY CLOCK GENERATORS,” which is incorporated herein by reference. 
     BACKGROUND 
     In a central processing unit (CPU), the operations of various logical components are controlled by a system clock which is generally generated utilizing a phase-lock loop (PLL). The operations of the various logical components are interrelated and, hence, various circuit path timing constraints typically exist. The actual timing associated with the circuit paths during operation of the CPU may depend upon the voltage supplied to the various components of the CPU. To ensure that the timing constraints are satisfied and that the CPU operates as expected, the frequency of the system clock may be selected according to worst-case criteria. In a relatively large and complex CPU, the supply voltage supplied to various components of the CPU may vary for a variety of reasons. If the frequency of the system clock is selected according to the worst-case criteria for all of the various components, system performance may be appreciably restricted. 
     SUMMARY 
     One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones. 
     Another embodiment of the invention comprises, for a central processing unit that comprises multiple clock zones, generating at least one power signal that is indicative of a power supply voltage within each of the clock zones, adjusting a frequency of a first local clock in a first clock zone of the clock zones in response to a respective power signal from the first clock zone, communicating the first clock zone frequency adjustment to a second clock zone, and adjusting a frequency of a second local clock in the second clock zone in response to the first clock zone frequency adjustment. 
     Another embodiment of the invention comprises, in each clock zone of a central processing unit, means for generating a power signal that is indicative of a power supply voltage within the clock zone, and means for modifying a frequency of a respective variable frequency clock in response to the power signal and in response to frequency adjustment communications from other clock zones. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a central processing unit (CPU) with multiple clock zones according to one representative embodiment. 
         FIG. 2  depicts a phase controller according to one representative embodiment. 
         FIG. 3  depicts a process flow for operating a phase controller according to one representative embodiment. 
         FIG. 4  depicts another process flow for operating a phase controller according to one representative embodiment. 
         FIG. 5  depicts a method of operation a CPU that includes multiple clock zones. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  depicts CPU  100  at a relatively high level according to one representative embodiment. CPU  100  may contain, as is well known, a large number of functional blocks and components (which are not shown). CPU  100  includes structure for providing respective clocks to functional blocks and components according to a plurality of zones (shown as  104 - 1  through  104 - 4 ). Zones  104 - 1  through  104 - 4  are separated from each other by one or more cycles of communication latency. 
     Each zone includes a respective variable clock generator  103 . Variable clock generators  103  generate a local clock for the respective zone that is derived from master phase-locked loop (PLL)  105 . In one representative embodiment, variable clock generators  103  may possess a limited capability of changing the frequency of the local clock within a single cycle. For example, variable clock generators  103  may be limited to adjusting their frequencies by changing the periods of their clocks by −1 “tick,”+1 “tick”, and +2 “ticks”, where a “tick” is a suitable fraction (e.g., 1/64) of the period of the input clock from master PLL  105 . 
     Each phase controller  101  receives input signals from one or several regional voltage detectors  102  (or, alternatively, thermal sensors) to control variable clock generators  103 . Specifically, each regional voltage detector  102  monitors the voltage of the CPU power supply within its localized area to detect when the voltage crosses a threshold level. Upon such detection, regional voltage detector  102  generates a signal indicative of the voltage condition for communication to phase controller  101 . Phase controller  101 , in turn, provides a suitable signal to variable clock generator  103  to modify its frequency. 
     When one of phase controllers  101  causes the frequency of the local clock within its zone to be changed, the respective phase controller  101  communicates this information to other phase controllers  104 . For example, phase controller  101  of zone  104 - 1  communicates its clock frequency adjustments to phase controllers  101  of zones  104 - 2  through  104 - 4 . The communication of the frequency adjustment may occur according to one or more cycles of latency. Specifically, the other phase controllers  101  receive the communication of the frequency adjustment during the next clock cycle or another subsequent clock cycle. Because the communication occurs according to one or more cycles of latency, the clocks associated with the phase controllers  101  that received the communication of the clock frequency adjustment are also out-of-phase relative to the clock associated with the frequency adjustment. To compensate for the phase misalignment, the responding phase controllers  101  temporarily adjust the frequency of their clocks beyond the communicated frequency adjustment to drive the phase misalignment to zero. When the phase misalignment is driven to zero, the responding phase controllers  101  cause another frequency adjustment (in the opposite direction) to cause the frequency of its local clock to match the frequency of the clock associated with the original frequency adjustment. 
       FIG. 2  depicts phase controller  101  in greater detail according to one representative embodiment. Phase controller  101  includes next phase controller state machine (PCSM) logic  201 . Next PCSM logic  201  is operable to control the state and, hence, the output signals from phase controller  101 . Next PCSM logic  201  receives inputs (e.g., “UP” or “DOWN” signals as appropriate) from regional voltage detectors  102  via line  206  (also denoted by “R”) to communicate the occurrence of a voltage transient or the like that necessitates a change in clock frequency. Next PCSM logic  201  further receives inputs from other phase controllers  101  via line  207  (also denoted by “D”) to enable phase controller  101  to synchronize its clock to adjustments made in clocks in other zones  104 . Next PCSM logic  201  further determines the next state of phase controller  101  as a function of the previous state by utilizing latch  202  and line  210 . Next PCSM logic  201  may receive inputs from a hierarchical controller (not shown) via lines  208  and  209  as discussed in greater detail in U.S. patent application Ser. No. 10/679,786, entitled “SYSTEMS AND METHODS FOR SYNCHRONIZING MULTIPLE VARIABLE FREQUENCY CLOCK GENERATORS.” 
     Phase controller  201  provides multiple output lines (shown as lines  204  and  205 ). Line  205  provides an output line from next PCSM logic  201 . When next PCSM logic  201  determines that a frequency adjustment is appropriate in response to the various input signals, PCSM logic  201  causes a suitable signal to be communicated via line  205  to variable clock generator  103 . In this representative embodiment, PCSM logic  201  communicates a signal to variable clock generator  103  to adjust the period of its clock by −1 tick, +1 tick, and +2 ticks, where a tick is a suitable fraction (e.g., 1/64) of the period of the input clock from master PLL  105 . PC output  203  determines when it is appropriate to signal a frequency change via line  204  instituted by phase controller  101  to other phase controllers  101  in other zones  104 . For example, if phase controller  101  made a frequency adjustment to synchronize to a prior frequency adjustment that occurred in another zone  104 , communication of the frequency adjustment in the current zone  104  is not necessary. 
       FIG. 3  depicts process flow  300  for operating phase controller  101  according to one representative embodiment. In step  301 , a voltage transient is detected by regional voltage detector  102 . In step  302 , an adjust signal is communicated from the regional voltage detector to phase controller  101 . In step  303 , phase controller  101  communicates an adjust signal to variable clock generator  103 . In step  304 , a logical comparison is made to determine whether an adjust signal was received from another phase controller. If so, the process flow proceeds to step  306 , where no communication of the local clock adjustment occurs. Specifically, because a clock adjustment has already occurred in another zone  104  and that adjustment has been communicated to cause similar adjustments in other zones  104 , it is not necessary for the zone  104  performing the clock adjustment in response to voltage transients to communicate its clock adjustment. If the logical comparison of step  304  is false, the process flow proceeds to step  305  where the clock adjustment is communicated to other phase controllers  101 . 
       FIG. 4  depicts process flow  400  for operating phase controller  101  according to one representative embodiment. In step  401 , communication of a frequency adjustment that occurred in another zone is received. In step  402 , a logical determination is made to determine whether a frequency adjustment was performed in the current zone in the previous cycle in response to a local voltage transient. If the logical determination of step  402  is true, the process flow proceeds to step  403  where no frequency adjustment is made, because the frequency of the local clock already equals the frequency of the clock associated with the communicated adjustment. If the logical determination of step  402  is false, the process flow proceeds to step  404 . In step  404 , the frequency of the local clock is varied by changing the period of the local clock by +2 ticks of the period of the clock of master PLL  105 . The adjustment by +2 ticks facilitates aligning the phase of the local clocks. Specifically, if an adjustment was made to only synchronize the frequency of the local clock to the frequency of the clock associated with the initial adjustment, the two clocks would be out-of-phase due to the one cycle of communication latency between the respective zones  104 . After multiple clock adjustments, the clock skew between zones  104  could cause CPU  100  to malfunction. However, by adjusting by +2 ticks, the local clock temporarily slows relative to the clock associated with the original adjustment thereby causing the phase misalignment to be eliminated. In step  405 , another adjustment (i.e., by −1 tick) is made to cause the frequency of the local clock to equal the frequency of the clock associated with the communicated frequency adjustment. 
     Process flow  300  of  FIG. 3  and process flow  400  of  FIG. 4  have been depicted as a linear set of operations for the convenience of the reader. However, it shall be appreciated that representative embodiments are not so limited. Some representative embodiments may implement suitable logic to perform selected operations within process flow  300  and/or process flow  400  concurrently. Moreover, selected operations may be performed by a single logical element, e.g., by utilizing a suitable truth table logic implementation for a state machine design and/or the like. 
     The invention may comprise a method of operating a CPU that includes multiple clock zones as illustrated in  FIG. 5 . The method includes generating at least one power signal that is indicative of a power supply voltage within each of the clock zones as shown at  501 . The method further includes adjusting a frequency of a first local clock in a first clock zone of the clock zones in response to a respective power signal from the first clock zone as shown at  503 ; communicating the first clock zone frequency adjustment to a second clock zone (shown at  505 ); and adjusting a frequency of a second local clock in the second clock zone in response to the first clock zone frequency adjustment (shown at  507 ). 
     By managing clock adjustments as discussed above, some representative embodiments may provide any of a number of advantages. In a relatively large CPU, some representative embodiments enable the response time to voltage transients to be reduced by utilizing a plurality of clock zones with respective phase controllers. Specifically, signals indicative of voltage transients may be routed relatively quickly to phase controllers. Similarly, the routing of the clocks varied under the control of the phase controllers to clock-consuming circuits in the CPU may occur relatively quickly. Therefore, the loop response time associated with the clocks is improved. By improving the loop response time, relatively small guard bands for timing issues are required and CPU performance is maximized. Likewise, worst case assumptions for analyzing timing constraints in CPU design are lessened. Moreover, some representative embodiments manage clock adjustments in a manner that maintains clock skew between zones within acceptable levels.

Technology Classification (CPC): 8