Patent Abstract:
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a differential input signal, a first power supply and a ground. The output signal may have a rail-to-rail voltage with a magnitude between the first power supply and the ground. The first circuit may also be configured to source an intermediate differential signal in response to the differential input signal, the first power supply and ground. The second circuit may be configured to sink the differential intermediate signal in response to the differential input signal, the first power supply, ground and a second power supply. The second circuit may flatten the transconductance of the first circuit relative to a common mode voltage of the differential input signal.

Full Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to amplifier circuits generally and, more particularly, to a method and/or apparatus for implementing a low-voltage constant-gm rail-to-rail CMOS input stage with improved gain. 
       BACKGROUND OF THE INVENTION 
       [0002]    Conventional amplifier circuits often implement operational amplifiers. Supply voltages tend to decrease as process technology scales down. In low voltage applications, signal levels remain the same to obtain a targeted signal-to-noise ratio. Conventional input differential transistor pairs cannot satisfy stringent signal-to-noise specifications. Conventional approaches suffer from drawbacks such as low DC gain when input common mode is close to ground. 
         [0003]    It would be desirable to implement a low-voltage constant-gm rail-to-rail CMOS stage with improved gain. It would also be desirable to implement a low voltage constant-gm rail-to-rail CMOS input stage that may be used in analog and/or mixed signal applications. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a differential input signal, a first power supply and a ground. The output signal may have a rail-to-rail voltage with a magnitude between the first power supply and the ground. The first circuit may also be configured to source an intermediate differential signal in response to the differential input signal, the first power supply and ground. The second circuit may be configured to sink the differential intermediate signal in response to the differential input signal, the first power supply, ground and a second power supply. The second circuit may flatten the transconductance of the first circuit relative to a common mode voltage of the differential input signal. 
         [0005]    The objects, features and advantages of the present invention include providing an amplifier stage that may (i) provide an improvement in gain, (ii) reduce variations in gain, (iii) reduce harmonic distortion with higher gain, (iv) be implemented without additional design specifications and/or extra gain stages, (v) provide a low-voltage constant-gm rail-to-rail CMOS input stage with improved gain, and/or (vi) overcome DC gain issues. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
           [0007]      FIG. 1  is a block diagram of the present invention; 
           [0008]      FIG. 2  is a more detailed diagram of the present invention; 
           [0009]      FIG. 3  is a plot of the comparison of transconductance versus input common mode voltage; 
           [0010]      FIG. 4  is a plot of a comparison of gain variation versus input common mode; 
           [0011]      FIG. 5  is a conceptual diagram of an N-type differential input stage; 
           [0012]      FIG. 6  is a conceptual diagram of a P-type differential input stage; 
           [0013]      FIG. 7  is a conceptual diagram of the current flow when an input voltage level is close to ground; and 
           [0014]      FIG. 8  is a conceptual diagram when an input voltage level is close to mid level and/or close to a supply level. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0015]    Referring to  FIG. 1 , a block diagram of a circuit  100  is shown in accordance with an embodiment of the present invention. The circuit  100  generally comprises a block (or circuit)  102  and a block (or circuit)  104 . The circuit  102  may provide a low voltage constant-gm rail-to-rail CMOS input stage that may be used in analog and/or mixed signal applications. The circuit  104  may be implemented as a compensation circuit. The circuit  100  may improve the gain of an input stage across a rail-to rail input common mode. The circuit  100  may also provide a higher gain and/or may improve harmonic distortion of an operational-amplifier. The circuit  100  may incorporate a general purpose low-voltage constant-gm rail-to-rail input stage  102  that may provide a solution to improve the gain across rail-to-rail input common mode. The circuit  100  may provide a gain enhancement. 
         [0016]    The circuit  102  may receive a signal (e.g., VDDA), a signal (e.g., VI+), a signal (e.g., VI−), and a signal (e.g., VSSA). The circuit  102  may present a current (e.g., IA), a current (e.g., IB), a signal (e.g., V 0 ), and a signal (e.g., V 0 B). The circuit  104  may receive the signal VDDA, a signal (e.g., VDDA/2), the signal VI+, the signal VI−, the current LA, the current IB and the signal VSSA. The signal VDDA may be a supply voltage. The signal VDDA/2 may have a magnitude around one half of the supply voltage VDDA. The signal VSSA may be ground voltage. 
         [0017]    Referring to  FIG. 2 , a more detailed diagram of the circuit  100  is shown. The circuit  100  may overcome limitations on the input common mode voltage VCMR that may commonly be associated with a typical n-channel or p-channel differential input stage. The signal VI (e.g., either VI+ or VI−) may be presented to the input terminal of each amplifier stage. The signal VI may have a voltage range when a particular amplifier becomes operation. The voltage range of the signal VI may be referred to as a voltage common mode range (VCMR). The signals VI+/VI− may represent a positive/negative terminal of each amplifier stage. Two floating voltage sources (e.g., VI++/VI−−) may be implemented by two similar source followers (e.g., S 1 -S 2  and/or S 3 -S 4 ) connected in front of the input terminals of one of the differential pairs ( 1 NS- 2 NS). The source followers S 1 -S 2  and/or S 3 -S 4  may provide a positive voltage shift on the signal VGS to the signal VCMR applied to the differential pair  1 NS- 2 NS. To ensure rail-to-rail operation, the voltage shift from the signal VCMR should normally keep the corresponding input pair active when the other differential pair (e.g.,  1 N- 2 N) is inactive (e.g., when the signal VCMR is close to ground). 
         [0018]    The circuit  102  generally comprises a section  110 , a section  112 , a section  114 , a section  115 , a section  116 , a section  118 , and a section  120 . The section  112  may include a transistor A 1 S and a transistor A 2 S. The section  112  may be active when a common mode is at a mid level. The section  114  may include a transistor S 1  and a transistor S 2 . The section  115  may include a transistor  1 N and a transistor  2 N. The transistor pair  1 N and  2 N may be active when an input mode is close to a level of the signal VDDA. The section  115  may also include the transistor  1 NS and the transistor  2 NS. The transistor  1 NS and  2 NS may be active when a common mode is close to a level of the signal SSA. The section  120  may include a transistor S 3  and a transistor S 4 . 
         [0019]    The transistor S 1  and a transistor S 2  may be implemented as PMOS transistors. Similarly, the transistor S 3  and the transistor S 4  may be implemented as PMOS transistors. The transistor pair S 1  and S 2  and the transistor pair S 3  and S 4  may be implemented as level shifters configured to shift an input level when the circuit  100  is active. 
         [0020]    For levels of the signal VCMR close to ground, the current source transistors (e.g., BA and BN) and hence, the transistor pairs A 1 -A 2  and  1 N- 2 N, are normally cut-off. Then, the small- and large-signal behaviors of the rail-to-rail input stage result only by the contribution of the differential pair  1 NS- 2 NS, which is biased with current equal to the current IC (the ensuing transconductance will be referred to as g m0 ). In the middle voltage range, both input pairs ( 1 N- 2 N and  1 NS- 2 NS) are active. However, a bias current equal to the current IC is provided to an input pair A 1 S-A 2 S, which cancels out the limiting current and transconductance contribution of one of the differential pairs of the input stage. Finally, for values of the signal VCMR close to the supply VDDA, the bias current IBS of the input level shifters becomes zero and, consequently, the input pairs A 1 S-A 2 S and  1 NS- 2 NS provide no contribution to the output. Thus, the only differential pair active is  1 N- 2 N, and the small and large signal behaviors of the stage are the same as in the above considered operating regions. The following TABLE 1 shows the current flowing in each of the differential pairs and through the load devices M 5 /M 6  when the circuit  104  is not present: 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 Current conducting 
                   
               
               
                   
                 Diff Pairs 
                 Current through 
               
             
          
           
               
                 VCMR Range 
                 1N-2N 
                 1NS-2NS 
                 A1S-A2S 
                 M5/M6(I L ) 
               
               
                   
               
               
                 Close to Ground 
                 0 
                 I C /2 
                 0 
                 I B -I C /2 
               
               
                 (VSSA) 
               
               
                 Mid-level 
                 I C /2 
                 I C /2 
                 I C /2 
                 I B -3I C /2 
               
               
                 Close to Supply 
                 I C /2 
                 I C /2 
                 I C /2 
                 I B -3I C /2 
               
               
                 (VDDA) 
               
               
                   
               
             
          
         
       
     
         [0021]    Open loop gain of the amplifier in  FIG. 2 , 
         [0000]      Av≈g m0 [g m4 r 04 r 02 ∥g m6 r 06 r 08 ]
 
         [0000]    Where, g mx  and r 0x  are the transconductance and output impedance of transistor MX in  FIG. 2  respectively. 
         [0022]    For simplicity assume, 
         [0000]      g m4 ≈g m6  
 
         [0000]      r 04 ≈r 06  
 
         [0000]      r 02 ≈r 08  
 
         [0000]      Therefore, 
         [0000]      Av≈g m0 [g m4 r 04 r 02 ]/2
 
         [0000]    Across rail-to-rail g m0  is nearly constant, therefore, 
         [0000]      Avαg m0 [g m4 r 04 r 02 ]/2
 
         [0000]      g m4 α√I L  
 
         [0000]      r 04 ,r 02 α1/I L  
 
         [0000]      Therefore, Avα√I L ×1/I L ×1/I L  
 
         [0000]      AvαI L   −3/2  
 
         [0000]      ΔAvα(ΔI L ) −3/2  [when g m0  is constant]
 
         [0023]    Therefore, when transconductance of the input stage  102  is constant, the current through the transistors M 5 /M 6  should also remain constant across rail-to-rail in order to have a constant gain Av. 
         [0024]    When the signal VCMR is close to the ground voltage VSSA, the transistors D 1 /D 2  are cut-off and no current flows through the transistor MD 3 . All of the current IC flows through the transistor MD 5  and the current IC flows through each node A/B. This compensates for the cut-off of the transistors  1 N/ 2 N and the transistors A 1 S/A 2 S. As a result, the current IL is maintained as I L =I B −3I C /2 when the signal VCMR is close to ground. 
         [0025]    When the signal VCMR is in the middle voltage or close to VDDA range then D 1 /D 2  are active and I C  flows through MD 3  and no current flows D 5 /D 6 /D 7 /D 8 . As a result no current flows through A/B and, consequently, I L =I B −3I C /2 is maintained at this input common mode range. The following TABLE 2 shows the current flowing in each differential pair and through the load devices M 5 /M 6 . 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
             
             
               
                   
                   
               
               
                   
                 Current conducting 
                   
               
               
                   
                 Diff Pairs 
                 Current through 
               
             
          
           
               
                 VCMR Range 
                 1N-2N 
                 1NS-2NS 
                 A1S-A2S 
                 M5/M6(I L ) 
               
               
                   
               
               
                 Close to Ground 
                 I C /2 
                 I C /2 
                 I C /2 
                 I B -3I C /2 
               
               
                 (VSSA) 
               
               
                 Mid-level 
                 I C /2 
                 I C /2 
                 I C /2 
                 I B -3I C /2 
               
               
                 Close to Supply 
                 I C /2 
                 I C /2 
                 I C /2 
                 I B -3I C /2 
               
               
                 (VDDA) 
               
               
                   
               
             
          
         
       
     
         [0026]    Referring to  FIG. 3 , a plot illustrating a comparison of the gm with respect to the signal VCMR in the case of the circuit  100  versus a conventional circuit is shown.  FIG. 3  shows the variation of transconductance GM with respect to the signal VCMR as being nearly the same. 
         [0027]    Referring to  FIG. 4 , a plot illustrating a comparison of DC gain with respect to the signal VCMR of the circuit  100  versus a conventional circuit. An example of minimum gain shown is 40 dB. The variation of gain of 40-45 dB illustrates an improvement from the gain of 28-43 dB without the circuit  104 . 
         [0028]    Referring to  FIG. 5 , a diagram illustrating an example of an N-type differential input stage used in the circuit  100  is shown. A voltage VCMR may be equal to VDDA−Vgs(MN)−Vdsat(IB). 
         [0029]    Referring to  FIG. 6 , a P-type differential input stage is shown. The circuit of  FIG. 6  illustrates the voltage VCMR as being equal to VDDA−Vgs(MP)−VDSAT(IB). 
         [0030]    Referring to  FIG. 7 , a conceptual diagram of the circuit  100  is shown when an input voltage is close to ground. In general, a current Il may be equal to a current Ib−3×Ic/2. 
         [0031]    Referring to  FIG. 8 , a diagram of the circuit  100  is shown when an input voltage is close to mid level or close to a supply voltage. In a current IL may be equal to a current Ib−3×Ic/2. In this case, the circuit  104  may be reduced to limit the current IC added to the overall current. 
         [0032]    The terms “may” and “generally” when used herein in conjunction with “is(are)” and verbs are meant to communicate the intention that the description is exemplary and believed to be broad enough to encompass both the specific examples presented in the disclosure as well as alternative examples that could be derived based on the disclosure. The terms “may” and “generally” as used herein should not be construed to necessarily imply the desirability or possibility of omitting a corresponding element. 
         [0033]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.

Technology Classification (CPC): 7