Patent Abstract:
Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.

Full Description:
FIELD OF THE INVENTION 
     This invention relates generally to tristate circuitry. 
     BACKGROUND 
     Tristate driver circuits are used to conditionally drive a signal onto a wire that is shared by multiple resources. Tristate driver circuits are sometimes used in conjunction with multiplexer circuits. The multiplexer may provide a selected input to the tristate driver which in turn drives the signal onto the shared resource wire. Multiplexers can be built in various ways. A multiplexer may be constructed from pass transistors. A multiplexer may also be constructed from a plurality of internal tristate circuits. A multiplexer may be a constructed from smaller multiplexer circuits which form stages of a larger multiplexer. 
       FIGS. 1A and 1B  illustrate two different prior art tristate circuits.  FIG. 1A  illustrates a known inverting tristate driver  101 . Circuit  101  is constructed from two stacked PMOS transistors,  11 P and  12 P and two stacked NMOS transistors  11 N and  12 N coupled as shown. The circuit is enabled as follows: A high enable signal at input en and a corresponding low negative enable signal at input n-en turn on, respectively, transistor  12 N and transistor  11 P which allows the signal at IN 1 A to drive an inverted signal at output OUT 1 A through transistors  12 P and  11 N. The opposite signals at input en and input n-en would turn off, respectively, transistor  12 N and transistor  11 P which in turn would prevent an input signal at input IN 1 A from driving a signal at output OUT 1 A. 
       FIG. 1B  illustrates a known non-inverting tristate driver  102 . Tristate driver  102  includes PMOS transistors  13 P,  14 P,  15 P, and  16 P and NMOS transistors  13 N,  14 N,  15 N, and  16 N. Circuit  102  is enabled as follows: A high enable signal at input en turns on transistor  13 N and turns off transistor  14 P and a low negative enable signal at input n-en turns off transistor  15 N and turns on transistor  15 P which allows the signal at IN 1 B to drive a non-inverted signal at output OUT 1 B through transistors  13 P,  14 N,  16 P, and  16 N. The opposite signal (i.e., a low) at enable input en would turn off transistor  13 N and turn on transistor  14 P and the opposite signal (i.e. a high) at negative enable input n-en would turn on transistor  15 N and turn off transistor  15 P which will prevent a signal at input IN 1 B from driving a signal at output OUT 1 B. 
     SUMMARY 
     The transistor arrangement shown in  FIG. 1A  requires that the output node be charged and discharged through two series transistors. When a tristate driver such as inverting tristate driver  101  is used to drive a signal on a shared resource wire, this arrangement requires use of relatively larger transistors (roughly twice a large) for a given drive strength than would be required for a normal two-transistor CMOS inverter at the output (in which charging and discharging of the output node occurs through a single transistor). In view of the significant output load at outputs to some shared resource wires, the required drive strength, and thus the corresponding transistor size difference required using the  FIG. 1A  arrangement at an output, can be significant. Non-inverting tristate driver  102  shown in  FIG. 1B , which just has a complimentary CMOS pair including  16 P and  16 N driving the output at OUT 1 B, allows use of relatively smaller drive transistors at that output. However, in this circuit, on currents for charging or discharging the gates of the output drive transistors (Ipon turns on transistor  16 P and Inon turns on transistor  16 N) both have to go through two transistors (in the case of Ipon, transistors  13 N and  14 N and in the case of Ion, transistors  13 P and  13 N) whereas the corresponding off currents for these transistors (Ipoff turns of transistor  16 P and Inoff turns off transistor  13 N) only have to go through one transistor (in the case of Ipoff, transistor  13 P and in the case of Inoff, transistor  14 N). This causes the transistors  16 P and  16 N to turn on more slowly than they turn off. Since  16 P is turning on when  16 N is turning off and vice versa, this can cause transitions in output signal wave forms to have longer rise/fall times than a simple inverter. Also, using a circuit such as circuit  102  of  FIG. 1B  to build all the input circuits of a tristate multiplexer requires  8 N transistors where “N” is the number of selectable inputs. 
     One embodiment of the present invention provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. In some embodiments, at least some of the selectively enabled input circuits comprise inverting tristate circuits including stacked PMOS and stacked NMOS transistors. In some embodiments, the output circuit comprises a two-transistor inverting CMOS stage such that an output node is charged and discharged through one transistor (e.g., charged through a PMOS transistor and discharged through an NMOS transistor). In one embodiment a gate of an output PMOS transistor is connected to a drain of a PMOS transistor in each of the plurality of input circuits and a gate of an output NMOS transistor is connected to a drain of an NMOS transistor in each of the plurality of input circuits. In another embodiment, a gate of an output PMOS transistor is connected to a drain of an NMOS transistor in each of the plurality of input circuits and a gate of an output NMOS transistor is connected to a drain of a PMOS transistor in each of the plurality of input circuits. 
     These and other embodiments are described more fully below. For purposes of illustration only, several aspects of particular embodiments of the invention are described by reference to the following figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a prior art inverting tristate driver. 
         FIG. 1B  illustrates a prior art non-inverting tristate driver. 
         FIG. 2  illustrates an exemplary tristate multiplexer consistent with one embodiment of the present invention, 
         FIG. 3  illustrates an exemplary tristate multiplexer consistent with another embodiment of the present invention. 
         FIG. 4  illustrates an exemplary data processing system including a field programmable gate array (“FPGA”) that includes exemplary selection circuits in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is presented to enable any person skilled iii the art to make and use the invention, and is provided in the context of particular applications and their requirements. Various modifications to the exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
       FIG. 2  illustrates a first embodiment of the present invention. Tristate multiplexer circuit  2000  comprises selectable input circuits  200 ,  201 , and  202 , output enable circuit  203 , and output drive circuit  204 . Selectable input circuits  200 ,  201 , and  202  each include stacked PMOS transistors and stacked NMOS transistors as follows: Circuit  200  includes PMOS transistors P 21  and P 22  and NMOS transistors N 21  and N 22 ; circuit  201  includes PMOS transistors P 23  and P 24  and NMOS transistors N 23  and N 24 ; and circuit  202  includes PMOS transistors P 25  and P 26  and NMOS transistors N 25  and N 26 . Enable circuit  203  comprises PMOS transistors P 27  and P 28  and NMOS transistors N 27  and N 28 . Output circuit  204  comprises a CMOS pair including PMOS transistor P 29  and NMOS transistor N 29 . 
     Tristate multiplexer  2000  has selectable inputs in 0 , in 1 , and in 2  corresponding to input circuits  200 ,  201 , and  202 . Each selectable input circuit has enable and corresponding negative enable inputs. When input en 0  is high (so that transistor N 22  is on and input n-en 0  is low (so that transistor P 21  is on), then circuit  200  is enabled and a signal at input in 0  is selected to drive output at output OUT 2000 . Similarly, when input en 1  is high (so that transistor N 24  is on) and input n-en 1  is low (so that transistor P 23  is on), then circuit  201  is enabled and a signal at input in 1  is selected to drive output at output OUT 2000 . When input en 2  is high (so that transistor N 26  is on) and input n-en 2  is low (so that transistor P 25  is on), then circuit  200  is enabled and a signal at input in 2  is selected to drive output at output OUT 2000 . 
     The transistors of output enable circuit  203  are coupled to output circuit  204  and to each of selectable input circuits  200 ,  201 , and  202  in a manner such that when signal en is high (so that transistor N 27  is on and transistor P 27  is off) and signal n-en is low (so that transistor N 28  is off and transistor P 28  is on), switching currents for switching on and off output drive transistors P 29  and N 29  flow through transistors of a selected input circuit. For example, if output enable circuit  203  is enabled as described above and selectable input circuit  201  is also enabled, a signal at input in 1  drives output at output OUT 2000  through transistors P 29  and N 29  and the switching currents for those output transistor currents flow through selected input circuit  201  as follows: The discharge current for turning on transistor P 29  flows through transistor N 27  of enable circuit  203  and through transistors N 23  and N 24  of input circuit  201 . The discharge current for turning off transistor N 29  flows through transistors N 23  and N 24  of input circuit  201 . The charging current for turning on transistor N 29  flows through transistor P 28  of enable circuit  203  and through transistors P 23  and P 24  of input circuit  201 . The charging current for turning off transistor P 29  flows through transistors P 23  and P 24  of input circuit  201 . 
     As those skilled in the art will appreciate, operation occurs in a comparable fashion if another of the inputs is selected. In each case, discharge current for turning on output transistor P 29  flows through transistor N 27  of output enable circuit  203  and charging current for turning on transistor N 29  flows through transistor P 28  of output enable circuit  203 . If input in 0  is selected, then discharge currents for turning on output transistor P 29  and turning off output transistor N 29  flow through transistors N 21  and N 22  of input circuit  200 . In that case, charging currents for turning on output transistor N 29  and turning off output transistor P 29  flow through transistors P 21  and P 22  of input circuit  200 . If input in 2  is selected, then discharge currents for turning on output transistor P 29  and turning off output transistor N 29  flow through transistors N 25  and N 26  of input circuit  202 . In that case, charging currents for turning on output transistor N 29  and turning off output transistor P 29  flow through transistors P 25  and P 26  of input circuit  202 . 
     In this sense, the illustrated embodiment, when enabled by enable circuit  203 , “merges” tristate input and tristate output circuitry to form a tristate multiplexer. In other words, transistors of a tristate input circuit used tier selectable input are also used as pathways for the charging and discharging current of the tristate output driver circuit transistor gate voltages. The illustrated arrangement can be applied to a multiplexer with any number of inputs. It can also be applied as just part of a larger multiplexer that uses different types of selectable input circuitry. In other words, although in the illustrated embodiment, all of the selectable input circuits are constructed from inverting tristate circuit structures (modified to be coupled through an output enable circuit), in alternative embodiments, some multiplexer input circuits may be constructed differently. Also, some inputs may be higher speed inputs than others, passing through few stages before driving output circuitry. 
       FIG. 3  illustrates an alternative embodiment of the present invention. Tristate multiplexer  3000  includes input circuits  300 ,  301 , and  302 , output enable circuit  303  and output circuit  304 . The difference between circuit  3000  of  FIG. 3  and circuit  2000  of  FIG. 2  is that the circuit of  FIG. 3  implements a “twisted” connection between input circuits and output PMOS and NMOS output drive transistors as will be further explained below. 
     Selectable input circuits  300 ,  301 , and  302  each include stacked PMOS transistors and stacked NMOS transistors as follows: Circuit  300  includes PMOS transistors P 31  and P 32  and NMOS transistors N 31  and N 32 ; circuit  301  includes PMOS transistors P 33  and P 34  and NMOS transistors N 33  and N 34 ; and circuit  302  includes PMOS transistors P 35  and P 36  and NMOS transistors N 35  and N 36 . Enable circuit  303  comprises PMOS transistors P 37  and P 38  and NMOS transistors N 37  and N 38 . Output circuit  304  comprises a CMOS pair including PMOS transistor P 39  and NMOS transistor N 39 . 
     Tristate multiplexer  3000  has selectable inputs in 0 ′, in 1 ′, and in 2 ′ corresponding to input circuits  300 ,  301 , and  302 . Each selectable input circuit has enable and corresponding negative enable inputs (en 0 ′ and n-en 0 ′ for input circuit  300 , en 1 ′ and n-en 1 ′ for input circuit  301 , and en 2 ′ and n-en 2 ″ for input circuit  302 ). These operate to enable or non-enable the selectable input circuits in the same manner already described in the context of the embodiment of  FIG. 2  and so will not be further described herein. 
     The transistors of output enable circuit  303  are coupled to output circuit  304  and to each of selectable input circuits  300 ,  301 , and  302  in a manner such that when signal en′ is high (so that transistor N 37  is on and transistor P 37  is off) and signal n-en′ is low (so that transistor N 38  is off and transistor P 38  is on), switching currents for switching on and off output drive transistors P 39  and N 39  flow through transistors of a selected input circuit. For example, if output enable circuit  303  is enabled as described above and selectable input circuit  301  is also enabled, a signal at input in 1 ′ drives output at output OUT 3000  through transistors P 39  and N 39  and the switching currents for those output transistor currents flow through selected input circuit  301  as follows: The discharge current for turning on transistor P 39  flows through transistors N 33  and N 34  of input circuit  301 . The discharge current for turning off transistor N 39  flows through transistor N 37  of output enable circuit  303  and through transistors N 33  and N 34  of input circuit  301 . The charging current for turning on transistor N 39  flows through transistors P 33  and P 34  of input circuit  301 . The charging current for turning off transistor P 39  flows through transistor P 38  of output enable circuit  303  and through transistors P 33  and P 34  of input circuit  301 . As those skilled in the art will appreciate, operation occurs in a comparable fashion if another of the inputs is selected: On currents will flow through either PMOS transistors (if charging to turn on output transistor N 39 ) or NMOS transistors (if discharging to turn on output transistor P 39 ) of the corresponding selected input circuit. Off currents will similarly flow through PMOS (if charging to turn off P 39 ) or NMOS (if discharging to turn off N 39 ) transistors of the selected input circuit (i.e., for input circuit  300 , P 31  and P 32  or N 31  and N 32  and for input circuit  302 , P 35  and P 36  or N 35  and N 36 ). Off currents will also flow through a transistor of output enable circuit  303 , i.e., through P 38  if a charging off current or through N 37  if a discharging off current. 
     Thus a difference between the embodiments of  FIG. 2  and  FIG. 3  is the following: In multiplexer  2000  of  FIG. 2 , the on switching currents for driving the output transistor gates travel through three transistors while the off currents travel through two transistors. By contrast, in multiplexer  3000  of  FIG. 3 , the on switching currents only travel through two transistors while the off currents travel through three transistors. The embodiment of  FIG. 3  thus may provide somewhat less signal delay than the embodiment of  FIG. 2 , however it also has the possibility of greater short circuit current at the output since one transistor may turn on before its complement turns off. 
     Tristate multiplexer circuitry embodying the principles illustrated by the circuitry of  FIG. 2  and/or  FIG. 3  may be implemented as part of any IC. A specific example of an IC is a field programmable gate array (“FPGA”). FPGAs (also referred to as programmable logic devices (“PLDs”), complex PLDs, programmable array logic, programmable logic arrays, field PLAs, erasable PLDs, electrically erasable PLDs, logic cell arrays, or by other names) provide the advantages of fixed ICs with the flexibility of custom ICs. FPGAs have configuration elements (i.e., programmable elements) that may be programmed or reprogrammed. Placing new data into the configuration elements programs or reprograms the FPGA&#39;s logic functions and associated routing pathways. Such configuration may be accomplished via data stored in programmable elements on the IC. Programmable elements may include dynamic or static RAM, flip-flops, electronically erasable programmable read-only memory (EEPROM) cells, flash, fuse, anti-fuse programmable connections, or other memory elements. Configuration may also be accomplished via one or more externally generated signals received by the IC during operation of the IC. Data represented by such signals may or may not be stored on the IC during operation of the IC. Configuration may also be accomplished via mask programming during fabrication of the IC. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. 
       FIG. 4  illustrates an exemplary data processing system  4000  including an FPGA  4010 . FPGA  4010  includes several selection circuits such as selection circuit  4001  in accordance with an embodiment of the present invention. 
     Data processing system  4000  may include one or more of the following additional components: processor  4040 , memory  4050 , input/output (I/O) circuitry  4020 , and peripheral devices  4030  and/or other components. These components are coupled together by system bus  4065  and are populated on circuit board  4060  which is contained in end-user system  4070 . A data processing system such as system  4000  may include a single end-user system such as end-user system  4070  or may include a plurality of systems working together as a data processing system. 
     System  4000  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic in system design is desirable. FPGA  4010  can be used to perform a variety of different logic functions. For example, FPGA  4010  can be configured as a processor or controller that works in cooperation with processor  4040  (or, in alternative embodiments, an FPGA might itself act as the sole system processor). FPGA  4010  may also be used as an arbiter for arbitrating access to shared resources in system  4000 . In yet another example, FPGA  4010  can be configured as an interface between processor  4040  and one of the other components in system  4000 . It should be noted that system  4000  is only exemplary. 
     While the present invention has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications and adaptations may be made based on the present disclosure, and are intended to be within the scope of the present invention. While the invention has been described in connection with what are presently considered to be the most practical and preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments but only by the following claims.

Technology Classification (CPC): 7