Patent Abstract:
A charge transfer circuit of a liquid crystal display includes at least one inductive element connectable between first and second common terminals, to a first and to a second groups of lines of the display, respectively.

Full Description:
PRIORITY CLAIM 
     The present application claims the benefit of French patent application Ser. No. 05/54130, filed Dec. 29, 2005, which application is incorporated herein by reference in its entirety. 
     1. Technical Field 
     Embodiments of the present invention generally relate to liquid crystal display screens (LCD) and, more specifically, to circuits for controlling such screens. 
     2. Discussion of the Related Art 
       FIG. 1  partially and very schematically shows a pixel  1  of a monochrome LCD screen or a sub-pixel of a color LCD screen. Electrically, each pixel  1  is formed of a control switch M (typically, a MOS transistor) and of a capacitor C 1 , as a memory cell. A first conduction terminal of switch M is connected to a column conductor Col, common to all the switches of the display panel column. The other conduction terminal is connected to a first electrode of capacitor C 1  of the pixel, having its second electrode connected to ground, the dielectric of capacitor C 1  being formed of the liquid crystal used for the display. The gates of switches M are connected, in rows, to line conductors Row. The presence of switch M generates a capacitive element C between its gate and its source, and thus between line Row and the first electrode of capacitance C 1  of cell  1 . Columns conductors Col are controlled by a column driver circuit  2  (CDRIVER) generally setting the luminance reference values while row conductors Row are controlled in scan mode by a row driver circuit  3  (GDRIVER). 
     For a color screen, each cell  1  forms a sub-pixel and the color is provided by a corresponding chromatic filter (RGB) arranged in front of each sub-pixel. 
       FIG. 2  partially and schematically shows the equivalent electric diagram of a liquid crystal display panel  10  and of its row control circuit In the example of  FIG. 2 , only two columns Col i  and Col i+1  have been shown. Similarly, only five rows Row 1 , Row 2 , Row 3 , Row n-1 , and Row n  have been shown. The screen integration on a substrate generally made of glass is no longer limited to the cells but also involves the row control circuits. These circuits comprise, for each row, an RS-type flip-flop B 1 , B 2 , B 3  . . . , Bn- 1 , and Bn, the direct Q output of which is used to control a switch K 1 , K 2 , K 3 , Kn- 1 , Kn placed on each row conductor to bring a supply voltage onto it. The S activation input of first flip-flop B 1  receives a scan start signal Start. The S activation input of flip-flop B 2  is connected to line Row 1 , downstream of switch K 1  with respect to the supply source. The S activation input of flip-flop B 3  is connected to line Row 2 , downstream of switch K 2 , etc. until the S activation input of the last flip-flop Bn connected to line Row n-1 . The R reset inputs of the flip-flops are respectively connected to the conductor of the row of next rank, downstream of the corresponding switch K, until the R input of the last flip-flop Bn which is looped back on row Row 1 . 
     The line powering is generally performed by a line scanning. The rows of odd rank Row 1 , Row 3 , . . . , Row n-1  are interconnected upstream of switches K 1 , K 3 , . . . Kn- 1  to a terminal  32  while the lines of even rank Row 2 , . . . Row n  are, upstream of their respective switches, connected to a terminal  33 . Terminals  32  and  33  are respectively connected to the junction points of pairs of switches Q 1  and Q 2 , respectively Q 3  and Q 4 , series-connected between terminals of application of respectively high and low turn-on and turn-off voltages V ON  and V OFF . 
     The scanning is performed by lines, starting, for example, with an odd line by turning on switches Q 1  and Q 4  and by turning off switches Q 2  and Q 3  for both supplying this odd line and forcing the turning-off of the even line of next rank. Signal Start applied on the S activation input of first flip-flop B 1  enables automatic row scanning. The addressing of an even row is performed symmetrically by turning off switches Q 1  and Q 4  and by turning on switches Q 2  and Q 3 . The switching of switches Q 1  to Q 4  is thus performed at the rate of the line scanning under control of a circuit  5  (CTRL). 
     A problem is that the series associations of elements C and C 1  of all columns of a row are in parallel and have a charge opposite to that of the next row. 
     To avoid too high a power loss, a charge recovery stage is generally provided, thus enabling, for each column, using the power stored in the pixels to be turned off of the row which has just been addressed to help the turning-on of the pixels of the next line. For this purpose, terminals  32  and  33  are generally connected by an assembly of two diodes in ant-parallel D 1  and D 2 , each in series with a resistor R 1  and R 2  and a switch S 1  and S 2 . 
       FIG. 3  shows an equivalent simplified electric diagram of  FIG. 2  enabling better illustrating the operation of the H bridge formed of switches Q 1 , Q 2 , Q 3 , and Q 4  and the charge transfer circuits formed of switches S 1 , S 2  and of their diodes and resistors in series. The assembly of the cells of an odd line of the panel has been symbolized by a block  35 , a switch Mo, and an equivalent capacitance 
             Co   (         1   Co     =     ∑     (       1   C     +     1     C   ⁢           ⁢   1         )         ,           
the sum comprising all the cells in the odd row). The assembly of the cells of the even rows has been symbolized by a block  36 , a switch Me and an equivalent capacitance
 
             Ce   (         1   Ce     =     ∑     (       1   C     +     1     C   ⁢           ⁢   1         )         ,           
the sum comprising all the cells in the even row). For simplification, the flip-flops used for the scanning have not been illustrated in  FIG. 3 . These flip-flops are in practice interposed between each terminal  32  and  33  and the odd and even lines of blocks  35  and  36 .
 
     For the turning-on of the pixels of the first odd line, switches Q 1  and Q 4  are turned on, which causes the application of a voltage V ON  on terminal  32  and V OFF  on terminal  33 . A current can then flow to charge the capacitances of pixels of this first line. At the end of this addressing period, transistors Q 1  and Q 4  are turned off and switch S 1  is turned on for a so-called power recovery or transfer phase, which enables precharging the next line (even) by the discharge of the odd line which has just been addressed. This phase places the first odd and even lines in an intermediary equilibrium voltage. Then, switches Q 2  and Q 3  are turned on to bring the voltage of the even line to level V ON  and end the discharge of the first odd line to level V OFF . At the end of the turning-on of the even line, switches Q 2  and Q 3  are turned off and switch S 2  is turned on to enable precharge of the next odd line and thus resume the operation by turning-on of switches Q 1  and Q 4 . 
     With known LCD screens or panels, losses remain high even with the charge transfer stages. For example, for a screen having its assemblies of even and odd lines respectively exhibiting equivalent 4.7-nF capacitances Ceq=Co=Ce, with a line scanning at a 166-kHz frequency f with a 35-volt turn-on voltage V ON  and a −25-volt turn-off voltage V OFF , losses amount to approximately 1.4 watts (f*Ceq(V ON -V OFF ) 2 /2). 
     Furthermore, with known displays the control of the switches S 1  and S 2  of the charge recovery stages is generally complex, due to the floating voltages of the terminals of these switches. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention improve the control of flat screens, especially with liquid crystals, with a charge transfer stage to decrease the power losses of such screens. 
     The control of the switches of charge transfer stages may also be simplified. 
     One embodiment of the present invention provides a liquid crystal display charge transfer circuit including at least one inductive element connectable between a first and a second common terminal, respectively, to a first and to a second group of lines of the display. 
     According to an embodiment of the present invention, said terminals are connected to the respective junction points of switches connected, in pairs, in series between third and fourth terminals of application of high and low line supply voltages. 
     According to an embodiment of the present invention, the circuit comprises two switches respectively in parallel with a diode, these parallel associations being in series between said first and second terminals, and said inductive element being interposed between the two switches. 
     According to an embodiment of the present invention, each switch has a first conduction terminal connected to the inductive element and its control terminal connected to its second conduction terminal by a parallel association of a resistive element, of a capacitive element, and of a voltage-limiting element, the control terminal of each switch being further respectively connected to the midpoints of series associations of diodes connected between a fifth terminal of provision of a control current and said third terminal of application of the high line supply voltage. 
     According to an embodiment of the present invention, said control current is provided by a current source connected via a third switch to said fifth terminal. 
     According to an embodiment of the present invention, said capacitive element comprises the gate-source capacitance of a MOS transistor forming the corresponding switch. 
     Embodiments of the present invention also provide a circuit for controlling a liquid crystal display. 
     Embodiments of the present invention include a circuit for controlling a liquid crystal display and may also include such a control circuit in a flat liquid crystal display. 
     Embodiments of the present invention will be discussed in detail in the following non-limiting description of example embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1 , previously described, very schematically and partially shows a liquid crystal display to which embodiments of the present invention apply; 
         FIG. 2 , previously described, shows an equivalent electric diagram of a liquid crystal display and of a conventional line control circuit with a supply and charge transfer stage; 
         FIG. 3 , previously described, shows a simplified electric diagram of the supply and charge transfer circuit of  FIG. 2 ; 
         FIG. 4  very schematically and partially shows a power supply circuit of a liquid crystal display according to an embodiment of the present invention; 
         FIGS. 5A ,  5 B,  5 C,  5 D,  5 E,  5 F, and  5 G are examples of timing diagrams illustrating the operation of the circuit of  FIG. 4 ; 
         FIG. 6  shows an embodiment of a circuit for controlling the charge transfer switches of the circuit of  FIG. 4 ; and 
         FIG. 7  shows a variation of charge transfer circuit according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those control steps and elements which are necessary to the understanding of embodiments of the present invention have been shown in the drawings and will be described hereafter. In particular, the provision of the different luminance control signals brought by the column control circuits has not been detailed, since embodiments of the present invention involve no necessary modifications of these circuits. The same is true for the line scanning performed by a conventional circuit (for example, of the type described in relation with  FIG. 2 ). 
     A feature of an embodiment of the present invention is to use an inductive element in the charge transfer stage of the display. 
       FIG. 4  shows an embodiment of the present invention. This drawing shows the equivalent electric diagram of a liquid crystal display in a representation to be compared with that of previously-described  FIG. 3 . 
     The assembly of cells of a line of odd rank is symbolized by a block  35 , a switch Mo, and an equivalent capacitor Co. The assembly of cells of a line of even rank is symbolized by a block  36 , a switch Me, and an equivalent capacitance Ce. As previously described, the line conductors are connected via scan switches (not shown) to common points, respectively  32  for odd lines and  33  for even lines. For simplification, the scan circuit has not been illustrated in  FIG. 4 . Points  32  and  33  are connected to the junction points of switches Q 1  and Q 2  and switches Q 3  and Q 4 , respectively, between two terminals of application of respectively high and low supply voltages V ON  and V OFF . 
     According to this embodiment of the present invention, charge transfer stage  38  connecting terminals  32  and  33  to form, with switches Q 1  to Q 4 , an H bridge, comprises two switches S 1  and S 2  in series and between which an inductive element L is interposed, each switch being in parallel with diodes D 1 , D 2  having anodes connected to terminals  33 , and  32 , respectively. 
     An inductance L made of ferrite may be used to optimize the loss reduction. 
       FIGS. 5A ,  5 B,  5 C,  5 D,  5 E,  5 F, and  5 G are timing diagrams illustrating, in examples of shapes of control signals of switches Q 1  and Q 4 , of switch S 1 , switches Q 2  and Q 3 , of switch S 2 , and in examples of shapes of voltages VCe and VCo across equivalent capacitors Ce and Co of the cells of an even and odd line, respectively, as well as in an example of shape of current I in the charge transfer stage, the operation of the circuit of  FIG. 4 . 
     As previously, the turning-on of the first odd line starts with a turning-on of switches Q 1  and Q 4  (time t 0 ), with switches Q 2  and Q 3  as well as switches S 1  and S 2  being off. Voltage VCo is then brought to level V ON  and voltage VCe is brought to level V OFF . The luminance reference values are provided by the column control circuit (not shown). In the indicated voltage levels, the influences of the different voltage drops of the switching elements in the ON state are neglected. 
     At a time t 1 , subsequent to the end of the addressing of the first odd line, switches Q 1  and Q 4  are turned off and switch S 1  is turned on to precharge the first even line by flowing of a current through diode D 2 , inductance L, and switch S 1 . The current through inductance L increases up to a maximum Ip before canceling at a time t 2 . Between times t 1  and t 2 , voltage VCe switches from level V OFF  to a level dose to level V ON  and voltage VCo switches from level V ON  to a level dose to level V OFF . The interval between times t 1  and t 2  is a function of equivalent capacitance Co and of the value of inductance 
               L   ⁡     (         t   ⁢           ⁢   2     -     t   ⁢           ⁢   1       =       π     2       ·       Co   ·   L           )       .         
The maximum current Ip also depends on equivalent capacitance Co and on inductance L and is equal to V ON -V OFF ·√{square root over (Co/2L)}.
 
     From a time t 3 , subsequent to time t 2 , switch S 1  is off and switches Q 3  and Q 2  are on to complete the charge of the cells of the even line (voltage VCe) to level V ON  and end the discharge of the cells of the odd line (voltage VCo) to level V OFF . The addressing of the cells of the first even line is performed during this phase. 
     At the end of this addressing phase (time t 4 ), switch S 2  is turned on while switches Q 2  and Q 3  are off to cause a precharge of the cells of the next odd line. A current then flows through diode D 1 , inductance L, and switch S 2 . This current is of course in reverse direction with respect to the current between times t 1  and t 2 . It also has a non-linear increase and decrease and a peak value V ON -V OFF ·√{square root over (Ce/2L)} which is a function of equivalent capacitance Ce. Similarly, the interval between times t 4  and t 5  during which a current flows through inductance L, and which conditions the duration for voltages VCe and VCo to respectively reach levels dose to levels V OFF  and V ON , depends on equivalent capacitance 
     
       
         
           
             
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     The same operation is then repeated for the next odd line (times t 0 ′, to t 2 ′), etc. 
     An advantage of this embodiment of the present invention is that it decreases losses by taking advantage of the resonance introduced by inductance L in charge transfer phases. Losses P during this resonance phase can be expressed as: 
               P   =       f   ·     C   eq     ·   π   ·         (       V   ON     -     V   OFF       )     2       4   ·     2           ⁢           C   eq     L       ·     R   eq           ,         
where Ceq=Ce=Co and where Req represents the sum of the resistances of the conductive row lines and of the switches in the on state. In the former example of a 4.7-nF equivalent capacitance Ceq, of a 166-kHz frequency, of a 35-volt voltage V ON , and of a −25-volt voltage V OFF , and estimating at 20 ohms the total equivalent resistance of the lines, a 0.213-watt loss to be compared with the previously-obtained 1.4 watts is obtained
 
     Another advantage of the resonance is that it smoothes switching edges. The value of inductance L (for a given panel) sets the dV/dt This enables decreasing cell-to-cell interferences. 
       FIG. 6  shows the electric diagram of a circuit for controlling switches S 1  and S 2  of  FIG. 4 , here made in the form of MOS transistors. The cells of an even and odd line are symbolized by the respective equivalent capacitances Ce and Co in series with respective resistances Re and Ro between terminals  33 , and  32 , respectively, and a grounded terminal  44 . 
     The respective gates of transistors S 1  and S 2  are connected to terminals  33  and  32  by parallel assemblies, each formed of a resistor R 11  or R 12 , of a capacitor C 1  or C 2  (possibly formed of the gate-source capacitance of transistor S 1  or S 2 ), and of a Zener diode DZ 1  or DZ 2  (or another voltage-limiting element). The function of diodes DZ 1  and DZ 2  is to protect the gates of transistors S 1  and S 2 . These gates are further connected to the respective junction points of diodes D 11  and D 12 , and D 13  and D 14 , connecting a terminal  40 , connected by a switch S 3  to a source  41  of a preferably constant current ( 10 ), to a terminal  42  of application of voltage V ON . Source  41  is supplied by a D.C. voltage Vcc, at least greater than voltage V ON  plus the on-state gate-source voltage (Vgs ON ) of transistor S 1  or S 2 . Diodes D 11  to D 14  selectively charge the gate of transistor S 1  or S 2  having its conduction terminal on the side of switches Q at the low level (typically V OFF  at the beginning, but the selection operates as long as the voltage is smaller than V ON ). Resistors R 11  and R 12  are used to discharge the gates of transistors S 1  and S 2  in the quiescent state. 
     Switch S 3  is controlled to be turned on at times t 1 , t 4 , t 1 ′, etc. to initiate the power recovery phases. 
     Taking the example of time t 1 , that is, once the addressing of an odd line is over, the turning-on of switch S 3  causes the flowing of a current from current source  41  through diode D 11  to charge capacitor C 1  in parallel on the gate of transistor S 1 . The flowing to terminal  33  rather than to terminal  32  results from the fact that, on turning-off of switches Q 1  and Q 3 , terminal  32  is approximately at level V ON  (at the voltage set by the cells of the odd line) while terminal  32  approximately is at level V OFF  (voltage of the cells of the even line). The fact that terminal  42  is at voltage V ON  takes part in the blocking of the upper portion (in the arbitrary orientation of the drawing) of the assembly. A current also flows through diode DZ 1  to start charging the cells of the even line (Ce, Re). 
     Once capacitor C 1  has reached a sufficient charge, it causes the turning-on of transistor S 1 . In fact, as compared with the illustration of  FIGS. 5A to 5G , this translates as a slight delay (set by the on-state gate-source voltage Vgs ON  of transistor S 1 , the current in source  41 , and capacitor C 1 ) on turning-on of switch S 1  with respect to time t 1 . A flowing of the current then establishes from the cells of the odd line (Co, Ro), through diode D 2 , inductance L, and switch S 1 , to reach the cells of the next even line (Ce, Re). Transistor S 1  remains on as long as the voltage across its gate is positive and is greater than the threshold set by diode DZ 1 . Switch S 3  remains on until capacitor C 1  has a sufficient charge (for example, on the order of from 10 to 12 volts). This amounts, for example, to a few hundreds of nanoseconds. 
     At time t 2 , the voltage of capacitor C 1  plus the voltage between point  33  and the ground becomes sufficient to turn on diode D 2 . This enables discharge of capacitor C 1  and blocking of transistor S 1 . As soon as switches Q 2  and Q 3  are turned on (time t 3 ), voltage V ON -V OFF  between terminals  33  and  32  confirms the blocking of the low portion of the assembly by the discharge of capacitor C 1  through diode D 12  and switch Q 3 . Further, the charge of the cells of the even line and the discharge of those of the odd line are carried on. 
     At the end of the even line cell addressing period (time t 4 ), the voltage of terminal  33  is V OFF , that of terminal  32  is V ON . Accordingly, a turning-on of switch S 3  from time t 4  causes the flowing of a charge current of capacitor C 2  to turn on transistor S 2 . An operation similar to that described hereabove for switch S 1  is repeated for switch S 2 . 
     An advantage of the circuit of  FIG. 6  is that it enables controlling both switches S 1  and S 2  by means of a same control circuit, and thus solving the problems of floating voltages of the conventional circuit ( FIG. 3 ). The control signal of switch S 3 , which is designated CT in  FIG. 6 , is, for example, generated by a circuit of control and synchronization ( 5 ,  FIG. 2 ) of the screen circuits (generally, of microprocessor type). 
     As a specific example, a circuit such as illustrated in  FIG. 6  may be formed with components having the following values:
         L=100 μH;   C 1 =C 2 =1 nF;   R  11 =R 12 =100 kΩ; and   DZ 1 =DZ 2 =10 Volts.       

       FIG. 7  illustrates a variation of the circuit of  FIG. 4  according to which two inductive elements L 1  and L 2  replace the conventional resistors of the assembly of  FIG. 3  according to another embodiment of the present invention. Such a variation enables decreasing losses with respect to this conventional assembly of  FIG. 3  but it does not enable simplifying the control as in the assembly of  FIGS. 4 and 6 . 
     Of course, the present invention and embodiments thereof are likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art In particular, the sizing of the circuit components according to the screen type (especially its scan frequency and the equivalent capacitances of its cells), is within the abilities of those skilled in the art. Further, the turn-on and turn-off times of the different switching elements which have been shown as being simultaneous may in practice be shifted in time, for example, to avoid simultaneous conduction periods risking short-circuiting the supply lines. Such switching elements arbitrarily designated as switches are in practice MOS transistors (except for switch S 3  which is, preferably, a bipolar transistor). 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto. 
     Flat screens such as LCD panels including embodiments of the present invention may be contained in a variety of different types of electronic devices, such as portable devices like cellular phones, personal digital assistants (PDAs), calculators, video/audio players, and so on, and may be contained in electronic systems such as computer systems.

Technology Classification (CPC): 6