Patent Abstract:
An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm 2 .

Full Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present disclosure generally relates to advanced transistor geometries and to electro-mechanical devices integrated with microelectronic circuits. 
         [0003]    Description of the Related Art 
         [0004]    Micro-electromechanical systems (MEMs) exist that combine electronic devices with mechanical structures to form electronically controlled moving parts for use as miniature sensors and actuators, for example. A typical MEMs device is shown in  FIG. 1  as a planar transistor in which the conduction channel is electrically coupled to the source but detached from the drain. When a current is applied to the gate, the detached end of the conduction channel makes contact with the drain, thereby closing the circuit and turning on the transistor switch. Like other MEMs devices, the electrical portion of the device shown in  FIG. 1  is disposed next to the mechanical portion, in substantially the same horizontal plane. As a result, the overall footprint is quite large, on the order of 10×10 μm 2 , whereas state-of-the-art electronic circuits are now measured in nanometers, about a thousand times smaller than MEMs devices. The relatively large size of current MEMs devices limits their production, packing density, precision, sensitivity, and economic value. 
       BRIEF SUMMARY 
       [0005]    An integrated transistor in the form of a nano-electromechanical switch eliminates current leakage and increases switching speed. The nano-electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position, breaking the circuit and restoring a void underneath the gate that does not permit current flow. Hence, the off-state current is forced to be zero, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. Use of a back bias, and a metallic tip on the cantilever can further improve sensitivity of the switch. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm 2 . 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0006]    In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. 
           [0007]      FIG. 1A  is a pictorial perspective view of an existing planar MEMs switch  50  according to the prior art. 
           [0008]      FIG. 1B  is derived from a photograph showing a top plan view of the existing planar MEMs switch  50  shown in  FIG. 1A , indicating a length scale. 
           [0009]      FIG. 2  is a flow diagram showing steps in a method of fabricating a nanoscale electromechanical switch as illustrated in  FIGS. 3A-6B , according to one embodiment as described herein. 
           [0010]      FIGS. 3A-5  are cross-sectional views of the nanoscale electromechanical switch at successive steps during fabrication using the method shown in  FIG. 2 . 
           [0011]      FIG. 6A  is a cross-sectional view, of a completed nanoscale electromechanical switch, according to a first embodiment. 
           [0012]      FIG. 6B  is a top plan view of the completed nanoscale electromechanical switch shown in  FIG. 6A . 
           [0013]      FIGS. 7-8C  are cross-sectional views of alternative embodiments to the completed nanoscale electromechanical switch shown in  FIGS. 6A-6B . 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure. 
         [0015]    Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.” 
         [0016]    Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure. 
         [0017]    Reference throughout the specification to integrated circuits is generally intended to include integrated circuit components built on semiconducting substrates, whether or not the components are coupled together into a circuit or able to be interconnected. Throughout the specification, the term “layer” is used in its broadest sense to include a thin film, a cap, or the like and one layer may be composed of multiple sub-layers. 
         [0018]    Reference throughout the specification to conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals, or similar materials includes such processes as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. For example, in some circumstances, a description that references CVD may alternatively be done using PVD, or a description that specifies electroplating may alternatively be accomplished using electro-less plating. Furthermore, reference to conventional techniques of thin film formation may include growing a film in-situ. For example, in some embodiments, controlled growth of an oxide to a desired thickness can be achieved by exposing a silicon surface to oxygen gas or to moisture in a heated chamber. 
         [0019]    Reference throughout the specification to conventional photolithography techniques, known in the art of semiconductor fabrication for patterning various thin films, includes a spin-expose-develop process sequence typically followed by an etch process. Alternatively or additionally, photoresist can also be used to pattern a hard mask (e.g., a silicon nitride hard mask), which, in turn, can be used to pattern an underlying film. 
         [0020]    Reference throughout the specification to conventional etching techniques known in the art of semiconductor fabrication for selective removal of polysilicon, silicon nitride, silicon dioxide, metals, photoresist, polyimide, or similar materials includes such processes as wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical-mechanical planarization (CMP) and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. In some instances, two such techniques may be interchangeable. For example, stripping photoresist may entail immersing a sample in a wet chemical bath or, alternatively, spraying wet chemicals directly onto the sample. 
         [0021]    Specific embodiments are described herein with reference to nano-electromechanical switching devices that have been produced; however, the present disclosure and the reference to certain materials, dimensions, and the details and ordering of processing steps are exemplary and should not be limited to those shown. 
         [0022]    Turning now to the figures,  FIG. 1A  shows an existing planar MEMs switch  50  mounted on top of a substrate. The switch  50  has a source terminal  52 , a gate terminal  54 , a drain terminal  56 , and a cantilever arm  58  of length L having a tip  59 . Each one of the terminals  52 ,  54 ,  56 , and the cantilever arm  58 , is made of a conductive material, e.g., a semiconductor or metal that conducts electric current. The cantilever arm  58  is a flexible, moveable member, extending out from the source terminal  52  to a distance beyond a nearest edge  60  of the drain terminal  56 . The gate terminal  54  is disposed to the side of the cantilever arm  58 . The cantilever arm  58  is spaced apart from the gate terminal  54  by a short distance so that when the gate terminal  54  is energized, the cantilever arm  58  is drawn toward the gate terminal  54 . Because the tip  59  of the cantilever arm  58  moves more freely than the fixed end nearest the source terminal  52 , the tip  59  can make contact with the drain terminal  56 . When the tip  59  contacts the drain terminal  56 , the switch  50  is closed, permitting flow of electric current between the source terminal  52  and the drain terminal  56 , through the cantilever arm  58 , which acts as a current channel. 
         [0023]      FIG. 1B  shows an enlarged view of the planar MEMs switching device  50  superimposed with a 3-μm length scale. The scale indicates that the cantilever arm  58  is about 10 μm long, which is consistent with the sizes of conventional MEMs devices. The overall footprint of the exemplary planar MEMs switch  50  is in the range of about 200 μm 2 . 
         [0024]      FIG. 2  shows steps in a method of fabricating a cantilever switch as a nanoscale transistor device suitable for use in integrated circuits, according to one embodiment. Unlike the planar MEMs switching device  50 , the cantilever switch described herein is integrated into a layered semiconductor structure that forms an extension of the substrate, and the process for fabricating the cantilever switch is fully compatible with conventional CMOS processes. Steps in a method  100  for constructing such a nanoscale cantilever switch on a silicon-on-insulator (SOI) substrate are further illustrated by  FIGS. 3-6B , and described below. A second embodiment built on a silicon substrate is shown in  FIG. 7 . Additional steps that can be used to construct a third embodiment are illustrated in  FIGS. 8A-8C . 
         [0025]    At  102 , a layered stack  122  is formed by epitaxially growing layers of first and second semiconductor materials, e.g., silicon germanium (SiGe) and silicon in an alternating arrangement on an SOI wafer, as shown in  FIGS. 3A and 3B . The SOI wafer includes a silicon substrate  114 , a buried oxide (BOX) layer  116  of thickness in the range of about 15-25 nm and, above the BOX layer  116 , an overlying silicon layer  118  having a thickness in the range of about 10-15 nm. Such an SOI wafer is a standard starting material that is commonly used in the semiconductor industry. Alternatively, a silicon wafer can be used as the starting material, and the BOX layer  116  and the overlying silicon layer  118  can be formed as initial steps of the present fabrication process. In one embodiment, a first region of SiGe  120  is formed at a same level as the overlying silicon layer  118  as follows: first, a hard mask having a first layer of silicon dioxide (SiO 2 ) and a second layer of silicon nitride (SiN) is formed on the overlying silicon layer  118 . The hard mask is patterned to remove a portion corresponding to the desired size of the SiGe  120 , and SiGe is epitaxially grown from the exposed surface of the overlying silicon layer  118 . The SiO 2  layer of the hard mask protects the overlying silicon layer  118  from contacting the SiN layer at high temperatures during the epitaxy. Then germanium from the SiGe region is driven downward into the overlying silicon layer  118  using a condensation process that is known in the art. The hard mask layer is then removed to produce the structure shown in  FIG. 3A . 
         [0026]    Next, a first additional silicon layer  124  that incorporates a second region of SiGe  126  is formed. In one embodiment, the first additional silicon layer  124  is grown epitaxially from the overlying silicon layer  118  to a thickness in the range of about 15-30 nm. The thickness of the first additional silicon layer  124  will determine the thickness, and will influence the flexibility, of the cantilever for the nanomechanical switch. The first additional silicon layer  124  can be doped in-situ during the epitaxy process, or by implantation, with negative ions, e.g., arsenic or phosphorous, to a concentration in the range of about 8.0 E19-3.0 E20 cm −3 . The first additional silicon layer  124  is then patterned, using a SiO2/SiN hard mask, to form an opening that is surrounded by silicon material. The second region of SiGe  126  can then be grown epitaxially to fill the opening using the same technique just described. The SiO2/SiN hard mask is then removed. 
         [0027]    Next, an additional silicon layer  128  that incorporates a third region of SiGe  130  is formed. In one embodiment, the additional silicon layer  128  is grown epitaxially from the first additional silicon layer  124  to a thickness in the range of about 10-15 nm. The thickness of the additional silicon layer  128  will determine a distance through which the cantilever will need to move to close the switch. Such a distance can be achieved with precision using epitaxy to form the additional silicon layer  128  and the third region of SiGe. The additional silicon layer  128  can be doped in-situ during the epitaxy process, or by implantation, with negative ions, e.g., arsenic or phosphorous, to a concentration in the range of about 1.0-2.0 E20 cm −3 . The additional silicon layer  128  is then patterned, using a SiO2/SiN hard mask, to form an opening that, again, is surrounded by silicon material. 
         [0028]    The third region of SiGe  130  can then be grown epitaxially to fill the opening. The SiO2/SiN hard mask is then removed to produce the structure shown in  FIG. 3B . 
         [0029]    At  104 , a conventional transistor gate structure  140  is formed on top of the third region of SiGe  130 , overlying the layered stack. First, a thin layer, e.g., 2-5 nm of a dielectric material, e.g., SiO 2  or a high-k material such as HfO 2 , is deposited, followed by layers of polysilicon and SiN. The SiO 2 , polysilicon, and SiN are then patterned to form the gate structure  140 , including a gate dielectric  148 , a gate electrode  150 , and an insulating cap  152 . Insulating sidewall spacers  154  are then formed in the usual way by conformal deposition of, for example, SiN, followed by anisotropic removal of the SiN portion overlying the gate electrode  150  down to the SiN cap  152 , leaving in place the sidewall portions of the SiN. The transistor gate structure  140  thus formed can be used as a mask for doping the additional silicon layer  128  to reduce resistance of the silicon. It will not matter if dopants are also incorporated into the third region of SiGe  130 , because the SiGe regions in the present structure are sacrificial. Alternatively, a metal gate can be used instead of a polysilicon gate. A metal gate can be formed by any conventional method, e.g., by a replacement metal gate (RMG) process in which, after the transistor structure  140  is formed, the polysilicon gate electrode is removed and replaced by a metal gate electrode. 
         [0030]    At  106 , epitaxial raised source and drain regions  142 ,  144  are formed on either side of the transistor gate structure  140 , as shown in  FIG. 4 . In one embodiment, the raised source and drain regions  142 ,  144  are grown epitaxially from the additional silicon layer  128  and the third region of SiGe  130  to a thickness in the range of about 20-35 nm. The raised source and drain regions  142 ,  144  can be doped in-situ with ions of a same polarity as those used to dope the first additional silicon layer  124 . The raised source and drain regions  142 ,  144  include facets  146  sloping down to the base of the sidewall spacers  154 . 
         [0031]    At  108 , portions of the raised source and drain regions  142 ,  144  are removed by a partially anisotropic etching process to form openings  162  at the base of the transistor gate structure  140 , thus exposing the third SiGe region  130 . The openings  162  are desirably in the range of 3-8 nm, thus leaving about a 5 nm gap between the base of the sidewall spacers  154  and the source and the inner corners of the faceted source and drain regions  142 ,  144 . 
         [0032]    At  110 , the SiGe portions of the layered stack are selectively removed to form a cavity  160  surrounding a cantilever arm  164  having a tip  166 , as shown in  FIGS. 5, 6A . In one embodiment, removal of sacrificial first, second, and third regions of SiGe,  120 ,  126 ,  130 , respectively, is accomplished by exposing the layered stack to hydrochloric acid (HCL). The HCL will selectively etch the regions of SiGe, leaving behind various layers of silicon. First, the HCL attacks the third region of SiGe  130  directly below the openings  162 , creating a void underneath the transistor gate structure  140 . Then, because the HCL is a fluid, e.g., a liquid etchant, the HCL will flow into the voids thus created, and continue etching out the second region of SiGe  126 , followed by the first region of SiGe  120 , thus releasing the cantilever arm  164 . The cantilever arm  164  is formed from remaining silicon in the first additional silicon layer  124  so that the cantilever arm  164  extends out from underneath the source region  142 , into the cavity  160  directly below the transistor gate structure  140 . When the SiGe removal step  110  is complete, the cantilever arm  164  can flex freely within the cavity  160 , toward or away from the transistor gate structure  140 , based on an electric potential of the gate electrode  150  relative to an electric potential of the cantilever arm  164 . 
         [0033]    In operation, when a sufficient positive voltage, exceeding a threshold value, is applied to the gate electrode  150 , the doped cantilever arm  164 , is deflected toward the oppositely doped gate. The cantilever arm  164  may flex enough that the tip  166  makes physical and electrical contact with the base of the drain region  144 . When such contact occurs, the electromechanical switch is closed as a current path is established from the source region  142  to the drain region  144 , wherein the cantilever arm  164  serves as a transistor channel. The threshold voltage can be tuned during fabrication by adjusting the thickness of the additional silicon layer  128 . In addition, a voltage, e.g., in the range of about 3-4 V can be applied via a backside electrical contact to the silicon substrate  114  to back-bias the BOX layer  116 , so as to repel the cantilever arm  164  and assist in moving the tip  166  toward the drain region  144 . The BOX layer  116  thus may serve as a back gate. When the voltage applied to the gate electrode  150  no longer exceeds the threshold voltage, the cantilever arm  164  relaxes and returns to its original extended position. Alternatively, the cantilever arm  164  and the source and drain regions  142 ,  144  can be positively doped to form a p-type device for which, in operation, a negative voltage is applied to the gate electrode  150 . 
         [0034]    In the extended position, the switch is open, i.e., an open circuit exists between the source  142  and the drain  144 . Thus, in the off state, no current flows through the cantilever arm  164 . Furthermore, because the cavity  160  is positioned directly underneath the transistor gate structure  140 , charge cannot leak from the tips of the source and drain regions  142 ,  144  into the substrate. A small amount of charge may migrate from the source and drain regions  142 ,  144  into the silicon layers  128 ,  124 ,  118  in response to localized electric fields. However, a current cannot flow from the source region  142  to the drain region  144  because the electrical path is blocked by either the cavity  160  or the insulating BOX layer  116 . Thus, the off-state leakage current is zero, preventing drainage of electric battery power supplied to the transistor. For the cantilever arm  164  to be flexible enough to open and close the switch, the cantilever arm  164  is designed to have suitable mechanical properties and dimensions that will allow the cantilever arm to respond to voltage levels used in integrated circuits, in the range of about 0.5-1.0 V. In one embodiment, the cantilever arm  164  has an aspect ratio of at least about 4.0, and the threshold voltage is about 0.8V. 
         [0035]    More generally, the switching action can be the result of one or more of a capacitive, electrostatic, or inductive effect. For example, the gate electrode  150 , drain region  144 , and cantilever arm  164  may incorporate electromagnetic materials having magnetic properties that are responsive to the influence of a voltage applied to the gate electrode  150 . 
         [0036]    At  112 , the openings  162  are sealed with a glass material  172 , to form a completed structure as shown in  FIG. 6A . In one embodiment the glass material  172  is a spin-on glass (SOG), a material well known in the art. The spin-on glass is a liquid material having a high viscosity at temperatures less than 100 C, which can be cured, following deposition, to form a solid state glass. Alternatively, SiO 2  can be sputtered over the openings  162  to form a seal. Once the openings  162  are sealed, the glass material  172  can then be recessed below the top surfaces of the source and drain regions  142 ,  144 . 
         [0037]      FIG. 6B  shows that the transistor gate structure  140  is anchored on isolation regions  180 , e.g., silicon dioxide insulating structures separating adjacent devices from one another. The isolation regions  180  extend behind and in front of a cut plane  182  of the cross-sectional views shown in  FIGS. 3A-6A . Thus, in  FIGS. 5 and 6A , the transistor gate structure  140  appears to be floating over the cavity  160 , but actually, the transistor gate structure  140  forms a bridge that extends over the cavity  160  in a direction transverse to the cut plane  182 . 
         [0038]      FIG. 7  shows a second embodiment of the nanoscale electromechanical switch in which the BOX layer  116  is omitted. In the second embodiment, SiGe can be formed at the same level as the overlying silicon layer  118  by simply growing the SiGe epitaxially from the underlying silicon substrate  114 . Alternatively, the overlying silicon layer  118  can be formed as a SiGe layer and patterned to incorporate regions of silicon, to achieve the same structure shown in  FIG. 7 . However, the embodiment shown in  FIG. 7  will not have the option of applying a back bias to the device to assist in moving the cantilever arm  164 . Doing so without the BOX layer  116  in place would simply short out the transistor by coupling the source to the drain through the silicon substrate  114  and the intervening additional layers of silicon  118 ,  124 ,  128 . Alternatively, the second embodiment shown in  FIG. 7  can be fabricated using the condensation process described above. 
         [0039]      FIGS. 8A-8C  illustrate a third embodiment of nanoscale electromechanical switch  200  in which sensitivity of the device is enhanced by fabricating the tip  166  from a metal, e.g., tungsten (W). Such a modification can be made to step  102 , as shown in  FIGS. 8A-8B .  FIG. 8A  shows incorporating a metal tip  192  into the first additional silicon layer  124 . Following formation of the second SiGe region  126 , a SiN hard mask is deposited and patterned with an opening that aligns with the leftmost end of the doped silicon that will be the cantilever arm  164 . The tip  166  of the cantilever arm  164  is then etched away and replaced with the metal tip  192 , e.g., by depositing tungsten and polishing the tungsten surface to stop on the SiN hard mask. While the SiN hard mask is still in place, the tungsten is recessed and the recessed area is filled with an oxide, e.g., SiO 2 , to form an oxide mask  194  covering the metal tip  192 . The oxide is planarized to stop on the SiN hard mask. Then the SiN hard mask is removed, leaving the oxide mask  194  covering the metal tip  192 . The oxide mask prevents exposure of the metal tip  192  during the subsequent epitaxial growth of the second additional silicon layer and the third region of SiGe. After the cavity  160  is formed ( FIG. 8B ), the oxide mask can be removed in an isotropic dry etch process that is selective to silicon and oxide. In one embodiment, the dry etch process employs a known etchant that is typically used to remove silicon-cobalt-nickel (SiCoNi) films. The etchant can enter the cavity  160  through the opening  162  adjacent to the drain region  144 .  FIG. 8C  shows the completed third embodiment of the nanoscale electromechanical switch  200 . During operation, a metal tip  196  helps reduce contact resistance between the cantilever arm  164  and the doped drain region  144 . 
         [0040]    It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims. 
         [0041]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. 
         [0042]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

Technology Classification (CPC): 1