Patent Abstract:
A power amplification circuit having three modes of operation and a single switch is disclosed. Only one switch is used to control three different load impedance levels, one load impedance level for each mode of operation. The remaining “switching” results from selectively biasing each power amplification path by turning ON or OFF amplifiers. A series L-C and a switch are used to control the load impedance. Additional modes of operation may also be created without requiring any additional switch. Further, multiple modes of operation may be implemented using no switches.

Full Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 61/445,213 filed Feb. 22, 2011, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The embodiments described herein relate to the field of power amplifiers, and particularly to a multi-mode (multi-state) power amplifier using a single output switch to control three or more different output impedance levels, and thus to control three or more power outputs. 
       BACKGROUND 
       [0003]    Conventionally, a three mode linear power amplifier requires multiple output switches to realize three modes. Multiple switches require substantial space (die area), and this is a serious problem. Using a single switch would use about 40% less die area, and will have additional advantages over conventional systems. 
         [0004]    Switch(es) are used to change between conductive and non-conductive states. Each switch needs proper sizing to reduce on-state loss, proper logic control and peripheral matching circuits. Reducing the number of switches thus reduces die area. 
       SUMMARY 
       [0005]    The present disclosure relates to the realization of a three mode linear power amplifier (PA) with three distinct load impedances for High, Medium, and Low power modes utilizing a single switch on the output. This reduces the average current consumption of the PA and increases handset talk time. Only one switch is needed to control three different load impedance levels. The remaining “switching” results from selectively biasing each PA chain (or path) by turning ON or OFF amplifiers. A series L-C and an FET switch are used to control the load impedance. 
         [0006]    In low power mode, the equivalent shunt L is large (relatively) and the effective series capacitance is small (relatively), resulting in a high impedance load. In the medium power mode, the equivalent shunt L is medium and the remaining inductance is connected in series with the chain capacitor, increasing the effective series capacitance and hence lowering the load impedance to a medium impedance load. In the high power mode, the switch is OFF and the load impedance is small. 
         [0007]    This invention allows the implementation of a three mode PA in roughly 40% less die area than in the prior art, because only one switch is used. The benefits of this invention include: three impedance levels using a single output switch, simpler logic than a conventional multiple switch three mode PA, low average current, and high power added efficiency (PAE). Additionally, a four (or more) mode PA may be similarly implemented using a single switch. Further, it is possible to implement an embodiment of this invention using no switches. 
         [0008]    Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. The values of various inductors, capacitors, etc. are for illustrative purposes only. 
           [0010]      FIG. 1  illustrates an exemplary amplifier architecture for a three mode amplifier with a single output switch. 
           [0011]      FIG. 2  illustrates a high power mode (HPM). 
           [0012]      FIG. 3  illustrates a medium power mode (MPM). 
           [0013]      FIG. 4  illustrates a low power mode (LPM). 
           [0014]      FIG. 5  illustrates a four mode power amplifier using only one switch. 
           [0015]      FIG. 6  illustrates different ways to implement MDLS inductor Lchain 1 . 
           [0016]      FIG. 7  illustrates the importance of the MDLS inductor Q on MPM efficiency. 
           [0017]      FIG. 8  illustrates gain of the three modes of the MDLS Power Amplifier. 
           [0018]      FIG. 9  illustrates the adjacent channel power (ACP). 
           [0019]      FIG. 10  illustrates the Power Added Efficiency (PAE) versus power out (Pout) for all three modes. 
           [0020]      FIG. 11  illustrates Power Added Efficiency (PAE) versus LPM loadline. 
           [0021]      FIG. 12  illustrates maximum linear output power and minimum necessary Icq. 
           [0022]      FIG. 13  illustrates the relative die area of this invention in comparison to conventional competitors. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. The term “connected” is defined broadly, and does not require a direct connection. For example a first element connected to a first node permits the existence of another element (such as a resistor) located electrically between the first element and the first node. 
         [0024]      FIG. 1  depicts an exemplary MDLS power amplifier architecture. There are three modes of operation: high power mode (HPM), medium power mode (MPM), and low power mode (LPM). Table 1, below, illustrates the preferred state of amplifiers (Q 1 H, Q 2 H, Q 1 M, Q 2 M, and Q 1 L) and the switch (SW 1 ) for each mode of operation. 
         [0000]    
       
         
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 State of Amplifiers and the Switch for Each Mode 
               
             
          
           
               
                   
                 ELEMENTS 
                 HPM 
                 MPM 
                 LPM 
               
               
                   
                   
               
               
                   
                 Q1H 
                 ON 
                 OFF 
                 OFF 
               
               
                   
                 Q2H 
                 ON 
                 OFF 
                 OFF 
               
               
                   
                 SW1 
                 OFF 
                 ON 
                 ON 
               
               
                   
                 Q1M 
                 OFF 
                 ON 
                 ON 
               
               
                   
                 Q2M 
                 OFF 
                 ON 
                 OFF 
               
               
                   
                 Q2L 
                 OFF 
                 OFF 
                 ON 
               
               
                   
                   
               
             
          
         
       
     
         [0025]    Operation of the three modes is discussed briefly here with respect to  FIG. 1  (and in more detail later with respect to  FIGS. 2-4 ). 
         [0026]    Referring to the bottom portion of  FIG. 1 , in high power mode (HPM), Q 1 H and Q 2 H are “ON”, whereas the switch (SW 1 ) and all other RF stages are “OFF”. A load line of approximately 4 ohms is presented to Q 2 H (at point H) using a standard matching network. 
         [0027]    The group of elements to the right of point H and below Cchain 1  is called an Output Matching Network (OMN). In the example of  FIG. 1 , the output matching network comprises three inductors and three capacitors. 
         [0028]    Referring to the middle portion of  FIG. 1 , in the medium power mode (MPM), Q 1 M, Q 2 M, and SW 1  are “ON”, whereas Q 1 H, Q 2 H, Q 2 L are “OFF” (and therefore omitted from  FIG. 3 ). In medium power mode (MPM), an impedance of about 30 ohms is presented to Q 2 M (at point M) by using a high pass matching network connected to the 4 ohm point (at point H) of the HPM. As shown in the MPM block at the top left of  FIG. 1 , the series combination of Lchain 1  and Cchain 1  forms an effective capacitance that is larger than Cchain 1  alone. Lchain 2  is the shunt L that completes the chain match which transforms the load from 4 ohms to 30 ohms. 
         [0029]    Referring to the top portion of  FIG. 1 , in the low power mode (LPM), Q 1 M, Q 2 L, and SW 1  are “ON”, whereas Q 1 H, Q 2 H, Q 2 M are “OFF” (and therefore omitted from  FIG. 4 ). Switch SW 1  in an ON state is represented by resistor Ron. The Output Matching Network (OMN) was discussed above. In low power mode (LPM) an impedance of about 90 ohms is presented to Q 2 L (at point L) by using a high pass matching network connected to the 4 ohm point (at point H). 
         [0030]    As shown in the LPM block at the top right of  FIG. 1 , the series capacitor is just Cchain 1 , while Lchain 1  and Lchain 2  form the shunt L which transforms the load from 4 ohms to 90 ohms. These three modes are discussed in more detail in  FIGS. 2-4 . 
         [0031]    From an engineering point of view, the loss in inductor Lchain 1  is very important to the performance of the power amplifier. An efficient Lchain 1  has a high quality factor (Q) value, and thus has low resistance and low losses. 
         [0032]      FIG. 2  illustrates a high power mode (HPM).  FIG. 2  omits portions of the circuit of  FIG. 1  which are effectively isolated by setting SW 1  in the OFF state. Amplifiers Q 1 M, Q 2 M, and Q 2 L from  FIG. 1  are preferably switched off (although this is not necessary if switch SW 1  is switched off). Q 1 H and Q 2 H are ON, and form the high power path. In one embodiment, switch SW 1  is omitted, and at least one amplifier in each non-utilized path is turned off. However, it is preferable to use SW 1 , because using SW 1  improves isolation when the high power mode (HPM) is used. 
         [0033]    In the high power mode, only the lower portion of  FIG. 1  is active, and only the active portion is illustrated in  FIG. 2 . The output of amplifier Q 2 H sees an impedance of 4 ohms (at point H). The load impedance of 4 ohms at point H is necessary to provide a peak output power of 31 dBm with Vcc=3.4V. 
         [0034]      FIG. 3  illustrates a medium power mode (MPM).  FIG. 3  omits portions of  FIG. 1  which are effectively isolated by turning off amplifiers QH 1 , QH 2 , and Q 2 L. Switch SW 1  is ON. Amplifiers Q 1 M and Q 2 M form the medium power path. Amplifier Q 2 M sees about 30 ohms (at point M). 
         [0035]    In medium mode, amplifier Q 2 M contacts the chain elements (Lchain 2 =2 nH, Lchain 1 =0.8 nH, and Cchain 1 =4 pF) at a location between Lchain 2  and Lchain 1 . Note that values for these chain elements are provided here for illustrative purposes only. The values used in this application pertain to operation at 1.9 GHz. 
         [0036]    Inductor Lchain 2  has a value of 2 nH. Inductor Lchain 1  has a value of 0.8 nH. Capacitor Cchain 1  has a value of 4 pF. These chain elements, operating at 1.9 GHz in the medium power configuration, are equivalent to an effective RF circuit comprising an inductor 2 nH and a capacitor of 8 pF, as shown on the right side of the large brace “}” in  FIG. 3 . 
         [0037]      FIG. 4  illustrates a low power mode (LPM).  FIG. 4  omits portions of  FIG. 1  which are effectively isolated by turning off amplifiers Q 1 H, Q 2 H, and Q 2 M. Amplifiers Q 1 M and Q 2 L are ON, and form the low power path. Note that in this example, amplifier Q 1 M is ON for the medium power mode and also for the low power mode. Amplifier Q 2 L sees about 90 ohms. 
         [0038]    In low power mode, amplifier Q 2 L contacts the chain elements (Lchain 2 =2 nH, Lchain 1 =0.8 nH, and Cchain 1 =4 pF) at a location between Lchain 1  and Cchain 1 . 
         [0039]    Amplifiers Q 1 M and Q 2 L constitute the low power path, and are ON. Switch SW 1  is ON. The other amplifiers (Q 1 H, Q 2 H, and Q 2 M) are OFF. 
         [0040]    Inductor Lchain 2  has a value of 2 nH. Inductor Lchain 1  has a value of 0.8 nH. Capacitor Cchain 1  has a value of 4 pF. These elements, operating at 1.9 GHz in the low power configuration, are equivalent to an effective RF circuit comprising an inductor 2.8 nH and a capacitor of 4 pF, as shown on the right side of the large brace “}” in  FIG. 4 . 
         [0041]      FIG. 5  illustrates a four (or more) mode power amplifier using only one switch. The three mode example of  FIG. 1  uses two chain matching inductors (Lchain 1  and Lchain 2 ). In  FIG. 5 , at least one additional inductor (Lchainn) and an associated amplifier (QLPMn) is added relative to the three mode example of  FIG. 1 . 
         [0042]    The notation and design of  FIG. 5  is generalized to expressly consider 4 or more modes. Additionally, much detail from  FIG. 1  has been intentionally omitted (such as amplifier Q 1 M which was used in the low power mode and also was used in the medium power mode). Please refer to  FIG. 5  and to this portion of the specification for terminology used in the claims. 
         [0043]    In general, an n+1 mode power amplifier of four or more modes may be created using one chain matching capacitor (Cchain 1 ), one RF switch (SW 1 ), one high power mode amplifier (Q_HPM), n additional power mode amplifiers (Q_LPM 1  through Q_LPMn), and n additional chain inductors (Lchain 1  through Lchainn). 
         [0044]    FIRST POWER PATH: The first power path is located at the bottom of  FIG. 5 . The first power path includes amplifier Q_HPM, as well as any amplifiers preceding amplifier Q_HPM (outputting towards Q_HPM). The first power path is associated with a high power mode (actually the highest power mode). 
         [0045]    The high (highest) power mode occurs when amplifier Q_HPM is ON (and, of course any other amplifiers in the path of Q_HPM are ON), SW 1  is OFF, and the other amplifiers in other paths are preferably all OFF, with the exception that any amplifier which shares the first power path must remain ON. This high power mode corresponds to a low impedance of Z_HPM at the first node. 
         [0046]    SECOND POWER PATH: In the second power path, a low (lowest) power mode occurs when amplifier Q_LPM 1  is ON (and any other amplifiers in the path of Q_LPM 1  are ON), SW 1  is ON, and at least one amplifier in each of the other paths is OFF (preferably all amplifiers in the other paths are OFF, except for amplifiers shared by the path including Q_LPM 1 ). 
         [0047]    Of course, as illustrated by the above three mode example, any amplifier which is shared by two or more paths must be ON when one of the paths which shares the shared amplifier is active (see Q 1 M in  FIG. 1 ). Similarly, each path preferably contains at least one amplifier that is not shared. This low power mode corresponds to a high impedance at Z_LPM 1 . In other words, Z_HPM&lt; . . . &lt;Z_LPM 1 . 
         [0048]    For the purpose of clarity and simplicity, we consider the case where there are four modes (n=3) so that no additional chain inductors and no additional power paths are needed relative to  FIG. 5 . A first power path passes through amplifier Q_HPM, a second power path passes through Q_LPM 1 , a third power path passes through Q_LPM 2 , and an (n+1)th (fourth in this case) power path passes through Q_LPMn. 
         [0049]    With respect to impedance: Z_HPM&lt;Z_LPMn&lt;Z_LPM 2 &lt;Z_LPM 1 . 
         [0050]    The order with respect to power is reversed relative to the order of impedance, as follows: first power path&gt;nth power path&gt;third power path&gt;second power path. 
         [0051]    THIRD POWER PATH Continuing, the first medium power (second lowest) output mode occurs when amplifier Q_LPM 2  is ON, and corresponds to an impedance of Z_LPM 2 . The claims refer to this output mode as “first medium power mode” for the case when there are four modes. This first medium power mode has more power than the low power mode, but less than the high power mode. This first medium power mode corresponds roughly to the medium power mode of the circuit of  FIG. 1  and  FIG. 3 . 
         [0052]    (N+1)TH POWER PATH. The (n+1)th (fourth power path) is described as a second (or nth) medium power mode. This second medium power mode has more power than the first medium power mode, but less than the high power mode. This second medium power mode corresponds roughly to extending the circuit of  FIG. 1  upwards by adding an additional power path (including at least one additional amplifier) above amplifier Q 2 M, plus inserting an additional chain inductor above Lchain 2  and below Vcc. The additional amplifier would be connected above Lchain 2  and below the additional chain inductor. 
         [0053]    To summarize more generally, for a four or more mode power amplifier the load impedances are ordered as follows: Z_HPM&lt;Z_LPMn&lt; . . . &lt;Z_LPM 2 &lt;Z_LPM 1 . The order with respect to power is reversed relative to the order with respect to impedance. 
         [0054]      FIG. 6  illustrates different ways to implement the MDLS inductor Lchain 1 . Specifically, the large bold circle at the top circuit of  FIG. 6  surrounds a printed spiral inductor, and the large bold ellipse at the bottom circuit of  FIG. 6  surrounds an inductor using three bond wires. 
         [0055]    The bond wires have some inductance at typical RF frequencies. The use of bond wires increases the quality factor (Q) of the MDLS inductor, which improves the LPM and MPM efficiency due to reduced output matching network losses. 
         [0056]      FIG. 7  illustrates the importance of the MDLS inductor Q on MPM efficiency. Specifically, Medium Power Mode (MPM) Power Added Efficiency (PAE) is graphed versus IND Q (the quality factor of the chain inductor Lchain 1 ). Typical printed spirals on GaAs (Gallium Arsenide) can have a Q as low as 5 while bond wires have Q well in excess of 25. As the Q value falls below 10, efficiency drops off dramatically. Thus, bond wires are strongly preferred, especially gold bond wires. 
         [0057]      FIG. 8  illustrates gain of the three modes of an MDLS Power Amplifier using bond wires for the inductor. The frequency is 1.88 GHz, Vcc is 3.4 V, and the measurements were made using IS95 CDMA modulation. 
         [0058]      FIG. 9  illustrates the adjacent channel power (ACP). Some systems require −42 dBc or less, and with a target of −48 dBc or less. 
         [0059]      FIG. 10  illustrates the Power Added Efficiency (PAE) versus power out (Pout) for all three modes. 
         [0060]      FIG. 11  illustrates Power Added Efficiency (PAE) versus LPM loadline at 8 dBm. The LPM load line has a significant impact on LPM efficiency, back off linearity, and minimum Icq. The MDLS architecture allows one to easily increase the LPM loadline above that of the MPM.  FIG. 11  shows the increase in LPM efficiency as the LPM load line increases from 30 ohms (the MPM load line) to 120 ohms. With a 90 ohm load line, the efficiency at 8 dBm increases from about 9.5% to 13%. 
         [0061]      FIG. 12  illustrates maximum linear output power and minimum necessary Icq (quiescent collector current, with no RF input) to maintain adjacent power channel ratio (ACP) less than −48 dBc at backed off power. A second advantage of the increased LPM load line is that as the Icq of the LPM is decreased, the linearity at back off power degrades less. 
         [0062]    Specifically,  FIG. 12  shows the minimum IN required for a 2 stage LPM to achieve −48 dBc ACPR (IS95). As the LPM load line increased, the maximum linear output power goes down, but the minimum required IN for −48 dBc linearity also goes down. If only 12 dBm maximum output power is required in the LPM, a 120 ohm load line will allow one to achieve that output power with about 15% less quiescent current than a 30 ohm load line. Alternatively, if one keeps Icq constant, increasing the LPM load line increases PAE and improves back-off linearity. 
         [0063]    An additional benefit of the MDLS architecture is the ability to control insertion phase changes between modes. The addition of Lchain 1  increases the degrees of freedom to reduce the insertion phase change between modes. The example PCS amplifier shown in  FIGS. 8-10  has a maximum phase delta of less than 25 degrees. 
         [0064]    Table 2 illustrates average current for various power amplifiers. Specifically, Table 2 compares the average current computed using different statistics for both the bond wire and the printed spiral (MMIC) implementation of the MDLS inductor. Data for a competitor&#39;s part is also included in the table. The higher Q of the bond wire implementation reduced the “urban” average current by about 0.5 mA. 
         [0000]    
       
         
               
             
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Average Current Comparison 
               
             
          
           
               
                   
                 MDLS 
                 MDLS 
                   
               
               
                   
                 (MMIC Inductor) 
                 (BW Inductor) 
                 Competitor C 
               
               
                   
                 (3 modes) 
                 (3 modes) 
                 Amplifier 
               
               
                   
                   
               
             
          
           
               
                 Urban environ. 
                 20.1 mA 
                 19.6 mA 
                 21.8 mA 
               
               
                 Suburban environ. 
                 42.2 mA 
                 41.5 mA 
                 46.4 mA 
               
               
                   
               
             
          
         
       
     
         [0065]    The first column is MDLS using a spiral inductor (MMIC Ind), the second column is MDLS using a bonded wire inductor (BW Ind), and the third column is a conventional power amplifier. 
         [0066]    The first row is values for average current using standards for simulating an urban environment. The second row is values for simulating a suburban environment. The lowest average current of 19.6 mA is for a bonded wire MDLS power amplifier in an urban environment. 
         [0067]      FIG. 13  illustrates the relative die area of this invention in comparison to conventional competitors. 
         [0068]    Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Technology Classification (CPC): 7