Patent Abstract:
A low side clamp circuit has a control portion, a sense portion, and a clamp portion. When the sense portion detects that the input voltage of an output stage of a buffer has gone below a threshold voltage, it triggers the control portion to quickly turn on a clamp transistor (in the clamp portion) to clamp the output voltage to the clamp voltage. The control portion and sense portion have cross-coupled transistors that create increased speed and a sharp response with little or no voltage offset with a wide range of load currents. A clamp current source draws current through a resistor coupled in series between the base of the output transistor in the control portion and the collector of the output transistor in the sense portion. The clamp current is set to ClLo/R, where ClLo is the clamp voltage. A high side clamp is also described.

Full Description:
FIELD OF THE INVENTION 
     This invention relates to voltage clamps and, in particular, to a fast and accurate low-side voltage clamp circuit that sets the minimum voltage at an output of another circuit. 
     BACKGROUND 
     In certain applications, it is desirable to control the highest level and the lowest level of an input signal. This is referred to as high-side and low-side clamping. High-side clamping may be used to limit the input signal to a device to avoid damage. Such a device may be an analog-to-digital converter (ADC). If the input signal is a differential signal, low-side clamping may be used to create a symmetrical differential input signal around a common mode voltage when the high-side is clamped. The clamping also limits the maximum range input signal to the ADC. Low-side clamping may also be used to set a minimum voltage into a downstream device to ensure proper operation of the downstream device. 
       FIG. 1  illustrates a buffer  10  (a driver) receiving an analog differential input signal (IN+ and IN−), assumed to be sine waves. The buffer  10  generates analog differential output signals AIN+ and AIN− that are clamped for receiving by a particular ADC  12 . The user selects the particular ADC  12  and may select the clamping requirements for the ADC  12  by providing certain control signals to the ClHi (clamp high-side) input terminal and Vcm (common mode voltage) input terminal of the buffer  10 . In one embodiment, the buffer  10  may automatically adjust the low-side clamp voltage, since the high-side clamp and low-side clamp voltages are assumed to be symmetrical around the common mode voltage. The dashed lines above and below the sine waves signify the high-side and low-side clamp voltages. Any input signal above or below the clamp voltages is clamped to the respective clamp voltage. 
       FIG. 2  illustrates a conventional low-side clamp circuit  16  coupled to an emitter follower output stage  17  of a buffer, such as buffer  10 . An input signal Vin at terminal  18  is coupled to the base of the NPN transistor QN 1 . Current flows through resistor R 1 , transistor QN 1 , and transistor QN 2  between the supply voltage Vcc and ground. A high gain differential amplifier  20  has an inverting input coupled to a reference voltage Vref and a non-inverting input coupled to the resistor R 1 . The output of the differential amplifier  20  is coupled to the base of transistor QN 2 . The differential amplifier  20  uses feedback to control the current through transistor QN 2  and resistor R 1  such that the voltage at the resistor R 1  equals the reference voltage Vref. The amplifier  20  maintains a constant collector current for transistor QN 1 . 
     The output voltage Vout is clamped to a desired low-side clamp voltage (ClLo) when Vin-Vbe tries to go below the clamp voltage. The user or the buffer sets ClLo by coupling the value ClLo+Vbe to the base of transistor Q 2 C. ClLo+Vbe is generated by a conventional voltage source. The transistor Q 2 C is connected in parallel with transistor QN 1  by sharing its emitter and collector regions. The transistors are scaled to have the same current density when on. Therefore, they may have different areas to cause them to conduct different currents with the same Vbe. The transistor Q 2 C turns on when the voltage at its emitter reaches ClLo and supplies current to the load connected to the output terminal  22 . Thus, the output voltage Vout cannot go below ClLo, and Vout is the maximum of ClLo or Vin-Vbe. The output impedance of transistor Q 2 C limits the accuracy of the clamp voltage. 
     One problem with the clamp circuit  16  is that is does not have a sharp response as Vin-Vbe approaches the clamp voltage, due to the clamp transistor Q 2 C not having a precise turn-on voltage. A sharp and accurate response is desired for an accurate low-side clamp voltage, especially when used in a buffer for a precision ADC. 
     Another problem with such “voltage mode” clamp circuits is that the clamp voltage, if too low, may cause a current source in the circuit that generates the value ClLo+Vbe to saturate. This creates a voltage offset in the clamp circuit. 
     Another problem with conventional low-side clamp circuits is that a varying offset between the intended clamp voltage and the actual clamp voltage may occur with varying load currents when the output is clamped. 
     What is needed is an accurate low-side clamp circuit with a sharp response to an input voltage falling below the clamp voltage and which can generate a very low clamp voltage. 
     SUMMARY 
     A low-side clamp circuit is disclosed. Bipolar transistors are used in the example, but other types of transistors may be used. The clamp circuit comprises a control portion, a sense portion, and a clamp portion. When the sense portion detects that the input voltage of an output stage of a buffer has gone below a threshold voltage, it triggers the control portion to quickly turn on a clamp transistor (in the clamp portion) to clamp the output voltage to the clamp voltage. There is very little current flow through the sense circuit when the clamp transistor is off. 
     The control portion and sense portion have cross-coupled transistors that bring about the increased speed and sharp response with little or no voltage offset with a wide range of load currents. The base of the sense portion output transistor is coupled to the collector of the control portion output transistor, and the collector of the sense portion output transistor is coupled to the base of the control portion output transistor via a resistor. 
     Instead of a clamp voltage being generated by a voltage source, a clamp current source is used, which draws current through the resistor coupled in series between the base of the output transistor in the control portion and the collector of the output transistor in the sense portion. Since the minimum voltage at the base of the output transistor in the control portion is a Vbe above ground, the clamp current source will not saturate under any condition. The clamp current is set to ClLo/R. Various other advantages arise by using a current controlled clamp circuit, including the ability to compensate for offsets with varying load currents. 
     Various other embodiments are described. One alternative circuit compensates for base currents in the sense portion siphoning off current in the control portion so that a high current output does not cause an offset voltage. Another alternative circuit compensates for voltage drops across the resistor to avoid an off set. Another alternative circuit places a diode between the clamp current source and a node in the control portion of the clamp circuit to prevent a reverse breakdown of the base-emitter junction of the clamp transistor in the event that the low-side clamp voltage is set to high. Features of the various circuits may be combined together. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a buffer having high-side and low-side clamps, where the buffer may contain the present invention. 
         FIG. 2  illustrates a conventional low-side clamp transistor connected in parallel with an output transistor in an output stage of a buffer. 
         FIG. 3  illustrates a low-side clamp in accordance with one embodiment of the invention, where the clamp has a sharp and accurate response even with varying load currents. The clamp may be connected to the output stage of  FIG. 2 . 
         FIG. 4  illustrates an improvement to the clamp of  FIG. 3  by adding a circuit to compensate for the base currents of transistors Q 2 C and Q 3 B. 
         FIG. 5  illustrates an improvement to the clamp of  FIG. 3  by adding a circuit to compensate for the base current of transistor Q 4 B. 
         FIG. 6  illustrates an improvement to the clamp of  FIG. 3  by adding a circuit to compensate for variations in voltage drop across the resistor due to the base current in the control portion. 
         FIG. 7  combines the techniques of  FIGS. 3-6  to minimize offset. 
         FIG. 8  illustrates a current source circuit, using a current minor and a current comparator, that may be used to generate the clamp current signal. 
         FIG. 9  illustrates a clamp circuit combining the circuit of  FIG. 8  with the circuit of  FIG. 7  plus the addition of diodes that protect the clamp transistor. 
         FIG. 10  is a variation of the circuit of  FIG. 9 . 
     
    
    
     Elements that are the same or equivalent are labeled with the same numeral. 
     DETAILED DESCRIPTION 
       FIG. 3  illustrates a low-side clamp circuit, in accordance with one embodiment of the invention, having a control portion  30 , a sense portion  32 , and a clamp portion  34 . The collector and emitter of the clamp transistor Q 2 C are connected across the output transistor QN 1  in  FIG. 2 , in one embodiment, or may share the collector and emitter of the output transistor QN 1 . In other embodiments, the clamp transistor Q 2 C may be connected across any transistor in an output voltage which is to be clamped. The output stage will typically be an emitter follower output stage. 
     In one embodiment, all the transistors in the control and sense portions are the same. In another embodiment, the areas of the transistors may be different to select the relative currents through the transistors. 
     The function of the circuit is to clamp the voltage at the output terminal  35  to the low-side clamp voltage ClLo, when the input voltage Vin ( FIG. 2 ) applied to the input terminal  18  of  FIG. 2  falls below ClLo+Vbe. The clamp transistor Q 2 C then turns on and supplies most or all of the current to the load connected to the output terminal  35 . 
     Transistors Q 3 B and Q 2 C are off and draw no current when there is no clamping action. The remaining transistors Q 3 A, Q 4 A, and Q 4 B draw only a small quiescent current when there is no clamping action. 
     The current through transistors Q 4 A and Q 3 A is set by the current source  36  generating current Io, so that their Vbe are fairly constant. The transistor Q 4 A has its collector shorted to its base to act as a diode. 
     When there is no clamping (transistor Q 3 B is off), the current through the transistor Q 4 B is set by the current source  38 , generating the current ClLo/R, and the base current of transistor Q 3 A. The current source  38  current is typically set by the user or the buffer to set the clamp voltage. The base of transistor Q 3 A is also connected to the current source  38 . The voltage at the base of the transistor Q 3 A is Vbe. The current ClLo/R generated by the current source  38  is set so that the voltage at the emitter of transistor Q 4 B is the low-side clamp voltage ClLo plus Vbe. The voltage across the resistor R is therefore ClLo. 
     Since the voltage at the emitter of transistor Q 4 B is ClLo+Vbe, the combined Vbe voltage drops of transistors Q 4 B and Q 4 A cause the voltage at the base of transistor Q 3 B to also be ClLo+Vbe. Since the bases and emitters of transistors Q 3 B and Q 2 C are made common, any input voltage Vin ( FIG. 2 ) below ClLo+Vbe will cause the emitters of transistors Q 3 B and Q 2 C to drop below ClLo, causing them to turn on and clamp the output terminal  35  at ClLo. 
     When transistor Q 3 B begins to turn on so will transistor Q 4 B, thus raising the base voltage of transistor Q 4 B and the emitter voltage of transistor Q 4 A. This raised emitter voltage is coupled to the bases of transistors Q 3 B and Q 2 C turning them on harder so as to provide a very fast and precise turn on threshold for the clamp transistor Q 2 C. 
     To reduce the current through the clamp circuit while allowing a high load current to flow through the clamp transistor Q 2 C, the area of transistor Q 3 B can be made much smaller than the area of transistor Q 2 C to obtain a 1:N ratio of the currents. In one embodiment, N equals 4. 
     The cross-coupling of the transistors Q 3 A and Q 3 B also substantially compensates for the varying Vbes of the transistors Q 4 B and Q 3 B as the current increases through these transistors during clamping. For example, during clamping when the current through transistors Q 4 B and Q 3 B has increased and their Vbes have increased, the summed voltage drop around the base-emitter loop of Q 4 B (up a Vbe), Q 4 A (down a Vbe), and Q 3 B (down a Vbe) is substantially constant despite the Vbes of transistors Q 4 B and Q 3 B increasing with increased current. Therefore, the clamp voltage at the output terminal  35  will be substantially the same at high load currents and low load currents, allowing the user to precisely set the clamp voltage by setting the current source  38  to generate a current of ClLo/R. 
     As seen, there is a sharper and more accurate response by the clamp circuit of  FIG. 3  compared to the circuit of  FIG. 2 . By using a current source  38  instead of a voltage source, ClLo can be made very low (close to ground), even with high current densities, without causing the saturation of any components forming part of a voltage source (where the saturation leads to offsets in the clamp voltage). 
       FIGS. 4-7  illustrate improvements to the circuit of  FIG. 3  by compensating for any offsets caused by the base currents in the control portion  30  and sense portion  32 . 
     The betas of the various transistors in  FIG. 3  are assumed to be 100 or higher. Therefore, the base currents will be about 1/100 th  of the collector currents. These small base currents in transistors Q 3 B and Q 4 B add some small error (offset) since they tap off current from the control portion  30  current path, which is designed for conducting a constant current Io (by current source  36 ). For the highest precision, such base currents, which vary during operation and with temperature, should be compensated for. 
       FIG. 4  illustrates an improvement to  FIG. 3  in that it compensates for the transistors&#39; Q 2 C and Q 3 B base currents being tapped off the emitter of transistor Q 4 A. A transistor Q 5  is connected in series with transistors Q 4 B and Q 3 B. PNP transistors Q 6 A and Q 6 B are connected as a current minor, and the collector of transistor Q 6 B is connected to the base of transistor Q 3 B. Transistors Q 5  and Q 3 B are matched so that they have the same base currents. The base current to transistor Q 5  is supplied by transistor Q 6 A, which causes the transistor Q 6 B to supply a proportional base current to the base of transistor Q 3 B. The size of transistor Q 6 B is selected to be N+1 the size of transistor Q 3 B to supply the base currents to both transistors Q 3 B and Q 2 C. In one example, transistor Q 2 C is four times (N=4) the size of transistor Q 3 B, so the size of transistor Q 6 B is five times the size of transistor Q 6 A. Therefore, no base current to transistors Q 3 B and Q 2 C is tapped off the current source  36  (generating Io) so that the current flow through transistors Q 4 A and Q 3 A is more constant. This results in stable Vbes of transistors Q 4 A and Q 3 B with varying output load currents and, thus, reduces any clamp voltage offset due to varying base currents (resulting from the varying load currents). 
     The base current of transistor Q 4 B also taps off current from the current source  36  and creates some small undesired offset due to the base current varying the current through the transistors Q 4 A and Q 3 A. The circuit of  FIG. 5  compensates for the base current of transistor Q 4 B by adding transistor Q 7 . The base of transistor Q 7  is connected to the collector of transistor Q 4 A, its collector is connected to the supply voltage, and its emitter is connected to the bases of transistors Q 4 A and Q 4 B. The current through transistor Q 7  supplies the base current to transistors Q 4 A and Q 4 B, where the base current is that needed to cause transistor Q 4 A to conduct the current Io. Therefore, rather than the current source  36  supplying all of the base current for transistor Q 4 B (as in  FIG. 3 ), it is only supplying 1/100 th  of that current to the base of transistor Q 7 . Thus, the current through transistors Q 4 A and Q 3 A is more constant despite variations in load currents. 
     The base current into transistor Q 3 A flows also through the resistor R and increases the voltage drop across the resistor R, causing the clamp voltage to rise (i.e., creates an offset between the actual clamp voltage during clamping and the desired clamp voltage). With a Io bias current of, for example, 1 mA, for a beta of 100, the base current into transistor Q 3 A may be 10 uA. Since the resistor R value is preferably high for minimal current consumption in the control portion  30 , such as 20 Kohms, the offset may be as much as 200 mV. 
       FIG. 6  compensates for this additional voltage drop across the resistor R by adding a matched value resistor R 2  between the bases of transistors Q 4 A and Q 4 B. The base current into transistor Q 4 A is supplied through the resistor R 2  to increase the voltage drop across resistor R 2  by the same amount that the voltage across resistor R decreases to compensate for the offset. Therefore, the clamp voltage does not change. 
     Any of the features described above for removing offset may be applied to the basic circuit of  FIG. 3 .  FIG. 7  illustrates the clamp circuit of  FIG. 3  modified to contain the compensation features of  FIGS. 4 ,  5 , and  6 . 
       FIG. 8  illustrates a current source  48  that may be used for the clamp current source  38  in  FIGS. 3-7 , although any other current source may be used for the current source  38 . The current source  48  contains two current sources  50  and  52 . The current source  50  (generating a current I 1 ) may be adjustable by the user and set to ClLo/R (previously described as the current generated by the current source  38 ) to select the clamp voltage. To prevent the clamp voltage from being set too low, such as a voltage that would cause the transistor QN 2  in the output stage  17  of  FIG. 2  to saturate during clamping, the current source  52  (generating a current I 2 ) is set to Vmin/R, where Vmin is fixed at the minimum allowable clamp voltage. By avoiding saturation of the transistor QN 2 , the transistor QN 2  can have quick recovery when the input voltage rises above the clamp voltage ClLo. The output current is therefore I 1  with a lower limit of I 2 . The operation of the remainder of the current source  48  would be easily understood by those skilled in the art. 
       FIG. 9  illustrates a clamp circuit combining the current source  48  of  FIG. 8 , with resistor R 3  added, and the clamp circuit of  FIG. 7 . In the event of a high output voltage and a low ClLo voltage, such as near ground, the diode D 2  prevents the clamp transistor Q 2 C and Q 3 B from exceeding a reverse breakdown base-emitter voltage. Since this is outside the intended region of the clamp operation, this is a fault condition. Under such a fault condition, the diode D 1  and resistor R 4  provide the extra current required so the ClLo can track the output. Without diode D 1  and resistor R 4 , the extra current would have to come out of the base of transistor Q 3 A. This would have resulted in a significant and undesirable increase in the collector current of transistor Q 3 A. While resistor R 4  may be nominally matched to resistor R, its value can be optimized to adjust the transistor Q 3 A collector current during such a fault condition. 
     The entire circuit of  FIG. 9  is preferably formed as a single integrated circuit. 
     As shown in  FIG. 10 , resistors R 3  and R 4  can be merged into a single resistor R 5  without loss of functionality. 
     The present invention may be part of the buffer  10  in  FIG. 1 . In the preferred embodiment, the buffer  10  of  FIG. 1  receives a high-side clamp voltage signal ClHi, set by the user, and a common mode signal Vcm, set by the user, identifying the intended midpoint between the differential input signals. The low-side clamp voltage (ClLo) is then automatically set by the buffer  10  by making the ClH 1  and ClLo symmetrical around Vcm. In another embodiment, the user sets ClLo directly by an external signal. 
     Although an embodiment of the invention has been shown as a low side clamp, all transistors in all embodiments may be formed of opposite conductivity types (NPN or PNP), with the ground and positive power supply reversed to form a high side clamp. 
     The clamping circuit may also be implemented with non-bipolar transistors, such as MOSFETs, or combinations of bipolar and non-bipolar transistors. The resistors may be replaced with any type of resistive element, including a MOSFET. Additional circuit elements may be inserted between the components shown in the examples. 
     While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications that are within the true spirit and scope of this invention.

Technology Classification (CPC): 7