Patent Abstract:
Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.

Full Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to microelectronic assemblies and, in particular, to substrates used in microelectronic assemblies and methods of fabricating such substrates. 
       BACKGROUND OF THE INVENTION 
       [0002]    Circuit panels or substrates are widely used in electronic assemblies. Typical circuit panels commonly include a dielectric element in the form of a sheet or plate of dielectric material having numerous conductive traces extending on the sheet or plate. The traces may be provided in one layer or in multiple layers, separated by layers of dielectric material. The circuit panel or substrate may also include conductive elements such as via liners extending through the layers of dielectric material to interconnect traces in different layers. Some circuit panels are used as elements of microelectronic packages. Microelectronic packages generally comprise one or more substrates with one or more microelectronic devices such as one or more semiconductor chips mounted on such substrates. The conductive elements of the substrate may include the conductive traces and terminals for making electrical connection with a larger substrate or circuit panel, thus facilitating electrical connections needed to achieve desired functionality of the devices. The chip is electrically connected to the traces and hence to the terminals, so that the package can be mounted to a larger circuit panel by bonding the terminals to contact pads on the larger circuit panel. For example, some substrates used in microelectronic packaging have terminals in the form of pins extending from the dielectric element. 
         [0003]    Despite considerable efforts devoted in the art heretofore to development of substrates and methods for fabricating such substrates, further improvement would be desirable. 
       SUMMARY OF THE INVENTION 
       [0004]    One aspect of the present invention provides a method for fabricating a substrate for a microelectronic package. The method desirably comprises forming a molded dielectric layer which surfaces are coplanar with bases and tips of conductive pins of the substrate. Conductive traces may be formed on one or both sides of the dielectric layer. 
         [0005]    Other aspects of the present invention provide substrates such as those fabricated using the disclosed method. Still further aspects of the invention provide microelectronic packages and assemblies which include one or more such substrates. 
         [0006]    The Summary is neither intended nor should it be construed as being representative of the full extent and scope of the present invention, which additional aspects will become more readily apparent from the detailed description, particularly when taken together with the appended drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a flow diagram illustrating a method in accordance with one embodiment of the present invention; 
           [0008]      FIGS. 2A-2I  are schematic, plan ( FIGS. 2A and 2I ), bottom ( FIGS. 2D and 2F ), and cross-sectional views ( FIGS. 2B-2C ,  2 E, and  2 G- 2 H) of portions of a substrate during successive stages of the method of  FIG. 1 ; 
           [0009]      FIGS. 3A-3B  are schematic, cross-sectional views of portions of a substrate fabricated during successive stages of a method according to a further embodiment of the invention; 
           [0010]      FIGS. 4A-4D  are schematic, cross-sectional views of portions of a substrate fabricated during successive stages of a method according to another embodiment of the invention; 
           [0011]      FIGS. 5A-5C  are schematic, cross-sectional views of portions of a substrate fabricated during successive stages of a method according to yet another embodiment of the invention; 
           [0012]      FIGS. 6A-6D  are schematic, cross-sectional views of portions of a substrate fabricated during successive stages of a method according to still another embodiment of the invention; 
           [0013]      FIG. 7A-7B  are schematic, cross-sectional views of portions a substrate fabricated during successive stages of a method according to one more embodiment of the invention; 
           [0014]      FIGS. 8A-8D  are schematic, cross-sectional views of portions a substrate fabricated during successive stages of a method according to yet further embodiment of the invention; and 
           [0015]      FIGS. 9A-9D  are schematic, cross-sectional views of exemplary microelectronic structures using the substrates fabricated in accordance with the method of  FIG. 1 . 
       
    
    
       [0016]    Herein, identical reference numerals are used, where possible, to designate identical elements that are common to the figures. The images in the drawings are simplified for illustrative purposes and are not depicted to scale. 
         [0017]    The appended drawings illustrate exemplary embodiments of the invention and, as such, should not be considered as limiting the scope of the invention that may admit to other equally effective embodiments. 
       DETAILED DESCRIPTION 
       [0018]      FIG. 1  depicts a flow diagram illustrating a method  100  for fabricating a substrate having a molded dielectric layer in accordance with one embodiment of the present invention. The method  100  includes processing steps performed during fabrication of the substrate. In some embodiments, these processing steps are performed in the depicted order. In alternate embodiments, at least two of these steps may be performed contemporaneously or in a different order. Sub-steps and auxiliary procedures (e.g., substrate transfers between processing reactors, substrate cleaning sub-steps, process control sub-steps, and the like) are well known in the art and, as such, herein are omitted. Cross-sectional views in the drawings are arbitrarily taken along a centerline  1 - 1  (shown in  FIG. 2A  only) of a conductive plate of a substrate being fabricated using the method  100 . 
         [0019]    The method  100  starts at step  102  and proceeds to step  104 . A method according to one embodiment of the invention uses a conductive plate  200  having a perimeter  202  ( FIG. 2A ). In this particular embodiment, the plate  200  comprises layers  204  and  206  of electrically conductive principal metal (e.g., copper (Cu)) and a conductive barrier layer  208 , such as a nickel (Ni) layer ( FIG. 2B ). A thickness of the plate  200  is generally selected in range from about 10 to 600 μm (e.g., 50 or 100 μm), whereas the layers  204 ,  206 , and  208  typically have thicknesses of about 5 to 300 μm, 5 to 300 μm, and 0.1 to 3 μm, respectively. In one exemplary embodiment, the thicknesses of the layers  204 ,  206 , and  208  are 15, 50, and 1 μm, respectively. 
         [0020]    At step  106 , a plurality of conductive pins  210  and at least one optional spacer  212  are formed on the plate  200  ( FIG. 2C ). Each pin  210  comprises a base  210 A and a tip  210 B, and the spacer  212  comprises a base  212 A and a tip  212 B. Widths of the bases  210 A,  212 A and tips  210 B,  212 B are generally selected in a range from about 50 to 1000 μm, for example, 200-300 μm. 
         [0021]    The spacer  212  generally has a closed-loop wall-like form factor and is disposed around an individual section of plate  200  or near the perimeter  202  (as shown), thus surrounding at least some of the pins  210 , as illustratively depicted in a bottom plan view ( FIG. 2D ) taken in the direction of arrow  219  in  FIG. 2C . In the particular embodiment, the spacer  212  comprises slots  218  (four slots  218  are arbitrarily shown) which may be used during a molding process of step  108 , as discussed below in reference to  FIG. 2E . In one embodiment, the pins  210  and spacer  212  are fabricated from the layer  206  by performing an etch process that uses the barrier layer  208  as an etch stop layer to determine a duration of the etch process. 
         [0022]    The pins  210  are formed at locations facilitating connectivity between elements of an electrical circuit of the substrate being fabricated. Such pins may have different form factors and be organized, for example, in one or more grid-like patterns having a pitch in a range from 100 to 10000 μm (e.g., 400-650 μm). 
         [0023]    In the next stage of the method, at step  108 , a molded dielectric layer  220  is formed on the plate  200  ( FIGS. 2E-2G ). In the molding process, a flowable composition is introduced between the pins  210  and cured to form the dielectric layer. The composition may be essentially any material which will cure to a solid form and form a dielectric. 
         [0024]    For example, compositions which cure by chemical reaction to form a polymeric dielectric, such as epoxies and polyimides may be used. In other cases, the flowable composition may be a thermoplastic at an elevated temperature, which can be cured to a solid condition by cooling. Preferably, the layer  220 , after molding, forms binding interfaces with features of the plate  200 . The composition may further include one or more additives influencing properties of the layer  220 . For example, such additives may include particulate materials such as silica or other inorganic dielectrics, or fibrous reinforcements such as short glass fibers. 
         [0025]    During the molding processes, the plate  200  is sandwiched between a press plate  214  and a counter element  216  (shown using phantom lines) which in this embodiment is part of a molding tool ( FIG. 2E ). The counter element  216  is abutted against the tips  210 B of the pins  210  and the flowable molding composition is injected or otherwise introduced into the space between the plate  200  and counter element  216 . 
         [0026]    In the particular embodiment depicted in  FIG. 2E , the molding composition is injected through at least one opening, or gate,  217  in the counter element  216  (as shown) and/or press plate  214 . Slots  218  are used as an escape passage for trapped air, and may also vent excess material of the molding composition. Upon completion of the molding process, the press plate  214  and the counter element  216  are removed ( FIG. 2G ). Ordinarily, the tips  210 B of the pins are free of molding composition at the completion of the molding step. In some instances, a thin film of molding composition may overlie the tips of some or all of the pins. If this occurs, the thin film can be removed by exposing the bottom surface  226  ( FIG. 2G ) of the molded dielectric layer to a brief plasma etching or ashing process which attacks the molded dielectric. 
         [0027]    In a variant of the molding step, the composition may be injected through the slots  218  in the spacer, and openings  217  in the counter element may serve as a vent. Alternatively, one or more openings (not shown) can be formed through layers  204  and  208  of the plate, and these openings may serve either as injection openings for the composition or as vents. In yet another variant, the composition may be provided as a mass disposed on the tips of the pins or on counter element  216  before the counter element is engaged with the tips of the pins, so that the composition is forced into the spaces between the pins as the pins are brought into abutment with the counter element. In another variant, when the plate  200  includes multiple spacers  212  defining individual sections of the plate, the openings  217  may selectively be associated with such sections. 
         [0028]    In another embodiment, the plate  200  may be a portion of a larger frame  242  incorporating a plurality of the plates  200  ( FIG. 2F ). As depicted, the frame  242  illustratively includes sprocket holes  244  and a peripheral wall  246 , which upper surface is coplanar with the tips  210 B and  212 B in the component plates  200 . In this embodiment, the press plate and counter element of the molding tool are extended over the plate  242  and the spacer  246 , respectively. Then, during the molding process, the molding composition is introduced simultaneously into the spaces between the component plates  200  and counter element  216  through individual gates  217  flowably coupled to a runner system of the molding tool. After the press plate and counter element are removed upon completion of the molding process, the component plates  200  may be separated (e.g., cut out) from the frame  242 . Alternatively, such separation may occur after step  110  discussed below in reference to  FIGS. 2H-2I . 
         [0029]    The molding step forms the dielectric element, or dielectric layer, with a bottom surface  226  coplanar with the tips  210 B of the pins and coplanar with the tip  212 B of the spacer ( FIG. 2G ). The molding step also forms the dielectric element with a top surface  228  in engagement with the layer  208  and hence coplanar with the bases  210 A of the pins and the base  212 A of the spacer. 
         [0030]    At step  110 , conductive traces  230  are formed from the layers  204  and  206  using, e.g., an etch process ( FIGS. 2H-2I ). Together with the pins  210 , the traces  230  form an electrical circuit of a substrate  240  fabricated using the method  100 . Each trace  230  may be connected to at least one pin  210  and/or to at least one other trace. However, some traces may “float”, i.e., be electrically disconnected from pins and other traces. Likewise, one or more of the pins may remain unconnected to traces, although typically most or all of the pins are connected to traces. 
         [0031]    At least one trace  230  may be a peripheral trace  230 A having a closed-loop pattern and surrounding at least some of pins or other traces as illustratively shown in  FIG. 2I , where such traces are depicted using solid lines connected to bases of the respective pins or other traces. In the depicted embodiment, the peripheral trace  230 A is disposed on the spacer  212 . The peripheral trace may further comprise contact areas  232  having greater widths than other portions of the trace. In operation, the peripheral traces, as well as the spacers  212 , may reduce electromagnetic interference (EMI) between electrical circuits present on the same or adjacent substrates. 
         [0032]    The traces  230  may have different widths, including the widths which are smaller than the widths of the bases  210 A and tips  210 B of the pins  210  (as shown in  FIGS. 2H-2I ), thus facilitating fabrication of the substrate  240  having high routing density. Generally, the widths of the traces  230  are selected in a range from about 5 to 100 μm (e.g., 20-40 μm), however, portions of traces (e.g., contact areas  234 ) or some traces may have widths greater than 100 μm. 
         [0033]    A substrate  340 A according to a further embodiment has a recess  302  formed in a central region, recess  302  being open to the bottom surface  226  of the dielectric layer. Such a substrate can be formed by a process substantially as discussed above with reference to  FIGS. 2A-2I , except that the pin-forming step is conducted so that no pins are formed in the central region, and the molding step is modified by using a counter element (not shown) having a projection extending upwardly in the central region. 
         [0034]    In a substrate  340 B of the embodiment of  FIG. 3B , the recess  306  extends all the way to the top surface  228  and thus forms an opening extending through the dielectric layer. Such a recess may be formed by a projection on the counter element which engages the plate during the molding process. In the embodiment of  FIG. 3B , the traces do not extend across the recess. However, some or all of the traces may extend across the recess. 
         [0035]    Alternatively, the dielectric layer may be fabricated using a counter element without such a projection, so that the entire bottom surface as molded is flat, and then machined or etched to form the recess  302  or opening  306 . In further variants, two or more recesses may be provided in the dielectric layer. Also, the recess need not be provided in a central region of the substrate. 
         [0036]    A substrate  440  according to a further embodiment of the invention is fabricated using a conductive plate  400  having a single layer  406  of the principal metal (e.g., Cu and the like) ( FIG. 4A ). Conductive pins  410  and an optional spacer  412  are formed on the plate  400  using an etch process or a plating process ( FIG. 4B ). The dielectric layer  220  ( FIG. 4C ) is fabricated using the process described above in reference to  FIG. 2E . Then, conductive traces  430 , including optional peripheral traces  430 A, may be formed from the plate  400  using an etch process, thereby completing a process of fabricating the substrate  440  ( FIG. 4D ). 
         [0037]    A substrate according to yet another embodiment of the invention is fabricated using two conductive plates  200  and  500  ( FIG. 5A ). In one embodiment, the plate  500  comprises a single layer  504  of the principal metal. In an alternate embodiment (not shown), a layer of conductive bonding material may be formed on an upper surface  506  of the layer  504 . In one particular embodiment ( FIG. 5B ), the plate  500  is connected to the tips  210 B of the pins  210  using a conventional metal-coupling process, such as thermosonic or ultrasonic bonding, eutectic bonding, solder bonding or the like. Then, during the molding process, the plate  500  serves as a counter element. In the molding operation, the polymer is injected between the plates  200  and  500 . Alternatively, the dielectric layer is molded as described above in reference to  FIG. 2E , and then the plate  500  is disposed on a bottom surface of the molded dielectric layer and, using metal-coupling process, is connected to the tips of the pins. 
         [0038]    Then, conductive traces  530  are fabricated from the plate  500  ( FIG. 5C ). The traces  530  may be formed before, after, or contemporaneously with the traces  230  using the same technique (i.e., etch process). The traces  530  may include optional peripheral traces (one peripheral trace  530 A is illustratively shown). Together, the pins  210  and traces  230 ,  530  form an electrical circuit of the substrate  540 . 
         [0039]    A process according to a further embodiment uses two conductive plates. Illustratively, such plates are multi-layered plates  200 A and  200 B ( FIG. 6A ), each of which includes principal metal layers  204  and  206  and etch stop layer  208  similar to the layers discussed above with reference to the plate  200  of  FIG. 2B . In alternate embodiments, at least one of these plates may be formed from a single layer of the principal metal, such as Cu. 
         [0040]    Pins  210  are fabricated in the plate  200 A as discussed above in reference to  FIG. 2C , and, similarly, pins  610  having bases  622  and tips  624  are fabricated in the plate  200 B ( FIG. 6B ). The locations of the pins  610  are selected so that, when the plates  200 A and  200 B are assembled together, the pins  210  and  610  can be mutually interspersed with each other in at least one region of a substrate  640 . For example, pins  210  can be provided as a first regular grid pattern having a particular pitch, whereas pins  610  can be provided as a second regular grid pattern having the same pitch. 
         [0041]    Since the pins are tapered (i.e., tips of the pins are smaller than their bases), in such a substrate the interspersed pins may be disposed closer to one another than the pins formed on the same plate, thus increasing density of the conductive pins in the substrate being fabricated. The tips  210 B of the pins on the first plate  200 A are abutted against the second plate  200 B, whereas the tips  610 B of the pins on the second plate are abutted against the first plate  200 A. Then, using a conventional metal-coupling process, the tips  210 B of the pins  210  are connected to the plate  200 B and the tips  610 B of the pins  610  are connected to the plate  200 A, respectively. 
         [0042]    The dielectric layer  220  is molded in the space between the plates ( FIG. 6C ) using a process discussed above in reference to  FIG. 2E  where one of the plates may be used as a counter element. Using an etch process, the layers  204  and  208  of the plates  200 A,  200 B are patterned to form the traces  230  and  630  (including optional peripheral traces  230 A and  630 A) of the substrate  640 . 
         [0043]    A process according to another embodiment uses the press plate and counter element forming, around a perimeter of the substrate being fabricated, an enclosure for the molding composition. The substrates may be fabricated with a peripheral spacer (substrate  740 A in  FIG. 7A  and substrates in  FIGS. 9C-9D ), as well as without the spacer (substrate  740 B in  FIG. 7B ). 
         [0044]    A process according to yet further embodiment uses a single plate  804  ( FIG. 8A ). The plate  804  is formed from the principal metal (e.g., copper plate) to a thickness from about 10 to 300 μm. Then, a barrier layer  808  (e.g., Ni barrier layer) is deposited on a bottom surface of the plate  804  ( FIG. 8B ). The barrier layer  808  is patterned to form, at pre-determined locations, pads  805  for conductive pins and optional spacers ( FIG. 8C ). Conductive pins  810  and spacers  812  may be formed on the pads  805  using, for example, a plating process ( FIG. 8D ). In the depicted embodiment, a resulting structure includes a peripheral spacer having slots  818 . Such a structure may further undergo molding and etching processes discussed above in reference to  FIGS. 2D-2I . Structures with plates and pins can be formed in other ways as well. For example, such a structure can be formed by coining a single metal layer or a multi-layer metallic laminate. 
         [0045]    Substrates fabricated according to yet further embodiments the method of  FIG. 1  may comprise combinations of features discussed above in reference to the substrates  240 ,  340 A- 340 B,  440 ,  540 ,  640 , and  740 A- 740 B. For example, the substrates  440 ,  540 ,  640 , and  740 A- 740 B may include recesses and/or openings, like those included in substrates  340 A- 340 B. 
         [0046]      FIGS. 9A-9D  depict a series of schematic, cross-sectional views of exemplary structures using the substrates fabricated in accordance with the method of  FIG. 1 . 
         [0047]    Microelectronic elements, or devices, may be mounted on the substrates using techniques such as a ball-bonding and/or wire-bonding technique. In  FIGS. 9A-9D , the devices adapted for mounting using the ball-bonding and wire-bonding techniques are collectively denoted using reference numerals  906  and  908 , respectively. Similarly, such techniques may be used for connecting the substrates stacked on one another or juxtaposed substrates. 
         [0048]    More specifically, the  FIGS. 9A ,  9 B, and  9 C depict exemplary microelectronic structures or units  901 ,  902 , and  903  each comprising one substrate  240 ,  540 , and  640 , respectively. In the embodiment depicted in  FIG. 9A , the substrate  240  is disposed on and connected to a circuit panel  912  and includes an electrically conductive EMI shield  910 . The tip ends of the pins of substrate  212  are solder bonded to contact pads of circuit panel  912 . The microelectronic devices  906 ,  908  and the EMI shield  910  are mounted on an upper surface  241  of the substrate  240 . The EMI shield  910  is ball-bonded to the peripheral trace  230 A of the substrate and, as such, electrically connected to the spacer  212 . Herein, the spacer  212  is further connected to ground contact pads  914  of the circuit panel  912 . For example, the unit including substrate  240 , devices  906  and  908  and shield  910  may be mounted to panel  912  using solder-bonding techniques commonly used for surface-mounting microelectronic elements on circuit boards. In embodiments shown in  FIG. 9B and 9C , the devices  906  and  908  are mounted on both sides of the substrates  540  and  640 , respectively. 
         [0049]    The substrates discussed above may be interconnected to form multi-substrate structures.  FIG. 9D  depicts an exemplary assembly, or package,  904  comprising two stacked units  640 A and  640 B, each of which includes a substrate as discussed above. One of the stacked units (denoted using a reference numeral  640 B) has a recess formed in the molded dielectric layer of the substrate. Thus substrate of the other unit  640 A constitutes a panel having a top surface, contact pads exposed at the top surface of said panel, and an additional circuit element  906  mounted to said panel and extending upwardly therefrom. The dielectric layer of unit  640 B overlies the top surface of the panel in unit  640 A. The additional circuit element  906  is received in the recess. The tip ends of the pins in unit  640 A are bonded to the contact pads of said panel. Illustratively, the peripheral lines and a portion of the traces of the stacked substrates of the units  640 A and  640 B are also connected using such a technique to form the assembly  904 . In a variant, the assembly  904  may comprise more than two substrates, or the substrates of different types. 
         [0050]    Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

Technology Classification (CPC): 7