Patent Abstract:
The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Full Description:
THE FIELD OF THE INVENTION  
         [0001]    The present invention relates to semiconductor integrated circuits and, more particularly, to fabrication of resistors during integrated circuit processing.  
         BACKGROUND OF THE INVENTION  
         [0002]    Integrated circuit designers use a variety of components to implement desired circuit functionality. These components may include bipolar and field-effect transistors, junction diodes, capacitors, and resistors.  
           [0003]    Resistors are used for a wide variety of circuit applications in which resistance values are required to be quite large. For example, a resistor might be used to limit the current between its terminals for a given applied voltage. Such an applied voltage might be due to electrostatic discharge (ESD) which can damage integrated circuits. By choosing a large resistance value, the current produced by an ESD pulse of given voltage can be reduced, affording more protection to the integrated circuit. Resistors can also be used in reference circuits such as a bandgap voltage reference or as feedback elements in conjunction with operational amplifier circuits. Another application of the integrated circuit resistor is its use with an integrated circuit capacitor to form a characteristic time constant for signal frequency filtering applications. In order to pass very low frequencies, the desired product of the resistance and capacitance might be appreciable, demanding large resistance values. In low-power applications, large resistors are useful for limiting currents thereby reducing power consumption.  
           [0004]    Integrated circuit resistors can be fabricated by the deposition of thin-film materials including nichrome or tantalum, but such implementations add process steps to a standard complementary metal-oxide-semiconductor (CMOS) process. Integrated circuit resistors can also be fabricated using standard CMOS processing steps. For example, resistors can be created from the polysilicon used to form the gate regions of metal-oxide-semiconductor field-effect transistors (MOSFETs), or from the diffused well regions in which MOSFETs are later created, or from the ion-implantation step used to create source and drain diffusion regions of MOSFETs.  
           [0005]    Since implementing a resistor uses area on an integrated circuit die, it is desirable to increase the resistance obtained using a given circuit area without adding complexity to a standard CMOS process.  
         SUMMARY OF THE INVENTION  
         [0006]    The primary object of this invention is to increase the resistance obtained from a diffusion resistor without increasing the integrated circuit area dedicated to implement the resistance and without increasing the complexity of the integrated circuit process.  
           [0007]    In particular, the present invention describes a method for utilizing the ion-implanted dopants which form the source and drain regions of n-channel and p-channel transistors to form a diffusion resistor composed of a first dopant and of banded regions of a counterdopant. In this way, the resistance of a diffusion resistor can be increased without increasing the area on the integrated circuit die occupied by the resistor or increasing the process complexity of a standard CMOS process.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1 is a schematic cross-sectional view of a supporting substrate upon which a first dopant region has been created in an active area region, and a masking layer has been formed.  
         [0009]    [0009]FIG. 2A shows the view of FIG. 1 after the masking layer is patterned and etched, and after counterdopant regions have been formed.  
         [0010]    [0010]FIG. 2B shows a schematic top view of the preferred embodiment of the resistor.  
         [0011]    [0011]FIG. 2C shows a schematic top view of an alternative embodiment of the resistor.  
         [0012]    [0012]FIG. 2D shows a schematic top view of an alternative embodiment of the resistor.  
         [0013]    [0013]FIG. 2E shows a schematic cross-sectional view of an embodiment used as an alternative to FIG. 2A.  
         [0014]    [0014]FIG. 3 shows the view of FIG. 2A after an insulating layer and contacts have been formed.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]    In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.  
         [0016]    In FIG. 1, a cross-sectional view of a semiconductor substrate  10  is schematically shown. In the preferred embodiment, this substrate  10  is a p-type silicon wafer, however other types of wafers may also be used, including an n-type silicon wafer, a silicon-on-insulator (SOI) wafer, or a wafer with an epitaxially grown surface layer. Using conventional CMOS process steps, active areas  11  are defined in which NMOS and PMOS field-effect transistors will be fabricated. A thick insulating Field-OXide (FOX)  12  is grown outside of these active areas  11  to isolate the transistors from each other. Active areas  11  are also defined where diffusion resistors will be fabricated. The shape of such active areas  11  will correspond to the diffusion resistor&#39;s shape on the surface of the semiconductor substrate  10 .  
         [0017]    Referring still to FIG. 1, a first dopant region  13  is formed within an active area  11 . In the preferred embodiment, first dopant region  13  is formed by the same ion-implantation step used to simultaneously create n-type heavily doped (n + ) NMOS transistor source/drain regions and n +  ohmic contacts (guardbars) to contact n-type diffused well (n-well) regions created in substrate  10  as part of a conventional n-well CMOS process flow.  
         [0018]    Referring still to FIG. 1, a masking layer  14  has been deposited everywhere on the wafer of FIG. 1. This photoresist (PR) masking layer  14  is used to mask the entire wafer except those regions defining a MOS source/drains, those regions defining ohmic contacts (guardbars) with doping type opposite to that of first dopant region  13 , and those regions where a counterdopant is to be introduced into the first dopant region  13 .  
         [0019]    In the cross-sectional view of FIG. 2A, the masking layer  14  has been patterned to form at least one opening  21  at least partially over the first dopant region  13 . Any opening  21  over first dopant region  13  has been used to define a counterdopant region  22  which at least partially intersects the first dopant region  13 . This differs from a conventional CMOS process flow, in which openings  21  in masking layer  14  are created only to define MOS source/drains and ohmic contacts (guardbars) with doping type opposite to that of first dopant region  13 . In a conventional CMOS process flow, openings  21  do not intersect the first dopant region  13 .  
         [0020]    In FIG. 2A, the approximate depth of the first dopant region  13  is indicated by first dopant depth  23 , and the approximate depth of the counterdopant region  22  is indicated by counterdopant depth  24 . These depths are approximate because the diffused junctions themselves are not abruptly defined, but graded. Also, these depths include a depletion region formed at the junction interface which depends on the voltage applied to the integrated circuit resistor.  
         [0021]    In the preferred embodiment, any counterdopant region  22  is created by the same ion-implantation step used to create PMOS source/drain diffusions and p-type heavily doped (p + ) ohmic contact regions (guardbars) to contact substrate  10 .  
         [0022]    Referring still to FIG. 2A, it should be well understood to one skilled in the art that n-type starting material could also be used as the substrate  10 . In this first alternative embodiment, the first dopant region  13  may be created with the same p +  ion-implantation step used to create PMOS source/drain diffusions and p +  guardbars to contact p-type diffused well (p-well) regions created in substrate  10  as part of a conventional p-well CMOS process flow. In this first alternative embodiment, the masking layer  14  defining openings  21  may be the same masking layer used to define NMOS source/drain diffusions and n +  guardbars to contact substrate  10 . In this first alternative embodiment, any counterdopant region  22  may be created by the same ion-implantation step used to create NMOS source/drain diffusions and n +  guardbars to contact substrate  10 .  
         [0023]    Referring still to FIG. 2A, it should be well understood by one skilled in the art that first dopant region  13  could be contained within a p-well created by conventional p-well CMOS processing using n-type wafer as the starting material for substrate  10 . In this second alternative embodiment, the first dopant region  13  may be created with the same ion-implantation step used to create NMOS source/drain diffusions and n +  guardbars to contact the n-type substrate  10 . In this second alternative embodiment, the masking layer  14  defining openings  21  may be the same masking layer used to define PMOS source/drain diffusions and p +  guardbars to contact a p-well region created in substrate  10  as part of a conventional p-well process flow. In this second alternative embodiment, any counterdopant region  22  may be created by the same ion-implantation step used to create PMOS source/drain diffusions and p +  guardbars to contact a p-well region created in substrate  10  as part of a conventional p-well process flow.  
         [0024]    Referring still to FIG. 2A, it should be well understood by one skilled in the art that first dopant region  13  could be contained within an n-well created by conventional n-well CMOS processing using a p-type wafer as starting material for substrate  10 . In this third alternative embodiment, the first dopant region  13  may be created with the same ion-implantation step used to create PMOS source/drain diffusions and p +  guardbars to contact the p-type substrate  10 . In this third alternative embodiment, the masking layer  14  defining openings  21  may be the same masking layer used to define NMOS source/drain diffusions and n +  guardbars to contact an n-well region created in substrate  10  as part of a conventional n-well process flow. In this third alternative embodiment, any counterdopant region  22  may be created by the same ion-implantation step used to create NMOS source/drain diffusions and n +  guardbars to contact an n-well region created in substrate  10  as part of a conventional n-well process flow.  
         [0025]    Referring still to FIG. 2A, the relative doping concentrations of the first dopant region  13  and counterdopant region  22  can be described. In the preferred embodiment, the counterdopant region  22  has a higher doping concentration than the first dopant region  13 , forming junction diodes between the first dopant region  13  and the counterdopant region  22 . The counterdopant region  22  terminal of each junction diodes is left unconnected. In the preferred embodiment, current flow through the first dopant region  13  is pinched between counterdopant depth  24  and the substrate  10 .  
         [0026]    [0026]FIG. 2B shows a schematic top view of the preferred embodiment looking at the surface of the wafer. The surface area of the counterdopant region  22  is enclosed by the surface area of the first dopant region  13 . It should be understood by one skilled in the art that many resistor shapes are defined on the surface of the wafer, including serpentine patterns, etc., and the top view of FIG. 2B is schematic only. If contacts to the first dopant region  13  are formed at points  25  and  26 , then the current through the first dopant region  13  between points  25  and  26  flows around the counterdopant regions  22  in those portions of the first dopant region  13  which are less deep than the counterdopant depth  24 . This pinching of the first dopant region  13  by the counterdopant regions  22  is therefore transverse to the direction of current flow between points  25  and  26  and parallel to the plane of the wafer&#39;s surface.  
         [0027]    [0027]FIG. 2C is a schematic top view of an alternate embodiment which shows the surface of the counterdopant region  22  extending outside the surface of the first dopant region  13 . This alternative embodiment results in further pinching of the first dopant region  13  by the counterdopant region  22  with this further pinching transverse to the direction of current flow between points  25  and  26  and parallel to the plane formed by the surface of the wafer.  
         [0028]    [0028]FIG. 2D is a schematic top view of an alternative embodiment which shows the surface of the counterdopant region  22  extending outside the surface of the first dopant region  13  such that current flow along the surface of the first dopant region  13  or at depths less than counterdopant depth  24  is completely blocked by at least one counterdopant region  22 . In this alternative embodiment, the pinching of the first dopant region is as shown in the cross-sectional view of FIG. 2A, between the counterdopant depth  24  and the substrate  10 .  
         [0029]    In the schematic cross-sectional view of FIG. 2E, the counterdopant depth  24  exceeds the first dopant depth  23 . This alternative embodiment can be used in conjunction with either top view shown in FIG. 2B or FIG. 2C. However, if the dopant concentration of the counterdopant region  22  exceeds the dopant concentration of the first dopant region  13  as stated above, FIG. 2E cannot be used in conjunction with FIG. 2D since the junction diode formed by the boundary between counterdopant region  22  and first dopant region  13  will completely block current conduction through the first dopant region  13 .  
         [0030]    Alternatively, the counterdopant region  22  can have a lower doping concentration than the first dopant region  13 . In this case, junction diodes are not formed. Since the doping concentration of the counterdopant region  22  is lower than the doping concentration of the first dopant region  13 , the effective net doping type of the counterdopant regions  22  is the same type as the first dopant region  13 . Such counterdopant regions  22  do not create junction diodes, but instead present regions of lower effective doping concentration than the doping concentration of the first dopant region  13 . Since resistivity increases as doping concentration is lowered, the counterdopant regions  22  present regions of higher resistivity than presented by the first dopant region  13  alone. Since no diodes are formed, the schematic cross-sectional view of FIG. 2E can be used in conjunction with the top view of FIG. 2D when the first dopant concentration exceeds the counterdopant concentration.  
         [0031]    In the schematic cross-sectional view of FIG. 3, the masking layer  14  of FIG. 2 has been removed by conventional photoresist stripping techniques, and an insulating layer  30  has been deposited as part of a conventional CMOS process. Contact holes  31  have been created in insulating layer  30  as part of a conventional CMOS process and separate metal contacts  32  to first dopant region  13  have been created by conventional CMOS processing techniques.

Technology Classification (CPC): 8