Patent Abstract:
A method and system for reproducing digital data read from a storage device. A second-order differentiation of a digital signal representing the digital data is calculated to control an automatic gain control (AGC) and phase lock loop (PLL) to rapidly correct amplitude and frequency offset of the digital signal being read from the storage device.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field:  
           [0002]    The present invention relates to an apparatus for reproducing data from a data recording medium and a method thereof. More particularly, it relates to an apparatus and a method for reproducing data in which rates of convergence for errors in amplitude and frequency of a signal read from the data recording medium are dynamically controlled to remove offset in the read signal.  
           [0003]    2. Description of Related Art:  
           [0004]    Typical examples of recording media for storing data, such as documents, images, and sound are a magnetic disk HDD (Hard Disk Drive), a DVD (Digital Video Disk or Digital Versatile Disk), an MO (Magneto-optic Disk), a CD (Compact Disk), and an LD (Laser Disk), or the like. FIG. 5( a ) shows an outline of a data reproduction apparatus  70  for reproducing digital data from a medium  72 . A read signal read from the medium  72  is digitized with a level determining unit  74  to be converted to a bit string (binary data) composed of 0&#39;s and 1&#39;s. The binary data is sent to a decoder  76  to be reproduced. For example, as shown in FIG. 5( b ), synchronization marks (Sync) for synchronization, address marks (AM), and data (DATA) are recorded in the medium  72 .  
           [0005]    [0005]FIG. 5( c ) shows an example of the structure of the level determining unit  74 . An automatic gain control (AGC) circuit  82  maintains a constant amplitude of a read signal read from medium  72 . An AGC output signal V(t) of constant amplitude is sent to a zero cross detector  84 . For example, the zero cross detector  84  defines a threshold level (slicing level) Vr, as shown in FIG. 6, based on the maximum and minimum values of the read signal V(t) to detect intersections (Pz 0 - 1 , 2 , 3 , 4 ) of the output signal V(t) and the slicing level Vr. Subsequently, the zero cross detector  84  sends a detection signal Z 0  indicative of the intersections to a binarization circuit  86 . The binarization circuit  86  defines time cells having a period determined by the frequency of the output signal V(t) detected by a phase-locked loop circuit (PLL)  88  to generate binary data based on presence or absence of the intersections Pz 0 - 1 , 2 , 3 , 4  (Time Tz0-1,2,3,4) in each time cell.  
           [0006]    The AGC circuit  82  keeps the amplitude of the output signal V(t) at a predetermined amplitude A 0  regardless of fluctuations of frequency in an input signal. The amplitude is controlled as a function of voltage αVca (α is a set value), which is proportional to an error or difference between the amplitude of the output signal V(t) and the predetermined amplitude A 0 . α can be adjusted by controlling the gain of an amplifier to amplify the voltage Vca. α is hereinafter referred to as a “feedback gain” of the AGC circuit  82 .  
           [0007]    PLL  88  defines time cells having a period determined by the frequency of the output signal V(t). The period is controlled as a function of voltage βVcp (β is a set value), which is proportional to an error or difference between the frequency of the output signal V(t) and the frequency of the time cells (a reciprocal of the cycle). β can be adjusted by controlling the gain of an amplifier to amplify the voltage Vcp. β is hereinafter referred to as a “feedback gain” of PLL  88 .  
           [0008]    When both feedback gains α and β of the AGC circuit  82  and PLL  88  are set high, sensitivity to errors becomes higher because of high amplification of the errors, so that the rate of convergence of the errors becomes faster. On the contrary, when a and β are set low, the sensitivity to the errors becomes lower because of low amplification, so that the convergence rates become slower.  
           [0009]    At early stages of operation of the AGC circuit  82  and PLL  88 , feedback gains a and b are set high to converge the errors rapidly. When operation is stabilized by the convergence of the errors, the feedback gains a and b are lowered to prevent malfunction caused by disturbance. Signals AGC-H/L and PLL-H/L outputted from a timer circuit  80  respectively switch the feedback gains a and b of the AGC circuit  82  and PLL  88 . The timer circuit  80  gives an instruction to operate at a high feedback gain during the early stages of the operation. After a lapse of a predetermined time, the timer circuit  80  gives an instruction to operate at a low feedback gain. The rate of error convergence is proportional to the feedback gains.  
           [0010]    For example, as a dot-dash-line in FIG. 7( a ) shows, a feedback gain is initially set to High to rapidly converge the error and then the feedback gain is set to Low. However, when noise is originated immediately before switching the setting of the feedback gain from High to Low, as a solid line in FIG. 7( a ) shows, the error is caused to converge slowly due to a low feedback gain. There is a possibility that the convergence of the error is not completed when an address mark (AM) is read due to the slow rate of convergence. Unless the convergence of the error has been completed, data may be unable to be read.  
           [0011]    As shown in FIG. 7( b ), there may be used a data recording format with repeated recording of synchronization and address marks to allow for the convergence time in the existence of noise. This data recording format wastes recording capacity because of overlapped recording of synchronization and address marks.  
           [0012]    When an MR (Magneto resistive) head is used for a read/write head of hard disk, heat generation caused by a touch of the MR head on the surface of a magnetic disk changes magneto resistance. The changes in magneto resistance cause noise called “Thermal Asperity”. Graphed as a dotted line in FIG. 2( a ), thermal asperity can be approximated by e −t/τ  (τ is a constant). A shift is caused by the thermal asperity at an intersection of the output signal V(t) and the slicing level Vr.  
           [0013]    Since thermal asperity lasts until the heated MR head has returned to its original temperature, it takes a long time to converge the shift. As shown in FIG. 5( c ), the level determining unit  74  generates an error correcting code (ECC) at the time of binarizing the read signal to send it to the decoder  76 . The error correction circuit  78  in the decoder  76  corrects errors in binary data using ECC. The error convergence time often, however, may be so long that ECC cannot work and thus data errors cannot be corrected using ECC.  
           [0014]    It is an object of the present invention to rapidly correct offset of a read signal which may cause data errors.  
         SUMMARY OF THE INVENTION  
         [0015]    A data reproduction apparatus according to the present invention includes a differentiating circuit for second-order differentiating an output signal outputted from an automatic gain control (AGC) circuit which receives a read signal read from a data recording medium; an arithmetic circuit for determining a time difference between a first intersection Pz 0  (Time Tz0) of the output signal and a slicing level, and a second intersection Pz 2  (Time Tz2) of the second-order differentiated signal and a zero level; a comparison circuit for comparing the determined time difference with a predetermined time to obtain a comparison value; and means responsive to the comparison circuit for controlling the setting of a rate of convergence for an error between the amplitude of the output signal of the AGC circuit and a predetermine amplitude, and the setting of a rate of convergence for an error between the frequency determined by the period of a time cell defined by a phase-locked loop circuit (PLL) and the frequency of the output signal from the AGC circuit.  
           [0016]    A data reproducing method according to the present invention includes the steps of: second-order differentiating an output signal outputted by an AGC circuit; detecting a second intersection Pz 2  of the second-order differentiated signal and a zero level; determining a time difference between a first intersection Pz 0  of the output signal and a slicing level, and the second intersection Pz 2 ; comparing the determined time difference with a predetermined time to obtain a comparison value; and controlling a rate of convergence for an error between the amplitude of the output signal from the AGC circuit and a predetermined amplitude, and a rate of convergence for an error between the frequency determined by the period of a time cell defined by PLL and the frequency of the output signal from the AGC circuit based on the comparison value.  
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1( a ) is a block diagram showing an example of the structure of a data reproduction apparatus according to the present invention.  
         [0018]    [0018]FIG. 1( b ) is a block diagram showing an example of the structure of a level determining unit shown in FIG. 1( a ).  
         [0019]    [0019]FIG. 2( a ) shows an outline of noise caused by thermal asperity.  
         [0020]    [0020]FIG. 2( b ) shows waveforms of outputs from an AGC circuit and a second-order differentiating circuit.  
         [0021]    [0021]FIG. 3 is a flow chart showing the detection procedure of occurrence and convergence of offset.  
         [0022]    [0022]FIG. 4 is a flow chart showing the change procedure of feedback gains of an AGC circuit and PLL.  
         [0023]    [0023]FIG. 5( a ) is a block diagram showing an example of the structure of a conventional data reproduction apparatus.  
         [0024]    [0024]FIG. 5( b ) is a figure showing an example of a data recording format of a medium.  
         [0025]    [0025]FIG. 5( c ) is a block diagram showing an example of the structure of a level determining unit shown in FIG. 5( a ).  
         [0026]    [0026]FIG. 6 is an graph of generation of binary data.  
         [0027]    [0027]FIG. 7( a ) shows an example of convergence of an error.  
         [0028]    [0028]FIG. 7( b ) shows another example of a data recording format of a medium.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0029]    With reference now to FIG. 1( a ), a data reproduction apparatus  20  of the present invention includes a level determining unit  10  for binarizing a read signal read from a medium  72 ; and a decoder  22  for decoding binary data. As shown in FIG. 1( b ), the level determining unit  10  includes an automatic gain control (AGC) circuit  82  for retaining the amplitude of the read signal at a predetermined value A 0 ; a zero cross detector  84  for detecting a first intersection Pz 0  of the output signal V(t) outputted from the AGC circuit  82  and a predetermined threshold level (Slicing level) Vr; and a binarization circuit  26  for generating binary data based on presence or absence of the intersection Pz 0  in each time cell. The binarization circuit  26  includes a phase-locked loop circuit (PLL)  88  for defining time cells having a period determined by the frequency of the output signal V(t).  
         [0030]    The level determining unit  10  further includes a differentiating circuit  12  for obtaining a second-order differential V″(t) of the output signal V(t) outputted from the AGC circuit  82 ; and an arithmetic/comparison circuit  14 . The second-order differentiated signal V″(t) from the differentiating circuit  12  is sent to the zero cross detector  84 . The zero cross detector  84  detects a second intersection Pz 2  of the second-order differentiated signal V″(t) and a zero level. After detecting the intersection Pz 2 , a detection signal Z 2  is sent to the arithmetic/comparison circuit  14 . A detection signal Z 0  indicative of the intersection Pz 0  of the output signal V(t) and the slicing level Vr is also sent to the circuit  14  by the zero cross detector  84 .  
         [0031]    As shown in FIG. 1( b ), the arithmetic/comparison circuit  14  functions as an arithmetic circuit for determining a time difference ΔT(=|Tz0−Tz2|) between the intersection Pz 0  (Time Tz0) and the intersection Pz 2  (Time Tz2) detected by the zero cross detector  84 , a comparison circuit for comparing the determined time difference ΔT with a predetermined time dT to obtain a comparison value, and means for controlling the setting of a rate of convergence for an error between the amplitude of the output signal V(t) of the AGC circuit  82  and the predetermined amplitude A 0 , and the setting of a rate of convergence for an error between the frequency determined by the period of the time cells defined by PLL  88  and the frequency of the output signal V(t) based on the comparison value.  
         [0032]    In the case of the second-order differentiated waveform V″(t) shown in FIG. 2( b ), the slicing level Vr is assumed to be a zero level. Feedback gain α of the AGC circuit  82  is controlled to adjust the rate of convergence of an error between the amplitude of the output signal V(t) of the AGC circuit  82  and the predetermined amplitude A 0 . A feedback gain β of PLL  88  is also controlled to adjust the rate of convergence of an error between the frequency determined by the period of the time cells and the frequency of the output signal V(t).  
         [0033]    The arithmetic/comparison circuit  14  detects the occurrence and convergence of offset in the read signal based on the result of comparison between the time difference ΔT and the predetermined time dT. For example, the occurrence and convergence of offset may be detected based on comparison results obtained in the current comparison and previous two consecutive comparisons. The arithmetic/comparison circuit  14  includes a memory (not shown) for storing the comparison values obtained in the previous two comparisons. When the current and previous two comparisons all indicate ΔT=|Tz0−Tz2|&gt;dT, the occurrence of offset is detected. When two or more comparisons out of the current comparison and the previous two comparisons indicate ΔT=|Tz0−Tz2|&lt;dT, the convergence of offset is detected.  
         [0034]    The predetermined time dT is set based on variations of the time difference ΔT predicted to cause malfunction of PLL  88 . PLL  88  can follow variations in frequency of the output signal V(t), as long as the time difference ΔT does not exceed a value D. When the time difference ΔT varies, however, beyond the value D, PLL  88  will malfunction. The predetermined time dT may be set to such a value D.  
         [0035]    When the occurrence or the convergence of offset is detected, the arithmetic/comparison circuit  14  gives an instruction to change the feedback gain α of the AGC circuit  82  and/or the feedback gain β of PLL  88 . The feedback gain α of the circuit  82  is controlled by a signal AGC-H/L (Automatic Gain Control-High/Low) to be sent from the circuit  14  to the circuit  82 . The feedback gain β of PLL  88  is controlled by a signal PLL-H/L (Phase Lock Loop-High/Low) to be sent from the circuit  14  to PLL  88 .  
         [0036]    The arithmetic/comparison circuit  14  sets the feedback gain of the AGC circuit  82  to a high gain at the early stages of inputting the read signal. Upon detection of the convergence of offset in a state that the circuit  82  operates at the high feedback gain, the circuit  14  gives the circuit  82  an instruction to operate at a feedback gain lower than the high gain and further gives PLL  88  an instruction to operate at a high feedback gain. In addition, the arithmetic/comparison circuit  14  gives PLL  88  an instruction to operate at a feedback gain lower than the high gain after a predetermined time TR has elapsed since the feedback gain of PLL  88  is switched to the high gain. The predetermined time TR is set according to the time required to synchronize the frequency of the time cells and the frequency of the output signal V(t). PLL  88  completes the synchronization in frequency between the time cells and the output signal V(t) within the time TR.  
         [0037]    Upon detection of the convergence of offset caused while the AGC circuit  82  and PLL  88  respectively operate at low feedback gains, the arithmetic/comparison circuit  14  gives PLL  88  an instruction to operate at a feedback gain higher than the low gain. After the predetermined time TR has elapsed since the feedback gain of PLL  88  is switched to the high gain, the arithmetic/comparison circuit  14  gives PLL  88  an instruction to operate at a low feedback gain.  
         [0038]    When offset occurs in a state that the AGC circuit  82  and PLL  88  respectively operate at low feedback gains, the arithmetic/comparison circuit  14  sends a signal INVAL indicating that binary data is invalid to the binarization circuit  26 . When thermal asperity occurs in a state that the AGC circuit  82  and PLL  88  operate at low feedback gains, the amplitude and the frequency is abnormal. The signal INVAL indicates that the read signal is in an abnormal state, so that the signal can be used as error correction information. The decoder  22  corrects errors in binary data in response to an error correcting code (ECC) and signal INVAL.  
         [0039]    The AGC circuit  82  sends a signal CZ 2  to nullify the detection of the intersection Pz 2  on the basis of the waveform of the read signal to the zero cross detector  84 . For example, the intersections Pz 0  other than those detected near the intermediate level of a peak to peak value of the read signal are nullified.  
         [0040]    Next, a description will be given to the operation of data reproduction using this data reproduction apparatus  20 .  
         [0041]    The AGC circuit  82  adjusts the amplitude of the read signal read from the medium  72  to the predetermined amplitude A 0  and then the zero cross detector  84  detects the intersections Pz 0  of the output signal V(t) and the slicing level Vr. Subsequently, PLL  88  defines time cells having a period determined by the frequency of the output signal V(t), so that the binarization circuit  26  generates binary data based on presence or absence of the intersection Pz 0  in each time cell.  
         [0042]    In the present invention, the feedback gain α of the AGC circuit  82  and the feedback gain β of PLL  88  are changed according to occurrence or convergence of offset of the read signal. FIG. 3 shows an example of the detection procedure of the occurrence or the convergence of offset. The occurrence or the convergence of offset is detected based on a time difference between the intersection Pz 0  (Time Tz0) of the output signal V(t) and the slicing level Vr, and the intersection Pz 2  (Time Tz2) of the second-order differential V″(t) of the output signal V(t) and the zero level.  
         [0043]    The differentiating circuit  12  second-order differentiates the output signal V(t) outputted from the AGC circuit  82  to produce the second-order differentiated signal V″(t). The zero cross detector  84  detects the intersection Pz 2  of the second-order differentiated signal V″(t) and the zero level, as shown in FIG. 2( b ). The AGC circuit  82  sends the signal CZ 2  for nullifying the detection of the intersection Pz 2  to the zero cross detector  84 . The signal CZ 2  can nullify the intersection Pz 2 , for example, detected in a noise portion adjacent to the peak of the output signal V(t).  
         [0044]    The arithmetic/comparison circuit  14  determines the time difference ΔT between the intersection Pz 0  (Time Tz0) and the intersection Pz 2  (Time Tz2) (S 110 ). The arithmetic/comparison circuit  14  compares the determined time difference ΔT with the predetermined time dT (S 112 ). 
         If Δ T=|Tz 0 −Tz 2 |&lt;dT,ER ( n )=0(S 114 ). 
         If Δ T=|Tz 0 −Tz 2 |&gt;dT,ER ( n )=1(S 116 ). 
         [0045]    The above ER(n) represents a comparison value obtained in the current comparison. For example, ER (n−1) indicates the comparison value which was obtained in the previous comparison and ER (n−2) indicates the comparison value which was obtained in the comparison before the previous comparison.  
         [0046]    The arithmetic/comparison circuit  14  detects the occurrence and convergence of offset of the read signal based on the current comparison value ER(n) and the comparison values ER (n−1) and ER (n−2) respectively obtained twice in the past. When all of the comparison values are 1 (S 118 ), it is assumed that the occurrence of offset is detected (S 120 ). When two or more comparison values are 0 (S 122 ), it is assumed that the convergence of offset is detected (S 124 ).  
         [0047]    Upon detection of the occurrence or the convergence of offset, the arithmetic/comparison circuit  14  changes the feedback gain α of the AGC circuit  82  and/or the feedback gain β of PLL  88 . FIG. 4 shows the change procedure of the feedback gain a of the AGC circuit  82  and the feedback gain β of PLL  88 .  
         [0048]    Since the amplitude of the read signal is required to be adjusted to the predetermined amplitude A 0  rapidly in an early stage of data reproduction, the feedback gain of the AGC circuit  82  is set to High (S 130 ). The feedback gain of PLL  88  is set to Low, so that binary data is valid. Upon detection of the convergence of offset in a state that the circuit  82  operates at the high feedback gain (S 132 ), the arithmetic/comparison circuit  14  gives the circuit  82  an instruction to operate at a feedback gain lower than the high gain (S 134 ). The amplitude of the output signal V(t) outputted from the circuit  82  at this time is stable.  
         [0049]    After stabilization of the amplitude of the output signal V(t), the arithmetic/comparison circuit  14  gives PLL  88  an instruction to operate at a high feedback gain to synchronize the frequency determined by the period of the time cells defined by PLL  88  with the frequency of the output signal V(t) in a short time (S 134 ). After a lapse of the predetermined time TR, since the arithmetic/comparison circuit  14  switched the feedback gain of PLL  88  to High (S 136 ), the circuit  14  gives PLL  88  an instruction to operate at a feedback gain lower than the high gain (S 138 ). The frequency determined by the time cells this time is synchronized with the frequency of the read signal.  
         [0050]    Upon detection of the occurrence of offset in a state that both of the AGC circuit  82  and PLL  88  are respectively operating at low feedback gains (S 142 ), the signal INVAL indicating binary data is invalid is sent from the arithmetic/comparison circuit  14  to the binarization circuit  26  (S 144 ). The binarization circuit  26  sends an error correcting code (ECC) and the signal INVAL together with the binary data to the decoder  22 . An error correcting circuit  24  in the decoder  22  corrects errors in the binary data using ECC and INVAL.  
         [0051]    Upon detection of the convergence of offset in a state that the AGC circuit  82  and PLL  88  are respectively operating at low feedback gains (S 132 ), the arithmetic/comparison circuit  14  gives PLL  88  an instruction to operate at a feedback gain higher than the low gain (S 134 ). The binary date becomes valid. The error between the frequency determined by the time cells and the frequency of the output signal V(t) is rapidly converged by operating PLL  88  at a high feedback gain. After the predetermined time has elapsed (S 136 ), PLL  88  operates at a low feedback gain (S 138 ). After the completion of reading data from the medium  72  (S 140 ), the processing shown in FIG. 4 has been completed.  
         [0052]    As described above, one embodiment according to the present invention has been described so far, but the present invention is not limited to this embodiment. For example, in a flow chart shown in FIG. 4, the frequency error in PLL  88  (S 134 , S 136 ) is converged after converging the amplitude error in the AGC circuit  82 , but it is also possible to converge the amplitude error in the AGC circuit  82  and the frequency error in PLL  88  at almost the same time.  
         [0053]    For a general data reproduction apparatus, an AGC circuit may often adjust the amplitude of an output signal V(t) to a predetermined amplitude A 0  during only an early stage of operation. It is also possible to change the feedback gain of an AGC circuit using a timer circuit as in a conventional data reproduction apparatus.  
         [0054]    In the flow chart shown in FIG. 3, although the occurrence and converge of offset has been detected based on comparison values obtained three times in the past, it is not limited to the past three times but it is possible to detect the occurrence and convergence of offset based on any number of comparison values. The conditions of occurrence of offset are not limited to twice out of three times either, but any number may be used. The conditions of convergence of offset are not limited to the entire three times, but any number may be adopted.  
         [0055]    As described above, specific embodiments of the present invention have been variously described so far, but the present invention is not limited to these embodiments. Also, any modification, variations or equivalent arrangements which may occur to those skilled in the art should be considered to be within the scope of the invention.  
         [0056]    There have thus been shown and described a novel data reproduction apparatus and a novel data reproducing method, which fulfill all the objects and advantages sought therefor. Many changes, modifications, variations, combinations, and other uses and applications of the subject invention will, however, become apparent to those skilled in the art after considering this specification and the accompanying drawings which disclose the preferred embodiments thereof. All such changes, modifications, variations and other uses and applications which do not depart from the spirit and scope of the invention are deemed to be covered by the invention, which is to be limited only by the claims which follow.

Technology Classification (CPC): 6