Patent Abstract:
A controller providing increased control with lesser final error for an actuator when there is a force accelerating the actuator, such as at the end of travel during a retract operation. An extension of the integrator may be provided for implementing a second direction to integrate a final error. One embodiment of the invention may comprise a counter and an analog multiplexer controlling the attenuation of the command voltage.

Full Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates in general to control of an actuator and, more particularly, to a method and apparatus for accurately controlling the velocity of an actuator member by monitoring the back electromotive force (“EMF”) of an actuator coil, and driving the coil with a voltage.  
       BACKGROUND OF THE INVENTION  
       [0002]     Conventional actuators, sometimes referred to as “motors”, have a movably supported member, and a coil. When a current is passed through the coil, a motive force is exerted on the member. A control circuit is coupled to the coil in order to controllably supply current to the coil. One example of such an arrangement is found in a hard disk drive, where the movable member of the actuator supports a read/write head adjacent a rotating magnetic disk for approximately radial movement of the head relative to the disk. There are situations in which it is desirable to move the member to one end of its path of travel at a predetermined velocity which is less than its maximum velocity. An example of such a situation is a power failure. In such a situation, it is desirable to move the member to a parking location, where it is held against potentially damaging movement which could occur if the member were not so parked. The movement of the member to the parking location is commonly referred to as a retract of the member.  
         [0003]     When a current is applied to the coil of the actuator, the member is subjected to a force tending to accelerate the member at a rate defined by the magnitude of the current, and in a direction defined by the polarity of the current. Consequently, in order to accelerate or decelerate the member until it is moving at a desired velocity and in a desired direction, it is important to know the actual direction and velocity of the member. In this regard, it is known that the back-EMF voltage on the coil of the actuator is representative of the velocity and direction of movement of the member. Specifically, the following relationship applies to actuators: 
 
 V   M =1 M   *R   M   +K   e ω
 
 where: 
 
 V M =voltage across actuator (motor), 
 
 I M =current through actuator, 
 
 R M =internal resistance of actuator, 
 
 K e =torque constant of actuator, and 
 
 ω=velocity of actuator. 
 
 The term, K e ω, represents the back-EMF of the actuator coil. 
 
         [0004]     Apparatus have been provided that control such actuators by providing a drive current to the coil of the actuator in response to the provision of a target speed voltage signal having a voltage corresponding to the target speed of the moveable member. For example, commonly assigned U.S. Pat. No. 6,040,671, entitled “CONSTANT VELOCITY CONTROL FOR AN ACTUATOR USING SAMPLED BACK EMF CONTROL,” and commonly assigned U.S. Pat. No. 6,184,645 entitled “VOLTAGE MODE DRIVE FOR CONTROL CIRCUIT FOR AN ACTUATOR USING SAMPLED BACK EMF CONTROL” discloses such an apparatus. However, such apparatus does not lend itself readily to providing such control in cases where forces can accelerate the actuator in the same direction driven by the control system.  
         [0005]     There is desired a control for an actuator when there is any force accelerating the actuator in any direction.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention achieves technical advantages as a controller providing increased control with lesser final error for an actuator when there is a force accelerating the actuator, such as at the end of travel during a retract operation. An extension of the integrator may be provided for implementing a second direction to integrate a final error. One embodiment of the invention may comprise a counter and an analog multiplexer controlling the attenuation of the command voltage.  
         [0007]     These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is a diagram of a typical prior art actuator control system;  
         [0009]      FIG. 2  is a block diagram of a prior art control unit for the system of  FIG. 1 ;  
         [0010]      FIG. 3  is a timing diagram for signals appearing in  FIG. 2 ;  
         [0011]      FIG. 4  is a block diagram of a preferred embodiment of the present invention; and  
         [0012]      FIG. 5  is a circuit diagram of a preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0013]      FIG. 1  is a diagrammatic view of a typical prior art system including an actuator  10  under control of a control circuit  12 . The particular system shown is that of a hard disk drive, in which the actuator  10  controls the movement of a member  20  on which a read/write head  34  is mounted. The control circuit  12  applies drive signals DRV+ on line  14  and DRV− on line  16  in response to a move command voltage signal V C  on line  18 . The drive signals DRV+ and DRV− cause motion in a member  20  of actuator  10  by setting up a force field in a coil  22  on the member  20 . The force field thus set up in coil  22  interacts with the magnetic field of a permanent magnet  24  disposed nearby. Member  20  is constrained to move about a shaft  26 , resulting in pivoting motion as shown by arrow  28 . The member is constrained in its movement between a first stop  30  and a second stop  32 . The result is that a magnetic head  34  is caused to move about a magnetic disk (not shown in this figure) in conjunction with the reading and writing of data from and to the magnetic disk in a hard drive system.  
         [0014]      FIG. 2  is a high level block diagram of a prior art control unit and the actuator it controls, such as is used in the system shown in  FIG. 1 . A control circuit  90  receives a move command signal VC on line  92  and provides drive current DRV+ and DRV− to an actuator. In  FIG. 2  the actuator shown is an idealized model  65  of an actuator. It will be appreciated that the control circuit  90  would be unable to “see” a significant difference between the actuator model  65  and an actual actuator, were an actual actuator connected to control circuit  90 .  
         [0015]     The actuator model  65  includes an ideal current sensor  66 , an inductance  68 , a resistance  70  and an ideal voltage-controlled voltage source  72 , all coupled in series between the two terminals  94 ,  96  of the actuator model  65 . The output  67  of the ideal current sensor  66  is a signal representing the current flowing through the actuator. This signal  67  is coupled to an input of an amplifier  74 , which has a gain K t  that represents a torque constant of the moveable member  20  ( FIG. 1 ). The output of the amplifier  74  is coupled to the input of a junction  76 , which adjusts the amplifier output using a signal representing a load torque. The output of junction  76  is coupled to the input of a circuit  78 , which makes an adjustment representative of the inertia J, of the member  20 .  
         [0016]     The output  80  of the circuit  78  is a signal which represents an acceleration of the member  20 . The signal  80  is integrated at  82 , in order to obtain a signal  84  which represents the velocity of the member  20 . The signal  84  is applied to the input of an amplifier  86  having a gain K e  that represents an electrical constant for the back-electromotive force (EMF) of the actuator. The output  88  of the amplifier  86  is a voltage V be  which represents the back-EMF voltage of the actuator. This voltage is applied to an input of the ideal voltage-controlled voltage source  72 , which reproduces this same voltage V be  across its output terminals. Since the voltage source  72  is ideal, it produces the output voltage regardless of whether there is any current flowing through source  72 .  
         [0017]     Since the signal  84  represents the actual velocity of the member  20 , and since the back-EMV voltage V be  present at  88  and across source  72  is proportional to the magnitude of signal  84 , it will be appreciated at the magnitude of the back-EMF voltage V be  across source  72  is an accurate representation of the actual velocity of the member  20 . However, when a current is flowing through the actuator model  65 , the resistance  70  produces a voltage which is added to the voltage V be  across the voltage source  72 . Consequently, so long as current is flowing through the actuator model  65 , it is not possible to accurately measure the voltage V be  alone, in order to accurately determine the actual velocity of the movable member.  
         [0018]     Therefore, the system of  FIG. 2  independently measures the back-EMF voltage V be , and thus determines the actual velocity of the member  20 . It does this by interrupting the current flow through the actuator coil  68  so that the voltage across the resistance  70  goes substantially to zero, after which the back-EMF voltage V be  is measured across the two terminals  94 ,  96 , of the actuator model  65 . It is a characteristic of the actuator that the back-EMF voltage V be  does not change rapidly after the current flow through the actuator model  65  is decreased to zero, once short term transient effects have died down.  
         [0019]     The control circuit  90  includes the following components. A junction  98  receives the retract command voltage signal V C  on line  92  that corresponds to a target velocity for the actuator member  20 . The output of junction  98  is provided to a proportional compensation unit  100  that provides a proportional amplification to the input provided thereto. Thus, the output of unit  100  is some multiple of the input, i.e., unit  100  is substantially a linear amplifier. Of course, the proportional factor in unit  100  may be one, in which case the output would be the same as the input.  
         [0020]     The output of terminal  98  is also provided to an integral compensation unit  102 , which provides a mathematical integration operation on its input to derive its output. The output of unit  100  provided to one input of terminal  104 , while the output of unit  102  is provided to another input of terminal  104 . The output of units  100  and  102  are added in terminal  104 , and the output, which is a voltage the level of which represents a commanded current level, I CMD , is provided on line  106  to a transconductance linear amplifier  108 . The outputs of amplifier  108  are the differential drive currents DRV+ and DRV− which are provided on lines  110  and  112 , respectively. The DRV+ signal is synchronous with a DRIVE control signal described below. Lines  110  and  112  are provided to input terminals  94  and  96 , respectively, of the actuator model  65 . Lines  110  and  112  are also connected to the differential inputs of a voltage sense unit  116 . The output of the voltage sense unit  116  is provided to a sampler unit  118 . A timer  120  generates two timing signals, a FLOAT timing signal which is applied to transconductance amplifier  108  and a SAMPLE timing signal which is applied to sampler unit  118 . The output of sampler unit  118 , on line  122  is provided to a second input to terminal  98 . The signal on line  122  is subtracted from the signal on line  92  in terminal  98 .  
         [0021]     The operation of the control circuit  90  of  FIG. 2  may be better understood by reference to the signal timing diagram shown in  FIG. 3 .  FIG. 3  shows the FLOAT timing signal, the SAMPLE timing signal, and the DRIVE drive signal, all mentioned above. These three signals are presented along a common horizontal time axis, and so their relative timings may be easily seen. As can be seen in  FIG. 3 , the FLOAT signal is a regularly recurring rectangular pulse. Looking now at one set of pulse signals, at timing  130  the FLOAT signal begins. This causes amplifier  108  ( FIG. 2 ) to turn off the drive signals, as can be seen by looking at the signal DRIVE in  FIG. 3 . After sufficient time for the transient effects in inductor  68  ( FIG. 2 ) of the actuator to die down, at timing  132 , a SAMPLE pulse begins. A SAMPLE pulse is provided for a sufficiently long period of time to enable the sampler unit  118  ( FIG. 2 ) to sense the voltage at the output of amplifier  116 . At time  134  the SAMPLE pulse ceases. After a small delay, at time  136 , the FLOAT signal ends. A short time thereafter, at time  138 , the drive signals resume. The sequence thus described repeats regularly. Details of the timings of these signals are provided below, in connection with the description of  FIG. 5 .  
         [0022]     Thus, in operation, the command voltage V C  is provided on line  92  to terminal  98 . There, it is combined with a voltage on line  122 , which is described in detail below. The output of terminal  98  is provided to the proportional compensation unit  100  and integral compensation unit  102 , the outputs of which are combined in terminal  104  to yield the current command signal I CMD . The current command signal I CMD  is converted into actual drive currents by the transconductance amplifier  108 , to yield the drive currents DRV+ and DRV− which are applied to the terminals  94  and  96 , respectively, on the actuator model  65 . At the same time, the voltage across terminals  94  and  96  is sensed by voltage sense unit  116 . The timer unit  120  applies the FLOAT signal to amplifier  108 , thus interrupting the drive current, a short time after which the SAMPLE signal is provided to sampler unit  118 , which samples and stores the voltage output from voltage sense unit  116 , thus the back-EMF voltage, undisturbed by voltage effects produced by the application of the drive currents, is sensed and stored in the sampler unit  118  on a regularly occurring basis. This sampled and held voltage is provided on line  122  to the terminal  98  where it is subtracted from the command voltage V CMD  to yield a feedback-corrected control voltage.  
         [0023]     The feedback-corrected command voltage is then applied to the proportional compensation unit  100  and the integral compensation unit  102 . As mentioned above, the proportional compensation unit  100  provides an output that is some multiple of its input. This multiple may be unity. The purpose of the proportional compensation unit  100  is to shape I CMD  so as to enable the control circuit  90  to respond better to large errors in the actual velocity, as compared with the desired, commanded velocity, while ensuring stability in the control circuit  90 . This is desired because, for example, in a retract operation, the situation in which the retract is initiated may be in the middle of a hard drive “hard seek” operation. In a hard seek the actuator coil is driven to the point of maximum velocity so as to rapidly move the head to a desired track on the hard drive. The voltage corresponding to this velocity might be, say, 7 Volts. By contrast, an exemplary voltage corresponding to a desired retract operation speed may be, say, one volt. The proportional compensation unit  100  allows the control circuit  90  to immediately respond to this wide disparity between actual speed and desired speed, without destabilizing the system. In selecting a suitable value for the proportional amplification factor, the practitioner should keep stability foremost, and set a bandwidth that is significantly less than the frequency of the SAMPLE signal pulses, while allowing relatively quick control of the actuator.  
         [0024]     The integral compensation unit  102 , as mentioned above, provides a mathematical integration operation on its input to derive its output. Thus, its response is slower than the proportional compensation unit  100 , and is unsuitable for reliance to respond to large errors in velocity, such as described above. This is why the proportional compensation unit  100  is provided. However, the proportional compensation unit  100  is not optimal for response to large changes in the torque load the actuator member may encounter. In such situations, the proportional compensation unit  100  is inadequate to maintain the desired relatively constant velocity. By contrast, the integral compensation unit  102  does respond well to even large and abrupt changes in torque load. When such a large torque load change is encountered, the integral compensation unit  102  gradually integrates the change in resultant velocity that the torque load change is inducing, and steadily increases the compensating current command to maintain the velocity constant. The result is adequate magnitude compensating current command, without destabilization of the control circuit  90 .  
         [0025]     However, while capable of providing good actuator control, the system described above in connection with  FIGS. 2 and 3  uses current mode output, which requires some form of current feedback. Current feedback may be difficult to obtain when the MOSFETs used to drive the actuator are external to the control IC. The preferred embodiment of the present invention improves upon the system of  FIG. 2 , and provides excellent control in systems where the drive transistors for the actuator are power MOSFETs external to the IC containing the control circuitry. The preferred embodiment provides such control without excessive expense, and is capable of operation in conditions of low voltage operation.  
         [0026]      FIG. 4  is a high level block diagram of a control unit  140  in accordance with a preferred embodiment of the present invention. The control circuit  140  receives a move command signal V C  on line  142  and provides drive voltages V DRV + and V DRV − to an actuator  65 . The command signal V C  on line  142  is provided to a junction  144  and to an inverse proportional compensation unit  146 . The output of junction  144  is provided to a proportional compensation unit  148  that provides a proportional amplification to the input provided thereto, and provides an output that is some multiple of the input. Thus, proportional compensation unit  148  may be a linear amplifier.  
         [0027]     The output of junction  144  is also provided to an integral compensation unit  150  that provides a mathematical integration operation on its input to derive its output. The output of unit  146  is provided to one input of a terminal  152 , while the output of unit  148  is provided to anther input of terminal  152 , and the output of unit  150  is provided to still another input of terminal  152 . The outputs of all three units  146 ,  148  and  150 , are added in terminal  152 , and the output, which is a voltage the level of which represents a command voltage, V CMD , is provided on line  154  to a linear amplifier  156  having a gain of K DRV . The outputs of amplifier  156  are the differential drive voltages V DRV + and V DRV − which are provided on lines  158  and  160 , respectively, to actuator  65 . The drive signal V DRV + is synchronous with a DRIVE control signal in a similar manner to the way in which the drive signal DRV+ in  FIG. 2  is synchronous with a DRIVE control signal in that configuration. Lines  158  and  160  are provided to the input terminals of the actuator  65 , and are also connected to the differential inputs of a voltage sense unit  162 . The output of the voltage sense unit  162  is provided to a sampler unit  164 . A timer  166  generates two timing signals, a FLOAT timing signal which is applied to linear amplifier  156  and a SAMPLE timing signal which is applied to sampler unit  164 . The output of sampler unit  164 , on line  168  is provided to a second input to terminal  144 . The signal on line  168  is subtracted from the signal on line  142  in terminal  144 .  
         [0028]     Some aspects of the operation of the control circuit  140  are similar to those of control circuit  90  of  FIG. 2 . In particular, the voltage sense unit  162 , sampler unit  164 , and timer  166  operate in a similar manner to corresponding voltage sense unit  116 , sampler unit  118 , and timer  120 , described above. Thus, the signals shown in  FIG. 3  are generated in essentially the same manner in the control circuit  140  of  FIG. 4 , and their function and relative timings are also essentially the same. However, it will be appreciated that the DRIVE and FLOAT signals in  FIG. 2  control the generation of the DRV+ and DRV− signals, while the corresponding DRIVE and FLOAT signals in  FIG. 4  control the generation of the V DRV + and V DRV − signals. Bearing that in mind, the timings of the signals used the control circuit  140  of  FIG. 4  may be readily understood from the description of the relative timings of signals described above in connection with  FIG. 3 , and such discussion will not be repeated here, in the interest of brevity.  
         [0029]     The function and operation of the proportional compensation unit  148  and of the integral compensation unit  150  are, likewise, similar to that of the proportional compensation unit  100  and of the integral compensation unit  102  of  FIG. 2 . However, it will be appreciated that in the control circuit  90  of  FIG. 2 , the compensation performed is for the purpose of ultimately generating a pair of control currents, the DRV+ and DRV− signals, while in the control circuit  140  of  FIG. 4 , the compensation performed is for the purpose of ultimately generating a pair of control voltages, the V DRV + and V DRV − signals. Otherwise, the compensation is the same.  
         [0030]     However, note that additional compensation unit  146  is provided. This unit provides inverse proportional compensation in the form of amplification by an inverse factor, specifically, the inverse of the amplification factor of amplifier  156 . Amplifier  156  has an amplification factor of K DRV , and so the amplification factor of unit  146  is 1/K DRV . The compensation provided by unit  146  is not on the output of terminal  144 . Rather, it is provided directly to the input command signal V C  on line  142 . The compensated output of unit  146  is then provided to terminal  152 , where it is combined with the outputs of compensation units  148  and  150 .  
         [0031]     A benefit of the novel compensation provided by unit  146  is to provide a net drive signal when the actuator is moving at a velocity substantially equal to that represented by the command signal V C , without requiring the integral compensation unit  150  to use a significant portion of its range. Since the control circuit  140  is a voltage drive system, when the back-EMF voltage is the same as the voltage of the command signal V C , in the absence of this novel compensation the output of the terminal  152  would be zero, and so the drive signals V DRV + and V DRV − would be zero, as well. It is generally desirable that the linear compensation factor K P  be small, to provide a relatively broad dynamic range for the linear compensation. However, because of the small K P , the integral compensation would end up generating the necessary signal to generate a drive signal to keep the actuator moving, were it not for the novel inverse proportional compensation. However, by providing the 1/K DRV  compensation to the command signal V C  itself, in steady state, where the actuator is moving at a velocity substantially equal to that represented by the command signal V C , the signal output by compensation unit  146  is V C /K DRV . After amplification by the amplifier  156 , this is provided as a drive signal V DRV + at a voltage of V C . In the absence of any substantial load this will be the correct voltage to hold the actuator in motion at the desired velocity. As a result, in such steady state no range need be used up by either the proportional compensation unit  148  or the integral compensation unit  150 . These compensation units are, therefore, fully available to compensate for their intended function.  
         [0032]     The system shown in  FIG. 4  may be implemented in circuitry or, alternatively in part or in whole in software.  FIG. 5  is a circuit diagram of a preferred embodiment of the present invention. The control circuit  200  shown in  FIG. 5  incorporates the features discussed above in conjunction with  FIG. 4 , and provides drive signals for an actuator (not shown in this figure). First, the components making up control circuit  200  will be described. Then, the principles of operation will be described.  
         [0033]     Two output lines  250  and  252  provide drive voltages V DRV + and V DRV −, respectively. Output line  250  is connected to one port of a resistor  254 , having a value of R, where R is a resistance value of, for example, 1k Ω. Resistor  254  is connected in series with a resistor  256 , having a value of R, to ground. The common connection node of resistor  254  and resistor  256  is connected to a plus input of a comparator  258 .  
         [0034]     Output line  252  is connected to one port of a resistor  260 , having a value of R. Resistor  260  is connected to one port of a resistor  262 , having a value of R, the other port of which is connected to a plus side of a voltage source  264  of a magnitude V C , being the same V C  as in  FIG. 4 . In hard disk drive actuator retract circuitry, the value of V C  may be, e.g., 250 millivolts, which is small enough so that it may be maintained for the entire duration of a retract after a power failure, as the system voltage is decaying to zero. A conventional low voltage regulator circuit may be used to establish this, and other reference voltages described below.  
         [0035]     The negative side of voltage source  264  is connected to ground. Thus, resistor  260 , resistor  262  and voltage source  264  are connected in series between line  252  and ground. The common connection node of resistor  260  and resistor  262  is connected to a minus input of comparator  258 . Resistors  260  and  262  form a 1:1 voltage “divider,” as do resistors  254  and  256 , and are provided as such because there is no attenuation of the feedback signal. The practitioner of ordinary skill in this art will understand that there may be instances in which it is desired to provide some attenuation in the feedback signal, in which case a correspondingly different ratio in the voltage divider will be appropriate. The voltage V C  is, as mentioned above, the desired back-EMF voltage for the commanded retract speed. Thus, at the input of comparator  258  a comparison is performed to determine whether the voltage V DRV + at line  250 , relative to the voltage V DRV − at line  252 , is above, or below, the desired back-EMF voltage, that is, V C . If it is above, then the output of comparator  258  will be driven high; if it is below, then the output of comparator  258  will be driven low.  
         [0036]     The output of comparator  258  is connected to the D input of a latch  266 . The output state of comparator  258  is captured periodically in latch  266 , in response to a SAMPLE signal provided at input  268  to latch  266 . The captured state is provided as Q and {overscore (Q)} outputs of latch  266 . These outputs are provided as inputs to a four bit up/down counter  270 , with the Q output of latch  266  providing the DOWN input to counter  270 , and the {overscore (Q)} output of latch  266  providing the UP input to counter  270 . Thus, counter  270  counts either up or down under control of the state captured in latch  266 . Also the Q output of latch  266  providing the UP input to counter  271 , and the {overscore (Q)} output of latch  266  providing the DN input to counter  271 . Thus, counter  271  counts either up or down under control of the state captured in latch  266 . The counter  271  will count up if counter  270  is at (0) Zero and the counter  270  will count up if counter  271  is at (0) Zero. Thus the counters  270  and  271  count in opposite directions, but never at the same time.  
         [0037]     The SAMPLE signal on input  268  is delayed by the DELAY circuit  272 , and the delayed SAMPLE signal is provided to the rising-edge-triggered count input of 4-bit counter  270 , thus causing counts of counter  270  at the delayed rising edges of the SAMPLE signal pulses. The delayed SAMPLE signal is also provided to the rising edge-triggered count input of 2-bit counter  271 , thus causing counts of counter  271  at the delayed rising edges of the SAMPLE signal pulses.  
         [0038]     The four bit output  274  of counter  270  is provided to the four bit input of a four bit digital-to-analog converter (“DAC”)  276 . The DAC  276  converts the digitized value at its four bit input to an analog voltage, in this case a voltage V INT  representing a mathematical integral of the difference of the voltage on line  250 , with respect to the voltage on line  252 , as is described in more detail below. The DAC  276  receives a regulated voltage V REG  and a reference current I on line  278 . The output of the DAC  276 , provided on line  282 , is a voltage at V c ×(1+1/A) provided by voltage source  280  via a 4-bit analog MUX  273 . MUX  273  is controlled by 4-bit control line  275  provided by counter  271 . It will be noted that the factor 1/A effects the 1/K DRV  compensation provided by inverse proportional compensation unit  146  discussed above in connection with  FIG. 4 , the factor A being K DRV . The factor A is selected to provide adequate responsiveness, while ensuring stability, according to conventional principles for selection of the gain factor for a drive amplifier for an actuator of the type being considered herein. An exemplary value is 6, but the particular value for the factor A is not limiting insofar as the scope of the instant invention is concerned.  
         [0039]     Advantageously, the counter  270  and counter  271  are coupled in phase with each other and are both responsive to delay circuit  272 . The 4-bit MUX  273  is selectively controlled by counter  271  via line  275  such that voltage source  280  is selectively a controlled and attenuated before being provided to DAC  276 , thereby providing a controlled output at  282  when a force is accelerating the actuator at the end of the travel during a retract operation, for instance if the forces keep pushing the actuator in the same direction that it is moving the integrator counter  270  will count down all the way to zero. At that point, the counter  271  is enabled and starts counting up and controlling the 4-bit MUX  273  via line  275  to attenuate the command voltage at the voltage source  280 . This will reduce the voltage at  282  that will eventually lower the outputs V DRV +250 and V DRV −252 to reduce the velocity of the actuator.  
         [0040]     The four bit up/down counter  270  has conventional logic circuitry included with it to permit it to detect when it has a count value of zero and it is in DOWN count mode. When such a condition occurs counter  270  provides an output signal on line  284 , which is provided to the D input of latch  286 . The value of the signal on line  284  is captured in latch  286  by the rising edge of the FLOAT signal (the falling edge of the {overscore (FLOAT)} signal), provided on input line  288 . The Q output of latch  286  is a PLUS signal, and is provided on line  290 , while the {overscore (Q)} output of latch  286  is a MINUS signal, and is provided on line  292 . The PLUS and MINUS signals are used in a manner described below.  
         [0041]     The value of the voltage difference between lines  250  and  252  is also sampled, by a capacitor  294 . The capacitor  294  is connected at one port to the common port of a switch  296  and at the other port to the common port of a switch  298 . Both switches  296 ,  298 , are single-pole-double-throw, and switch in unison from a DRIVE position to a SAMPLE position, in response to the SAMPLE signal, and return to the DRIVE position when the SAMPLE signal is removed. Both switches  296 ,  298 , are shown in the DRIVE position in the figure. All other switches in  FIG. 5  are also single-pole-double-throw, except for switch  318 , described below, which is a three-position-single-pole switch. All switches may be implemented as a pair of FETs, with the signal identifying the switch position in  FIG. 5  being provided to the gate of the respective FET for enablement of that switch position. Note that switch  318  is also a pair of FETs, with the third, OFF “position” being the consequence of the fact that the SAMPLE and DRIVE signals do not completely overlap, as shown in  FIG. 3 .  
         [0042]     The SAMPLE position port of switch  296  is connected to the V DRV + output line  250 . The SAMPLE position port of switch  298  is connected to the V DRV − output line  252 . Thus, the voltage difference between lines  250  and  252  is sampled at the same level as the voltage comparison is made at the input of comparator  258 .  
         [0043]     The DRIVE position port of switch  298  is connected to the common port of a switch  308 . A MINUS position port of switch  308  is connected to ground, while a FLOAT OR PLUS position port is connected to a MINUS port of a switch  312  and to the input of a buffer amplifier (gain=1)  314 . The other switch position port of switch  312 , a FLOAT OR PLUS position port, is connected to ground. The common port of switch  312  is connected to one port of a capacitor  316 . The other port of capacitor  316  is connected to the common port of a switch  318 . A DRIVE port of switch  318  is connected to a DRIVE port of switch  296 . A SAMPLE port of switch  318  is connected to the output of DAC  276 , i.e., to line  282 . An intermediate, OFF position of switch  318  floats.  
         [0044]     Thus, when the switches are in the DRIVE and FLOAT OR PLUS positions, the compensated command voltage from DAC  276 ,  
             V   c     ⁢     x   ⁡     (     1   +     1   a       )         +     v   INT       ,       
 
         [0045]     stored on capacitor  316 , minus the back-EMF voltage sampled and stored on capacitor  294 , is provided as V CMD  to the input of buffer amplifier  314 . However, when the switches are in the DRIVE and MINUS positions, the inverse of that is provided as V CMD  to the input of buffer amplifier  314 , that is, the inverse of the compensated command voltage from DAC  276 ,  
             V   c     ⁢     x   ⁡     (     1   +     1   a       )         +     v   INT       ,       
 
         [0046]     stored on capacitor  316 , minus the back-EMF voltage sampled and stored on capacitor  294 , due to the reversal of switch positions.  
         [0047]     The output of buffer amplifier  314  is connected to one port of a resistor  320  having a resistance of R. The other port of resistor  320  is connected to the non-inverting input of a differential amplifier  322  and to one port of a resistor  324  having a resistance of AR. The other port of resistor  324  is connected to the common port of a switch  326 . A resistor  328  having a resistance of AR is connected between a voltage source V M  and the inverting input of differential amplifier  322 . The inverting input of differential amplifier  322  is also connected to one port of a resistor  330  having a resistance of R, the other port of which is connected to ground. The output of differential amplifier  322  is connected to the common port of a switch  332 .  
         [0048]     A MINUS port of switch  326  is connected to the drain of an NFET device  334 , while a MINUS port of switch  332  is connected to the gate of NFET device  334 . The source of NFET device  334  is connected to ground. A PLUS port of switch  326  is connected to the drain of an NFET device  336 , while a PLUS port of switch  332  is connected to the gate of NFET device  336 . The source of NFET device  336  is connected to ground.  
         [0049]     The differential amplifier  322 , in conjunction with resistors  320 ,  324 ,  328  and  330 , performs an amplification of the compensated command signal V CMD  by the factor A, again, being the factor K DRV  described above in conjunction with  FIG. 4 .  
         [0050]     The drain of NFET device  334  is also connected to the V DRV + output line  250 , and to the source of a large current NFET  338 , one of two “high side drivers.” The drain of NFET device  338  is connected to the actuator voltage supply V M . The gate of NFET device  338  is connected to the output of an AND gate  340 . One input of AND gate  340  is connected to the PLUS signal line  290 , while the other input of AND gate  340  is connected to the {overscore (FLOAT)} signal line  288 .  
         [0051]     The drain of NFET device  336  is also connected to the V DRV − output line  252 , and to the source of a high current NFET  342 , the other of the two “high side drivers.” The drain of NFET device  342  is connected to the actuator voltage supply V M . The gate of NFET device  342  is connected to the output of an AND gate  344 . One input of AND gate  344  is connected to the MINUS signal line  292 , while the other input of AND gate  344  is connected to the {overscore (FLOAT)} signal line  288 . It will be appreciated that the NFET devices  338 ,  342 ,  334  and  336 , may be either off chip or on chip.  
         [0052]     The power supply for AND gate  340  and AND gate  344  is the power supply V DD . The voltage level of this supply may be some voltage greater than V M , for example 2×V M . This voltage may be stored on an external hold capacitor (not shown), if desired. This voltage ensures that the output signals of AND gate  340  and AND gate  344  are sufficiently high to drive their associated NFET devices  338  and  342 , respectively, to a fully saturated ON state, even as the system supply voltage decays after a power failure.  
         [0053]     A retract enable signal enables gates  340  and  344  through negative logic. Thus, {overscore (RETEN)} is applied on line  346  to an inverting enable port of AND gate  340  and AND gate  344 .  
         [0054]     In operation, the control circuit  200  provides the active drive voltage through either line  250  or  252 , as the case may be, as either device  338  is on and device  342  is off, or device  342  is on and device  338  is off. When device  338  is on, a closed path is formed from the actuator voltage supply V M , through the actuator and device  336 , to ground. When device  342  is on, a closed path is formed from the actuator voltage supply V M , through the actuator and device  334 , to ground. This provides two selectable drive directions to the actuator member.  
         [0055]     Thus, this invention allows for voltage mode control of the velocity of an actuator. The approach described herein allows the use of either internal or external MOS transistors. In cases where external MOS transistors are required it eliminates the need for additional current sensing circuitry that would be required for current mode control. Therefore, in such instances where external MOS transistors are required, this approach is simpler and less expensive to implement.  
         [0056]     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.

Technology Classification (CPC): 6