Patent Abstract:
A feedback controlled substrate bias generator having a substrate bias level sensing circuit, a charge pump circuit and an improved oscillator is disclosed. The substrate bias level sensing circuit is coupled to a semiconductor substrate for sensing a bias voltage of the semiconductor substrate and outputting a control signal in response to the sensed bias voltage. The charge pump circuit is coupled to the semiconductor substrate and the substrate bias level sensing circuit for receiving a clock pulse and the control signal and supplying the bias voltage to the semiconductor substrate in response to the received signals. The improved oscillator is coupled to the charge pump circuit for generating the clock pulse. The improved oscillator has a loop circuit having a plurality of serially and circularly coupled inverters each of which has a source terminal applied to voltage from a voltage source, an input terminal for receiving an input signal and an output terminal for outputting an output signal. The improved oscillator further has a plurality of switches each of which has a control terminal, a first terminal coupled to the source terminal of a corresponding inverter of the loop circuit and a second terminal coupled to the voltage source. Each of the switches electrically cuts the first and second terminals when the input signal of the one of the inverters except for the corresponding inverter changes from one level to another.

Full Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the priority of Japanese Application Serial, No. 324809/1991, filed Dec. 9, 1991, the subject matter of which is incorporated herein by reference. This application also claims an invention a part of which is disclosed in the copending application Serial No. 07/519,572, filed May 7, 1990, (now Pat. No. 5,113,088 issued May 12, 1992) which is a continuation-in-part of application Serial No. 07/433,213, filed Nov. 7, 1989 now abandoned. The above copending application which is commonly assigned by this applicant claims the priority of Japanese Application Serial No. 283,448/1998, filed Nov. 9, 1988. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to a feedback controlled substrate bias generator suitable for use in a semiconductor memory circuit, and more specifically to a feedback controlled substrate bias generator comprising a feedback controller having a circuit for sensing a bias level of a semiconductor substrate, a charge pump circuit and an improved oscillator. 
     A feedback controlled substrate bias generator has been disclosed in U.S. Pat. Nos. 4,142,114, 4,439,692, 4,471,290 and 4,794,278, for example. The disclosed substrate bias generator comprises an oscillator for generating a clock signal, a charge pump circuit electrically connected to the oscillator, for generating a bias voltage level to be applied to a semi-conductor substrate, and a sensing circuit for detecting the bias voltage level applied to the semiconductor substrate and for controlling either the oscillator or the charge pump circuit based on the sensed bias voltage level. 
     The output terminal of the sensing circuit is electrically connected to a first input terminal of an inhibition gate such as a NOR gate or a NAND gate. A second input terminal of the inhibition gate is electrically connected with the output terminal of the oscillator. The output terminal of the inhibition gate is electrically connected to the charge pump or the oscillator so as to inhibit a clock signal from being input to the charge pump circuit or stop the operation of the oscillator. 
     The oscillator is however operated even if the clock signal is inhibited from being input to the charge pump circuit. Therefore, the current used up by the oscillator increases. When the oscillator is restarted after having been inactivated, an initial condition set to the oscillator provides unstable oscillations. There was thus a possibility of a substrate voltage remaining inconstant. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a feedback controlled substrate bias generator which can provide less current consumption. 
     It is another object of the present invention to provide a feedback controlled substrate bias generator which can provide a stable substrate voltage. 
     A feedback control led substrate bias generator according to the present invention has a substrate bias level sensing circuit, a charge pump circuit and an improved oscillator. The substrate bias level sensing circuit is coupled to a semiconductor substrate for sensing a bias voltage of the semicnductor substrate and outputting a control signal in response to the sensed bias voltage. The charge pump circuit is coupled to the semiconductor substrate and the substrate bias level sensing circuit for receiving a clock pulse and the control signal and supplying the bias voltage to the semiconductor substrate in response to the received signals. The improved oscillator is coupled to the charge pump circuit for generating the clock pulse. The improved oscillator has a loop circuit having a plurality of serially and circularly coupled inverters each of which has a source terminal applied to a voltage from a voltage source, an input terminal for receiving an input signal and an output terminal for outputting an output signal. The improved oscillator further has a plurality of switches each of which has a control terminal, a first terminal coupled to the source terminal of a corresponding inverter of the loop circuit and a second terminal coupled to the voltage source. Each of the switches electrically cuts the first and second terminals when the input signal of the one of the inverters except for the corresponding inverter changes from one level to another. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a feedback controlled substrate bias generator according to a first embodiment of the present invention; 
     FIG. 2 is a circuit diagram illustrating a charge pump circuit shown in FIG. 1; 
     FIG. 3 is a circuit diagram depicting a substrate bias level sensing circuit shown in FIG. 1; 
     FIG. 4 is a waveform chart for describing the operation of an oscillator shown in FIG. 1; 
     FIG. 5 is a circuit diagram showing a feedback controlled substrate bias generator according to a second embodiment of the present invention; 
     FIG. 6 is a waveform chart for describing the operation of an oscillator shown in FIG. 5; and 
     FIG. 7 is another waveform chart for describing the operation of the oscillator shown in FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a circuit diagram showing a feedback controlled substrate bias generator according to a first embodiment of the present invention. 
     The substrate bias generator comprises an oscillator  100  operated in a ring-like arrangement (a ring oscillator), a charge pump circuit  200  electrically connected to the oscillator  100  and a semiconductor substrate  10 , and a substrate bias level sensing circuit  300  electrically connected to the semiconductor substrate  10  and the charge pump circuit  200 . 
     The oscillator  100  outputs a clock signal S 100  to the charge pump circuit  200 . The oscillator  100  also has five inverter circuits or stages  110 ,  120 ,  130 ,  140 ,  150  each of which are successively cascade-connected to one another through four nodes N 111 , N 121 , N 131  and N 141 . Further, the output node N 151  of the inverter circuit  150  is electrically connected with the input terminal of a waveform shaping buffer circuit, i.e., a waveform shaping buffer  160  and the input terminal of the inverter circuit  110 . The output terminal of the buffer  160  is electrically connected to a CMOS inverter  164 . 
     The inverter circuits  110 ,  120 ,  130 ,  140 ,  150  respectively include CMOS inverters  111 ,  121 ,  131 ,  141 ,  151  comprised of PMOS transistors  111   a ,  121   a ,  131   a ,  141   a ,  151   a  and NMOS transistors  111   b ,  121   b ,  131   b ,  141   b ,  151   b , for inverting signals output from the prestage or anterior inverter circuits and supplying the inverted signals to the poststage or posterior inverter circuits, respectively. PMOS transistors (first switching means)  112 ,  122 ,  132 ,  142 ,  152  are respectively connected between the sources of the PMOS transistors  111   a ,  121   a ,  131   a ,  141   a ,  151   a  and a power source voltage V CC  (first power source voltage). NMOS transistors (second switching means)  113 ,  123 ,  133 ,  143 ,  153  are respectively connected between the sources of the NMOS transistors  111   b ,  121   b ,  131   b ,  141   b ,  151   b  and the ground (second power source voltage) V SS . The gates of the PMOS transistors  112 ,  122 ,  132 ,  142 ,  152  and the gates of the NMOS transistors  113 ,  123 ,  133 ,  143 ,  153  in the respective inverter circuits  110 ,  120 ,  130 ,  140 ,  150  are electrically connected to their corresponding terminals of the CMOS inverters of the inverter circuits turned two stages backwardly of the present inverter circuit or present stage. 
     The buffer  160  and the CMOS inverter  164 , which is electrically connected to the buffer  160  and comprised of a PMOS transistor  164   a  and an NMOS transistor  164   b , have a waveform shaping function for causing a waveform of a signal which appears at the output node N 151  of the final inverter circuit  150  to abruptly rise and fall. The buffer  160  comprises a CMOS inverter  161  comprised of a PMOS transistor  161   a  and an NMOS transistor  161   b , for inverting the signal which appears at the output node N 151  of the final inverter circuit  150  and outputting the inverted signal to the CMOS inverter  164  through an output node N 161 , a PMOS transistor (first switching means)  162  electrically connected between the source of the PMOS transistor  161   a  and the power source voltage V CC , and an NMOS transistor (second switching means)  163  electrically connected between the source of the NMOS transistor  161   b  and the ground V SS . The gates of the PMOS transistor  162  and the NMOS transistor  163  are electrically connected to the input terminal of the CMOS inverter  141  of the inverter circuit  140  which is located two stages backwardly of the present stage. Stated another way, the gates of the PMOS transistor  162  and NMOS transistor  163  are electrically connected to the output node of an inverter circuit located 2K stages before the last inverter circuit  150 , where K is an integer. 
     FIG. 2 is a circuit diagram showing the charge pump circuit shown in FIG.  1 . The charge pump circuit  200  includes a NAND gate circuit  201  which has two input terminals. One of the input terminals is connected to the oscillator  100  and receives the clock pulse S 100 . The other input terminal is connected to the substrate bias level sensing circuit  300 . The output terminal of the NAND gate circuit  201  is connected to a first terminal of a capacitor  202  through a node N 210 . The charge pump circuit  200  further includes a series connection of NMOS transistors  203  and  204  between the ground V SS  and node N 212  through a node N 211 . The drain of the NMOS transistor  203  is connected to the ground V SS . The source and gate of the NMOS transistor  203 , the drain of the NMOS transistor  204  and a second terminal of the capacitor  202  are connected to the node N 211 . The source and gate of the NMOS transistor  204  are connected to the node  212  which is connected to the semiconductor substrate  10 . 
     FIG. 3 is a circuit diagram showing the substrate bias level sensing circuit shown in FIG.  1 . The substrate bias level sensing circuit  300  has a series connection of NMOS transistors  301 ,  302  and  303  between the power source voltage V CC  and the semiconductor substrate  10 . The drain and gate of the NMOS transistor  301  are connected to the power source voltage V CC . The source of the NMOS transistor  301  and the gate and drain of the NMOS transistor  302  are connected to a node N 310 . The source of the NMOS transistor  302  and the drain and gate of the NMOS transistor  303  are connected together. The source of the NMOS transistor  303  is connected to the semiconductor substrate  10 . Inverters  304  and  305  are connected in series to the node N 310 . The output terminal of the inverter  305  is connected to the charge pump circuit  200 . 
     The operation of the substrate bias generator according to the present embodiment will now be described below. Incidentally, the operations of the charge pump circuit  200  and the level detector  300  have been disclosed in a co-pending application Ser. No. 519,572, filed May 7, 1990 (now Pat. No. 5,113,088 issued May 12, 1992) assigned to the same assignee as the present application, whose subject matter is incorporated herein by reference. Their detailed description will therefore be omitted. 
     FIG. 4 is a waveform chart for describing the operation of the oscillator  100  shown in FIG.  1 . The operation of the substrate bias generator will be described below with reference to FIGS. 1 and 4. 
     In the oscillator  100 , the inverter circuits  110 ,  120 ,  130 ,  140  and  150  respectively invert signals output from the inverter circuits  150 ,  110 ,  120 ,  130  and  140  of the previous stages and feed back the same to the corresponding inverter circuits  120 ,  130 ,  140 ,  150  and  110  of the subsequent stages. As a result, a pulse signal having a predetermined period is supplied to the buffer  160  from the output node N 151  of the inverter circuit  150  serving as the final stage. Then, the buffer  160  inverts the signal supplied from the node N 151 . Further, the buffer  160  outputs the inverted signal to the CMOS inverter  164  from the node N 161  thereof. The CMOS inverter  164  inverts a signal supplied from the node N 161  to produce a pulse signal S 100  having a given period. The pulse signal S 100  thus produced is output to the charge pump circuit  200 . Thus, the buffer  160  and the CMOS inverter  164  converts the signal at the node N 151  whose waveform gently rises and falls into the pulse signal S 100  whose waveform abruptly rises and falls. 
     When a substrate bias voltage V bb  supplied to the substrate  10  from the charge pump circuit  200  is higher than a predetermined voltage, the substrate bias level sensing circuit  300  brings a control signal S 300  to an “H” level. When, on the other hand, the substrate bias voltage V bb  is lower than the predetermined voltage, the substrate bias level sensing circuit  300  renders the control signal S 300  “L” in level. When the control signal S 300  is “H” in level, the charge pump circuit  200  starts a charge pump operation. When the control signal S 300  is “L” in level, the charge pump circuit  200  stops the charge pump operation. As a result, the substrate bias voltage V bb  of the substrate  10  is controlled so as to be kept at a voltage not greater than the predetermined voltage at all times. 
     The operation of each of the inverter circuits  110 ,  120 ,  130 ,  140  and  150  will now be described below. Incidentally, the inverter circuits  110 ,  120 ,  130 ,  140  and  150  are identical in operation to each other. Therefore, the inverter circuit  110  will be described below as a typical example. 
     A signal input to the CMOS inverter  111  of the inverter circuit  110  and a signal input to each of the gates of the PMOS transistor  112  and the NMOS transistor  113  represent signals output from the inverter circuits  150  and  130  respectively. Therefore, the signal input to the CMOS inverter  111  and the signal input to each of the gates of both the PMOS transistor  112  and the NMOS transistor  113  differ in phase from each other. 
     At a time t shown in FIG. 4, an intermediate voltage which appears at the output node N 151  of the inverter circuit  150 , is input to the input terminal of the CMOS inverter  111  of the inverter circuit  110 . Therefore, the PMOS transistor  111   a  and the NMOS transistor  111   b  are both turned on. On the other hand, an “H” level signal which appears at the output node N 131  of the inverter circuit  130 , is input to the gates of both the PMOS transistor  112  and the NMOS transistor  113 . Therefore, the PMOS transistor  112  is brought to an off state and the NMOS transistor  113  is brought to an on state. Since the PMOS transistor  112  is brought to the off state, through current I can be prevented from flowing from the power source voltage V CC  to the ground V SS . 
     Other inverter circuits  120 ,  130 ,  140  and  150  can be handled in the same manner as the inverter circuit  110 . That is, at least any one of the transistors of each of other inverter circuits  120 ,  130 ,  140  and  150 , which are series-connected between the power source voltage V CC  and the ground V SS , is turned off. Therefore, the through current I does not flow from the power source voltage V CC  to the ground V SS . 
     Further, the wave-form shaping buffer  160  employed in the substrate bias generator according to the present embodiment also includes the PMOS transistor  162  and the NMOS transistor  163  both connected in series with the CMOS inverter  161  as the switching means. It is therefore possible to reliably prevent the through current I from flowing from the power source voltage V CC  to the ground V SS . Control signals of the PMOS and NMOS transistors  112  and  113 ,  122  and  123 ,  132  and  133 ,  142  and  143 ,  152  and  153 , and  162  and  163  respective pairs of which serve as the switching means and are employed in their corresponding inverter circuits  110 ,  120 ,  130 ,  140 ,  150  and buffer circuit  160 , represent signals output from the inverter circuits  110 ,  120 ,  130 ,  140 ,  150  respectively. It is therefore unnecessary to provide additional control means for generating such control signals. 
     FIG. 5 is a circuit diagram showing a feedback controlled substrate bias generator according to a second embodiment of the present invention. The same element of structure as those employed in the substrate bias generator shown in FIG. 1 are identified by the same reference numerals. 
     The substrate bias generator according to the second embodiment has an oscillator  400  operated in a ring-like arrangement, which differs from the oscillator  100  shown in FIG. 1. A charge pump circuit  200  similar to that shown in FIG. 1 is electrically connected to the output terminal of the oscillator  400 . Further, a substrate bias level sensing circuit  300  is electrically connected to the charge pump circuit  200 . 
     The oscillator  400  supplies a frequency-variable pulse signal S 400  to the charge pump circuit  200 . The oscillator  400  also has five inverter circuits  410 ,  420 ,  430 ,  440 ,  450 . The output nodes N 411 , N 421 , N 431 , N 441 , N 451  of the inverter circuits  410 ,  420 ,  430 ,  440 ,  450  are cascade-connected to one another. The output node N 451  of the inverter circuit  450  is electrically connected to a waveform shaping buffer  460  and a CMOS inverter  464 . Further, the oscillator  400  includes a CMOS inverter  470  comprised of a PMOS transistor  470   a  and an NMOS transistor  470   b , for inverting a control signal S 300  output from the substrate bias level sensing circuit  300  and outputting a control signal S 470  therefrom. 
     The inverter circuits  410 ,  420 ,  430 ,  440 ,  450  respectively include CMOS inverters  411 ,  421 ,  431 ,  441 ,  451  which invert signals output from the prestage inverter circuits respectively and supply the inverted signals to the poststage inverter circuits which are comprised of PMOS transistors  411   a ,  421   a ,  431   a ,  441   a ,  451   a  and NMOS transistors  411   b ,  421   b ,  431   b ,  441   b ,  451   b  respectively. The inverter circuits  410 ,  420 ,  430 ,  440 ,  450  respectively include PMOS transistors  412 ,  422 ,  432 ,  442 ,  452  (first switching means) connected between their corresponding high-voltage input nodes N 412 , N 422 , N 432 , N 442 , N 452  of the CMOS inverters  411 ,  421 ,  431 ,  441 ,  451  and a power source voltage V CC , and NMOS transistors  413 ,  423 ,  433 ,  443 ,  453  (second switching means) connected between their corresponding low-voltage input nodes N 413 , N 423 , N 433 , N 443 , N 453  and the ground V SS . The PMOS transistors  412 ,  422 ,  432 ,  442 ,  452  serving as the first switching means respectively include PMOS transistors  412   a ,  422   a ,  432   a ,  442   a ,  452   a  on/off-controlled in accordance with the a control signal S 470 , and PMOS transistors  412   b ,  422   b ,  432   b ,  442   b ,  452   b  which are controlled so as to be normally turned on. The PMOS transistors  412   a ,  422   a ,  432   a ,  442   a ,  452   a  are respectively parallel-connected between the high-voltage input nodes N 412 , N 422 , N 432 , N 442 , N 452  of the CMOS inverters  411 ,  421 ,  431 ,  441 ,  451  and the power source voltage V CC . Similarly, the PMOS transistors  412   b ,  422   b ,  432   b ,  442   b ,  452   b  are respectively parallel-connected between the high-voltage input nodes N 412 , N 422 , N 432 , N 442 , N 452  and the power source voltage V CC . The NMOS transistors  413 ,  423 ,  433 ,  443 ,  453  serving as the second switching means respectively include NMOS transistors  413   a ,  423   a ,  433   a ,  443   a ,  453   a  controlled so as to be normally turned on, and NMOS transistors  413   a ,  423   a ,  433   a ,  443   a ,  453   b  on/off-controlled in accordance with the control signal S 300 . The NMOS transistors  413   a ,  423   a ,  433   a ,  443   a ,  453   a  are respectively parallel-connected between the low-voltage input nodes N 413 , N 423 , N 433 , N 443 , N 453  and the ground V SS , whereas the NMOS transistors  413   b ,  423   b ,  433   b ,  443   b ,  453   b  are respectively parallel-connected between the low-voltage input nodes N 413 , N 423 , N 433 , N 443 , N 453  and the ground V SS . 
     The buffer  460  and the CMOS inverter  464  have a waveform shaping function for shaping rising and falling waveforms of a signal which appears at the output node N 451  of the inverter circuit  450  corresponding to the final stage into abrupt waveforms. The buffer  460  comprises a CMOS inverter  461  comprised of a PMOS transistor  461   a  and an NMOS transistor  461   b , for inverting the signal which appears at the output node N 451  and outputting the inverted signal from a node N 461 , a PMOS transistor (first switching means)  462  electrically connected between the source of the PMOS transistor  461   a  and the power source voltage V CC , and an NMOS transistor (second switching means)  463  electrically connected between the source of the NMOS transistor  461   b  and the ground V SS . The gates of the PMOS transistor  462  and the NMOS transistor  463  are electrically connected to the output node N 431  of the inverter circuit  430 . The CMOS inverter  464  connected to the output node N 461  of the buffer  460  inverts the signal output from the node N 461  and supplies the inverted signal, i.e., a pulse signal S 400  to the charge pump circuit  200 . The CMOS inverter  464  includes a PMOS transistor  464   a  electrically connected to the power source voltage V CC  and an NMOS transistor  464   b  electrically connected to the ground GND, i.e., V SS . 
     The operation of the substrate bias generator according to the second embodiment will next be described below with reference to FIGS. 6 and 7. 
     FIG. 6 is a view for describing each of the waveforms of signals which appear at the nodes in the oscillator  400  where the charge pump circuit  200  is in operation because the substrate bias voltage V bb  is less than a predetermined level, the control signals S 300 , S 470  are “H” and “L” in level respectively and the PMOS transistor  412   a  and the NMOS transistor  413   b  of the inverter circuit  410  are both in an on state. FIG. 7 is a view for describing each of waveforms of signals which appear at the nodes in the oscillator  400  where the charge pump circuit  200  is in nonoperation because the substrate bias voltage V bb  is maintained at the predetermined level, the control signals S 300 , S 470  are “L” and “H” in level respectively and the PMOS transistor  412   a  and the NMOS transistor  413   b  of the inverter circuit  410  are both in an off state. Incidentally, each of Ta, Tb (Ta&lt;Tb) shown in FIGS. 6 and 7 represent a period of the pulse signal S 400 . 
     When the substrate bias voltage V bb  does not reach the predetermined level as shown in FIG. 6, the charge pump circuit  200  is operated so as to bring the control signal S 300  output from the substrate bias level sensing circuit  300  to an “H” level. The control signal S 300  is inverted by the inverter  470  to thereby produce the control signal S 470  which is brought to an “L” level. Therefore, the PMOS transistors  412   a ,  422   a ,  432   a ,  442   a ,  452   a  respectively included in the PMOS transistors  412 ,  422 ,  432 ,  442 ,  452 , serving as the first switching means, of the inverter circuits  410 ,  420 ,  430 ,  440 ,  450  are turned on, so that the equivalent resistances of the first switching means  412 ,  422 ,  432 ,  442 ,  452  are reduced. Further, the NMOS transistors  413   b ,  423   b ,  433   b ,  443   b ,  453   b  included in the NMOS transistors  413 ,  423 ,  433 ,  443 ,  453 , serving as the second switching means, are brought to the on state, so that the equivalent resistances of the second switching means  413 ,  423 ,  433 ,  443 ,  453  are also reduced. Since the equivalent resistances of the first switching means  412 ,  422 ,  432 ,  442 ,  452  and those of the second switching means  413 ,  423 ,  433 ,  443 ,  453  are reduced as described above, the period Ta of the pulse signal S 400  supplied from the oscillator  400  to the charge pump circuit  200  is made shorter. The charge pump circuit  200  supplies a voltage not greater than a voltage of a predetermined level to the substrate  10  so that the substrate bias voltage V bb  is rapidly brought to a voltage which does not exceed the predetermined voltage. 
     When the substrate bias voltage V bb  is brought to predetermined level voltage as shown in FIG. 7 the control signal S 300  output from the substrate bias level sensing circuit  300  is rendered “L” in level so that the charge pump circuit  200  is inactivated. At this time, the control signal S 300  which is “L” in level, is inverted by the CMOS inverter  470  so as to produce a control signal S 470  which is “H” in level. Therefore, the PMOS transistors  412   a ,  422   a ,  432   a ,  442   a ,  452   a  of the first switching means  412 ,  422 ,  432 ,  442 ,  452  in the inverter circuits  410 ,  420 ,  430 ,  440 ,  450 , and the NMOS transistors  413   b ,  423   b ,  433   b ,  443   b ,  453   b  of the second switching means  413 ,  423 ,  433 ,  443 ,  453  in the inverter circuits  410 ,  420 ,  430 ,  440 ,  450  are all turned off, so that only the normally on-controlled PMOS transistors  412   b ,  422   b ,  432   b ,  442   b ,  452   b  and NMOS transistors  413   a ,  423   a ,  433   a ,  443   a ,  453   a  are turned on. As a result, the equivalent resistances of the first switching means  412 ,  422 ,  432 ,  442 ,  452  and those of the second switching means  413 ,  423 ,  433 ,  443 ,  453  increase as compared with the case where the substrate bias voltage V bb  shown in FIG. 6 does not reach the predetermined level voltage. Accordingly, a period Tb of the pulse signal S 400  output from the oscillator  400  becomes longer than the period Ta. An oscillating cycle or period within a time interval which makes it unnecessary to produce the output of the oscillator  400  can therefore be increased, thereby making it possible to reduce the power consumption. 
     The buffer  460  has the CMOS inverter  461 , which is electrically connected with the PMOS transistor  462  and the NMOS transistor  463 . Therefore, any one of the transistors series-connected between the power source voltage V CC  and the ground V SS  can be brought to the off state, thereby making it possible to effectively prevent the through current from flowing. 
     Incidentally, the present invention is not necessarily limited to the present embodiment and various modifications can be made. The following modifications can be shown by way of illustrative example. 
     (a) The first embodiment shown in FIG.  1  and the second embodiment shown in FIG. 5 can bring about advantageous effects independently of each other. However, a further great effect can also be obtained by combining the first and second embodiments together. 
     For example, the first switching means  412 ,  422 ,  432 ,  442 ,  452  shown in FIG. 5 are electrically connected in series with the PMOS transistors  112 ,  122 ,  132 ,  142 ,  152  of the inverter circuits  110 ,  120 ,  130 ,  140 ,  150  shown in FIG. 1, respectively. Further, the second switching means  413 ,  423 ,  433 ,  443 ,  453  shown in FIG. 5 are electrically connected in series with the NMOS transistors  113 ,  123 ,  133 ,  143 ,  153 , respectively. With this arrangement, the advantageous effects of the first and second embodiments can be brought about, and the substrate bias generator whose dissipated power is very low and has a superb characteristic can be produced. 
     (b) The oscillators  100 ,  400  shown in FIGS. 1 and 5 respectively comprise the five inverter circuits  110 ,  120 ,  130 ,  140 ,  150  and the five inverter circuits  410 ,  420 ,  430 ,  440 ,  450 . However, the number of the inverter circuits may be arbitrarily set. In this case, the gates of the PMOS transistors  112 ,  122 ,  132 ,  142 ,  152  and those of the NMOS transistors  113 ,  123 ,  133 ,  143 ,  153  in the inverter circuits  110 ,  120 ,  130 ,  140 ,  150  shown in FIG. 1 may be on-off controlled in accordance with the output signals of the inverter circuits turned  2 K (where K=is a natural number) stages backwardly of the present stage. 
     Having now fully described the invention, it will be apparent to those skilled in the art that many changes and modifications can be made without departing from the spirit or scope of the invention as set forth herein.

Technology Classification (CPC): 7