Patent Abstract:
A semiconductor device includes a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor including a III-nitride N-channel layer on one portion of the buffer layer, and a III-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor including a III-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III-nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer, and a III-nitride cap layer doped with P-type dopants on top of the P-channel layer.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is related to L&amp;P 629865-2, U.S. patent application Ser. No. 14/041,667 filed Sep. 30, 2013, and U.S. Pat. No. 8,853,709, issued Oct. 7, 2014, which are incorporated herein by reference as though set forth in full. 
     STATEMENT REGARDING FEDERAL FUNDING 
     None 
     TECHNICAL FIELD 
     This disclosure relates to GaN complementary metal-oxide-semiconductor (CMOS) technology. 
     BACKGROUND 
     GaN N-channel transistors are known in the prior art to have excellent high-power and high-frequency performance. However, there are applications in which it is desirable to have a P-channel GaN transistor that can work with a GaN N-channel transistor on the same integrated circuit or substrate so that a high performance complementary metal-oxide-semiconductor (CMOS) integrated-circuit (IC) can be realized. The embodiments of the present disclosure answer these and other needs. 
     SUMMARY 
     In a first embodiment disclosed herein, a semiconductor device comprises a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor comprising a III-nitride N-channel layer on one portion of the buffer layer, and a III-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor comprising a III-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III-nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer, and a III-nitride cap layer doped with P-type dopants on top of the P-channel layer. 
     In another embodiment disclosed herein, a method for providing a semiconductor device comprises forming a III-nitride (III-N) layer buffer layer on a substrate, forming a III-N N-channel layer on the buffer layer, forming a III-N N-barrier layer on the N-channel layer, forming a first dielectric layer on top of the N-barrier layer, etching the first dielectric layer, the N-barrier layer, and the N-channel layer to form a first mesa for an N-channel transistor and to expose a portion of the buffer layer, forming a second dielectric layer over the first mesa and over a first area of the exposed portion of the buffer layer, wherein the first area is adjacent the first mesa, and wherein a remaining portion of the buffer layer is exposed, forming on top of the remaining exposed portion of the buffer layer a III-N P-barrier layer, forming on top of the III-N P-barrier layer a III-N P-channel layer, forming on top of the III-N P-channel layer a III-N P-cap layer, wherein the III-N P-barrier layer, the III-N P-channel layer, and the III-N P-cap layer form a second mesa for a P-channel transistor, and wherein the first and second mesa are separated by the first area on the buffer layer, removing the second dielectric, and implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor. 
     These and other features and advantages will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features, like numerals referring to like features throughout both the drawings and the description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in accordance with the present disclosure; and 
         FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O  show a process flow for fabrication a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in accordance with the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention. 
     The present disclosure describes a GaN CMOS technology which integrates N-channel and P-channel GaN transistors on the same wafer. The result is a high performance GaN-based complementary metal-oxide-semiconductor (CMOS) integrated circuit. CMOS IC is the preferred topology for many circuit applications, due to its high noise immunity and low power consumption. 
     L&amp;P 629856-2, which is incorporated by reference, describes a P-channel transistor. The GaN ICs of the present disclosure integrate N-channel and P-channel transistors on a common substrate and have better performance than a circuit with discrete GaN N-channel and/or P-channel transistors because more functionality can be achieved with less power consumption. An advantage of the GaN ICs of the present disclosure is that their performance is better than what can be attained with Si CMOS, because high performance N-channel and P-channel GaN transistors are used. 
       FIG. 1  shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in accordance with the present disclosure. The substrate  10  can be GaN, AlN, Sapphire, SiC, Si or any other suitable substrate material.  FIG. 1  is further described below with reference to  FIG. 2O . 
       FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O  show a process flow for fabrication a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in accordance with the present disclosure.  FIG. 2O  is the same as  FIG. 1 , but is also shown in the process flow for completeness. 
     Referring now to  FIG. 2A , a III-N layer buffer layer  12  is on the substrate  10 , and may be grown by chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The buffer layer  12  may be GaN. On top of the buffer layer  12  is III-N N-channel layer  14 , which may be GaN, and which may be grown by MOCVD or MBE. On top of the III-N N-channel layer  14  is a III-N N-barrier layer  16 , which may be grown by MOCVD or MBE. The barrier layer  16  can be AlGaN, AlInN, AlInGaN, AlN, or a combination of these layers. The barrier layer  16  has a wider bandgap than the N-channel layer  14 , and the thickness of the barrier layer  16  is typically in the range of 1˜100 nm. 
     A layer of dielectric  18  is deposited on top of the N-barrier layer  16 . The dielectric  18  may be SiN, SiO 2 , SiON, AlN, or any combination of those, and may have a thickness of 1˜500 nm. 
     Next with reference to  FIG. 2B , the dielectric  18 , the barrier layer  16 , and the channel layer  14  are etched to create a mesa  52  of the channel layer  14 , the barrier layer  16  and the dielectric  18  and to expose a portion of the buffer layer  12 . 
     Then as shown in  FIG. 2C , a dielectric  60  is formed over the mesa  52  and over an area  54  of the exposed portion of the buffer layer  12 . 
     Next with reference to  FIG. 2D , on top of the remaining portion  56  of the buffer layer  12 , a III-N P-barrier layer  20  may be grown by MOCVD or MBE. The P-barrier layer  20  can be AlGaN, AlInN, AlInGaN, AlN, or a combination of these. The thickness of the P-barrier layer  20  is typically in the range of 1˜100 nm. The P-barrier layer  20  assists in the accumulation of holes. On top of the III-N P-barrier layer  20 , a III-N P-channel layer  22  may be grown by MOCVD or MBE. The P-channel layer  22  is typically GaN, with a narrower bandgap than the P-barrier layer  20 . The thickness of the P-channel layer  22  is typically in the range of 1˜100 nm. 
     On top of the III-N P-channel layer  22 , a III-N P-cap layer  24  may be grown by MOCVD or MBE. The III-N P-cap layer  24  is typically GaN doped with Mg. The Mg concentration can vary across the P-cap layer  24 . The thickness of the P-cap layer  24  is typically 1˜100 nm. 
     Then, as shown in  FIG. 2E , the dielectric  60 , which masked the mesa  52  and the area  54  of the buffer layer  12  while forming the P-barrier layer, the P-channel layer, and the P-cap layer, is removed. The result, as shown in  FIG. 2E  is the mesa  52  for an N-channel transistor, and a mesa  58  for a P-channel transistor. 
     Next, as shown in  FIG. 2F , the mesa  52  may be isolated from the mesa  58  by ion implantation  50  in the area  54  and on the sides of mesas  52  and  58 . 
     Then, as shown in  FIG. 2G , a dielectric  26  is deposited over the P-cap layer  24  of mesa  58 , and over a portion of area  54  between the mesa  52  and the mesa  58 . 
     Next, as shown in  FIG. 2H , a P-gate trench  62  is formed in dielectric  26 . The bottom of the P-gate trench  62  may extend partially or entirely through the P-cap layer  24 , and may also extend partially through the P-channel layer  22 . 
     Then, as shown in  FIG. 2I , a N-gate trench  64  is formed in dielectric  18 . The bottom of the trench  64  may extend partially or entirely through the dielectric  18 , partially or entirely through the barrier layer  16 , and partially or entirely through the N-channel layer  14 , so that the N-gate trench stops anywhere between the top surface of dielectric  18  and the top surface of the buffer layer  12 . 
     Next, as shown in  FIG. 2J , a dielectric  28  is formed over the device, so that the dielectric  28  is on top of dielectric  18 , covering the bottom and sides of N-gate trench  64 , on top of dielectric  26 , and covering the bottom and sides of P-gate trench  62 . The dielectric  28  is typically a stack of AlN/SiN layer, grown by MOCVD. The dielectric  28  may also be only deposited in the N-gate trench  64  and the P-gate trench  62  to insulate the N-gate electrode  32  and the P-gate electrode  42 , respectively, for low gate leakage current. 
     Then, as shown in  FIG. 2K , N-ohmic openings  70  and  72  are made on opposite sides of the N-gate trench  64 . The openings  70  and  72  are made through the dielectric  28 , and may be made partially or entirely through the dielectric  18 , and in some cases partially or entirely through the N-barrier layer  16 . 
     Next, as shown in  FIG. 2L , the openings  70  and  72  are filled with metal to form N-ohmic electrodes  74  and  76 , forming source and drain contacts, respectively, for the N-channel transistor. 
     Then, as shown in  FIG. 2M , P-ohmic openings  80  and  82  are formed on opposite sides of the P-gate trench  62 . The openings  80  and  82  are made through the dielectric  28 , through the dielectric  26 , and in some cases partially or entirely through the P-cap layer  24 . 
     Next, as shown in  FIG. 2N , the openings  80  and  82  are filled with metal to form P-ohmic electrodes  84  and  86 , forming source and drain contacts, respectively, for the P-channel transistor. 
     Finally, as shown in  FIG. 2O , the N-gate trench  64  is filled with metal  32  to form a gate contact for the N-channel transistor, and the P-gate trench  62  is filled with metal  42  to form a gate contact for the P-channel transistor. 
     The result is a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors, as shown in  FIG. 1 , which is the same as  FIG. 2O . 
     Referring now to  FIG. 1 , the substrate  10  may be but is not limited to GaN, AlN, Sapphire, SiC, or Si. The III-N buffer layer  12  is on the substrate  10 . As shown in  FIG. 1 , on top of one portion of the buffer layer  12 , is the III-N N-channel layer  14  on the buffer layer  12 , and the III-N N-barrier layer  16  on the N-channel layer  14 . On top of another portion of the buffer layer  12 , is the III-N P-barrier layer  20  on the buffer layer  12 , the III-N P-channel layer  22  on the P-barrier layer  20 , and the III-N P-Cap layer  24  on the P-channel layer  22 . 
     The dielectric  28  covers the bottom and sides of N-gate trench  64 , and the bottom and sides of P-gate trench  62 , as described above. Metal  32  fills gate trench  64  to form a gate contact for the N-channel transistor, and metal  42  fills gate trench  62  to form a gate contact for the P-channel transistor. 
     N-ohmic electrodes  74  and  76  provide source and drain contacts, respectively, for the N-channel transistor, and P-ohmic electrodes  84  and  86  provide source and drain contacts, respectively, for the P-channel transistor. 
     Ion implantation  50  in the area  54  between the N-channel transistor and the P-channel transistor provides isolation of the N-channel transistor from the P-channel transistor. 
     A person skilled in the art will understand that the order of the steps of the process flow of  FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O  may be in another order to achieve the GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit shown in  FIG. 1 . A person skilled in the art will also understand that well known steps of patterning and etching may be used in the process flow, such as for example to remove a layer or portion of a layer. Such well known processes are not described in detail, because they are widely used in semiconductor processing. 
     Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein. 
     The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . .”

Technology Classification (CPC): 7