Patent Abstract:
A method for fabricating an integrated circuit includes providing a substrate having thereon a material layer; forming trenches in the material layer; forming damascened wires in the trenches; covering the damascened wires and the material layer with a cap layer; forming a through hole in the cap layer that exposes a portion of the material layer; and removing the material layer thereby forming an air gap between the damascened wires.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a continuation-in-part of U.S. application Ser. No. 12/246,451 filed Oct. 6, 2008, which is included in its entirety herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates, in general, to a method for fabricating an integrated circuit. More particularly, the present invention relates to a method for fabricating an integrated circuit with an air gap. 
         [0004]    2. Description of the Prior Art 
         [0005]    Semiconductor manufacturers have been trying to shrink transistor size in integrated circuits (IC) to improve chip performance, which leads to the result that the integrated circuit speed is increased and the device density is also greatly increased. However, under the increased IC speed and the device density, the RC delay becomes the dominant factor. 
         [0006]    To facilitate further improvements, semiconductor IC manufacturers have been driven by the trend to resort to new materials utilized to reduce the RC delay by either lowering the interconnect wire resistance, or by reducing the capacitance of the inter-layer dielectric (ILD). A significant improvement is achieved by replacing the aluminum (Al) interconnects with copper, which has 30% lower resistivity than that of Al. Further advances are facilitated by improving electrical isolation and reducing parasitic capacitance in high density integrated circuits. 
         [0007]    Current attempts to improve electrical isolation and reduce parasitic capacitance in high density integrated circuits involve the implementation of low-k dielectric materials such as FSG, HSQ, SiLK™, FLAREK™. To successfully integrate the low K dielectric materials with conventional semiconductor manufacturing processes, several basic characteristics including low dielectric constant, low surface resistivity (&gt;10 15 Ω), low compressive or weak tensile (&gt;30 MPa), superior mechanical strength, low moisture absorption and high process compatibility are required. 
         [0008]    While the aforesaid materials respectively have a relatively low dielectric constant, they are not normally used in semiconductor manufacturing process due to increased manufacturing complexity and costs, potential reliability problems and low integration between the low-k materials and metals. Therefore, there is a strong need in this industry to provide a method for fabricating an integrated circuit in order to improve the integrated circuit performance. 
       SUMMARY OF THE INVENTION  
       [0009]    It is one objective of the present invention to provide an improved method for forming an integrated circuit with air gap in order to solve the above-mentioned conventional problems. 
         [0010]    To meet these ends, according to one aspect of the present invention, there is provided a method for fabricating an integrated circuit. A substrate having thereon a first conductive wire and a second conductive wire is provided. A liner layer is formed on the first conductive wire and second conductive wire. An ashable material layer is filled into a space between the first conductive wire and second conductive wire. The ashable material layer is then polished to expose a portion of the liner layer. A cap layer is formed on the ashable material layer and on the exposed liner layer. A through hole is extended into the cap layer to expose a portion of the ashable material layer. Thereafter, the ashable material layer is removed by way of the through hole. 
         [0011]    In one aspect, another embodiment of this invention provides a method for fabricating an integrated circuit, comprising the steps of providing a substrate having thereon a material layer; forming trenches in the material layer; forming damascened wires in the trenches; covering the damascened wires and the material layer with a cap layer; forming a through hole in the cap layer that exposes a portion of the material layer; and removing the material layer thereby forming an air gap between the damascened wires. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0013]      FIG. 1  to  FIG. 8  are schematic, cross-sectional diagrams showing a method for fabricating an integrated circuit in accordance with one preferred embodiment of this invention. 
           [0014]      FIG. 9  to  FIG. 14  are schematic, cross-sectional diagrams showing a method for fabricating an integrated circuit in accordance with another embodiment of this invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0015]    Without the intention of a limitation, the invention will now be described and illustrated with reference to the preferred embodiments of the present invention. 
         [0016]      FIG. 1  to  FIG. 8  are schematic, cross-sectional diagrams showing a method for fabricating an integrated circuit in accordance with the preferred embodiment of this invention. As shown in  FIG. 1 , a substrate  10  is provided. A first conductive wire  12   a  and a second conductive wire  12   b  are provided on the substrate  10 . The first conductive wire  12   a  is adjacent to the second conductive wire  12   b.  For example, a space (S) between the first conductive wire  12   a  and the second conductive wire  12   b  ranges between 30 nanometers and 500 nanometers. According to this embodiment of the present invention, the first and second conductive wires  12   a  and  12   b  are both composed of metal such as aluminum, but not limited thereto. 
         [0017]    It is understood that in other embodiments the first and second conductive wires  12   a  and  12   b  may be composed of copper or aluminum/copper alloys. According to this embodiment of the present invention, the first conductive wire  12   a  has an exposed top surface  112   a  and exposed sidewalls  114   a,  and the second conductive wire  12   b  has an exposed top surface  112   b  and exposed sidewalls  114   b.    
         [0018]    As shown in  FIG. 2 , subsequently, a chemical vapor deposition (CVD) process is carried out to deposit a conformal liner layer  14  on the top surface  112   a  and sidewalls  114   a  of the first conductive wire  12   a  and the top surface  112   b  and sidewalls  114   b  of the second conductive wire  12   b.  The liner layer  14  also covers the substrate  10 . 
         [0019]    According to this embodiment of the present invention, the liner layer  14  preferably comprises silicon oxide or silicon nitride and has thickness of 0-1000 angstroms. The thickness of the liner layer  14  is insufficient to fill the space  13  between the first conductive wire  12   a  and the second conductive wire  12   b.  In other embodiments, the liner layer  14  may comprise SiO 2 , Si 3 N 4 , SiON, SiC, SiOC, SiCN or any other suitable materials. 
         [0020]    According to the preferred embodiment, the liner layer  14  can protect the first conductive wire  12   a  and the second conductive wire  12   b  from corrosion. The liner layer  14  also acts as a polishing stop layer during the subsequent chemical mechanical polishing (CMP) process. 
         [0021]    As shown in  FIG. 3 , an ashable material layer  16  is formed on the liner layer  14 . The ashable material layer  16  may comprise carbon layer or fluorine-doped carbon layer. According to the preferred embodiment, the ashable material layer  16  is filled into the space  13  between the first conductive wire  12   a  and the second conductive wire  12   b.  The space  13  may be completely or partially filled with the ashable material layer  16 . In a situation where the space  13  is not filled with the ashable material layer  16 , a void (not shown) may be formed within the space  13 . 
         [0022]    According to the preferred embodiment of this invention, the ashable material layer  16  may be formed by CVD methods such as PECVD method and HDPCVD method, or spin-on deposition (SOD) methods. 
         [0023]    As shown in  FIG. 4 , subsequently, a planarization process such as CMP process is performed to polish away a portion of the ashable material layer  16 , thereby exposing the liner layer  14  on the top surface  112   a  of the first conductive wire  12   a  and the liner layer  14  on the top surface  112   b  of the second conductive wire  12   b.  As previously mentioned, the liner layer  14  acts as a polishing stop layer during the CMP process. After the CMP process, a top surface of the ashable material layer  16  is substantially coplanar with the exposed surfaces of the liner layer  14 . 
         [0024]    As shown in  FIG. 5 , a conventional CVD process is carried out to deposit a cap layer  18  on the ashable material layer  16  and on the exposed surfaces of the liner layer  14 . According to the preferred embodiment of this invention, the cap layer  18  is a silicon oxide layer. However, the cap layer  18  may be a silicon nitride layer or a low-k dielectric layer. 
         [0025]    It is one germane feature of this invention that the ashable material layer  16  in the space  13  must sustain the high temperatures during the CVD deposition of the cap layer  18 . Generally, the temperature employed to deposit the cap layer  18  is about 350° C. In this case, the ashable material layer  16  in the space  13  must sustain at least 350° C. In this regard, some organic materials or photoresist materials are inapplicable to the present invention method. 
         [0026]    As shown in  FIG. 6 , a photoresist pattern  20  is formed on the cap layer  18 . The photoresist pattern  20  has an aperture  20   a  exposing a portion of the cap layer  18  directly above the space  13 . The method for forming the photoresist pattern  20  may include conventional lithographic process such as photoresist coating, exposure, development and baking. 
         [0027]    As shown in  FIG. 7 , thereafter, an etching process such as a dry etching process is performed to etch the cap layer  18  through the aperture  20   a  of the photoresist pattern  20 , thereby forming a through hole  18   a  in the cap layer  18 . The through hole  18   a  exposes a portion of the ashable material layer  16 . The photoresist pattern  20  is then stripped off. 
         [0028]    As shown in  FIG. 8 , an ashing process is carried out. For example, oxygen plasma is utilized to completely remove the ashable material layer  16  between the first conductive wire  12   a  and the second conductive wire  12   b  by way of the through hole  18   a  of the cap layer  18 , thereby forming an air gap  30  between the first conductive wire  12   a  and the second conductive wire  12   b.  Subsequently, a CVD process is performed to form a dielectric layer  32  over the cap layer  18 . The dielectric layer  32  seals the through hole  18   a  of the cap layer  18  thereby forming a hermetic air gap  30 . According to the preferred embodiment of this invention, the dielectric layer  32  may be silicon oxide or low-k dielectric materials. In other embodiments, the deposition of the dielectric layer  32  may be implemented concurrently with the aforesaid ashing process. 
         [0029]    The method for fabricating the integrated circuit structure of the present invention has at least the following advantages: (1) The method is completely compatible with current integrated circuit manufacturing processes and no additional investment or development of new equipment is required; (2) The method is cost effective; and (3) The method can provide maximized and unified air gap structure between metal interconnection lines, which is capable of effectively reducing RC delay and improving performance of the integrated circuit device. 
         [0030]      FIG. 9  to  FIG. 14  are schematic, cross-sectional diagrams showing a method for fabricating an integrated circuit in accordance with another embodiment of this invention. As shown in  FIG. 9 , a substrate  100  is provided. The substrate  100  may be a silicon substrate or any suitable semiconductor substrate known in the art. It is to be understood that the substrate  100  may further comprises circuit elements such as transistors or capacitors and dielectric layers or conductive wires overlying the circuit elements, which are not shown for the sake of simplicity. An ashable material layer  116  is formed on a top surface of the substrate  100 . The ashable material layer  116  may be made of thermal degradable polymers, carbon or fluorine-doped carbon. Some of the typical thermal degradable polymers are disclosed, for example, in U.S. Pub. No. 2007/0149711 A1 assigned to Dow Global Technologies Inc., which should not be used to limit the scope of the invention. 
         [0031]    Subsequently, as shown in  FIG. 10 , trenches  116   a  are formed in the ashable material layer  116 . Each of the trenches  116  exposes a portion of the underlying substrate  100 . The trenches  116   a  may be line-shaped trenches or via holes. It is noteworthy that although only the exemplary single damascene process is shown through  FIG. 9  to  FIG. 14 , the present invention may be applicable to dual damascene processes or any other types of copper damascene process. After the formation of the trenches  116   a,  a diffusion barrier layer  120  such as Ta/TaN or Ti/TiN is deposited on interior surface of the trenches  116   a  and on the top surface of the ashable material layer  116 . A low-resistance metal layer  122  such as copper is then deposited on the diffusion barrier layer  120  and fills the trenches  116   a.    
         [0032]    As shown in  FIG. 11 , a conventional chemical mechanical polishing (CMP) process is then carried out to polish the low-resistance metal layer  122  until the low-resistance metal layer  122  and the diffusion barrier layer  120  directly above the top surface of the ashable material layer  116  are completely removed. After CMP, the remanent low-resistance metal layer  122  and the diffusion barrier layer  120  damascened in the trenches  116   a  constitute damascened interconnection wires  200 . Each of the damascened interconnection wires  200  has a top surface that is substantially flush with the top surface of the ashable material layer  116 . 
         [0033]    Thereafter, a cap layer  124  is deposited on the substrate to cover the damascened interconnection wires  200  and the ashable material layer  116 . Suitable materials for the cap layer  124  include but not limited to SiOC, SiO 2 , Si 3 N 4 , SiCN, SiC. 
         [0034]    As shown in  FIG. 12 , a conventional photolithographic process and etching process are performed to form through holes  124   a  in the cap layer  124 . The aforesaid photolithographic process may include photoresist coating and baking, exposure and development. Each of the through holes  124   a  exposes a portion of the ashable material layer  116  between the damascened interconnection wires  200  and does not expose any of the damascened interconnection wires  200 . 
         [0035]    As shown in  FIG. 13 , using the cap layer  124  as a protection layer that protects the top surface of the damascened interconnection wires  200 , an oxygen plasma etching process is performed to etch and remove the ashable material layer  116 , thereby forming air gaps  130  between the damascened interconnection wires  200 . 
         [0036]    As shown in  FIG. 14 , subsequently, a CVD process is performed to form a dielectric layer  132  over the cap layer  124 . The dielectric layer  132  seals the through hole  124   a  of the cap layer  124  thereby forming a substantially hermetic air gap  130 . According to the preferred embodiment of this invention, the dielectric layer  132  may be silicon oxide or low-k dielectric materials. In other embodiments, the deposition of the dielectric layer  132  may be implemented concurrently with the aforesaid ashing process. 
         [0037]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 7