Patent Abstract:
The present invention relates to a semiconductor memory device in which current consumption incurred by excessive over-driving can be prevented by dividing a memory core region into a plurality of memory blocks and then over-driving only sense amplifiers of a corresponding memory block.

Full Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a sense amp over-driving structure and method of over-driving a sense amplifier thereof.  
         [0003]     2. Discussion of Related Art  
         [0004]     As a driving voltage of semiconductor memory devices is gradually lowered, the processing speed thereof requires the high speed and several technical solutions for satisfying the requirement have been proposed. One of them is a sense amp over-driving method in which a sense amplifier is driving with a driving power being divided into two. However, the sense amp over-driving method has a drawback in that current of a memory device is excessively consumed due to excessive over-driving.  
         [0005]     Of the existing over-driving methods, there is a blind method. In the blind method, when a restore line RTO connected to a PMOS transistor of a sense amplifier (not shown) and a restore line /S connected to a NMOS transistor of the sense amplifier are enabled, an external power supply voltage (VDD) and a cell power supply voltage (Vcore) are shorted for a predetermined pulse period to prevent the cell power supply voltage (Vcore) from lowering. The blind method, however, has a drawback in that excessive current is consumed since current is supplied to the corresponding whole bank.  
       SUMMARY OF THE INVENTION  
       [0006]     An advantage of the present invention is that it prevents current consumption by excessive over-driving by over-driving only a sense amplifier of a corresponding memory block after dividing a memory core region into a plurality of memory blocks.  
         [0007]     A semiconductor memory device having a sense amp over-driving structure according to a first aspect of the present invention includes a plurality of memory blocks having sense amplifiers, a sense amp over-driving controller that combines a plurality of block select signals for selecting the memory blocks and a sense amp over-driving signal and generating a plurality of block over-driving signals, and a sense amp over-driver that over-drives only sense amplifier of a memory block in which an actual operation is performed in response to the plurality of block over-driving signals.  
         [0008]     A sense amp over-driving method of a semiconductor memory device according to a second aspect of the present invention includes the steps of dividing a memory core region into a plurality of memory blocks having sense amplifiers, combining a plurality of block select signals for selecting the memory blocks and a sense amp over-driving signal for over-driving the sense amplifiers and generating a plurality of block over-driving signals, and over-driving only sense amplifiers of a memory block in which an actual operation is performed, of the plurality of memory blocks in response to the plurality of block over-driving signals. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a block diagram showing a semiconductor memory device having a sense amp over-driving structure according to a preferred embodiment of the present invention;  
         [0010]      FIG. 2  is a circuit diagram showing a sense amp over-driver and a sense amplifier shown in  FIG. 1 ;  
         [0011]      FIG. 3  is a timing diagram showing waveforms of signals of  FIG. 1 ; and  
         [0012]      FIG. 4  shows a current waveform by sense amp over-driving of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0013]     The present invention will now be described in connection with preferred embodiments with reference to the accompanying drawings.  
         [0014]      FIG. 1  is a block diagram showing a semiconductor memory device having a sense amp over-driving structure according to a preferred embodiment of the present invention.  
         [0015]     Referring to  FIG. 1 , the semiconductor memory device includes memory blocks BK 0  to BK 3 , sense amp over-driving controllers  110 - 1 ,  110 - 2  and sense amp over-driver units  120 - 1 ,  120 - 2 .  
         [0016]     Only four memory blocks are shown in  FIG. 1 . However, the number of memory blocks may be varied depending on the size of a bank. Furthermore, sense amplifier regions (SA) on upper/lower sides of a memory cell region (MC). The sense amp over-driving controllers  110 - 1 ,  110 - 2  and the sense amp over-driver units  120 - 1 ,  120 - 2  are disposed on right and left sides of the memory blocks BK 0  to BK 3 .  
         [0017]     The sense amp over-driving controller  110 - 1  logically combines block select signals (BS 0  to BS 3 ) and a sense amp over-driving signal (SAOVDP) and generates a block over-driving signal (BSAOVDP 0  to BSAOVDP 4 ) for over-driving a sense amplifier within the sense amplifier region (SA) of a corresponding memory block.  
         [0018]     The sense amp over-driving controller  110 - 1  includes NOR gates NR 1  to NR 5 , inverters IV 1  to IV 5  and NAND gates ND 1  to ND 5 . The NOR gates NR 1  performs a NOR operation on a ground voltage (VSS) and a block select signal (BS 0 ). The NOR gates NR 2  performs a NOR operation on the block select signals (BS 0 , BS 1 ). The NOR gates NR 3  performs a NOR operation on the block select signals (BS 1 , BS 2 ). The NOR gates NR 4  performs a NOR operation on the block select signals (BS 2 , BS 3 ). The NOR gates NR 5  performs a NOR operation on the block select signal (BS 3 ) and the ground voltage (VSS). The inverters IV 1  to IV 5  invert output signals of the NOR gates NR 1  to NR 5 , respectively, and output inverted signals.  
         [0019]     The NAND gate ND 1  performs a NAND operation on the output signal of the inverter IV 1  and the sense amp over-driving signal (SAOVDP) and generates a block over-driving signal (BSAOVDP 0 ) for over-driving a sense amplifier within the sense amplifier region (SA) of the first memory block BK 0 .  
         [0020]     The NAND gates ND 2  performs a NAND operation on the output signal of the inverter IV 2  and the sense amp over-driving signal (SAOVDP) and generates a block over-driving signal (BSAOVDP 1 ) for over-driving a sense amplifier of the sense amplifier region (SA) of the first or second memory block BK 0  or BK 1 .  
         [0021]     The NAND gates ND 3  performs a NAND operation on the output signal of the inverter IV 3  and the sense amp over-driving signal (SAOVDP) and generates a block over-driving signal (BSAOVDP 2 O) for over-driving a sense amplifier within the sense amplifier region (SA) of the second or third memory block BK 1  or BK 2 .  
         [0022]     The NAND gates ND 4  performs a NAND operation on the output signal of the inverter IV 4  and the sense amp over-driving signal (SAOVDP) and generates a block over-driving signal (BSAOVDP 3 ) for over-driving a sense amplifier within the sense amplifier region (SA) of the third or fourth memory block BK 2  or BK 3 .  
         [0023]     The NAND gates ND 5  performs a NAND operation on the output signal of the inverter IV 4  and the sense amp over-driving signal (SAOVDP) and generates a block over-driving signal (BSAOVDP 4 ) for over-driving a sense amplifier within the sense amplifier region (SA) of the fourth memory block BK 4 .  
         [0024]     The sense amp over-driver units  120 - 1  over drives sense amplifiers of a corresponding memory block in response to the block over-driving signals (BSAOVDP 0  to BSAOVDP 4 ), and includes PMOS transistors MP 1  to MP 5 .  
         [0025]     The PMOS transistor MP 1  applies a current, which is generated by the external power supply voltage (VDD), to the restore line RTO shown in  FIG. 2 , which will be described later, in response to the block over-driving signal (BSAOVDP 0 ) when the block select signal (BS 0 ) becomes logic high, thus over-driving corresponding sense amplifiers of the first memory block BK 0 .  
         [0026]     The PMOS transistor MP 2  applies a current, which is generated by the external power supply voltage (VDD), to the restore line RTO in response to the block over-driving signal (BSAOVDP 1 ) when the block select signal (BS 0  or BS 1 ) becomes logic high, thus over-driving corresponding sense amplifiers of the first or second memory block BK 0  or BK 1 .  
         [0027]     The PMOS transistor MP 3  applies a current, which is generated by the external power supply voltage (VDD), to the restore line RTO in response to the block over-driving signal (BSAOVDP 2 ) when the block select signal (BS 1  or BS 2 ) becomes logic high, thus over-driving corresponding sense amplifiers of the second or third memory block BK 2  or BK 3 .  
         [0028]     The PMOS transistor MP 4  applies a current, which is generated by the external power supply voltage (VDD), to the restore line RTO in response to the block over-driving signal (BSAOVDP 3 ) when the block select signal (BS 2  or BS 3 ) becomes logic high, thus over-driving corresponding sense amplifiers of the third or fourth memory block BK 3  or BK 4 .  
         [0029]     The PMOS transistor P 5  applies a current, which is generated by the external power supply voltage (VDD), to the restore line RTO in response to the block over-driving signal (BSAOVDP 4 ) when the block select signal (BS 3 ) becomes logic high, thus over-driving corresponding sense amplifiers of the fourth memory block BK 4 .  
         [0030]      FIG. 2  shows a sense amp over-driver MP shown in  FIG. 1 , sense amplifier drivers MP 11 , MN 11  within the sense amplifier region (SA) and one sense amplifier SA 1 . Though one sense amplifier is shown the sense amplifier region (SA), it is assumed that a plurality of sense amplifiers exists in the sense amplifier region (SA).  
         [0031]      FIG. 3  is a timing diagram showing waveforms of signals of  FIG. 1 .  
         [0032]     In  FIG. 3 , the sense amp over-driving signal (SAOVDP) is generated as a high pulse at the moment when the sense amplifier enable signals (SAP, SAN) are enabled as logic high after the block select signal (BS) is enabled as logic high.  
         [0033]     A method of over-driving sense amplifiers within the first memory block BK 0  will be described below as an example with reference to  FIGS. 2 and 3 .  
         [0034]     If the first block select signal (BS 1 ) is enabled as logic high, the sense amplifier enable signals (SAP, SAN) are driven as logic high after a predetermined time elapses. If the sense amp over-driving signal (SAOVDP) becomes a high pulse, the sense amp over-driving controllers  110 - 1 ,  110 - 2  generate the block over-driving signals (BSAOVDP 0 , BSAOVDP 1 ) of a low pulse. Therefore, the PMOS transistors MP 1 , MP 2 , MP 6 , MP 7  within the sense amp over-driver units  120 - 1 ,  120 - 2  are turned on, so that a current generated by the external power supply voltage (VDD) is applied to the restore line RTO. At this time, the sense amplifier drivers MP 11 , MN 11  within the sense amplifier region (SA) shown in  FIG. 2  are already turned on before the sense amp over-drivers MP 1 , MP 2 , MP 6 , MP 7  are turned on. Therefore, if the sense amp over-drivers MP 1 , MP 2 , MP 6 , MP 7  are turned on, a current by the external power supply voltage (VDD) and a current by the cell power supply voltage (Vcore) become short and only sense amplifiers of a selected memory block BK 0  are over-driven accordingly.  
         [0035]     As described above, only sense amplifiers of a memory block in which an actual operation is performed are over-driven using the block select signal (BS), and sense amplifiers of a memory block in which an actual operation is not performed are not over-driven. It is thus possible to prevent current consumption incurred by excessive over-driving.  
         [0036]      FIG. 4  shows a current waveform by sense amp over-driving of  FIG. 1 . Only sense amplifiers of a memory block in which an operation is actually performed are over-driven. Therefore, it can be seen that current by over-driving is not excessively consumed. In  FIG. 4 , ODR indicates a case where over-driving is performed and NODR indicates a case where over-driving is not performed.  
         [0037]     As described above, according to the present invention, only sense amplifiers of a memory block requiring an operation are over-driven. Therefore, existing excessive current consumption can be saved, which is very effective in low-power design.  
         [0038]     Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims.

Technology Classification (CPC): 6