Patent Abstract:
A write driver circuit ( 38 ) uses a matching resistors (R 0 , R 1 ) to match the impedance of the head ( 32 ) disposed between output nodes (OUTP, OUTN). Control circuitry (Q 4 , Q 5 , Q 6 , Q 7 , R 2 , R 4 , R 6  and R 7 ) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver ( 40   a   , 40   b ), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q 28  and Q 29 ) to provide enhanced current to the bases of the output transistors on an as needed basis.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of the filing date of copending provisional application U.S. Ser. No. 60/515,508, filed Oct. 29, 2003, entitled “Power Efficient AB Driver For Use in Disk Drive Preamplifier Write Drivers”. 

   STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
   Not Applicable 
   BACKGROUND OF THE INVENTION 
   1. Technical Field 
   This invention relates in general to disk storage devices and, more particularly, to a high speed preamplifier/write driver. 
   2. Description of the Related Art 
   Almost all business and home computers use a hard disk drive storage system for mass storage requirements. A hard disk drive stores data by individually modifying the magnetic orientation of small regions of a disk surface. As shown in  FIG. 1 , a hard disk drive  10  typically includes one or more rotating disks  12 . A head assembly  14  associated with each surface of the disks  12  typically includes separate read and write heads for reading data from the disk and writing data to the disk. The write head is essentially a small coil of wire which stores data by magnetizing small regions along a disk&#39;s tracks. A current driven through the write head in a first direction magnetizes a small region of the disk under the head at a first orientation and a current driven through the write head in the opposite direction magnetizes a small region of the disk under the head at a second orientation. The read head distinguishes the magnetic orientation of each bit location to derive logical “1s” and “0s”. 
   The circuit which drives the write head is referred to as a “write driver”, which is part of the read/write preamplifier  16 . The write driver controls the direction of the flow of current through the head, responsive to information from the channel circuitry  18 . The channel circuitry receives data from the hard drive controller  20  of the computer  22 . The computer  22  further includes processing circuitry and other components (not shown). 
   A recent requirement from disk drive manufacturers is that the preamplifier write driver provides a symmetric write driver signal for reduced noise coupling. A symmetric write driver must have equal and opposite positive and negative write driver signals over all frequency data patterns. These write driver signals must be symmetric in amplitude as well as transient behavior. If the positive and negative write driver signals are well matched in amplitude and transient behavior, the write driver will have virtually no common-mode signal component. The requirement of a symmetrical write driver is driven by read head reliability as the new generation of magneto-resistive (MR) heads is much more sensitive to capacitive coupling from the write driver. Non-symmetrical write drivers with large common-mode voltage components can capacitively couple damaging voltage levels, both differentially and single-ended, to the read head. Generally symmetrical write drivers have been developed to address this problem. 
   Write drivers drive the write head differentially to achieve the maximum voltage possible across the write head for both positive and negative transitions. The requirement of driving the write head differentially means that both sides of the write driver must have bi-directional drive capability. 
     FIGS. 2   a  and  2   b  illustrate examples of typical prior art current-mode write drivers. Unlike voltage-mode write drivers, where an impedance match resistor can be placed in series with the low impedance output of the voltage drive device, current-mode write drivers must place the impedance match resistor in parallel with the high-impedance output of the current drive device. Traditionally, in symmetrical write drivers (with the common-mode output voltage kept near ground), the impedance match resistor has been placed either from each output node to ground through a capacitor or across the output nodes through a capacitor. The purpose of the capacitor is to prevent DC current from being stolen by the impedance match resistors. 
   These methods have two main drawbacks. First, a large amount of current is shunted away from the inductive write head load (connected between the output nodes) through the low-valued impedance match resistors during the overshoot or pulsing time period when the output voltages can swing near rail to rail (−5 v to +5 v). This current is essentially wasted since it is not being delivered to the write head, which increases power dissipation without increasing performance. Secondly, the capacitor must be sized somewhat large to realize a low impedance at frequencies of interest and provide effective impedance matching. This capacitance, along with the impedance match resistance, creates an RC pole that lies well within the write data frequency range. Thus, settling is not achieved. The corresponding RC decay adversely affects the write current waveshape and hurts performance. The capacitor therefore limits the maximum frequency of the write driver. 
   In  FIG. 2   a , the output ports OUTP and OUTN drive the inductive write head load  32 . OUTP and OUTN are driven by the output devices Q 0 , Q 1 , Q 2  and Q 3 . The symmetrical nature of an NPN differential pair (Q 2 –Q 3 ) balanced by a PNP differential pair (Q 0 –Q 1 ) provides the ability to keep the common-mode output voltage around ground over a high frequency pattern. Q 0 –Q 3  are driven by the differential write data input voltages VTOPN, VTOPP, VBOTN, VBOTP. If VTOPP is at a lower potential than VTOPN and VBOTN is at a higher potential than VBOTP, then PNP transistor Q 1  and NPN transistor Q 2  will conduct, while PNP transistors Q 0  and NPN transistor Q 3  will not conduct. Accordingly, a current path is established from Vcc to Vee (as shown by the dotted line) through R 5 , Q 1 , head  32 , Q 2  and R 3 . Similarly, If VTOPN is at a lower potential than VTOPP and VBOTP is at a higher potential than VBOTN, then PNP transistor Q 0  and NPN transistor Q 3  will conduct, while PNP transistors Q 1  and NPN transistor Q 2  will not conduct. Accordingly, a current path is established from Vcc to Vee in the opposite direction through head  32 . The write driver of  FIG. 2   b  works in a similar fashion; the difference between the circuits of  FIGS. 2   a  and  2   b  concerns the manner in which impedance matching is performed. 
   In  FIG. 2   a , impedance matching is provided by the impedance match resistors R 0  and R 1  (both having a value equal to half of the matching resistance) along with C 0  and C 1 . In  FIG. 2   b , impedance matching is provided by the impedance match resistors R 20  and R 21  (both having a value equal to half of the matching resistance) along with C 4 . The DC voltage of both OUTP and OUTN, as well as the AC common-mode output voltage, is set around ground by R 14  and R 15  in  FIG. 2   a  and by R 16  and R 17  in  FIG. 2   b . The value of these resistors is large compared to the impedance match resistors. 
   As mentioned above, the output voltages OUTP and OUTN can swing near rail to rail (−5 v to +5 v). Typical impedance match resistors are valued around 70 ohms differential. As an example, a differential output voltage swing of 8 v (which allows headroom for circuitry) during the overshoot phase placed across a differential match resistance of 70 ohms shunts 114 mA away from the write head load through the match resistors. This large amount of wasted current significantly increases power dissipation without any increase in performance. 
   Accordingly, a need has arisen for a balanced current-mode write driver with improved power efficiency and without an RC pole that limits the speed of the device. 
   BRIEF SUMMARY OF THE INVENTION 
   In the present invention, a hard disk storage system comprises a magnetic disk, a head for writing data to the disk and a preamplifier for orienting a current through the head in a desired direction responsive to a data signal. The preamplifier comprises circuitry coupled across the head at first and second output nodes to provide a current path through the head in a direction responsive to the data signal, a first matching resistor coupled between a first reference node and the first output node and a second matching resistor coupled between a second reference node and the second output node. Control circuitry maintains the voltage of the first reference node at substantially the same voltage as the first output node and maintains the voltage of the second reference node at substantially the same voltage as the second output node. 
   Because the matching resistors are coupled between nodes at substantially the same voltage, the amount of power dissipated to impedance match the outputs of the write driver is substantially reduced. Further, since no capacitors are needed, the impedance matching is DC coupled and there is no RC pole and corresponding settling issue as in the prior art. Thus, better performance is obtained with less power wasted. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  illustrates a hard drive system coupled to a computer; 
       FIGS. 2   a  and  2   b  illustrate prior art write drivers used in the preamplifier of the hard drive system of  FIG. 1 ; 
       FIG. 3  is a schematic representation of an improved write driver; 
       FIG. 4  is a timing diagram showing the operation of the write driver of  FIG. 3 ; 
       FIG. 5  is a schematic representation of prior art AB driver; 
       FIG. 6  illustrates an improved AB driver for use in the circuit of  FIG. 3 ; and 
       FIG. 7  is a timing diagram illustrating the operation of the AB driver of  FIG. 6 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention is best understood in relation to  FIGS. 3–7  of the drawings, like numerals being used for like elements of the various drawings. 
     FIG. 3  illustrates a schematic representation of a write driver circuit  38  with low power dissipation which eliminates the need for a capacitor. For purposes of illustration, components with a similar function to those shown in  FIG. 2   a  are labeled with the same reference. Thus, the core output structure of the output devices Q 0 –Q 3  (with R 3 , R 5 ) and the impedance match resistors R 0  and R 1  can be the same as in the prior art. Also, the input write data voltages and output nodes can remain the same. 
   The embodiment of  FIG. 3  adds control circuitry provided by transistors Q 4 , Q 5 , Q 6  and Q 7  (with R 2 , R 4 ), reference resistors R 6 , R 7 , and low output impedance drivers  40   a  and  40   b , which minimizes the current through the matching resistors R 0  and R 1  and eliminates the need for a capacitor. Q 6  and Q 7  are PNP transistors, each having an emitter coupled to V CC  through resistor R 4 . The base of Q 6  is coupled to VTOPN and the base of Q 7  is coupled to VTOPP. The collector of Q 6  is coupled to the input of driver  40   a  (node VREFP) and the collector of Q 7  is coupled to the input of driver  40   b  (node VREFN). The collector of NPN transistor Q 4  is coupled to the input of driver  40   a  and the collector of NPN transistor Q 5  is coupled to the input of driver  40   b . The base of Q 4  is coupled to VBOTN and the base of Q 5  is coupled to VBOTP. The emitters of Q 4  and Q 5  are coupled to V ee  through R 2 . R 6  is coupled between the input of driver  40   a  and ground and R 7  is coupled between the input of driver  40   b  and ground. The output of driver  40  is coupled to R 0  and the output of driver  40   b  is coupled to R 1 . The opposite side of R 0  and R 1  are the OUTP and OUTN signals, respectively. 
   The low output impedance drivers  40   a  and  40   b  can be realized in a number of ways, one example being a class AB driver. A preferred embodiment of a class AB driver is shown in  FIGS. 6 and 7 . The currents through Q 4 , Q 5 , Q 6  and Q 7  automatically track the output currents through Q 2 , Q 3 , Q 0  and Q 1 , respectively, by virtue of the connections shown. Specifically, looking at one pair of these transistors, since the bases of Q 0  and Q 6  are driven by the same voltage (VTOPN) and since both have emitter degeneration to V CC , their currents will track and follow each other in whatever ratio is specified. Q 6  and Q 4  drive reference resistor R 6 , generating reference voltage VREFP at the input of driver  40   a . Q 7  and Q 5  drive reference resistor R 7 , generating reference voltage VREFN at the input to driver  40   b . Reference resistors R 6  and R 7  are tied to ground, which sets the DC voltage of VREFP and VREFN around ground as well as the AC common-mode voltage of (VREFP+VREFN)/2. The reference voltages VREFP and VREFN are applied to the inputs of the low-impedance drivers, which drive R 0  and R 1 . This ultimately sets the DC voltage of OUTP and OUTN around ground as well as the AC common-mode voltage of (OUTP+OUTN)/2. 
   By driving the impedance match resistors R 0  and R 1  in this fashion, the drawbacks of prior art are overcome. Besides driving the impedance match resistors R 0  and R 1  at a low output impedance to keep match at all times, the purpose of the drivers  40   a  and  40   b  is to minimize the amount of current through the impedance match resistors R 0  and R 1 . This is achieved by having the output of each driver  40   a  or  40   b  track or follow its respective output node OUTP or OUTN. The low-impedance drivers are driven by the internal nodes VREFP and VREFN, which mimic the behavior of the output voltages OUTP and OUTN, respectively. With both ends of each impedance match resistor near the same voltage, the amount of current shunted away from the write head load through the impedance match resistors R 0  and R 1  during the overshoot phase is minimized. While generating the input voltages for the drivers dissipates power, as well as operating the drivers themselves, circuit methods are utilized to reduce the power spent in this area. For example, the currents from Q 4 –Q 7  are set smaller than the output currents from Q 0 –Q 3 , while the reference resistors R 6  and R 7  are sized larger than the impedance match resistors R 0  and R 1  for optimal transient performance. In addition, low-power techniques can be employed in the driver circuitry, as described in connection with  FIGS. 6 and 7 . Overall, the amount of power dissipated to impedance match the outputs of the write driver is substantially reduced from the prior art. Also, since there are no capacitors in the new art, the impedance matching is DC coupled and there is no RC pole and corresponding settling issue as in the prior art. Thus, the circuit of  FIG. 3  achieves better performance with less power. 
   A detailed analysis of the operation of the circuit of  FIG. 3  is provided in conjunction with the timing diagram in  FIG. 4 . The input write data voltages VTOPP, VTOPN, VBOTP, and VBOTN are conditioned to have 3 states: off, pulse (overshoot), and settled (DC write data). These input write data voltages are all synchronized to transition at the same point in time by circuitry not shown here. 
   At time=t0, VTOPN and VBOTP are in the settled DC write data state, while VBOTN and VTOPP are in the off state. Thus Q 6  is supplying current to R 6 , Q 5  is supplying current to R 7 , Q 0  is supplying current to OUTP, and Q 3  is supplying current to OUTN. Q 4 , Q 2 , Q 1 , and Q 7  are off. While these currents put a small DC component on VREFP, VREFN, OUTP, and OUTN, these voltages are still near ground. 
   At time=t1, all of the input write data voltages switch polarity. VTOPN and VBOTP switch to the off state (thus, Q 6 , Q 0 , Q 3 , Q 5  turn off). Both VBOTN and VTOPP enter the overshoot or pulsed phase. During this overshoot phase, Q 4 , Q 2 , Q 1 , and Q 7  each output a pulse of high current which drives VREFP and OUTP low and VREFN and OUTN high. It is during this transition that the output voltages OUTP and OUTN can swing near the rails. OUTP goes from around GND to near −5 v and OUTN goes from around GND to near +5 v. As described earlier, this is the large differential voltage that shunts a large amount of current away from the write head when placed across the differential impedance match resistance in the prior art. This drawback of prior art is overcome with the new art as VREFP tracks OUTP and VREFN tracks OUTN as indicated in  FIG. 4 . Thus, the differential voltage placed across each impedance match resistor R 0  and R 1  is minimized, as is the current R 0  and R 1  shunt away from the write head. Note that the AC overshoot pulse of OUTP and OUTN are equal and opposite, thus keeping the common-mode voltage of (OUTP+OUTN)/2 near ground. 
   At time=t2, the circuit enters a settled state. VTOPN and VBOTP are still in an off state, so Q 6 , Q 0 , Q 3 , and Q 5  remain off. VBOTN and VTOPP enter their settled DC write data state. Q 4  is supplying current to R 6 , Q 7  is supplying current to R 7 , Q 2  is supplying current to OUTP, and Q 1  is supplying current to OUTN. While these currents put a small DC component on VREFP, VREFN, OUTP, and OUTN, these voltages are still near ground. 
   At time=t3, the input write data voltages switch polarity again. VBOTN and VTOPP switch to an off state (Q 4 , Q 2 , Q 1 , Q 7  turn off). VTOPN and VBOTP enter the overshoot or pulsed phase. During this overshoot phase, Q 6 , Q 0 , Q 3 , and Q 5  each output a pulse of high current which drives VREFP and OUTP high and VREFN and OUTN low. OUTP goes from around ground to near +5 v and OUTN goes from around ground to near −5 v. The same benefits and improvements over prior art described with regard to time=t1 apply to this state as well. 
   At time=t4, the circuit once again enters a settled state and is back to the original state described in time=t0. 
   The drivers  40   a–b  shown in  FIG. 3  can be implemented using an AB driver. However, AB drivers used in disk drive preamplifier write drivers require large currents to handle the near rail to rail voltage swings at current day data rates in excess of 2 Gb/s. Specifically, the input stage needs large bias currents to supply the large transient base currents that the output stage requires during fast slewing of the large output voltage swing. Traditional AB drivers supply this input stage bias current with large fixed DC currents. This generates high power dissipation, which is a critical parameter for preamplifier write drivers and must be minimized. 
     FIG. 5  shows a schematic representation of a prior art AB driver circuit  50 . The input stage comprises transistors Q 22  and Q 23 , and current sources I 20  and I 21 . The output stage comprises Q 20  and Q 21 . Q 23  and Q 22  have bases coupled to Vin. The collector of NPN transistor Q 23  is coupled to V CC . Current source I 21  is coupled between the emitter of Q 23  and V ee . The collector of PNP transistor Q 22  is coupled to V ee . Current source I 20  is coupled between V CC  and the emitter of transistor Q 22 . The base of NPN transistor Q 20  is coupled to the emitter of Q 22  and the base of PNP transistor Q 21  is coupled to the emitter of Q 23 . The emitters of Q 20  and Q 21  are coupled together at the output node, Vout. The collector of Q 20  is coupled to V CC  and the collector of Q 21  is coupled to V ee . 
   The input stage sets up the bias for the output stage and drives the output stage. In the application of preamplifier write drivers disclosed herein, the output (Vout) of the AB driver  50  is used to drive a resistor (R 0  or R 1 ) that impedance matches the transmission line to the inductive write head  32 . The fixed DC bias current sources mentioned above are I 20  and I 21 . If these currents are too small and do not provide sufficient drive to handle the base currents of the output devices Q 20  and Q 21 , then the output devices Q 20  and Q 21  will turn off. This in turn causes loss of impedance match, which will degrade performance of the write driver. To prevent the output devices Q 20  and Q 21  from turning off, the DC currents for I 20  and I 21  must be sized large to ensure proper operation during the worst case scenario (i.e., where Vout—either OUTN or OUTP—is pulsed), which generates high power dissipation and is the drawback of the prior art. 
     FIG. 6  illustrates a schematic representation of an improved AB driver  60 , as used in the write driver of  FIG. 3  (for purposes of illustration, only the left side of the write driver of  FIG. 3  is shown). The output node of the write driver is labeled OUT and swings near rail to rail voltage (+5 v, −5 v). This node is driven by the output devices Q 2  and Q 0 , along with the impedance match resistor R 0 . The purpose of the AB driver  60  is to drive the impedance match resistor R 0  and keep match at all times while minimizing the amount of current through R 0 . As described in connection with  FIG. 3 , this is achieved by having the output of the AB driver track or follow the output node. The AB driver  60  adds Q 28 , R 26 , Q 29 , and R 22  to the prior art AB driver  50 . R 26  is coupled between V CC  and the emitter of PNP transistor Q 28 . The collector of Q 28  is coupled to the emitter of Q 22 . The base of Q 28  is driven by VTOP (VTOPN for driver  40   a  and VTOPP for driver  40   b ). R 22  is coupled between V ee  and the emitter of NPN transistor Q 29 . The collector of Q 29  is coupled to the emitter of Q 23 . The base of Q 29  is driven by VBOT (VBOTN for driver  40   a  and VBOTP for driver  40   b ). 
   Q 28  and Q 29  inject transient or pulsed currents into the input stage (at the emitters of Q 22  and Q 23 , respectively) to supply the additional base current to the output devices Q 20  and Q 21  as needed when VTOP or VBOT are pulsed (resulting in OUT being pulsed). This enables the fixed DC currents I 20  and I 21  to be reduced significantly (to a level needed to supply base current to keep the output devices turned on when VTOP of VBOT, and hence OUT, is settled) and lowers the overall RMS or average power dissipation without sacrificing any performance. It should be noted that for some applications, the bias current I 20  and I 21  could be removed altogether depending upon the DC current level of Q 28  and Q 29 . 
   For this application, there is a time period when there is no current out of Q 28  and Q 29  and thus I 20  and I 21  are still utilized, albeit at a much lower DC current which enables the power savings at issue. One important point to make is that the transient or pulsed currents from Q 28  and Q 29  are synchronized in time with the input voltage Vin so that the pulse currents occur exactly when needed without any delay, which is necessary for operation at 2 Gb/s+(see timing diagram in  FIG. 7 ). This is achieved by having these pulsed current sources derived from the same source that drives the input of the AB driver. In other words, this is achieved by having both Q 4  and Q 29  (or Q 6  and Q 28 ) driven by the same signal VBOT (or VTOP). Attempting to use feedback from the output devices Q 20  and Q 21  to supply the base current would be too slow to function well at 2 Gb/s+ due to the inherent delay of the feedback circuitry. This entire circuitry is driven by the write data voltage signals VTOP and VBOT, the timing of which is shown in  FIG. 7 . 
   A detailed analysis of operation of the circuit of  FIG. 6  is given in conjunction with the timing diagram of  FIG. 7 . As in the case of  FIG. 4 , the input write data voltages are conditioned to have 3 states: off, pulse (overshoot), and settled (DC write data). 
   At time=t0, VTOP is at settled DC write data and VBOT is off. Thus Q 6  is supplying current to R 4 , Q 28  is supplying a low DC current to AB driver input device Q 22 , and Q 0  is supplying current to the output node (OUT). Q 4 , Q 29 , and Q 2  are off. The AB driver  60  is in a settled state and the input stage does not require a high bias current to handle the output stage base current. 
   At time=t1, the input write data voltages VTOP and VBOT switch polarity. VTOP turns off (Q 6 , Q 28  and Q 0  turn off) and VBOT enters the overshoot or pulsed phase. It is during this transition that the output voltage OUT swings from around ground to near −5 v (see Vin in  FIG. 7 ). If operating at continuous data transitions (i.e., no settling allowed to occur), this voltage swing could be from near rail to rail (+5 v to −5 v) and the output of the AB driver  60  must keep up to minimize power dissipation in R 0 . Swinging this much voltage with a fast risetime requires high current through Q 21 , which in turn requires a high Q 21  base current. Because Q 29  is driven by VBOT, the bias current from Q 29  is pulsed at exactly the same time that Q 21  requires the additional base current (as well as current to charge the capacitance at that node). The amount of current supplied by Q 29  at the peak of its pulse is about the value the prior art AB driver  50  needs to set for its fixed DC current sources (I 20  and I 21 ). However, the large pulsed current provided by Q 29  only remains there for a short time, then drops to a much lower settled level, as VBOT transitions from overshoot to settled. Because it is synchronized with the AB driver input voltage Vin, Q 29  provides high current only during the time it is needed and then reduces to a lower current when high current is not needed (see IC 29  in  FIG. 7 ). This reduces the overall average bias current for the input stage and enables power savings without sacrificing performance. 
   At time=t2, the circuit enters a settled state. VTOP is still off and VBOT is now in its settled DC write data state. Q 4  is supplying current to R 4 , Q 29  is supplying a low DC current to AB driver input device Q 23 , and Q 2  is supplying current to the output node. Q 6 , Q 28 , and Q 0  are still off. Since the AB driver  60  is in a settled state, the input stage does not need a high bias current to handle the output stage base current. 
   At time=t3, the input write data voltages VTOP and VBOT switch polarity again. VBOT turns off and VTOP enters the overshoot or pulsed phase. The output voltage swings from around ground to +5 v (or at continuous data transitions from −5 v to +5 v) and the output of the AB driver  60  follows. This requires a high current through Q 20 , which in turn requires a high Q 20  base current. This is provided by pulsed current source Q 28  in the exact same manner as described for Q 29  in the time=t1 paragraph above (see IC 28  in  FIG. 7 ), yielding the same benefits and improvements over prior art. 
   At time=t4, the circuit once again enters a settled state and is back to the original state described in time=t0. 
   Accordingly, transistors Q 28  and Q 29  act as switched current sources to provide current to the bases of AB drive output transistors Q 20  and Q 21 , respectively, at the exact times that the additional current is needed at one of the output transistors and switch to either an off or a settled state when the high currents are no longer needed to drive the output transistors. Hence, the high current needed for data transitions on an as needed basis, greatly saving power. 
   Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.

Technology Classification (CPC): 6