Patent Abstract:
A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Full Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to switching mode power supplies and in particular to pulse width modulation regulation devices (PWM) used in these power supplies. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  schematically shows a conventional switching mode power supply. The regulated voltage Vout is taken from the terminals of a filtering capacitor Cf. This capacitor is connected in series with an inductor L between a reference potential, the ground Vground, and the output of a push-pull stage  10  formed by a pair of complementary MOS transistors, powered between the ground and a positive voltage Vbattery, for example a battery voltage. 
         [0005]    A differential amplifier  12  supplies an error voltage Verror proportional to the difference between a reference voltage Vreference and the output voltage Vout. A comparator  14  receives the voltage Verror and a periodic sawtooth signal Vper produced by a ramp generator  16 . The comparator  14  thus supplies a pulse width modulated signal whose duty factor is proportional to the error voltage Verror. This pulse width modulated signal is shaped by a circuit DRV driving the complementary pair  10 . 
         [0006]      FIG. 2  is a chronogram showing the generation of the pulse width modulated signal from the error signal Verror and the sawtooth signal Vper. The signal comprises Vper a periodic succession of rising ramps of same slope, starting from 0 and whose magnitude is constant and lower than Vbattery. 
         [0007]    In  FIG. 2 , the voltage Verror is halfway up the ramps and defines a pulse width modulation signal having a duty factor of 0.5—the pulse width modulated signal is at 1 for the part of the ramps below Verror, and at 0 for the part of the ramps above Verror. 
         [0008]    Details about making and operating systems of this type are described in [&lt;&lt;Fundamentals of Power Electronics&gt;&gt;, Robert W. Erikson, Dragan Maksimovic; Kluwer Academic Publishers; 3rd Revised edition (January 2001)]. 
         [0009]    In  FIG. 2 , when the error voltage Verror tends toward 0, i.e., when the output current of the switching mode power supply is low, the duty factor of the pulse width modulated signal also tends toward 0. Given the reaction time of the circuits, it is not possible to generate pulses having a quasi-zero width, hence it results that the duty factor becomes inaccurate. This inaccuracy is increased by the fact that the signal Verror, tending toward 0, disappears in the noise and its fluctuations become indistinguishable by the comparator  14 . The result is fluctuations of the regulated voltage Vout when it tends toward its setpoint value, which may be unacceptable in some applications. 
         [0010]    To avoid this drawback, it has been suggested to connect the low power supply terminal of the comparator to a negative power supply source with respect to the Vground, so that the comparator may take a low noise measurement of the voltage Verror when it tends toward 0. It therefore uses an additional power supply source. 
         [0011]    It has also been suggested to set a reduced value of the duty factor, so that the pulse width always remains in a range where it may be determined with enough accuracy. It renders the system more complex due to the fact that this offset must be compensated when the output voltage is near the setpoint voltage. In addition, because the system is then always in a switching mode, especially when idle, the current consumption is increased. 
       BRIEF SUMMARY 
       [0012]    There is therefore a need for a pulse width modulation device offering sufficient accuracy when the error voltage is near 0, while having a simple structure consuming little energy. 
         [0013]    This need is tended to by providing a ramp signal defining the on and off phases of a switching transistor to perform a pulse width modulation, having at periodic intervals: an initial value at an on/off threshold voltage of the switching transistor; a step exceeding the initial value by an error voltage corresponding to a duty factor setpoint of the pulse width modulation; and a ramp, having a same slope for all the intervals, joining the step to the initial value, whereby the duration of the on phase of the switching transistor is proportional to the error voltage, with the same proportionality coefficient for all the intervals. 
         [0014]    There is also provided a pulse width modulation device comprising a switching transistor having a gate, a source, and a drain for defining the modulation phases; a capacitor; switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor; and a constant current source connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold. 
         [0015]    According to an embodiment, the device comprises the switching transistor having its gate connected to a first terminal of the capacitor and its source connected to a reference potential line; a diode connected, in the first phase, between the first terminal of the capacitor and the reference potential line; and a transistor forming the constant current source, connecting the first terminal of the capacitor to the reference potential line. 
         [0016]    According to an embodiment, the diode is formed by a transistor having the same characteristics as the switching transistor, the diode and the switching transistor being connected to have respective bias currents of same value. 
         [0017]    According to an embodiment, the device comprises a circuit arranged to interrupt the current of the current source while the switching transistor is off. 
         [0018]    According to an embodiment, the diode is part of a Wilson current mirror. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0019]    Non-limiting and non-exhaustive embodiments are described with reference to the following drawings, wherein like labels refer to like parts throughout the various views unless otherwise specified. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn are not intended to convey any information regarding the actual shape of the particular elements and have been selected for ease of recognition in the drawings. Embodiments discussed herein will be described in the following description, in relation with, but not limited to the appended figures wherein: 
           [0020]      FIG. 1 , previously described, schematically shows a conventional switching mode power supply; 
           [0021]      FIG. 2 , previously described, is a chronogram showing the generation of a pulse width modulation signal in the power supply of  FIG. 1 ; 
           [0022]      FIG. 3  is a chronogram showing the operating principle of a pulse width modulation device without comparator; 
           [0023]      FIG. 4  schematically shows a first embodiment of a modulator operating according to the principle of  FIG. 3 ; 
           [0024]      FIG. 5  is a more detailed chronogram showing the operation of the modulator of  FIG. 4 ; and 
           [0025]      FIG. 6  schematically shows a second embodiment of a modulator without comparator. 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    To avoid the drawbacks linked to the comparator in a pulse width modulator, a modulator without comparator is provided hereinafter. 
         [0027]      FIG. 3  is a chronogram showing the basic operation of such a modulator. A sawtooth voltage signal Vr is also used here, comprising ramps following one another at periodic intervals. They all have the same, decreasing slope. However, they have a variable magnitude, proportional to the instantaneous error voltage Verr, and they start from a quiescent value Vt different from zero. The value Vt corresponds to the on/off threshold of a switching transistor controlled by the signal Vr. 
         [0028]    Each ramp starts, at a time determined by a periodic clock, by a step corresponding to the error voltage Verr, above the voltage Vt, and then decreases with a constant slope, the same for each successive ramp, until reaching again the quiescent value Vt. Thus, the duration of each ramp is proportional to the value of the initial step, equal to the error voltage Verr. 
         [0029]    The quiescent value Vt corresponding to the turn-off limit of the switching transistor, this transistor is conductive only during the ramps, as shown by the evolution of the signal PWM. 
         [0030]      FIG. 4  shows an embodiment of a modulator operating according to the principle of  FIG. 3 . It comprises a capacitor C associated to three switches S 1 , S 2  and S 3 . A first terminal of the capacitor C, on which the sawtooth voltage Vr is produced, is connected to the gate of the above-mentioned switching transistor, an N-channel MOS transistor MN 1  whose source is connected to the ground node GND. The transistor MN 1  is biased from the positive power supply line Vbat by a current source MI 2 . The gate of the transistor MN 1  is also connected to the ground GND node by a constant current source MI 3 . A switch S 4  is arranged to interrupt the current of the source MI 3 . 
         [0031]    The switch S 1  connects the first terminal of the capacitor C to the ground GND node through a diode MD 4 . The second terminal of the capacitor C is connected to the ground by the switch S 2  and connected by the switch S 3  to a terminal receiving the error voltage Verr, supplied at low impedance by an amplifier, like in  FIG. 1 . The switches S 1  and S 2  are controlled in phase by a reset signal RST. The switches S 3  and S 4  are controlled by a signal NRST in phase opposition with the signal RST. 
         [0032]    The current source MI 3  is actually an N-channel MOS transistor connected as a current mirror to copy the current flowing through a diode MD 5 . The diode MD 5  is connected to the ground and is biased from the line Vbat by a current source MI 6 . The diode MD 4  is biased from the line Vbat by a current source MI 7 . 
         [0033]    The current sources MI 2 , MI 6  and MI 7  are actually P-channel MOS transistors connected as current mirrors to copy the current flowing through a diode MD 8 , also connected to the line Vbat. The diode MD 8  is biased from the ground by a reference current source Iref. This current source Iref thus sets, proportionally to the size ratios of the transistors involved, the values of all the other current sources. 
         [0034]    The modulation control signal PWM is supplied by an inverter  40  whose input is connected to the drain of the switching transistor MN 1 . 
         [0035]      FIG. 5  is a chronogram showing the operation of the modulator of  FIG. 4 . It shows an example of evolution of the reset signal RST and of various resulting signals, in particular the voltage on a node n 1  corresponding to the terminal of the capacitor connected to the switch S 3 , the voltage on a node n 2  between the diode MD 4  and the switch S 1 , the sawtooth voltage Vr, and the modulated signal PWM. 
         [0036]    The signal RST determines by successive pulses the pulse width modulation intervals. It is generally periodic. 
         [0037]    The signals shown in dotted lines correspond to an embodiment described below. Now, only the signals in solid lines are considered. 
         [0038]    The signal RST is at zero when idle. The switches S 1  and S 2  are opened, whereas the switches S 3  and S 4  are closed. The node n 1  is at the voltage Verr. The node n 2  is at the threshold voltage Vt imposed by the diode MD 4 . The capacitor C is connected in series between the terminal receiving the voltage Verr and the current source MI 3 . At the end of a modulation interval, i.e., near the start of a new pulse RST, the current source MI 3  ends up pulling the potential Vr on the capacitor toward a voltage near zero: the capacitor C is charged at the voltage Verr. 
         [0039]    At a time t 0 , a pulse of the signal RST starts. The switches S 1  and S 2  are closed, connecting the capacitor C across diode MD 4 , whereas the switches S 3  and S 4  are open. The node n 1  is pulled to the ground. Due to the charge in the capacitor, the diode MD 4  is momentarily unbiased and the voltage on the node n 2  drops by the voltage Verr across the capacitor. The voltage of the node n 2  increases progressively, pulled by the current source MI 7 , until it reaches the value Vt imposed by the diode MD 4 . The voltage across the capacitor is then worth Vt. The duration of the pulse RST is preferably sufficient for this value Vt to be reached on the node n 2  before the end of the pulse. 
         [0040]    During this reset phase, the voltage Vr follows the voltage of the node n 2 . The voltage Vt preferably corresponds to the on/off threshold of the switching transistor MN 1 . Thus this value, reached by the signal Vr at the end of the reset phase, is still insufficient to turn on the transistor MN 1 , at least sufficiently to pull the input of the inverter  40  to the ground against the current source MI 2 . 
         [0041]    Preferably, to guarantee that the voltage Vt imposed by the diode MD 4  corresponds to the on/off threshold of the transistor MN 1 , the diode MD 4  is formed by a transistor matched with the transistor MN 1 , and these transistors are both biased by a current of same value. To obtain currents of same value, the transistors forming the current sources MI 2  and MI 7  are also matched. 
         [0042]    When the signal RST returns to its idle value, the switches S 1  and S 2  are opened, whereas the switch S 3  is closed. The voltage Vr is subjected to a rising step of the value Verr; the voltage Verr carried by the switch S 3  is superimposed to the charge voltage Vt of the capacitor to form the signal Vr. 
         [0043]    The current source MI 3  discharges the capacitor with a constant slope. The voltage Vr decreases linearly until reaching nearly zero. 
         [0044]    During the phase where the signal Vr is above the value Vt, the transistor MN 1  is on and pulls the input of the inverter  40  to zero. The result is a state at 1 of the signal PWM during this phase. As shown in  FIG. 5  for successive modulation intervals, the duration at 1 of the signal PWM is proportional to the step of the signal Vr above Vt, i.e., the error voltage Verr. 
         [0045]      FIG. 6  shows an embodiment of a modulator of the type of  FIG. 4 , comprising some enhancements. 
         [0046]    The diode MD 4  is integrated into a Wilson current mirror, which produces a node n 2  having a low impedance. The Wilson mirror includes the diode MD 4  and two N-channel MOS transistors MN 9  and MN 10 . The transistor MN 9  has its source connected to the diode MD 4  (node n 2 ) and its drain connected to the line Vbat. The gate of the transistor MN 9  is connected to the drain of the transistor MN 10 . The gate of the transistor MN 10  is connected to the node n 2  and its source is connected to the ground. The input current of the Wilson mirror is supplied to the drain of the transistor MN 10  by a current source MI 11 , a P-channel MOS transistor forming a mirror with the diode MD 8 . 
         [0047]    The Wilson mirror operates so that the source voltage of the transistor MN 9  establishes at a value such that the resulting current in the diode MD 4  is equal to the current injected by the current source MI 11 . 
         [0048]    Using this Wilson mirror, the transistor MN 9  maintains the voltage of the node n 2  at Vt, in particular during the reset phase, as shown in dotted lines in  FIG. 5 . It allows the duration of the pulses RST to be reduced, since the capacitor C is charged at low impedance by the transistor MN 9 . A risk of damaging the transistors connected to the node n 2  by voltage levels which may exceed nominal values is also avoided. The voltage Vr corresponds to the voltage of the node n 2  during the reset phases. 
         [0049]    In addition, an N-channel MOS switching transistor MN 12  replaces the switch S 4  of  FIG. 4  between the current source MI 3  and the ground. The gate of this transistor is controlled by an AND gate  60  receiving on one input the inverse reset signal NRST. Another input of the gate  60  receives the signal PWM supplied by the inverter  40 . To compensate for the influence of the transistor MN 12  on the current mirror MD 5 /MI 3 , a transistor MN 13  having the same characteristics as the transistor MN 12  is arranged between the diode MD 5  and the ground. The gate of the transistor MN 13  receives the voltage Vbat, so that the transistor MN 13  is always conductive. 
         [0050]    With this configuration, the current source MI 3  only produces current when useful, i.e., during the active phases of the signal PWM, where it is used to discharge the capacitor C. The current of the source MI 3  is interrupted outside these phases, which allows the current consumption of the circuit to be reduced. As shown in dotted lines in  FIG. 5 , the result is that the signal Vr stabilizes at the value Vt at the end of each active phase. 
         [0051]    In the  FIG. 5  chronogram, it appears not to be useful to combine the signals NRST and PWM with an AND gate—the signal PWM alone may be enough to control the transistor MN 12 . However, when the duty factor of the signal PWM tends toward 1, it is the signal NRST that causes the transistor MN 12  to turn off before the signal PWM, thus avoiding a current consumption during the reset phase. 
         [0052]    The various embodiments described above can be combined to provide further embodiments. The embodiments may include structures that are directly coupled and structures that are indirectly coupled via electrical connections through other intervening structures not shown in the figures and not described for simplicity. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Technology Classification (CPC): 7