Patent Abstract:
Aspects of the disclosure provide method and apparatus for detecting attributes of an input power supply. The method includes receiving a first signal generated based on a second signal that is predictive. The first signal includes a portion that substantially corresponds to the second signal. Further, the method includes detecting attributes of the portion of the first signal that substantially corresponds to the second signal, and determining attributes of the second signal based on the attributes of the portion of the first signal that substantially corresponds to the second signal.

Full Description:
INCORPORATION BY REFERENCE 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/368,483, “Voltage Level and Frequency Detection for Rectified Sine Wave with Distorted Trailing Edge” filed on Jul. 28, 2010, which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
         [0003]    Power circuits are used to regulate an input power supply to an appropriate form for driving a load. In an example, a power circuit includes a power factor correction (PFC) circuit to align phases of a driving current with a driving voltage in order to improve driving efficiency. 
       SUMMARY 
       [0004]    Aspects of the disclosure provide method and apparatus for detecting attributes of an input power supply. The method includes receiving a first signal generated based on a second signal that is predictive. The first signal includes a portion that substantially corresponds to the second signal. Further, the method includes detecting attributes of the portion of the first signal that substantially corresponds to the second signal, and determining attributes of the second signal based on the attributes of the portion of the first signal that substantially corresponds to the second signal. 
         [0005]    In an embodiment, the second signal includes a leading portion and a trailing portion that is symmetrical to the leading portion. In an example, the second signal has a sinusoidal waveform, and the first signal includes a leading portion that substantially corresponds to the second signal. The method includes detecting a fixed level on the leading portion of the first signal, and predicting a time when a trailing portion of the second signal is at the fixed level. Specifically, the method includes detecting a second level that is larger than the fixed level on the leading portion of the first signal, measuring a time duration between the detection of the fixed level and the second level, detecting the second level on the trailing portion of the first signal, and predicting the time when the trailing portion of the second signal is at the fixed level based on the detection of the second level on the trailing portion of the first signal and the measured time duration. 
         [0006]    In another example, the method includes detecting a first proportional-to-peak level on the leading portion of the first signal, detecting a second proportional-to-peak level on the leading portion of the first signal, and measuring a time duration between the detections. Further, the method includes determining at least one of a frequency and a period of the second signal based on the first proportional-to-peak level, the second proportional-to-peak level and the time duration. In addition, the method includes determining a zero-crossing time of the second signal based on the first proportional-to-peak level, the second proportional-to-peak level and a time duration between the detections. 
         [0007]    Aspects of the disclosure provide a circuit for detecting attributes of an input power supply, and generating control signals for regulating the input power supply based on the detected attributes. The circuit includes a detection circuit, and a control circuit. The detection circuit is configured to receive a first signal generated based on a second signal that is predictive. The first signal includes a portion that substantially corresponds to the second signal. The detection circuit is configured to detect attributes of the portion of the first signal that substantially corresponds to the second signal, and determine attributes of the second signal based on the attributes of the portion of the first signal that substantially corresponds to the second signal. The control circuit is configured to generate control signals to regulate the second signal based on the determined attributes of the second signal. 
         [0008]    Aspects of the disclosure also provide a power circuit for providing power to a load. The power circuit includes a regulation circuit, and a detect-and-control circuit. The regulation circuit is configured to receive an alternating current (AC) power supply having a sinusoidal waveform, regulate the AC power supply to generate an output power supply, and provide the output power supply to the load. The detect-and-control circuit includes a detection circuit and a control circuit. The detection circuit is configured to receive a signal generated based on the AC power supply. The signal includes a portion that substantially corresponds to the AC power supply. The detection circuit is configured to detect attributes of the portion of the signal that substantially corresponds to the AC power supply, and determine attributes of the AC power supply based on the attributes of the portion of the signal that substantially corresponds to the AC power supply. The control circuit is configured to generate control signals based on the determined attributes of the AC power supply, and provide the control signals to the regulation circuit to regulate the AC power supply. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein: 
           [0010]      FIG. 1  shows a block diagram of an electronic system example  100  according to an embodiment of the disclosure; 
           [0011]      FIG. 2  shows a plot  260  of waveforms according to an embodiment of the disclosure; 
           [0012]      FIG. 3A  shows a flowchart outlining a process example  300  according to an embodiment of the disclosure; 
           [0013]      FIG. 3B  shows a plot  360  of waveforms according to an embodiment of the disclosure; 
           [0014]      FIG. 4A  shows a block diagram of a detection circuit  440  according to an embodiment of the disclosure; 
           [0015]      FIG. 4B  shows a plot  460  of waveforms according to an embodiment of the disclosure; 
           [0016]      FIG. 5A  shows a flowchart outlining a process example  500  according to an embodiment of the disclosure; and 
           [0017]      FIG. 5B  shows a plot  560  of waveforms according to an embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0018]      FIG. 1  shows a block diagram of an electronic system example  100  according to an embodiment of the disclosure. The electronic system  100  includes a power circuit  110  that provides power to drive a load  104 . The power circuit  110  receives an input power supply, such as an alternating current (AC) power supply having a fire line of a line voltage V LINE  and a neutral line of a neutral voltage V NEUTRAL  as shown in  FIG. 1 . The power circuit  110  regulates the input power supply to generate an output power supply having appropriate attributes, and the output power supply drives the load  104 . 
         [0019]    In the  FIG. 1  example, the power circuit  110  includes a detect-and-control circuit  120  and a regulation circuit  115 . The detect-and-control circuit  120  is configured to detect attributes of the input power supply, generate control signals based on the detected attributes, and provide the generated control signals to the regulation circuit  115 . 
         [0020]    The regulation circuit  115  is configured to regulate the input power supply according to the control signals provided by the detect-and-control circuit  120 , and provide regulated power supply to the load  104 . These elements are coupled together as shown in  FIG. 1 . 
         [0021]    In an example, the detect-and-control circuit  120  is implemented as integrated circuit (IC) on an IC chip. Further, in the example, the ground connection of the IC chip is electrically coupled to a ground connection VSS. It is noted that the load  104  is grounded to VSS′. The ground VSS′ can be the same ground as the ground VSS, or can be different from the ground VSS depending on the configuration of the regulation circuit  115 . In an embodiment, the electronic system  100  includes a scaling circuit  105  to scale the line voltage V LINE  or neutral voltage V NEUTRAL  and generates an input voltage V IN  within an appropriate range. The input voltage V IN  is provided to the IC chip to detect the attributes of the input power supply. In another embodiment, the scaling circuit  105  is not needed, or the scaling circuit  105  is also integrated into the IC chip. 
         [0022]    According to an aspect of the disclosure, generally, the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has a sinusoidal waveform, and the input voltage V IN  with regard to VSS has a half sinusoidal waveform. However, the input voltage V IN  with regard to VSS can be distorted due to the load  104 . 
         [0023]    For example, when the load  104  is relatively heavy (e.g., requires relatively large current), the input voltage V IN  with regard to VSS has the half sinusoidal waveform. However, when the load  104  is relatively light (e.g., requires relatively small current), the waveform of the input voltage V IN  with regard to VSS is distorted due to insufficient discharging of the capacitor  103 . According to an embodiment of the disclosure, the detect-and-control circuit  120  is configured to use the input voltage V IN  to detect the attributes of the input power supply, and the detection is independent of load status of the load  104 . Thus, the detect-and-control circuit  120  can generate accurate control signals to control the regulation circuit  115 . 
         [0024]    In an example, the regulation circuit  115  includes a bridge rectifier  101  that rectifies the input from the AC power supply. Further, the regulation circuit  115  includes a power factor correction (PFC) circuit  102  that is configured to align phases of a driving current with a driving voltage to the load  104  to improve driving efficiency. In an example, the line voltage W LINE  has a frequency of 50 Hz. The PFC circuit  102  includes a switch (not shown) that is controlled to switch on and off at a much higher frequency than 50 Hz, for example, in the order of KHz. In each switch cycle that the switch is switched on and off, an average driving current is a function of the line voltage V LINE  during the switch-on time. Thus, the average driving current has substantially the same phase as the line voltage V LINE . 
         [0025]    To suitably control the PFC circuit  102 , in an example, the detection-and-control circuit  120  is configured to detect various attributes of the line voltage V LINE , such as line frequency of the AC power supply, zero-crossing of the line voltage V LINE , time when the line voltage V LINE  is at a fixed voltage level, and the like, and to generate control signals based on the detected attributes. 
         [0026]    According to an embodiment of the disclosure, when the load  104  is relatively heavy, the input voltage V IN  with regard to VSS has a half sinusoidal waveform compared to the sinusoidal waveform of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL . Specifically, when the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  is larger than or equal to zero, the waveform of the input voltage V IN  with regard to VSS follows the waveform of the line voltage V LINE  with regard to the neutral voltage Y NEUTRAL . When the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  is smaller than zero, the input voltage V IN  with regard to VSS keeps at zero. 
         [0027]    Further, the waveform of the input voltage V IN  with regard to VSS includes leading portions and trailing portions. In an example, the leading portions are portions that rise from zero to peak value of the half sinusoidal waveform, and the trailing portions are portions that drop from the peak value to zero. 
         [0028]    According to the embodiment, when the load  104  is relatively light, the leading portions still follow the sinusoidal waveform, but the trailing portions are distorted from the sinusoidal waveform due to insufficient capacitor discharging, for example. In an example, the distortions are relatively small near peaks of the sinusoidal waveform, and are relatively large near zero-crossings on the trailing portions. Thus, attribute detections that rely on the trailing portions, such as fixed voltage detection, zero-crossing detection, line frequency detection, and the like, may be inaccurate. 
         [0029]    According to an aspect of the disclosure, the detect-and-control circuit  120  is configured to detect attributes of the input power supply substantially independent of the load  104 . In an embodiment, the detect-and-control circuit  120  detects attributes of the input power supply based on non-distorted portions or less distorted portions, such as the leading portions, of the input voltage V IN  with regard to VSS. Further, because the sinusoidal waveform of the input power supply is a predictive waveform, the detection-and-control circuit  120  predicts certain attributes of the input power supply, based on the attribute detections on the leading portions of the input voltage V IN  with regard to VSS. Thus, the attribute detection for the input power supply does not rely on attribute detection on the trailing portions of the input voltage V IN  with regard to VSS. 
         [0030]    In an embodiment, the detect-and-control circuit  120  includes a detection circuit  140  and a control circuit  130 . The detection circuit  140  includes any suitable circuit to detect attributes, such as time of a fixed voltage value, zero-crossings, line frequency, and the like, of the AC power supply (the line voltage V LINE  with regard to the neutral voltage V NEUTRAL ) according to the non-distorted portions and/or less distorted portions of the input voltage V IN  with regard to VSS. The control circuit  130  generates suitable control signals based on the detected attributes, and provides the control signals to the regulation circuit  115 . 
         [0031]    In an embodiment, the detection circuit  140  includes comparators (not shown) configured to output signals that indicate when the input voltage V IN  with regard to VSS are at certain voltage levels, such as fixed voltage level, proportional-to-peak values, and the like. 
         [0032]    In another embodiment, the detection circuit  140  includes counters (not shown) to measure time durations between events, and to predict time for events. In an example, a counter is configured to include a count-up control, a count-down control, and a stop control. The count-up control is configured to activate the counter to count up from zero, for example. The stop control is configured to stop the counter from counting, and store the counted value. The count-down control is configured to activate the counter to count down from a previously stored value. The detection circuit  140  includes suitable control logic, such as in state machine form, and the like, to control the operations of the counter, for example, based on outputs from the comparators. In an example, the counter is configured to generate an output signal, such as a relatively high voltage level, when the counted value is equal to a specific value, such as zero. 
         [0033]    In another embodiment, the detection circuit  140  includes integrators (not shown) to measure time durations between events, and to predict time for events. In an example, an integrator is configured to integrate during the count-up and discharge during the count-down. The integrator is configured to stop when its output reaches zero. The time constant of the integrator can also be configured such that the up and down integration rate are set differently. 
         [0034]    It is noted that the detect-and-control circuit  120  can include any circuit components, such as logic circuit, state machine, processor, memory, digital circuit, analog circuit, and the like. 
         [0035]      FIG. 2  shows a plot  260  of waveform examples according to an embodiment of the disclosure. The plot  260  includes a first curve  270  and a second curve  280 . The first curve  270  corresponds to the waveform of the normalized line voltage V LINE  with regard to the neutral voltage V NEUTRAL  in the  FIG. 1  example, and the second curve  280  corresponds to the waveform of the normalized input voltage V IN  with regard to VSS in the  FIG. 1  example. The first curve  270  has a sinusoidal waveform. The second curve  280  is load dependent. For example, when the load  104  is relatively heavy, the second curve  280  has a half sinusoidal waveform. When the load  104  is relatively light, the trailing portions of the half sinusoidal waveform are distorted, such as the distorted trailing portions  281  and  282  shown in  FIG. 2 . 
         [0036]    According to an aspect of the disclosure, the detect-and-control circuit  120  detects attributes of the line voltage V LINE  with regard to the neutral Voltage V NEUTRAL  based on non-distorted portions, such as the leading portions, of the input voltage V IN  with regard to VSS. Further, because the sinusoidal waveform of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  is a predictive waveform, the detection-and-control circuit  120  predicts certain attributes of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL , based on the attributes detections on the leading portions of the input voltage V IN  with regard to VSS. Thus, the attribute detection for the input power supply does not rely on attribute detection on the trailing portions of the input voltage V IN  with regard to VSS. 
         [0037]    For example, a fixed voltage value (e.g., a fixed normalized voltage value) on the leading portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  can be detected based on a detection of a corresponding fixed voltage value on the leading portion of the input voltage V IN  with regard to VSS, as shown by A; and a fixed voltage value on the trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  is predicted based on attribute detections at the non-distorted, or less distorted portions of the input voltage V IN  with regard to VSS, as shown by B. It is noted that the prediction can be based on one or more detections at the non-distorted portions or less-distorted portions. 
         [0038]      FIG. 3A  shows a flowchart outlining a process example  300  for the detect-and-control circuit  120  to use a counter to predict a time when a trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has a fixed voltage value according to an embodiment of the disclosure. The process starts at S 301 , and proceeds to S 305 . 
         [0039]    At S 305 , the detect-and-control circuit  120  detects that the input voltage V IN  with regard to VSS is at a leading portion. In an example, the detect-and-control circuit  120  detects that the input voltage V IN  with regard to VSS is larger than zero and consistently increases, and the detect-and-control circuit  120  determines that the input voltage V IN  with regard to VSS is at a leading portion. 
         [0040]    At S 310 , the detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS to a first reference voltage V REF1 , and determines whether the input voltage Y IN  with regard to VSS is equal to or larger than the first reference voltage V REF1 . It is noted that the first reference voltage V REF1  can be determined based on the fixed voltage value. For example, when the scaling factor between the input voltage V IN  and the line voltage V LINE  is one, the first reference voltage V REF1  is equal to the fixed voltage value. When the input voltage V IN  with regard to VSS is equal to or larger than the first reference voltage V REF1 , the process proceeds to S 315 ; otherwise, the process returns to S 310 . 
         [0041]    At S 315 , the detect-and-control circuit  120  starts the counter to count up from zero. 
         [0042]    At S 320 , the detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS to a second reference voltage V REF2  that is larger than first reference voltage V REF1 , and determines whether the input voltage V IN  with regard to VSS is equal to or larger than the second reference voltage V REF2 . In an embodiment, the second reference voltage V REF2  is smaller than a peak value of the input voltage V IN  with regard to VSS by a relatively small value. When the input voltage V IN  with regard to VSS is equal to or larger than the second reference voltage V REF2 , the process proceeds to S 325 ; otherwise, the process returns to S 320 . 
         [0043]    At S 325 , the detect-and-control circuit  120  stops the counter, and stores the counted value. 
         [0044]    At S 330 , the detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS to the second reference voltage V REF2 , and determines whether the input voltage V IN  with regard to VSS is equal to or smaller than the second reference voltage V REF2 . When the input voltage V IN  with regard to VSS is equal to or smaller than the second reference voltage V REF2 , the process proceeds to S 335 ; otherwise, the process returns to S 330 . 
         [0045]    At S 335 , the detect-and-control circuit  120  starts the counter to count down from the stored value. 
         [0046]    At S 340 , the detect-and-control circuit  120  determines whether the counter counters to zero. In an embodiment, the counter outputs a relatively high voltage value when the counter counts to zero, and the detect-and-control circuit  120  is configured to wait for the counter to output the relatively high voltage value. When the counter outputs the relatively high voltage value, the process proceeds to S 345 ; otherwise, the process returns to S 340 . 
         [0047]    At S 345 , the detect-and-control circuit  120  generates an output signal indicating at that time the trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has the fixed voltage value. Then, the process proceeds to S 399  and terminates. 
         [0048]    It is noted that the process  300  can be suitably adjusted. In an example, the detect-and-control circuit  120  uses an integrator instead of the counter. 
         [0049]      FIG. 3B  shows a plot  360  of waveform examples according to the process  300 . The plot  360  includes a curve  380  of the input voltage V IN  with regard to VSS. The trailing portion of the input voltage V IN  with regard to VSS may be distorted, as shown by  381 , due to load. The detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS with the first reference voltage V REF1  and the second reference voltage V REF2 , and controls the operation of the counter/integrator based on the comparison. 
         [0050]    For example, the input voltage V IN  with regard to VSS starts to increase from time  0 . At time t 1 , a first event that the input voltage V IN  with regard to VSS is equal to the first reference voltage V REF1  happens, and then the detect-and-control circuit  120  starts the counter to count up. The input voltage V IN  with regard to VSS continues to increase. At time t 2 , a second event that the input voltage V IN  with regard to VSS is equal to the second reference voltage V REF2  happens, and then the detect-and-control circuit  120  stops the counter. It is noted that the counted number corresponds to a time duration between the first event and the second event. The input voltage V IN  with regard to VSS continues to increase to the peak value V PEAK  and starts to decrease. At time t 3 , a third event that the input voltage V IN  with regard to VSS is equal to the second reference voltage V REF2  happens, and then the detect-and-control circuit  120  starts the counter to count down. At time t 4 , the counter is zero, and the detect-and-control circuit  120  generates an output signal that indicates, at time t 4 , the trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has the fixed voltage value. 
         [0051]    In an embodiment, the first reference voltage V REF1  and the second reference voltage V REF2  are generated based on a band-gap voltage that is substantially constant. For example, the band-gap voltage is substantially independent of process variations and temperature variations. 
         [0052]    In another embodiment, the first reference voltage V REF1  is proportional to the peak value V PEAK  (V REF1 =K×V PEAK ) and a time duration T 1  between time t 1  to time t 4  is measured. Because arc sin 
         [0000]    
       
         
           
             
               
                 K 
                 + 
                 
                   
                     
                       T 
                        
                       
                           
                       
                        
                       
                         1 
                         / 
                         2 
                       
                     
                     T 
                   
                   × 
                   2 
                 
               
               = 
               
                 π 
                 2 
               
             
             , 
           
         
       
     
         [0000]    where T denotes a period of the input power supply, then Eq. 1 is used to calculate a line frequency (f=1/T) of the input power supply: 
         [0000]    
       
         
           
             
               
                 
                   f 
                   = 
                   
                     
                       ( 
                       
                         
                           1 
                           2 
                         
                         - 
                         
                           
                             arcsin 
                              
                             
                                 
                             
                              
                             K 
                           
                           π 
                         
                       
                       ) 
                     
                     
                       T 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0053]    It is noted that the line frequency of the input power supply can be calculated based on detections of two proportional-to-peak voltages on the leading portions of the input voltage V IN  with regard to VSS to improve accuracy. 
         [0054]      FIG. 4A  shows a block diagram of a detection circuit  440  according to an embodiment of the disclosure. The detection circuit  440  can be included in the detect-and-control circuit  120  to detect a line frequency of the AC power supply. The detection circuit  440  includes four resisters R 1 -R 4 , two diodes D 1  and D 2 , a calibration switch S, a capacitor C HOLD , two comparators  442  and  444 , and a counter/integrator  446 . These elements are coupled together as shown in  FIG. 4A . 
         [0055]    Due to the direction of the diode D 1 , the voltage V R  held by the capacitor C HOLD  corresponds to a fraction of the peak value V PEAK    
         [0000]    
       
         
           
             
               ( 
               
                 
                   V 
                   R 
                 
                 = 
                 
                   
                     V 
                     PEAK 
                   
                   × 
                   
                     
                       R 
                       4 
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                       + 
                       
                         R 
                         3 
                       
                       + 
                       
                         R 
                         4 
                       
                     
                   
                 
               
               ) 
             
             . 
           
         
       
     
         [0000]    The comparator  442  compares a voltage V A  to the voltage V R , and starts the counter/integrator  446  when a first event that the voltage V A  is equal to or larger than the voltage V R  happens, which means 
         [0000]    
       
         
           
             
               V 
               LINE 
             
             ≥ 
             
               
                 
                   R 
                   4 
                 
                 
                   
                     R 
                     2 
                   
                   + 
                   
                     R 
                     3 
                   
                   + 
                   
                     R 
                     4 
                   
                 
               
               × 
               
                 
                   V 
                   PEAK 
                 
                 . 
               
             
           
         
       
     
         [0000]    The comparator  444  compares a voltage V B  to the voltage V R , and stops the counter/integrator  446  when a second event that the voltage V B  is equal to or larger than the voltage V R  happens, which means 
         [0000]    
       
         
           
             
               V 
               LINE 
             
             ≥ 
             
               
                 
                   R 
                   4 
                 
                 
                   
                     R 
                     3 
                   
                   + 
                   
                     R 
                     4 
                   
                 
               
               × 
               
                 
                   V 
                   PEAK 
                 
                 . 
               
             
           
         
       
     
         [0000]    The counted number corresponds to a time duration T 1  between the first event and the second event. The time duration can be used to calculate the line frequency. 
         [0056]    In an embodiment, after the counter/integrator  446  stops, a pulse signal controls the calibration switch S to close and open. Thus, the voltage held by the capacitor C HOLD  corresponds to the fraction of the most recent peak value V PEAK . 
         [0057]    It is noted that, in an embodiment, the detection circuit  440  can be implemented on an IC chip. In another embodiment, a portion of the detection circuit  440 , such as the comparators  442  and  444  and the counter/integrator  446  can be implemented on an IC chip. 
         [0058]      FIG. 4B  shows a plot  460  of waveform examples for the detection circuit  440  according to an embodiment of the disclosure. The plot  460  includes a curve  480  of the normalized line voltage V LINE  with regard to VSS. The detection circuit  400  measures a time during T 1  between the first event that the normalized line voltage V LINE  with regard to VSS is equal to or larger than K 1   
         [0000]    
       
         
           
             
               ( 
               
                 
                   K 
                    
                   
                       
                   
                    
                   1 
                 
                 = 
                 
                   
                     R 
                     4 
                   
                   
                     
                       R 
                       2 
                     
                     + 
                     
                       R 
                       3 
                     
                     + 
                     
                       R 
                       4 
                     
                   
                 
               
               ) 
             
             , 
           
         
       
     
         [0000]    and the second event that the normalized line voltage V LINE  with regard to VSS is larger than K 2   
         [0000]    
       
         
           
             
               ( 
               
                 
                   K 
                    
                   
                       
                   
                    
                   2 
                 
                 = 
                 
                   
                     R 
                     4 
                   
                   
                     
                       R 
                       3 
                     
                     + 
                     
                       R 
                       4 
                     
                   
                 
               
               ) 
             
             . 
           
         
       
     
         [0059]    Then, Eq. 2 is used to calculate the line frequency: 
         [0000]    
       
         
           
             
               
                 
                   f 
                   = 
                   
                     
                       ( 
                       
                         
                           arcsin 
                            
                           
                               
                           
                            
                           K 
                            
                           
                               
                           
                            
                           2 
                         
                         - 
                         
                           arcsin 
                            
                           
                               
                           
                            
                           K 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       ) 
                     
                     
                       T 
                        
                       
                           
                       
                        
                       1 
                       × 
                       2 
                        
                       π 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   2 
                 
               
             
           
         
       
     
         [0060]    According to an embodiment of the disclosure, the detect-and-control circuit  120  can further calculate time of zero-crossings. For example, Eq. 3 is used to calculate a time duration T 2  from the second event to a first zero crossing, and Eq. 4 is used to calculate a time duration T 3  from the second event to a second zero crossing: 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                      
                     
                         
                     
                      
                     2 
                   
                   = 
                   
                     
                       T 
                        
                       
                           
                       
                        
                       1 
                       × 
                       
                         ( 
                         
                           π 
                           - 
                           
                             arcsin 
                              
                             
                                 
                             
                              
                             K 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         ) 
                       
                     
                     
                       ( 
                       
                         
                           arcsin 
                            
                           
                               
                           
                            
                           K 
                            
                           
                               
                           
                            
                           2 
                         
                         - 
                         
                           arcsin 
                            
                           
                               
                           
                            
                           K 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   3 
                 
               
             
             
               
                 
                   
                     T 
                      
                     
                         
                     
                      
                     3 
                   
                   = 
                   
                       
                   
                    
                   
                     
                       T 
                        
                       
                           
                       
                        
                       2 
                     
                     + 
                     
                       1 
                       
                         2 
                          
                         f 
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   4 
                 
               
             
           
         
       
     
         [0061]      FIG. 5A  shows a flowchart outlining a process example  500  for the detect-and-control circuit  120  to use two counters to calculate the line frequency of the AC power supply and to predict a time when the trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has a fixed voltage value. The process starts at S 501 , and proceeds to S 505 . 
         [0062]    At S 505 , the detect-and-control circuit  120  detects that the input voltage V IN  with regard to VSS is at a leading portion. In an example, the detect-and-control circuit  120  detects that the input voltage V IN  with regard to VSS is larger than zero and consistently increases. Then, the detect-and-control circuit  120  determines that the input voltage V IN  with regard to VSS is at a leading portion. 
         [0063]    At S 510 , the detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS to a reference voltage V REF , and determines whether the input voltage V IN  with regard to VSS is equal to or larger than the reference voltage V REF . It is noted that the reference voltage V REF  can be determined based on the fixed voltage value. For example, when the scaling factor between the input voltage V IN  and the line voltage V LINE  is one, the reference voltage V REF  is equal to the fixed voltage value. When the input voltage V IN  with regard to VSS is equal to or larger than the reference voltage V REF , the process proceeds to S 515 ; otherwise, the process returns to S 510 . 
         [0064]    At S 515 , the detect-and-control circuit  120  starts a first counter to count up from zero. 
         [0065]    At S 520 , the detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS to a first proportional-to-peak voltage TH 1  (K 1 ×V PEAK ) that is larger than reference voltage V REF , and determines whether the input voltage V IN  with regard to VSS is larger than the first proportional-to-peak voltage TH 1 . When the input voltage V IN  with regard to VSS is equal to or larger than the first proportional-to-peak voltage TH 1 , the process proceeds to S 525 ; otherwise, the process returns to S 520 . 
         [0066]    At S 525 , the detect-and-control circuit  120  stops the first counter, and stores the counted value. Further, the detect-and-control circuit  120  starts a second counter of a first rate to count up from zero. 
         [0067]    At S 530 , the detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS to a second proportional-to-peak voltage TH 2  (K 2 ×V PEAK ) that is larger than the first proportional-to-peak voltage TH 1  and determines whether the input voltage V IN  with regard to VSS is equal to or larger than the second proportional-to-peak voltage TH 2 . When the input voltage V IN  with regard to VSS is equal to or larger than the second proportional-to-peak voltage TH 2 , the process proceeds to S 535 ; otherwise, the process returns to S 530 . 
         [0068]    At S 535 , the detect-and-control circuit  120  stops the second counter from counting up and starts the second counter of a second rate to count down. 
         [0069]    At S 540 , the detect-and-control circuit  120  determines whether the second counter counts to zero. When the second counter counts to zero, the process proceeds to S 545 ; otherwise, the process returns to S 540 . 
         [0070]    At S 545 , the detect-and-control circuit  120  starts the first counter to count down. 
         [0071]    At S 550 , the detect-and-control circuit  120  determines whether the first counter counts to zero. When the second counter counts to zero, the process proceeds to S 555 ; otherwise, the process returns to S 550 . 
         [0072]    At S 555 , the detect-and-control circuit  120  generates an output signal indicating at that time the trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has the fixed voltage value. Then, the process proceeds to S 599  and terminates. 
         [0073]    It is noted that the process  500  can be suitably adjusted. In an example, the detect-and-control circuit  120  uses integrators instead of the counters. 
         [0074]      FIG. 5B  shows a plot  560  of waveform examples according to the process  500 . The plot  560  includes a curve  580  of the input voltage V IN  with regard to VSS. The trailing portion of the input voltage V IN  with regard to VSS may be distorted, as shown by  581 , due to load. The detect-and-control circuit  120  compares the input voltage V IN  with regard to VSS with the reference voltage V REF , the first proportional-to-peak voltage TH 1 , and the second proportional-to-peak voltage TH 2 , and controls the operation of the first counter and the second counter based on the comparisons. 
         [0075]    For example, the input voltage V IN  with regard to VSS starts to increase from time t 0 . At time t 1 , a first event that the input voltage V IN  with regard to VSS is equal to the reference voltage V REF  happens, and then the detect-and-control circuit  120  starts the first counter to count up. The input voltage V IN  with regard to VSS continues to increase. At time t 2 , a second event that the input voltage V IN  with regard to VSS is equal to the first proportional-to-peak voltage TH 1  happens, and then the detect-and-control circuit  120  stops the first counter and starts the second counter of a first rate to count up from zero. The input voltage V IN  with regard to VSS continues to increase. At time t 3 , a third event that the input voltage V IN  with regard to VSS is equal to the second proportional-to-peak voltage TH 2  happens, and then the detect-and-control circuit  120  stops the second counter from counting up and starts the second counter to count down at a second rate. The input voltage V IN  with regard to VSS continues to increase to the peak value V PEAK  and starts to decrease. At time t 4 , the second counter counts to zero, and then the detect-and-control circuit  120  starts the first counter to count down. At time t 5 , the first counter is zero, and the detect-and-control circuit  120  generates an output signal indicating at that time the trailing portion of the line voltage V LINE  with regard to the neutral voltage V NEUTRAL  has the fixed voltage value. 
         [0076]    It is noted that the first rate and the second rate can be suitably chosen according to Eq. 5: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       first 
                        
                       
                           
                       
                        
                       rate 
                     
                     
                       second 
                        
                       
                           
                       
                        
                       rate 
                     
                   
                   = 
                   
                     
                       π 
                       - 
                       
                         arcsin 
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                         K 
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                          
                         1 
                       
                       - 
                       
                         arcsin 
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                          
                         K 
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                          
                         2 
                       
                     
                     
                       
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                          
                         K 
                          
                         
                             
                         
                          
                         2 
                       
                       - 
                       
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                          
                         K 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                 
               
               
                 
                   Eq 
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                    
                   5 
                 
               
             
           
         
       
     
         [0077]    In addition, the line frequency can be calculated using Eq. 2 based on K 1 , K 2  and the time duration T 1  between time t 2  and time t 3 , for example. 
         [0078]    While the subject matter of the present disclosure has been described in conjunction with the specific embodiments thereof that are proposed as examples, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the present disclosure as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the scope of the present disclosure.

Technology Classification (CPC): 8