Patent Abstract:
A frequency jittering control circuit wherein by means of the characteristics of a PLL whose input switches between different frequencies, the output frequency of the PLL swings between the different frequencies to achieve the desired frequency jittering.

Full Description:
FIELD OF THE INVENTION  
       [0001]    The present invention relates to a frequency jittering control circuit and a method for using the same, in particular to a frequency jittering control circuit and a method which do not require a digital counter. The omission of the digital counter greatly reduces the complexity of the circuit. 
       BACKGROUND OF THE INVENTION  
       [0002]    To avoid electromagnetic interference (EMI) generated by high frequency signals, frequency jittering is a method that is often used in high frequency electronic products. Conventionally, frequency jittering is achieved by means of a digital counter; following the counts generated by the digital counter, the frequency shifts within a narrow range. The digital counter may be designed to provide sequential or random counts, and the frequency correspondingly shifts sequentially or randomly. A typical frequency jittering control circuit employing a digital counter may be found in U.S. Pat. No. 6,229,366. 
         [0003]    The drawbacks to use a digital counter are as follows: first, a digital counter is a huge circuit device; it is made of T flip-flops, and T flip-flops heavily consume circuit area. Moreover, in such frequency jittering control circuits, a designer has to design current source devices of different current amounts, and the corresponding control mechanism of the different current source devices by the output of the digital counter. Thus, the conventional circuit employing a digital counter is disadvantageous in that it is costly and complicated. 
       SUMMARY OF THE INVENTION  
       [0004]    In view of the foregoing, it is an objective of the present invention to provide a frequency jittering control circuit and a method thereof, which do not require a digital counter. The present invention takes advantage of the characteristics of a phase lock loop (PLL) in a very inventive way; by switching the input frequency of the PLL, the output frequency of the PLL swings between two frequency limits to provide the desired frequency jittering function. Moreover, the resulted frequency after frequency jittering is more random and smoother, providing a better anti-EMI effect than that resulting from conventional random counts by a digital counter. 
         [0005]    In accordance with the foregoing and other objectives of the present invention, and as disclosed by one embodiment of the present invention, a frequency jittering control circuit is disclosed, which comprises: at least two oscillators generating different reference frequencies; and a PLL having an input switching between the at least two oscillators. 
         [0006]    As disclosed by another embodiment of the present invention, a frequency jittering control circuit is disclosed, which comprises: a multi-frequency oscillator generating at least two different reference frequencies; and a PLL having an input switching between the at least two reference frequencies. 
         [0007]    According to another aspect of the present invention, a frequency jittering control method is disclosed, which comprises: generating at least two different frequencies, and providing a PLL having an input switching between the at least two reference frequencies so that its output swings between the at least two reference frequencies. 
         [0008]    It is to be understood that both the foregoing general description and the following detailed description are provided as examples, for illustration rather than limiting the scope of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0009]    These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
           [0010]      FIG. 1  is a schematic diagram showing a first embodiment of the present invention; 
           [0011]      FIG. 2  is a circuit diagram showing a typical structure of an oscillator; 
           [0012]      FIG. 3  is a schematic diagram showing a second embodiment of the present invention; and 
           [0013]      FIGS. 4A-4C  show three embodiments of the multi-frequency oscillator according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0014]    The present invention takes advantage of the characteristics of a PLL in an inventive way.  FIG. 1  is a schematic circuit diagram illustrating a first embodiment of the present invention. As shown in the figure, according to the present embodiment, a frequency jittering control circuit  20  includes two oscillators  22  and  24 , which generate two different reference frequencies respectively. A multiplexer  26  receives the outputs from the two oscillators  22  and  24 , and selects one of them. The output of the multiplexer  26  is electrically connected with the input of the PLL  28 , and thus the PLL  28  will gradually adjust its output frequency to be consistent with the output frequency of the multiplexer  26 . 
         [0015]    The circuit shown in  FIG. 1  operates as follows. At first, a user may set the reference frequencies of the two oscillators  22  and  24  as the upper and lower limits of the range for frequency jittering. The PLL  28  may start from any frequency, and the multiplexer  26  may start by selecting anyone of its inputs. When or after the PLL  28  synchronizes its output frequency to the output frequency of the multiplexer  26 , a signal S 0  is generated to switch the multiplexer  26  to the other frequency input. Due to the phase lock function of the PLL  28 , the output frequency of the PLL  28  will gradually increase or decrease, until it again synchronizes its output frequency to the output frequency of the multiplexer  26 . At or after this time point, the PLL  28  again sends a signal S 0  to switch the multiplexer  26  to the other frequency input. As such, the output frequency of the PLL  28  will swing between the upper and lower limits of the range, achieving the frequency jittering function. 
         [0016]    In comparison with the conventional frequency jittering method by means of a digital counter, the frequency spectrum of the present invention is smoother. The time point when the signal S 0  is generated could be any point in the waveform of the other frequency, and thus the swing is more random, providing a better anti-EMI effect. 
         [0017]    The above embodiment employs two oscillators with two different reference frequencies. Under the same spirit, it can be readily conceived to use more than two oscillators for the multiplexer  26  to switch among the different inputs. Here it should be emphasized that it is also possible to use only one oscillator, to generate two or more reference frequencies. 
         [0018]      FIG. 2  shows a typical structure of an oscillator. It works as follows. The signal S 2  or S 1  decides whether the circuit charges the capacitor C by the charging current source IC, or discharges the capacitor C by the discharging current source ID. The voltage across the capacitor C is compared with a high-level input VH of a high-level comparator  31  to generate the signal S 1 , and compared with a low-level input VL of a low-level comparator  32  to generate the signal S 2 . The charging and discharging of the capacitor C generate oscillation signals. 
         [0019]    Referring to  FIG. 3  and  FIGS. 4A-4C , a multi-frequency oscillator  32  can be made by slightly modifying the circuit shown in  FIG. 2 . As a first example ( FIG. 4A ), the multi-frequency oscillator  32  is provided with two charging current sources IC 1  and IC 2  of different current amounts, and the signal S 0  sent by the PLL  28  controls a multiplexer  42  to switch between the two charging current sources IC 1  and IC 2 . By this arrangement, the output of the PLL  28  also achieves the desired frequency jittering function. By the same token, similar effect can be achieved by providing two discharging current sources. 
         [0020]    As another example, referring to  FIG. 4B , the multi-frequency oscillator  32  is provided with two capacitors C 1  and C 2  of different capacitances, and the signal S 0  sent by the PLL  28  controls a multiplexer  42  to switch between the two capacitors C 1  and C 2 . As yet another example, referring to  FIG. 4C , the multi-frequency oscillator  32  is provided with two high-level reference voltage inputs VH 1  and VH 2 , and the signal S 0  sent by the PLL  28  controls a multiplexer  42  to switch between the two inputs VH 1  and VH 2 . (By the same token, the multi-frequency oscillator  32  can be provided with two low-level reference voltage inputs.) All the above arrangements can construct a multi-frequency oscillator  32  that is able to cause the PLL  28  to swing between an upper and a lower limits of a preset range, achieving the desired frequency jittering function more smoothly and more randomly than prior art. 
         [0021]    Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, they are for illustrative purpose rather than for limiting the scope of the present invention. Other variations and modifications are possible. For example, one may insert circuit devices which do not affect the primary function of the circuit between two of the illustrated devices. In view of the foregoing, it is intended that the present invention cover all such modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.

Technology Classification (CPC): 7