Patent Abstract:
Provided is a band gap constant-voltage circuit capable of achieving a quick startup time to thereby preventing an output voltage from being stabilized at 0 V due to noise or the like even under the normal condition. The band gap constant-voltage circuit according to the present invention includes: an output voltage detecting circuit for monitoring a voltage at an output terminal; and a current source which has a current value controlled through an output of the output voltage detecting circuit, in which the current source supplies a bipolar transistor constituting a level shifter circuit with a current when the voltage at the output terminal is lower than a predetermined voltage.

Full Description:
This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. JP2006-041690 filed Feb. 18, 2006, the entire content of which is hereby incorporated by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a band gap constant-voltage circuit, in particular, a startup circuit capable of securely outputting an output voltage upon power-up to thereby achieve a quick startup time. 
   2. Description of the Related Art 
     FIG. 2  is a circuit diagram of a conventional band gap constant-voltage circuit. The voltage circuit is constituted of PMOS transistors P 21 , P 22 , P 23 , P 24 , and P 25 , NMOS transistors NL 21 , NL 22 , and NL 23 , an n-channel type depression transistor ND 21 , bipolar transistors B 21  and B 22 , and resistors R 21 , R 22 , R 23 , and R 24 , and capacitor C 21 . In  FIG. 2 , when a ratio of the number of the bipolar transistor B 21  provided as a first bipolar transistor to that of the bipolar transistor B 22  provided as a second bipolar transistor is set to 1:N, an output voltage VREF expressed by an equation 1 can be obtained under a normal condition.
   VREF=VBE+Vtx 1 nN (1 +R 21 /R 22)  (equation 1) 
   In the equation 1, VBE is a voltage applied across the base and the emitter of a bipolar transistor, and Vt is obtained by the equation of Vt=kT/q, where k is a Boltzmann constant, T is an absolute temperature, and q is an electron charge. A state where the output voltage VREF is outputted is referred to as normal condition. 
   Therefore, the conventional example of  FIG. 2  is configured so as to be capable of outputting a predetermined output voltage VREF from an output terminal under a stable normal condition when a power supply voltage is applied across a power supply terminal VDD of high potential and a power supply terminal VSS of low potential. 
   (Patent Document 1) JP 2004-318604 A 
   However, the conventional band gap constant-voltage circuit shown in  FIG. 2  is slow in startup upon power-on, and therefore has a drawback in that the output voltage is stabilized at 0 V due to noise or the like even under the normal condition. 
   SUMMARY OF THE INVENTION 
   The present invention has been made to solve the above-mentioned problem, and has an object to provide a band gap constant-voltage circuit capable of achieving a quick startup time upon power-on to thereby preventing an output voltage from being stabilized at 0 V due to noise or the like even under the normal condition. 
   According to the band gap constant-voltage circuit of the present invention, in order to solve the above-mentioned problem, a voltage of an output terminal VREF 11  is monitored through a gate of a transistor NM 11 . Further, the drain of a transistor P 119  is connected to an emitter of a bipolar transistor B 11  so as to cause a current to flow through the bipolar transistor. 
   According to the band gap constant-voltage circuit of the present invention having the above-mentioned configuration, it is possible to achieve a quick startup time upon power-on and to prevent an output voltage from being stabilized at 0 V due to noise or the like even under the normal condition. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
       FIG. 1  is a circuit diagram showing a band gap constant-voltage circuit according to the present invention; and 
       FIG. 2  is a circuit diagram showing a conventional band gap constant-voltage circuit. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  is a circuit diagram showing a band gap constant-voltage circuit according to the present invention. 
   As shown in  FIG. 1 , the band gap constant-voltage circuit includes a differential amplifier, a level shifter circuit connected to an input of the differential amplifier, and a constant-voltage circuit. 
   The differential amplifier of the band gap constant-voltage circuit is constituted of a pair of p-channel type transistors P 112  and P 113 , n-channel type transistors NL 11  and NL 12 , the n-channel type transistors NL 11  and NL 12  each having a low threshold value (of, for example, 0.45 V). (Hereinafter, n-channel type transistor is abbreviated as n-type transistor, and p-channel type transistor is abbreviated as p-type transistor.) 
   The source of the n-type transistor NL 11  is connected to a ground which serves as a reference potential, while the drain thereof is connected to the drain of the p-type transistor P 112 . Also, the gate of the n-type transistor NL 11  is connected to the gate of the n-type transistor NL 12 . Further, the drain and the gate of the n-type transistor N 11  are connected to each other (diode connection). The source of the n-type transistor NL 12  is connected to a ground, while the drain thereof is connected to the drain of the p-type transistor P 113 , and the gate thereof is connected to the gate of the n-type transistor NL 11 . The sources and the back-gates of the p-type transistor P 112  and the p-type transistor P 113  are connected at a node  11  in common, and connected to a power supply voltage VCC through a p-type transistor P 108  and a p-type transistor P 104 . The gate of the p-type transistor P 112  is connected to the source of a p-type transistor P 114 , while the gate of the p-type transistor P 113  is connected to the source of a p-type transistor P 115 . 
   The n-type transistor NL 13  having a low threshold voltage (of, for example, 0.45 V) is connected to the output terminal of the differential amplifier, and is connected to the output terminal VREF 11  through a p-type transistor P 111  and a resistor R 14 . The source of the p-type transistor P 111  is connected to the drain of a p-type transistor P 107 . The gate of the p-type transistor P 107  is connected to the gate of the p-type transistor P 104  and is also connected to the gate of a p-type transistor P 103  which is used as a constant-current source. The p-type transistor P 107  is supplied with a current at the gate from the constant-current source to turn on and off the gate. In response to this, the p-type transistor P 107  supplies the output terminal VREF 11  with a current from the power supply voltage VCC through the resistor R 14 . 
   The p-type transistor P 104  is connected to the p-type transistor P 103  which is used as a constant-current source. The drain of the p-type transistor P 104  is connected to the differential amplifier through the p-type transistor P 108 , while the source thereof is connected to the power supply voltage VCC. Further, the gate of the p-type transistor P 104  is connected to the gate of each of the p-type transistors P 107 , P 106 , and P 105 . At the same time, the gate of the p-type transistor P 104  is also connected to the gate of the p-type transistor P 103  which is used as a constant-current source. The p-type transistor P 104  is supplied with a current at the gate from the constant-current source to turn on and off the gate. In response to this, the p-type transistor P 104  supplies the differential amplifier with a current from the power supply voltage VCC. Also, the p-type transistor P 103 , the p-type transistor P 104 , the p-type transistor P 105 , p-type transistor P 106 , and the p-type transistor P 107 , which are used as constant-voltage sources, constitute a current mirror circuit. 
   The p-type transistor P 104  is connected to the differential amplifier through the p-type transistor P 108  connected in cascode. In this manner, it is possible to prevent a channel length from being modulated, to thereby supply the differential amplifier with a stable current. Similarly, the p-type transistor P 105  is connected in cascode with a p-type transistor P 109 . The p-type transistor P 106  is connected in cascode with a p-type transistor P 110 . The p-type transistor P 107  is connected in cascode with the p-type transistor P 111 . 
   The p-type transistor P 103  and an n-type depression transistor ND 13  are connected to each other through the drains thereof, and used as a constant-voltage source. The n-type depression transistor ND 13  used as a direct-current power source has the source and the gate connected to a ground, and has the drain connected to the drain of the p-type transistor P 103 . The source of the p-type transistor P 103  is connected to the power supply voltage VCC, while the drain thereof is connected to the drain of the n-type depression transistor ND 13 . The p-type transistor P 103  has the drain and the gate connected to each other (diode connection), and the gate thereof is connected to the gate of each of the p-type transistor P 104 , p-type transistor P 105 , p-type transistor P 106 , and the p-type transistor P 107 . Similarly, a p-type transistor P 102  and an n-type depression transistor ND 12  are also used as a constant-voltage source, and the gate of the p-type transistor P 102  is connected to the gate of each of the p-type transistor P 108 , p-type transistor P 109 , and p-type transistor P 110 . A p-type transistor P 101  and an n-type depression transistor ND 11  are also used as a constant-voltage source, and the gate of the p-type transistor P 101  is connected to the gate of the p-type transistor P 111 . 
   The p-type transistor P 114  used as a level shifter circuit has the drain connected to a ground. The source of the p-type transistor P 114  is connected to the power supply voltage VCC through the gate of the p-type transistor P 112 , the p-type transistor P 109 , and the p-type transistor P 105 . Also, the gate of the p-type transistor P 114  is connected to the output terminal VREF 11  through a resistor R 12  and R 14 . Similarly, the p-type transistor P 115  used as a level shifter circuit has the drain connected to a ground, while the source thereof is connected to the power supply voltage VCC through the gate of the p-type transistor P 113 , the p-type transistor P 110 , and the p-type transistor P 106 . Also, the gate of the p-type transistor P 115  is connected to the output terminal VREF 11  through a resistor R 11  and R 14 . 
   Connected between the output terminal VREF 11  and a ground are the resistor R 12 , the resistor R 13 , and a bipolar transistor B 12  in this order from the output terminal VREF 11  side through the resister  14 . In addition, connected between the output terminal VREF 11  and a ground are the resistor R 11  and a bipolar transistor B 11  in this order from the output terminal VREF 11  side through the resister  14 . 
   The bipolar transistor B 12  has the base and the collector both connected to a ground, while the emitter thereof is connected to a resistor R 13 . The resistor R 13  is connected to the bipolar transistor B 12  at one end, while connected to the resistor  12  and to the gate of the p-type transistor P 114  at the other end. The resistor R 12  is connected to the resistor R 13  and to the gate of the p-type transistor P 114  at one end, while connected to the output terminal VREF 11  at the other end through the resister  14 . 
   The bipolar transistor B 11  has the base and the collector both connected to a ground, while has the emitter connected to the resistor R 11  and to the gate of the p-type transistor P 115 . Also, the resistor R 11  is connected to the bipolar transistor B 12  at one end, while connected to the output terminal VREF 11  at the other end through the resister  14 . 
   The band gap constant-voltage circuit of the present invention further includes a startup circuit  1  described as follows. 
   The startup circuit  1  is constituted of an n-type transistor NM 11  and a p-type transistor P 119 . The n-type transistor NM 11  is an output voltage detecting circuit for detecting a voltage of the output terminal VREF 11 . The p-type transistor P 119  is a current source controlled by an output from the output voltage detecting circuit. 
   The n-type transistor NM 11  has the gate connected to the output terminal VREF 11 , and has the source connected to the drain of a p-type transistor P 117 . The p-type transistor P 117  constitutes a current mirror circuit with a p-type transistor P 116 , and causes a constant current generated by an n-type depression transistor ND 14  to flow through the n-type transistor NM 11 . The n-type depression transistor ND 14  used as a direct current source has the source and the gate connected to a ground. 
   A p-type transistor P 118  and an n-type transistor NM 12  constitute an inverter. The inverter is connected to a node of the p-type transistor P 117  and the n-type transistor NM 11  and uses the node as input. The output of the inverter constituted of the p-type transistor P 118  and the n-type transistor NM 12  is connected to the gate of the p-type transistor P 119  which is used as a current source. The source of the p-type transistor P 119  is connected to the power source voltage VCC while the drain thereof is connected the emitter of the bipolar transistor B 11 . 
   Next, an operation of the above-mentioned startup circuit  1  of the band gap constant-voltage circuit according to the present invention is explained. 
   When power is turned on, the n-type transistor NM 11  remains turned off because the voltage at the output terminal VREF 11  is lower than the threshold voltage value of the n-type transistor NM 11 . Accordingly, the n-type transistor NM 12  is turned on and the p-type transistor P 119  is turned on. When the p-type transistor P 119  is turned on, a current flow through the bipolar transistor B 11 , which increases a voltage at the emitter of the bipolar transistor B 11 , with the result that the voltage at the output terminal VREF 11  is increased. The voltage at the output terminal VREF 11  is increased to exceed the threshold voltage value of the n-type transistor NM 11 , to thereby turn on the n-type transistor NM 11 . Therefore, the p-type transistor P 118  is turned on and the p-type transistor P 119  is turned off, leading to a suspension of a current supply to the bipolar transistor B 11 . 
   Therefore, according to the startup circuit  1  described above, it is possible to achieve a quick startup time upon power-up of the band gap constant-voltage circuit. Further, it is also possible to control the startup time upon power-up by adjusting the size of the p-type transistor P 119 . 
   Also, the n-type transistor MN 11  monitors the voltage at the output terminal VREF 11  not only on power-up but all other times and operates so as to keep the voltage at the output terminal VREF 11  constant. Therefore, it is also possible to prevent the voltage at the output terminal VREF 11  from being stabilized at 0 V due to an influence of noise or the like.

Technology Classification (CPC): 6