Patent Abstract:
A sampling circuit and method are disclosed. The sampling circuit includes a buffer, a holding capacitor, a set of switches, and at least two voltage references. The buffer drives buffered analog input signal via a first switch to a first node of holding capacitor. A second switch connects a second node of the holding capacitor to a first reference voltage. A third switch connects the second node of the holding capacitor to a second reference voltage. When the first and second switches are closed, charge accumulates on the holding capacitor. Opening the second switch terminates charging. The third switch biases the charged capacitor to the second reference voltage and the sampled output is taken from the first node of the holding capacitor. A rotary clock and control circuit provide the precise timing for the switches, especially the opening of the second switch, which determines the end of the sampling time.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application incorporates by reference U.S. Pat. No. 6,556,089. 
   This application claims priority to and incorporates by reference Great Britain Application GB0416803 AO, titled “ROTARY FLASH ADC, filed on Jul. 27, 2004, in Great Britain. 
   FIELD OF THE INVENTION 
   The present invention relates generally to analog to digital converters and more particularly to the sample and hold circuitry used therein. 
   DESCRIPTION OF THE RELATED ART 
   In analog to digital conversion (ADC) systems, when a conversion is performed, an analog signal must be sampled at an instant in time and then held while a digital equivalent of the signal is computed.  FIG. 1  shows a convention dual-slope A/D conversion system, which includes an integrator  12 , with integration capacitor  14  and integration resistor  16 , comparator  18 , voltage reference, digital pulse generator  22  and binary counter  24 . Also included are switches S 1   26  and S 2   28  for controlling the various phases of measurement. In such a system, the analog signal vIN must be held stable during a precise time interval in which the first phase of an integration occurs. During the second phase, an integration of a stable reference occurs. The time to integrate the stable reference back to a known condition is measured digitally and is proportional to the sampled input signal. Key to this system is the quality of the sample and hold circuitry. 
   Conventional sample and hold circuits, such as the one shown in  FIG. 2 , usually include an input buffer stage  32 , an input transmission gate S 1   34 , a holding capacitor C  36 , and an output buffer stage  38 . The input buffer  32  replicates the analog input signal while minimizing the load on the analog signal. The input buffer  32  also provides the current to charge the holding capacitor  36 . The output buffer  38  replicates the capacitor voltage when the transmission gate  34  is open. It also common for sample and hold circuits to have a buffer chain in the path of the signal that controls the transmission gate, which is typically a MOS transistor. 
   Existing sample and hold circuits have a problem with precision due to aperture jitter. Aperture jitter (cycle-to-cycle) occurs when the sampling window moves with respect to the input waveform. This is an especially difficult problem when the input waveform is a high slew rate signal. Sampling a little earlier gives one voltage and sampling a little later gives a different voltage. The time uncertainty of the sampling window translates to uncertainty in the digital word used to represent the sampled quantity. The higher the frequency of the input voltage, the greater the potential error. In addition to the time uncertainty of the sampling window, inaccurate timing for defining the window means that part of the sampling interval is used up, thereby slowing the circuitry down. 
   Another problem with the existing art is signal feedthough from the analog input due to parasitic capacitances of the MOSFET device. 
   As a result of the above deficiencies current sample and hold circuits typically have a 400 femtosecond (fs) to 500 fs rating for the jitter of the sampling window. 
   Prior art has attempted to deal with these deficiencies by minimizing the delay of the buffer chain (a main source of jitter), driving the MOSFET pass transistor with a high amount of current and by driving the gate of the MOSFET pass transistor with a high slew rate signal. 
   One particular solution uses a resonant circuit whose output has a large amplitude sine wave buffered with a single stage that drives the sampling switch. The high amplitude is helpful in reducing the jitter of sampling window because of its high slew rate (high dV/dt). A deficiency of this approach is that the high voltage output may be greater than the supply voltage, Vdd, creating problems with the operation of the sampling switch when implemented as a MOSFET device. Furthermore, the resonant circuit frequency of the resonant circuit is “pulled” (altered) by the capacitances of the sampling circuit, making the exact resonant frequency a function of the circuitry. 
   Also, because of the presence of parasitic capacitances on the MOSFET, such as the gate capacitances, (gate-to-drain c GD , gate-to-source c GS ), which are a function of the voltages on the device, analog input voltages modulate the waveform used to control (open and close) the switch and therefore affect the sampling period. This error is not the same as jitter, because it is proportional to the input signal. 
   There is a need for a more precise sample and hold circuit, one that can avoid sampling errors even with very fast analog input signals. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention is directed to the above need. The invention is a completely new solution using rotary clocks which provide a plurality of clocks having any desired phase relationship. Rotary clock cycle-to-cycle jitter is very low, in the 10 fs range. 
   One embodiment of the present invention is a sampling circuit, which includes a buffer, a holding capacitor, three switches, a multi-phase oscillator, and a control circuit. The buffer has an input for receiving an input signal to be sampled, and drives at its output a buffered version of the input signal. The holding capacitor is configured to hold between its first and second nodes a voltage representative of a sampled, buffered input signal. The first switch is connected between the buffer output and the first node of the holding capacitor, where the first node of the holding capacitor is configured to provide the sampled output voltage. The second switch is connected between the second node of the holding capacitor and a first reference voltage. The third switch is connected between the second node of the holding capacitor and a second reference voltage. The multi-phase oscillator is configured to provide one or more clock signals, one of which operates the second switch. The control circuit receives the one or more rotary clock signals and provides timing pulses for opening and closing the first switch and third switches. The first switch and second switch are closed during sampling of the input signal and the second switch is opened to end the sampling. After the second switch is opened, the control circuit closes the third switch to bias the voltage on the charging capacitor with the second reference voltage. 
   Another embodiment of the present invention is a method for sampling an input signal. The method includes connecting a first node of a holding capacitor to a first reference voltage by means of a first switch, connecting a second node of a holding capacitor to the analog signal by means of a second switch, and accumulating charge on a second node of the holding capacitor during a prescribed interval of time while the analog signal is connected to the holding capacitor. The first node of the holding capacitor is then disconnected from the first reference voltage to end the accumulation of charge and the second node of the holding capacitor is disconnected from the analog signal. The first node of the holding capacitor is then connected to a second reference voltage by means of a third switch, and the sampled analog signal is available on the second node of the holding capacitor. 
   One advantage of the present invention is that precise timing control of the switches is possible via the many phases that are available from the rotary traveling wave clock. This precise timing control allows the sampling window to be a precise value. 
   Yet another advantage of the present invention is that there is minimal effect on the rotary clock due to the arrangement of the holding capacitor and the second switch. This helps to preserve the favorable characteristics, including low jitter, of the rotary clock for the circuit. 
   Yet another advantage of the present invention is that the second switch can be a large semiconductor device when the auxiliary switch is used, because the second switch changes state with practically no voltage across it. 
   Yet another advantage is that an A to D circuit can be built with more bits of precision because of the low noise and precise timing characteristics of the rotary traveling wave clock. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
       FIG. 1  shows a conventional analog-to-digital converter; 
       FIG. 2  shows the conventional approach to sampling; 
       FIG. 3  shows an embodiment of the present invention; 
       FIG. 4  shows a timing diagram for controlling the sampling circuit of the present invention; 
       FIG. 5  shows an embodiment of the present invention using MOS transistors; and 
       FIG. 6  shows a timing diagram for the circuitry of figure 5. 
       FIG. 7  is an outline diagram for a transmission-line structure hereof; 
       FIG. 8  shows a Moebius strip; 
       FIG. 9  is an outline circuit diagram for a traveling wave oscillator hereof; 
       FIG. 10  is another outline circuit diagram for a traveling wave oscillator hereof; 
       FIGS. 11   a  and  11   b  are equivalent circuits for distributed electrical models of a portion of a transmission-line hereof; 
       FIG. 12  shows a pair of back-to-back inverters connected across part of a transmission-line; and 
       FIGS. 13   a  and  13   b  are outline and equivalent circuit diagrams of CMOS back-to-back inverters. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3  shows an embodiment  40  of the present invention. The sampling system  40  includes switches SA  42 , SB  44 , SC  46 , SD  48  and SE  49 , a rotary clock oscillator  50  (described in U.S. Pat. No. 6,556,089), an input buffer  52 , a sampling capacitor  54 , a voltage reference  56 , and control circuitry  58 . 
   Switch SE  49  connects the input analog voltage to the input buffer  52 . Switch SB  44  connects the output of the input buffer  52  to a first node of the charging capacitor C  54 . Switch SA  42  connects a second node of the charging capacitor  54  to a ground reference node  60 . Switch SC  46  connects the second node of the charging capacitor  54  to a voltage reference node  62 . Switch SD  48  is connected in parallel with switch SA  42 , and is discussed below. The voltage reference Vref  56  can be any voltage, including the ground potential. The rotary clock oscillator  50  and control circuit  58  provide the clock taps and timing controls for the various switches. 
   Operation 
   Referring to  FIG. 4 , which shows the sampling interval divided into four phases, Φ 1 , Φ 2 , Φ 3 , Φ 4  sampling occurs during a interval t 1 ≦t≦t 5  of the rotary clock. Prior to the start t 1  of the sampling interval, switches SA  42 , SC  46  and SD  48  are open and SB  44  and SE  49  are closed. When switches SA  42 , SB  44  and SE  49  are closed at t 1 , sampling starts and charge accumulates on capacitor C  54 . Sampling is completed at t 5  when switch SA  42  opens, disconnecting the charging capacitor  54  from ground node  60  and thus preventing the accumulation of more charge on capacitor C  54 . A short time later at t 6 , switch SB  44  opens, isolating the charging capacitor  54 , which now floats for an instant. No charge injection occurs when switch SB  44  opens. At the same or nearly the same time t 6 , switch SC  46  closes, causing both sides of the charging capacitor  54  to increase by a voltage equal to Vref. During interval t 7 ≦t≦t 8 , switch SD  48 , described in more detail below, pre-discharges any charge on switch SA  42 . Of course, other timing schemes are possible and timing can be improved with more timing phases of the rotary clock  50 . 
     FIG. 5  shows an embodiment of the present invention using MOS transistors. Transistor M 1   82  connects between the analog input vIN, and the gate of transistor M 2   84 . The gate of transistor M 1   82  connects to the mux signal. Transistor M 2   82  is connected between a current source  86  (at its source) and the drain of transistor M 3   88 , whose source is connected to ground. Transistors M 4   90  and M 5   92  are connected in parallel with their drains connected to the gate of transistor M 6   94  and their sources connected to ground. The gate of transistor M 6   94  is the storage node  96  for the sampled voltage, vHOLD. The gate of M 5   92  is connected to the samp signal and the gate of M 4   90  is connected to the help signal. The source (output) of transistor M 2   84  is connected to the source of transistor M 6   94 , whose capacitance acts as the holding capacitor Chold. The drain of transistor M 6   96  is the circuit output. Transistor M 7   98  connects the source of M 6   94  to a reference voltage Vref  100 . The gate of transistor M 7   98  is connected to the sample_delayed signal. Transistors M 8   102  and M 9   104  are used in a calibration circuit. Transistors M 10   106  and M 11   108  comprise a current mirror to supply current to the transistor M 2   84 . 
     FIG. 6  shows selected timing signals for controlling the circuitry of  FIG. 5 . The signal sample_delayed in  FIG. 5  (Samp_delayed in  FIG. 6 ) is turned on first, at t 0 , to turn on the buffer (source follower) transistor M 2   84  by providing a path to ground for the current source from the current mirror M 10 /M 11   86 . At t 0 , the mux signal is also asserted, which causes the input switch M 1   82  to connect the input signal vIN to the gate of the buffer transistor M 2   84 . Following this, the samp signal is asserted, at t 1 , causing the M 5   92  transistor to conduct. This provides a ground reference for one node of the holding capacitor (at the gate of transistor M 6   94 ). Charge accumulation occurs while the sample signal is asserted. When the samp signal is de-asserted at t 5 , sampling stops and a short time later, after t 6 , the mux signal is de-asserted, isolating transistor M 2   84  from the analog input signal vIN. Following de-assertion of the samp signal, the sample_delayed signal is de-asserted, at t 6 , causing the source follower  84  to be inactivated and the reference voltage  100  to bias the charge on the holding capacitor by turning on transistor M 7   98 . The sampled voltage is taken from the drain of the transistor M 6   94 . 
   The transistor M 5   92  (the sampling transistor) operates without any significant drain to source voltage (Vds). This has the advantage of causing any turn-off charge injection to the gate of the M 5   92  transistor to become a constant, thereby allowing the appropriate rotary clock signal to be directly connected to the gate. The fast edge rate and low phase noise of the rotary clock signal then controls the switching of the M 5  transistor  92 . 
   The transistor M 4   90  is used, in some embodiments such as the one shown, to pre-discharge the drain of transistor M 5   92  before, transistor M 5   92  is turned on. 
   The holding capacitor Chold is the gate to channel/drain/source capacitance of the transistor M 6   95 . This is permissible because the MOS transistor is always operating in the enhancement region (triode region) of operation making use of this capacitance reliable. 
   Setting the Size of the Holding Capacitance 
   The relation kT/VC&lt;LSB, which assures that the thermal noise level is less than the least significant bit (LSB) of the digital representation of the input signal, can be used to set the size of C. The size of C, referring to  FIG. 3 , then sets the size of the switch SA&#39;s resistance encountered during charging and this puts a limit on the W/L ratio of a MOS transistor used for switch SA. It is desirable to have the charging time equal to 10RC, where C is determined by kT/VC&lt;LSB relation, and R=R SA  is the resistance of switch SA. For example, if the input signal has a range of 1 volt and there is to be 16-bit digital representation of the signal, then the LSB is about 15 uV. Setting C to 100 fF, causes kT/VC to be about 0.04 uV and the relative noise level to be about 0.25% of the LSB. With an oscillator frequency of 5 GHz ( 1/200 pS), a convenient sampling period is about 100 pS. This means that the RC time constant should not exceed 10 pS and constrains R to be about 100 ohms or less. 
   Auxiliary Switch 
   When switch SA  42 , in  FIG. 3 , is implemented as a MOS transistor (M 5   92  in  FIG. 5 ) some precautions need to be taken to assure the best results. It has been discovered that the rotary clock is most affected when the edges of the clock pass the input (gate) of the SA transistor. Before or after the edges of the clock pass the gate, there is little or no effect on the clock. Thus, to minimize the effect on the rotary clock when the SA switch is activated, an auxiliary switch SD  48  (M 4   90  in  FIG. 5 ), in one embodiment, is employed. The switch is turned on just ahead in time of the sampling interval, at time t 7  in  FIG. 4 , to bleed off (pre-discharge) any charge on the second node of the capacitor C  54 , so that when the SA  42  transistor is turned on, there is practically no voltage across it. This prevents the rotary clock from being disturbed because, when the edges of the clock pass the SA transistor  42 , there is no voltage across the transistor and thus little or no coupling occurs from drain of the transistor back to the clock. The auxiliary switch SD  48  need only be strong enough to bleed the charge; it does not need to be so strong as to hold the full charge of the capacitor. The auxiliary switch SD  48  is conveniently controlled from a buffered tap on the rotary clock. This configuration allows the intrinsic jitter of the rotary clock to be controlling, saves power, and allows the SA transistor  42  to be larger than otherwise (because its capacitance has little or no effect on the rotary clock). 
   The rotary clock may be tuned to a PLL that is driven from a reference clock received from a clock input pin on chip. The PLL averages the noise of the reference clock because of its low pass filter. The PLL multiplies up the frequency to run the rotary clock and tunes the rotary clock by varactor or switched capacitor. 
   Known transmission-lines broadly fall into two categories in that they are either open-ended or specifically terminated either partially or fully. Transmission-lines as proposed herein are different in being neither terminated nor open-ended. They are not even unterminated as such term might be understood hitherto; and, as unterminated herein, are seen as constituting a structural aspect of invention, including by reason of affording a signal path exhibiting endless electromagnetic continuity. 
     FIG. 7  shows such a transmission-line  515  as a structure that is further seen as physically endless, specifically comprising a single continuous “originating” conductor formation  517  shown forming two appropriately spaced generally parallel traces as loops  515   a ,  515   b in  FIG. 9  with a cross-over at  519  that does not involve any local electrical connection of the conductor  517 . Herein, the length of the originating conductor  517  is taken as S, and corresponds to two ‘laps’ of the transmission-line  515  as defined between the spaced loop traces  515   a ,  515   b  and through the cross-over  519 . 
   This structure of the transmission-line  515  has a planar equivalence to a Moebius strip, see  FIG. 8 , where an endless strip with a single twist through 180° has the remarkable topology of effectively converting a two-sided and two-edged, but twisted and ends-joined, originating strip to have only one side and one edge, see arrows endlessly tracking the centre line of the strip. From any position along the strip, return will be with originally left- and right-hand edges reversed, inverted or transposed. The same would be true for any odd number of such twists along the length of the strip. Such a strip of conductive material would perform as required for signal paths of embodiments of this invention, and constitutes another structural aspect of invention. A flexible substrate would allow implementing a true Mobius strip transmission-line structure, i.e. with graduality of twist that could be advantageous compared with planar equivalent cross-over  519 . A flexible printed circuit board so formed and with its ICs mounted is seen as a feasible proposition. 
     FIG. 9  is a circuit diagram for a pulse generator, actually an oscillator, using the transmission-line  515  of  FIG. 7 , specifically further having plural spaced regenerative active means conveniently as bi-directional inverting switching/amplifying circuitry  521  connected between the conductive loop traces  515   a ,  515   b . The circuitry  521  is further illustrated in this particular embodiment as comprising two inverters  523   a ,  523   b  that are connected back-to-back. Alternatives regenerative means that rely on negative resistance, negative capacitance or are otherwise suitably non-linear, and regenerative (such as Gunn diodes) or are of transmission- line nature. It is preferred that the circuitry  521  is plural and distributed along the transmission- line  515 , further preferably evenly, or substantially evenly; also in large numbers say up to 100 or more, further preferably as many and each as small as reasonably practical. 
   Inverters  523   a ,  523   b  of each switching amplifier  521  will have the usual operative connections to relatively positive and negative supply rails, usually V+ and GND, respectively. Respective input/output terminals of each circuit  521  are shown connected to the transmission- line  515  between the loops  515   a ,  515   b  at substantially maximum spacing apart along the effectively single conductor  517 , thus each at substantially halfway around the transmission- line  515  relative to the other. 
     FIG. 10  is another circuit diagram for an oscillator using a transmission-line structure hereof but with three cross-overs  519   1 ,  519   2 ,  519   3 , thus the same Moebius strip-like reversing/inverting/transposing property as applies in  FIG. 9 . The rectangular and circular shapes shown for the transmission-line  515  are for convenience of illustration. They can be any shape, including geometrically irregular, so long as they have a length appropriate to the desired operating frequency, i.e. so that a signal leaving an amplifier  521  arrives back inverted after a ful ‘lap’ of the transmission-line  515 , i.e. effectively the spacing between the ioops  515   a ,b plus the crossover  519 , traversed in a time Tp effectively defining a pulse width or half-cycle oscillation time of the operating frequency. 
   Advantages of evenly distributing the amplifiers  521  along the transmission-line  515  are twofold. Firstly, spreading stray capacitance effectively lumped at associated amplifiers  521  for better and easier absorbing into the transmission-line characteristic impedance Zo thus reducing and signal reflection effects and improving poor waveshape definition. Secondly, the signal amplitude determined by the supply voltages V+ and GND will be more substantially constant over the entire transmission-line  515  better to compensate for losses associated with the transmission-lines dielectric and conductor materials. A continuous closed-loop transmission- line  515  with regenerative switching means  521  substantially evenly distributed and connected can closely resemble a substantially uniform structure that appears the same at any point. 
   A good rule is for elementary capacitance and inductance (Ce and Le) associated with each regenerative switching means and forming a resonant shunt tank LC circuit to have a resonant frequency of 1/(2π√{square root over (L e C e )}) that is greater than the self-sustaining oscillating frequency F (F 3 , F 5  etc.) of the transmission-line  515 . 
     FIG. 11   a  is a distributed electrical equivalent circuit or model of a portion of a transmission-line  515  hereof. It shows alternate distributed resistive (R) and inductive (L) elements connected in series, i.e. R 0  connected in series with L 1  in turn connected in series with R   2   and so on for a portion of loop  515   a , and registering L 0  connected in series with R 1  in turn connected in series with L 2  and so on for the adjacent portion of loop  515   b ; and distributed capacitive elements C 0  and C 1  shown connected in parallel across the transmission-line  15  thus to the loops  515   a  and  515   b  between the resistive/inductive elements R 0 / L 1  and the inductive/resistive elements L 0 / R 1 , respectively for C 0  and between the inductive/resistive elements L 1 / R 2  and the resistive/inductive elements R 1 / L 2 , respectively for C 1 : where the identities R 0 =R 1 =R 2 , L 0 =L 1 =L 2  and C 0 =C 1  substantially hold and the illustrated distributed RLC model extends over the whole length of the transmission-line  515 . Although not shown, there will actually be a parasitic resistive element in parallel with each capacitive element C, specifically its dielectric material. 
     FIG. 11   b  is a further simplified alternative distributed electrical equivalent circuit or model that ignores resistance, see replacement of those of  FIG. 11   a  by further distribution of inductive elements in series at half (L/2) their value (L) in  FIG. 11   a . This model is useful for understanding basic principles of operation of transmission-lines embodying the invention. 
   During a ‘start-up’ phase, i.e. after power is first applied to the amplifiers  521 , oscillation will get initiated from amplification of inherent noise within the amplifiers  521 , thus begin substantially chaotically though it will quickly settle to oscillation at a fundamental frequency F, typically within nano-seconds. For each amplifier  521 , respective signals from its inverters  523   a  and  523   b  arrive back inverted after experiencing a propagation delay Tp around the transmission-line  515 . This propagation delay Tp is a function of the inductive and capacitive parameters of the transmission-line  515 ; which, as expressed in henrys per meter (L) and in farads per meter (C) to include all capacitive loading of the transmission-line, lead to a characteristic impedance Zo=SQR (L/C) and a line traverse or propagation or phase velocity-Pv=1/SQRT(L/C). Reinforcement, i.e. selective amplification, of those frequencies for which the delay Tp is an integer sub-divisor of a half-cycle time gives rise to the dominant lowest frequency, i.e. the fundamental frequency F=1/(2•Tp), for which the sub-divisor condition is satisfied. All other integer multiples of this frequency also satisfy this sub-divisor condition, but gain of the amplifiers  521  falls off, i.e. decreases, for higher frequencies, so the transmission-line  515  will quickly settle to fundamental oscillation at the frequency F. 
   The transmission-line  515  has endless electromagnetic continuity, which, along with fast switching times of preferred transistors in the inverters  523   a  and  523   b , leads to a strongly square wave-form containing odd harmonics of the fundamental frequency F in effectively reinforced oscillation. At the fundamental oscillating frequency F, including the odd harmonic frequencies, the terminals of the amplifiers  521  appear substantially unloaded, due to the transmission-line  515  being ‘closed-loop’ without any form of termination, which results very desirably in low power dissipation and low drive requirements. The inductance and capacitance per unit length of the transmission-line  515  can be altered independently, as can also be desirable and advantageous. 
     FIG. 12  shows a pair of back-to-back inverters  523   a ,  523   b  with supply line connectors and indications of distributed inductive (L/2) and capacitive (C) elements of a transmission-line as per  FIG. 11   b .  FIG. 13   a  shows N-channel and P-channel Mosfet implementation of the back-to-back inverters  523   a  and  523   b , see out of NMOS and PMOS transistors.  FIG. 13   b  shows an equivalent circuit diagram for NMOS (N1, N2) and PMOS (P1, P2) transistors, together with their parasitic capacitances. The gate terminals of transistors P1 and N1 are connected to the conductive trace  515   a  and to the drain terminals of transistors P2 and N2. Similarly, the gate terminals of transistors P2 and N2 are connected to the conductive trace  515   b  and to the drain terminals of transistors P2 and N2. The PMOS gate-source capacitances CgsP1 and CgsP2, the PMOS gate-drain capacitances CgdP1 and CgdP2, and the PMOS drain-source and substrate capacitances CdbP1 and CdbP2, also the NMOS gate-source capacitances CgsN1 and CgsN2, the NMOS gate-drain capacitances CgdN1 and CgdN2, and the NMOS drain-source and substrate capacitances CdbN1 and CdbN2 are effectively absorbed into the characteristic impedance Zo of the transmission-line, so have much less effect upon transit times of the individual NMOS and PMOS transistors. The rise and fall times of the waveforms Φ1 and Φ2 are thus much faster than for prior circuits. 
   Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.

Technology Classification (CPC): 6