Patent Abstract:
A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.

Full Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   This application is a continuation of U.S. Application Ser. No. 11/111,305, filed Apr. 20, 2005, which is a division of U.S. Application Ser. No. 10/442,670, filed May 20, 2003, now U.S. Pat. No. 6,916,745, the disclosures of which are incorporated herein by reference for all purposes. 

   BACKGROUND OF THE INVENTION 
   The present invention relates to semiconductor MOSFET technology and more particularly to a trench MOSFET having self-aligned features. 
   Power MOSFETs (metal oxide semiconductor field effect transistors) are well known in the semiconductor industry. One variety of power MOSFETs is the vertically-conducting trench MOSFET. A cross-section view of such a MOSFET is shown in  FIG. 1 . MOSFET  100  has trenches  111  each including a polysilicon gate  112  insulated from body regions  114  by a gate dielectric  110 . Source regions  116  flank each side of trenches  111 . Dielectric layer  120  insulates gates  112  from overlying metal layer  126 . Substrate region  102  forms the drain of MOSFET  100 . 
   When MOSFET  100  is biased in the on state, current flows vertically between source regions  116  and substrate  102 . The current capability of MOSFET  100  in the on state is a function of the drain to source resistance (Rds on ). To improve the current capability of the MOSFET, it is necessary to reduce the Rds on . One way to reduce the Rds on  of the trench MOSFET is to increase the trench density (i.e., to increase the number of trenches per unit area). This may be achieved by reducing the cell pitch. However, reducing the cell pitch of MOSFETs is limited by the particulars of the MOSFET cell structure and the specific process recipe used to manufacture the MOSFET. Reducing the cell pitch is made further difficult by such limitations of the manufacturing process technology as the minimum critical dimensions the photolithography tools are configured to resolve, the minimum required spacing between different cell regions as dictated by the design rules, and the misalignment tolerances. 
   The different dimensions that determine the minimum cell pitch for trench MOSFET  100  are shown in  FIG. 1 . Dimension A is the minimum trench width the photolithography tools are configured to resolve, dimension B is the minimum contact opening the photolithography tools are configured to resolve, dimension C is the minimum trench-to-contact spacing dictated by the design rules, and dimension D is the contact registration error tolerance or contact misalignment tolerance. The minimum cell pitch for MOSFET  100  thus equals A+B+2C+2D. Reduction of any of these dimensions without complicating the process technology is difficult to achieve. 
   Thus, a new approach wherein the cell pitch of the trench MOSFET can be reduced without increasing the process complexity is desirable. 
   BRIEF SUMMARY OF THE INVENTION 
   In accordance with an embodiment of the invention, a field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions. 
   In one embodiment, a metal layer extends into each contact opening for contacting the regions along sidewalls of the source regions. 
   In another embodiment, the entirety of each source region is disposed below a corresponding one of the common upper sidewalls. 
   In another embodiment, each of the common upper sidewalls together with a sidewall of a corresponding source region form a sidewall of a contact opening. 
   In another embodiment, the FET includes a gate electrode recessed in each trench, a gate dielectric insulating the gate electrode from adjacent body regions, and a dielectric region extending in each trench over the gate electrode. 
   In another embodiment, the dielectric region has at least a portion that is fully contained within each trench, and sidewalls of the at least a portion of the dielectric region together with sidewalls of adjacent source regions form sidewalls of the contact openings. 
   In yet another embodiment, the dielectric region has at least a portion that: (a) is fully contained within each trench, and (b) defines upper portions of opposing sidewalls of the contact openings. 
   In yet another embodiment, the dielectric region has a portion that: (a) is fully contained within each trench, and (b) extends directly over at least a portion of an adjacent source region. 
   The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a cross-section view of a conventional trench MOSFET; 
       FIGS. 2A-2K  show cross-section views at different stages of manufacturing a trench MOSFET in accordance with an embodiment of the present invention; 
       FIG. 3  is a graph showing the effect of cell pitch reduction on Rds on ; 
       FIGS. 4A and 4B  show an alternate method for forming trenches in accordance with another embodiment of the invention; and 
       FIG. 5  is an exemplary cross-section view corresponding to that in  FIG. 2K , and is provided to show a more accurate representation of the contours of the trenches in accordance with one embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In accordance with the present invention, a structure and method for forming a trench MOSFET having self-aligned features which result in cell pitch reduction without increasing the process complexity are disclosed. In one embodiment, trenches are formed in an epitaxial layer in such manner that the trench sidewalls fan out near the top of the trench over source regions. An insulating layer formed along a top portion of each trench together with the source regions defines the contact openings between adjacent trenches for contacting the source and body regions. This structure and method of forming the trenches leads to a MOSFET which has source regions and contact openings self-aligned to the trenches. This in turn enables the 2D portion of the cell pitch of prior art MOSFET  100  ( FIG. 1 ) to be eliminated and the dimension B to be reduced to thus obtain a reduced cell pitch without introducing any process complexities 
     FIGS. 2A-2K  are cross-section views at different stages of manufacturing a trench MOSFET in accordance with an embodiment of the present invention. In  FIG. 2A , a lightly doped N-type epitaxial layer  204  extends over a highly-doped N-type substrate  202 . A layer of a material which is resistant to silicon etch having a thickness in the range of 2,000-10,000 Å is formed over epitaxial layer  204 . In one embodiment, an oxide layer having a thickness of about 5,000 Å is used. Using a masking step, predefined portions of the layer of material resistant to silicon etch are removed so that only regions  206  remain. In the embodiment wherein an oxide layer is used, conventional dry or wet etch may be used to remove the predefined portions of the oxide layer. 
   In  FIG. 2B , a first silicon etch is carried out to form a mid-section  208  of a plurality of trenches. The spacing between regions  206  defines the width of mid-section  208  which is in the range of 0.2-2.0 μm. Mid-section  208  extends from the exposed surface areas of epitaxial layer  204  to a depth in the range of 0.5-3.0 μm. In one embodiment, the width and depth of mid-section  208  are about 0.35 μm and 1.0 μm, respectively. Conventional methods for etching silicon, for example, reactive ion etching (REI), may be used to form mid-section  208  of the trenches. 
   In  FIG. 2C , portions of regions  206  are removed to expose additional surface areas  207  of epitaxial layer  204 . Smaller regions  206   a  having a thickness in the range of 1,000-9,000 Å thus remain. In the embodiment where regions  206  are from oxide, regions  206  are isotropically etched so that smaller oxide regions  206   a  having a thickness of about 2,500 Å remain. 
   In  FIG. 2D , a second silicon etch is carried out to remove portions of epitaxial layer  204  along its exposed surfaces to thereby form outer sections  208   b  of the trenches. As shown, mid-section  208   a  extends deeper than outer sections  208   b . Outer sections  208   b  extend from surface areas  208   b  of epitaxial layer  204  to a depth in the range of 0.1-1.0 μm. In one embodiment, the depth of outer sections  208   b  is about 0.4 μm. Note that the second silicon etch also removes silicon from along the bottom of the mid-section  208  though it is not necessary to do so. As with the first silicon etch, conventional methods for etching silicon, for example, reactive ion etching (REI), may be used for the second silicon etch. 
   While  FIGS. 2A-2D  show one method for forming trenches having a deep mid-section and shallow outer sections, the invention is not limited to this particular method. For example, an alternate method for forming trenches having similar physical characteristics is shown in  FIGS. 4A and 4B . After forming isolated regions  206  of for example oxide or photoresist, as in  FIG. 2A , an isotropic silicon etch is carried out so that openings  203  are created in epitaxial layer  204  between adjacent regions  206  as shown in  FIG. 4A . The isotropic etch removes silicon from under regions  206  as shown. Next, keeping regions  206  intact, a conventional silicon etch is carried out to form deeper mid-sections  203   a  of the trenches as shown in  FIG. 4B . As can be seen, each trench has a deep mid-section  203   a  and shallow outer sections  203   b  extending under regions  206 . 
   Referring back to  FIGS. 2A-2K , in  FIG. 2E , remaining regions  206   a  may optionally be removed at this stage of the process. An insulating layer  210  is then formed along the surface of epitaxial layer  204  using conventional methods. Sidewalls of the trenches are thus coated with insulating layer  210 . Insulating layer  210  has a thickness in the range of 50-1,000 Å. In one embodiment, insulating layer  210  is a gate oxide having a thickness of about 400 Å. 
   Next, using conventional polysilicon deposition techniques, a polysilicon layer  212  having a thickness in the range of 1,000-15,000 Å is deposited over insulating layer  210  to fill the trenches. In one embodiment, polysilicon layer  212  has a thickness of about 5,500 Å and is doped with impurities. In yet another embodiment, prior to forming polysilicon layer  212 , a thick insulating layer is formed along the bottom of the mid-section  208   a  of the trenches. This advantageously reduces the gate capacitance of the MOSFET. 
   In  FIG. 2F , polysilicon layer  212  is etched back to form gates  212   a  in mid-section  208   a  of the trenches. Polysilicon layer  212  is etched back such that its upper surface is recessed below the outer sections  208   b  of the trenches. This insures that no polysilicon is left in the outer sections  208   b  of the trenches which may otherwise short the gate to the source and also block the source and body implants carried out later in the process. However, the extent to which the polysilicon layer  212  is etched back must be carefully controlled to insure that at least a portion of the gate overlaps with the source regions formed in later steps. Conventional polysilicon etching techniques may be used to etch back polysilicon layer  212 . 
   P-type body regions  214  are then formed in epitaxial layer  204  between adjacent trenches by implanting P-type impurities such as boron. The P-type implant is symbolically shown by arrows  218  which indicate that no mask is needed. Body regions  214  extend into epitaxial layer  204  to a depth primarily dictated by the target channel length. Next, highly-doped N-type regions  216  are formed in body regions  214  by implanting N-type impurities such as arsenic or phosphorous. N-type regions  216  extend along the top surface of body regions  214  and directly below outer sections  208   b  of the trenches. The N-type implant is symbolically shown by arrows  219  which indicate that no masking is needed for this implant either. Conventional ion implantation techniques may be used for both implant steps. 
   In  FIG. 2G , a dielectric layer  220 , such as BPSG, is formed over the entire structure using conventional techniques. Dielectric layer  220  has a thickness in the range of 2,000-15,000 Å. In one embodiment, the thickness of dielectric layer  220  is about 8,000 Å. Next, a conventional dielectric flow step is carried out to obtain a planar surface as shown in  FIG. 2H . Dielectric layer  220   a  is then etched until silicon is reached as shown in  FIG. 2I . After the dielectric etch, dielectric regions  220   b  which are fully contained in the trenches remain while surface areas of N-type regions  216  are exposed. 
   In  FIG. 2J , a conventional silicon etch is carried out to form contact openings  222 . Sufficient amount of silicon is removed so that along with the upper portion of N-type regions  216  a top layer of body regions  214  is also removed. This insures that: (i) a top surface of body regions  214   a  becomes exposed so that contact can be made to body regions  214   a , (ii) of N-type region  216 , source regions  216   a  separated by body regions  214   a  remain, and (iii) sidewall areas of source regions  216   a  become exposed so that contact can be made to source regions  216   a . In  FIG. 2K , metal layer  226  is deposited to contact body regions  214   a  and source regions  216   a . Before metal  226  is deposited, a layer of heavily doped P-type region  224  may optionally be formed along the top surface of body regions  214   a  using conventional ion implantation techniques. The heavily doped region  224  helps achieve an ohmic contact between metal  226  and body region  214   a . As shown, metal layer  224  is insulated from gates  212   a  by the dielectric layer  220   b  extending along the top surface of each trench. 
   Referring back to  FIG. 2J , the silicon etch carried out to form contact openings  222  exposes portions of insulating layer  210  extending along the sidewalls of outer sections  208   b  of the trenches. As can be seen, the exposed portions of insulating layer  210  together with the exposed sidewall area of source regions  216   a  advantageously define contact openings  222  between adjacent trenches. Thus, with no masking steps used in forming either source regions  216   a  or contact openings  222 , source regions  216   a  and contact openings  222  which are self-aligned to the trenches are formed. 
   Because source regions  216   a  and contact openings  222  are self-aligned to the trenches, the need to account for contact misalignment as in conventional techniques (dimension D in  FIG. 1 ) is eliminated. Furthermore, the contact openings (dimension B in  FIG. 1 ) can be made smaller than the photolithography tools are typically configured to resolve. Thus, not only the 2D term is eliminated from the minimum cell pitch A+B+2C+2D of the conventional trench MOSFET in  FIG. 1 , but the term B can be made much smaller. For the same process technology, a much smaller cell pitch is therefore obtained without increasing the process complexity. 
   The small cell pitch results in an increase in the number of trenches per unit area which in turn has the desirable effect of lowering the Rds on . This is more clearly shown in  FIG. 3 .  FIG. 3  is a graph showing the effect of cell pitch reduction on Rds on . The vertical axis represents Rds on , and the horizontal axis represents the cell pitch. The numbers along the vertical axis are merely illustrative and do not reflect actual values of Rds on . Two curves are shown with the upper curve corresponding to a gate-source bias of 4.5V and the lower curve corresponding to a gate-source bias of 10V. For the same process technology, the self-aligned features of the present invention result in a reduction of the cell pitch from 1.8 μm to 1.0 μm. This cell pitch reduction results in about a 30% reduction in Rds on , in the case of 10V biasing and about a 25% reduction in the case of 4.5V biasing. 
   The cross-section views in  FIGS. 2A-2K  are merely illustrative and are not intended to limit the layout or other structural aspects of the cell array. Furthermore, these figures may not accurately reflect the actual shape of all the various regions as they would appear in an actual device.  FIG. 5  is an exemplary cross-section view corresponding to that in  FIG. 2K , and is provided to show a more accurate representation of the contours of the trenches in accordance with one embodiment of the invention. Because of the small dimensions of some of the regions and the effects of such processing steps as temperature cycles, a rounding of many of the corners occurs during processing. As a result, the trenches appear Y-shaped as shown in  FIG. 5  rather than T-shaped as shown in  FIG. 2K . However, it is to be understood that the invention is not limited to a particular shape of the trenches. 
   While the above is a complete description of the embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, the process steps depicted in  FIGS. 2A-2K  are for manufacturing an N-channel MOSFET. Modifying these process steps to obtain an equivalent P-channel MOSFET would be obvious to one skilled in the art in light of the above teachings. Similarly, modifying the process steps to obtain other types of semiconductor devices such as insulated gate bipolar transistor (IGBT) would be obvious to one skilled in the art in light of the above teachings. 
   Also, body region  214  ( FIG. 2F ) may be formed earlier in the processing sequence. For example, in  FIG. 2A , prior to forming regions  206 , P-type impurities may be implanted into epitaxial layer  204  or a P-type epitaxial layer may be grown over epitaxial layer  204 . Similarly, N-type regions  216  ( FIG. 2F ) may be formed earlier in the processing sequence. For example, a blanket implant of N-type impurities may be carried out to form a highly-doped N-type region in the body region before forming the trenches. The highly-doped N-type region however needs to extend deeper into the body region than that depicted in  FIG. 2F  so that after the trenches are formed, at least a portion of the N-type region extends below the outer sections of the trenches. Also, a deeper silicon etch would be required in  FIG. 2J  in order to reach a surface of the body region. 
   In a further variation, epitaxial layer  204  may have a graded doping concentration rather than a fixed doping concentration, or may be made of a number of epitaxial layers each having a different doping concentration, or may be eliminated all together depending on the design goals. Moreover, the trenches may extend clear through epitaxial layer  204  and terminate within substrate  202 . 
   Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.

Technology Classification (CPC): 8