Patent Abstract:
A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2013-0063000, filed on May 31, 2013, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, a semiconductor device and a method for fabricating the same having a buried gate electrode. 
         [0004]    2. Description of the Related Art 
         [0005]    In a conventional gate structure, a plurality of gates are formed on a substrate, and a landing plug contact is formed between the gates and is coupled to a source/drain. A storage node contact is formed on the landing plug contact and couples a capacitor to the substrate. 
         [0006]    Recently, as a semiconductor device has been minimized, a gate is not formed on a substrate, and a buried gate structure is proposed. That is, a gate is buried in a trench after forming the trench by etching the substrate. 
       SUMMARY 
       [0007]    Exemplary embodiments of the present invention are directed to a semiconductor device and a method for fabricating the same, which reduce an overlap area between a passing gate and an adjacent cell. 
         [0008]    Exemplary embodiments of the present invention are directed to a semiconductor device and a method for fabricating the same, which improve a row hammering and a gate induced drain leakage (GIDL). 
         [0009]    In accordance with an exemplary embodiment of the present invention, a semiconductor device includes a substrate including an element isolation region, a trench formed in the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on the gate electrode, wherein a pin is formed on the gate electrode between two adjacent active regions. 
         [0010]    In accordance with another exemplary embodiment of the present invention, a semiconductor device includes a substrate having an element isolation region, a trench formed in the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on the gate electrode, wherein the element isolation region is formed on the gate electrode and includes a pin formed on the gate electrode between two adjacent active regions. 
         [0011]    In accordance with still another exemplary embodiment of the present invention, a semiconductor device includes a substrate having an element isolation region, a first trench formed in the element isolation region, a first gate electrode buried in the first trench, a plurality of active regions formed on the first gate electrode, and a second trench formed in the element isolation region, in parallel with the first trench, and a second gate electrode buried in the second trench, wherein the element isolation region is formed on the first gate electrode between two adjacent active regions, and includes a pin formed protrudedly on a bottom surface of the first trench. 
         [0012]    In accordance with still another exemplary embodiment of the present invention, a semiconductor device includes a substrate having an element isolation region and an active region defined by the element isolation region; trenches formed on the active region and the element isolation region and a gate electrode buried in the trenches, wherein the trenches have a same depth on the active region and the element isolation region. 
         [0013]    In accordance with still another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes forming an element isolation region on a substrate, forming a trench having a pin by etching the element isolation region, and forming a gate electrode that buries the trench. 
         [0014]    Before the forming of the trench having the pin, the method further includes forming a hard mask pattern for blocking a region where a pin is formed. 
         [0015]    The gate electrode includes a first region having a first thickness and a second region having a second thickness thicker than the first thickness, and the first region is formed on the pin. 
         [0016]    In accordance with still another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes forming an element isolation region and a plurality of active regions defined by the element isolation region, on a substrate, forming a first trench having a pin by etching the element isolation region, forming a second trench having a planarized surface by etching the active regions, and forming a first gate electrode and a second gate electrode which bury the first trench and the second trench, respectively. 
         [0017]    Before the forming of the first trench, the method further includes forming a first hard mask pattern for blocking a region where the pin is partially formed on the element isolation region. 
         [0018]    In the forming of the first trench and the second trench, the first trench and the second trench are simultaneously formed using a single second mask pattern as an etching mask. 
         [0019]    The second hard mask pattern has a line shape. 
         [0020]    The first trench and the second trench have a same depth. 
         [0021]    The first gate electrode includes a first region having a first thickness and a second region having a second thickness thicker than the first thickness, and the first region is formed on the pin. 
         [0022]    The gate electrode includes a metal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. 
           [0024]      FIGS. 2A to 2F  are plane views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention. 
           [0025]      FIGS. 3A to 3F  are cross-sectional views illustrating a method for fabricating a semiconductor device, taken along A-A′ line shown in  FIGS. 2A to 2F . 
           [0026]      FIGS. 4A to 4F  are cross-sectional views illustrating a method for a fabricating a semiconductor device, taken along B-B′ line shown in  FIGS. 2A to 2F . 
           [0027]      FIG. 5  is a block diagram illustrating a memory card. 
           [0028]      FIG. 6  is a block diagram illustrating an electronic system. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, reference numerals correspond directly to the like numbered parts in the various figures and embodiments of the present invention. 
         [0030]    The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” means not only “directly on” but also “on” something with an intermediate feature(s) or a layer(s) therebetween, and that “over” means not only directly on top but also on top of something with an intermediate feature(s) or a layer(s) therebetween. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence. 
         [0031]    In general, a buried gate of a line type is formed to be expanded toward a short axis direction of an active region. A trench is formed on an element isolation layer of a buried gate region by a mask of a line type. Herein, in case of an element isolation layer having an etching line width relatively wider than that of the short axis direction of the active region, a trench deeper than the active region may be formed by a loading effect. 
         [0032]    A conducting material is buried in the trench formed on the element isolation layer during a buried gate forming process. A buried gate formed on the element isolation layer other than the active region is referred to as a passing gate. Herein, a bottom plane of the passing gate may be located lower than a bottom plane of the buried gate. 
         [0033]    An interference between a passing gate and a neighboring cell has an influence on a device performance. Especially, according to a change of a design rule, a distance between the passing gate and the neighboring cell is shortened, and according as a bottom plane of the passing gate is located lower than a bottom plane of the buried gate, an overlap area between the passing gate and the neighboring cell is increased. Thus, a gate induced drain leakage (GIDL) caused by a potential difference between the passing gate and a cell data is deteriorated, and a row hammering issue occurs. To solve this concern, embodiments of the present invention provide a semiconductor device and a method for fabricating the same which minimizes an Interference between a passing gate and a neighboring cell by forming a trench of the passing gate having a pin shape. 
         [0034]      FIG. 1  is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. 
         [0035]    As shown in  FIG. 1 , a plurality of active region  103  is defined by forming an element isolation region  102  on a substrate  101 . A trench  104  having a pin F is formed on the element isolation region  102 . The pin F is formed higher than a bottom plane of the trench  104 . The element isolation region  102  may include an insulating material. 
         [0036]    A buried gate electrode  105  is formed to be buried in the trench  104 . The buried gate electrode  105  may adjust an etching thickness to bury an entire surface of the trench  104  having the pin F. Although the buried gate electrode  105  is shown in  FIG. 1  to bury an upper portion of the substrate  101 , a surface of the buried gate electrode  105  may be formed lower than a surface of the substrate  101  excluding the buried gate region  105 . 
         [0037]    The buried gate electrode  105  may include a first region having a first thickness D1 and a second region having a second thickness D2 thicker than the first thickness D1 by the active region  103  and the pin F, and may be formed to have a bottom plane of an uneven shape having the first region and the second region. That is, a buried thickness of the buried gate electrode  105  on the pin F region, which is protruded higher than a bottom plane of the trench  104 , may be thinner than those of other regions. 
         [0038]    Since a buried thickness of the buried gate electrode  105  on the pin F region is decreased, an overlap area between the buried gate electrode  105  and a neighboring cell may be reduced during a post-process. Thus, a row hammering and a gate induced drain leakage (GIDL) are improved. 
         [0039]      FIGS. 2A to 2F  are plane views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.  FIGS. 3A to 3F  are cross-sectional views illustrating a method for a fabricating a semiconductor device, taken along A-A′ line shown in  FIGS. 2A to 2F .  FIGS. 4A to 4F  are cross-sectional views illustrating a method for a fabricating a semiconductor device, taken along B-B′ line shown in  FIGS. 2A to 2F . For the convenience of the descriptions,  FIGS. 2A to 2F ,  FIGS. 3A to 3F  and  FIGS. 4A to 4F  will be described together according to a process sequence. 
         [0040]    As shown in  FIGS. 2A ,  3 A and  4 A, a plurality of active regions  13  are defined by forming an element isolation region  12  on a substrate  11 . The substrate  11  may include a semiconductor substrate. The substrate  11  may include a silicon substrate, a silicon germanium substrate or a silicon-on-insulator (SOI) substrate. 
         [0041]    The element isolation region  12  may be formed by a shallow trench isolation (STI) process. A wall oxide, a liner and a gap-fill material are sequentially formed on the element isolation region  12 . The liner may include silicon nitride and silicon oxide. The silicon nitride may include Si 3 N 4 , and the silicon oxide may include SiO 2 . The gap-fill material may include silicon oxide such as a spin-on-dielectric (SOD). The gap-fill material may include silicon nitride. Herein, the silicon nitride may be gap-filled using the silicon nitride used as the liner. 
         [0042]    The active regions  13  defined by the element isolation region  12  may have a bar shape having a long axis and a short axis. In a long axis direction of the active regions  13 , the active regions  13  may be formed to have a uniform interval, and the element isolation region  12  between the active regions  13  may be formed to have a uniform interval. In a short axis direction of the active regions  13 , the active regions  13  may be formed to have an uniform interval, but the element isolation region  12  may be formed to have a narrow line width and a wide line width as shown in  FIG. 4A . A first element isolation region  12 A having the wide line width may be formed deeper than a second element isolation region  12 B having the narrow line width due to a loading effect caused by a line width difference during forming of the element isolation region  12 . That is, a trench may be formed to have a bottom plane of the first element isolation region  12 A lower than that of the second element isolation region  12 B. 
         [0043]    Subsequently, a first hard mask layer  14  is formed on the substrate  11  having the element isolation region  12 . The first hard mask layer  14  is used as an etch mask of the substrate  11  to form a buried gate in a post-process, and may be formed with a material having an etching selectivity. The first hard mask layer  14  may include an insulating material. 
         [0044]    Subsequently, a second hard mask pattern  15  is formed on the first hard mask layer  14 . The second hard mask pattern  15  is used in forming a pin on a passing gate, which is formed on the element isolation region  12 , and may be patterned using a mask process for blocking an area where the pin is to be formed. The second hard mask pattern  15  may be locally formed on, for example, only the area where the pin is to be formed during a subsequent trench process. More specifically, the second hard mask pattern  15  may be formed on an upper part of the element isolation region  12  between the active regions  13  in the long axis direction as shown in  FIG. 3A , and may be locally formed on a center of the first element isolation region  12 A in the short axis direction as shown in  FIG. 4A . 
         [0045]    The mask process for forming the second hard mask pattern  15  may be performed using a cut-mask for isolating the active regions of the line type. In case of the cut-mask, for example, only a local portion is opened to separate the active regions of the line type to have a bar shape. But, in case that the cut-mask is applied using a negative photoresist layer, a mask process for blocking a local portion may be performed. Since a region where the second hard mask pattern  15  is formed is overlapped with a cut-mask region, if a patterning is performed using the cut-mask, a process margin may be acquired without performing an additional mask process. 
         [0046]    The second hard mask pattern  15  may be formed with a same material as the first hard mask layer  14 . The second hard mask pattern  15  may include an Insulating material. For example, the insulating material may include silicon oxide. The silicon oxide may include tetra-ethyl-ortho-silicate (TEOS) oxide. 
         [0047]    As shown in  FIGS. 2B ,  3 B and  4 B, a planarization layer  16  is formed on the first hard mask layer  14  and the second hard mask layer  15 . The planarization layer  16  may work as an etching barrier of the first hard mask layer  14  and the second hard mask layer  15 , and may implement a subsequent patterning easily by reducing a height difference between the first hard mask layer  14  and the second hard mask layer  15 . Thus, a fluid membrane for reducing a height difference between the first hard mask layer  14  and the second hard mask layer  15 , may be applied as the planarization layer  16 . The planarization layer  16  may be formed with a material having an etching selectivity for the first hard mask layer  14  and the second hard mask layer  15 . The planarization layer  16  may be formed with a spin-on-carbon (SOC) layer or a spin-on-dielectric (SD) layer and the like. 
         [0048]    Next, a photoresist layer pattern  17  is formed on the planarization layer  16 . An anti-reflective layer may further formed on the planarization layer  16  before forming the photoresist layer pattern  17 . The photoresist layer pattern  17  of a line type may be formed to be extended toward to a short axis direction of the active region. The photoresist layer pattern  17  may be patterning with a line and spacer type, which defines a buried gate region. Since a cross sectional view of  FIG. 4B  shows a buried gate region, the photoresist layer pattern  17  is not shown in  FIG. 4B . 
         [0049]    As shown in  FIGS. 2C ,  3 C and  4 C, a planarization pattern  16 A is formed by etching the planarization layer  16  using the photoresist layer pattern  17 . 
         [0050]    In an etching process for forming the planarization layer pattern  16 A, the second hard mask pattern  15  is exposed firstly by the height difference between the first hard mask layer  14  and the second hard mask layer  15 , but remains without loss by the etching selectivity. That is, the first hard mask layer  14  and the second hard mask layer  15  work as an etching stop when the planarization layer pattern  16 A is formed. 
         [0051]    The planarization pattern  16 A is patterned to define the buried gate region of the line type extended toward the short direction of the active region  13  as same as the photoresist layer pattern  17 . Since a cross sectional view of  FIG. 4C  shows a buried gate region, the planarization layer  16  is etched, and the first hard mask layer  14  and the second hard mask layer  15  remain. 
         [0052]    As shown in  FIGS. 2D ,  3 D and  4 D, first trenches  18  and second trenches  19  are formed by etching the substrate  11 . The first and second trenches  18  and  19  provide a region where a buried gate is formed. As the first and second trenches  18  and  19  of a line type are formed to be extended toward the short axis direction of the active region, the first and second trenches  18  and  19  may be further formed on element isolation region. The first trench  18  of the active region may be formed to have a planarized surface, and the second trench  19  of the element isolation region  19  may be formed to have a pin F. 
         [0053]    As shown in  FIG. 3D , in a long axis direction of the active region  13 , the second trench  19  of the element isolation region may be prevented from being formed thicker than the first trench  18  of the active region by locally forming the second hard mask pattern  15  on an upper portion of the element isolation region  12  having a faster etching speed than an etching speed of the substrate  11  in an etching process for forming the trenches  18  and  19 . 
         [0054]    As shown in  FIG. 4D , the second trench  19  having the height difference by the second hard mask pattern  15  is formed on the buried gate region of the short direction of the active region  13 . Herein, the second trench  19  has the pin F, which may be protrudedly formed higher than a bottom of the second trench  19 . Moreover, an exposed region of the element isolation region  12  is adjusted by locally forming the second hard mask pattern  15 , and an etch loading effect may be prevented by forming the pin F. Thus, the second trench  19  having a same depth irrespective of a line width. 
         [0055]    As shown in  FIGS. 2E ,  3 E and  4 E, a conductive material  20  is buried in the first and second trenches  18  and  19 . A gate insulating layer (not shown) may be formed on a surface of the first and second trenches  18  and  19  before the conductive material  20  is formed. The conductive material  20  for forming the buried gate electrode may be formed with a metal containing layer. The metal containing layer may include titanium (Ti), tantalum (Ta), tungsten (W) or the like. The metal containing layer may include at least one selected from a group consisting of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN) and tungsten (W). 
         [0056]    For example, the conductive material  20  may include titanium nitride (TiN), tantalum nitride (TaN) or tungsten (W). The conductive material  20  may include a two-layer structure of TiN/W in which a tungsten (W) layer is stacked on a titanium nitride (TiN) layer or a two-layer structure of TaN/W in which a tungsten (W) layer is stacked on a tantalum nitride (TaN) layer. The conductive material  20  may include a two-layer structure of WN/W in which a tungsten (W) layer is stacked on a tungsten nitride (WN) layer, and may include a metal material having a low resistance. 
         [0057]    As shown in  FIGS. 2F ,  3 F and  4 F, a buried gate electrode  21  is formed by etching the conductive material  20 . The etching for forming the buried gate electrode  21  may be performed through an etch back process. 
         [0058]    The buried gate electrode  21  is recessed in the first trench  18  as shown in  FIG. 3F . A surface of the buried gate electrode  21  has a lower height than a surface of the substrate  11 . Meanwhile, as shown in  FIG. 4F , an etching thickness may be adjusted to bury an entire surface of the second trench  19  having the pin F on the buried gate region. The buried gate electrode  21  may be formed to have a bottom plane of an uneven shape including a first region and a second region. The first region have a first thickness D1 by the active region  13  and the pin F, and the second region have a second thickness D2 thicker than the first thickness D1. That is, a buried thickness of the buried gate electrode  21  may be formed thinner than those of other regions due to the pin F that is protruded higher than a bottom plane of the second trench  19 . 
         [0059]    Thus, since an overlap of the buried gate electrode  21  with a neighboring cell may be reduced during a post-process as the buried thickness of the buried gate electrode  21  is reduced, a row hammering and a gate induced drain leakage (GIDL) may be improved. 
         [0060]    During the post-process, a sealing layer (not shown) may be formed on the buried gate electrode  21 . The sealing layer may gap-fill the first and second trenches  18  and  19  on the buried gate electrode  21 . The sealing layer may perform an operation for protecting the buried gate electrode  21 . The sealing layer may include an insulator material. The sealing layer may include a silicon nitride. 
         [0061]      FIG. 5  is a block diagram illustrating a memory card. 
         [0062]    As shown in  FIG. 5 , a memory card  200  may include a controller  210  and a memory  220 . The controller  210  and the memory  220  may exchange electrical signals. To be specific, the memory  220  and the controller  210  may exchange a data in response to a command of the controller  210 . Thus, the memory card  200  may store the data in the memory  220  or output the data from the memory  220  to an external device. The memory  220  may include the semiconductor device having aforementioned patterns. The memory card  200  may be used as a data storage medium for diverse portable devices. For example, the memory card  200  may include a memory stick card, a smart media card (SM), a secure digital card (SD), a mini secure digital card (mini SD) or a multi media card (MMC). 
         [0063]      FIG. 6  is a block diagram illustrating an electronic system. 
         [0064]    As shown in  FIG. 6 , the electronic system  300  may include a processor  310 , an input/output device  330  and a chip  320 , which perform a data communication through a bus  340 . The processor  310  performs a program and controls the electronic system  300 . The input/output device  330  may be used in Inputting or outputting data to or from the electronic system  300 . The electronic system  300  may be coupled to an external device, such as a personal computer or a network, and exchange data with the external device by using the input/output device  330 . The chip  320  may store a code and data for the operation of the processor  310  and perform an operation applied by the processor  310 . For example, the chip  320  may include the semiconductor device having aforementioned patterns. The electronic system  300  may include diverse electronic control devices having the chip  320 . For example, the electronic system  500  may be used for mobile phones, MP3 players, navigators, solid-state disk (SSD), household appliances, or the like. 
         [0065]    Embodiments of the present invention may reduce an overlap of a buried gate with a neighboring cell by forming a trench having a pin to form the buried gate. Thus, embodiments of the present invention may improve a row hammering and a GIDL. 
         [0066]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Technology Classification (CPC): 7