Patent Abstract:
Disclosed herein is a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation of the arithmetic unit and the individual memory.

Full Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present invention contains subject matter related to Japanese Patent Application JP 2007-316938 filed in the Japan Patent Office on Dec. 7, 2007, the entire contents of which being incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor chip including a plurality of processing devices such as processor elements or the like. 
         [0004]    2. Description of the Related Art 
         [0005]    A semiconductor chip including a plurality of identical processor elements (Processing Elements: PE) is known. 
         [0006]    Each PE includes an arithmetic unit (core), an individual memory (LS: Local Storage) connected to the core on a one-to-one basis, and a communication unit (COM) for performing communication with another PE. 
         [0007]    Techniques of using the individual memory (LS) of an unused core between PEs, or lending and borrowing the LS of a core between PEs in such a semiconductor system are proposed (see “NGARC Forum 2007 Kyushu University, Memory Architecture of Next-Generation Multiprocessor,” for example). 
         [0008]    In addition, techniques of turning off power to the whole of a PE by a power gate (PG) are known (see Japanese Patent No. 3899092, for example). 
         [0009]      FIGS. 1A ,  1 B, and  1 C are diagrams showing an example of a configuration when the techniques of a power gate are applied to the proposed techniques of lending and borrowing the LS of a core between PEs. 
         [0010]    In the example of  FIG. 1 , two PEs, that is, a PE-a and a PE-b are connected to a power supply potential Vcc and configured such that an LS can be lent and borrowed between the PE-a and the PE-b. 
         [0011]    The PE-a includes a core  1   a,  an LS  2   a  of the core  1   a,  and a communication unit (COM)  3   a.  Then, the PE-a has a power control unit  4   a  formed by a power gate that is connected between the power supply terminal of the PE-a as a whole and the power supply potential Vcc and which can turn on and off the power supply line. 
         [0012]    The PE-b includes a core  1   b,  an LS  2   b  of the core  1   b,  and a communication unit (COM)  3   b.  Then, the PE-b has a power control unit  4   b  formed by a power gate that is connected between the power supply terminal of the PE-b as a whole and the power supply potential Vcc and which can turn on and off the power supply line. 
         [0013]    The communication unit  3   a  of the PE-a and the communication unit  3   b  of the PE-b are connected to each other. 
         [0014]    As shown in  FIG. 1A , when both of the PE-a and the PE-b are operated, the PE-a and the PE-b are both maintained in an on state (operating state) by the power control units  4   a  and  4   b.    
         [0015]    As shown in  FIG. 1B , when only the PE-a is operated, the PE-a is maintained in the on state (operating state) by the power control unit  4   a,  and the PE-b is maintained in an off state (non-operating state) by the power control unit  4   b.    
         [0016]    As shown in  FIG. 1C , when the PE-a operates and the PE-a uses the LS  2   b  of the PE-b, that is, the PE-a borrows the LS  2   b  of the PE-b (the PE-b lends the LS  2   b  to the PE-a), the PE-a and the PE-b are both maintained in the on state by the power control units  4   a  and  4   b.    
       SUMMARY OF THE INVENTION 
       [0017]    In the above-described techniques, however, when the PE-a operates and uses the LS  2   b  of the PE-b, even though the core  1   b  of the PE-b is not used, the PE-a and the PE-b are both maintained in the on state by the power control units  4   a  and  4   b,  and the core  1   b  is supplied with power. 
         [0018]    The constitution of  FIG. 1  consequently has a disadvantage of having difficulty in operating with a minimum necessary power consumption and wasting power. 
         [0019]    It is desirable to provide a semiconductor chip that can suppress unnecessary power consumption and operate with a minimum necessary power consumption. 
         [0020]    According to a first embodiment of the present invention, there is provided a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation of the arithmetic unit and the individual memory. 
         [0021]    Preferably, each of the processing devices has a communication unit enabling communication with another processing device, and the communication unit is controlled to be on when the individual memory is on, and is controlled to be off when the individual memory is off. 
         [0022]    Preferably, the control unit independently controls supply of power to the arithmetic unit and the individual memory. 
         [0023]    Preferably, the control unit independently controls supply of a clock to the arithmetic unit and the individual memory. 
         [0024]    Preferably, the individual memory is divided into a plurality of individual memories, and the control unit independently controls supply of power to the plurality of divided individual memories. 
         [0025]    Preferably, the individual memory is divided into a plurality of individual memories, and the control unit independently controls supply of a clock to the plurality of divided individual memories. 
         [0026]    Preferably, each of the processing devices has a communication unit enabling communication with another processing device, the communication unit is controlled to be on when the individual memory is on, and is controlled to be off when the individual memory is off, and the control unit includes a plurality of transistors connected between a power supply potential and respective power supply terminals of the arithmetic unit, the divided individual memories, and the communication unit, a gate of each of the plurality of transistors being supplied with a signal controlling turning on and off of the transistor, and a power gate control unit configured to independently control turning on and off of the plurality of transistors according to a control signal. 
         [0027]    Preferably, each of the processing devices has a communication unit enabling communication with another processing device, the communication unit is controlled to be on when the individual memory is on, and is controlled to be off when the individual memory is off, and the control unit includes a plurality of gates connected between a power supply potential and respective clock terminals of the arithmetic unit, the divided individual memories, and the communication unit, the plurality of gates each being supplied with a signal that controls passage of the clock, and a gate control unit configured to independently control the plurality of gates according to a control signal. 
         [0028]    According to a second embodiment of the present invention, there is provided a semiconductor chip including: a plurality of processing devices that can communicate with each other; a main processing device configured to supply each of the processing devices with a control signal for performing control according to a role allotted to each of the processing devices; and a bus for connecting the plurality of processing devices to an external part; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation involving power consumption of the arithmetic unit and the individual memory according to a control signal supplied by the main processing device. 
         [0029]    According to the embodiments of the present invention, each of the plurality of processing devices in the semiconductor chip has an individual memory connected to an arithmetic unit on a one-to-one basis. In each of the processing devices, turning on and off of operation involving power consumption of the arithmetic unit and the individual memory is controlled individually. 
         [0030]    According to the embodiments of the present invention, it is possible to suppress unnecessary power consumption, and perform operation with a minimum necessary power consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIGS. 1A ,  1 B, and  1 C are diagrams showing an example of a configuration when the techniques of a power gate are applied to the proposed techniques of lending and borrowing the LS of a core between PEs; 
           [0032]      FIGS. 2A ,  2 B, and  2 C are diagrams showing an outline of a basic configuration of a semiconductor chip according to an embodiment of the present invention; 
           [0033]      FIG. 3  is a diagram showing a general configuration of a semiconductor chip according to the present embodiment and a state of supply of a gate control signal to each PE; 
           [0034]      FIG. 4  is a chart of a procedure for determining the value of the gate control signal GCTL supplied from a main PE to each PE; 
           [0035]      FIG. 5  is a diagram showing an example of implementation of a power gate in each PE of the semiconductor chip according to the present embodiment; and 
           [0036]      FIG. 6  is a diagram showing an example of implementation of a clock gate in each PE of the semiconductor chip according to the present embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0037]    Preferred embodiments of the present invention will hereinafter be described with reference to the drawings. 
         [0038]      FIGS. 2A to 2C  are diagrams showing an outline of a basic configuration of a semiconductor chip according to an embodiment of the present invention. 
         [0039]    Description in the following will be made of a case of two PEs. A structure is supposed in which two PEs, that is, PE-a and PE-b are connected to each other by communication units (COM). 
         [0040]    The semiconductor chip  10  in  FIGS. 2A to 2C  is configured such that two PEs  11  (PE-a) and  12  (PE-b) can lend and borrow an LS (individual memory) to and from each other. 
         [0041]    The PE  11  (PE-a) includes a core  111 , an LS  112  of the core  111 , and a communication unit (COM)  113 . Then, the PE  11  (PE-a) has a power control unit  114  formed by a power gate that is connected between the power supply terminal TV of the core  111  in the PE  11  (PE-a) and a power supply potential Vcc and which can turn on and off the power supply line, and a power control unit  115  formed by a power gate that is connected between the power supply terminal TV of the LS  112  and the power supply potential Vcc and which can turn on and off the power supply line. 
         [0042]    Incidentally, the communication unit (COM)  113  is formed so as to be supplied with power by the LS  112  via a power line LP. Hence, when the power control unit  115  is on, the LS  112  and the communication unit (COM)  113  are supplied with power. When the power control unit  115  is off, on the other hand, the LS  112  and the communication unit (COM)  113  are not supplied with power. 
         [0043]    The PE  12  (PE-b) includes a core  121 , an LS  122  of the core  121 , and a communication unit (COM)  123 . Then, the PE  12  (PE-b) has a power control unit  124  formed by a power gate that is connected between the power supply terminal TV of the core  121  in the PE  12  (PE-b) and the power supply potential Vcc and which can turn on and off the power supply line, and a power control unit  125  formed by a power gate that is connected between the power supply terminal TV of the LS  122  and the power supply potential Vcc and which can turn on and off the power supply line. 
         [0044]    Incidentally, the communication unit (COM)  123  is formed so as to be supplied with power by the LS  122  via a power line LP. Hence, when the power control unit  125  is on, the LS  122  and the communication unit (COM)  123  are supplied with power. When the power control unit  125  is off, on the other hand, the LS  122  and the communication unit (COM)  123  are not supplied with power. 
         [0045]    The communication unit  113  of the PE  11  (PE-a) and the communication unit  123  of the PE  12  (PE-b) are connected to each other by a bus  13 . 
         [0046]    As shown in  FIG. 2A , when both of the PE  11  (PE-a) and the PE  12  (PE-b) are operated, all the elements of the core  111 , the LS  112 , and the communication unit  113  of the PE  11  (PE-a) and the core  121 , the LS  122 , and the communication unit  123  of the PE  12  (PE-b) are maintained in an on state by the power control units  114 ,  115 ,  124 , and  125 . 
         [0047]    As shown in  FIG. 2B , when only the PE  11  (PE-a) is operated, all the elements of the core  111 , the LS  112 , and the communication unit  113  of the PE  11  (PE-a) are maintained in an on state by the power control units  114  and  115 . On the other hand, all the elements of the core  121 , the LS  122 , and the communication unit  123  of the PE  12  (PE-b) are maintained in an off state by the power control units  124  and  125 . 
         [0048]    As shown in  FIG. 2C , in a case where the PE  11  (PE-a) operates and the PE  11  (PE-a) uses the LS  122  of the PE  12  (PE-b), that is, the PE  11  (PE-a) borrows the LS  122  of the PE  12  (PE-b) (the PE  12  (PE-b) lends the LS  122  to the PE  11  (PE-a)) when the capacity of the LS  112  of the PE  11  (PE-a) alone is not sufficient, for example, power control is performed as follows. 
         [0049]    All the elements of the core  111 , the LS  112 , and the communication unit  113  of the PE  11  (PE-a) are maintained in an on state by the power control units  114  and  115 . 
         [0050]    On the other hand, in the PE  12  (PE-b), the core  121  is maintained in an off state by the power control unit  124 , and the LS  122  and the communication unit  123  are maintained in an on state by the power control unit  125 . 
         [0051]    Thus, when an LS (individual memory) is lent and borrowed, power to the core not being operated can be turned off, whereby the power consumption of the part of the core can be reduced. Therefore operation with a minimum necessary power consumption is made possible. 
         [0052]    Incidentally, when a larger number of PEs are implemented, and also when an LS in a PE that is not made to perform arithmetic processing which PE is set as a memory common to each PE is used, power consumption can be lowered by not supplying power to the core of the PE whose LS is used. 
         [0053]    The above description has been made of a case where a core and an LS are subjected to on/off control independently of each other by a power gate. However, a core and an LS can be subjected to on/off control independently of each other by a clock gate, for example. 
         [0054]    Description will next be made of a general configuration of a semiconductor chip including a plurality of PEs having the configuration shown in  FIGS. 2A to 2C  and an example of supply of gate control signals. 
         [0055]      FIG. 3  is a diagram showing a general configuration of a semiconductor chip according to the present embodiment and a state of supply of a gate control signal to each PE. 
         [0056]    The semiconductor chip  20  includes a main PE (Main PE)  21 , a plurality of PEs (four PEs in  FIG. 3 )  11  (PE-a),  12  (PE-b),  13  (PE-c), and  14  (PE-d) that can lend and borrow an LS (individual memory), and an AXI (Advanced extensible Interface) bus  22 . 
         [0057]    Incidentally, in  FIG. 3 , the PEs that can lend and borrow an LS (individual memory) are identified by similar references to those of  FIGS. 2A to 2C  to facilitate understanding. 
         [0058]    In the semiconductor chip  20  of  FIG. 3 , the PEs  11  (PE-a),  12  (PE-b),  13  (PE-c), and  14  (PE-d) are supplied with respective gate control signals GCTL-a, GCTL-b, GCTL-c, and GCTL-d from the main PE  21 . 
         [0059]    The main PE  21  performs power control according to roles allotted to the respective PEs  11  (PE-a),  12  (PE-b),  13  (PE-c), and  14  (PE-d). 
         [0060]    The programs and data interfaces COMIO-a, COMIO-b, COMIO-c, and COMIO-d of the respective PEs  11  (PE-a),  12  (PE-b),  13  (PE-c), and  14  (PE-d) are connected to the AXI bus  22 , whereby a communication path of communication of the semiconductor chip  20  with an outside is secured. 
         [0061]      FIG. 4  is a chart of a procedure for determining the value of the gate control signal GCTL supplied from the main PE to each PE. 
         [0062]    This procedure may be performed by either of software control and hardware control, and can be implemented by a program in the main PE or the like. 
         [0063]    At a start of GCTL control, whether there is a request to stop the whole of the PEs is first determined (ST 1 ). When a result of the determination is Yes, a setting is made such that GCTL=0, and then the process is ended (ST 2 ). 
         [0064]    When it is determined in step ST 1  that the request is not a request to stop the whole of the PEs, the process proceeds to a next step to determine whether the request is a request to operate the whole of the PEs (ST 3 ). When a result of the determination is Yes, a setting is made such that GCTL=1, and then the process is ended (ST 4 ). 
         [0065]    When it is determined in step ST 3  that the request is not a request to operate the whole of the PEs, whether the request is a request to operate the whole of the LSs is determined (ST 5 ). When a result of the determination is Yes, a setting is made such that GCTL=2, and then the process is ended (ST 6 ). 
         [0066]    When it is determined in step ST 5  that the request is not a request to operate the whole of the LSs, the process proceeds to a next step to determine whether the request is a request to operate the LS 1 , the LS 2 , and the LS 3  (ST 7 ). When a result of the determination is Yes, a setting is made such that GCTL=3, and then the process is ended (ST 8 ). 
         [0067]    When it is determined in step ST 7  that the request is not a request to operate the LS 1 , the LS 2 , and the LS 3 , the process proceeds to a next step to determine whether the request is a request to operate the LS 1  and the LS 2  (ST 9 ). When a result of the determination is Yes, a setting is made such that GCTL=4, and then the process is ended (ST 10 ). 
         [0068]    When it is determined in step ST 9  that the request is not a request to operate the LS 1  and the LS 2 , the process proceeds to a next step, where a setting is made such that GCTL=5, and then the process is ended (ST 11 ). 
         [0069]    With the configuration and the procedure described above, when an LS area is enlarged or an LS is used as a memory shared between PEs, it is possible to turn off power or a clock to a core not used in a PE, rather than turning on and off power or a clock to the whole of the PEs. 
         [0070]    An example of implementation of a power gate and a clock gate in the present embodiment will be described below. 
         [0071]      FIG. 5  is a diagram showing an example of implementation of a power gate in each PE of the semiconductor chip according to the present embodiment. 
         [0072]    In  FIG. 5 , a PE is identified by reference numeral  200 . 
         [0073]    The PE  200  in  FIG. 5  includes a core  210 , an LS  220 , a communication unit  230 , and a power gate control unit  240 . 
         [0074]    In the example of  FIG. 5 , the LS  220  is divided into four banks  221 ,  222 ,  223 , and  224 . 
         [0075]    The communication unit  230  includes a communication unit core (COM CORE)  231 , a communication unit PE (COM PE)  232 , and a communication unit memory (COM MEMORY)  233 . 
         [0076]    The power gate control unit  240  includes a power gate control block (PGC block)  241  and p-channel MOS (PMOS) transistors  242  to  249  whose sources are connected to a power supply potential Vcc and whose drains are connected to the power supply terminal TV of the core  210 , the respective power supply terminals TV of the four banks  221 ,  222 ,  223 , and  224 , and the respective power supply terminals TV of the communication unit core (COM CORE)  231 , the communication unit PE (COM PE)  232 , and the communication unit memory (COM MEMORY)  233 , the core  210 , the banks  221 ,  222 ,  223 , and  224 , the communication unit core (COM CORE)  231 , the communication unit PE (COM PE)  232 , and the communication unit memory (COM MEMORY)  233  each being an element block. 
         [0077]    The gates of the PMOS transistors  242  to  249  are connected to respective gate control lines CTL 242  to CTL 249  of the PGC block  241 . 
         [0078]      FIG. 5  shows two interfaces for data of one PE. 
         [0079]    One interface is COMIO for loading/storing a program, transferring data before operation and after the operation, and the like. The other interface is GCTLIF for controlling the power gate. 
         [0080]    The PGC block  241  encodes an input signal (gate control signal) GCTL from GCTLIF to the PE  200 , and then supplies an on/off control signal to the gates of the PMOS transistors  242  to  249 , which turn on or off power supply to each block. 
         [0081]    In a case of the gate control signal GCTL=0 in the encoding process of the PGC block  241 , all gate control signals of the PGC block  241  are output at a high level, so that all the PMOS transistors  242  to  249  are turned off to stop power supply to all the blocks. 
         [0082]    In a case of the gate control signal GCTL=1, all the gate control signals of the PGC block  241  are output at a low level, so that all the PMOS transistors  242  to  249  are turned on to supply power to all the blocks. 
         [0083]    In a case of the gate control signal GCTL=2, the PMOS transistors  248 ,  249 ,  243  to  246  which control power to the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the banks  221  (Bank 1 ),  222  (Bank 2 ),  223  (Bank 3 ), and  224  (Bank 4 ) are turned on, and the PMOS transistors  242  and  247  which control power to the communication unit core (COM CORE)  231  and the core (CORE)  210  are turned off. Thus, the LSs of the banks  221  to  224  are usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0084]    In a case of the gate control signal GCTL=3, the PMOS transistors  248 ,  249 ,  243  to  245  which control power to the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the banks  221  (Bank 1 ),  222  (Bank 2 ), and  223  (Bank 3 ) are turned on, and the PMOS transistors  242 ,  247 , and  246  which control power to the communication unit core (COM CORE)  231 , the core (CORE)  210 , and the bank  224  (Bank 4 ) are turned off. Thus, the LSs of the banks  221  to  223  are usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0085]    In a case of the gate control signal GCTL=4, the PMOS transistors  248 ,  249 ,  243 , and  244  which control power to the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the banks  221  (Bank 1 ) and  222  (Bank 2 ) are turned on, and the PMOS transistors  242 ,  247 ,  245 , and  246  which control power to the communication unit core (COM CORE)  231 , the core (CORE)  210 , and the banks  223  (Bank 3 ) and  224  (Bank 4 ) are turned off. Thus, the LSs of the banks  221  and  222  are usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0086]    In a case of the gate control signal GCTL=5, the PMOS transistors  248 ,  249 , and  243  which control power to the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the bank  221  (Bank 1 ) are turned on, and the PMOS transistors  242 ,  247 , and  244  to  246  which control power to the communication unit core (COM CORE)  231 , the core (CORE)  210 , and the banks  222  (Bank 2 ),  223  (Bank 3 ), and  224  (Bank 4 ) are turned off. Thus, the LS of the bank  221  is usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0087]    An example of implementation of a clock gate will next be described. 
         [0088]      FIG. 6  is a diagram showing an example of implementation of a clock gate in each PE of the semiconductor chip according to the present embodiment. 
         [0089]    A PE  200 A in  FIG. 6  is different from the PE  200  in  FIG. 5  in that a clock gate control unit  250  is provided in place of the power gate control unit, a clock gate control block (CGC block)  251  is disposed in place of the PGC block  241 , and two-input AND gates  252  to  259  are arranged in place of the PMOS transistors  242  to  249 . The outputs of the AND gates  252  to  259  are respectively connected to the clock terminal TCK of a core  210 , the respective clock terminals TCK of four banks  221 ,  222 ,  223 , and  224 , and the respective clock terminals TCK of a communication unit core (COM CORE)  231 , a communication unit PE (COM PE)  232 , and a communication unit memory (COM MEMORY)  233 , the core  210 , the banks  221 ,  222 ,  223 , and  224 , the communication unit core (COM CORE)  231 , the communication unit PE (COM PE)  232 , and the communication unit memory (COM MEMORY)  233  each being an element block. 
         [0090]    The CGC block  251  encodes an input signal (gate control signal) GCTL from GCTLIF to the PE  200 A, and then supplies an on/off control signal to the gates of the AND gates  252  to  259 , which turn on or off supply of a clock CLK to each block. 
         [0091]    In a case of the gate control signal GCTL=0 in the encoding process of the CGC block  251 , all clock control signals of the CGC block  251  are output at a low level, so that the outputs of all the AND gates  252  to  259  are set to a low level to stop the clock supply to all the blocks. 
         [0092]    In a case of the gate control signal GCTL=1, all the clock control signals are output at a high level, so that the outputs of all the AND gates  252  to  259  pass the clock CLK as it is to supply the clock CLK to all the blocks. 
         [0093]    In a case of the gate control signal GCTL=2, inputs of the AND gates  258 ,  259 ,  253  to  256  which perform clock control on the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the banks  221  (Bank 1 ),  222  (Bank 2 ),  223  (Bank 3 ), and  224  (Bank 4 ) are set to a high level to supply the clock CLK, and inputs of the AND gates  252  and  257  which perform clock control on the communication unit core (COM CORE)  231  and the core (CORE)  210  are set to a low level to stop supplying the clock CLK. Thus, the LSs of the banks  221  to  224  are usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0094]    In a case of the gate control signal GCTL= 3 , the inputs of the AND gates  258 ,  259 ,  253  to  255  which perform clock control on the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the banks  221  (Bank 1 ),  222  (Bank 2 ), and  223  (Bank 3 ) are set to a high level to supply the clock CLK, and the inputs of the AND gates  252 ,  257 , and  256  which perform clock control on the communication unit core (COM CORE)  231 , the core (CORE)  210 , and the bank  224  (Bank 4 ) are set to a low level to stop supplying the clock CLK. Thus, the LSs of the banks  221  to  223  are usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0095]    In a case of the gate control signal GCTL=4, the inputs of the AND gates  258 ,  259 ,  253 , and  254  which perform clock control on the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the banks  221  (Bank 1 ) and  222  (Bank 2 ) are set to a high level to supply the clock CLK, and the inputs of the AND gates  252 ,  257 ,  255 , and  256  which perform clock control on the communication unit core (COM CORE)  231 , the core (CORE)  210 , and the banks  223  (Bank 3 ) and  224  (Bank 4 ) are set to a low level to stop supplying the clock CLK. Thus, the LSs of the banks  221  and  222  are usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0096]    In a case of the gate control signal GCTL=5, the inputs of the AND gates  258 ,  259 , and  253  which perform clock control on the communication unit PE (COM PE)  232 , the communication unit memory (COM MEMORY)  233 , and the bank  221  (Bank 1 ) are set to a high level to supply the clock CLK, and the inputs of the AND gates  252 ,  257 , and  254  to  256  which perform clock control on the communication unit core (COM CORE)  231 , the core (CORE)  210 , and the banks  222  (Bank 2 ),  223  (Bank 3 ), and  224  (Bank 4 ) are set to a low level to stop supplying the clock CLK. Thus, the LS of the bank  221  is usable, and unnecessary power to the core (CORE)  210  and the like is cut off. 
         [0097]    Because the semiconductor chip according to the present embodiment has the configuration as described above, the semiconductor chip according to the present embodiment can realize the following effects. 
         [0098]    Power to a core not being operated when an LS (individual memory) is lent and borrowed can be turned off, whereby the power consumption of the part of the core can be reduced. Therefore operation with a minimum necessary power consumption is made possible. 
         [0099]    Power control is performed on each of LSs divided in banks, whereby only a minimum of LSs are operated according to necessary LS size. Thus operation with a minimum necessary power consumption is made possible. 
         [0100]    It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Technology Classification (CPC): 8