Patent Abstract:
The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs.

Full Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits. 
       BACKGROUND 
       [0002]    A variety of techniques are used to stack packaged integrated circuits into a module. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. Both leaded and BGA (e.g., CSP) type packaged integrated circuits (ICs) have been stacked. Although array packaging has become widely adopted, leaded packages are still employed in large volumes in low cost applications such as, for example, flash memory, which typically is packaged in thin small outline packages otherwise known as TSOPs. 
         [0003]    When leaded packages such as TSOPs are stacked, a variety of techniques have been employed. In some cases, the leads alone of packaged circuits have been used to create the stack and interconnect its constituent elements. In other techniques, structural elements such as printed circuit boards (PCBs) are used to create the stack and interconnect the constituent elements. 
         [0004]    Circuit boards and rail-like structures in vertical orientations have been used for years to provide interconnection between stack elements. For example, in U.S. Pat. No. 5,514,907 to Moshayedi, a technique is described for creating a multi-chip module from surface-mount packaged memory chips. The devices are interconnected on their lead-emergent edges through printed circuit boards oriented vertically to a carrier or motherboard that is contacted by connective sites along the bottom of the edge-placed PCBs. The PCBs have internal connective rail-like structures or vias that interconnect selected leads of the upper and lower packaged memory chips. Japanese Patent Laid-open Publication No. Hei 6-77644 discloses vertical PCBs used as side boards to interconnect packaged circuit members of the stack. In U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack. Another technique for stacking leaded packaged ICs with carrier structures or interposers oriented along lead bearing sides of packaged devices such as TSOPs is disclosed by the present assignee, Staktek Group L.P., in U.S. Pat. No. 6,608,763 issued Aug. 19, 2003, to Burns et al., which is incorporated herein by reference for all purposes. 
         [0005]    Many of the previously cited and known techniques for using PCBs and similar interposer structures for stacking leaded packaged devices into modules have evolved to meet the increased connective complexity presented by, for example, stacking memory components that have two or more chip enables per packaged device. Connectivity complexities, however, can arise in any applications where there is a need to connect non-adjacent leads of the module ICs. In some cases, this evolution has included use of interposer designs that employ four metal-layer designs to implement the more complex connection strategies required by more complex devices. Size limitations and other factors applicable to packaged IC stacking, however, have led to complexities in via and connection strategies. For example, trace routing and other connective requirements for interposers or carrier structures used in many applications may require the use of buried vias and/or blind vias. In various applications, the micro vias are used for blind vias. The use of multi-layer PCBs with buried vias and blind vias to address complex routing and other connective demands, however, increases costs and may present quality issues due to tight tolerances required. 
         [0006]    What is needed, therefore, is a new system and method for stacking leaded packaged devices that accommodates interconnection between the constituent ICs of a multi-package stacked module without use of an interposer or carrier structure but yet can implement more complex connection strategies. 
       SUMMARY 
       [0007]    The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the body of one or more leaded packaged ICs bears circuitry to provide stacking-related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs. In a preferred two-IC stack embodiment, at least some connections between respective upper and lower ICs are implemented by interconnection of respective leads of the upper and lower stack ICs while stacking-related connections are implemented with the circuitry borne by the body of the upper one of the ICs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  depicts an exemplar circuit module in accordance with an embodiment illustrating exemplar circuitry borne by the body of the upper leaded packaged IC. 
           [0009]      FIG. 2  depicts a plan view of the stack depicted in  FIG. 1  further illustrating, the circuitry borne by the body of the upper IC. 
           [0010]      FIG. 3A  depicts a side view of a portion of an exemplar stack in accordance with an embodiment. 
           [0011]      FIG. 3B  depicts a side view of a portion of an exemplar stack in accordance with an alternative embodiment. 
           [0012]      FIG. 4  is an enlarged perspective view of an exemplar stack illustrating circuitry borne by the body of the upper IC to implement selective stacking related connections. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]      FIG. 1  depicts an exemplar circuit module  5  in accordance with an embodiment illustrating exemplar circuitry borne by the body of the upper leaded packaged IC. As shown, module  5  employs circuitry  25  shown within the dotted line circle that implements electrical connections devised to allow selective enablement of upper and lower ICs  20  and  10 , respectively. 
         [0014]    Each of ICs  10  and  20  are, in the described preferred embodiment, encapsulated memory circuits disposed in thin small outline packages known as TSOPs. Each of the constituent ICs of the depicted exemplar module  5  exhibit IC bodies  12 , while upper IC  20  exhibits leads  22  and lower IC  10  exhibits leads  24 . In the depicted embodiment of stacked module  5 , as shown in further detail in later FIGS., leads  22  of upper IC  20  differ from leads  24  of lower IC  10  in that leads  22  of upper IC  20  extend down from the upper IC  20  to lower IC  10  at certain respective lead positions along edges or sides  27   1  and  27   2  of module  5 . Those of skill will recognize that techniques other than direct lead-to-lead connection may be employed to effectuate the connections illustrated as direct lead-to-lead connection shown in the embodiment shown in  FIG. 1 . For example, but less frequently, a carrier structure or interposer such as those depicted in U.S. patent application Ser. No. 11/452,531, filed Jun. 14, 2006 or U.S. patent application Ser. No. 11/452,532, filed Jun. 14, 2006 (both of which being assigned to Staktek Group L.P.) may be employed to provide the direct lead-to-lead connections between respective ICs of module  5  but typically, there are efficiencies in direct lead-to-lead connection between selective corresponding leads as illustrated which, when used with circuitry  25 , provide connective circuitry to implement a stacked module. As those of skill will recognize, leads are sometimes referred to as pins. 
         [0015]    Other package types may be used with the present invention as well as packaged circuits other than memories but, as described here with examples, many embodiments will be implemented with memories in TSOP packaging. Flash memory circuits implemented in TSOP packaging are one type of preferred constituent ICs  10  and  20 . In the illustrated embodiment, there is no gap between IC  10  and IC  20 , but embodiments may exhibit an air gap between constituent ICs or, alternatively, a heat transference material or adhesive between the ICs. The employed adhesive may be thermally conductive. 
         [0016]      FIG. 2  depicts a plan view of the stack depicted in  FIG. 1  further illustrating circuitry  25  borne by body  12  of upper IC  20 . Body  12  is typically but not always, plastic. Circuitry  25  is typically comprised of plural traces  31  that provide stacking-related connections between upper IC  20  and lower IC  10 . Stacking-related connections can include, for example, selective enablement so that only one of the constituent ICs of a circuit module  5  is enabled at a time. 
         [0017]    Circuitry  25  may be implemented in a variety of ways including, as a non-limiting example, printing conductive traces  31  with a conductive ink that is preferably curable. Other exemplar alternative constructions for traces  31  may include dispensable conductive materials, for example, such as conductive particles suspended in an adhesive, a conductive ink, or conductive epoxy. Solder paste is one type of such conductive material that could be used for traces  31 . Conductive traces  31  may also be devised with a conductive pattern that is constructed on a release liner, laminated or transferred to the body of the IC and then the release liner pulled away. In any case, traces are typically to be borne by the surface of body  12  of IC  20 . Exemplar conductive traces that are borne by the surface  28  of an IC are identified in the Figs as  31 A while traces that reside in channels or grooves imposed in body  12  will be identified as traces  31 B. Later  FIG. 3A  illustrates traces  31 A that reside on the surface  28  of body  12 . As another example, circuitry  25  may also be implemented with conductive traces that are plated conductive material residing either on the surface  28  of body  12 , or in etched channels or grooves  29  imposed with, for example, a laser.  FIG. 3B  illustrates an example of circuitry  25  implemented with traces  31 B implemented as plated conductive material residing in channels  29  disposed in body  12  of IC  20 . 
         [0018]      FIGS. 3A and 3B  depict in more detail leads  24  and  22 . Plural leads emerge from peripheral walls, sides or edges  27  of ICs  20  and  10 . Leads may emerge from one or more sides of the leaded packaged ICs. Leads  22  of IC  20  emergent from peripheral side  27   1  of upper IC  20  have a long transit section  30  that brings lead  22  into proximity with lead  24  to allow electrical contact between the respective leads that may be realized with solder or other connective  32 . As another example, the leads may be welded together. Illustrated lead  24  of lower IC  10  is shown as having foot  34 , shoulder  36  and transit section  30 . In practice, leads  22  and  24  and, in particular, transit sections  30 , are surfaces from which heat from the internal chip(s) of the respective TSOPs may be dissipated. Shoulder  36  of lead  24  can extend from and include the planar part of lead  24  emergent from peripheral wall  27  to the end of the curvature into transit section  30 . Transit section  30  is often a substantially straight path but may exhibit curvature. As leads  24  emerge from the package periphery  27 , a supportive shelf or plane is created or defined by the heads of the plurality of leads on a side. These features of leads  24  are present in conventional TSOP packaged memory circuits such as flash memory available from major suppliers of packaged memories. Foot  34  is provided to allow the mounting of the IC on a mounting field provided typically by a printed circuit or other signal transit board. Surface mount soldering techniques or other methods known in the art may be employed to make such connections. Those of skill will recognize that various combinations of lead features may be present in different packaged ICs that may be deployed in embodiments of the present invention. 
         [0019]      FIG. 4  is an exemplar enlarged depiction of a portion of a circuit module  5  in accordance with an embodiment. Circuitry  25  (within the dotted line circle) consists of exemplar traces  31 A and  31 B that participate in connections that participate in realization of selective connection between a mounting field exemplified by contacts MF 1 -MFn shown below feet  34  of leads  24  of lower IC  10  and selected enable or other functional pins of upper IC  20 . The illustration of  FIG. 4  depicts two of many available alternatives for disposing traces to be borne by body  12  of an IC. Trace  31 A exemplifies traces that reside on the surface  28  of body  12  of IC  20  (e.g., as conductive ink) and trace  31 B exemplifies traces that reside in channels  29  disposed onto surface  28  of body  12  of IC  20 . Both types of traces are shown in  FIG. 4  merely to illustrate a few of the modes available to implement traces borne by body  12  of the IC but, in practice, typical traces in a circuit module  5  will all be implemented alike. 
         [0020]    Following is a description of an exemplar connection in which trace  31 B 1  participates. MF 1  is a contact pad in a mounting field MF to which module  5  is connected. MF may be, for example, on a motherboard. MF 1  is connected to lead  24   1  (through the foot of that lead  24   1 ). Lead  24   1  is connected to lead  22   1  which is connected to trace  31 B 1  that is borne by body  12  of IC  20  and extends about to lead  24 E 1 . Thus, if site MF 1  is the source for an enable signal and leads  22   1  and  24   1  are in a N/C position on ICs  20  and  10 , respectively, and lead  24 E 1  is an enable pin for IC  20 , persons of skill will understand that IC  20  can be enabled by a signal applied to MF 1 . Those of skill will notice that lead  24 E 1  has been truncated or clipped to avoid connection with the corresponding lead  24  of IC  10  because the enable signal conveyed through trace  31 B 1  is devised to enable IC  20  while leaving IC  10  unaffected. No carrier structure or interposer was required to selectively enable IC  20 . Another exemplar connection identified between MF 2  and  24 E 2  is realized through trace  31 A 1  as shown. Provision of multiple such connective paths such as the example of one such path as illustrated between MF 1  and  24 E 1  illustrate the flexibility of the embodiments through which realization of a variety of intra-stack and/or stacking related connections in circuit module  5  can be implemented. 
         [0021]    Although the present invention has been described in detail, it will be apparent that those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Technology Classification (CPC): 7