Patent Abstract:
A method and apparatus by which ATSC-receiver-compatible digital TV signals may be generated without most of the discrete and/or high-complexity components required by the ATSC specification, through the use of a precomputation of digital filter coefficients that consolidates multiple functions into a single step, and through the derivation of multiple required carrier frequencies using a single oscillator circuit. The resulting design meets all requirements of the ATSC specification, reducing significantly the cost of the necessary signal-processing functions, and in a manner compatible with the VLSI (very-large-scale-integrated) circuit technologies of the field.

Full Description:
FIELD OF THE INVENTION 
       [0001]    This invention concerns electronic circuits, more specifically electronic circuits used in the processing of digital television signal processing. 
       BACKGROUND OF THE INVENTION 
       [0002]    ATSC (Advanced Television Standards Committee) Digital TV, as mandated for broadcast use by the FCC, requires specialized signal processing in the television receiver modulator which is not amenable to low-cost implementation in consumer electronics. This requirement has so far prevented the introduction of low-cost modulators in digital television products to provide the same functionality as the ubiquitous NTSC (National Television Standards Committee) modulators in analog NTSC TV products. 
         [0003]    The technology of advanced television systems using digital television signal processing, including the processing of high-definition television (HDTV) signals for consumer broadcast, reception, and presentation, incorporates many advanced signal-processing concepts, methods, and devices. The field&#39;s technology addresses the general problem of transmitting high-definition and rapid-motion video streams via both wireless and other modes of communication to large numbers of users concurrently at reasonable cost. The standards for advanced television systems are published by the Advanced Television Standards Committee (ATSC), and are available at www.atsc.org/standards.html. The ATSC standard of particular interest with respect to the present invention is the ATSC Digital Television Standard A/53, incorporated herein by reference. 
         [0004]    Also of particular relevance to the present invention is the MPEG-2 standard used to encode moving pictures and associated audio information. The MPEG-2 standard is in continuous evolution—copies of the standard, identified as ISO/IEC 13818, may be purchased at the International Standards Organization (ISO) at the ISO Website: www.iso.org/iso/iso_catalogue/, also incorporated herein by reference. 
         [0005]    As defined by the ATSC standard in the present art, the modulation of the MPEG-2 transport stream carrying the information for the viewer is performed using an 8-VSB (8-bit vestigial sideband) modulator. The 8-VSB modulator converts the MPEG-2 stream into a radio-frequency signal to be broadcast or otherwise conveyed to the user&#39;s receiver for demodulation, decoding, and presentation as images and sound. An informative article on the 8-VSB modulation process is titled “What Exactly is 8-VSB Anyway?”, by David Sparano, available on the Web at http://www.broadcast.net/˜sbe1/8vsb/8vsb.htm and incorporated herein by reference. 
         [0006]    The modulation process as described by ATSC Standard: Digital Television Standard (A/53), Revision D, 19 Jul. 2005 consists of the following steps:
       1. The MPEG-2 transport stream is processed as described in the standard cited hereinabove and applied to an 8-VSB modulator. In the present art, the digital processing required prior to the 8-VSB modulator is readily accomplished by integrated circuits and does not create a significant cost or complexity problem.   2. The resulting channel stream applied to the S-VSB modulator is post-filtered by a raised-cosine-squared Nyquist filter to confine the signal to the allocated 6 MHz-wide channel, and to form a matched filter in combination with the second raised-cosine-squared filter in the television receiver. Because of the severe restrictions placed by the FCC on radiation in adjacent channels this filtering is sophisticated, and is typically done at low intermediate frequencies (IFs) such as 45 MHz, where thermal drift of the components is not a problem in maintaining the exacting filter profile.   3. The resulting IF ATSC signal must then be frequency-converted to the desired channel, and the resulting undesired image mixing product suppressed by filtering where it falls in the TV band(s), either directly or by subsequent conversions.   4. Allowing the modulator to be channel-agile, meaning that the modulator can process signals acceptably and uniformly for output on any channel, normally requires additional complexity, typically by conversion of the IF ATSC signal first to a 2 nd  high IF above the TV bands, so that a second conversion to a selectable final channel may be done using a low-pass filter to suppress 2 nd  IF feed-through   5. The pilot carrier frequency in the final channel is initially positioned to center the signal&#39;s upper sideband in the 6-MHz channel, and may be modified by exacting offsets under certain conditions of adjacent or co-channel usage. This combination of precision and agility requires elaborate frequency synthesis.       
 
         [0012]    The modulator constructed in accordance with the above steps is both too large and too expensive to replace NTSC modulators in consumer equipment as it is migrated to support ATSC digital TV. 
         [0013]    For additional background, two articles, one titled “A Compatible Narrowband 8VSB Transmission System”, published by Axcera of Lawrence, Pa., available at http://broadcast.axcera.com/bet_paper.pdf, and the other titled “Architecture of a DSP Based Dual-Mode ATSC/NTSC Television Exciter and Transmitter”, by David L. Hershberger, Continental Electronics, Inc., available at http://www.contelec.com/pdf%5Cdspdtv.pdf, are incorporated herein by reference. 
         [0014]    A good general reference on digital signal processing is the book titled “Understanding Digital Signal Processing” by Richard G. Lyons, Addison Wesley Longman 1997, ISBN 0-201-63467-8. 
       SUMMARY 
       [0015]    The invention provides a method and apparatus by which ATSC-receiver-compatible digital TV signals may be generated without most of the discrete and/or high-complexity components required by the ATSC specification. The invention achieves its unique simplifications both through a precomputation of digital filter coefficients that consolidates multiple functions into a single step, and through the derivation of multiple required carrier frequencies using a single oscillator circuit. The invention accomplishes its purpose in a manner that is capable of meeting all requirements of the ATSC specification, while reducing significantly the cost of the necessary signal-processing functions, and in a manner compatible with the VLSI (very-large-scale-integrated) circuit technologies of the field. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The present invention is disclosed with reference to the accompanying drawings, wherein: 
           [0017]      FIG. 1  summarizes the processing of the MPEG-2 video stream, from the trellis encoding stage to the digital-to-analog conversion stage, according to the present art. 
           [0018]      FIG. 2  summarizes the processing of the MPEG-2 video stream through the same stages as in  FIG. 1  according to the invention. 
           [0019]      FIG. 3  shows the invention&#39;s use of a single crystal oscillator circuit to derive multiple carrier and timing frequencies. 
           [0020]      FIG. 4  shows the invention&#39;s use of the radio-frequency spectrum. 
           [0021]      FIG. 5  summarizes the structure and data flow of the invention&#39;s finite-impulse-response (FIR) filter. 
           [0022]      FIG. 6  shows the component structure of one stage of the FIR filter of  FIG. 5  using a separate ROM unit for each shift register. 
           [0023]      FIG. 6A  shows the component structure of one stage of the FIR filter of  FIG. 5  using a shared ROM for each pair of shift registers having the same stored coefficient values. 
           [0024]      FIG. 7  shows the simplified block structure of one stage of the FIR filter of  FIG. 5 . 
           [0025]      FIG. 8  shows the invention&#39;s FIR filter tap coefficient ROM storage and addressing. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    The architecture described by the requirements of the prior art has raised cost and complexity issues that impede the inclusion of ATSC-standard television modulators in consumer electronics. The present invention mitigates these problems through the construction of a simplified modulator more suited to the limited space and cost objectives of consumer electronics while providing the following functions.
       1. selects the UHF television channel range of desired for the signal output,   2. uses carefully-placed IF (intermediate frequency) carrier and LO (local oscillator) frequencies,   3. uses the Weaver modulator architecture to fold the signal during processing,   4. eliminates the use of D-to-A (digital-to-analog) trellis encoders followed by a conventional balanced modulator normally required by the Weaver modulator,   5. tunes the finite impulse response (FIR) filter ROM tap values for improved output D-to-A dynamic range utilization,   6. uses a single crystal oscillator to derive reference frequencies that are sufficiently high to facilitate spurious filtering and provide acceptable phase noise characteristics.       
 
         [0033]    Most agile consumer NTSC modulators provide output on UHF channels, and most ATSC broadcasts are on UHF. Furthermore, the FCC has announced that UHF channels  52  and above are being reassigned to other services. UHF channels  14 - 51  are uniformly spaced 6 MHz apart. The invention therefore provides for the processing of agile ATSC output in the UHF channel  14 - 51  range, which offers the highest flexibility with lowest complexity. The resulting output frequency band is then 470-698 MHz. 
         [0034]    Since the output band is substantially less than one octave, and since it is desirable that no IF or LO harmonics should appear in the output band, the invention places the fixed IF below the output band, but above half the frequency of the bottom of the output band (470 MHz), and places the LO frequency above the output band. 
         [0035]    In an optimized embodiment, the invention places the IF geometrically approximately the same ratio below the output band as the lowest LO frequency is above the output band, thereby allowing similar geometric cutoff rates for the upper and lower slopes of the output bandpass filter. This optimization also allows the shared use of a base oscillator frequency for both IF and LO generation, simplifying the invention&#39;s implementation. See  FIG. 4 . The invention uses a local oscillator (LO) frequency which is a multiple of 6 MHz, simplifying the synthesis of frequencies in 6 MHz steps to match the spacing of the UHF channels. On the basis of this usage, the invention derives a nominal IF frequency of 382-388 MHz and a nominal LO frequency of 858-1080 MHz, placing the lowest output frequency at 1.21 times the highest IF frequency, and the lowest LO frequency at 1.23 times the highest output frequency, i.e. approximately equal ratios. The invention also provides for adjustment of the IF and LO frequencies in 6 MHz increments or some submultiple thereof thereby simplifying the design of the bandpass filter noted above, and allowing optimum positioning of the undesired IF and LO signals on its rejection slopes. 
         [0036]    The Weaver modulator used in the present invention is a modulator design and implementation that uses low-pass filters and quadrature mixers to eliminate one sideband of the incoming signal to create a vestigial-sideband (VSB) output signal at a specific baseband center frequency. 
         [0037]    To reduce cost and complexity, the invention incorporates the Weaver modulator architecture to fold the signal around its baseband center frequency, while producing I and Q (In-phase and Quadrature) versions of the half-baseband signals, which when low-pass filtered may then be quadrature recombined to produce a single-sideband signal with the original baseband content in its one sideband. This technique allows a single low-pass filter to shape both the upper and low edges of the baseband, providing the symmetry desired in the ATSC signal spectrum, and control of emissions in the adjacent channels. In contrast to the prior art, the invention eliminates the use of a separate D-to-A trellis modulator followed by a balanced modulator, conventionally employed with Weaver modulation. 
         [0038]    See  FIG. 1 . In the conventional implementation, the 3-bit digital input  4  from Reed-Solomon encoding and pseudorandomization would be converted 5 to an 8-bit trellis code, and a DC offset added 6 to insert the desired amount of carrier signal. The resulting signal would then be processed  7  by a balanced modulator followed by an FIR (finite impulse response) digital filter, producing a low-pass-filtered quadrature baseband signal. The baseband signal would then be applied 8 to a second set of balanced modulators, and the result processed  9  through digital-to-analog conversion, resulting in a band-passed single-sideband (SSB) signal including quadrature as required 10. The trellis coding, carrier insertion, balanced modulation, filtering, and second balanced modulation comprise five separate stages of processing. The present invention combines four of the five stages into a single stage, thereby simplifying and accelerating the processing of the signal. 
         [0039]    To combine the processing steps, the invention precomputes all values required for all of the four processing steps, and uses the precomputed values as FIR filter coefficients in a single filtering processing step that accomplishes all the processing of the Weaver modulator. See  FIG. 2 . In summary, the invention accomplishes the following objectives:
       1. The invention precomputes the trellis magnitude  100  required for each FIR step, multiplying the trellis magnitude after addition of the desired carrier insertion offset by the desired FIR tap weights, and using the products as 3-bit address normalized tap weights in the FIR ROMs. This precomputation eliminates the need for the D-to-A trellis coding.   2. During processing, the invention duplicates the effects of using balanced modulators, i.e., reversal of the modulation waveform polarity, by reversing the binary value of each FIR tap when required. This has the same effect as if the input had been reversed in polarity. The invention accomplished this effect by applying an XOR (exclusive-OR) bitwise operation to the FIR ROM ones-complement output under control of a phase signal at the balanced modulator carrier frequency, causing the binary value of each FIR tap to reverse at that rate. This simple reuse of the binary FIR tap values eliminates the separate modulation step ordinarily required to provide balanced modulator output.   3. The invention further scales  104  the FIR ROM tap values during precomputation so that the highest total value reached on the largest step is just at the full scale of the D-to-A conversion, thereby utilizing the converter to its full capacity, and maximum dynamic range.   4. The invention extends  105  the FIR ROM taps in bit depth at the LSB (least-significant-byte) end of the ROM addresses, so that the final summation arriving at the D-to-A converter is accurate to within one LSB-range of addresses in the D-to-A converter.       
 
         [0044]    In a preferred embodiment, the invention precomputes the FIR filter tap values, and computes filter outputs usable in the D-to-A stage, through the following steps, as shown in  FIG. 2 : 
         [0045]    1. Select a digital representation that can produce the negative of a value using a simple exclusive-or (XOR) operation. The ones-complement representation is an example of such a representation. 
         [0046]    2. The required trellis encoding uses eight levels having the values −7, −5, −3, −1, +1, +3, +5, +7, and the required pilot carrier insertion level is +1.25 units relative to the trellis code insertion scale. Map the trellis code values summed with the pilot carrier insertion level to produce a new trellis having the values −5.75, −3.75, −1.75, +0.25, +2.25, +4.24, +6.25, +8.25. The new trellis code values map to a 7-bit signed value with the least-significant bit (LSB) signifying 0.25 (2 −2 ) and the most-significant bit (MSB) signifying 8 (2 3 ), giving 6 bits of value plus a sign bit. Since there are still only eight unique trellis levels, the 7-bit signed value can still be represented as a 3-bit ROM input. 
         [0047]    3. Determine  102  the coefficients (tap values) of a suitable FIR filter. The ATSC requirements specify target filter responses for the passband, transition band, and stopband of the signal being filtered. The determination of suitable FIR filter coefficients is a process well-known in the art, which will produce the desired filter coefficients and resultant response characteristics. Using the coefficients produced and a peak signal level, compute  103  the step-by-step processing weights for the peak signal level (+8.25) from the trellis values of the previous step. 
         [0048]    4. Normalize  104  the filter coefficients so that the maximum computed  103  input level times the filter coefficient summation will be the maximum signed input value usable in the D-to-A conversion process, i.e., (0FFFF . . . ), thereby utilizing fully the dynamic range of the D-to-A converter. 
         [0049]    5. Determine  105  the number of bits required to maximize the spectral purity of the processed signal as follows. First, assume that each coefficient reaches a rounded-high level, so that every result is rounded upwards. The result is that the output level would be too high by an error factor of the integer equal to the number of coefficients divided by 2, or for the case of 31 coefficients, 16 (=2 4 ), requiring 4 bits. But adding one bit to the coefficient size, making 5 added bits, produces correctly-rounded results using simple truncation. Given the 7-bit trellis and the 5-bit addition, the coefficients therefore require 12 bits during processing, which may be truncated to 8 bits after final summation. 
         [0050]    6. There are only 3 bits of input to the FIR filter, not including the carrier phase input. Consequently, store  106  the 12-bit coefficients, indexed by the 8 trellis values, in a lookup read-only memory (ROM) having a 3-bit lookup input. 
         [0051]    7. The FIR filter coefficients have values symmetrical around the center of the filter, so that given an odd number N of filter taps, the n th  filter tap and the (N−n+1) th  filter tap have the same values in the filter ROM. This characteristic of the FIR filter optionally permits use of the same ROM unit twice: once for stage n and once for stage N−n+1, during processing in a single step, if the hardware required to look up and hold two input values is less burdensome than duplication of the ROM. See  FIG. 6A  for a single-ROM embodiment of the invention. 
         [0052]    8. In digital signal processing in the present invention, the production of a balanced modulator signal requires only a phase reversal of the filter output. The carrier phase input signal is used to trigger the computation of filter stage output using the XOR (e.g., twos-complement) of the ROM output value, thereby producing a negated output value. 
         [0053]    9. At the carrier frequency, the trellis step durations equal 90 degrees of phase at the balanced modulator carrier frequency. Thus the trellis level is the same for both I and Q, with a relative delay of 90 degrees of carrier phase. Accordingly, duplication of the FIR filter is avoided by instead providing two outputs from a single filter, the direct output (I) and the same output delayed 90 degrees in a latch. This simplification can be extended to the design of the following D/A converter, which can be made to accept a single input, and provide quadrature output by introduction of a 90 degree delay in a second Analog output. (Q). Most of the steps listed above, i.e., the trellis encoding, the inclusion of DC offset  101 , the FIR filter coefficient computation  102 , the coefficient normalization  104  and extension  105 , and the computation of modified FIR filter coefficient values  106 , are performed at the time the circuit is designed and built, and in combination are accomplished in a single FIR filter processing step at the time a signal is processed  107 ,  109 , producing the same band-passed single-sideband signal, with quadrature, 10 as in the prior art. Because the output of the FIR filter includes both the processed input signal and the quadrature of that signal, the invention&#39;s single FIR filtering step digitally eliminates the need for handling differential delay distortion at baseband frequencies in any subsequent analog filters after digital-to-analog conversion, an advantage of the invention. The ability of the digital filtering process to maintain precise phase relationships between the basic signal and its quadrature feeds an ideal input to the analog modulation process that follows, thereby eliminating expensive and difficult filtering in the analog realm. 
         [0054]    The invention&#39;s example FIR filter contains 31 shift registers  401 , selected as the smallest number considered capable of producing the root-raised-cosine filtering results in passband, transition band, and stopband as defined by the ATSC specification. See  FIGS. 5 ,  6 , and  7 .  FIG. 5  shows the overall configuration of functions in the FIR filter. The shift registers  401  are connected serially, so that each 3-bit signal input moves as shown  402  from register to register. Tap lines  403  between registers capture the signal for output calculation and summation. Each tap line  403  provides input to a filter tap  420 , where the filter tap coefficient outputs have been precalculated and stored. Each filter tap  420  sends its selected output via an output bus  404  to an adder circuit  430  connected to the previous adder circuit  430  and the next adder circuit  430 . The final adder circuit  430  supplies the final sum to an accumulator circuit as in a conventional FIR filter. 
         [0055]      FIG. 6  shows a closeup view of a pair of shift register stages. Each shift register stage comprises one shift register  401 , one filter tap  420 , and one adder  430 , connected as shown. Each filter tap  420  further comprises an address decoder  421 , a read-only memory  422 , and an XOR converter  423 . The shift registers  401  are connected to each other via a carrier line  450  and three data lines  451 ,  452 ,  453 . Each address decoder is connected to a ROM by address buses  405 . Each ROM is connected to an XOR converter by a data bus  404 . The adders are connected to each other and to the XOR converters via data buses  404 . 
         [0056]      FIG. 6A  shows a closeup view of a pair of shift register stages in which the ROMs  422  for each matching pair of filter taps shown in  FIG. 6  have been merged into a single ROM  429 . As in  FIG. 6 , each shift register stage comprises one shift register  401 , one filter tap  420 , and one adder  430 , connected as shown. Each filter tap  420  further comprises an address decoder  421 , access to a read-only memory  429 , and an XOR converter  423 . The shift registers  401  are connected to each other via a carrier line  450  and three data lines  451 ,  452 ,  453 . Each address decoder is connected to a ROM by address buses  405 . Each ROM is connected to an XOR converter by a data bus  404 . The adders are connected to each other and to the XOR converters via data buses  404 . 
         [0057]    In embodiments in which the precomputed filter tap coefficients are the same for filter stages equidistant from the middle of the filter, the invention provides for the use of dual-port ROM, allowing the use of a single ROM for each pair of such filter stages.  FIG. 7  provides a block-level view of one shift register pair of  FIG. 5 . 
         [0058]      FIG. 8  illustrates the storage and lookup of filter tap coefficients in each ROM  422  of  FIG. 6 . Three address bits  481  are input on address bus  405 , and ROM  422  retrieves the precomputed filter tap coefficient value  482  stored at the corresponding address in ROM. Each different input address value  481  maps to a corresponding trellis code value entered at the beginning of the precomputation process. The retrieved filter tap coefficient value  482  is output on data bus  404 , which is connected to an XOR converter. 
         [0059]    To improve the economics of the modulator, the invention eliminates components and complexity through the use of the highest possible reference frequencies, effectively reducing spurious signals and phase noise. The invention derives all necessary reference frequencies from a single crystal oscillator, eliminating sets of components associated with additional oscillator circuitry. See  FIG. 3 . The invention&#39;s design selects an oscillator frequency using the following criteria: 
         [0060]    The invention&#39;s choice of quartz crystal oscillator  201  frequency falls in the range of 10-30 MHz, which is optimal for cost and performance. The invention&#39;s range allows generation of 6 MHz frequencies for the local oscillator steps from a base of 6, 12, 18, 24, or 30 MHz. 
         [0061]    In a 30 MHz crystal reference embodiment, the invention uses its candidate 30 MHz crystal frequency to create a 10 MHz frequency  301  using a divide-by-3 circuit  202 . The invention then multiplies out  204  to a 770 MHz frequency  303 , and then applies  208  a divide-by-two circuit to produce the 385 MHz center frequency  308  of the Weaver modulator. The invention readily uses the 770 MHz frequency  303  to provide the required quadrature. 
         [0062]    In its 30 MHz crystal reference embodiment, the invention creates a 6 MHz step frequency  302  using a divide-by-5 circuit  203  to downconvert the 30 MHz oscillator input  201  to provide local oscillator frequencies  305  and RF channel frequencies  306 . Using a divide-by-2 circuit  207 , the invention also provides a 3 MHz base frequency  304  for PLLs and MPEG-2 use. 
         [0063]    In its 30 MHz crystal reference embodiment, the invention&#39;s resulting high phase detector frequencies for all PLLs (3 MHz and above) allow the use of low-cost oscillators in all PLLs while still obtaining acceptable phase noise characteristics. This advantage is due to the high loop gain possible at low frequencies with a high phase detection frequency. 
         [0064]    The invention derives the 27 MHz MPEG-2 video frequency by using a rate-multiplier PLL (phase-locked-loop), which constructs a multiple of the 3 MHz base frequency  304 . The multiple is used in turn for creating  209  the 27 MHz frequency  310 . The PLL design is usable since the phase noise restrictions are relatively less demanding during the processing of the MPEG-2 signal. 
         [0065]    While the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof to adapt to particular situations without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.

Technology Classification (CPC): 7