Patent Abstract:
A comparator according to the present invention can generate an output signal of low or high level by comparing a first and second input voltages that have a common voltage. An input stage circuit of a comparator according to the present invention receives a common voltage detection signal. The common voltage is supplied with a first offset voltage when the common voltage detection signal is on low level, and the common voltage is supplied with a second offset voltage when the common voltage detection signal is on high level. Then, the input stage circuit performs amplification to output a voltage difference between the first input voltage and the second input voltage to the comparator. Accordingly, the comparator with offset voltage according to the present invention can sufficiently amplify the input signal difference of low common voltage by selectively applying different offset voltages to a common voltage in accordance with the common voltage level of the input signal. The present invention can be applied to a comparator with offset voltage and an analogue comparator having a differential input stage.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a comparator with offset voltage, more particularly, to an analogue comparator having a differential input stage. 
     2. Background of the Related Art 
     An input stage of a comparator is generally constituted with a differential circuit that amplifies the voltage difference of two input signals. The two input signals are cancelled by each other when they have opposite phases and equal magnitudes, which results in no output signal. 
     FIG. 1 is a diagram that shows a differential circuit enabling to control an offset voltage. FIG. 1 is a diagram from U.S. Pat. No. 4,754,169. 
     Referring to FIG. 1, a current I of a reference current source is I=V REF /R 1 . Additional details of the reference current source are shown in FIG.  2 . The current I further becomes I=I REF =I 1 =V REF /R 1  by a current mirror, and an offset voltage V OFF  results in accordance with current I 1  between both ends of resistor R 0  as set forth by equation (1) as follows:                      V   OFF     =       I   1     ·     R   0                   =       (       V   REF     /     R   1       )     ·     R   0                   =       V   REF     ·     (     R0   /   R1     )                     (   1   )                                
     If the reference voltage V REF  is constant, a predetermined offset voltage is generated by adjusting a ratio of two resistors R 0  and R 1 . In this case, the resistors R 0  and R 1  should be fabricated by the same process. 
     As described above, the related art differential circuit has various disadvantages. The differential circuit according to a related art, which is constituted with NMOS transistors, is unable to work normally when a common voltage lower than about 1V is applied thereto. 
     The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter. 
     Another object of the present invention is to provide a comparator with an offset voltage that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art. 
     Another object of the present invention is to provide an input stage of a comparator that can sufficiently amplify an input signal difference of low common voltage. 
     Another object of the present invention is to provide an input stage of a comparator that enables amplification of an input signal difference of low common voltage sufficiently by applying offset voltage to the common voltage in accordance with the level of the common voltage. 
     To achieve at least the above objects and other advantages in a whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, a comparator according to the present invention generates an output signal of low or high level by comparing a first input voltage to a second input voltage which have a common voltage. 
     To further achieve the above objects in a whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, an input stage circuit of a comparator according to the present invention includes wherein the comparator generates a comparison result signal for a first input voltage and a second input voltage that each have a common voltage, wherein the input stage circuit receives a common voltage detection signal, wherein the common voltage is supplied with a first offset voltage when the common voltage detection signal is a first level, wherein the common voltage is supplied with a second offset voltage when the common voltage detection signal, is a second level, and wherein the input stage circuit amplifies to output a voltage difference between the first input voltage and the second input voltage to the comparator. 
     To further achieve the above objects in a whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, a comparator that generates an output signal by comparing a first input voltage to a second input voltage according to the present invention that includes a bias voltage generator that produces a first bias voltage and a second bias voltage, a common voltage detector that generates a common voltage detection signal responsive to a level of a common voltage of the first and second input voltages, and an input stage circuit amplifies a voltage difference between the first input voltage and the second input voltage, wherein the common voltage is supplied with a first offset voltage when the common voltage detection signal is a first level, and wherein the common voltage is supplied with a second offset voltage when the common voltage detection signal is a second level. 
     To further achieve the above objects in a whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, includes an input stage circuit of a comparator, the comparator generating an output signal for a second input voltage to a first input voltage received by the input stage circuit, wherein the first and second input voltages have a common voltage, wherein the input stage circuit receives a common voltage detection signal, wherein the common voltage is supplied with a first offset voltage when the common voltage detection signal is a first level, and wherein the common voltage is supplied with a second offset voltage when the common voltage detection signal is a second level, and wherein the input stage circuit amplifies to output a voltage difference between the first input voltage and the second input voltage to the comparator. 
     To further achieve the above objects in a whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, includes a method for operating a comparator that includes receiving the first and second input voltages each having a common voltage, receiving a common voltage detection signal, supplying the common voltage with a first offset value to reduce a common voltage level for the first input voltage when the common voltage detection signal is a first level, supplying the common voltage with a second offset value to increase a common voltage level of the second input voltage when the common voltage detection signal is a second level, amplifying a difference between the first and second input voltages to output a voltage difference to the comparator, and comparing the voltage difference in the comparator to output a comparison result of the first and second input voltages. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein: 
     FIG. 1 is a diagram that shows a differential circuit according to a related art; 
     FIG. 2 is a diagram that shows a reference current generating circuit of a differential circuit according to a related art; 
     FIG. 3 is a diagram that shows a circuit of a comparator with an offset voltage according to a preferred embodiment of the present invention; 
     FIG. 4 is a diagram that shows a circuit of a preferred embodiment of a bias voltage generator of a comparator according to the present invention; 
     FIG. 5 is a diagram that shows a circuit of a preferred embodiment of a common voltage detector of a comparator according to the present invention; 
     FIG. 6A is a diagram that shows a circuit for operational characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is lower than VDD/2; 
     FIG. 6B is a diagram that shows a graph of voltage characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is lower than VDD/2; 
     FIG. 7A is a diagram that shows a circuit for operational characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is higher than VDD/2; and 
     FIG. 7B is a diagram that shows a graph of voltage characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is higher than VDD/2. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 3 is a diagram that shows a circuit of a preferred embodiment of a comparator with offset voltage according to the present invention. As shown in FIG. 3, an input stage circuit  302  of a comparator  304  according to the preferred embodiment of the comparator includes a P channel driving circuit  306 , an N channel driving circuit  308 , and a current output part  310 . 
     The P channel driving circuit  306  includes a serial circuit controlled by P channel bias voltage V BIASP  and a common voltage detection voltage S COM , and a parallel circuit controlled by an N channel input voltage V INN  and P channel input voltage V INP . In the serial circuit, a couple of PMOS transistors  312  and  314  are coupled in series between power source voltage VDD and the parallel circuit. Gates of the PMOS transistors  312  and  314  are controlled by the P channel bias voltage V BIASP  and the common voltage detection signal S COM , respectively. In the parallel circuit, a PMOS transistor  320  and a resistor  318  are coupled in parallel with another PMOS transistor  316 . Gates of the PMOS transistors  316  and  320  are preferably controlled by the N channel input signal V INN  and the P channel input signal V INP , respectively. 
     The N channel driving circuit  308  includes a serial circuit controlled by N channel bias voltage V BIASN  and a common voltage detection voltage S COM , and a parallel circuit controlled by an N channel input voltage V INN  and P channel input voltage V INP . In the serial circuit, a couple of NMOS transistors  328  and  330  are coupled in series between ground voltage and the parallel circuit. Gates of the NMOS transistors  330  and  328  are controlled by the N channel bias voltage V BIASN  and the common voltage detection signal S COM , respectively. In the parallel circuit, series coupled NMOS transistor  322  and resistor  324  together are coupled in parallel with NMOS transistor  326 . Gates of the NMOS transistors  322  and  326  are controlled by the N channel input signal V INN  and the P channel input signal V INP , respectively. 
     In the current output part  310 , preferably a pair of PMOS transistors  332  and  334  of a diode connection type organize an active load, while four NMOS transistors  336 ,  338 ,  340 , and  342  constitute a current source. 
     The parallel circuit of the N channel driving circuit is coupled to nodes  346  and  348 . Once the N channel driving circuit  308  is activated, the PMOS transistors  332  and  334  operate as an active load of the N channel driving circuit  308 . The current source  336 ,  338 ,  340 , and  342  is coupled to the parallel circuit of the P channel driving circuit  306 , which works as a current source only when the P channel driving circuit  306  is activated. 
     A non-inversion input terminal (+) and an inversion terminal (−) of the comparator  304  are coupled to the nodes  346  and  348 , respectively. The comparator  304  generates an output signal OUT of low level when a node voltage V N346  is higher than the other node voltage V N343 , and generates the output signal OUT of high level when the node voltage V N348  is higher than the other node voltage V N346 . 
     FIG. 4 is a diagram that shows a circuit of a preferred embodiment of a bias voltage generator of a comparator according to the present invention. As shown in FIG. 4, PMOS transistors  402  and  404  are active loads and an NMOS transistor  408  is a constant voltage source having a diode connection structure. 
     Reference voltage V REF  is inputted to a non-inversion input terminal (+) of a logic amplifier  412 , while an inversion input terminal (−) is coupled to a ground voltage through a resistor  410 . An output of the logic amplifier  412  controls a gate voltage of an NMOS transistor  406 . Thus, drain voltage of the NMOS transistor  406  maintains the same level of the reference voltage V REF  and the current flowing through the resistor  410  is also constant as I 1 =V REF /R 410 . The reference current I 1  produces a P channel bias voltage V BIASP  and an N channel bias voltage V BIASN . 
     FIG. 5 is a diagram that shows a circuit of a preferred embodiment of a common voltage detector of a comparator according to the present invention. As shown in FIG. 5, an N channel input voltage V INN  and a P channel input voltage V INP  are input to both ends of a pair of resistors  502  and  504  coupled in series to each other. As the N channel input voltage V INN  and the P channel input voltage V INP  have opposite phases, components of the respective alternating currents cancel each other to show only a direct current component at a node  510 . 
     Two inverters  506  and  508  coupled in series from the node  510  output a common voltage detection signal S COM  as a logic signal by changing the DC voltage of the node  510 . The common voltage detection signal S COM  is on high level when the DC level of the common voltage is equal to or higher than logic threshold voltage V LT , and on low level when the DC level of the common voltage is lower than logic threshold voltage V LT . In this case, the logic threshold voltage V LT  of the inverters  506  and  508  is preferably VDD/2. 
     Operation of the comparator will now be described. In the input stage circuit  302 , current I P  flowing through the PMOS transistor  312  of the P channel driving circuit  306  and the other current I N  flowing through the NMOS transistor  330  of the N channel driving circuit  308  depend on the P channel bias voltage V BIASP  and the N channel bias voltage V BIASN , respectively, where I P =I N =αI 1 (α is a coefficient). 
     Offset voltage V P  generated from the current I P  between both ends of the resistor  318  of the P channel driving circuit  306  is represented by equation (2) as follows:                      V   P     =       I   P     ·     R   P                   =     α                     I   1     ·     R   318                     =       α        (       V   REF     /     R   410       )       ·     R   318                   =       V   REF     ·   α   ·     (       R   318     /     R   410       )                     (   2   )                                
     Offset voltage V N  generated from the current I N  between both ends of the resistor  324  of the N channel driving circuit  308  is represented by equation (3) as follows:                      V   N     =       I   N     ·     R   N                   =     α                     I   1     ·     R   324                     =       α        (       V   REF     /     R   410       )       ·     R   324                   =     α   ·     V   REF     ·     (       R   324     /     R   410       )                     (   3   )                                
     Once the resistors  318  and  324  have the same resistance, a prescribed offset voltage is generated because V N =V P . 
     FIG. 6A is a diagram that shows a circuit for operational characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is lower than VDD/2. FIG. 6B is a diagram that shows a graph of voltage characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is lower than VDD/2. 
     As shown in FIG.  6 A and FIG. 6B, operations of the preferred embodiment of the input stage circuit when a level of common voltage V COM  ranges 0 V to VDD/2 will now be described. The common voltage detection signal S COM  outputted from the common voltage detector  500  becomes low level since V COM &lt;V LT . Thus, the PMOS transistor  314  of the P channel driving circuit  306  becomes turned on, while the NMOS transistor  328  of the N channel driving circuit  308  becomes turned off. 
     The input stage circuit  302  of the comparator  304  according to the preferred embodiment is equalized with the circuit shown in FIG. 6A since the P channel driving circuit  306  has an influence on the current output part  310 , but the N channel driving circuit  308  has no influence thereon. In this case, the input stage circuit in FIG. 6A may be regarded as the P channel driving circuit  306  combined with the current output part  310 . 
     As shown in FIG. 6A, the voltage V SG316  between the node  344  and the gate of the PMOS transistor  316  and the other voltage V SG320  between the node  344  and the gate of the PMOS transistor  320  are represented by equation (4) as follows: 
     
       
         V SG316 =V N344 −V INN V SG320 =V N344 −V P −V INP   (4) 
       
     
     When V SG316 &lt;V SG320 , that is, V INN &gt;(V INP +V P ), the current flowing through the drain of the PMOS transistor  316  is larger than that flowing through the drain of the PMOS transistor  320 . Therefore, the current flowing through the NMOS transistors  336  and  338  from the current source of the current output part  310  to the ground is larger than that flowing through the NMOS transistors  340  and  342 . As a result, an output signal OUT of the comparator  304  becomes high level since the node voltage V N348  is relatively higher than the other node voltage V N346 . 
     On the other hand, when V SG316 &gt;V SG320 , that is, V INN &lt;(V INP +V P ), the current flowing through the drain of the PMOS transistor  320  is larger than that flowing through the drain of the PMOS transistor  316 . Therefore, the current flowing through the NMOS transistors  340  and  342  from the current source of the current output part  310  to the ground is larger than that flowing through the NMOS transistors  336  and  338 . As a result, the output signal OUT of the comparator  304  becomes low level since the node voltage V N346  is higher than the other node voltage V N348 . Such voltage characteristics are shown in FIG.  6 B. As shown in FIG. 6B, when V INN &lt;(V INP +V P ), the output signal OUT becomes high level. 
     FIG. 7A is a diagram that shows a circuit for operational characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is higher than VDD/2. FIG. 7B is a diagram that shows a graph of voltage characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is higher than VDD/2. 
     The input stage circuit  302  of the comparator  304  according to the preferred embodiment is equalized with the circuit shown in FIG. 7A since the N channel driving circuit  308  has an influence on the current output part  310 , but the P channel driving circuit  306  has no influence thereon. FIG. 7A is an equivalent circuit of an input stage circuit when VDD/2&lt;V COM &lt;VDD, where the active loads  332  and  334  of the current output part  310  may be regarded as combined with the N channel driving circuit  308 . 
     The input stage circuit  302  of the comparator  304  according to the preferred embodiment is equalized with the circuit shown in FIG. 7A since the N channel driving circuit  308  has an influence on the differential amplifier  310 , but the P channel driving circuit  306  has no influence thereon. FIG. 7A is an equivalent circuit of an input stage circuit when VDD/2&lt;V COM &lt;VDD, where the active loads  332  and  334  of the differential amplifier  310  may be regarded as combined with the N channel driving circuit  308 . 
     As shown in FIG. 7A, the voltage V GS322  between the node  350  and the gate of the NMOS transistor  322  and the other voltage V GS326  between the node  350  and the gate of the NMOS transistor  326  are represented by equation (5) as follows: 
     
       
         V GS322 =V INN −V N −V N350 V GS326 =V INP −V N350   (5) 
       
     
     When V GS322 &gt;V GS326 , that is, V INN &gt;(V INP +V N ), the current flowing through the drain of the NMOS transistor  322  is larger than that flowing through the drain of the NMOS transistor  326 . Therefore, the output signal OUT of the comparator  304  becomes low level since the node voltage V N346  is relatively higher than the other node voltage V N348 . 
     On the other hand, when V GS316 &gt;V GS320 , that is, V INN &lt;(V INP +V N ), the current flowing through the drain of the NMOS transistor  326  is larger than that flowing through the drain of the PMOS transistor  320 . Therefore, the output signal OUT of the comparator  304  becomes high level since the node voltage V N348  is higher than the other node voltage V N346 . Such voltage characteristics are shown in FIG.  7 B. 
     As shown in FIG. 7B, when V INN &gt;(VNP+V N ), the output signal OUT becomes high level. 
     As described above, preferred embodiments according to the present invention have various advantages. The preferred embodiments of a comparator with offset voltage according to the present invention enables sufficient amplification of an input signal difference of low common voltage by selectively applying an offset voltage to a common voltage in accordance with the common voltage level of the input signal. 
     The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.

Technology Classification (CPC): 7