Patent Abstract:
A bonding process for a chip bonded to a thin film substrate is disclosed. The thin film substrate has a thickness of about less than 500 um. Curvature occurs in the thin film substrate due to Coefficient of Temperature Expansion (CTE) mismatch for different materials between the dielectric material and the embedded circuitry, where cooling and heating is applied during fabrication. A temporary carrier is prepared for the thin film substrate to paste, a flatten process is applied by a roller thereon so that the curvature of the thin film substrate can be eliminated and facilitated for of chips to be bonded thereto.

Full Description:
[0001]    This application is a continuation-in-part application of U.S. application Ser. No. 14/509,395 filed Oct. 8, 2014, the disclosure of which is incorporated by reference herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a high density film for IC package, especially relates to a high density film without having any interposer. A traditional interposer includes such as a semiconductor interposer with through silicon via (TSV) or a glass interposer with through glass via (TGV) embedded therein. 
         [0004]    2. Description of Related Art 
         [0005]      FIG. 1  shows a prior art substrate for IC package 
         [0006]      FIG. 1  shows a prior art substrate for IC package disclosed in US2014/0102777A1 which has an embedded silicon interposer  20 . The silicon interposer  20  has four later sides  206 . A molding compound  22  wraps the silicon interposer  20  around the four lateral sides  206 . A plurality of via metal  200  is made through the silicon interposer  20 . An insulation liner  201  is made between the through via  200  and the silicon interposer  20  for an electrical insulation there-between. A top redistribution layer  21  is made on top of the silicon interposer  20  with a plurality of metal pad  210  exposed on top. The plurality of metal pad  210  on top is provided for accommodating an IC chip (not shown) to mount. A circuit built-up layer  25  is made on bottom of the silicon interposer  20  with a plurality of metal pad  220  configured on bottom. A plurality of solder ball  4  is configured and each solder ball  4  is configured on bottom of a corresponding bottom metal pad  220 . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  shows a prior art IC package. 
           [0008]      FIGS. 2A ˜ 2 M show a process for fabricating a high density film according to the present invention. 
           [0009]      FIGS. 2N ˜ 2 S show an IC package using the high density film according to the present invention. 
           [0010]      FIG. 3  shows a process flow for fabricating a high density film according to the present invention. 
           [0011]      FIG. 4  shows a further process flow for fabricating a high density film according to the present invention. 
           [0012]      FIG. 5  shows a process flow for fabricating an IC package using the high density film according to the present invention. 
           [0013]      FIG. 6  shows a thin film substrate according to the present invention. 
           [0014]      FIG. 7  shows registration problem due to the curvature of the thin film substrate. 
           [0015]      FIGS. 8A ˜ 8 J show a first bonding process according to the present invention. 
           [0016]      FIGS. 9A ˜ 9 J show a second bonding process according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]      FIGS. 2A ˜ 2 M show a process for fabricating a high density film according to the present invention. 
         [0018]      FIG. 2A  shows a temporary carrier I is prepared, a first release layer  31  is applied on top of the temporary carrier I, and a seed layer  32 , such Ti/Cu, is formed on top of the first release layer  31 . 
         [0019]      FIG. 2B  shows a patterned photoresist  33  is formed on top of the seed layer  32 . 
         [0020]      FIG. 2C  shows a plurality of bottom pad  341  is formed on top of the seed layer  32 . 
         [0021]      FIG. 2D  shows the patterned photoresist  33  is removed and a plurality of bottom pad  341  is left. 
         [0022]      FIG. 2E  shows the seed layer  32  between pads  341  are removed. 
         [0023]      FIG. 2F  shows a first redistribution circuitry  342  is formed following IC design rule, using the plurality of bottom pad  341  as a starting point, comprising the steps: a first dielectric layer  351  is applied on top of the bottom pad  341 , and then a first redistribution circuitry  342  is formed through traditional technique. 
         [0024]      FIG. 2G  shows a plurality of first top pad  343  is formed comprising the following steps: a second dielectric layer  352  is applied on top of the first redistribution circuitry  342 , a plurality of first top pad  343  is formed through traditional technique. A first redistribution circuitry  342  and a plurality of first top pad  343  are exemplified in this embodiment. The redistribution circuitry layer can be repeatedly processed to even more layers to fan out the circuitry if desired. The bottom pad  341 , the first redistribution circuitry  342  and the first top pad  343  are collectively called circuitry film RDL I. 
         [0025]      FIG. 2H  shows the temporary carrier I is removed to form a circuitry film RDL I. And then a singulating process is performed to produce a plurality of single unit of circuitry film RDL I. 
         [0026]      FIG. 2I  shows a single unit of circuitry film RDL I. 
         [0027]      FIG. 2J  shows a temporary carrier II is prepared. A second release layer  311  is applied on top of the temporary carrier II. A plurality of circuitry film RDL I is arranged on top of the second release layer  311 . 
         [0028]      FIG. 2K  shows a second redistribution circuitry  441  is formed following PCB design rule, using the plurality of first top pad  343  as a starting point, comprising the steps: a third dielectric layer  451  is applied on top of the circuitry film RDL I, and then a second redistribution circuitry  441  is formed through traditional technique. 
         [0029]    The dielectric layer used for PCB process can be one of Ajinomoto build-up films (ABF) or Pre-preg (PP). 
         [0030]      FIG. 2L  shows a plurality of second top pad  442  is formed, comprising the steps: a fourth dielectric layer  452  is applied on top of the second redistribution circuitry  441  and the third dielectric layer  451 , a plurality of second top pad  442  is formed through traditional technique. A second redistribution circuitry  441  and a plurality of second top pad  442  are exemplified in this embodiment. The redistribution circuitry can be repeatedly processed to even more layers to fan out the circuitry if desired. The redistribution circuitry  441  and the second top pad  442  are collectively called circuitry film RDL II. A high density film (RDL I+RDL II) is formed on top of the second release layer  311 . 
         [0031]      FIG. 2M  shows the temporary carrier II is removed, and a high density film (RDL I+RDL II) is released. 
         [0032]      FIGS. 2N ˜ 2 S show a fabricating process for an IC package using the high density film according to the present invention. 
         [0033]      FIG. 2N  shows at least one chip  51  is mounted on a bottom of the bottom pad  341 . 
         [0034]      FIG. 2O  shows a molding compound  511  is applied to encapsulate the chip or chips  51 . 
         [0035]      FIG. 2P  shows a thinning process is applied onto the molding compound  511  to reveal a bottom surface of the chip  51  for heat dissipation of the chip. 
         [0036]      FIG. 2Q  shows a dielectric layer  521  is applied between the second top pads  442 , and a plurality of solder ball  52  is planted, each solder ball  52  is configured on top of a corresponding top pad  442 . 
         [0037]      FIG. 2R  shows a heat sink  53  is configured on a bottom surface of the chip  51  for further heat dissipation. 
         [0038]      FIG. 2S  shows a single unit of the IC package is formed after a singulating process applied on the product of  FIG. 2R . 
         [0039]      FIG. 3  shows a process flow for fabricating a high density film according to the present invention, comprises: 
         [0040]    fabricating a bottom redistribution layer RDL I following IC design rule, with a plurality of bottom pad  341  formed on bottom, and with a plurality of first top pad  343  formed on top; wherein the density of the plurality of bottom pad  341  is higher than the density of the plurality of first top pad  343 ; and 
         [0041]    fabricating a top redistribution layer RDL II following PCB design rule, using the plurality of the first top pad  343  as a starting point; with a plurality of second top pad  442  formed on top; wherein a density of the plurality of first top pad  343  is higher than a density of the plurality of second top pad  442 . 
         [0042]      FIG. 4  shows a further process flow for fabricating a high density film, comprises: 
         [0043]    preparing a temporary carrier I; 
         [0044]    applying a first release layer  31  on top of the temporary carrier I; 
         [0045]    forming a seed layer  32  on top of the first release layer  31 ; 
         [0046]    forming a plurality of bottom pad  341  on top of the seed layer; 
         [0047]    etching the seed layer between the bottom pads  341 ; 
         [0048]    forming a bottom redistribution layer RDL I following IC design rule, using the bottom pad  341  as a starting point; with a plurality of first top pad  343  formed on top, to form circuitry film RDL I; 
         [0049]    removing the temporary carrier I to release the circuitry film RDL I; 
         [0050]    singulating the circuitry film RDL I to produce a plurality of RDL I unit 
         [0051]    preparing a temporary carrier II; 
         [0052]    applying a second release layer  311  on top of the temporary carrier II; 
         [0053]    arranging a plurality of the RDL I unit on top of the second release layer  311 ; 
         [0054]    forming a second top redistribution layer RDL II following PCB design rule on top of the plurality of RDL I unit, using the first top pad  343  as a starting point; with a plurality of second top pad  442  formed on top; and 
         [0055]    removing the temporary carrier II to release a high density film (RDL I+RDL II). 
         [0056]      FIG. 5  shows a process flow for fabricating an IC package using the high density film according to the present invention, comprises: 
         [0057]    removing the temporary carrier I to release the bottom redistribution layer RDL I; 
         [0058]    singulating the bottom redistribution layer RDL I to produce a plurality of RDL I unit; 
         [0059]    preparing a temporary carrier II; 
         [0060]    applying a second release layer  311  on top of the temporary carrier II; 
         [0061]    arranging a plurality of the RDL I unit on a top of the second release layer  311 ; 
         [0062]    forming a second top redistribution layer RDL II following PCB design rule on top of the plurality of RDL I unit, using the plurality of first top pad  343  as a starting point; with a plurality of second top pad  442  formed on top; 
         [0063]    removing the temporary carrier II to release a high density film (RDL I+RDL II); 
         [0064]    mounting at least one chip  51  on bottom of the plurality of bottom pad  341 ; 
         [0065]    molding the chip  51  with a molding compound  511 ; 
         [0066]    thinning the molding compound  511  from bottom to reveal the bottom surface of the chip  51 ; 
         [0067]    mounting a heat sink  53  on bottom of the chip  51 ; and 
         [0068]    singulating to produce a plurality of separated unit. 
         [0069]      FIG. 6  shows a thin film substrate according to the present invention. 
         [0070]      FIG. 6  shows a thin film substrate  11  which has a plurality of substrate units for chips to package. The thin film substrate  11  is fabricated the same as, or similar to, the process fabricating the thin film substrate of  FIG. 2M . 
         [0071]    Since the thin film substrate  11  has a thickness of about 50-200 um, some curvature  113  may exists due to Coefficient of Temperature Expansion (CTE) mismatch of the dielectric material and the embedded circuitry to which cooling and heating applied during its fabrication process. 
         [0072]    An enlarged view of the thin film substrate  11  is shown in a circle  114 , the thin film substrate  11  has a plurality of top pads  111  adapted for a chip to be electrically coupled to. A solder mask  112  is applied on a top surface of the thin film substrate  11  to expose a central area of each top pad  111 . The thin film substrate  11  has a plurality of bottom pads  271 . A solder mask  272  is applied to cover the bottom side of the thin film substrate  11  to expose a central area of the bottom pads  271  so that a solder ball  273  can be planted on a corresponding bottom pad  271  in a later process; wherein a density of the top pads is higher than a density of the bottom pads. 
         [0073]    The top side of the thin film substrate  11  is a pad high density side for a chip to mount thereon and therefore also called a chip side. In the meanwhile, the bottom side of the thin film substrate  11  is a pad low density side fabricated for the package mounting to printed circuit board and therefore also called a PCB side. 
         [0074]      FIG. 7  shows registration problem due to the curvature of the thin film substrate. 
         [0075]      FIG. 7  shows that curvature  113  is shown with the thin film substrate  11  fixed on a working table  10  with fixtures to fix at points  101 . An enlarged view in the circle area  115  shows that a chip  12  has a plurality of metal pillars  121  on bottom. A registration problem, electrically coupling, or bonding problem occurs while the metal pillars  121  are aligned with the top pads  111  due to the curvature  113  of the thin film substrate  11 . For example, the metal pillars at two ends can not contact the bottom pads  111  while the middle metal pillars contact the bottom pad  111  due to curvature  113  of the thin film substrate  11 . 
         [0076]      FIGS. 8A ˜ 8 J show a first bonding process according to the present invention. 
         [0077]    For simplification and better understanding to the reader, the dimensions for the elements in the figures are not in scale, and partial elements are omitted in some of the figures, for example, bottom pads  271  and solder mask  272  are not shown in  FIGS. 8A ˜ 8 H, and  9 A˜ 9 H. 
         [0078]      FIG. 8A  shows: 
         [0079]    preparing a thin film substrate  11  which has curvature  113 , the thin film substrate  11  has a plurality of top pads  111  and has a plurality of bottom pads  271 ; a density of the top pads  111  is higher than a density of the bottom pads  271 ; 
         [0080]    preparing a temporary carrier  21 ; 
         [0081]    applied adhesive layer  22  on a top surface of the temporary carrier  21 ; 
         [0082]      FIG. 8B  shows: 
         [0083]    pasting the thin film substrate  11  on a top surface of the adhesive layer  22 ; and flattening the thin film substrate  11  with a roller  23  so that the thin film substrate  11  is flattened to eliminate the curvature  113  of the thin film substrate  11 ; 
         [0084]      FIG. 8C  shows: 
         [0085]    a flattened thin film substrate  11  is configured on the top surface of the temporary carrier  21  with the adhesive layer  22  sandwiched in between the thin film substrate  11  and the temporary carrier  21 ; 
         [0086]      FIG. 8D  shows: 
         [0087]    preparing a plurality of chips  12 , each chip  12  has a plurality of metal pillars  121  on bottom and an underfill material  24  wrapping the metal pillars  121  on bottom; and each chip  12  has a plurality of metal pillars  121  configured on bottom; 
         [0088]      FIG. 8E  shows: 
         [0089]    placing the plurality of chips  12  onto the flattened thin film substrate  11 ; 
         [0090]      FIG. 8F  shows: 
         [0091]    heating to bound the chips  12  to the thin film substrate  11  with heat  26 ; 
         [0092]      FIG. 8G  shows: 
         [0093]    molding the chips  12  to form a package sheet with a molding compound  25 ; 
         [0094]      FIG. 8H  shows: 
         [0095]    releasing the package sheet from the temporary carrier  21 ; 
         [0096]      FIG. 8I  shows: 
         [0097]    forming solder mask  272  on bottom of the thin film substrate  11  and exposing a bottom surface of each bottom pad  271 ; 
         [0098]      FIG. 8J  shows: 
         [0099]    singulating the package sheet to produce a plurality of package units. 
         [0100]    Each package unit comprises a chip  12  embedded in the molding compound  25 . Underfill  24  is configured in a space between the chip  12  and the thin film substrate  11 . Chip  12  is bonded to the thin film substrate  11  through metal pillars  121  electrically coupled to the top pads  111 . A plurality of bottom pads  271  is configured on a bottom surface of the thin film substrate  11 . A solder ball  273  is configured on a bottom surface of a corresponding bottom pad  272 . 
         [0101]      FIGS. 9A ˜ 9 J show a second bonding process according to the present invention. 
         [0102]      FIG. 9A  shows: 
         [0103]    preparing a thin film substrate  11  which has curvature  113 , the thin film substrate  11  has a plurality of top pads  111  and has a plurality of bottom pads  271  ( FIG. 7 ); a density of the top pads  111  is higher than a density of the bottom pads  271  ( FIG. 7 ); 
         [0104]    preparing a temporary carrier  21 ; 
         [0105]    applied adhesive layer  22  on a top surface of the temporary carrier  21 ; 
         [0106]    pasting the thin film substrate  11  on a top surface of the adhesive layer  22 ; and 
         [0107]    flattening the thin film substrate  11  with a roller  23  so that the thin film substrate  11  is flattened to eliminate the curvature  113  of the thin film substrate  11 ; 
         [0108]      FIG. 9B  shows: 
         [0109]    a flattened thin film substrate  11  is configured on the top surface of the temporary carrier  21  with the adhesive layer  22  sandwiched in between the thin film substrate  11  and the temporary carrier  21 ; 
         [0110]      FIG. 9C  shows: 
         [0111]    applying underfill material  24  on top surface on the thin film substrate  11 ; 
         [0112]      FIG. 9D  shows: 
         [0113]    preparing a plurality of chips  12 , each chip  12  has a plurality of metal pillars configured on bottom; 
         [0114]      FIG. 9E  shows: 
         [0115]    placing the plurality of chips  12  onto the flattened thin film substrate  11 ; 
         [0116]      FIG. 9F  shows: 
         [0117]    heating to bound the chips  12  to the thin film substrate  11  with heat  26 ; 
         [0118]      FIG. 9G  shows: 
         [0119]    molding the chips  12  to form a package sheet with a molding compound  25 ; 
         [0120]      FIG. 9H  shows: 
         [0121]    releasing the package sheet from the temporary carrier  21 ; 
         [0122]      FIG. 9I  shows: 
         [0123]    forming solder mask  272  on bottom of the thin film substrate  11  and exposing a bottom surface of each bottom pad  271 ; 
         [0124]      FIG. 9J  shows: 
         [0125]    singulating the package sheet to produce a plurality of package units. 
         [0126]    Each package unit comprises a chip  12  embedded in the molding compound  25 . Underfill  24  is configured in a space between the chip  12  and the thin film substrate  11 . Chip  12  is bonded to the thin film substrate  11  through metal pillars  121  electrically coupled to the top pads  111 . A plurality of bottom pads  271  is configured on a bottom surface of the thin film substrate  11 . A solder ball  273  is configured on a bottom surface of a corresponding bottom pad  272 . 
         [0127]    While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.

Technology Classification (CPC): 7