Patent Abstract:
A method of fabricating a dual damascene opening, comprising the following sequential steps. A structure having a stop layer formed over a second low-k material layer formed over a stop layer formed over a first low-k material layer is provided. These layers are etched to form a via opening exposing a portion of the structure. A photoresist layer is formed over the second low-k material layer stop layer and filling the via opening. The photoresist layer having a treated upper portion including a central trench pattern area that is wider than, and substantially centered over, the via opening. The treated upper portion of the photoresist layer preventing any effects to the underlying photoresist layer so that the underlying photoresist layer does not deleteriously interact with the first or second low-k material layer. Removing: (1) the central trench pattern area of the upper treated portion of the photoresist and the photoresist under the central trench pattern area a to form a trench pattern opening exposing a portion of the second low-k material layer stop layer under the removed central trench pattern area; and (2) the photoresist layer within the via opening while leaving a portion of the photoresist layer within the via opening overlying the portion of the structure that was exposed by the via opening. Transferring the trench pattern opening to the second low-k material layer stop layer and the second low-k material layer to form a trench substantially centered over the remaining via opening and completing the dual damascene opening.

Full Description:
BACKGROUND OF THE INVENTION 
     A typical prior art via-first dual damascene process to form a dual damascene structure within a CVD low-k intermetal dielectric (IMD) layer includes: via formation (patterning and etching); formation of a protective layer at the bottom of the via; then trench formation (patterning and etching). Once the via is formed, the CVD low-k material is exposed along the via&#39;s sidewalls. 
     The article entitled “0.15 μm ArF Excimer Laser Lithography using Top Surface Imaging with High Contrast Silylation Agent B(DMA)DS”, T. Ohfuji and N. Aizaki, 1994 Symposium on VLSI Technology Digest of Technical Papers, pages 93 and 94, describes silylation with B(DMA)DS and applied to a 193 nm wavelength ArF laser. 
     The article entitled “CVD Photoresist Processes for Sub-0.18 Design Rules”, T. Weidman et al., 1998 Symposium on VLSI Technology Digest of Technical Papers, pages 166 and 167, describes a process for photoresist deposition for imaging a layer for 193 nm wavelength lithography. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of an embodiment of the present invention to provide an improved method of forming dual damascene structures. 
     It is another object of an embodiment of the present invention to prevent interaction of CVD low-k material with the DUV photoresist during trench patterning. 
     Other objects will appear hereinafter. 
     It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a stop layer formed over a second low-k material layer formed over a stop layer formed over a first low-k material layer is provided. These layers are etched to form a via opening exposing a portion of the structure. A photoresist layer is formed over the second low-k material layer stop layer and filling the via opening. The photoresist layer having a treated upper portion including a central trench pattern area that is wider than, and substantially centered over, the via opening. The treated upper portion of the photoresist layer preventing any effects to the underlying photoresist layer so that the underlying photoresist layer does not deleteriously interact with the first or second low-k material layer. Removing: ( 1 ) the central trench pattern area of the upper treated portion of the photoresist and the photoresist under the central trench pattern area to form a trench pattern opening exposing a portion of the second low-k material layer stop layer under the removed central trench pattern area; and ( 2 ) the photoresist layer within the via opening while leaving a portion of the photoresist layer within the via opening overlying the portion of the structure that was exposed by the via opening. Transferring the trench pattern opening to the second low-k material layer stop layer and the second low-k material layer to form a trench substantially centered over the remaining via opening and completing the dual damascene opening. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which: 
     FIGS. 1 to  4  schematically illustrate a first preferred embodiment of the present invention. 
     FIGS. 5 to  8  schematically illustrate a second preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Unless otherwise specified, all structures, layers, steps, methods, etc. may be formed or accomplished by conventional steps or methods known in the prior art. 
     A Problem Known to the Inventors 
     The following problem is known to the inventors and is not to be considered prior art for the purposes of this invention. 
     One problem known to the inventors in the typical prior art via-first dual damascene process is having the exposed CVD low-k material within the via formed in the IMD layer. The exposed CVD low-k material on the via sidewalls will interact with materials in subsequent process steps, such as a deep ultraviolet (DUV) patterning step in the formation of the trench of the dual damascene structure. 
     During the photo exposure in the trench formation, the DUV photoresist will generate carboxylic acid after the DUV exposure which can interact with unsaturated bonds (e.g. as C═O and CN with excess e-pair in black diamond and also other bonds such as in SiOH) in CVD low-k materials that may comprise the IMD layer. Such an interaction will result in residual materials that are difficult to remove after the trench patterning in a typical prior art via-first dual damascene process. 
     First Embodiment—Silylation Process Scheme 
     Initial Structure—First Embodiment 
     FIG. 1 illustrates a structure  10  with an exposed conductive structure  12 . 
     Structure  10  is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer. 
     Conductive structure  12  is preferably comprised of a metal or metal alloy such as, for example, aluminum, copper, gold, etc., and may be a conductive plug or conductive line. 
     A first stop layer  14  is formed over structure  10  and conductive structure  12 . A first CVD low-k material layer  16  is formed over the first stop layer  14 . A second stop layer  18  is formed over the first low-k material layer  16 . A second CVD low-k material layer  20  is formed over the second stop layer  18 . A third stop layer  22  is then formed over the second CVD low-k material layer  20 . 
     The first, second and third stop layers  14 ,  18 ,  22  are preferably formed of nitride, silicon nitride (SiN), silicon carbide (SiC) or silicon oxynitride (SiON); and are preferably from about 300 to 600 Å thick and more preferably from about 400 to 600 Å. 
     The first and second CVD low-k material layers  16 ,  20  may be intermetal dielectric (IMD) layers and may be formed of Black Diamond™ manufactured by Applied Materials or Coral™ available from Novellus The first and second CVD low-k material layers  16 ,  20  are preferably from about 3000 to 7000 Å thick and more preferably from about 4000 to 6000 Å. 
     As shown in FIG. 1, a via patterning and etching is performed through the third stop layer  22 , the second low-k material layer  20 , the second stop layer  18 , the first low-k material layer  16  and the first stop layer  14  to form via  24  exposing at least a portion of the conductive structure  12 . The via  24  patterning and etching may be performed by conventional methods and processes. 
     Silylation Process 
     As shown in FIG. 2, a silylation photoresist (PR) layer  26  is formed over the structure of FIG. 1, filling via  24 . Silylation PR layer  26  is preferably formed by spin coating and is preferably a material comprised of a photoacid generator (PAG). Silylation PR layer  26  is preferably formed to a height of from about 4000 to 8000 Å and more preferably from about 4000 to 6000 Å above the third stop layer  22 . 
     Then, using optical trench mask  30  roughly centered over via  24  and having a width greater than via  24 , the upper portion  28  of silylation PR layer  26  is exposed as at  32 , using optical trench mask  30  as a mask, and preferably using deep ultraviolet (DUV) light in a top surface image process. DUV exposure  32  includes the presence of oxygen (O 2 ). Upper portion  28  of silylation PR layer  26  has a thickness of preferably from about 1000 to 4000 Å. 
     The cross-linking in the trench pattern area  36  of upper portion  28  of silylation PR layer  26  is achieved by then performing a hard bake at a temperature of from about 100 to 200° C. No cross-linking is achieved in the center, non-exposed area  34  of upper portion  28  of silylation PR layer  26 . 
     Then a silylation process is performed to transform the outer, exposed areas  36  of upper portion  28  of silylation PR layer  26  into silylated portions  36  having a thickness of preferably from about 1000 to 4000 Å. The non-cross-linked center trench pattern area  34  of upper PR layer portion  28  does not react to the silylation process. The silylation process is performed using tetra-methyl-di-silazane (TMDS) at a temperature of preferably from about 100 to 200° C. 
     It is noted that the cross-linking, silylation process and DUV photo exposure occurs only within the upper portion  28  of silylation PR layer  26  (also known as top surface imaging) and therefore no carboxylic acid is formed within the silylation PR layer  26  at the via  24  sidewall and thus there is no adverse interaction between the silylation PR layer  26  and the exposed first and second CVD low-k material layers  16 ,  20  after the DUV exposure  32 . This eliminates the PR poison issue known to the inventors as discussed above as none of the photoresist adjacent to the exposed portions of the low-k material layers  16 ,  20  is exposed to DUV. 
     Reactive Ion Etch (RIE) 
     As shown in FIG. 3, using the outer, cross-linked portions  36  of silylation PR layer  26  as masks, the structure of FIG. 2 is subjected to a reactive ion etch (RIE)  38  that etches away the center, unexposed portion  34  of silylation PR layer  26  and the portion of PR layer  26  substantially beneath the unexposed PR portion  34  down to the second stop layer  18  (forming a trench pattern opening  40  within the etched silylation PR layer  26 ′ above the second stop layer  18 ) and a portion of the PR layer  26  within the via  24  but leaving a portion  42  of PR layer  26 ′ within the via  24  overlying the conductive structure  12 . The portion  42  of PR layer  26 ′ overlying the conductive structure  12  protects the conductive structure  12  during the subsequent processes and may be left with proper control of the RIE process  38 . 
     RIE  38  is preferably an O 2  and SO 2  RIE conducted at the following parameters: 
     a pressure of preferably from about 5 to 50 mTorr; 
     a power of preferably from about 100 to 500 W; 
     a temperature of preferably from about 20 to 60° C.; 
     an O 2  flow rate of preferably from about 20 to 200 sccm; 
     an SO 2  flow rate of preferably from about 10 to 80 sccm; 
     a He flow rate of preferably from about 40 to 80 sccm; and 
     a CF 4  flow rate of preferably from about 0 to 50 sccm. 
     Formation of Trench  44  Over the Remaining Via  24 ′ to Form a Dual Damascene Opening  46   
     As shown in FIG. 4, the trench pattern opening  40  within the etched PR layer  26 ′ is transferred to the lower third stop layer  22 ′ and second CVD low-k layer  20 ′ above the second stop layer  18  preferably by a dry etch process to form trench opening  44  over the remaining via opening  24 ′. PR portion  42  overlying the conductive structure  12  helps to protect the conductive structure  12  from etching damage. 
     The PR portion  42  and the remaining etched silylation PR layer  26 ′ with the outer, exposed areas  36  of upper etched portion  28 ′ of etched silylation PR layer  26 ′ are stripped away. 
     Trench opening  44  and remaining via opening  24 ′ together form dual damascene opening  46  that exposes at least a portion of conductive structure  12 . 
     Further processing may continue, including, for example, a planarized conductive dual damascene structure  48  within dual damascene opening  46  that is preferably comprised of a metal such as aluminum, copper or gold, for example. 
     Second Embodiment—CVD Photoresist Scheme 
     Initial Structure—Second Embodiment 
     The initial structure of the second embodiment is essentially the same as the initial structure for the first embodiment. That is FIG. 5 illustrates a structure  110  with an exposed conductive structure  112 . 
     Structure  110  is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer. 
     Conductive structure  112  is preferably comprised of a metal or metal alloy such as, for example, aluminum, copper, gold, etc., and may be a conductive plug or conductive line. 
     A first stop layer  114  is formed over structure  110  and conductive structure  112 . A first CVD low-k material layer  116  is formed over the first stop layer  114 . A second stop layer  118  is formed over the first CVD low-k material layer  116 . A second CVD low-k material layer  120  is formed over the second stop layer  118 . A third stop layer  122  is then formed over the second CVD low-k material layer  120 . 
     The first, second and third stop layers  114 ,  118 ,  122  are preferably formed of nitride, silicon nitride (SiN), silicon carbide (SiC) or silicon oxynitride (SiON); and are each preferably from about 300 to 600 Å thick and more preferably from about 400 to 600 Å. 
     The first and second CVD low-k material layers  116 ,  120  may be intermetal dielectric (IMD) layers and may be formed of Black Diamond™ (Applied Materials) or Coral™ (Novellus) and are more preferably formed of Black Diamond. The first and second CVD low-k material layers  116 ,  120  are preferably from about 3000 to 7000 Å thick and more preferably from about 4000 to 6000 Å. 
     As shown in FIG. 5, a via patterning and etching is performed through the third stop layer  122 , the second CVD low-k material layer  120 , the second stop layer  118 , the first CVD low-k material layer  116  and the first stop layer  114  to form via  124  exposing at least a portion of the conductive structure  112 . The via  124  patterning and etching may be performed by conventional methods and processes. 
     Formation of Undercoat PR Layer  126  and CVD PR  128   
     As shown in FIG. 6, an undercoat photoresist (PR) layer  126  is formed over the structure of FIG. 5, filling via  124 . The undercoat PR layer  126  is then hard-baked. 
     Undercoat PR layer  126  is preferably formed by spin coating and is preferably a DUV PR or I-line PR. Undercoat PR layer  126  is preferably formed to a height of from about 4000 to 8000 Å and more preferably from about 4000 to 6000 Å above the third stop layer  122 . 
     In a key step of the second embodiment and as shown in FIG. 6, a chemical vapor deposition (CVD) PR layer  128  is then formed over the undercoat PR layer  126  to a thickness of preferably from about 900 to 2600 Å and more preferably from about 1000 to 2500 Å. CVD PR layer  128  is preferably formed by a plasma enhanced chemical vapor deposit (PECVD) method. Preferably, methylsilane gas is deposited and then polymerized by a CVD method, and more preferably by a plasma enhanced chemical vapor deposition (PECVD) method at a low temperature of preferably from about 65 to 135° C. and more preferably about 150° C., to form a plasma polymerized methylsilane (PPMS) polymer CVD PR layer  128 . 
     Then, using optical trench mask  130  roughly centered over via  124  and having a width greater than via  124 , the PPMS PR layer  128  is exposed as at  132 , using optical trench mask  130  as a mask, and preferably using deep ultraviolet (DUV) light. DUV exposure  132  includes the presence of oxygen (O 2 ) which further networks the PPMS polymer comprising the exposed PPMS PR layer  128  into a glass-like siloxane (that is referred to as “PPMSO”) portions  134  that act as hard mask portions, and leaving an unexposed portion  136  of PPMS PR layer  128  substantially beneath trench mask  130 . 
     It is noted that by using PPMS PR layer  128 , undercoat PR layer  126  is not exposed to the DUV light  132  and therefore no carboxylic acid is formed within the undercoat PR layer  126  and thus there is no adverse interaction between the undercoat PR layer  126  and the exposed first and second CVD low-k material layers  116 ,  120  after the DUV exposure  132 . This eliminates the PR poison issue known to the inventors as discussed above as none of the photoresist adjacent to the exposed portions of the CVD low-k material layers  116 ,  120  is exposed to DUV. 
     Cl 2  Plasma Treatment/O 2  RIE 138 
     As shown in FIG. 7, Cl 2  plasma is used to remove the unreacted/unexposed PPMS PR portion  136  (i.e. develop into negative tone) at the following parameters: 
     a pressure of preferably from about 4 to 10 mTorr; 
     a source power of preferably from about 300 to 600 W; 
     a temperature of preferably from about 0 to 60° C.; 
     an HBr flow rate of preferably from about 80 to 150 sccm; 
     a Cl 2  flow rate of preferably from about 50 to 100 sccm; and 
     an He-O 2  flow rate of preferably from about 10 to 30 sccm. 
     Then, using hard mask PPMSO portions  134  of exposed PPMS PR layer  128  as masks, the structure of FIG. 6 is subjected to an O 2  reactive ion etch (RIE)  138  that etches away the undercoat PR 126 substantially beneath the now removed PPMS PR portion  136  down to the second stop layer  118  (forming a trench pattern opening  140  within the etched undercoat PR layer  126 ′ above the second stop layer  118 ) and a portion of the undercoat PR  126  within the via  124  but leaving a portion  142  of undercoat PR within the via  124  overlying the conductive structure  112 . The portion  142  of undercoat PR overlying the conductive structure  112  protects the conductive structure  112  during the subsequent processes and may be left with proper control of the O 2  RIE process  138 . 
     The O 2  RIE 138 also transforms the PPMSO portions  134  into low-density oxide forming low-density oxide portions  134 ′. 
     The O 2  RIE 138 is conducted at the following parameters: 
     a source power of preferably from about 600 to 950 W; 
     a pressure of preferably from about 4 to 10 mTorr; and 
     an O 2  flow rate of preferably from about 30 to 60 sccm. 
     Formation of Trench  144  Over the Remaining Via  124 ′ to Form a Dual Damascene Opening  146   
     As shown in FIG. 8, the trench pattern opening  140  within the etched undercoat PR layer  126 ′ is transferred to the lower third stop layer  122  and the second CVD low-k layer  120  above the second stop layer  118  preferably by a dry etch process to form trench opening  144  over the remaining via opening  124 ′. The dry etch process removes the low-density oxide portions  134 ′ (formerly PPMSO portions  134 ) so that the etched undercoat PR  126 ′ functions as a mask when etching the exposed third stop layer  122  and the then the second CVD low-k material layer  120  when forming trench opening  144 . 
     The undercoat PR portion  142  overlying the conductive structure  112  and the etched undercoat PR  126 ′ that functioned as a mask in forming trench opening  144  is then stripped away. 
     Trench opening  144  and remaining via opening  124 ′ together form dual damascene opening  146  that exposes at least a portion of conductive structure  112 . 
     Further processing may continue, including, for example, a planarized conductive dual damascene structure  148  within dual damascene opening  146  that is preferably comprised of a metal such as aluminum, copper or gold, for example. 
     Advantages of one or more Embodiments of the Present Invention 
     The advantages of one or more embodiments of the present invention include: 
     1. in-situ formation of protective layer at the bottom of via opening thus reducing the number of steps otherwise required to form such a protective layer; 
     2. interaction between DUV PR and CVD low-k material is prevented; and 
     3. better resolution is achieved due to the patterning occurring only at the upper thin layer. 
     While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.

Technology Classification (CPC): 7