Patent Abstract:
A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transistor to ground. The use of two feedback loops allows the design of a voltage regulator in which it small-signal impedance, as seen by a power rail, has a phase not less than −90 degrees. This mitigates interactions between the power rail and the voltage regulator that may lead to oscillations, without the need for a relatively large de-coupling capacitor. Other embodiments are described and claimed.

Full Description:
FIELD 
       [0001]    Embodiments of the present invention relate to electronic circuits, and more particularly, to voltage regulators. 
       BACKGROUND 
       [0002]    A large class of linear voltage regulators provides a regulated voltage by way of a feedback loop comprising an operational amplifier and a pass transistor. An example of a linear voltage regulator is illustrated in  FIG. 2 . As is well known, a negative feedback loop regulates the voltage at node  202  to match a reference voltage V REF , where the feedback loop is formed by the output port of amplifier A connected to the gate of pass transistor Q, and the drain of transistor Q connected to the positive input port of amplifier A. The reference voltage V REF  is applied at the negative input port to amplifier A. Load  204  is the circuit for which a regulated voltage is desired, and capacitor  204  is a de-coupling capacitor. Load  204  may be, for example, a circuit within a microprocessor. Particular examples include, but are not limited to, a phase locked loop, a delay locked loop, or a thermal sensor. 
         [0003]    Let Z REG  denote the small-signal impedance presented by the linear voltage regulator to voltage rail  204 . It has been observed that there may be an undesirable interaction between the supply voltage Vcc at voltage rail  204  and the linear voltage regulator of  FIG. 2 . In particular, it has been observed that if the phase of the impedance Z REG  falls below −90 degrees, there may be spontaneous oscillations at voltage rail  204 . This problem is more likely to worsen as the number of linear voltage regulators connected to voltage rail  204  increases, as for example in applications in which there are more than one microprocessor core or more than one I/O (Input/Output) channel. 
         [0004]    A linear voltage regulator of the type illustrated in  FIG. 2  is generally designed so that the poles of its closed-loop transfer function are the zeros of its impedance Z REG . This results in the phase of the impedance Z REG  being less than −90 degrees, unless the linear voltage regulator is designed to be over-damped. However, such an over-damped design is not necessarily trivial or desirable for some applications, as it generally requires a relatively large capacitor for compensation. Furthermore, such a relatively large capacitor results in a linear voltage regulator with a low operating bandwidth. A low operating bandwidth linear voltage regulator may need a large output de-coupling capacitor to provide adequate power supply rejection (PSR). But large output de-coupling capacitors are not necessarily desirable because of their size, and because of possible current leakage. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  illustrates an embodiment of the present invention. 
           [0006]      FIG. 2  is a prior art linear voltage regulator. 
           [0007]      FIG. 3  is the small-signal circuit model for the embodiment of  FIG. 1 . 
           [0008]      FIG. 4  illustrates plots of the magnitude and phase of the small-signal impedance for the model of  FIG. 3 . 
           [0009]      FIG. 5  illustrates a portion of a computer system utilizing embodiments of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0010]      FIG. 1  illustrates an embodiment of the present invention, which may be termed a dual path linear voltage regulator. A regulated voltage V REG  at node  102  is provided to load  104 . Load  104  may comprise a circuit, such as for example an analog circuit in which a well-regulated voltage is desired. In the embodiment of  FIG. 1 , a reference voltage V REF , applied at input port  106  of operational amplifier A 1 , sets the regulated voltage V REG . The dual path linear voltage regulator tracks V REF  and adjusts its output voltage V REG  so that these two voltages match. The reference voltage V REF  may be generated by any one of well-known circuits, such as for example by a band-gap reference circuit. 
         [0011]    Input port  106  is the inverting, or negative, input port of operational amplifier A 1 . Output port  108  of operational amplifier A 1  is connected to the gate of transistor Mn. In the embodiment of  FIG. 1 , transistor Mn is an nMOSFET (n-Metal Oxide Semiconductor Field Effect Transistor). The source of transistor Mn is grounded (connected to substrate  110 ). The drain of transistor Mn is connected to input port  112 , which is the non-inverting, or positive, input port of operational amplifier A 1 . The drain of transistor Mn is also connected to node  102  and to decoupling capacitor  120 . 
         [0012]    Output port  108  is connected to input port  114 , the non-inverting, or positive, input port of operational amplifier A 2 . Output port  116  is connected to the inverting, or negative, input port of operational amplifier A 2 . Operational amplifier A 2  is configured as a unity-gain buffer so that the voltage at output port  116  follows that of output port  108 . Output port  116  is also connected to the gate of transistor Mp. In the embodiment of  FIG. 1 , transistor Mp is a pMOSFET. The drain of transistor Mp is connected to node  102 , and the source of Mp is connected to voltage rail  118 . Transistor Mp may be referred to as a pass transistor. Capacitor  122  is used to insert a low bandwidth pole at the output of operational amplifier A 1 , and it also improves the PSR by enabling transistor Mp to better reject V CC  noise. 
         [0013]    With the drain of transistor Mp connected to positive input port  112 , there is a first feedback loop comprising operational amplifier A 1 , operational amplifier A 2 , and transistor Mp. With the drain of transistor Mn connected to positive input port  112 , there is a second feedback loop comprising operational amplifier A 1  and transistor Mn. This is the motivation for referring to an embodiment represented by  FIG. 1  as a dual path linear voltage regulator. 
         [0014]    In operation, if the voltage at node  102 , V REG , were to increase above its desired regulated value, V REF , then the output voltage at output port  108  would increase. Because operational amplifier A 2  is configured as a unity-gain buffer, the voltage at output port  116  would also increase, reducing the magnitude of the gate-to-source voltage of pass transistor Mp, causing pass transistor Mp to source less current to load  104 , and thereby counteracting an increase in voltage at node  102 . In addition, when the voltage at output port  108  increases, there is an increase in the gate-to-source voltage of transistor Mn. As a result, transistor Mn shunts current from node  102  to ground, further counteracting an increase in voltage at node  102 . Accordingly, transistor Mn may be referred to as a shunt transistor. 
         [0015]    For some embodiments, the operating bandwidth of the second feedback loop may be designed to be larger than that of the first feedback loop. For such embodiments, operational amplifier A 2  lowers the magnitude of the gate-to-source voltage of transistor Mp slower than the rate that operational amplifier A 1  increases the gate-to-source voltage of transistor Mn. 
         [0016]    If the voltage V REG  at node  102  were to decrease below V REF , then the output voltage at output port  108  would decrease, thereby increasing the magnitude of the gate-to-source voltage of pass transistor Mp, causing pass transistor Mp to source more current to load  104 , thereby counteracting a decrease in voltage at node  102 . In addition, a decrease in voltage at output port  108  below V REG  decreases the gate-to-source voltage of shunt transistor Mn, causing shunt transistor Mn not to shunt current to ground. If for some embodiments the operating bandwidth of the second feedback loop is larger than that of the first feedback loop, then amplifier A 2  would increase the gate-to-source voltage of transistor Mp slower than the rate that amplifier A 1  would decrease the magnitude of the gate-to-source voltage of transistor Mn. 
         [0017]    Transistor Mn shunts current from node  102  to ground when its gate-to-source voltage exceeds its threshold voltage. Although the shunting function provided by transistor Mn may degrade efficiency, the relatively fast response of the second feedback loop provided by amplifier A 1  in conjunction with transistor Mn allows for the use of a smaller output de-coupling capacitor than might be needed if the second feedback loop were not present. Letting Z REG  denote the small-signal impedance of the dual path linear voltage regulator as seen by voltage rail  118 , Z REG  is expected to have a phase not below −90 degrees. As a result, it is expected that output de-coupling capacitor  120  need not be as large as what might be needed if the second feedback loop were not present, and embodiments need not be over-damped in order for the phase of Z REG  not to fall below −90 degrees. Z REG  may be referred to as the regulator impedance. 
         [0018]    An expression for the regulator impedance as seen by voltage rail  118  may be derived from a small-signal circuit model for  FIG. 1 , which is shown in  FIG. 3 . In  FIG. 3 , the small-signal model for transistor Mn is represented by voltage-controlled current source  302  and small-signal resistor  304 , where gm n  is the small-signal transconductance of transistor Mn. The small-signal model for transistor Mp is represented by voltage-controlled current source  306  and small-signal resistor  308 , where gm p  is the small-signal transconductance of transistor Mp. The small-signal impedance for load  104  is represented by impedance  310 . Small-signal current source  312  is introduced to calculate the regulator impedance Z REG , where if v x  is the small-signal voltage at node  314  and i x  is the current provided by current source  312 , then Z REG =v x /i x . 
         [0019]    With the variables shown in  FIG. 3  representing the various corresponding small-signal currents and impedances as indicated in  FIG. 3 , an expression for Z REG  may be derived, which is given below. 
         [0000]    
       
         
           
             
               Z 
               REG 
             
             = 
             
               
                 
                   
                     
                       
                         
                           
                             ( 
                             
                               1 
                               + 
                               
                                 s 
                                 
                                   ω 
                                   lbw 
                                 
                               
                               + 
                               
                                 Ao 
                                 lbw 
                               
                             
                             ) 
                           
                         
                       
                       
                         
                           
                             
                               ( 
                               
                                 
                                   
                                     gm 
                                     n 
                                   
                                    
                                   
                                     r 
                                     op 
                                   
                                    
                                   
                                     R 
                                     x 
                                   
                                    
                                   
                                     Ao 
                                     hbw 
                                   
                                 
                                 + 
                                 
                                   
                                     ( 
                                     
                                       1 
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                                           ω 
                                           x 
                                         
                                       
                                     
                                     ) 
                                   
                                    
                                   
                                     ( 
                                     
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                                           ω 
                                           hbw 
                                         
                                       
                                     
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                                    
                                   
                                     ro 
                                     p 
                                   
                                 
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                                     R 
                                     x 
                                   
                                    
                                   
                                     ( 
                                     
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                                         s 
                                         
                                           ω 
                                           l 
                                         
                                       
                                     
                                     ) 
                                   
                                 
                               
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                             + 
                           
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         gm 
                         p 
                       
                        
                       
                         r 
                         op 
                       
                        
                       
                         R 
                         x 
                       
                        
                       
                         Ao 
                         hbw 
                       
                        
                       
                         Ao 
                         lbw 
                       
                     
                   
                 
               
               
                 
                   
                     
                       ( 
                       
                         1 
                         + 
                         
                           s 
                           
                             ω 
                             lbw 
                           
                         
                         + 
                         
                           Ao 
                           lbw 
                         
                       
                       ) 
                     
                   
                 
                 
                   
                     
                       
                         ( 
                         
                           
                             
                               gm 
                               n 
                             
                              
                             
                               r 
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                              
                             
                               R 
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                           + 
                           
                             
                               ( 
                               
                                 1 
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                                   s 
                                   
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                               ) 
                             
                              
                             
                               ( 
                               
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                         ) 
                       
                        
                       
                         ( 
                         
                           
                             
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                               p 
                             
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                               r 
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                           + 
                           1 
                         
                         ) 
                       
                     
                   
                 
               
             
           
         
       
     
         [0000]    The variables R x  and ω x  in the above expression are defined as: 
         [0000]    
       
         
           
             
               
                 R 
                 x 
               
               = 
               
                 
                   R 
                   L 
                 
                  
                 
                    
                    
                 
                  
                 
                   ro 
                   n 
                 
               
             
             , 
             
               
 
             
              
             and 
           
         
       
       
         
           
             
               ω 
               x 
             
             = 
             
               
                 
                   
                     ro 
                     n 
                   
                   + 
                   
                     R 
                     L 
                   
                 
                 
                   
                     ro 
                     n 
                   
                    
                   
                     R 
                     L 
                   
                    
                   
                     C 
                     d 
                   
                 
               
               . 
             
           
         
       
     
         [0000]    In the above-displayed expression, Ao hbw  is the open loop DC gain of operational amplifier A 1 , Ao lbw  is the open loop DC gain of operational amplifier A 2 , ω lbw  is the open loop bandwidth of operational amplifier A 2 , and ω hbw  is the open loop bandwidth of operational amplifier A 1 . 
         [0020]      FIG. 4  shows plots of the magnitude and phase of Z REG  for typical values substituted for the variables in the above-displayed expression for Z REG . As seen from the plots, the phase angle for Z REG  does not fall below −90 degrees. 
         [0021]    Embodiments of the present invention are expected to find wide applications. One such application is to regulate the voltage provided to one or more circuits in one or more microprocessor execution cores by utilizing one or more dual path linear voltage regulators.  FIG. 5  illustrates such an application, where a simplified, high-level diagram of a portion of a typical computer system is illustrated. In  FIG. 5 , microprocessor  502  communicates with chipset  504 , where chipset  504  provides communication to system memory  506  and other I/O components, represented by block  508 . Chipset  504  may comprise one or more distinct die, and memory  506  may represent a hierarchy of memory. Embodiments of the present invention may find application in microprocessor  502 , indicated as blocks  500 , as well as in other system components in  FIG. 5 . Applications of embodiments of the present invention are not limited to computer systems. 
         [0022]    Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. 
         [0023]    It is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected together by an interconnect (transmission line). In integrated circuit technology, the interconnect may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected together by polysilicon, or copper interconnect, where the length of the polysilicon, or copper interconnect, is comparable to the gate lengths. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON. 
         [0024]    It is also to be understood in these letters patent that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B. 
         [0025]    It is also to be understood in these letters patent that various circuit blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit blocks may still be considered connected to the larger circuit because the various switches may be considered as included in the circuit block.

Technology Classification (CPC): 6