Patent Abstract:
A feedback equalizer is provided that minimizes the critical path time in a multi-level modulation receiver. The critical path is reduced by parallel operation of some summation components of the feedback equalizer. The critical path is further reduced by pre-computing coefficients for the feedback equalizer. Further, the critical path is reduced using an adaptive feedback equalizer which uses parallelism or pre-computation to calculate the feedback equalization coefficients using an adaptation engine.

Full Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
   This patent application claims the benefit under Title 35, United States Code, section 119(e), of U.S. Provisional Patent Application Ser. No. 60/593,824 filed Feb. 17, 2005 and entitled “Feedback Equalizer for Communications Receiver,” by inventor Chia-Liang Lin, the entire subject matter of which is incorporated herein by reference. 

   COPYRIGHT NOTICE 
   This patent document contains copyrightable subject matter that may include (by way of example and not by way of limitation) computer software elements, source code, flow charts, screen displays, and other copyrightable subject matter. The following notice shall apply to these elements: Copyright© Realtek Semiconductor Corp., Hsinchu, Taiwan. All rights reserved. 
   LIMITED WAIVER OF COPYRIGHT 
   In accordance with 37 CFR section 1.71(e) a portion of the disclosure of this patent document may contain material to which a claim for copyright is made. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the United States Patent and Trademark Office patent file or records, as long as the above Copyright Notice remains legible on all copies. The copyright owner reserves all other national and international copyright rights. 
   FIELD OF THE INVENTION 
   The present invention relates to communication systems and in particular to feedback equalization in a multi-level modulation communications system to combat channel dispersion. 
   BACKGROUND OF THE INVENTION 
   A feedback equalizer (FBE) has been known in prior art to compensate for the channel dispersion in a communications system. A typical prior art communication system  100  is shown in  FIG. 1 . The communication system  100  consists of a transmitter  101 , a channel  102 , and a receiver  103 . A typical transmitter  101  includes the following components: an encoder  105  that processes the transmit data (TX data) using a certain encoding scheme, a digital-to-analog converter (DAC)  106  that converts the encoded data into analog voltage waveform, and a low-pass filter (LPF)  107  that filters out the high frequency noises. A typical communications receiver  103  includes the following components: an amplifier (AMP)  108  that compensates for the insertion loss suffered by the transmitted waveform due to the channel  102 , a low-pass filter (LPF)  109  that filters out the high-frequency noises, an analog-digital converter (ADC)  110  that converts the analog voltage into digital samples, a feed-forward equalizer (FFE)  111  and a feedback equalizer (FBE)  115  that compensates for the dispersion suffered by the transmitted waveform due to the channel  102 , a summer  112 , a decision device  113  which determines the most likely encoded TX data transmitted from the transmitter  101 , a decoder  114  which performs the decoding and recovers the original TX data. A typical receiver  103  also includes a timing control unit  116  and a voltage controlled oscillator (VCO)  117  or a number controlled oscillator (NCO)  117 , which generates a clock signal that is in synchronization with the clock used by the remote transmitter  101 . The local clock signal is provided to sample the analog waveform at the input of the ADC  110 , and also to synchronize all the digital circuits in the receiver  103 . 
   The above described communication system of  FIG. 1  applies to most communication systems that utilize multi-level modulation schemes. For example, PAM-4 (4-level pulse amplitude modulation) is a multi-level modulation scheme that converts the encoded TX data  202  into a 4-level analog waveform  201  as shown in  FIG. 2 . For a binary signaling scheme, for example, NRZ (non-return-to-zero), there is no need for using sophisticated ADC  110  and DAC  106  devices to handle the multi-level signaling, and the communication system  100  can be simplified, as shown in  FIG. 3  as a modified communications system  300 . Here, a line driver  304  generates either a high or low voltage depending on whether the encoded TX data (digital data to be transmitted) is 1 or 0. In the receiver  303 , the decision unit, timing control unit, and VCO/NCO (voltage controlled oscillator or number controlled oscillator) of  FIG. 1  are consolidated in a unit known as clock data recovery (CDR)  309 , which reproduces the clock signal used by the remote transmitter  301  and recovers the encoded TX data sent by the remote transmitter  301  over channel  302 . Remote transmitter  301  includes encoding  305 . Receiver  303  also includes amp  306 , FFE  307 , summer  308 , FBE  311 , and decoding  310 . The recovered data is labeled as RX data in  FIG. 3 . 
   A prior art feedback equalizer (FBE)  400  is shown in  FIG. 4 . Here, we show a 3-tap FBE  401 . The M-level quantizer  402  is a decision device that determines the most likely level. The quantizer output is latched and synchronized by the local recovered clock signal. The quantizer output D n , also known as the decision, is provided as input to the FBE  401 . Inside the FBE, there are two Data Flip Flop (DFF) latches  405  and  406 , which store the previous two decisions, D n-1 , and D n-2 . The three decisions (current decision D n  from the quantizer  402 , plus the previous two decision D n-1 , and D n-2 ) are scaled by three respective gain factors C 1 , C 2 , and C 3 , and the results are summed at summation point  407  to generate the FBE output Y n . The FBE output Y n  is subtracted from the input X n  at summation point  404  resulting in the modified input to the M-level quantizer  402  and thus forming a feedback loop. 
   One problem with the prior art FBE techniques is the critical path in the feedback loop. The critical path is the longest time delay path through a circuit that, in effect, sets the limit on the maximum operating speed of a circuit. In the example of  FIG. 4 , the current decision from quantizer output D n  needs to be scaled by the gain factor C 1 , added at summation point  407  to the scaled outputs from the previous decisions two decision D n-1 , and D n-2 , and then subtracted from the quantizer input at summation point  404 , and the result needs to be settled before the rising edge of next clock cycle. The output D n  is coupled to decoder  403 . For example, in 1 GHz operation of the feedback equalizer of  FIG. 4 , the contribution Y n  needs to settle within 1 nanosecond (1 clock cycle at 1 GHz). This high speed equalization circuit implementation may be very difficult to achieve. 
   An implementation of a prior art FBE for NRZ receiver is shown in  FIG. 5 . Note that NRZ is a binary signaling system employing two levels of amplitude, for example +1 and −1. The 2-level quantizer  502  of  FIG. 5  can be implemented as a comparator  508  comparing the input, which is X n −Y n , versus the reference level 0. If the input is greater than the reference level 0, the comparator outputs +1. If the input is less than the reference level 0, the comparator outputs −1. In other words, the comparator outputs +1 if X n  is greater than Y n , otherwise it outputs −1. The comparator output is synchronized by the local recovered clock using a DFF  509 , resulting in the current decision D n , which is fed as input to the FBE  501 , which includes DFF  505  and DFF  506 . The output D  n  is coupled to decoder  503 . The critical path problem in this example is the same as described above for  FIG. 4 . What is needed is a FBE that alleviates the critical path problem. 
   SUMMARY OF THE INVENTION 
   Methods, apparatus and systems for a new method of implementing a feedback equalizer that minimizes the critical path time in a multi-level modulation receiver. The critical path is reduced by parallel operation of some summation components of the feedback equalizer. The critical path is further reduced by pre-computing coefficients for the feedback equalizer. Further, the critical path is reduced using an adaptive feedback equalizer that uses parallelism or pre-computation to calculate the feedback equalization coefficients using an adaptation engine. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, which are not necessarily drawn to scale, like numerals describe substantially similar components throughout the several views. Like numerals having different letter suffixes represent different instances of substantially similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. 
       FIG. 1  illustrates a typical prior art communication system. 
       FIG. 2  illustrates a prior art 4-level pulse amplitude modulation analog waveform and the corresponding digital data. 
       FIG. 3  illustrates a prior art communications system for a binary signaling scheme for non-return-to zero (NRZ) modulation. 
       FIG. 4  illustrates a prior art 3-tap feedback equalizer used with an M-level quantizer. 
       FIG. 5  illustrates a prior art feedback equalizer for non-return-to zero (NRZ) receiver with a 2-level quantizer. 
       FIG. 6  is a block diagram illustrating a 3-tap feedback equalizer used with an M-level quantizer in accordance with some embodiments of the present invention. 
       FIG. 7  is a block diagram illustrating a 3-tap feedback equalizer used with a 2-level quantizer in accordance with some embodiments of the present invention. 
       FIG. 8  is a block diagram illustrating a shortened critical path for a 2-level modulation communication system. 
       FIG. 9  is a block diagram illustrating an M-level feedback equalization for an M-level modulation communications system. 
       FIG. 10  is a block diagram illustrating a look-ahead equalization architecture using 2-level NRZ modulation as an example. 
       FIG. 11  is a block diagram illustrating a differential charge pump based adaptation engine for equalization in a multi-level modulation communication systems. 
       FIG. 12  is a block diagram illustrating a switch coefficient adaptation engine for equalization in a multi-level modulation communication systems. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. 
   In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. Additionally, in this description, the phrase “exemplary embodiment” means that the embodiment being referred to serves as an example or illustration. While the specification described several example embodiments of the invention considered best modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. 
     FIG. 6  is a block diagram illustrating a 3-tap feedback equalizer  600  used with an M-level quantizer in accordance with some embodiments of the present invention. Instead of subtracting the FBE output Y n  from the input to the quantizer input at a summation point, as was shown in the example of  FIG. 4  above, the embodiment shown in  FIG. 6  adjusts the quantizer levels by an offset of Y n . Thus, FBE  601  output Y n  as shown in  FIG. 6  is applied to offset input of the quantizer  602 . In this embodiment, the quantizer adjusts its internal reference level(s) according to the offset provided by the FBE  601 , while the input X n  is kept intact. FBE  601  includes DFF  605 , DFF  606 , and summer  607 . The output D n  is coupled to decoder  603 . In this embodiment, the offset in the quantizer reference level is equivalent to a negative offset at the input so the effect of offsetting the quantizer level(s) is equivalent to offsetting the input. This improves the speed of the circuit of  FIG. 6  by minimizing the critical path length through the circuit. 
   An exemplary embodiment of a FBE for non-return-to zero (NRZ) modulation according to some embodiments of the present invention is shown in  FIG. 7 . As described above in connection with the discussion of  FIG. 5 , NRZ is a binary or 2-level signaling system employing two levels of amplitude for which we will assign amplitude levels of +1 and −1 for this example. The 2-level quantizer  702  of communication system  700  of  FIG. 7  is implemented as a comparator  708  comparing the input X n  to the output Y n , where 2-level quantizer  702  includes a DFF  709 . Y n  is output from FBE  701  that includes DFF  705  and DFF  706 . In contrast to subtracting Y n  from X n  at a summation point and then comparing the result with a reference level 0 as shown in  FIG. 5 , the embodiment of the present invention shown in  FIG. 7  directly compares X n  with Y n . In other words, the reference level is offset from 0 to Yn. The output D n  is coupled to decoder  703 . The result from the quantizer is similarly accurate or the same but the critical path in  FIG. 7  is shortened because the original four-operand summation operation of  FIG. 5  (utilizing summation points  507  and  504 ) is replaced by a three-operand summation  707  in  FIG. 7 . 
     FIG. 8  is another embodiment of the present invention that results in a shorter critical path for a 2-level modulation communication system  800 . The critical path is further reduced by distributing the feedback signals to two summation points  810 ,  811  operating substantially in parallel as shown in  FIG. 8 , and presenting the two summation results to the comparator input and the quantizer offset input, respectively. In this embodiment, the output of the FBE  801  is effectively Y n =C 1 ×D n +C 2 ×D n-1 +C 3 ×D n-2 . As shown in  FIG. 8 , among the FBE outputs, the component C 3 ×D n-1  is subtracted from the input X n  at summation point  810  while the remaining amount C 1 ×D n +C 2 ×D n-1  summed at summation point  811  is provided as an offset to the reference level input for comparator  808  of quantizer  802  that includes DFF  809 . The output D n  is coupled to FBE  801  that includes DFF  805  and DFF  806 . The output D n  is also coupled to decoder  803 . The result is still accurate and the same, yet the critical path is further reduce to two substantially parallel two-operand summations. 
   An M-level generalized embodiment of feedback equalization of communication system  900  in accordance with some embodiments of the present invention is shown in  FIG. 9 . In this embodiment, instead of generating a single FBE output Y n  and subtracting it from the input X n , the FBE  901  decomposes Y n  into two outputs W n  and Z n , where Y n =W n +Z n . Between the two FBE outputs, W n  is provided to the M-level quantizer  902  as offset to its internal comparator(s), and Z n  is subtracted from the input X n  at summer  912 . The quantizer output will be exactly the same as that in the prior art examples described above, but the critical path is substantially reduced and minimized by choosing an appropriate decomposition of Y n  into W n  and Z n . The output D n  is coupled to decoder  903 . 
   To further reduce the critical path in FBE, a look-ahead architecture is utilized in some embodiments of the present invention. An exemplary embodiment of a look-ahead architecture  1000  is given in  FIG. 10  using NRZ as an example (2-level modulation), although the look-ahead architecture can be generalized to multi-level modulation for one skilled in the art upon studying the present specification.  FIG. 10  shows an example of a 3-tap FBE  1001  where the FBE output is Y n =C 1 ×D n +C 2 ×D n-1 +C 3 ×D n-2 . FBE  1001  includes DFF  1005 , DFF  1006 , and summer  1015 . We can apply the C 1 ×D n  term as the offset to the quantizer  1002 , and the remaining term (C 2 ×D n-1 +C 3 ×D n-2 ) as the offset to the input X n  at summation point  1014 . However, instead of using the same clock for both the quantizer  1002  and the FBE  1001 , we use two clocks: clock  1  and clock  2 . Both clocks are synchronized to each other, but the phase of clock  2  is ahead of the phase of clock  1 . In this manner, the critical path is the contribution of the C 1 ×D n  term, because it is triggered by clock  1  (which is trailing clock  2 ). Clock  2  is used for triggering the (C 2 ×D n-1 +C 3 ×D n-2 ) term. For 2-level modulation such as NRZ, D n  has two possible values: +1 and −1, and there are two possible comparator offsets: C 1  and −C 1 , which depend on the value D n . In this embodiment, the critical path is reduced by comparing (at parallel operating comparators  1016  and  1017 ) the input upfront at summation point  1014 , which is X n −(C 2 ×D n−l +C 3 ×D n-2 ) compared to the two possible reference levels: C 1  and −C 1 . A multiplexer  1018  is used to choose between the two parallel comparator outputs based on the decision D n . The critical path caused by the computation of the C 1 ×D n  term is then removed, because the two possible outcomes of C 1 ×D n  and therefore the two possible comparator outputs have been pre-computed. The output D n  is coupled to decoder  1003 . 
   In the embodiment of a multi-level quantizer with a look-ahead architecture, an M-level quantizer can be implemented as (M- 1 ) comparators, having reference levels L 1 , L 2 , . . . , and L M-1 . The exemplary embodiments of binary (2-level) quantizers described above can be generalized to an M-level quantizer, wherein each of the (M- 1 ) comparators adjusts its respective reference levels by the amount provided by the FBE. The look-ahead architecture can also be applied by pre-computing the input versus all possible reference values and then selecting the correct comparator output using the decision D n    
   In an embodiment of an adaptive feedback equalizer, the FBE coefficients (C 1 , C 2 , and C 3 , etc) can be adapted by an adaptation engine. The adaptation algorithms, for example LMS (least mean square) are well known to those skilled in the art and thus not described here. In general, an adaptation algorithm adapts the coefficient, for example C 2 , in the following manner
 
 C 1 (next)   =C 1 (current) ±Δ
 
   Here, Δ is the increment (or decrement) to the coefficient. Several implementation schemes for the adaptation of the FBE coefficients in embodiments of the present invention are further presented here. For example, and not by way of limitation, a charge pump based adaptation or a switch coefficient adaptation algorithm may be used for the adaptation engine. 
     FIG. 11  shows a differential charge pump based adaptation  1100 . The adaptation logic  1130  receives D n  from the decision device and generates two control signals: UP and DN (for up and down, respectively). When UP=1 and DN=0, a current of I + is sourcing into the capacitor C. The voltage across C, which is C 2   + -C 2   − is increased accordingly. When UP=0 and DN=1, a current of I − is sinking from the capacitor C. The voltage across C, which is C 2   + −C 2   − is decreased accordingly. When UP=DN=0, no current is sourcing to or sinking from the capacitor C, therefore the voltage across C remains unchanged. The differential voltage C 2   + and C 2   − , which forms the effective feedback coefficient C 2  of the FBE, is thus adapted according to the control from the adaptation logic. Here, a common mode feedback circuit (CMFB)  1131  is used to establish the common mode or mean value of C 2   + and C 2   − . The mean value of C 2   + and C 2   − is estimated and compared to a desired CM (common mode) reference. The error between the mean value and CM ref is used to control the currents I + and I − , until the mean value reaches the desired reference. 
   A switch coefficient adaptation  1200  according to some embodiments of the present invention is shown in  FIG. 12 . Here, the coefficient C 2  is limited to only N pre-defined levels, such as C 2   (1) , C 2   (2) , . . . , and C 2   (N) . Again, the adaptation logic  1230  receives D n  from the decision device and generates two control signals: UP and DN (for UP and DOWN, respectively). An up/down counter  1260  increments if UP=1 and DN=0, decrements if UP=0 and DN=1, and remains unchanged for any other combined value of UP and DN. The up/down counter  1260  also saturates when it reaches a pre-determined maximum value, or a pre-determined minimum value. The counter output is quantized by N-level quantizer  1250  into one of the N possible values from 1 to N. The quantizer output is provided as the selection control input to multiplexer  1240  to select one of the N pre-defined levels of the coefficient C 2 . Thus, this embodiment also generally operates for multi-level modulation schemes. 
   CONCLUSION 
   Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the invention includes any other implementations in which the above structures, apparatus, systems, method and computer-readable media are used.

Technology Classification (CPC): 7