Patent Abstract:
A surge energy transfer circuit comprises a surge protection device, gas tube, inductor and high voltage capacitor for significantly reducing surge energy entering a power facility, lowering a remnant surge voltage to convert the surge energy in a voltage form. The converted voltage is superimposed to an operating power to slightly cause a rise of a peak value of the operating voltage. After the surge energy is converted in tens of mS, the operating power returns to a normal voltage value. Accordingly, the lifetime of the surge protection device can be extended and the surge immunity of the power facility can be improved to normal under surge interference situations.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a surge energy transfer circuit related to surge suppression techniques, and more particularly to an integrated circuit that can not only absorb surge energy but also convert the remaining surge energy into usable voltage form that also completely protects power facilities. 
         [0003]    2. Description of the Related Art 
         [0004]    Surge vulnerability interference arises from the large energies involved, making it a major source of surge interference. Lighting flash surge (LFS) is a typical source of surge interference. As a practical matter, power facilities are prone to failure when confronted with LFS due to insufficient surge protection. 
         [0005]    As for adequate surge protection schemes used for securing normal operations of power facilities, many patents have been disclosed, such as U.S. Pat. No. 5,353,189 “Surge protector for vehicular traffic monitoring equipment”, U.S. Pat. No. 5,617,284 “Power surge protection apparatus and method”, U.S. Pat. No. 5,038,245 “Method and apparatus for suppressing electrical transients”, U.S. Pat. No. 4,677,518 “Transient voltage surge suppressor”, U.S. Pat. No. 4,584,622 “Transient voltage surge suppressor”, and the like. All of these patents basically employ a structure that emphasizes on the use of a clamping voltage or remnant surge voltage suppression while lacking an adequate consideration of processing surge energy. 
         [0006]    Remnant surge voltage is not the main cause leading to power facility failures. Remnant surge energy generated by a residual current flowing in the power equipment must be taken into account as well. According to ANSI/IEEE C62.41 standard “Recommended Practice on Characterization of Surges in Low-Voltage (1000 V and Less) AC Power Circuits”, outdoor power facilities are classified as C category devices for surge interference. A combination waveform surge test in accordance with the C3 category is 20 kV 1.2/50 μSec and 10 kA 8/20 μSec. The energy generated by the combination waveform surge can go up to more than 1,000 Joules and easily destroy power facilities. 
         [0007]    The reason that methods of the prior art are ineffective in processing surge energy lies in using circuits built around a surge protection device, a gas tube choke, to process the surge and targeted at reducing the remnant surge voltage of the power supply end of power facilities. However, as the current withstanding capability of the choke is low, there are no methods explaining how to reduce the remnant surge energy of the power supply end of power facilities. In fact, methods or techniques for reducing remnant surge voltage fail to effectively process surge energy, with the result that surge energy may still easily destroy power equipment. 
         [0008]    To overcome the shortcomings of the prior, the inventor has disclosed an effective alternative in US Patent Application No. 2009/0109585 A1, entitled “Series surge suppression structure”, that is, a method that takes the clamping voltage and energy storage into account, to significantly reduce remnant surge voltage and remnant energy entering power facilities, thereby achieving a superior protection result. 
         [0009]    In pursuit of constant betterment, a surge energy transfer circuit is further developed to absorb and transfer surge energy by means of a parameter adjustment design, significantly lowering the surge energy entering power facilities and reducing remnant surge voltages, and ensuring to substantially protect power facilities and enhance surge immunity within power facilities. 
       SUMMARY OF THE INVENTION 
       [0010]    An objective of the present invention is to provide a surge energy transfer circuit that not only absorbs surge energy but also converts the remaining surge energy into a usable form to thoroughly protect power facilities. 
         [0011]    To achieve the foregoing objective, a surge energy transfer circuit has an input terminal, an output terminal, an energy absorption unit, a surge energy transfer unit, a surge energy charge and discharge unit and an equipotential grounding unit. 
         [0012]    The surge absorption unit is connected to the input terminal and has two surge protection devices (SPD) for absorbing a percentage of input surge energy. 
         [0013]    The surge energy transfer unit is connected to the surge absorption unit, and is formed by at least two inductors having an identical inductance or at least two groups of inductors having an identical inductance for temporarily storing a remaining percentage of the input surge energy and converting the remaining percentage of the input surge energy into a usable voltage, in which the percent of the converted surge energy out of the input surge energy is equal to the percent of a figure obtained by subtracting the input surge energy absorbed by the surge absorption unit from the input surge energy out of the input surge energy. 
         [0014]    The surge energy charge and discharge unit is connected to the surge energy transfer unit and the output terminal, and has at least one high voltage capacitor or at least one group of high voltage capacitors to charge and discharge the voltage converted from the remaining percentage of the inputted surge energy, in which a time duration elapsing for charging or discharging is determined by a magnitude of the selected high voltage capacitor. 
         [0015]    The equipotential grounding unit is connected to the surge absorption unit, the surge transfer unit, the surge energy charge discharge unit, the input terminal and the output terminal, and has at least two SPDs having identical characteristics so as to maintain a constant voltage at the output terminal when the input surge energy is coupled to ground, thereby significantly reducing the input surge energy and a remnant surge voltage represented by the converted form of voltage by serially connecting a circuit formed by the foregoing units to a path through which a surge passes. 
         [0016]    The surge energy transfer circuit has the following advantages: 
         [0017]    1. The SPD, inductors and high voltage capacitors are employed to reduce the remnant surge voltage, convert surge energy into a voltage form superimposed on the operating power to slightly increase the operating voltage. Given this approach, the lifetime of the SPD is extended and the surge immunity of power facilities is also increased. 
         [0018]    2. The SPD and gas tube are serially connected with the input terminal to form a two-stage surge suppression unit that effectively enhances surge suppression capabilities. 
         [0019]    3. A two-port structure, one port being the input terminal and the other being the output terminal for protecting power facilities, protects the power facilities by way of a serial connection. 
         [0020]    4. The input terminal is connected with an external power source, and the output terminal is connected to a power facility. The surge energy transfer circuit can be serially connected to an external wire and the power facility to form a surge energy transferring means, thereby substantially increasing the surge immunity of power facilities. 
         [0021]    More importantly, adopting the present invention not only converts surge energy into a usable voltage form and calculates the operating voltage rise range and the lasting time duration, but also builds products in compliance with customized demand. Accordingly, the present invention can be extensively applied to various types of power facilities to effectively avoid surge interference and keep power facilities operating normally. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]      FIG. 1  is a functional block diagram of a surge energy transfer circuit in accordance with the present invention; 
           [0023]      FIG. 2  is a circuit diagram of the surge energy transfer circuit in  FIG. 1 ; 
           [0024]      FIG. 3  is a test diagram showing normal mode coupling for the surge energy transfer circuit in  FIG. 1 ; 
           [0025]      FIG. 4  is a test diagram showing common mode coupling to ground for the transfer circuit in  FIG. 1 ; 
           [0026]      FIG. 5  is a circuit diagram of a multi-stage circuit composed of multiple surge energy transfer circuits in  FIG. 2 ; 
           [0027]      FIG. 6  is a perspective view showing different circuit modules formed by the surge energy transfer circuit in  FIG. 2 ; 
           [0028]      FIG. 7  is a perspective view showing the circuit modules in  FIG. 6  having a respective cover; 
           [0029]      FIG. 8  is a functional block diagram of a three-phase Y-connected product built with three modules shown in  FIGS. 6 and 7 ; and 
           [0030]      FIG. 9  is a functional block diagram of a three-phase Δ-connected product built with three modules shown in  FIGS. 6 and 7 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0031]    The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed. 
         [0032]    With reference to  FIGS. 1 and 2 , a surge energy transfer circuit  10  in accordance with the present invention has an input terminal  12 , an output terminal  34 , a surge absorption unit  1 , a surge energy transfer unit  2 , a surge energy charge and discharge unit  3 , and an equipotential grounding unit  4 . 
         [0033]    The surge absorption unit  1  is connected to the input terminal  12 , and includes two or more surge protection devices (SPD)  11  having functionally identical characteristics and serving to absorb a percent of the input surge energy. Additionally, to facilitate to mark reference numerals in the description while not disobeying word meaning, the relevant SPD is relocated ahead of the surge protection device  11 . 
         [0034]    The surge energy transfer unit  2  is connected to the surge absorption unit  1 , and includes at least two inductors  21  having an equal inductance or two groups of inductors  21  having an equal inductance (despite two inductors being illustrated in  FIG. 2 , the number of inductors is not so limited when the surge energy transfer unit is implemented) for temporarily storing a remaining percentage of the input surge energy exceeding a specific percentage thereof and for converting the remaining percentage of the input surge energy into a usable voltage form, in which the percentage of the converted surge energy out of the entire input surge energy is equal to the percent of the figure subtracting the surge energy absorbed by the surge absorption unit  1  from the input total surge energy out of the entire input surge energy. 
         [0035]    The surge energy charge and discharge unit  3  is connected to the surge energy transfer unit  2  and an output terminal  34 , and includes at least one high voltage capacitor  31  or at least one group of high voltage capacitors (despite a high voltage capacitor illustrated in  FIG. 2 , the number of high voltage capacitors is not so limited when the surge energy charge and discharge unit is implemented) to charge and discharge the voltage converted from surge energy, in which the time duration for charging or discharging is determined by the magnitude of the selected high voltage capacitor  31 . 
         [0036]    The equipotential grounding unit  4  is connected to the surge absorption unit  1 , the surge transfer unit  2 , the surge energy charge discharge unit  3 , the input terminal  12  and the output terminal  34 , and includes at least two SPDs  41  having functionally identical characteristics so that the surge energy transfer circuit can generate an equipotential effect to a surge coupled through ground. 
         [0037]    With reference to  FIGS. 1 and 2 , when implemented, the surge energy transfer circuit  10  may have a two-port structure. One port is the input terminal  12  connected with a power source or a signal line, and the other port is the output terminal  12  serving as a protection terminal for a power facility. 
         [0038]    The two or two groups of inductors  21  are parallelly connected between the input terminal  12  and the output terminal  34 . The one or one group of high voltage capacitors  31  is/are connected with one end of each of the two inductors  21  that are connected to the output terminal  34 . The surge absorption unit  1  has two SPDs  11  crossly connected with the two inductors  21 . Two ends of each of the two SPDs  11  are respectively connected to one end of one of the two inductors  21  and one end of the other of the two inductors  21 . The surge absorption unit  1  is intersected with the two inductors  21  at nodes C 1 , C 2  adjacent to the input terminal  12  and nodes C 3  and C 4  adjacent to the output terminal  34 . The equipotential grounding unit  4  has four SPDs  41  having functionally identical characteristics. Each of the four SPDs  41  is connected between each of the four nodes C 1 , C 2 , C 3 , C 4  and ground. 
         [0039]    When being implemented, the surge energy transfer circuit  10  further includes a SPD  51  and a gas tube  52  serially connected to the input terminal  12  to constitute a two-stage surge suppression structure for higher surge suppression effect. 
         [0040]    Given the foregoing structure, the surge energy transfer circuit  10  can be serially connected between an external connection wire and a power facility to create a surge energy transfer and protection effect, thereby substantially reducing the surge energy that enters the power facility to maintain normal operations of the power facility and extend the life duration of the power facility. Specifically, the life durations of the SPDs  11 ,  41 ,  51  are extended and the surge immunity of the power facility is enhanced so that the power facility can keep operating when encountering surges from the environment. 
         [0041]    The present invention further includes a method for how to calculate surge energy with a voltage form converted from the surge energy so as build a practical product in accordance with a customized voltage rise margin and lasting time duration. 
         [0042]    With reference to  FIG. 2 , the surge energy transfer circuit  10  has three SPDs  11 ,  41 ,  51 , a gas tube  52 , an inductor  21  and a high voltage capacitor  31 . The converted surge energy entering the power facility and the resulting suppression effect can be expressed by the following equations. 
         [0043]    The SPDs  11 ,  41 ,  51  used in the mathematical derivation of the method in accordance with the present invention are designed based on various clamping voltages V clamping . The higher the V clamping  is, the lower a residual current I r  flowing through the SPD  11  is, and the lower the V clamping  is, the higher the residual current I r  flowing through the SPD  11  is. The mathematical derivation of the method of the present invention adopts a design framework letting values of residual currents flowing through the SPD between C 1 , C 4  be k, and a value of a residual current flowing through the inductor  21  be 1−k, in which the value of k is in a range from 0.1 to 0.9. 
         [0044]    1. With reference to  FIGS. 2 and 3 , when an operating voltage is applied to the input terminal  12  and a vulnerability interference surge enters the input terminal  12 , normal mode coupling occurs. 
         [0045]    Given a voltage V 34  of the output terminal  34  of the surge energy transfer circuit  10  for protecting the power facility, energy E L  is stored in two inductors  21 , and an inductance L and a voltage V L  of the inductor  21 , an energy E (L)  is momentarily stored in the inductor  21  and a transient voltage V (L)  of the inductor  21  when a surge current I L  flows through the inductor  21  can be respectively expressed as follows: 
         [0000]        E   (L) =2×(½)× L ( I   L ) 2   =L [(1− k )× I   r ] 2  
 
         [0000]        V   (L)   =L ( dI   L   /dt )=(1− k )× L ( dI   r   /dt )
 
         [0046]    A remnant surge voltage of the output terminal  34 , V r , is expressed by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           r 
                         
                         = 
                         
                           
                             V 
                             clamping 
                           
                           - 
                           
                             V 
                             
                               ( 
                               
                                 △ 
                                  
                                 
                                     
                                 
                                  
                                 L 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             V 
                             clamping 
                           
                           - 
                           
                             
                               ( 
                               
                                 1 
                                 - 
                                 k 
                               
                               ) 
                             
                             × 
                             
                               L 
                                
                               
                                 ( 
                                 
                                   
                                      
                                     
                                       I 
                                       r 
                                     
                                   
                                   / 
                                   
                                      
                                     t 
                                   
                                 
                                 ) 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0047]    where k is in a range of 0.1 to 0.9. 
         [0048]    As known from equation (1), the magnitude of the inductor  21  (L) is inversely proportional to the remnant surge voltage Vr. The less the remnant surge voltage decreases when the value of the inductor  21  (L) increases, and increases when the value of the inductor  21  (L) decreases. By varying the magnitude of the inductor  21  (L), the value of the remnant surge voltage Vr can be precisely controlled. Such an approach has a more definite and substantial suppression effect than conventional surge voltage suppression approaches. 
         [0049]    After a residual current passes through the inductor  21 , energy E (L)  momentarily stored in the inductor  21  is released to the high voltage capacitor  31  and the SPD  11  connected to C 3  and C 2 . A k proportion of the residual current flows through the SPD  11  connected to C 3  and C 2 . The remaining (1-2 k) proportion of the residual current flows through the high voltage capacitor  31 . The voltage increment of the output terminal  34 , V (34) , is expressed by: 
         [0000]        V   (34) =(1 /C )∫(1−2 k ) I   r   dt   (2)
 
         [0050]    where C is a value of the high voltage capacitor and k is in a range of 0.1 to 0.9. 
         [0051]    As indicated by Equation (2), the voltage increment V (34)  is reversely proportional to the value C of the high voltage capacitor  31 . The V (34)  decreases when the value C of the high voltage capacitor  31  increases, and increases when the V (34)  decreases. 
         [0052]    A power frequency is a frequency constituted by the inductor  21  and the high voltage capacitor  31 . Thus, after the residual current passes through the output terminal  34 , the transient total voltage of the output terminal  34  rises to V T    
         [0000]    
       
      
       V 
       T 
       =V 
       34 
       +V 
       (34)  
      
     
         [0053]    The transient total energy Ec momentarily stored in the high voltage capacitor connected with the output terminal  34  can be expressed as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     E 
                     c 
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       CV 
                       c 
                       2 
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       E 
                       34 
                     
                     + 
                     
                       E 
                       
                         ( 
                         △34 
                         ) 
                       
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       
                         ∫ 
                         
                           t 
                           0 
                         
                         
                           t 
                           1 
                         
                       
                        
                       
                         
                           ( 
                           
                             
                               V 
                               34 
                             
                             × 
                             
                               I 
                               34 
                             
                           
                           ) 
                         
                          
                         
                            
                           t 
                         
                       
                     
                     + 
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             2 
                              
                             k 
                           
                         
                         ) 
                       
                        
                       
                         
                           ∫ 
                           
                             t 
                             0 
                           
                           
                             t 
                             1 
                           
                         
                          
                         
                           
                             ( 
                             
                               
                                 V 
                                 
                                   △ 
                                    
                                   
                                       
                                   
                                    
                                   34 
                                 
                               
                               × 
                               
                                 I 
                                 r 
                               
                             
                             ) 
                           
                            
                           
                              
                             t 
                           
                         
                       
                     
                   
                 
               
             
           
         
       
     
         [0054]    where t 0 -t 1  is a lasting time duration of a waveform of the residual current I r . 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             2 
                              
                             k 
                           
                         
                         ) 
                       
                        
                       
                         
                           ∫ 
                           
                             t 
                             0 
                           
                           
                             t 
                             1 
                           
                         
                          
                         
                           
                             ( 
                             
                               
                                 V 
                                 
                                   △ 
                                    
                                   
                                       
                                   
                                    
                                   34 
                                 
                               
                               × 
                               
                                 I 
                                 r 
                               
                             
                             ) 
                           
                            
                           
                              
                             t 
                           
                         
                       
                     
                     = 
                     
                       
                         
                           1 
                           2 
                         
                          
                         
                           CV 
                           
                             ( 
                             △34 
                             ) 
                           
                           2 
                         
                       
                       = 
                       
                         
                           
                             1 
                             2 
                           
                            
                           
                             QV 
                             
                               ( 
                               △34 
                               ) 
                             
                           
                         
                         = 
                         
                           
                             1 
                             2 
                           
                            
                           
                             ( 
                             
                               1 
                               - 
                               
                                 2 
                                  
                                 k 
                               
                             
                             ) 
                           
                            
                           
                             ( 
                             
                               
                                 I 
                                 r 
                               
                               × 
                               t 
                             
                             ) 
                           
                            
                           
                             V 
                             
                               ( 
                               
                                 △ 
                                  
                                 
                                     
                                 
                                  
                                 34 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   ; 
                 
               
             
             
               
                 
                   
                       
                   
                    
                   
                     
                       CV 
                       
                         ( 
                         
                           △ 
                            
                           
                               
                           
                            
                           34 
                         
                         ) 
                       
                     
                     = 
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             2 
                              
                             k 
                           
                         
                         ) 
                       
                        
                       
                         ( 
                         
                           
                             I 
                             r 
                           
                           × 
                           t 
                         
                         ) 
                       
                     
                   
                 
               
             
           
         
       
     
         [0055]    A lasting time duration of the voltage increment V (34)  is t 
         [0000]    
       
         
           
             
               
                 
                   t 
                   = 
                   
                     
                       1 
                       
                         
                           ( 
                           
                             1 
                             - 
                             
                               2 
                                
                               k 
                             
                           
                           ) 
                         
                          
                         
                           I 
                           r 
                         
                       
                     
                      
                     
                       CV 
                       
                         ( 
                         
                           △ 
                            
                           
                               
                           
                            
                           34 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0056]    As indicated by Equation (3), the lasting time duration t of the voltage increment V (34)  is proportional to the value C of the high voltage capacitor  31 . The lasting time duration t of the voltage increment V (34)  is longer when the value C of the high voltage capacitor  31  is larger, and is shorter when the value C of the high voltage capacitor  31  is smaller. 
         [0057]    From Equations (1), (2) and (3), the remnant surge voltage Vr of the output terminal  34  of the surge energy transfer circuit  10 , the inductance of the inductor  21 , the value of the high voltage capacitor, and low voltage increment of the output terminal V (34)  and long lasting time duration t or high voltage increment of the output terminal V (34)  and short lasting time duration t can be effectively and precisely planned and designed to meet different customized demands and raise surge immunity of power facilities. 
         [0058]    With reference to  FIG. 3 , an actual testing diagram (L-N) for common mode coupling of the surge energy transfer circuit  10  is shown. An operating voltage AC 110V is applied to the power input terminal  12 . A combination wave surge combined by 10 KV 1.2/50 μS and 5 k A 8/20 μS is coupled to the input terminal  12 . The test results show that a peak value of the operating voltage at the output terminal  34  rises from 145 V to 154V, which represents an increase rate of 6.2%. After lasting for 58 mSec (3.5 cycles), the operating voltage at the output terminal  34  returns to 145V (note: the voltage attenuation ratio in  FIG. 3  is 100). It is evident that the present invention has a good surge energy transfer and suppression effect. 
         [0059]    Moreover, as there are many nonlinear loads in an actual operating environment, the resulting power waveform is distorted accordingly. The power frequency constituted by the inductor  21  and the high voltage capacitor  31  in the surge energy transfer circuit  10  of the present invention can be employed to completely improve the distortion of the power waveform during the lasting time duration of the voltage increment V (34)  after the residual current passes through. 
         [0060]    2. With reference to  FIGS. 2 and 4 , when an operating voltage is applied to the input terminal, a vulnerability interference surge enters the input terminal  12  through ground to form a common mode coupling for the surge. 
         [0061]    Transient voltage increments for 4 SPDs  41  connected between ground and C 1 , C 2 , C 3 , C 4  and having a functionally identical characteristics are V( 1G ), V( 2G ), V( 3G ) and V( 4G ) respectively. When a surge current flows through, a transient total voltage of the output terminal  34 , V C  can be expressed as follows: 
         [0000]        V   C   =V   34 +( V   (Δ1G)   −V   (Δ2G) )+( V   (Δ3G)   −V   (Δ4G) )  (4)
 
         [0062]    Since the four SPDs  41  have the same characteristics, V (Δ1g) =V (Δ2G) , V (Δ3G) =V (Δ4G) . The four SPDs  41  serve to mutually cancel the surge voltage. Therefore, the output terminal  34  is maintained in an equipotential effect to suppress the common mode coupling of the surge. 
         [0063]    With reference to  FIG. 4 , an actual testing diagram (L, N-G common mode coupling) of the surge energy transfer circuit  10  is shown. When an operating AC voltage of 220V is applied to the input terminal  12 , a combination wave surge, 10 kV, 1.2/50 μS, 5 k A, 8/20 μS enters the input terminal  12  and is coupled to ground; a test result shows that a peak value of the operating voltage at the output terminal  34  rises from 291V to 308V and indicates an increase rate of 5.8%. After lasting 25 mS (1.5 cycles), the operating voltage at the output terminal  34  returns to 291V (note: the voltage attenuation ratio in  FIG. 4  is 100, and a current and voltage output transfer ratio is 1V/100 A). It is evident that the equipotential grounding design of the present invention has superior surge energy transfer and suppression effect. 
         [0064]    Moreover,  FIGS. 3 and 4  show a significant aspect. A surge suppression effect generated by the surge energy transfer circuit  10  can be clearly derived from the foregoing equations (1), (2), (3) and (4). A combined suppression effect for enhancing surge immunity and penetration suppression of protected power facilities can be definitely addressed to effectively improve the drawbacks of conventional approach. 
         [0065]    Additionally, customized requirements can be easily achieved by utilizing equations (1), (2), (3) and (4). In accordance with different operating voltages (AC and DC) of power facilities, the specifications of the corresponding SPD  11 , the inductor  21 , and the high voltage capacitor  21  can be obtained from simple calculations to build a product in compliance with practical requirements. 
         [0066]    With reference to  FIG. 2 , not only can the surge energy transfer circuit  10  of the present invention be used to provide a single-stage circuit but can also be used to provide a multi-stage circuit with several single-stage circuits serially connected as shown in  FIG. 5  or, as shown in  FIGS. 6 and 7 , to practically provide various products using a module  100  based on standard requirements. Furthermore, with reference to  FIGS. 8 and 9 , three of the modules  100  can be integrated in accordance with consumer demand to build three-phase products that are Y-connected and Δ-connected with the input terminal  12  and the output terminal  34  to provide a diversified and extensive product range. 
         [0067]    Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Technology Classification (CPC): 7