Patent Abstract:
In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data strip over an associated serial channel, a reception module to receive the plurality of data stripes over the associated serial channels and track a number of errors per channel, and a controller to deactivate a serial channel and reconfigure said transmission module and said reception module to utilize remaining data channels for striping data if the number of errors in the serial channel exceeds a threshold.

Full Description:
[0001]    This application claims priority under 35 U.S.C. §119(e) of U.S. Provisional Application No. 60/367,630 entitled “Error Detection and Correction of Data Striped Over Multiple Serial Channels” filed on Mar. 25, 2002 which is herein incorporated by reference, but is not admitted to be prior art. 
     
    
     
       BACKGROUND  
         [0002]    High-speed store-and-forward devices, such as switches and routers, used in today&#39;s communication networks have a large amount of data passing through them. These devices typically include a set of line cards, which perform various operations within the communication networks. Communication between these line cards usually takes place over a backplane, which provides connectivity among the line cards, e.g., via dedicated point-to-point or switched communication paths. With advances in serial communication technologies, the preferred choice for high-speed backplanes today is to use one or more high-speed serial links (channels). High-speed serial data can be carried over either electrical backplanes or optical backplanes. If an optical backplane is used, the transmitting line card must convert electrical signals to optical signals and send the optical signals over fiber, and the destination line card must receive the optical signals from the fiber and reconvert them to electrical signals. The backplane may be used to switch data between line cards or may transport the data without switching. Serializers and deserializers are used, in conjunction with an encoding scheme, such as 8-bit to 10-bit encoding, to create a self-clocked high-speed serial electrical data stream. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0003]    [0003]FIG. 1 illustrates an exemplary system having multiple line cards connected through serial links over a point-to-point or switched backplane, according to one embodiment;  
         [0004]    [0004]FIGS. 2A and B illustrate exemplary charts explaining how a frame is striped (interleaved) across data channels, according to one embodiment;  
         [0005]    [0005]FIG. 3 illustrates an exemplary transmission module, according to one embodiment;  
         [0006]    [0006]FIG. 4 illustrates an exemplary receiving module, according to one embodiment;  
         [0007]    [0007]FIG. 5 illustrates an exemplary flowchart of the processing of a frame received over a plurality of channels, according to one embodiment;  
         [0008]    [0008]FIG. 6 illustrates an exemplary parity byte calculation, according to one embodiment;  
         [0009]    [0009]FIG. 7 illustrates an exemplary transmission module, according to one embodiment;  
         [0010]    [0010]FIG. 8 illustrates an exemplary receiving module, according to one embodiment;  
         [0011]    [0011]FIGS. 9A and B illustrate an exemplary flowchart of the processing of a frame received over a plurality of channels, according to one embodiment; and  
         [0012]    [0012]FIG. 10 illustrates an exemplary frame and stripe format, according to one embodiment. 
     
    
     DETAILED DESCRIPTION  
       [0013]    [0013]FIG. 1 illustrates an exemplary system  100  for transmitting data amongst various sources and destinations. The system may transmit the data using any number of protocols including Asynchronous Transfer Mode (ATM), Internet Protocol (IP), and Time Division Multiplexing (TDM). The data may be sent in variable length or fixed length blocks, such as cells, packets or frames. The communication lines used to transmit data may be fiber, copper, or other mediums. The system includes at least one store-and forward device  105 , such as a router or packet switch. The store-and-forward device  105  includes multiple line cards connected together through serial links over a point-to-point or switched backplane. A plurality of ingress modules  110  are connected through a backplane  120  to a plurality of egress modules  130 . The backplane  120  may be electrical or optical. The ingress modules  110  and the egress modules  130  are typically two sides of a line card. The line cards may be Ethernet (e.g., Gigabit, 10 Base T), ATM, Fibre channel, Synchronous Optical Network (SONET), and Synchronous Digital Hierarchy (SDH), amongst others. According to one embodiment, the data transmitted over the backplane is broken up into segments (e.g., frames). In a packet switch, the segment includes a single packet or a set of packets sent from a source line card to destination line card. Each segment has a defined maximum length which does not exceed a predetermined maximum length.  
         [0014]    In order to meet bandwidth requirements the data (e.g., frames) being transmitted from one card to another card over the backplane is striped over multiple high-speed serial channels N between the cards. Striping is accomplished by breaking the data up and transmitting portions of the data over each of the N channels. For example, if the frame to be striped had W bytes, each channel would transmit W/N bytes. According to one embodiment, a first byte (e.g., byte 0) is transmitted over a first channel (e.g., channel 0), a second byte (e.g., byte 1) is transmitted over a second channel (e.g., channel 1), and so on until an N th  byte (e.g., byte N−1) is transmitted over the N th  channel (e.g., channel N−1). Once each channel has transmitted a byte, the next byte (e.g., byte N) is transmitted on the first channel (e.g., channel 0). The process is repeated until all W bytes in the frame are transmitted. One way to look at this is that the data is broken up into W/N groups, with each group having N bytes. One byte (of the N bytes) from each group is then transmitted to each data channel (of the N data channels). The bytes belonging to a frame that travel on one specific channel is called a stripe. For example, the sequence of bytes 0, N, 2N, 3N, etc. would make up stripe 0 (e.g., the part of the frame traveling on channel 0). Note that some channels may have less than W/N bytes (or may have no data) and that the last group may have less than N bytes.  
         [0015]    [0015]FIG. 2A illustrates an exemplary chart explaining how a frame including W bytes is striped (interleaved) across N data channels. The first column lists the byte number (0 to W−1), the second column lists the data channel number (0 to N−1) and the third column the group number (0 to (W/N)−1). As illustrated, bytes 0 to N−1 are striped over data channels 0 to N−1 to form a first group (group 0); bytes N to 2N−1 are striped over data channels 0 to N−1 to form a second group (group 1); and so on until bytes ((W/N)−1)N to W−1 are striped over data channels 0 to N−1 to form a last group (group (W/N)−1).  
         [0016]    [0016]FIG. 2B illustrates an exemplary chart explaining how a frame including 26 bytes is striped (interleaved) across 6 data channels. This example would create 4 groups having 6 bytes each and a fifth group having two bytes. As illustrated, the first six bytes (bytes 0 to 5) are striped over each data channel (channels 0 to 5) to form a first group (group 0); the next six bytes (bytes 6 to 11) are striped over each data channel (channels 0 to 5) to form a second group (group 1); and so on until the last two bytes (bytes 24-25) are striped over the first two data channels (channels 0 and 1) to form a last group (group 4).  
         [0017]    The various embodiments are in no way intended to be limited to the striping assignments discussed above. Rather, the bytes can be transmitted over the channels in any order. For example, byte 0 could be assigned to channel (N−1), byte 1 could be assigned to channel (N−2) and so on. Moreover, the various embodiments are not limited to transmitting the data byte by byte. The data could be transmitted bit by bit, sector by sector, block of bytes by block of bytes, or block of bits by block of bits, where a block can be defined by a user. Furthermore, the various embodiments are not limited to receiving frames that are organized as W bytes. Rather the frames could be organized by bits, sectors, or other ways.  
         [0018]    Before transmission, a cyclic redundancy code (CRC) is computed for the frame. The CRC is inserted at the end of the frame and is transmitted along with the frame (data). Also, a separate CRC is computed for each stripe and is sent as part of the stripe.  
         [0019]    [0019]FIG. 3 illustrates an exemplary transmission module  300 , according to one embodiment. The transmission module  300  receives an input frame that is W bytes long at a CRC generator  310  that generates a CRC for the entire frame. The entire frame including the CRC is provided to a striper  320 . The striper  320  divides the W bytes into N groups and selects the channel for each group to be transmitted over. That is, one group will be transmitted over each of the N channels. A CRC is generated for each stripe and is inserted at the end of the stripe by a CRC module  330 . The stripe and the associated CRC for each channel are then provided to a transmitter  340  for transmitting over the backplane. There are a total of N transmitters  340 , one for each data channel. In the event of channel failures (discussed later) the transmission module can be reconfigured to stripe the data over fewer channels. Up to P channels can be configured out of the system so that the data can be striped over a minimum of N-P channels.  
         [0020]    The data sent over each channel (stripe) is received and buffered and the frame is recreated. A CRC is computed for the entire received frame and compared to the CRC that was transmitted with the frame in order to check for errors in the received frame. In addition, a CRC is computed for each channel and compared to the transmitted CRC for the channel to check for errors in the strip. If the computed CRC does not match with the transmitted CRC at the end of the stripe, the data within the stripe is deemed to be in error. The CRC error indication for each channel is ORed with an error signal from a corresponding physical receiver device. The physical receiver device indicates errors such as loss of signal etc. The ORed error signal is referred to as a channel error. If there is an error for the overall frame and/or one or more channel errors the frame is discarded.  
         [0021]    Each channel is provided with a channel-specific error counter and an associated threshold register. When any channel-specific error count exceeds the threshold, there is a provision for an interrupt to be issued to the processor (or custom hardware) controlling the system. The software (or custom hardware) would set the value of the threshold such that in a given interval, if the number of errors exceed the value specified in the threshold register, it is likely that the channel has a permanent hardware problem. The system may then be shut down to replace one or more components to restore full throughput. If the error count does not exceed the threshold in the specified interval, it is likely that any errors that occurred were random in nature and may be ignored. At the end of each specified interval, the channel-specific error counts are reset. Note that the software (or custom hardware), needs to keep a rolling average of the per-channel error count.  
         [0022]    Fixing a channel may cause down time on the system. According to one embodiment, the CPU (custom hardware) may reconfigure the system to stripe the data over fewer channels (N−1 channels, N−2 channels, etc.). In general, the data can be striped over any number of channels in the range N-P (minimum) to N (maximum). This allows for P channels to fail, and still have data transmission over the backplane and through the switching chips to the destination line card, albeit at a reduced bandwidth. The value of P is determined by the reduction of throughput that can be tolerated.  
         [0023]    [0023]FIG. 4 illustrates an exemplary receive module  400 , according to one embodiment. The receive module  400  includes N serial channel receivers  410  for receiving and buffering data over the N data channels. A CRC module  420  generates a CRC for each data channel (stripe). The stripes are provided to a destriper  430  that takes the N channels and converts it back into a W byte (or bit, etc.) frame. The destriper  430  forwards the frame to a CRC computation module  440  that computes the CRC for the entire frame and then compares the generated frame CRC to the transmitted frame CRC, and the generated stripe CRCs to the transmitted stripe CRCs to determine errors. Errors in any channel are recorded and compared to an error threshold. If the channel exceeds the error threshold it is configured out of the system until it can be repaired. Up to P channels can be configured out of the system so that the striped data can be transmitted using as little as N-P channels (minimum number of channels).  
         [0024]    [0024]FIG. 5 illustrates an exemplary flowchart of the processing of a frame received over a plurality of channels. Initially, the received frame is checked for an error indicated by the frame-level CRC ( 500 ). If there is no error in the frame level CRC ( 500  No), then each individual stripe is checked for errors based on the CRC or an error indication from the physical receiver device ( 505 ). If there is no error in any channel ( 505  No), then the frame is declared good and is sent out for further processing ( 510 ). If there are one or more channels with errors ( 505  Yes), then the error is an uncorrectable error. The frame is discarded and the corresponding per-channel error counters are incremented ( 515 ).  
         [0025]    If there was a frame level CRC error ( 500  Yes), then a determination is made as to whether there are any channel errors ( 520 ). If there are no channel errors ( 520  No), then the frame is discarded and the frame error count is incremented ( 525 ). If there were channel errors ( 520  Yes) then the frame is discarded, the frame error count is incremented, and the channel error count(s) are incremented ( 530 ). After any incrementing of channel errors ( 515 ,  525 ,  530 ) the error count of each channel is compared to error thresholds ( 535 ). If the threshold is not exceeded ( 535  No) for every channel then the process is complete. If the threshold is exceeded for at least one channel ( 535  Yes) an interrupt is issued to a CPU, or custom hardware ( 540 ). The CPU (custom hardware) receives the interrupt indicating that the threshold(s) has been exceeded, and makes a determination as to whether there are enough usable channels remaining to support the system ( 545 ). That is, if we take the faulty channel out of service are the number of channels remaining at least equal to the minimum number of channels (N-P) required to meet the bandwidth requirements of the system? If the number of channels remaining after deactivating the faulty channels is less than the minimum number of channels ( 545  No), then the system is shut down for servicing ( 550 ). If the number of channels remaining after deactivating the faulty channels is still at least equal to the minimum number of channels ( 545  Yes), then the system is reconfigured to utilize only working channels ( 555 ).  
         [0026]    The exemplary process flow described above is not the only embodiment but is merely an example. Numerous modifications could be made to the process flow (e.g., the order could be rearranged and/or individual operations could be combined or split apart).  
         [0027]    Discarding an entire frame because of a single channel failure is not desirable. This situation may be perpetuated if multiple channels continually fail at different times, with no channel failing enough to exceed the threshold. In this case numerous frames are discarded, but none of the channels is deactivated. According to one embodiment, the CPU (custom hardware) may switch from a graceful degradation mode (the mode described above where if a channel(s) has multiple errors that exceed a threshold they can be configured out of the system) to a single channel error correction mode. The single channel error correction mode allows a single channel error to be corrected.  
         [0028]    In this embodiment, the N serial channels are divided into M data channels and K parity channels. The parity channels are used to send parity information associated with the data being sent. If the data is being striped by bytes then the parity will be transmitted by bytes as well. The parity bytes (or other grouping) are used for correction of errors. The M data channels are divided into groups and each group is associated with a parity channel. As there are K parity channels it follows that there will be K groups of data channels and each group will have M/K channels. For each byte within a group (e.g., M/K channels) there is an associated parity byte in the corresponding parity channel. In a preferred embodiment, each parity byte is generated by XORing (that is, computing the logical Exclusive-OR operation of) each bit of each associated byte in the data channels within the group. For example, bit 0 of the parity byte is the XOR of the bits in position zero of all the bytes in that group, bit 1 is the XOR of the bits in position one of all the bytes in that group, and so on.  
         [0029]    [0029]FIG. 6 illustrates an exemplary parity byte calculation for a group of 3 data channels that are utilized to transmit a plurality of bytes. The parity byte is calculated by XORing each bit of the data bytes. The various embodiments are in no way intended to be limited to generating the parity data by XORing associated bits together. Rather, there are multiple methods for generating parity data (e.g., bits, bytes, etc.).  
         [0030]    If there is channel error on only a single data channel (e.g., error is confined to a single stripe) associated with a group of channels, the data for that channel (stripe) can be recovered. The data for the channel is recovered by XORing the data from all the other channels (data and parity) in the group. The recovered data replaces the received data for that channel (stripe). Once the data is recovered for the errored channel (stripe), the frame is reassembled from all the received channels (stripes) and the corrected channel (stripe). A second CRC check is then performed on the frame. If this CRC check passes, the entire frame is deemed error-free and accepted by the receiver. An error count is incremented for the data channel having the failure. If the error count exceeds some predefined threshold, action may be taken to fix the channel (discussed later).  
         [0031]    If there is only a single channel error on a parity channel associated with a group of channels, the received data within the group is processed normally (as if there were no error). An error count is incremented for the parity channel having the failure. If the error count exceeds some predefined threshold, action may be taken to fix the channel (discussed later).  
         [0032]    It should be noted that if there is a channel error (data or parity as discussed above) that there should also be a frame level error. If there is a channel error but no frame level error the frame will be discarded and the channel error count is incremented.  
         [0033]    If errors are detected in more than one channel (whether data or parity) in a group, the error is uncorrectable. The frame is discarded and a frame error counters are incremented. If the error count exceeds some predefined threshold, action may be taken to fix the channel.  
         [0034]    If the frame level CRC indicates an error, but there are no channel errors detected in any group, then it is an uncorrectable error. The frame is discarded and a frame error counter is incremented.  
         [0035]    The above descriptions apply for each group of channels. The actions in one group are independent of the actions required (or taken) in other groups.  
         [0036]    [0036]FIG. 7 illustrates an exemplary transmission module  700 , according to one embodiment. The transmission module  700  is much like the transmission module  300  of FIG. 3 with the exception that the N serial channels are divided into M data channels and K parity channels. A CRC generator  710  receives a frame and generates a CRC for the entire frame. The entire frame including the CRC is provided to a striper  720 . The striper  720  divides the frame into M groups and selects the channel for each group to be transmitted over. A CRC is generated for each stripe and is inserted at the end of the stripe by a CRC module  730 . The stripe and the associated CRC for each channel are then provided to a transmitter  740  for transmitting over the backplane. Each parity channel is associated with a group of M/K data channels. The M/K data channels associated with each parity channel are provided to a parity generator  750  that generates the parity data associated with the group of data channels. As previously mentioned, if the data channels are transmitting data byte by byte the parity data will be a parity byte. In a preferred embodiment, the parity generator  750  is an XOR gate for each bit of the data being transmitted at a time. The XOR gate receives an associated bit from each of the group of M/K data channels. A CRC is generated for each parity channel stripe and is inserted at the end of the parity stripe by a CRC module  760 . The parity stripe and the associated CRC for each parity channel are then provided to a transmitter  770  for transmitting over the backplane.  
         [0037]    It should be noted that the transmitters  740  and the transmitters  770 , as well as the CRC modules  730  and the CRC modules  760 , are illustrated separately for convenience of pointing out the difference between the parity channels and the data channels. However, it should in no way be construed to require different CRC modules and transmitters for parity channels and data channels. Rather, the CRC modules and the transmitters could be the same. In fact, according to one embodiment, the transmission module  700  can easily be reconfigured to have more data channels or more parity channels.  
         [0038]    [0038]FIG. 8 illustrates an exemplary receive module  800 , according to one embodiment. The receive module  800  is much like the receive module  400  of FIG. 4 with the exception that parity bits are received and used for regeneration (correction) of errored stripes. The receive module  800  includes M serial channel receivers  810  for receiving and buffering data over the M data channels. A CRC module  820  generates a CRC for each data channel (stripe). The stripes are provided to a destriper  830  that takes the M channels and converts it back into a frame. The destriper  830  forwards the frame to a CRC computation module  840  that computes the CRC for the entire frame and then compares the generated frame CRC to the transmitted frame CRC, and the generated stripe CRCs to the transmitted stripe CRCs to determine errors. The receive module  800  also includes K serial channel receivers  850  for receiving parity data. A CRC module  860  generates a CRC for each parity channel (stripe). Each parity channel and the data channels that are associated with the parity channel as part of a group, are provided to error correction modules  870 . There is one error correction module  870  for each of the M/K groups. The error correction modules can recreate data lost on an individual channel within a group. As previously discussed, the data can be recreated by XORing all of the other channels (data and parity) within the group. Accordingly, in a preferred embodiment, the error correction modules  870  are XOR gates. The error correction modules  870  provide the corrected data channels to the destriper  830 .  
         [0039]    It should be noted that the receivers  810  and the receivers  850 , as well as the CRC modules  820  and the CRC modules  860 , are illustrated separately for convenience of pointing out the difference between the parity channels and the data channels. However, it should in no way be construed to require different receivers and CRC modules for parity channels and data channels. Rather, the receivers and CRC modules could be the same type of receivers. In fact, according to one embodiment, the receiver module  800  can easily be reconfigured to have more data channels or more parity channels.  
         [0040]    [0040]FIGS. 9A &amp; B illustrate an exemplary flowchart of the processing of a frame received over a plurality of channels. The flowchart of FIGS. 9A &amp; B is similar to the flowchart of FIG. 5 with the exception that a switch to the single channel error correction mode (described above) from the graceful degradation mode (described above) is possible. The mode of the system may be switched at any point in time either automatically or by an operator. One possible occasion for the switch in mode would be the case where the error threshold has not been exceeded for any particular channel but that there have been multiple single channel failures causing multiple frames to be discarded. In this case the system could reconfigure itself to include parity channels (thus reducing the bandwidth available for the data) so that the errors could be self-correcting.  
         [0041]    As previously mentioned, errors within a single channel per group can be corrected in the single channel error correction mode. Thus, the process will require a determination of the mode of the system. Referring to FIGS. 9A and B, the channel error determination ( 520 ) is modified to be a determination as to whether there was a single channel error ( 900 ). If the errors were not limited to a single channel error ( 900  No), the frame is discarded ( 905 ). Also, the frame error count is incremented and the channel error counts for the errored channels are incremented ( 905 ). If the error was limited to a single channel error ( 900  Yes), a determination is made as to whether the system is in single-channel error correction mode ( 910 ). If it is determined that the system is not in single channel error correction mode ( 910  No) the frame is discarded, the frame error count is incremented and the channel error count for the errored channel is incremented ( 920 ). If the errors were limited to a single channel per group ( 910  Yes), a determination is made as to whether the channel having the error is the parity channel ( 930 ). If the channel error was not in the parity channel ( 930  No), the data is the channel is recreated (corrected) by XORing all the other stripes within that group, the frame is generated using the corrected stripe, the frame is sent out, and the channel error count for the errored channel is incremented ( 940 ). If the channel error was in the parity channel ( 930  Yes), the frame is sent out, and the parity channel error count is incremented ( 950 ).  
         [0042]    After any incrementing of channel errors, whether the frames were discarded ( 920 ,  940 ) or the frames were transmitted  950 , the error count is compared to the threshold ( 535 ) and if exceeded the CPU receives an interrupt. However, as the single channel error correction mode cannot deactivate and reconfigure channels a determination will have to be made as to which mode the system is in before proceeding. Accordingly, after the CPU (custom hardware) receives an interrupt ( 540 ) indicating that a threshold(s) has been exceeded a determination will be made as to whether the system is in graceful degradation mode ( 960 ). If the system is not in graceful degradation mode ( 960  No), the CPU (custom hardware) will perform the necessary actions ( 970 ). The necessary actions may be to shut down and repair the system now, tag the system for shut down/repair in the future, or switch to graceful degradation mode. If the system was in graceful degradation mode ( 960  Yes), the system proceeds to determine if the number of usable channels is sufficient  545 .  
         [0043]    According to one embodiment, there is also a provision for test data to be sent over one or more channels. Errors detected on the received data are recorded per-channel. This can be used by the software (or custom hardware) to test individual channels before deciding the number of channels to use, or as a periodic self-diagnostic feature.  
         [0044]    The exemplary process flow described above is not the only embodiment but is merely an example. Numerous modifications could be made to the process flow (e.g., the order could be rearranged and/or individual operations could be combined or split apart).  
         [0045]    According to another embodiment, the system may act in both the single channel error correction mode and the graceful degradation mode at the same time. This embodiment is similar to the embodiment of FIGS. 9A and B with the exception that the graceful degradation determination  960  and associated perform action  970 , as well as single channel error correction determination  910  and associated discard frame  920  are no longer required. The system will utilize both data and parity channels so that single channel error corrections can be made. In the event that one or more of the channels exceed the associated thresholds  535 , the CPU (custom hardware) will make a determination if there are sufficient channels available to deactivate the channel or channels  545 . In this embodiment, the determination is not just made on data channels as in the embodiment of FIGS. 9A and B (at least N-P channels). In this embodiment, a determination will have to be made as to whether enough data channels are available with enough associated parity channels to be able to handle single channel error detection. Therefore a minimum number of data channels and associated parity channels need to be defined.  
         [0046]    According to one embodiment, it would be possible to continue processing if there were channels to support the data but not the parity. However, the continued processing would be with limited or no single error correction. If the determination is that enough channels do not exist ( 545  No) then the system is shut down for servicing ( 550 ). If the determination is made that there are enough channels available, the system is reconfigured to use only the working channels ( 555 ).  
         [0047]    [0047]FIG. 10 illustrates an exemplary frame and stripe format. In this example, high speed serial electrical channels are used over a backplane, and switched using a crossbar. There are total of eight serial channels with seven channels used for data and one channel used for parity. All seven data channels belong to one group so that only a single parity channel is required to provide error correction for the seven data channels. The encoding scheme used for framing is the industry-standard 8-bit to 10-bit encoding. It provides a “Start of Frame Delimiter” (SFD) symbol, an “End of Frame Delimiter” (EFD) symbol, and an “Idle Character” symbol. The input data  1000  is broken into frames, and each frame is appended with a frame-level CRC  1010 . The frame-level CRC  1010  is computed over all the data bytes (or bits, etc.) of the frame. The data is striped over the seven data channels  1020 , byte by byte. The data can be striped across the channels in other manners, such as bit by bit or group by group. A parity channel  1030  transmits parity data for the group which is the XOR of all the data from the seven data channels. According to a preferred embodiment, the parity data is derived by the bit-wise XOR of the corresponding bytes of each of the seven data channels.  
         [0048]    Each of the channels initially transmits a first stripe for the frame  1040  that is the start of frame symbol. This is followed by the data stripe (data for the seven data channels  1020  and parity data for the parity channel  1030 )  1050 . A last data stripe  1060  is the CRC computed for each stripe. A last stripe for the frame  1070  is the end of frame symbol. If only a single channel fails, the channel can be recreated (fixed) by XORing all the other channels in the group. If one of the channels records enough errors to cross the threshold level, the system could either shut down for servicing (now or later) or could reconfigure itself to a graceful degradation mode in which case that channel would be reconfigured out of the system and the data would be transmitted over the remaining channels.  
         [0049]    According to an embodiment in which the system can be reconfigured between single channel error correction mode and graceful degradation mode, if a single channel failed once the system was reconfigured to remove the channel (whether a data channel or the parity channel) the data would continue be transmitted over seven channels but would have no parity channel and thus no error correction.  
         [0050]    According to an embodiment in which the system supports both single channel error correction mode and graceful degradation mode, the system can continue to correct errors while at the same time reconfiguring to deactivate faulty channels. For example, if a data channel failed the data could be striped over the remaining six data channels and the parity channel could continue be used for error correction. However, if the system needed at least  6  data channels to meet bandwidth requirements if a second channel failed the parity channel would have to be deactivated which would eliminate the error correction capability at that point.  
         [0051]    Although the detailed description has been illustrated by reference to specific embodiments, various changes and modifications may be made. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.  
         [0052]    Different implementations may feature different combinations of hardware, firmware, and/or software. For example, some implementations feature computer program products disposed on computer readable mediums. The programs include instructions for causing processors to perform techniques described above.  
         [0053]    The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.

Technology Classification (CPC): 7