Patent Abstract:
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a Divisional of pending U.S. patent application Ser. No. 09/032,256, filed Feb. 27, 1998. 
    
    
     TECHNICAL FIELD 
     This invention relates to clocked integrated circuits that deliver data, and more particularly to a method and apparatus for adjusting the timing of data presented to an output terminal relative to a clock signal. 
     BACKGROUND OF THE INVENTION 
     Clock signals are used by a wide variety of digital circuits to control the timing of various events occurring during the operation of the digital circuits. For example, clock signals are used to designate when command signals, data signals, and other signals used in memory devices and other computer components are valid and can thus be used to control the operation of the memory device or computer system. For instance, a clock signal can be used to develop sequential column addresses when an SDRAM is operating in burst mode. 
     Retrieving valid data from a clocked memory device at a specified time can be difficult to coordinate. After a memory address is selected, the data travels out of the selected memory cell, is amplified, passes through configuration circuitry (if the memory chip has multiple configurations) and passes through an output buffer before the data is read. Before the advent of synchronous memory circuits, data simply appeared at an output terminal following a propagation delay after the data was requested. In a synchronous memory circuit, data delivery is synchronized with a clock signal. Many circuits have been created to coordinate data signals with clock signals, with varying degrees of success. Two of the problems to solve are determining how fast and with what regularity the data signal propagates through the chip circuitry. Because data output is often coordinated with a clock signal that is external to the memory chip, computer simulations of signal propagation within a chip are performed to align the external clock signal with the data delay of the synchronous memory device. Static time delays are then designed into the memory circuit based on the simulation predictions. Because of production variations, improper assumptions, and other factors ultimately causing timing errors, the data does not always arrive at the output terminal at the desired time. As computer clock speeds increase, the window for providing valid data to the output terminal closes, making it more difficult to ensure the correct delivery time of data from the memory circuit. 
     An example of a circuit that provides data to a data pad at a specific time relative to an external clock is shown in FIG.  1 . An output circuit  2  includes a memory array  5  that contains an array of individual memory cells (not shown). Once a particular memory cell is selected to be read, complementary signals corresponding to the contents of the memory cell travel to a pair of respective I/O and I/O* lines. The signals on the I/O and I/O* lines are sensed and amplified by a data sensing circuit  10 , which produces a DATA* signal at an output. An external clock signal is received at a clock circuit input  7  and passes through clock circuitry  15  to become a CLKDOR* signal. The CLKDOR* signal may differ from the external clock signal in a variety of ways, including phase, orientation, and duty cycle, however, their overall periodic cycle length is the same. Oftentimes, to properly match timing of the data arriving at the data pad with the external clock signal, a static delay is added within the clock circuitry  15 . 
     The DATA* signal is presented to a passgate  20  and passed to an output node  21  when the signal CLKDOR* signal is HIGH and its complement from an inverter  17  is LOW. From the output node  21 , the DATA* signal is input to a NOR gate  30  along with a TRISTATE signal. An output from the NOR gate  30  leads to a passgate  24 . When the CLKDOR* signal is LOW and its complement from the inverter  17  is HIGH, the output from the NOR gate  30  passes through the passgate  24  and becomes the signal DQHI. Another NOR gate  32  combines the output of the NOR gate  30  with the TRISTATE signal. This output from the NOR gate  32  is presented to a pair of passgates  22 ,  26 . The passgate  22  receives the signal from the NOR gate  32  and, when the CLKDOR* signal is LOW and its complement from the inverter  17  is HIGH, feeds it back to the output node  21 . The passgate  26  passes the signal it receives from the NOR gate  32  as an output signal DQLO when the signal CLKDOR* is LOW and its complement from the inverter  17  is HIGH. 
     If the signal DQHI is HIGH, a pull-up circuit  36  raises a DQ pad  40  to a HIGH voltage. Conversely, if DQLO is HIGH, it activates a pull-down circuit  38  to pull the DQ pad  40  to a ground voltage. The output circuit  2  is designed so that the pull-up circuit  36  and the pull-down circuit  38  cannot operate simultaneously. When neither the pull-up circuit  36  nor the pull-down circuit  38  is active, the DQ pad  40  is neither pulled up to a HIGH voltage nor pulled down to ground, but instead remains in a high-impedance state. 
     The circuit operation of the data delivery circuit  2  will now be explained. When the CLKDOR* signal is HIGH and the DATA* signal is HIGH, a HIGH signal passes to the output node  21 . Assuming that the TRISTATE signal is low to enable the NOR gates  30  and  32  so they act as inverters, when the CLKDOR* signal goes LOW, the passgate  22  couples the output of the NOR gate  32  to the input of the NOR gate  30 , output node  21 . The NOR gates  30  and  32  then latch the HIGH at the output node  21  to the output of the NOR gate  32 . At the same time, a LOW is latched to the output of the NOR gate  30 . The HIGH at the output of the NOR gate  32  is coupled through the passgate  26  to the pull-down circuit  38 . The HIGH signal DQLO causes the pull-down circuit  38  to pull the DQ pad  40  to ground. At the same time, the LOW signal at the output of the NOR gate  30  passes through the passgate  24 . The LOW DQHI signal does not activate the pull-up circuit  36 , as explained above. Alternatively, if the DATA* signal is LOW, a LOW signal is passed to the output node  21  when the CLKDOR* signal is HIGH. When the CLKDOR* signal drops LOW, the LOW signal at the output node  21  is latched by the NOR gates  30  and  32 , is fed back to the output node  21  through the passgate  22 , and also propagates through the passgate  26  to make DQLO LOW. Concurrently, the LOW signal at the data output node  21  causes the NOR gate  30  to output a HIGH signal that passes through the passgate  24  to provide a HIGH DQHI signal. The HIGH DQHI signal causes the pull-up circuit  36  to connect the DQ pad  40  to a HIGH voltage. If the TRISTATE signal is HIGH, neither DQHI nor DQLO will be HIGH regardless of the state of the DATA* signal. Thus, the DQ pad  40  floats in a high impedance state. 
     When a computer system is designed, specifications for signal timing are determined. Some of the signals and timings used in the design are shown in FIG.  2 . One of the design specifications is an access time, T AC , used to designate a maximum time between a rising edge of an external clock signal and when a valid data signal arrives at the DQ pad  40 . Additionally, another specified time parameter is the output hold time, T OH , indicative of a minimum time for how long the data will be held at the DQ pad  40  following a subsequent rising edge of the external clock. For example, as illustrated in FIG. 2, a READ command signal is input to a memory circuit sometime between a rising edge of a clock pulse CP 0  and a clock pulse CP 1 . At a time CP 1 , the READ command is latched and read by the memory circuit, indicating data is to be read from a memory cell in a memory array. The data is read from the array and placed at the DQ pad  40  under the control of the CLKDOR* signal. The specification T AC  indicates a maximum time until the desired data is placed on the DQ pad  40 . The data is held at the DQ pad  40  for a time no less than the specification T OH , as measured from a subsequent clock pulse after the READ command is latched. As shown in FIG. 2, T AC1  is the time measured from CP 2  until Data 1  is stable on the DQ line. T AC2  is the time measured from CP 3  until Data 2  is stable on the DQ line, and so on. The time T AC1  will be nearly identical to the other access times T AC2 , T AC3 , etc. under the same operating conditions. Also shown in FIG. 2, T OH1  is the time measured from the next clock pulse following when Data 1  appears on the DQ line, i.e., CP 3 , to the time when Data 1  begins to transition off the DQ line. As above, the measured hold times T OH2 , T OH3 , etc. will be nearly identical to one another under similar operating conditions. 
     During the design phase of a memory chip, a designer determines how much after each clock pulse the CLKDOR* signal should fire. This delay determines when the data is made available on the DQ line relative to the external clock signal. Typically, a delay value is chosen that provides a tolerance for both the T AC  and T OH  parameters. If the CLKDOR* signal fires too soon after the external clock signal, the chip will easily pass the T AC  specification, but may fail the T OH  specification. If the CLKDOR* signal fires too late, the chip will easily pass the T OH  specification but may fail the T AC  specification. These time compensations, by virtue of being fabricated as part of the circuit, generally cannot be changed after manufacture of an integrated circuit. When memory chips fail their timing specifications, they are sold as lesser quality chips for a reduced price, or even destroyed. Thus, there is an economic incentive to maximize the number of chips that meet or exceed the timing specifications. As a consequence of increasing computer speeds, this already small window for proper data timing is reducing. Because of process variations, errors in design assumptions, the wide range of temperatures and voltages in which the chips are warrantied to perform, and other factors, an increasing number of memory chips fail to meet the increasingly stringent design specifications. 
     SUMMARY OF THE INVENTION 
     An adjustable data delay circuit comprises a clocked data passing circuit that receives a clock signal and a data signal. An adjustable time delay circuit is coupled to the clock signal for adjusting the time the data is delivered to an output terminal relative to the clock signal. The adjustable time delay circuit includes a plurality of delay gates, each individually selected by control signals. One path in the time delay circuit that includes the desired delay gate is selected by the control signals. The clock signal passing through the selected delay gate is then used to control the time when the data is delivered to the output terminal. 
     In one embodiment, the control signals are made by selectively coupling a pattern of control inputs to a reference voltage. 
     In another embodiment, the passgates are arranged in a plurality of columns such that each column has a number of passgates that is an integer power of 2. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional clocked data delivery circuit. 
     FIG. 2 is a timing diagram of various signals during the operation of the clocked data circuit of FIG.  1 . 
     FIG. 3 is a schematic diagram of an adjustable clocked data circuit according to one embodiment of the present invention. 
     FIG. 4A is a schematic diagram of a delay adjusting circuit according to one embodiment of the present invention. 
     FIG. 4B is a chart showing how different delay times are selected using one embodiment of the present invention. 
     FIG. 5A is a schematic diagram of a conventional adjustable impedance device. 
     FIG. 5B is a schematic diagram of another conventional adjustable impedance device. 
     FIG. 6 is a block diagram of a synchronous dynamic random access memory including the adjustable time delivery circuit of FIG.  3 . 
     FIG. 7 is a block diagram of a computer system including the random access memory of FIG.  6 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     One embodiment of an adjustable time delay circuit  102  in accordance with the invention is illustrated in the schematic diagram of FIG.  3 . The adjustable delay circuit  102  includes some of the same components as the output circuit  2 , shown in FIG.  1 . Identical components of the output circuit  2  and the adjustable time circuits  102  have been given the same reference numbers, and for the sake of brevity, identical components will not be described in further detail. The adjustable time data circuit  102  includes a delay adjusting circuit  60  located between the clock circuitry  15  and the control inputs to the passgates  20 ,  22 ,  24 , and  26 . As later described, the delay adjustment circuit  60  can be located in various places in the adjustable delay circuit  102 , and is shown in this location of the adjustable delay circuit  102  for illustration. 
     As shown in FIG. 4A, the CLKDOR* signal is input to the delay adjusting circuit  60  at an input terminal  62 . From there it is split into four paths, passing through a delay circuit  70 , having a delay of 1.0; a delay circuit  72 , having a delay of 0; a delay circuit  74 , having a delay of 0.5; and a delay circuit  76 , having a delay of 1.5. The delay times 0, 0.5, 1.0, and 1.5 are an indication of relative measure and do not necessarily indicate a specific time period. These delay times are selected such that the delay that would have been designed into the output circuit  2  appears as a middle value of the range of delay values eligible for selection. In this way, the data delivery of a memory chip can be “accelerated” by selecting a delay time shorter than the built-in delay of the prior art circuit, or “decelerated” by selecting a delay time longer than the built-in delay of the prior art circuit. The output signals from the delay circuits  70 ,  72 ,  74 , and  76  are input to a passgate  80 , a passgate  82 , a passgate  84 , and a passgate  86 , respectively. The passgates  80 ,  82 ,  84 , and  86  are controlled by a control signal A and its complement formed by passing A through an inverter  92 . The signals from the passgates  80  and  82  combine as an input to a passgate  88 , and the signals from the passgates  84  and  86  combine as an input to a passage  90 . The outputs from the passgates  88  and  90  connect at an output terminal  95 , and form an output signal OUT. The passgates  88 , and  90  are controlled by a control signal B and its complement formed by passing B through an inverter  94 . 
     Referring back to FIG. 2, the benefits of having an adjustable CLKDOR* signal will be described. As previously stated, adding delay to the CLKDOR* signal in relation to the CLK signal allows the designer to provide a tolerance for the T AC  and T OH  specifications. After the chip is produced, the T AC  and T OH  specifications, and others, are tested. If the chip does not pass all of the specifications, it cannot be sold at the current market price for the highest quality chips. By including an adjustable timing circuit within the memory chip, chips that do not meet the T AC  and T OH  specifications after manufacture may be able to be adjusted in order to meet the specifications. 
     For example, the specifications may direct that T AC  can be no more than 6 ns and T OH  cannot be less than 3 ns. Assume that T AC1  measured 4 ns and T OH1  measured 2.5 ns. The specification for T AC  is easily passed (the shorter the better), but the chip fails the T OH  specification because it does not hold the data for a long enough time on the DQ lines. By adding a 1 ns delay to the time when the CLKDOR* signal fires, the chip can be brought within the specifications. The T AC1  increases to 5 ns (still passing the 6 ns specification) and the T OH1  increases to hold the data valid on the DQ lines for 3.5 ns, passing the 3 ns specification. 
     The delay adjusting circuit  60  of FIG. 4A is controlled by control signals A and B. These control signals provide a HIGH or LOW signal to the passgates depending on a state of a respective adjustable impedance circuit  96 . Two different kinds of adjustable impedance devices are shown, one in FIG.  5 A and one in FIG.  5 B. One type of adjustable impedance circuit  96  is a circuit containing an antifuse  65 , shown in FIG.  5 A. The antifuse  65  is made from a pair of conducting plates  110  and  112  separated by a dielectric material  115 . Antifuses are devices similar to small capacitors. They have a natural and a blown state. When the antifuse  65  is in a natural state, the dielectric material  115  electrically insulates the pair of plates  110  and  112 . Because the dielectric material  115  is intact, the node C is electrically insulated from the ground voltage. To change the antifuse  65  to its blown state, a high electric field is passed across the dielectric material  115  by raising C gnd  to a programming voltage, for example, 10 volts, while enabling a PROGRAM transistor. This is usually done after chip fabrication and packaging, but can be completed before packaging. When the high electric field is placed across the dielectric material  115 , it breaks down and loses its insulative properties. This allows the plates  110  and  112  to contact one another creating a relatively low resistive contact. When blown, the antifuse  65  couples the node C to the node C gnd , that is normally held at the ground voltage, unless the antifuse is being programmed, as described above. To test the state of the antifuse  65  a Read* signal is strobed LOW. That connects node C to the Vcc voltage. If the antifuse  65  is blown, the node C is quickly brought down to ground. An inverter  50  causes a HIGH signal to be sent to a BLOWN output. The HIGH signal also keeps a HOLD transistor OFF. Conversely, if the antifuse  65  is in its natural state, node C will not be pulled down to ground and BLOWN will carry a LOW signal. This low signal also enables the HOLD transistor, keeping node C at the voltage Vcc. 
     The other adjustable impedance circuit  96 , shown in FIG. 5B contains a fuse  68 . The fuse  68  also has a natural and a blown state. In its natural state, the fuse  68  couples a node D to the ground voltage. The fuse  68  is blown by passing a high current through it, or by some other means such as cutting it with a laser, for example. When the fuse  68  is blown, the node D is disconnected from the ground voltage. As with the antifuse  65 , the fuse  68  may be blown before or after packaging. Also as described above, the adjustable impedance circuit  96  of FIG. 5B is read in a similar manner. The Read* signal strobes LOW raising a node D to the Vcc voltage. If the fuse  68  is intact, node D is coupled to ground and BLOWN is LOW. This LOW signal passes through an inverter  52  to keep the HOLD transistor OFF. If the fuse is blown, node D is charged to Vcc and BLOWN is pulled HIGH. 
     Referring back to FIG. 4A, the adjustable impedance circuits  96  may be either of the structures shown in FIGS. 5A or  5 B. By coupling the signals A and B to a voltage using antifuses  65  or fuses  68 , the manufacturer can easily select the signals A and B to be either HIGH or LOW, as desired. Although described here as controlling only one adjustable delay circuit  102 , a single delay adjusting circuit  60  may be used to adjust any or all of the adjustable delay circuits within a memory chip, thereby controlling the data delivery time at any or all of the DQ pads on the memory chip. 
     The operation of the delay adjusting circuit  60  will now be described. In operation, one of the four delay times is selected through the states of signals A and B, as shown in the chart in FIG.  4 B. If A and B are each connected to respective adjustable impedance circuits  96  that are BLOWN, both A and B will be HIGH, indicated as “1” in FIG.  4 B. This places the passgates  82 ,  86 , and  90  in a passing state. Because the passgates  86  and  90  are passing, the signal CLKDOR* passes through the delay gate  76  having a delay of 1.5, and through the passgates  86  and  90  to the output terminal  95 . The CLKDOR* signal also passes through the delay gate  72 , having no delay and through the passgate  82 , but is blocked at the passgate  88 , which is in a blocking state by virtue of a HIGH B signal and a LOW signal received from the inverter  94 . By selecting the states of the signals A and B (by selectively adjusting the impedance circuits  96 ), it is easy to adjust the time delay of a clock signal input to the delay adjusting circuit  60 . In one embodiment, the delay time selected by keeping the adjustable impedance circuits  96  in their natural state will be the delay most likely to provide the greatest tolerances for both T AC  and T OH . In FIG. 4A this desired delay is 1.0. In this way, the majority of the memory chips will pass the T AC  and T OH  specifications without further adjustment, saving labor and equipment costs. Only in the extraordinary case will the delay need adjustment. Although shown here with only two columns of passgates controlled by the signals A and B, it is apparent that a greater selection of delay times can be made available with the addition of more control signals and more passgates, or that the passgates could have a different configuration. For instance, eight different delay times are efficiently selectable if three control signals are used, with three columns, one each containing two, four and eight passgates. 
     Although the delay adjusting circuit  60  is shown after the clock circuitry  15 , it can appear in many locations in a synchronized memory circuit, some of which are illustrated in FIG.  3 . For instance, the delay adjusting circuit  60  can appear directly before the clock circuitry  15 . If the delay adjusting circuit  60  is placed after the passgates  24  and  26 , the delay adjusting circuit must be implemented in pairs because the data has two separate paths. Only one delay adjusting circuit  60  is needed if it is located between an output terminal  37  and the DQ pad  40 . Of course, there are other locations where the delay adjusting circuit  60  could be placed, as long as it is between the clock signal input  7  and the DQ pad  40 . 
     A synchronous dynamic random access memory (SDRAM)  200  using the adjustable time delay circuit  102  of FIG. 3 is shown in FIG.  6 . The SDRAM  200  has a control logic circuit  202  receiving a clock signal CLK and a clock enable signal CKE. In the SDRAM  200 , all operations are referenced to a particular edge of an internal clock signal ICLK and a data read clock CLKDOR*, both generated from the clock signal CLK. The edge of the ICLK signal that is used is typically the rising edge, while the data read operations are referenced to the falling edge of the CLKDOR*, as known in the art. The delay adjusting circuit  60  is preferably included in the control logic  202  to adjust the timing of the data read clock CLKDOR* relative to the clock signal CLK. In practice, a variety of internal clock signals may be generated from the clock signal CLK, and only some of them may have their timing controlled by the delay adjusting circuit  60 . However, in the interest of brevity, only two internal clock signals, ICLK and CLKDOR* are shown. The control circuit  202  further includes a command decode circuit  204  receiving a number of command signals on respective external terminals of the SDRAM  200 . These command signals typically include a chip select signal {overscore (CS)}, write enable signal {overscore (WE)}, column address strobe signal {overscore (CAS)}, and row address strobe signal {overscore (RAS)}. Specific combinations of these signals define particular data transfer commands of the SDRAM  200  such as ACTIVE, PRECHARGE, READ, and WRITE as known in the art. An external circuit, such as a processor or memory controller generates these data transfer commands to read data from and to write data to the SDRAM  200 . 
     The SDRAM  200  further includes an address register  206  operable to latch an address applied on an address bus  208 , and output the latched address to the control circuit  202 , a column address latch  210 , and a row address multiplexer  212 . During operation of the SDRAM  200 , a row address with a bank address BA and a column address with the bank address are sequentially latched by the address register  206  under control of the control circuit  202 . In response to the latched bank address BA and row address, the control circuit  202  controls the row address multiplexer  212  to latch and output the row address to one of a row address latch  214  and  216 . The row address latches  214  and  216 , when activated, latch the row address from the row address multiplexer  212  and output this latched row address to an associated row decoder circuit  222  and  224 , respectively. The row decoder circuits  222  and  224  decode the latched row address and activate a corresponding row of memory cells in memory banks  218  and  220 , respectively. The memory banks  218  and  220  each include a number of memory cells (not shown) arranged in rows and columns, each memory cell operable to store a bit of data and having an associated row and column address. 
     When a column address and bank address BA is applied on the address bus  208 , the column address is latched by the address register  206  under control of the control circuit  202 , and output to a column address latch  210 , which latches the column address and in turn outputs the column address to a burst counter circuit  226 . The burst counter circuit  226  operates to develop sequential column addresses beginning with the latched column address when the SDRAM  200  is operating in a burst mode. The burst counter  226  outputs the developed column addresses to a column address buffer  228 , which in turn outputs the developed column address to a pair column decoder circuits  230  and  231 . The column decoder circuits  230  and  231  decode the column address and activates one of a plurality of column select signals  232  corresponding to the decoded column address. The column select signals  232  are output to sense amplifier and I/O gating circuits  234  and  236  associated with the memory banks  218  and  220 , respectively. The sense amplifier and I/O gating circuits  234  and  236  sense and store the data placed on the digit lines  235  and  237 , respectively, by the memory cells in the addressed row and to thereafter couple the digit lines  235  or  237  corresponding to the addressed memory cell to an internal data bus  238 . The internal data bus  238  is coupled to a data bus  240  of the SDRAM  200  through either a data input register  242  or a data output register  244 . In the preferred embodiment, the adjustable time delay circuit  102  is coupled to the data output register  244 . This circuit is used to adjust the time data is presented to the data bus in reference to the clock signal CLK. A data mask signal DQM controls the circuits  234  and  236  to avoid data contention on the data bus  240  when, for example, a READ command is followed immediately by a WRITE command, as known in the art. 
     In operation, during a read data transfer operation, an external circuit, such as a processor, applies a bank address BA and row address on the address bus  208  and provides an ACTIVE command to the command decode circuit  204 . This applied address and command information is latched by the SDRAM  200  on the next rising edge of the clock signal CLK, and the control circuit  202  thereafter activates the addressed memory bank  218  or  220 . The supplied row address is coupled through the row address multiplexer  212  to the row address latch  214  or  216  associated with the addressed bank, and this row address is thereafter decoded and the row of memory cells in the activated memory bank  218  or  220  is activated. The sense amplifiers in the sense amplifier and I/O gating circuit  234  or  236  sense and store the data contained in each memory cell in the activated row of the addressed memory bank  218  or  220 . 
     The external circuit thereafter applies a READ command to the command decode circuit  204  including a column address and bank address BA on the address bus  208 , both of which are latched on the next rising edge of the clock signal CLK. The latched column address is then routed through the circuits  210 ,  226 , and  228  to the column decoder circuit  230  under control of the control circuit  204 . The column decoder  230  decodes the latched column address and activates the column select signal  232  corresponding to that decoded column address. In response to the activated column select signal  232 , the sense amplifier and I/O gating circuit  234  or  236  transfers the addressed data onto the internal data bus  238 , and the data is then transferred from the internal data bus  238  through the data output register  244  and onto the data bus  240  where it is read by the external circuit. 
     During a write data transfer operation, after activating the addressed memory bank  218  or  220  and the addressed row within that bank, the external circuit applies a WRITE command to the command decode circuit  204  including a column address and bank address BA on the address bus  208  and data on the data bus  240 . The WRITE command, column address, and data are latched respectively into the command decode circuit  204 , address register  206 , and data input register  242  on the next rising edge of the clock signal CLK or an internal clock signal not generated by the delay adjusting circuit  60 . The data latched in the data input register  242  is placed on the internal data bus  238 , and the latched column address is routed through the circuits  210 ,  226 , and  228  to the column decoder circuit  230  under control of the control circuit  204 . The column decoder  230  decodes the latched column address and activates the column select signal  232  corresponding to that decoded address. In response to the activated column select signal  232 , the data on the internal data bus  238  is transferred through the sense amplifier and I/O gating circuit  234  or  236  to the digit lines  235  or  237  corresponding to the addressed memory cell. The row containing the addressed memory cell is thereafter deactivated to store the written data in the addressed memory cell. 
     Although the adjustable time delay circuit  102  has been described as being used in the SDRAM  200 , it will be understood that it may also be used in other types of integrated circuits such as synchronous graphics RAM (SGRAM), or synchronous static RAM (synchronous SRAM). Those skilled in the art realize the differences between SDRAM and other types of memories, and can easily implement the adjustable time delay circuit  102 . 
     FIG. 7 is a block diagram of a computer system  300  including the SDRAM  200  of FIG.  5 . The computer system  300  includes a processor  302  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. Coupled to the processor  302  is a synchronous SRAM circuit  303 , used for a memory cache or other memory functions. In addition, the computer system  300  includes one or more input devices  304 , such as a keyboard or a mouse, coupled to the processor  302  to allow an operator to interface with the computer system  300 . Typically, the computer system  300  also includes one or more output devices  306  coupled to the processor  302 , such output devices typically being a printer or a video terminal. One or more data storage devices  308  are also typically coupled to the processor  302  to store data or retrieve data from external storage media (not shown). Examples of typical data storage devices  308  include hard and floppy disks, tape cassettes, compact disk read-only memories (CD-ROMs), and digital videodisk read-only memories (DVD-ROMs). The processor  302  is typically coupled to the SDRAM  200  and to the synchronous SRAM  303  through a control bus, a data bus, and an address bus to provide for writing data to and reading data from the SDRAM and synchronous SRAM. A clocking circuit (not shown) typically develops a clock signal driving the processor  302 , SDRAM  200 , and synchronous SRAM  303  during such data transfers. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.

Technology Classification (CPC): 6