Patent Abstract:
An RF micro-electro-mechanical system including a first silicon wafer having a top surface and a bottom surface. The top surface being opposite the bottom surface. A bore extends through the first silicon wafer. A micro-electro-mechanical device is provided and coupled to the top surface of the first silicon wafer. An electrical feed line then extends along the bottom surface of the first silicon wafer and an electrical interconnect electrically couples the micro-electro-mechanical device and the electrical feed line through the bore.

Full Description:
STATEMENT OF GOVERNMENTAL SUPPORT  
       [0001] This invention was made with Government support under Grant No. ECS-9979374 awarded by the National Science Foundation and Grant No. 2001-0694-02 awarded by the U.S. Army. The government has certain rights in this invention. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention generally relates to RF MEMS switches and, more particularly, to a RF MEMS switch that provides lower loss and better performance in K-band and further provides a method of fabrication of the RF MEMS package with all components on a single wafer without the need for external wires.  
         BACKGROUND OF THE INVENTION  
         [0003]    Integrated circuit (IC) packaging and testing has evolved over the past years due to the maturity of the IC industry, the availability of highly advanced infrastructure, and the wide applicability of the integrated circuits. In general, the goal for IC packaging is to provide an electrical interface to active chips in the system, to supply signal power and ground interconnections, to facilitate heat dissipation, and to at least partially protect the chips from the environment.  
           [0004]    On the other hand, the requirements of micro electro mechanical systems (MEMS) packaging are different from those of IC packaging in that MEMS packaging requirements are application specific and, thus, different designs are used for different circuits. This lack of standardization leads to excessive cost associated with MEMS products.  
           [0005]    Similarly, millimeter wave systems for commercial, scientific, or military applications are rapidly emerging that require development of packaging technologies that are capable of shielding high radio frequencies. For example, the performance requirements for high-density, high frequency (i.e. 5-100 GHz) packages are very stringent, since poor design and fabrication can lead to increased cavity resonances and cross-talk between neighboring circuits. Although many low cost materials can be utilized for packaging, such as plastic and alumina, these materials typically suffer from poor electrical performance at frequencies beyond 10 GHz.  
           [0006]    Silicon on the other hand has been extensively used and studied in the electronics industry. Its electrical properties have enabled the semiconductor industry to use it as the primary dielectric material in developing integrated circuits, while its mechanical properties have been utilized to develop high performance micro-electro-mechanical system (MEMS) structures.  
         SUMMARY OF THE INVENTION  
         [0007]    According to the teachings of the present invention, an RF micro-electro-mechanical system is provided having an advantageous construction. The RF MEMS system includes a first silicon wafer having a top surface and a bottom surface. The top surface is opposite the bottom surface. A bore extends through the first silicon wafer. A micro-electro-mechanical device is provided and coupled to the top surface of the first silicon wafer. An electrical feed line then extends along the bottom surface of the first silicon wafer and an electrical interconnect electrically couples the micro-electro-mechanical device and the electrical feed line through the bore.  
           [0008]    Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:  
         [0010]    [0010]FIG. 1 is a cross-sectional view illustrating an RF MEMS switch assembly according to a first embodiment of the present invention;  
         [0011]    [0011]FIG. 2 is a plan view illustrating the RF MEMS switch assembly with the top wafer removed for clarity;  
         [0012]    [0012]FIG. 3 is an enlarged plan view illustrating the RF MEMS switch assembly with the top wafer removed for clarity  
         [0013]    [0013]FIG. 4 is a perspective view of the RF MEMS switch assembly illustrating the bottom side of the top wafer, the top side of the bottom wafer, and the bottom side of the bottom wafer;  
         [0014]    [0014]FIG. 5 is a graph illustrating the measured response of the RF interconnect;  
         [0015]    [0015]FIG. 6 is a graph illustrating the measured response of RF MEMS switch assembly;  
         [0016]    [0016]FIG. 7 is a cross-sectional view illustrating an RF MEMS switch assembly according to a second embodiment of the present invention;  
         [0017]    [0017]FIG. 8 is a perspective view illustrating an interconnect along an inclined plane of a cavity formed on the bottom wafer;  
         [0018]    [0018]FIG. 9 is an enlarged perspective view illustrating the interconnect along the inclined plane of the cavity formed on the bottom wafer;  
         [0019]    [0019]FIG. 10 is a perspective view of the RF MEMS switch assembly illustrating the top side of the bottom wafer and the bottom side of the bottom wafer according to another embodiment of the present invention;  
         [0020]    [0020]FIG. 11 is a perspective view illustrating the RF MEMS switch assembly having a MEMS switch fabricated thereon;  
         [0021]    [0021]FIG. 12 is a graph illustrating the measured response of the RF inconnect before fabricating the MEMS switch; and  
         [0022]    [0022]FIG. 13 is a graph illustrating the measured response of the RF interconnect after fabricating the MEMS switch.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.  
         [0024]    Referring to FIG. 1, an RF MEMS switch assembly  10  is illustrated according to the principles of the present invention. RF MEMS switch assembly  10  generally includes a top wafer  12  and a bottom wafer  14 , which are generally bonded together about their peripheral edge at bond  16 . In the exemplary embodiment appropriate through-wafer interconnects extend through bottom wafer  14 . More particularly, these through-wafer interconnects include an RF interconnect  18  and a direct current (DC) interconnect  20 . As will be described in detail, RF interconnect  18  and DC interconnect  20  are electrically coupled to a MEMS switch or other device  22  and, thus, provide the necessary RF feed and DC feed to MEMS switch  22 .  
         [0025]    RF MEMS switch assembly  10  further includes an RF feed line  24  electrically coupled to RF interconnect  18  and a DC feed line  26  electrically coupled to DC interconnect  20 . RF feed line  24  and DC feed line  26  formed (or printed) on a side opposite of MEMS switch  22  on bottom wafer  14 .  
         [0026]    Preferably, top wafer  12  includes a cavity  28  formed along bottom side  32   a  that is sized to accommodate MEMS switch  22 . Moreover, in this embodiment it is preferable that top wafer  12  and bottom wafer  14  are each a high-resistivity, double-side polished silicon wafers having a 8700 Å SiO 2  layer  34  disposed on top sides  30   a ,  30   b  and bottom sides  32   a ,  32   b . However, it should be appreciated that the teachings of the present invention should not be regarded as being limited to the specific wafer composition and arrangement disclosed in this exemplary embodiment. Still further, it is preferable that bond  16  is made of a gold, gold/chrome, or platinum material. However, any bonding material sufficient to achieve and maintain a satisfactory bond may be used.  
         [0027]    RF interconnect  18  and DC interconnect  20  provide advantages over known designs, such as, but not limited to, excellent electrical performance in K-band. That is, RF MEMS switch assembly  10  is capable of an insertion loss of 0.1 dB and a return loss of 32 dB at 20 GHz. Moreover, RF MEMS switch assembly  10  is manufactured concurrently with MEMS switch  22  on bottom wafer  14  and includes vertical electrical interconnections. Therefore, RF MEMS switch assembly  10  does not require solder bumps or bond wires to achieve signal propagation, which is a signature of conventional systems.  
       FABRICATION  
       [0028]    Fabrication of RF MEMS switch assembly  10  is a multiphase process involving both surface and bulk micromachining. As described above, top wafer  12  and bottom wafer  14  are preferably high-resistivity double-side polished silicon wafers. In the present embodiment, top wafer  12  is 200 μm thick and bottom wafer  14  is 100 μm thick. SiO 2  layer  34  is thermally deposited on top side  30   a ,  30   b  and bottom side  32   a ,  32   b  of top wafer  12  and bottom wafer  14 , respectively, to allow for dual side processing. A 500/9500 Å Cr/Au layer  36  is deposited on bottom wafer  14  using a conventional lift-off process in order to form RF feed lines  24  and DC feed lines  26 . SiO 2  is then patterned on top side  30   b  of bottom wafer  14  using infrared (IR) alignment and then etched fully in buffered hydrofluoric acid (BHF) at a rate of 1000 Å/min. Oxide-patterned RF interconnect  18  and DC interconnect  20  are etched in potassium hydroxide (KOH) at an etch rate of 30 Å/min. Finally, RF feed line  24 , DC feed line  26 , RF interconnect  18 , and DC interconnect  20  are then metallized. A Cr/Au layer is deposited around the peripheral edge  36  of each wafer  12 ,  14  to be used for thermocompression bonding to form bond  16 .  
         [0029]    Fabrication of MEMS switch  22  requires an independent five mask process of top side  30   b  of bottom wafer  14 . It should be noted that in order to facilitate further processing of bottom wafer  14 , bottom wafer  14  may be mounted on a glass slide using photoresist (SHIPLEY PR-1827). However, it should be understood that this step is optional. The method of manufacturing MEMS switch  22  includes first depositing 2000 Å of plasma enhanced chemical vapor deposition (PECVD) silicon nitride in a predetermined patterned over the location where MEMS switch  22  is to be placed. A sacrificial layer of 3 μm thick polyimide (DUPONT PI2545) is then spun cast, soft baked, and patterned to define anchor points  38  for MEMS switch  22  (see FIG. 2) for anchor points. To define the structure of MEMS switch  22 , 2 μm of Ni is electroplated upon bottom wafer  22 . Furthermore, 4 μm of Ni is selectively electroplated on the switch actuation pads. Sacrificial etching of the 3 μm thick polyimide layer and supercritical CO 2  drying and release of MEMS switch  22  is performed. MEMS switch  22  is shown in FIG. 3 where a scanning electron image of MEMS switch  22  and the RF interconnect is presented.  
         [0030]    Cavity  28  is then etched on top wafer  12 . The fabrication process steps are similar to the steps set forth above. That is, (a) a lift-off process is used for the metallization of Cr/Au (500/9500 Å) to fabricate a square metallic rim on underside  32   a  of top wafer  12 ; (b) SiO 2  is patterned on both sides of top wafer  12  using infrared (IR) alignment to define cavities and probe windows for the final alignment of top wafer  12  and bottom wafer  14  prior to bonding; (c) SiO 2  is then etched partially or fully in buffered hydrofluoric acid (BHF) at a rate of 1000 Å/min; and finally (d) the oxide-patterned cavities and probe windows are anisotropically etched in potassium hydroxide (KOH) at a rate of 30 Å/hour.  
         [0031]    Thermocompression bonding of top wafer  12  and bottom wafer  14  is performed with an ELECTRONIC VISIONS EV 501 Manual Wafer Bonder. Initially, top wafer  12  and bottom wafer  14  are cleaned with organic solvents in order to prevent any surface contamination. Once aligned, using appropriate alignment marks and probe windows, top wafer  12  and bottom wafer  14  are clamped together in the bond fixture and are heated to 350° C. A force of 200 N is applied to top wafer  12  and bottom wafer  14  for 30 minutes in order to achieve proper adhesion.  
         [0032]    With particular reference to FIG. 4, RF MEMS switch assembly  10  is illustrated in an accordion fashion to illustrate bottom side  32   a  of top wafer  12 , top side  30   b  of bottom wafer  14 , and bottom side  32   b  of bottom wafer  14 . As can be seen, top wafer  12  includes cavity  28  disposed along bottom side  32   a  of top wafer  12 . Similarly, bottom wafer  14  includes the plurality of RF interconnects  18  and DC interconnects  20 . A top side  40  of RF interconnect  18  is shown on top side  30   b  of bottom wafer  14 . A bottom side  42  of RF interconnect  18  is shown on bottom side  32   b  of bottom wafer  14 . Likewise, a top side  44  of DC interconnects  20  is shown on top side  30   b  of bottom wafer  14 . A bottom side  46  of DC interconnects  20  is shown on bottom side  32   b  of bottom wafer  14 . RF feed line  24  is shown being electrically coupled to bottom side  42  of RF interconnect  18  and a DC feed line  26  is shown being electrically coupled to bottom side  46  of DC interconnect  20 . DC interconnects  20  are connected to the FGC ground plane and to anchor points  38 . The distance between RF interconnect  18  and MEMS switch  22  is approximately 200 μm in the lateral direction.  
         [0033]    Referring now to FIGS.  7 - 9 , an FGC interconnect  48  is illustrated that is employed to interconnect RF feed line  24  and DC feed line  26  along an inclined plane  50  according to a second embodiment of the present invention. This second embodiment provides a method of achieving the favorable properties set forth in regard to the first embodiment when bottom wafer  14  is more than 100 μm thick. In this example, a bottom wafer  14 ′ is illustrated having a thickness of 200 μm. Accordingly, a cavity  100  is formed in bottom wafer  14 ′. Preferably, cavity  100  is sized to reduce a through thickness A to approximately 100 μm.  
         [0034]    More particularly, FGC interconnect  48  is fabricated by anisotropic etching of bottom wafer  14 ′ and photolithographic patterning of electrophoretically deposited photoresist. That is, bottom wafer  14 ′ is anisotropically etched in tetramethyl ammonium hydroxide (TMAH). TMAH is preferred over potassium hydroxide, since it produces smoother walls in cavity  100 . For the electrophoretic deposition, bottom wafer  14 ′ is coated with a metallic seed layer and is then immersed into a bath of suitable photoresist, such as SHIPLEY PEPR 2400. A potential difference is then applied between bottom wafer  14 ′ and a counter electrode (not shown), to produce FGC interconnect  48 . The quality and thickness of the photoresist coverage are dependent on the bath temperature, the resist concentration, and the deposition voltage. Following deposition, the desired pattern is exposed with a conventional mask aligner and developed. A lift-off technique is then utilized to achieve the final metal deposition.  
       Measured Results  
       [0035]    Referring to FIG. 5, a graph is shown illustrating the measured S-parameter (dB) of RF interconnect  18  versus the applied frequency. For these measurements, an HP 8510C vector network analyzer is utilized on an ALESSI probe station with 150 μm pitch GGB picoprobes. Through-Reflect-Line (TRL) calibration is performed using on wafer calibration standards fabricated in conjunction with the circuits to be tested. MULTICAL, developed by NIST, is used to implement the TRL calibration. After deembeding the loss of the FGC feeding line, RF interconnect  18  demonstrates a 0.1 dB insertion loss, a 32 dB return loss at 20 GHz, and a 55% bandwidth. Thus, the loss due to each interconnect  18 ,  20  is approximately 0.05 dB.  
         [0036]    Referring now to FIG. 6, the measured response of RF MEMS switch assembly  10  can been seen. When MEMS switch  22  is in an up position, its capacitance is 38 fF and, therefore, has only a minor effect on the response of the circuit. The loss due to individual MEMS switch  22  is on the order of 0.16 dB at 40 GHz and, hence, the insertion loss of the total circuit of RF MEMS switch assembly  10  is increased by only a small amount.  
         [0037]    When MEMS switch  22  is in the down position its capacitance increases to 1.6 pF (as can be seen by the S-parameter). The isolation of RF MEMS switch assembly  10  is approximately −22 dB at 40 GHz. As can be seen in FIG. 6, resonance occurs at around 29 GHz, which degrades the performance of RF MEMS switch assembly  10  in both the up and down positions. Comparing the measurements illustrated in FIGS. 5 and 6, it can be seen that the operational frequency band for RF MEMS switch assembly  10  is between 11 and 24 GHz, with an insertion loss of 0.15 dB (switch loss included) and an isolation of −16 dB at 24 GHz.  
         [0038]    As described above, packaging of high frequency MEMS devices is often challenging since achieving signal distribution and environmental protection requires careful design and fabrication. RF MEMS switch assembly  10  of the present invention provides a method for overcoming such challenges. Particularly, RF MEMS switch assembly  10  demonstrates an insertion loss of 0.1 dB and a return loss of 32 dB at 20 GHz, which was unattainable until now.  
         [0039]    In order to increase the operational bandwidth of RF MEMS switch assembly  10 , a new interconnect is provided. Again the concept of interconnecting from a 50 Ω FGC line (50-80-50 μm) to a much wider 50 Ω FGC line (90-220-90 μm) in order to allow for the anisotropic etching of the interconnects is adhered to. However, it should be understood that by removing the stubs that have been previously used to tune the transition, a much broader response is achievable. This new interconnect is illustrated in FIGS. 10 and 11, while the response is illustrated in FIGS. 12 and 13. Specifically, FIG. 10 illustrates the top side of the bottom wafer and the bottom side of the bottom wafer. As can be appreciated from the graphs of FIGS. 12 and 13, this new interconnect can be operated from 0-50 GHz and has no unwanted resonances.  
         [0040]    The measured response of the vertical back-to-back transition is displayed in FIG. 12. The package demonstrates an operation bandwidth from DC-40 GHz with a return loss lower than −25 dB throughout the band. The measuresments summarized in FIGS. 12 and 13 include a 2700 μm through line, therefore the total insertion loss is about 0.4 dB at 38 GHz. If the losses from the FGC feeding lines are deembedded, the transition demonstrates a 0.06 dB loss up to 40 GHz and, thus, the loss die to each individual via transition is insignificant and approximately 0.03 dB. Taking into account the fact that no external wire bonding is needed in order to achieve signal propagation, this is the only loss introduced by the present invention.  
         [0041]    Referring now to FIG. 13, the measured response of the complete RF transition and MEMS switch in both the up and down position is illustrated. The up-capacitance of the switch, as extracted from the S-parameters, is 70 fF. This capacitance introduces a loss of approximately 0.3 dB at 20 GHz. The return loss at higher frequencies is increased due to the capacitance introduced by the switch, however it remains below −10 dB up to 40 GHz. When the switch is in the down position, its capacitance increases to 1.9 pF (as can be extracted from the S-parameters) and the measured isolation is approximately −23 dB at 40 GHz. These measured results illustrate that the broad bandwidth of this package renders it applicable for both low and high frequency MEMS devices.  
         [0042]    MEMS technology has major applications in developing smaller, faster and less energy consuming devices provided that reliability of packaging and interconnection technology is sufficiently addressed. The present invention presents a low cost, on-wafer, silicon micromachined packaging scheme for RF MEMS switches having excellent electrical performance in K-band.  
         [0043]    The description of the invention is merely exemplary in nature and, thus, variations that do not depart from the gist of the invention are intended to be within the scope of the invention. Such variations are not to be regarded as a departure from the spirit and scope of the invention.

Technology Classification (CPC): 1