Patent Abstract:
A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a division of U.S. application Ser. No. 15/201,628 filed Jul. 5, 2016, which is included in its entirety herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
       [0002]    The present invention relates to the field of semiconductor processing. More particularly, the present invention relates to a method of planarizing a substrate surface that is capable of improving amorphous-Si CMP loading and achieving high degree of planarity. 
       2. Description of the Prior Art 
       [0003]    Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. 
         [0004]    However, variation in pattern density causes difference of CMP removal rate between dense region and semi-dense region, resulting in poor within-die (WID) loading. Therefore, there is a need in this industry to provide an improved method of planarizing a substrate surface that is capable of improving the WID loading. 
       SUMMARY OF THE INVENTION 
       [0005]    It is one object of the invention to provide an improved method of planarizing a substrate surface that is capable of improving amorphous-Si CMP loading and achieving high degree of planarity. 
         [0006]    According to one aspect of the invention, a method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the major surface of the material layer. The photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate. At least a portion of the material layer not covered by the photoresist pattern is etched away. The photoresist pattern is removed. A polish stop layer is deposited on the major surface of the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer. A dry etching process is performed to etch the cap layer, the polishing stop layer, and the material layer. 
         [0007]    According to one embodiment, a method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A polish stop layer is deposited on the major surface of the material layer. A cap layer is deposited on the polish stop layer. A photoresist pattern is formed on the cap layer. The photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate. At least a portion of the cap layer not covered by the photoresist pattern is etched away. The photoresist pattern is removed. A chemical mechanical polishing (CMP) process is performed to polish the cap layer. A dry etching process is performed to etch the cap layer, the polishing stop layer, and the material layer. 
         [0008]    According to another embodiment, a method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A polish stop layer is deposited on the major surface of the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer. A photoresist pattern is formed on the cap layer. The photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate. At least a portion of the cap layer not covered by the photoresist pattern is etched away. The photoresist pattern is removed. A dry etching process is performed to etch the cap layer, the polishing stop layer, and the material layer. 
         [0009]    According to another embodiment, a method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A polish stop layer is deposited on the major surface of the material layer. A photoresist pattern is formed on the polish stop layer. The photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate. At least a portion of the polish stop layer not covered by the photoresist pattern is etched away. The photoresist pattern is removed. A cap layer is deposited on the polish stop layer and on the material layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  to  FIG. 6  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with one embodiment of the invention. 
           [0012]      FIG. 7  to  FIG. 13  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with another embodiment of the invention. 
           [0013]      FIG. 14  to  FIG. 20  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with other embodiments of the invention. 
           [0014]      FIG. 21  to  FIG. 26  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with still another embodiment of the invention. 
           [0015]      FIG. 27  to  FIG. 32  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with yet another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. 
         [0017]    The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. 
         [0018]    The terms substrate used herein include any structure having an exposed surface onto which a layer may be deposited according to the present invention, for example, to form the integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. The term substrate may include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. 
         [0019]    Please refer to  FIG. 1  to  FIG. 6 .  FIG. 1  to  FIG. 6  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with one embodiment of the invention. 
         [0020]    As shown in  FIG. 1 , a substrate  1  is provided. The substrate  1  may comprise a semiconductor bulk layer  10  such as a silicon layer, a silicon substrate, or the like. The semiconductor bulk layer  10  may have a pre-selected conductivity type, for example, P type or N type. According to various embodiments, the semiconductor bulk layer  10  may include, but not limited to, silicon, silicon-containing material, GaN-on-silicon (or other materials of Group III-V), grapheme-on-silicon or silicon-on-insulator (SOI), but is not limited thereto. 
         [0021]    An isolation layer  12  maybe formed on or in the semiconductor bulk layer  10 . For example, the isolation layer  12  may comprise shallow trench isolation (STI). 
         [0022]    According to the embodiment, the substrate  1  may further comprise a plurality of fin structures  101  and  102 , which may be integrally formed with the semiconductor bulk layer  10  and may protrude from a top surface of the isolation layer  12 . According to the embodiment, the fin structures  101  are arranged in the first region R 1  and the fin structures  102  are arranged in the second region R 2 . The first region R 1  and the second region R 2  may be two spaced-apart, non-overlapping regions. 
         [0023]    According to the embodiment, the fin structures  101  are more densely packed than the fin structures  102 . A material layer  14  such as an amorphous silicon layer may be deposited on the fin structures  101  and  102  and on the isolation layer  12 . 
         [0024]    The fin structures  101  and  102  are covered with the material layer  14 . According to the embodiment, the material layer  14  has a major surface S with a topography including a large bump  14   a  in the first region R 1  and several small bumps  14   b  in the second region R 2 . According to the embodiment, the material layer  14  has a relatively lower removal rate in the first region R 1  than that in the second region R 2  during a chemical mechanical polishing (CMP) process due to the topography of the major surface S. 
         [0025]    As shown in  FIG. 2 , a mask layer  20  including a hard mask  21  and a photoresist pattern  22  is formed on the major surface S of the material layer  14 . An opening  200  is formed in the mask layer  20  to expose the material layer  14  in the first region R 1 . The second region R 2  is covered with the mask layer  20 . According to the embodiment, the large bump  14   a  in the first region R 1  is exposed in the opening  200 . 
         [0026]    As shown in  FIG. 3 , using the photoresist pattern  22  and the hard mask  21  as an etching hard mask, an etching process is performed to remove at least a portion of the material layer  14  from the opening  200 . Subsequently, the remaining mask layer  20  including the photoresist pattern  22  and the hard mask  21  is completely removed. At this point, the large bump  14   a  in the first region R 1  may be eliminated to thereby form a surface that is coplanar with or lower than the surface in the second region R 2 . 
         [0027]    As shown in  FIG. 4 , after removing the mask layer  20 , a polish stop layer  31  is conformally deposited on the major surface S of the material layer  14 . According to the embodiment, the polish stop layer may comprise silicon nitride, but is not limited thereto. Subsequently, a cap layer  32  is conformally deposited on the polish stop layer  31 . According to the embodiment, the cap layer  32  may comprise silicon oxide or amorphous silicon. According to the embodiment, the cap layer  32  may have a topography that is similar to that of the major surface S of the material layer  14 . 
         [0028]    As shown in  FIG. 5 , after depositing the cap layer  32 , a chemical mechanical polishing (CMP) process is performed to polish the cap layer  32 . According to the embodiment, the CMP process stops on the polish stop layer  31 . According to the embodiment, at the end point and upon the exposure of the polish stop layer  31 , a portion of the cap layer  32  may remain in the first region R 1 . 
         [0029]    As shown in  FIG. 6 , a dry etching process is then performed to etch the remaining cap layer  32 , the polishing stop layer  31 , and the material layer  14  until a target thickness t of the material layer  14  is reached. According to the embodiment, the dry etching process is performed at a substantially same etching rate with respect to the cap layer  32 , the polishing stop layer  31 , and the material layer  14 . According to the embodiment, after the dry etching process is completed, the material layer  14  has a flat major surface. 
         [0030]    Please refer to  FIG. 7  to  FIG. 13 .  FIG. 7  to  FIG. 13  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with another embodiment of the invention. 
         [0031]    As shown in  FIG. 7 , likewise, a substrate  1  is provided. The substrate  1  may comprise a semiconductor bulk layer  10  such as a silicon layer, a silicon substrate, or the like. An isolation layer  12  maybe formed on or in the semiconductor bulk layer  10 . For example, the isolation layer  12  may comprise shallow trench isolation (STI). 
         [0032]    According to the embodiment, the substrate  1  may further comprise a plurality of fin structures  101  and  102 , which may be integrally formed with the semiconductor bulk layer  10  and may protrude from a top surface of the isolation layer  12 . According to the embodiment, the fin structures  101  are arranged in the first region R 1  and the fin structures  102  are arranged in the second region R 2 . The first region R 1  and the second region R 2  may be two spaced-apart, non-overlapping regions. 
         [0033]    According to the embodiment, the fin structures  101  are more densely packed than the fin structures  102 . A material layer  14  such as an amorphous silicon layer may be deposited on the fin structures  101  and  102  and on the isolation layer  12 . 
         [0034]    The fin structures  101  and  102  are covered with the material layer  14 . According to the embodiment, the material layer  14  has a major surface S with a topography including a large bump  14   a  in the first region R 1  and several small bumps  14   b  in the second region R 2 . According to the embodiment, the material layer  14  has a relatively lower removal rate in the first region R 1  than that in the second region R 2  during a chemical mechanical polishing (CMP) process due to the topography of the major surface S. 
         [0035]    As shown in  FIG. 8 , a mask layer  20  including a hard mask  21  and a photoresist pattern  22  is formed on the major surface S of the material layer  14 . A plurality of openings  200   a  is formed in the mask layer  20  to partially expose the material layer  14  in the first region R 1 . The second region R 2  is completely covered with the mask layer  20 . According to the embodiment, the large bump  14   a  in the first region R 1  is partially exposed in the openings  200   a.    
         [0036]    As shown in  FIG. 9 , using the photoresist pattern  22  and the hard mask  21  as an etching hard mask, an etching process is performed to remove at least a portion of the material layer through the openings  200   a.    
         [0037]    Subsequently, as shown in  FIG. 10 , the remaining mask layer  20  including the photoresist pattern  22  and the hard mask  21  is completely removed. At this point, the large bump  14   a  in the first region R 1  may be transformed into several small bumps. 
         [0038]    As shown in  FIG. 11 , after removing the mask layer  20 , a polish stop layer  31  is conformally deposited on the major surface S of the material layer  14 . According to the embodiment, the polish stop layer may comprise silicon nitride, but is not limited thereto. Subsequently, a cap layer  32  is conformally deposited on the polish stop layer  31 . 
         [0039]    According to the embodiment, the cap layer  32  may comprise silicon oxide or amorphous silicon. According to the embodiment, the cap layer  32  may have a topography that is similar to that of the major surface S of the material layer  14 . 
         [0040]    As shown in  FIG. 12 , after depositing the cap layer  32 , a chemical mechanical polishing (CMP) process is performed to polish the cap layer  32 . According to the embodiment, the CMP process stops on the polish stop layer  31 . According to the embodiment, at the end point and upon the exposure of the polish stop layer  31 , a portion of the cap layer  32  may remain on the polish stop layer  31 . 
         [0041]    As shown in  FIG. 13 , a dry etching process is then performed to etch the remaining cap layer  32 , the polishing stop layer  31 , and the material layer  14  until a target thickness t of the material layer  14  is reached. According to the embodiment, the dry etching process is performed at a substantially same etching rate with respect to the cap layer  32 , the polishing stop layer  31 , and the material layer  14 . According to the embodiment, after the dry etching process is completed, the material layer  14  has a flat major surface. 
         [0042]    Please refer to  FIG. 14  to  FIG. 20 .  FIG. 14  to  FIG. 20  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with other embodiments of the invention, wherein like numeral numbers designate like layers, elements, or regions. 
         [0043]    As shown in  FIG. 14 , a substrate  1  is provided. The substrate  1  may comprise a semiconductor bulk layer  10  such as a silicon layer, a silicon substrate, or the like. An isolation layer  12  maybe formed on or in the semiconductor bulk layer  10 . For example, the isolation layer  12  may comprise shallow trench isolation (STI). 
         [0044]    According to the embodiment, the substrate  1  may further comprise a plurality of fin structures  101  and  102 , which may be integrally formed with the semiconductor bulk layer  10  and may protrude from a top surface of the isolation layer  12 . According to the embodiment, the fin structures  101  are arranged in the first region R 1  and the fin structures  102  are arranged in the second region R 2 . The first region R 1  and the second region R 2  may be two spaced-apart, non-overlapping regions. 
         [0045]    According to the embodiment, the fin structures  101  are more densely packed than the fin structures  102 . A material layer  14  such as an amorphous silicon layer may be deposited on the fin structures  101  and  102  and on the isolation layer  12 . 
         [0046]    The fin structures  101  and  102  are covered with the material layer  14 . According to the embodiment, the material layer  14  has a major surface S with a topography including a large bump  14   a  in the first region R 1  and several small bumps  14   b  in the second region R 2 . 
         [0047]    A polish stop layer  31  is conformally deposited on the major surface S of the material layer  14 . According to the embodiment, the polish stop layer  31  may comprise silicon nitride, but is not limited thereto. Subsequently, a cap layer  32  is conformally deposited on the polish stop layer  31 . According to the embodiment, the cap layer  32  may comprise silicon oxide or amorphous silicon. According to the embodiment, the cap layer  32  may have a topography that is similar to that of the major surface S of the material layer  14 . 
         [0048]    According to the embodiment, the cap layer  32  has a relatively lower removal rate in the first region R 1  than that in the second region R 2  during a chemical mechanical polishing (CMP) process due to the topography of the major surface S and the pattern density of the fin structures  101  and  102 . 
         [0049]    As shown in  FIG. 15 , a mask layer  20  including a hard mask  21  and a photoresist pattern  22  is formed on the top surface of the cap layer  32 . An opening  200  is formed in the mask layer  20  to expose the cap layer  32  in the first region R 1 . The second region R 2  is covered with the mask layer  20 . Alternatively, as shown in  FIG. 20 , the top surface of the cap layer  32  may be partially exposed by a mask layer  20  having a plurality of openings  200   a.    
         [0050]    As shown in  FIG. 16 , using the photoresist pattern  22  and the hard mask  21  as an etching hard mask, an etching process is performed to remove at least a portion of the cap layer  32  from the opening  200  (or from the openings  200   a  as depicted in  FIG. 20 ). 
         [0051]    Subsequently, as shown in  FIG. 17 , the remaining mask layer  20  including the photoresist pattern  22  and the hard mask  21  is completely removed. 
         [0052]    As shown in  FIG. 18 , a chemical mechanical polishing (CMP) process is performed to polish the cap layer  32 . According to the embodiment, the CMP process stops on the polish stop layer  31 . According to the embodiment, at the end point and upon the exposure of the polish stop layer  31 , a portion of the cap layer  32  may remain on the polish stop layer  31 . 
         [0053]    As shown in  FIG. 19 , a dry etching process is then performed to etch the remaining cap layer  32 , the polishing stop layer  31 , and the material layer  14  until a target thickness t of the material layer  14  is reached. According to the embodiment, the dry etching process is performed at a substantially same etching rate with respect to the cap layer  32 , the polishing stop layer  31 , and the material layer  14 . According to the embodiment, after the dry etching process is completed, the material layer  14  has a flat major surface. 
         [0054]    Please refer to  FIG. 21  to  FIG. 26 .  FIG. 21  to  FIG. 26  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with still another embodiment of the invention, wherein like numeral numbers designate like layers, elements, or regions. 
         [0055]    As shown in  FIG. 21 , likewise, a substrate  1  is provided. The substrate  1  may comprise a semiconductor bulk layer  10  such as a silicon layer, a silicon substrate, or the like. An isolation layer  12  maybe formed on or in the semiconductor bulk layer  10 . For example, the isolation layer  12  may comprise shallow trench isolation (STI). 
         [0056]    According to the embodiment, the substrate  1  may further comprise a plurality of fin structures  101  and  102 , which may be integrally formed with the semiconductor bulk layer  10  and may protrude from a top surface of the isolation layer  12 . According to the embodiment, the fin structures  101  are arranged in the first region R 1  and the fin structures  102  are arranged in the second region R 2 . The first region R 1  and the second region R 2  may be two spaced-apart, non-overlapping regions. In some embodiments, the first region R 1  may be contiguous with the second region R 2 . 
         [0057]    According to the embodiment, the fin structures  101  are more densely packed than the fin structures  102 . A material layer  14  such as an amorphous silicon layer may be deposited on the fin structures  101  and  102  and on the isolation layer  12 . 
         [0058]    The fin structures  101  and  102  are covered with the material layer  14 . According to the embodiment, the material layer  14  has a major surface S with a topography including a large bump  14   a  in the first region R 1  and several small bumps  14   b  in the second region R 2 . 
         [0059]    A polish stop layer  31  is conformally deposited on the major surface S of the material layer  14 . According to the embodiment, the polish stop layer  31  may comprise silicon nitride, but is not limited thereto. Subsequently, a cap layer  32  is conformally deposited on the polish stop layer  31 . According to the embodiment, the cap layer  32  may comprise silicon oxide or amorphous silicon. According to the embodiment, the cap layer  32  may have a topography that is similar to that of the major surface S of the material layer  14 . 
         [0060]    According to the embodiment, the cap layer  32  has a relatively lower removal rate in the first region R 1  than that in the second region R 2  during a chemical mechanical polishing (CMP) process due to the topography of the major surface S and the pattern density of the fin structures  101  and  102 . 
         [0061]    As shown in  FIG. 22 , after depositing the cap layer  32 , a chemical mechanical polishing (CMP) process is performed to polish the cap layer  32 . According to the embodiment, the CMP process stops on the polish stop layer  31 . According to the embodiment, at the end point and upon the exposure of the polish stop layer  31 , a portion of the cap layer  32  may remain on the polish stop layer  31 . 
         [0062]    As shown in  FIG. 23 , a mask layer  20  including a hard mask  21  and a photoresist pattern  22  is formed on the top surface of the cap layer  32 . An opening  200  is formed in the mask layer  20  to expose the cap layer  32  in the first region R 1 . The second region R 2  is covered with the mask layer  20 . 
         [0063]    As shown in  FIG. 24 , using the photoresist pattern  22  and the hard mask  21  as an etching hard mask, an etching process is performed to remove at least a portion of the cap layer  32  from the opening  200 . 
         [0064]    Subsequently, as shown in  FIG. 25 , the remaining mask layer  20  including the photoresist pattern  22  and the hard mask  21  is completely removed. 
         [0065]    As shown in  FIG. 26 , a dry etching process is then performed to etch the remaining cap layer  32 , the polishing stop layer  31 , and the material layer  14  until a target thickness t of the material layer  14  is reached. According to the embodiment, the dry etching process is performed at a substantially same etching rate with respect to the cap layer  32 , the polishing stop layer  31 , and the material layer  14 . According to the embodiment, after the dry etching process is completed, the material layer  14  has a flat major surface. 
         [0066]    Please refer to  FIG. 27  to  FIG. 32 .  FIG. 27  to  FIG. 32  are schematic, cross-sectional diagrams showing an exemplary method of planarizing a substrate surface in accordance with yet another embodiment of the invention, wherein like numeral numbers designate like layers, elements, or regions. 
         [0067]    As shown in  FIG. 27 , a substrate  1  is provided. The substrate  1  may comprise a semiconductor bulk layer  10  such as a silicon layer, a silicon substrate, or the like. An isolation layer  12  may be formed on or in the semiconductor bulk layer  10 . For example, the isolation layer  12  may comprise shallow trench isolation (STI). 
         [0068]    According to the embodiment, the substrate  1  may further comprise a plurality of fin structures  101  and  102 , which may be integrally formed with the semiconductor bulk layer  10  and may protrude from a top surface of the isolation layer  12 . According to the embodiment, the fin structures  101  are arranged in the first region R 1  and the fin structures  102  are arranged in the second region R 2 . The first region R 1  and the second region R 2  may be two spaced-apart, non-overlapping regions. 
         [0069]    A third region R 3  may be situated between the first region R 1  and the second region R 2 . According to the embodiment, no fin structure is formed within the third region R 3 . A top surface of the third region R 3  is lower than that of either the first region R 1  or the second region R 2 . 
         [0070]    According to the embodiment, the fin structures  101  are more densely packed than the fin structures  102 . A material layer  14  such as an amorphous silicon layer may be deposited on the fin structures  101  and  102  and on the isolation layer  12 . 
         [0071]    The fin structures  101  and  102  are covered with the material layer  14 . According to the embodiment, the material layer  14  has a major surface S with a topography including a large bump  14   a  in the first region R 1  and several small bumps  14   b  in the second region R 2 . 
         [0072]    A polish stop layer  31  is conformally deposited on the major surface S of the material layer  14 . According to the embodiment, the polish stop layer  31  may comprise silicon nitride, but is not limited thereto. 
         [0073]    As shown in  FIG. 28 , a mask layer  20  including a hard mask  21  and a photoresist pattern  22  is formed on the top surface of the polish stop layer  31  only within the third region R 3 . The polish stop layer  31  is exposed in the first region R 1  and in the second region R 2 . 
         [0074]    As shown in  FIG. 29 , using the photoresist pattern  22  and the hard mask  21  as an etching hard mask, an etching process is performed to remove at least a portion of the cap layer  32  from the first region R 1  and the second region R 2  . The remaining mask layer  20  is then removed, leaving the polish stop layer  31  in the third region R 3  intact. 
         [0075]    Subsequently, as shown in  FIG. 30 , a cap layer  32  is conformally deposited on the polish stop layer  31 . According to the embodiment, the cap layer  32  may comprise silicon oxide or amorphous silicon. According to the embodiment, the cap layer  32  may have a topography that is similar to that of the major surface S of the material layer  14 . 
         [0076]    According to the embodiment, the cap layer  32  has a relatively lower removal rate in the first region R 1  than that in the second region R 2  during a chemical mechanical polishing (CMP) process due to the topography of the major surface S and the pattern density of the fin structures  101  and  102 . According to the embodiment, the removal rate of the cap layer  32  in the third region R 3  is faster than that of the first region R 1  or the second region R 2 . 
         [0077]    As shown in  FIG. 31 , after depositing the cap layer  32 , a chemical mechanical polishing (CMP) process is performed to polish the cap layer  32 . According to the embodiment, the CMP process stops on the polish stop layer  31 . 
         [0078]    As shown in  FIG. 32 , a dry etching process is then performed to etch the remaining polishing stop layer  31  and the material layer  14  until a target thickness t of the material layer  14  is reached. According to the embodiment, the dry etching process is performed at a substantially same etching rate with respect to the polishing stop layer  31  and the material layer  14 . According to the embodiment, after the dry etching process is completed, the material layer  14  has a flat major surface. 
         [0079]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 7