Patent Abstract:
Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates to radiation-hardened circuits, and more particularly to a radiation-hardened latch circuit for reducing the propagation of pulses and other effects caused by single event transients. 
         [0003]    2. Discussion of the Related Art 
         [0004]    Single event transients (“SET”) can cause voltage glitches and pulses to be generated within an integrated circuit, thus causing disruption and degradation of performance by, for example, undesired switching of circuit blocks. These pulses and glitches can further propagate throughout the integrated circuit causing even further disruption and degradation of performance. 
         [0005]    What is desired, therefore, is a method and circuit that is itself radiation-hardened and will eliminate or at least substantially reduce the propagation of voltage pulses or glitches throughout the integrated circuit caused by the SET event. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    According to a first embodiment of the present invention, a radiation hardened latch circuit comprises a first latch stage having a first input for receiving a data signal, a second input for receiving a clock signal, and an output, and a second latch stage having a first input coupled to the output of the first latch stage, a second input for receiving an inverted clock signal, and an output for providing an output signal. The first latch stage comprises a first N-channel cascode stage coupled to the first input thereof, a second N-channel cascode stage coupled to the second input thereof, and a cross-coupled P-channel cascode stage coupled to the output thereof. The second latch stage comprises a first N-channel cascode stage coupled to the first input thereof, a second N-channel cascode stage coupled to the second input thereof, and a cross-coupled P-channel cascode stage coupled to the output thereof. The first and second inputs of the first and second latch stages comprise differential inputs. 
         [0007]    According to a second embodiment of the present invention, a radiation hardened latch circuit comprises a first latch stage having a first input for receiving a data signal, a second input for receiving a clock signal and an output, a second latch stage having an input-coupled to the output of the first latch stage and an output, a third latch stage having a first input coupled to the output of the second latch stage, a second input for receiving an inverted clock signal and an output, and a fourth latch stage having an input coupled to the output of the third latch stage and an output for providing an output signal. The first and third latch stages each comprise a first N-channel cascode stage coupled to the first input thereof, a second N-channel cascode stage coupled to the second input thereof, and a cross-coupled P-channel cascode stage coupled to the output thereof. The second and fourth latch stages each comprise an N-channel cascode stage coupled to the input thereof, and a cross-coupled P-channel cascode stage coupled to the output thereof. The first and second inputs of the first and third latch stages comprise differential inputs. 
         [0008]    According to a third embodiment of the present invention, a radiation hardened signal distribution circuit comprises a plurality of serially coupled latch circuits having an input for receiving an input signal, an output for providing an output signal, and an intermediate node for providing a tap signal. Each latch circuit comprises two or four latch stages, and the input signal can comprise a clock signal. 
         [0009]    According to a fourth embodiment of the present invention, a radiation hardened integrated circuit comprises a plurality of integrated circuit portions each for providing a standalone circuit function, and a plurality of latch circuits not associated with the standalone circuit function for interconnecting the plurality of circuit portions. The latch circuit can comprise a single latch circuit, or two serially-coupled latch circuits. In turn, the latch circuits can comprise two or four latch stages. 
         [0010]    According to a method of the present invention, radiation hardening an integrated circuit comprises providing a plurality of standalone circuit functions with a plurality of integrated circuit portions, and interconnecting the plurality of integrated circuit portions with a plurality of latch circuits not associated with the standalone circuit function. The latch circuits can comprise two or four latch stages. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0011]    The invention, together with its various features and advantages and other aspects, can be readily understood from the following more detailed description taken in conjunction with the accompanying drawing figures, in which: 
           [0012]      FIG. 1  is a schematic of a first RS latch circuit according to the prior art; 
           [0013]      FIG. 2  is a schematic of a second RS latch circuit according to the prior art; 
           [0014]      FIG. 3A  is a schematic of a first test circuit according to the present invention; 
           [0015]      FIG. 3B  is a schematic of a second test circuit according to the present invention; 
           [0016]      FIG. 4  is a schematic of a first latch circuit having two latch stages according to the present invention; 
           [0017]      FIG. 5  is a schematic of a second latch circuit having four latch stages according to the present invention; 
           [0018]      FIG. 6A  is a schematic of a clock distribution circuit according to the prior art; 
           [0019]      FIG. 6B  is a schematic of a clock distribution circuit according to the present invention; 
           [0020]      FIG. 7  is a block diagram of a first circuit partitioning for reducing SET glitches in an integrated circuit according to the present invention; and 
           [0021]      FIG. 8  is a block diagram of a second circuit partitioning for reducing SET glitches in an integrated circuit according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Referring now to  FIG. 1 , an RS latch  100  according to the prior art is shown. A P-channel transistor T 0  has a source coupled to VDD, a gate coupled to an RB input, and a drain coupled to a QB output. A P-channel transistor T 1  has a source coupled to VDD, a gate coupled to an SB input, and a drain coupled to a Q output. Transistors T 2  and T 3  form a cross-coupled pair. The N-channel transistor T 2  has a source coupled to VSS, a gate coupled to the Q output, and a drain coupled to the QB output. The N-channel transistor T 3  has a source coupled to VSS, a gate coupled to the QB output, and a drain coupled to the Q output. 
         [0023]    The logic state diagram for RS latch  100  is given below: 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Mode 
                 RB 
                 SB 
                 Q N+1   
                 QB N+1   
               
               
                   
                   
               
             
             
               
                   
                 N/A 
                 0 
                 0 
                 1 
                 1 
               
               
                   
                 NORMAL 
                 0 
                 1 
                 1 
                 0 
               
               
                   
                 NORMAL 
                 1 
                 0 
                 0 
                 1 
               
               
                   
                 NOOP 
                 1 
                 1 
                 Q N   
                 QB N   
               
               
                   
                   
               
             
          
         
       
     
         [0024]    It was observed by the inventor that the NOOP mode of operation wherein the RB and SB inputs are both high and the N/A mode of operation wherein the RB and SB inputs are both low could be used to stop the propagation of an errant input signal caused by an SET event. Errant pulses or glitches on the RB and SB inputs do not propagate past the output of the RS latch. 
         [0025]    Referring now to  FIG. 2 , an RS latch  200  according to the prior art is shown. Transistors T 0  and T 1  form a cross-coupled pair. The P-channel transistor T 0  has a source coupled to VDD, a gate coupled to a Q output, and a drain coupled to a QB output. The P-channel transistor T 1  has a source coupled to VDD, a gate coupled to the QB output, and a drain coupled to the Q output. An N-channel transistor T 2  has a source coupled to VSS, a gate coupled to an S input, and a drain coupled to the QB output. An N-channel transistor T 3  has a source coupled to VSS, a gate coupled to an R input, and a drain coupled to the Q output. 
         [0026]    The logic state diagram for RS latch  200  is given below: 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Mode 
                 R 
                 S 
                 Q N+1   
                 QB N+1   
               
               
                   
                   
               
             
             
               
                   
                 NOOP 
                 0 
                 0 
                 Q N   
                 QB N   
               
               
                   
                 NORMAL 
                 0 
                 1 
                 1 
                 0 
               
               
                   
                 NORMAL 
                 1 
                 0 
                 0 
                 1 
               
               
                   
                 N/A 
                 1 
                 1 
                 0 
                 0 
               
               
                   
                   
               
             
          
         
       
     
         [0027]    It was similarly observed by the inventor that the N/A mode of operation wherein the R and S inputs are both high and the NOOP mode of operation wherein the R and S inputs are both low could be used to stop the propagation of an errant input signal caused by an SET event. Errant pulses or glitches on the R and S inputs do not propagate past the output of the RS latch. 
         [0028]    According to the present invention, a first test circuit  300 A is shown in  FIG. 3A  for measuring the error rate for injected pulses. Test circuit  300  includes a first RS latch  302 , a last RS latch  304 , and plurality of serially coupled circuits under test (CUT) CUT 1 , CUT 2 , CUT 3 , and CUT 4 . While two RS latches and four CUTs are shown in test circuit  300 , any number of CUTs could be used. The Q output of latch  302  is coupled to the inputs of CUT 1 . The output of a CUT (CUT 1 , for example) is coupled to the input of the next CUT in the chain (CUT 2 , for example). A first latch  302  has an RB input coupled to the Resetb input of the test circuit, and an SB input coupled to the Setb input of the test circuit. A last latch  304  has an RB input coupled to the output of CUT 4 , an SB input coupled to the Setb input of the test circuit, a Q output coupled to the Err output of the test circuit, and a QB output coupled to the Errb output of the test circuit. In operation, the test circuit  300 A is used to test the SET sensitivity of various circuits. 
         [0029]    According to the present invention, a second test circuit  300 B is shown in  FIG. 3B  for measuring the error rate for injected pulses. Test circuit  300 B includes a plurality of serially coupled RS latches I 0 , I 1 , I 2 , I 3 , I 4 , and I 5 . While six RS latches are shown in test circuit  300 B, any number of latches could be used. The Q and QB outputs of each latch are coupled to the S and R inputs of the next latch in the chain. A first latch I 0  has an RB input coupled to the Resetb input of the test circuit, and an SB input coupled to the Setb input of the test circuit. A last latch I 5  has an RB input coupled to the Q output of latch I 4 , an SB input coupled to the Setb input of the test circuit, a Q output coupled to the Err output of the test circuit, and a QB output coupled to the Errb output of the test circuit. A SET pulse injection point for positive going pulses is at the R input of latch I 2 . A SET pulse injection point for negative going pulses is at the S input of latch I 3 . In operation, the test circuit  300 B is also used to test the SET sensitivity of various circuits. 
         [0030]    While an ordinary prior art RS latch could be used for the purpose of stopping glitches from propagating throughout an integrated circuit, the RS latch itself should be radiation hardened. That is to say, the RS latch of the prior art will be ineffective for stopping glitch propagation if it is directly hit by an SET event. 
         [0031]    According to an embodiment of the present invention, a radiation hardened latch circuit  400  is shown in  FIG. 4  wherein a first latch stage T 0 , T 1 , T 2 , T 3 , T 4 , T 5 , has a first input for receiving a D data signal directly and through inverter T 22 , T 23 , a second input for receiving a CLK clock signal, and an output N 1 , N 2 . A second latch stage T 12 , T 13 , T 14 , T 15 , T 18 , T 19  has a first input coupled to the output of the first latch stage, a second input for receiving an inverted clock signal through inverter T 20 , T 21 , and an output for providing an output signal Q, QB. The first latch stage comprises a first N-channel cascode stage T 4 , T 5  coupled to the first input thereof, a second N-channel cascode stage coupled to the second input thereof T 2 , T 3 , and a cross-coupled P-channel cascode stage T 0 , T 1  coupled to the output thereof. The second latch stage comprises a first N-channel cascode stage T 12 , T 13  coupled to the first input thereof, a second N-channel cascode stage T 14 , T 15  coupled to the second input thereof, and a cross-coupled P-channel cascode stage T 18 , T 19  coupled to the output thereof. As can be seen in  FIG. 4 , the first and second inputs of the first and second latch stages comprise differential inputs. The outputs of the first and second latch stages are also differential outputs. 
         [0032]    According to an embodiment of the present invention, a radiation hardened latch circuit  500  is shown in  FIG. 5  wherein a first latch stage T 0 , T 1 , T 2 , T 3 , T 4 , and T 5  has a first input for receiving a data signal directly and through inverter T 22 , T 23 , a second input for receiving a CLK clock signal, and an output N 1 , N 2 . A second latch stage T 6 , T 7 , T 8 , T 9  has an input coupled to the output of the first latch stage, and an output N 3 , N 4 . A third latch stage T 12 , T 13 , T 14 , T 15 , T 18 , T 19  has a first input coupled to the output of the second latch stage, a second input for receiving an inverted clock signal through inverter T 20 , T 21 , and an output N 5 , N 6 . A fourth latch stage T 10 , T 11 , T 16 , T 17  has an input coupled to the output of the third latch stage, and an output Q, QB for providing an output signal. The first and third latch stages each comprise a first N-channel cascode stage coupled to the first input thereof, a second N-channel cascode stage coupled to the second input thereof, and a cross-coupled P-channel cascode stage coupled to the output thereof. The second and fourth latch stages each comprise an N-channel cascode stage coupled to the input thereof, and a cross-coupled P-channel cascode stage coupled to the output thereof. The first and second inputs of the first and third latch stages comprise differential inputs. The first and third latch stages also comprise differential outputs. The second and fourth latch stages have differential inputs and outputs. 
         [0033]    Referring now to  FIG. 6A , a prior art clock distribution circuit  602  is shown including a plurality of inverters I 1  through  14 . Any number of inverters can be used as is known in the art. A first inverter I 1  receives a CLK IN input signal, and a last inverter I 4  provides a CLK OUT output signal. Intermediate tap nodes TAP 1 , TAP 2 , and TAP 3  provide the clock signal or inverted clock signals as is known in the art. The clock distribution circuit  602  is adequate for providing a plurality of clock signals throughout an integrated circuit. However, once generated SET induced glitches will propagate from the generation point throughout the entire circuit. 
         [0034]    Referring now to  FIG. 6B  a radiation hardened signal distribution circuit  604  according to the present invention comprises a plurality of serially coupled latch circuits RS 1 , RS 2 , RS 3 , and RS 4 . A first latch RS 1  has an input for receiving an input signal CLK IN and CLKB IN. A last latch RS 4  has an output for providing an output signal CLK OUT and CLKB OUT. A plurality of intermediate nodes provide clock and inverted clock tap signals TAP 1 A, TAP 1 B, TAP 2 A, TAP 2 B, TAP 3 A, and TAP 3 B. While requiring additional circuitry, the clock distribution circuit of  FIG. 6B  has the advantage that any SET induced glitches are stopped at least at the next latch stage and do not propagate further through the latch chain. Each latch circuit can comprise one or more latch stages as simple as shown in  FIG. 1  or  FIG. 2  or more complex latches as shown in  FIG. 4  or  FIG. 5 . Each latch circuit can comprise two latch stages as was shown with respect to latch circuit  400  shown in  FIG. 4  for additional radiation hardening. Each latch stage can also comprise four latch stages as was shown with respect to latch circuit  500  shown in  FIG. 5  for still further additional radiation hardening. While an input clock signal is shown in  FIG. 6B  other types of input signals can of course be distributed as desired. 
         [0035]    Referring now to  FIG. 7 , a radiation hardened integrated circuit  700  comprises a plurality of integrated circuit portions CKT # 1 , CKT # 2 , CKT # 3 , each for providing a standalone circuit function. A plurality of single latch circuits RS 1 , RS 2  not associated with the standalone circuit function are provided for interconnecting the plurality of circuit portions. The additional single latch circuits RS 1 , RS 2  are used solely for stopping the propagation of SET induced glitches as previously discussed. Each one of the single latch circuits can include two or four latch stages for additional radiation hardening as previously discussed. 
         [0036]    Referring now to  FIG. 8 , a radiation hardened integrated circuit  800  comprises a plurality of integrated circuit portions CKT # 1 , CKT # 2 , CKT # 3 , each for providing a standalone circuit function. A plurality of two serially-coupled latch circuits RS 1 , RS 2  and RS 3 , RS 4  not associated with the standalone circuit function are provided for interconnecting the plurality of circuit portions. The additional latch circuits RS 1 , RS 2  and RS 3 , RS 4  are used solely for stopping the propagation of SET induced glitches as previously discussed. Each one of the latch circuits can include two or four latch stages for additional radiation hardening as previously discussed. 
         [0037]    A method of radiation hardening an integrated circuit has been shown comprising providing a plurality of standalone circuit functions with a plurality of integrated circuit portions, and interconnecting the plurality of integrated circuit portions with a plurality of latch circuits not associated with the standalone circuit function. 
         [0038]    It is to be understood that the above-described circuits, embodiments, and drawing figures are merely illustrative of the many possible specific embodiments that can be devised to represent applications of the principles of the present invention. Numerous and varied other arrangements can be devised in accordance with these principles by those skilled in the art without departing from the spirit and scope of the invention. For example, the exact details of the circuit topography, component values, power supply values, as well as other details may be obviously changed to meet the specifications of a particular application.

Technology Classification (CPC): 7