Patent Abstract:
A liquid crystal display and a control method thereof are disclosed. The pixel of the liquid crystal display comprises: a first switch element, a second switch element, a first storage capacitor, a second storage capacitor, a first liquid crystal capacitor, and a second liquid crystal capacitor. The control method comprises: providing a first sub-pixel charge stage, a second sub-pixel charge stage, and a normal display stage. The first sub-pixel charge stage comprises: turning on the first switch element and the second switch to input a first gray level signal to the first storage capacitor, the second storage capacitor, the first liquid crystal capacitor, and the second liquid crystal capacitor. The second sub-pixel charge stage comprises: turning off the second switch element and inputting a second gray level signal to the first storage capacitor and the first liquid crystal capacitor. The normal display stage comprises: turning off the first switch element.

Full Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwan Application Serial Number 96150838, filed Dec. 28, 2007, which is herein incorporated by reference. 
     FIELD OF THE INVENTION 
     This invention relates to a liquid crystal display, and more particularly, to a Multi-Domain Vertical Alignment (MVA) liquid display. 
     BACKGROUND OF THE INVENTION 
     Because of the advance of display technologies and the improvement of human life, people set higher and higher requirement for displays. A Liquid Crystal Display (LCD) can be easily made into a light, thin, short and small product, so that the LCD becomes the most popular display instead of a Cathode Ray Tube (CRT) display. A Multi-domain Vertical Alignment (MVA) display is a kind of LCD and has large viewing angle, so that the MVA display is highly expected. In the MVA display, aligning structure in a special shape is used to divide liquid crystal molecules corresponding to a pixel of the MVA display into several liquid crystal regions, and the optical characteristic of each of the liquid crystal regions can be used to compensate that of the others, so that the MVA display has large viewing angle for users. However, because the gray level-to-brightness curves corresponding to all viewing angles are different from each other, users can find brightness difference, when they watch the MVA display at different viewing angles. This effect is called color shift. 
     In conventional technologies, because the color shift between a side-view angle and a front-view angle is slight when the MVA display shows high gray level data and low gray level data, the MVA display controls the pixels thereof to show high gray level data and low gray level data simultaneously and set the continuous integration value of the high gray level data and low gray level data to be a value of a intermediate gray level data of a predetermined color, thereby the intermediate gray level data is showed by the MVA display. As mentioned above, the MVA display uses complementary high gray level data and low gray level data to decrease the opportunity of the generation of the color shift effect. 
     SUMMARY OF THE INVENTION 
     An aspect of the present invention is to provide a LCD and the control method thereof to show high gray level data and low gray level data simultaneously. 
     According to an embodiment of the present invention, the LCD includes a data line, a first scan line, a first reference signal line, and a first pixel. The first scan line is crossed over the data line. The first reference signal line is crossed over the data line. The first pixel includes a first switch element, a first storage capacitor, a second switch element, a second storage capacitor, a first liquid crystal capacitor, and a second liquid crystal capacitor. The first switch element is electrically connected to the data line and the first scan line. The first storage capacitor is electrically connected to the first switch element and the first reference signal line. The second switch element is electrically connected to the first switch element and the first reference signal line. The second storage capacitor is electrically connected to the second switch element and the first reference signal line. The first liquid crystal capacitor is electrically connected to the first switch element and the first storage capacitor. The second liquid crystal capacitor is electrically connected to the second switch element and the second storage capacitor. 
     According to another embodiment of the present invention, in the LCD control method, a first sub-pixel charge stage is firstly provided. Then, a second sub-pixel charge stage is provided. Thereafter, a normal display stage is provided. In the first sub-pixel charge stage, a first gray level signal is firstly outputted to the first pixel via the data line. Then, a first enable signal is outputted to the first switch element via the first scan line to input the first gray level signal to the first storage capacitor and the first liquid crystal capacitor. Thereafter, a second enable signal is outputted to the second switch element via the first reference signal line to input the first gray level signal to the second storage capacitor and the second liquid crystal capacitor. In the second sub-pixel charge stage, a second gray level signal is firstly outputted to the first pixel via the data line. Then, the first enable signal is outputted to the first switch element via the first scan line to input the second gray level signal to the first storage capacitor and the first liquid crystal capacitor. Thereafter, a first disable signal is outputted to the second switch element via the first reference signal line to enable the second storage capacitor and the second liquid crystal capacitor to store the first gray level signal. In the normal display stage, a second disable signal is outputted to the first switch element via the first scan line to enable the first storage capacitor and the first liquid crystal capacitor to store the second gray level signal. In addition, the first gray level signal is different from the second gray level signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
         FIG. 1  is a structure diagram showing a Liquid Crystal Display (LCD) according to a first embodiment of the present invention; 
         FIG. 2  is a circuit diagram showing pixels of the LCD according to the first embodiment of the present invention; 
         FIG. 3  is a flow chart showing a pixel control method of the LCD according to the first embodiment of the present invention; 
         FIG. 4  is a time sequence diagram showing the time sequence of the scan signal and the reference signal according to the first embodiment of the present invention; 
         FIG. 5  is a structure diagram showing a LCD according to a second embodiment of the present invention; 
         FIG. 6  is a circuit diagram showing pixels of the LCD according to the second embodiment of the present invention; and 
         FIG. 7  is a time sequence diagram showing the sequences of the control signals and the scan signals of the LCD according to the second embodiment of present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In order to make the illustration of the present invention more explicit and complete, the following description is stated with reference to  FIG. 1  through  FIG. 7 . 
     Refer to  FIG. 1  and  FIG. 2  simultaneously.  FIG. 1  is a structure diagram showing a Liquid Crystal Display (LCD)  100  according to a first embodiment of the present invention.  FIG. 2  is a circuit diagram showing pixels of the LCD  100  according to the first embodiment of the present invention. The LCD  100  includes a plurality of pixel rows  101 , and each of the pixel rows  101  includes a plurality of pixels  102 . Each of the pixels  102  is corresponding to a scan line, a data line, and a reference signal line, and includes two switches and two storage capacitors. In this embodiment, the pixel row  101   a  includes a pixel  102   a , and the pixel row  101   b  includes a pixel row  102   b . In  FIG. 2 , the pixel  102   a  is corresponding to a scan line  120 , a data line  122 , and a reference signal line  124 , and includes two sub-pixels  102   a ′ and  102   a ″. The sub-pixel  102   a ′ includes a first storage capacitor  152  and a first liquid crystal capacitor  142 . The sub-pixel  102   a ″ includes a second storage capacitor  156  and a second liquid crystal capacitor  146 . The pixel  102   b  is corresponding to scan line  130 , the data line  122  and a reference signal line  134 . There is a scan signal  126  inputted into the san line  120 , and there is a scan signal  136  inputted into the scan line  130 , and there is a data signal  123  inputted into the data line  122 , and there is a reference signal  128  inputted into the reference signal line  124 , and there is a reference signal  138  is inputted into the reference signal line  134 . 
     In the pixel  102   a , a first switch  150  is electrically connected to the scan line  120  and the data line  122 . The first storage capacitor  152  is electrically connected to a first switch  150  and the reference signal line  124 . The first liquid crystal capacitor  142  is electrically connected to the first switch  150  and a reference voltage source. The first witch  150  is controlled by the scan signal  126  to enable the first storage capacitor  152  and the first liquid crystal capacitor  142  to receive the data signal  123 . A second switch  154  is electrically connected to the first switch  150  and the reference signal line  124 . The second storage capacitor  156  is electrically connected to the second switch  154  and the reference signal line  124 . The second liquid crystal capacitor  146  is electrically connected to the second switch  154  and the reference voltage source. When the first switch  150  is turned on, the second switch  154  can be turned on by the reference signal  128  to enable the second storage capacitor  156  and the second liquid crystal capacitor  146  to receive the data signal  123 . 
     As mentioned above, the first switch  150  is used to determine if the sub-pixel  120   a ′ receives the data signal  123 , and the first switch  150  and the second switch  154  are used to determine if the sub-pixel  120 ″ receives the data signal  123 . When the sub-pixel  120   a ″ is controlled to receive the data signal  123 , it is required to turn on the first switch  150  via the scan line  120 . When the sub-pixel  120   a ″ is controlled to receive the data signal  123 , it is required to turn on the first switch  150  via the scan line  120  and turn on the second switch  154  via the reference signal line  124 . 
     Similarly, in the pixel  102   b  the third switch  160  is electrically connected to the scan line  130  and the data line  122 . A third storage capacitor  162  is electrically connected to a third switch  160  and a reference signal line  134 . A third liquid crystal capacitor  172  is electrically connected to a third switch  160  and the reference voltage source to turn on the third switch  160  in accordance with the scan signal  136  to enable the third storage capacitor  162  and the third liquid crystal capacitor  172  to receive the data signal  123 . A fourth switch  164  is electrically connected to the third switch  160  and the reference signal line  134 . The fourth storage capacitor  166  is electrically connected to the fourth switch  164  and the reference signal line  134 . The fourth liquid crystal capacitor  176  is electrically connected to the fourth switch  164  and the reference voltage source. When third switch  160  is turned on, the fourth switch can be turned on in accordance with the reference signal  138  to enable the fourth storage capacitor  166  and the fourth liquid crystal capacitor  176  to receive the data signal  123 . 
     Refer to  FIG. 3  and  FIG. 4  simultaneously.  FIG. 3  is a flow chart showing a pixel control method  200  of the LCD  100  according to the first embodiment of the present invention.  FIG. 4  is a time sequence diagram showing the time sequence of the scan signal and the reference signal according to the first embodiment of the present invention. In the pixel control method  200 , a first sub-pixel charge stage  202 , a second sub-pixel charge stage  204 , and a normal display stage  206  are performed in sequence. In the following description, the pixel  102  is taken as an example to explain the pixel control method  200 , and the present invention is not limited thereto. 
     In the first sub-pixel charge stage, the data signal  123  is a first gray level signal. The first switch  150  and the second switch  154  are respectively turned on by the scan signal  126  and the reference signal  128 , thereby applying the first gray level signal on a terminal of each of the storage capacitor  152 , the first liquid crystal capacitor  142 , the second storage capacitor  156 , and the second liquid crystal capacitor  146 . The reference signal  128  is an “on” voltage used to turn on the second switch  154 . In the second sub-pixel charge stage  204 , the reference signal  128  is then changed to be a “off” voltage used to turn off the second switch  154 , thereby maintaining the first gray level applied on the second storage capacitor  156  and the second liquid crystal capacitor  146 . In the second sub-pixel charge stage  204 , the data signal  123  is changed to be a second gray level signal and applied on the terminal of each of the first storage capacitor  152  and a first liquid crystal capacitor  142  via the first switch  150 . In the normal display stage  206 , the scan signal is changed to be an “off” voltage used to turn off the first switch  150 , thereby maintaining the second gray level signal applied on the terminal of each of the first storage capacitor  152  and a first liquid crystal capacitor  142 . Because the scan lines of the LCD  100  are sequentially turned off, when the pixel row  101  is turned on, each of the pixels  102  can be controlled with the pixel control method  200 . 
     By using the pixel control method  200 , the pixel  102   a  can respectively store the first gray level signal and the second gray level signal in the sub-pixel  102   a ′ and  102   a ″ at the same time. The first gray level signal can be used to drive a first liquid crystal molecules group corresponding the second liquid crystal capacitor  146  to enable the first liquid crystal molecules group to show a first gray level. Similarly, the second gray level signal can be used to drive a second liquid crystal molecules group corresponding the first liquid crystal capacitor  142  to enable the second liquid crystal molecules group to show a second gray level. The continuous integration of the values of the first gray level and the second gray level stands for a gray level value of a predetermined color of the pixel  102 . Thus, low color shift function can be realized by using two sub-pixels  102   a ′ and  102   a ″ to show a high gray level data and a low gray level data at the same time to show a intermediate gray level of the predetermined color. 
     It is noted that in the pixel control method  200 , the first storage capacitor  152 , the first liquid crystal capacitor  142 , the third storage capacitor  162 , and the third liquid crystal capacitor  172  art pre-charged, so that the voltage of each of the first storage capacitor  152 , the first liquid crystal capacitor  142 , the third storage capacitor  162 , and the third liquid crystal capacitor  172  can be rapidly changed to a voltage corresponding to the second gray level signal. Therefore, lesser time can be arranged to the second sub-pixel stage  204  for circuit operation, and more time can be arranged to the first sub-pixel stage  202  for circuit operation to make sure each of the second storage capacitor  156 , the second liquid crystal capacitor  146 , the fourth storage capacitor  166 , and the fourth liquid crystal capacitor  176  can store a voltage corresponding to the first gray level signal, thereby optimizing the display of the LCD  100 . 
     Refer to  FIG. 5  and  FIG. 6  simultaneously.  FIG. 5  is a structure diagram showing a LCD  300  according to a second embodiment of the present invention.  FIG. 6  is a circuit diagram showing pixels of the LCD  300  according to the second embodiment of the present invention. The LCD  300  is similar to the LCD  100 , but the difference is in that each of the pixel rows  301  includes a signal generation circuit  304 , and the LCD  300  further includes control signal lines  306  and  308  electrically connected to the signal generation circuit  304  of each of the pixel rows  301 . A pixel row  301   a  includes a pixel  102   a  and a signal generation circuit  304   a , and a pixel row  301   b  includes a pixel  102   b  and a signal generation circuit  304   b , wherein the pixel row  301   b  is adjacent to the pixel row  301   a , and the elements included in the signal generation circuit  304   a  are the same as that included in the signal generation circuit  304   b . In the following description, the signal generation circuits  304   a  and  304   b  are taken as examples to explain the operation of the LCD  300 , and the present invention is not limited thereto. 
     The signal generation circuit includes a switch  310  and a signal conversion circuit  312  including switches  314  and  316 . A gate electrode and a source electrode of the switch  310  are electrically connected to the scan line  120 , and a drain electrode of the switch  310  is electrically connected to the signal conversion circuit  312 , so that the scan signal  126  can be outputted to the signal conversion circuit  312  in a one-way direction. In the signal conversion circuit  312 , a source electrode of the switch  314  is electrically connected to the switch  310 , and a drain electrode of the switch  314  is electrically connected to the reference signal line  124 , and a gate electrode of the switch  314  is electrically connected to the control signal line  306 . The switch  314  is used to determine if the scan signal  126  is outputted to the reference signal line  124  in accordance with the control signal  320  transmitted by the control signal line  306 . A source electrode of the switch  316  is electrically connected to a ground reference voltage source Vss, and a drain electrode of the switch  316  is electrically connected to the reference signal line  124 , d  and a gate electrode of the switch  316  is electrically connected to the control signal line  308 . The switch  316  is used to determine if a ground reference voltage is outputted to the reference signal line  124  in accordance with the control signal  330  transmitted by the control signal line  308 . When the switch  314  is turned on according to the control signal  320  transmitted by the control signal line  306  to output the scan signal  126  to the reference signal line  124 , the switch  316  is turned off according to the control signal  330  transmitted by the control signal line  308 , thereby signals on the reference signal line  124  do not be affected by the reference voltage source Vss. When the switch  316  is turned on according to the control signal  330  transmitted by the control signal line  308  to output the ground reference voltage to the reference signal line  124 , the switch  314  is turned off according to the control signal  320  transmitted by the control signal line  306 , thereby signals on the reference signal line  124  do not be affected by the signals coming from the switch  310 . Similarly, the signal generation circuit  304   b  includes a switch  340  and a signal conversion circuit  342 . The signal conversion circuit  342  includes switches  344  and  346 . A gate electrode and a source electrode of the switch  340  are electrically connected to the scan line  130 , and a drain electrode of the switch  340  is electrically connected to the signal conversion circuit  342 , so that the scan signal  136  can be outputted to the signal conversion circuit  342  in a one-way direction. In the signal conversion circuit  342 , a source electrode of the switch  344  is electrically connected to the switch  340 , and a drain electrode of the switch  344  is electrically connected to the reference signal line  134 , and a gate electrode of the switch  344  is electrically connected to the control signal line  308 . The switch  344  is used to determine if the scan signal  136  is outputted to the reference signal line  134  in accordance with the control signal  330 . A source electrode of the switch  346  is electrically connected to the ground reference voltage source Vss, and a drain electrode of the switch  346  is electrically connected to the reference signal line  134 , d  and a gate electrode of the switch  346  is electrically connected to the control signal line  306 . The switch  346  is used to determine if the ground reference voltage is outputted to the reference signal line  134  in accordance with the control signal  320 . When the switch  344  is turned on according to the control signal  330  transmitted by the control signal line  308  to output the scan signal  136  to the reference signal line  134 , the switch  346  is turned off according to the control signal  320  transmitted by the control signal line  306 , thereby signals on the reference signal line  134  do not be affected by the reference voltage source Vss. When the switch  346  is turned on according to the control signal  320  transmitted by the control signal line  306  to output the ground reference voltage to the reference signal line  134 , the switch  344  is turned off according to the control signal  330  transmitted by the control signal line  308 , thereby signals on the reference signal line  134  can not be affected by the signals coming from the switch  340 . 
     Referring to  FIG. 7 .  FIG. 7  is a time sequence diagram showing the sequences of the control signals and the scan signals of the LCD  300  according to the second embodiment of present invention. In the following description, the signal generation circuit  304   a  is taken as an example to explain how the signal generation circuit generates the reference signal. 
     In the first sub-pixel charge stage  202 , the switch  310  is turned on according to the scan signal  126 , and the switch  314  is turned on according to the first control signal  320 , and the switch  316  is turned off according to the second control signal  330 , so that the scan signal  126  is outputted to the reference signal line  124 . Because the type of the of the second switch  154  is the same as that of the first switch  150 , and the first switch  150  can be turned on according to the control signal  126 , therefore the second switch  154  can be turned on according to the scan signal  126  transmitted to the reference signal line  124 , and the first gray level signal transmitted from the data line  122  is respectively applied on a terminal of each of the first storage capacitor  152 , the first liquid crystal capacitor  142 , the second storage capacitor  156 , and the second liquid crystal capacitor  146 . In the second sub-pixel charge stage  204 , the switch  314  is turned off according to the first control signal  320 , and the switch  316  is turned on according to the second control signal  330  to enable the ground reference voltage to be outputted to the reference signal line  124  to turn off the second switch  154 , therefore the first gray level signals stored in the second storage capacitor  156  and the second liquid crystal capacitor  146  are maintained, and the second gray level signal from the data line  122  is applied on a terminal of each of the first storage capacitor  152  and the first liquid crystal capacitor  142 . In the normal display stage  206 , the scan signal  126  is maintained in a low level voltage, so that the first switch  150  and the second switch  154  are turned off, and the first gray level signal is maintained in the second storage capacitor  156  and the second liquid crystal capacitor  146 , and the second gray level signal is maintained in the first storage capacitor  152  and the first liquid crystal capacitor  142 . In addition, in the above description, the second control signal  330  and the first control signal  320  are in phase opposition. 
     In the following description, the signal generation circuit  304   b  is taken as an example to explain the operation of the LCD  300 . In the first sub-pixel charge stage  202 , the switch  340  is turned on according to the scan signal  136 , and the switch  346  is turned off according to the first control signal  320 , and the switch  344  is turned on according to the second control signal  330 , so that the scan signal  136  is outputted to the reference signal line  134 . Because the type of the of the fourth switch  164  is the same as that of the third switch  160 , and the third switch  160  can be turned on according to the control signal  136 , therefore the fourth switch  164  can be turned on according to the scan signal  136  transmitted to the reference signal line  134 , and the first gray level signal transmitted from the data line  122  is respectively applied on a terminal of each of the third storage capacitor  162 , the third liquid crystal capacitor  174 , the fourth storage capacitor  166 , and the fourth liquid crystal capacitor  176 . In the second sub-pixel charge stage  204 , the switch  346  is turned on according to the first control signal  320 , and the switch  344  is turned off according to the second control signal  330  to enable the ground reference voltage to be outputted to the reference signal line  134  to turn off the fourth switch  164 , therefore the first gray level signals stored in the fourth storage capacitor  166  and the fourth liquid crystal capacitor  176  are maintained, and the second gray level signal from the data line  122  is applied on a terminal of each of the third storage capacitor  162  and the third liquid crystal capacitor  174 . In the normal display stage  206 , the scan signal  136  is maintained in a low level voltage, so that the third switch  160  and the fourth switch  164  are turned off, and the first gray level signal is maintained in the fourth storage capacitor  166  and the second liquid crystal capacitor  176 , and the second gray level signal is maintained in the third storage capacitor  162  and the third liquid crystal capacitor  174 . 
     In the second embodiment, the phase difference between the scan signal  126  and the scan signal  136  is used to properly setup the first control signal  320  and the second control signal  330 , so that the phase difference between the first control signal  320  and the second control signal  330  is the same as that between scan signal  126  and the scan signal  136 , and each of the pixels of the LCD  300  can be controlled via the scan line, the data line, the first control signal line, and the second control line only. It is not necessary to increase the number of the pins of a driver IC to provide signals to each of the reference signal lines, thereby the design cost of the driver IC can be decreased. 
     As is understood by a person skilled in the art, the foregoing embodiments of the present invention are strengths of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Technology Classification (CPC): 6