Patent Abstract:
An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of application Ser. No. 13/775,570, filed Feb. 25, 2013, which is a divisional of application Ser. No. 12/688,254, filed Jan. 15, 2010, which is a continuation of prior application Ser. No. 11/839,716, filed Aug. 16, 2007, each of the disclosures of which are incorporated by reference herein in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to semiconductor fuses, and particularly to electrically programmable semiconductor fuses. 
       BACKGROUND 
       [0003]    Electrically programmable fuses (efuses) used in re-routing circuits are programmed using a high electron current that induces a large gap in the conducting silicide layer. The programming uses a large power density in a short period of time. The result is a permanent resistance shift in the efuse that is not easily controlled and cannot be reversed. 
       BRIEF SUMMARY 
       [0004]    The shortcomings of the prior art are overcome and additional advantages are provided through the provision of an electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. 
         [0005]    An exemplary method for fabricating an electrically programmable fuse includes developing a first photoresist of a fuse mask on a hardmask of a substrate, etching through the hardmask, etching to form an undercut portion below the hardmask, developing a second photoresist of the fuse mask on the hardmask, etching to form a trench in the substrate, depositing a liner in the trench, seeding the trench, and electroplating the trench. 
         [0006]    An exemplary method for programming and reprogramming an electrically reprogrammable fuse includes programming the electrically reprogrammable fuse by inducing an electron current from a first programming wire through an interconnect to a second programming wire operative to effect electromigration in the interconnect, such that a void is formed between the interconnect and a sensing wire, and reprogramming the electrically reprogrammable fuse by inducing an electron current from the second programming wire through the interconnect to the first programming wire operative to effect electromigration in the interconnect, such that the interconnect contacts the sensing wire. 
         [0007]    An alternate exemplary method for fabricating an electrically programmable fuse includes developing a first photoresist of a fuse mask on a hardmask of a substrate, wherein a sacrificial layer is disposed between the hardmask and the substrate, etching through the hardmask and the sacrificial layer, etching the sacrificial layer to form an undercut portion below the hardmask, developing a second photoresist of the fuse mask on the hardmask, etching to form a trench in the substrate, depositing a liner in the trench, seeding the trench, electroplating the trench, polishing the electroplate overburden, and depositing a cap material. 
         [0008]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0009]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0010]      FIG. 1   a  illustrates a perspective view of one example of an efuse. 
           [0011]      FIG. 1   b  illustrates a side view of the efuse of  FIG. 1   a.    
           [0012]      FIG. 1   c  illustrates a partially cut-away front view efuse of  FIG. 1   b , taken along the line B-B. 
           [0013]      FIG. 2   a  illustrates an example of programming an efuse. 
           [0014]      FIG. 2   b  illustrates an example of the sensing state of an efuse. 
           [0015]      FIG. 2   c  illustrates an example of reversing the programming of an efuse. 
           [0016]      FIGS. 3   a - 3   h  illustrate one example of a method for fabricating an efuse. 
           [0017]      FIG. 4  illustrates one example of an alternate method for fabricating an efuse. 
       
    
    
       [0018]    The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. 
       DETAILED DESCRIPTION 
       [0019]    A system involving electrically reprogrammable fuses are provided. Several exemplary embodiments are described. 
         [0020]    In this regard, an efuse may be used to re-route circuits in semiconductors. For example, typical semiconductors include logic etched permanently on a chip. However, efuses may dynamically reprogram semiconductor chips while they are in use. 
         [0021]    Existing efuses may include poly-silicon stripes with a thin layer of silicide covering the top of the stripes. Programming these efuses requires passing a pulse of high electron current through the efuse. The pulse of the electron current induces a large gap in the conducting silicide layer caused by the electromigration of atoms in the metal. The resistance of the poly-silicon stripe shifts from about 100 ohms to 1 kohm or greater in the programmed efuse. The amount of resistance shift using this type of efuse cannot be easily controlled because the programming process uses a large amount of power density in a short period of time (approximately 1 msec, for example). The programming is also not reversible. 
         [0022]    Thus, it is desirable for the resistance shift induced by programming an efuse to be set more accurately. Additionally it is desirable to allow the reversible programming of efuses. The embodiments described below allow for the reversible programming of efuses that may be set to a resistance value more accurately than previous embodiments. 
         [0023]    FIG. la illustrates a perspective view of an exemplary embodiment of an efuse  100 . The efuse  100  includes an interconnect  102  and studs  108  and  110  (e.g. tungsten carbide) disposed between two poly-silicon programming wires  104  and  106  respectively. In the illustrated embodiment, the interconnect  102  is copper. However, the interconnect  102  may alternatively include any of a variety of metals including a combination of metals. A sensing wire  112  contacts the interconnect  102 . Extension  114  of the interconnect  102  may be included as a reservoir for the efuse  100 . 
         [0024]      FIG. 1   b  illustrates a side view of the exemplary embodiment of an efuse  100 . The interconnect  102  is disposed in a dielectric substrate  120 . In this embodiment, a cavity  116  has been formed in the substrate around the upper portion of the interconnect  102 . 
         [0025]      FIG. 1   c  illustrates a partially cut-away front view of the efuse  100 , taken along the lines B-B in FIG. lb. Programming wire  104  contacts stud  108 . The interconnect  102  contacts the sensing wire  112 . Additionally, the front portion  117  of the cavity  116  in the substrate  120 , and the two sidewall cavities  118  between the interconnect  102  and the substrate  120  are illustrated. 
         [0026]    Prior to programming the efuse  100 , signals may pass from the sensing wire  112  through the interconnect  102  to a variety of circuit components. Programming physically alters the interconnect  102  increasing the resistance of the interconnect  102  such that signals cannot effectively pass through the efuse. 
         [0027]    The operation of the efuse is illustrated in  FIGS. 2   a - 2   c .  FIG. 2   a  illustrates the programming of the efuse. In programming, the electron current  218  flows through the interconnect  102  from the first programming wire  104  to the second programming wire  106 . The studs  108  and  110  disposed between the interconnect  102  and the programming wires  104  and  106  are conductive, and act as blocking boundaries against atom diffusion during electromigration. The electronically conductive blocking boundaries facilitate the electrical communication between the interconnect  102  and the programming wires  104  and  106  in the dielectric material  120 , while preventing atoms from diffusing between the interconnect  102  and the programming wires  104  and  106 . The flow of electron current  218  causes an electromigration of the metal in the interconnect  102 . The flow of electrons displaces atoms in the surface of the interconnect  102  resulting in a surface void  217  forming between the interconnect  102  and the sensing wire  112 . In this embodiment, sidewall cavities  116  accelerate the electromigration in the interconnect  102 . 
         [0028]    A free surface is often the fastest diffusion path during electromigration. Fabricating sidewall cavities on the top portion of an interconnect effectively creates channels with free metal surface, thereby inducing accelerated electromigration process during fuse programming. Also, the accelerated electromigration is limited to the top portion of the interconnect, resulting the fast formation of a thin void at the top interface between the interconnect  102  and the sensing wire  112  after programming. Therefore, the programming time to generate such small and thin void is minimized. 
         [0029]      FIG. 2   b  shows the efuse in a sensing state. If a signal cannot pass from the sensing wire  112  through the interconnect  102  to the second programming wire  106 , the efuse is effectively an open circuit. 
         [0030]      FIG. 2   c  illustrates the reversing of the programming of the efuse. Reversing the bias of the programming electron current results in reversing the programming of the efuse. Thus, electron current  218  flows from the second programming wire  106  through the interconnect  102  to the first programming wire  104 . This electron current flow results in the electromigration of metal atoms that fill the surface void  217 . The surface void  217  is replaced by metal atoms such that a connection between the sensing wire  112  and the interconnect  102  results. Reversing the programming of the efuse effectively lowers the resistance of the interconnect  102 , allowing the efuse to pass signals through the interconnect  102  to the sensing wire  112 . 
         [0031]    This embodiment includes a reservoir  114 . Reservoir  114  acts as a depository for the atoms displaced during electromigration, and helps to prevent the disfigurement or extrusion of the efuse following electromigration. 
         [0032]      FIGS. 3   a - 3   h  illustrate a side cutaway view of the steps in an exemplary method of fabricating an efuse. Referring to  FIG. 3   a , substrate  302  is a dielectric material such as for example, but not limited to, SiO 2 , Si 3 N 4 , SiCOH, silsesquioxanes, C doped oxides (i.e., organosilicates that include atoms of Si, C, O and/or H, thermosetting polyarylene ethers, SiLK(a polyarylene ether available from Dow Chemical Corporation), JSR (a spin-on silicon-carbon contained polymer material available from JSR Corporation), etc., or layers thereof. A hardmask  304  formed on dielectric material  302  provides mechanical protection during chemical mechanical polishing (CMP) of the semiconductor chip, and may be one of many suitable materials such as silicon nitride or silicon oxide. To fabricate the efuse, a photoresist  306  of the fuse mask is developed on the hardmask  304 . The exposed portion  308  of the photoresist  306  will define the area of the efuse. 
         [0033]    The next step in fabricating the efuse is shown in  FIG. 3   b . The hardmask  304  is removed in the area defined by the photoresist  306  using an etching process such as reactive ion etching (RIE). 
         [0034]      FIG. 3   c  illustrates the next step in the fabricating method where an undercut  310  is formed under the hardmask  304 . The undercut  310  is formed using any suitable etching process. In this exemplary method, the undercut  310  is formed in the substrate  302  using a wet process isotropic etching. The undercut  310  is etched approximately, on the order of, 10 nm under the lip of the area defined by the hardmask  304  and approximately, in the order of, 10 nm in depth below the hardmask  304 . 
         [0035]    After the undercut  310  is etched in the substrate  302 , a second photoresist  312  is developed on the hardmask  304  as shown in  FIG. 3   d . The second photoresist may be similar to the first photoresist or may be different. A trench  314  is etched in the substrate  302  using an etching process such as RIE as depicted in  FIG. 3   e.    
         [0036]      FIG. 3   f  shows a liner  316  that is deposited using chemical vapor deposition or physical vapor deposition, for example. Once the liner  316  is deposited, the trench  314  is seeded to prepare the trench  314  for electroplating. In this exemplary embodiment, copper is used for the seeding and electroplating, however any suitable metal may be used such as, for example, silver or aluminum.  FIG. 3   g  illustrates the trench  314  following electroplating with copper  318 . The trench  314  is filled with copper  318 . Because the undercuts  310  are not electroplated with copper  318 , a cavity  322  is thus formed around the upper portion of the filled trench  314 . 
         [0037]    Finally, the excess copper  318  that is not in the trench  314  (i.e., the overburden) is removed using a method such as CMP, for example, and a cap layer  320  is layered over the substrate  302 .  FIG. 3   h  shows the completed efuse including the interconnect  324  and cavities  322 , with a cap layer  320 . 
         [0038]      FIG. 4  illustrates an alternate method for fabricating an efuse. In this method, a sacrificial layer  405  is disposed between the substrate  402  and the hardmask  404 . The sacrificial layer  405  may be any suitable dielectric material such as silicon oxide, for example. The sacrificial layer  405  partially defines the area of the undercut  410  during the isotropic etching step. By using a sacrificial layer  405 , the isotropic etching of the undercut  410  may be limited to an area partially defined by the sacrificial layer  405 , and thus, the etching may be more precise. Other than the use of a sacrificial layer  405 , fabrication process for the efuse in this alternate method is similar to the fabrication method described above and shown in  FIGS. 3   a - 3   h.    
         [0039]    While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Technology Classification (CPC): 7