Patent Abstract:
A semiconductor integrated circuit includes: an internal circuit formed on a semiconductor chip, power being supplied thereto via a first power supply wire and a second power supply wire; input and output pads that exchange an input signal or an output signal with the internal circuit; input and output cells including first electrostatic protection elements that protect the internal circuit from electrostatic discharge between the input and output pads and the first or second power supply wire; and second power supply protection elements provided adjacent to the input and output cells and including diode strings connected between the first power supply wire and the second power supply wire.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-201257, filed on Sep. 1, 2009; the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor integrated circuit, and, more particularly is suitably applied to a method of improving electrostatic discharge immunity of the semiconductor integrated circuit. 
         [0004]    2. Description of the Related Art 
         [0005]    In a semiconductor integrated circuit, to protect an internal circuit formed on a semiconductor chip, in some case, an electrostatic protection circuit is provided on the same semiconductor chip. 
         [0006]    For example, Patent Document 1 “Mong-Dou Ker and Kun-Hsien Lin ‘ESD Protection Design for I/O Cells With Embedded SCR Structure as Power-Rail ESD Clamp Device in Nanoscale CMOS Technology’ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005” discloses a method of providing silicon controlled rectifiers (SCRs) connected between power supply wires in input cells and output cells and, when electrostatic discharge is detected between the power supply wires, turning on the SCRs to thereby protect an internal circuit from electrostatic discharge damage. 
         [0007]    Patent Document 2 “James W. Miller, Melanie Etherton, Michael G. Khazhinsky, Michael Stockinger, and James C. Weldon ‘Comprehensive ESD Protection for Flip-Chip Products in a Dual Gate Oxide 65 nm CMOS Technology’ EOS/ESD SYMPOSIUM 06-186 4A.4-1 TO 4A.4-10” discloses a method of providing field effect transistors connected between power supply wires in I/O cells and, when electrostatic discharge is detected between the power supply wires, turning on the field effect transistors to thereby protect an internal circuit from electrostatic discharge damage. 
         [0008]    However, in the methods disclosed in Patent Documents 1 and 2, the SCRs or the field effect transistors are used to protect the internal circuit from electrostatic discharge damage. Therefore, a trigger circuit is necessary and, moreover, a device area is increased to improve a discharge ability. 
         [0009]    In the method disclosed in Patent Document 1, because the SCRs are used, responsiveness to a high-speed surge is poor. In the method disclosed in Patent Document 2, because the field effect transistors are used, uniform operation performance is poor. 
       BRIEF SUMMARY OF THE INVENTION 
       [0010]    A semiconductor integrated circuit according to an embodiment of the present invention comprises: a first power supply pad arranged in a peripheral section of a semiconductor chip; a second power supply pad arranged in the peripheral section of the semiconductor chip; a first power supply wire connected to the first power supply pad; a second power supply wire connected to the second power supply pad; an internal circuit formed on the semiconductor chip, power being supplied thereto via the first power supply wire and the second power supply wire; input and output pads that exchange an input signal or an output signal with the internal circuit; input and output cells including first electrostatic protection elements that protect the internal circuit from electrostatic discharge between the input and output pads and the first or second power supply wire; and second power supply protection elements provided adjacent to the input and output cells and including diode strings connected between the first power supply wire and the second power supply wire. 
         [0011]    A semiconductor integrated circuit according to an embodiment of the present invention comprises: a first power supply pad arranged in a peripheral section of a semiconductor chip; a second power supply pad arranged in the peripheral section of the semiconductor chip; a first power supply wire connected to the first power supply pad; a second power supply wire connected to the second power supply pad; an internal circuit formed on the semiconductor chip, power being supplied thereto via the first power supply wire and the second power supply wire; input and output pads that exchange an input signal or an output signal with the internal circuit; input and output cells including first electrostatic protection elements that protect the internal circuit from electrostatic discharge between the input and output pads and the first or second power supply wire; and second power supply protection elements provided in the input and output cells to be arranged between the first power supply wire and the second power supply wire and including diode strings connected between the first power supply wire and the second power supply wire. 
         [0012]    A semiconductor integrated circuit according to an embodiment of the present invention comprises: a first power supply pad arranged in a peripheral section of a semiconductor chip; a second power supply pad arranged in the peripheral section of the semiconductor chip; a first power supply wire connected to the first power supply pad; a second power supply wire connected to the second power supply pad; an internal circuit formed on the semiconductor chip, power being supplied thereto via the first power supply wire and the second power supply wire; first and second input and output pads that exchange an input signal or an output signal with the internal circuit; a first diode string connected between the first power supply wire and the second power supply wire such that a forward direction of the connection is a direction from a high potential side to a low potential side, the first diode string forming a discharge path for a surge current input to the first input and output pad; and a second diode string connected between the first power supply wire and the second power supply wire such that a forward direction of the connection is a direction from a high potential side to a low potential side, the second diode string forming a discharge path for a surge current input to the second input and output pad. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a plan view of the schematic configuration of a semiconductor integrated circuit according to a first embodiment of the present invention; 
           [0014]      FIG. 2  is an enlarged plan view of an A section shown in  FIG. 1 ; 
           [0015]      FIG. 3  is a diagram of an equivalent circuit of the A section shown in  FIG. 2 ; 
           [0016]      FIG. 4  is a diagram of an equivalent circuit of each of power supply protection elements including diode strings S 2  to S 6  provided among input and output cells shown in  FIG. 3 ; 
           [0017]      FIG. 5  is a plan view of a layout configuration of the power supply protection elements including the diode strings shown in  FIG. 4 ; 
           [0018]      FIG. 6  is a plan view of the schematic configuration of a peripheral section of a semiconductor integrated circuit according to a second embodiment of the present invention; 
           [0019]      FIG. 7  is a plan view of the schematic configuration of a peripheral section of a semiconductor integrated circuit according to a third embodiment of the present invention; and 
           [0020]      FIG. 8  is a plan view of a layout configuration of power supply protection elements shown in  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Exemplary embodiments of the present invention are explained in detail below with reference to the accompanying drawings. The present invention is not limited by the embodiments. 
         [0022]      FIG. 1  is a plan view of the schematic configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 
         [0023]    In  FIG. 1 , an internal circuit  2  is formed on a semiconductor chip  1 . As the internal circuit  2 , for example, a signal processing circuit such as a logic circuit, a processor, a memory, an image sensor, or an ASIC can be formed. 
         [0024]    Pad electrodes  4  are arranged in a peripheral section of the semiconductor chip  1 . A peripheral circuit  3  is arranged between the pad electrodes  4  and the internal circuit  2 . As the pad electrodes  4 , power supply pads  4   a  and  4   b  and input and output pads  4   c  to  4   f  can be provided. The power supply pad  4   a  can deliver a low-potential power supply VSS. The power supply pad  4   b  can deliver a high-potential power supply VDD. The input and output pads  4   c  to  4   f  can exchange signals input or output between the input and output pads  4   c  to  4   f  and the internal circuit  2 . 
         [0025]      FIG. 2  is an enlarged plan view of an A section shown in  FIG. 1 . 
         [0026]    In  FIG. 2 , on the peripheral circuit  3 , power supply cells  3   a  and  3   b  and input and output cells  3   c  to  3   f  are respectively arranged to correspond to the power supply pads  4   a  and  4   b  and the input and output pads  4   c  to  4   f . In the power supply cells  3   a  and  3   b , power supply protection elements that protect the internal circuit  2  from electrostatic discharge between power supply wires  7  and  8  can be provided. In the input and output cells  3   c  to  3   f , electrostatic protection elements that protect the internal circuit  2  from electrostatic discharge between the input and output pads  4   c  to  4   f  and the power supply wires  7  and  8  can be provided. In the input and output cells  3   c  to  3   f , input buffers that input signals, which are applied to the input and output pads  4   c  to  4   f , to the internal circuit  2 , output buffers that output a signal, which is output from the internal circuit  2 , to the outside via the input and output pads  4   c  to  4   f , level shifters that shift signals, which are input to and output from the internal circuit  2 , to a predetermined level, or the like can also be provided. For example, in the output cell  3   c , an inverter can be used as the input buffer. In the output cell  3   c , a first field effect transistor and a second field effect transistor can be used as the output buffer. The first field effect transistor is connected between the power supply wire  7  and the input and output pad  4   c . A gate potential of the first field effect transistor is controlled by a signal output from the internal circuit  2 . The second field effect transistor is connected between the power supply wire  8  and the input and output pad  4   c . A gate potential of the second field effect transistor is controlled by a signal output from the internal circuit  2 . 
         [0027]    A spacer cell  5  is arranged in a space between the input and output cells  3   e  and  3   f . Power supply protection elements  6   a  to  6   c  are respectively arranged in spaces among the input and output cells  3   c  to  3   f . Power supply protection element  6   d  is arranged in a space outside output cell  3   f . A power supply protection element  6   e  is arranged on the spacer cell  5 . The power supply wires  7  and  8  are drawn around in the peripheral section of the semiconductor chip  1  to cross the power supply cells  3   a  and  3   b , the input and output cells  3   c  to  3   f , and the power supply protection elements  6   a  to  6   e.    
         [0028]    The power supply pad  4   a  is connected to the power supply wire  7  and the power supply pad  4   b  is connected to the power supply wire  8 . The power supply cells  3   a  and  3   b  and the power supply protection elements  6   a  to  6   e  are connected between the power supply wires  7  and  8 . The input and output pads  4   c  to  4   f  are connected to the internal circuit  2  respectively via the input and output cells  3   c  to  3   f . Power supply protection elements  6   a  to  6   e  can include diode strings connected between the power supply wires  7  and  8 . An array pitch H 2  of the input and output pads  4   c  to  4   e  is desirably set larger than cell width H 1  of the input and output cells  3   c  to  3   e  to make it possible to insert the power supply protection elements  6   a  to  6   b  among the output cells  3   c  to  3   f.    
         [0029]      FIG. 3  is a diagram of an equivalent circuit of the A section shown in  FIG. 2 .  FIG. 4  is a diagram of an equivalent circuit of a diode string. 
         [0030]    In  FIG. 3 , a diode D 11  is provided in the power supply cell  3   a  shown in  FIG. 2 . A diode string S 1  is provided as a power supply protection element in the power supply cell  3   b  shown in  FIG. 2 . Diodes D 12  and D 13  are provided in the input and output cell  3   c . Diodes D 14  and D 15  are provided in the input and output cell  3   d . Diodes D 16  and D 17  are provided in the input and output cell  3   e . Diodes D 18  and D 19  are provided in the input and output cell  3   f . Diode strings S 2  to S 6  are respectively used as the power supply protection elements  6   a  to  6   e . As shown in  FIG. 4 , each of the diode strings S 2  to S 6  can be configured by connecting n (n is an integer equal to or larger than 2) diodes D 1  to Dn in series. Parasitic resistor R 1  and R 2  are present in the power supply wires  7  and  8 . 
         [0031]    The power supply protection element of the power supply cell  3   b  does not always have to be the diode string S 1 . A device other than the diode string S 1  such as a MOS transistor, a bipolar junction transistor (BJT), or an SCR can also be used. 
         [0032]    The diode D 11  is connected between the power supply wires  7  and  8  such that a forward direction of the connection is a direction from a low potential side to a high potential side. The diodes D 12 , D 14 , D 16 , and D 18  are connected between the respective input and output pads  4   c  to  4   f  and the power supply wire  8  such that a forward direction of the connection is a direction from a low potential side to a high potential side. The diodes D 13 , D 15 , D 17 , and D 19  are connected between the respective input and output pads  4   c  to  4   f  and the power supply wire  7  such that a forward direction of the connection is a direction from a low potential side to a high potential side. The diode strings S 1  to S 6  are connected between the power supply wires  7  and  8  such that a forward direction of the connection is a direction from a high potential side to a low potential side. The number n of the diodes D 1  to Dn of each of the diode strings S 1  to S 6  is desirably set to be within a specification of standby leak between the power supply wires  7  and  8 . 
         [0033]    When a surge voltage is applied to the power supply pads  4   a  and  4   b , the diode D 11  of the power supply cell  3   a  or the diode string S 1  of the power supply cell  3   b  and the diode strings S 2  to S 6  provided among the input and output cells  3   c  to  3   f  function via the parasitic resistors R 1  and R 2  according to the polarity of the surge and perform electrostatic discharge (ESD) protection. In this case, a high protection ability can be expected compared with a protection ability obtained when the diode string S 1  alone of the power supply cell  3   b  absorbs a surge between power supplies. 
         [0034]    Protection of the internal circuit  2  is performed in several ways as explained below when a surge voltage is applied to the input and output pads  4   c  to  4   f  and flows to the power supply pads  4   a  and  4   b . The input and output pad  4   f  present in a position most distant from the power supply pads  4   a  and  4   b  among the input and output pads  4   c  to  4   f  is explained as an example. 
         [0035]    When a surge having negative polarity is input to the input and output pad  4   f  with the power supply pad  4   a  set as a reference pad, the diode D 19  performs clamp operation and protects the internal circuit  2 . Because a discharge ability of the diode D 19  is high, the influence of the parasitic resistors R 1  and R 2  can be generally neglected. 
         [0036]    When a surge having positive polarity is input to the input and output pad  4   f  with the power supply pad  4   b  set as a reference pad, the diode D 18  performs clamp operation and protects the internal circuit  2 . Because a discharge ability of the diode D 18  is high, the influence of the parasitic resistors R 1  and R 2  can be generally neglected. 
         [0037]    When a surge having positive polarity is input to the input and output pad  4   f  with the power supply pad  4   a  set as a reference pad, the diode strings S 1  to S 6  connected to the power supply wires  7  and  8  via the diode D 18  perform clamp operation and protect the internal circuit  2 . In this case, compared with protection performed by only the diode string S 1  mounted on the power supply cell  3   b , when the diode strings S 2  to S 6  are mounted among the input and output cells  3   c  to  3   f , the diode strings S 1  to S 6  can easily cooperatively operate during discharge, the influence of the parasitic resistors R 1  and R 2  can be reduced. Even the input and output pad  4   f  present most distant from the power supply pad  4   a  can perform sufficient ESD protection. 
         [0038]    When a surge having negative polarity is input to the input and output pad  4   f  with the power supply pad  4   b  set as a reference pad, the diode strings S 1  to S 6  connected to the power supply wires  7  and  8  via the diode D 19  perform clamp operation and protect the internal circuit  2 . In this case, compared with protection performed by only the diode string S 1  mounted on the power supply cell  3   b , when the diode strings S 2  to S 6  are mounted among the input and output cells  3   c  to  3   f , the diode strings S 1  to S 6  can easily cooperatively operate during discharge, the influence of the parasitic resistors R 1  and R 2  can be reduced. Even the input and output pad  4   f  present most distant from the power supply pad  4   b  can perform sufficient ESD protection. 
         [0039]    The diode strings S 2  to S 6  are respectively used as the power supply protection elements  6   a  to  6   e . This makes it unnecessary to provide a trigger circuit and makes it possible to improve a discharge ability and suppress an increase in a device area. Compared with responsiveness to a high-speed surge obtained when SCRs are used as the power supply protection elements  6   a  to  6   e , it is possible to improve the responsiveness, improve uniform operation performance, and cause the power supply protection elements  6   a  to  6   e  to stably operate in parallel. 
         [0040]    The power supply protection elements  6   a  to  6   c  are respectively arranged in the spaces among the input and output cells  3   c  to  3   f . This makes it possible to reduce, even when a large surge current flows to the power supply wires  7  and  8 , the length of a discharge path for the surge current and suppress a voltage rise due to the parasitic resistors R 1  and R 2  of the power supply wires  7  and  8 . Therefore, it is possible to stably protect the internal circuit  2  from electrostatic discharge damage. 
         [0041]      FIG. 5  is a plan view of a layout configuration of the power supply protection elements shown in  FIG. 2 . 
         [0042]    In  FIG. 5 , diodes  11  to  13  connected in series are provided in the diode strings S 2  to S 6  shown in  FIG. 3 . N wells W 1  to W 3  surrounded by a P-type high-concentration diffusion layer F 10  are respectively provided in the diodes  11  to  13 . The P-type high-concentration diffusion layer F 10  can configure a guard ring. 
         [0043]    In the N well W 1 , an N-type high-concentration diffusion layer F 1 , a P-type high-concentration diffusion layer F 2 , and an N-type high-concentration diffusion layer F 3  are arranged side by side in a wiring direction of the power supply wires  7  and  8 . In the N well W 2 , a P-type high-concentration diffusion layer F 4 , an N-type high-concentration diffusion layer F 5 , and a P-type high-concentration diffusion layer F 6  are arranged side by side in the wiring direction of the power supply wires  7  and  8 . In the N well W 3 , an N-type high-concentration diffusion layer F 7 , a P-type high-concentration diffusion layer F 8 , and an N-type high-concentration diffusion layer F 9  are arranged side by side in the wiring direction of the power supply wires  7  and  8 . The N-type high-concentration diffusion layer F 1 , the P-type high-concentration diffusion layer F 4 , and the N-type high-concentration diffusion layer F 7  are desirably arranged on one straight line. The P-type high-concentration diffusion layer F 2 , the N-type high-concentration diffusion layer F 5 , and the P-type high-concentration diffusion layer F 8  are desirably arranged on one straight line. The N-type high-concentration diffusion layer F 3 , the P-type high-concentration diffusion layer F 6 , and the N-type high-concentration diffusion layer F 9  are desirably arranged on one straight line. 
         [0044]    Wiring layers M 1  to M 6  are formed on the N wells W 1  to W 3 . The wiring layer M 1  is connected to the N-type high-concentration diffusion layer F 1  via contacts C 1  and connected to the P-type high-concentration diffusion layer F 4  via contacts C 4 . The wiring layer M 2  is connected to the P-type high-concentration diffusion layer F 2  via contacts C 2 . The wiring layer M 3  is connected to the N-type high-concentration diffusion layer F 3  via contacts C 3  and connected to the P-type high-concentration diffusion layer F 6  via contacts C 6 . The wiring layer M 4  is connected to the N-type high-concentration diffusion layer F 7  via contacts C 7  and connected to the P-type high-concentration diffusion layer F 10  via contacts C 10 . The wring layer M 5  is connected to the N-type high-concentration diffusion layer F 5  via contacts C 5  and connected to the P-type high-concentration diffusion layer F 8  via contacts C 8 . The wiring layer M 6  is connected to the N-type high-concentration diffusion layer F 9  via contacts C 9  and connected to the P-type high-concentration diffusion layer F 10  via contacts C 0 . 
         [0045]    Wiring layers M 7  to M 9  are formed on the wiring layers M 1  to M 6 . The wiring layer M 7  is connected to the wiring layer M 4  via vias  32  and connected to the power supply wire  7 . The wiring layer M 8  is connected to the wiring layer M 2  via vias B 1  and connected to the power supply wire  8 . The wiring layer M 9  is connected to the wiring layer M 6  via vias B 3  and connected to the power supply wire  7 . 
         [0046]    In the embodiment shown in  FIG. 5 , a configuration in which the diodes  11  to  13  are connected in series in three stages is explained as an example. However, to increase the number of stages of diodes connected in series, the diodes  11  to  13  shown in  FIG. 5  only have to be repeatedly arranged in a direction orthogonal to the power supply wires  7  and  8 . Therefore, it is possible to increase the number of stages of the diodes connected in series without increasing the width of the power supply protection elements  6   a  to  6   d  shown in  FIG. 2 . Even when the spaces among the input and output cells  3   c  to  3   f  are narrow, it is possible to respectively arrange the power supply protection elements  6   a  to  6   d  in the spaces among the input and output cells  3   c  to  3   f.    
         [0047]    The wiring layers M 7  to M 9  can be formed on a wiring layer different from a wiring layer on which the power supply wires  7  and  8  shown in  FIG. 2  are formed. However, the wiring layers M 7  to M 9  can also be formed on a wiring layer same as the wiring layer on which the power supply wires  7  and  8  shown in  FIG. 2  are formed. 
         [0048]      FIG. 6  is a plan view of the schematic configuration of a peripheral section of a semiconductor integrated circuit according to a second embodiment of the present invention. 
         [0049]    In  FIG. 6 , pad electrodes are arranged in zigzag in a peripheral section of a semiconductor chip. As the pad electrodes, power supply pads  14   a  and  14   b  and input and output pads  14   c  to  14   f  are provided. Power supply cells  13   a  and  13   b  and input and output cells  13   c  to  13   f  are respectively arranged to correspond to the power supply pads  14   a  and  14   b  and the input and output pads  14   c  to  14   f . Power supply protection elements  16   a  to  16   c  are respectively arranged in spaces among the input and output cells  13   c  to  13   f . Power supply wires  17  and  18  are drawn around in the peripheral section of the semiconductor chip to cross the power supply cells  13   a  and  13   b , the input and output cells  13   c  to  13   f , and the power supply protection elements  16   a  to  16   d.    
         [0050]    The power supply pad  14   a  is connected to the power supply wire  17 . The power supply pad  14   b  is connected to the power supply wire  18 . The power supply cells  13   a  and  13   b  and the power supply protection elements  16   a  to  16   d  are connected between the power supply wires  17  and  18 . The input and output pads  14   c  to  14   f  are connected to an internal circuit respectively via the input and output cells  13   c  to  13   f . The power supply protection elements  16   a  to  16   d  can include diode strings connected between the power supply wires  17  and  18 . An array pitch H 12  of the input and output pads  14   c  to  14   f  is desirably set larger than cell width H 11  of the input and output cells  13   c  to  13   f  to make it possible to insert the power supply protection elements  16   a  to  16   c  among the input and output cells  13   c  to  13   f . The diode D 11  shown in  FIG. 3  can be provided in the power supply cell  13   a . In the power supply cell  13   b , the diode string S 1  shown in  FIG. 3  can also be provided or a device other than the diode string S 1  such as a MOS transistor, a BJT, or a SCR can also be provided. 
         [0051]    The power supply protection elements  16   a  to  16   c  are respectively arranged in the spaces among the input and output cells  13   c  to  13   f . This makes it possible to stably protect the internal circuit from electrostatic discharge damage while suppressing an increase in a device area even when the pad electrodes are arranged in zigzag. 
         [0052]      FIG. 7  is a plan view of the schematic configuration of a peripheral section of a semiconductor integrated circuit according to a third embodiment of the present invention. 
         [0053]    In  FIG. 7 , pad electrodes are arranged in a peripheral section of a semiconductor chip. As the pad electrodes, power supply pads  24   a  and  24   b  and input and output pads  24   c  to  24   f  are provided. Power supply cells  23   a  and  23   b  and input and output cells  23   c  to  23   f  are respectively arranged to correspond to the power supply pads  24   a  and  24   b  and the input and output pads  24   c  to  24   f . A spacer cell  25  is arranged in a space between the input and output cells  23   e  and  23   f . Power supply protection elements  26   c  to  26   f  are respectively provided in the input and output cells  23   c  to  23   f . Power supply wires  27  and  28  are drawn around in the peripheral section of the semiconductor chip to cross the power supply cells  23   a  and  23   b  and the input and output cells  23   c  to  23   f . The power supply protection elements  26   c  to  26   f  can be respectively provided in the input and output cells  23   c  to  23   f  to be arranged between the power supply wires  27  and  28 . The power supply protection elements  26   c  to  26   f  can also be arranged to overlap the power supply wires  27  and  28 . 
         [0054]    The power supply pad  24   a  is connected to the power supply wire  27 . The power supply pad  24   b  is connected to the power supply wire  28 . The power supply cells  23   a  and  23   b  and the power supply protection elements  26   a  to  26   f  are connected between the power supply wires  27  and  28 . The input and output pads  24   c  to  24   f  are connected to an internal circuit respectively via the input and output cells  23   c  to  23   f . The power supply protection elements  26   c  to  26   f  can include diode strings connected between the power supply wires  27  and  28 . An array pitch H 21  of the input and output pads  24   c  to  24   e  is desirably set to correspond to cell width H 22  of the input and output cells  23   c  to  23   d . The diode D 11  shown in  FIG. 3  can be provided in the power supply cell  23   a . In the power supply cell  23   b , the diode string S 1  shown in  FIG. 3  can be also be provide or a device other than the diode string S 1  such as a MOS transistor, a BJT, or a SCR can also be provided. 
         [0055]    The power supply protection elements  26   c  to  26   f  are arranged between the power supply wires  27  and  28 . This makes it unnecessary to provide a space between the input and output cells  23   e  and  23   f  and makes it possible to stably protect the internal circuit from electrostatic discharge damage while suppressing an increase in a device area. 
         [0056]      FIG. 8  is a plan view of a layout configuration of the power supply protection elements shown in  FIG. 7 . 
         [0057]    In  FIG. 8 , the diode strings included in the power supply protection elements  26   c  to  26   f  shown in  FIG. 7  include diodes  21  to  23  connected in series. N wells W 11  to W 13  surrounded by a P-type high-concentration diffusion layer F 17  are respectively provided in the diodes  21  to  23 . The P-type high-concentration diffusion layer F 17  can configure a guard ring. 
         [0058]    In the N well W 11 , a P-type high-concentration diffusion layer F 11  and an N-type high-concentration diffusion layer F 12  are arranged side by side in a direction orthogonal to the power supply wires  27  and  28 . In the N well W 12 , a P-type high-concentration diffusion layer F 13  and an N-type high-concentration diffusion layer F 14  are arranged side by side in the direction orthogonal to the power supply wires  27  and  28 . In the N well W 13 , a P-type high-concentration diffusion layer F 15  and an N-type high-concentration diffusion layer F 16  are arranged side by side in the direction orthogonal to the power supply wires  27  and  28 . 
         [0059]    Wiring layers M 11  to M 14  are formed on the N wells W 11  to W 13 . The wiring layer M 11  is connected to the P-type high-concentration diffusion layer F 11  via contacts C 11 . The wiring layer M 12  is connected to the N-type high-concentration diffusion layer F 12  via contacts C 12  and connected to the P-type high-concentration diffusion layer F 13  via contacts C 13 . The wiring layer M 13  is connected to the N-type high-concentration diffusion layer F 14  via contacts C 14  and connected to the P-type high-concentration diffusion layer F 15  via contacts C 15 . The wiring layer M 14  is connected to the N-type high-concentration diffusion layer F 16  via contacts C 16  and connected to the P-type high-concentration diffusion layer F 17  via contacts C 17 . 
         [0060]    The power supply wires  27  and  28  are formed on the wiring layers N 11  to M 14 . The power supply wire  27  is connected to the wiring layer M 14  via vias B 12 . The power supply wire  28  is connected to the wiring layer N 11  via vias B 11 . 
         [0061]    In the embodiment shown in  FIG. 8 , a configuration in which the diodes  21  to  23  are connected in series in three stages is explained as an example. However, to increase the number of stages of diodes connected in series, the diodes  21  to  23  only have to be repeatedly arranged in a direction orthogonal to the power supply wires  27  and  28 . 
         [0062]    In the embodiment explained above, a method of arranging the input and output cells not to overlap the input and output pads is explained. However, the present invention can also be applied to a structure in which the input and output cells are arranged under the input and output pads. 
         [0063]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Technology Classification (CPC): 7