Patent Abstract:
A data driver for driving pixels in an active matrix organic LED (AMOLED) is provided. The data driver includes a plurality of converters configured to convert to analog current signals from digital voltage signals in order to drive the pixels to emit light. Each converter has a plurality of current mirror devices configured to generate mirrored current signals by inputting two control signals. Meanwhile, the mirrored current signals can maintain their preciseness even if deviation of the characteristics of the transistors implanted within the current mirror devices occurs during fabricating.

Full Description:
[0001]    This Application claims priority to Taiwan Patent Application No. 092103685 filed on Feb. 21, 2003.  
         FIELD OF INVENTION  
         [0002]    The present invention relates to a data driver for an active matrix organic light emitting display (AMOLED), which is configured to convert digital voltage signals into analog current signals to drive pixels in the display to emit light.  
         BACKGROUND OF THE INVENTION  
         [0003]    Pixels in an AMOLED are driven by analog current signals; however, the signals that control the pixels to emit light are digital voltage signals. Therefore, each AMOLED needs a data driver (or source driver) to convert digital control voltage signals into analog current signals.  
           [0004]    [0004]FIG. 1 illustrates a data driver  1  of the prior art. As it shows, the data driver  1  includes a first shift register  101 , a data register  103 , a voltage latch  105 , a converter  107 , a current latch  109 , a current source  111 , and a second shift register  113 . The converter  107  is configured to receive the digital voltage signals  110 , which will later drive pixels to emit light, from the voltage latch  105 , and to convert the digital voltage signals  110  into analog current signals  112  based on the reference currents provided by the current source  111 . The second shift register  113  is configured to switch on or off each cell in the current latch  109  in order to store the analog current signals  112  sent by the converter  107 . After a proper period of time, an enabling signal  108  enables the current latch  109  so that all the analog current signals  114 , identical to the analog current signals  112 , are able to reach all pixels of the AMOLED to present a transient frame.  
           [0005]    The framework of the converter  107  is basically a current mirror. FIG. 2 illustrates one kind of current mirror of the prior art. With reference to FIG. 2, a reference current I s , generated by the current source  111  shown in FIG. 1, mirrors I p1 , I p2 , I p3 , etc. through a transistor MP 1 . It is noted that the values of the mirrored currents, e.g. I p1 , I p2 , I p3 , etc., are associated with the characteristics, i.e. aspect ratio, threshold voltage, and mobility, of MP 2 , MP 3 , MP 4 , etc. Once any deviation from the theoretical characteristics of the transistors is induced during fabricating, the practical values of the mirrored current I p1 , I p2 , I p3  etc. will bring error as well. The error, even if it is tiny, might still influence the gray level that an analog current signal actually sets in due to the narrow band of each gray level and, therefore, pixels might emit unexpected illumination.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention discloses a data driver for an active matrix organic light emitting display (AMOLED), which converts digital voltage signals into analog current signals in order to drive all pixels in the display to emit light.  
           [0007]    The data driver includes a first shift register, a data register, a data latch, a second shift register, and N converters. The first shift register is configured to provide an N-bit first control signal. The data register is configured to store N M-bit digital voltage signals by switching on the cells in it in turn in response to the first control signal, and to send the N digital voltage signals to the data latch. The data latch is configured to receive the N digital voltage signals and respectively transmit them to the N converters in response to an enabling signal. The second shift register is configured to provide an (M+1)-bit second control signal to control the procedure of converting the digital voltage signals into analog current signals.  
           [0008]    Each converter of the data driver of the present invention is a digital-voltage-to-analog-current converter with M units regarded as current sources. Each current source (or each unit) includes two control signals to enable or disable the transistors within so as to control the generation timing of mirrored currents. The current source can overcome the drawbacks of the prior art and, therefore, the mirrored current does not deviate even if the characteristics of the transistors within have been changed during fabricating. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 illustrates a data driver of the prior art.  
         [0010]    [0010]FIG. 2 is the exemplary circuitry of a current mirror of the prior art.  
         [0011]    [0011]FIG. 3 illustrates the data driver of the present invention.  
         [0012]    [0012]FIG. 4 illustrates the converter of the present invention.  
         [0013]    [0013]FIG. 5 is the circuitry of a current mirror of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0014]    With reference to FIG. 3, the data driver  2  disclosed by the present invention includes a first shift register  201 , a data register  203 , a data latch  205 , a second shift register  207 , and N converters  209 . The first shift register  201  is configured to receive a data shift signal  202  and provide an N-bit first control signal  204 . The first control signal  204  is transmitted to the data register  203  to switch on the cells in the data register  203  so that N M-bit digital voltage signals  206  are stored in turn. The digital voltage signals  206  are the signals that need to be converted into analog current signals  218 , which are then respectively transmitted through data lines to drive pixels and make pixels emit light. After receiving and storing all of the digital voltage signals  206 , the data register  203  will send these signals  206  to the data latch  205 . The data latch  205  is switched on by an enabling signal  210  at a particular timing so that the digital voltage signals  208 , identical to the digital voltage signals  206 , are able to be transmitted to N converters  209  respectively. The second shift register  207  is configured to provide an (M+1)-bit second control signal  216  in response to a signal  214  to activate the procedure of converting digital voltage signals  212 , identical to the digital voltage signals  208 , to analog current signals  218  in N converters  209 . The converters  209  are digital-voltage-to-analog-current converters with the same function that the current latch  109  shown in FIG. 1 has. Each of the converters  209  is capable of seizing the converted analog current signals  218  and does not release them to pixels until all of the digital voltage signals  212  have been converted.  
         [0015]    To specify one preferred embodiment of the converters  209  of the present invention, each digital voltage signal is assumed to be a 6-bit signal. As shown in FIG. 4, each of the N converters  209 , responsive to a 6-bit input, is required to have 6 first devices  301  and 6 second devices  303 . Each first device  301 , responsive to one of the preceding 6 bits SW 0 ˜SW 5  of the second control signal  216 , is configured to generate one of the 6 first mirrored currents I m0 ˜I m5  respectively, and to transmit it to the corresponding second device  303 . Each second device  303 , responsive to both a last bit SW 6  of the second control signal  216  and one of the 6 first mirrored currents I m0 ˜I m5 , is configured to generate one of the 6 second mirrored currents I 10 ˜I 15 . Finally, the specific digital voltage signal  212  is converted into an analog current signal  218  when all of the 6 second mirrored currents I 10 ˜I 15  are added together.  
         [0016]    Take the unit  3  shown in FIG. 4 as an example, the first device  301  converts the reference current I ref1  provided by the current source  211  into a first mirrored current I m1  after receiving the second bit SW 1  of the second control signal  216 . The second device  303  then converts the first mirrored current I m1  into a second mirrored current I 11 , according to the value of the second bit D 1  of the specific digital voltage signal  206  while receiving the last bit SW 6  of the second control signal  216 .  
         [0017]    The current source  211  of the embodiment has at least 6 outputs so that it provides 6 different reference currents I ref0 ˜I ref5  for the 6 first devices  301  to respectively generate the 6 first mirrored currents I m0 ˜I m5 . The value of each 6 referent currents I ref0 ˜I ref5  is 2 times larger than that of each preceding one. If I ref0 =2 μA, for example, then I ref1 =4 μA, I ref2 =8 μA, I ref3 =16 μA, I ref4 =32 μA, and I ref5 =64 μA. Assuming that one of the digital voltage signals is (D 5 D 4 D 3 D 2 D 1 D 0 )=(101001), the corresponding analog current signal I TOTAL  generated by the converter  209 , as shown in FIG. 4, will equal IM 0 +I m3 +I m5 =I ref0 +I ref3 +I ref5 =82 μA.  
         [0018]    [0018]FIG. 5 illustrates the circuitry of the unit  3  shown in FIG. 4. The converter  209  can provide a high level voltage source VDD and a low level voltage source VSS externally or internally. The first device  301  includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , and a first capacitor C 1 . The first transistor M 1  and the second transistor M 2  are n-channel TFTs, and the third transistor M 3  is a p-channel TFT. All of the transistors M 1 , M 2 , and M 3  include a source, a drain, and a gate respectively. Since there is no difference between the source and the drain of a TFT, both are renamed as a first terminal and a second terminal in the following description to avoid misunderstanding. The first capacitor C 1  includes a first end  1  st and a second end  2 nd. The interconnections within the first device  301  include: the gate G of the first transistor M 1  is configured to input the second bit SW 1  of the second control signal  216 , the second terminal  2 nd of the first transistor M 1  is connected to the second output I ref1  of the current source  211 , the first terminal  1  st of the first transistor M 1  is respectively connected to the first terminal  1  st of the second transistor M 2  and the second terminal  2 nd of the third transistor M 3 , the gate G of the second transistor M 2  is connected to the gate G of the first transistor M 1 , the second terminal  2 nd of the second transistor M 2  is respectively connected to the gate G of the third transistor M 3  and the second end  2 nd of the first capacitor C 1 , and the first end  1  st of the first capacitor C 1  is respectively connected to the first terminal  1  st of the third transistor M 3  and the high level voltage source VDD.  
         [0019]    The second device  303  includes a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a seventh transistor M 7 , and a second capacitor C 2 . The transistors M 4 ˜M 7  are all n-channel TFTs having a first terminal  1  st, a second terminal  2 nd, and a gate G. The second capacitor C 2  includes a first end  1  st and a second end  2 nd. The interconnections within the second device  303  include: the gate G of the fourth transistor M 4  is configured to input the last bit SW 6  of the second control signal  216 , the second terminal  2 nd of the fourth transistor M 4  is connected to the second terminal  2 nd of the third transistor M 3  of the first device  301 , the first terminal  1  st of the fourth transistor M 4  is respectively connected to the first terminal  1  st of the fifth transistor M 5  and the second terminal  2 nd of the sixth transistor M 6 , the gate G of the fifth transistor M 5  is connected to the gate G of the fourth transistor M 4 , the second terminal  2 nd of the fifth transistor M 5  is respectively connected to the gate G of the sixth transistor M 6  and the second end  2 nd of the second capacitor C 2 , the first end  1  st of the second capacitor C 2  is respectively connected to the first terminal  1  st of the sixth transistor M 6  and the low level voltage source VSS, the first terminal  1  st of the seventh transistor M 7  is connected to the second terminal  2 nd of the sixth transistor M 6 , and the gate G of the seventh transistor M 7  is configured to input the second bit D 1  of the 6-bit digital voltage signal  212 .  
         [0020]    The second bit SW 1  of the second control signal  216  is used to enable or disable the first transistor M 1  and the second transistor M 2 . When SW 1  is high, the first transistor M 1  and the second transistor M 2  are enabled so that the second reference current I ref1  provided by the current source  211  is able to flow through the first transistor M 1  and the third transistor M 3  and hence charge the first capacitor C 1 . In other words, the second reference current I ref1  is converted into a corresponding first voltage stored in the first capacitor C 1 . After the first capacitor C 1  is fully charged, SW 1  will switch to a low level so that the first transistor M 1  and the second transistor M 2  are disabled and, therefore, the first voltage is saved in the first capacitor C 1 .  
         [0021]    The last bit SW 6  of the second control signal  216  is used herein to enable or disable the fourth transistor M 4  and the fifth transistor M 5 . When SW 6  is high, the fourth transistor M 4  and the fifth transistor M 5  are enabled so that the first voltage stored in the first capacitor C 1  is able to convert into a second voltage stored in the second capacitor C 2 . After the second capacitor C 2  is fully charged, SW 6  switches to a low level to disable the fourth transistor M 4  and the fifth transistor M 5  and, therefore, the second voltage is saved in the second capacitor C 2 . If the second bit D 1  of the digital voltage signal  212  transmitted to the converter  209  shown in FIG. 4 is high, the second voltage will be converted into the second mirrored current I 11  flowing through the sixth transistor M 6  and the seventh transistor M 7 . Otherwise, the transistor M 7  will be off and the second mirrored current I 11  will not appear.  
         [0022]    The equation showing the relation of the current and the potential difference between the gate and the source of a field effect transistor (FET) in a saturation region is  
         i   D     =       1   2        μ                   C   OX          W   L            (       v   GS     -     V   t       )     2                             
 
         [0023]    According to this equation, when the first capacitor C 1  is in charging mode, the second reference current I ref1  can be converted into a corresponding V GS  stored in the first capacitor C 1  regardless of the practical aspect ratio, threshold voltage, or mobility of the third transistor M 3 . When SW 6  is high, the V GS  stored in the first capacitor C 1  is converted into the first mirrored current I m1  to charge the second capacitor C 2  through the transistors M 3 , M 4 , and M 6 . Because the V GS  still biases on the third transistor M 3 , the value of the second mirrored current I 11  is substantially equal to that of the first mirrored current I m1 , i.e. equal to the reference current I ref1 .  
         [0024]    Based on the aforementioned function of the unit  3 , one can appreciate that the unit  3  is a current mirror. In this current mirror, SW 1  is regarded as a first control signal for enabling or disabling the first transistor M 1  and the second transistor M 2 ; SW 1  also assures that the reference current I ref1  be converted into the first voltage stored in the first capacitor C 1 . Moreover, SW 6  is regarded as a second control signal for enabling or disabling the fourth transistor M 4  and the fifth transistor M 5 ; SW 6  assures that the first voltage be converted into the corresponding second voltage stored in the second capacitor C 2 . The second mirrored current I 11  is then generated in reference to the second voltage, i.e. in reference to the reference current I ref1 . The framework of the current mirror of the present invention has an advantage of generating a steady mirrored current without respect to the characteristics of the transistors within.  
         [0025]    The frameworks and functions of other units shown in FIG. 4 are identical to those of the unit  3 . As FIG. 4 shows, the second terminals of all the seventh transistors M 7  of the second device  303  are respectively connected to a common node n 1 . A sum I TOTAL  of all the currents flowing through the common node n 1  is one of the analog current signals  218 , which drives one pixel in an AMOLED to emit light. There are N converters  209  provided by the present invention to drive N pixels in an AMOLED to emit light simultaneously.  
         [0026]    As set forth above, the data driver of the present invention is capable of converting digital voltage control signals for controlling pixels to emit light into analog current signals that can drive OLEDs directly. Moreover, the data driver of the present invention is capable of generating steady analog current signals even if the characteristics of the transistors within deviate from theoretical values during fabricating.

Technology Classification (CPC): 7