Patent Abstract:
A test array includes row conductors, column conductors, and memory cells located at crossing points of the row and column conductors. The test array can have groups of the row conductors or the column conductors electrically coupled, or ganged together, so that they share common terminals. Other selected row and column conductors can have individual terminals. In this configuration, memory cells located at the intersection of row and column conductors that have individual terminals can have their characteristics measured using a test apparatus. Ganging together groups of row or column conductors means that the test array has fewer terminals for connection to the test apparatus. Therefore, a test apparatus having a limited number of probes for connection to test array terminals can be used to test arrays of various sizes.

Full Description:
TECHNICAL FIELD  
         [0001]    The technical field is test arrays and methods for testing memory arrays. More specifically, the technical field is test methods and arrays that allow for accurate testing of arrays without undue time or expense.  
         BACKGROUND  
         [0002]    Cross point memory arrays include memory cells located at cross points of horizontal row conductors and vertical column conductors. The memory cells function as the storage elements in cross point memory arrays, and can typically store binary states of either “1” or “0.” The memory cells, the row and column conductors, and other circuitry may be disposed on a substrate. Examples of known cross point memory arrays include non-volatile memories such as one time programmable (OTP) memories, and re-programmable memories. Memory arrays require testing in many circumstances, such as before production on a large scale, and during the development phase of new memory arrays. Testing can involve measuring characteristics of a memory array such as the resistance of memory cells, uniformity of memory cells properties, RH response, resistance-voltage characteristics, and other characteristics.  
           [0003]    One approach to testing is to construct a full scale memory array tester including a full integration of driver circuitry, switching circuitry, and other peripheral circuitry. The term “full scale” indicates that the array to be tested includes a number of memory cells that is generally of the same order of magnitude as the number of memory cells that will be included in a final memory product. Using this approach, the characteristics of the test array can be determined by selectively switching the states of the memory cells and by measuring the characteristics of the memory cells under different operating conditions. This testing technique may be effective in determining the characteristics of a test array, but the production of a full scale tester including peripheral circuitry is very expensive and time consuming.  
           [0004]    Another technique for testing arrays involves constructing a test array having a full integration of peripheral circuitry in the test array. The characteristics of the test array can therefore be tested using the peripheral circuitry in the array. This technique is also expensive and time consuming, because it involves constructing a completed array during the testing phase.  
           [0005]    Another technique for testing memory arrays is to construct a test array that is smaller in scale than the memory array that will be used in the final memory product. The results from the small scale test array are utilized as representative of the results of a full scale memory array. This technique may be unsatisfactory because small scale testing cannot duplicate loading effects, settling times, and other phenomena that occur in full scale arrays. Small scale testing therefore may not be sufficiently accurate for some applications.  
           [0006]    A need therefore exists for a test array and a method for accurately testing memory arrays that do not involve excessive cost or delay.  
         SUMMARY  
         [0007]    According to a first aspect, a test array comprises a plurality of row conductors, a plurality of column conductors, and a plurality of memory cells located at cross points of the row and column conductors. The row and the column conductors can include groups of conductors that are electrically coupled, or “ganged” together. The ganged conductors may be coupled to a common terminal. The row and column conductors also include conductors that are connected to individual terminals. Memory cells located at cross points of row and column conductors connected to individual terminals can have their characteristics measured by a test apparatus during testing. The groups of ganged row and column conductors can have common currents or potentials applied to the ganged conductors during testing.  
           [0008]    According to the first aspect, the number of terminals of the test array may be relatively small. Therefore, a test apparatus having a limited or a fixed number of probes for connection to the test array can be used to test the array. By selectively ganging together row and/or column conductors, a very large test array can be tested with a test apparatus having a relatively small number of probes.  
           [0009]    Also according to the first aspect, the test array can be tested at full scale without undue expense. In addition, a full integration of switching and other circuitry is not required in the test array for testing. Therefore, a test array can be assembled relatively cheaply and quickly, reducing the time and cost for development of new arrays.  
           [0010]    Also according to the first aspect, the use of a full scale test array provides more reliable test data than small scale test data because loading effects, settling times, and other characteristics are more accurately predicted by full scale arrays. This feature helps ensure that test data from selected memory cells in the test array are representative of how a full scale final product memory array based on the test array design will perform.  
           [0011]    According to a second aspect, a method of testing a test array includes applying an input to a selected row conductor, wherein the selected row conductor crosses a selected memory cell, measuring an output from a selected column conductor, wherein the selected column conductor crosses the selected memory cell, and applying a common input to common terminals of the test array. The common terminals are each coupled to a group of ganged column conductors.  
           [0012]    According to the second aspect, the application of a common input to the groups of column conductors allows an expected operational environment of the test array to be simulated. Because the common input can be applied to groups of column conductors through the common terminals, the test array requires fewer terminals to connect to the test apparatus used to test the test array. In addition, the test apparatus requires fewer probes for connection with the test array terminals.  
           [0013]    Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying figures. 
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0014]    The detailed description will refer to the following figures wherein like reference numerals refer to like elements and wherein:  
         [0015]    [0015]FIG. 1 is a schematic view of a test array according to a first embodiment;  
         [0016]    [0016]FIG. 2 is a schematic view of a test array according to a second embodiment;  
         [0017]    [0017]FIG. 3 is a schematic view a test apparatus; and  
         [0018]    [0018]FIG. 4 is a schematic view of test board of the test apparatus illustrated in FIG. 3. 
     
    
     DETAILED DESCRIPTION  
       [0019]    Test arrays and a method for testing arrays will be discussed by way of preferred embodiments and by way of the figures.  
         [0020]    [0020]FIG. 1 is a schematic view of a test array  100  according to a first embodiment. The test array  100  includes a plurality of row conductors  110  and column conductors  120 . The row conductors  110  cross the column conductors  120  at memory cells  130 . The test array  100  is a cross point memory array, and can be of any cross point memory type, such as, for example, a magnetic random access memory (MRAM), a fuse memory, an anti-fuse memory, a charge storage, a mask read only (mask ROM) memory, and other memory types.  
         [0021]    The row conductors  110  of the test array  100  terminate in conductive terminals  112 , and the column conductors  120  terminate in conductive terminals  122 . In FIG. 1, the terminals  112 ,  122  are illustrated as conductive pads. However, any form of conductive terminal is appropriate for use in the test array  100 . The terminals  112 ,  122  are used to couple the test array  100  to a test device (not illustrated in FIG. 1) to determine characteristics of the memory array  100 . The terminals  112 ,  122  can be disposed over a substrate (not illustrated) of the array  100 . The test array  100  illustrated in FIG. 1 comprises q row conductors  110 , p column conductors  120 , and p×q memory cells  130 , where p and q are integers.  
         [0022]    According to the first embodiment, a number of the column conductors  120  of the test array  100  are electrically coupled, or “ganged” together as a group  124 , and have a common output at common terminals  126 . A “group” can comprise, for example, two or more conductors (the individual conductors in the groups  124  are not shown for illustrative purposes). In FIG. 1, the first two column conductors  110  each terminate in individual terminals  122 . The column conductors  120  in columns  3  through n are electrically coupled and terminate in common terminals  126 , where n is an integer. The effect of this arrangement is to reduce the number of terminals for connection with a test apparatus during testing of the test array  100 . The common terminals can be disposed over a substrate (not illustrated) of the test array  100 .  
         [0023]    Because specified column conductors  120  share common terminals  126 , test data would not ordinarily be gathered from the memory cells  130  that are coupled to the ganged column conductors  120 . Data is ideally taken from memory cells  130  crossing column conductors  120  that have individual terminals  122 . A tester therefore determines what number of memory cells  130  should be accessible to test measurements to provide a statistically representative sample of the characteristics of the test array  100 . A number of column conductors  120  are chosen to terminate in the individual conductive pads  122  to allow measurements of the desired sample population of memory cells  130 . The remaining column conductors  120  can be ganged into the groups  124 . The number of column conductors  120  having individual terminals  122  may therefore depend upon the size of test array  100 , and the statistical sample (i.e., the number of memory cells  130  accessible for measurement) desired for a particular application.  
         [0024]    The inclusion of the common terminals  126  allows common inputs, such as, for example, potentials, currents, or other inputs, to be applied to the ganged conductors  120  in the groups  124 . Potentials, currents, and other inputs may be applied to the groups  124  during testing in order to simulate an expected operating environment for the test array  100 . An expected operational environment of the device is, generally, the conditions anticipated for a final product memory array based on the test array  100  design. This feature helps ensure that test data from selected memory cells  130  in the test array  100  are representative of how a memory array based on the test array  100  design will perform in actual operation.  
         [0025]    Depending upon the test measurements to be taken from the test array  100 , the groups  124  and the column conductors  120  may need only one terminal  126 ,  122 , respectively. For example, if the testing process for a test array  100  will only involve the application of a potential to selected column conductors  120 , the column conductors  120  may need only one terminal  122 ,  126 , rather than a terminal  122 ,  126  at each end.  
         [0026]    In FIG. 1, two column conductors  120  terminate in individual terminals  122 , and 3-n column conductors  120  share a common terminal  126 . The pattern of 1, 2, 3-n, 1, 2, 3-n . . . repeats over the p column conductors  120 . The pattern of 1, 2, 3-n, 1, 2, 3-n . . . is exemplary of an arrangement for ganging together selected column conductors  120 , and other arrangements are possible. One possible alternative arrangement is, for example 1, 2-n, 1, 2-n, . . .  
         [0027]    In FIG. 1, only selected column conductors  120  are electrically coupled to reduce the number of terminals for connection with a test apparatus during testing. FIG. 2 illustrates an alternative embodiment of a test array  200  having ganged row and column conductors.  
         [0028]    Referring to FIG. 2, the memory array  200  includes row conductors  210  that either terminate in individual terminals  212 , or that are ganged together as a group  214  and that share common terminals  216 . Similarly, the column conductors  220  either terminate in individual terminals  222 , or are ganged together as a group  224  and share common terminals  226 . In FIG. 2, the terminals  212 ,  222 ,  216 ,  226  are illustrated as conductive pads. However, any form of conductive terminal is appropriate for use in the test array  200 . The terminals  212 ,  222 ,  216 ,  226  can be disposed over a substrate (not illustrated) of the test array  200 .  
         [0029]    The row conductors  210  include a repeating pattern of 1 individual conductor  210  followed by 2 through m ganged conductors  210 , with a total of q row conductors  210 . The column conductors  220  include a repeating pattern of 1 column conductor  220  followed by 2-n ganged column conductors  220 , totaling p column conductors  220 . In this embodiment, m, n, p and q are integers.  
         [0030]    According to the above embodiments, a test array can include a selected number of row and/or column conductors that are electrically coupled, or ganged together, to reduce the number of terminals for connection with test probes during the testing process. One advantage to this arrangement is that test arrays of different size can be tested by a test apparatus having a relatively small number of probes. Advantageously, test arrays in a particular lab or other testing environment can be constructed to correspond to one of a set of a standardized number of terminals, so that a single test apparatus can be utilized to test a variety of test arrays. The number of terminals in test arrays can be standardized by selectively ganging a greater or lesser number of row and/or column conductors into groups.  
         [0031]    Another advantage to the above embodiments is that a test array having a relatively large number of memory cells can be accurately tested. In other words, the test array can be tested at full size. Therefore characteristics such as loading effects, defect density, settling times, and other characteristics of the test array will be similar to a final product memory array based on the test array design. In addition, there is no requirement for the integration of switching circuitry and other peripheral circuitry in order to test the test array.  
         [0032]    A test apparatus  10  for testing test arrays is discussed below with reference to FIGS. 3 and 4. FIG. 3 is a schematic view of the test apparatus  10 , and FIG. 4 is a schematic view of a test board  20  of the test apparatus  10 .  
         [0033]    Referring to FIG. 3, the test apparatus  10  comprises a test board  20 , test electronics  12 , and a processor  90 . The test board  20  is coupled to the test electronics  12  by conductors  22 . The test electronics  12  comprises a multiplexer  30 , a decoder  40 , a read amplifier  50 , a read/write control  60 , and a current source  70 . The processor  90  is coupled to the test electronics  12  via Add, Data, and R/W lines through an I/O device  92 .  
         [0034]    In FIG. 3, the test board  20  is symbolically represented with a test array  100  mounted on the test board  20 , however other test array embodiments discussed in this specification may also be tested with the test apparatus  10 . The test board  20  supports the test array  100  during testing, and includes conductive probes that can provide inputs to row and column conductors  110 ,  120  of the test array  100 , and can also receive outputs from the row and column conductors  110 ,  120 . The test array  100  is mounted on the test board  20  so that selected probes of the test board  20  contact selected terminals of the test array  100 . The test board  20  is discussed in detail below with reference to FIG. 4.  
         [0035]    The test apparatus  10  can supply, for example, inputs such as potentials and currents to ganged row and column conductors  110 ,  120  to simulate an expected operational environment for the test array  100 . The processor  90  controls the testing process, and may comprise, for example, a central processing unit. The processor  90  can operate the test apparatus  10  in either a write mode, in which memory cells  130  in the test array  100  can be programmed, or a read mode, in which characteristics of the test array  100  can be measured. The read/write control  60  controls the test electronics  12  in the read and write modes. The multiplexer  30  serves to multiplex signals between the row and column conductors  110 ,  120 , and the decoder  40  decodes data to and from the multiplexer  30 . Data from the test array  100 , such as current magnitudes, are detected by the read amplifier  50  before forwarding to the processor  90  on the Data line. The current source  70  can be a programmable current source used to supply write currents to the test array  100 . The test electronics  12  can also include digital-to-analog converters and other converters so that the current source  70  can provide, for example, read voltages and other inputs to the test array  100 .  
         [0036]    [0036]FIG. 4 is a schematic view of the test board  20 . The test board  20  includes a plurality of probes  25  for contacting conductive terminals of a test array. The probes  25  are arranged in sets  26 - 29  to contact both individual and common terminals of a test array when the test array is placed on the test board  20 . The sets  26 - 29  may each have differing numbers of probes  25  to accommodate different test array configurations.  
         [0037]    Each of the probes  25  may be connected to one of the conductors  22  leading to the test electronics  12 . The controller  90  can instruct the test electronics  12  to receive an output from a column or row conductor coupled to a particular probe  25 , or to apply an input, such as a write voltage or current, or a read voltage or current, to a column or row conductor coupled to a particular probe  25 .  
         [0038]    A test array can be oriented in several ways on the test board  20  by rotating the test array  90  degrees before mounting on the test board  20 . This feature allows different arrangements of row and column conductors to be coupled to different sets  26 - 29  of probes  25 .  
         [0039]    According to the above embodiments, the number of probes  25  on the test board  20  can be relatively small because row and column conductors in a test array can be ganged to receive a common input from the test board  20 . For example, in FIG. 4, the test board  20  includes  16  probes in set  26 , and  24  probes in set  28 . The probes in set  26 , and the corresponding (i.e., directly across from) probes in set  28 , can be coupled to column conductors having individual terminals. The probes in set  28  that do not correspond to a probe in set  26  can be coupled to a common terminal in the test array to allow, for example, an equal potential to be applied to ganged column conductors.  
         [0040]    In one mode of operation, a selected memory cell located at the cross point of a row line and a column conductor having an individual terminal can have its resistance measured by the test apparatus  10 . In this mode, a read current is generated by applying a read voltage to the row line crossing the selected memory cell, and the column conductor crossing the selected memory cell can be coupled to the test electronics  12  via the conductors  22 . The column conductor crossing the selected memory cell includes an individual terminal. The value of the read current through the selected memory cell can be determined by the read amplifier  50 . The processor  90  can determine the selected memory cell  130  resistance from the read current value. During the read operation, a common input, such as a potential, can be applied to the remaining column conductors in the test array, including ganged and individual conductors.  
         [0041]    In the above examples, if selected column conductors were not ganged, a probe would be required to contact a terminal of each column conductor terminal in order to provide every column conductor of the test array with the potential. This feature is particularly advantageous in applications in which an equal potential, or another common input, is used to simulate expected operating conditions in the test array.  
         [0042]    According to the above embodiments, common inputs can be supplied to any conductors in a test array without undue expense or delay in the development process. The test array can be at or near full scale, so that loading effects, settling times, and other characteristics measured from the test array can be similar to a final product array based on the test array design.  
         [0043]    A further advantage is that the test apparatus  10  can be used to test arrays of different size. By ganging together selected numbers of row and column conductors, a fixed number of conductive pads can be used in any test array. Therefore, a test apparatus  10  having a fixed or limited number of probes can be used to test various arrays.  
         [0044]    In the present specification, the terms “row” and “column” do not imply a fixed orientation in a memory array. In addition, the terms “row” and “column” do not necessarily imply an orthogonal relationship.  
         [0045]    While the testing methods and apparatuses have been described with reference to the exemplary embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations.

Technology Classification (CPC): 6