Patent Abstract:
An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.

Full Description:
RELATED APPLICATIONS 
     The present application is based on, and claims priority from, Taiwan Application Number 96147382, filed Dec. 12, 2007 the disclosure of which is hereby incorporated by reference herein in its entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a fast locked all digital phase lock loop and control method thereof. 
     2. Description of the Related Art 
     All digital phase lock loop (PLL) technology is one of the major technological breakthroughs for wireless communication, because it may be implemented easier in system on chip (SOC) devices manufactured by advanced semiconductor process than the analog phase lock loop. However, designing an all digital PLL with features such as fast locking and low phase noise is challenging. 
       FIG. 1  is a schematic diagram of a conventional all digital phase lock loop viewed in the phase domain. Following, a digital phase lock loop is briefly introduced. However, for a more detailed description of the digital phase lock loop in  FIG. 1 , reference can be made to U.S. Pat. No. 7,145,399. 
     The phase error φ E  between the variable signal f v  and reference signal f ref  can be determined by the phase detector  115 . As shown in  FIG. 1 , the phase detector  115  has three inputs, where one input is provided by inputting the reference signal f ref  to the reference phase accumulator  105  and is regarded as the phase of the reference signal f ref . Another input is provided by inputting the variable signal f v  to the oscillator phase accumulator  140  and the sampler  145  and is regarded as the phase of the variable signal f v . The last input is the fractional phase error between the variable signal f v  and reference signal f ref . The sum of the three inputs is the phase error φ E . 
     The loop filter  120  filters the phase error φ E  and/or adjusts the magnitude of phase error φ E . The loop filter  120  generates an oscillator tuning word (OTW) to modify the output of a digitally controlled oscillator (DCO)  125 , i.e. the variable signal f v . 
     In the current design of the all digital phase lock loops, gear shift mechanism and type II and higher order loop filters are utilized for achieving the purposes of fast locking and low phase noise. In U.S. Pub. No. 2003/0234693, an all digital phase lock loop is disclosed. 
     However, designers still must design an adaptive all digital phase lock loop. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment consistent with the invention, there is provided an all digital phase lock loop is disclosed, comprising a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word comprises a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator capable to be adjusted by the second tuning word is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word. 
     An exemplary embodiment consistent with the invention, there is provided a control method for a phase lock loop is disclosed, comprising low pass filtering a phase error for several times to generate an oscillator tuning word to control a digitally controlled oscillator, wherein the oscillator tuning word comprises a first tuning word and a second tuning word, and the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word; detecting two filter outputs of a front low pass filter and a back low pass filter; determining whether the two filter outputs meet a predetermined condition; adjusting the second tuning word when the two filter outputs meet the predetermined condition. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a schematic diagram of a conventional all digital phase lock loop viewed in the phase domain. 
         FIG. 2  is a schematic diagram of an exemplary embodiment of a loop filter  600  consistent with the invention. 
         FIG. 3  is a schematic diagram of an exemplary embodiment of a decision circuit  700  consistent with the invention 
         FIG. 4  is a schematic diagram of part of a digitally controlled oscillator  800 . 
         FIG. 5  is a schematic diagram of another exemplary embodiment of a loop filter  800  consistent with the invention. 
         FIG. 6  is a flowchart  900  of an exemplary embodiment of a control method for a phase lock loop consistent with the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments consistent with the present invention do not represent all implementations consistent with the invention. Instead, they are merely examples of systems and methods consistent with aspects related to the invention as recited in the appended claims. 
       FIG. 2  is a schematic diagram of an exemplary embodiment of a loop filter  600  consistent with the invention. The loop filter  600  receives the phase error φ E  and accordingly controls a digitally controlled oscillator. When the loop filter  120  of  FIG. 1  is replaced by the loop filter  600 , an all digital phase lock loop consistent with the invention is generated. The loop filter  600  of  FIG. 2  outputs an oscillator tuning word comprising a process-voltage-temperature (PVT) tuning word, an acquisition (ACQ) tuning word, and a tracking (ACK) tuning word. For example, the oscillator tuning word output by the loop filter  600  has 22 bits, OTW[ 0 : 21 ], wherein the 8 bits OTW[ 14 : 21 ] is the PVT tuning word, the 8 bits OTW[ 6 : 13 ] is the ACQ tuning word, and the 6 bits OTW[ 0 : 5 ] is the ACK tuning word. The tracking tuning word is generated based on the sum of the output of a multiplier  604  and the accumulated value from an accumulator  608 . The frequency range of the digitally controlled oscillator capable to be adjusted by the PVT tuning word is large and thus accordingly, the adjustment step is also large. The PVT tuning word generally reduces the bad effect due to the Process-Voltage-Temperature variations of the chip. The frequency range of the digitally controlled oscillator capable to be adjusted by the ACK tuning word is small and thus accordingly, the accuracy of adjustment is large. The ACK tuning word is used for calibrating the frequency of the all digital phase lock loop when tracking the carrier signal. The frequency range of the digitally controlled oscillator capable to be adjusted by the ACQ tuning word and corresponding accuracy of adjustment is within the average. The ACQ tuning word is used for calibrating the frequency of the all digital phase lock loop when determining the frequency channel. 
     The loop filter  600  of  FIG. 2  has a plurality of stages of the low pass filters  602   a - 602   c . In  FIG. 2 , each low pass filter is an infinite impulse response (IIR) filter or a finite impulse response (FIR) filter. The output of the low pass filter  602   c  can be transmitted to a multiplier  604  to be multiplied with a loop gain α. The loop gain α also can be applied to other low pass filters to adjust the filter output of each low pass filter. The phase error φ E  can be multiplied with a loop gain β, by a multiplier  606 , and then transmitted to the accumulator  608 . The sum of the multiplier  604  and accumulator  608  generates the tracking tuning word. In a word, the low pass filters  602   a  to  602   c  and the multiplier  604  forms a type II higher order filter and its time response is slower because the phase error φ E  is processed by several stages of the low pass filters and accordingly the tracking tuning word is affected by the phase error φ E . The multiplier  606  and accumulator  608  provide a faster path for the phase error φ E  to affect the tracking tuning word. 
     The loop filter  600  of  FIG. 2  further comprises two modification circuits  610   a  and  610   b . The modification circuit  610   a  has two decision circuits,  6104   a  and  6106   a , an accumulator  6102   a  and an adder  6108   a . The modification circuit  610   b  has two decision circuits,  6104   b  and  6106   b , an accumulator  6102   b  and an adder  6108   b . Although the function block diagrams of the modification circuits  610   a  and  610   b  shown in  FIG. 2  are the same as each other, the circuits of the same function block may be implemented by different circuits. 
     The modification circuit  610   a  directly detects the outputs of the low pass filters  602   a  and  602   b . Once the modification circuit  610   a  detects that the outputs of the low pass filters  602   a  and  602   b  meet a predetermined condition, the modification circuit  610   a  modifies the PVT tuning word via the adder  612 . Thus, the frequency of the all digital phase lock loop, i.e. the frequency of the variable signal f v , can be significantly changed. 
     The modification circuit  610   b  directly detects the output of the low pass filter  602   b  and indirectly detects the output of the last stage of the low pass filter, i.e. the low pass filter  602   c , via the multiplier  604  and adder  618 . Once the modification circuit  610   b  detects that the outputs of the low pass filters  602   b  and  602   c  meet a predetermined condition, the modification circuit  610   b  modifies the ACQ tuning word, wherein the predetermined condition of the modification circuit  610   a  may be the same as or different from the predetermined condition of the modification circuit  610   b.    
       FIG. 3  is a schematic diagram of an exemplary embodiment of a decision circuit  700  consistent with the invention. The decision circuit shown in  FIG. 3  can be applied to the decision circuit  6104   a ,  6104   b ,  6106   a  or  6106   b . The comparator  702  compares the input of the decision circuit  700  and a predetermined upper bond (UPB), and the comparator  704  compares the input of the decision circuit  700  and a predetermined lower bond (LWB). The output of the comparator  702  or comparator  704  is 1 or −1, and the sum of the two outputs, by the adder  706 , is the output of the decision circuit  700 . The function of the decision circuit  700  is described in the following. If the input of the decision circuit  700  is higher than the UPB, the output of the decision circuit  700  is 1. If the input of the decision circuit  700  is lower than the LWB, the output of the decision circuit  700  is −1. If the input of the decision circuit  700  is between the LWB and UPB, the output of the decision circuit  700  is 0. If the output of the decision circuit  700  varies acutely, the input of the decision circuit  700  can be multiplied with a parameter λ to decrease the variation of the output of the decision circuit  700 . 
     Take the modification circuit  610   b  in  FIG. 2  for example, if the decision circuits  6104   b  and  6106   b  adopt the decision circuit  700  in  FIG. 3 , the UPB and LWB of the decision circuit  6104   b  respectively is UPBa and LWBa, and the UPB and LWB of the decision circuit  6106   b  respectively is UPBb and LWBb, the function of the modification circuit  610   b  is described in the following. 
     When the phase is approximately locked, i.e., the phase error φ E  is very small, the output of the filter  602   b  is substantially maintained between UPBa and LWBa, and the output of the filter  602   c  is substantially maintained between UPBb and LWBb. Accordingly, the outputs of the decision circuits  6104   b  and  6106   b  are 0, and the output of the accumulator  6102   b  does not change. Thus, the ACQ tuning word is not affected by the output of the accumulator  6102   b.    
     When the phase error φ E  increases, the output of the filter  602   b  may diverge from the range between UPBa and LWBa, and the output of the filter  602   c  may later diverge from the range between UPBb and LWBb. Since the response of the whole phase lock loop is quite slow, the described two diverging trends are substantially the same. The time delay is because the output of the low pass filter  602   c  is generated by low pass filtering the output of the low pass filter  602   b . For example, when the output of the low pass filter  602   b  suddenly exceeds UPBa and the output of the low pass filter  602   c  is still between the UPBb and LWBb, the output of the decision circuit  6104   b  becomes  1 , the output of the decision circuit  6106   b  is still 0, and the output of the accumulator  6102   b  periodically increases by 1 according to the input clock signal. Thus, the modification circuit  610   b  periodically increases the ACQ tuning word by 1. The output of the low pass filter  602   c  follows the output of the low pass filter  602   b , but the output of the low pass filter  602   c  later varies. Once the output of the low pass filter  602   c  is larger than UPBb, the outputs of the decision circuits  6104   b  and  6106   b  are also 1, the accumulator  6102   b  stops increasing its output and the modification circuit  610   b  also stops increasing the ACQ tuning word. Similarly, when the outputs of the low pass filters  602   b  and  602   c  decrease, the modification circuit  610   b  may periodically decrease the ACQ tuning word and after a period of time, the modification circuit  610   b  stops affecting the ACQ tuning word. 
     In other words, the modification circuit  610   b  determines whether the amount of times the low pass filter  602   b  is output is too much according to the UPBa and LWBa. Once the amount of times the low pass filter  602   b  is output is too much, the modification circuit  610   b  roughly adjusts the output frequency of a digitally controlled oscillator. The UPBa and LWBa serve as a stop mechanism for the modification circuit  610   b . In other words, the UPBa and LWBa determines the amount of frequency adjustments. 
     According to the above description of the modification circuit  610   b , those skilled in the art can easily understand the operation of the modification circuit  610   a . When the modification circuit  610   a  determines that the amount of times the low pass filter  602   a  is output is too much, the modification circuit  610   a  coarsely adjusts the output frequency of a digitally controlled oscillator. The UPBa and LWBa serve as a stop mechanism for the modification circuit  610   a . In other words, the UPBa and LWBa determines the amount of frequency adjustments. 
     As to the UPB and LWB of each decision circuit, the UPB and LWB are respectively determined based on circuit design or requirement. 
     The modification circuits  610   a  and  610   b  quickly and coarsely adjust the output frequency of a digitally controlled oscillator. Without the modification circuits  610   a  and  610   b  in  FIG. 2 , the PVT tuning word can only be affected by the carry bit of the ACQ tuning word, and the ACQ tuning word only can be affected by the carry bit of the ACK tuning word. Thus, the PVT tuning word and the ACQ tuning can only be increased by 1 after each phase lock operation. Compared with  FIG. 2 , the modification circuits  610   a  and  610   b  provide a mechanism for quickly and coarsely adjusting the output frequency of the digitally controlled oscillator by a large margin. It can be expected that an all digital phase lock loop with the loop filter  600  in  FIG. 2  can lock its phase quickly. 
     Although the loop filter  600  in  FIG. 2  is shown by a functional block, the loop filter  600  can be implemented by hardware or software. 
       FIG. 4  is a schematic diagram of part of a digitally controlled oscillator  800 . The digitally controlled oscillator  800  comprises one inductor and a plurality of capacitors, and its output frequency is determined by the following equation: f DCO =1/squr(L*C total ), wherein the C total  is the sum of the capacitances of activated capacitors. The capacitors in the digitally controlled oscillator  800  are substantially divided into four banks: a PVT bank, an ACQ bank, a tracking bank and a partial tracking bank. The capacitors in the PVT bank are Δ C 0   P  . . . ΔC 7   P , arranged binary-weighted, respectively selected by the control signal d 0   P  . . . d 7   P . The PVT tuning word is applied to some interfaces and the control signal is generated after the PVT tuning word is processed by the interfaces. In other word, the capacitors in the PVT bank are controlled by the PVT tuning word. Similarly, the capacitors in the ACQ bank are controlled by the ACQ tuning word. The capacitors in the tracking band are the same (unit-weighted) and the capacitance of each capacitor is designed as small as possible. The signals d 0   TI  . . . d 63   TI  are generated after the tracking tuning word is decoded and processed by some interface. If the capacitance provided by the tracking bank cannot effectively suppress the phase noise, the capacitors in the partial tracking bank can be initiated to provide capacitance. The capacitance of each capacitor in the partial tracking bank is the same as the capacitor in the tracking bank. The partial tracking bank is controlled by a ΣΔ modulator to provide fine capacitance accuracy and the control signal d 0   TF  . . . d 7   TF  is generated by the ΣΔ modulator. Basically, the tracking bank and the partial tracking bank are controlled by the tracking tuning word. As previously described, the PVT tuning word coarsely adjusts the output frequency of the digitally controlled oscillator. The tracking finely adjusts tuning of the output frequency of the digitally controlled oscillator and the ACQ tuning word averagely adjusts the output frequency of the digitally controlled oscillator. Therefore, the smallest capacitor in the PVT bank is larger than the smallest capacitor in the ACQ bank and the smallest capacitor in the ACQ bank is larger than each capacitor in the tracking bank and the partial tracking bank. 
     Please refer to  FIG. 2 , wherein the modification circuit  610   a  is coupled to the low pass filter  602   a  and the low pass filter  602   b , the low pass filter  602   a  is a front low pass filter, and the low pass filter  602   b  is a back low pass filter to process the filter output of the low pass filter  602   a . Similarly, the modification circuit  610   b  is coupled to the low pass filter  602   b  and the low pass filter  602   c , the low pass filter  602   b  is a front low pass filter, and the low pass filter  602   c  is a back low pass filter. Thus, the low pass filter  602   b  is the back low pass filter detected by the modification circuit  610   a  and the front low pass filter detected by the modification circuit  610   b . However, it is not necessary that the modification circuits  610   a  and  610   b  detect the same low pass filter.  FIG. 5  is a schematic diagram of another exemplary embodiment of a loop filter  800  consistent with the invention, wherein the modification circuits  610   a  and  610   b  do not detect the same low pass filter. 
     Please also refer to  FIG. 2  and  FIG. 6  for reference.  FIG. 6  is a flowchart  900  of an exemplary embodiment of a control method for a phase lock loop consistent with the invention. When an all digital phase lock loop with the loop filter  600  shown in  FIG. 2  starts tracking a reference signal, the coarse tracking in the step  902  is first executed, and after a period of time, the fast tracking in the step  904  is executed. 
     In the step  902 , the modification circuits  610   a  and  610   b  are enabled, and the loop gain α and partial gain β do not change. Thus, the ACQ tuning word may be slightly affected by the carry bit of the tracking tuning word, and may be heavily affected by the modification circuit  610   b . Similarly, the PVT tuning word may be slightly affected by the carry bit of the ACQ tuning word, and may be heavily affected by the modification circuit  610   a.    
     After a period of time or when the coarse tuning has been substantially finished, the values of the accumulators  6102   a  and  6102   b  are substantially fixed and the method goes to the step  904 . In step  904 , the modification circuits  610   a  and  610   b  are disabled, and the loop gain a and partial gain β can be first increased and then decreased after a period of time. In other words, when executing the step  904 , the loop gain a and partial gain β can be the same as the loop gain α and partial gain β in step  902  for a period of time. After that, the phase lock operation is substantially finished, and in order to reduce the noise caused by the phase lock loop, a smaller loop gain α and partial gain β are adopted. The operation for reducing the loop gain α and partial gain β can be implemented at more than one time according to the circuit design and the phase lock speed requirement. It is recommended that the operation of reducing the loop gain α and partial gain β be executed at least two times. 
     An all digital phase lock loop with higher order loop filters consistent with the invention is provided. The disclosed all digital phase lock loop can reduce the phase noise that is self generated and coarsely and quickly adjust its output frequency to achieve the goal of fast phase lock. 
     It will be appreciated that the present invention is not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof. It is intended that the scope of the invention only be limited by the appended claims.

Technology Classification (CPC): 7