Patent Abstract:
A multi-chip electronic package and methods of manufacture are provided. The method comprises adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting comprises placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further comprise lowering the lid until the pistons contact the chip shim. The method further comprises separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further comprises dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further comprises sealing the lid to the chip carrier with sealant.

Full Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to semiconductor package structures and methods of manufacture and, more particularly, to multi-chip electronic packages and methods of manufacture. 
       BACKGROUND 
       [0002]    Thermal management of multi-chip electronic packages is critical to ideal performance of the multi-chip electronic packages. Currently, multi-chip electronic packages encapsulate chips between a lid and chip carrier by forming a customized gap between pistons of the lid and the chips mounted on the chip carrier, and dispensing a thermal interface material (TIM) within the gap. The gap is formed by the use of a chip shim placed between pistons of the lid and the chips of the multi-chip electronic packages. 
         [0003]    Referring to  FIGS. 1   a  and  1   b , a plurality of chips  12  are shown attached to a chip carrier  10 . During assembly, a chip shim  15  is placed between pistons  16  and chip  12  in order to form a gap between the pistons  16  and the chips  12  ( FIG. 1   a ). A lid or hat  14  (hereinafter referred to as a lid) is positioned over the chip carrier  10 . The lid has “pistons”  16  that are moved such that they contact the chip shim  15 . The lid  14  is then removed from the chip carrier  10 , and the pistons  16  are fixedly attached to the lid  14 . The chip shim  15  is removed and thermal interface material is then placed on the chips. Once the thermal interface material is on the chips  12 , the chip carrier  10  and lid  14  are sealed to one another in order to encapsulate the chips  12  ( FIG. 1   b ). As shown in  FIG. 1   b , the surface of the lid  14  will typically contact a surface of the chip carrier  10 , in the assembled state. 
         [0004]    The assembly process described with reference to  FIGS. 1   a  and  1   b , however, results in a large thermal interface gap between the surface of the chip  12  and the respective piston  16 , e.g., on the order of about 80 microns or more. This resultant thermal interface gap is largely due to the structural constraints of the lid  14 , e.g., the edges of the lid  14  contacting the surface of the chip carrier  10 , when in the assembled state. More specifically, the structural constraint of the assembly physically blocks the lid from moving closer to the chip carrier  10 , hence preventing the pistons from closing such thermal interface gap. And, due to this larger gap, additional large thermal interface gap, e.g., 80 microns or more, is between the pistons  16  and the chips  12  which, in turn, actually reduces the thermal performance of the Multi-chip module (MCM). That is, the added thermal paste to fill the gap between the chip  12  and the respective piston  16  with higher thermal resistance increases chip temperature in MCM. 
         [0005]    Also, the direct load through particles between the lid  14  and the chip carrier  10  results in a load distributed more uniformly across the chip carrier  10 . This reduces load and decreases on the stress on the chip carrier  10 . The warpage of the lid  14  further degrades thermal performance for additional TIM between the hat and heatsink. 
         [0006]    Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove. 
       SUMMARY 
       [0007]    In a first aspect of the invention, a method comprises adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting comprises placing a chip shim on the one or more chips on the chip carrier and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The lid is placed on a seal shim and then lowered on one or more pistons which contact the chip shim. The adjusting further comprises displacing the one or more pistons and lid individually until full surface contact with both the chip shim and the seal shim is established and fixing the one or more pistons to the lid in the displaced position. The method further comprises separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further comprises dispensing thermal interface material on the one or more chips and lowering the lid until a gap filled with the thermal interface material where TIM gap is about a particle size of the thermal interface material. The method further comprises sealing the lid to the chip carrier with sealant between the lid and the chip carrier. 
         [0008]    In another aspect of the invention, a method comprises placing a seal shim on at least one of a lid and a chip carrier and placing a chip shim over chips on the chip carrier. The method further comprises placing the lid and the chip carrier in proximity to one another such that pistons of the lid are in registration with chips on the chip carrier. The seal shim prevents the lid from contacting with the chip carrier. The method further comprises contacting the pistons with the chip shim, fixing the pistons to the lid in a contacted position with the chips, and moving apart the lid and the chip carrier. The method further comprises removing the seal shim and the chip shim. The method further comprises dispensing thermal interface material on the chips and placing sealant on at least one of the lid and the chip. The method further comprises moving the lid and the chip carrier together to compress the thermal interface material to a particle size between the pistons and the chips. The method further comprises sealing the lid to the chip carrier with sealant. In embodiments, the seal module is non-hermetic with polymer sealant material or can also be hermetic with solder seal. 
         [0009]    In yet another aspect of the invention, a structure comprises a lid encapsulating at least one chip mounted on a chip carrier. A gap is between the pistons of the lid and respective ones of the chips. The gap is a particle size of thermal interface material within the gap, which contacts the pistons and the respective ones of the chips. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0010]    The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention. 
           [0011]      FIGS. 1   a  and  1   b  show conventional multi-chip electronic packages and methods of manufacture; 
           [0012]      FIGS. 2-4 ,  5   a ,  5   b , and  6  show stages of fabricating multi-chip electronic packages in accordance with aspects of the present invention; 
           [0013]      FIGS. 7   a  and  7   b  show performance graphs of a multi-chip electronic package manufactured in accordance aspects of the present invention vs. a conventional multi-chip electronic package; 
           [0014]      FIG. 8  shows a graph of lid warpage vs. sealant (seal band) thickness; 
           [0015]      FIG. 9  shows a graph comparing module TIM movement (“pumping”) and sealant thickness for lid pumping during accelerated thermal cycling (ATC), lab power cycling and field-use power cycling; and 
           [0016]      FIG. 10  shows stress analysis in the chip carrier obtained from thermo-mechanical analysis of a conventional multi-chip electronic package and a multi-chip electronic package in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    The invention relates to semiconductor structures and methods of manufacture and, more particularly, to multi-chip electronic packages and methods of manufacture. More specifically, the present invention addresses the thermal management design of multi-chip electronic packages by using a seal shim to control a thermal interface gap provided between a lid and chips (mounted on a chip carrier) of the multi-chip electronic packages. In embodiments, the seal shim is positioned between a surface of the lid and the chip carrier, during the initial stage of assembly, e.g., adjustment of the pistons of the lid. In embodiments, the seal shim is thicker than the chip shim, used in the assembly process, in order to provide a reduced thermal interface gap between the lid and the chips. In embodiments, the seal shim may have a thickness of about two or more times the thickness of the chip shim. The gap between the lid and chip can be provided with a removable standoff or any temporary structure, to provide a gap larger than the TIM gap during lid setup. 
         [0018]    Advantageously, in embodiments, by using the seal shim of the present invention it is possible to reduce the thermal interface gap between the lid and the respective chips. In this way, it is possible to increase the thermal efficiency of the package and hence increase chip performance. For example, the thermal interface gap can be reduced to about a particle thickness contained in TIM, e.g., 30 microns. More specifically, the thermal interface gap can be reduced to about 30 microns, compared to a gap of about 80 microns in conventional assembly methodologies. Also, using the seal shim results in a uniform repeatable thermal interface gap down to the TIM particle height at multiple chip sites simultaneously. Moreover, the use of the seal shim of the present invention can reduce the TIM pumping (cycling movement), thus providing improved module lid (“hat”) flatness (reduce warpage), lower stresses imposed on the chip carrier, and eliminate the use of a spar plate, in the assembly process. 
         [0019]    It has also been found that by using the seal shims of the present invention, it is possible to, amongst other advantages:
       (i) achieve a 30 micron TIM gap with very reliable thermal data with little or no degradation on package performance or integrity;   (ii) use any TIM material in order to achieve an increased thermal performance by TIM gap down to TIM particle size. For example, the present invention provides improved thermal resistance over existing technology of about 50% by reducing the thermal interface gap;   (iii) create reliable low stress structures with lid and chip carrier mechanically-coupled through multiple chip sites rather than a single peripheral mechanical connection;   (iv) decouple the lid from the chip carrier thereby reducing the distortion of the lid surface and enabling more uniform heatsink interface; and   (v) allow the piston to bottom out on the compressed TIM without the lid contacting the chip carrier surface, thereby reducing stress on the chip carrier within the package.       
 
         [0025]      FIG. 2  shows a beginning process and related structures in accordance with aspects of the invention. More specifically,  FIG. 2  shows a plurality of chips  12  attached to a chip carrier  10 . A lid or hat  14  (hereinafter referred to as a lid) is positioned over the chip carrier  10  such that “pistons”  16  are aligned (registered) with each of the chips  12 , respectively. The pistons  16  can be releasably attached to the lid  14  by many different methods. For example, the pistons  16  can be soldered to the lid  14  by solder, or attached by an epoxy of other adhesive. In embodiments, the pistons  16  can be made from copper, for example, and should have a same or substantially same footprint as the chips  12 . The pistons  16  can be spring loaded into the lid  14  using springs or other resilient mechanisms “S” attached to the lid  14 . 
         [0026]    Still referring to  FIG. 2 , during assembly, a flexible chip shim  15  is placed between the pistons  16  and chips  12  in order to form a thermal interface gap between the pistons  16  and the chips  12 . In embodiments, the chip shim  15  (can be attached by adhesive or mechanically) has a thickness of about 50 microns. A seal shim  20  is located on an underside surface of the lid  14  (and/or a surface of the chip carrier), preferably near an edge thereof and remote from the chips  12 . The seal shim  20  can be stainless steel, brass, plastic or other stable material, for example. The lid  14  can be made from materials such as copper, aluminum, Kovar (Kovar is an iron-nickel-cobalt alloy with a coefficient of thermal expansion similar to that of hard (borosilicate) glass), AlSiC (aluminum silicon carbide), SiSiC (silicon silicon carbide), and AlN (aluminum nitride). 
         [0027]    In embodiments, the seal shim  20  is thicker than the chip shim  15 . For example, the seal shim  20  can be about 50 microns thicker than the chip shim  15 ; although other dimensions are also contemplated by the present invention. For example, the seal shim  20  can have a thickness of about two or more times that of the chip shim  15 . In any of the embodiments, the thickness of the seal shim  20  allows more head room between the lid  14  and the chip carrier  10 , compared to conventional systems. In this way, for example, the use of the seal shim  20  will allow the piston  16  to bottom out on compressed TIM without the lid  14  contacting the surface of the chip carrier  10 , thereby reducing stress on the package, amongst other features and advantages described herein. Advantageously, the method and structure of the present invention is customizable for chips and chip shims of different sizes (e.g., different thickness), and shapes. Alternative methods of removable standoffs can be used instead of seal shims. 
         [0028]    In  FIG. 3 , the lid  14  and/or the chip carrier  10  are moved in close proximity to one another. The pistons  16  should be aligned (registered) with each of the chips  12 , respectively. As shown in  FIG. 3 , the distance between the lid  14  and the chip carrier  10  is constrained by the seal shim  20 , since the seal shim  20  is thicker than the chip shim  15 . In this way, the lid  14  and/or the chip carrier  10  will always remain separated from one another, i.e., the lid  14  will not bottom out on the chip carrier  10 . Once the lid  14  and/or the chip carrier  10  are in close proximity to one another and the pistons  16  and chips  12  are aligned, the pistons  16  are released in order to come into direct contact with the chip shim  15 . As shown in  FIG. 3 , the pistons are moved by a distance ‘x’, compared to the piston position shown in  FIG. 2 . 
         [0029]    As described in greater detail below, the distance between the lid  14  and the chip carrier  10  (resulting from the thickness of the seal shim  20 ) will result in a thermal interface gap between the pistons  16  and the chips  12  of about a particle size of the TIM. The use of the seal shim  20  ensures this precise thermal gap between the pistons  16  and chips  12 , regardless of the variation in height of the chips or the thickness of the chip shim. That is, the method of the present invention will ensure that there is a uniform thermal gap between each piston  16  and chip  12  for TIM to be dispensed therebetween, regardless of chip variation, as the entire lid  14  will be raised above the chip carrier  10 , with the starting point being the thickness of the seal shim  20 , e.g., thereby allowing the piston  16  to move sufficiently downward prior to the lid  14  contacting the chip carrier  14 . This is in contrast to known methods in which a thermal interface gap between the pistons  16  and chips  12  is determined by only a chip shim. The gap using the present invention is based on the TIM particle size. 
         [0030]    The pistons  16  can be released from the lid  14  using many different methods. For example, when the pistons  16  are soldered to the lid  14  by eutectic solder, the entire assembly can be placed in a reflow furnace to bring the solder to a melting point. When the solder reaches its melting point, the pistons  16  will be released and will move into direct contact with the chip shim  15 . At this stage of processing, for example, the pistons  16  can be forced into direct contact with the chip shim  15  by the force of the springs or other resilient mechanisms “S” of a fixture or mechanism attached to the lid  14 . As the assembly cools, the solder will then harden and again fix the pistons  16  to the lid  14 , but now in a lowered position. The position of the pistons  16  are in a final position, with respect to the lid  14 . 
         [0031]    In the case of an adhesive or epoxy or other bonding agent, a chemical solution can be used to release the pistons  16  from the lid  14 . Once the pistons  16  are released, they will move into direct contact with the chip shim  15 . At this stage of processing, for example, the pistons  16  can be forced into direct contact with the chips  12  by the force of the springs or other resilient mechanisms “S” of a fixture or mechanism attached to the lid  14 . In this lowered position, the pistons  16  can then be fixed to the lid  14  by, for example, adhesive or epoxy or other bonding agent (including a solder). The position of the pistons  16  are in a final position, with respect to the lid  14 . 
         [0032]    As shown in  FIG. 4 , the back side of the pistons  16  can be planarized to a flat surface  18  with the surface of the lid  14 . In embodiments, the planarization can be performed by a mechanical planarization process such as, for example, a grinding or cutting process, well known to those of skill in the art. The planarization allows good thermal contact between the lid and an external cooling device such as a heat sink or cold plate. 
         [0033]      FIGS. 5   a  and  5   b  show different methods of attaching the lid  14  to the chip carrier  10 . As shown in each of the embodiments, the seal shim  20  and the chip shim  15  are removed from the package, prior to final assembly. A sealant  22  is placed on either (or both) the lid  14  or the chip carrier  10 , by use of a fluid dispenser needle with a pressure plunger or auger, as shown at reference numeral  23 . For example, in  FIG. 5   a , the sealant  22  is attached to a side of the lid  14 , facing the chip carrier  10 . In  FIG. 5   b , the sealant  22  is attached to a side of the chip carrier  10 , facing the lid  14 . In both  FIGS. 5   a  and  5   b , the sealant  22  can be, for example, silicon, adhesive or epoxy, for example, known to those of skill in the art. In embodiments, the sealant  22  can be applied prior to or concurrently with the application of the TIM  26 . 
         [0034]    In  FIG. 6 , the lid  14  and chip carrier  10  are attached to one another with the sealant  22 . Prior to encapsulating the chips  12  within the multi-chip electronic package  100 , the TIM  26  is dispensed on the chips  12 . The TIM  26  can be any conventional TIM, and will be placed within the gap formed by the combination of the seal shim  20  and chip shim  15  (due to the fact the lid (and pistons) is raised in  FIG. 3 ). As discussed above, the method of the present invention will ensure that there is a uniform thermal interface gap “G” between each piston  16  and chip  12  for TIM to be dispensed therebetween, regardless of chip height and tilt variation, as the entire lid will be raised above the chip carrier  10 . Also, as shown in  FIG. 6 , the use of the seal shim will allow the piston to bottom out on the compressed TIM without the lid  14  contacting the surface of the chip carrier  10 , thereby reducing stress on the package. This will also reduce lid warpage, in addition to increasing the thermal performance of the package. 
         [0035]    In embodiments, the thermal interface gap “G” is about 30 microns or a particle size of the TIM. For example, in embodiments, the thermal interface gap “G” can be customized by the particle size of the TIM. In this way, the smaller sized distance between the lid  14  and the chip  10  will accommodate a smaller amount of TIM which, in turn, increases the thermal efficiency (performance) of the package and hence increase chip performance. This is possible due to the use of the seal shim  20  maintaining a space between the lid  14  and the chip carrier  10  during the initial assembly process. 
         [0036]    Also, as shown in  FIG. 6 , the lid  14  no longer makes contact with a surface of the chip carrier  10 , providing many of the advantages noted above. Thus, the lid  14  and the chip carrier  10  are decoupled, thereby reducing the distortion of the lid surface and enabling more uniform heatsink interface. This also creates a reliable low stress structure with lid and chip carrier mechanically-coupled through multiple chip sites rather to than a single peripheral mechanical connection. This low stress is achieved by separating the lid  14  from the chip carrier  10  with the adhesive  22 , for example. 
         [0037]    In embodiments, the chip carrier and lid can be a non-hermetically sealed module that passes a bubble leak test with epoxy or silicone seal materials. In further embodiments, the chip carrier and lid can be a hermetic sealed module that passes fine line testing. In this embodiment, the chip carrier and lid can be rigidly connected by a solder seal, for example, eutectic Sn63/Pb37. The rigid connection can also be, for example, a metal or glass seal which makes the hermetically sealed module impermeable to the environment. 
         [0038]      FIGS. 7   a  and  7   b  show performance graphs of a multi-chip electronic package in accordance with the present invention vs. a conventional multi-chip electronic package. More specifically,  FIG. 7   a  shows a performance graph of a conventional package of four chips (CP 0 , CP 1 , CP 2 , CP 3 ) and each chip with 8 cores. This performance graph shows that after about 500 cycles, the temperature begins to increase about 5° C. In comparison,  FIG. 7   b  shows a performance graph of a package of eight cores manufactured in accordance with aspects of the present invention, e.g., a decreased thermal interface gap. This performance graph shows that after about 1250 cycles, the temperature still remains about the same. In this way, the package manufactured in accordance with the present invention achieves an increased thermal performance. For example, the present invention provides improved thermal resistance over existing technology of about 50% by reducing the thermal interface gap. 
         [0039]      FIG. 8  shows a graph of lid warpage vs. sealant (seal band) thickness. This graph shows that lid warpage is a function of sealant thickness. For example, less warpage of the lid occurs as the sealant thickness is increased, both in the post cure and post load situations. More specifically, the lid warpage is significantly reduced at a sealant thickness of 200 microns, compared to a sealant thickness of 50 microns. As should be understood, the sealant thickness can be adjusted by using the seal shim of the present invention. 
         [0040]      FIG. 9  shows module TIM movement (“pumping”) comparison graph for pumping during accelerated thermal cycling (ATC), lab power cycling and field-use power cycling. The graph shows bondline thickness (BLT) cycling vs. sealant thickness. More specifically, this graph shows sealant thickness of 30 microns to 200 microns between 0 and 18 micron BLT cycling. As shown in this graph, stress significantly decreases as a function of sealant thickness. More specifically, this graph shows that stress on the package, e.g., carrier decreases as the sealant becomes thicker. As noted above, the sealant thickness can be adjusted by using the seal shim of the present invention. 
         [0041]      FIG. 10  shows stress analysis in the carrier obtained from thermo-mechanical analysis of a conventional multi-chip electronic package and a multi-chip electronic package in accordance with the present invention. As shown, the stresses imposed on the conventional multi-chip electronic package (80 μm TIM Gap, 30 μm sealband) are much greater than that imposed on the multi-chip electronic package of the present invention (30 μm TIM Gap, 80 μm sealband). This is due to the use of the seal shim  20 , which decouples the lid  14  from the chip carrier  10 . More specifically, it is now possible to use a thicker sealant layer between the lid  14  and the chip carrier, by using the seal shim  20 . 
         [0042]    The method as described above is used in the packaging of integrated circuit chips. The integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0043]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0044]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims, if applicable, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principals of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Accordingly, while the invention has been described in terms of embodiments, those of skill in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.

Technology Classification (CPC): 7