Patent Abstract:
A source driver of a display including a timing controller, the source driver and a display panel may include a digital-to-analog converter configured to output an analog value corresponding to a digital data signal supplied from the timing controller of the display panel. An amplification unit is configured to amplify the analog value in a switched capacitor mode to produce an amplified result, and to output the amplified result as a driving signal for driving a unit column line of the display panel. Therefore, since area and power consumption can be further reduced compared with a related source driver, costs can be reduced and Electromagnetic Interference (EMI) can be improved by the reduction of power consumption.

Full Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0134232 (filed on Dec. 26, 2008), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    Hereinafter, the general structure of a source driver included in a display will be described with reference to the accompanying drawings.  FIG. 1  is a circuit diagram of a related source driver which includes an R-string  20 , a switch box  30 , a level shifter  40  and a buffer  50 . For a detailed configuration and operation of the source driver shown in  FIG. 1 , reference may be made to Behzad Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001; and K. Martin and D. A. Johns, Analog Integrated Circuit Design, New York: Wiley, 1997. Accordingly, the detailed description of the detailed operation of the components shown in  FIG. 1  will be omitted. 
         [0003]    In the related source driver shown in  FIG. 1 , the level shifter  40  shifts the levels of data signals D 0  to D N-1  to levels which can drive the high-voltage switch box  30 . This is because the switch box  30  cannot be driven by low level data signals D 0  to D N-1 . A source driver which necessarily requires the left shifter  40  occupies a large area. 
         [0004]    In addition, as resolution is increased, the number of high-voltage transistors included in the switch box  30  is increased by (2N−1) and the number of level shifters  40  is increased by N. Therefore, as the resolution is increased, the size of the source driver is further increased. 
         [0005]    Since a voltage gain of the buffer  50  connected to an output driving voltage V out  is “1”, for example, in order to output the output driving voltage V out  of 9V, the level of the supply voltage VDD 1  should also be increased to about 9V. Also, the signals having the levels increased by the level shifter  40  are supplied to the switch box  30 . For these reasons, the transistors configuring the switch box  30  should be high-voltage transistors. Therefore, the size of the switch box  30 , with the larger sized high-voltage transistors, is also increased. As a result, since the related source driver shown in  FIG. 1  has a complicated configuration, a large area and high power consumption are required. 
       SUMMARY 
       [0006]    Embodiments relate to a source driver of a display with a small area and low power consumption using the amplification principle of a switched capacitor mode. Embodiments relate to a source driver of a display which includes a timing controller, the source driver and a display panel. The source driver may include a digital-to-analog converter configured to output an analog value corresponding to a digital data signal supplied from the timing controller of the display panel. An amplification unit is configured to amplify the analog value in a switched capacitor mode to produce an amplified result, and to output the amplified result as a driving signal for driving a unit column line of the display panel. 
         [0007]    Since the source driver of the display according to embodiments uses an amplifier in a switched capacitor mode mounted at an output side, unlike a related source driver using a unit buffer mounted at the output side, the following effects are obtained. First, since a supply voltage VDD 2  having a level smaller than that of a supply voltage VDD 1  used in the related source driver may be used, a switch box employing high-voltage transistors in the related art can employ low-voltage transistors and thus an area thereof can be reduced. Second, since a level shifter is not required unlike the related source driver using the level shifter, it is possible to further reduce power consumption and area. Third, since an operational amplifier is provided on the next stage of two Metal-Insulator-Metal (MIM) capacitors in an amplification unit in a switched capacitor mode, it is possible to further reduce the area of the source driver. 
         [0008]    Therefore, since an area and power consumption can be further reduced compared with the related source driver as described above, cost can be reduced and Electromagnetic Interference (EMI) can be improved by the reduction of power consumption. 
     
    
     
       DRAWINGS 
         [0009]      FIG. 1  is a circuit diagram of a general source driver. 
           [0010]    Example  FIG. 2  is a circuit diagram of a source driver according to embodiments. 
           [0011]    Example  FIGS. 3A and 3B  are views showing a state in which first to fifth switches shown in example  FIG. 2  are turned on/off in response to a switching signal and an inverted switching signal. 
       
    
    
     DESCRIPTION 
       [0012]    Hereinafter, the schematic configuration and the operation of a display will be described prior to the description of embodiments. In general, the display includes a timing controller, a plurality of source drivers (or column driving circuits) and gate drivers (or row driving circuits), and a display panel. The timing controller controls the gate drivers and the source drivers, and the gate drivers and the source drivers drive the display panel. The display panel displays an image according to scanning signals R 1  to R n  supplied from the gate drivers and data signals C 1  to C m  supplied from the source drivers. The display may include various display panels, which can be used between the timing controller and a display driving integrated circuit, such as a Liquid Crystal Display (LCD) panel (for example a Thin-Film Transistor (TFT) LCD, a Super Twisted Nematic (STN)-LCD), a Ferroelectric Liquid Crystal Display (FLCD), a Plasma Display Panel (PDP), an Organic Luminescence Electro Display (OLED) panel, or a Field Emission Display (FED). The timing controller can transmit various control signals for controlling the source driver and data to the source driver. 
         [0013]    Hereinafter, a source driver of a display according to embodiments will be described with reference to the accompanying drawings. Example  FIG. 2  is a circuit diagram of a source driver according to embodiments. The source driver shown in example  FIG. 2  may include a Digital-to-Analog Converter (DAC)  60  and an amplification unit  70 . The DAC  60  may generate an analog value corresponding to N digital data signals D 0  to DN−1 supplied from the timing controller, and output the generated analog value to the amplification unit  70 . 
         [0014]    The DAC  60  may be implemented by a voltage divider  62  and a decoder  64 . The voltage divider  62  divides a supply voltage VDD 2  into n voltages having different levels and outputs the divided n voltages having the different levels to the decoder  64 . The voltage divider  62  may be implemented by n string resistors R 0  to R n-1  connected between the supply voltage VDD 2  and ground in series. 
         [0015]    The decoder  64  may decode the n voltages having the different levels supplied from the voltage divider  62  in response to the digital data signals D 0  to D N-1  and output the decoded result to the amplification unit  70  as an analog value. The decoder  64  may be implemented by the switch box  64  having a plurality of switches which are switched to convert the n voltages having the different levels into the analog value in response to the digital data signals D 0  to D N-1 . The switches of the switch box  64  may be implemented by MOS transistors as shown in example  FIG. 2 . According to embodiments, the MOS transistors may be low-voltage transistors unlike high-voltage transistors included in the switch box  30  shown in  FIG. 1 . For example, the MOS transistors may be NMOS, PMOS or CMOS transistors. 
         [0016]    Meanwhile, the amplification unit  70  amplifies the analog value (for example, analog voltage) supplied from the DAC  60  in a switched capacitor mode and outputs the amplified result as a driving signal V out  for driving a unit column line of the display panel. In general, amplifiers in a switched capacitor mode have capacitors. Accordingly, the analog voltage output from the DAC  60  may be amplified to a desired value and output as the output voltage V out  by adjusting the values of the capacitors included in the amplification unit  70 . 
         [0017]    The components of the amplification unit  70  shown in example  FIG. 2  are only exemplary and embodiments are not limited to such a circuit configuration. For example, if the analog voltage is amplified by the capacitor values so as to output the output driving voltage V out , the circuit may have an alternate configuration. 
         [0018]    According to embodiments, the amplification unit  70  shown in example  FIG. 2  includes first to fifth switches  72  to  80 , first and second capacitors C 1  and C 2 , and an operational amplifier  90 . The configuration of the components included in the amplification unit  70  will now be described. 
         [0019]    The operational amplifier  90  may have a negative input terminal (−) connected to one side of each of the first and second capacitors C 1  and C 2 , an output terminal connected to the driving signal V out , and a positive input terminal (+) connected to ground. 
         [0020]    The first capacitor C 1  may be connected between the negative input terminal (i.e., the inverting input denoted by “−”) of the operational amplifier  90  and the first switch  72 . The second capacitor C 2  may be connected between the negative input terminal (−) of the operational amplifier  90  and the second switch  74 . 
         [0021]    The first switch  72  may be connected to the first capacitor C 1  and the output terminal of the DAC  60 , and may be switched in response to a switching signal S. The second switch  74  may be connected between the second capacitor C 2  and the output terminal of the DAC  60 , and may be switched in response to the switching signal S. The third switch  76  may be connected between a contact point between the second switch  74  and the second capacitor C 2  and ground and may be switched in response to an inverted switching signal SB. The fourth switch  78  may be connected between a contact point between the first switch  72  and the first capacitor C 1  and the output terminal of the operational amplifier  90  and may be switched in response to the inverted switching signal SB. The fifth switch  80  may be connected between the negative input terminal (−) and the output terminal of the operational amplifier  90  and may be switched in response to the switching signal S. 
         [0022]    The principle of operation of the amplification unit  70  having the above-described configuration will now be described. Example  FIGS. 3A and 3B  are views showing a state in which the first to fifth switches  72  to  80  shown in example  FIG. 2  are turned on/off in response to the switching signal S and the inverted switching signal SB. 
         [0023]    First, if the switching signal S is at a “High” logic level and the inverted switching signal SB is at a “Low” logic level, the connection structure of the amplification unit  70  shown in example  FIG. 2  is obtained as shown in example  FIG. 3A . If the switching signal S is at a “Low” logic level and the inverted switching signal SB is at a “High” logic level, the connection structure of the amplification unit  70  shown in example  FIG. 2  shown in example  FIG. 3B  is obtained. 
         [0024]    A variation in quantity Q of electric charge charged in the capacitors C 1  and C 2  in the connection structure shown in example  FIG. 3A  and a variation AQ in quantity Q of electric charge stored in the capacitors C 1  and C 2  in the connection structure shown in example  FIG. 3B  are equal as shown in Equation 1. This is based on the law of conservation of charge. 
         [0000]      ΔQ1=ΔQ2  Equation 1 
         [0025]    Equation 1 is expressed by Equation 2. 
         [0000]        Q 1( S=L )− Q 1( S=H )= Q 2( S=L )− Q 2( S=H )  Equation 2 
         [0026]    where, S=L indicates that the switching signal is at the “Low” logic level and S=H indicates that the switching signal is at the “High” logic level. Accordingly, as shown in Equation 3, it can be seen that the analog value V in  output from the DAC  60  is amplified so as to generate the output voltage V out  which is the driving signal. 
         [0000]    
       
         
           
             
               
                 
                   
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         [0027]    It can be seen from Equation 3 that a voltage gain (V out /V in ) can be adjusted by adjusting the values of the capacitors C 1  and C 2 . 
         [0028]    In the source driver according to embodiments, the amplifier  70  of the switched capacitor mode may be provided at the output side of the source driver, instead of a unit buffer  50 . Therefore, a supply voltage VDD 2  having a level smaller than that of the supply voltage VDD 1  used for driving the R-string  20  in the related source driver shown in  FIG. 1  may be used. For example, the general supply voltage VDD 1  is 9 volts, but the supply voltage VDD 2  shown in  FIG. 2  need only be 3 volts. 
         [0029]    In addition, the transistors included in the switching box  30  shown in  FIG. 1  are high-voltage transistors, but the transistors for implementing the switching box  64  shown in example  FIG. 2  do not need to be high-voltage transistors and, instead, the low-voltage transistors are sufficient. Since the size of the low-voltage transistor is smaller than that of the high-voltage transistor, the switch box  64  of the source driver shown in example  FIG. 2  according to embodiments may be smaller than that of the switch box  30  shown in  FIG. 1 . 
         [0030]    In addition, the related source driver shown in  FIG. 1  uses the level shifter  40 , but the source driver according to embodiments does not require the level shifter  40 . Accordingly, it is possible to further reduce the size and power consumption of the source driver. In addition, since the operational amplifier  90  is provided on the next stage of the two Metal-Insulator-Metal (MIM) capacitors C 1  and C 2 , it is possible to further reduce the area of the source driver. 
         [0031]    It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.

Technology Classification (CPC): 6