Patent Abstract:
Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad therefrom. An ESD event detector is provided for detecting an ESD event on the pad. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.

Full Description:
TECHNICAL FIELD OF THE INVENTION  
         [0001]    The present invention pertains in general to protection devices and, more particularly, to protection devices for protecting integrated circuit devices from electrical transients, including electrostatic discharge (ESD) events.  
         BACKGROUND OF THE INVENTION  
         [0002]    Integrated circuit devices have been subject to ever increasing susceptibility to damage from applications of excessive voltages, for example, by electrostatic discharge (ESD) events. This susceptibility is due, in large part, to ever decreasing gate oxide thicknesses which have resulted as very large scale integration (VLSI) circuit geometries continued to shrink. In particular, during an ESD event, charge is transferred between one or more pins of the integrated circuit to another conducting object in a time period that is typically less than one microsecond. This charge transfer can generate voltages that are large enough to break down insulating film (e.g., gate oxides) on the device, or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting.  
           [0003]    There have been many attempts made in the prior art to protect semiconductor devices, with particular attention to the problem of protecting field effect transistor devices from such ESD events. In the early days of MOS technology, a simple clamp was utilized such that a high voltage or ESD event on a pad or input pin associated with the integrated circuit resulted in “clamping” the voltage to ground with use of simple clipping diodes. Further, structures were incorporated in the circuitry associated with one or more of the input/output (IO) circuits that utilized reverse breakdown semiconductor junctions that would become conductive at high voltages. However, these devices sometimes prove to be insufficient to completely absorb the energy due to the conductivity therethrough or the speed thereof.  
           [0004]    Recent ESD devices utilize clamping transistors that are turned on in the event of an ESD event. The control circuitry for this transistor typically includes a resistor and capacitor connected in series between the power supply and ground. Whenever an ESD event occurred that either pulled the pad below ground or above the supply terminal, the pn junction associated with a drive transistor, for example, on the pad would be forward biased and cause the ESD transistor to turn on and clamp the output across the output drive transistors to prevent damage thereto. However, the circuitry must be added to each I/O circuit and corresponding pad.  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention disclosed and claimed herein, in one aspect thereof, comprises an electrostatic discharge (ESD) protection device for protecting an integrated circuit with associated terminals, each having a functional relationship to the operation of the integrated circuit, the integrated circuit having an output driver with a p-channel transistor and n-transistor pair connected between one of the terminals configured as a power supply terminal and one of the terminals configured as a ground terminal for driving an associated one of the terminals configured as an input/output pad. An ESD event detector is provided for detecting an ESD event on any of the terminals. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:  
         [0007]    [0007]FIG. 1 illustrates a prior art non overlap logic generator for driving a pair of output drive transistors and an ESD protection circuit;  
         [0008]    [0008]FIGS. 2 and 3 illustrate details of the prior art configuration of FIG. 1;  
         [0009]    [0009]FIG. 4 illustrates a general diagrammatic view of the ESD protection device of the present disclosure; and  
         [0010]    [0010]FIG. 5 illustrates a more detailed logic diagram of the ESD protection device in association with the output drive circuitry of the present disclosure.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]    Referring now to FIG. 1, there is illustrated a logic diagram for a prior art ESD protection device. A pad  102  is provided that provides an input/output (I/O) function for the integrated circuit. It should be understood that there are many pads typically associated with an integrated circuit, only one of which is illustrated in the embodiment of FIG. 1. The pad  102  is typically driven by a driver circuit for driving a node  104  connected to pad  102 . The driver circuit consists of an n-channel transistor  106  operable to drive the node  104  to ground, transistor  106  having the source-drain path thereof connected between node  104  and ground. The driver circuit is also comprised of a p-channel transistor  108  for pulling the node  104  up to Vdd, this allowing current to be driven to the node  104  through the source-drain path of transistor  108  connected between Vdd and node  104 .  
         [0012]    A non-overlap logic generator  110  is provided for driving the gates of transistors  106  and  108 . The drive signal for the gate of transistor  106  is referred to as an “ng” drive signal and the drive for the gate of transistor  108  is referred to as a “pg” drive signal. Generator  110  receives two inputs, an “n” drive input and an “pb” drive input. The generator is operable to allow for tri-stating of the driver such that the gate of transistor  108  will remain high and the gate of transistor  106  will remain low such that there is no conduction there through in the tri-state configuration.  
         [0013]    The generator  110  is comprised of a NAND gate  112  having one input thereof connected to the “n” input signal the other input thereof connected to the “pg” output node on the gate of transistor  108 . A NOR gate  114  has one input thereof connected to the “pb” input signal and the other input thereof connected to the “ng” output signal that drives transistor  106 . The output of NOR gate  114  is input to an invertor  116 , the output thereof connected to the “pg” drive signal to transistor  108 . The output of NAND gate  112  is connected to the input of an invertor  118 , the output thereof connected to the “ng” output signal that drives transistor  106 .  
         [0014]    In operation, when the state of the pad  102  is low, and “pb” goes low, pad  102  will remain low until the state of “n” goes low. When “n” goes low, the output of NAND gate  112  goes high and the output of invertor  118  goes low, turning off transistor  106  and driving pad  102  high, since NOR gate  114  will drive the output of inverter  116  low and turn on transistor  108 . If “n” then goes high, and then “pb” goes high, then the output of inverter  16  will be driven high, turning off transistor  108  and driving the output of NAND gate low and the output of inverter  118  high, turning on transistor  106 .  
         [0015]    For the purpose of addressing ESD events, the transistors  106  and  108  must be protected in the event that the pad  102  is subjected to a high-going spike or a low-going spike as well as all internal transistors connected to node  104  and the supply nodes. Illustrated in FIG. 1 in phantom is an intrinsic diode  120  having the anode connected to ground and the cathode thereofconnected to the node  104 , and a phantom diode  122  having the anode thereof connected to node  104  and the cathode thereofconnected to V dd . The diodes  120  and  122  are an intrinsic part of the transistors  106  and  108 , as is well know in the art. Further, the transistors  106  and  108  can be fabricated to accentuate or provide an enhanced ESD pn junction across the transistor. In general, the diode results from the p-substrate for the n-channel transistor  106 , for example, that is connected to ground wherein the pn junction exists between the source and drain in transistor  106  (or transistor  108 ) and the p-substrate. For a p-channel device, the diode is between the p-drain and the n-well connected to V dd .  
         [0016]    With reference to FIGS. 2 and 3, there is illustrated a detail of a high going spike and a low going spike, respectively. When the pad  102  is pulled high in the presence of an ESD event, this will cause diode  122  to become forward biased and conduct. If, on the other hand, the pad  102  were pulled low below ground, this would cause diode  120  to conduct. A clamp n-channel transistor  124  is provided with the source/drain path thereof connected between the Vdd and ground and the gate thereof connected to a node  126 . Node  126  is connected to one side of a resistor  128 , the other side thereof connected to ground, node  126  also connected to one plate of a capacitor  130 , the other side thereof connected to V dd . When the pad  102  goes high, diode  122  will pull the top plate of capacitor  130  at the V dd  terminal high, thus pulling node  126  high and turning transistor  124  on. When pad  102  goes low, diode  120  will pull the ground node low, with node  126  remaining high due to the fact that the capacitor  130  is still connected on the top plate thereofto V dd . This will cause transistor  124  to conduct and “clamp” V dd  and ground, thus protecting transistors  106  and  108 . (Note that a p-channel transistor could have been utilized as the clamp transistor by merely reversing the capacitor  130  and resistor  128  of FIG. 1).  
         [0017]    Referring now to FIG. 4, there is illustrated an overall logic diagram of the ESD protection circuit of the present disclosure. The output is provided on a node  404  that drives an output pad  406 . Two drive transistors, a p-channel transistor  408  and an n-channel transistor  410  are provided with the source-drain path of the p-channel transistor  408  connected between V dd  and node  404 , and the source-drain path of transistor  410  connected between node  404  and ground. The gate of transistor  408  and the gate of transistor  410  are driven by a non-overlap logic generator, as was described hereinabove with reference to FIG. 1. The input signals to the generator are comprised of the primary “n” drive logic signal and the “pb” drive signal. The “n” signal is input to one input of a two-input NAND gate  412 , the other input thereof connected to the gate of transistor  408 . The output of the NAND gate  412  is connected to the input of a bypass circuit  414 , the output thereof connected to the input of an invertor  416 , the output of inverter  416  driving the gate of transistor  410 . The “pb” signal is input to one input of a two-input NOR gate  418 , the other input thereof connected to the output of invertor  416 . The output of the NOR gate  418  is connected to the input of a bypass circuit  420 , the output thereof connected to the input of an invertor  422 , the output of inverter  422  connected to the gate of transistor  408 . When the bypass circuits  414  and  420  are operating to bypass the logic function associated therewith, the generator of FIG. 4 will operate identical to the generator  110  of FIG. 1.  
         [0018]    An ESD capacitor  430  has a top plate thereof connected to V dd  and a bottom plate thereof connected to an ESD control node  432 . An ESD resistor  434  is connected between node  432  and ground. The ESD control node  432  is connected to a control input on both of the bypass circuits  420  and  414 .  
         [0019]    As noted herein above, each of the transistors  408  and  410  has associated therewith an intrinsic diode (not shown), such that raising of the pad  406  high through an ESD event will result in the diode pn junction associated with transistor  408  being forward biased and pulling the V dd  terminal high relative to ground. This will cause node  432  to be pulled up, which will cause bypass circuit  414  to output a low signal regardless of the state of any of the other logic circuitry and drive a logic high on the output of invertor  416  turning on transistor  410 , and bypass circuit  420  will also output a logic “high” state to drive the output of invertor  422  low, turning on transistor  408 , such that transistor  410  and  408  clamp V dd  to ground. The bypass circuits  414  and  420  are pushed “forward” of the controlling logic circuitry embodied in the NOR gate  418  and the NAND gate  412 . This bypass circuits  414  and  420  therefore utilizes the source/drain path transistors  408  and  410  in lieu of a separate n-channel transistor clamp for clamping V dd  to ground.  
         [0020]    Referring now to FIG. 5, there is illustrated a detailed logic diagram of a circuit FIG. 4 and the bypass circuitry  414  and  420 . The pb signal is input to one input of a two input OR gate  502 , the other input thereof connected to the gate of transistor  410 . The output of OR gate  502  is connected to one input of the two input NAND gate  504 , the other input thereof connected to a node  506 . Node  506  is connected to the output of an invertor  508 , the input thereof connected to the ESD control node  432 . The output of NAND gate  504  is connected to the input of invertor  422  in order to drive the gate of transistor  408 .  
         [0021]    The “n” input signal is input to one input of a two-input AND gate  510 , the other input thereof connected to the output of invertor  422 . The output of AND gate  510  is input to one input of a two-input NOR gate  512 , the output thereof connected to the input of the invertor  416  and the other input of NOR gate  512  is connected to the output of an invertor  518 , the input of invertor  518  connected to node  506 . It should be noted that the other input of NOR gate  512  not connected to the output of AND gate  510  could be connected directly to node  532 . By utilizing the invertor  518 , some “clock bouncing” can be ameliorated.  
         [0022]    In operation, when “n” is at a logic “low,” the output of AND gate  510  is low and, when no ESD event is present, the output of invertor  518  will be low due to node  432  being low. This will result in the output of NOR gate  512  being high and the output of invertor  416  being low, thus turning off transistor  410 . This will also place a logic “low” on the input to OR gate  502 . Shortly thereafter, “pb” is taken low, which will result in the output of OR gate  502  going low and the output of AND gate  504  being high and the output of invertor  422  being low, turning on transistor  408 .  
         [0023]    For the opposite logic state, “pb” goes high, resulting in a logic high to the input of NAND gate  504 . The other input to NAND gate  504 , during a non-ESD event will be high, such that the output of NAND gate  504  is low and the output of invertor  422  is high, turning off transistor  408 . “n” goes high, raising the output of AND gate  510  high and causing the output of NOR gate  512  to go low and the output of invertor  416  to go high, turning on transistor  410 . Transistor  408  will therefore be turned off and transistor  410  turned on.  
         [0024]    During a high going ESD event, node  432  will be “high” due to the intrinsic pn junction in transistor  408  being forward biased and current being driven to the V dd  terminal. This will result in node  506  being pulled low, which results in the output of NAND gate  504  going high and the output of invertor  422  going low and turning on transistor  408 . Similarly, the output of invertor  518  will be at a logic “high” resulting in the output of NOR gate  512  going low and the output of invertor  416  going high, turning on transistor  410 . Therefore, for a high going ESD event, transistors  408  and  410  will be turned on clamping the V dd  to ground.  
         [0025]    In the opposite condition, wherein the pad is subjected to a negative-going ESD event, ground will be pulled low resulting in node  432  being at a “high” voltage level to cause node  506  to go low. This will also result in transistors  408  and  410  being turned on. It is noted that the logic associated with the gates  502  and  510 , which form part of the non-overlap generator are not a portion of the control logic that controls transistors  408  and  410  being turned on during the ESD event. As such, the gates  504  and  512  associated with the bypass operation are disposed “forward” of the normally operating gate logic. In general, the gates  502  and  504  are referred to as an OR-NAND configuration and the gates  510  and  512  are referred to as an AND-NOR combination.  
         [0026]    Although the preferred embodiment has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Classification (CPC): 7