Patent Abstract:
There is provided a semiconductor package configured for externally controlled power management. Instead of integrating voltage regulation on-chip as done conventionally, power regulation is moved externally to the PCB level, providing numerous package advantages including size, simplicity, power efficiency, integration flexibility, and thermal dissipation. In particular, the use of flip-chip package configurations provides ready access to power supply bumps, which also allows the use of a universal receiving PCB and power supply through simple reconfiguring of voltage traces. As a result, flexible power management can be implemented, and portions of semiconductor packages may be managed for performance or thermal considerations, which may be of particular use for applications such as multi-core processors.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to semiconductor packages, and more specifically to power management of semiconductor packages. 
     2. Background Art 
     Today, system-on-chip (SOC) process geometries are shrinking further into deep sub-micron regions to provide greater logic capacity for higher performance. However, these high-performance SOCs also bring corresponding demands for power consumption. In order to adequately meet these power demands, increasingly costly package designs and cooling configurations have been developed. 
     Efficient SOC designs in a compact form factor is highly desirable, particularly for heavily loaded data center applications where many SOCs may run in parallel, or in mobile battery-powered applications where power consumption and physical footprint must be carefully optimized. Reduction of fabrication costs and increases in yield through simplified package design may also comprise important considerations. 
     In particular, it is desirable to be able to turn off unused logic blocks, such as processor cores, to reduce power consumption and thermal dissipation demands. Conventionally, this has been done by using on-chip power transistors to switch power, or on-chip regulators for both switching and voltage adjustments. However, efficiency demands often require a large portion of the die to be dedicated to power devices, and power leakage remains an issue even in off-states. Thus, the addition of these power elements to a package lowers efficiency and increases cost, complexity, and form factor. 
     Accordingly, there is a need in the art for a package configuration that can effectively address the aforementioned difficulty of supplying power for high performance SOCs in a simple, efficient, cost effective, and space saving manner. 
     SUMMARY OF THE INVENTION 
     There is provided a semiconductor package configured for externally controlled power management, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein: 
         FIG. 1  shows a diagram of an exemplary semiconductor package configured for conventional on-die power management; 
         FIG. 2A  shows a top plan view of an exemplary semiconductor package configured for externally controlled power management, according to one embodiment of the present invention; 
         FIG. 2B  shows a cross sectional view of an exemplary semiconductor package configured for externally controlled power management, according to one embodiment of the present invention; and 
         FIG. 3  is a flowchart presenting a method for a power supply of a printed circuit board (PCB) to provide power management for a semiconductor device mounted on said PCB, according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Although the invention is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art. The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention to which use the principles of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be borne in mind that, unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. 
       FIG. 1  shows a diagram of an exemplary semiconductor package configured for conventional on-die power management. Diagram  100  of  FIG. 1  includes semiconductor device  110 , which includes circuit blocks  120   a - 120 , switches  125   a - 125   b , and power devices  130   a - 130   b . Circuit blocks  120   a - 120   b  may comprise, for example, processing cores of a multi-core processor. During idle periods when there is only light load remaining in a processing workload queue, it may be desirable to turn off voltage to one or more cores. Thus, power devices  130   a - 130   b  may utilize switches  125   a - 125   b  to control on-chip voltage for circuit blocks  120   a - 120   b . Alternatively, it may be desirable to adjust voltage through the use of voltage regulators. For example, to optimize performance for single-core processes, voltage may be increased for a single circuit block. To optimize for power savings, voltage may be decreased for one or more circuit blocks. These voltage adjustment preferences may for example be encapsulated in a power management policy embedded in the package or provided externally through software control. For example, a power management policy may be based on thermal management using internal thermal sensors to determine an appropriate voltage and operating frequency. 
     However, as discussed above, the use of a conventional on-die power supply as shown in  FIG. 1  has several disadvantages. The area of semiconductor device  110  must be increased to accommodate switches  125   a - 125   b  and power devices  130   a - 130   b , resulting in a larger form factor and reduced yields. Even if switches  125   a - 125   b  are opened to turn off power to circuit blocks, power leakage still occurs, resulting in lower power efficiency. The additional complexity of integrating on-chip power regulation for SOC packages results in increased design, fabrication, and testing costs. 
     Thus, moving to  FIG. 2A ,  FIG. 2A  shows a top plan view of an exemplary semiconductor package configured for externally controlled power management, according to one embodiment of the present invention. Diagram  200  of  FIG. 2A  includes semiconductor device  210 . Semiconductor device  210  is configured as a flip-chip, with circuit blocks  220   a - 220   b  each including a four by four grid of solder bumps. A four by four grid is shown for simplicity, and alternative embodiments may include different arrangements of solder bumps, including greater or fewer bumps. As shown in diagram  200 , a pair of power and ground bumps are indicated by VDD bumps  231   a - 213   b  and VSS bumps  232   a - 232   b . When connected to an external voltage supply, these power bumps may provide operating power for each respective circuit block. For simplicity, each circuit block only has a single pair of power bumps indicated, but alternative embodiments may include several solder bumps reserved for receiving power. 
     Moving to  FIG. 2B ,  FIG. 2B  shows a cross sectional view of an exemplary semiconductor package configured for externally controlled power management, according to one embodiment of the present invention. Semiconductor device  210  is flipped and soldered to matching pads on PCB  240 . In addition, power device  230 , which may comprise a voltage regulated switching power supply, is integrated onto PCB  240 . PCB  240  may also include traces to connect VDD bumps  231   a - 231   b  and VSS bumps  232   a - 232   b  to power device  230 . 
     In this manner, power device  230  can directly control the supply voltage to semiconductor device  210 . Thus, circuit block power management can be easily implemented by increasing, decreasing, or cutting off voltage to corresponding power bumps on semiconductor device  210 . Moreover, power device  230  can flexibly adapt to different flip-chip solder bump configurations of semiconductor device  210  by simply reconfiguring the traces used for voltage management. In this manner, a common universal PCB and power supply configuration can be used for a wide variety of applications. Additionally, since power regulation functions are consolidated to the board-mounted power device  230  rather than on-chip, the disadvantages of on-chip power regulation discussed above in conjunction with  FIG. 1  are avoided. In particular, the inefficient voltage leakage resulting from on-chip power circuitry can be greatly reduced or eliminated. The physical separation of power device  230  from semiconductor device  210  also spreads out the generation of heat, allowing for more efficient thermal dissipation and simplified cooling solutions. Thus, compared to conventional semiconductor package designs using on-chip power management, the semiconductor package of the present invention is reduced in size, complexity, and cost with increased efficiency and flexibility for PCB integration. 
       FIG. 3  is a flowchart presenting a method for a power supply of a printed circuit board (PCB) to provide power management for a semiconductor device mounted on said PCB, according to one embodiment of the present invention. Certain details and features have been left out of flowchart  300  of  FIG. 3  that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more sub-steps or may involve specialized equipment, as known in the art. While steps  310  through  330  shown in flowchart  300  are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart  300 . 
     Referring to step  310  of flowchart  300  in  FIG. 3  and diagram  200  of  FIGS. 2A and 2B , step  310  of flowchart  300  comprises power device  230  determining a voltage to apply to circuit block  220   a  of semiconductor device  210  mounted on PCB  240 . As previously described, voltage may be determined based on power management policy, processing workload, or other factors. Voltage may also be set to zero to completely turn off particular unneeded circuit blocks, reducing power consumption. 
     Referring to step  320  of flowchart  300  in  FIG. 3  and diagram  200  of  FIGS. 2A and 2B , step  320  of flowchart  300  comprises power device  230  establishing electrical paths to VDD bump  231   a  and VSS bump  232   a  of circuit block  220   a . As shown in  FIG. 2B , traces are available on PCB  240  to connect power device  230  to the desired bumps on semiconductor device  210 . In addition, as previously described, power device  230  may be able to flexibly adapt to different flip-chip solder bump configurations of semiconductor device  210  by simply reconfiguring the traces used. In this manner, semiconductor devices with different solder bump configurations can be supported on a single universal PCB and power supply platform. 
     Referring to step  330  of flowchart  300  in  FIG. 3  and diagram  200  of  FIGS. 2A and 2B , step  320  of flowchart  300  comprises power device  230  supplying the voltage determined in step  310  using the electrical paths established in step  320  to power a plurality of logic components of circuit block  220   a . As previously discussed, circuit block  220   a  may, for example, comprise a core of a multi-core processor. Thus, step  330  may provide power for the core to perform data processing, calculations, or other logic duties. 
     Steps  310 - 330  may also be repeated to adjust other circuit blocks of semiconductor device  210 , such as circuit block  220   b . In this manner, finely tuned semiconductor package power management is possible without requiring on-die power management devices, allowing the use of simplified semiconductor packages with reduced size and cost but with increased efficiency and flexibility for PCB integration. 
     From the above description of the embodiments of the present invention, it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the present invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Technology Classification (CPC): 7