Patent Abstract:
A processor frequency adjustment circuit for adjusting a frequency of a processor includes a voltage converting module, a first reference voltage generating module, a clock chip, a voltage comparing module. The voltage converting module converts a pulse voltage into a constant voltage. The first reference voltage generating module generates a first reference voltage. The voltage comparing module is connected with the voltage converting module, the first reference voltage generating module, and the clock chip to compare the constant voltage with the first reference voltage, and generates a first voltage level signal to a first terminal of the clock chip; the clock chip adjusts the frequency of the processor in response to obtaining the first voltage level signal.

Full Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to circuitry, and particularly, to a processor frequency adjustment circuit. 
     2. Description of Related Art 
     Processor frequency specifies the operation speed of the processor for a computer, and most processors are set to run at a default frequency. The processor frequency can be manually adjusted to increase the computing power of the processor. However, manual adjustment is troublesome and cannot be done in real time to correspond to the workload of the computer. 
     Therefore, what is needed is a processor frequency adjustment circuit that overcomes the above-mentioned problem. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of a processor frequency adjustment circuit. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
         FIG. 1  is a schematic diagram of a processor frequency adjustment circuit in accordance with an exemplary embodiment. 
         FIG. 2  is a circuit diagram of the processor frequency adjustment circuit of  FIG. 1 , in accordance with an exemplary embodiment 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , a processor frequency adjustment circuit  100  includes a voltage converting module  50 , a first voltage generating module  40 , a second voltage generating module  20 , a voltage comparing module  30 , and a clock chip  70 . The processor frequency adjustment circuit  100  can adjust the processor frequency of a computer using a read/write of a hard drive as an indicator for a workload of the computer. 
     A Southbridge chipset of the computer can output a pulse voltage (Vs) changing in correspondence to the read/write of the hard drive, and the voltage converting module  50  converts the pulse voltage into a constant voltage (Vd). The first voltage generating module  40  and the second voltage generating module  20  generate a first reference voltage (Vref 1 ) and a second reference voltage (Vref 2 ), respectively. In the present embodiment, the first reference voltage is set to be higher than the second reference voltage. The first reference voltage, the second reference voltage, and the constant voltage are applied to the voltage comparing module  30 . The voltage comparing module  30  compares the first reference voltage, the second reference voltage, and the constant voltage to determine the workload of the hard drive, and transmits a low voltage level or a high voltage level to a first terminal CKL 1  and a second terminal CKL 2  of the clock chip  70 . If Vd&gt;Vref 1 , the hard drive is determined to be idle, and the clock chip  70  controls the processor to work at a default frequency; if Vref 2 &lt;Vd&lt;Vref 1 , the hard drive is determined to be at low workload, and the clock chip  70  controls the processor to work at a high frequency, higher than the default frequency; if Vd&lt;Vref 2 , the hard drive is determined to be at high workload, and the clock chip  70  controls the processor to work at the highest frequency. 
     Referring to  FIG. 2 , the voltage converting module  50  includes a resistor R 1  and a capacitor C, and the pulse voltage is applied through the resistor R 1  and is grounded through the capacitor C. The constant voltage is formed between the resistor R 1  and the capacitor, and is output from the voltage converting module  50  to the voltage comparing module  30 . The first voltage generating module  40  includes a resistor R 2  and a resistor R 3  connected between a power supply pin VCC and ground. The first reference voltage is formed between the resistor R 2  and the resistor R 3 , and can be adjusted by changing the resistances of the resistor R 2  and the resistor R 3 . The first reference voltage is output from the first voltage generating module  40  to the voltage comparing module  30 . 
     The voltage comparing module  30  includes an operational amplifier U 1 , a switch T 1 , and a switch T 3 . The constant voltage and the first reference voltage are connected with an inverting input and a non-inverting input of the operational amplifier U 1 , respectively, and the output of the operational amplifier U 1  is connected with the switch T 1 . In the present embodiment, the switch T 1  is a nMOSFET, and an gate of the switch T 1  is connected with the output of the operational amplifier U 1  through a resistor R 6 ; a source of the switch T 1  is grounded; an drain of the switch T 1  is connected with VCC through a resistor R 8 , and a node between the drain and the resistor R 8  is further connected with a switch T 3 . In the present embodiment, the switch T 3  is an npn transistor, and a base of the switch T 3  is connected to the node between the drain of the switch T 1  and the resistor R 8 ; a collector of the switch T 3  is connected with VCC through a resistor R 10 ; an emitter of the switch T 3  is grounded. A node between the collector of the switch T 3  and the resistor R 10  is further connected to the first terminal CKL 1  of the clock chip  70 . 
     The second voltage generating module  20  includes a resistor R 4  and a resistor R 5  with an identical layout as the first voltage generating module  40  to determining the second reference voltage, and the second reference voltage is output from the second voltage generating module  20  to the voltage comparing module  30 . The voltage comparing module  30  further includes an operational amplifier U 2 , a resistor R 7 , a switch T 2 , a resistor R 9 , a switch T 4 , and a resistor R 11  with an identical layout as the operational amplifier U 1 , the resistor R 6 , the switch T 1 , the resistor R 8 , the switch T 3 , and the resistor R 10 . A node between a collector of the switch T 4  and the resistor R 11  is connected to the second terminal CKL 2  of the clock chip  70 . 
     When the hard drive is idle, the constant voltage converted by the voltage converting module  50  is higher than the first reference voltage and the second reference voltage, and thus in the operational amplifier U 1 , the inverting input is higher than the non-inverting input, and a low voltage level is output to the gate of the switch T 1  to open the switch T 1 . The base of the switch T 3  is connected to VCC when the switch T 1  is open, and the switch T 3  is closed. When the switch T 3  is closed, the first terminal CKL 1  of the clock chip  70  is grounded and acquires a low voltage level. As the constant voltage is also higher than the second reference voltage, the second terminal CKL 2  acquires a low voltage level as well as the first terminal CKL 1 , and the clock chip  70  allows the processor to work at a default frequency. 
     When the hard drive is at low workload, the constant voltage converted from the voltage converting module  50  is lower than the first reference voltage and higher than the second reference voltage, and thus in the operational amplifier U 1 , the inverting input is lower than the non-inverting input, and a high voltage level is output to the gate of the switch T 1  to close the switch T 1 . The base of the switch T 3  is grounded when the switch T 1  is closed, and the switch T 3  is opened. When the switch T 3  is opened, the first terminal CKL 1  of the clock chip  70  is connected to VCC and acquires a high voltage level. As the constant voltage is higher than the second reference voltage, the second terminal CKL 2  acquires a low voltage level, and the clock chip  70  controls the processor to work at a high frequency. 
     When the hard drive is at high workload, the constant voltage converted from the voltage converting module  50  is lower than the first reference voltage and the second reference voltage. The first terminal CKL 1  and the second terminal CKL 2  both acquire high voltage level, and the clock chip  70  controls the processor to work at a highest frequency. 
     Therefore, the processor frequency adjustment circuit  100  can automatically adjust the frequency of the processor in accordance with the workload of the hard drive. In the present embodiment, the first terminal CKL 1  and the second terminal CKL 2  of the clock chip  70  are used to divide the processor frequency into three segments, and increasing or decreasing the number of terminals of the clock chip  70  an the corresponding circuit can change the segment number of the processor frequency. 
     Although the present disclosure has been specifically described on the basis of this exemplary embodiment, the disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the embodiment without departing from the scope and spirit of the disclosure.

Technology Classification (CPC): 8