Patent Abstract:
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to present device information in response to one or more externally generated signals. The second circuit may be configured to store the device information. The third circuit may have (i) a first mode configured to program the device information into the second circuit and (ii) a second mode configured to transfer the device information from the second circuit to the first circuit.

Full Description:
FIELD OF THE INVENTION 
   The present invention relates to a method and/or apparatus for implementing controllers generally and, more particularly, to a method and/or apparatus for implementing enhanced device identification in a controller. 
   BACKGROUND OF THE INVENTION 
   Conventional protocol controllers often implement some form of software device identification. For example, the Peripheral Connect Interface (PCI) bus protocol provides two 16-bit identification fields called Vendor ID and Device ID. Software drivers access these fields to identify which hardware devices to control. 
   In a conventional protocol chip, the identification fields are hardwired. The conventional methodology calls for the identification fields to be updated any time a functional change is made to the chip. Updating the fields each time a functional change is made can potentially cause a problem because the functional change can involve mask layers that are not used for generating the identification information. 
   It would be desirable to implement identification fields that may be updated by software. 
   SUMMARY OF THE INVENTION 
   The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to present device information in response to one or more externally generated signals. The second circuit may be configured to store the device information. The third circuit may have (i) a first mode configured to program the device information into the second circuit and (ii) a second mode configured to transfer the device information from the second circuit to the first circuit. 
   The objects, features and advantages of the present invention include providing a method and/or apparatus for implementing enhanced device identification that may (i) implement identification fields that can be updated by software, (ii) provide on chip memory and firmware for updating and storing start of day (SOD) information and device identification fields, (iii) allow changes in identification fields without costly mask changes, (iv) replace or eliminate external devices for updating internal identifiers and/or (v) allow firmware to internally store permanent and semi-permanent information at any time. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  is a block diagram of a preferred embodiment of the present invention; 
       FIG. 2  is a more detailed block diagram of a preferred embodiment of the present invention; and 
       FIG. 3  is a flow diagram of an example operation in accordance with a preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 1 , a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  is generally implemented as a single integrated circuit (or chip). The circuit  100  may be implemented, in one example, as a protocol controller. The circuit  100  generally comprises a block (or circuit)  102 , a block (or circuit)  104 , and a block (or circuit)  106 . The circuit  102  may be implemented as an on-chip storage device. The circuit  102  may comprise, in one example, a non-volatile memory (e.g., EEPROM, NVRAM, etc.). However, other types of memory may be implemented accordingly to meet the design criteria of a particular implementation. The circuit  102  generally replaces external devices (e.g., external EEPROM that are read at power-up) that are used in conventional approaches to update internal identifiers (e.g., start of day (SOD) information). 
   The circuit  104  may comprise firmware that may be configured to update, in one example, one or more device identification fields of the circuit  100 . The device identification fields are generally updated with information contained within the memory  102 . Such updating may allow changes to be made in the identification fields of the device  100  without costly mask changes to the IC device. The circuit  104  may also be configured to program (or update) information stored in the memory  102 . For example, the circuit  104  may comprise firmware (i) containing the SOD information and/or register values and (ii) configured to program the SOD information and/or register values into the circuit  102 . Alternatively, the firmware may be configured to accept SOD information and/or register values from external to the circuit  100  (e.g., from a host). The firmware may be further configured to store permanent and semi-permanent information in addition to the SOD information and register values in the memory  102 . 
   The circuit  106  may be implemented, in one example, as one or more host accessible registers. The circuit  106  may be configured to present device identifiers in response to a request from the host (e.g., a request generated by a software driver). In one example, the circuit  104  may be configured to update (or program) the device identifiers in the circuit  106  from information stored in the memory  102 . In another example, the circuit  106  may be configured to retrieve device identifiers from the circuit  102  and present the retrieved identifiers to the host. 
   Referring to  FIG. 2 , a more detailed block diagram of the circuit  100  of  FIG. 1  is shown. In one example, the circuits  102 ,  104  and  106  may be coupled by an internal bus  108 . The internal bus  108  may be implemented, in one example, as an AHB bus. However, other appropriate busses may be implemented accordingly to meet the design criteria of a particular application. In one example, the circuit  102  may be coupled to the bus  108  via a circuit  110 . The circuit  110  may be implemented, in one example, as an AHB slave device. The circuit  104  may be implemented, in one example, as an AHB master device. However, other types of devices may be implemented accordingly to meet the design criteria of a particular application. 
   The circuit  104  (e.g., the master device) generally communicates with the circuit  110  (e.g., the slave device) to store information in and/or retrieve information from the memory  102 . When the information is retrieved, the circuit  104  or the circuit  110  may be configured to route the information to the circuit  106  via the bus  108 . The circuit  106  may be configured to present the retrieved information to a host device  112  via, in one example, an interface  114 . The interface  114  may be implemented, in one example, as a PCI interface. However, other types of interfaces may be implemented accordingly to meet the design criteria of a particular application. 
   Referring to  FIG. 3 , a flow diagram  200  is shown illustrating an example operation in accordance with a preferred embodiment of the present invention. Following power-on of a device incorporating the present invention (e.g., the block  202 ), communication with the host device may be suspended. For example, a boot mechanism of the device  100  may be disabled (e.g., the block  204 ). In general, the boot mechanism may be disabled to allow time for initialization of the device  100 . For example, start of day (SOD) information and/or device identifiers of the device  100  may be initialized from the internal memory  102  (e.g., the block  204 ). 
   In one example, the circuit  102  may comprise an on-chip, non-volatile storage media with one or more flags. The one or more flags may be configured to indicate whether the circuit  102  has been programmed with SOD information and/or device identifiers. Firmware may be configured to check the flags (e.g., the block  206 ). When the flags are in a first state (e.g., not set), the firmware may be configured to program SOD information and internal register values (e.g., device identifiers) into the circuit  102  via the internal data bus  108  (e.g., the block  208 ). The SOD information and internal register values to be programmed may be contained, in one example, within the firmware. Alternatively, the firmware may be configured to accept the information from the host driver. When the flags are in a second state (e.g., set), the firmware may be configured to read the register values from the circuit  102  and program SOD information and/or registers of the chip  100  (e.g., the block  210 ). Once the start of day information and/or registers have been initialized (or updated), the boot mechanism may be enabled (e.g., the block  212 ). 
   The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted or set) and off (e.g., de-asserted or not set) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. 
   The function performed by the flow diagram of  FIG. 3  may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Technology Classification (CPC): 6