Patent Abstract:
A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to fabrication methods of semiconductor packages, and more particularly, to a fabrication method of a semiconductor package for improving the product reliability. 
         [0003]    2. Description of Related Art 
         [0004]    Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high electrical performance. Accordingly, fan out packaging technologies have been developed to meet the miniaturization requirement of semiconductor packages. 
         [0005]      FIGS. 1A to 1D  are schematic cross-sectional views showing a fabrication method of a fan out semiconductor package  1  according to the prior art. 
         [0006]    Referring to  FIG. 1A , a carrier  10  is provided and an adhesive layer  11  is formed on the carrier  10 . 
         [0007]    Then, a plurality of semiconductor elements  12  are disposed on the adhesive layer  11 . Each of the semiconductor elements  12  has an active surface  12   a  with a plurality of electrode pads  120  and a non-active surface  12   b  opposite to the active surface  12   a . The semiconductor elements  12  are attached to the adhesive layer  11  via the active surfaces  12   a  thereof. 
         [0008]    Referring to  FIG. 1B , an encapsulant  13  is laminated on the adhesive layer  11  for encapsulating the semiconductor elements  12 . 
         [0009]    Referring to  FIG. 1C , a curing process is performed to cure the encapsulant  13 , and then the adhesive layer  11  and the carrier  10  are removed to expose the active surfaces  12   a  of the semiconductor elements  12 . 
         [0010]    Referring to  FIG. 1D , an RDL (Redistribution Layer) process is performed to form an RDL structure  14  on the encapsulant  13  and the active surfaces  12   a  of the semiconductor elements  12 . The RDL structure  14  is electrically connected to the electrode pads  120  of the semiconductor elements  12 . 
         [0011]    Then, an insulating layer  15  is formed on the RDL structure  14 , and portions of the RDL structure  14  are exposed from the insulating layer  15  so as for a plurality of conductive elements  16  such as solder bumps to be mounted thereon. 
         [0012]    However, large stresses may be generated during the curing process of the encapsulant  13  and dispersed by the carrier  10 . As such, referring to FIG.  1 D′, warpage easily occurs on edges of the encapsulant  13  after the carrier  10  is removed. Therefore, it becomes difficult for the RDL structure  14  to be aligned with the electrode pads  120  of the semiconductor elements  12 . The greater the size of the carrier  10  is, the more severe the position tolerance between the semiconductor elements  12  becomes, thereby adversely affecting the electrical connection between the RDL structure  14  and the semiconductor elements  12 . As such, the product reliability and yield are reduced. 
         [0013]    Therefore, there is a need to provide a fabrication method of a semiconductor package so as to overcome the above-described drawbacks. 
       SUMMARY OF THE INVENTION 
       [0014]    In view of the above-described drawbacks, the present invention provides a fabrication method of a semiconductor package, which comprises the steps of: providing a carrier; disposing at least a semiconductor element on the carrier, wherein the semiconductor element has an active surface with a plurality of electrode pads and a non-active surface opposite to the active surface, and the semiconductor element is disposed on the carrier via the active surface thereof; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element, wherein the encapsulant has a first surface bonded to the carrier and a second surface opposite to the first surface, and the encapsulant further has a pressure area defined around the semiconductor element; removing the carrier to expose the first surface of the encapsulant and the active surface of the semiconductor element; disposing at least a pressure member on the pressure area of the encapsulant; and forming an RDL structure on the active surface of the semiconductor element and the first surface of the encapsulant, wherein the RDL structure is electrically connected to the electrode pads of the semiconductor element. 
         [0015]    In the above-described method, the pressure member can have a frame. 
         [0016]    In the above-described method, two pressure members can be disposed on both the first surface and the second surface of the encapsulant, respectively. For example, the pressure area of the encapsulant can be sandwiched between the pressure members. 
         [0017]    In the above-described method, the at least a pressure member can be made of an iron material or a magnetic body. 
         [0018]    In the above-described method, the at least a pressure member can be disposed on only one of the first surface and the second surface of the encapsulant. 
         [0019]    In the above-described method, the encapsulant can be formed by molding, thin film laminating or printing. 
         [0020]    In the above-described method, the pressure area can be located on edges of the first or second surface of the encapsulant. 
         [0021]    In the above-described method, if a plurality of semiconductor elements are provided, the pressure area can further be located between any two adjacent ones of the semiconductor elements. 
         [0022]    The above-described method can further comprise forming on the RDL structure an insulating layer having a plurality of openings for exposing portions of the RDL structure. 
         [0023]    The above-described method can further comprise performing a singulation process after forming the RDL structure, and the at least a pressure member can be removed through the singulation process. 
         [0024]    According to the present invention, after the carrier is removed, the pressure member is disposed on the pressure area of the encapsulant for providing a support force to keep the structure flat, thereby mitigating warpge of the encapsulant. 
         [0025]    As such, warpage of the encapsulant does not increase as the size of the carrier increases. Therefore, the RDL structure can be effectively aligned with and electrically connected to the semiconductor element so as to improve the product reliability and yield and reduce the fabrication cost. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0026]      FIGS. 1A to 1D  are schematic cross-sectional views showing a conventional fabrication method of a semiconductor package, wherein FIG.  1 D′ shows warpage of the structure of  FIG. 1C ; and 
           [0027]      FIGS. 2A to 2F  are schematic cross-sectional views showing a fabrication method of a semiconductor package according to the present invention, wherein FIG.  2 D′ is an upper view of  FIG. 2D , FIG.  2 D″ is an upper view showing another embodiment of  FIG. 2D . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0028]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
         [0029]    It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “upper”, “on”, “first”, “second” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention. 
         [0030]      FIGS. 2A to 2F  are schematic cross-sectional views showing a fabrication method of a semiconductor package  2  according to the present invention. 
         [0031]    Referring to  FIG. 2A , a carrier  20  is provided, and a plurality of semiconductor elements  22  are array arranged on the carrier  20 . 
         [0032]    In the present embodiment, the carrier  20  can be a wafer type substrate or a panel type substrate. The carrier  20  can have a base board  200  made of glass, and a release layer  201  and an adhesive layer  202  sequentially formed on the base board  200 . Each of the semiconductor elements  22  has an active surface  22   a  with a plurality of electrode pads  220  and a non-active surface  22   b  opposite to the active surface  22   a . The semiconductor elements  22  are attached to the adhesive layer  202  via the active surfaces  22   a  thereof. 
         [0033]    Referring to FIGS.  2 B and  2 D′, an encapsulant  23  is formed on the adhesive layer  202  of the carrier  20  and the semiconductor elements  22  for encapsulating the semiconductor elements  22 . The encapsulant  23  has a first surface  23   a  bonded to the carrier  20  and a second surface  23   b  opposite to the first surface  23   a . The encapsulant  23  further has a pressure area t defined around the semiconductor elements  22 . 
         [0034]    In the present embodiment, the encapsulant  23  is made of a thin film and formed through laminating, or made of an adhesive material and formed through printing. In other embodiments, the encapsulant  23  can be made of a molding compound and formed through a molding process. 
         [0035]    Generally, the encapsulant  23  needs to be cured through a heating process, thus increasing internal stresses of the encapsulant  23 . The internal stresses can be dispersed by the carrier  20 . 
         [0036]    The pressure area t can be located on edges of the first surface  23   a  or the second surface  23   b  of the encapsulant  23 . 
         [0037]    Further, the active surfaces  22   a  of the semiconductor elements  22  are coplanar with the first surface  23   a  of the encapsulant  23 . 
         [0038]    Referring to  FIG. 2C , the carrier  200  and the release layer  201  and the adhesive layer  202  on the carrier  200  are removed to expose the first surface  23   a  of the encapsulant  23  and the active surfaces  22   a  of the semiconductor elements  22 . 
         [0039]    Referring to FIGS.  2 D and  2 D′, a pressure member  21  is disposed on the pressure area t of the encapsulant  23 . 
         [0040]    In the present embodiment, the pressure member  21  is of a frame and has two portions respectively disposed on the first and second surfaces  23   a ,  23   b  of the encapsulant  23 . The two portions of the pressure member  21  are aligned with each other so as to sandwich the pressure area t of the encapsulant  23  between them. Preferably, the two portions of the pressure member  21  are made of an iron material or mutually attractive magnetic bodies. In another embodiment, the two portions of the pressure member  21  can be not aligned with each other. 
         [0041]    In another embodiment, the pressure member  21  can be disposed on only one of the first surface  23   a  and the second surface  23   b  of the encapsulant  23 . 
         [0042]    Referring to FIG.  2 D″, a pressure area t′ is further defined between the semiconductor elements  22  so as for the pressure member  21  to be disposed thereon. 
         [0043]    According to the present invention, after the carrier  20  is removed, the pressure member  21  provides a support force to keep the structure flat, thereby mitigating warpage of the encapsulant  23 . 
         [0044]    Referring to  FIG. 2E , an RDL process is performed to form an RDL structure  24  on the active surfaces  22   a  of the semiconductor elements  22  and the first surface  23   a  of the encapsulant  23 . The RDL structure  24  is electrically connected to the electrode pads  220  of the semiconductor elements  22 . 
         [0045]    In the present embodiment, the RDL structure  24  has a dielectric layer  240  formed on the first surface  23   a  of the encapsulant  23  and the active surfaces  22   a  of the semiconductor elements  22 , a circuit layer  241  formed on the dielectric layer  240 , and a plurality of conductive vias  242  formed in the dielectric layer  240  for electrically connecting the circuit layer  241  and the electrode pads  220  of the semiconductor elements  22 . 
         [0046]    Thereafter, an insulating layer  25  is formed on the RDL structure  24  and has a plurality of openings for exposing portions of the circuit layer  241 . Then, a plurality of conductive elements  26  such as solder bumps are formed on the exposed portions of the circuit layer  241 . 
         [0047]    The dielectric layer  240  can be made of polyimide (PI), benezocyclobutene (BCB) or polybenzoxazole (PBO). 
         [0048]    In other embodiments, the RDL structure can have a plurality of dielectric layers  240  and a plurality of circuit layers  241  formed on the dielectric layers  240 . 
         [0049]    Referring to  FIG. 2F , a singulation process is performed along cutting paths S of  FIG. 2E  so as to obtain a plurality of semiconductor packages  2 . Also, the pressure member  21  is removed through the singulation process. 
         [0050]    According to the present invention, the pressure member  21  is disposed on the pressure area t of the encapsulant  23  for providing a support force to keep the structure flat, thereby mitigating warpge of the encapsulant  23 . 
         [0051]    Therefore, warpage of the encapsulant  23  does not increase as the size of the carrier  20  becomes larger. Accordingly, the conductive vias  242  of the RDL structure  24  can be effectively aligned with and electrically connected to the electrode pads  220  of the semiconductor elements  22  so as to improve the product reliability and yield and reduce the fabrication cost. 
         [0052]    The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.

Technology Classification (CPC): 7