Patent Abstract:
Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item making it possible to discharge the intermediate node for the duration of said time window, characterized in that the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means.

Full Description:
PRIORITY CLAIM 
     This application claims priority from French patent application No. 06/07335, filed Aug. 16, 2006, which is incorporated herein by reference. 
     TECHNICAL FIELD 
     An embodiment of this invention relates to a bistable circuit and, in particular, to a bistable circuit capable of being involved in the production of a latch, a flip-flop, and so on. 
     BACKGROUND 
     A flip-flop is a component commonly used in microelectronics to store a binary value or “state”. A common way of producing it is to assemble two latches, respectively called a master latch and a slave latch. A latch is typically a bistable circuit, of which the structure, known in itself, includes two inverters connected head-to-tail. One or the other or both of these inverters can be tristate inverters. 
     The flip-flop has two distinct periods:
         a transparent period during a short time window around an edge of the clock signal, during which an input data item can be transferred to the level of the flip-flop output, and   a storage period, in which the latch maintains the state of its output regardless of the input data. During this period, the output of the latch therefore provides the most recent information that has passed through it in its previous transparent state.       

     In the case of a flip-flop triggered on a rising clock edge, the first latch (master) is transparent when the clock signal is at low level (logic 0) and in storage mode when the clock signal is at high level (logic 1). The second latch (slave) is transparent when the clock signal is high level and in storage mode when the clock signal is at low level. Thus, the resulting latch is transparent during the rising edge of the clock signal. 
     An example of this type of latch, based on a so-called “Hybrid Latch Flip-Flop” (HLFF) architecture, is presented in the article “Flow-through latch and edge triggered flip-flop hybrid elements” of H. Partovi et al., IEEE 1996, International Solid State Circuit Conference, which is incorporated by reference. 
       FIG. 1  shows an embodiment according to the prior art of the master latch of an HLFF-type flip-flop. The operation of this latch is based on the use of a delayed clock signal. To this end, the bistable structure of the master latch integrates a delay chain based on CH inverters. The delay chain CH includes three series-connected inverters I 1 , I 2  and I 3 . The inverter I 1  receives, at the input, the clock signal CLK, so that the inverse clock signal CLK/ delayed three times through the three inverters I 1 , I 2  and I 3  is generated at the output of the inverter chain. 
     In the detail, a first inverter of the bistable circuit of  FIG. 1  is constituted by a pMos-type transistor P 1 , of which a source is connected to a power supply source Vdd of the circuit and of which a gate is connected to the clock input CLK of the circuit, and three nMos-type transistors, respectively MN 1 , MN 2  and MN 3 , connected in series between the drain of the transistor P 1  and a ground of the circuit. The gate of transistor MN 1  is controlled by the delayed inverse clock signal CLK/ delivered at the output of the delay chain CH. The gate of transistor MN 2  is controlled by an input data item Data and the gate of transistor MN 3  is controlled by the clock signal CLK. The common point M of transistors P 1  and MN 1  is connected to the input of a second inverter of the bistable circuit providing the output Out and by means of which the first inverter is looped back to its input. 
     The second inverter is formed by three Mos transistors P 2 , N 2  and N 3 , connected in series between the supply voltage Vdd and a ground of the circuit. In the detail, the pMos-type transistor P 2  has its source connected to the power supply voltage Vdd of the circuit, and its drain connected to the drain of the nMos-type transistor N 2  so as to provide the output Out, with the gates of transistors P 2  and N 2  being connected together to the intermediate node M of the bistable circuit. The source of transistor N 2  is connected to the drain of the nMos-type transistor N 3 , of which the source is connected to the ground of the circuit and of which the gate is connected to the clock input CLK of the circuit. 
     The operation of the circuit of  FIG. 1  is as follows. When the clock signal CLK is at low level, the node M is pre-charged to Vdd by means of transistor P 1  which is turned on, with the path to the ground being closed by means of transistor MN 3 , which is off, whereas transistor MN 1  is on due to the inverse clock signal CLK/ at high level applied to its gate. 
     In a next clock edge, the signal CLK switches to high level. Transistor MN 3  is then turned on. As the inverter-based delay chain CH creates a certain delay, the inverse clock signal CLK/ applied to the gate of MN 1  is therefore kept at high level for the duration of this delay, leaving transistor MN 1  on. During the delay created by the delay chain CH, there is therefore a time window during which transistors MN 1  and MN 3  are simultaneously on. At the end of this delay, the delayed clock signal CLK/ will drop to low level, then controlling the closing of the path constituted by the nMos transistors MN 1 , MN 2  and MN 3 . 
     Thus, during the short time window available around the clock edge following the pre-charge phase during which transistors MN 1  and MN 3  are simultaneously on:
         if the data input signal Data is at low level, the path of the nMos transistors MN 1  to MN 3  is blocked and the intermediate node M is kept at high level at its pre-charge value. A logic 0 is then transmitted to the level of the output Out, since the two nMos N 2  and N 3  are on;   if, on the other hand, the data input signal Data is at high level, MN 2  is turned on, which opens the path of transistors MN 1  to MN 3  and the intermediate node M is discharged (pulled to the ground) by means of the three transistors MN 1  to MN 3 . A logic 1 is then transmitted to the level of the output Out, and transistor N 2  is again turned off while P 2  is on.       

     The flip-flop is therefore transparent for the duration of the delay created by the delay chain, defining a time window in which both the clock and the delayed clock are at the high level, enabling the input data to be transferred to the output. 
     This structure is advantageous owing to the switching speed due to the pre-charge of the node M, but it is limited by the difficulty of obtaining the time window, defining a period of latch transparency that is long enough to allow the discharge of the node M. 
     Indeed, it is possible to have a situation in which the transistors MN 1 , MN 2  and MN 3  forming the discharge means of the node M are rather slow, while the inverters I 1 , I 2  and I 3  are rather fast. A configuration of this type can lead to an unfavorable situation, in which the time needed to discharge the node M through the battery MN 1 /MN 2 /MN 3  is greater than the duration of the time window provided by the chain of inverters I 1 , I 2 , I 3  during which transistor MN 1  of the discharge battery is kept on. More specifically, as the inverter chain is rather fast, during a rising clock edge, it does not make it possible to produce a sufficiently long delay, which means that the delayed clock signal falls too quickly to be able to give the battery of nMos MN 1 , MN 2  and MN 3  the time to discharge the node M when the data signal Data is at the high level. 
     This defective operation of the latch can be explained by mismatches of the Mos transistors used, on the one hand, in the inverter-based delay chain CH and, on the other hand, in the path of nMos MN 1 , MN 2  and MN 3 , occurring in their production. Thus, problems of repeatability in the transistor production method can mean that Mos transistors have characteristics that diverge with respect to those expected, which distorts the performance expected in terms of the current capable of being drawn by the Mos respectively from the inverter chain CH and the path MN 1 /MN 2 /MN 3 , capable of resulting in a defective operation in terms of the assembly&#39;s dynamics, as explained above. 
     One way of overcoming these undesirable effects related to mismatches is to have the delay produced by the delay chain be longer than the discharge time of the longest node M engaged by the transistor path MN 1 /MN 2 /MN 3 . One way of delaying the inverter chain CH in order to prepare for this worst-case scenario is to adjust the W/L ratio (W being the width and L being the length) of the transistors of the inverter chain CH so as to reduce the amount of current passed through by each of them. 
     However, such a choice intended to take into account in the delay chain worst-case delay of the discharge path MN 1 /MN 2 /MN 3 , while ensuring that the node M has the time necessary to be discharged through the path MN 1 /MN 2 /MN 3 , may impair the performance of the latch. Indeed, by thus increasing the duration of the time window defined by the delay chain, the duration of the transparency window of the latch, and therefore also the time of establishing and of maintaining the input data are increased, which may adversely affect the use of the latch, since it means that the input data must be held for a longer time, according to the time during which the inverter chain CH has not yet turned off the transistor MN 1 . 
     This choice of adjusting the W/L ratio of the transistors of the inverter chain with respect to the W/L ratio of the transistors of the path MN 1 /MN 2 /MN 3 , also has the disadvantage of not being capable of being implemented in all transistor production processes. 
     SUMMARY 
     An embodiment of this invention is therefore intended to solve one or more of these disadvantages by making it possible to best align the delay created by the inverter chain to the time necessary for the node M of the latch to be discharged through the path of nMos transistors, so as to obtain a bistable circuit better suited to the possible variations in the process for production of the transistors of the structure. 
     An embodiment of the invention thus relates to a bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item making it possible to discharge the intermediate node for the duration of said time window, wherein the delay means include means for temporally adjusting the duration of the time window to the time needed for the discharging of the intermediate node through said discharge means. 
     According to an embodiment, as the delay means include an inverter chain and the discharge means include a path of nMos transistors connected in series between the pre-charge means and a ground of the circuit, the means for time adjustment of the delay means are integrated at the level of a modified inverter of the inverter chain, in the form of a path of nMos transistors replicating the transistor path of the discharge means, connected in series with a pMos transistor of said inverter. 
     The means for discharging the intermediate node advantageously may also include a logic combination stage between at least two input data items of the circuit. 
     The logic combination stage may include a network of transistors arranged in the transistor path of the discharge means so as to perform a predetermined logic function between the input data items, wherein said transistors constituting the logic combination stage are each controlled respectively by one of the input data items. 
     The transistor path of the modified inverter of the delay chain advantageously may include a number of stages identical to that of the transistor path of the means for discharging the intermediate node. 
     According to an alternative, the transistor path of the modified inverter of the delay chain includes fewer stages than the transistor path of the means for discharging the intermediate node. 
     An embodiment of the invention also relates to a latch including a bistable circuit. 
     An embodiment of the invention relates to a flip-flop including a master latch and a slave latch, in which the master latch is a latch as described above. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features and advantages of one or more embodiments of this invention will become more clear upon reading the following description given by way of an illustrative and non-limiting example, in reference to the appended figures. 
         FIG. 1  shows the structure according to the prior art of the master portion of an HLFF-type flip-flop latch. 
         FIG. 2  shows the structure of  FIG. 1  improved according to an embodiment of the invention. 
         FIG. 3  shows an alternative embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Starting with the bistable structure of  FIG. 1 , the time performance of the discharge path MN 1 /MN 2 /MN 3  is transferred to the inverter chain CH producing the delay, so that if the transistors of the discharge path are slow, the delay chain will be slow and, conversely, if they are fast, the delay chain will be fast. 
       FIG. 2  shows this principle, in which the elements already described in reference to  FIG. 1  have the same reference. 
     In the example of  FIG. 2 , the inverter I 1  of the delay chain is modified so as to integrate specific means that enable the delay chain CH to temporally adjust its delay to the discharge time needed to discharge the intermediate node M through the transistors MN 1 , MN 2  and MN 3  of the discharge path. 
     A conventional inverter includes a pMos transistor and an nMos transistor connected in series between the power supply and the ground and controlled on their gate by the same signal. The modified inverter I 1  according to the example includes, in the place of a single nMos, multiple nMos transistors, respectively MND 1 , MND 2  and MND 3 , connected in series between a pMos transistor P 3  and the ground, all controlled by the same signal on their gate, which are intended to replicate the structure of the nMos transistors MN 1 , MN 2  and MN 3  of the discharge path at the level of the structure of the inverter I 1 . 
     Thus, with respect to a conventional inverter used in the delay chain, the modified inverter I 1  may make it possible to more reliably transfer the behavior of the transistors of the discharge path when the node M is discharged. Indeed, when there is a clock edge, the clock signal switches to 1, and the capacitance formed between I 1  and I 2  is discharged through MND 1 , MND 2  and MND 3  to produce a 0, which will be propagated through I 2  to make a 1, then through I 3  to make a 0, which finally turns off the transistor MN 1 . The objective is to have the discharge through the transistors MND 1 , MND 2  and MND 3  of the inverter I 1  replicate the discharge of the node M through the transistors MN 1 , MN 2  and MN 3  of the discharge path. The time of propagation through the conventional inverters I 2  and I 3  then normally forms the margin available in the time window defined by the delay chain for discharging the node M. 
     According to an alternative of the example described in  FIG. 2 , the inverter of the modified delay chain could just as well be the inverter located in the second (I 2 ) or third (I 3 ) position in the delay chain. 
     According to another embodiment described in reference to  FIG. 2 , the structure of the discharge path is replicated in the modified inverter I 1 , i.e. the path of nMos transistors MND 1  to MND 3  of the modified inverter I 1  of the delay chain includes a number of stages, in this case three, identical to that of the path of nMos transistors MN 1  to MN 3  of the means for discharging the node M, wherein the sizes of the transistors of the discharge path and the modified inverter path, respectively, are also ideally identical. 
     However, this ideal configuration may be costly in terms of both consumption and space occupied on the circuit, although it makes it possible to ensure that the time for discharging the intermediate node M via the discharge path MN 1 /MN 2 /MN 3  is substantially perfectly replicated through the path MND 1 /MND 2 /MND 3  of the modified inverter of the delay chain. 
     In addition, the sizes of the transistors MND 1 /MND 2 /MND 3  of the modified inverter of the delay chain may advantageously be chosen to be smaller than those of the transistors MN 1 /MN 2 /MN 3  of the path for discharging the intermediate node, for example by a factor of 5, so as to find a compromise between the relatively reliable monitoring and consideration of the time for discharging the intermediate node in the delay chain and the constraints on consumption and bulk of the circuit. 
     An alternative solution for saving space would also be to remove an nMos transistor, i.e. transistor MND 2  according to the example, of the modified inverter in the delay chain. This solution may be made, however, at the expense of a good time adaptation of the delay chain to the time for discharging the intermediate node through the discharge path. 
     Finally, an embodiment shown in  FIG. 3  includes integrating a logic combination stage COMB in the means for discharging the intermediate node M. The logic combination stage COMB according to the example of  FIG. 3  includes two nMos transistors MN 2  and MN 4 , connected in series in the discharge path between transistors MN 1  and MN 3 , respectively controlled by the input data Data 1  and Data 2 , and in this way performs the AND logic function between the two input data items Data_ 1  and Data_ 2 . The intermediate node M is then discharged by discharge means when both the data item Data_ 1  is 1 and the data item Data_ 2  is 1, and, therefore, results in the NOT AND logic operation (Data_ 1  AND Data_ 2 ), which amounts to integrating a NOT AND gate in the bistable circuit according to the example. 
     The use of an onboard logic function in the actual bistable circuit advantageously may make it possible to gain the delay created by the logic gate, which would otherwise be provided upstream of the bistable circuit in order to produce the logic function in question. Actually, a bit less than this delay is gained, because the combination of the logic gate with the bistable circuit requires an additional Mos to be added, MN 4  according to the example, in the discharge path in order to produce the corresponding logic combination stage. 
     In this embodiment of the bistable with onboard logic via a network of nMos transistors integrated in the discharge means between transistors MN 1  and MN 3 , to produce a predetermined logic function between input data items Data_ 1  to Data_n of the circuit, the modified delay chain CH according to an embodiment of the invention then may replicate the discharge path as explained above, therefore including the network of transistors of the discharge path performing the logic function. 
     Thus, according to the example of  FIG. 3 , the modified inverter I 1  includes four transistor stages, respectively MND 1 , MND 2 , MND 3  and MND 4 , in the same way that the modified discharge path, which includes integrated logic, includes the four transistor stages, respectively MN 1 , MN 2 , MN 3  and MN 4 . In this way, the time window defined by the delay chain is best adapted to the time for discharging the node M via the discharge path with onboard logic. 
     One or both of the circuits of  FIGS. 2 and 3  may be included in an integrated circuit (IC) such as a memory or microprocessor, which may be included in a system such as a computer system. In the system, the IC may be coupled to another IC such as a controller. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.

Technology Classification (CPC): 7