Patent Abstract:
A method and a circuit dynamically adjust a frequency of a clock signal that drives the operations of a power converter. The method includes (a) detecting a change from a predetermined value in an output voltage of the power converter; and (b) upon detecting the change, changing the frequency of the clock signal so as to restore the output voltage. The change, such as a load step-up, may be detected by comparing a feedback signal generated from the output voltage and a predetermined threshold voltage. In one implementation, changing the switching frequency is achieved in increasing (e.g., doubling) the frequency of the clock signal, as needed. The frequency of the clock signal need only be changed for a predetermined time period.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application relates to and claims priority of U.S. provisional patent application (“Copending Provisional Application”), Ser. No. 61/810,661, entitled “Dynamic Switching Frequency Adjustment for Fast Transient Response,” filed on Apr. 10, 2013. The disclosure of the Copending Provisional Application is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a control loop in a power converter. In particular, the present invention relates to dynamically adjusting the switching frequency in a control loop of a power converter to provide a fast response to output transients. 
     2. Discussion of the Related Art 
     In a power converter, the output capacitor is a key factor in achieving a high power density. There are two main design considerations for an output capacitor: (a) steady state voltage ripple and (b) voltage spike during a transient. In a conventional power converter, the total output capacitance is mainly designed for transient response. Good transient response is normally achieved by optimizing the bandwidth of the power converter&#39;s control loop. However, due to non-linearity, a higher bandwidth does not always result in a better transient response. This can be illustrated, for example, by a peak current mode-controlled power converter. 
       FIG. 1( a )  is a schematic diagram showing single-phase circuit configuration  100  for one type of power converter. As shown in  FIG. 1( a ) , circuit configuration  100  includes a control module  101  receiving an input voltage V in  and providing clock signals  102   a  and  102   b , which drive switch  103  (“top-side switch”) and switch  104  (“bottom-side switch”), respectively. The operations of top-side switch  103  and bottom-side switch  104  transfer energy to output capacitor  106  through output inductor  105 . Based on feedback signal (V FB ), control module  101  operates to maintain output voltage V O  at a steady state value. In some power converters, multiple sets of inductors and top-side and bottom-side switches may be used in a “multi-phase” configuration to drive a common output voltage. 
       FIG. 1( b )  shows the waveforms of output voltage (V O ), the output current (I O ), and the switching node signal (SW), in response to a step increase in load current of 15 A. In the power converter of  FIG. 1( a ) , the design parameters are: (a) a 12-volt input voltage (V in ), (b) a 1-volt nominal output voltage (V O ), (c) a 400 kHz switching frequency (f SW ), (d) a 250 nH inductor (L), and (e) a 860 μF output capacitance (C OUT ), provided by two 330 μF/9 mΩ tantalum polymer capacitors, and two 100 μF/2 mΩ ceramic capacitors. The control loop bandwidth is around 60 kHz with 72° phase margin. As shown in  FIG. 1( a ) , at time t=500 μs, the output load current increases by a 15 A step. Because the step current increase occurs immediately after the top-side switch is turned off, output voltage V O  on the output capacitor drops rapidly to 0.92 volts until the top-side switch turns on again at the beginning of the next switching cycle (t=502.5 μs, about 2.3 μs later). During the switching cycle delay, the feedback control loop provides no help reducing the voltage drop at the output capacitor. The situation is more acute with small duty-cycle operation, as shown in  FIG. 1 . 
     A non-linear control scheme may reduce the switching cycle delay. In the non-linear control loop a threshold voltage is selected. When the output voltage falls below the threshold voltage, a voltage undershoot condition is deemed occurred. When the voltage undershoot condition is detected, the top-side switch is immediately turned on, rather than waiting for the beginning of the next switching cycle. There are, however, two drawbacks in this method. First, the monitored threshold voltage is sensitive to both component values and the layout. Second, the nonlinear control scheme may interact with one or more other control loops (e.g., a linear control loop) to create undesired oscillations. These drawbacks introduce unreliability in conventional designs. 
     SUMMARY 
     According to one embodiment of the present invention, a method and a circuit dynamically adjust the frequency of a clock signal that drives the operations of a power converter. The method includes (a) detecting a change from a predetermined steady state value in an output voltage of the power converter; and (b) upon detecting the change, changing the frequency of the clock signal so as to restore the output voltage to the predetermined steady state value. The change, such as a load step-up, may be detected by comparing a feedback signal generated from the output voltage and a predetermined threshold voltage. In one implementation, changing the switching frequency is achieved by increasing (e.g., doubling) the frequency of the clock signal, as needed. According to one embodiment of the present invention, the frequency of the clock signal need only be changed for a predetermined time period. 
     The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1( a )  is a schematic diagram showing single-phase circuit configuration  100  for one type of power converter. 
         FIG. 1( b )  shows the waveforms of output voltage (V O ), the output current (I O ), and the switching signal that controls the top-side switch of a power converter, in response to a step increase of 15 A load current. 
         FIG. 2  illustrates a dynamic frequency adjustment scheme for improving transient response, according to one embodiment of the present invention. 
         FIGS. 3( a ) and 3( b )  show the performances of a conventional system and the same system adapted for using a dynamic switching frequency adjustment scheme of the present invention, respectively. 
         FIGS. 4( a ) and 4( b )  show the performances of a conventional system during a 10 A load current step-up and a 10 A load current step-down, respectively. 
         FIGS. 5( a ) and 5( b )  show the operations of a system using a dynamic switching frequency adjustment scheme of the present invention that substantially meets the design specifications of the conventional system of  FIGS. 4( a ) and 4( b )  under a 0 A-to-10 A step-up and under 10 A-to-0 A step-down in load current, respectively. 
         FIG. 6  shows the voltage spike reductions for various threshold values, in accordance with one embodiment of the present invention. 
         FIG. 7( a )  shows clock circuit  700  which provides a clock signal for dynamically adjusting the switching frequency of a power converter for a load step-up, in accordance with one embodiment of the present invention. 
         FIG. 7( b )  shows selected signals of circuit  700  for implementing the dynamically adjusted switching frequency scheme. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     According to one embodiment of the present invention, a dynamic switching frequency adjustment scheme improves transient response.  FIG. 2  illustrates this dynamic frequency adjustment scheme, according to one embodiment of the present invention.  FIG. 2  shows output voltage V O , feedback signal V FB , and the switching clock signals of the present invention. Feedback signal V FB  may be derived from and may be made proportional to output voltage V O . The methods of the present invention detect a transient change in output voltage V O , such as a voltage undershoot condition. The voltage undershoot condition occurs, for example, when output voltage V O  falls below a threshold voltage, such as during a load “step-up” (i.e., a sharp rise in load current). In the example of  FIG. 2 , feedback voltage V FB  is 0.6V and the threshold voltage is set at 0.975 times V FB , or 585 mV. When the voltage undershoot condition is detected, a controller switches to a higher switching frequency, so as to reduce the switching cycle delay. In  FIG. 2 , the frequency is doubled. As shown in  FIG. 2 , at the higher switching frequency, the delay between detecting the voltage undershoot condition and the time the top-side switch is turned on (i.e., the switching cycle delay) is reduced from 2.31 μs to 1.05 μs. Consequently, the voltage undershoot is reduced from 86 mV ( FIG. 1 ) to 46 mv, which is approximately a 46% reduction. The higher frequency operation may be maintained for 10 to 20 original switching cycles to ensure output voltage V O  recovers smoothly. Thus, the voltage spike experience during the transient condition is significantly reduced, or equivalently, a smaller output capacitance is required to meet the same transient spike window. The methods of the present invention are equally applicable in multi-phase power converters as in single-phase power converters. 
       FIGS. 3( a ) and 3( b )  show the performances of a conventional system and the same system adapted for using the dynamic switching frequency adjustment scheme of the present invention, respectively. The system of  FIGS. 3( a ) and 3( b )  has the following design parameters: (a) a 12-volt input voltage (V in ), (b) a 1-volt nominal output voltage (V O ), (c) a 400 kHz switching frequency (f SW ), (d) a 330 nH inductor (L), and (e) a 860 μF output capacitance (C OUT ), provided by two 330 μF/9 mΩ tantalum polymer capacitors, and two 100 μF/2 mΩ ceramic capacitors. As shown in  FIGS. 3( a ) and 3( b ) , the voltage undershoot is reduced from 133 mV to 89 mV by doubling the clock frequency for a load current step-up from 0 A to 20 A. 
     As discussed above, the methods of the present invention allow the same design specification to be achieved with a lesser output capacitance requirement. For example,  FIGS. 4( a ) and 4( b )  show the performances of a conventional system during a 10 A load current step-up and a 10 A load current step-down, respectively. This conventional system uses peak current mode control. The design specification for that conventional system is: (a) a 12-volt input voltage (V in ), (b) a 1-volt nominal output voltage (V O ), (c) a 400 kHz switching frequency (f SW ), and (d) a 40 mV peak-to-peak voltage (V pp ) limit for 10 A step-up and 10 A step-down in load currents. In the example of  FIGS. 4( a ) and 4( b ) , these specifications are substantially satisfied by a 330 nH inductor (L), and a 2220 μF output capacitance (C OUT ), which was provided by four 330 μF/6 μmΩ tantalum polymer capacitors, and nine 100 μF/2 mΩ ceramic capacitors. As seen in  FIGS. 4( a ) and 4( b ) , a 22.25 mV negative voltage spike is experienced during a 0 to 10 A step-up in load current, and a 19.5 mV during a 10 A to 0 A step-down in load current, thus providing a total peak-to-peak voltage spike of 41.75 mA. 
     The design specification of the conventional system of  FIGS. 4( a ) and 4( b )  may be met using a dynamic switching frequency adjustment scheme of the present invention with a lesser requirement on the output capacitance.  FIGS. 5( a ) and 5( b )  show the operations of such a system under a 0 A-to-10 A step-up and under 10 A-to-0 A step-down in load current, respectively. In the example of  FIGS. 5( a ) and 5( b ) , the switching frequency is doubled, when a voltage undershoot condition (i.e., load current step up) is detected, and halved, when a voltage overshoot condition is detected (i.e., load current step-down) is detected. In  FIGS. 5( a ) and 5( b ) , a 18.3 mV negative voltage spike is experienced during a 0 to 10 A step-up in load current, and a 23.75 mV during a 10 A to 0 A step-down in load current, thus providing a total peak-to-peak voltage spike of 42.05 mA. The specification is met by a 330 nH inductor (L), and a 1720 μF output capacitance (C OUT ), which was provided by four 330 μF/6 mΩ tantalum polymer capacitors, and four 100 μF/2 mΩ ceramic capacitors, which represents a reduction of output capacitance by 23%. Fewer ceramic capacitors also save significant cost. Further, as compared to the conventional nonlinear control method described above, a power converter using a dynamic switching frequency adjustment scheme of the present invention need only run in a linear control loop. Consequently, there is no concern related to interactions between a nonlinear control loop and a linear control loop, so that transient recovery can occur smoothly. 
     An additional advantage of a system using a method of the present invention is its relative insensitivity to threshold setting.  FIG. 6  shows the voltage spike reductions for threshold values that are set from 0.99 times of reference voltage V ref  to 0.95 times reference voltage V ref . Reference voltage V ref  may be set to, for example, 0.6V. As shown in  FIG. 6 , for a 10 A load current step-up, doubling the switching frequency provides the same performance improvement (i.e., a voltage spike reduction from 86 mV to 46 mV) over the range of threshold voltages between 0.96*V ref  and 0.99*V ref . 
       FIG. 7( a )  shows clock circuit  700  which provides a clock signal for dynamically adjusting the switching frequency of a power converter for a load step-up, in accordance with one embodiment of the present invention.  FIG. 7( b )  shows selected signals of circuit  700  for implementing the dynamically adjusted switching frequency scheme. As shown in  FIG. 7( a ) , circuit  700  receives (i) feedback signal V FB , representative of output voltage V O , (ii) threshold voltage V threshold , and (iii) clock signals CLK 1  and CLK 2  of the same frequency, but separated in phase by a 180°. The waveforms of clock signals CLK 1  and CLK 2  are shown as waveform  751  and  752  in  FIG. 7( b ) . When comparator  701  detects a load step-up condition, which occurs when V FB  falls below threshold voltage V threshold , its output signal triggers one-shot timer  702  to provide a pulse in enable signal  703 . The pulse in enable signal  703  has a duration spanning about 10 cycles of clock signal CLK 1 . Enable signal  703  is shown as waveform  753  in  FIG. 7( b ) . Enable signal  703  causes clock signal CLK 2  to be merged by AND gate  704  and OR gate  705  with clock signal CLK 1  to provide output clock signal CLKx. The waveform of output clock signal CLKx is shown as waveform  754  in  FIG. 7( b ) . As shown in  FIG. 7( b ) , in waveform  754 , the frequency of output clock signal CLKx is doubled during the duration of the pulse in enable signal  703 . 
     The above detailed description is provided above to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.

Technology Classification (CPC): 7