Patent Abstract:
A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a signal delay circuit and a signal delay method, and particularly relates to a signal delay circuit and a signal delay method, which mix delay signals with different delay amount. 
     2. Description of the Prior Art 
       FIG. 1  illustrates a prior art signal delay circuit. As shown in  FIG. 1 , the signal delay circuit  100  includes a plurality of continuous delay stages  101 - 109 . The delay stage  101  delays an input signal IN to generate a delay signal DS 1 , and the delay stage  103  delays the delay signal DS 1  from a previous delay stage to generate a delay signal DS 2  . . . . That is, the outputs of each delay stage has different delay amounts from the input signal IN. After that, the signal delay circuit utilizes a multiplexer  111  to select one of the delay signals DS 1 , DS 2  . . . DS n-1 , DS n  as the output signal OUT. However, complicated design for the multiplexer  111  is needed in this structure. Also, some delay will be caused to the signals. Furthermore, higher accuracy for signals is needed since speed of modern electronic devices largely increases. Therefore, the signal delay circuit  100  needs more delay stages to reach such requirement. Thereby the circuit region increases and the complexity for controlling the signal delay circuit  100  goes up as well. 
     In some signal delay circuits, a plurality of multiplexers are utilized as delay stages, and a plurality of control signals are applied thereon to select. However, more than two output terminals and more than two multiplexers are needed for this structure. Accordingly, more circuit region is needed and hard to be controlled. Besides, such structure causes more input loading. 
     Therefore, a signal delay circuit and a signal delay method are needed to improve above-mentioned problems. 
     SUMMARY OF THE INVENTION 
     One objective of the present application is to provide a signal delay circuit and a signal delay method with low input loading and smaller circuit region. 
     One embodiment of the present invention discloses a signal delay circuit, comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal; wherein the signal delay circuit can selectively enable the delay units of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled. 
     Another embodiment of the present invention discloses a signal delay method, for a signal delay circuit including a first delay path and a second delay path, wherein the first delay path and the second delay path share at least one delay unit. The signal delay method comprises: utilizing the first delay path to delay a first input signal to generate a first delay signal; utilizing the second delay path to delay the first input signal to generate a second delay signal; and mixing the first delay signal and the second delay signal to generate a first mixed signal. 
     In view of above-mentioned embodiments, the signal delay circuit according to the present invention can have smaller input and output loading. Additionally, different mixed signals can be utilized to perform fine tune to obtain more accurate clock signals, besides utilizing each delay stage to perform coarse tune. Moreover, delay for coarse tune and fine tune have better adjusting linearity since the same delay stage(s) is/are utilized to perform both the fine tune and coarse tune. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a prior art signal delay circuit. 
         FIG. 2  is a circuit diagram illustrating a signal delay circuit according to one embodiment of the present invention. 
         FIG. 3  is a schematic diagram illustrating the operation for the signal delay circuit shown in  FIG. 2 . 
         FIG. 4-FIG .  7  are extended embodiments for the embodiment shown in  FIG. 2 . 
         FIG. 8  illustrates a signal delay method according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
       FIG. 2  is a circuit diagram illustrating a signal delay circuit according to one embodiment of the present invention. AS shown in  FIG. 2 , the signal delay circuit  200  includes a first delay stage  201 , a second delay stage  203  and a third delay stage  205 . It should be noted that although  FIG. 2  depicts three delay stages, but it does not mean to limit the number of delay stages. The number of delay stages can be more or less than three. In  FIG. 2 , the first delay stage  201  delays the input signal IN to generate DS 1  at the output terminal OUT. The second delay stage  203  cooperates with part of the first delay stage  201  to delay the input signal IN to generate DS 2  at the same output terminal OUT. Similarly, the third delay stage  205  cooperates with part of the first delay stage  201  and part of the second delay stage  203  to delay the input signal IN to generate DS 3  at the same output terminal OUT. The detail operation for generating delay signals DS 1 , DS 2  and DS 3  will be described as below. 
     In one embodiment, the first delay stage  201  includes delay units  202 ,  204 , and the second delay stage  203  includes delay units  206 ,  208  and  210 . The input terminals of the delay unit  202  and the delay unit  206  receive the input signal IN. The input terminal of the delay unit  204  can receive outputs of the delay units  202  and  210 . The input terminal of the delay unit  208  receives the output of the delay unit  206 , and the input terminal of the delay unit  210  receives the output of the delay unit  208 . Similarly, the third delay stage  205  includes delay units  206 ,  208  and  210 , and the arrangement thereof is the same as which of the second delay stage  203 , this is omitted for brevity here. 
       FIG. 3  is a schematic diagram illustrating the operation for the signal delay circuit shown in  FIG. 2 . As shown in  FIG. 3 , the delay signal DS 1  is generated by path  1 , which has an order of: delay unit  202  to  204 , and then to the output terminal OUT. The delay signal DS 2  is generated by path  2 , which has an order of: delay unit  206  to  208 ,  210 ,  204  and then to the output terminal OUT. Similarly, the delay signal DS 3  is generated bypath  3 , which has an order of: delay unit  206  to  212 ,  214 ,  216 ,  210 ,  204  and then to the output terminal OUT. That is, the delay signal CS 1  is generated by only the first delay stage  201 , the delay signal CS 2  is generated by the second delay stage  203  with part of the first delay stage  201  (the delay unit  204 ). Also, the delay signal CS 3  is generated by the third delay stage  205  with part of the second delay stage  203  (delay units  206  and  210 ) and part of the first delay stage  201  (the delay unit  204 ). It should be noted, in this embodiment, the delay unit is implemented by an inverter and the signal delay circuit  200  is designed that the input signal IN and the output signal OUT do not have opposite phases. Accordingly, the first delay stage  201  includes only two delay units  202  and  204 , but the second delay stage  203  and the third delay stage  205  both have three delay units. However, the first delay stage  201  can have three delay stages if the item that the phases are opposite or not is not concerned. Besides, the delay unit can be implemented by other devices, and the arrangement and the number thereof will be different corresponding to used devices. 
     The signal delay circuit according to the present invention not only can generate delay signals with different delay amounts via different paths but also can generate mixed signals with different delay amount via combining more than two paths. Take the embodiment shown in  FIG. 2  for example, DS 1  and DS 2  will be combined to generate a first mixed signal MS 1  if path  1  and path  2  are combined. The delay amount of the first mixed signal MS 1 , which is named first mixed delay amount here, is between the delay amounts of DS 1  and DS 2 . The value thereof can be computed by mathematical function such as interpolation. The detail steps of how to compute MS 1  based on DS 1 , DS 2  are well known for persons skilled in the art, thus is omitted for brevity here. Similarly, if path  1 , path  2 , and path  3  are combined, DS 1 , DS 2  and DS 3  can be combined to generate a mixed signal. Also, a different mixed signal can be generated if path  3  is combined with one of path  1  and path  2 . 
     The signal delay circuit of the present invention can have other arrangement besides the delay stage arrangement shown in  FIG. 2  and  FIG. 3 .  FIG. 4-FIG .  6  are extended embodiments for the embodiment shown in  FIG. 2 . It should be noted that the first delay stage is symbolized as D 1  and the second delay stage is symbolized as D 2  . . . in following embodiments for brevity. In the embodiment shown in  FIG. 4 , the first delay stage  401  and the second delay stage  403  can be utilized to generate delay signals DS 1 , DS 2  or mix delay signals DS 1 , DS 2  to generate a mixed signal MS 1 , as above-mentioned description. Similarly, the third delay stage  405  and the fourth delay stage  407  can be utilized to generate delay signals DS 3 , DS 4  or mix delay signals DS 3 , DS 4  to generate a mixed signal MS 2 . The signals from two sides can be further mixed to generate a new mixed signal. For example, a new mixed signal MS 3  can be generated via mixing the mixed signal MS 1  with the delay signal DS 3 , and a new mixed signal MS 4  can be generated via mixing the mixed signal MS 1  with the delay signal DS 4 . The relation between the delay signals DS 1 , DS 2 , and mixed signals MS 1 , MS 3  and MS 4  can be shown as  FIG. 4 . It should be noted that, the mixed signal MS 1  generated from the delay stages  401 ,  403  and the delay signals DS 3  and DS 4  generated from the delay stages  405 ,  407  are taken for example. However, if the mixed signal MS 1  is replaced with the mixed signal MS 2  generated from the delay stages  405 ,  407 , and delay signals DS 3 , DS 4  are replaced with delay signals DS 1  and DS 2  generated from the delay stages  401 ,  403 , the signals still have the same relation. 
     In one embodiment, if the delay amount of the third delay stage  405  is designed to be the same with which of the first delay stage  401 , and the delay amount of the fourth delay stage  407  is designed to be the same with which of the second delay stage  403 , then DS 3  will be the same as DS 1 , and DS 2  will be the same as DS 4 . In this case, only one of the first delay stage  401  and the third delay stage  405  is enabled, or both are enabled, will cause the same situation. That is, generate DS 1  at the output terminal OUT. Similarly, only one of the second delay stage  403  and the fourth delay stage  407  is enabled, or both are enabled, will cause the same situation. That is, generate DS 2  at the output terminal OUT. 
     The signal delay circuit of the present invention is not limited to the symmetrical structure shown in  FIG. 4 , which has symmetric delay stages at both sides. In  FIG. 5 , the signal delay circuit  500  does not include the fourth delay stage  407  shown in  FIG. 4 . The operation for the signal delay circuit  500  shown in  FIG. 5  is similar with the signal delay circuit  400  shown in  FIG. 4 . The first delay stage  401  and the second delay stage  403  can be utilized to generate delay signals DS 1 , DS 2  or the mixed signal MS 1 . The mixed signal MS 1  and the delay signal DS 3  can be mixed to generate the mixed signal MS 2 . As above-mentioned, if the delay amount of the third delay stage  405  is adjusted to be the same as which of the first delay stage  401 , DS 3  will be the same as DS 1 . Also, if the first delay stage  401  and the third delay stage  405  are both enabled but the second delay stage  403  is disabled, DS 1  will be generated at the output terminal OUT. Similarly, if the delay amount of the third delay stage  405  is adjusted to be the same as which of the delay signal DS 2 , DS 3  will be the same as DS 2 . In this case, if the second delay stage  403  and the third delay stage  405  are both enabled but part of the delay units of the first delay stage  401  is disabled such that DS 1  is not generated, DS 2  will be generated at the output terminal OUT. 
     Moreover, the signal delay circuit of the present invention can receives different input signals and outputs delay signals with more variation. In  FIG. 6 , the signal delay circuit  600  includes first to eighth delay units  602 - 612 . The first to fourth delay units  602 - 608  receive the first input signal IN 1 , and the fifth to eighth delay units  612 - 616  receive the second input signal IN 2 . As above-mentioned description, first to fourth delay units  602 - 608  can generate delay signals DS 1 , DS 2 , DS 3 , DS 4  and mixed signals MS 1  (DS 1 +DS 2 ), MS 2  (DS 3 +DS 4 ), MS 3 (MS 1 +DS 3 ), MS 4 (MS 1 +DS 4 ). Similarly, fifth to eighth delay units  610 - 616  can generate delay signals DS S , DS 6 , DS 7 , DS 8  and mixed signals MS 5  (DS 5 +DS 6 ), MS 6  (DS 7 +DS 8 ), MS 7  (MS 5 +DS 7 ), MS 8 (MS 5 +DS 8 ). Signals of one side can be mixed with signals with the other side to generate a new mixed signal at the output terminal OUT. For example, a new mixed signal can be generated via mixing MS 4  and MS 7 . 
     In one embodiment, the delay amounts of the first, the third, the fifth and the seventh delay units  602 ,  606 ,  610  and  614  are set to be the same, and the delay amounts of the second, the fourth, the sixth and the eighth delay units  604 ,  608 ,  612  and  616  are set to be the same. In this case, DS 1 =DS 3 =DS 5 =DS 7 =DS 2 =DS 4 =DS 6 =DS 8  MS 1 =MS 2 =MS 5 =MS 6 , MS 3 =MS 7 , MS 4 =MS 8 . The relations for each signal can be shown as  FIG. 7 . In  FIG. 7 , MS 9  is generated via mixing MS 3  and DS 1 , MS 19  is generated via mixing MS 1  and MS 3 , MS 11  is generated via mixing MS 1  and MS 4 , MS 12  is generated via mixing MS 4  and DS 2 . 
     In view of above-mentioned embodiments, the signal delay method shown in  FIG. 8  can be obtained, which includes the following steps: 
     
       801 
     
     Utilize a first delay path, such as path  1  in  FIG. 3 , in the signal delay circuit to delay the first input signal IN to generate a first delay signal DS 1 . 
     
       803 
     
     Utilize a second delay path, such as path  2  in  FIG. 3 , to delay the first input signal to generate a second delay signal DS 2 . 
     
       805 
     
     Mix the first delay signal DS 1  and the second delay signal DS 2  to generate a first mixed signal MS 1 . 
     Corresponding to the embodiment shown in  FIG. 5 , the signal delay method depicted in  FIG. 8  further comprise: utilizing a third delay path, such as the path passing through the third delay stage  405  in  FIG. 5 , to delay the first input signal IN to generate a third delay signal DS 3 . Also, the third delay signal DS 3  can be utilized to mix with one of the first delay signal DS 1  and the second delay signal DS 2  to generate a mixed signal. 
     Corresponding to the embodiment shown in  FIG. 4 , the signal delay method depicted in  FIG. 8  further comprise: utilizing a fourth delay path, such as the path passing through the fourth delay stage  407  in  FIG. 4 , to delay the first input signal IN to generate a fourth delay signal DS 4 . The third and the fourth delay paths share at least one delay unit. The third delay signal DS 3  and the fourth delay signal DS 4  are mixed to generate a second mixed signal MS 2 , and the first mixed signal MS 1  can be mixed with one of the third delay signal DS 3 , the fourth delay signal DS 4  and the second mixed signal MS 2  to generate a new mixed signal. 
     Corresponding to the embodiment shown in  FIG. 4 , the signal delay method depicted in  FIG. 8  further comprise: utilizing the fifth delay path, such as the path passing through the fifth delay stage  610  in  FIG. 6 , to delay a second input signal IN 2  to generate a fifth delay signal DS 5 ; utilizing the sixth delay path, such as the path passing through the sixth delay stage  612  in  FIG. 6 , to delay the second input signal IN 2  to generate a sixth delay signal DS 6 , wherein the fifth delay path and the sixth path share at least one delay unit; utilizing the seventh delay path, such as the path passing by the seventh delay stage  614  in  FIG. 6 , to delay the second input signal IN 2  to generate a seventh delay signal DS 7 ; utilizing the eighth delay path, such as the path passing by the eighth delay stage  616  in  FIG. 6 , to delay the second input signal IN 2  to generate a eighth delay signal DS 8 , wherein the seventh delay path and the eighth path share at least one delay unit. The signal delay method further comprises mixing the fifth delay signal DS 5  and the sixth delay signal DS 6  to generate a fifth mixed signal MS 5  and mixing the seventh delay signal DS 7  and the eighth delay signal DS 8  to generate a sixth mixed signal MS 6 . The fifth mixed signal MS 5  can be mixed with one of the seventh delay signal DS 7 , the eighth delay signal DS 8  and the sixth mixed signal MS 6  to generate a new mixed signal. 
     In view of above-mentioned embodiments, the signal delay circuit according to the present invention can have smaller input and output loading. Additionally, different mixed signals can be utilized to perform fine tune to obtain more accurate clock signals, besides utilizing each delay Stage to perform coarse tune. Moreover, delay for coarse tune and fine tune have better adjusting linearity since the same delay stage(s) is/are utilized to perform both the fine tune and coarse tune. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 7