Patent Abstract:
A jack detection circuit includes a transition circuit and an AD converter. The transition circuit linearizes analog signals sent from a switching circuit. The AD converter converts the linearized analog signals to digital output signals thereby decreasing the complexity of signal recognition.

Full Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan Patent Application Serial Number 095125989, filed on Jul. 17, 2006, the full disclosure of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention generally relates to a detection circuit, and more particularly to a jack detection circuit. 
     2. Description of the Related Art 
     The majority of the present electronic products, e.g. personal computers or multimedia products, provide at least two jacks as the transmission interface of analog signals. When a user plugs a jack or key device into the jacks, an information unit, e.g. central processing unit, recognizes the device or its signal in accordance with a jack or key state of the device or the signal outputted therefrom. A keyboard module is widely used as a jack (or key) device. When a user presses any keys on the keyboard module, it will send out an analog signal such that an information unit can recognize the keys which are pressed. Conventionally, the analog signal is utilized to control switching states of a switching circuit  90 , as shown in  FIG. 1 , so as to change an equivalent resistance of the switching circuit  90  and further to generate a voltage signal V in1 . Afterward, the voltage signal V in1  is converted to a digital signal by an analog-to-digital converter (AD converter) and then outputted from an output bus N such that the information unit (not shown) can perform corresponding activities according to the outputted digital signal. 
       FIG. 1  shows a conventional switching module having a switching circuit  90  connected to an AD converter  80  in series, and an input voltage of the AD converter  80  is V in1 . The switching circuit  90  includes four switches SW 4 , SW 3 , SW 2  and SW 1 , and the conducting states of these switches are determined by a jack state or a key state of a jack or key device or its signal. In addition, the conducting priority of the switches SW 4 , SW 3 , SW 2  and SW 1  of the switching circuit  90  is SW 4 &gt;SW 3 &gt;SW 2 &gt;SW 1 . When the switch SW 4  is turned on (conduction), then Vin 1 =0 volt; when the switch SW 3  is turned on, then Vin 1 =V CC ×/(R 5 +R 4 ) volt; when the switch SW 2  is turned on, then Vin 1 =V CC ×(R 4 +R 3 )/(R 5 +R 4 +R 3 ) volt; when the switch SW 1  is turned on, then Vin 1 =V CC ×(R 4 +R 3 +R 2 )/(R 5 +R 4 +R 3 +R 2 ) volt; and when all the switches are OFF, then Vin 1 =V CC ×(R 4 +R 3 +R 2 +R 1 )/(R 5 +R 4 +R 3 +R 2 +R 1 ) volt. Generally, the input voltage V in1  is non-linearly varied in accordance with different conducting states; therefore, the interval of comparison voltage of the AD converter  80  has to be non-linear, or a higher bit rate AD converter has to be utilized. 
       FIG. 2  shows another conventional switching circuit  91  cascaded with an AD converter  80 . In this case, the switches SW 4 , SW 3 , SW 2  and SW 1  of the switching circuit  91  have identical conducting priorities, i.e. their ON and OFF states are determined by the jack or key state or the signal from the jack or key device. Normally, under different conducting states of the switches, an input voltage V in2  of the AD converter  80  various non-linearly. In this manner, the interval of comparison voltage of the AD converter  80  has to be non-linear, or a higher bit rate AD converter has to be utilized. However, this will increase the complexity of signal recognition. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a jack detection circuit so as to solve the above mentioned problems. 
     It is a further object of the present invention to provide a jack detection circuit so as to provide linearly varied input signals for an AD converter. 
     In order to achieve above objects, a jack detection circuit of the present invention is utilized for detecting a jack or key state of an analog device and/or its analog signal so as to generate a digital signal, and the jack detection circuit includes a switching circuit, a transition circuit and an AD converter (analog-to-digital converter). The switching circuit forms an equivalent resistance in accordance with the jack or key state of the analog device or its analog signal. The transition circuit is coupled to the switching circuit and generates a reference current in accordance with a first reference voltage and the equivalent resistance. The AD converter is coupled to the transition circuit and generates the digital signal according to the reference current. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects, advantages, and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
         FIG. 1  shows a circuit diagram of a conventional jack detection circuit. 
         FIG. 2  shows a circuit diagram of another conventional jack detection circuit. 
         FIG. 3  shows a block diagram of the jack detection circuit according to the first embodiment of the present invention. 
         FIG. 4  shows a circuit diagram of the jack detection circuit according to the first embodiment of the present invention. 
         FIG. 5  shows a circuit diagram of the jack detection circuit according to the second embodiment of the present invention. 
         FIG. 6  shows a circuit diagram of the jack detection circuit according to the third embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to  FIG. 3 , it illustrates a block diagram of a jack detection circuit according to the first embodiment of the present invention. The jack detection circuit is utilized for detecting a jack or key state of an analog device and/or its analog signal so as to generate a digital signal. The jack detection circuit includes a switching circuit  91 , a transition circuit  10  and an analog-to-digital converter  20  (AD converter for abbreviation hereinafter). The transition circuit  10  transfers a first signal inputted from the switching circuit  91  to a second signal, wherein one embodiment of the first and the second signals includes an analog current signal. The AD converter  20  converts and outputs the second signal to a digital output signal. 
     Referring to  FIG. 4 , it depicts a circuit diagram of the jack detection circuit in accordance with the first embodiment of the present invention including the switching circuit  91 , the transition circuit  10 , the AD converter  20  and a resistor R 5 . The resistor R 5  has a first end and a second end, wherein the first end is coupled to a second signal output terminal of the transition circuit  10 , and the second end is coupled to a reference voltage, e.g. a ground end. In this embodiment, the switching circuit  91  has four resistor units and each of the resistors has one of the four switches SW 1 , SW 2 , SW 3  and SW 4  and a corresponding resistance element, e.g. resistors R 1 , R 2 , R 3  and R 4 . The switches SW 1 , SW 2 , SW 3  and SW 4  can be controlled by an analog device so as to be in an ON state or in an OFF state. For example, if the analog device is a keyboard, each key on the keyboard corresponds to one switch or a group of switches. When a user presses a key on the keyboard, its corresponding switch or switches will be conducted (turned on). In another example, if an analog device is plugged to the jack detection circuit shown in  FIG. 3 , the switches can be impressed to conduct by a plugging force from a user. In this embodiment, assume R 1 =R ohm, R 2 =2R ohm, R 3 =4R ohm and R 4 =8R ohm. In addition, depending on different applications, the number of resistor units of the switching circuit  91  could be four as well as any other number. 
     Referring to  FIG. 4  again, the transition circuit  10  according to the first embodiment of the present invention includes a first reference voltage generator  11  and a first current mirror  12 . The first reference voltage generator  11  has an operational amplifier  111  and a first transistor  112 . The positive input terminal of the operational amplifier  111  receives a first reference voltage V ref , its negative input terminal is connected to the source of the first transistor  112  and coupled to the switching circuit  91  and its output terminal is coupled to the gate of the first transistor  112 . If the operational amplifier  111  is an ideal amplifier, the voltage on the negative input terminal V ref ′ is substantially identical to the first reference voltage V ref  on the positive input terminal. Therefore, a corresponding current I in3  can be determined by the voltage V ref ′ divided by the equivalent resistance of the switching circuit  91 , and their relationships are shown in Table 1. 
     The first current mirror  12  includes a second transistor  121  and a third transistor  122  having their gates connected with each other. If the ratio aspect of the transistor  121  is identical to that of the transistor  122 , a current aI in3  proportional to the current I in3  can be formed. Because the operation and implementation of a current mirror are well known by the person skilled in the art, their detailed descriptions will not be described herein. 
     
       
         
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 digital 
               
               
                   
                   
                   
                   
                   
                   
                 output 
               
               
                 SW 1   
                 SW 2   
                 SW 3   
                 SW 4   
                 I in3   
                 V in3   
                 signal 
               
               
                   
               
             
             
               
                 Off 
                 Off 
                 Off 
                 Off 
                 0 
                 0 
                 0000 
               
               
                 Off 
                 Off 
                 Off 
                 On 
                 V ref /8R 
                 aI in3  × R 5  = X 
                 0001 
               
               
                 Off 
                 Off 
                 On 
                 Off 
                 V ref /4R 
                 aI in3  × R 5  = 2X 
                 0010 
               
               
                 Off 
                 Off 
                 On 
                 On 
                 (V ref /8R + V ref /4R) 
                 aI in3  × R 5  = 3X 
                 0011 
               
               
                 Off 
                 On 
                 Off 
                 Off 
                 V ref /2R 
                 aI in3  × R 5  = 4X 
                 0100 
               
               
                 Off 
                 On 
                 Off 
                 On 
                 (V ref /8R + V ref /2R) 
                 aI in3  × R 5  = 5X 
                 0101 
               
               
                 Off 
                 On 
                 On 
                 Off 
                 (V ref /4R + V ref /2R) 
                 aI in3  × R 5  = 6X 
                 0110 
               
               
                 Off 
                 On 
                 On 
                 On 
                 (V ref /8R + V ref /4R + V ref /2R) 
                 aI in3  × R 5  = 7X 
                 0111 
               
               
                 On 
                 Off 
                 Off 
                 Off 
                 V ref /R 
                 aI in3  × R 5  = 8X 
                 1000 
               
               
                 On 
                 Off 
                 Off 
                 On 
                 (V ref /8R + V ref /R) 
                 aI in3  × R 5  = 9X 
                 1001 
               
               
                 On 
                 Off 
                 On 
                 Off 
                 (V ref /4R + V ref /R) 
                 aI in3  × R 5  = 10X 
                 1010 
               
               
                 On 
                 Off 
                 On 
                 On 
                 (V ref /8R + V ref /4R + V ref /R) 
                 aI in3  × R 5  = 11X 
                 1011 
               
               
                 On 
                 On 
                 Off 
                 Off 
                 (V ref /2R + V ref /R) 
                 aI in3  × R 5  = 12X 
                 1100 
               
               
                 On 
                 On 
                 Off 
                 On 
                 (V ref /8R + V ref /2R + V ref /R) 
                 aI in3  × R 5  = 13X 
                 1101 
               
               
                 On 
                 On 
                 On 
                 Off 
                 (V ref /4R + V ref /2R + V ref /R) 
                 aI in3  × R 5  = 14X 
                 1110 
               
               
                 On 
                 On 
                 On 
                 On 
                 (V ref /8R + V ref /4R + V ref /2R + V ref / 
                 aI in3  × R 5  = 15X 
                 1111 
               
               
                   
                   
                   
                   
                 R) 
               
               
                   
               
               
                 wherein X = (aV ref  × R 5 )/8R 
               
             
          
         
       
     
     Referring to  FIG. 4  again, an input end of the AD converter  20 , according to the first embodiment of the present invention, is connected between the first current mirror  12  and the first end of the resistor R 5 . The AD converter  20  is a voltage AD converter and its input voltage V in3  equals a multiplication of the current aI in3  and the resistor R 5 , i.e. V in3 =R 5 ×aI in3  as shown in Table 1, and hence the input voltage V in3  has linear characteristics. After the input voltage V in3  is converted by the AD converter  20 , a corresponding digital output signal will be outputted from the output bus N. The relationships between the conducting states of the switching circuit  91 , the input voltage V in3  of the AD converter  20  and the digital output signals are also shown in Table 1. In this embodiment, since the switching circuit  91  has four switches, the outputted digital signals are four-bit digital signals. 
     Referring to  FIG. 5 , it illustrates a jack detection circuit according to the second embodiment of the present invention. The jack detection circuit also includes the switching circuit  91 , the AD converter  20  and the resistor R 5 , and the jack detection circuit also has a transition circuit  30  which has a reference voltage generator  31  and a current mirror  32 . This embodiment differs from the first embodiment in the types of the transistors, i.e. the transistors in the transition circuit  30  of the second embodiment are P-type transistors while the transistors in the transition circuit  10  of the first embodiment are N-type transistors. A negative input terminal of the operational amplifier  311  receives the first reference voltage V ref , its positive input terminal is connected to the source of the transistor  321  and coupled to the switching circuit  91 , and its output terminal is connected to the gate of the transistor  321 . In this manner, the transition circuit  30  can also transfer a first signal I in4  to a second signal aI in4  which varies linearly in accordance with the conducting states of the switching circuit  91 . Therefore, the AD converter  20  receives an input voltage V in4 =R 5 ×aIin 4  and can have linearly varied interval of comparison voltage. 
     Referring to  FIG. 6 , it shows a jack detection circuit according to the third embodiment of the present invention. The jack detection circuit also includes the transition circuit  10 , the resistor R 5  and the switching circuit  91 . The differences herein with respect to the first embodiment are that the third embodiment further includes a comparison current circuit  40  and the type of the AD converter  50  is different. The transition circuit  10  also transfers a first signal I in5  to a second signal aI in5 , as described above. The comparison current circuit  40  comprises a second reference voltage generator  41  and a second current mirror  42 . The second reference voltage generator  41  has an operational amplifier  411  and a transistor  412 . A positive input terminal of the operational amplifier  411  receives a second reference voltage V ref ″ (in this embodiment the second reference voltage V ref ″ equals the first reference voltage V ref ), its output terminal is coupled to the gate of the transistor  412 , and its negative input terminal is connected to the source of the transistor  412  and coupled to a first end of the resistor R 5 . The second end of the resistor R 5  is coupled to a reference voltage, e.g. a ground end, so as to form a reference current I ref =V ref ″/R 5  flowing through the transistor  412 . In this embodiment, the second current mirror  42  maps the reference current I ref  to a comparison current I c  which is inputted, together with the second signal aI in5  of the transition circuit  10 , into the AD converter  50  to be compared, and finally a digital output signal will be outputted from the output bus N. The AD converter  50  in this embodiment is a current AD converter, which is utilized for comparing the second signal aI in5  outputted from the transition circuit  10  with the comparison current I c  outputted from the comparison current circuit  40 , and the second signal aI in5  varies linearly in accordance with conducting states of the switching circuit  91 . 
     In addition, embodiments shown in  FIG. 4 ,  FIG. 5  and  FIG. 6  can be varied and implemented by other circuit structure, for example but not limited to, interchanging the V CC  and the ground shown in all figures. 
     Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.

Technology Classification (CPC): 7