Patent Abstract:
Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an Nx1 MUX. The Nx1 MUX is controlled by the skew controller. The output of the Nx1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

Full Description:
TECHNICAL FIELD  
       [0001]     The present invention relates in general to board level transmission line drivers and receivers, and in particular, to methods for compensating for timing skew between differential data channels.  
       BACKGROUND INFORMATION  
       [0002]     Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.  
         [0003]     When using inter-chip high-speed signaling, noise and coupling between signal lines (cross talk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its compliment to a differential receiver. In this manner, noise and coupling affect both the signal and the compliment equally. The differential receiver only senses the difference between the signal and its compliment as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and cross talk have on signal quality. On the negative side, differential signaling increases pin count by a factor of two for each data line. Additionally, an empty wiring channel is usually added between each differential channel which further adds to the wiring inefficiency.  
         [0004]     The structure of a printed circuit board (PCB) is sometimes not homogeneous. It is common to find a weave structure on many laminates as shown in  FIG. 1 . Given the space between the components of a differential pair and the weave structure of PCBs, it is possible to find differential pairs with an orientation as shown in  FIG. 1  where the exemplary signal traces Data  103  and Data_b  105  do not have the same substrate configuration. In one case, the signal trace Data  103  has a dielectric substrate comprising the continuous fiberglass strand material  102 . In the other case, the signal trace Data_b has a dielectric substrate comprising fiberglass strands  101  in one direction and an epoxy fiberglass mix  104  in between the channels of fiberglass strands  101 . This results in the transmission lines formed by the signal traces having differing relative permittivities which results in the transmission lines having differing propagation delays.  
         [0005]     A differential pair having a signal and complement signal transmitted over matched transmission lines would have a received signal waveform substantially represented by the waveforms of  FIG. 2A  where the transition cross over points  203  and  204  are symmetrical. However, if the two transmission lines had different propagation delays, the resulting waveforms may look like the waveforms of  FIG. 2B  where the transition cross over points  203  and  204  are no longer symmetrical and occur at differing voltage levels resulting in timing skew between the two signals when detected in a differential receiver.  
         [0006]     With net lengths of tens of centimeters, differential skew delays due to PCB laminate weaves may approach tens of picoseconds. Presently transmission data rates of 10 gigabits per second means a bit width of only 100 picoseconds. Clearly, tens of picoseconds of in-pair timing skew for differential pairs is not negligible for these high data rates. In-pair differential skew may cause asymmetric crossover and aggravate common mode sensitivities. One solution that is been proposed is to use a diagonal trace pattern as shown in  FIG. 3  where signal traces Data  301  and Data_b  302  are run at a diagonal with respect to the orthogonal strands  101  and  102 . See U.S. Pat. No. 6,304,700 and U.S. Patent Application 2004/0181764. This solution allows both signal traces Data  301  and Data_b  302  to have an equal mix of substrate composition. While this may be an improvement of  FIG. 1 , adhering to this configuration may make wiring rules difficult.  
         [0007]     There is, therefore, a need for a signaling scheme that enables the skew between differential data channels to be compensated without complicating layout rules. The scheme must be programmable and easy to implement and modify.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention uses two single ended off-chip drivers (OCD) to implement differential signal by having each data path transmit a data signal and its complement. Each of the OCDs is preceded by a programmable delay element. The input to the delay elements are coupled to the output of a two-input multiplexer (MUX) that receives the data signal for the path and a common clock signal. Under control of a select signal, either a data signal or a common clock signal is coupled to the data path comprising a transmission lines over the non-homogeneous PCB substrate. Each of the transmission lines is terminated in a suitable terminator and received in one input of a differential receiver. The two inputs to the differential receiver are also coupled to a phase detector whose output is coupled to the input of a Nx1 MUX. Skew control logic generates the select signals for the driver side MUXes as well as the select signal for the receiver side Nx1 MUX. The output of the Nx1 MUX is coupled as a feedback error signal to the skew control logic in a single feedback channel which is used to align each differential data channel.  
         [0009]     To align the differential data channels, each differential data channel is selected in sequence by coupling the common clock signal to the drivers of the two transmission lines and selecting the phase detector for that channel as the output of the Nx1 MUX. The skew control logic then adjusts the delays in series with each driver until the phase detector output measures a predetermined amount of phase shift or delay error. Then a next differential data channel is selected and the process is repeated until all the delays for the differential data channels are set to minimize the inter-channel timing skew.  
         [0010]     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:  
         [0012]      FIG. 1  illustrates signal traces on a PCB with orthogonal strands of fiberglass;  
         [0013]      FIG. 2A  illustrates waveforms of ideal matched differential signals; and  
         [0014]      FIG. 2B  illustrates waveforms of differential signals with unequal delay causing timing skew;  
         [0015]      FIG. 3  illustrates a prior art diagonal signal trace pattern to reduce delay differences;  
         [0016]      FIG. 4  is a circuit diagram illustrating a current steering circuit for differential signaling;  
         [0017]      FIG. 5  is a circuit diagram illustrates a true-complement differential signaling;  
         [0018]      FIG. 6  is a circuit diagram illustrates a true-complement differential signaling with programmable delay according to embodiments of the present invention;  
         [0019]      FIG. 7  is a circuit diagram illustrates a true-complement differential signaling with programmable delay and selectable input data according to embodiments of the present invention;  
         [0020]      FIG. 8  is a circuit block diagram illustrating a system for aligning a N channel bus according to embodiments of the present invention;  
         [0021]      FIG. 9  is a circuit block diagram illustrating a phase detector output states according to embodiments of the present invention;  
         [0022]      FIG. 10  is a flow diagram of method steps employed to align N differential data channels according to embodiments of the present invention; and  
         [0023]      FIG. 11  is a block diagram a data processing system suitable for practicing embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0024]     In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.  
         [0025]     Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. In the following, data channel refers to a single transmission path and differential data channel refers to a pair of transmission paths. Each differential data channel comprises transmission paths for a logic signal and the complement of the logic signal coupled to a single differential receiver.  
         [0026]      FIG. 4  is a circuit diagram of a current steering circuit for realizing differential signaling. Current source  409  supplies a constant current to field effect transistors (FETs)  407  and  408 . When Data  103  is a logic one and Data_b  105  is a logic zero, FET  407  is turned ON and FET  408  is turned OFF. The current  409  flows through transmission line  404  and resistor  403  and pulls node  413  to a logic zero. Since FET  408  is OFF, resistor  402  and power supply voltage  411  pulls node  414  to a logic one. Therefore, the output of differential receiver  401  is a logic one corresponding to the value of Data  103 . When Data_b  105  is a logic one and Data  103  is a logic zero, the input logic states of nodes  413  and  414  reverse. The current  409  now flows through transmission line  405  and resistor  402  and pulls node  414  to a logic zero. FET  407  is OFF, thus resistor  403  and power supply voltage  411  pulls node  413  to a logic one. In this case, the output of differential receiver  401  is a logic zero corresponding to the value of Data_b  105 .  
         [0027]      FIG. 5  is a circuit diagram of true-complement data transmission using single ended drivers to realize differential signaling. Data  103  is coupled to off-chip driver (OCD)  501  and Data_b  105  is coupled to OCD  502 . The output of OCD  501  drives transmission line  404  and output of OCD  502  drives transmission line  405 . The transmission lines  404  and  405  are terminated in a compatible termination network  503  coupled to nodes  413  and  414  and the inputs of receiver  401 . Data  103  transmits the true state of a logic signal and Data_b  105  transmits the complement of the logic signal. The circuit configuration  500  is used for differential signaling because single ended OCDs are generally easier to implement than true differential drivers.  
         [0028]      FIG. 6  is a circuit diagram of true-complement data transmission using single ended drivers where programmable delay elements  601  and  602  are inserted between the input signals Data  103  and Data_b  105 , respectively. Programming signals  603  and  604  are used to set the insertion delay in each data channel. In this manner, the skew between the data channel transmitting Data  103  and the data channel transmitting Data_b  105  is adjusted so the signals arriving at nodes  413  and  414  may be phase or transition aligned.  
         [0029]      FIG. 7  is a circuit diagram of the circuit in  FIG. 6  with the addition of a multiplexer (MUX) in each differential data channel to allow either a clock signal  704  or the data signals Data  103  and Data_b  105  to be transmitted to differential receiver  401 . If the data channels are to be aligned, then data select  701  selects clock  704  as the input to both data channels. Since the same signal is transmitted over both data channels, then the inherent delay differences may be compensated by adjusting programmable delay elements  601  and  602 . Initially, program signal  603  and delay select  604  may be programmed to set programmable delay elements  601  and  602  to one-half their maximum delays. This allows delay to be added or subtracted to compensate for either leading or lagging phase shifts between the data channels. The common clock signals are transmitted by OCDs  501  and  502  through transmission lines  404  and  405  respectively. Termination network  503  is configured to be compatible with the transmission lines and the drivers and receivers. The phase shift between the signals arriving at nodes  413  and  414  represents the time delay difference between the two data channels. Unless compensated for by adjusting the relative delays of programmable delay elements  601  and  602 , the data channel timing skew will effect the signal quality of the signal generated on the output of differential receiver  401 .  
         [0030]      FIG. 8  is a block diagram of a system for aligning N differential channels according to embodiments of the present invention. Skew controller  801  controls the channel skew alignment process. When align channels command  807  transitions to a logic one, skew controller  801  starts the alignment process by selecting differential data channel  1  for the alignment process. Control signal  701  selects clock  704  as the input to programmable delay elements  601  and  602  using MUXes  702  and  703 . Likewise, control programming signals  603  and  604  set programmable delay elements  601  and  602  to a portion of their maximum delay (e.g., one-half). OCDs  501  and  502  drive the common clock signal  704  over transmission lines  404  and  405  where they are terminated by termination network  503  at nodes  413  and  414 . Phase detector  803  generates logic states corresponding to the phase differences between the signals arriving at nodes  413  and  414 . Skew controller  801  selects the output of phase detector  803  as the phase error feedback signal  805  using MUX  802 . Depending on the number of outputs (P) necessary to determine the phase between the signals at nodes  413  and  414 , MUX  802  is a PxN by P MUX. In one embodiment, phase detector  803  has two logic outputs with four logic states, thus MUX  802  would be a 2Nx2 MUX.  
         [0031]     Depending on the “value” of the phase error feedback signal  805 , skew controller adjusts the delays of programmable delay elements  601  and  602  until the phase error feedback  805  indicates that the timing skew between the data channels in differential data channel  1  is within a predetermined minimum value. When this value is reached, the program values of program signals  603  and  604  are latched or held while the next channel is selected for alignment. Alignment continues until differential data channel N is aligned using phase detector  804 . When the alignments are completed, then skew controller  801  signals to the system (e.g., system  1300 ) that bus alignment is complete and the system can switch to operation mode wherein actual data signals (e.g., Data  103  and Data_b  105 ) are transmitted between the driver side and the receiver.  
         [0032]      FIG. 9  is a block diagram of an exemplary phase detector  803  illustrating the logic states of the two outputs PD_out  904  and PD_out  905 . Phase detectors are known in the art and may be tailored to meet the requirements of skew controller  801 . In one embodiment, phase detector  803  has two digital outputs representing four logic states as follows:  
         [0033]     State 1: first delay signal  901  lags second delay signal  902  and PD_out  904  is a logic 1 and PD_out  905  is a logic 0.  
         [0034]     State 2: first delay signal  901  leads second delay signal  902  and PD_out  904  is a logic 0 and PD_out  905  is a logic 1.  
         [0035]     State 3: first delay signal  901  is in phase with second delay signal  902  and PD_out  904  is a logic 1 and PD_out  905  is a logic 1.  
         [0036]     State 4: the phase difference between first delay signal  901  and second delay signal  902  is indeterminate and PD_out  904  is a logic 0 and PD_out  905  is a logic 0.  
         [0000]     It is understood that other phase detector states may be used that are compatible with a skew controller  801  and still be within the scope of the present invention.  
         [0037]      FIG. 10  is a flow diagram of method steps used in embodiments of the present invention. In step  1001 , skew controller  801  receives a align channels command  807  from the system employing embodiments of the present invention. In step  1002 , controller  801  selects the differential data channel  1  to align. In step  1003 , the clock  704  is selected as the input to both of the data channels and phase detector  803  is selected to provide the phase error feedback signal  805 . In step  1004 , the delays of programmable delay elements  601  and  602  are set to one-half their maximum delay. The phase error is measured in step  1005  and in step  1006 , the delays in programmable delay elements  601  and  602  are adjusted until phase error feedback indicates the phase error is within a predetermined minimum value. The program inputs setting the delays in the preceding data channels are latched. In step  1007 , the next differential data channel is selected. In step  1008 , a test is done to determine if all channels have been aligned. If all channels have been aligned, then in step  1009  a functional mode is resumed by selecting Data  103  and Data_b  105  as the transmitted data signals. If all the differential data channels have not been aligned, then a branch is taken back to step  1003 .  
         [0038]      FIG. 11  is a high level functional block diagram of a representative data processing system  1100  suitable for practicing the principles of the present invention. Data processing system  1100  includes a central processing system (CPU)  1110  operating in conjunction with a system bus  1112 . System bus  1112  operates in accordance with a standard bus protocol, such as the ISA protocol, compatible with CPU  1110 . CPU  1110  operates in conjunction with electronically erasable programmable read-only memory (EEPROM)  1116  and random access memory (RAM)  1114 . Among other things, EEPROM  1116  supports storage of the Basic Input Output System (BIOS) data and recovery code. RAM  1114  includes, DRAM (Dynamic Random Access Memory) system memory and SRAM (Static Random Access Memory) external cache. I/O Adapter  1118  allows for an interconnection between the devices on system bus  1112  and external peripherals, such as mass storage devices (e.g., a hard drive, floppy drive or CD/ROM drive), or a printer  1140 . A peripheral device  1120  is, for example, coupled to a peripheral control interface (PCI) bus, and I/O adapter  1118  therefore may be a PCI bus bridge. User interface adapter  1122  couples various user input devices, such as a keyboard  1124  or mouse  1126  to the processing devices on bus  1112 . Display  1138  which may be, for example, a cathode ray tube (CRT), liquid crystal display (LCD) or similar conventional display units. Display adapter  1136  may include, among other things, a conventional display controller and frame buffer memory. Data processing system  1100  may be selectively coupled to a computer or telecommunications network  1141  through communications adapter  1134 . Communications adapter  1134  may include, for example, a modem for connection to a telecom network and/or hardware and software for connecting to a computer network such as a local area network (LAN) or a wide area network (WAN). CPU  1110  and other components of data processing system  1100  may contain logic circuitry in two or more integrated circuit chips that are coupled with off-chip differential signaling. The timing skew between data channels of the differential data channels may be aligned using the system and method according to embodiments of the present invention.  
         [0039]     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Classification (CPC): 7