Patent Abstract:
A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Full Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwan Application Serial Number 96126042, filed Jul. 17, 2007, which is herein incorporated by reference. 
     BACKGROUND 
     1. Field of The Invention 
     The present invention relates to a technique of manufacturing a semiconductor device. More particularly, the present invention relates to a method of making a planar-type bottom electrode for semiconductor devices. 
     2. Description of Related Art 
     For applications of semiconductor devices, capacitors have been extensively used for applications related to data storage. Taking dynamic random access memory (DRAM) for example, a DRAM contains a plurality of memory unit cells for data storage. Each memory unit cell comprises a capacitor and a transistor to store data. 
     Planar-type capacitors are one kind of capacitor structure that is currently used. A planar-type capacitor forms bottom electrodes, dielectrics and plate electrodes in one hole of a dielectric layer. Compared with concave type capacitors, the planar-type capacitors have larger space to receive thicker dielectric (such as high-k dielectrics) and the plate electrode. Thicker dielectrics help reduce current leakage of capacitor. 
     Using high-k dielectrics may improve capacitance of the memory cell unit, and Equivalent Oxide Thickness (EOTs) of this kind of materials has an inverse proportional relationship to its k value. In other words, when using a dielectric with a higher dielectric constant to replace a dielectric with a lower dielectric constant, the higher dielectric may deposit a thicker film keeping the same capacitance so as to reduce the degree of current leakage. 
     However, with the feature size of the devices is continuously reduced to a desired size, concave type capacitors have reached their manufacturing limitations, i.e. the hole in the dielectric layer can not provide sufficient space to receive the bottom electrodes, the dielectrics and the plate electrodes. 
     Therefore, there is a need to provide an improved method of making capacitors to provide enough space to receive the bottom electrodes, the dielectrics and the plate electrodes to mitigate or obviate the aforementioned problems. 
     SUMMARY 
     An object of the present invention is to provide a method of making capacitor bottom electrodes for semiconductor devices. The capacitor provides sufficient space to receive and hold the bottom electrodes, dielectrics and the plate electrodes. 
     An embodiment of a method in accordance with the present invention forms a sacrificial layer structure on a substrate. The next step defines a plurality of first trenches in the sacrificial layer structure, wherein the first trenches are arranged in a first direction. Insulating material fills the first trenches to form an insulating layer in the first trenches. 
     The next step defines a plurality of second trenches in the sacrificial layer structure, wherein the second trenches are arranged in a second direction, such that the second trenches cross the first trenches. A bottom electrode material fills the second trenches to form a bottom electrode layer in the second trenches, wherein the insulating layers separate respectively the bottom electrode layers. 
     The sacrificial layer structure is removed, which defines respectively receiving rooms between neighboring bottom electrode layers and neighboring insulating layers. 
     Another embodiment of a method in accordance with the present invention forms a plurality of insulating layers on a substrate wherein the insulating layers are arranged in a first direction. A plurality of bottom electrode layers forms on the substrate wherein the bottom electrode layers are arranged in a second direction, the second direction intercrosses the first direction. The insulating layers separate respectively the bottom electrode layers to define respectively receiving rooms between neighboring bottom electrode layers and neighboring the insulating layers. 
     According to the embodiments in accordance with the present invention, applying the present invention has some advantages as follows. 
     With the receiving rooms defined by the insulating layers and the bottom electrode layers, there is sufficient space for each receiving room to receive and hold the dielectrics and the plate electrodes. The integration of the semiconductor device is improved. The demand of smaller feature size of the device is met. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings wherein: 
         FIG. 1   a  is a schematic top view of a semiconductor device with a first embodiment of a method in accordance with the present invention when first upper trenches and first trenches are defined in a sacrificial layer structure; 
         FIG. 1   b  is a schematic section view of the device along line AA in  FIG. 1   a;    
         FIG. 1   c  is a schematic section view of the device along line aa in  FIG. 1   a;    
         FIG. 2   a  is a schematic top view of the device in  FIG. 1   a  when a next step is performed; 
         FIG. 2   b  is a schematic section view of the device along line AA in  FIG. 2   a;    
         FIG. 2c  is a schematic section view of the device along line aa in  FIG. 2   a;    
         FIG. 3   a  is a schematic top view of the device in  FIG. 2   a  when a next step is performed; 
         FIG. 3   b  is a schematic section view of the device along line AA in  FIG. 3   a;    
         FIG. 3   c  is a schematic section view of the device along line BB in  FIG. 3   a;    
         FIG. 4   a  is a schematic top view of the device in  FIG. 3   a  when a next step is performed; 
         FIG. 4   b  is a schematic section view of the device along line BB in  FIG. 4   a;    
         FIG. 4   c  is a schematic section view of the device along line bb in  FIG. 4   a;    
         FIG. 5   a  is a schematic top view of the device in  FIG. 4   a  when a next step is performed; 
         FIG. 5   b  is a schematic section view of the device along line BB in  FIG. 5   a;    
         FIG. 5   c  is a schematic section view of the device along line bb in  FIG. 5   a;    
         FIG. 6   a  is a schematic top view of the device in  FIG. 5   a  when a next step is performed; 
         FIG. 6   b  is a schematic section view of the device along line BB in  FIG. 6   a;    
         FIG. 6   c  is a schematic section view of the device along line bb in  FIG. 6   a;    
         FIG. 7   a  is a schematic top view of the device in  FIG. 6   a  when a next step is performed; 
         FIG. 7   b  is a schematic section view of the device along line BB in  FIG. 7   a;    
         FIG. 7   c  is a schematic section view of the device along line bb in  FIG. 7   a;    
         FIG. 8   a  is a schematic top view of a semiconductor device with a second embodiment of a method in accordance with the present invention when first upper trenches and first trenches are defined in a sacrificial layer structure and an insulating material fills the trenches; 
         FIG. 8   b  is a schematic section view of the device along line AA in  FIG. 8   a;    
         FIG. 8   c  is a schematic section view of the device along line aa in  FIG. 8   a;    
         FIG. 9   a  is a schematic top view of the device in  FIG. 8   a  when a next step is performed; 
         FIG. 9   b  is a schematic section view of the device along line AA in  FIG. 9   a;    
         FIG. 9   c  is a schematic section view of the device along line BB in  FIG. 9   a;    
         FIG. 10   a  is a schematic top view of the device in  FIG. 9   a  when a next step is performed; 
         FIG. 10   b  is a schematic section view of the device along line AA in  FIG. 10   a;    
         FIG. 10   c  is a schematic section view of the device along line BB in  FIG. 10   a;    
         FIG. 11   a  is a schematic top view of the device in  FIG. 10   a  when a next step is performed; 
         FIG. 11   b  is a schematic section view of the device along line AA in  FIG. 11   a;    
         FIG. 11   c  is a schematic section view of the device along line aa in  FIG. 11   a;    
         FIG. 12   a  is a schematic top view of the device in  FIG. 11   a  when a next step is performed; 
         FIG. 12   b  is a schematic section view of the device along line AA in  FIG. 12   a;    
         FIG. 12   c  is a schematic section view of the device along line aa in  FIG. 12   a;    
         FIG. 13   a  is a schematic top view of the device in  FIG. 12   a  when a next step is performed; 
         FIG. 13   b  is a schematic section view of the device along line AA in  FIG. 13   a;    
         FIG. 13   c  is a schematic section view of the device along line aa in  FIG. 13   a;    
         FIG. 14   a  is a schematic top view of the device in  FIG. 13   a  when a next step is performed; 
         FIG. 14   b  is a schematic section view of the device along line AA in  FIG. 14   a;    
         FIG. 14   c  is a schematic section view of the device along line aa in  FIG. 14   a;    
         FIG. 15   a  is a schematic top view of the device in  FIG. 14   a  when a next step is performed; 
         FIG. 15   b  is a schematic section view of the device along line AA in  FIG. 15   a ; and 
         FIG. 15   c  is a schematic section view of the device along line aa in  FIG. 15   a.    
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     An embodiment of a method of making capacitor bottom electrodes for semiconductors in accordance with the present invention may be applied to semiconductor devices, such as DRAM. The following description provides an illustrative example of making capacitor bottom electrodes of DRAM. A DRAM comprises a plurality of storage nodes. Each storage node needs capacitors. The capacitor comprises bottom electrodes, dielectrics and plate electrodes. 
     Refer to  FIG. 1   a ,  FIG. 1   b  and  FIG. 1   c . A first embodiment in accordance with the present invention comprises forming a sacrificial layer structure  200  on a substrate  100 . An etching stop layer  300  is formed between the sacrificial layer structure  200  and the substrate  100 . The substrate  100  contains storage node contacts  310 . The sacrificial layer structure  200  comprises a lower layer  210  and an upper layer  220 . The lower layer  210  may be a silicon oxide layer, such as SiO 2 . The upper layer  220  may be polysilicon. 
     The next step is to define multiple first trenches  230  in the sacrificial layer structure  200 . The first trenches  230  are arranged in a first direction. The first trenches  230  are defined by a mask layer  400  (such as a photo resistant mask) and a hard mask layer  401  that pattern the upper layer  220  to form multiple first upper trenches  231 . A dry etching process may form the first upper trenches  231  in the upper layer  220 . In the embodiment, the first upper trenches are tapered trenches, i.e. the width of the trench is gradually narrowed along the direction towards the lower layer  210 . After the first upper trenches  231  are formed, a dry etching process through the first upper trenches  231  may form the first trenches  230  in the lower layer  210 . Thus, tapered first upper trenches  231  can generate smaller line widths for the first trenches  230  than the line widths provided by the reticles. The mask layer  400  may be stripped after the first trenches  230  have been defined. 
     Refer to  FIG. 2   a ,  FIG. 2   b  and  FIG. 2   c . The next step removes the upper layer  220  of the sacrificial layer structure  200 . A wet etching process may remove the upper layer  220 . 
     Refer to  FIG. 3   a ,  FIG. 3   b  and  FIG. 3   c . An insulating material fills the first trenches  230 . The insulating material is partially etched (etching back) to reduce its height in the first trenches  230  and to form an insulating layer  110  in each of the first trenches  230 . Therefore, the height of the insulating layer  110  is smaller than the depth of the first trench  230  because of the etching back process. The insulating material may be silicon nitride. A protective layer  500  is deposited on the lower layer  210  after the etching back process. The protective layer  500  partially fills the first groves  230  and may be polysilicon (Poly Si). 
     Further refer to  FIG. 4   a ,  FIG. 4   b  and  FIG. 4   c . Multiple second upper trenches  241  are defined in the protective layer  500  to form multiple second trenches  240  in the lower layer  210  of the sacrificial layer structure  200  (as shown in  FIG. 5   c ). The second trenches  240  are arranged in a second direction such that the second trenches intersect the first trenches. In the embodiment, the first direction is substantially perpendicular to the second direction. 
     The process of defining the second trenches  240  is similar to that of defining the first trenches  230 . Using a mask layer  410  (such as a photo resistant layer) patterns the protective layer  500  so as to form the second upper trenches  241  in the protective layer  500 . The mask layer  410  may be stripped after the second upper trenches  241  are defined in the protective layer  500  with a dry etching process. In the embodiment, the second upper trenches  241  are tapered trenches, i.e. the width of the trench is gradually narrowed along the direction towards the lower layer  210 . 
     Refer to  FIG. 5   a ,  FIG. 5   b  and  FIG. 5   c . Etching the lower layer  210  through the second upper trenches  241  defines the second trenches  240  in the lower layer  210  with the dry etching process. Likewise, tapered second upper trenches  241  generate smaller line widths for the second trenches  240  than the line width provided by the reticles. 
     Refer to  FIG. 6   a ,  FIG. 6   b  and  FIG. 6   c . An electrode material fills the second trenches  240 . The electrode material is partially etched (etching back) to reduce its height in the second trenches  240  and form a bottom electrode layer  120  in each of the second trenches  240 . The insulating layers  110  respectively separate the bottom electrode layer  120 . Therefore, the height of the bottom electrode layer  120  is smaller than the depth of the second trench  240  because of the etching back process. 
     Refer to  FIG. 7   a ,  FIG. 7   b  and  FIG. 7   c . The lower layer  210  of the sacrificial layer structure  200  and the protective layer  500  may be stripped by wet etching process. The removal of the lower layer  210  forms a receiving room  130  between a pair of neighboring insulating layers  110  and a pair of neighboring bottom electrode layers  120 . The receiving room  130  may receive and hold the dielectrics and the plate electrodes. 
     Refer to  FIG. 8   a ,  FIG. 8   b  and  FIG. 8   c . A second embodiment of a method of making a capacitor bottom electrode provides alternative steps when the first trenches  230  and the first upper trenches  231  have been defined as shown in  FIG. 1   a  to  FIG. 1   c . An insulating material layer  111  may be deposited on the sacrificial layer structure  200  and fills simultaneously the first trenches  230  and the first upper trenches  231  so as to form an insulating layer  110  in each of the first trenches  230 . The insulating material may be nitride. 
     Refer to  FIG. 9   a ,  FIG. 9   b  and  FIG. 9   c . The next step defines multiple second trenches  240  in the lower layer  210  of the sacrificial layer structure  200  (as shown in  FIG. 11   b ). The second trenches  240  are arranged in a second direction such that the second trenches intersect the first trenches. In the embodiment, the first direction is substantially perpendicular to the second direction. 
     Further refer to  FIG. 10   a ,  FIG. 10   b  and  FIG. 10   c . The process of defining the second trenches  240  is similar to that of defining the first trenches  230 . Using a mask layer  410  (such as a photo resist layer) and a bottom anti reflective coating (BARC) layer  411  patterns the insulating material layer  111  so as to form the second upper trenches  241  in the insulating material layer  111 . The second upper trenches  241  are tapered trenches, i.e. the width of the trench is gradually narrowed along the direction towards the lower layer  210 , and expose partially the upper layer  220  (Poly-Si layer) under the insulating material layer  111 . The mask layer  410  may be stripped after the second upper trenches  241  are defined in the insulating material layer  111  with dry etching process. 
     Refer to  FIG. 11   a ,  FIG. 11   b  and  FIG. 11   c . The second trenches  240  may be defined by etching the upper layer  220  and the lower layer  210  with a dry etching process through the second upper trenches  241 . 
     Refer to  FIG. 12   a ,  FIG. 12   b  and  FIG. 12   c . The next step removes the rest silicon oxide and poly silicon inside the second trenches  240  (i.e. the silicon oxide and poly silicon of the upper layer  220  and the lower layer  210  reside on the sidewalls of the insulating layer  110 ) by a wet etching process. 
     Refer to  FIG. 13   a ,  FIG. 13   b  and  FIG. 13   c . A bottom electrode material  121  fills the second trenches  240  so as to form a bottom electrode layer  120  in the second trenches  240 . 
     Refer to  FIG. 14   a ,  FIG. 14   b  and  FIG. 14   c . The bottom electrode material  121  is etched (etching back). The insulating layer  110  is partially etched to reduce its height in the first trenches  230 . The insulating layer  100  separates respectively the bottom electrode layer  120 . 
     Refer to  FIG. 15   a ,  FIG. 15   b  and  FIG. 15   c . The rest silicon oxide and polysilicon (i.e. the upper layer  220  and the lower layer  210  of the sacrificial layer structure  200  between the insulating layer  110  and the bottom electrode layer  120 ) is removed. The removal of the upper layer  220  and the lower layer  210  may use wet etching process, and forms a receiving room  130  between a pair of the insulating layers  110  and a pair of the bottom electrode layers  120 . The receiving room  130  may receive and hold the dielectrics and the plate electrodes. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Technology Classification (CPC): 7