Patent Abstract:
In many high voltage circuits, it often needs to shift the logic voltage level to keep the circuit normal operation. In the class-D amplifier circuitry, it needs to shift the voltage level of pulse width modulation (PWM) signal to control the connecting of different power switches. In other applications, such as a driver to drive amplifier of an audio device, it also needs a level shift circuit to maintain the circuitry in normal voltage operation. Therefore, this invention is to provide a novel level shift circuit with high performance, low cost and low power dissipation characteristics.

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a level shift circuit, and more particularly, to the level shift circuit that has a low power dissipation and is realized in a more simplified way.  
         [0003]     2. Description of Related Art  
         [0004]     As shown in  FIG. 1 , one integrated circuit (IC) could exist different supply voltages for different applications, a level shift circuit  100  is required between two circuitries with different supply voltages to adjust the level of logic signals so as to maintain the normal operation of the circuitry.  FIG. 2  is a diagram showing the signal relation between an input signal S 1  and an output signal S 2  of the level shift circuit  100  in  FIG. 1 . As shown in  FIG. 2 , after the output signal S 2  passes the level shift circuit  100 , its logic value does not change, but its voltage level is different. The voltage level of V H1  is shifted to the voltage level of V H2 , and the voltage level of V L1  is shifted to the Voltage level of V L2 .  
         [0005]     In U.S. Pat. Nos. 5,057,721, 5,351,182, 6,362,679, 6,362,831 and 6,501,321, a level shift circuit making use of current and resistance to generate levels is disclosed. The level shift circuit using this method to generate levels will consume a large amount of power and require a complicated circuit to ensure the reliability and performance.  
         [0006]     Besides, U.S. Pat. No. 6,476,672 discloses a level shift circuit of low power dissipation, high reliability and high performance, but it needs to generate four complicated control signals to achieve the function of level shifting.  
       SUMMARY OF THE INVENTION  
       [0007]     It is an object of the present invention to provide a level shift circuit of high performance, high reliability, low power dissipation, more simplified realization and low cost.  
         [0008]     It is an object of the present invention to provide a level shift circuit for driving an audio device.  
         [0009]     According to an exemplary embodiment of the claimed invention, a level shift circuit is disclosed. The level shift circuit comprises a first voltage level transfer unit, for transferring the voltage level of a first input signal from a first voltage level to a second voltage level and outputting a first level transferred control signal; a second voltage level transfer unit, for transferring the voltage level of a second input signal from the first voltage level to the second voltage level and outputting a second level transferred control signal; and a control block circuit coupled to the first voltage level transfer unit and the second voltage level transfer unit, for outputting an output signal according to the first level transferred control signal and the second level transferred control signal; wherein the first input signal and the second input signal are inversed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:  
         [0011]      FIG. 1  is a diagram showing the function of a level shift circuit;  
         [0012]      FIG. 2  is a clock diagram of a level shift circuit;  
         [0013]      FIG. 3  is a circuit diagram of a level shift circuit according to a first embodiment of the present invention;  
         [0014]      FIG. 4  is a timing diagram of all the signals in  FIG. 3 ;  
         [0015]      FIG. 5  is a circuit diagram of the control block circuit in  FIG. 3  according to an embodiment of the present invention;  
         [0016]      FIG. 6  is a circuit diagram of a level shift circuit according to a second embodiment of the present invention;  
         [0017]      FIG. 7  is a timing diagram of all the signals in  FIG. 6 ; and  
         [0018]      FIG. 8  is a circuit diagram of the control block circuit in  FIG. 6  according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]      FIG. 3  is a circuit diagram of a level shift circuit  300  according to a first embodiment of the present invention. The level shift circuit  300  comprises a first voltage level transfer unit  316 , a second voltage level transfer unit  318 , a control block circuit  310 , a first PMOS pull-up transistor  312  and a second PMOS pull-up transistor  314 . The first voltage level transfer unit  316  further comprises a NMOS transistor  302  and a PMOS transistor  304 , wherein the gate of NMOS transistor  302  receives a first input signal which is operated in first voltage level (Vdd and Vss), the source of the NMOS transistor  302  is coupled to the supply voltage Vss, and the drain and gate of PMOS transistor  304  are respectively coupled to the NMOS transistor  302  and supply voltage VL for outputting the level transferred control signal X 1  (operated in VH and VL level). On the other hand, the second voltage level transfer unit  318  comprises NMOS transistor  306  and PMOS transistor  308 , wherein the gate of NMOS transistor  306  receives a second input signal which operated in first voltage level (Vdd and Vss), the source of the NMOS transistor  306  is coupled to the supply voltage Vss, and the drain and gate of PMOS transistor  308  are respectively coupled to the NMOS  306  transistor and supply voltage VL for outputting the level transferred control signal X 2  (operated in VH and VL level). It is noticed that the first input signal In and the second input signal InB are inversed signal. Furthermore, the process of first voltage level transfer unit  316  and second voltage level transfer unit  318  are implemented by high-voltage process.  
         [0020]     The function of the level shift circuit  300  is to shift the voltage level of input signal In from first voltage level to second voltage level ((Vss and Vdd level) to (VL and VH level)). As shown in  FIG. 3 , when the NMOS transistor  302  receives the first input signal In, the PMOS transistor  304  generates a level transferred control signal X 1  to the control block circuit  310 . On the other hand, when the NMOS transistor  306  receives the second input signal InB, the PMOS transistor  308  also generates a level transferred control signal X 2  to control block circuit  310 . It is obvious that the voltage level of the two control signals X 1  and X 2  have been shifted to the second voltage level (VH and VL) for controlling a control block circuit  310 , wherein the control block circuit  310  coupled between VH and VL. When the control block circuit  310  receives the first control signal X 1  and the second control signal X 2 , an output signal Out will be generated. The level of the output signal Out is the voltage between VH and VL, and the logic value of the output signal Out corresponds to the first input signal In. Additionally, after the control block circuit  310  receives the first control signal X 1  and the second control signal X 2 , two operation signals Y 1  and Y 2  will be generated, which is to adjust the voltage level of the first control signal X 1  and the second control signal X 2  through transistors  312  and  314 , respectively.  
         [0021]      FIG. 4  is a diagram of all the signals in  FIG. 3 . As shown in  FIG. 4 , when the first input signal In changes from 0 (Vss) to 1 (Vdd), the first control signal X 1  will be pulled down to 0 (VL). Since the control block circuit  310  detects the first control signal X 1  pulled down, it will set Y 2  to 0 (VL). At this time, the output signal Out will be set to 1 (VH) so as to make the output signal correspond to the first input signal with logic value (1). On the other hand, when Y 2  is pulled down to 0 (VL), the PMOS pull-up transistor  314  will pull up the second control signal X 2 . At this time, due to Y 1  is 1 (VH) and InB already becomes 0 (VL), only the parasitic capacitances of the transistors  302 ,  304 ,  306  and  308  are charged and discharged, hence having a very low power dissipation. When the second control signal X 2  is charged to 1 (VH), the control block circuit  310  will pull up Y 2  to 1 (VH) so as to stop the transistor  314  to pull up X 2 . On the contrary, when the first input signal In changes from 1 (Vdd) to 0 (Vss), the operations of the level shift circuit  300  are reversed to mentioned above, therefore the further detail description is omitted for brevity.  
         [0022]      FIG. 5  is a circuit diagram of the control block circuit  500  in  FIG. 3  according to an embodiment of the present invention. As shown in  FIG. 5 , when the first input signal In is 1 (Vdd), the signal st ought to be 1 (VH). When both the first control signal X 1  and the second control signal X 2  are 0 (VL), the signal rs is set to 1 (VH). One of st and stb is necessarily 1 (VH). If stb is 1 (VH), then Y 1  is 0 (VL), and X 1  is pulled up to 1 (VH). Subsequently, rst becomes 1 (VH) to set st to 1 (VH), and rs becomes 0 (VL). At this time, because In is 1 (Vdd), X 1  will be pulled down to 0 (VL) again, and rs will be set to 1 (VH) again, and Y 2  will be set to 0 (VL). After the second control signal X 2  is set to 1 (VH), Y 1  and Y 2  will become 1 (VH) again, waiting for the next time of change of In. At this time, the circuit is in the proper state. This shows that the circuit itself can restore to the correct state.  
         [0023]      FIG. 6  is a circuit diagram of a level shift circuit  600  according to a second embodiment of the present invention. The level shift circuit  600  comprises a first voltage level transfer unit  616 , a second voltage level transfer unit  618 , a control block circuit  610 , a first NMOS pull-down transistor  612  and a second NMOS pull-down transistor  614 . The first voltage level transfer unit  616  further comprises PMOS transistor  602  and NMOS transistor  604 , wherein the gate of PMOS transistor  602  receives a first input signal which is operated in first voltage level (Vdd and Vss), the source of the PMOS transistor  602  is coupled to the supply voltage Vdd, and the drain and gate of NMOS transistor  604  are respectively coupled to the PMOS transistor  602  and supply voltage VH for outputting the level transferred control signal X 1  (operated in VH and VL level). On the other hand, the second voltage level transfer unit  618  comprises PMOS transistor  606  and NMOS transistor  608 , wherein the gate of PMOS transistor  606  receives a second input signal which is operated in first voltage level (Vdd and Vss), the source of the PMOS transistor  606  is coupled to the supply voltage Vdd, and the drain and gate of NMOS transistor  608  are respectively coupled to the PMOS  606  transistor and supply voltage VH for outputting the level transferred control signal X 2  (operated in VH and VL level). It is noticed that the first input signal In and the second input signal InB are inversed signal. Furthermore, the process of first voltage level transfer unit  616  and second voltage level transfer unit  618  is implemented by high-voltage process.  
         [0024]     As the first embodiment, the function of the level shift circuit  600  is to shift the voltage level of input signal In from first voltage level to second voltage level ((Vss and Vdd level) to (VL and VH level)). As shown in  FIG. 6 , when the PMOS transistor  602  receives the first input signal In, the NMOS transistor  604  generates a level transferred control signal X 1  to the control block circuit  610 . On the other hand, when the PMOS transistor  606  receives the second input signal InB, the PMOS transistor  608  also generates a level transferred control signal X 2  to control block circuit  610 . It is obvious that the voltage level of the two control signals X 1  and X 2  have been shifted to the second voltage level (VH and VL) for controlling a control block circuit  310 , wherein the control block circuit  610  is coupled between VH and VL. When the control block circuit  610  receives the first control signal X 1  and the second control signal X 2 , an output signal Out will be generated. The level of the output signal Out is also between VH and VL, and the logic value of the output signal Out corresponds to the first input signal In. Additionally, after the control block circuit  610  receives the first control signal X 1  and the second control signal X 2 , two operation signals Y 1  and Y 2  will be generated, which for adjusting the voltage level of the first control signal X 1  and the second control signal X 2  through transistors  612  and  614 , respectively.  
         [0025]      FIG. 7  is a timing diagram of all the signals in  FIG. 6 . As shown in  FIG. 7 , when the first input signal In changes from 1 (Vdd) to 0 (Vss), the first control signal X 1  will be pulled up to 1 (VH) by NMOS transistor  604 . Accordingly, after the control block circuit  610  detects that the first control signal X 1  being pulled up, the control block circuit  610  will set Y 2  to 1 (VH). At this time, the output signal Out will be set to 0 (VL) so as to make the output signal correspond to the first input signal with logic value (0). On the other hand, When Y 2  is pulled up to 1 (VH), the NMOS pull-down transistor  614  will pull down the second control signal X 2 . At this time, due to Y 1  is 0 (VL) and InB already becomes 1 (VH), only the parasitic capacitances of the transistors  602 ,  604 ,  606  and  608  are charged and discharged, hence having a very low power dissipation. When the second control signal X 2  is discharged to 0 (VL), the control block circuit  610  will pull down Y 2  to 0 (VL) so as to stop the transistor  614  to pull down X 2 . On the contrary, when the first input signal In changes from 0 (Vdd) to 1 (Vss), the operations of the level shift circuit  600  are reverse to mentioned above, therefore the further detail description is omitted for brevity.  
         [0026]      FIG. 8  is a circuit diagram of the control block circuit  800  in  FIG. 6  according to an embodiment of the present invention. The control block circuit  800  can accomplish the functions of the signals in  FIG. 7 . Besides, when the signal is at the initial state or is erroneous, the circuit also has the function of restoring to the correct state by itself.  
         [0027]     Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.

Technology Classification (CPC): 7