Patent Abstract:
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near f T , the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of application Ser. No. 11/243,825, filed Oct. 5, 2005, now U.S. Pat No. 7,190,736, issued Mar. 13, 2007, which is a continuation of application Ser. No. 09/943,968, filed Aug. 30, 2001, which is now U.S. Pat. No. 6,956,908, issued Oct. 18, 2005. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to the timing of clock and data signals in integrated circuits. More specifically, the invention relates to simultaneous transmission of digital data and clock signals to eliminate skewing of the data and clock signals with respect to each other. 
   2. State of the Art 
   Digital integrated circuits typically include multiple logic elements, with the timing of operation of each logic element controlled by a clock signal. It is common for an integrated circuit chip to have one central clock generator, with the signal from the clock generator being distributed around the integrated circuit via clock-line interconnects. An important consideration in the design of digital integrated circuits is the timing of the arrival of clock and data signals at various logic elements. 
   Variation in clock signal arrival time is referred to as clock skew. A variety of techniques have been used to provide clock connections that are symmetrical and all of the same length in order to minimize clock skew at the various logic elements, including, for example, the methods of Yip and Carrig. See, K. Yip, “Clock tree distribution: balance is essential for a deep-submicron ASIC design to flourish,” IEEE Potentials, vol. 16, no. 2, pp. 11-14, April-May, 1997; and K. M. Carrig et al., “Clock methodology for high-performance microprocessors,” Proc. Custom Integrated Circuits Conference, Santa Clara, Calif., pp. 119-122, May 5-8, 1997. A number of prior art approaches are illustrated in  FIGS. 1A-1D . 
     FIG. 1A  illustrates an H-tree clock-distribution, which is used primarily in custom layouts and has varying tree interconnect segment widths to balance skew throughout the chip. 
     FIG. 1B  shows a clock grid clock-distribution structure. The clock grid is the simplest clock-distribution structure and has the advantage of being easy to design for low skew. However, it is area inefficient and power hungry because of the large amount of clock interconnect required. Nevertheless, some chip vendors are using this clock structure for microprocessors. 
     FIG. 1C  depicts a balanced tree clock-distribution structure. The balanced tree is the clock-distribution structure most commonly used in high performance chips. See, J. L. Neves et al., “Automated synthesis of skew-based clock-distribution networks,” VLSI Design, vol. 7, no. 1, pp. 31-57, 1998. In order to carry current to the branching segments, the clock line is widest at the root of the tree and becomes progressively narrower at each branch. As a result, the clock line capacitance increases exponentially with distance from the leaf cell (clocked element) in the direction of the root of the tree (clock input). Moreover, additional chip area is required to accommodate the extra clock line width in the regions closer to the root of the tree. 
   As shown in  FIG. 1D , buffers may be added at the branching points of the balanced tree structure. Adding buffers at the branching points of the tree significantly lowers clock interconnect capacitance, because it reduces the clock line width required toward the root. 
   One prior art alternative to generating clock signals centrally and distributing them about the chip is to partition the chip design into blocks, as shown in  FIG. 2 . A synchronous clock signal is used only within a single block, while communication between different blocks is performed on an asynchronous basis. See, T. Meincke et al., “Globally asynchronous locally synchronous architecture for large high-performance ASICs,” IEEE Symposium On Circuits and Systems, Orlando, Fla., Vol. 2, pp. 512-515, 30 May-2 Jun., 1999. 
   In the past, clock design has not typically been considered within the context of full chip timing. Existing design methodologies typically treat clock skew as a problem to be eliminated, and most designers strive to achieve zero skew. However, producing clock signals with zero skew may not be the optimum way to achieve either the safest or the highest performance clock design. It is often the case that, even after zero skew is attained, chip failures are caused by simultaneous switching current or other timing related problems. 
   There remains a need for a method of coordinating the timing of clock and data signals on a chip that can be achieved with a simple design and a minimum number of critical paths on the chip. It would be desirable to reduce the power consumption associated with clock-distribution lines or other chip timing circuitry. It would also be desirable to reduce the sensitivity of chip timing to process variations and various intermittent noises. Finally, there is an ongoing need for the development of higher speed methods for clocking data to provide enhanced chip performance. 
   BRIEF SUMMARY OF THE INVENTION 
   The methodology of the present invention addresses the problem of meeting a chip&#39;s timing requirements by combining clock timing with data path timing. Clock skew is treated not as a problem but as a controllable design variable which may be used to optimize overall chip timing. The invention achieves simultaneous distribution of clock and data signals by performing phase shift keying of digital data signals on clock frequency AC carrier signals, transmitting the keyed signals to different locations on the chip, and demodulating the keyed signals to retrieve digital data and clock signals. The inventive method may be used for signal interconnections on integrated circuits, interposers, and circuit boards. 
   The present invention reduces the number of critical paths on the chip in order to simplify designs and achieve timing closure. The present invention also allows increased clock frequency, thereby improving chip performance. Further, the present invention increases tolerance of chip timing to process variations and intermittent noise. The present invention may be used to create a larger timing budget to reduce power consumption. The present invention may also be used to reduce peak current and simultaneous switching noise to eliminate interference between digital and analog circuits. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention: 
       FIG. 1A  shows a prior art H-tree clock-distribution structure; 
       FIG. 1B  shows a prior art clock grid clock-distribution structure; 
       FIG. 1C  shows a prior art balanced tree clock-distribution structure; 
       FIG. 1D  shows a prior art balanced tree clock-distribution structure that includes buffers at branching points for reduction of clock-interconnect capacitance; 
       FIG. 2  illustrates a prior art method of partitioning a system into multiple blocks; 
       FIG. 3  is a block diagram of a device including circuitry for phase shift keying and demodulation of clock and digital data signals according to the present invention; 
       FIG. 4  is a block diagram depicting components of the inventive system used to perform differential Phase Shift Keying of digital data and clock signals; 
       FIG. 5  depicts a lead phase shift network used in the block diagram of  FIG. 4 ; 
       FIG. 6  depicts a lag phase shift network used in the block diagram of  FIG. 4 ; 
       FIG. 7A  illustrates the signal V x =A sin(ωt+φ) output by the lead phase shift network of  FIG. 5 ; 
       FIG. 7B  shows the signal V   x   =A sin(ωt−φ) output by the lag phase shift network of  FIG. 6 ; 
       FIG. 8  shows a demodulator circuit for recovering digital data from differential Phase Shift Keyed signals; and 
       FIG. 9  shows circuitry for recovering a clock signal from differential Phase Shift Keyed signals. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In the present invention, analog signal techniques are used for signal interconnections on integrated circuits, interposers, and circuit boards. The clock signal is used as a high frequency carrier for signal interconnection and is modulated by the digital data using phase shift keying (PSK). PSK refers to a modulation technique that alters the phase of the carrier. Binary phase shift keying (BPSK), which is used in the present invention, has two phases, represented by the binary values 0 and 1. PSK is a special type of amplitude modulation, or a type of amplitude shift keying (ASK) which creates signals having values −1 or 1, and its bandwidth is the same as that of ASK. The inventive method includes the use of binary phase shift keying and low frequency differential modulation of the phase of a high frequency carrier. This approach results in a narrow bandwidth of the modulated signal comparable to that obtained with simple amplitude shift keying. 
     FIG. 3  is a block diagram of a device  2  including circuitry for performing phase shift keying of clock and digital data signals and subsequent demodulation of the PSK signals to retrieve the clock and digital data signals. Device  2  may be an integrated circuit, interposer, circuit board, or similar device. Device  2  includes phase shift keying circuitry  4 , which performs phase shift keying of the digital data signal X onto the clock signal CLK to generated phase shift keyed signals V x  and V   x   . Phase shift keying circuitry  4  is located near the clock source on device  2 . PSK signals V x  and V   x    are transmitted on interconnection lines  9  and  13  to digital signal demodulator  6 . Digital signal demodulator  6  demodulates PSK signals V x  and V   x   to retrieve digital data signal X. Digital data signal X and PSK signals V x  and V   x    are input to clock signal demodulator  8 , which demodulates PSK signals V x  and V   x    to retrieve the clock signal. The clock signal and digital data signal X are input to clocked element  10  with no relative time delay between the two. Digital signal demodulator  6  and clock signal demodulator  8  are located close to clocked element  10  but may be located at some distance from phase shift keying circuitry  4 . 
     FIG. 4  is a schematic diagram of differential phase shift keying circuitry  4  that may be used to perform the differential phase shift keying signal interconnection technique of the present invention. A sinusoidal oscillator signal sin(ωt) having a radian frequency ω at the clock signal frequency for the chip is generated by oscillator  1 . The oscillator signal is sent simultaneously to phase shifter  3  and phase shifter  5 . Digital signal X is input to phase shifter  3  and controls the phase shift produced in the oscillator signal by phase shifter  3 , while the complementary digital signal  X  is input to phase shifter  5  and controls the phase shift produced in the oscillator signal by phase shifter  5 . The output of phase shifter  3  is fed to driver amplifier  7  and, from there, transmitted on interconnection line  9 . The output of phase shifter  5  is fed to driver amplifier  11  and subsequently transmitted on interconnection line  13 . Interconnection line  9  and interconnection line  13  are low impedance interconnection lines with matched terminating impedances  15  and  17 , respectively. 
   As shown in  FIG. 5 , phase shifter  3  is a lead phase shift network made up of capacitor  19  and voltage variable resistor  21  forming a high pass filter. Capacitor  19  has a capacitance C 1  and voltage variable resistor  21  has a resistance of R 1 . Voltage variable resistor  21  is an NMOS transistor configured as a voltage variable resistor, with digital signal X connected to its gate to regulate the value of resistance R 1 . Phase shifter  3  produces a positive phase shift φ in the input signal when X has a logical high value. Thus, when the input to phase shifter  3  is sin(ωt) and X has a logical high value, the output will be V x =A sin(ωt+φ), and when X has a logical low value, the output will be V x =A sin(ωt), where A is an arbitrary constant. V x  is plotted in  FIG. 7A . 
     FIG. 6  depicts phase shifter  5 , which is a lag phase shift network made up of voltage variable resistor  23  and capacitor  25  forming a low pass filter. Capacitor  25  has a capacitance C 2  and voltage variable resistor  23  has a resistance of R 2 . Voltage variable resistor  23  is an NMOS transistor configured as a voltage variable resistor, with complementary digital input  X  connected to its gate to regulate the value of resistance R 2 . Phase shifter  5  produces a phase shift of equal magnitude but opposite sign to that produced by phase shifter  3 ; thus, it produces a negative phase shift φ in the input signal. Thus, when the input to phase shifter  5  is sin(ωt) and  X  has a logical high value, the output will be V   x   =A sin(ωt−φ), and when  X  has a logical low value, the output will be V   x   =A sin(ωt) where A is the arbitrary constant found in the expression for V x . V   x    is plotted in  FIG. 7B . 
   Both phase shifter  3  and phase shifter  5  utilize phase shift networks of the type used in high frequency ring oscillators as disclosed in U.S. patent application Ser. No. 09/860,131, filed May 17, 2001, now U.S. Pat. No. 6,535,071, issued Mar. 18, 2003, in which the frequency of oscillation can be near f T  of the transistors. 
   The phase shift keyed signals V x  and V   x    are transmitted on matched interconnection lines  9  and  13  to the vicinity of the clocked element  10 . V x  and V   x    each contain both clock and phase shift keyed digital data. Any signal skew which occurs over the length of interconnection lines  9  and  13  should be substantially the same for the signals on the two interconnection lines. At the clocked element  10 , PSK signals V x  and V   x    are demodulated to recover the digital signal X and the clock signal. 
   Digital signal demodulator  6 , which is used to demodulate the digital signal encoded in signals V x  and V   x   , is depicted in  FIG. 8 . Digital signal demodulator  6  includes differential amplifier  27 , transistor amplifier circuit  29  which functions as an inverter or single stage amplifier, RC filter  31 , and comparator  33 . Signals V x  and V   x    are fed into the positive and negative inputs, respectively, of a differential amplifier  27 . The difference between V x  and V   x    is V x −V   x   =A sin(ωt+φ)−A sin(ωt−φ)=2A cos(ωt)sin(φ) when X has a logical high value. When X has a logical low value, V x −V   x   =0. As noted previously, A is an arbitrary constant amplitude, ω is the radian frequency of the carrier or oscillator frequency and φ is the amount of phase modulation at the input. Since φ, the amount of phase modulation, only has two values, zero and some finite value, then the differential output of the receiver is a pulse modulated sine or cosine wave at the carrier frequency. 
   Transistor amplifier circuit  29  is made up of diode-connected PMOS load transistor  35  and NMOS transistor  37 . The demodulator circuit of  FIG. 8  takes advantage of the nonlinear characteristics of PMOS load transistor  35  to recover digital data from PSK signals. For simplicity, it can be assumed that PMOS load transistor  35  and NMOS transistor  37  have matching characteristics. Power supply voltage V DD  is connected to the source of PMOS load transistor  35 . Power supply voltage V DD =4V T , where V T  is the threshold voltage of the PMOS load transistor  35  and NMOS transistor  37 . The nominal DC voltage at the output of differential amplifier  27  and the input of transistor amplifier circuit  29  is 2V T  when no AC signal is output by differential amplifier  27 . The corresponding voltage at the output of transistor amplifier circuit  29  is also 2V T. When V   x  and V   x    are applied to the inputs of differential amplifier  27 , the output is: 
     V   1 =2 V   T +2 A  cos(ω t )sin(φ) when X has a logical high value and  V   1 =2 V   T  when X has a logical low value. 
   If the signal amplitude 2 A is made comparable to V T  of the transistors, the output from transistor amplifier circuit  29  is:
 
 V   2 =2 V   T −2 A  cos(ω t )sin(φ)−[4 A   2 /(4 V   T )] cos 2 (ω t )sin 2  (φ),
 
which, as can be seen, includes a component that depends on the square of the AC component of the input signal.
 
   RC filter  31 , which is a simple RC low pass filter at the output of transistor amplifier circuit  29 , is made up of resistor  39  having a resistance R 3  and capacitor  41  having a capacitance C 3 . The output of RC filter  31  is:
 
 V   3 =2 V   T −½[(4 A   2 /(4 V   T ))sin 2 (φ)],
 
which is the DC component of the output of transistor amplifier circuit  29  and corresponds to the average value of cosine squared. Signal V 3  is input to comparator  33  and compared to reference signal V ref =2V T  to produce an output signal V 4  which has a value of either sin 2 (φ) or zero. V 4  is the recovered digital data signal.
 
     FIG. 9  illustrates the circuitry of clock signal demodulator  8 , which is used to recover the clock signal from the modulated RF carrier. Also shown are matched output impedances  15  and  17  of interconnection lines  9  and  13 , respectively. 
   Clock signal demodulator  8  includes two phase shift networks, lag phase shift network  43  and lead phase shift network  45 . Lag phase shift network  43  includes a low pass filter made up of voltage variable resistor  47  having resistance R 4  and capacitor  49  having resistance C 4 . The input to lag phase shift network  43  is signal V x  from interconnection line  9 . Voltage variable resistor  47  is an NMOS transistor configured as a voltage variable resistor. The resistance R 4  of voltage variable resistor  47  is controlled by voltage V 5 , which is connected to the gate of the NMOS transistor. V 5 =V DC −BV 4 , where V DC  is a constant DC voltage, B is an arbitrary constant, and V 4  is the recovered digital signal output by the demodulator circuit shown in  FIG. 8 . The output of lag phase shift network  43  is fed into driver amplifier  51 . The output of driver amplifier  51  is V 7 =Dsin(ωt+φ−θ), where D is an arbitrary constant, ω is the radian frequency of the clock signal, φ is the phase shift introduced by phase shifter  3  (see  FIG. 4 ) during phase shift keying of the digital data, and θ is the phase shift introduced by lag phase shift network  43 . 
   Lead phase shift network  45  includes a high pass filter made up of capacitor  53  having capacitance C 5  and voltage variable resistor  55  having resistance R 5 . The input to lead phase shift network  45  is signal V   x    from interconnection line  13 . Voltage variable resistor  55  is an NMOS transistor configured as a voltage variable resistor. The resistance R 5  of voltage variable resistor  55  is controlled by voltage V 6 , which is connected to the gate of the NMOS transistor. V 6 =V DC +BV 4 , where V DC , B, and V 4  are as defined previously. The output of lead phase shift network  45  is fed into driver amplifier  57 . The output of driver amplifier  57  is V 8 =Dsin(ωt−φ+θ), where D is the same arbitrary constant as found in the equation for V 7 , ω is the radian frequency of the clock signal, φ is the phase shift introduced by phase shifter  5  (see  FIG. 4 ) during phase shift keying of the digital data, and θ is the phase shift introduced by lead phase shift network  45 . 
   In lag phase shift network  43  and lead phase shift network  45 , changing the resistance values R 4  and R 5  changes the phase shift of each network. In lead phase shift network  45 , decreasing R 5  increases the phase shift θ, making it more positive, since the corner frequency, ω c , moves up closer to the carrier frequency, ω. In lag phase shift network  43 , increasing R 4  lowers the corner frequency ω c  and makes θ more negative, or shifts the phase of the incoming signal to more negative values. 
   The gains and characteristics of lag phase shift network  43  and lead phase shift network  45  are adjusted so that φ=θ. An analog adder  59  made up of resistors  61 ,  63 , and  65  and amplifier  67  is used to average signals V 7  and V 8  to reduce noise and errors and yield output V 9 , which equals the clock signal sin(ωt) without the modulation of the digital data. In this manner, the clock signal can be recovered. 
   The frequency limiting element in this system is not the oscillator, carrier frequency, digital modulation frequency, or line characteristics but, rather, is likely to be the receiver amplifier. By using a relatively small number of CMOS elements in the circuitry of the invention, power consumption is kept low. The novel PSK method allows clock and data signals to be transmitted over any distance and to remain synchronized with each other. Speed and performance of the device are thus enhanced.

Technology Classification (CPC): 7