Patent Abstract:
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD protection, are provided. An ESD structure may be associated with each interconnect, either individually or shared between two or more interconnects. Each interconnect includes a contact tip for establishing a temporary electrical connection with a bond pad of the semiconductor device and a contact pad for electrically interfacing the bond pad with external burn-in and/or test equipment. The ESD structure may be implemented, for example, as a fusible element or a shunting element, such as a pair of diodes, a diode-resistor network, or a pair of transistors. The interconnect may be employed as part of an insert including a plurality of interconnects that provides ESD protection to a plurality of integrated circuits of at least one semiconductor device.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to the manufacture of semiconductor devices, such as bare dice or dice contained on a wafer. More specifically, the present invention relates to an improved apparatus and method for providing electrostatic discharge protection to a test fixture which is electrically connected to a semiconductor device during burn-in and/or testing.  
           [0003]    2. State of the Art  
           [0004]    It is well known that electrostatic discharge (ESD) can damage semiconductor devices. Thus, ESD protection circuits are typically integrated into a semiconductor die to protect the input and output circuitry. Exemplary ESD protection circuitry located between a bonding pad and internal circuitry of a semiconductor device are disclosed in U.S. Pat. No. 5,500,546, issued Mar. 19, 1996, entitled “ESD Protection Circuits Using Zener Diodes”, to Marum et al. and in U.S. Pat. No. 6,040,733, issued Mar. 21, 2000, entitled “Two-stage Fusible Electrostatic Discharge Protection Circuit”, to Casper et al.  
           [0005]    In order to conserve the amount of surface area, or “real estate”, consumed on a die, ESD circuitry may not always be included as part of the die. In such a case, ESD protection is typically included in the packaging for the die or in higher-level packaging, as when the die is used to construct multi-chip modules or other semiconductor die-based devices.  
           [0006]    Bare (i.e., unpackaged) dice may be burned-in and tested during the manufacturing process to ensure that each die is a known good die (KGD). For burn-in and testing, a bare die is placed in a carrier which provides a temporary electrical connection with the bond pads of the die for interconnection with external test circuitry. Akram et al., in U.S. Pat. No. 6,018,249, issued Jan. 25, 2000 (hereinafter “Akram &#39;249”), which is assigned to the assignee of the present invention and hereby incorporated herein in its entirety by this reference, discloses a test system for testing semiconductor components which includes an interconnect for making temporary electrical connection with the semiconductor components.  
           [0007]    Further, Akram et al., in U.S. Pat. No. 6,016,060, issued Jan. 18, 2000 (hereinafter “Akram &#39;060”), which is assigned to the assignee of the present invention and hereby incorporated herein in its entirety by this reference, discloses an interconnect for temporarily establishing electrical communication with semiconductor components having contact bumps. FIG. 1 shows one embodiment of test fixture disclosed in Akram &#39;060. As shown in FIG. 1, that test fixture, which is referred to in Akram &#39;060 as “interconnect  20 ”, includes a substrate  24  and a plurality of contact members  22  arranged on substrate  24  so as to contact and electrically engage the bond pads of a semiconductor device (not shown) to be burned-in or tested. Each contact member  22  is electrically connected to a corresponding contact pad  31  of the test fixture (interconnect  20 ) through a conductor  30 . The contact pads  31  are configured to provide an electrical connection from external test circuitry (not shown) to the bond pads of the semiconductor device.  
           [0008]    Handling of a bare semiconductor device, or die, without internal ESD protection circuitry during burn-in and test processes can destroy the semiconductor device. To protect semiconductor devices from ESD damage, state-of-the-art test carriers, such as those disclosed in U.S. Pat. No. 6,136,137 to Farnworth et al. and U.S. Pat. No. 6,099,597 to Yap et al., include conductive metal surfaces that conduct built-up electrostatic charges away from carrier surfaces which touch, or are in close proximity to, the bare semiconductor devices.  
           [0009]    Test fixtures that include ESD protection circuitry placed thereon so as to protect the input and output bond pads of a bare semiconductor device without its own internal ESD protection circuitry are not known in the art.  
         BRIEF SUMMARY OF THE INVENTION  
         [0010]    The present invention includes apparatus and methods for providing external electrostatic discharge (ESD) protection to the circuitry of a semiconductor device during burn-in and testing thereof. The semiconductor device may include its own ESD protective elements or may lack such elements. When external ESD structures that incorporate teachings of the present invention are used with semiconductor devices that include ESD protective elements, the external ESD structures may shield or buffer the ESD protective elements of the semiconductor device from ESD events that may occur prior to final packaging or normal operational use of the semiconductor device, such as during testing thereof. Such protection may be provided by “sizing” the external EDS structures to shunt excess voltage at a lower threshold voltage than the threshold voltage for which the ESD protective elements of the semiconductor device are configured.  
           [0011]    An exemplary embodiment of an apparatus incorporating teachings of the present invention comprises a test fixture, which is referred to herein as an “insert” and as a “test interconnect” or, for simplicity, as an “interconnect”. The insert includes at least one, and normally a plurality of, interconnect circuits. The insert includes structures for providing protection against ESD damage, hereinafter referred to for simplicity as “ESD structures”, along each interconnect circuit thereof, between a contact tip, or contact element, and corresponding test pad of the interconnect circuit. The contact tips of the insert are configured to temporarily contact and establish electrical connection with corresponding bond pads of a semiconductor device to be burned-in or tested. The test pads are configured to communicate with corresponding circuits of a burn-in or test apparatus.  
           [0012]    Each ESD structure is configured to substantially eliminate voltage “spikes” associated with ESD events. The ESD structures may be implemented in a variety of ways including, but not limited to, as a voltage shunt, such as a diode-resistor network or group of transistors, as a fusible element, or otherwise.  
           [0013]    Another embodiment of the present invention comprises an insert comprising a plurality of interconnect circuits and an ESD structure that is common to at least some of the plurality of interconnect circuits.  
           [0014]    The method of the present invention may be performed with an insert configured to provide ESD protection to a semiconductor device while in temporary contact with a bond pad of the semiconductor device. As used herein, the term “bond pad” may include a bond pad or other contact that is ultimately in communication with a bond pad or other conductive path, such as a trace of a redistribution layer (RDL) leading to integrated circuitry, of a semiconductor device, such as a lead, solder ball, or other conductive element of a packaged semiconductor device. Accordingly, the method may comprise burning-in or testing a variety of types of semiconductor devices, including, without limitation, bare and substantially bare semiconductor devices, chip-scale packages (CSPs), and packaged semiconductor devices (e.g., leaded semiconductor devices and semiconductor devices which include discrete conductive elements protruding from a major surface thereof, such as in a grid array or otherwise).  
           [0015]    Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    In the drawings, which illustrate exemplary embodiments of various aspects of the present invention and in which like references refer to like parts in different views or embodiments:  
         [0017]    [0017]FIG. 1 is a schematic plan view of a prior art insert including a plurality of interconnect circuits;  
         [0018]    [0018]FIG. 2 is a combined block diagram/enlarged schematic representation of an interconnect circuit of an insert which includes electrostatic discharge protection circuitry, or an ESD structure, in accordance with the present invention;  
         [0019]    [0019]FIG. 3 is a combined block diagram/enlarged schematic representation of the interconnect circuit of FIG. 2, illustrating an example of an ESD structure, which comprises a diode-resistor network;  
         [0020]    [0020]FIG. 4 is a top plan layout representation of the diode-resistor network of FIG. 3, of which the diodes comprise a voltage shunting element;  
         [0021]    [0021]FIG. 5A is an enlarged top plan layout of diode D 1  of FIG. 4;  
         [0022]    [0022]FIG. 5B is a cross-sectional representation of diode D 1  of FIG. 5A;  
         [0023]    [0023]FIG. 6 is a top plan layout representation of a variation of a voltage shunting element that may be used as at least a part of the ESD structure of FIG. 2;  
         [0024]    [0024]FIG. 7 is a cross-sectional representation of the shunting element of FIG. 6, taken along line  7 - 7  thereof;  
         [0025]    [0025]FIG. 8 is a cross-sectional representation of another variation of a voltage shunting element, which includes a pair of transistors, that may be used as at least a part of the ESD structure of FIG. 2;  
         [0026]    [0026]FIG. 9 is a combined block diagram/enlarged schematic representation of an interconnect circuit including the voltage shunting element of FIG. 8;  
         [0027]    [0027]FIG. 10 is a combined block diagram/enlarged schematic representation of the interconnect circuit of FIG. 2 illustrating another example of an ESD structure, which comprises a fusible element; and  
         [0028]    [0028]FIG. 11 is a top plan layout of the fusible element of FIG. 10. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0029]    With reference to FIG. 2, a combined block diagram/enlarged schematic representation of an insert  18  according to the present invention with electrostatic discharge protection circuitry (ESD structures  40 ) is shown. Insert  18  includes each of the elements described in Akram &#39;060, the disclosure of which has been incorporated by reference, including a substrate  12 , such as a bulk semiconductor substrate (e.g., a full or partial wafer of silicon, gallium arsenide, indium phosphide, etc.) on which is formed a plurality of interconnect circuits  10 . Each interconnect circuit  10  includes a contact member or tip  22 , a conductor  30  that extends laterally from its corresponding contact tip  22 , and a contact pad  31  at an opposite end of conductor  30  from contact tip  22 . Each contact tip  22  is configured to engage and establish electrical contact with a bond pad of a semiconductor device (not shown). Each contact pad  31  is configured to provide an electrical connection from external test circuitry (not shown) to the bond pad of the semiconductor device through its corresponding conductor  30  and contact tip  22 .  
         [0030]    In addition, each interconnect circuit  10  of an insert  18  that incorporates teachings of the present invention includes an ESD structure  40 . As shown, ESD structure  40  is positioned at an intermediate position along the length of a conductor  30 . As such, conductor  30  may comprise a conductive element  32   a  that extends between and electrically connects contact pad  31  and ESD structure  40  to one another and another conductive element  32   b  that extends between and electrically connects ESD structure  40  and contact tip  22  to each other. Conductive elements  32   a  and  32   b  may be configured so as to aid in positioning all of the contact pads  31  and contact tips  22  of insert  18  at locations that respectively correspond to the arrangements of electrical connectors of external test equipment (not shown) and bond pads of a semiconductor device (not shown) so as to make sufficient contact therewith. However, the ESD structure  40  may be connected directly to contact pad  31  without the use of conductive element  32   a  or to contact tip  22  without the use of conductive element  32   b . The ESD structure  40  may also be connected directly between the contact pad  31  and the contact tip  22  without the use of either conductive element  32   a  or  32   b , or incorporated within the structure of either contact pad  31  or contact tip  22 .  
         [0031]    [0031]FIG. 3 depicts a combined block diagram/enlarged schematic representation of the insert  18  of FIG. 2 illustrating the ESD structure  40  as a diode-resistor network  42 , which shunts excess voltage from interconnect circuit  10  (FIG. 2). Diode-resistor network  42  includes a resistive element R 1  which is electrically connected to the contact pad  31  through conductive element  32   a , a resistive element R 2  electrically connected to resistive element R 1  at node  36  and to contact tip  22  through conductive element  32   b , a diode D 1  electrically connected between a V DD  voltage (i.e., power) potential and node  36 , and a diode D 2  electrically connected between a V SS  voltage (i.e., ground) potential and node  36 . Resistive elements R 1  and R 2  limit the peak current which flows from contact pad  31  or contact member  22  through diodes D 1  and D 2  during an ESD event. Diode D 1  may be configured to turn on when the voltage potential at node  36  is greater than or equal to V DD +0.7 Volts and diode D 2  may be configured to turn on when the voltage potential at node  36  is less than or equal to V SS −0.7 Volts, thus “clamping” the voltage potential at node  36  to levels which will not damage the semiconductor device. One skilled in the art will recognize that the V DD  voltage potential and the V SS  voltage potential may be the same voltage potentials used to power the semiconductor device electrically connected to contact member  22  during burn-in and testing.  
         [0032]    [0032]FIG. 4 is a top plan layout representation of the diode-resistor network  42  of FIG. 3 as implemented on a silicon substrate  12  (not shown). Resistive elements R 1  and R 2  may each be formed as a slab of polysilicon with known resistivity. As shown in FIG. 4, resistive elements R 1  and R 2  may be shaped so as to increase the length and, hence, the total electrical resistance of the resistive elements. Conductive connector  54  provides an electrical connection between resistive elements R 1  and R 2 , as well as between diodes D 1  and D 2  at a point corresponding to node  36  of FIG. 3.  
         [0033]    For clarity, FIGS. 5A and 5B show an enlarged layout of diode D 1 . While the enlarged layout is only shown for diode D 1 , it should be noted that the layout of diode D 2  may be substantially identical to that of diode D 1 . FIG. 5A shows a top plan layout of diode D 1  while FIG. 5B shows a corresponding cross-sectional plan layout of diode D 1  of FIG. 5A. Diode D 1  includes a P-type silicon region  48  or “P well” formed in a silicon substrate. An N+ region  50  and a P+ region  52  are formed within the P well region  48  to form a “PN junction” typical of a diode. Thus, the N+ region  50  corresponds to a cathode and the P+ region  52  corresponds to an anode of diode D 1 . As seen in FIG. 4, diode D 1  is electrically connected to conductive connector  54  through P+ region  52  and to a V DD  bus  56  through N+ region  50 . Conductive connectors  54  and  56  are electrically isolated from substrate  24  and the P well region  48  thereof by a dielectric layer  51  (e.g., a layer comprising silicon dioxide or another suitable dielectric material). Further, diode D 2  is electrically connected to conductive connector  54  through N+ region  50  and to a V SS  bus  58  through P+ region  52 .  
         [0034]    Another example of a voltage shunting element  60  that may be used as ESD structure  40  in interconnect circuit  10  of the insert  18  shown in FIG. 2 is depicted in FIGS. 6 and 7. As shown in FIGS. 6 and 7, voltage shunting element  60  comprises a pair of elongate but isolated spaced-apart n-wells  62  and  64  formed in a p-type substrate  12 . N-well  62  communicates with the conductive element  32 , while n-well  64  communicates with a V DD  voltage potential. N-wells  62  and  64  are formed in a p-type material, such as substrate  12  or a layer of p-type material  61  which is formed over and electrically isolated from substrate  12 .  
         [0035]    An insulative, or dielectric, layer  14  is located over n-wells  62  and  64 , as well as over the semiconductive material in which n-wells  62  and  64  are formed, to electrically isolate structures, such as conductive elements  32 , contact pads  31 , and contact tips  22 , from substrate n-wells  62  and  64  and the layer of semiconductive material in which they are formed. A center member  68  of a dielectric isolation structure  67 , such as trench isolation structure, extends downward into substrate  12  to electrically isolate n-wells  62  and the p-type material  61 P 2  in which n-wells  62  are formed from adjacent regions  61 P 1 , of p-type material  61 . Dielectric isolation structure  67  also includes laterally extending members  69  that electrically isolate the regions of n-well is  62  and regions  61 P, that correspond to a particular interconnect circuit  10  from the regions of n-wells  62  and regions  61 P, that correspond to an adjacent interconnect circuit  10  from one another and, thus, prevent electrical shorting between adjacent interconnect circuits  10 . Electrically conductive vias  16  and  17  extend through the insulative layer  14  and electrically connect each conductive element  32  to a corresponding n-well  62  region and to a corresponding region  61 P of p-type material  61  located between n-well  62  and n-well  64 , respectively. Similar contacts  16   VSS  are used to contact p-type material  61 P 2  of substrate  12  and conductive element  30   SS  that extends over insulative layer  14  and to a ground pad  63  through which the V SS  voltage potential is communicated. N-well  64  communicates with the V DD  potential by way of an electrically conductive via  17   VDD  that contacts n-well  64  and extends through insulative layer  14  to a conductive element  30   VDD  that extends over insulative layer  14  and to a power pad  65  through which the V DD  voltage potential is communicated.  
         [0036]    As such, in voltage shunting element  60 , diode D 1  of the schematic shown in FIG. 3 is formed at the junction  66  between the region  61 P of p-type material  61  and n-well  64 . Diode D 2  of the schematic shown in FIG. 3 is present in voltage shunting element  60  at the junction between n-well  62  and the p-type material  61 P 2  connected to V SS  by electrically conductive via  16   VSS .  
         [0037]    Substrate  12  may be patterned, as known in the art, to form contact tips  22 . By way of example, contact tips  22  having the shapes of pillars or truncated pyramids may be formed from substrate  12  by known photomask and isotropic etch processes, such as those described in U.S. Pat. No. 5,483,741 to Akram et al., the disclosure of which is hereby incorporated herein in its entirety by this reference. When potassium hydroxide (KOH) is used as the anisotropic etchant, a silicon substrate  12  is etched at an angle of about 54°, with silicon located beneath inside corners being substantially protected from the etchant. Accordingly, an H-shaped mask may be used to pattern the silicon of substrate  12  to provide protrusions which could be used in the fabrication of contact tips  22  that have the shapes of truncated pyramids. A completed contact tip  22  having a truncated pyramid configuration and a top with dimensions of about 40 μm×40 μm would fit into a bond pad having dimensions of about 100 μm×100 μm.  
         [0038]    Known processes may be used to fabricate each of the features of voltage shunting element  60 . By way of example only, each n-well  62 ,  64  may be formed by masking a lightly doped p-type material  61  (e.g., silicon, polysilicon, etc.) and implanting or diffusing dopant (e.g., phosphorus or antimony) into regions of substrate  12  that are exposed through the mask (e.g., a photomask), as known in the art. Also, insulative layer  14  may be grown or deposited onto substrate  12  and the protrusions thereof that will subsequently form parts of contact tips  22  by known techniques appropriate for the type of insulative material desired (e.g., a silicon oxide, silicon nitride, silicon oxynitride, etc.). Apertures  15  may then be formed through insulative layer  14  at locations where electrically conductive vias  16 ,  17  are desired. Known mask and etch processes, which, of course, are suitable for removing the material of insulative layer  14 , may be employed to form apertures  15 . Next, a layer of conductive material, such as a metal (e.g., aluminum, copper, titanium, tungsten, etc.), metal alloy, or conductively doped (e.g., to have a p-type conductivity) polysilicon, may be formed over insulative layer  14  and within the apertures  15  that are formed through insulative layer  14 .  
         [0039]    The conductive material within apertures  15  forms electrically conductive vias  16 ,  17 . One or more conductive elements  32  may be formed by patterning the layer of conductive material (e.g., aluminum, copper, titanium, tungsten, etc.), as known in the art, such as by suitable mask and etch processes. Each contact pad  31  and contact tip  22  may be formed simultaneously with or separately from the fabrication of each conductive element  32 . By way of example only, a first conductive layer comprising titanium silicide (TiSi x ), which will prevent bond pads of a semiconductor device from fusing to contact tip  22 , may be formed on insulative layer  14  and a second conductive layer comprising aluminum formed over the TiSi x . These conductive layers may then be patterned to form the electrically conductive structures of an interconnect circuit  10 .  
         [0040]    Yet another exemplary embodiment of ESD structure  40  (FIG. 2) incorporating teachings of the present invention comprises a voltage shunting element  70  that includes a pair of transistors  72  and  73 , as depicted in FIG. 8, both of which communicate with conductive element  32  of interconnect circuit  10  (FIG. 2). An insulative layer  71  electrically isolates each transistor  72 ,  73  from substrate  12  of insert  18  (FIG. 2) on which voltage shunting element  70  is being used. As shown, each transistor  72 ,  73  includes spaced-apart source and drain wells  75  and  76 , respectively, formed in a semiconductive layer  74 , such as a polysilicon layer, which has been formed on insulative layer  71 . By way of example, wells  75  and  76  may comprise regions of semiconductive layer  74  that have been doped to have an n-type conductivity and the remainder of semiconductive layer  74  may comprise a p-type material. A gate dielectric  78  of each transistor  72 ,  73  is located on semiconductive layer  74 , laterally between wells  75  and  76 . A conductive element  80  of each transistor  72 ,  73  overlies gate dielectric  78 . Conductive element  80  may be formed from any suitable, electrically conductive material, such as conductively doped polysilicon or a metal. Sidewall spacers  81  and  82  are positioned laterally adjacent to each side of conductive element  80 .  
         [0041]    Transistor  72 , which communicates with V DD , includes a conductive link  84  that extends between and provides electrical communication between conductive element  80  and source well  75 . A first contact element  85  establishes communication between conductive element  32  (depicted as overlying voltage shunting element  70 ) and the drain well  76  of transistor  72 , while a second contact element  87  establishes communication between V SS  and conductive link  84  and, thus, with both conductive element  80  and the source well  75  of transistor  72 .  
         [0042]    In transistor  73 , which communicates with V SS , conductive link  84  extends between and electrically contacts conductive element  80  and the drain well  76 . First and second contact elements  86  and  88 , respectively, electrically communicate with different portions of transistor  73 . First contact element  86  establishes electrical communication between the source well  75  of transistor  73  and V DD . Second contact element  88  electrically connects an associated conductive line  32  (depicted as overlying voltage shunting element  70 ) with conductive link  84  of transistor  73  and, thus, with the conductive element  80  and the drain well  76 , with which conductive link  84  communicates.  
         [0043]    Known fabrication processes may be used to form the various features of transistors  72  and  73 , as well as the underlying insulative layer  71 , overlying insulative layer  90 , and contact elements  85 - 88 .  
         [0044]    An electrical schematic representation of a voltage shunting element  70  of the type shown in FIG. 8 is provided in FIG. 9.  
         [0045]    [0045]FIG. 10 depicts a combined block diagram/enlarged schematic representation of another insert  18  of FIG. 2, illustrating ESD structure  40  as comprising a fusible element  44 . Fusible element  44  is configured to electrically connect to contact pad  31  through conductive element  32   a . Similarly, fusible element  44  is configured to electrically connect to the contact member  22  through conductive element  32   b.    
         [0046]    [0046]FIG. 11 is a top plan layout of fusible element  44  of FIG. 10, as implemented on a silicon substrate  12  (not shown). Fusible element  44  may be implemented using metal, a metal alloy, polysilicon or other conducting material and may be fabricated by know processes. Fusible element  44  is shaped so as to fuse during an ESD event. If fusible element  44  fuses, or is “blown”, during an ESD event, the fused or “blown” fusible element  44  may provide a visual indicator of the ESD event, which may be useful for determining where the ESD event occurred or even why the ESD event occurred.  
         [0047]    Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some exemplary embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions, and modifications to the invention, as disclosed herein, which fall within the meaning and scope of the claims are to be embraced thereby.

Technology Classification (CPC): 7