Patent Abstract:
A device and method for driving a converter circuit that supplies a charge via a first electronic switch and a second electronic switch alternately turned on and off. A generator module generates a memory signal, indicating the duration of a first dead-time interval. A delay module, sensitive to the memory signal controls turning-on of the first electronic switch with a delay, with respect to turning-off of the second electronic switch, so that a second dead-time interval has a duration substantially equal to the duration of the first dead-time interval.

Full Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from European patent application No. 05425865.2, filed Dec. 2, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     The invention relates to techniques for driving power converters, in particular of the type the operation of which is based upon a pulse-driving technique, such as for example a pulse-width-modulation (PWM) driving technique.  
       BACKGROUND  
       [0003]     In order to provide a clearer picture in which to contextualize embodiments of the invention, useful reference may be made to the block diagram represented in  FIG. 1 , which is a block diagram of a voltage regulator designed to drive a load L through a voltage regulator VR, controlled by means of two electronic switches (typically two MOSFETs) set between a supply voltage V IN  and the ground G, with the function, respectively, of high-side switch HS and low-side switch LS.  
         [0004]     The configuration represented in  FIG. 1  is provided purely by way of example of a possible context for application of embodiments of the invention and hence must not be understood as in any way limiting the scope of the invention itself.  
         [0005]     Usually, the voltage regulator VR is driven through the collectors or drains of the two high-side and low-side MOSFETs (or equivalent components) HS and LS, connected to one another, while the corresponding driving terminals (bases or gates) are driven by a driver D that receives a PWM driving signal from a controller C. The input of the controller is derived from an error amplifier EA, which detects the deviation between a reference voltage V REF  and a feedback signal F drawn from the load L through a feedback line F.  
         [0006]     Basically, the PWM signal output from the controller C drives the switches HS and LS, enabling transfer of the energy from an input represented by the supply voltage V IN  to an output represented by the load L.  
         [0007]     The voltage-regulator diagram represented in  FIG. 1 , which, as has been said, has a character purely of example, comprises in itself various possible alternative solutions. In particular, in the case of topologies of a double-ended type, such as the ones referred to as half-bridge or active-clamp topologies, the control of the switches HS and LS occurs in a complementary way. In particular, for half-bridge topologies, the complementary or asymmetrical control is actuated so as to obtain zero-voltage switching (ZVS) of the electronic switches HS and LS. Since the latter are usually components, such as MOSFETs, in order to guarantee that zero-voltage switching occurs, it is necessary to introduce between turning-off of one of the MOSs and turning-on of the other a dead time, which can be programmed to a desired value.  
         [0008]     A solution commonly adopted in controllers for double-ended topologies with complementary driving envisages external programmability of the dead time by using a dedicated pin, to which a resistor is connected. A solution of this type is described in the National Semiconductor data sheet “LM 5025 Active Clamp Voltage Mode PWM Controller”, March, 2004, which is incorporated herein by reference.  
         [0009]     Alternatively, instead of using a dedicated pin, it is possible to consider exploiting a pin that enables locking of a frequency of an oscillator. A solution of this type is described in the publication by George E. Danz “HP5500 High Voltage (500V DC ) Power Supply Driver IC” Intersil Intelligent Power, December 1993, which is also incorporated herein by reference. As described in this publication, it is possible to consider making the oscillator by programming it externally through a resistive-capacitive (R T -C T ) network that generates a sawtooth waveform. During the descending ramp of the sawtooth, a clock pulse is issued, which can be used as dead time.  
         [0010]     This behavior is schematically represented in the diagrams of  FIG. 2 . In particular,  FIG. 2  is constituted by four superimposed diagrams, designated, respectively, by a, b, c, and d, referred to one and the same time scale t on the abscissa. The uppermost diagram, designated by a, represents the sawtooth waveform generated by the resistive-capacitive network in question. As regards the block diagram of  FIG. 1 , this network can be viewed as being in the controller C, even though it is usually external to the controller to enable programmability of the oscillator.  
         [0011]     The diagram designated by b corresponds to a train of clock pulses used for generating the dead time T dead . The pulse train, which is also generated within the controller C, can be treated (via a logic circuit in the controller C) in such a way as to separate the even pulses E from the odd pulses O.  
         [0012]     The aim again here is to use the leading edge of the odd pulses O to turn off the low-side MOS LS and the trailing edges of the same pulses to turn on the high-side MOS HS. Furthermore, as described in the publication by George E. Danz cited previously, it is possible to consider using the leading edge of the even pulses E to turn off the high-side MOS HS and the trailing edge of the same pulses to turn on the low-side MOS LS. In this way, between turning-off of one MOS and turning-on of the other, there elapses the same time, and moreover the even pulses E limit the maximum time of conduction of the high-side MOS HS and guarantee that the maximum duty cycle is less than 50%.  
         [0013]     This type of behavior is represented in the further diagrams of  FIG. 2  designated by c and d. The corresponding waveforms represent the waveforms that the driver D applies to the gate of the low-side MOS LS (diagram c) and to the gate of the high-side MOS HS (diagram d).  
         [0014]     In diagrams b, c and d of  FIG. 2 , the symbols H and L obviously designate a logic signal of a “high” level and a “low” level, respectively. It may be noted that the switching frequency f sw  is exactly half that of the sawtooth signal of the oscillator and that, during the time intervals designated by T dead , both of the MOSs HS and LS are off.  
         [0015]     By adopting this solution, the behavior of the circuit is in effect fixed in a rigid way by the train of clock pulses. The system described in the Danz publication functions in the way described above, guaranteeing that the two time intervals introduced between turning-off of one MOS and turning-on of the other are equal (because they are obtained once again starting from the clock). In this case, the MOS HS is always turned off by the clock.  
         [0016]     In the case where it were necessary to turn the MOS HS off before (for example, via a signal generated by a control loop), it is no longer possible to use the trailing edge of the even pulse of the clock to turn on the MOS LS after the time T dead  because turning-off of the MOS HS would occur at an instant that is asynchronous with respect to the clock.  
         [0017]     There exist applications in which it is effectively required that the high-side MOS HS be turned off in response to the control loop, in other words by a completely asynchronous signal. In these conditions of asynchronous operation, to turn on the low-side MOS LS after the dead time equal to the one introduced between turning-off of the low-side MOS LS and turning-on of the high-side MOS HS, it is not possible to use the even pulses E of the clock signal of diagram b.  
       SUMMARY  
       [0018]     In the light of what has been described above, an aspect of the present invention is enabling the aforesaid operation in an asynchronous way and enabling assurance that, between turning-off of the high-side MOS HS (in general, the electronic switch) and turning-on of the low-side component or switch LS, there is once again present the same “dead” time inserted between turning-off of the low-side switch LS and turning-on of the high-side switch HS. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     Embodiments of the invention will now be described, purely by way of non-limiting example, with reference to the annexed drawings, in which:  
         [0020]      FIGS. 1 and 2 , corresponding to the known art, have already been described;  
         [0021]      FIG. 3  is a block diagram that illustrates one embodiment of the present invention;  
         [0022]      FIG. 4  is a detailed block diagram of one of the modules represented in  FIG. 3 , namely, a control circuit, according to one embodiment of the present invention; and  
         [0023]      FIG. 5  is a set of timing diagrams, designated, respectively, as a to g, which represent, on the basis of a common time scale, the pattern of various signals generated during operation of the components of  FIGS. 3 and 4 . 
     
    
     DETAILED DESCRIPTION  
       [0024]     The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.  
         [0025]     Basically, the circuit diagram of  FIG. 3  amounts to the same basic scheme as the circuit diagram of  FIG. 1 . For this reason, elements that are identical or equivalent to one another have been designated in  FIGS. 1 and 3  with the same references.  
         [0026]     In the diagram of  FIG. 3 , the driver D of  FIG. 1  is represented split into two parts, D 1  and D 2 , which perform, respectively, the driving of the high-side component or switch (MOSFET) HS and of the low-side component or switch (MOSFET) LS.  
         [0027]     The part of the driver D 1  that drives the high-side component HS receives at input the odd pulses CK ODD  (designated also by O in diagrams b of  FIGS. 2 and 5 ) of a train of clock pulses produced by a generator designated as CLOCK.  
         [0028]     In the exemplary embodiment illustrated herein (which, it is emphasized, is nothing more than an example), the driver D 1  uses the trailing edges of the odd pulses O to turn on the high-side MOS HS.  
         [0029]     The part of the driver D 1  that drives the high-side component HS also receives at input the PWM signal coming from the controller C, which, through the error amplifier EA, receives the feedback signal F from the load L.  
         [0030]     The chain of elements EA, C and D 1  is configured (in a known way) so that the driver D 1  turns off the high-side MOS HS as a result of the issuing of the feedback signal F.  
         [0031]     For this purpose, the driver D 1  receives a PWM signal in the form of a narrow pulse (see diagram c of  FIG. 5 ), generated as a result of the comparison between the signal present on the feedback line F and the signal V REF  at input to the block EA of  FIG. 3 .  
         [0032]     The part of the driver D 2  that drives the low-side component LS also receives the odd pulses CK ODD  (i.e., O in diagrams b of  FIGS. 2 and 5 ) and uses the leading edges of these pulses to turn off the low-side MOS LS.  
         [0033]     Turning-on of the low-side MOS LS is instead controlled by the driver D 2  as a function of a signal T PRG  produced by a dead-time generator  10 , the function of which is to ensure that, between turning-off of the high-side MOS HS (controlled in an asynchronous way, i.e., in general in a way not co-ordinated with the clock signal produced by the clock generator) and turning-on of the low-side component LS, there is always present the same “dead” time inserted between turning-off of the low-side switch LS and turning-on of the high-side switch HS.  
         [0034]     The generator  10 , roughly resembling a delay line with variable-delay value, receives at input the following signals: 
        the odd pulses CK ODD  (i.e., O in diagrams b of  FIGS. 2 and 5 );     the PWM signal of the controller C;     a supply voltage V SUPPLY  ( FIG. 4 ), regulated via a MOSFET  20  adjusted with a gate voltage V START +V GS .        
 
         [0038]     The generator  10  produces at an output a signal T PRG  (see diagram g of  FIG. 5 ) that functions—via its trailing edge—as a turning-on signal for the low-side switch LS.  
         [0039]     If we examine the diagram of the generator  10  appearing in  FIG. 4  in greater detail, it may be noted that a MOSFET  20  is set with its drain connected to the voltage V SUPPLY  and its source coming, through a switch  30  (which will be described in greater detail in what follows), under a capacitive component (capacitor) C, the pin or plate of which, opposite to the MOSFET  20 , is connected to ground G. Across the capacitor C there will thus in general be present a voltage V C .  
         [0040]     The references  11   a  and  11   b  designate two current generators (made according to any known circuit scheme), which are able to supply or drain a d.c. current of equal intensity I with respect to the line of connection between the MOSFET  20  and the capacitor C according to the state of opening or closing of respective switches  12  and  13 .  
         [0041]     The switches  30 ,  12  and  13  are usually ordinary solid-state switches (e.g., transistors or FETs) built according to altogether known criteria.  
         [0042]     The reference number  14  designates then a flip-flop FF, the input of which is driven with the PWM signal coming from the controller C (a PWM signal which, as has been seen, contains in itself the information of feedback of the load present on the line F).  
         [0043]     The flip-flop  14  has an output Q, which generates the signal T PRG  that drives the switch  13  both in opening and in closing.  
         [0044]     The reference number  18  designates a comparator, the threshold level of which is fixed at a voltage value V START  (see also the gate supply of the MOSFET  20 ). The comparator  18  is configured in such a way as to compare the signal V C  present across the capacitor C with the aforesaid threshold value V START . The output of the comparator  18  functions as clocking input of the flip-flop  14  and is also transferred, through a logic inverter  19  to the switch  30 .  
         [0045]     For immediate reference with regard to the ensuing description, it is recalled that, in  FIG. 5 , diagrams a and b have the same meaning assumed in  FIG. 2 . Diagram c of  FIG. 5  illustrates, instead, the pattern of the PWM signal (indicated also at input to the block  14  of  FIG. 4 ) whereas diagrams d and e illustrate the driving signals (or, more correctly, the states of conduction or “turning-on”—high logic level H—and of non-conduction or “turning-off”—low logic level L—of the low-side MOSFET LS and high-side MOSFET HS.  
         [0046]     Diagram f represents the voltage V C  across the capacitor C, which varies between the value V START  and a value designated in general by V STOP .  
         [0047]     Finally, diagram g represents the dead-time pulse imposed between turning-off of the high-side MOSFET HS and turning-on of the low-side MOSFET LS.  
         [0048]     To illustrate operation of the circuit represented in  FIG. 4  it will be assumed that initially the signal CK ODD  (corresponding to the odd pulses O of the train of pulses of diagrams b of  FIGS. 2 and 4 ) is at the low level and that the capacitor C is discharged. With these conditions, the voltage across the capacitor C is lower than the threshold voltage V START , which constitutes the threshold level of the comparator  18 .  
         [0049]     The output of the comparator  18  is hence at the low logic level, so that the flip-flop  14  is reset. The signal T PRG  is at the low level; the switch  30  is thus closed, and the switches  12  and  13  are open.  
         [0050]     With these conditions, the voltage across the capacitor C increases up to the value V START , and once this value is reached the output of the comparator  18  goes to a high level so that the reset input of the flip-flop  14  goes to the high level and the switch  30  goes into an opening condition. In these conditions, the voltage across the capacitor C remains at the value V START . As soon as the signal CK ODD  goes to the high level, the switch  12  closes and the voltage across the capacitor C starts again to increase throughout the dead time of the clock pulse O, the leading edge of which corresponds to turning-off of the low-side MOSFET LS. The current I is chosen so as to guarantee that the voltage across the capacitor C will increase linearly for a time fixed by the duration of the aforesaid pulse (i.e., by the dead-time interval associated to the odd pulses of the clock signal). This pattern is clearly detectable in diagram f of  FIG. 5 .  
         [0051]     As soon as the signal CK ODD  goes to the low level, the switch  12  opens, and the charge of the capacitor C is interrupted. In the time corresponding to the dead time, the voltage across the capacitor C has passed from the value V START  to the value V STOP  (see again diagram f of  FIG. 5 ). The charge accumulated on the capacitor C thus constitutes a memory signal, which stores the duration of the (first) dead-time interval that has elapsed between turning-off of the low-side switch LS and turning-on of the high-side switch HS.  
         [0052]     When the signal HS goes to the low level in so far as the corresponding MOSFET HS turns off in response to the control loop (compare diagrams c and e of  FIG. 4 ), the output Q of the flip-flop  14  (and hence the signal T PRG  that drives the switch  13 ) goes to the high level, and the switch  13  goes into a closing condition.  
         [0053]     Assuming that the current generators  11   a  and  11   b  generate currents of substantially the same intensity (with opposite direction), the voltage across the capacitor C drops at this point from the value V STOP  to the value V START  with a slope equal to the one with which it had previously risen from the value V START  to the value V STOP . In other words, the time for discharging the capacitor C will be equal to that of charging. Of course, by “charging/discharging” is meant here the passage between the voltage values V START  and V STOP .  
         [0054]     As soon as the capacitor C discharges, i.e., when the voltage across it reaches the value V START , the output of the comparator  18  returns to the low level, resetting the flip-flop  14 , i.e., taking the signal T PRG  to the low level, which, in addition to opening the switch  13 , turns on the low-side switch LS through the driver D 2 .  
         [0055]     The above occurs with a delay, with respect to the feedback pulse signal obtained starting from the signal sent by the load L on the line F, which has a value equal to the dead-time interval desired, and this in so far as the charge accumulated on the capacitor C constitutes a memory signal, which stores the duration of the (first) dead-time interval that has elapsed between turning-off of the low-side switch LS and turning-on of the high-side switch HS. In this way, it ensures that between turning-off of the high-side MOSFET (in general, the electronic switch) HS and turning-on of the low-side component or switch LS there is always present a (second) interval of “dead” time equal to the dead-time interval inserted between turning-off of the low-side switch LS and turning-on of the high-side switch HS.  
         [0056]     The signal T PRG , issued during the process of discharging of the capacitor C, conveys in fact the information of memory of the dead time between turning-off of the low-side MOS LS and turning-on of the high-side MOS HS: the value stored can consequently be used as the dead time between turning-off of the high-side MOS HS and turning-on of the low-side MOS LS, rendering the two dead-time intervals in question substantially identical to one another, i.e., substantially of equal duration.  
         [0057]     The expression “of substantially equal duration” of the first dead-time interval and of the second dead-time interval is intended of course to take into account the approximations in each case linked to the determination and measurement of the duration of the intervals.  
         [0058]     Of course, without prejudice to principles of the invention, the details of construction of alternative embodiments may vary widely with respect to what is described and illustrated herein, without departing from the scope of the present invention, as defined by the annexed claims. In particular, persons skilled in the art will appreciate that, even though the example embodiments represented herein refer to the use of MOSFET components as electronic switches HS and LS, other embodiments include alternative types of electronic switches with similar functions that are to be switched alternately into a state of conduction or activation (switch “on”) and into a state of non-conduction or deactivation (switch “off”) in cases where it is necessary to ensure correct definition of the period of dead time. For example, in other embodiments of the invention the electronic switches are formed by bipolar transistors or similar components. It is moreover evident that the roles of the two high-side and low-side switches can be reversed, so causing the action of driving described herein with reference to the low-side switch LS to be applied to the high-side switch HS, and vice versa.  
         [0059]     Power converters formed according to embodiments of the present invention may be contained in a variety of different types of electronic systems. In the example of  FIG. 3 , the load L can thus be viewed as corresponding to different types of electronic circuitry depending upon the type of electronic system containing the power controller. The load L may thus be viewed as corresponding to computer circuitry, cellular telephone circuitry, portable digital assistant circuitry, automotive control circuitry, and so on.

Technology Classification (CPC): 7