Patent Abstract:
An effective method enhances energy saving at low load in a resonant converter with a hysteretic control scheme for implementing burst-mode at light load. The method causes a current controlled oscillator of the converter to stop oscillating when a feedback control current of the output voltage of the converter reaches a first threshold value, and introduces a nonlinearity in the functional relation between the frequency of oscillation and said feedback control current or in a derivative of the functional relation, while the control current is between a lower, second threshold value and the first threshold value, such that the frequency of oscillation remains equal or smaller than the frequency of oscillation when the control current is equal to the second threshold value. Several circuital implementations are illustrated, all of simple realization without requiring any costly microcontroller.

Full Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure concerns in general resonant switching converters circuits and in particular a control method of a resonant dc-dc converter aimed to optimize conversion efficiency (i.e., the ratio between the power provided to the load and that drawn from the input source) at low load, and a circuital implementation thereof, preferably realized in integrated form. 
         [0003]    2. Description of the Related Art 
         [0004]    Resonant converters represent a broad class of switching converters and include a resonant circuit playing an active role in determining the input-output power flow. In these converters, a bridge (half-bridge) consisting of four (or two) power switches (typically power MOSFETs) supplied by a dc voltage generates a square voltage wave that is applied to a resonant circuit (also termed resonant tank) tuned to a frequency close to the fundamental frequency of the square wave. Because of its selective response, the resonant circuit mainly responds to the fundamental component and negligibly to the higher order harmonics of the square wave. As a result, the circulating power may be modulated by varying the frequency of the square wave, holding the duty cycle constant at 50%. Moreover, depending on the resonant circuit configuration, the currents and/or voltages associated with the power flow have a sinusoidal or piecewise sinusoidal shape. 
         [0005]    These voltages and/or currents are rectified and filtered so as to provide DC power to the load. In offline applications (i.e., those operated from the power line), the rectification and filtering system supplying the load is coupled to the resonant tank circuit by means of a transformer providing galvanic isolation between the source and the load, to comply with safety regulations. As in every isolated dc-dc converters, also in this case a distinction is made between a primary side (as related to the primary winding of the transformer) connected to the input source and a secondary side (as related to the secondary winding(s) of the transformer) providing power to the load through the rectification and filtering system. 
         [0006]    As an example of resonant converter,  FIG. 1  shows the so-called LLC resonant converter, probably today&#39;s most widely used resonant converter, especially in its half-bridge version. The designation LLC stems from the fact that the resonant tank employs two inductors (L) and a capacitor (C). 
         [0007]    The resonant converter comprises a “totem-pole” of transistors M 1  and M 2  connected between the input voltage source node Vin and ground GND, controlled by a control circuit. The common terminal HB between the transistors M 1  and M 2  is connected to a resonant tank comprising a series of a capacitor Cr, an inductance Ls and another inductance Lp connected in parallel to a transformer with a center-tap secondary winding. The two windings of the center-tap secondary are connected to the anodes of two diodes D 1  and D 2 , whose cathodes are both connected to the parallel of a capacitor Cout and a resistance Rout; the output voltage Vout of the resonant converter is across said parallel while the DC output current Iout flows through Rout. 
         [0008]    Resonant converters offer considerable advantages as compared to traditional switching converters (which are not resonant, but typically PWM—Pulse Width Modulation—controlled): waveforms without steep edges, low switching losses in the power switches due to their soft-switching operation, high conversion efficiency (&gt;95% is easily reachable), ability to operate at high frequencies, low EMI generation (Electro-Magnetic Interference). All these features make resonant converters ideal candidates when high power density is to be achieved, that is, when conversion systems capable of handling considerable power levels in a relatively small space are preferred. 
         [0009]    As in most DC-DC converters, the output voltage is kept constant against changes in the operating conditions (i.e., the input voltage Vin and the output current Iout) through a control system that uses closed-loop negative feedback. As shown in the block diagram of  FIG. 2 , this is achieved by comparing a portion of the output voltage Vout to a reference voltage Vref, their difference (error signal) is amplified by an error amplifier whose output Vc (control voltage) is transferred to the primary side across the isolation boundary typically via an optocoupler. The optocoupler changes the control voltage Vc into a control current I FB . Note that normally the circuit arrangement comprising the error amplifier and the optocoupler is such that the control voltage Vc and the control current I FB  change in opposite directions: if Vc increases I FB  decreases, if Vc decreases, I FB  increases. The control current I FB  modifies a quantity X within the converter which the power carried by the converter substantially depends on. 
         [0010]    In resonant converters, as mentioned earlier, this significant quantity is the switching frequency of the square wave stimulating the resonant tank (X=ƒ sw ). In nearly all practical resonant converters, if frequency rises the delivered power decreases and vice versa. 
         [0011]    A consideration common to many applications of switching converters, resonant and not, is that conversion efficiency is maximized also under light load conditions to comply with regulations and recommendations on energy saving (e.g., EnergyStar, CEC, Eu CoC, Climate Savers, etc.). 
         [0012]    A popular technique for optimizing light load efficiency in all switching converters (resonant and not) is to make them work in the so-called “burst-mode”. With this operating mode the converter works intermittently, with series (bursts) of switching cycles separated by time intervals during which the converter does not switch (idle time). When the load is such that the converter has just entered burst-mode operation, the idle time is short; as the load decreases, the duration of the bursts decreases as well and the idle time increases. In this way, the average switching frequency is considerably reduced and, consequently, so is the effect of the two major contributors to power losses at light load: 
         [0013]    1) switching losses associated to the parasitic elements in the converter 
         [0014]    2) conduction losses related to the flow of reactive current in the resonant tank (e.g., the magnetizing current in the transformer). In fact, this current only flows while the converter is switching and is essentially zero during the idle time. 
         [0015]    The duration of the bursts and the idle time are determined by the feedback loop so that the output voltage of the converter always remains under control. To explain the mechanism governing this operation it is convenient to refer to a concrete example. 
         [0016]      FIG. 3  shows how burst-mode operation is implemented in the integrated control circuit L 6599  by STMicroelectronics, as well as a simplified schematic of its internal current-controlled oscillator (CCO).  FIG. 4  shows the oscillator waveform of the CCO, its relationship with the gate drive signals for M 1  and M 2  produced by the pulse-train generator and the voltage of the half-bridge midpoint HB, i.e., the square wave voltage applied to the resonant tank. 
         [0017]    The CCO is programmed by means of the capacitor C 1  connected from pin CF to ground and by the current I R  sourced by the pin RFmin, which provides an accurate reference voltage Vr (=2 V). I R  is internally mirrored and a current K M ·I R  is alternately sourced and sunk from pin CF, originating a symmetrical triangular waveform included between a peak value (=3.9 V) and a valley value (=0.9 V) across C 1 . As a result, the higher the current I R , the faster C 1  is charged and discharged and the higher the oscillation and switching frequency (ƒ osc ) Denoting with ΔV osc  the peak-to-valley swing of the oscillator (=3 V), the following relationship can be found: 
         [0000]    
       
         
           
             
               f 
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         [0018]    The current I R  is the sum of the current flowing through R 1  (=Vr/R 1 ) and the current I FB  sunk by the phototransistor of the optocoupler OC that transfers the control voltage Vc across the isolation boundary. Therefore, the current I FB  actually modulates I R , closing the feedback loop that regulates the output voltage of the converter and making it work at a frequency given by: 
         [0000]    
       
         
           
             
               f 
               sw 
             
             = 
             
               
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                     K 
                     M 
                   
                   
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         [0019]    Note that this is done consistently with the relationship that links the delivered power to frequency in the resonant converter and the configuration of the feedback circuit. In fact, when the load demands less power, the output voltage tends to increase; the feedback loop reacts by reducing the control voltage Vc, which increases the OC current I FB , and, therefore, the switching frequency as well, thus reducing the delivered power and counteracting the output voltage rise. 
         [0020]    The timing components R 1 , R 2  and C 1  define the oscillation frequency range of the CCO. In particular, R 1  sets the minimum operating frequency, which occurs when the current I FB  is zero: 
         [0000]    
       
         
           
             
               f 
               
                 sw 
                 · 
                 min 
               
             
             = 
             
               
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                   · 
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                 . 
               
             
           
         
       
     
         [0021]    R 2  along with R 1  sets the maximum operating frequency, that is, the frequency at which the device enters burst-mode operation, in which the device operates in short bursts, separated by idle periods. In fact, when I FB  is such that the voltage on pin STBY, V STBY , is lower than the threshold voltage V th , the output of the comparator CO 1  goes high and inhibits the oscillator and the pulse-train generator, causing both switches M 1  and M 2  to stay off. This frequency is given by: 
         [0000]    
       
         
           
             
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                 · 
                 max 
               
             
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                   . 
                 
               
             
           
         
       
     
         [0022]    Therefore, there is a discontinuity in the ƒ osc  vs. I FB  relationship, so that its complete expression is: 
         [0000]    
       
         
           
             
               
                 
                   
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                               . 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
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         [0023]    With the aid of  FIG. 5  it is possible to explain burst-mode operation as follows. 
         [0024]    When the load decreases (and the switching frequency rises) to the point that V STBY  falls below the threshold V th , the converter stops switching and the idle time begins. Since no more energy is delivered during the idle time, the load is supplied only by the filtering system (normally, the output capacitor bank Cout shown in  FIG. 1 , which here acts as energy reservoir as well) and the output voltage starts decaying. The feedback loop reacts to this by increasing the control voltage Vc, so I FB  decreases and V STBY  rises; as V STBY  exceeds V th  by a quantity equal to the hysteresis V H  of the comparator CO 1 , the output thereof goes low thus re-enabling the oscillator and the pulse-train generator. M 1  and M 2  restart switching and the idle time ends. Due to this, the output voltage increases and, consequently, Vc decreases, I FB  increases and V STBY  decreases: as soon as it falls again below V th  the converter stops switching again, and so on. 
         [0025]    Note that the oscillator frequency at the beginning of a burst, ƒ osc.bb , is slightly lower than ƒ osc.max , in fact: 
         [0000]    
       
         
           
             
               
                 
                   
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       BRIEF SUMMARY 
       [0026]    The performance of the above illustrated technique is rather good and the benefit in terms of efficiency improvement significant. However, the efficiency targets set by the upcoming regulations and recommendations concerning energy saving are becoming more and more demanding and it is tough to meet them even with resonant converters and their present day burst-mode control techniques. As a matter of fact, substantially all the control devices for resonant converters commercially available have a burst-mode operation that, apart from some minor details not concerning efficiency optimization, works in the way illustrated above. 
         [0027]    There is a demand for a new and more efficient burst-mode technique that would make easier to meet these new challenging targets. Many studies on this topic are ongoing, a review of which is provided by the appended list of references. 
         [0028]    In [1], a new technique is proposed where the “burst duty cycle”, intended as the ratio of the duration of a burst to their repetition period, is changed depending on the output current Iout, while the switching frequency is kept constant within each burst. This technique cannot be easily used in systems where the control device is located on the primary side because the information coming from the output current sensing circuit has to cross the isolation boundary. Additionally, in [1] the usage of an MCU is proposed, which limits the applicability of the method to high-end systems where cost is not a prime concern. 
         [0029]    In [2] a hysteretic (in the end, synonymous with burst-mode) control scheme is proposed where the converter always operates at the resonance frequency of the resonant tank and the low-side MOSFET M 2  is kept always on during the idle time. This technique is simple but has the drawback of depleting the energy in the resonant tank completely. When a burst starts, the energetic state of the resonant tank has to be restored, similarly to a start-up condition but without high frequency operation that limits circulating currents. Big currents, large output voltage ripple and audible noise are expected. 
         [0030]    In [3] a novel LLC burst mode control with a constant duration of the bursts and optimal switching pattern is proposed. The duration of bursts is constant, while the idle time is modulated by load conditions. In each burst, a three pulse switching pattern is implemented to keep output voltage low frequency ripple at a minimum. Also in this case the usage of an MCU is proposed, which brings the same limitations mentioned earlier. 
         [0031]    In [4] a method is proposed in which the converter operates below the resonance frequency of the resonant tank during burst-mode, which seems to be quite a design limitation. 
         [0032]    According to an embodiment described in the present disclosure a new and more efficient burst-mode technique is provided, as compared to those discussed above, that, on one hand, provides a substantially improved efficiency with limited drawbacks in terms of output voltage ripple increase and audible noise, and, on the other hand, lends itself to a relatively simple and low-cost circuit implementation. 
         [0033]    According to another embodiment, a circuital implementation of the new and more efficient burst-mode method is disclosed, preferably to be realized in integrated form on a silicon chip. According to a further embodiment, a control device for resonant converters is disclosed, embedding the aforesaid circuit and a resonant converter controlled by the control device. 
         [0034]    According to an embodiment, a method for controlling operation of a resonant converter is provided, including controlling a switching frequency of the converter, and thereby its power output, in direct relation to a feedback current, shifting the converter to an idle condition when the feedback current exceeds a first threshold, and introducing a nonlinearity into the relation of the switching frequency and the feedback current when the current exceeds a second threshold, lower than the first threshold. 
         [0035]    According to another embodiment, a device for controlling a resonant converter is provided, that includes a current controlled oscillator having an input configured to receive a feedback control current from the controller and an output configured to provide a switching control signal for the converter, at a frequency that is related to a value of the feedback control signal current. The device also includes a burst mode control circuit configured to introduce a nonlinearity into the relation of the switching control signal frequency and the feedback control signal current while the control signal current is greater than a first threshold, and to shift the current controlled oscillator to an idle condition while the feedback control signal current is greater than a second threshold, higher than the first threshold. 
         [0036]    According to an embodiment, the burst mode control circuit is configured the prevent the frequency of the switching control signal from increasing while the feedback control signal current is greater than the first threshold. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0037]      FIG. 1  shows a known LLC resonant half-bridge converter as an example of resonant dc-dc converters that can be rendered more efficient by the method of this disclosure. 
           [0038]      FIG. 2  shows a block diagram illustrating a typical known example of output voltage regulation control loop in a resonant dc-dc converter such as that described with reference to  FIG. 1 . 
           [0039]      FIG. 3  shows the known current-controlled oscillator (CCO) in the commercial device L 6599  from STMicroelectronics as well as the circuit that implements the burst-mode operation. 
           [0040]      FIG. 4  shows the triangular wave generated by the CCO of  FIG. 3 , and its relationship with the gate-drive signals produced by the pulse-train generator. 
           [0041]      FIG. 5  shows the key waveforms that illustrate burst-mode operation of the CCO of  FIG. 3 , at light load. 
           [0042]      FIGS. 6A-E  show five possible examples of nonlinearity (“A”, “B”, “C”, “D”, “E”) in the ƒ osc (I FB ) function that, according to the applicant&#39;s findings, increase the energy transferred by a switching cycle of a resonant converter during burst-mode operation. 
           [0043]      FIG. 7  shows an exemplary embodiment of a circuit that implements a nonlinearity of type “A” in the ƒ osc (I FB ) function. 
           [0044]      FIG. 8  shows an exemplary embodiment of a circuit that implements a nonlinearity of type “B” in the ƒ osc (I FB ) function. 
           [0045]      FIG. 9  shows an exemplary embodiment of a circuit that implements a nonlinearity of type “C” in the ƒ osc (I FB ) function. 
           [0046]      FIG. 10  shows a first exemplary embodiment of a circuit that implements a nonlinearity of type “D” in the ƒ osc (I FB ) function. 
           [0047]      FIG. 11  shows a second exemplary embodiment of a circuit that implements a nonlinearity of type “D” in the ƒ osc (I FB ) function. 
           [0048]      FIG. 12  shows a third exemplary embodiment of a circuit that implements a nonlinearity of type “D” in the ƒ osc (I FB ) function. 
           [0049]      FIG. 13  shows a first exemplary embodiment of a circuit that implements a nonlinearity of type “E” in the ƒ osc (I FB ) function. 
           [0050]      FIG. 14  shows a second exemplary embodiment of a circuit that implements a nonlinearity of type “E” in the ƒ osc (I FB ) function. 
           [0051]      FIG. 15  shows a third exemplary embodiment of a circuit that implements a nonlinearity of type “E” in the ƒ osc (I FB ) function. 
           [0052]      FIG. 16  shows an external circuit that used for testing purposes, to implement a nonlinearity of type “C” in the ƒ osc (I FB ) function of STMicroelectronics resonant converter controller L 6599 . 
           [0053]      FIG. 17  shows evaluation data of the light-load efficiency observed in a 90 W LLC resonant converter based on STMicroelectronics controller L 6599  with the external circuit of  FIG. 16 , as compared to the same controller in a conventional circuit. 
           [0054]      FIG. 18  are oscilloscope screen shots showing that the increase in the output voltage ripple caused by the circuit in  FIG. 16  is acceptably low. 
       
    
    
     DETAILED DESCRIPTION 
       [0055]    As mentioned earlier, the effectiveness of burst-mode operation in increasing light load efficiency stems from the reduction of the average switching frequency, which leads to a reduction of the switching losses associated to the parasitic elements in the converter and of the conduction losses associated to the reactive currents flowing in the resonant tank. 
         [0056]    Therefore, to optimize efficiency during burst-mode operation, the power demanded by the load should be provided while minimizing the average switching frequency or, in other words, the number of switching cycles the converter performs per second. This can be achieved by maximizing the energy carried by the converter in each cycle, so as to reduce the number of cycles over time. 
         [0057]    Since in a resonant converter the power it delivers increases when the switching frequency is reduced, the energy per cycle will increase if during burst-mode the converter is forced to switch at a lower frequency. Therefore, with reference to the schematic in  FIG. 3 , the principle behind embodiments described in the present disclosure is to introduce a nonlinearity in the ƒ osc (I FB ) function just prior to reaching the discontinuity at I FB =(Vr−V th )/R 2 . To achieve a lower switching frequency this nonlinearity should originate an interval (I FB .a−I FB .b) where either the function ƒ osc (I FB ) or its derivative dƒ osc /dI FB  or both have a step discontinuity such that ƒ osc (I FB )≦ƒ osc (I FB .a) for I FB ε(I FB .a, I FB .b). I FB .a represents the point on the ƒ osc (I FB ) characteristic at which the nonlinearity begins, and I FB .b is the point on ƒ osc (I FB ) at which the circuit stops switching and enters idle time mode. Between the two points, although the current I FB  continues to rise, the switching frequency ƒ osc  does not, thus reducing the overall average switching frequency during burst mode operation. 
         [0058]    When increasing the energy-per-cycle level in burst-mode, this can produce an increase of the ripple in the output voltage. A trade-off can be employed to increase the energy-per-cycle without unduly increasing the ripple. 
         [0059]    An assumption that is done in the following discussion is that the current level I FB .bb=(Vr−V th −V H )/R 2  (refer to eq. (2)) at which the converter resumes switching is always ≧I FB .a. 
         [0060]      FIGS. 6A-6E  show five possible examples of nonlinearity meeting the above assumption and that lend well themselves to a simple circuit implementation. Nonlinearities “A” and “B” keep ƒ osc (I FB ) continuous and have a discontinuity in the derivative; nonlinearity “C” introduces a discontinuity in ƒ osc (I FB ) only; nonlinearities “D” and “E” introduce a discontinuity both in ƒ osc (I FB ) and its derivative. Nonlinearities “C” and “D” look almost identical. However, after the discontinuity, with the former the slope of ƒ osc (I FB ) is unchanged, whereas with the latter the slope of ƒ osc (I FB ) changes too. For small amplitude of the discontinuities, which is what happen in practice, they are actually nearly indistinguishable. 
         [0061]    In the following discussion some practical implementations of the nonlinearities of  FIGS. 6A-E  will be shown. They all refer to an exemplary current controlled oscillator (CCO) structure similar to that depicted in  FIG. 3 , including two current mirrors connected to a timing capacitor C 1  and wherein one or both mirrors are coupled, through other current mirrors in cascade, to a dedicated input pin of the oscillator in order to make possible that the charge and/or discharge current of the timing capacitor C 1  be proportional to a current (I r ) sunk through said dedicated input pin. 
         [0062]    Of course, similar types of functionality can be realized starting from different oscillator structures, with appropriate modifications that, in view of present disclosure, will be obvious to the skilled artisan. 
         [0063]    The circuit shown in  FIG. 7  is an example of implementation of the nonlinearity “A,” employing a current controlled oscillator (CCO)  10 A, a burst mode control circuit  12 A, a comparator CO 1 , and a pulse-train generator  13  according to one embodiment. The CCO  10 A includes a first current mirror  14 , including transistors Q 2 , Q 3 , Q 4 , bias resistor R B , and an inhibit switch SW; and a second current mirror  16 , including transistors Q 5 , Q 6 , connected to a timing capacitor C 1 . The inhibit switch SW enables (when closed) the oscillator by connecting the first current mirror  14  to a first clamp circuit  18 , including op-amp OA 1  and transistor Q 1 , in order to make possible that the charge and/or discharge current of the timing capacitor C 1  be proportional to a current (I r ) sunk through said dedicated input pin. Also connected to the input pin RFmin are resistors R 1 , R 2  and the optocoupler OC. The CCO  10 A also includes comparators CO 2 , CO 3 , a flip-flop FF, and a transistor Q 7  coupled to the second current mirror  16 . 
         [0064]    The burst mode control circuit  12 A includes a second clamp circuit  20  including an op-amp OA 2  and a transistor Q 8  coupled by another input pin STBY to the optocoupler OC; a current mirror  22  including transistors Q 9 , Q 10 ; a current mirror  24  including transistors Q 11 , Q 12 ; and a reference current source providing a reference current I ref . 
         [0065]    As long as I FB &lt;I FB .a (i.e., V STBY &gt;V th ), where I FB .a=(Vr−V th )/R 2 , it is I R2 =I FB  and I S =0. When I FB  equals I FB .a (i.e., when V STBY =V th ), a second precision clamp circuit  20  made up of the op-amp OA 2  and transistor Q 8  is activated and prevents V STBY  from further decreasing. Therefore, as the optocoupler OC sinks a current I FB &gt;I FB .a the current through R 2  remains fixed at I FB .a, and the oscillator frequency at ƒ osc (I FB .a). The extra current I S =I FB −I FB .a is provided by the clamp circuit  20 , in particular by Q 8 . This current is mirrored by transistors Q 9 , Q 10  and compared to the reference current I ref  mirrored by transistors Q 11 , Q 12 . As long as I S &lt;I ref  the collector of Q 11  is substantially at Vcesat and the output of the comparator CO 1  is low. When I S  becomes larger than I ref , the Vce of Q 11  goes up and as it exceeds V th1  the output of CO 1  goes high and inhibits the oscillator through the switch SW and the pulse-train generator  13 . Note, incidentally, that I FB .b=I FB .a+I ref . Note also that the CCO is exactly the same as that shown in  FIG. 3 . 
         [0066]    The circuit shown in  FIG. 8  is an example of implementation of the nonlinearity “B” employing a current controlled oscillator  10 B and a burst mode control circuit  12 B according to another embodiment. It can be thought as derived from the circuit in  FIG. 7  with the addition of current mirrors  26 ,  28 ,  30  in the CCO  10 B and current mirrors  32 ,  34  in the burst mode control circuit  12 B. The current mirror  26  includes transistors Q 3 , Q 4 , Q 15 , bias resistor R B , and inhibit switch SW, current mirror  28  includes transistors Q 14 , Q 16 , current mirror  30  includes transistors Q 2 , Q 13 , current mirror  32  includes transistors Q 9 , Q 10 , Q 17 , and current mirror  34  includes transistors Q 18 , Q 19 . 
         [0067]    It works substantially in the same way as the circuit in  FIG. 7 , except that the mirror  34  subtracts the current I S , sourced by Q 8 , from the current I R  sourced by Q 1  and going from Q 13  to the mirror  28 . Thus, this mirror and the subsequent mirrors  16 ,  26  in the chain, mirror I R −I S . As a result, the larger I S , the smaller the current KM·(I R −I S ) charging and discharging C 1  and, therefore, the lower ƒ osc (I FB )=ƒ osc (2I FB .a−I FB ). 
         [0068]    I FB .a and I FB .b are the same as in the previous circuit. For simplicity, the mirrors  32 ,  34  work with a 1:1 mirroring ratio; with a different mirroring ratio it is possible to change the slope of the ƒ osc (I FB ) characteristic in the region (I FB .a, I FB .b). 
         [0069]    The circuit of  FIG. 9  is an exemplary implementation of the nonlinearity “C” including a CCO  10 C and a burst mode control circuit  12 C according to an embodiment. The CCO is the same as that shown in  FIG. 3  except for the addition of a switch SPDT 1  that is configured to switch the reference voltage on the non-inverting input of the op-amp OA 1  between Vr and a second value Vr r &lt;Vr. The burst mode control circuit  12 C includes a comparator CO 4  having a non-inverting input coupled to the input pin STBY, an inverting input that receives the threshold voltage V th1 , and an output coupled to a control terminal of the switch SPDT 1 . Either reference voltage value is selected by the output of the comparator CO 4 : if the output is high (which occurs when I FB &lt;I FB .a i.e., V STBY &gt;V th1 , the single-pole double-throw switch SPDT 1  connects the non-inverting input of op-amp OA 1  to Vr, otherwise to Vr r . 
         [0070]    As V STBY =V th1  and the output of CO 4  goes low, the resulting drop ΔVr=Vr−Vr r  in the reference voltage for OA 1  determines the same drop ΔVr in the voltage appearing on the pin RFmin. As a consequence, also V STBY  will drop by ΔVr since I FB  is unchanged. If ΔVr≧V th1 −V th , V STBY  will immediately fall below V th , which asserts the output of CO 1  high, thus inhibiting the oscillator through the switch SW, and the pulse-train generator. In this case it is substantially I FB .a=I FB .b=(Vr−V th1 )/R 2 . If, instead ΔVr&lt;V th1 −V th , the frequency drop resulting from ΔVr voltage, equal to: 
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         [0000]    will force the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  will quickly fall below V th (&lt;V th1 ), thus triggering the same series of events as in the previous case. Note that the change ΔVr does not modify the slope of the ƒ osc (I FB ) relationship. 
         [0071]    In this case it is I FB .a=(Vr−V th1 )/R 2 , I FB .b=(Vr−V th )/R 2 . 
         [0072]    The circuit in  FIG. 10  is a first exemplary circuit that implements the nonlinearity “D” employing a CCO  10 D and a burst mode control circuit  12 D according to an embodiment. The burst mode control circuit  12 D includes a comparator CO 4  having a non-inverting input coupled to the input pin STBY, an inverting input that receives the threshold voltage V th1 , and an output coupled to the base of a transistor Q 21  coupled between the bases of transistors Q 18 , Q 19  and ground. The comparator CO 1  has its inverting and non-inverting inputs respectively coupled to the input pin STBY and the threshold voltage V th  and its output coupled to the switch SW and the pulse-train generator  13 . The CCO  10 D has the same structure as that in the circuit in  FIG. 8 , with the addition of a transistor Q 20  that mirrors a portion k1 (k1&lt;1) of I R  towards a current mirror  36 , including transistors Q 18 , Q 19 , of the burst mode control circuit  12 D. This subtracts the current k1I R  from the current I R  going from Q 13  to the mirror  28 . Thus, this mirror and the subsequent mirrors  14 ,  16 ,  26  in the chain, mirror (1−k1)I R . 
         [0073]    As long as I FB &lt;I FB .a (i.e., V STBY &gt;V th1 ), the output of comparator CO 4  is high, Q 21  is on and the mirror  36  is disabled; the current flowing through the chain of mirrors  14 ,  16 ,  28  is IR and the charge/discharge current for C 1  is KM·IR. As V STBY =V th1  the output of CO 4  goes low, Q 21  is switched off and the mirror  36  is activated; the current flowing through the chain of mirrors  14 ,  16 ,  28  jumps from IR to (1−k1)IR and the charge/discharge current for C 1  to KM·(1−k1)IR. 
         [0074]    The resulting frequency decrease will force the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  will quickly fall below V th (&lt;V th1 ), will assert the output of CO 1  high, thus inhibiting the oscillator through the switch SW and the pulse-train generator  13 . 
         [0075]    Also in this circuit it is I FB .a=(Vr−V th1 )/R 2 , I FB .b=(Vr−V th )/R 2 . 
         [0076]    The circuit in  FIG. 11  is a second exemplary circuit that implements the nonlinearity “D,” and includes a CCO  10 E and a burst mode control circuit  12 E according to another embodiment. The CCO  10 E includes a current mirror  38 ; including transistors Q 2 , Q 3 , Q 4 , Q 22 , Q 23  and inhibit switch SW; transistor Q 24  coupled between Q 22  and ground; transistor Q 25  coupled between Q 23  and ground; a first diode D 1  coupled between the emitters of Q 22  and Q 3 ; and a second diode D 2  coupled between the emitters of Q 23  and Q 4 . In this case the current mirror  38 , which charges and discharges C 1 , is split in two modules: Q 23 +Q 4  (charge), Q 22 +Q 3  (discharge via Q 5 , Q 6 ). Transistors Q 23  and Q 22  mirror a portion k1 (k1&lt;1) of IR, Q 4  and Q 3  mirror the remaining portion (1−k1) of IR. 
         [0077]    As long as V STBY &gt;V th1 , the output of comparator CO 4  is low, Q 24  and Q 25  are off, thus Q 22  and Q 23  deliver their collector current to the mirror Q 5 , Q 6  via diode D 1  and to capacitor C 1  via diode D 2 , respectively. Therefore, the charge/discharge current for C 1  is KM·IR. As V STBY =V th1  the output of CO 4  goes high, Q 24  and Q 25  are turned on, thus the collector current k1IR of both Q 22  and Q 23  is diverted to ground. The diodes D 1  and D 2  isolate Q 24  and Q 25  so that the oscillator operation is unaffected except for the charge/discharge current for C 1  that jumps to KM·(1−k1)IR. 
         [0078]    Also in this case, the resulting frequency decrease forces the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  quickly falls below V th (&lt;V th1 ), which asserts the output of comparator CO 1  high, thus inhibiting the oscillator through the switch SW and the pulse-train generator  13 . 
         [0079]    I FB .a and I FB .b are the same as in the previous circuit. 
         [0080]    The circuit in  FIG. 12  is a third exemplary circuit that implements the nonlinearity “D,” and includes a CCO  10 F and a burst mode control circuit  12 F according to a further embodiment. 
         [0081]    The burst mode control circuit  12 F is the same as the burst mode control circuit  12 B of  FIG. 9 . The CCO  10 F is the same as that shown in  FIG. 3  except for the addition of a single-pole double-throw switch SPDT 2  that is configured to switch the reference voltage on the non-inverting input of the comparator CO 2  between a first value V V1  and a second value V V2 &lt;V V1 . Either value is selected by the output of the comparator CO 4 : if the output is high (which occurs when V STBY &gt;V th1 ), the single-pole double-throw switch SPDT 2  connects the non-inverting input to V V1 , otherwise to V V2 . Note that V V1  corresponds to the 0.9 V reference voltage shown in the schematics in  FIGS. 7 to 11 . 
         [0082]    As long as V STBY &gt;V th1 , the output of CO 4  is high and the oscillator swing is ΔVosc=3.9−V V1 . As V STBY =V th1  and the output of CO 4  goes low, the peak-to-valley swing ΔVosc will increase by the difference V V1 −V V2 , thus originating a step reduction both in ƒ osc (I FB ) and in the slope of ƒ osc (I FB ) (refer to eq. 1), like the first two exemplary circuits. This frequency drop will force the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  will quickly fall below V th  (&lt;V th1 ), the output of CO 1  will be asserted high, thus inhibiting the oscillator through the switch SW, and the pulse-train generator. 
         [0083]    I FB .a and I FB .b are still the same. 
         [0084]    Obviously, the very same functionality can be obtained by changing the reference voltage for comparator CO 3  from a first value Vp 1  (=3.9 V) to a second value Vp 2 &gt;Vp 1 . 
         [0085]    It is worth noticing that the nonlinearity “E” can be thought as the combination of nonlinearity “D” and nonlinearity “A”. As such, one embodiment of its implementation can be the combination of the circuit in  FIG. 7  and the circuit in  FIG. 10 . This is shown in the exemplary circuit in  FIG. 13 , which includes a CCO  10 G and a burst mode control circuit  12 G. 
         [0086]    As long as I FB &lt;I FB .a (i.e., V STBY &gt;V th ), where I FB .a=(Vr−V th1 )/R 2 , it is I R2 =I FB  and I S =0. The output of CO 4  is high, Q 21  is on and the mirror  36  is off; the current flowing through the chain of mirrors  16 ,  26 ,  28  is IR and the charge/discharge current for C 1  is KM·IR. As V STBY =V th1  the output of CO 4  goes low, Q 21  is switched off and the mirror  36  is activated; the current flowing through the chain of mirrors  16 ,  26 ,  28  jumps from IR to (1−k1)IR and the charge/discharge current for C 1  to KM·(1−k1)IR. 
         [0087]    The resulting frequency decrease will force the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  will quickly fall and reach V th (&lt;V th1 ). The precision clamp made up of the op-amp OA 2  and Q 8  is activated and prevents V STBY  from further decreasing. Therefore, as the optocoupler sinks a current I FB &gt;(Vr−V th )/R 2 , I R2  is constant, and so is the oscillator frequency. The extra current I S  is provided by Q 8 . This current is mirrored by current mirror  22  and compared to the reference current I ref  mirrored by mirror  24 . As long as I S &lt;I ref  the collector of Q 11  is substantially at Vcesat and the output of the comparator CO 1  is low. When I S  becomes larger than I ref , the Vce of Q 11  goes up and as it exceeds Vth 2  the output of CO 1  goes high and inhibits the oscillator through the switch SW and the pulse-train generator  13 . 
         [0088]    In this circuit it is: I FB .a=(Vr−V th1 )/R 2 , I FB .b=(Vr−V th )/R 2 +I ref . 
         [0089]    According to an alternative embodiment, the implementation of nonlinearity “E” can be the combination of the circuit in  FIG. 7  and the circuit in  FIG. 11 . This is shown in the circuit in  FIG. 14 , which includes a CCO  10 H and a burst mode control circuit  12 H. 
         [0090]    As long as I FB &lt;I FB .a (i.e., V STBY &gt;V th ), where I FB .a=(Vr−V th1 )/R 2 , it is I R2 =I FB  and I S =0. The output of CO 4  is low, Q 24  and Q 25  are off, thus Q 22  and Q 23  deliver their collector currents to the mirror Q 5 , Q 6  via D 1  and to C 1  via D 2 , respectively. Therefore, the charge/discharge current for C 1  is KM·IR. As V STBY =V th1  the output of CO 4  goes high, Q 24 , Q 25  are turned on, thus the collector current k1IR of both Q 22  and Q 23  is diverted to ground. The diodes D 1  and D 2  isolate Q 24  and Q 25  so that the oscillator operation is unaffected except for the charge/discharge current for C 1  that jumps to KM·(1−k1)IR. 
         [0091]    Again, the resulting frequency decrease will force the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  will quickly fall down to V th (&lt;V th1 ). The precision clamp made up of the op-amp OA 2  and Q 8  is activated and prevents V STBY  from further decreasing. Therefore, as the optocoupler sinks a current I FB &gt;(Vr−V th )/R 2 , I R2  is constant, and so is the oscillator frequency. The extra current I S  is provided by Q 8 . This current is mirrored by Q 13 , Q 14  and compared to the reference current I ref  mirrored by Q 9 , Q 10 . As long as I S &lt;I ref  the collector of Q 11  is substantially at Vcesat and the output of the comparator CO 1  is low. When I S  becomes larger than I ref , the Vce of Q 11  goes up and as it exceeds V th2  the output of CO 1  goes high and inhibits the oscillator through the switch SW and the pulse-train generator  13 . 
         [0092]    In this circuit it is: I FB .a=(Vr−V th1 )/R 2 , I FB .b=(Vr−V th )/R 2 +I ref . 
         [0093]    Finally, according to an embodiment, the implementation of nonlinearity “E” can be the combination of the circuit in  FIG. 7  and the circuit in  FIG. 12 . This is shown in the circuit in  FIG. 15 , which includes a CCO  10 I and a burst mode control circuit  12 I. 
         [0094]    As long as I FB &lt;I FB .a (i.e., V STBY &gt;V th ), where I FB .a=(Vr−V th1 )/R 2 , it is I R2 =I FB  and I S =0. The output of CO 4  is high and the single-pole double-throw switch SPDT connects the non-inverting input to V V1 &gt;V V2 , so that the oscillator swing is ΔVosc=3.9−V V1 . As V STBY =V th1  and the output of CO 4  goes low and the swing ΔVosc increases by the difference V V1 −V V2 , thus originating a step reduction in ƒ osc (I FB ). 
         [0095]    Once more, the resulting frequency decrease will force the feedback loop to react by increasing I FB  to compensate for the sudden increase of energy delivery, so V STBY  will quickly fall down to V th (&lt;V th1 ), thus triggering the same series of events as in the previous cases. 
         [0096]    Among the five nonlinearities considered so far, the nonlinearity “A” has the advantage of leaving the CCO unchanged but appears to be the least effective since it exercises just a mild clamping action on the oscillator frequency. Additionally, it has the least flexibility: it is just a fixed change of slope to zero. All the others appear to be more effective because they exercise a stronger action on the oscillator frequency (they actually reverse the feedback from negative to positive) and the intensity of their action can be adjusted by changing either the mirroring ratios or the switched reference voltages. 
         [0097]    The nonlinearity “C” has also the advantage of keeping the CCO unchanged but introduces a fixed jump in the oscillator frequency proportional to the minimum switching frequency ƒ osc .min=ƒ osc (0) (refer to equations 1 and 3) and not to the switching frequency in the discontinuity point ƒ osc (I FB .a). This means that, depending on the frequency range, this discontinuity could be too large in some cases or too small in others. Programming the amplitude of the discontinuity with an external circuit could be a solution but would employ an additional dedicated pin, which might not be available. The discontinuity “C”, therefore, will not be considered for integration. 
         [0098]    The simplest implementation seems to be that of the nonlinearity “D”, in particular the circuit in  FIG. 12 , in which are added just a comparator CO 4  and the switch SPDT 2 . The experimental verifications have been therefore focused on nonlinearity “D”, although nonlinearities “B” and “E” look promising in terms of performance too and are definitely worth further investigations. 
         [0099]    To evaluate the effectiveness in terms of light load efficiency improvement an experiment has been realized using an external circuit to simulate that kind of nonlinearity. To this purpose, the circuit of  FIG. 16  has been built and connected to the resonant controller L 6599  mentioned earlier, and the effectiveness evaluated on a 90 W LLC resonant converter (Vin=400 V, Vout=19 V). 
         [0100]    The circuit is composed of a current generator (R 3 , R 4 , D 4 , Q 26 ) that sources about 20 μA when the base of Q 26  is pulled low via R 5  by the output of one of the comparators included in the LM 393 . This comparator receives on its inverting input a reference voltage generated by the shunt regulator TL 431  and the adjustment circuit composed of R 6 , R 9  and the potentiometer R 8 . The non-inverting input is connected to STBY through R 7  that, in combination with R 10  provides the comparator with a small hysteresis. R 8  has been tuned to the values of V th , and the hysteresis V H  of CO 1  in the L 6599 , to properly set the position of I FB .a at (Vr−V th −V H )/R 4 . 
         [0101]    When transistor Q 26  is turned on, the current IR has a sudden 20 μA negative step change. 20 μA is about 10% of IR when I FB =I FB .a. This causes an equal change in the charge/discharge current of C 1  (in the L 6599 , KM=1) and, therefore, a proportional reduction in the switching frequency, which triggers the above described reversal of the feedback sign and pushes V STBY  below V th . 
         [0102]    It is worth noticing that this circuit implements the nonlinearity “C” and not the nonlinearity “D”. In fact, the circuit of  FIG. 16 , although similar in concept to the circuit in  FIG. 10 , subtracts a fixed amount of current, so it creates a discontinuity in ƒ osc (I FB ) but leaves its slope unchanged. However, as previously highlighted, for small discontinuities like in our case they are almost indistinguishable, so their difference in terms of performance is not expected to be significant. 
         [0103]    The results of the bench evaluation of the experimental converter are summarized in the graph of  FIG. 17 , where the efficiency with and without the external circuit are compared. The load range taken into consideration goes from 0.25 to 7.5 W, i.e., from 0.28% to 8.3% of the nominal load. In this range the external circuit has brought an efficiency rise around 5% on average. As shown in the oscilloscope pictures of  FIG. 18 , the increase in the output voltage ripple is moderate and, for most applications, tolerable: from 1% to 1.2% of Vout. 
         [0104]    One skilled in the art will recognize that corresponding voltage-controlled oscillators could be used in place of the current-controlled oscillators discussed above. 
       REFERENCES 
       [0000]    
       
         [1] B. Wang, X. Xin, S. Wu, H. Wu, J. Ying, “Analysis and Implementation of LLC Burst Mode for Light Load Efficiency Improvement”, Applied Power Electronics Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual IEEE, Page(s): 58-64. 
         [2] J. Qin, Z. Moussaoui, J. Liu, G. Miller, “Light Load Efficiency Enhancement of a LLC Resonant Converter”, Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE, Page(s): 1764-1768 
         [3] F. Weiyi, F. C. Lee, P. Mattavelli, H. Daocheng, C. Prasantanakorn, “LLC resonant converter burst mode control with constant burst time and optimal switching pattern”, Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE, Page(s): 6-12 
         [4] Y. Liu, “High Efficiency Optimization of LLC Resonant Converter for Wide Load Range”. Thesis, Virginia Polytechnic Institute and State University, 2007. 
       
     
         [0109]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Technology Classification (CPC): 7