Patent Abstract:
A level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between source and drain of each of the first transistor and the second transistor.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2013-213144 filed on Oct. 10, 2013, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein are related to a level shifter, a DC (direct current)-DC converter, and a level shift method. 
     BACKGROUND 
     A DC-DC converter has two switch elements which are cascode-coupled between a power supply and the ground and performs DC-DC conversion by turning the two switch elements on and off in a complementary manner. As these two switch elements, N-channel metal-oxide semiconductor field effect transistors (MOSFETs) are used. An N-channel MOSFET has a lower on-resistance and a smaller parasitic capacitance (a smaller amount of capacitance charging and discharging) than a p-channel MOSFET. 
     Related techniques are disclosed in Japanese Laid-open Patent Publication No. 2010-4198 and a non-patent document: V. Pinon et al. (STMicroelectronics), “A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130 MHz Switched-Mode Power Supply”, ISSCC Dig. Tech. Papers, pp. 564-565, February 2008. 
     SUMMARY 
     According to an aspect of the embodiment, a level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal which is in a complementary relation with the first input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between a source and a drain of each of the first transistor and the second transistor. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates an example of a DC-DC converter; 
         FIG. 2  illustrates an example of a DC-DC converter; 
         FIG. 3  illustrates an example of an operation of a level shifter; 
         FIG. 4  illustrates an example of a DC-DC converter; 
         FIG. 5  illustrates an example of an operation of a level shifter; 
         FIG. 6  illustrates an example of a method for determining a capacitance of a capacitive element; 
         FIG. 7  illustrates an example of a method for determining a capacitance of a capacitive element; 
         FIG. 8  illustrates an example of a DC-DC converter; 
         FIG. 9  illustrates an example of result of breakdown-voltage validation for transistors; 
         FIG. 10  illustrates an example of result of breakdown-voltage validation for transistors; and 
         FIG. 11  illustrates an example of result of breakdown-voltage validation for transistors. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     A potential at a source of one of two switch elements which is coupled to the power supply side (called a high-side switch hereinbelow) changes from 0 V to a power supply voltage. In order to drive the high-side switch, a level shifter and a booster circuit, for example, a bootstrap circuit, are used to change a control signal (gate signal) to a voltage larger than the power-supply voltage. 
     For example, the voltage exceeding the power-supply voltage and applied to a transistor included in the level shifter may exceed a breakdown voltage of the transistor. Therefore, if a transistor with a high withstanding voltage is used, manufacture costs might increase. 
       FIG. 1  illustrates an example of a DC-DC converter. A DC-DC converter  1  may be a buck circuit, and includes a level shifter  2 , a booster circuit  3 , inverters  4  and  5 , a buffer  6 , a pulse signal generator  7 , a high-side switch HSW, a low-side switch LSW, a coil Lx, and a capacitive element Cx. 
     The high-side switch HSW and the low-side switch LSW may be n-channel MOSFETs, and are cascode-coupled between a power supply and the ground. Via the coil Lx, an output terminal OUT and one terminal of the capacitive element Cx are coupled to a midpoint between the high-side switch HSW and the low-side switch LSW. The other terminal of the capacitive element Cx is coupled to ground. 
     An output signal VoutP of the level shifter  2  is input as a control signal to a gate of the high-side switch HSW via the inverter  4 . A pulse signal generated by the pulse signal generator  7  is input as a control signal to a gate of the low-side switch LSW via the buffer  6 . The inverter  4  may operate at a voltage obtained by boosting Vdd (power-supply voltage) in the booster circuit  3 . The buffer  6  may operate at Vdd. 
     The level shifter  2  changes the potential level of the control signal to the high-side switch HSW by receiving the voltage obtained by the booster circuit  3  by boosting Vdd and changing the potential level of the pulse signal generated by the pulse signal generator  7 . 
     The level shifter  2  receives an input signal VinP which is the pulse signal generated by the pulse signal generator  7  and an input signal VinN obtained by inverting, in the inverter  5 , the logic level of the pulse signal generated by the pulse signal generator  7 . For example, the input signal VinP and the input signal VinN may be in a complementarity relation with each other. The inverter  5  may operate at Vdd. 
     In  FIG. 1 , the booster circuit  3  may be a bootstrap circuit. The booster circuit  3  includes: a diode  3 - 2  whose anode is coupled to the power supply and whose cathode is coupled to the level shifter  2 ; and a capacitive element  3 - 1  whose one terminal is coupled to the cathode of the diode  3 - 2  and the other terminal is coupled to the midpoint between the high-side switch HSW and the low-side switch LSW. The booster circuit  3  boosts Vdd when the high-side switch HSW is on. 
     The level shifter  2  includes input inverters  2 - 1  and  2 - 2 , cascode portions  2 - 3  and  2 - 4 , a latch portion  2 - 5 , a transistor pair  2 - 6 , and a potential-difference suppression circuit  2 - 7 . 
     The input inverter  2 - 1  inverts the logic level of the input signal VinP, and the input inverter  2 - 2  inverts the logic level of the input signal VinN. The input inverters  2 - 1  and  2 - 2  may operate at Vdd. 
     The cascode portion  2 - 3  includes a transistor Tr 1  which is a p-channel MOSFET and a transistor Tr 2  which is an n-channel MOSFET, the transistors Tr 1  and Tr 2  being cascode-coupled to each other. The cascode portion  2 - 3  transmits an input signal VA which is a signal obtained by inverting the logic level of the input signal VinP in the input inverter  2 - 1 . 
     A source of the transistor Tr 1  is coupled to the latch portion  2 - 5 , and a drain of the transistor Tr 1  is coupled to a drain of the transistor Tr 2 . A gate of the transistor Tr 1  is coupled to the transistor pair  2 - 6  and the midpoint between the high-side switch HSW and the low-side switch LSW. 
     A source of the transistor Tr 2  is coupled to an output terminal of the input inverter  2 - 1 , and Vdd is applied to a gate of the transistor Tr 2 . The cascode portion  2 - 4  includes a transistor Tr 3  which is a p-channel MOSFET and a transistor Tr 4  which is an n-channel MOSFET, the transistors Tr 3  and Tr 4  being cascode-coupled to each other. The cascode portion  2 - 4  transmits an input signal VC which is a signal obtained by inverting the logic level of the input signal VinN in the input inverter  2 - 2 . 
     A source of the transistor Tr 3  is coupled to the latch portion  2 - 5 , and a drain of the transistor Tr 3  is coupled to a drain of the transistor Tr 4 . A gate of the transistor Tr 3  is coupled to the midpoint between the high-side switch HSW and the low-side switch LSW. 
     A source of the transistor Tr 4  is coupled to an output terminal of the input inverter  2 - 2 , and Vdd is applied to a gate of the transistor Tr 4 . The latch portion  2 - 5  includes transistors Tr 5  and Tr 6  which are p-channel MOSFETs. The latch portion  2 - 5  outputs, as a control signals to the high-side switch HSW, output signals VoutP and VoutN obtained by changing, based on a voltage obtained by boosting Vdd, the potential of the input signal VA or VC transmitted from the cascode portion  2 - 3  or  2 - 4 , and also retains the output signals VoutP and VoutN. In  FIG. 1 , the output signal VoutP may be used as the control signal. 
     Sources of the transistors Tr 5  and Tr 6  are coupled to the booster circuit  3 , and a voltage Vbst is applied to the sources of the transistors Tr 5  and Tr 6 . The voltage Vbst may be a voltage obtained by boosting Vdd, for example, 2Vdd, when the booster circuit  3  performs boosting operation. A drain of the transistor Tr 5  is coupled to a gate of the transistor Tr 6  and the source of the transistor Tr 1  of the cascode portion  2 - 3 . A drain of the transistor Tr 6  is coupled to a gate of the transistor Tr 5  and the source of the transistor Tr 3  of the cascode portion  2 - 4 . 
     The transistor pair  2 - 6  has transistors Tr 7  and Tr 8  which are n-channel MOSFETs. A drain of the transistor Tr 7  is coupled to the drain of the transistor Tr 5  and the gate of the transistor Tr 6  of the latch portion  2 - 5 . A drain of the transistor Tr 8  is coupled to the drain of the transistor Tr 6  and the gate of the transistor Tr 5  of the latch portion  2 - 5 . 
     The potential-difference suppression circuit  2 - 7  is coupled in parallel to the cascode portion  2 - 3 , and may suppress a potential difference between the source and the drain of each of the transistors Tr 1  and Tr 2 . In the cascode portion  2 - 3 , the output signal VoutN has a voltage obtained by boosting Vdd, at a falling timing of the input signal VA. If the rate of fall of the output signal VoutN is slower than that of a potential VB at a midpoint between the transistors Tr 1  and Tr 2 , the potential difference between the source and the drain of the transistor Tr 1  might increase, resulting in that a drain-source voltage exceeds its breakdown voltage (see  FIG. 3 ). If the rate of fall of the potential VB is slower than that of the input signal VA, the potential difference between the source and the drain of the transistor Tr 2  might increase, resulting in that a drain-source voltage exceeds its breakdown voltage (see  FIG. 3 ). Therefore, the potential-difference suppression circuit  2 - 7  may have a function to reduce increase in the drain-source potential difference (see  FIG. 5 ). 
     In the potential-difference suppression circuit  2 - 7 , the above function may be implemented by two breakdown-voltage protection elements  2 - 7   a  and  2 - 7   b . The breakdown-voltage protection elements  2 - 7   a  and  2 - 7   b  may, for example, each be a capacitive element or multiple diodes coupled in series. 
     When capacitive elements are used as the breakdown-voltage protection elements  2 - 7   a  and  2 - 7   b  (see  FIG. 4 ), the capacitive elements adjust the rate of fall of the potential of the output signal VoutN and the potential VB. Thus, the drain-source voltage of each of the transistor Tr 1  and Tr 2  might not exceed the breakdown voltage. 
     When diodes are used as the breakdown-voltage protection elements  2 - 7   a  and  2 - 7   b  (see  FIG. 8 ), the diodes are coupled in series, the number of the diodes being determined based on the breakdown voltage of the transistor Tr 1  and/or the transistor Tr 2 . Thus, the diodes are turned on before the drain-source voltage of each of the transistors Tr 1  and Tr 2  reaches the breakdown voltage, and the diodes thus perform clipping. 
     Such provision of the potential-difference suppression circuit  2 - 7  may decrease occurrence of a case where a voltage exceeding a breakdown voltage is applied to the transistors Tr 1  and Tr 2 . For this reason, transistors with a high breakdown voltage do not have to be used as the transistors Tr 1  and Tr 2 , which may decrease the costs for manufacturing the level shifter  2  and the DC-DC converter  1 . 
     In the cascode portion  2 - 4 , the output signal VoutP is Vdd at a falling timing of the input signal VC (see  FIG. 3 ). Thus, a potential difference exceeding Vdd might not be applied to the transistors Tr 3  and Tr 4 . For this reason, the potential-difference suppression circuit  2 - 7  provided to the cascode portion  2 - 3  does not have to be provided to the cascode portion  2 - 4 . 
     The provision of the transistor pair  2 - 6  in which the transistors Tr 7  and Tr 8  are coupled in the coupled state illustrated in  FIG. 1  may decrease occurrence of a case where a voltage exceeding a breakdown voltage is applied to the transistors Tr 5  and Tr 6  of the latch portion  2 - 5 . 
       FIG. 2  illustrates an example of a DC-DC converter. 
     Elements of a DC-DC converter  1   a  illustrated in  FIG. 2  which are substantially the same as or similar to elements of the DC-DC converter  1  illustrated in  FIG. 1  are denoted by the same reference numerals, and the description thereof will be omitted or reduces. A level shifter  2   a  of the DC-DC converter is illustrated in  FIG. 2  is not provided with the potential-difference suppression circuit  2 - 7  illustrated in  FIG. 1 . A transistor pair  2 - 6   a  has a different configuration from the transistor pair  2 - 6  of the level shifter  2  illustrated in  FIG. 1 . 
     One I/O terminal (source or drain) of the transistor Tr 7  of the transistor pair  2 - 6   a  is coupled between the transistor Tr 1  of the cascode portion  2 - 3  and the transistor Tr 5  of the latch portion  2 - 5 . One I/O terminal of the transistor Tr 8  is coupled between the transistor Tr 3  of the cascode portion  2 - 4  and the transistor Tr 6  of the latch portion  2 - 5 . 
     Vdd is applied to the other I/O terminals of the transistors Tr 7  and Tr 8 . The gates of the transistors Tr 7  and Tr 8  are coupled to the midpoint between the high-side switch HSW and the low-side switch LSW (and the coil Lx). The transistor pair  2 - 6   a  has a function to reduce increase in the potential difference between the output signal VoutN or VoutP and the boosted voltage Vbst when the output signal VoutN or VoutP transitions. 
     Other configurations illustrated in  FIG. 2  may be substantially the same as or similar to the configuration of the DC-DC converter  1  illustrated in  FIG. 1 .  FIG. 3  illustrates an example of an operation of a level shifter.  FIG. 3  illustrates the input signals VinN and VinP, the input signal VA to the cascode portion  2 - 3 , the potential VB at the midpoint between the transistors Tr 1  and Tr 2 , the input signal VC to the cascode portion  2 - 4 , the potential VD at the midpoint between the transistors Tr 3  and Tr 4 , and the output signals VoutN and VoutP, as well as the voltage Vbst supplied to the latch portion  2 - 5 . For example, the booster circuit  3  may boost Vdd to, but not limited to, 2Vdd. 
     At an initial stage of “State 1”, the high-side switch HSW is on so that the voltage Vbst obtained by the booster circuit  3  is 2Vdd. At a falling timing of the input signal VA, the transistors Tr 5  and Tr 6  are on and off, respectively, and the output signal VoutN and the potential VB are about 2Vdd, while the output signal VoutP is at a potential lower than Vdd. 
     When the input signal VinP rises from 0 V to Vdd and the input signal VinN falls from Vdd to 0 V, the input signal VA of the cascode portion  2 - 3  falls from Vdd to 0 V. Thereby, the potential VB starts falling to 0 V with a delay equivalent to a delay by the transistor Tr 2 . The potential of the output signal VoutN also starts falling, but since the Transistor Tr 5  is on, the rate of fall is slower than that of the potential VB. 
     The input signal VC to the cascode portion  2 - 4  rises from 0 V to Vdd by the fall of the potential of the input signal VinN, and the potential VD starts rising with a delay equivalent to a delay by the transistor Tr 4 . As the potential of the output signal VoutN decreases, the transistor Tr 6  starts being turned on. Thus, the potential of the output signal VoutP and the potential VD increase up to about 2Vdd. 
     In “State 2”, once the output signal VoutP increases up to about 2Vdd, the transistor Tr 5  is turned off. Thus, the output signal VoutN falls at a higher rate down to 0 V. Output of the inverter  4  becomes Low level, and the voltage Vbst falls to Vdd by turning-off of the high-side switch HSW. Thereby, the output signal VoutP also falls to about Vdd. 
     In “State 3”, when the input signal VinP falls from Vdd to 0 V and the input signal VinN rises from 0 V to Vdd, the input signal VA of the cascode portion  2 - 3  rises from 0 V to Vdd. Subsequently, the potential VB and the potential of the output signal VoutN also start rising. 
     By the rise of the potential of the input signal VinN, the input signal VC to the cascode portion  2 - 4  falls from Vdd to 0 V. The potential VD subsequently falls, as well. By the fall of the potential VD, the output signal VoutP also starts falling, but since the transistor Tr 6  is on, the rate of the fall is slower that of the potential VD. As the potential of the output signal VoutP decreases, the transistor Tr 5  starts being turned on. 
     In “State 4”, when the output signal VoutP reaches about 0 V, output of the inverter  4  becomes High level, turning on the high-side switch HSW so that the booster circuit  3  performs boosting operation. Consequently, the voltage Vbst becomes twice as large as Vdd, and the output signal VoutN and the potential VB also increase to about 2Vdd. 
     Once the high-side switch HSW is turned on, Vdd is applied to the source of the high-side switch HSW. Thus, Vdd is applied to the gates of the transistors Tr 1 , Tr 3 , Tr 7 , and Tr 8 . For example, when the output signal VoutP is about 0 V and the output signal VoutN is about Vdd, the transistor Tr 3  is off, and the transistors Tr 8  and Tr 7  of the transistor pair  2 - 6   a  are on and off, respectively. Thus, the potential of the output signal VoutP rises via the transistor Tr 8  up until it reaches a voltage lower than Vdd by a threshold voltage Vth of the transistor Tr 8 . 
     In the operation of the level shifter  2   a  described above, in “State 1”, the falling timing of the potential VB is later than the falling timing of the input signal VA. Hence, a voltage equal to or larger than Vdd may be applied to between the drain and source of the transistor Tr 2 . The rate of fall of the potential of the output signal VoutN is slower than that of the potential VB. Hence, a voltage equal to or larger than Vdd may be applied to between the drain and source of the transistor Tr 1 . In this way, in “State 1”, a voltage exceeding the breakdown voltage of the transistor Tr 1  or Tr 2  might be applied. 
     In “State 4”, when the voltage Vbst is 2Vdd, the output signal VoutP is a voltage lower than Vdd by the threshold voltage Vth of the transistor Tr 8 . Thus, a voltage equal to or larger than Vdd may be applied to between the drain and source of the transistor Tr 6  of the latch portion  2 - 5 , and a voltage equal to or larger than Vdd may be applied to between the drain and source of the transistor Tr 5  of the latch portion  2 - 5 . In this way, in “State 4”, a voltage exceeding the breakdown voltage of the transistor Tr 5  or Tr 6  of the latch portion  2 - 5  might be applied. 
       FIG. 4  illustrates an example of a DC-DC converter. The DC-DC converter illustrated in  FIG. 4  has a level shifter using capacitive elements as breakdown voltage protection elements. 
     In a DC-DC converter  1   b , a potential-difference suppression circuit  2   b - 7  of a level shifter  2   b  has capacitive elements C 1  and C 2 . The capacitive element C 1  is coupled between the output terminal of the input inverter  2 - 1  and the midpoint between the transistors Tr 1  and Tr 2  of the cascode portion  2 - 3 . The capacitive element C 2  is coupled between the drain of the transistor Tr 1  and the midpoint between the transistors Tr 1  and Tr 2  of the cascode portion  2 - 3 . 
       FIG. 5  illustrates an example of an operation of a level shifter.  FIG. 5  illustrates the input signals VinN and VinP, the input signal VA to the cascode portion  2 - 3 , the potential VB at the midpoint between the transistors Tr 1  and Tr 2 , the input signal VC to the cascode portion  2 - 4 , the potential VD at the midpoint between the transistors Tr 3  and Tr 4 , and the output signals VoutN and VoutP, as well as the voltage Vbst supplied to the latch portion  2 - 5 . 
     In the level shifter  2   b  illustrated in  FIG. 4 , “State 1” may be divided into Steps S 1  and S 2  below: 
     (Step S 1 ) The potential VB falls from 2Vdd to Vdd almost at the same time that the input signal VA falls, due to feedforward from the capacitive element C 1 . The capacitance of the capacitive element C 1  is set to a certain value, for example, Cmin or larger. Thus, when the potential of the input signal VA is 0 V, the potential VB may be about Vdd. For this reason, occurrence of a case where a drain-source voltage to the transistor Tr 2  exceeds Vdd may be suppressed. Hence, a transistor with a high breakdown voltage might not have to be used as the transistor Tr 2 . In Step S 1 , the potential of the output signal VoutN largely falls at almost the same time that the potential VB falls, due to feedforward from the capacitive element C 2 . 
     (Step S 2 ) Due to a voltage retaining function of the capacitive element C 1 , when the voltage VB falls from Vdd to 0 V at a lower rate, the rate of fall of the potential VB decreases. The potential of the output signal VoutN further decreases due to a current source effect of the transistor Tr 1  and the capacitive element C 2 . For this reason, occurrence of a case where a drain-source voltage to the transistor Tr 1  exceeds Vdd may be suppressed. Hence, a transistor with a high breakdown voltage might not have to be used as the transistor Tr 1 . 
       FIG. 6  illustrates an example of a method for setting the capacitance of a capacitive element. The capacitance of the capacitive element C 1  may be set in  FIG. 6 .  FIG. 6  illustrates an equivalent circuit of part of the level shifter  2  having a signal source  10  and two capacitive elements C 1  and Cpb. The signal source  10  may be an equivalently-illustrated part configured to supply the input signal VA. The capacitive element Cpb is a gate-drain parasitic capacitance of the transistors Tr 1  and Tr 2 . 
     When Vmax is the breakdown voltage of the transistor Tr 2 , the condition for the potential VB may be VB Vmax. Assume that, when the potential of the input signal VA falls down to 0 V, ΔC 1  is the amount of change in voltage across the capacitive element C 1 , and ΔC pb  is the amount of voltage change in voltage across the capacitive element Cpb. Then, under an assumption that the total amount of charge does not change, Formula (1) below is obtained:
 
 C   1   ·ΔC   1   =C   pb   ·ΔC   pb   (1)
 
     where C 1  indicates the capacitance of the capacitive element C 1 , and C pb  indicates the capacitance of the capacitive element Cpb. Formula (2) below is obtained by rearranging Formula (1):
 
 C   1   =C   pb   ·ΔC   pb   /ΔC   1   =C   pb ·(2 Vdd−VB )/( VB−Vdd ).  (2)
 
     To satisfy the relation VB Vmax, the capacitance C 1  only has to satisfy the relation of Formula (3) below:
 
 C   1   ≧C   pb ·(2 Vdd−V max)/( V max− Vdd ).  (3)
 
     “C pb ·(2Vdd−Vmax)/(Vmax−Vdd)” in the above formula may correspond to Cmin. 
       FIG. 7  illustrates an example of a method for setting a capacitance of a capacitive element. The capacitance of the capacitive element C 2  may be set in  FIG. 7 .  FIG. 7  illustrates an equivalent circuit of part of the level shifter  2  having a signal source  11  and two capacitive elements C 2  and CpboutN. The signal source  11  may be an equivalently-illustrated part configured to generate the potential VB. The capacitive element CpboutN is the parasitic capacitance of the transistors Tr 1 , Tr 5 , Tr 6 , Tr 7 , and Tr 8  which are coupled to a node N 1  in  FIG. 4 . 
     When the capacitive element C 2  is added, the output signal VoutN falls at the same time that the potential VB falls, decreasing the potential difference between the potential VB and the output signal VoutN. Consequently, the transistor Tr 1  may be protected so that a drain-source voltage will not exceed the breakdown voltage of the transistor Tr 1 . The larger the capacitance of the capacitive element C 2 , the more effective that may be. 
     However, too large capacitance of the capacitive element C 2  makes the falling width of the output signal VoutN large, which may possibly cause the drain-source voltage to the transistor Tr 5  or the gate-source voltage to the transistor Tr 6  of the latch portion  2 - 5  to exceed the breakdown voltage. For this reason, when the potential VB falls down to 0 V, the voltage of the output signal VoutN (simply referred to as VoutN hereinbelow) may satisfy the relation of Formula (4) below:
 
 V out N≧Vbst−V max=2 Vdd−V max.  (4)
 
     Since the total amount of charge does not change, a capacitance C 2  of the capacitive element C 2  is expressed as Formula (5) below:
 
 C   2   =C   pboutN ·(2 Vdd−V out N )/ V out N.   (5)
 
     To satisfy the relation in Formula (4), the capacitance C 2  only has to satisfy the relation in Formula (6) below:
 
 C   2   ≦C   pboutN   ·V max/(2 Vdd−V max).  (6)
 
     If the capacitance C 2  of the capacitive element C 2  is increased, the rate of fall of the potential of the output signal VoutN becomes high, which may possibly protect the transistor Tr 1 . For example, providing an upper limit to the capacitance C 2  as indicated in Formula (6) may decrease occurrence of a case where a drain-source voltage exceeding the breakdown voltage of the transistor Tr 5  of the latch portion  2 - 5  is applied to the transistor Tr 5 . 
     The potential-difference suppression circuit  2   b - 7  includes the capacitive elements C 1  and C 2 . The potential-difference suppression circuit  2   b - 7  may suppress occurrence of direct current and decrease power consumption. Between “State 3” and “State 4” depicted in  FIG. 5 , the voltage Vbst and the output signal VoutN are about Vdd, and the output signal VoutP is about 0 V. Thus, the transistors Tr 5  and Tr 6  are on and off, respectively, and the transistors Tr 7  and Tr 8  of the transistor pair  2 - 6  are off and on, respectively. The transistor Tr 8  is coupled to the coil Lx. When the output signal VoutP is about 0 V, the high-side switch HSW is turned on, and therefore the voltage at the source of the high-side switch HSW becomes about Vdd. Thus, the output signal VoutP rises to about Vdd. In the transistor pair  2 - 6  of the level shifter  2   b , the gate of the transistor Tr 8  is not coupled to the coil Lx, but is coupled so that the output signal VoutN may be input thereto. For this reason, when the transistor Tr 8  is on, the output signal VoutP might not fall short of Vdd by the amount of Vth, and therefore the output signal VoutP may be maintained at about Vdd. In “State 4”, the potential difference between the voltage Vbst and the output signal VoutP is about Vdd. Hence, occurrence of a case may be suppressed where a voltage exceeding the breakdown voltage is applied to the transistor Tr 5  or Tr 6  of the latch portion  2 - 5 . 
       FIG. 8  illustrates an example of a DC-DC converter. The DC-DC converter illustrated in  FIG. 8  has a level shifter using diodes as breakdown voltage protection elements. 
     A potential-difference suppression circuit  2   c - 7  of a level shifter  2   c  of a DC-DC converter is includes diodes Da 1  to Dan and Db 1  to Dbn. The diodes Da 1  to Dan are coupled in series between the output terminal of the input inverter  2 - 1  and the midpoint between the transistors Tr 1  and Tr 2 . The cathode is coupled to the output terminal of the input inverter  2 - 1 , and the anode is coupled to the midpoint between the transistors Tr 1  and Tr 2 . 
     The diodes Db 1  to Dbn are coupled in series between the midpoint between the transistors Tr 1  and Tr 2  and the drain of the transistor Tr 1 . The cathode is coupled to the midpoint between the transistors Tr 1  and Tr 2 , and the anode is coupled to the drain of the transistor Tr 1 . 
     The number of the diodes Da 1  to Dan and Db 1  to Dbn may be set according to the breakdown voltage of the transistors Tr 1  and Tr 2 . The number of the diodes Da 1  to Dan and that of the diodes Db 1  to Dbn may be set to satisfy Formula (7) below:
 
 Vds max&gt; n·Vf   (7)
 
     where Vdsmax is the drain-source breakdown voltage of the transistors Tr 1  and Tr 2 , and Vf is a forward voltage of the diodes Da 1  to Dan and Db 1  to Dbn. 
     For example, when Vdsmax=5.5 V and Vf=0.6 V, n may be 9. Before a drain-source voltage exceeding the breakdown voltage Vdsmax is applied to the transistor Tr 1  or Tr 2 , the diodes Da 1  to Dan and Db 1  to Dbn are turned on to possibly protect the transistors Tr 1  and Tr 2 . 
     Since the potential-difference suppression circuit  2   c - 7  includes the diodes Da 1  to Dan and Db 1  to Dbn, the circuit area may be reduced compared to a case using capacitive elements. 
       FIG. 9  illustrates an example of result of breakdown-voltage validation for transistors.  FIG. 9  illustrates a result of withstanding-voltage validation by simulation for the transistors Tr 1 , Tr 2 , Tr 5 , or Tr 6  of the level shifter  2   a  illustrated in  FIG. 2 . The horizontal axis represents time (ns), and the vertical axis represents voltage (V).  FIG. 9  illustrates drain-source voltages Vdstr 1 , Vdstr 2 , and Vdstr 6  of the transistors Tr 1 , Tr 2 , and Tr 6  and a gate-source voltage Vgstr 5  of the transistor Tr 5 . Vmax and −Vmax indicate the breakdown voltage of the transistor Tr 1 , Tr 2 , Tr 5 , or Tr 6 . 
     As depicted in  FIG. 9 , in the level shifter  2   a , the drain-source voltage Vdstr 2  of the transistor Tr 2  exceeds the breakdown voltage Vmax. The drain-source voltage Vdstr 1  and Vdstr 6  of the transistors Tr 1  and Tr 6  exceed the breakdown voltage −Vmax. The gate-source voltage Vgstr 5  of the transistor Tr 5  also exceeds the breakdown voltage −Vmax. 
     Since a voltage exceeding the breakdown voltage Vmax or −Vmax is applied to the transistors Tr 1 , Tr 2 , Tr 5 , and Tr 6  of the level shifter  2   a , the transistors Tr 1 , Tr 2 , Tr 5 , and Tr 6  may break. 
       FIG. 10  illustrates an example of result of breakdown-voltage validation for transistors.  FIG. 10  illustrates a result of breakdown-voltage validation by simulation for the transistors of the level shifter  2   b  having the potential-difference suppression circuit using capacitive elements. The horizontal axis represents time (ns), and the vertical axis represents voltage (V). Like  FIG. 9 ,  FIG. 10  illustrates drain-source voltages Vdstr 1 , Vdstr 2 , and Vdstr 6  of the transistors Tr 1 , Tr 2 , and Tr 6  and a gate-source voltage Vgstr 5  of the transistor Tr 5 . 
     As depicted in  FIG. 10 , in the level shifter  2   b  having the potential-difference suppression circuit  2   b - 7  using the capacitive elements C 1  and C 2 , a voltage exceeding the breakdown voltage Vmax or −Vmax is not applied to the transistors Tr 1 , Tr 2 , Tr 5 , and Tr 6 . Hence, transistors with a high breakdown voltage might not have to be used. 
       FIG. 11  illustrates an example of result of breakdown-voltage validation for transistors.  FIG. 11  illustrates a result of breakdown-voltage validation by simulation for the transistors of the level shifter  2   c  having the potential-difference suppression circuit using diodes. The horizontal axis represents time (ns), and the vertical axis represents voltage (V). Like  FIG. 9 ,  FIG. 11  illustrates drain-source voltages Vdstr 1 , Vdstr 2 , and Vdstr 6  of the transistors Tr 1 , Tr 2 , and Tr 6  and a gate-source voltage Vgstr 5  of the transistor Tr 5 . 
     As depicted in  FIG. 11 , in the level shifter  2   c  having the potential-difference suppression circuit  2   c - 7  using the diodes Da 1  to Dan and Db 1  to Dbn, a voltage exceeding the breakdown voltage Vmax or −Vmax is not applied to the transistors Tr 1 , Tr 2 , Tr 5 , and Tr 6 . Hence, transistors with a high breakdown voltage might not have to be used. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Technology Classification (CPC): 7