Patent Abstract:
A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to U.S. Provisional Patent Application No. 61/504,948, entitled “Asynchronous Power Disconnect,” filed on Jul. 6, 2011, the entire contents of which are incorporated herein by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The disclosed subject matter is generally related to network on chip (NoC) design. 
       BACKGROUND 
       [0003]    One valuable feature (among many others) of modern network-on-chips (NoCs) is the ability to run part of the network at a first clock frequency and part of the network at a second clock frequency. This allows part of the network with high data transfer bandwidth requirements to run fast while other parts run more slowly, easing the timing closure challenge for engineers and electronic design automation (EDA) tools. Separate clock domains also allow parts of a chip to run at different frequencies depending on the data processing requirements, using a slower clock frequency to save dynamic power while data processing requirements are relatively low. Separate clock domains are also useful when parts of the network are a significant distance apart on the chip because clock tree insertion and balancing across significant distances is difficult. Allowing parts of the NoC to run just with localized clocks avoids that difficulty. 
         [0004]    A network on chip employs a unit of logic known as a clock domain adapter to transfer data correctly between logic in two different clock domains. In particular, a clock domain adapter for transferring data between asynchronous clock domains is known as an asynchronous clock domain adapter. The logic of an asynchronous clock domain adapter generally comprises two portions: a sender that sends data and a receiver that receives data. 
         [0005]      FIG. 1  is a simplified block diagram illustrating an example asynchronous clock domain adapter unit  100 . The adapter unit  100  includes circular buffer  102 , multiplexer  104 , write control  106  and read control  108 . Data sender logic is clocked in a sending clock domain while data receiver logic is clocked in a receiving clock domain. In adapter unit  100 , the signals that pass between the sender and receiver include data elements in circular buffer  102 , also known as a bisynchronous first-in-first-out (FIFO) buffer. The circular buffer  102  can be coupled to the multiplexer  104 . The multiplexer  104  outputs data elements from the circular buffer  102  based on a read pointer (RdPtr) value. The write control unit  106  is configured to control a Gray coded write data counter for generating a write count (WrCnt). The read control unit  108  is configured for controlling a Gray coded read data counter  106  for generating a read count (RdCnt) and the read pointer (RdPtr). 
         [0006]    Another valuable feature of an asynchronous clock domain adapter is the ability to power off part of the network-on-chip without causing functional failure or data loss or corruption for the rest of the chip. The ability to power off part of a chip is useful for saving power. Power-off is typically used when a processing function is not required. For example, a video codec intellectual property (IP) block might be powered off in a mobile device application processor when no video is being played. 
         [0007]    The set of logic that is powered on or off together is known as a power domain. Within a wake-up sequence, some (usually most) of the logic in the power domain is reset to a known state. This enables the engagement of an appropriate data transfer protocol from a predictable state of operation. In conventional power disconnect units the logic on both sides (the already-awake and the waking-up) run on a common clock. This ensures that one side does not take on an unpredictable state while the other side is beginning to engage the communication protocol. 
         [0008]    In conventional NoCs, an asynchronous clock domain adapter sender and an asynchronous clock domain adapter receiver can reside in the same power domain. If one is running while the other is powered off the adapter unit can take on an unpredictable state, leading to data loss or instability. Specifically, when an asynchronous clock domain adapter unit is powered on and reset, the state of WrCnt in the sender and the state of WrCnt in the synchronization registers of the receiver are both the same and the state of RdCnt in the receiver and RdCnt in the synchronization registers of the sender are the same and RdPtr is known to the write control unit  106 . If one wakes up and is reset while the other is still running they would tend to reset with unsynchronized pointers, leading to data being sent twice or data being lost or other unpredictable behavior. 
         [0009]    In other words, an asynchronous clock domain adapter unit and a power disconnect unit may operate correctly in series if there is no asynchronous clock domain adapter between the master and slave sides of a power disconnect unit and there is no power disconnect unit between the asynchronous clock domain adapter sender and the asynchronous clock domain adapter receiver. 
         [0010]    When laying out a chip it is often desirable to have logic within a single clock domain localized within a common region. This is because it is difficult to insert and balance a clock tree when the clock nets extend over significant distances. It is also often desirable to have logic within a single power domain localized within a common region. This is because it is difficult to comingle the wiring carrying power from many different power supplies within a shared region of the chip. Basically, localization is valuable, and increasingly so as modern chips are designed with increasingly many power domains and increasingly many clock domains. 
         [0011]    Furthermore, it is valuable to have a small number of network-on-chips. This is because the complexity of transferring data through a network-on-chip occurs at the edges of the network where packets are encoded and decoded and all of the interconnecting logic is relatively simple. The fewer network-on-chips, the less logic overhead is required for encoding and decoding packets. Such logic is expensive in silicon die area, logic path delay, and clock cycles of latency for transferring data. As a result, network-on-chips must span multiple, and usually many, clock domains and power domains. 
         [0012]      FIG. 2  illustrates a network-on-chip with a physical distance between sides of a power disconnect unit downstream of an asynchronous clock domain adapter unit. An impediment to localization arises when an asynchronous clock domain adapter and a power disconnect unit are placed in series within a data link in a network-on-chip.  FIG. 2  shows an initiator IN that request a write transaction to send data to a target TA through an asynchronous clock domain adapter sender SE REQ in the request path, an asynchronous clock domain adapter receiver RE REQ in the request path, a downstream disconnect unit master side manager MA, and a disconnect unit slave side manager SL. Response data is returned through SL and MA and an asynchronous clock domain adapter sender SE RSP and an asynchronous clock domain adapter receiver RE RSP. The physical placement of the units is such that MA and SL are far apart (indicated by the dashed line). In this configuration the units have good localization in the power domains but have poor localization in clock domains. The clock signal of clock domain Y spans the significant distance between the logic of MA and SL. This configuration challenges clock tree insertion. 
         [0013]      FIG. 3  illustrates a network-on-chip with a physical distance between senders and receivers of asynchronous clock domain adapter units upstream of a power disconnect unit. More particularly,  FIG. 3  shows a configuration of the same components but with MA and SL close together and with SE REQ separated from RE REQ by a significant distance and SE RSP separated from RE RSP by a significant distance. This configuration is preferable to that of  FIG. 2  for clock tree insertion because no clock signals spans a significant distance. However, this configuration requires the power supply of power domain A to span the significant distance, which challenges supply rail routing. 
         [0014]      FIG. 4  illustrates a network-on-chip with a distance between senders and receivers of asynchronous clock domain adapter units downstream of a power disconnect unit. More particularly,  FIG. 4  shows a configuration in which the power disconnect unit is upstream of the asynchronous clock domain adapters in the request data flow. The asynchronous clock domain adapter unit senders and receivers are placed at a significant distance. This configuration suffers a supply rail routing challenge. 
         [0015]      FIG. 5  is a network-on-chip with a distance between sides of a power disconnect unit upstream of an asynchronous clock domain adapter unit. More particularly,  FIG. 5  shows a configuration with the same components but with the power disconnect unit master side manager and slave side manager placed at a significant distance. This configuration suffers a clock tree insertion challenge. 
         [0016]    Some network-on-chips do not include a response path. For such configurations  FIGS. 2-5  are applicable, but without the SE RSP and RE RSP components and no response data path. 
         [0017]      FIG. 6  illustrates an example power disconnect unit. Request data from master to slave and response data from slave to master are connected as in any system of a single power domain, except that they are separated by power isolation cells. The SocketConn signal indicates to the slave that the master is connected and can send traffic. The SlvRdy signal indicates to the master that the slave can be safely powered off without the loss of transactions in flight. SocketConn and SlvRdy are also connected between master and slave through power isolation cells. The clock signal is generated in the power-on domain and connected to the power-off domain through an isolation cell. 
         [0018]    The disclosed invention pertains, particularly, to networks of clocked logic. A unit with an ability to correctly transfer data between logic in a first clock domain and logic in a second clock domain is known as an asynchronous clock domain adapter. This is because the two clocks have no synchronized relationship to each other. The invention does not pertain to networks of asynchronous logic, also known as self-timed logic. Such networks transfer data without a corresponding clock signal. 
       SUMMARY 
       [0019]    The disclosed implementations are directed to a power disconnect module that integrates an asynchronous clock domain crossing. In some implementations, a power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0020]      FIG. 1  illustrates an asynchronous clock domain adapter unit. 
           [0021]      FIG. 2  illustrates a power disconnect unit with a physical distance between sides of a power disconnect unit downstream of an asynchronous clock domain adapter unit. 
           [0022]      FIG. 3  illustrates a power disconnect unit with a physical distance between senders and receivers of asynchronous clock domain adapter units upstream of a power disconnect unit. 
           [0023]      FIG. 4  illustrates a power disconnect unit with a physical distance between senders and receivers of asynchronous clock domain adapter units downstream of a power disconnect unit. 
           [0024]      FIG. 5  illustrates a power disconnect unit with a physical distance between sides of a power disconnect unit upstream of an asynchronous clock domain adapter unit. 
           [0025]      FIG. 6  illustrates a conventional power disconnect unit. 
           [0026]      FIG. 7  is an example power disconnect unit with a physical distance between the sides of a power disconnect unit and a distance between the senders and receivers of asynchronous clock domain adapter units. 
           [0027]      FIG. 8  illustrates an example power disconnect unit with a mode to bypass the asynchronous clock domain adapter unit. 
           [0028]      FIG. 9  illustrates an example power disconnect unit that includes two asynchronous clock domain adapter units. 
           [0029]      FIG. 10  illustrates an example timing diagram for a master domain power off and power on sequence of a power disconnect unit engaging data transfer protocol. 
           [0030]      FIG. 11  illustrates an example timing diagram for a slave domain power off and power on sequence of a power disconnect unit engaging data transfer protocol. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    A network-on-chip is disclosed that includes an asynchronous clock domain adapter unit inserted between a master side manager and a slave side manager of a power disconnect unit. An example of such a network-on-chip is shown in  FIG. 7 . 
         [0032]      FIG. 7  is an example power disconnect unit with a physical distance between the sides of a power disconnect unit and a physical distance between the senders and receivers of asynchronous clock domain adapter units. 
         [0033]    In some implementations, a power disconnect unit  700  can include an initiator  702  (IN) connected to a target  704  (TA) through a request datapath and a response datapath. IN and TA can be independently powered on and off within power domains A and B respectively. The power disconnect protocol can be between a master side manager  706  (MA) and a slave side manager  708  (SL). In this example, within the power disconnect unit  700  the request datapath passes through an upstream sender  710  (SE REQ) and a downstream receiver  712  (RE REQ) of an asynchronous clock domain adapter unit. Likewise, within the power disconnect unit  700  the response datapath passes through a sender  714  (SE RSP) and a receiver  716  (RE RSP) of an asynchronous clock domain adapter unit. The upstream and downstream components are physically placed at a significant distance apart (indicated by the dashed lines). The upstream components can operate within a single power domain A and clock domain X. The downstream components can operate within a single power domain B and clock domain Y. As a result, no clock signal passes the significant distance between components and no power rail wires are routed the significant distance between components. As a result, the logic of all units is localized, avoiding the challenges of significant distance clock tree insertion and significant distance power rail routing. 
         [0034]      FIG. 8  illustrates an example power disconnect unit with a mode to bypass the asynchronous clock domain adapter unit. More particularly,  FIG. 8  shows another example power disconnect unit  800  comprising a request path but no response path. A master side manager  802  (MA) sends data through an upstream router  804  (UR) that, in one mode, sends data through a sender  806  (SE) and a receiver  808  (RE) of an asynchronous clock domain adapter to a downstream multiplexer  810  (DM) that passes the data to slave side manager  812  (SL) and, in another mode, sends data directly through DM  810  to SL  812 , bypassing SE  806  and RE  808 . Such an embodiment allows the chip to avoid data delay inherent to an asynchronous clock domain adapter unit when running in a mode in which clock domain X and clock domain Y are synchronized. 
         [0035]      FIG. 9  illustrates an example power disconnect unit that includes two asynchronous clock domain adapter units. More particularly,  FIG. 9  shows a more detailed diagram of the example implementation of  FIG. 7 . In  FIG. 9 , request data from the power disconnect unit master side manager  706  to the slave side manager  708  and response data from slave side manager  708  to master side manager  706  are connected through asynchronous clock domain adapter unit senders  710  and receivers  712 , except that they are separated by power isolation cells  902 . 
         [0036]    In this example, the SocketConn signal indicates to the slave that the master is connected and can send traffic. The ConnAck signal is the resynchronized copy of SocketConn, plus 2 cycles. It is resynchronized in the master side manager  706  and resets the asynchronous clock domain adapter sender  710 , once the power disconnect unit slave side manager  708  has done the same on the asynchronous clock domain adapter receiver  712 . The SlvRdy signal indicates to the master side manager that the slave side manager can be safely powered off without the loss of transactions in flight. SocketConn, ConnAck, and SlvRdy are also connected between the master side manager  706  and slave side manager  708  through power isolation cells  902 . The clock signals on the master side and slave side are generated separately (and physically distant) in their respective power domains. The asynchronous clock domain adapter senders  710  and  714  and receivers  712  and  716  each receive a power on signal  904  that, when asserted, resets the component logic. The master side manager  706  generates ReqPwrOn to reset the request path asynchronous clock domain adapter sender  710  and generates RspPwrOn to reset the response path asynchronous clock domain adapter receiver  712 . The slave side manager  708  generates ReqPwrOn to reset the request path asynchronous clock domain adapter receiver  712  and generates RspPwrOn to reset the response path asynchronous clock domain adapter sender  714 . 
         [0037]      FIG. 10  is an example timing diagram for a master domain power off and power on sequence of a power disconnect unit engaging a data transfer protocol. Referring to the implementation shown in  FIG. 9 , after the system level power manager requests power-off of the master power domain, the following steps occur: 
         [0038]    1. The power disconnect unit master side manager fences new requests. The process of fencing includes stalling the request path or responding with an error signal; 
         [0039]    2. The power disconnect unit master side manager waits until it has drained (received all pending) responses from the power disconnect unit slave side manager for all pending requests; 
         [0040]    3. The power disconnect unit master side manager deasserts SocketConn. It also disables the response asynchronous clock domain adapter receiver by deasserting MstRspPwrOn. This prevents spurious transmissions in the response path caused by the SE RSP reset that will occur later; 
         [0041]    4. The power disconnect unit slave side manager disables the response asynchronous clock domain adapter sender by deasserting SlvRspPwrOn. This resets the SE RSP unit, including RdCnt and the WrCnt synchronization registers. The power disconnect unit slave side manager also disables the request asynchronous clock domain adapter receiver by deasserting SlvReqPwrOn. This prevents spurious transmissions in the request path caused by the SE REQ reset that will occur later; 
         [0042]    5. The power disconnect unit slave side manager deasserts ConnAck to indicate that it is ready for the power disconnect; 
         [0043]    6. The power disconnect unit master side manager disables the request asynchronous clock domain adapter sender by deasserting MstReqPwrOn. This resets the SE REQ unit, including WrCnt and the RdCnt synchronization registers; and 
         [0044]    7. The system level power manager disconnects the power supply from the master domain. SocketConn remains undriven while SlvRdy and ConnAck are held by the power disconnect unit slave side manager. 
         [0045]    When the system level power manager requests wake-up of the master power domain, it connects power and deasserts reset. The following steps occur for the wake-up: 
         [0046]    1. The power disconnect unit master side manager asserts SocketConn. It also resets and enables the response asynchronous clock domain adapter receiver by asserting MstRspPwrOn. At this step, the power disconnect unit master side manager is able to receive request packets, but will assert backpressure upstream to stall traffic; 
         [0047]    2. The power disconnect unit slave side manager receives SocketConn and asserts ConnAck. It also resets and enables the response asynchronous clock adapter sender by asserting SlvRspPwrOn. It also resets and enables the request asynchronous clock adapter receiver by asserting SlvReqPwrOn; 
         [0048]    3. The power disconnect unit master side manager receives ConnAck and enables and resets the request asynchronous clock domain adapter sender by asserting MstReqPwrOn. It also stops stalling and request data transfers and begins sending the requests through the request asynchronous clock domain adapter unit; and 
         [0049]    4. The power disconnect unit slave side manager receives data transfer responses and passes them through the asynchronous clock domain adapter receiver to the power disconnect unit master side manager. 
         [0050]      FIG. 11  is an example timing diagram for a slave domain power off and power on sequence of a power disconnect unit engaging data transfer protocol. When the system level power manager requests power-off and power-on of the slave domain, the steps are the same as for power-off and power-on of the master domain except that, as shown in  FIG. 11 , the power disconnect unit slave side manager can signal to the power disconnect unit master side manager that it wants to power off and wants to power on. This can be done with the SlvRdy signal before step 1 in each procedure above. Also, when the slave domain is powered off, the power disconnect unit master side manager holds SocketConn and SlvRdy and ConnAck remain undriven.

Technology Classification (CPC): 8