Patent Abstract:
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a divisional of application Ser. No. 10/338,530, filed Jan. 8, 2003, pending, which is a divisional of application Ser. No. 09/819,472, filed Mar. 28, 2001, now U.S. Pat. No. 6,545,498, issued Apr. 8, 2003, which is a divisional of application Ser. No. 09/166,369, filed Oct. 5, 1998, now U.S. Pat. No. 6,329,832, issued Dec. 11, 2001. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates in general to semiconductor manufacturing and, more specifically, to in-line testing of flip-chip semiconductor assemblies. 
   2. State of the Art 
   As shown in  FIG. 1 , in a conventional process  10  for manufacturing flip-chip semiconductor assemblies, singulated dice are flip-chip attached with a conductive epoxy or solder to a printed circuit board (PCB) or other substrate to form a flip-chip semiconductor assembly. Once the dice are attached by curing of the epoxy or reflow of the solder, the dice are then encapsulated, underfilled, or both, using a nonconductive epoxy or other encapsulation material. The electrical characteristics of the flip-chip semiconductor assembly are then tested and, if the assembly passes the test, it is selected for shipping to customers. 
   If the flip-chip semiconductor assembly does not pass the test, then it proceeds to a repair station, where it is repaired using one or more “known-good dice” (KGD)  12  (i.e., dice that have already passed all standard electrical tests and have been through burn-in). Specifically, those dice in the assembly that are believed to have caused the assembly to fail the test are electrically disconnected from the rest of the assembly, typically using laser fuses. One or more KGD are then attached to the PCB of the assembly to replace the disconnected dice. Once the KGD are attached, the assembly is retested and, if it passes, it too is selected for shipping to customers. 
   The conventional KGD repair process described above generally works well to repair flip-chip semiconductor assemblies, but the process necessary to produce KGD can be an expensive one. Also, the described KGD repair process does not test for, or repair, problems with the interconnections between the dice and the PCB in a flip-chip semiconductor assembly. Rather, it only repairs problems with non-functioning dice or defective solder bumps. Finally, the KGD in the described repair process end up going through burn-in twice: a first time so they can be categorized as a KGD, and a second time when the flip-chip semiconductor assembly to which they are attached goes through burn-in. This is obviously a waste of burn-in resources and also stresses the KGD far beyond that necessary to weed out infant mortalities. 
   Therefore, there is a need in the art for a method of testing flip-chip semiconductor assemblies that reduces or eliminates the need for the KGD repair process described above. 
   BRIEF SUMMARY OF THE INVENTION 
   In a method for electrically testing a flip-chip semiconductor assembly in accordance with this invention, the assembly is tested using, for example, an in-line or in-situ test socket or probes after one or more integrated circuit (IC) dice and a substrate, such as a printed circuit board (PCB), are brought together to form the assembly and before the IC dice are encapsulated or otherwise sealed for permanent operation. As a result, any problems with the IC dice or their interconnection to the substrate can be fixed before sealing of the dice complicates repairs. The method thus avoids the problems associated with conventional known-good-die (KGD) repairs. Also, speed grading can be performed while the dice are tested. 
   The assembly may be manufactured using a “wet” conductive epoxy, such as a heat-snap-curable, moisture-curable, or radiation-curable epoxy, in which case bond pads on the IC dice can be brought into contact with conductive bumps on the substrate formed of the epoxy for the testing, which can then be followed by curing of the epoxy to form permanent die-to-substrate interconnects if the assembly passes the test. If the assembly does not pass the test, the lack of curing allows for easy repair. After curing but before sealing of the IC dice, the assembly can be tested again to detect any interconnection problems between the IC dice and the substrate. 
   The assembly may also be manufactured using a “dry” conductive epoxy, such as a thermoplastic epoxy, for conductive die-attach, in which case the IC dice and the substrate can be brought together and the epoxy cured to form permanent die-to-substrate interconnections, after which the testing may take place. Since the testing occurs before sealing of the IC dice, repair is still relatively easy. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       FIG. 1  is a flow chart illustrating a conventional repair method for flip-chip semiconductor assemblies using known-good dice (KGD); 
       FIG. 2  is a flow chart illustrating a method for in-line testing of flip-chip semiconductor assemblies in accordance with this invention; 
       FIG. 3  is an isometric view of a flip-chip semiconductor assembly and in-line test socket or probes implementing the method of  FIG. 2 ; 
       FIG. 4  is a flow chart illustrating a method for in situ testing of flip-chip semiconductor assemblies in accordance with this invention; and 
       FIG. 5  is an isometric view of a flip-chip semiconductor assembly and in situ test socket implementing the method of FIG.  4 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   As shown in  FIGS. 2 and 3 , in a process  20  for manufacturing flip-chip semiconductor assemblies in accordance with this invention, a printed circuit board (PCB)  22  is indexed into a die attach station (not shown), where it is inserted into an in-line test socket  24  or contacted by probes  25 . It will be understood by those having skill in the technical field of this invention that the invention is applicable not only to PCBs, but also to a wide variety of other substrates used in the manufacture of flip-chip semiconductor assemblies. 
   When conductive epoxy dots  26  or “pads” deposited on the PCB  22  at the die ends of die-to-board-edge conductive traces  30  are made from a “wet” epoxy (i.e., a quick-cure epoxy such as a heat-snap-curable, radiation-curable, or moisture-curable epoxy), then integrated circuit (IC) dice  28  are pressed (active surfaces down) against the dots  26  during flip-chip attach so electrical connections are formed between the dice  28  and the in-line test socket  24  or probes  25  through the dots  26  and conductive traces  30  on the PCB  22 . Of course, it will be understood that the invention is also applicable to other flip-chip die-attach methods including, for example, solder-based methods. It will also be understood that the dice  28  may be of any type, including, for example, Dynamic Random Access Memory (DRAM) dice, Static RAM (SRAM) dice, Synchronous DRAM (SDRAM) dice, microprocessor dice, Application-Specific Integrated Circuit (ASIC) dice, and Digital-Signal Processor (DSP) dice. 
   Once such electrical connections are formed, an electrical test is performed on the flip-chip semiconductor assembly  32  formed by the dice  28  and the PCB  22  using the in-line test socket  24  or probes  25 . This test typically involves checking for open connections that should be closed, and vice versa, but it can also involve more, fewer, or different electrical tests as need dictates. For example, the testing may also include speed grading the dice  28  for subsequent speed sorting. Also, the testing typically occurs while the PCB  22  is singulated from its carrier (not shown). 
   If the assembly  32  fails the test, it is diverted to a rework station, where any dice  28  identified as being internally defective or as having a defective interconnection with the PCB  22  can easily be removed and reworked, either by repairing the failing dice  28  themselves or by repairing conductive bumps (not shown) on the bottom surfaces of the dice  28  used to connect the dice  28  to the conductive epoxy dots  26  on the PCB  22 . Once repaired, the assembly  32  returns for retesting and, if it passes, it is advanced in the process  20  for quick curing along with all assemblies  32  that passed the test the first time through. 
   During quick cure, the “wet” epoxy dots  26  of the assembly  32  are cured, typically using heat, radiation, or moisture. The assembly  32  is then electrically tested again to ensure that the quick curing has not disrupted the interconnections between the dice  28  and the conductive traces  30  through the conductive epoxy dots  26  and the bumps (not shown) on the bottom surfaces of the dice  28 . If quick curing has disrupted these interconnections, then the assembly  32  proceeds to the rework station, where the connections between the bumps and the dots  26  can be repaired. The repaired assembly  32  is then retested and, if it passes, it proceeds to encapsulation (or some other form of sealing) and, ultimately, is shipped to customers along with those assemblies  32  that passed this testing step the first time through. Of course, it should be understood that this invention may be implemented with only one test stage for “wet” epoxy assemblies, although two stages are preferable. 
   When the conductive epoxy dots  26  are made from a “dry” epoxy (e.g., a thermoplastic epoxy), then the PCB  22  is indexed and inserted into the in-line test socket  24  or connected to the probes  25  as described above, but the dice  28  are attached to the PCB  22  using heat before the assembly  32  proceeds to testing. Testing typically takes place while the PCB  22  is singulated from its carrier (not shown). 
   During testing, if the assembly  32  fails, then it proceeds to a rework station, where the bumps on the bottom of the dice  28 , the dice  28  themselves, or the interconnection between the bumps and the conductive epoxy dots  26  can be repaired. The repaired assembly  32  then proceeds to encapsulation (or some other form of sealing) and, eventually, is shipped to customers along with those assemblies  32  that passed the testing the first time through. 
   Thus, this invention provides a repair method for flip-chip semiconductor assemblies that is less expensive than the previously described known-good-die (KGD) based rework process, because it does not require the pretesting of dice that the KGD process requires. Also, the methods of this invention are applicable to testing for both internal die defects and die-to-PCB interconnection defects, and to repairing interconnections between dice and a PCB in a flip-chip semiconductor assembly, whereas the conventional KGD process is not. In addition, these inventive methods do not waste bum-in resources, in contrast to the conventional KGD process previously described. Finally, this invention allows for early and convenient speed grading of flip-chip semiconductor assemblies. 
   As shown in  FIGS. 4 and 5 , in a process  40  for manufacturing flip-chip semiconductor assemblies in accordance with this invention, a printed circuit board (PCB)  42  is indexed into a die attach station (not shown), where it is inserted into an in situ test socket  44 . It will be understood by those having skill in the technical field of this invention that the invention is applicable not only to PCBs but also to a wide variety of other substrates used in the manufacture of flip-chip semiconductor assemblies. 
   When conductive epoxy dots  46  or “pads” deposited on the PCB  42  at the die ends of die-to-board-edge conductive traces  50  are made from a “wet” epoxy (i.e., a quick-cure epoxy such as a heat-snap-curable, radiation-curable, or moisture-curable epoxy), then integrated circuit (IC) dice  48  are pressed (active surfaces down) against the dots  46  during flip-chip attach so electrical connections are formed between the dice  48  and the in situ test socket  44  through the dots  46  and conductive traces  50  on the PCB  42 . Of course, it will be understood that the invention is also applicable to other flip-chip die-attach methods including, for example, solder-based methods. It will also be understood that the dice  48  may be of any type, including, for example, Dynamic Random Access Memory (DRAM) dice, Static RAM (SRAM) dice, Synchronous DRAM (SDRAM) dice, microprocessor dice, Application-Specific Integrated Circuit (ASIC) dice, and Digital Signal Processor (DSP) dice. 
   Once such electrical connections are formed, an electrical test is performed on the flip-chip semiconductor assembly  52  formed by the dice  48  and the PCB  42  using the in situ test socket  44 . This test typically involves checking for open connections that should be closed, and vice versa, but it can also involve more, fewer, or different electrical tests as need dictates. If the assembly  52  fails the test, it is diverted to a rework station, where any dice  48  identified as being internally defective or as having a defective interconnection with the PCB  42  can easily be removed and reworked, either by repairing the failing dice  48  themselves or by repairing conductive bumps (not shown) on the bottom surfaces of the dice  48  used to connect the dice  48  to the conductive epoxy dots  46  on the PCB  42 . Once repaired, the assembly  52  returns for retesting and, if it passes, it is advanced in the process  40  for quick curing along with all assemblies  52  that passed the test the first time through. 
   During quick cure, the “wet” epoxy dots  46  of the assembly  52  are cured, typically using heat, radiation, or moisture. The assembly  52  is then electrically tested again to ensure that the quick curing has not disrupted the interconnections between the dice  48  and the conductive traces  50  through the conductive epoxy dots  46  and the bumps (not shown) on the bottom surfaces of the dice  48 . If quick curing has disrupted these interconnections, then the assembly  52  proceeds to another rework station, where the connections between the bumps and the dots  46  can be repaired. The repaired assembly  52  is then retested and, if it passes, it proceeds to encapsulation (or some other form of sealing) and, ultimately, is shipped to customers along with those assemblies  52  that passed this testing step the first time through. Of course, it should be understood that this invention may be implemented with only one test stage for “wet” epoxy assemblies, although the two stages shown in  FIG. 4  are preferable. 
   When the conductive epoxy dots  46  are made from a “dry” epoxy (e.g., a thermoplastic epoxy), then the PCB  42  is indexed and inserted into the in situ test socket  44  as described above, but the dice  48  are attached to the PCB  42  using heat before the assembly  52  proceeds to testing. During testing, if the assembly  52  fails, then it proceeds to a rework station, where the bumps on the bottom of the dice  48 , the dice  48  themselves, or the interconnection between the bumps and the conductive epoxy dots  46  can be repaired. The repaired assembly  52  then proceeds to encapsulation (or some other form of sealing) and, eventually, is shipped to customers along with those assemblies  52  that passed the testing the first time through. 
   Thus, this invention provides a repair method for flip-chip semiconductor assemblies that is less expensive than the previously described known-good-die (KGD) based rework process, because it does not require the pretesting of dice that the KGD process requires. Also, the methods of this invention are applicable to testing for both internal die defects and die-to-PCB interconnection defects, and to repairing interconnections between dice and a PCB in a flip-chip semiconductor assembly, whereas the conventional KGD process is not. In addition, these inventive methods do not waste burn-in resources, in contrast to the conventional KGD process previously described. 
   Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent methods that operate according to the principles of the invention as described herein.

Technology Classification (CPC): 8