Patent Abstract:
An inverter circuit for lighting discharge lamps with reduced power consumption is disclosed. The inverter circuit comprises: a transformer having a resonant circuit formed by a parasitic capacitance of a discharge lamp; an H-bridge circuit to drive a primary side of the transformer at a frequency which is less than a series resonant frequency of the resonant circuit, and at which phase difference in voltage and current at the primary side of the transformer falls within a predetermined range from its minimum; a logic circuit to produce, based on an output signal of an oscillating circuit, gate signals for driving the H-bridge circuit; and a step-up circuit to step up a DC supply voltage (Vcc) based on another output signal of the oscillating circuit, and to supply the logic circuit with the stepped up DC voltage as a supply voltage for producing the gate signals.

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to an inverter circuit for lighting discharge lamps for use in a liquid crystal display unit, and the like, and particularly to an inverter circuit with a high power efficiency.  
         [0003]     2. Description of the Related Art  
         [0004]     In some conventional inverter circuits for lighting discharge lamps, a resonant circuit may be formed by leakage inductance at the secondary side of a transformer and by parasitic capacitance in a discharge lamp connected as load, and the primary side of the transformer may be driven by a resonant frequency of the resonant circuit thus formed. An example of such inverter circuits is disclosed in U.S. Pat. No. 6,114,814. Such a conventional inverter circuit to drive the primary side by the resonant frequency involves phase difference in voltage and current at the primary side of the transformer consequently failing to achieve a favorable power efficiency.  
         [0005]     In order to cope with the problem described above, Japanese Patent Application Laid-Open No. 2003-168585 discloses an inverter circuit for discharge lamps, in which a transformer is driven in a frequency range where phase difference in voltage and current at the primary side of the transformer is small thereby providing a high power efficiency, whereby the power efficiency of the transformer is improved. The inverter circuit for discharge lamps disclosed in the aforementioned Japanese Patent Application Laid-Open No. 2003-168585 comprises: a transformer where a resonant circuit is formed by parasitic capacitance in a discharge lamp and auxiliary capacitance; and an H-bridge circuit where the primary side of the transformer is driven at a frequency which is less than a series resonant frequency of the resonant circuit, and at which phase difference in voltage and current at the primary side of the transformer falls within a predetermined range from its minimum, thus the power efficiency is improved.  
         [0006]     In an inverter circuit for discharge lamps used in a liquid crystal television (TV) which is one example of liquid crystal display (LCD) units, a supply voltage ranges from 12 to 24V. For example, in a separate driving inverter which is described in connection with the aforementioned inverter circuit disclosed in Japanese Patent Application Laid-Open No. 2003-168585, and which uses a leakage magnetic flux type transformer, an inverter control IC to constitute a control section of the inverter circuit is operated by a supply voltage of 5.0V, and an H-bridge circuit with an FET to drive a transformer thereby lighting discharge lamps is operated by a voltage of 12 to 24V.  
         [0007]     Recently, a liquid crystal TV is increasing in its screen size, and as many as 8 to 24 discharge lamps are employed in one liquid crystal TV, and also the length of discharge lamps is increased to, for example, 1300 mm. This results in increasing the power consumption up to 180 W. Accordingly, in case of a large-sized liquid crystal TV, its inverter circuit and its discharge lamps are responsible for most of the power consumption, and therefore the inverter circuit is required to be further improved in efficiency for reducing its power consumption.  
         [0008]     In order to answer the above-described requirement for improved efficiency of an inverter circuit for discharge lamps, there is provided an inverter circuit in which a voltage supplied to the H-bridge circuit for lighting discharge lamps is increased from conventional 12 to 24V up to, for example, 120V. Since, current flowing in the FET can be reduced due to the increased supply voltage in the inverter circuit, loss due to on-resistance of the FET can be reduced, and also since current flowing in a primary winding of a transformer can be reduced, copper loss can be reduced. Thus, its efficiency is improved. Here, two supply voltages are involved: one is 120V supplied to the H-bridge for lighting the discharge lamps, and the other is 5V supplied to the inverter control IC. The withstand voltage of the FET of the H-bridge must be increased, and a high gate source voltage is required to drive the FET with a high withstand voltage. For example, if the withstand voltage of the FET of the H-bridge is set at 200V, the gate source voltage of the FET of the H-bridge must be 10V or higher. Consequently, the FET cannot be driven by a voltage of 5V supplied to the inverter control IC if used as it is supplied, and the voltage supplied must be stepped up by a discharge pump, a bootstrap, or a step-up DC-to-DC converter in order to duly drive the FET.  
         [0009]     However, employing a step-up circuit like the aforementioned discharge pump, bootstrap, or step-up DC-to-DC converter complicates the circuit structure and increases the number of components. Also, another problem is that there is difference between frequency of an oscillating circuit to operate the H-bridge circuit and frequency of another oscillating circuit to operate the step-up circuit, which produces interference at a reference voltage of the inverter control IC thus interrupting a stable operation of the circuit.  
       SUMMARY OF THE INVENTION  
       [0010]     The present invention has been made in light of the above problems, and it is an object of the present invention to provide an inverter circuit for lighting discharge lamps, which is simply structured, enables stable operation of a circuit, and which has a further enhanced efficiency thereby reducing power consumption.  
         [0011]     In order to achieve the object, according to one aspect of the present invention, an inverter circuit for lighting discharge lamps comprises: a transformer having a resonant circuit formed by a parasitic capacitance of a discharge lamp; an H-bridge circuit to drive a primary side of the transformer at a frequency which is less than a series resonant frequency of the resonant circuit, and at which phase difference in voltage and current at the primary side of the transformer falls within a predetermined range from its minimum; a logic circuit to generate, based on an output signal of an oscillating circuit, gate signals for driving the H-bridge circuit; and a step-up circuit to step up a DC supply voltage based on another output signal of the oscillating circuit, and to supply the logic circuit with the stepped up DC supply voltage as a supply voltage for generating the gate signals. Thus, the step-up circuit does not require an oscillating circuit dedicated thereto reducing the number of components, whereby the high withstand voltage FET of the H-bridge circuit can be controlled by a simplified circuitry with reduced cost. Consequently, the supply voltage to the H-bridge circuit can be increased therefore enabling current flowing in the FET to be decreased thus reducing loss due to on-resistance of the FET with the simplified circuitry. Also, since the step-up ratio of the transformer can be decreased, current at the primary side of the transformer can be decreased and therefore copper loss can be reduced, whereby efficiency can be improved for reduction in power consumption. Further, since one oscillating circuit is provided for common use, interference generated at reference voltage is prevented thus achieving a stable circuit operation.  
         [0012]     In the aspect of the present invention, the oscillating circuit may be formed by the parasitic capacitance of the discharge lamp and an auxiliary capacitance parallel-connected to the discharge lamp. Consequently, a desired oscillating frequency can be achieved easily according to the auxiliary capacitance.  
         [0013]     In the aspect of the present invention, the step-up circuit may comprise: an error amplifier to output a voltage in accordance with an output voltage of the step-up circuit; and a PWM circuit to output a pulse voltage having a pulse width according to the voltage outputted from the error amplifier based on the output signal from the oscillating circuit. Consequently, a constant and stable voltage can be easily outputted.  
         [0014]     In the aspect of the present invention, the step-up circuit may further comprise a slow-start circuit connected to the PWM circuit. Consequently, a transitional excess voltage is prevented from being generated at an output of the step-up circuit.  
         [0015]     In the aspect of the present invention, the slow-start circuit provided in the step-up circuit may have a shorter rise time than a slow-start circuit to start the H-bridge circuit. Consequently, the logic circuit can rise up stably, and therefore the H-bridge connected to the logic circuit can also rise up stably.  
         [0016]     And, in the aspect of the present invention, the inverter circuit may further comprise a protection circuit to stop an operation of the step-up circuit when detecting an abnormal circumstance at a side of the transformer provided with the discharge lamp.  
         [0017]     Further, since a reference voltage circuit to supply circuits with reference voltages required by the circuits, a stable inverter circuit free from malfunction can be provided. And, in the inverter circuit according to the present invention, the transformer is driven at a frequency lower than a resonant frequency therefore avoiding influence of a high order frequency, which makes it to easier to design a transformer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]      FIG. 1  is a block diagram of an inverter circuit for lighting discharge lamps, according to an embodiment of the present invention;  
         [0019]      FIG. 2  is a graph showing a frequency characteristic of admittance /Y/ of a primary side of a transformer when a resonant circuit is formed at a secondary side thereof in the inverter circuit of  FIG. 1 , and showing another frequency characteristic of phase difference  0  in voltage and current in the inverter circuit of  FIG. 1 ;  
         [0020]      FIG. 3  is a block diagram of a step-up circuit in the inverter circuit of  FIG. 1 ;  
         [0021]      FIG. 4  is a waveform chart of output signals of respective slow-start circuits used in the step-up circuit and a PWM circuit in the inverter circuit of  FIG. 1 ;  
         [0022]      FIGS. 5A  to  5 E are operation timing charts on the inverter circuit of  FIG. 1 ;  
         [0023]      FIGS. 6A  to  6 F are timing charts of gate signals in the inverter circuit of  FIG. 1 ; and  
         [0024]      FIG. 7  is an explanatory chart of an operation of a protection circuit in the inverter circuit of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0025]     A preferred embodiment of the present invention will hereinafter be described with reference to the accompanying drawings.  
         [0026]     A block diagram of an inverter circuit for discharge lamps according to an embodiment of the present invention is shown in  FIG. 1 . For easier understanding, an explanation will be first made on a case where a predetermined voltage Va of a terminal  28   a  is not applied to an inverting input terminal  11   a  of an error amplifier  11  thus light modulation does not occur.  
         [0027]     An output of a chopping wave  7  of an oscillating circuit  4  is inputted to a PWM circuit  8 . A discharge lamp  9  for backlighting a liquid crystal display (LCD) is disposed in an LCD unit  2  provided at a secondary side of a transformer  1  (in practice, a plurality of discharge lamps and transformers are used, but only one each thereof is illustrated for the purpose of explanation), and its voltage  9   a  is inputted to the aforementioned inverting input terminal  11   a  of the error amplifier  11  by means of a current-to-voltage converter circuit  10  which converts current flowing in the discharge lamp  9  into voltage. A series oscillating circuit is formed by parasitic capacitance  3  at the discharge lamp  9 , capacitors  31  and  32  connected to the discharge lamp  9  in parallel, and leakage inductance of the transformer  1 . The capacitors  31  and  32  function as auxiliary capacitance for the parasitic capacitance  3 .  
         [0028]     The error amplifier  11  outputs to the PWM circuit  8  an output voltage  12  according to the current of the discharge lamp  9 , and the PWM circuit  8  compares the chopping wave  7  and the output voltage  12  of the error amplifier  11  and inputs a pulse signal  13  to a counter circuit  14 .  
         [0029]     A slow-start circuit  34  outputs to the PWM circuit  8  an output signal of a start driving signal  56  for comparatively gentle rise-up, thereby preventing generation of an instantaneous overvoltage at the time of start.  
         [0030]     The chopping wave  7  which is an output signal of the oscillating circuit  4  is determined by values of a resistor  5  and a capacitor  6 , and an output pulse signal  16  of the oscillating circuit  4 , which is synchronized with the chopping wave  7 , is inputted to counter circuits  14  and  15 , and a logic circuit  29 . According to the output pulse signal  16  of the oscillating circuit  4  and output pulse signals of the counter circuits  14  and  15 , the logic circuit  29  powered by a supply voltage  76  of 10V supplied from a step-up circuit  100  generates gate signals  18 ,  19 ,  20  and  21  with a pulse amplitude of 10V, which are to be inputted to an H-bridge circuit  17 .  
         [0031]     The H-bridge circuit  17  is structured such that a series circuit consisting of PMOS (A 1 ) and NMOS (B 2 ) and a series circuit consisting of PMOS (A 2 ) and NMOS (B 1 ) are connected to each other in parallel, and operates according to the gate signals  18 ,  19 ,  20  and  21 . A DC supply voltage Vb of 120V for lighting the discharge lamp  9  is converted by the gate signals  18 ,  19 ,  20  and  21  with a pulse amplitude of 10V in the H-bridge circuit  17 , and lights the discharge lamp  9  through the transformer  1 .  
         [0032]     Accordingly, when a burst circuit  22  does not operate thereby not allowing the predetermined voltage Va from the terminal  28   a  be applied to the inverting input terminal  11   a  of the error amplifier  11 , light is not modulated, and the current of the discharge lamp  9  is inputted to the inverting input terminal  11   a , thus the discharge lamp  9  is feedback-controlled and lighted.  
         [0033]     Referring to  FIG. 2 , an AC current within a frequency indicated by A flows at the primary side of the transformer  1 , and a constant current control is accomplished within a high power efficiency range to light the discharge lamp  9  shown in  FIG. 1 .  
         [0034]     A discussion will now be made on an operation of the step-up circuit  100 .  
         [0035]     The step-up circuit  100  steps up a DC supply voltage Vcc of 5V, and supplies the stepped up DC voltage to the logic circuit  29  as the aforementioned supply voltage  76 . The chopping wave  7 , which is the output signal from the oscillating circuit  4 , and which is used for controlling the H-bridge circuit  17 , is inputted also to the step-up circuit  100 .  
         [0036]     Referring to  FIG. 3 , the aforementioned DC supply voltage Vcc of 5V is applied to the step-up circuit  100 , is stepped up by a step-up type chopper circuit formed by a transistor  73  to operate on the chopping wave  7 , an inductor  74 , and a diode  77 , then is smoothed by a capacitor  78  into a DC voltage of 10V, and is outputted from the step-up circuit  100  as the DC supply voltage  76  for the logic circuit  29 .  
         [0037]     In the step-up circuit  100 , PWM control is performed by using an error amplifier  71  and a PWM circuit  72 , and a constant voltage output is achieved. An output voltage of the step-up circuit  100  is detected by resistors  81  and  82 , and is compared with a reference voltage Ve by the error amplifier  71  which then outputs a voltage according to the output voltage of the step-up circuit  100 . In the PWM circuit  72 , the output of the error amplifier  71  is compared with the chopping wave  7  outputted from the oscillating circuit  4 , and a pulse signal whose pulse width is feedback-controlled is outputted from the PWM circuit  72 . This pulse signal makes the transistor  73  undergo switching, thereby outputting the DC supply voltage  76  of a constant voltage. Thus, the logic circuit  29  is provided with the supply voltage  76  and thereby enabled to output the gate signals  18 ,  19 ,  20  and  21  of a high voltage capable of driving an FET of high withstand voltage used in the H-bridge circuit  17 .  
         [0038]     Since the chopping wave  7  outputted from the oscillating circuit  4  is used in common for controlling the H-bridges circuit  17  and the step-up circuit  100 , and shared by the both circuits, the step-up circuit  100  does not need to have an independent oscillating circuit dedicated thereto thus simplifying the circuitry of the step-up circuit  100 . Also, since the H-bridge circuit  17  and the step-up circuit  100  share the use of the chopping wave  7  outputted from the oscillating circuit  4 , the operating frequencies of the both circuits coincide with each other, whereby interference which occurs at a reference voltage when operating frequencies differ from each other can be avoided thus eliminating an instable circuit operation and ensuring a stable circuit operation.  
         [0039]     A slow-start circuit  75  outputs to the PWM circuit  72  a signal to command comparatively gentle rise-up at the start of operation of the step-up circuit  100  so that the pulse signal outputted from the PWM circuit  72  is kept from having a too large width to thereby prevent generation of transitional excess voltage at the output of the step-up circuit  100 .  
         [0040]     Referring to  FIG. 4  showing a waveform chart of output signals of slow-start circuits  75  and  34  used in the step-up circuit  100  and the PWM circuit  8 , respectively, in the inverter circuit of  FIG. 1 , a rise time T1 of the slow-start circuit  75  used in the step-up circuit  100  is set to be shorter than a rise time T2 of the slow-start circuit  34  used in the PWM circuit  8  so that the logic circuit  29  is allowed to rise up by the slow-start circuit  34  only after the supply voltage  76  is stabilized, whereby the logic circuit  29  can rise up stably, and therefore the H-bridge circuit  17  connected to the logic circuit  29  can also rise up stably.  
         [0041]     An operation of the burst circuit  22  performing light control of the discharge lamp  9  will be described with reference to  FIGS. 1 and 5 A to  5 E. Referring to  FIG. 1 , the burst circuit  22  can be set up in either of two modes: one mode is such that a resistor  23  has its resistance set at a predetermined value or more whereby a predetermined pulse signal  24  inputted to a DUTY terminal  24   a  is outputted from the burst circuit  22  as a first burst signal  25   b  (refer to  FIG. 5D ); and the other mode is such that the resistor  23  has its resistance set at less than a predetermined value whereby a chopping wave voltage  27  (refer to  FIG. 5B ) determined by the resistor  23  and a capacitor  26  is compared with a DC voltage  36  (refer to  5 B) inputted to the DUTY terminal  24   a  thereby outputting a second burst signal (pulse wave)  25   a  (refer to  FIG. 5C ).  
         [0042]     When the first burst signal  25   b  from the burst circuit  22  is “H”, a transistor  28  is turned on causing the error amplifier  11  to output to the PWM circuit  8  an output voltage  12  in accordance with current in the discharge lamp  9 , whereby an output (refer to  5 E) of the H-bridge circuit  17  is formed based on the chopping wave  7  shown in  FIG. 5A , which puts the discharge lamp  9  into operation. When the first burst signal  25   b  from the burst circuit  22  is “L”, the transistor  28  is turned off causing the inverting input terminal  11   a  of the error amplifier  11  to be pulled up to the predetermined voltage Va supplied to the terminal  28   a , whereby the error amplifier  11  is put in non-operation causing the H-bridge circuit  17  to stop its operation, which puts the discharge lamp  9  in non-operation. Thus, the discharge lamp  9  is caused to operate intermittently by the first burst signal  25   b , and light control is performed. In this connection, when the second burst signal  25   a  is used, the discharge lamp  9  has it light controlled in the same manner, which allows selective usage of the first and second burst signals  25   b  and  25   a.    
         [0043]     The gate signals  18  (refer to  FIG. 6B ) and  19  (refer to  FIG. 6C ), which are both formed at the logic circuit  29  by the supply voltage  76  from the step-up circuit  100 , and which have a pulse amplitude of 10V, alternately rise up respectively at each upper peak  18   u  and  19   u  (refer to FIG.  6 A) of the chopping wave  7  by means of counter circuits  14  and  15 , and the logic circuit  29 , and alternately fall down respectively at each cross point  18   d  and  19   d  (refer to  FIG. 6A ) of the chopping wave  7  and the output signal  12  of the error amplifier  11 . Gates of the PMOS (A 1 ) and the PMOS (A 2 ) rise up and fall down respectively by the gate signals  18  and  19  having a pulse amplitude of 10V.  
         [0044]     Also, the gate signals  20  (refer to  FIG. 6D ) and  21  (refer to  FIG. 6E ), which are both formed at the logic circuit  29  by the supply voltage  76  from the step-up circuit  100 , and have a pulse amplitude of 10V, alternately rise up respectively at each lower peak  20   u  and  21   u  (refer to  FIG. 6A ) of the chopping wave  7  by means of the counter circuits  14  and  15 , and the logic circuit  29 , and alternately fall down respectively at cross each point  20   d  and  21   d  (refer to  FIG. 6A ) of the chopping wave  7  and the output signals  12  of the error amplifier  11 . Gates of the NMOS (B 1 ) and the NMOS (B 2 ) rise up and fall down respectively by the gate signals  20  and  21  having a pulse amplitude of 10V.  
         [0045]     Referring to  FIGS. 6B  to  6 E, the gate signals  21  and  20  rise up behind the gate signals  18  and  19 , respectively, and referring to  FIG. 6F , the gate signals  18  and  19  fall down behind the gate signals  21  and  20 , respectively, by a time t1 predetermined by a delaying circuit  35 . Consequently, the PMOS (A 1 ) PMOS (A 2 ) and the NMOS (B 1 )/NMOS (B 2 ) do not turn on concurrently. Thus, the gate signals  18 ,  19 ,  20  and  21  which do not allow the PMOS (A 1 )/PMOS (A 2 ) and the NMOS (B 1 ) NMOS (B 2 ) to turn on concurrently can be easily formed by the chopping wave  7  and the output voltage  12 .  
         [0046]     An error amplifier  51  for voltage feedback compares an applied voltage signal  55  of the discharge lamp  9  inputted to an inverting input terminal  51   a  with a preset value Vc, and outputs to a protection circuit  50  and the PWM circuit  8  an output voltage  52  in accordance with the voltage applied to the discharge lamp  9 . The protection circuit  50  incorporates a comparator circuit (not shown), to which the output voltage  52  from the error amplifier  51  for voltage feedback, and a transformer output current signal  53  from a resistor  57  provided in series with the secondary side of the transformer  1  are inputted. The applied voltage signal  55  is formed such that a voltage at a connection of the capacitors  31  and  32  disposed at the output side of the transformer  1  is divided by resistors  58  and  59 .  
         [0047]     The error amplifier  51  for voltage feedback, when the applied voltage signal  55  is inputted to its inverting input terminal  51   a , compares the applied voltage signal  55  with the preset value Vc, and outputs the output voltage  52  to the PWM circuit  8 , and the voltage applied to the discharge lamp  9  is feedback-controlled. Accordingly, for example, when the discharge lamp  9  is not connected or poorly connected, an open voltage can be defined as a preset value. Also, when the discharge lamp  9  is not connected or poorly connected, it can happen that the output voltage at the secondary side of the transformer  1  shows an abnormal value. In such a case, the output voltage  52  of the error amplifier  51  for voltage feedback inputted to the protection circuit  50 , and the transformer output current signal  53  are compared with the reference voltage of the comparator circuit (not shown) of the protection circuit  50 , and if the output voltage  52  of the error amplifier  51  or the transformer output current signal  53  exceeds the reference voltage, then the logic circuit  29  is caused to stop its operation, whereby an excess current to the discharge lamp  9 , and an excess voltage to the transformer  1  can be prevented. Further, the protection circuit  50 , when the output voltage  12  of the error amplifier  11  is inputted, functions to prevent an excess current to the discharge lamp  9  and an excess voltage to the transformer  1 . Thus, when an abnormal circumstance is detected at a side of the transformer  1  having the discharge lamp  9 , the protection circuit  50  stops the operation of the logic circuit  29  thereby preventing damages to the transformer  1  and relevant circuits. In this connection, the protection circuit  50  is adapted to stop the operation of the logic circuit  29  only when a voltage exceeds a value predetermined by a built-in timer, whereby it is prevented from happening that the operation of the logic circuit  29  is falsely stopped when an excess voltage is instantaneously applied for some reasons.  
         [0048]     Referring to  FIG. 7 , the supply voltage Vcc is supplied to the step-up circuit  100 , the oscillating circuit  4 , the PWM circuit  8 , the error amplifiers  11  and  51 , the protection circuit  50 , and the reference voltage circuit  90 . The supply voltage Vcc supplied to the reference voltage circuit  90  is converted into lower reference voltages Vc and Ve, and the reference voltage Vc is inputted to the error amplifiers  11  and  51 , and the protection circuit  50  while the reference voltage Ve is inputted to the step-up circuit  100 .  
         [0049]     When the protection circuit  50  detects something abnormal at the side of the transformer  1  having the discharge lamp  9  connected, the logic circuit  29  is caused to stop its operation thereby preventing damages to the transformer  1  and relevant circuits. Especially, the H-bridge circuit  17 , to which the supply voltage Vb of 120V for lighting the discharge lamp  9  is supplied, must be caused to infallibly stop its operation. In this regard, the protection circuit  50 , when detecting something abnormal at the side of the transformer  1  provided with the discharge lamp  9 , stops the operation of the reference voltage circuit  90  thereby reducing to a zero voltage the reference voltage Ve inputted to the step-up circuit  100 , which stops an output of the supply voltage  76  supplied from the step-up circuit  100  to the logic circuit  29  resulting in surely stopping the operation of the logic circuit  29 . Consequently, the operation of the H-bridge circuit  17  can be reliably stopped without fail.  
         [0050]     In the inverter circuit according to the present invention, the circuits excluding the H-bridge circuit  17 , the transformer  1 , and the discharge lamp  9  may be constituted by inverter control IC&#39;s.  
         [0051]     While the present invention has been illustrated and explained with respect to specific embodiments thereof, it is to be understood that the present invention is by no means limited thereto but encompasses all changes and modifications that will become possible within the scope of the appended claims.

Technology Classification (CPC): 7