Patent Abstract:
A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.

Full Description:
TECHNICAL FIELD 
   The present invention provides a low space consuming linear time-driver circuit that is based upon the small capacitor charge of the merged region of a 5V tolerant cascoded NMOS device, a single gate device and a zener diode. 

   
     DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  is a circuit schematic illustrating a time-driver circuit in accordance with the concepts of the present invention that utilizes a cascoded NMOS design. 
       FIG. 1B  is a partial cross-section drawing of an emodiment of the  FIG. 1A  circuit taken along the cascoded NMOS device structure of  FIG. 1A . 
       FIGS. 1C and 1D  are graphs illustrating merged region node voltage over time for various capacitor values for the FIG.  1 A/ 1 B circuit. 
       FIGS. 2A and 2B  are graphs illustrating the calculated transient characteristic for merged region node voltage as a function of the capacitor, the gate resistive divider ratio and the V DD  level for the  FIG. 1A  circuit. 
       FIG. 3A  is a circuit schematic illustrating a time-driver circuit in accordance with the concepts of the present invention that utilizes a non-cascoded NMOS design. 
       FIG. 3B  is a partial cross section drawing of an embodiment of an NMOS device in the  FIG. 3  circuit. 
       FIG. 4  is a graph illustrating the calculated transient characteristic for the merged region node voltage as a function of the capacitor, the gate resistive divider ratio and the V DD  level for the  FIG. 3A  circuit. 
   

   DESCRIPTION OF THE INVENTION 
   Time-driver circuits are one of the important elements for the active clamps used in electrostatic discharge (ESD) protection circuits. Because simple, but space-consuming RC-timers are typically used in these ESD application, the drivers are typically implemented as corner cells in the overall circuit layout. As a result, the timer time domain is limited by 6–8 usec. 
     FIG. 1A  shows a time-driver circuit  100  in accordance with the concepts of the present invention that utilizes a cascoded NMOS design.  FIG. 1B  shows a cross-section of an embodiment of the  FIG. 1A  time-driver circuit taken along the cascoded NMOS structure of the  FIG. 1A  circuit  100 . 
   The  FIG. 1  circuit  100  includes cascoded NMOS devices  102  and  104  connected between a positive voltage supply V DD  and a negative voltage supply V SS . The gate of the lower NMOS device  104  is connected to the negative voltage supply V SS  by a resistor R G . The gate of the upper NMOS transistor  102  is connected to the common node of a resistive divider  108  that includes resistor R D1  and resistor RD 2 . The merged (common) node  110  of the cascoded NMOS devices  102  and  104  provides a capacitive charge C T  that is disposed between the cascoded structure common node  110  and the positive voltage supply V DD . 
   Evaluation of the circuit  100  shown in  FIG. 1B  has demonstrated that a linear voltage dependence is produced in a wide range of parameters under extremely small component values. The cascoded NMOS device utilized for the  FIG. 1B  test circuit was taken at w=10 microns. The millisecond range is achieved for a capacitor value C T  of about 100 fF only. 
   The output node voltage V(t) of the circuit is supposed to be loaded on the circuit starting with the low equivalent capacitance input realized by minimum dimension devices. 
   The operational principle of the circuit is as follows. Under initial conditions, V DD =0, the capacitor C T  is discharged and the potential of the cascoded structure common node  110  is equal to V DD =0. The gate potential of the lower NMOS device  104  is also zero. The gate potential of the upper NMOS device  104  is defined by the ratio R D1 /R D2  of the resistive divider  108 . After the positive supply V DD  is applied and a fast current through the parasitic capacitance C T  of the device, the potential of the merged cascoded structure common node  110  starts to change due to the charge of the capacitor C T . The gate potential of the lower NMOS device  104  remains zero. The gate potential of the upper NMOS device  102  is defined by the ration R D1 /R D2  of the resistive divider  108  and is lower than the potential of the cascoded structure common node  110 . Thus, both NMOS devices  1 – 2  and  104  are in the off state. The capacitor C T  continues to charge by the leakage current through the upper NMOS device  102  until equilibrium is defined by the gate potentials. 
     FIGS. 1C and 1D  are graphs showing voltages of the merged cascoded structure common node  110  over time for various capacitor values C T  for the FIG.  1 A/ 1 B circuit. 
     FIGS. 2A and 2B  are graphs that illustrate the calculated transient characteristics for the merged region node voltage as a function of the capacitor C T , the gate resistive divider ratio R D1 /RD 2  and the V DD  level for the FIG.  1 A/ 1 B circuit. 
   Those skilled in the art will appreciate that similar principles can be realized for a 3.3V or lower tolerant voltage based on a non-cascoded NMOS design, as shown in  FIG. 3A .  FIG. 3B  shows a cross-section of an embodiment of an NMOS device  202  in the  FIG. 3A  circuit  200 . 
   The  FIG. 3A  circuit  200  includes an NMOS device  202  that is connected between a positive supply V DD  and a negative supply V SS . The gate of the NMOS device  202  is connected to the common node  204  of a resistive divider  206  that includes a resistor R D3  that is connected between the positive supply C DD  and the resistive divider common node  204  and a resistor R D4  that connected between the resistive divider common node  204  and the negative supply V SS . As in the case of the cascoded NMOS design discussed above in conjunction with FIGS.  1 A/ 1 B, a capacitor C T  is connected between the output V(t) of the NMOS device  202  and the positive supply V DD . 
     FIG. 4  is a graph that shows the calculated transient characteristic for the merged region node voltage as a function of the capacitor C T , the resistive divider ratio R D3 /R D4  and the V DD  level for the  FIG. 3A  non-cascoded circuit  200 . 
   It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and structures and methods within the scope of these claims and their equivalence be covered thereby.

Technology Classification (CPC): 7