Patent Abstract:
A servo controller for a disk drive controller comprising a storage device that stores communication information for a plurality of devices and a serial port controller located on the servo controller that communicates with the storage device, that receives a request to communicate with one of the plurality of devices, and that allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 10/385,039, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,039,771). This application also relates to the subject matter of U.S. patent application Ser. No. 10/384,992, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,492,545); U.S. patent application Ser. No. 10/385,022, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,080,188); U.S. patent application Ser. No. 10/384,991, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,457,903); U.S. patent application Ser. No. 10/385,042, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,099,963); U.S. patent application Ser. No. 10/385,405, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,064,915); and U.S. patent application Ser. No. 10/385,056, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,219,182). The disclosures of the above applications are incorporated herein by reference. 
    
    
     FIELD 
     The present invention relates generally to storage systems, and more particularly to disk drive servo controllers. 
     BACKGROUND 
     The statements in this section merely provide background information related to the present disclosure and may not constitute prior art. 
     Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and disk drives. In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system. 
     The main memory is typically smaller than disk drives and may be volatile. Programming data is often stored on the disk drive and read into main memory as needed. The disk drives are coupled to the host system via a disk controller that handles complex details of interfacing the disk drives to the host system. Communications between the host system and the disk controller is usually provided using one of a variety of standard I/O bus interfaces. 
     Typically, a disk drive includes one or more magnetic disks. Each disk (or platter) typically has a number of concentric rings or tracks (platter) on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding with a read or write operation. Data is accessed serially, one bit at a time and typically, each disk has its own read/write head. 
       FIG. 1  shows a disk drive system  100  with platters  101 A and  101 B, an actuator  102  and read/write head  103 . Typically, multiple platters/read and write heads are used. Platters  101 A- 101 B have assigned tracks for storing system information, servo data and user data. 
     The disk drive is connected to the disk controller that performs numerous functions, for example, converting digital data to analog head signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering. To perform the various functions for transferring data, the disk controller includes numerous components. 
     To access data from a disk drive (or to write data), the host system must know where to read (or write data to) the data from the disk drive. A driver typically performs this task. Once the disk drive address is known, the address is translated to cylinder, head and sector based on platter geometry and sent to the disk controller. Logic on the hard disk looks at the number of cylinders requested. Servo controller firmware instructs motor control hardware to move read/write heads  103  to the appropriate track. When the head is in the correct position, it reads the data from the correct track. 
     Typically, read and write head  103  has a write core for writing data in a data region, and a read core for magnetically detecting the data written in the data region of a track and a servo pattern recorded on a servo region. 
     A servo system  104  detects the position of head  103  on platter  101 A according to a phase of a servo pattern detected by the read core of head  103 . Servo system  104  then moves head  103  to the target position. 
     Servo system  104  servo-controls head  103  while receiving feedback for a detected position obtained from a servo pattern so that any positional error between the detected position and the target position is negated. 
     Typically, a servo controller in system  104  communicates with various serial port programmable devices coupled via a serial port interface. The serial port interface enables transmission of commands and configuration data. One such device is shown in  FIG. 3 , as the “read channel device  303 ”. An example of such a product is “88C7500 Integrated Read channel” device sold by Marvell Semiconductor Inc®. 
     There is no standard for these various serial port devices to communicate with the servo controller. For example, length of address and length of data fields may vary from one device to the next. Hence, a single serial port connection is not typically used for plural devices having different protocols. Conventional techniques require a separate controller for each device. This is commercially undesirable because it adds costs and extra logic on a chip. 
     Therefore, what is desired is an efficient system that allows an embedded disk controller to communicate with plural devices through a single serial port controller interface. 
     SUMMARY 
     A servo controller for a disk drive controller comprises a storage device that stores communication information for a plurality of devices. A serial port controller located on the servo controller communicates with the storage device, receives a request to communicate with one of the plurality of devices, and allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol. 
     In other features of the invention, the storage device includes at least one register. Logic that enables the plurality of devices to receive at least one of a write request and a read request. The serial port controller arbitrates between a plurality of the requests to communicate. The serial port controller communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device. The communication information includes at least one of address information, write data information, and read data information. The serial port controller outputs an enabling signal to the one of the plurality of devices according to the communication information and the request. A routing device communicates with the serial port controller, the storage device, and the plurality of devices and allows data to flow at least one of to and from the plurality of devices. At least one of the serial port controller and the storage device are located on one of an integrated circuit (IC) and a system on a chip (SOC) with the servo controller. 
     A method for communicating with serial port devices with a servo controller for a disk drive controller comprises storing communication information for a plurality of devices in a storage device, communicating with the storage device at serial port controller located on the servo controller, receiving a request to communicate with one of the plurality of devices at the serial port controller, and allowing communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol. 
     In other features of the invention, the storage device includes at least one register. The method further comprises enabling the plurality of devices to receive at least one of a write request and a read request. The serial port controller arbitrates between a plurality of the requests to communicate. The serial port controller communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device. The communication information includes at least one of address information, write data information, and read data information. The serial port controller outputs an enabling signal to the one of the plurality of devices according to the communication information and the request. The method further comprises communicating with the serial port controller, the storage device, and the plurality of devices with a routing device, and allowing data to flow at least one of to and from the plurality of devices with the routing device. 
     A servo controller for a disk drive controller comprises storage means for storing communication information for a plurality of devices and serial port control means located on the servo controller for communicating with the storage means, for receiving a request to communicate with one of the plurality of devices, and for allowing communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol. 
     In other features of the invention, the storage means includes at least one register. The servo controller further comprises logic means for enabling the plurality of devices to receive at least one of a write request and a read request. The serial port controller arbitrates between a plurality of the requests to communicate. The serial port control means communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device. The communication information includes at least one of address information, write data information, and read data information. The serial port control means outputs an enabling signal to the one of the plurality of devices according to the communication information and the request. The servo controller further comprises routing means for communicating with the serial port control means, the storage means, and the plurality of devices and for allowing data to flow at least one of to and from the plurality of devices. At least one of the serial port control means and the storage means are located on one of an integrated circuit (IC) and a system on a chip (SOC) with the servo controller. 
     In still other features, the systems and methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage and/or other suitable tangible storage mediums. 
     Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the disclosure, are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing features and other features of the present invention will now be described. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
         FIG. 1  shows a block diagram of a disk drive; 
         FIG. 2  is a block diagram of an embedded disk controller system, according to one aspect of the present invention; 
         FIG. 3  is a block diagram showing the various components of the  FIG. 3  system and a two-platter, four-head disk drive, according to one aspect of the present invention; 
         FIG. 4  is a block diagram of a servo controller, according to one aspect of the present invention; 
         FIG. 5  is a schematic of a serial port controller, according to one aspect of the present invention; 
         FIGS. 6A and 6B  provides examples of timing diagrams as used by the serial port controller of  FIG. 5  during a write and read phase, respectively, according to one aspect of the present invention; and 
         FIG. 7  is a flow diagram of executable steps for a state machine used by the serial port controller, according to one aspect of the present invention. 
     
    
    
     DRAWINGS 
     The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. 
     DETAILED DESCRIPTION 
     The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure. 
     To facilitate an understanding of the preferred embodiment, the general architecture and operation of an embedded disk controller will be described initially. The specific architecture and operation of the preferred embodiment will then be described. 
       FIG. 2  shows a block diagram of an embedded disk controller system  200  according to one aspect of the present invention. System  200  may be an application specific integrated circuit (“ASIC”). 
     System  200  includes a microprocessor (“MP)  201  that performs various functions described below. MP  201  may be a Pentium® Class processor designed and developed by Intel Corporation® or an ARM processor. MP  201  is operationally coupled to various system  200  components via buses  222  and  223 . Bus  222  may be an Advance High performance (AHB) bus as specified by ARM Inc. Bus  223  may an Advance Peripheral Bus (“APB”) as specified by ARM Inc. The specifications for AHB and APB are incorporated herein by reference in their entirety. 
     System  200  is also provided with a random access memory (RAM) or static RAM (SRAM)  202  that stores programs and instructions, which allows MP  201  to execute computer instructions. MP  201  may execute code instructions (also referred to as “firmware”) out of RAM  202 . 
     System  200  is also provided with read only memory (ROM)  203  that stores invariant instructions, including basic input/output instructions. 
     System  200  is also provided with a digital signal processor (“DSP”)  206  that controls and monitors various servo functions through DSP interface module (“DSPIM”)  208  and servo controller interface  210  operationally coupled to a servo controller (“SC”)  211 . 
     DSPIM  208  interfaces DSP  206  with MP  201  and allows DSP  206  to update a tightly coupled memory module (TCM)  205  (also referred to as “memory module”  205 ) with servo related information. MP  201  can access TCM  205  via DSPIM  208 . 
     Servo controller interface (“SCI”)  210  includes an APB interface  213  that allows SCI  210  to interface with APB bus  223  and allows SC  211  to interface with MP  201  and DSP  206 . 
     SCI  210  also includes DSPAHB interface  214  that allows access to DSPAHB bus  209 . SCI  210  is provided with a digital to analog and analog to digital converter  212  that converts data from analog to digital domain and vice-versa. Analog data  220  enters module  212  and leaves as analog data  220 A to a servo device  221 . 
     SC  211  has a read channel device (RDC) serial port  217 , a motor control (“SVC”) serial port  218  for a “combo” motor controller device, a head integrated circuit (HDIC) serial port  219  and a servo data (“SVD”) interface  216  for communicating with various devices. 
       FIG. 3  shows a block diagram with disk  100  coupled to system  200 , according to one aspect of the present invention.  FIG. 3  shows a read channel device  303  that receives signals from a pre-amplifier  302  (also known as head integrated circuit (HDIC)) coupled to disk  100 . One example of a read channel device  303  is manufactured by Marvell Semiconductor Inc.®, Part Number 88C7500, while pre-amplifier  302  may be a Texas instrument, Part Number SR1790. Pre-amplifier  302  is also operationally coupled to SC  211 . Servo data (“SVD”)  305  is sent to SC  211 . 
     A motor controller  307  (also referred to as device  307 ), (for example, a motor controller manufactured by Texas Instrument®, Part Number SH6764) sends control signals  308  to control actuator movement using motor  307 A. It is noteworthy that spindle  101 C is controlled by a spindle motor (not shown) for rotating platters  101 A and  101 B. SC  211  sends plural signals to motor controller  307  including clock, data and “enable” signals to motor controller  307  (for example, SV_SEN, SV_SCLK and SV_SDAT). 
     SC  211  is also operationally coupled to a piezo controller  509  that allows communication with a piezo device (not shown). One such piezo controller is sold by Rolm Electronics®, Part Number BD6801 FV. SC  211  sends clock, data and enable signals to controller  509  (for example, SV_SEN, SV_SCLK and SV_SDAT). 
       FIG. 4  shows a block diagram of SC  211 , according to one aspect of the present invention. 
       FIG. 4  shows SC  211  with a serial port controller  404  for controlling various serial ports  405 - 407 . 
     SC  211  also has a servo-timing controller (“STC”)  401  that automatically adjusts the time base when a head change occurs. Servo controller  211  includes an interrupt controller  411  that can generate an interrupt to DSP  206  and MP  201 . Interrupts may be generated when a servo field is found (or not found) and for other reasons. SC  211  includes a servo monitoring port  412  that monitors various signals to SC  211 . 
     SC  211  uses a pulse width modulation unit (“PWM”)  413  for supporting control of motor  307 A PWM, and a spindle motor PWM  409  and a piezo PWM  408 . 
     MP  201  and/or DSP  206  use read channel device  303  for transferring configuration data and operational commands through SC  211  (via read channel serial port interface  406 ). 
       FIG. 5  shows a block diagram of serial port controller  404 , according to one aspect of the present invention. The example only shows how serial port controller  404  allows communication between system  200  and motor controller  307  and piezo controller  509 . It is noteworthy that the invention is not limited to just these two or any particular number of devices. 
     Controller  404  includes a state machine  404 A that has access to piezo controller  509  and device  307  information in registers  501  and  503  (that includes controller  509  and  307  protocol information), for MP  201  (referred to as Client  1  in  FIG. 5  for illustration purposes only). State machine  404 A can also access controller  509  and device  307  information in registers  502  and  504  for DSP  206  (referred to as Client  2  in  FIG. 5  for illustration purposes only). Typically information in registers  501 - 504  includes address fields for each device ( 509  or  307  in this example), length of the data fields and timing control information (for example, if data from a certain device is captured on the rising or falling edge of a clock signal,) and setup and hold time data for the active edge of a clock signal. 
     Controller  404  also includes various registers, for example, registers  515 - 517  for storing address, write data and read data for controller requested by client  1 , and registers  518 - 520  for storing address, write data and read data for a device requested by client  2 . Information from register  515 - 520  is sent to a router  521  that allows MP  201  or DSP  206  to communicate with controller  509  or device  307 . 
     Request to Write: The following example shows how MP  201  (or any other component) can write data to a device (in this example, controller  509  or device  307 ). MP  201  sends a request  506  that is received by state machine  404 A. MP  201  then adds the address and data in register  515  and  516 . Based on the information in registers  501 - 504 , state machine  404 A determines the identity of the device to which MP  201  wants to write. State machine  404 A then sets up the device by generating signal  508  or  513  that enables controller  509  or device  307 , respectively. Thereafter, data is written to controller  509  or device  307 . 
       FIG. 6A  provides a timing diagram showing the relationship between signals  513 ,  512  and  511  to write data to device  307 . Signal  512  is a serial clock that is used for synchronizing data transfer between a client and the device. 
     Request to Read: The following example shows how DSP  206  (or any other component) can read data from a device (in this example, controller  509  or device  307 ). A request  507  is received by state machine  404 A from DSP  201 . DSP  201  also provides an address to register  518 . Based on the information in registers  501  and  502 , state machine  404 A determines the identity of the device to read data. State machine  404 A then sets up signal  508  or  513  to read data from controller  509  or device  307 . 
       FIG. 6B  provides a timing diagram showing the relationship between signals  508 ,  512  and  511  to read data from controller  509 . 
       FIG. 7  is a flow diagram showing executable process steps used by state machine  404 A, according to one aspect of the present invention. 
     In step S 700 , state machine  404 A is in an idle state. When it receives requests from various clients (MP  201  and DSP  206 ), state machine  404 A enters an arbitration mode in step S 701 . One of the clients wins arbitration and is then allowed to communicate to an external device,  509  or device  307 . 
     In step S 702 , state machine  404 A reads programmed information about a device (for example, controller  509  or device  307 ) from registers  501 - 504 . 
     In step S 703 , state machine  404 A transmits the appropriate device address to the client who won arbitration in step S 701 . 
     In step S 704 , state machine  404 A, transmits data via router  521 , to controller  509  or device  307 , for a write mode. Thereafter, the process returns to step S 700 . 
     In step S 705 , state machine  404 A, collects data via router  521 , from controller  509  or device  307 , for a read mode and the data is sent to register  520  for later recovery by the requesting client. Thereafter, the process returns to step S 700 . 
     In one aspect of the present invention, the servo controller with a single state machine can communicate with multiple serial port devices, and each device may have a different protocol. 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

Technology Classification (CPC): 6