Patent Abstract:
A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.

Full Description:
FIELD OF THE INVENTION 
     The present invention relates to a high speed switch that includes data converter physical ports that boost performance by providing flexibility, programmability, security and reliability. 
     RELATED ART 
     High speed switches and routers typically include a plurality of physical ports, each of which includes a corresponding digital transceiver. Each digital transceiver is capable of receiving a stream of serial digital input data from an external device. Upon receiving serial digital input data, the digital transceiver converts the serial digital input data into parallel digital data using a serializer-deserializer (SERDES) circuit. This parallel digital data is provided to a control circuit, which controls the routing of the parallel digital data in accordance with a particular protocol. In general, the control circuit causes the parallel digital data to be routed through a switch fabric to another physical port of the switch. The digital transceiver associated with this physical port converts the parallel digital data into a stream of serial digital output data, which is provided to an external device. 
     As described above, conventional high-speed switches typically operate exclusively in response to digital input and output signals. It would be desirable to have a high-speed switch that has the flexibility to operate in response to analog signals as well as digital signals. 
     SUMMARY 
     Accordingly, the present invention provides an improved communication system that implements a high-speed switch that includes both high-speed serial physical ports and high-speed data converter physical ports that operate in conjunction with intelligent protocols. As defined herein, intelligent protocols have features to manage signal latency, control and routing through the switch. 
     A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric to the serial physical ports or other data converter physical ports, in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric (and originating from the serial physical ports or other data converter physical ports) may be converted to an analog output signal on the switch, in accordance with a serial protocol. The converted analog output signal may then be transmitted to an external destination. 
     The high-speed switch can be used to implement a base station radio card. In this embodiment, a serial physical port of the high-speed switch receives digital baseband and control signals from a baseband card. The high-speed switch routes the received digital baseband and control signals to a signal processing block (through another serial physical port of the high-speed switch). In response, the signal processing block provides a digital baseband output signal, which is routed through the high-speed switch to a data converter physical port that performs digital-to-analog conversions. This data converter physical port converts the received digital baseband output signal to an analog output signal, which can be transmitted externally using a wired or wireless system. In an alternate embodiment, the high-speed switch can route the digital baseband signal provided by the baseband card directly to the data converter physical port that performs the digital-to-analog conversion (bypassing the signal processing block). 
     An external receiver circuit can be configured to receive an analog input signal, which is transmitted externally on a wired or wireless system. The external receiver circuit provides the analog input signal to a data converter physical port of the switch that performs analog-to-digital conversions. This data converter physical port converts the received analog input signal to a digital input signal, which is routed through the high-speed switch to the signal processing block (via a serial physical port of the switch). The signal processing block processes the digital input signal, and then forwards this processed digital input signal to the baseband card (through the high-speed switch). Alternately, the digital input signal can be routed through the high-speed switch directly to the baseband card. 
     In another embodiment, the digital input signal can be routed from the data converter physical port to a serial physical port of the switch. The serial physical port converts the digital input signal into a serial data output signal, which is transmitted to an external device coupled to the serial physical port. 
     The invention will be better understood by reference to the following detailed description in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a multi-port switch in accordance with one embodiment of the present invention. 
         FIG. 2  is a block diagram of a communication system that uses the switch of  FIG. 1  in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a high-speed switch  100 , which includes high-speed serial physical ports P 1 -P N . Switch  100  includes the following main functional blocks: control logic block  101 , transceiver block  102 , data converter block  105  and switch fabric  150 . Data converter block  105  includes analog-to-digital (A/D) physical interface  103  and digital-to-analog (D/A) physical interface  104 . 
     As described in more detail below, control logic block  101  and physical ports P 1 -P N  support one or more serial data protocols, which may include (but not limited to), the following: serial rapid input/output (SRio) protocol, Ethernet protocol, PCI Express (PCIe) protocol, Common Public Radio Interface (CPRI) protocol, and Joint Electron Device Engineering Council (JEDEC) data converter protocol. 
     The transceiver block  102  includes “J” transceivers  102   1 - 102   J , each of which can be assigned to an interface port individually. Alternately, more than one of the transceivers  102   1 - 102   J  can be bundled and assigned to one interface port. The transceivers  102   1 - 102   J  convert serial digital data (both control and baseband data) received on ports P 1 -P J  into parallel digital data, which is transmitted on parallel bus system  106 . The transceiver block  102  is bi-directional and converts parallel digital data received from switch fabric  150  (via control block  101 ) into high-speed serial digital data, which is transmitted to serial ports P 1 -P J . The transceivers  102   1 - 102   J  in transceiver block  102  transmit and receive digital signals on the corresponding physical ports P 1 -P J  simultaneously. That is, transceivers  102   1 - 102   J  may receive input signals on physical ports P 1 -P J , respectively, and at the same time, transmit output signals on these same physical ports P 1 -P J . The transceivers  102   1 - 102   J  are configured to operate in accordance with one or more serial protocols. 
     The A/D physical interface  103  includes “K” analog-to-digital converters (ADCs)  103   1 - 103   K . ADCs  103   1 - 103   K  convert analog input signals received on the respective ports P J+1 -P J+K  into L-bit digital baseband signals (wherein “L” is greater than one). The digital baseband signals provided by ADCs  103   1 - 103   K  are provided to control block  101 , and are routed through switch fabric  150 . As described in more detail below, the analog input signals received on ports P J+1 -P J+K  may be provided, for example, by the outputs of radio frequency receivers. 
     The D/A physical interface  104  includes “M” digital-to-analog converters (DACs)  104   1 - 104   M . DACs  104   1 - 104   M  convert L-bit digital baseband signals received from the switch fabric  150  (via control block  101 ) into analog output signals that are provided to ports P J+K+1 -P N  (wherein N=J+K+M). As described in more detail below, the analog output signals provided on ports P J+K+1 -P N  may be routed, for example, to radio frequency transmitters. 
     Control block  101  supports the one or more serial interface protocols (e.g., SRio, CPRI, PCIe, Ethernet and JEDEC), which are implemented within high-speed switch  100 . Control block  101  also controls the routing function, which is implemented by switch fabric  150 . Signals provided to control block  101  from ADCs  103   1 - 103   K  may be routed to transceivers  102   1 - 102   J  and DACs  104   1 - 104   M . Signals provided to control block  101  from transceivers  102   1 - 102   J  may be routed to transceivers  102   1 - 102   J  and DACs  104   1 - 104   M . The output signals transmitted from a particular physical port may have been originally received on the same physical port or on a different physical port. 
       FIG. 2  is a block diagram of a communication system  200  that implements the high-speed switch  100  in accordance with one embodiment of the present invention. Communication system  200  includes baseband card  201 , a backplane or fiber connector  205 , radio card  210 , receiver medium  220 , receiver circuits  221 , transmitter medium  230 , transmitter circuits  231 , and feedback circuits  240 . Radio card  210  includes high-speed switch  100 , field-programmable gate array (FPGA)/digital signal processor (DSP)  211  and SRio/CPRI interface  214 . In the described embodiments, high-speed switch  100  supports the SRio protocol. 
     Baseband card  201  includes a processor  202 , which transmits digital baseband and control output signals in accordance with the SRio protocol to SRio/CPRI interface  204 . In response, SRio/CPRI interface  204  performs an SRio-to-CPRI conversion, which allows the baseband and control signals to be transmitted to backplane/fiber connector  205  in accordance with the CPRI protocol. Note that SRio/CPRI interface  204  also performs a CPRI-to-SRio conversion to allow CPRI protocol signals received from backplane/fiber connector  205  to be transmitted to processor  202  in accordance with the SRio protocol. 
     The SRio/CPRI interface  214  on radio card  210  operates in a manner similar to the SRio/CPRI interface  204  on baseband card  201 . That is, SRio/CPRI interface  214  allows digital baseband and control signals to be transmitted to/from backplane/fiber connector  205  in accordance with the CPRI protocol, and allows digital baseband and control signals to be transmitted to/from high-speed switch  100  in accordance with the SRio protocol. The described embodiment implements the CPRI protocol over backplane/fiber connector  205 , and the SRio protocol within high-speed switch  100  and processor  202 . However, it is understood that these protocols are only exemplary, and that other serial protocols may be used in other embodiments. It is also understood that in yet another embodiment, a single serial protocol may be used to transfer information between processor  202  and high-speed switch  100  through the backplane/fiber connector  205 . In yet another embodiment, processor  202  may be located on radio card  210 , and be coupled directly to a physical port (e.g., port P I ) of high-speed switch  100 , thereby eliminating the need for baseband card  201 , backplane/fiber connection  205  and SRio/CPRI interface  214 . 
     In the embodiment illustrated by  FIG. 2 , SRio/CPRI interface  214  is coupled to transceiver  102   1  of high-speed switch  100  via physical port P. In the described embodiments, transceiver  102   1  is configured to implement the SRio protocol. However, in other embodiments, transceiver  102   1  could be configured to implement another serial protocol, in order to match the serial protocol implemented by the processor  202  on baseband card  201 . 
     The baseband and control signals transmitted from processor  202  enter the high-speed switch  100  through transceiver  102   1 , and are provided to control block  101 . Note that transceiver  102   1  performs a serial-to-parallel conversion of the received baseband and control signal. In accordance with one embodiment of the present invention, control block  101  routes these baseband and control signals through switch fabric  150 , to transceiver  102   2 . Transceiver  102   2  performs a parallel-to serial conversion of the received baseband and control signals. FPGA/DSP  211  of radio card  210  is coupled to transceiver  102   2  via physical port P 2 . As a result, the baseband and control signals received by transceiver  102   2  are transmitted to FPGA/DSP  211 . In the described embodiments, transceiver  102   2  is configured to implement the SRio protocol. However, in other embodiments, transceiver  102   2  could be configured to implement another serial protocol, in order to match the serial protocol implemented by FPGA/DSP  211 . 
     FPGA/DSP  211  processes the received digital baseband signal to create a processed digital baseband signal, which is sent back to the high-speed switch  100  (via transceiver  102   2 ), and is routed to D/A physical interface  104  (via control block  101  and switch fabric  150 ). Transceiver  102   2  performs a serial-to-parallel conversion of the received digital baseband signal. Processing performed by FPGA/DSP  211  may include, but is not limited to, signal conditioning, filtering, and sample rate conversion. As described in more detail below, the processed (parallel) digital baseband signal is routed to D/A physical interface  104 , and is converted to an analog output signal, which is transmitted from high-speed switch  100 . 
     FPGA/DSP  211  also processes the received digital control signal to create a digital response signal, which is sent back to the high-speed switch  100  (via transceiver  102   2 ), and is routed to processor  202  (via control block  101 , switch fabric  150 , transceiver  102   1 , SRio/CPRI interface  214 , backplane/fiber connector  205  and SRio/CPRI interface  204 ). 
     In an alternate embodiment, control block  101  may route the digital baseband signal received from processor  202  through switch fabric  150 , directly to D/A physical interface  104 , without involving FPGA/DSP  211 . It is also noted that the digital baseband and control signals transmitted from processor  202  to high-speed switch  100  may alternately be routed to other transceivers  102   3 - 102   J  in transceiver block  102 , in a manner known by those skilled in the art. 
     Each of the DACs  104   1 - 104   M  in D/A physical interface  104  is capable of receiving a processed (parallel) digital baseband signal from control block  101  (via switch fabric  150 ). The processed digital baseband signals received by DACs  104   1 - 104   M  are converted into analog output signals, which are provided to transmitter circuits  231 . Transmitter circuits  231  combine the analog output signals provided by DACs  104   1 - 104   M  with corresponding radio-frequency (RF) carrier signals, thereby creating RF output signals, which are transmitted through transmitter medium  230 . Transmitter medium  230  may include a transmitter antenna array that transmits the RF output signals wirelessly over the air. Alternately, transmitter medium  230  may include physical cables or twisted-pair conductors that transmit the RF output signals in a wired manner. The transmitted RF output signals are received at a remote location, and are processed to recreate the digital signals originally received by DACs  104   1 - 104   M . The manner in which the RF output signals are processed to recreate the original digital signals is described in more detail below (in the description of the operation of receiver medium  220 , receiver circuits  221  and ADCs  103   1 - 103   A ). 
     Receiver medium  220  receives radio-frequency (RF) input signals from external transmission sources (not shown). These RF input signals are similar to the RF output signals provided by transmitter circuits  231 . Receiver medium  220  may include a receiver antenna array that receives RF input signals that are transmitted wirelessly over the air. Alternately, receiver medium  220  may include physical cables or twisted-pair conductors that receive the RF input signals in a wired manner. Receiver medium  220  provides the received RF input signals to receiver circuits  221 . Receiver circuits  221  perform analog signal processing on the received RF input signals (e.g., filtering the RF carrier signals from the received RF input signals and conditioning the filtered signal) to create analog input signals, which are transmitted to corresponding ADCs  103   1 - 103   A  of A/D physical interface  103 . Each of the ADCs  103   1 - 103   A  samples the corresponding analog input signal received from receiver circuits  221  in order to create a parallel digital input signal. The parallel digital input signals provided by ADCs  103   1 - 103   A  are transmitted on parallel bus system  106  to control block  101 . Control block  101 , in turn, causes the parallel digital baseband signals received from ADCs  103   1 - 103   A  to be routed through switch fabric  150 . 
     In accordance with one embodiment, the control block  101  causes the parallel digital baseband signals received from ADCs  103   1 - 103   A  to be routed to FPGA/DSP  211  for digital signal processing (e.g., conditioning, filtering, sample rate conversion, observe the integrity of the received signal). After performing the desired digital signal processing, FPGA/DSP  211  may transmit the resulting processed digital baseband signal to processor  202  (via transceiver  102   2 , control block  101 , switch fabric  150 , transceiver  102   1 , SRio/CPRI interface  214 , backplane/fiber connector  205 , and SRio CPRI interface  204 ). Alternately, FPGA/DSP  211  may transmit the resulting processed digital baseband signal to one (or more) of transceivers  102   2 - 102   J , wherein the processed digital baseband signal is serialized, using a serial protocol, for transmission to other components that are connected to the switch. 
     In an alternate embodiment, the parallel digital baseband signals output from ADCs  103   1 - 103   A  may be directly routed to processor  202  (via control block  101 , switch fabric  150 , transceiver  102   1 , SRio/CPRI interface  214 , backplane/fiber connector  205 , and SRio CPRI interface  204 ), without involving FPGA/DSP  211 . 
     In yet another embodiment, the parallel digital baseband signals output from ADCs  103   1 - 103   A  may be routed to other transceivers  102   3 - 102   J  (via control block  101  and switch fabric  150 ). These transceivers  102   3 - 102   J  serialize the received parallel digital baseband signals (using a serial protocol), and transmit these serialized signals to other components that are connected to the switch. 
     In accordance with another embodiment of the present invention, the RF output signals provided by transmitter circuits  231  are also transmitted to feedback receiver circuits  240 . Feedback receiver circuits  240  process the RF output signals in the same manner that receiver circuits  221  process the RF input signals. Feedback receiver circuits  240  provide the resulting analog input signals to ADCs  103   B - 103   K , which perform an analog-to-digital conversion in the same manner as ADCs  103   1 - 103   A , thereby creating parallel digital baseband signals, which are transmitted to control block  101 . Control block  101  causes the parallel digital baseband signals received from ADCs  103   B - 103   K  to be routed to FPGA/DSP  211 . FPGA/DSP  211  compares the parallel digital baseband signals received from ADCs  103   B - 103   K  with the corresponding parallel digital baseband signals originally transmitted to DACs  104   1 - 104   M , in order to observe the integrity of the signals transmitted from the transmitter circuits  231 . FPGA/DSP  211  may transmit the results of this comparison to processor  202  (via transceiver  102   2 , control block  101 , switch fabric  150 , transceiver  102   1 , SRio/CPRI interface  214 , backplane/fiber connector  205 , and SRio CPRI interface  204 ). The results of this comparison may be used to improve the integrity of signals subsequently transmitted from the transmitter circuits  231 . 
     High-speed switch  100  introduces a significant amount of flexibility, programmability, security and reliability to radio card  210 . In accordance with one embodiment, high speed switch  100  supports physical ports P 1 -P N  with different speeds and compatible protocols. In accordance with another embodiment, different physical ports P 1 -P N  of high-speed switch  100  may support different protocols. 
     Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. For example, it is understood that communication system  200  can be used in any wireless or wired communication network, including, but not limited to, wireless cellular, Personal Communication System (PCS), wireless Local Area Network, Wireless Wide Area Network, WiMax, Video and Audio Wireless Broadcasting, line of sight microwave, military, optical, and satellite communication systems. It is also understood that in the communication system  200  of  FIG. 2 , additional peripheral devices could be connected to transceivers  102   3 - 102   J , (i.e., physical ports P 3 -P J ) thereby allowing these additional peripheral devices to communicate through high-speed switch  100 . Thus, the present invention is only intended to be limited by the following claims.

Technology Classification (CPC): 7