Patent Abstract:
Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.

Full Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS  
       [0001]     This application claims the priority of Korean Patent Application No. 10-2005-0024076, filed on Mar. 23, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This application relates to semiconductor memory devices, and more particularly, to semiconductor memory devices with a shared open bit line sense amplifier architecture.  
         [0004]     2. Description of the Related Art  
         [0005]     In a dynamic random access memory (DRAM), design considerations such as the arrangement of memory cells, each including a transistor and a capacitor, and the arrangement of sense amplifiers that sense and amplify data output from each memory cell are significant in determining the area and the performance of the DRAM. In general, a memory cell array including a sense amplifier is arranged according to an open bit line method or a folded bit line method.  
         [0006]      FIG. 1  illustrates the open bit line method, in which a memory cell MC is positioned at each intersection of a word line WL and a bit line BL to maximize the density of each memory cell MC and minimize the area of a chip. If the minimum design dimension is F, it is possible to manufacture a memory cell with an area of 4F 2 . However, since each sense amplifier SA must be designed to be arranged inside the pitch of a bit line BL, the design rules for sense amplifiers SA are tight, reducing flexibility in the design of the layout of the sense amplifiers SA. Furthermore, since a pair of bit lines BL connected to the sense amplifier SA are not arranged in the same cell array block, one side of the pair of the bit lines BL may be affected by noise generated in one cell array block, while the other side of the pair is not. Thus, a semiconductor memory device fabricated according to the open bit line method is vulnerable to noise.  
         [0007]      FIG. 2  illustrates a relaxed open bit line method in which a memory cell MC is positioned at each intersection of a word line WL and a bit line BL and each sense amplifier SA is arranged inside the pitch of two bit lines BL. It is easier to design the layout of the sense amplifier SA using the relaxed open bit line method than using the open bit line method. However, it is still difficult to design the layout of the sense amplifier SA using the relaxed open bit line method. In addition, a semiconductor memory device manufactured according to the relaxed open bit line method is vulnerable to noise similar to one manufactured according to the open bit line method.  
         [0008]      FIG. 3  illustrates a folded bit line method in which a sense amplifier SA is arranged inside the pitch of four bit lines BL, and thus, it is easier to design than a sense amplifier using the open bit line method. In addition, since a pair of bit lines BL connected to the sense amplifier SA are installed in the same cell array block, both sides of the pair of the bit lines BL are affected by noise generated in the cell array. Thus, a semiconductor memory device manufactured using the folded bit line method is more immune to noise. However, a memory cell MC manufactured according to the folded bit line method has an area of 8F 2 . The area of the memory cell MC may be double that of the memory cell MC manufactured according to the open bit line method, increasing the required chip area.  
         [0009]     As described above, the area of a memory cell array manufactured according to the open bit line method is reduced, but the memory cell array is vulnerable to noise. In contrast, a memory cell array manufactured according to the folded bit line method is more immune to noise, but the area of a memory cell array is increased.  
         [0010]     Since the trend in DRAMs is to increase capacity, the open bit line method has been used in arranging memory cells to reduce the area of each memory cell array. Accordingly, a method of arranging sense amplifiers that reduces noise is required.  
       SUMMARY OF THE INVENTION  
       [0011]     An embodiment includes a memory device including memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.  
         [0012]     A further embodiment includes a method of operating a memory device including selecting a pair of bit lines from at least four bit lines coupled to a sense amplifier, and sensing the two bit lines using the sense amplifier. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The above and other aspects and advantages of the invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0014]      FIG. 1  illustrates a dynamic random access memory (DRAM) fabricated according to the open bit line method;  
         [0015]      FIG. 2  illustrates a DRAM fabricated according to the relaxed open bit line method;  
         [0016]      FIG. 3  illustrates a DRAM fabricated according to the folded bit line method;  
         [0017]      FIG. 4  illustrates a DRAM with a shared open bit line sense amplifier architecture according to an embodiment;  
         [0018]      FIGS. 5 through 7  illustrate connection of sense amplifiers to bit lines in the DRAM illustrated in  FIG. 4 ;  
         [0019]      FIG. 8  is a circuit diagram of circuits of bit lines connected to a first sense amplifier illustrated in  FIG. 4 ;  
         [0020]      FIG. 9  illustrates a layout of the circuit diagram of  FIG. 6 ;  
         [0021]      FIG. 10  illustrates the operating sequence of a sense amplifier in the DRAM illustrated in  FIG. 4 ;  
         [0022]      FIG. 11  is a timing diagram of the sensing operation of a sense amplifier according to an embodiment; and  
         [0023]      FIG. 12  illustrates equalization of bit lines in the DRAM illustrated in  FIG. 4 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]     Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements in the drawings.  
         [0025]      FIG. 4  illustrates a dynamic random access memory (DRAM)  400  with a shared open bit line sense amplifier architecture according to an embodiment. Referring to  FIG. 4 , the DRAM  400  includes first through third memory cell arrays  410 A,  410 B, and  410 C, each having cells arranged in the form of a matrix. In the first through third memory cell arrays  410 A,  410 B, and  410 C, DRAM cells MC, each including a transistor and a capacitor, are arranged at intersections of word lines WLi and bit lines BLj (i denotes a number from 0 to 11, and j denotes a number from 0 to 3). That is, the first through third memory cell arrays  410 A,  410 B, and  410 C are manufactured according to the open bit line method. If the minimum design dimension is F, the memory cell MC may have an area of 4F 2  or 6F 2 .  
         [0026]     A first sense amplifier  420  is arranged inside the pitch of four bit lines BL 0  through BL 3  between the first and second memory cell arrays  410 A and  410 B, and a second sense amplifier  430  is arranged inside the pitch of four bit lines BL 0  through BL 3  between the second and third memory cell arrays  410 B and  410 C. Thus, the first sense amplifier  420  is shared by the first and second memory cell arrays  410 A and  410 B, and the second sense amplifier  430  is shared by the second and third memory cell arrays  410 B and  410 C.  
         [0027]      FIG. 4  illustrates that first through fourth word lines WL 0  through WL 3  are in the first memory cell array  410 A, fifth through eighth word lines WL 4  through WL  7  are in the second memory cell array  410 B, and ninth through twelfth word lines WL 8  through WL 11  are in the third cell array  410 C. However, the number of word lines in each memory cell array is not limited to four. Referring to  FIG. 4 , one of the first and second amplifiers  420  and  430  is positioned inside the pitch of the four bit lines BL 0  through BL 3  in the first through third memory cell arrays  410 A,  410 B, and  410 C. However, one of the first and second amplifiers  420  and  430  may also be positioned inside the pitch of every 4N bit lines (N≧1).  
         [0028]     In this embodiment, the four bit lines BL 0  through BL 3  in the first through third memory cell arrays  410 A,  410 B, and  410 C, and the first and second sense amplifiers  420  and  430  connected to the four bit lines BL 0  through BL 3  are collectively labeled a unit of layout  440 . It is possible to manufacture a large-capacity DRAM  400  by using the unit of layout  440  repeatedly.  
         [0029]     The bit lines BL 0  through BL 3  of the first and second memory cell arrays  410 A and  410 B adjacent the ends of the first sense amplifier  420  are connected to the first sense amplifier  420 . Specifically, a first bit line BL 0   A  and a third bit line BL 2   A  of the first memory cell array  410 A are connected to the left side of the first sense amplifier  420 , and a first bit line BL 0   B  and a third bit line BL 2   B  of the second memory cell array  410 B are connected to the right side of the first sense amplifier  420 .  
         [0030]     The bit lines BL 0  through BL 3  of the second and third memory cell arrays  410 B and  410 C which are positioned at the ends of the second sense amplifier  430 , respectively, are connected to the second sense amplifier  430 . Specifically, a second bit line BL 1   B  and a fourth bit line BL 3   B  of the second memory cell array  410 B are connected to the left side of the second sense amplifier  430 , and a second bit line BL 1   C  and a fourth bit line BL 3   C  of the third memory cell array  410 C are connected to the right side of the second sense amplifier  430 .  
         [0031]     The first sense amplifier  420  uses the third bit line BL 2   B  of the second memory cell array  410 B as a reference in sensing the first bit line BL 0   A  of the first memory cell array  410 A, and the first bit line BL 0   B  of the second memory cell array  410 B as a reference in sensing the third bit line BL 2   A  of the first memory cell array  410 A. Similarly, as illustrated in  FIG. 5 , the first sense amplifier  420  uses the third bit line BL 2   A  of the first memory cell array  410 A as a reference in sensing the first bit line BL 0   B  of the second memory cell array  410 B, and the first bit line BL 0   A  of the first memory cell array  410 A as a reference in sensing the third bit line BL 2   B  of the second memory cell array  4101 B.  
         [0032]     In other words, to sense one of the bit lines BL 0   A  and BL 2   A  of the first memory cell array  410 A as a data line, the first sense amplifier  420  uses one of the bit lines BL 2   B  and BL 0   B  of the second memory cell array  410 B that is diagonal to the sensed bit line as a reference line. To sense one of the bit lines BL 0   B  and BL 2   B  of the second memory cell array  410 B as a data line, the first sense amplifier  420  uses one of the bit lines BL 2   A  and BL 0   A  of the first memory cell array  410 A that is diagonal to the sensed bit line as a reference line.  
         [0033]     Referring to  FIG. 6 , the second sense amplifier  430  uses the fourth bit line BL 3   C  of the third memory cell array  410 C as a reference in sensing the second bit line BLIB of the second memory cell array  410 B, and the second bit line BL 1   C  of the third memory cell array  410 C as a reference in sensing the fourth bit line BL 3   B  of the second memory cell array  410 B. Similarly, referring to  FIG. 7 , the second sense amplifier  430  uses the fourth bit line BL 3   B  of the second memory cell array  410 B as a reference in sensing the second bit line BL 1   C  of the third memory cell array  410 C, and the second bit line BL 1   B  of the second memory cell array  410 B as a reference in sensing the fourth bit line BL 3   C  of the third memory cell array  410 C.  
         [0034]     That is, to sense one of the bit lines BL 1   B  and BL 3   B  of the second memory cell array  410 B as a data line, the second sense amplifier  430  uses one of the bit lines BL 3   C  and BL 1   C  of the third memory cell array  410 C that is diagonal to the sensed bit line as a reference line. Also, to sense one of the bit lines BL 1   C  and BL 3   C  of the third memory cell array  410 C as a data line, the second sense amplifier  430  uses one of the bit lines BL 3   B  and BL 1   B  of the second memory cell array  410 B that is diagonal to the sensed bit line as a reference line.  
         [0035]      FIG. 8  is a circuit diagram of circuits of bit lines connected to the first sense amplifier  420 . Referring to  FIG. 8 , first and second equalization circuits  610  and  630 , first and second isolation units  620  and  640  (also referred to as switching units), a column selection unit  650 , and a second sense amplifier  420  are installed between first and third bit lines BL 0   A  and BL 2   A  of a first memory cell array  410 A, and first through third bit lines BL 0   B  and BL 2   B  of the second memory cell array  410 B.  
         [0036]     The first equalization circuit  610  is connected between the first and third bit lines BL 0   A  and BL 2   A  of the first memory cell array  410 A. The first equalization circuit  610  equalizes the voltages of the first and third bit lines BL 0   A  and BL 2   A  of the first memory cell array  410 A with a voltage of Vcc/2 in response to an equalization signal EQ.  
         [0037]     The first isolation unit  620  selectively connects the first and third bit lines BL 0   A  and BL 2   A  of the first memory cell array  410 A to the first sense amplifier  420  in response to a first isolation signal ISO_A and a second isolation signal ISO_B. The first isolation unit  620  includes a first isolation transistor  621  and a second isolation transistor  622 . The first isolation transistor  621  transmits a signal of the first bit line BL 0   A  of the first memory cell array  410 A to a first sensing node  421  of the first sense amplifier  420  in response to the first isolation signal ISO_A. The second isolation transistor  622  transmits a signal of the third bit line BL 2   A  of the first memory cell array  410 A to a second sensing node  422  of the first sense amplifier  420  in response to the second isolation signal ISO_B.  
         [0038]     The second equalization circuit  630  is connected between the first and third bit lines BL 0   B  and BL 2   B  of the second memory cell array  410 B, and equalizes the voltages of the first and third bit lines BL 0   B  and BL 2   B  of the second memory cell array  410 B with a voltage of Vcc/2 in response to the equalization signal EQ.  
         [0039]     The second isolation unit  640  includes a third isolation transistor  641  which transmits a signal of the first bit line BL 0   B  of the second memory cell array  410 B to the first sensing node  421  of the first sense amplifier  420  in response to the second isolation signal ISO_B, and a fourth isolation transistor  642  which transmits a signal of the third bit line BL 2   B  of the second memory cell array  410 B to the second sensing node  422  of the first sense amplifier  420  in response to the first isolation signal ISO_A.  
         [0040]     The first sense amplifier  420  includes a first PMOS transistor  423  connected between a power supply voltage Vcc and the first sensing node  421 , with a gate connected to the second sensing node  422 ; a second PMOS transistor  424  connected between the power supply voltage Vcc and the second sensing node  422 , with a gate connected the first sensing node  421 ; a first NMOS transistor  425  connected between the first sensing node  421  and a ground voltage Vss, with a gate connected to the second sensing node  422 ; and a second NMOS transistor  426  connected between the second sensing node  422  and the ground voltage Vss, whose gate is connected to the first sensing node  421 .  
         [0041]     The column selection unit  650  applies a voltage of the first sensing node  421  sensed by the first sense amplifier  420  and a voltage of the second sensing node  422  to a data line DIO in response to a column selection signal CSL.  
         [0042]     In the circuits illustrated in  FIG. 8 , the first isolation unit  620  transmits a signal of the first bit line BL 0   A  of the first memory cell array  410 A to the first sensing node  421  of the first sense amplifier  420  in response to the first isolation signal ISO_A. The second isolation unit  640  transmits a signal of the third bit line BL 2   B  of the second memory cell array  410 B to the second sensing node  422  of the first sense amplifier  420  also in response to the first isolation signal ISO_A. Accordingly, the first sense amplifier  420  performs a sensing operation using the first bit line BL 0   A  of the first memory cell array  410 A and the third bit line BL 2   B  of the second memory cell array  410 B as a data line and a reference, or a reference line and a data line, respectively.  
         [0043]     Alternatively, the first isolation unit  620  transmits a signal of the third bit line BL 2   A  of the first memory cell array  410 A to the second sensing node  422  of the first sense amplifier  420  in response to the second isolation signal ISO_B. The second isolation unit  640  transmits a signal output from the first bit line BL 0   B  of the second memory cell array  410 B to the first sensing node  421  of the first sense amplifier  420  in response to the second isolation signal ISO_B. Thus, the first sense amplifier  420  performs a sensing operation using the third bit line BL 2   A  of the first memory cell array  410 A and the first bit line BL 0   B  of the second memory cell array  410 B as a data line and a reference line, respectively, or a reference line and a data line, respectively.  
         [0044]     The operation of the first isolation unit  620  matches the above operation of the first sense amplifier  420  that uses, as a reference line, the bit line BL 2   B  or BL 0   B  of the second memory cell array  410 B that is diagonal to the bit line BL 0   A  or BL 2   A  of the first memory cell array  410 A to be sensed as a data line, and uses, as a reference line, the bit line BL 2   A  or BL 0   A  of the first memory cell array  410 A that is diagonal to the bit line BL 0   B  or BL 2   B  of the second memory cell array  410 B to be sensed as a data line.  
         [0045]      FIG. 9  illustrates a layout of the circuits of  FIG. 8 . Referring to  FIG. 9 , the first equalization circuit  610 , the first isolation unit  620 , the column selection unit  650 , the second sense amplifier  420 , the second isolation unit  640 , and the second equalization circuit  630  are arranged inside the pitch of the four bit lines BL 0  through BL 3  between the first memory cell array  410 A and the second memory cell array  410 B.  
         [0046]      FIG. 10  illustrates an operating sequence of each sense amplifier with the shared open bit line architecture sense amplifier, illustrated in  FIG. 4 . Referring to  FIG. 10 , first, the first sense amplifier  420  performs a sensing operation using the first bit line BL 0   A  of the first memory cell array  410 A and the third bit line BL 2   B  of the second memory cell array  410 B as a data line and a reference line, respectively, or as a reference line and a data line, respectively ({circle around (1)}). Second, the second sense amplifier  430  performs a sensing operation using the second bit line BL 1   B  of the second memory cell array  410 B and the fourth bit line BL 3   C  of the third memory cell array  410 C as a data line and a reference line, respectively, or as a reference line and a data line, respectively ({circle around (2)}). Third, the first sense amplifier  420  performs a sensing operation using the third bit line BL 2   A  of the first memory cell array  410 A and the first bit line BL 0   B  of the second memory cell array  410 B as a data line and a reference line, respectively, or as a reference line and a data line, respectively ({circle around (3)}). Fourth, the second sense amplifier  430  performs a sensing operation using the fourth bit line BL 3   B  of the second memory cell array  410 B and the second bit line BL 1   C  of the third memory cell array  410 C as a data line and a reference line, respectively, or as a reference line and a data line, respectively ({circle around (4)}).  
         [0047]     The reason why a sensing operation is performed in the sequence from the first sensing operation {circle around (1)} to the fourth sensing operation {circle around (4)} will now be described. In the first sensing operation {circle around (1)}, the first sense amplifier  420  senses the first bit line BL 0   A  of the first memory cell array  410 A and the third bit line BL 2   B  of the second memory cell array  410 B to fully swing the voltage of the first bit line BL 0   A  of the first memory cell array  410 A and the voltage of the third bit line BL 2   B  of the second memory cell array  410 B to a power supply voltage Vcc and the ground voltage Vss, respectively. Therefore, the second bit line BL 1   B  and the fourth bit line BL 3   B , which are adjacent to the third bit line BL 2   B  of the second memory cell array  410 B, are coupled to the third bit line BL 2   B  and thus affected by noise.  
         [0048]     To reduce problems of the second bit line BL 1   B  of the second memory cell array  410 B caused by noise in the second sensing operation {circle around (2)}, the second sense amplifier  430  senses the second bit line BL 1   B  of the second memory cell array  410 B and the fourth 4 bit line BL 3   C  of the third memory cell array  410 C. As a result of the second sensing operation {circle around (2)}, the voltage of the second bit line BL 1   B  of the second memory cell array  410 B and the voltage of the fourth bit line BL 3   C  of the third memory cell array  410 C fully swing to the power supply voltage Vcc and the ground voltage Vss, respectively. Thus, the first bit line BL 0   B  adjacent to the second bit line BL 1   B  of the second memory cell array  410 B is coupled to the second bit line BL 1   B , thus affected by noise.  
         [0049]     To reduce problems of the first bit line BL 0   B  of the second memory cell array  410 B caused by noise in the third sensing operation {circle around (3)}, the first bit line BL 0   B  of the second memory cell array  410 B and the third bit line BL 3   A  of the first memory cell array  410 A are sensed. Lastly, in the fourth sensing operation {circle around (4)}, the second sense amplifier  430  senses the fourth bit line BL 3   B  of the second memory cell array  410 B and the second bit line BL 1   C  of the third memory cell array  410 C.  
         [0050]     As described with reference to  FIG. 8 , similar to the first and second isolation units  620  and  640  connected to the first sense amplifier  420 , third and fourth isolation units (not shown) that operate in response to the first and second isolation signals ISO_A and ISO_B, respectively, can be installed between the second and fourth bit lines BL 1   B  and BL 3   B  of the second memory cell array  410 B and the second sense amplifier  430  and between the second sense amplifier  430  and the second and fourth bit lines BL 1   C  and BL 3   C  of the third memory cell array  410 C. In this case, referring to  FIG. 11 , the first sensing operation {circle around (1)} and the second sensing operation {circle around (2)} are simultaneously performed at a point of time t 1 , and then, the third sensing operation {circle around (3)} and the fourth sensing operation {circle around (4)} are simultaneously performed at a point of time t 2 .  
         [0051]      FIG. 12  illustrates equalization of bit lines of the DRAM  400  of  FIG. 4 . Referring to  FIGS. 8 and 12 , the first and second isolation units  620  and  640  turn off the first and second isolation transistors  621 ,  622 ,  641 , and  642  when the first and second isolation signals ISO_A and ISO_B are deactivated. Then, the first bit line BL 0   A  and the third bit line BL 2   A  of the first memory cell array  410 A, and the first bit line BL 0   B  and the third bit line BL 2   B  of the second memory cell array  410 B are separated from the first sense amplifier  420 . Likewise, the second bit line BL 1   B  and the fourth bit line BL 3   B  of the second memory cell array  410 B, and the second bit line BL 1   C  and the fourth bit line BL 3   C  of the third memory cell array  410 C are separated from the second sense amplifier  430 .  
         [0052]     The first equalization unit  610  equalizes the voltages of the first bit line BL 0   A  and the third bit line BL 2   A  of the first memory cell array  410 A, which are separated from the first sense amplifier  420 , with a voltage of Vcc/2 in response to the equalization signal EQ. The second equalization circuit  630  equalizes the voltages of the first bit line BL 0   B  and the third bit line BL 2   B  of the second memory cell array  410 B, which are separated from the first sense amplifier  420 , with the voltage of Vcc/2 in response to the equalization signal EQ. Also, the voltages of the second bit line BL 1   B  and the fourth bit line BL 3   B  of the second memory cell array  410 B and the second bit line BL 1   C  and the fourth bit line BL 3   C  of the third memory cell array  410 C, which are separated from the second sense amplifier  430 , are equalized with the voltage of Vcc/2 in response to the equalization signal EQ. The voltages of all the bit lines of the DRAM  400  are equalized to the voltage of Vcc/2 in response to the equalization signal EQ.  
         [0053]     Accordingly, in a DRAM according to an embodiment, one memory cell is arranged at each intersection of a word line and a bit line, a sense amplifier is arranged inside the pitch of four bit lines in an open bit line architecture with each memory cell having an area of 4F 2 , and a sense amplifier is arranged to be shared by a first memory cell array and a second memory cell array on opposite sides of the sense amplifier. In the sense amplifier, two bit lines are connected to a first memory cell array and two bit lines are connected to a second memory cell array. Also, to sense a bit line of the first memory cell array as a data line, a sense amplifier uses, as a reference line, a bit line of the second memory cell array that is diagonal to the data line.  
         [0054]     Although embodiments have been described with reference to three memory cell arrays and two sense amplifiers, one of ordinary skill in the art will understand that embodiments may include any number of memory cell arrays or sense amplifiers.  
         [0055]     Although a sense amplifier having isolation units have been described with reference to selectively connecting one bit line from two bit lines to one side of the sense amplifier, one of ordinary skill in the art will understand that an isolation unit may selectively connect one bit line from more than two bit lines to one side of the sense amplifier.  
         [0056]     While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Classification (CPC): 6