Patent Abstract:
In a frequency-voltage conversion circuit, integrating means gives a predetermined slope for rising or falling of a rectangular pulse signal. First comparing means compares an output value of the integrating means with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. Storing means stores and retains the threshold value. Smoothing means smooths the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. Second comparing means compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing means on the basis of the comparison result.

Full Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present application is a divisional of copending application Ser. No. 09/450,331 filed on Nov. 29, 1999. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a frequency-voltage conversion circuit and a receiving apparatus applicable for a direct conversion receiver which receives and demodulates a FSK Frequency Shift Keying) signal. 
     A superheterodyne method and a direct conversion method are generally used in a FSK (Frequency Shift Keying) receiver. In each method, demodulation is carried out by the use of the known F-V (Frequency-Voltage) conversion. 
     Referring to FIG. 1, description will be made about a related direct conversion receiver using the F-V conversion. 
     In a Weber receiver illustrated in FIG. 1 the direct conversion receiver, a base-band cross signal is brought up to intermediate frequency (namely, up-conversion is conducted), and the F-V conversion is performed. 
     The FSK signal sent from a receiver (not shown) is received by an antenna  101 , is amplified by a high frequency amplifier  102 , and is given to mixers  103  and  104 , respectively. 
     A local oscillator  107  produces an oscillation signal. The oscillation signal is shifted with π/2 by the use of a π/2 shifter  105 , and is given to the mixer  103 . Further, the frequency signal from the local oscillator  107  is directly given to the mixer  104 . 
     Low pass filters (hereinafter, abbreviated as LPFs)  106  and  108  are connected to the mixers  103  and  104 , respectively. In this condition, output signals from the mixers  103  and  104  are given to the LPSs  106  and  108 , respectively. 
     Each of the LPFs  106  and  108  has passing band equivalent to the base band signal, and realizes or obtains selectivity between adjacent channels. Further, the LPFs  106  and  108  supply output signals corresponding to signals from the mixers  103  and  104  into an up-conversion portion  130 . 
     In this case, the up-conversion portion  130  is composed of mixers  109  and  110 , a local oscillator  113 , a π/2 shifter, and an adder  112 , as illustrated in FIG.  1 . 
     With this structure, the mixer  109  is given with an oscillation signal from the local oscillator  113 . Further, the oscillation signal from the local oscillator  113  is shifted with π/2 by a π/2 shifter  111 , and is given to the mixer  110 . 
     Signals multiplied by the mixers  109  and  110  are added by the adder  112  Alternatively, the multiplied signals may be subtracted by a subtracter (not shown). An output signal of the adder  112  is converted by the use of a delay detection portion  114 . 
     In the above-mentioned Weber receiver  131 , a carrier wave frequency of the received FSK signal is defined as ω/2 π while frequency deviation is defined as ±Δω/2 π. In this condition, the received FSK signal Sr FSK  is represented by the following equation. 
     
       
           Sr   FSK =cos(ω±Δω) t    
       
     
     In this event, when the output signal S OSC1  of the local oscillator  107  is defined as S OSC1 =sin ωt, the output signals S MIX3  and S MIX4  of the mixers  103  and  104  are represented by the following equations, respectively. 
     
       
           S   MIX3 =cos(ω±Δω) t ·cos ω t = ½{cos(ω±Δω+ω) t +cos(ω±Δω·ω)  t}= ½{cos(2ω±Δω) t +cos(±Δω t )} 
       
     
     
       
           S   MIX4 =cos(ω±Δω) t ·sin ω t = ½{sin(ω±Δω+ω) t +sin(ω±Δω·ω) t}= ½{sin(2ω±Δω) t +sin(±Δω t )} 
       
     
     First terms of these equations are removed by the LPFs  106  and  108 . Therefore, the outputs S LPF6  and S LPF8  of the LPFs  106  and  108  are represented by the following equations. 
     
       
           S   LPF6 =½{cos(Δω t )}  (1)  
       
     
     
       
           S   LPF8 =±½{sin(Δω t )}  (2)  
       
     
     In this case, when calculation is carried out without limiter amplifiers  128  and  129  so as to be readily understood, an output signal Vout of the up-conversion portion  130  is modified as follows. Herein, it is to be noted that the output signal of the local oscillator  113  is defined by S OSC2 =sin ω2t. 
     
       
           Vout= ½{cos(Δω t )sin ω2 t )}±½{sin(Δω t )cos ω2 t )}=½{sin(ω2±Δω)}  (3)  
       
     
     From the above-mentioned result, the base band signal I, Q is converted to a signal having frequency deviation of ±Δω/2πwhen the intermediate frequency ω2/2π is defined as a center. 
     Subsequently, when the limiter amplifiers  128  and  129  are inserted between the LPF  106  and the mixer  109  or between the LPF  108  and the mixer  110 , the condition is explained as follows. 
     When inputs into the mixers  109  and  110  becomes rectangular wave by the limiter amplifiers  128  and  129 , outputs S LPF6′  and S LPF8′ , are modified as follows by Fourier transforming the above-mentioned equations (1) and (2) Herein, it is to be noted that constant is defined as k=2/π. 
     
       
           S   LPF6′   =k {cos(Δω t )}+⅓·cos(3 Δωt ) +⅕·cos(5 Δωt )+. . .}  (1′)  
       
     
     
       
           S   LPF8′   =k {sin(ω2±ω) t + ⅓·sin(3(ω2±Δω) t + ⅕·sin(5(ω2±Δω) t )+. . .}  (2′)  
       
     
     Namely, the output Vout′ of the up-conversion portion  130  is similarly considered to be the modification of the above-mentioned equation (3). Thereby, the following equation is introduced. 
     
       
         Vout= k {sin(ω2±ω)  t + ⅓·sin(3(ω2±Δω) t + ⅕·sin(5(ω2±Δω) t )+. . .}  (3′)  
       
     
     Consequently, it is found out that the conversion-up becomes possible even when the limiter amplifiers  128  and  129  are inserted between the LPF  106  and the mixer  109  or between the LPF  108  and the mixer  110 . 
     Although the Weber receiver  131  has been suggested as a SSB (Single Side Band) receiver, it is found out that the Weber receiver  131  is applicable as the FSK receiver, as explained above. 
     The output signal of the adder  112  is given to the delay detection portion  114 , and the F-V conversion is carried out in the delay detection portion  114 . 
     In FIG. 2, a detail structure of the delay detection portion  114  is illustrated. Further, a timing chart showing change (waveform) of each signal of each portion in the delay detection portion  114  is illustrated in FIG.  3 . 
     A signal V A  from the adder  112  is converted into output signals V B  and V C  by removing amplitude demodulation components by the use of a limiter amplifier  119 . 
     Subsequently, the output signals V B  and V C  are converted into signals V D  and V E  having desired slopes at rising through common-emitter transistors  121  and  221 . Further, the signals V D  and V E  are converted into signals V F  and V G  by comparators  123  and  223  given with threshold level V TH26  from a reference voltage  126 . 
     In this event, the transistors  121  and  221  are coupled to constant current sources  120 ,  220  and capacitors  122 ,  222 , respectively. 
     Moreover, the signals V F  and V G  are converted into a signal V H  via an AND gate (namely logical product). Thereby, pulse signal line, which has constant amplitude and constant delay time τ, is formed, as illustrated in FIG.  3 . 
     Finally, the pulse signal line V H  is integrated by a LPF  125 , and converted into a voltage value V I  corresponding to frequency. Further, the obtained voltage V I  is converted into a logic data signal consisting of “1” and “0” by a converter (not shown). 
     In FIG. 4, frequency spectrums are illustrated so as to explain the above-mentioned structure. In an intermediate stage in the FIG. 4, center frequency between frequency of “1” and frequency of “0” becomes carrier wave frequency. 
     In FIG. 5, characteristic obtained the delay detection portion  114  is illustrated. In the above-mentioned example, demodulation sensitivity KD is defined as KD=2τ V [V/Hz]. Consequently, the characteristic is affected by variation of τ and V. Herein, it is to be noted that τ represents delay time while V indicates output amplitude of the signal V H . 
     Moreover, the delay time τ is inversely proportional to variation of the constant current sources  120  and  220  illustrated in FIG. 2, and is proportional to variation of static capacitance of the capacitors  122  and  222 . Further, the delay time τ is proportional to the threshold voltage V TH26 . 
     Specifically, the demodulation sensitivity is fluctuated by variation of manufacturing condition. In addition, Further, F-V conversion output amplitude is varied in the direct-conversion method using the F-V conversion. As a result, receiving condition may be deteriorated. 
     Further, the power supply voltage is restricted from the same reason, and reneality of the F-V conversion is degraded. In consequence, receiving condition is also degraded. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of this invention to provide a frequency-voltage conversion circuit which is capable of correcting manufacturing variation and change with time caused by the variation. 
     It is another object of this invention to provide a frequency-voltage conversion circuit which is capable of demodulating a FSK signal with stable and high sensibility and linearity. 
     In a frequency-voltage conversion circuit according to this invention, integrating means gives a predetermined slope for rising or falling of a rectangular pulse signal. 
     First comparing means compares an output value of the integrating means with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. 
     Storing means stores and retains the threshold value. Smoothing means smooths the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. 
     Second comparing means compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing means on the basis of the comparison result. 
     In this case, the integrating means comprises a constant current device which produces constant current, and a static capacitance device which stores the current. 
     With such a structure, the second comparing means discharges the electric charge from the storing means when the voltage value is higher than the reference voltage. 
     On the other hand, the second comparing means charges electric charge for the storing means when the voltage value is lower than the reference voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a related direct conversion receiver using F-V conversion; 
     Fig. 2 is a connection diagram showing a detail structure of the delay detection portion  114  illustrated in FIG. 1; 
     FIG. 3 is a timing chart showing change (waveform) of each signal of each portion in the delay detection portion  114  illustrated in FIG. 1; 
     FIG. 4 is diagram showing frequency spectrums for explaining function of the direct-conversion receiver; 
     FIG. 5 is a characteristic diagram showing characteristic obtained by the delay detection portion  114  illustrated in FIG. 1; 
     FIG. 6 is a block diagram showing a structure of a receiver according to a first embodiment of this invention; 
     FIG. 7 is a connection diagram showing a detail structure of the delay detection portion  14  illustrated in FIG. 6; 
     FIG. 8 is a timing chart showing change (waveform) of each signal of each portion in the delay detection portion  14  illustrated in FIG. 6; 
     FIG. 9 is a characteristic diagram showing difference of F-V conversion characteristic (demodulation sensitivity) due to difference of threshold level V TH16 ; 
     FIG. 10 is a connection diagram showing a detail structure of a delay detection portion  14  in frequency-voltage conversion circuit according to a second embodiment of this invention; and 
     FIG. 11 is a timing chart showing change (waveform) of each signal of each portion in the delay detection portion illustrated in FIG.  10 . 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Hereinafter, description will be made about embodiments of this invention with drawings. 
     First Embodiment 
     Referring to FIG. 6, description will be made about a first embodiment of this invention. 
     A FSK (Frequency Shift Keying) signal transmitted from a transmitter (not shown) is received via an antenna  1 , is amplified by a high-frequency amplifier  2  ,and is given to mixers  3  and  4 , respectively. 
     An oscillation signal from a local oscillator  7  is shifted with 2/π by a 2/π shifter  5 . The shifted signal is given to the mixer  3  while the oscillation signal from the local oscillator  7  is directly given to the mixer  4 . 
     The mixers  3  and  4  are connected to LPFs (Low Pass Filters)  6  and  8  as channel filters, respectively. Output signals of the mixers  3  and  4  are given to the LPFs  6  and  8 . 
     Each of the LPFs  6  and  8  has passing band equivalent to a base band signal, and realizes or obtains selectivity between adjacent channels. Further, the LPFs  6  and  8  supply output signals corresponding to signals from the mixers  3  and  4  into an up-conversion portion  30 . 
     The up-conversion portion  30  is composed of a mixer  9 , a mixer  10 , a local oscillator  13 , a 2/π shifter  11 , and an adder  12 . The mixer  9  is given with an oscillation signal from the local oscillator  13 . On the other hand, the oscillation signal from the local oscillator  13  is shifted with 2/π by the 2/π shifter  5 . The shifted signal is given to the mixer  10 . 
     Signals multiplied by the mixers  9  and  10  are added by the use of an adder  12 . Alternatively, the multiplied signals may be subtracted by a subtracter (not shown). 
     The reference numeral  32  represents a switch which switches a signal obtained by a Weber receiver  31  with an output signal of the local oscillator  13 . The reference numeral  14  indicates a delay detection portion which F-V converts an output signal of the switch  32 . Further, the reference numeral  18  represents a control portion which controls the switch  32  and the delay detection portion  14 . 
     The switch  32  gives the output signal of the local oscillator  13  into the delay detection portion  14  when a control signal S 18  is put into “H” (high level). On the other hand, the switch  32  gives the output signal of the adder  12  into the delay detection portion  14  when the control signal S 18  is put into “L” (low level). 
     In FIG. 7, a signal V A  (rectangular pulse signal) from the above adder  12  is removed amplitude modulation components thereof by a limiter amplifier  19 , and is converted into output signals V B  and V C  respectively. 
     Subsequently, the output signals V B  and V C  are converted into signals V D  and V E  having desired slopes at rising through common-emitter transistors  21   a  and  21   b . Herein, it is to be noted that each of the signals V D  and V E  may have the slope at falling. 
     Further, the signals V D  and V E  are converted into signals V F  and V G  by comparators  23   a  and  23   b.    
     In this event, the transistors  21   a  and  21   b  are coupled to constant current sources  20   a ,  20   b  and capacitors  22   a ,  22   b , respectively. The comparators  23   a  and  23   b  are coupled to a capacitor  16 , and is given with an output signal of a VI amplifier  15 . 
     Further, the signals V F  and V G  are converted into a signal V H  via an AND gate (logical product). Thereby, a pulse signal line V H , which has constant amplitude and constant delay time τ, is formed, as illustrated in FIG.  8 . 
     The pulse signal line V H  is integrated by a LPF  25 , and is converted into a voltage value V I  corresponding to frequency. 
     Further, the voltage value V I  is compared with a reference voltage  17  (V REF ). An output signal of the V I  amplifier  15  is supplied as a reference voltage of the comparator  23   a ,  23   b.    
     With such a structure, when the control signal S 18  is put into “L” (low level), the switch  32  selects the output of the adder  32 . Consequently, the VI amplifier  15  is put into an off-state (namely, an output terminal is opened). Consequently, electric charge (threshold level V TH16 ) of the capacitor  16  is retained or kept. 
     On the other hand, when the control signal S 18  is put into “H” (high level), the switch  32  selects the output signal of the local oscillator  32 . As a result, the VI amplifier  15  is put into an on-state. Thereby, feedback in the delay detection portion  14  is activated. 
     As mentioned above, the signal V A  from the delay detection portion  14  is removed the amplitude modulation components thereof by the limiter amplifier  19 , and is converted into the signals V B  and V C . In this event, the signals V B  and V C  have phases reverse to each other. 
     Subsequently, the output signals V B  and V C  are converted into signals V D  and V E  by the common-emitter transistors  21   a  and  21   b , and further, converted into signals V F  and V G  by the comparators  23   a  and  23   b . Herein, it is to be noted that each of the comparators  23   a  and  23   b  has the threshold level V TH16 . 
     Further, the signals V F  and V G  are converted into a signal V H  by via the AND gate. Thereby, pulse signal line V H  having the constant amplitude and the constant delay time τ is formed, as described before. 
     Finally, the pulse signal line V H  is integrated by the LPF  25 , and is converted into the voltage value V I  corresponding to the frequency of the signal V A . 
     The voltage value V I  is compared with the reference voltage V REF . As a result of the comparison, when the voltage value V I  is higher than the reference voltage V REF , the output of the VI amplifier  15  is put into “L”. Thereby, electric charge off the capacitor  16  is discharged. In consequence, the threshold level V TH16  is lowered or reduced. 
     On the other hand, when the voltage value V I  is lower than the reference voltage V REF , the output of the VI amplifier  15  is put into “H”. Thereby, electric charge of the capacitor  16  is charged. Thereby, the threshold level V TH16  is increased. 
     In the first embodiment, the delay time τ is adjusted on the condition that the control signal S 18  is put into “H”. Thereby, the voltage value V I  from the delay detection portion  14  is converged to the reference voltage V REF . In this event, frequency given to the delay detection portion  14  is equal to center frequency of a second FSK signal. 
     On the other hand, when the control signal S 18  is put into “L”, a normal receiving state appears. In this case, frequency given to the delay detection portion  14  is equal to the second FSK signal. Therefore, the control signal S 18  is put into “H” during signal receiving wait state or during signal receiving state unnecessary to receive a signal. 
     The above-mentioned delay time τ is inversely proportional to current variation of the constant current source  20   a ,  20   b . Further, the delay time τ is proportional to variation of static capacitance of the capacitor  22   a ,  22   b , and is proportional to the threshold voltage V TH16  as the reference voltage given to the comparator  23   a ,  23   b.    
     In this embodiment, when the voltage value V I  is higher than the reference voltage V REF , the delay time τ becomes higher than a value to be essential. In this case, the VI amplifier  15  discharges electric charge of the capacitor  16  so as to reduce V TH16 . Thereby, the delay time τ becomes low. In consequence, the voltage value V I  is reduced, and the voltage value V I  is finally is converged to V REF . 
     On the other hand, when the voltage value V I  is lower than the reference voltage V REF , the delay time τ becomes lower than the value to be essential. In this event, the VI amplifier  15  charges electric charge of the capacitor  16  so as to increase V TH16 . Thereby, the delay time τ becomes high. Consequently, the voltage value V I  is increased, and the voltage value V I  is finally is converged to V REF . 
     In FIG. 9, F-V conversion characteristic (demodulation sensibility) is illustrated in accordance with difference of the threshold levels V TH16 . 
     Herein, it is to be noted that each straight line A, B and C in FIG. 9 corresponds to each level A, B and C illustrated in FIG.  8 . 
     The voltage value V I  is equal to a voltage corresponding to center frequency of the second FSK signal. Therefore, the voltage corresponding to the center frequency is compatible with the reference voltage V REF . Thereby, variation of the demodulation sensibility is substantially eliminated, and the F-V conversion characteristic is corrected as the straight line B illustrated in FIG.  9 . 
     When the receiving sate becomes normal by putting the control signal S 18  into “L”, the reference voltage V REF  is used as reference voltage of a comparator or an A/D (Analog/Digital) converter given with the voltage VI, and thereby, corresponds to center frequency of accurate second FSK signal. 
     Second Embodiment 
     Referring to FIG. 10, description will be made about a second embodiment of this invention. Herein, it is to be noted that the same reference numeral is attached to the same portion as each portion illustrated in FIG.  7 . 
     In the second embodiment, a current control portion  27  is controlled by the use of a control signal S 18  from the control portion  18 . The current control portion  27  compares the voltage value V I  with the reference voltage V REF , and controls constant current sources  40   a  and  40   b  on the basis of the comparing result via the feedback. 
     With such a structure, when the control signal S 18  is put into “L” (low level), current value of the constant current source  40   a ,  40   b  is kept to a constant value. On the other hand, when the control signal S 18  is put into “HH” (high level), the output of the local oscillator  13  selected by the switch  32  is given thereto. Thereby, the current control portion  27  is put into an on-state. Consequently, the feedback becomes active. 
     In this event, a signal V A  is removed amplitude modulation components thereof by the limiter amplifier  19 , and is converted into signals V B  and V C . The signals V B  and V C  are given with desired slopes corresponding to current values determined by constant current sources  40   a  and  40   b , and are converted into signals V D  and V E . 
     Further, the signals V D  and V E  are converted into signals V F  and V G  by comparators  23   a  and  23   b . In this event, each of the comparators are given with threshold level V TH26 . 
     Further, logic product (negative logic product) is carried out for the signals V F  and V G  through an AND gate  24 . Thereby, pulse signal line V H  is generated, as illustrated in FIG.  11 . 
     In the pulse signal line V H , amplitude and delay time τ are constantly kept. This signal line V H  is integrated by a LPF  25 , and is converted into voltage value V I  corresponding to the frequency of the signal V A . 
     In this case, the voltage value V I  is compared with the reference voltage V REF . As the result of the comparison, when the voltage value V I  is higher than the reference voltage V REF , the current control portion  27  controls so as to increase current value of the constant current source  40   a ,  40   b.    
     On the other hand, when the voltage value V I  is lower that the reference voltage V REF , the current control portion  27  controls so as to reduce the current value of the constant current source  40   a ,  40   b.    
     More specifically, when the control signal S 18  is put into “H” (namely, the feedback is in an active state), the delay time τ is adjusted. Further, the F-V converted voltage value V I  is converged into the reference voltage V REF . On the other hand, when the control signal S 18  is put into “L”, normal receiving state appears. 
     Therefore, the control signal S 18  is put into “H” so as to perform the feedback during signal receiving wait state or during signal receiving state unnecessary to receive a signal. 
     The delay time τ is inversely proportional to variation of the current value of the constant current source  40   a ,  40   b , and is proportional to static capacitance of the capacitor  22   a ,  22   b . Further, the delay time τ is proportional to the threshold level V TH26  given to the comparator  23   a ,  23   b.    
     In this embodiment, when the voltage value V I  is higher than the reference voltage V ERF , the delay time τ is becomes larger than a value to be essential. In such a case, the current control portion  27  controls so as to increase the current value of the constant current source  40   a ,  40   b . Thereby, the voltage value V I  becomes low, and the voltage value V I  finally converges into V REF . 
     On the other hand, when the voltage value V I  is lower than the reference voltage V ERF , the delay time τ is becomes lower than the value to be essential. In this case, the current control portion  27  controls so as to reduce the current value of the constant current source  40   a ,  40   b . Thereby, the voltage value V I  becomes large, and the voltage value V I  finally converges into V REF . 
     Herein, it is to be noted that the voltage value V I  is a voltage which corresponds to center frequency of the second FSK signal. Therefore, the voltage corresponding to the center frequency is made to be compatible with the referential voltage V REF . Thereby, variation of demodulation sensibility is substantially eliminated. Further, the F-V conversion characteristic is corrected as the straight line B illustrated in FIG.  9 . 
     When the control signal S 18  is put into “L” and is in the normal receiving state, the reference voltage V REF  is used as the reference voltage of a comparator or a A/D converter which is supplied with the voltage value V I , and thereby, accurately corresponds to the center frequency of the second FSK signal.

Technology Classification (CPC): 7