Patent Abstract:
A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.

Full Description:
BACKGROUND  
       [0001]     The present disclosure relates generally to integrated circuit (IC) designs, and more specifically to a layout design of six-transistor (6T) static random access memory (SRAM) cell.  
         [0002]     A standard 6T SRAM cell has six transistors formed on a bulk semiconductor substrate. Among the six transistors, four are N-channel devices (NMOS transistors) categorized according to their functions as two pull-down transistors and two pass-gate transistors. The remaining two transistors are P-channel devices (PMOS transistors) functioning as pull-up transistors.  
         [0003]     Conventionally, the pull-down transistor is located next to the pass-gate transistor, wherein an N-type doped region is implemented as the drains and the sources for both transistors. The pull-down transistors are required to withstand a high level of current, and are therefore designed to be large in physical size. Compared to the pull-down transistors, the pass-gate transistors are designed to be much smaller in physical size as they are not required to withstand such high level current. Thus, the doped regions of the pull-down transistors can be much wider than those of their adjacent pass-gate transistors. Due to the mismatched sizes of the pull-down transistor and the pass-gate transistor, the conventional SRAM cell is particularly susceptible to reliability defects caused by deviation of fabrication process.  
         [0004]     Desirable in the art of IC designs are additional designs that can eliminate the width mismatch issue while reducing the overall size of the 6T SRAM cell.  
       SUMMARY  
       [0005]     The present invention discloses a 6T SRAM cell. In one embodiment, the cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.  
         [0006]     The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  schematically illustrates a standard 6T SRAM cell.  
         [0008]      FIG. 2  illustrates a conventional layout design for the 6T SRAM cell shown in  FIG. 1 .  
         [0009]      FIG. 3  illustrates a layout design for the standard 6T SRAM cell in accordance with one embodiment of the present invention.  
     
    
     DESCRIPTION  
       [0010]      FIG. 1  schematically illustrates a standard 6T SRAM cell  100 , which includes a first inverter  102 , a second inverter  104  and two pass-gate transistors: a first pass-gate transistor  106  and a second pass-gate transistor  108  (both pass-gate transistors are NMOS transistors). The first inverter  102  includes a first pull-up transistor  110  (PMOS transistor) and a first pull-down transistor  112  (NMOS transistor) while the second inverter  104  includes a second pull-up transistor  114  (PMOS) and a second pull-down transistor  116  (NMOS transistor). The gates of the first pull-up transistor  110  and the first pull-down transistor  112  are coupled together at a node  118  along with the drains of the second pull-up transistor  114  and the second pull-down transistor  116 . The drains of the first pull-up transistor  110  and the first pull-down transistor  112  are also coupled together at a node  120  along with the gates of the second pull-up transistor  114  and the second pull-down transistor  116 . The sources of the first pull-up transistor  110  and the second pull-up transistor  114  are coupled to the supply source VCC, while the sources of the first pull-down transistor  112  and the second pull-down transistor  116  are coupled to the complementary supply source VSS. As for the first pass-gate transistor  106 , the gate is coupled to a wordline (WL), the source is coupled to a bitline (BL), and the drain is coupled to the node  120 . The second pass-gate transistor  108  is set up in a similar configuration where the gate is also coupled to a wordline (WL), the source is coupled to a bitline bar (BLB), and the drain is coupled to the node  118 .  
         [0011]     During read or write operations of the device, both the first pass-gate transistor  106  and the second pass-gate transistor  108  are designed to be selected or turned on by the signals on the wordlines (WL). The bitline BL or bitline bar BLB will charge up to provide enough current to program or read the SRAM cell  100 .  
         [0012]      FIG. 2  illustrates a conventional layout design  200  for the standard 6T SRAM cell shown in  FIG. 1 . Referring to  FIGS. 1 and 2  simultaneously, since the two sides of the standard 6T SRAM cell  100  are identical, only one side of the layout design that includes the second pass-gate transistor  108 , the second pull-up transistor  114 , and the second pull-down transistor  116  will be described in detail. The second pass-gate transistor  108  and the second pull-down transistor  116  are constructed on a P-type well  202 . An elongated N-type doped region  204  formed on the P-type well  202  is implemented as the drains and the sources of the second pass-gate transistor  108  and the second pull-down transistor  116 . An elongated gate structure  206  is placed above the N-type doped region  204  to form the gate of the second pass-gate transistor  108 , while another elongated gate structure  208  is placed above the N-type doped region  204  to form the gate of the second pull-down transistor  116 . A separate elongated P-type doped region  210  is formed under the gate structure  208  on an N-type well  212  to form the drain and the source of the second pull-up transistor  114 . The elongated gate structure  208  overlies the P-type doped region  210  to form the gate of the second pull-up transistor  114 .  
         [0013]     This conventional layout design presents several reliability issues. Both the first and the second pull-down transistors  112  and  116  are required to withstand a high level of current and are designed to be large in physical size, while both the first and the second pass-gate transistors  106  and  108  are designed to be much smaller in physical size. This means that the elongated N-type doped region  204  for the first and the second pull-down transistors  112  and  116  will be much wider than the width of the same for the first and the second pass-gate transistors  106  and  108 . Due to the deviation of fabrication process, it is possible that the location of the elongated gate structure  208  would shift to an intermediate area  205  between the wider portion of the N-type doped region  204  and the narrower portion of the same. This mismatch between the wider and narrower portions of the N-type doped region  204  would change the channel length of the shifted gate structure  208 , thereby causing reliability issues.  
         [0014]     The following will provide a detailed description of a layout design for a 6T SRAM cell constructed on a silicon-on-insulator (SOI) substrate by swapping the locations of the pull-up transistor and the pull-down transistor in accordance with one embodiment of the present invention. It is noted that while the proposed SRAM cell is constructed on the SOI substrate, the bulk-substrate may also be used as an alternative of the invention.  
         [0015]      FIG. 3  illustrates a proposed layout design  300  for a 6T SRAM cell corresponding to the circuit diagram shown in  FIG. 1 , in accordance with one embodiment of the present invention. The locations of the pull-up transistors and the pull-down transistors within the layout design are swapped compared to the conventional layout design shown in  FIG. 2 . Referring simultaneously to  FIGS. 1 and 3 , since the two sides of the 6T SRAM cell  100  are identical, only one side of the layout design shown in a block  302 , including the second pass-gate transistor  108 , the second pull-up transistor  114 , and the second pull-down transistor  116 , will be described in detail.  
         [0016]     The first and the second pull-up transistors  110  and  114  are not required to withstand a high level of current, and therefore they can be designed much smaller in physical size than the first and the second pull-down transistors  112  and  116 . In order to reduce the width mismatch issue between the pull-down transistors and the pass-gate transistors, the locations of the pull-up transistors and the pull-down transistors within this layout design  300  are swapped compared with the conventional layout design. Since the second pull-up transistor  114  is a PMOS transistor, it is formed on an N-type well  304  that is placed right next to a P-type well  306 , on which the second pass-gate transistor is constructed. Similarly, the first pull-up transistor  110  is formed on a separated N-type well placed right next to a P-type well, on which the first pass-gate transistor  106  is constructed. The second pull-down transistor  116  and the second pass-gate transistor  108  are formed on the P-type well  306 . An elongated P-type doped region  308  is disposed to form the drain and source of the second pull-up transistor  114  (a similar elongated P-type doped region is disposed to form the drain and source of the first pull-up transistor  110 ). An elongated N-type doped region  310  is disposed to form the drain and source of the second pass-gate transistor  108  (similar elongated N-type doped region is used to form the drain and the source of the first pass-gate transistor  106 ). Since the materials used to form the second pull-up transistor  114  and the second pass-gate transistor  108  are doped with different types of impurities, a soft contact  312  that has a P-type portion and N-type portion is implemented at the junction of the two elongated doped regions  308  and  310 . An elongated gate structure  314  is placed above the N-type doped region  310  to form the gate of the second pass-gate transistor  108 , while an elongated gate structure  316  is placed above the P-type doped region  308  to form the gate of the second pull-up transistor  114 . An elongated N-type doped region  318  is implemented on the P-well  306  to form the drain and the source of the second pull-down transistor  116 . The elongated gate structure  316  also extends above the elongated N-type doped region  318  to form the gate of the pull-down transistor  116 . Note that the soft contact  312  is coupled to a contact  320  through metal interconnects (not shown in this figure), that is implemented at the elongated N-type doped region  318  to provide a connection between the drain of the second pull-down transistor  116  and the node  118  shown in  FIG. 1 .  
         [0017]     With this proposed layout design, the width mismatch issue is avoided where the width of the P-type doped region  308  for the pull-up transistor  114  and the width of the N-type doped region  310  for the pass-gate transistor remain the same. There is no intermediate area of a different width between these two doped regions. Thus, the SRAM cell fabricated based on the layout out design  300  is less susceptible to reliability issues, when the location of the gate structure shifts due to deviation of fabrication process. The widths of the first and the second pull-down transistors  112  and  116  can be increased independently to increase the beta-ratio (I DSAT  of the pull-down transistor to I DSAT  of the pass-gate transistor) while the widths of the first and the second pass-gate transistors  106  and  108  and the first and the second pull-up transistors  110  and  114  can also be increased together to lower the alpha-ratio (I DSAT  of the pull-up transistor to I DSAT  of the pass-gate transistor).  
         [0018]     The substrate may be silicon, gallium arsenide, gallium nitride, strained silicon, silicon germanium, silicon carbide, carbide, diamond, and/or other materials, preferably silicon-on-insulator (SOI) substrate, such as a silicon-on-sapphire substrate, a silicon germanium-on-insulator substrate, or another substrate comprising an epitaxial semiconductor layer on an insulation layer. In this embodiment, all of the transistors are constructed on an SOI substrate, so that the various wells can be disposed next to each other without having an isolation structure interposed therebetween.  
         [0019]     Table I compares test data of threshold voltage and off-state source current for the pass-gate transistors, the pull-down transistors, and the pull-up transistors within the two different standard 6T SRAM cells created based on the proposed layout design shown in  FIG. 3  and the conventional layout design shown in  FIG. 2 . For all three transistors, the threshold voltage (Vt) is increased by using the proposed layout design shown in  FIG. 3 . For example, the threshold voltage of the pass-gate transistor is increased by 42.8 mV. The off-state source current (I soff ) for the pass-gate transistor and the pull-down transistor are also reduced by at least 50%, thereby demonstrating a significant decrease in sub-threshold leakage. For example, the off-state source current for the pass-gate transistor is reduced by 58.8%.  
                           TABLE I                               STI           UHD SRAM Devices   STD layout 200   layout 300   Delta                   PG 0.12/0.115 Vt_gm (V)   0.3787 V   0.4215 V   42.8 mV       PG 0.12/0.115 I soff  (μA/ea)   34   14   −58.8%       PD 0.18/0.1 Vt_gm (V)   0.4639 V   0.4874 V   23.5 mV       PD 0.18/0.1 I soff  (μA/ea)   45   21   −53.3%       PU 0.11/0.11 Vt_gm (V)   −0.2984 V     −0.3176 V     19.2 mV       PU 0.11/0.11 I soff  (μA/ea)   −153      −93     −39.2%                  
 
         [0020]     The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0021]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.

Technology Classification (CPC): 8