Patent Abstract:
A wireless transmit receive unit (WTRU) recovers data from a plurality of data signals received as a received vector. The WTRU determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The WTRU comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/172,113, filed on Jun. 14, 2002, which is a continuation-in-part of patent application Ser. No. 10/083,189, filed on Feb. 26, 2002, which claims priority from U.S. Provisional Patent Application No. 60/332,950, filed on Nov. 14, 2001. 

   BACKGROUND 
   This invention generally relates to solving linear systems. In particular, the invention relates to using array processing to solve linear systems. 
   Linear system solutions are used to solve many engineering issues. One such issue is joint user detection of multiple user signals in a time division duplex (TDD) communication system using code division multiple access (CDMA). In such a system, multiple users send multiple communication bursts simultaneously in a same fixed duration time interval (timeslot). The multiple bursts are transmitted using different spreading codes. During transmission, each burst experiences a channel response. One approach to recover data from the transmitted bursts is joint detection, where all users data is received simultaneously. Such a system is shown in  FIG. 1 . The joint detection receiver may be used in a user equipment or base station. 
   The multiple bursts  90 , after experiencing their channel response, are received as a combined received signal at an antenna  92  or antenna array. The received signal is reduced to baseband, such as by a demodulator  94 , and sampled at a chip rate of the codes or a multiple of a chip rate of the codes, such as by an analog to digital converter (ADC)  96  or multiple ADCs, to produce a received vector,  r . A channel estimation device  98  uses a training sequence portion of the communication bursts to estimate the channel response of the bursts  90 . A joint detection device  100  uses the estimated or known spreading codes of the users&#39; bursts and the estimated or known channel responses to estimate the originally transmitted data for all the users as a data vector,  d . 
   The joint detection problem is typically modeled by Equation 1.
 
 A d +n= r     Equation 1
 
 d  is the transmitted data vector;  r  is the received vector;  n   is the additive white gaussian noise (AWGN); and A is an M×N matrix constructed by convolving the channel responses with the known spreading codes.
 
   Two approaches to solve Equation 1 is a zero forcing (ZF) and a minimum mean square error (MMSE) approach. A ZF solution, where n is approximated to zero, is per Equation 2.
 
   d   =( A   H   A ) −1   A   H     r     Equation 2
 
A MMSE approach is per Equations 3 and 4.
 
   d =R   −1   A   H   r   Equation 3
 
 R=A   H   A+σ   2   I   Equation 4
 
σ 2  is the variance of the noise, n, and I is the identity matrix.
 
   Since the spreading codes, channel responses and average of the noise variance are estimated or known and the received vector is known, the only unknown variable is the data vector,  d . A brute force type solution, such as a direct matrix inversion, to either approach is extremely complex. One technique to reduce the complexity is Cholesky decomposition. The Cholesky algorithm factors a symmetric positive definite matrix, such as Ã or R, into a lower triangular matrix G and an upper triangular matrix G H  by Equation 5.
 
{tilde over ( A )} or  R=GG   H   Equation 5
 
A symmetric positive definite matrix, Ã, can be created from A by multiplying A by its conjugate transpose (hermetian), A H , per Equation 6.
 
 Ã=A   H   A   Equation 6
 
For shorthand, {tilde over (r)} is defined per Equation 7.
 
 {tilde over (r)}=A   H     r     Equation 7
 
As a result, Equation 1 is rewritten as Equations 8 for ZF or 9 for MMSE.
 
 Ã d ={tilde over (r)}   Equation 8
 
 R d ={tilde over (r)}   Equation 9
 
To solve either Equation 8 or 9, the Cholesky factor is used per Equation 10.
 
 GG   H     d ={tilde over (r)}   Equation 10
 
A variable y is defined as per Equation 11.
 
 G   H   d=y   Equation 11
 
Using variable y, Equation 10 is rewritten as Equation 12.
 
 Gy={tilde over (r)}   Equation 12
 
The bulk of complexity for obtaining the data vector is performed in three steps. In the first step, G is created from the derived symmetric positive definite matrix, such as Ã or R, as illustrated by Equation 13.
 
 G =CHOLESKY ( Ã or  R )  Equation 13
 
Using G, y is solved using forward substitution of G in Equation 8, as illustrated by Equation 14.
 
 y =FORWARD SUB( G,{tilde over (r)} )  Equation 14
 
Using the conjugate transpose of G, G H ,  d  is solved using backward substitution in Equation 11, as illustrated by Equation 15.
 
 d =BACKWARD SUB( G   H   ,y )  Equation 15
 
An approach to determine the Cholesky factor, G, per Equation 13 is the following algorithm, as shown for Ã or R, although an analogous approach is used for R.
 
                                                                                   for i = 1 : N                for j = max(1, i − P) : i − 1                λ = min(j + P, N)           a i : λ, i  = a i : λ, i  − a i, j * · a i:λ,j ;                end for;           λ = min(i + P, N)           a i : λ, i  = a i : λ, i /a ii ;                end for;           G = Ã or R;                        
a d,e  denotes the element in matrix Ã or R at row d, column e. “:” indicates a “to” operator, such as “from j to N,” and (·) H  indicates a conjugate transpose (hermetian) operator.
 
   Another approach to solve for the Cholesky factor uses N parallel vector-based processors. Each processor is mapped to a column of the Ã or R matrix. Each processor&#39;s column is defined by a variable μ, where μ=1:N. The parallel processor based subroutine can be viewed as the following subroutine for μ=1:N. 
                                                                                                       j = 1           while j &lt; μ                recv(g j:N ,left)           if μ &lt; N                send(g j:N ,right)                end           a μ:N,μ  = a μ:N,μ  − g μ *g μ:N             j = j + 1                end           a μ:N,μ  = a μ:N,μ /{square root over (a μμ )}           if μ &lt; N                send(a μ:N,μ ,right)                end                        
recv(·,left) is a receive from the left processor operator; send(·,right) is a send to the right processor operator; and g K,L  is a value from a neighboring processor.
 
   This subroutine is illustrated using  FIGS. 2   a - 2   h .  FIG. 2   a  is a block diagram of the vector processors and associated memory cells of the joint detection device. Each processor  50   1  to  50   N  ( 50 ) operates on a column of the matrix. Since the G matrix is lower triangular and Ã or R is completely defined by is lower triangular portion, only the lower triangular elements, a k,1  are used. 
     FIGS. 2   b  and  2   c  show two possible functions performed by the processors on the cells below them. In  FIG. 2   b , the pointed down triangle function  52  performs Equations 16 and 17 on the cells (a □□  to a N□ ) below that μ processor  50 .
 v←a μ:N,μ /√{square root over (a μμ )}  Equation 16 a μ:N,μ :=v  Equation 17 
“←” indicates a concurrent assignment; “:=” indicates a sequential assignment; and v is a value sent to the right processor.
 
   In  FIG. 2   c , the pointed right triangle function  52  performs Equations 18 and 19 on the cells below that μ processor  50 .
 
v←μ  Equation 18
 
 a   μ:N,μ   :=a   μ:N,μ   −v   μ   v   μ:N   Equation 19
 
v k  indicates a value associated with a right value of the k th  processor  50 .
 
     FIGS. 2   d - 2   g  illustrate the data flow and functions performed for a 4×4 G matrix. As shown in the  FIGS. 2   d - 2   g  for each stage  1  through  4  of processing, the left most processor  50  drops out and the pointed down triangular function  52  moves left to right. To implement  FIGS. 2   d - 2   g , the pointed down triangle can physically replace the processor to the right or virtually replace the processor to the right by taking on the function of the pointed down triangle. 
   These elements are extendable to an N×N matrix and N processors  50  by adding processors  50  (N−4 in number) to the right of the fourth processor  50   4  and by adding cells of the bottom matrix diagonal (N−4 in number) to each of the processors  50  as shown in  FIG. 2   h  for stage  1 . The processing in such an arrangement occurs over N stages. 
   The implementation of such a Cholesky decomposition using either vector processors or a direct decomposition into scalar processors is inefficient, because large amounts of processing resources go idle after each stage of processing. 
   Accordingly, it is desirable to have alternate approaches to solve linear systems. 
   SUMMARY 
   A user equipment or base station, generically referred to as a wireless transmit receive unit (WTRU), recovers data from a plurality of data signals received as a received vector. The user equipment determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The WTRU comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector. 

   
     BRIEF DESCRIPTION OF THE DRAWING(S) 
       FIG. 1  is a simplified diagram of a joint detection receiver. 
       FIGS. 2   a - 2   h  are diagrams illustrating determining a Cholesky factor using vector processors. 
       FIGS. 3   a  and  3   b  are preferred embodiments of N scalar processors performing Cholesky decomposition. 
       FIGS. 4   a - 4   e  are diagrams illustrating an example of using a three dimensional graph for Cholesky decomposition. 
       FIGS. 5   a - 5   e  are diagrams illustrating an example of mapping vector processors performing Cholesky decomposition onto scalar processors. 
       FIGS. 6   a - 6   j  for a non-banded and  FIGS. 6   e - 6   j  for a banded matrix are diagrams illustrating the processing flow of the scalar array. 
       FIG. 7  is a diagram extending a projection of  FIG. 4   a  along the k axis to an N×N matrix. 
       FIGS. 8   a - 8   d  are diagrams illustrating the processing flow using delays between the scalar processors in the 2D scalar array. 
       FIG. 8   e  is a diagram of a delay element and its associated equation. 
       FIG. 9   a  illustrates projecting the scalar processor array of  FIGS. 8   a - 8   d  onto a 1D array of four scalar processors. 
       FIG. 9   b  illustrates projecting a scalar processing array having delays between every other processor onto a 1D array of four scalar processors. 
       FIGS. 9   c - 9   n  are diagrams illustrating the processing flow for Cholesky decomposition of a banded matrix having delays between every other processor. 
       FIGS. 9   o - 9   z  illustrate the memory access for a linear array processing a banded matrix. 
       FIGS. 10   a  and  10   b  are the projected arrays of  FIGS. 9   a  and  9   b  extended to N scalar processors. 
       FIGS. 11   a  and  11   b  illustrate separating a divide/square root function from the arrays of  FIGS. 10   a  and  10   b.    
       FIG. 12   a  is an illustration of projecting a forward substitution array having delays between each processor onto four scalar processors. 
       FIG. 12   b  is an illustration of projecting a forward substitution array having delays between every other processor onto four scalar processors. 
       FIGS. 12   c  and  12   d  are diagrams showing the equations performed by a star and diamond function for forward substitution. 
       FIG. 12   e  is a diagram illustrating the processing flow for a forward substitution of a banded matrix having concurrent assignments between every other processor. 
       FIGS. 12   f - 12   j  are diagrams illustrating the processing flow for forward substitution of a banded matrix having delays between every other processor. 
       FIGS. 12   k - 12   p  are diagrams illustrating the memory access for a forward substitution linear array processing a banded matrix. 
       FIGS. 13   a  and  13   b  are the projected arrays of  FIGS. 12   a  and  12   b  extended to N scalar processors. 
       FIGS. 14   a - 14   d  are diagrams illustrating the processing flow of the projected array of  FIG. 12   b.    
       FIG. 15   a  is an illustration of projecting a backward substitution array having delays between each processor onto four scalar processors. 
       FIG. 15   b  is an illustration of projecting a backward substitution array having delays between every other processor onto four scalar processors. 
       FIGS. 15   c  and  15   d  are diagrams showing the equations performed by a star and diamond function for backward substitution. 
       FIG. 15   e  is a diagram illustrating the processing flow for backward substitution of a banded matrix having concurrent assignments between every other processor. 
       FIGS. 15   f - 15   j  are diagrams illustrating the processing flow for backward substitution of a banded matrix having delays between every other processor. 
       FIGS. 15   k - 15   p  are diagrams illustrating the memory access for a backward substitution linear array processing a banded matrix. 
       FIGS. 16   a  and  16   b  are the projected arrays of  FIGS. 15   a  and  15   b  extended to N scalar processors. 
       FIGS. 17   a - 17   d  are diagrams illustrating the processing flow of the projected array of  FIG. 15   b.    
       FIGS. 18   a  and  18   b  are the arrays of  FIGS. 13   a ,  13   b ,  16   a  and  16   b  with the division function separated. 
       FIGS. 19   a  and  19   b  are diagrams of a reconfigurable array for determining G, forward and backward substitution. 
       FIGS. 20   a  and  20   b  are illustrations of breaking out the divide and square root function from the reconfigurable array. 
       FIG. 21   a  illustrates bi-directional folding. 
       FIG. 21   b  illustrates one directional folding. 
       FIG. 22   a  is an implementation of bi-directional folding using N processors. 
       FIG. 22   b  is an implementation of one direction folding using N processors. 
       FIG. 23  is a preferred slice of a simple reconfigurable processing element. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 3   a  and  3   b  are preferred embodiments of N scalar processors  54   1  to  54   N  ( 54 ) performing Cholesky decomposition to obtain G. For simplicity, the explanation and description is explained for a 4×4 G matrix, although this approach is extendable to any N×N G matrix as shown in  FIGS. 3   a  and  3   b.    
     FIG. 4   a  illustrates a three-dimensional computational dependency graph for performing the previous algorithms. For simplicity,  FIG. 4   a  illustrates processing a 5 by 5 matrix with a bandwidth of 3. The functions performed by each node are shown in  FIGS. 4   b - 4   e . The pentagon function of  FIG. 4   b  performs Equations 20 and 21.
 y←√{square root over (a in )}  Equation 20 a out ←y  Equation 21 
← indicate a concurrent assignment. a in  is input to the node from a lower level and a out  is output to a higher level.  FIG. 4   c  is a square function performing Equations 22 and 23.
 y←z*  Equation 22 a out ←a in −|z| 2   Equation 23   FIG. 4   d  is an octagon function performing Equations 24, 25 and 26.
 y←w  Equation 24 x←a in /w  Equation 25 a out ←x  Equation 26   FIG. 4   e  is a circle function performing Equations 27, 28 and 29.
 y←w  Equation 27 x←z  Equation 28 a out ←a in −w*z  Equation 29 
     FIG. 5   a  is a diagram showing the mapping of the first stage of a vector based Cholesky decomposition for a 4×4 G matrix to the first stage of a two dimensional scalar based approach. Each vector processor  52 ,  54  is mapped onto at least one scalar processor  56 ,  58 ,  60 ,  62  as shown in  FIG. 5   a . Each scalar processor  56 ,  58 ,  60 ,  62  is associated with a memory cell, a ij . The function to be performed by each processor  56 ,  58 ,  60 ,  62  is shown in  FIGS. 5   b - 5   e .  FIG. 5   b  illustrates a pentagon function  56 , which performs Equations 30 and 31.
 y←√{square root over (a ij )}  Equation 30 a ij :=y  Equation 31 
:=indicates a sequential assignment. y indicates a value sent to a lower processor.  FIG. 5   c  illustrates an octagonal function  58 , which performs Equations 32, 33 and 34.
 y←w  Equation 32 x←a ij /w  Equation 33 a ij :=x  Equation 34 
w indicates a value sent from an upper processor.  FIG. 5   d  illustrates a square function  60 , which performs Equations 35 and 36.
 y←z*  Equation 35   a   ij   :=a   ij   −|z|   2   Equation 36 
x indicates a value sent to a right processor.  FIG. 5   e  illustrates a circular function  62 , which performs Equations 37, 38 and 39.
 y←w  Equation 37 x←z  Equation 38   a   ij   :=a   ij   −w*z   Equation 39   FIGS. 6   a - 6   d  illustrate the data flow through the scalar processors  56 ,  58 ,  60 ,  62  in four sequential stages (stages  1  to  4 ). As shown in  FIGS. 6   a - 6   d , a column of processors  56 ,  58  drops off after each stage. The process requires four processing cycles or N in general. One processing cycle for each stage. As shown in  FIG. 5   a , ten (10) scalar processors are required to determine a 4×4 G matrix. For an N×N matrix, the number of processors required is per Equation 40.
 
   
     
       
         
           
             
               
                 
                   
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                 Equation 
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                 40 
               
             
           
         
       
     
   
     FIGS. 6   e - 6   j  illustrate the processing flow for a banded 5 by 5 matrix. Active processors are unhatched. The banded matrix has the lower left three entries (a 41 , a 51 , a 52 , not shown in  FIGS. 6   e - 6   j ) as zeros. As shown in  FIG. 6   e , in a first stage, the upper six processors are operating. As shown in  FIG. 6   f , the six active processors of stage  1  have determined g 11 , g 21  and g 31  and three intermediate results, α 22 , α 32  and α 33  for use in stage  2 . 
   In stage  2 , six processors (α 22 , α 32 , α 33 , ã 42 , ã 43 , ã 44 ) are operating. As shown in  FIG. 6   g  (stage  3 ), values for g 22 , g 32  and g 42  and intermediate values for β 33 , β 43 , β 44  have been determined in stage  2 . In  FIG. 6   h  (stage  4 ), values for g 33 , g 43  and g 53  and intermediate values for γ 44 , γ 54  and γ 55  have been determined. In  FIG. 6  (stage  5 ), g 44  and g 54  and intermediate value δ 55  have been determined. In  FIG. 6   j  (final stage), the remaining value g 55  is available. As shown in the figures, due to the banded nature of the matrix, the lower left processors of an unloaded matrix are unnecessary and not shown. 
   The simplified illustrations of  FIGS. 6   a - 6   d  are expandable to an N×N matrix as shown in  FIG. 7 . As shown in that figure, the top most processor  56  performs a pentagon function. Octagon function processors  58  extend down the first column and dual purpose square/pentagon processors  64  along the main diagonal, as shown by the two combined shapes. The rest of the processors  66  are dual purpose octagonal/circle processors  66 , as shown by the two combined shapes. This configuration determines an N×N G matrix in N processing cycles using only scalar processors. 
   If the bandwidth of the matrix has a limited width, such as P, the number of processing elements can be reduced. To illustrate, if P equals N−1, the lower left processor for a N1  drops off. If P equals N-2, two more processors (a N-11  and a N2 ) drop off. 
   Reducing the number of scalar processing elements further is explained in conjunction with  FIGS. 8   a - 8   e  and  9   a  and  9   b .  FIGS. 8   a - 8   e  describe one dimensional execution planes of a four (4) scalar processor implementation of  FIGS. 6   a - 6   d . A delay element  68  of  FIG. 8   e  is inserted between each concurrent connection as shown in  FIG. 8   a . The delay element  68  of  FIG. 8   e  delays the input y to be a sequential output x, per Equation 41.
 
y:=x  Equation 41
 
For each processing cycle starting at t 1 , the processors sequentially process as shown by the diagonal lines showing the planes of execution. To illustrate, at time t 1 , only processor  56  of a 11  operates. At t 2 , only processor  58  of a 21  operates and at t 3 , processors  58 ,  60  of a 31  and a 22  operate and so on until stage  4 , t 16 , where only processor  56  of a 44  operates. As a result, the overall processing requires N 2  clock cycles across N stages.
 
   Multiple matrices can be pipelined through the two dimensional scalar processing array. As shown in  FIGS. 8   a - 8   d , at a particular plane of execution, t 1  to t 16 , are active. For a given stage, up to a number of matrices equal to the number of planes of execution can be processed at the same time. To illustrate for stage  1 , a first matrix is processed along diagonal t 1 . For a next clock cycle, the first matrix passes to plane t 2  and plane t 1  is used for a second matrix. The pipelining can continue for any number of matrices. One drawback to pipelining is pipelining requires that the data for all the matrices be stored, unless the schedule of the availability of the matrix data is such that it does not stall. 
   After a group of matrices have been pipelined through stage  1 , the group is pipelined through stage  2  and so forth until stage N. Using pipelining, the throughput of the array can be dramatically increased as well as processor utilization. 
   Since all the processors  56 ,  58 ,  60 ,  62  are not used during each clock cycle, when processing only 1 matrix, the number of processing elements  56 ,  58 ,  60 ,  62  can be reduced by sharing them across the planes of execution.  FIGS. 9   a  and  9   b  illustrate two preferred implementations to reduce processing elements. As shown in  FIG. 9   a , a line perpendicular to the planes of execution (along the matrix diagonals) is shown for each processing element  56 ,  58  of the first column. Since all of the processors  56 ,  58 ,  60 ,  62  along each perpendicular operate in different processing cycles, their functions  56 ,  58 ,  60 ,  62  can be performed by a single processor  66 ,  64  as projected below. Processing functions  56  and  60  are performed by a new combined function  64 . Processing functions  58  and  62  are performed by a new combined function  66 . The delay elements  68  and connections between the processors are also projected. Although the left most processing element is shown as using a dual function element  66 , that element can be simplified to only perform the octagonal function  58 , if convenient for a non-banded matrix. 
     FIG. 10   a  is an expansion of  FIG. 9   a  to accommodate an N×N G matrix. As shown in  FIG. 10   a , N processors  66 ,  64  are used to process the N×N G matrix. As shown in  FIG. 3   a , the processing functions of  FIG. 10   a  can be performed by N scalar processors  54 . The same number of scalar processors as the bandwidth, P, can be used to process the G matrix in the banded case. 
   In the implementation of  FIG. 3   a , each processor is used in every other clock cycle. The even processors operate in one cycle and the odd in the next. To illustrate, processor  2  (second from the right) of  FIG. 9   a  processes at times t 2 , t 4  and t 6  and processor  3  at t 3  and t 5 . As a result, two G matrices can be determined by the processing array at the same time by interlacing them as inputs to the array. This approach greatly increases the processor utilization over the implementation of  FIG. 7 . 
   To reduce the processing time of a single array, the implementation of  FIG. 9   b  is used. The delay elements between every other processor connection is removed, as shown in  FIG. 9   b . At time t 1 , only processor  56  of a 11  operates. However, at t 2 , processors  58 ,  60  at a 21 , a 22  and a 31  are all operating. Projecting this array along the perpendicular (along the diagonals of the original matrix) is also shown in  FIG. 9   b . As shown, the number of delay elements  68  is cut in half. Using this array, the processing time for an N×N G matrix is cell (NP−(P 2 −P)/2). Accordingly, the processing time for a single G matrix is greatly reduced. 
   Another advantage to the implementations of  FIGS. 7 ,  3   a  and  3   b  is that each processing array is scalable to the matrix bandwidth. For matrices having lower bandwidths (lower diagonal elements being zero), those elements&#39; processors  58 ,  66  in  FIG. 7  drop out. With respect to  FIGS. 3   a  and  3   b , since the lower diagonal elements correspond to the left most perpendicular lines of  FIGS. 9   a  and  9   b , the processors projected by those perpendicular lines drop out. To illustrate using  FIG. 9   a , the bandwidth of the matrix has the processing elements  58 ,  62  of a 41 , a 31  and a 42  as zeros. As a result, the projection to processors  66  (left most two) are unnecessary for the processing. As a result, these implementations are scalable to the matrix bandwidth. 
     FIGS. 9   c - 9   n  illustrate the timing diagrams for each processing cycle of a banded 5 by 5 matrix having a bandwidth of 3 with delays between every other connection. At each time period, the value associated with each processor is shown. Active processors are unhatched. As shown in the figures, the processing propagates through the array from the upper left processor in  FIG. 9   c , stage  1 , time  0  (ã 11 ) to the lower right processor in  FIG. 9   n , stage  5  (δ 55 ). As shown in the figures, due to the banded nature of the matrix, the lower left processors of an unbanded matrix processing are unnecessary and not shown. 
     FIGS. 9   o - 9   z  illustrate the timing diagrams and memory access for each processing cycle of a linear array, such as per  FIG. 9   b , processing a banded 5 by 5 matrix. As shown, due to the 5 by 5 matrix having a bandwidth of 3, only three processors are needed. The figures illustrate that only three processors are required to process the banded matrix. As also shown, each stage has a relatively high processor utilization efficiency, which increases as N/p increases. 
   To reduce the complexity of the processing elements, the divide and square root function are not performed by those elements (pulled out). Divides and square roots are more complex to implement on an ASIC than adders, subtractors and multipliers. 
   The only two functions which perform a divide or a square root is the pentagon and octagon functions  56 ,  58 . For a given stage, as shown in  FIGS. 6   a - 6   d , the pentagon and octagon functions  56 ,  58  are all performed on a single column during a stage. In particular, each of these columns has a pentagon  58  on top and octagons  58  underneath. Since each octagon  58  concurrently assigns its w input to its y output, the output of the pentagon  56  flows down the entire column, without the value for w being directly stored for any a ij . The octagon  58  also uses the w input to produce the x output, which is also fed back to a ij . The x output is used by the square and circle functions  60 ,  62  in their a ij  calculations. As a result, only the value for each octagon&#39;s x output needs to be determined. The x output of the octagon is the a ij  for that octagon  58  divided by the value of the w input, which is the same for each octagon  58  and is the y output of the pentagon  56 . Accordingly, the only division/square root function that is required to be performed is calculating x for the octagon  58 . 
   Using Equations 34 and 30, each octagon&#39;s x output is that octagon&#39;s a ij  divided by the square root of the pentagon&#39;s a ij . Using a multiplier instead of a divider within each octagon processor, for a given stage, only the reciprocal of the square root of the pentagon&#39;s a ij  needs to be determined instead of the square root, isolating the divide function to just the pentagon processor and simplifying the overall complexity of the array. The reciprocal of the square root would then be stored as the a ij  of the matrix element associated with the pentagon instead of the reciprocal. This will also be convenient later during forward and backward substitution because the divide functions in those algorithms become multiples by this reciprocal value, further eliminating the need for dividers in other processing elements, i.e. the x outputs of  FIGS. 12   d  and  15   d . Since the pentagon function  56  as shown in  FIGS. 9   a  and  9   b  is performed by the same processor  64 , the processors  66 ,  64  can be implemented using a single reciprocal/square root circuit  70  having an input from the pentagon/square processor  64  and an output to that processors  64 , as shown in  FIGS. 10   a  and  10   b . The result of the reciprocal of the square root is passed through the processors  66 .  FIGS. 11   a  and  11   b  correspond to  FIGS. 10   a  and  11   b . Separating the reciprocal/square root function  70  simplifies the complexity of the other processor  66 ,  64 . Although the divide/square root circuit  70  can be implemented by using a reciprocal and a square root circuit, it is preferably implemented using a look up table, especially for a field programmable gate array (FPGA) implementation, where memory is cost efficient. 
   After the Cholesky factor, G, is determined, y is determined using forward substitution as shown in  FIGS. 12   a  and  12   b . The algorithm for forward substitution is as follows. 
             for   ⁢           ⁢   j     =     1   ⁢     :     ⁢   N                         ⁢       y   j     =       1     g   jj       ⁢     (       r   j     -       ∑     i   =   1       j   -   1       ⁢           ⁢       g   ji     ⁢     y   i           )                   end       
For a banded matrix, the algorithm is as follows.
 
                                                                                   for j = 1:N                for i = j + 1:min(j + p,N)                r i  = r i  − G ij r j ;                end for;                end for;           y = r j ;                        
g LK  is the corresponding element at row L, column K from the Cholesky matrix, G.
 
     FIGS. 12   a  and  12   b  are two implementations of forward substitution for a 4×4 G matrix using scalar processors. Two functions are performed by the processors  72 ,  74 , the star function  72  of  FIG. 12   c  and the diamond function  74  of  FIG. 12   d . The star  72  performs Equations 42 and 43.
 y←w  Equation 42 x←z−w*g ij   Equation 43 
The diamond function  74  performs Equations 44 and 45.
 x←z/g ij   Equation 44 y←x  Equation 45 
   Inserting delay elements between the concurrent connections of the processing elements as in  FIG. 12   a  and projecting the array perpendicular to its planes of execution (t 1  to t 7 ) allows the array to be projected onto a linear array. The received vector values from {tilde over (r)}, r 1 -r 4 , are loaded into the array and y 1 -y 4  output from the array. Since the diamond function  74  is only along the main diagonal, the four (4) processing element array can be expanded to process an N×N matrix using the N processing elements per  FIG. 13   a . The processing time for this array is 2 N cycles. 
   Since each processing element is used in only every other processing cycle, half of the delay elements can be removed as shown in  FIG. 12   b . This projected linear array can be expanded to any N×N matrix as shown in  FIG. 13   b . The processing time for this array is N cycles. 
   The operation per cycle of the processing elements of the projected array of  FIG. 13   b  is illustrated in  FIGS. 14   a - 14   d . In the first cycle, t 1 , of  FIG. 13   a , r 1  is loaded into the left processor  1  ( 74 ) and y 1  is determined using r 1  and g 11 . In the second cycle, t 2 , of  FIG. 14   b , r 2  and r 3  are loaded, g 31 , g 21  and g 22  are processed and y 2  is determined. In the third cycle, t 3 , of  FIG. 14   c , r 4  is loaded, g 41 , g 42 , g 32 , g 33  are loaded, and y 3  is determined. In the fourth cycle, t 4 , of  FIG. 14   d , g 43  and g 44  are processed and y 4  is determined. 
     FIGS. 12   e - 12   j  illustrate the timing diagrams for each processing cycle of a banded 5 by 5 matrix.  FIG. 12   e  shows the banded nature of the matrix having three zero entries in the lower left corner (a bandwidth of 3). 
   To show that the same processing elements can be utilized for forward as well as Cholesky decomposition,  FIG. 12   f  begins in stage  6 . Stage  6  is the stage after the last stage of  FIGS. 9   c - 9   n.    
   Similarly,  FIGS. 12   k - 12   p  illustrate the extension of the processors of  FIGS. 9   o - 9   z  to also performing forward substitution. These figures begin in stage  6 , after the 5 stages of Cholesky decomposition. The processing is performed for each processing cycle from stage  6 , time  0  ( FIG. 12   k ) to the final results ( FIG. 12   p ), after stage  6 , time  4  ( FIG. 12   o ). 
   After the y variable is determined by forward substitution, the data vector can be determined by backward substitution. Backward substitution is performed by the following subroutine. 
             for   ⁢           ⁢   j     =     N   ⁢     :     ⁢   1                         ⁢       d   j     =       1     g   jj       ⁢     (       y   j     -       ∑     i   =     j   +   1       N     ⁢           ⁢       g   ji   *     ⁢     d   i           )                   end       
For a banded matrix, the following subroutine is used.
 
                                                                                   for j = N :1                y j  = y j  /G JJ   H j;           for i = min(1, j − P): j − 1                y i  = y i  − G ij   H y j                  end for;                end for;           d = y;                        
(·)* indicates a complex conjugate function. g* LK  is the complex conjugate of the corresponding element determined for the Cholesky factor G. Y L  is the corresponding element of  y .
 
   Backward substitution is also implemented using scalar processors using the star and diamond functions  76 ,  78  as shown in  FIGS. 15   a  and  15   b  for a 4×4 processing array. However, these functions, as shown in  FIGS. 15   c  and  15   d , are performed using the complex conjugate of the G matrix values. Accordingly, Equations 42-45 become 46-49, respectively.
 
y←w  Equation 46
 
x←z−w*g ij *  Equation 47
 
x←z/g* jj *  Equation 48
 
y←x  Equation 49
 
   The delays  68  at the concurrent assignments between processors  76 ,  78 , the array of  FIG. 15   a  is projected across the planes of execution to a linear array. This array is expandable to process an N×N matrix, as shown in  FIG. 16   a . The  y vector values are loaded into the array of  FIG. 16   a  and the data vector,  d , is output. This array takes 2N clock cycles to determine  d . Since every other processor operates in every other clock cycle, two  d  s can be determined at the same time. 
   Since each processor  76 ,  78  in  16   a  operates in every other clock cycle, every other delay can be removed as shown in  FIG. 15   b . The projected array of  FIG. 15   b  is expandable to process an N×N matrix as shown in  FIG. 16   b . This array takes N clock cycles to determine  d . 
   The operations per cycle of the processing elements  76 ,  78  of the projected array of  FIG. 16   b  is illustrated in  FIGS. 17   a - 17   d . In the first cycle, t 1 , of  FIG. 17   a , y 4  is loaded, g* 44  is processed and d 4  is determined. In the second cycle, t 2 , of  FIG. 17   b , y 2  and y 3  are loaded, g* 43  and g* 33  are processed and d 3  is determined. In the third cycle, t 3 , of  FIG. 17   c , y 1  is loaded, g* 41 , g* 42 , g* 32  and g* 22  are processed and d 2  is determined. In the fourth cycle, t 4 , of  FIG. 17   d , g* 43  and g* 44  are processed and d 4  is determined. 
     FIGS. 15   e - 15   j  illustrates the extension of the processors of  FIGS. 12   e - 12   j  to performing backward substitution on a banded matrix.  FIG. 15   e  shows the banded nature of the matrix having three zero entries in the lower left corner. 
   The timing diagrams begin in stage  7 , which is after stage  6  of forward substitution. The processing begins in stage  7 , time  0  ( FIG. 15   f ) and is completed at stage  7 , time  4  ( FIG. 15   j ). After stage  7 , time  4  ( FIG. 15   j ), all of the data, d 1  to d 5 , is determined. 
   Similarly,  FIGS. 15   k - 15   p  illustrate the extension of the processors of  FIGS. 12   k - 12   p  to also performing backward substitution. These figures begin in stage  7 , after stage  6  of forward substitution. The processing is performed for each processing cycle from stage  7 , time  0  ( FIG. 15   k ) to the final results ( FIG. 15   p ). As shown in  FIGS. 9   c - 9   n ,  12   e - 12   j  and  15   e - 15   j , the number of processors in a two dimensional array can be reduced for performing Cholesky decomposition, forward and backward substitution for banded matrices. As shown by  FIGS. 9   o - 9   z ,  12   k - 12   p , the number of processors in a linear array is reduced from the dimension of matrix to the bandwidth of banded matrices. 
   To simplify the complexity of the individual processing elements  72 ,  74 ,  76 ,  78  for both forward and backward substitution, the divide function  80  can be separated from the elements  72 ,  74 ,  76 ,  78 , as shown in  FIGS. 18   a  and  18   b .  FIGS. 18   a  and  18   b  correspond to  FIGS. 16   a  and  16   b , respectively. Although the data associated with the processing elements  72 ,  74 ,  76 ,  78  for forward and backward substitution differ, the function performed by the elements  72 ,  74 ,  76 ,  78  is the same. The divider  80  is used by the right most processor  74 ,  78  to perform the division function. The divider  80  can be implemented as a look up table to determine a reciprocal value, which is used by the right most processor  74 ,  78  in a multiplication. Since during forward and backward substitution the reciprocal from Cholesky execution already exists in memory, the multiplication of the reciprocal for forward and backward substitution can utilize the reciprocal already stored in memory. 
   Since the computational data flow for all three processes (determining G, forward and backward substitution) is the same, N or the bandwidth P, all three functions can be performed on the same reconfigurable array. Each processing element  84 ,  82  of the reconfigurable array is capable of operating the functions to determine G and perform forward and backward substitution, as shown in  FIGS. 19   a  and  19   b . The right most processor  82  is capable of performing a pentagon/square and diamond function,  64 ,  74 ,  78 . The other processors  84  are capable of performing a circle/octagon and star function  66 ,  72 ,  76 . When performing Cholesky decomposition, the right most processor  82  operates using the pentagon/square function  64  and the other processors  84  operate using the circle/octagon function  66 . When performing forward and backward substitution, the right most processor  82  operates using the diamond function  74 ,  78  and the other processors  84  operate using the star function  72 ,  76 . The processors  82 ,  84  are, preferably, configurable to perform the requisite functions. Using the reconfigurable array, each processing element  82 ,  84  performs the two arithmetic functions of forward and backward substitution and the four functions for Cholesky decomposition, totaling six arithmetic functions per processing element  82 ,  84 . These functions may be performed by an arithmetic logic unit (ALU) and proper control logic or other means. 
   To simplify the complexity of the individual processing elements  82 ,  84  in the reconfigurable array, the divide and square root functionality  86  are preferably broken out from the array by a reciprocal and square root device  86 . The reciprocal and square root device  86 , preferably, determines the reciprocal to be in a multiplication, as shown in  FIGS. 20   a  and  20   b  by the right most processor  82  in forward and backward substitution and the reciprocal of the square root to be used in a multiplication using the right most processor data and passed through the processors  84 . The determination of the reciprocal and reciprocal/square root is, preferably, performed using a look up table. Alternately, the divide and square root function block  86  may be a division circuit and a square root circuit. 
   To reduce the number of processors  82 ,  84  further, folding is used.  FIGS. 21   a  and  21   b  illustrate folding. In folding, instead of using P processing elements  82 ,  84  for a linear system solution, a smaller number of processing elements, F, are used for Q folds. To illustrate, if P is nine (9) processors  82 ,  84 , three (3) processors  82 ,  84  perform the function of the nine (9) processors over three (3) folds. One drawback with folding is that the processing time of the reduced array is increased by a multiple Q. One advantage is that the efficiency of the processor utilization is typically increased. For three folds, the processing time is tripled. Accordingly, the selection of the number of folds is based on a trade off between minimizing the number of processors and the maximum processing time permitted to process the data. 
     FIG. 21   a  illustrates bi-directional folding for four processing elements  76   1 ,  76   2 ,  76   3 ,  76   4 / 78  performing the function of twelve elements over three folds of the array of  11   b . Instead of delay elements being between the processing elements  76   1 ,  76   2 ,  76   3 ,  76   4 / 78 , dual port memories  86   1 ,  86   2 ,  86   3 ,  86   4  ( 86 ) are used to store the data of each fold. Although delay elements (dual port memories  86 ) may be present for each processing element connection, such as for the implementation of  FIG. 12   a , it is illustrated for every other connection, such as for the implementation of  FIG. 12   b . Instead of dual port memories, two sets of single port memories may be used. 
   During the first fold, each processors&#39; data is stored in its associated dual port memory  86  in an address for fold  1 . Data from the matrix is also input to the processors  76   1 - 76   3 ,  76   4 / 78  from memory cells  88   1 - 88   4  ( 88 ). Since there is no wrap-around of data between fold  1  processor  76   4 / 78  and fold  3  processor  76   1 , a dual port memory  86  is not used between these processors. However, since a single address is required between the fold  1  and fold  2  processor  76   1  and between fold  2  and fold  3  processor  76   4 / 78 , a dual port memory  86  is shown as a dashed line. During the second fold, each processor&#39;s data is stored in a memory address for fold  2 . Data from the matrix is also input to the processors  76   1 - 76   3 ,  76   4 / 78  for fold  2 . Data for fold  2  processor  76   1  comes from fold  1  processor  76   1 , which is the same physical processor  76   1  so (although shown) this connection is not necessary. During the third fold, each processor&#39;s data is stored in its fold  3  memory address. Data from the matrix is also input to the processors  76   1 - 76   3 ,  76   4 / 78  for fold  3 . Data for fold  3  processor  76   4 / 78  comes from fold  2  processor  76   4 / 78  so this connection is not necessary. For the next processing stage, the procedure is repeated for fold  1 . 
     FIG. 22   a  is an implementation of bi-directional folding of  FIG. 21   a  extended to N processors  76   1 - 76   N-1 ,  76   N / 78 . The processors  76   1 - 76   N-1 ,  76   N / 78  are functionally arranged in a linear array, accessing the dual port memory  86  or two sets of single port memories. 
     FIG. 21   b  illustrates a one directional folding version of the array of  11   b . During the first fold, each processor&#39;s data is stored in its associated dual port memory address for fold  1 . Although fold  1  processor  76   4 / 78  and fold  3  processor  76   1  are physically connected, in operation no data is transferred directly between these processors. Accordingly, the memory port  86   4  between them has storage for one less address. Fold  2  processor  76   4 / 78  is effectively coupled to fold  1  processor  76   1  by the ring-like connection between the processors. Similarly, fold  3  processor  76   4 / 78  is effectively coupled to fold  2  processor  76   1 . 
     FIG. 22   b  is an implementation of one directional folding of  FIG. 20   b  extended to N processors. The processors  76   1 - 76   N-1 ,  76   N / 78  are functionally arranged in a ring around the dual memory. 
   To implement Cholesky decomposition, forward and backward substitution onto folded processors, the processor, such as the  76   4 / 78  processor, in the array must be capable of performing the functions for the processors for Cholesky decomposition, forward and backward substitution, but also for each fold. As shown in  FIGS. 20   a  and  20   b  for processor  76   4 / 78 . Depending on the implementation, the added processor&#39;s required capabilities may increase the complexity of that implementation. To implement folding using ALUs, one processor (such as 76 4 / 78  processor) performs twelve arithmetic functions (four for forward and backward substitution and eight for Cholesky) and the other processors only perform six functions. 
     FIG. 23  illustrates a slice of a preferred simple reconfigurable PE that can be used to perform all six of the functions defined in Cholesky decomposition, forward substitution, and backward substitution. This PE is for use after the divides are isolated to one of the PEs (referred to as follows as PE 1 ). Two slices are preferably used, one to generate the real x and y components, the other to generated their imaginary components. The subscripts i and r are used to indicate real and imaginary components, respectively. 
   The signals w, x, y, and z are the same as those previously defined in the PE function definitions. The signals a q  and a d  represent the current state and next state, respectively, of a PE&#39;s memory location being read and/or written in a particular cycle of the processing. The names in parentheses indicate the signals to be used for the second slice. 
   This preferred processing element can be used for any of the PEs, though it is desirable to optimize PE 1 , which performs the divide function, independently from the other PEs. Each input to the multiplexers  94   1  to  94   8  is labeled with a ‘0’ to indicate that it is used for PE 1  only, a ‘−’ to indicate that it is used for every PE except PE 1 , or a ‘+’ to indicate that it is used for all of the PEs. The isqr input is connected to zero except for the real slice of PE 1 , where it is connected to the output of a function that generates the reciprocal of the square root of the a q   r  input. Such a function could be implemented as a LUT with a ROM for a reasonable fixed-point word size. 
   As shown in  FIG. 23 , the output of multiplexers  94   1  and  94   2  are multiplied by multiplier  96   1 . The output of multiplexers  94   3  and  94   4  are multiplied by a multiplier  96   2 . The outputs of multipliers  96   1  and  96   2  is combined by an add/subtract circuit  98 . The output of the add/subtract circuit  98  is combined with the output of multiplexer  94   5  by a subtractor  99 . The output of subtractor  99  is an input to multiplexer  94   8 .

Technology Classification (CPC): 6