Patent Abstract:
A time-multiplexed common mode feedback circuit provides a common mode feedback signal during active phases of a clock signal. The common mode feed back circuit includes capacitors which are charged during the inactive phases of the clock signals. In one embodiment, the common mode feedback signal is provided by two generator circuits each driven by a respective one of two non-overlapping clock signals. In that embodiment, the generator circuits provide the common mode feedback signal during the active phases of their respective clock signals.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to differential amplifiers and bias circuits often used in conjunction with differential amplifiers. In particular, the present invention relates to providing a low-noise common mode feedback signal for adjusting common mode output voltage of a differential amplifier, and a bias current source which is immune to process variations. 
     2. Discussion of the Related Art 
     Differential amplifiers are building blocks of many analog circuits, especially analog amplifiers circuits in which high gain and high signal fidelity are required. An example of such an analog amplifier circuit can be a digital-to-analog conversion circuit suitable for use in computer graphics applications. To achieve the goals of high gain and high signal fidelity, differential amplifiers are required to have high common mode rejection, so as to provide the requisite dynamic output range. 
     Bias circuits are often used in conjunction with many applications of a differential amplifier. In an analog integrated circuit, for example, a bias circuit is often used to generate a reference current, which is then mirrored throughout the integrated circuit as a reference bias current wherever such a current is needed. However, variations in the manufacturing process of transistor current mirrors can result in significant variations in the mirrored current. For example, a 10% variation in the channel length of an MOS transistor in a current mirror can result in a more than 10% variation in the mirrored current. 
     Current sources are also extensively used with differential amplifiers. For example, a current source is frequently found in an input stage of a differential amplifier. Such a current source preferably has high noise-immunity and a high output impedance. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a feedback circuit in a differential amplifier provides a common mode feedback signal based on the common mode component of a differential output signal of the differential amplifier. The common mode output circuit includes (a) a first generator circuit providing, during an active phase of the first clock signal, a voltage approximating a common mode component of the differential signal plus a bias voltage; and (b) a second generator circuit also providing the voltage approximating the common mode component of the differential signal plus the bias voltage, but during an active phase of the a second clock signal, which is active when the first clock signal is inactive. 
     In one embodiment, the common mode feedback circuit includes, in each generator circuit, one or more capacitors which are charged during an inactive phase of the clock signal associated with the generator circuit. The charge in the capacitors provides the requisite bias voltage in the common mode feedback signal. A control circuit multiplexes each generator circuit between providing the common mode feedback signal and charging the capacitors to provide the bias voltage. The control circuit includes a number of transistor switches each controlled by an appropriate clock signal. 
     In one embodiment, in each generator circuit, the capacitors are configured such that, during the inactive phase of the clock signal associated with the generator circuit, the capacitors are coupled in parallel for charging by a current source and, during the active phase of the clock signal, the capacitors are coupled in series. In that series configuration, the differential signal is coupled across the series capacitors and a common terminal of the capacitor provides the common mode feedback signal. 
     According to another aspect of the present invention, a current source compensated for process variation includes (a) a first transistor of a first channel length receiving a reference voltage at a control terminal and generating a first current at an output terminal, and (b) a second transistor of a second channel length much longer than the channel length of the first transistor, receiving at its control terminal the reference voltage and generating at its output terminal a second current. The first and second currents are combined to provide the output current of compensated current source. Because of its much longer channel length, the second transistor is much less sensitive to channel length variations resulting from process variations. Thus, the second transistor can provide a compensating current that is insensitive to the process variations affecting the first transistor, while the first transistor can provide the high current output required. In some applications, especially in differential amplifiers, the bandwidth of a differential amplifier can be significantly enhanced by a bias current from a compensated current source of the present invention. 
     The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a  shows schematically a differential amplifier circuit  100  including a time-interleaved common mode feedback circuit  102 , in accordance with the present invention. 
     FIG. 1 b  shows schematically differential amplifier  101  of FIG. 1 a &#39;s differential amplifier circuit  100 . 
     FIG. 1 c  shows schematically CMFB circuit  102  of FIG. 1 a &#39;s differential amplifier circuit  100 , in accordance with the present invention. 
     FIG. 1 d  shows a switch  180 , which can be used to implement any of switches  142 - 147  and  152 - 157  of FIG. 1 c.    
     FIG. 2 shows an improved current source  300  with a compensating current for process variations, in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides a time-interleaved common mode feedback circuit using non-overlapping clock signals. One embodiment of the present invention in a differential amplifier  100  is shown schematically in FIG. 1 a . As shown in FIG. 1 a , a differential amplifier circuit  100  includes a differential amplifier  101 , which receives a differential signal V in  across input terminals  103   a  and  103   b  and provides a differential output signal V o  across terminals  104   a  and  104   b . A common mode feedback circuit (“CMFB circuit”)  102 , discussed in further detail below, receives differential output signal V o , and provides an output signal V fb  (terminal  105 ), which is used to diminish any common mode component of output signal V o  across terminals  104   a  and  104   b . In differential amplifier circuit  100 , CMFB circuit  102  receives non-overlapping clock signals φ 1  and φ 2  on terminals  110  and  111  respectively. Clock signals φ 1  and φ 2  are used to charge capacitors in CMFB circuit  120 . 
     FIG. 1 b  is a schematic circuit for differential amplifier  101  of FIG. 1 a . As shown in FIG. 1 b , differential input signal V in  across terminals  103   a  and  103   b  control the gate terminals of transistors  112  and  113 , which receive currents from current sources  106  and  107 . Voltage V in  thus controls the relative magnitudes of current flowing in transistors  112  and  113 , thereby providing an amplified output signal V o  across terminals  104   a  and  104   b . Common mode feedback signal V fb  is received at terminal  105 . Common mode feedback signal V fb  operates to diminish any common mode offset voltage in output signal V o  of terminals  104   a  and  104   b  through resistors  108  and  109  respectively. 
     FIG. 1 c  shows schematically CMFB circuit  102  of FIG. 1 a . As shown in FIG. 1 c , CMBF circuit  102  includes feedback generator circuits  102   a  and  102   b . In CMBF circuit  102 , diode-connected PMOS transistor  150  and current source  161  provide a bias voltage V bias  which is used, in conjunction with a reference voltage V CM , to charge capacitors  140 ,  141 ,  150  and  151  in the manner described below. CMFB circuit  102  also includes switches  142 - 147  and  152 - 157 , each of which is controlled by one of the non-overlapping clock signals φ 1  or φ 2 . 
     In CMBF circuit  102 , clock signal φ 1 , when active (i.e., at logic high), closes switches  142 ,  145 ,  147 ,  153 ,  154  and  156 . Concurrently, clock signal φ 2  opens switches  143 ,  144 ,  146 ,  152 ,  155  and  157 . Thus, when clock signal φ 1  is active, capacitors  140  and  141  are coupled serially between terminals  104   a  and  104   b  and capacitors  150  and  151  are coupled in parallel between reference signals V bias  and V CM  for charging. In this configuration, capacitors  150  and  151 , each having a capacitance C, is charged to a charge Q according to: 
     
       
           CQ =( V   bias   −V   CM ) 
       
     
     Concurrently, because of charge sharing at capacitors  140  and  141 , signal V fb  at terminal  105  has a magnitude which is equal to any common mode offset voltage in V o  plus an offset voltage equal to (V bias −V CM ) Specifically, the following equations hold: 
     
       
         
           V 
           fb 
           =CQ 
           1 
           +V 
           ON 
         
       
     
     
       
           V   fb   =C( 2 Q−Q   1 )+ V   OP   
       
     
     where V ON  and V OP  are the voltages at terminals  104   b  and  104   a  respectively. Thus,          V   fb     =       (       V   bias     -     V   CM       )     +         V   ON     +     V   OP       2                              
     Therefore, voltage V fb  is the common mode offset voltage in V o  plus the bias voltage (V bias −V CM ). By canceling the common mode offset voltage through the feedback signal V fb , differential amplifier  101  continues to have a high common mode rejection. CMFB circuit  102  is advantageous because the bias voltage allows CMFB circuit  120  to operate even when V o  is very small. 
     Similarly, clock signal φ 2 , when active, closes switches  152 ,  155 ,  157 ,  143 ,  144  and  146 . Concurrently, clock signal φ 2  opens switches  142 ,  145 ,  147 ,  153 ,  154  and  156 . Thus, when clock signal φ 2  is active, capacitors  150  and  151  are coupled serially between terminals  104   a  and  104   b  and capacitors  140  and  141  are coupled in parallel between reference signals V bias  and V CM  when charging. 
     FIG. 1 d  shows a switch  180 , which can be used to implement any of switches  142 - 147  and  152 - 157 . As shown in FIG. 1 d , switch  180  includes NMOS transistors  181 - 183  and PMOS transistors  184 - 186 . In switch  180 , the gate terminals of transistors  182 ,  184  and  186  are driven by a clock signal φ, while transistors  181 ,  183  and  185  are driven by the clock signal φ′, which is the complement signal of clock signal φ. Accordingly, input node  187  is coupled to output node  188 , when clock signal  100   is active, and isolated from output node  188 , when clock signal φ is inactive. 
     FIG. 2 shows a current source  300  with a compensation current for process variations, suitable for use in generating bias currents. As shown in FIG. 2, a current source  301  generates a current I which is mirrored by NMOS transistor  302  to provide current I in each of NMOS transistors  303  and  304 . The currents in NMOS transistors  303  and  304  are mirrored by PMOS transistors  305  and  307  to provide, upon predetermined scaling of PMOS transistors  305  and  307 , currents I 1  and I 2  in PMOS transistors  306  and  308 , respectively. Currents I 1  and I 2  are combined and output at terminal  309 . In current source  300 , PMOS transistor  306  is provided a channel length much longer than the channel length of PMOS transistor  308 , thereby rendering PMOS transistor  306  to be much less sensitive on a percentage basis to variations in channel length due to process variations. In one embodiment, PMOS transistor  306  is provided a width of 10 microns and a channel length of 3.2 microns, while PMOS transistor  308  is provided a width of 24 microns and a channel length of 0.48 microns. Consequently, in that embodiment, current I 1  is approximately {fraction (1/16)} or 6.25% of current I 2 . Thus, PMOS transistor  306  corrects for a process variation of about 6% in PMOS transistor  308 . Such compensation are especially advantageous when the compensated current is used in a differential amplifier. With a reliable reference current generated by a current source of the present invention, the operational bandwidth of the differential amplifier can be increased by as much as 25%. 
     The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.

Technology Classification (CPC): 7