Patent Abstract:
The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Divisional of pending U.S. patent application Ser. No. 11/247,510, filed Oct. 11, 2005 and entitled “SWITCHING DEVICE FOR A PIXEL ELECTRODE AND METHODS FOR FABRICATING THE SAME,” the contents of which are incorporated by reference herein. 
     
    
     BACKGROUND 
       [0002]    The invention relates to a display device, and more particularly to a switching device for a pixel electrode and methods for fabricating the same. 
         [0003]    Bottom-gate type thin film transistors (TFTs) are widely used for thin film transistor liquid crystal displays (TFT-LCDs).  FIG. 1  is a sectional view of a conventional bottom-gate type TFT structure  100 . The TFT structure  100  typically comprises a glass substrate  110 , a gate  120 , a gate-insulating layer  130 , a channel layer  140 , an ohmic contact layer  150 , a source  160  and a drain  170 . 
         [0004]    As the size of TFT-LCD panels increases, metals having low resistance are required. For example, gate lines employ low resistance metals such as Cu and Cu alloy in order to improve operation of the TFT-LCD. 
         [0005]    However, Cu can react with radicals to form Cu oxide in subsequent processes, thereby increasing resistance. Also, Cu diffuses easily and reacts with silicon to form CuSi x , significantly affecting reliability of the device. 
         [0006]    JP 2000-332015, the entirety of which is hereby incorporated by reference, discloses a method of forming CuSi x . A layer of CuSi x  is formed between a silicon-rich nitride layer and a Cu layer, enhancing adhesion therebetween. 
       SUMMARY 
       [0007]    Thin film transistors and fabrication methods thereof are provided. Diffusion of Cu is reduced, and no extra processes such as photolithography are required. 
         [0008]    An embodiment of a fabrication method comprises forming a gate on a substrate. A first CuSi x  layer is formed on the gate by plasma treatment on the gate in a silane-containing chamber. The temperature of the chamber is substantially about 180° C. to 370° C. 
         [0009]    To enhance the barrier properties of the first CuSi x  layer, a subsequent plasma treatment is performed on the first CuSi x  layer in a chamber containing N 2  and NH 3 . The temperature of the chamber is substantially about 180° C. to 370° C. 
         [0010]    An insulating layer is formed on the first CuSi x  layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. A pixel electrode is formed, electrically connecting to the source or the drain. 
         [0011]    Another embodiment of a method comprises forming a second CuSi x  layer between the semiconductor layer and the source/drain. 
         [0012]    Formation of the second CuSi x  layer comprises forming a Cu layer or a Cu alloy layer on the semiconductor layer and performing a plasma treatment on the Cu layer or the Cu alloy layer in a silane-containing chamber. The temperature of the chamber is substantially about 180° C. to 370° C. 
         [0013]    To enhance the barrier properties of the second CuSi x  layer, a subsequent plasma treatment is performed on the second CuSi x  layer in a chamber containing N 2  and NH 3 . The temperature of the chamber is substantially about 180° C. to 370° C. 
         [0014]    In these embodiments, the first CuSi x  layer is conformally formed on the gate. The substrate comprises a glass substrate. The insulating layer comprises a silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide or aluminum oxide layer. The semiconductor layer comprises silicon. The source/drain comprises Cu or Cu alloy. 
         [0015]    Thin film transistors (TFTs) of the invention can be bottom-gate or top-gate, serving as a switching device for a pixel electrode when the source/drain are electrically in contact with a pixel electrode. In addition, the TFTs of the invention can be applied in display such as LCD. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0016]    The invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings. 
           [0017]      FIG. 1  is a sectional view of a conventional TFT structure. 
           [0018]      FIGS. 2A to 2F  are sectional views of an exemplary process for fabricating a first embodiment of a TFT structure of the present invention. 
           [0019]      FIGS. 3A to 3H  are sectional views of an exemplary process for fabricating a second embodiment of a TFT structure of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
     First Embodiment 
       [0020]    An exemplary process for fabricating a first embodiment of TFTs of the invention is shown in  FIGS. 2A-2F . 
         [0021]    In  FIG. 2A , a Cu layer (not shown) is formed on a substrate  210 , for example, by chemical vapor deposition (CVD), electrochemical plating (ECP), or physical vapor deposition (PVD). The Cu layer is deposited, forming a gate  220  on the substrate  210 . The substrate  210  may be a glass substrate. The gate  220  may be copper with thickness substantially about 100 nm to 500 nm. 
         [0022]    In  FIGS. 2B and 2C , a first CuSi x  layer  227  is conformally formed on the gate  220  by plasma treatment  225  of the gate  220  in a silane-containing chamber. The temperature of the chamber is substantially about 180□ to 370□. Silicon atoms react with the surface of the gate  220  of Cu, forming the first CuSi x  layer  227 , preventing Cu from diffusing to the insulating layer  230  shown in  FIG. 2E . The thickness of the first CuSi x  layer  227  is substantially about 5 nm to 100 nm. 
         [0023]    In  FIG. 2D , a subsequent plasma treatment  225   a  is performed on the first CuSi x  layer  227  in a chamber containing N 2  and NH 3 . The temperature of the chamber is substantially about 180° C. to 370° C. Nitrogen atom reacts with the surface of the first CuSi x  layer  227  to form N—Si bond, thereby enhancing the barrier properties of the first CuSi x  layer. 
         [0024]    In  FIG. 2E , an insulating layer  230  is formed on the first CuSi x  layer  227 . A semiconductor layer (not shown) is formed on the insulating layer  230 . The insulating layer  230  comprises silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide or aluminum oxide. The semiconductor layer comprising a channel layer  240  and an ohmic contact layer  250  is defined on a portion of the gate-insulating layer  230  by deposition and patterning. The channel layer  240  can be an undoped amorphous silicon layer formed by CVD. The ohmic contact layer  250  can be an impurity-added silicon layer formed by CVD. The impurity can be n type dopant (for example, P or As) or p type dopant (for example, B). 
         [0025]    In  FIG. 2F , a Cu layer (not shown) is formed on the ohmic contact layer  250 , for example, by CVD, ECP, or PVD. The source/drain  260 / 270 , of Cu or Cu alloy, are formed on the ohmic contact layer  250  by selectively etching through the Cu layer, the ohmic contact layer  250 , exposing a portion of the surface of the channel layer  240 . A pixel electrode is formed, electrically connected to the source/drain  260 / 270 . A resultant thin film transistor  200  is obtained. 
       Second Embodiment 
       [0026]    An exemplary process for fabricating a second embodiment of TFTs of the present invention is shown in  FIGS. 3A-3H . 
         [0027]    In  FIG. 3A , a Cu layer (not shown) is formed on a substrate  210 , for example, by chemical vapor deposition (CVD), electrochemical plating (ECP), or physical vapor deposition (PVD). The Cu layer is etched, forming a gate  220  on the substrate  210 . The substrate  210  may be a glass substrate. The gate  220  may be copper with thickness substantially about 100 nm to 500 nm. 
         [0028]    In  FIGS. 3B and 3C , a first CuSi x  layer  227  is conformally formed on the gate  220  by performing plasma treatment  225  of the gate  220  in a silane-containing chamber. The temperature of the chamber is substantially about 180° C. to 370° C. Silicon atoms react with the surface of the gate  220  of Cu, forming the first CuSi x  layer  227 , preventing Cu from diffusing to the insulating layer  230  shown in  FIG. 3E . The thickness of the first CuSi x  layer  227  is substantially about 5 nm to 100 nm. 
         [0029]    In  FIG. 3D , a subsequent plasma treatment  225   a  is performed on the first CuSi x  layer  227  in a chamber containing N 2  and NH 3 . The temperature of the chamber is substantially about 180° C. to 370° C. Nitrogen atom reacts with the surface of the first CuSi x  layer  227  to form N—Si bond, thereby enhancing the barrier properties of the first CuSi x  layer. 
         [0030]    In  FIG. 3E , an insulating layer  230  is formed on the first CuSi x  layer  227 . A semiconductor layer (not shown) is formed on the insulating layer  230 . The insulating layer  230  comprises silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide or aluminum oxide. The semiconductor layer comprising a channel layer  240  and an ohmic contact layer  250  is defined on a portion of the gate-insulating layer  230  by deposition and patterning. The channel layer  240  can be an undoped amorphous silicon layer formed by CVD. The ohmic contact layer  250  can be an impurity-added silicon layer formed by CVD. The impurity can be n type dopant (for example P or As) or p type dopant (for example B). 
         [0031]    In  FIG. 3E , a Cu layer  252  is formed on the ohmic contact layer  250 , for example, by CVD, ECP, or PVD. 
         [0032]    In  FIGS. 3F and 3G , a Cu layer  252  is formed on the semiconductor layer. In other embodiments, a Cu alloy layer can be formed in place of the Cu layer. Plasma treatment is performed on the Cu layer  252 , completely forming a second CuSi x  layer  252   a . The second CuSi x  layer  252   a  prevents diffusion of Cu from the source/drain  260 / 270  shown in  FIG. 3H  to the underlying substrate. The plasma treatment  254  is performed in a silane-containing chamber. The temperature of the chamber is substantially in a rang of about 180° C. to about 370° C. The thickness of the second CuSi x  layer  252   a  is substantially in a rang of about 5 nm to 100 nm. 
         [0033]    In  FIG. 3G , a subsequent plasma treatment  254   a  is performed on the second CuSi x  layer  252   a  in a chamber containing N 2  and NH 3 . The temperature of the chamber is substantially about 180° C. to 370° C. Nitrogen atoms react with the surface of the second CuSi x  layer  252   a  to form N—Si bond, thereby enhancing the barrier properties of the second CuSi x  layer. 
         [0034]    In  FIG. 3H , a Cu layer (not shown) is formed on the second CuSi x  layer  252   a , for example, by CVD, ECP, or PVD. The source/drain  260 / 270 , of Cu or Cu alloy, is formed on the second CuSi x  layer  252   a  by selectively etching through the Cu layer, second CuSi x  layer  252   a , the ohmic contact layer  250 , exposing a portion of the surface of the channel layer  240 . A pixel electrode is formed, electrically connecting to the source/drain  260 / 270 . A resultant thin film transistor  300  is obtained. 
         [0035]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Classification (CPC): 7