Patent Abstract:
The invention provides a method and apparatus for optimizing instruction prefetch and caching in a processor. In the preferred embodiment, a path prediction circuit maintains information about which cache lines are likely to be executed in the future. This information is used to independently fetch the predicted cache lines, store them in a prefetch queue, and load them in to the instruction cache as instructions contained in these lines are about to be decoded by the processor. A plurality of cache lines can be in the process of being simultaneously fetched from main memory to load the prefetch queue.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to a method and an apparatus for instruction caching in computer processors.  
           [0003]    2. Description of Related Art  
           [0004]    Known instruction memory caching schemes for computer processors use cache memory to improve processor efficiency. Typically, when an instruction is fetched by the processor, an instruction cache is accessed to determine whether a copy of the memory holding the instruction is in the cache. If so, the instruction is provided to the processor from the instruction cache. If not, the main memory is accessed and a portion of the contents of the main memory that contains the instruction is copied to the instruction cache. The copied information is a cache line.  
           [0005]    Because the instruction execution path is likely to continue sequentially and because instructions are often repeatedly executed, once the cache line is cached, the processor need not access main memory so long as the instructions being executed are from cache lines resident in the instruction cache. Thus, caching instructions reduces processor delays that would otherwise result from main memory fetches.  
           [0006]    One problem which has arisen in the art is that instruction caching does not avoid all instruction memory access delays. One reason for this is that when sequential instruction execution reaches the end of a cache line, the subsequent cache line must be fetched from instruction memory if the subsequent cache line is not already in the instruction cache. Waiting for the subsequent cache line stalls the processor. Another reason for processor stalls is because branch instructions alter the sequential instruction fetch sequence within the instruction execution path. Thus, the cache line that contains the next instruction that is to be executed after a branch instruction may not be resident in the instruction cache. This requires that the prior art fetch the target instruction from main memory instead of from the instruction cache.  
           [0007]    Both of these reasons invoke a main memory fetch that results in the processor incurring delays that are relatively much longer than delays incurred due to fetches from the instruction cache. The fetch to main memory thus delays the processing of the instruction execution path until the fetch for the cache line containing the needed instruction is completed.  
           [0008]    One skilled in the art will understand that the main memory may itself be cached (for example a level 2 cache). However the main memory cache is relatively slower than the instruction cache.  
           [0009]    Another problem is that only one cache line is read from memory into the instruction cache at a time and during the fetch the instruction cache can not be accessed to get instructions. Thus, if a subsequently accessed cache line would have required a linefill from main memory, the processor would incur an additional delay for a second cache linefill request from main memory, after it fetched all needed instructions from the first line resident in the instruction cache.  
           [0010]    Accordingly, it would be desirable to provide a caching scheme that predicts and pre-fetches a number of cache lines that are expected to be needed in the future to overlap this process with other processor activities and thus minimize the amount of time the instruction cache is unavailable to the processor.  
         SUMMARY OF THE INVENTION  
         [0011]    The invention provides a method and apparatus for optimizing instruction prefetch and caching in a processor. In the preferred embodiment, a path prediction circuit maintains information about which cache lines are likely to be executed in the future. This information is used to independently fetch the predicted cache lines, store them in a prefetch queue, and load them in to the instruction cache as instructions contained in these lines are about to be decoded by the processor.  
           [0012]    The foregoing and many other aspects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments that are illustrated in the various drawing figures. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 illustrates an instruction processing architecture in accordance with a preferred embodiment;  
         [0014]    [0014]FIG. 2 illustrates a method for loading the prefetch queue using the instruction processing architecture of FIG. 1;  
         [0015]    [0015]FIG. 3 illustrates a method for loading the instruction cache from the prefetch queue using the instruction processing architecture of FIG. 1;  
         [0016]    [0016]FIG. 4 illustrates a method for executing instruction from the instruction cache using the instruction processing architecture of FIG. 1.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]    [0017]FIG. 1 illustrates an instruction processing architecture, indicated by general reference character  100  that includes a memory system  101 , a prefetch queue  103 , an instruction cache (data) memory  105 , an instruction parse/decode logic  107 , and an instruction execute logic  109 . Cache lines are fetched from the memory system  101  and cached in the instruction cache (data) memory  105  until instructions fetched from these cache lines are decoded and parsed by the instruction parse/decode logic  107  and executed by the instruction execute logic  109 . The instruction cache (data) memory  105  is organized to so as to hold one or more instruction cache lines from the memory system  101 .  
         [0018]    The instruction execute logic  109  gathers information relating to the results of execution of control transfer instructions. This information is passed by an update/correct predictor path  111  to a path predictor logic  113  where the path predictor logic  113  adjusts its predictors dependent on the outcome of the execution. The processing of instruction data from the instruction cache (data) memory  105  by the instruction parse/decode logic  107  and the instruction execute logic  109  is relatively much faster than the time required to fetch an instruction cache line from the memory system  101 . One of the goals of the invention is to preload the prefetch queue  103  so that the missing instruction cache line can be readily loaded into the instruction cache (data) memory  105  when it is needed, so that the instruction parse/decode logic  107  and the instruction execute logic  109  do not stall waiting for instruction data if the next cache line accessed by the program flow misses in the instruction cache.  
         [0019]    The path predictor logic  113  communicates with a prefetch pointer logic  115  that includes a prefetch pointer and control logic for performing the prefetch operations described herein. The prefetch pointer logic  115  provides an ‘advance predictor’ signal  116  to the path predictor logic  113  when the prefetch pointer logic  115  finishes processing of sequentially fetched instructions contained in one cache line. The path predictor logic  113  responds to the ‘advance predictor’ signal  116  by providing a ‘new prefetch pointer’ signal  117  responsive to the past execution history. The ‘new prefetch pointer’ signal  117  includes the predicted address of an upcoming instruction. Upper bits of this address represent the address of the cache line that is expected to be needed. Thus, as the prefetch pointer logic  115  is able to initiate a linefill, the prefetch pointer is advanced along the instruction execution path.  
         [0020]    One example of the path predictor logic  113  is provided by U.S. patent application Ser. No. 09/429,590 filed Oct. 28, 1999 entitled BLOCK-BASED BRANCH TARGET BUFFER hereby incorporated by reference in its entirety.  
         [0021]    An instruction execution path is a sequence of addresses of executed instructions. Thus, given an address and an execution history, the path predictor logic  113  can predict the instruction execution path for the execution of subsequent instructions. The instruction execution path can be represented by a sequence of instruction cache lines. One skilled in the art will understand that this arrangement of the path predictor logic  113  and the prefetch pointer logic  115  allows the prediction of which instruction cache lines are to be executed based on the addresses of the cache lines being fetched.  
         [0022]    A ‘current prefetch pointer’ signal  119  is provided to an instruction cache (tag) memory  121 . The instruction cache (tag) memory  121  determines whether the instruction cache line containing the instruction at the ‘current prefetch pointer’ signal  119  is already in the instruction cache (data) memory  105 . A LRU memory  123  is used when a cache miss occurs to identify which cache way the missing line is to be written to. The instruction cache (tag) memory  121  sends a ‘hit/miss, way number’ signal  125  result to the prefetch pointer logic  115  and the prefetch queue  103 . The prefetch pointer logic  115  uses the ‘hit/miss, way number’ signal  125  to determine whether to originate a linefill request. If the instruction cache line is not currently cached nor in the process of being fetched, the prefetch pointer logic  115  sends a ‘linefill request’ signal  127  to the memory system  101  that will eventually respond with memory data  129 . The memory data  129  supplied by the memory system  101  flows into the prefetch queue  103  where it is accumulated. After control information about one instruction cache line is loaded into the prefetch queue  103 , another prefetch lookup operation can be initiated by the prefetch pointer logic  115 . Thus, the prefetch pointer logic  115  initiates as many linefill requests as possible to the memory system  101 . One skilled in the art will understand that some number of instruction cache lines within the predicted instruction execution path can thus be selected. The upcoming instruction cache lines are those in the instruction execution path that contain instructions that are expected to be executed relatively soon.  
         [0023]    The prefetch queue  103  includes a data portion  135  and a control portion  137  organized into a plurality of entries. A prefetch queue entry  139  in the prefetch queue  103  is but one of the entries that can be contained by the prefetch queue  103 . The prefetch queue entry  139  (as shown) is located at the head of the prefetch queue  103 . An instruction cache line from the memory system  101  is read into the data portion  135  for each queued instruction cache line as it arrives from memory. The control portion  137  for each queued instruction cache line stores the status and address of the instruction cache line as received from the instruction cache (tag) memory  121 . The address of the cache line is obtained from the prefetch pointer logic  115  and the status contains the ‘hit/miss, way number’ signal  125  from the instruction cache (tag) memory  121  and the LRU memory  123  associated with the instruction cache line.  
         [0024]    Once the instruction cache line is completely fetched and stored in the prefetch queue  103 , it is eventually transferred to the instruction cache (data) memory  105  (via a ‘cache line data’ signal  133 ) where it is made available to the instruction parse/decode logic  107  of the processor. At the same time, the address from the control portion  137  of the prefetch queue  103  is transferred to the instruction cache (tag) memory  121  via a ‘tag fill data’ signal  141 .  
         [0025]    One skilled in the art will understand that the prefetch queue  103  can have a fixed number of entries, a variable number of entries or otherwise. In a preferred embodiment, the prefetch queue  103  contains a fixed number of entries (for example eight entries). Such a one will also understand that the data portion  135  of each entry can be implemented as storage that can contain the entire cache line, or be a pointer or index to a pool of buffers that can contain the entire cache line (for example, the buffer pool may contain two buffers). The actual details of the implementation of the invention is subject to performance and cost tradeoffs and encompass many variations not detailed here but understood by one skilled in the art.  
         [0026]    Information in the cache line in the prefetch queue  103  is simultaneously written into the instruction cache (tag) memory  121  and the instruction cache (data) memory  105  when the cache line is at the head of the prefetch queue  103 , the linefill operation has completed, and the previous entry in at the head of the prefetch queue  103  has been processed.  
         [0027]    Once the instruction cache line is loaded into the instruction cache (data) memory  105  each instruction within the cache line is available to the instruction parse/decode logic  107  that is configured to parse and decode the instruction. The parsed instruction is then executed by the instruction execute logic  109 . If the executed instruction causes a change in the instruction execution path away from the predicted instruction execution path, the path predictor logic  113  is updated using the update/correct predictor path  111 . This comprises a prediction modification mechanism that updates execution history information in the path predictor logic  113  so that future predictions are responsive to the execution history of the instructions within the instruction cache line.  
         [0028]    Preferred methods for loading and emptying the prefetch queue  103  as well as adjusting the path predictor logic  113  are subsequently described with respect to FIG. 2, FIG. 3 and FIG. 4 respectively.  
         [0029]    One skilled in the art will understand that many path prediction mechanisms can be used when implementing the path predictor logic  113 . These include using a single, multiple bit, or correlated predictor state as is known in the art of branch prediction. In addition, the techniques relating to fetch-block predictions described by the application incorporated by reference can also be used.  
         [0030]    [0030]FIG. 2 illustrates a load prefetch queue process  200 , used with the instruction processing architecture  100  of FIG. 1. The load prefetch queue process  200  initiates at a ‘start’ terminal  201  and continues to a ‘predict instruction path’ step  203 . The ‘predict instruction path’ step  203  uses prediction techniques (as previously discussed) to predict which instructions will be executed based on execution history. An ‘identify upcoming instruction cache line’ step  205  determines the next expected cache line that contains instructions on the execution path. Some embodiments support a variable number of entries in the prefetch queue  103 . Other embodiments use a fixed number of entries. If a fixed number of entries can be in the prefetch queue  103 , a ‘stall for prefetch queue entry’ step  207  stalls the load prefetch queue process  200  until an entry in the prefetch queue  103  becomes available. Once an entry becomes available (or if an entry was available), the load prefetch queue process  200  continues to an ‘add entry to prefetch queue’ step  209  that queues an entry at the tail of the prefetch queue  103 . Next, a ‘cache line already in cache’ decision step  211  determines whether the cache line determined by the ‘identify upcoming instruction cache line’ step  205  is already resident in the instruction cache (data) memory  105 . If the cache line is already resident in the instruction cache (data) memory  105 , the load prefetch queue process  200  continues to a ‘load control field in prefetch queue’ step  213 . The ‘load control field in prefetch queue’ step  213  loads the control portion  137  of the new entry with the HIT and the cache way number such that the prefetch queue entry identifies the cache line residing in the instruction cache (data) memory  105 . The load prefetch queue process  200  continues back to the ‘predict instruction path’ step  203  to predict the next cache line in the execution sequence.  
         [0031]    However, if the ‘cache line already in cache’ decision step  211  determined that the cache line found by the ‘identify upcoming instruction cache line’ step  205  was not already in the instruction cache (data) memory  105 , the load prefetch queue process  200  continues to a ‘stall for cache line buffer’ step  215 . Each entry in the prefetch queue  103  includes the data portion  135 . In some implementations, the data portion  135  can contain sufficient memory to hold a cache line. Other implementations provide a limited pool of cache line buffers. For implementations that have a pool of cache line buffers, the ‘stall for cache line buffer’ step  215  stalls the load prefetch queue process  200  until one of the cache line buffers is free. One skilled in the art will understand that the ‘stall for cache line buffer’ step  215  is not needed if a cache line buffer exists for each entry in the prefetch queue  103 . Once a cache line buffer becomes available, a ‘load buffer’ step  217  acquires the buffer and starts a memory transfer into the cache line buffer of cache line from memory. The load prefetch queue process  200  continues back to the ‘predict instruction path’ step  203  to predict the next cache line in the execution sequence.  
         [0032]    In one preferred embodiment the ‘load buffer’ step  217  performs its function by acquiring a cache line buffer and initiating a linefill request to the memory system  101  directed toward the acquired cache line buffer.  
         [0033]    Thus, the load prefetch queue process  200  queues up entries into the prefetch queue  103 .  
         [0034]    [0034]FIG. 3 illustrates a ‘load instruction cache process’  300  that loads the instruction cache (data) memory  105  from the prefetch queue  103  (thus, unloading the prefetch queue  103 ). The ‘load instruction cache process’  300  initiates at a ‘start’ terminal  301  and continues to a ‘test head of prefetch queue’ step  303  that examines the control portion  137  of the head entry (for example, the entry at the position indicated by the prefetch queue entry  139 ) of the prefetch queue  103 . A ‘cache line hit’ decision step  305  determines whether the cache line is already in the instruction cache (data) memory  105  by checking for a HIT in the control portion  137  of the prefetch queue entry  139 . If the cache line is already in the instruction cache (data) memory  105 , the ‘load instruction cache process’  300  continues to an ‘advance prefetch queue’ step  307  to advance the prefetch queue  103  (thus, moving another entry to the head of the prefetch queue  103  and making an entry available for the ‘stall for prefetch queue entry’ step  207 ).  
         [0035]    However, if the ‘cache line hit’ decision step  305  did not detect a HIT, the ‘load instruction cache process’  300  continues to a ‘buffer full’ decision step  309 . The ‘buffer full’ decision step  309  determines whether the cache line transfer from memory initiated by the ‘load buffer’ step  217  has completed. If the transfer has not completed, the ‘load instruction cache process’  300  waits for the cache line to be transferred. Once the cache line is transferred to the buffer, the ‘load instruction cache process’  300  continues to a ‘copy buffer to instruction cache’ step  311  that copies the cache line from the buffer to the instruction cache (data) memory  105 . Then a ‘release buffer’ step  313  releases the buffer (for embodiments that have a restricted number of buffers) for reuse by the ‘load buffer’ step  217  and the ‘load instruction cache process’  300  continues to the ‘advance prefetch queue’ step  307 .  
         [0036]    Thus, entries are removed from the prefetch queue  103  and cache lines that are predicted to be needed and not present in the instruction cache data memory are loaded into the instruction cache (data) memory  105 .  
         [0037]    [0037]FIG. 4 illustrates an ‘instruction execution process’  400  that initiates at a ‘start’ terminal  401  and continues to a ‘request instruction’ step  403 . The ‘request instruction’ step  403  requests an instruction from the instruction cache (data) memory  105  using techniques known in the art. A ‘parse/decode instruction’ step  405  parses and decodes the instruction and an ‘execute instruction’ step  407  executes the instruction. These steps are also well known in the art. An ‘update predictor’ step  409  examines the result of the execution of the instruction to determine whether the result of the instruction execution has changed the execution path from what was expected. If the instruction path changed from what was predicted, the path predictor logic  113  is modified by the update/correct predictor path  111  and the prefetch pointer logic  115  is modified to reflect the new execution path. In addition, the prefetch queue  103  is flushed to remove existing entries that were based on the previously predicted execution path.  
         [0038]    One skilled in the art will understand that the load prefetch queue process  200  does not show the steps used to initialize the instruction cache (data) memory  105 , the instruction cache (tag) memory  121 , or the path predictor logic  113 . However, such a one would understand how to so initialize.  
         [0039]    One skilled in the art will understand that the invention enables multiple linefill requests to be initiated to the memory system  101  before the instruction data contained in the requested cache lines is needed by the instruction parse/decode logic  107 . Thus, the latency of accessing the memory system  101  will have less impact on performance of the processor since such memory access will overlap with the operation of the instruction parse/decode logic  107  working on instructions that are younger in the program flow. Thus, the invention reduces processing delays by preloading cache lines from memory based on a predicted execution path.  
         [0040]    While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention, and these variations would become clear to one of ordinary skill in the art after perusal of the specification, drawings and claims herein.

Technology Classification (CPC): 6