Patent Abstract:
There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.

Full Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2013-031367 filed on Feb. 20, 2013, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a level shift circuit mounted on a semiconductor device. 
         [0004]    2. Background Art 
         [0005]    A conventional level shift circuit will be described.  FIG. 2  is a circuit diagram illustrating a conventional level shift circuit. 
         [0006]    When an input voltage VIN goes to a high level, namely, a first power supply voltage VDD 1 , then an inverter  51  causes the gate voltage of an NMOS transistor  52  to become a ground voltage VSS. This causes the NMOS transistor  52  to turn off. Meanwhile, an NMOS transistor  53  turns on and an output voltage VOUT goes to a low level, namely, the ground voltage VSS. At this time, a PMOS transistor  54  is on, the voltage of an internal node N 1  is a second power supply voltage VDD 2 , and a PMOS transistor  55  is off 
         [0007]    Further, when the input voltage VIN goes to the low level, namely, the ground voltage VSS, the inverter  51  causes the gate voltage of the NMOS transistor  52  to become the first power supply voltage VDD 1 . Then, the NMOS transistor  52  turns on, the voltage of the internal node N 1  becomes the ground voltage VSS, the PMOS transistor  55  turns on, and the output voltage VOUT goes to the high level, namely, the second power supply voltage VDD 2 . At this time, the NMOS transistor  53  is off (refer to, for example, Patent Document 1). 
         [0008]    [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-134690 
         [0009]    However, according to the art disclosed in Patent Document 1, if the first power supply voltage VDD 1  becomes lower than a minimum operating power supply voltage of the level shift circuit, then the circuit malfunctions, inconveniently making the output voltage VOUT unstable. 
       SUMMARY OF THE INVENTION 
       [0010]    The present invention has been made with a view toward solving the problem described above and an object of the invention is to provide a level shift circuit free from malfunction. 
         [0011]    To solve the problem described above, a level shift circuit according to the present invention is adapted to convert a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit includes a control circuit which detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage by a detection signal of the control circuit. 
         [0012]    According to the present invention, if the first power supply voltage is lower than the minimum operating power supply voltage, an output voltage of the level shift circuit is forcibly fixed to the second power supply voltage or the ground voltage, thus preventing the level shift circuit from malfunctioning. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a circuit diagram illustrating a level shift circuit according to an embodiment of the present invention; and 
           [0014]      FIG. 2  is a circuit diagram illustrating a conventional level shift circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0015]    The following will describe an embodiment of the present invention with reference to the accompanying drawings. 
         [0016]    First, the configuration of a level shift circuit will be described.  FIG. 1  is a circuit diagram of the level shift circuit. In the figure, the voltage of a first supply terminal is a first power supply voltage VDD 1 , the voltage of a second supply terminal is a second power supply voltage VDD 2 , and the voltage of a ground terminal is a ground voltage VSS. The level shift circuit converts a received signal of the first power supply voltage VDD 1  into a signal of the second power supply voltage VDD 2  and outputs the converted signal. 
         [0017]    The level shift circuit includes a signal processing circuit  10  and a control circuit  20 . The signal processing circuit  10  has an inverter  11 , NMOS transistors  12  and  13 , PMOS transistors  14  and  15 , and switches  16  and  17 . The control circuit  20  has an NMOS transistor  21 , a current source  22 , and an inverter  23 . 
         [0018]    In the level shift circuit, the input terminal of the signal processing circuit  10  is the input terminal of the level shift circuit. The output terminal of the signal processing circuit  10  serves as the output terminal of the level shift circuit. A first control signal terminal of the signal processing circuit  10  and a first control signal terminal of the control circuit  20  are interconnected. A second control signal terminal of the signal processing circuit  10  and a second control signal terminal of the control circuit  20  are interconnected. 
         [0019]    In the signal processing circuit  10 , the input terminal of the inverter  11  is connected to the input terminal of the signal processing circuit  10  and the gate of the NMOS transistor  13 , the output terminal thereof is connected the gate of the NMOS transistor  12 , the supply terminal thereof is connected to the first supply terminal, the ground terminal thereof is connected to a ground terminal. The source of the NMOS transistor  12  is connected to a ground terminal, while the drain thereof is connected to an internal node N 1 . The source of the NMOS transistor  13  is connected to a ground terminal, while the drain thereof is connected to an internal node N 2 . The switch  16  is provided between the internal node N 1  and the ground terminal. The switch  17  is provided between the output terminal of the signal processing circuit  10  and the internal node N 2 . The gate of the PMOS transistor  14  is connected to the output terminal of the signal processing circuit  10 , the source thereof is connected to a second supply terminal, and the drain thereof is connected to the internal node N 1 . The gate of the PMOS transistor  15  is connected to the internal node N 1 , the source thereof is connected to the second supply terminal, and the drain thereof is connected to the output terminal of the signal processing circuit  10 . The switch  16  is controlled by a signal of the first control signal terminal of the signal processing circuit  10 . The switch  17  is controlled by a signal of the second control signal terminal of the signal processing circuit  10 . 
         [0020]    In the control circuit  20 , the gate of the NMOS transistor  21  is connected to a first supply terminal, the source thereof is connected to a ground terminal, and the drain thereof is connected to an internal node N 3 . The current source  22  is provided between the second supply terminal and the internal node N 3 . The input terminal of the inverter  23  is connected to the internal node N 3  and a first control signal terminal of the control circuit  20 , the output terminal thereof is connected to a second control signal terminal of the control circuit  20 , the supply terminal thereof is connected to a second supply terminal, and the ground terminal thereof is connected to a ground terminal. 
         [0021]    The NMOS transistor  21  and the current source  22  constitute a voltage detector circuit. The input terminal of the voltage detector circuit is the gate of the NMOS transistor  21 , while the output terminal thereof is the internal node N 3 . The voltage detector circuit detects when the first power supply voltage VDD 1  becomes a voltage of the total of a minimum operating power supply voltage and a predetermined voltage. The voltage is a threshold voltage of the voltage detector circuit, which is higher by a predetermined voltage than a power supply voltage at which the level shift circuit cannot actually operate, namely, the minimum operating power supply voltage. The predetermined voltage is adjusted, as necessary, according to the specifications of a semiconductor device. More specifically, the threshold voltage of the voltage detector circuit is adjusted by adjusting, as necessary, the threshold voltage and the size of the NMOS transistor  21  and the current amount of the current source  22 . 
         [0022]    A description will now be given of the operation of the level shift circuit in the case where the first power supply voltage VDD 1  is lower than the minimum operating power supply voltage. 
         [0023]    At this time, the first power supply voltage VDD 1  is lower than the threshold voltage of the voltage detector circuit. This causes the NMOS transistor  21  to turn off. The voltage of the internal node N 3  is pulled up by the current source  22  to the second power supply voltage VDD 2 . In other words, the first control signal becomes the second power supply voltage VDD 2 . The switch  16  is composed of, for example, an NMOS transistor, and when the gate voltage reaches the second power supply voltage VDD 2 , the switch  16  turns on, causing the voltage of the internal node N 1  to become the ground voltage VSS. Hence, the PMOS transistor  15  turns on, and the output voltage VOUT is forcibly fixed to the second power supply voltage VDD 2 . Thus, in the case where the first power supply voltage VDD 1  is lower than the minimum operating power supply voltage, the output voltage VOUT of the level shift circuit is forcibly fixed to the second power supply voltage VDD 2 , thus preventing the level shift circuit from malfunctioning. 
         [0024]    The voltage of the internal node N 3  is the second power supply voltage VDD 2 , so that the second control signal is set to the ground voltage VSS by the inverter  23 . The switch  17  is, for example, an NMOS transistor, and the gate voltage is the ground voltage VSS, so that the switch  17  is off. 
         [0025]    Thus, if the first power supply voltage VDD 1  is lower than the threshold voltage of the voltage detector circuit, then the output voltage VOUT of the level shift circuit is forcibly fixed to the second power supply voltage VDD 2 . 
         [0026]    A description will now be given of the operation of the level shift circuit in the case where the first power supply voltage VDD 1  is higher than a voltage of the total of the minimum operating power supply voltage and the predetermined voltage. 
         [0027]    At this time, the first power supply voltage VDD 1  is higher than the threshold voltage of the voltage detector circuit. This causes the NMOS transistor  21  to turn on. The voltage of the internal node N 3  becomes the ground voltage VSS. In other words, the first control signal becomes the ground voltage VSS, so that the switch  16  turns off. Further, the inverter  23  causes the second control signal to be the second power supply voltage VDD 2 , so that the switch  17  turns on. 
         [0028]    Then, when the input voltage VIN goes to the high level, namely, the first power supply voltage VDD 1 , the inverter  11  causes the gate voltage of the NMOS transistor  12  to become the ground voltage VSS. This turns the NMOS transistor  12  off Meanwhile, the NMOS transistor  13  turns on and the output voltage VOUT goes to the low level, namely, the ground voltage VSS. At this time, the PMOS transistor  14  is on, the voltage of the internal node N 1  is the second power supply voltage VDD 2 , and the PMOS transistor  15  is off 
         [0029]    Further, when the input voltage VIN goes to the low level, namely, the ground voltage VSS, the inverter  11  causes the gate voltage of the NMOS transistor  12  to become the first power supply voltage VDD 1 . Then, the NMOS transistor  12  turns on, the voltage of the internal node N 1  becomes the ground voltage VSS, the PMOS transistor  15  turns on, and the output voltage VOUT goes to the high level, namely, the second power supply voltage VDD 2 . At this time, the NMOS transistor  13  is off. 
         [0030]    If the first power supply voltage VDD 1  is higher than the threshold voltage of the voltage detector circuit as described above, then the output voltage VOUT of the level shift circuit depends on the input voltage VIN. 
         [0031]    The current source  22  may use, for example, a resistive element, as long as the pull-up function is implemented. 
         [0032]    Further, the control signal supplied to the switch  16  and the control signal supplied to the switch  17  may be interchanged, and the output terminal and the internal node N 1  of the level shift circuit may be interchanged. 
         [0033]    The gate of the NMOS transistor  21  is directly connected to the first supply terminal. Alternatively, however, the gate of the NMOS transistor  21  may be connected to the first supply terminal through a resistance voltage divider circuit.

Technology Classification (CPC): 7