Patent Abstract:
An inverter circuit with a current detection circuitry includes a main bridge circuit connected between the pair of DC input nodes, the main bridge circuit converting the received DC voltage to a primary AC current so as to output the primary AC current through an output terminal to be connected to a load; a supplementary bridge circuit connected in parallel to the main bridge circuit between the pair of DC input nodes, the supplementary bridge circuit having a circuit configuration identical to that of the main bridge circuit with smaller circuit parameters in at least some of constituent circuit elements so as to generate a detection-use AC current that is a prescribed fraction of said AC current outputted by the main bridge circuit. The detection-use AC current is detected by a current detector so as to calculate the amount of the primary AC current.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    Technical Field 
         [0002]    The present technique relates to a current detection device and a semiconductor device. 
         [0003]    Background Art 
         [0004]    Recent years have seen the continued development of semiconductor devices known as Insulated Gate Bipolar Transistors (IGBTs), and Intelligent Power Modules (IPMs) containing driver circuits for driving IGBTs. 
         [0005]    An IPM is a power semiconductor module for power switching, and supplies power to powered electronic products such as motors, robots, inverters, and converters. An IPM also detects current flowing in a semiconductor element and protects the semiconductor element on the basis of the detected current information. 
         [0006]    As a conventional current detection technique, a technique has been proposed in which the direction of an output current flowing in a power semiconductor device equipped with a sense function is detected and outputted to a CPU. Then, a gain amount, offset amount, and the like of current detection properties are adjusted by a setting signal outputted from the CPU in accordance with the direction of the output current (Patent Document 1). 
       RELATED ART DOCUMENT 
     Patent Document 
       [0000]    
       
         Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2012-90499 
       
     
       SUMMARY OF THE INVENTION 
       [0008]    A typical configuration for current detection has a current detection unit provided on the main line of the IPM or on a bus bar provided in the main line, such that a load current is detected. 
         [0009]    However, according to such a configuration, the current detection unit detects a main current, which is a large current flowing in the main line, as the load current. If a current transformer, for example, is accordingly used as the current detection unit, the size of the unit will increase. This leads to a problem in that the scale of the device will increase as well. 
         [0010]    Having been achieved in light of such circumstances, it is an object of the present invention to provide a current detection device and a semiconductor device that achieve a reduction in the scales of the devices. Accordingly, the present invention is directed to a scheme that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
         [0011]    Additional or separate features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings. 
         [0012]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides an inverter circuit having a current detection circuitry, including: a pair of DC input nodes configured to receive a DC voltage: a main bridge circuit connected between the pair of DC input nodes, the main bridge circuit converting the received DC voltage to a primary AC current so as to output the primary AC current through an output terminal to be connected to a load; a supplementary bridge circuit connected in parallel to the main bridge circuit between the pair of DC input nodes for calculating an amount of the AC current outputted by the main bridge circuit, the supplementary bridge circuit having a circuit configuration identical to that of the main bridge circuit with smaller circuit parameters in at least some of constituent circuit elements so as to generate a detection-use AC current that is a prescribed fraction of said AC current outputted by the main bridge circuit, an output line of the supplementary bridge circuit carrying the detection-use AC current being connected to the output terminal of the main bridge circuit to supplement the primary AC current; and a current detector disposed on said output line of the supplementary bridge circuit to detect the detection-use AC current and output a signal corresponding to the detected detection-use AC current that is said prescribed fraction of the primary AC current from the main bridge circuit. 
         [0013]    In another aspect, the present disclosure provides a three-phase semiconductor inverter circuit having a current detection circuitry, including: a pair of DC input nodes configured to receive a DC voltage; a U-phase main bridge circuit connected between the pair of DC input nodes, the U-phase main bridge circuit converting the received DC voltage to a primary U-phase AC current so as to output the primary U-phase AC current through a U-phase output terminal to be connected to a load; a U-phase supplementary bridge circuit connected in parallel to the U-phase main bridge circuit between the pair of DC input nodes for calculating an amount of the U-phase AC current outputted by the U-phase main bridge circuit, the U-phase supplementary bridge circuit having a circuit configuration identical to that of the U-phase main bridge circuit with smaller circuit parameters in at least some of constituent circuit elements so as to generate a detection-use U-phase AC current that is a prescribed fraction of said U-phase AC current outputted by the U-phase main bridge circuit, an output line of the U-phase supplementary bridge circuit carrying the detection-use U-phase AC current being connected to the U-phase output terminal of the U-phase main bridge circuit to supplement the primary U-phase AC current; a U-phase current detector disposed on said U-phase output line of the U-phase supplementary bridge circuit to detect the detection-use U-phase AC current and output a U-phase signal corresponding to the detected detection-use U-phase AC current that is said prescribed fraction of the primary U-phase AC current from the main bridge circuit; a V-phase main bridge circuit connected between the pair of DC input nodes, the V-phase main bridge circuit converting the received DC voltage to a primary V-phase AC current so as to output the primary V-phase AC current through a V-phase output terminal to be connected to the load; a V-phase supplementary bridge circuit connected in parallel to the V-phase main bridge circuit between the pair of DC input nodes for calculating an amount of the V-phase AC current outputted by the V-phase main bridge circuit, the V-phase supplementary bridge circuit having a circuit configuration identical to that of the V-phase main bridge circuit with smaller circuit parameters in at least some of constituent circuit elements so as to generate a detection-use V-phase AC current that is a prescribed fraction of said V-phase AC current outputted by the V-phase main bridge circuit, an output line of the V-phase supplementary bridge circuit carrying the detection-use V-phase AC current being connected to the V-phase output terminal of the V-phase main bridge circuit to supplement the primary V-phase AC current; a V-phase current detector disposed on said V-phase output line of the V-phase supplementary bridge circuit to detect the detection-use V-phase AC current and output a V-phase signal corresponding to the detected detection-use V-phase AC current that is said prescribed fraction of the primary V-phase AC current from the main bridge circuit; a W-phase main bridge circuit connected between the pair of DC input nodes, the W-phase main bridge circuit converting the received DC voltage to a primary W-phase AC current so as to output the primary W-phase AC current through a W-phase output terminal to be connected to the load; a W-phase supplementary bridge circuit connected in parallel to the W-phase main bridge circuit between the pair of DC input nodes for calculating an amount of the W-phase AC current outputted by the W-phase main bridge circuit, the W-phase supplementary bridge circuit having a circuit configuration identical to that of the W-phase main bridge circuit with smaller circuit parameters in at least some of constituent circuit elements so as to generate a detection-use W-phase AC current that is a prescribed fraction of said W-phase AC current outputted by the W-phase main bridge circuit, an output line of the W-phase supplementary bridge circuit carrying the detection-use W-phase AC current being connected to the W-phase output terminal of the W-phase main bridge circuit to supplement the primary W-phase AC current; and a W-phase current detector disposed on said W-phase output line of the W-phase supplementary bridge circuit to detect the detection-use W-phase AC current and output a W-phase signal corresponding to the detected detection-use W-phase AC current that is said prescribed fraction of the primary W-phase AC current from the main bridge circuit. 
         [0014]    The U-phase bridge circuit includes a U-phase main bridge circuit that outputs a first U-phase current through a first U-phase output line connected to a load, and a U-phase current detection bridge circuit that is connected in parallel to the U-phase main bridge circuit and that outputs a second U-phase current through a second U-phase output line connected at one end to the first U-phase output line. 
         [0015]    The V-phase bridge circuit includes a V-phase main bridge circuit that outputs a first V-phase current through a first V-phase output line connected to the load, and a V-phase current detection bridge circuit that is connected in parallel to the V-phase main bridge circuit and that outputs a second V-phase current through a second V-phase output line connected at one end to the first V-phase output line. 
         [0016]    The W-phase bridge circuit includes a W-phase main bridge circuit that outputs a first W-phase current through a first W-phase output line connected to the load, and a W-phase current detection bridge circuit that is connected in parallel to the W-phase main bridge circuit and that outputs a second W-phase current through a second W-phase output line connected at one end to the first W-phase output line. 
         [0017]    The U-phase current detection unit is disposed in the second U-phase output line and detects the second U-phase current. The V-phase current detection unit is disposed in the second V-phase output line and detects the second V-phase current. The W-phase current detection unit is disposed in the second W-phase output line and detects the second W-phase current. 
         [0018]    The present invention makes it possible to reduce the scale of a device. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a diagram illustrating an example of the configuration of a current detection device. 
           [0020]      FIG. 2  is a diagram illustrating an example of the configuration of a conventional inverter constituted by an IPM. 
           [0021]      FIG. 3  is a diagram illustrating a current transformer. 
           [0022]      FIG. 4  is a diagram illustrating an example of the configuration of an IPM. 
           [0023]      FIG. 5  is a diagram illustrating a correspondence relationship between a surface area ratio and a current ratio. 
           [0024]      FIG. 6  is a diagram illustrating a correspondence relationship between a surface area ratio and a current ratio. 
           [0025]      FIG. 7  is a diagram illustrating a correspondence relationship between a surface area ratio and a current ratio. 
           [0026]      FIG. 8  is a diagram illustrating the configuration of a variation on a current detection bridge circuit. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0027]    Embodiments will be described hereinafter with reference to the drawings. 
         [0028]      FIG. 1  is a diagram illustrating an example of the configuration of a current detection device (i.e., an inverter circuit having a current detection circuitry). A current detection device  1  includes a bridge circuit  1   a  (a first bridge circuit or main bridge circuit), a bridge circuit  1   b  (a second bridge circuit or supplementary bridge circuit), a current detection unit  1   c  (current detector), and driver circuits  30 - 1  and  30 - 2 . 
         [0029]    The bridge circuit  1   a  is a main bridge circuit that supplies current to a load M, and includes transistors Tr 1   a  and Tr 2   a  and diodes D 1   a  and D 2   a . The bridge circuit  1   b  is a bridge circuit for detection current in addition to supplying current to the load M, and includes transistors Tr 1   b  and Tr 2   b  and diodes D 1   b  and D 2   b.    
         [0030]    The bridge circuit  1   a  outputs a current Im (a first current or primary AC current) through an output line Lm (a first output line) connected to the load M. The bridge circuit  1   b  is connected in parallel to the bridge circuit  1   a , and outputs a current Is (a second current or detection-use AC current) through an output line Ls (a second output line) connected at one end to the output line Lm. The current detection unit  1   c  is disposed in the output line Ls and detects the current Is. 
         [0031]    With respect to the connection relationships between the elements, a collector of the transistor Tr 1   a  is connected to a collector of the transistor Tr 1   b , cathodes of the diodes D 1   a  and D 1   b , and a P terminal. The P terminal corresponds to a power source terminal, for example. 
         [0032]    An emitter of the transistor Tr 2   a  is connected to an emitter of the transistor Tr 2   b , anodes of the diodes D 2   a  and D 2   b , and an N terminal. The N terminal corresponds to a GND terminal, for example. 
         [0033]    Meanwhile, an emitter of the transistor Tr 1   a , a collector of the transistor Tr 2   a , an anode of the diode D 1   a , and a cathode of the diode D 2   a  are connected to an output terminal OUT through the output line Lm, and the load M is connected to the output terminal OUT. 
         [0034]    Furthermore, an emitter of the transistor Tr 1   b , a collector of the transistor Tr 2   b , an anode of the diode D 1   b , and a cathode of the diode D 2   b  are connected to the output line Ls. One end of the output line Ls is connected to a node n on the output line Lm, and the current detection unit  1   c  is inserted into the output line Ls. 
         [0035]    Bases of the transistors Tr 1   a  and Tr 1   b  are connected to an output terminal of the driver circuit  30 - 1 , and bases of the transistors Tr 2   a  and Tr 2   b  are connected to an output terminal of the driver circuit  30 - 2 . 
         [0036]    Here, a current transformer is employed as the current detection unit  1   c . The current transformer is inserted onto the output line Ls, and current information of the current Is detected by the current transformer (i.e., a signal corresponding to the detected current Is) is inputted to, for example, a host control unit (controller)  4  (the structure of the current transformer will be described later with reference to  FIG. 3 ). 
         [0037]    On the basis of the current information, the control unit  4  generates drive control signals s 1  and s 2  for controlling switching of the transistors, and sends those signals to the driver circuits  30 - 1  and  30 - 2 , respectively. The driving of the high-side transistor Tr 1   a  in the bridge circuit  1   a  and the high-side transistor Tr 1   b  in the bridge circuit  1   b  is controlled by the same high-side driver circuit  30 - 1 . 
         [0038]    Meanwhile, the driving of the low-side transistor Tr 2   a  in the bridge circuit  1   a  and the low-side transistor Tr 2   b  in the bridge circuit  1   b  is controlled by the same low-side driver circuit  30 - 2 . 
         [0039]    Additionally, a surface area ratio between a first active surface area of first semiconductor devices (the transistors Tr 1   a  and Tr 2   a  and the diodes D 1   a  and D 2   a ) included in the bridge circuit  1   a  and a second active surface area of second semiconductor devices (the transistors Tr 1   b  and Tr 2   b  and the diodes D 1   b  and D 2   b ) included in the bridge circuit  1   b  is equal to a current ratio between the current Im and the current Is. Accordingly, the second active surface area is made smaller than the first active surface area and the current Im is made lower than the current Is (correspondence relationships between the surface area ratio and the current ratio will be described later with reference to  FIGS. 5 to 7 ). 
         [0040]    Thus the current detection device  1  is configured such that the bridge circuit  1   b  for detection current, which is constituted of the second semiconductor devices whose current capacities are lower than the first semiconductor devices in the bridge circuit  1   a , is connected in parallel to the bridge circuit  1   a , and detects the current Is (&lt;the current Im) flowing in the bridge circuit  1   b . This makes it possible to reduce the size of the current detection unit  1   c  that detects the current Is, which in turn makes it possible to reduce the scale of the device. 
         [0041]    A conventional current detection configuration and issues therewith to be solved will be described next, before going into detail about the technique according to the present invention. First, the configuration of an IPM that detects current by having a current transformer inserted onto a main line thereof will be described. 
         [0042]      FIG. 2  is a diagram illustrating an example of the configuration of a conventional inverter constituted by an IPM. This diagram illustrates a conventional configuration that detects current by having a current transformer inserted into a main line. 
         [0043]    An inverter  100  includes an IPM  110  and a host controller  40 . The IPM  110  includes diodes D 1  to D 6  and D 11  to D 16 , a capacitor C 1 , and IGBTs  11  to  16 . 
         [0044]    In the IPM  110 , the diodes D 1  to D 6 , which form a three-phase rectifying bridge circuit, the smoothing capacitor C 1 , the IGBTs  11  to  16 , which are semiconductor switches, and the diodes D 11  to D 16  are disposed between a high-voltage bus L 1  and a GND bus L 2 . Driver circuits  31  to  36  for driving the IGBTs  11  to  16 , respectively, are connected to the IGBTs  11  to  16 , respectively. 
         [0045]    A load M is connected to output terminals OUT 1  to OUT 3  of the IPM  110 . The IPM  110  transforms a DC high voltage flowing in the bus L 1  into three-phase alternating current and supplies power to the load M from AC main lines La, Lb, and Lc. 
         [0046]    The IPM  110  drives the load M by switching a current of an inductive load such as a motor on and off, and thus the diodes D 11  to D 16 , which are freewheeling diodes (FWDs), are connected to the IGBTs  11  to  16  in order to return the load current. 
         [0047]    In other words, counter EMF is produced from the inductive load such as a motor the instant the IGBTs  11  to  16  turn off, and thus the load current at this time is returned by connecting the diodes D 11  to D 16  in reverse-parallel to the IGBTs  11  to  16 , respectively. 
         [0048]    Connection relationships among the constituent elements will be described next. An anode of the diode D 1  is connected to an output end a 1  of an AC source A 0  and a cathode of the diode D 2 . An anode of the diode D 3  is connected to an output end a 2  of the AC source A 0  and a cathode of the diode D 4 . An anode of the diode D 5  is connected to an output end a 3  of the AC source A 0  and a cathode of the diode D 6 . 
         [0049]    Meanwhile, cathodes of the diodes D 1 , D 3 , and D 5 , one end of the capacitor C 1 , collectors of the IGBTs  11 ,  13 , and  15 , and cathodes of the diodes D 11 , D 13 , and D 15  are connected by the bus L 1  to a P terminal. 
         [0050]    Furthermore, anodes of the diodes D 2 , D 4 , and D 6 , another end of the capacitor C 1 , emitters of the IGBTs  12 ,  14 , and  16 , and anodes of the diodes D 12 , D 14 , and D 16  are connected by the bus L 2  to an N terminal. 
         [0051]    Meanwhile, an emitter of the IGBT  11  is connected to an anode of the diode D 11 , a collector of the IGBT  12 , a cathode of the diode D 12 , and the output terminal OUT 1 . The output terminal OUT 1  is connected to the load M by the main line La. 
         [0052]    An emitter of the IGBT  13  is connected to an anode of the diode D 13 , a collector of the IGBT  14 , a cathode of the diode D 14 , and the output terminal OUT 2 . The output terminal OUT 2  is connected to the load M by the main line Lb. Meanwhile, a current transformer CT 1   b  is inserted into the main line Lb between the output terminal OUT 2  and the load M. 
         [0053]    An emitter of the IGBT  15  is connected to an anode of the diode D 15 , a collector of the IGBT  16 , a cathode of the diode D 16 , and the output terminal OUT 3 . The output terminal OUT 3  is connected to the load M by the main line Lc. Meanwhile, a current transformer CT 1   c  is inserted into the main line Lc between the output terminal OUT 3  and the load M. 
         [0054]    The current transformers CT 1   b  and CT 1   c  are connected to the controller  40 . Drive control signals s 1  to s 6  from the controller  40  are connected to input terminals of the driver circuits  31  to  36 , respectively. Output terminals of the driver circuits  31  to  36  are connected to bases of the IGBTs  11  to  16 , respectively. 
         [0055]    Here, the controller  40  generates the drive control signals s 1  to s 6 . The drive control signals s 1  to s 6  are pulse signals (Pulse Width Modulation (PWM) signals) that repeatedly alternate between H level and L level, and pulsewidths thereof are determined on the basis of received current information. 
         [0056]    The drive control signals s 1  to s 6  sent from the controller  40  are inputted into the driver circuits  31  to  36 , respectively, and switching of the IGBTs  11  to  16  is controlled by the driver circuits  31  to  36  driving the gates thereof. 
         [0057]    In the switching control, for example, in the case where a gate driving level outputted from the driver circuit  31  is H level, a gate voltage is applied to the IGBT  11 , and the IGBT  11  turns on and enters a conductive state as a result. Meanwhile, in the case where the gate driving level outputted from the driver circuit  31  is L level, the IGBT  11  turns off and enters a non-conductive state as a result. The same switching control is carried out for the IGBTs  12  to  16  as well. 
         [0058]    Current detection by the current transformer will be described next.  FIG. 3  is a diagram illustrating a current transformer. A current transformer CT is a hollow coil in which an electric line is wrapped around a core material made from a ferromagnetic body. 
         [0059]    When a line L 11  in which current flows is passed through a hole of the current transformer CT, current can be obtained from a line L 12  connected to the current transformer CT at a winding number ratio of 1:n. For example, if a current i 1  flows in the line L 11 , a current i 2  flowing in the line L 12  will be i 2 =i 1 /n. Additionally, if a resistor R is connected to the line L 12  and the resistor R is taken as a load, a voltage V 2  in proportion to the current i 1  (=i 1 ·R/n) can be obtained. 
         [0060]    In this manner, information of the current detected by the current transformer CT is fed back to the controller  40 . On the basis of this current information, the controller  40  outputs the drive control signals s 1  to s 6  for controlling the IGBTs  11  to  16  on and off. 
         [0061]    Issues to be solved will be described next. As illustrated in  FIG. 2 , with the IPM  110 , the current transformer CT 1   b  is inserted into the main line Lb and the current transformer CT 1   c  is inserted into the main line Lc, and a load current (output current) is detected. 
         [0062]    Note that if the load currents flowing in two of the three main lines La, Lb, and Lc are known, the load current flowing in the remaining main line can be found through calculations, and it is for this reason that the current transformers CT 1   b  and CT 1   c  are inserted into the main lines Lb and Lc in the IPM  110  illustrated in  FIG. 2 . 
         [0063]    In this manner, the conventional IPM  110  is configured such that the load currents flowing in the main lines are detected by current transformers, which makes it necessary for the IPM  110  to handle thick main lines or a wide bus bar attached to the main lines. This results in an increase in the sizes of the current transformers and an increase in the space needed to dispose the current transformers, and thus it has been difficult to reduce the size of the device. 
         [0064]    Additionally, the greater the current rating of the IPM  110 , the more the widths of the main lines will increase. This increases the diameter of the holes in the current transformers, which in turn increases the sizes of the current transformers. 
         [0065]    Furthermore, it is desirable that parasitic inductance and parasitic impedance be reduced in order to realize lower noise, lower loss, and so on in the IPM  110 . In this case, the main lines, the bus bar, and so on are made wider and shorter, but making these elements wider also increases the sizes of the current transformers. There is thus a problem in that if an attempt is made to reduce the size it becomes difficult to reduce the parasitic elements. 
         [0066]    Meanwhile, according to the above-described Patent Document 1 (Japanese Patent Application Laid-Open Publication No. 2012-90499), the semiconductor device is divided into a main region and a sense region (a current detection region). Current is detected by obtaining current flowing in the sense region as detection current (sense current) and using a sense resistor to transform the current into a voltage signal. 
         [0067]    However, insulation is a problem when sending a current signal detected using the configuration according to Patent Document 1 (that is, current information transformed into a voltage signal by the sense resistor) to a host controller. For safety reasons, sufficient insulation is required between the host controller and the IPM. Thus components such as an insulation amplifier for transmitting the current information, as well as an A/D converter, a digital isolator, and the like for transmitting the current information as a digital signal, are necessary. 
         [0068]    Here, insulation amplifiers capable of transmitting signals with a high level of precision are expensive, and lead to an increase in costs. Furthermore, the number of components will increase both in the case where an insulation amplifier is used, and in the case where a configuration that transmits using digital values. 
         [0069]    Having been achieved in light of such circumstances, the present invention provides a current detection device and a semiconductor device that solve the above-described conventional issues with current detection, and achieve a reduction in the scales of the devices. 
         [0070]    A configuration and operations in the case where the current detection device  1  according to the present invention is applied in an IPM semiconductor device will be described next.  FIG. 4  is a diagram illustrating an example of the configuration of the IPM. Note that in  FIG. 4 , a rectifying bridge circuit that takes an AC voltage from an AC source (corresponding to the diodes D 1  to D 6  illustrated in  FIG. 2 ) and a smoothing capacitor (corresponding to the capacitor C 1  illustrated in  FIG. 2 ). 
         [0071]    An IPM  1 - 1  corresponding to the semiconductor device according to the present invention includes main bridge circuits  10   u ,  10   v , and  10   w , current detection bridge circuits  20   u ,  20   v , and  20   w , current transformers CT 1  to CT 3 , and driver circuits  31  to  36 . In the same manner as the configuration illustrated in  FIG. 2 , the IPM  1 - 1  operates a load M connected to output terminals OUT 1  to OUT 3  on the basis of switching control implemented by a host controller  40 . 
         [0072]    For a U phase, the main bridge circuit  10   u  (a U-phase main bridge circuit) and the current detection bridge circuit  20   u  (a U-phase current detection bridge circuit) are disposed as a U-phase bridge circuit  1   u.    
         [0073]    The main bridge circuit  10   u  includes IGBTs  11  and  12  and diodes D 1   l  and D 12  as first U-phase semiconductor devices. The current detection bridge circuit  20   u  includes IGBTs  21  and  22  and diodes D 21  and D 22  as second U-phase semiconductor devices. 
         [0074]    For a V phase, the main bridge circuit  10   v  (a V-phase main bridge circuit) and the current detection bridge circuit  20   v  (a V-phase current detection bridge circuit) are disposed as a V-phase bridge circuit  1   v.    
         [0075]    The main bridge circuit  10   v  includes IGBTs  13  and  14  and diodes D 13  and D 14  as first V-phase semiconductor devices. The current detection bridge circuit  20   v  includes IGBTs  23  and  24  and diodes D 23  and D 24  as second V-phase semiconductor devices. 
         [0076]    For a W phase, the main bridge circuit  10   w  (a W-phase main bridge circuit) and the current detection bridge circuit  20   w  (a W-phase current detection bridge circuit) are disposed as a W-phase bridge circuit  1   w.    
         [0077]    The main bridge circuit  10   w  includes IGBTs  15  and  16  and diodes D 15  and D 16  as first W-phase semiconductor devices. The current detection bridge circuit  20   w  includes IGBTs  25  and  26  and diodes D 25  and D 26  as second W-phase semiconductor devices. 
         [0078]    Note that Si (silicon), SiC (silicon carbide), or the like is used as the material of the IGBTs  11  to  16  and  21  to  26  in  FIG. 4 . The diodes D 11  to D 16  and D 21  to D 26 , meanwhile, are constituted of Si-FWDs or Schottky barrier diodes (SiC-SBDs). Additionally, although IGBTs are used as the semiconductor switches in  FIG. 4 , Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may be used instead. 
         [0079]    Here, the main bridge circuit  10   u  outputs a main current Im_U (a first U-phase current) through an output line Lm 1  (a first U-phase output line) connected to the load M. The current detection bridge circuit  20   u  is connected in parallel to the main bridge circuit  10   u , and outputs a sense current Is_U (a second U-phase current) through an output line Ls 1  (a second U-phase output line) connected at one end to the output line Lm 1 . 
         [0080]    The main bridge circuit  10   v  outputs a main current Im_V (a first V-phase current) through an output line Lm 2  (a first V-phase output line) connected to the load M. The current detection bridge circuit  20   v  is connected in parallel to the main bridge circuit  10   v , and outputs a sense current Is_V (a second V-phase current) through an output line Ls 2  (a second V-phase output line) connected at one end to the output line Lm 2 . 
         [0081]    The main bridge circuit  10   w  outputs a main current Im_W (a first W-phase current) through an output line Lm 3  (a first W-phase output line) connected to the load M. The current detection bridge circuit  20   w  is connected in parallel to the main bridge circuit  10   w , and outputs a sense current Is_W (a second W-phase current) through an output line Ls 3  (a second W-phase output line) connected at one end to the output line Lm 3 . 
         [0082]    The current transformer CT 1  (a U-phase current detection unit), which is a first current transformer, is disposed in the output line Ls 1  and detects the sense current Is_U. The current transformer CT 2  (a V-phase current detection unit), which is a second current transformer, is disposed in the output line Ls 2  and detects the sense current Is_V. 
         [0083]    The current transformer CT 3  (a W-phase current detection unit), which is a third current transformer, is disposed in the output line Ls 3  and detects the sense current Is_W. The flow of current is indicated by double-ended arrows in  FIG. 4 , and this is to indicate the flow of current from the bridge circuits to the load M and the return of current from the load M to the bridge circuits. 
         [0084]    Connection relationships among the constituent elements will be described next. Collectors of the IGBTs  11 ,  13 ,  15 ,  21 ,  23 , and  25  and cathodes of the diodes D 11 , D 13 , D 15 , D 21 , D 23 , and D 25  are connected by a bus L 1  to a P terminal. 
         [0085]    Emitters of the IGBTs  12 ,  14 ,  16 ,  22 ,  24 , and  26  and anodes of the diodes D 12 , D 14 , D 16 , D 22 , D 24 , and D 26  are connected by the bus L 2  to an N terminal. 
         [0086]    An emitter of the IGBT  21 , an anode of the diode D 21 , a collector of the IGBT  22 , and a cathode of the diode D 22  are connected by the output line Ls 1  of the current detection bridge circuit  20   u.    
         [0087]    An emitter of the IGBT  11 , an anode of the diode D 11 , a collector of the IGBT  12 , a cathode of the diode D 12 , and the output terminal OUT 1  are connected by the output line Lm 1  of the main bridge circuit  10   u . The current transformer CT 1  is inserted into the output line Ls 1 , and the output line Ls 1  and output line Lm 1  are connected by a node n 1 . 
         [0088]    Meanwhile, an emitter of the IGBT  23 , an anode of the diode D 23 , a collector of the IGBT  24 , and a cathode of the diode D 24  are connected by the output line Ls 2  of the current detection bridge circuit  20   v.    
         [0089]    An emitter of the IGBT  13 , an anode of the diode D 13 , a collector of the IGBT  14 , a cathode of the diode D 14 , and the output terminal OUT 2  are connected by the output line Lm 2  of the main bridge circuit  10   v . The current transformer CT 2  is inserted into the output line Ls 2 , and the output line Ls 2  and output line Lm 2  are connected by a node n 2 . 
         [0090]    Furthermore, an emitter of the IGBT  25 , an anode of the diode D 25 , a collector of the IGBT  26 , and a cathode of the diode D 26  are connected by the output line Ls 3  of the current detection bridge circuit  20   w.    
         [0091]    An emitter of the IGBT  15 , an anode of the diode D 15 , a collector of the IGBT  16 , a cathode of the diode D 16 , and the output terminal OUT 3  are connected by the output line Lm 3  of the main bridge circuit  10   w . The current transformer CT 3  is inserted into the output line Ls 3 , and the output line Ls 3  and output line Lm 3  are connected by a node n 3 . 
         [0092]    The current detection lines of the current transformers CT 1  to CT 3  are connected to the controller  40 . An output terminal of the driver circuit  31  is connected to bases of the IGBTs  11  and  21 , and an output terminal of the driver circuit  32  is connected to bases of the IGBTs  12  and  22 . 
         [0093]    An output terminal of the driver circuit  33  is connected to bases of the IGBTs  13  and  23 , and an output terminal of the driver circuit  34  is connected to bases of the IGBTs  14  and  24 . An output terminal of the driver circuit  35  is connected to bases of the IGBTs  15  and  25 , and an output terminal of the driver circuit  36  is connected to bases of the IGBTs  16  and  26 . 
         [0094]    Here, on the basis of the information of currents detected by the current transformers CT 1  to CT 3 , the controller  40  generates driving control signals (not illustrated) for controlling switching of the transistors and sends the generated signals to the driver circuits  31  to  36 , respectively. 
         [0095]    The driving of the IGBT  11  within the main bridge circuit  10   u  (a first U-phase high-side transistor) and the driving of the IGBT  21  of the current detection bridge circuit  20   u  (a second U-phase high-side transistor) are controlled by the same driver circuit  31  (a U-phase high-side driver circuit). 
         [0096]    The driving of the IGBT  12  within the main bridge circuit  10   u  (a first U-phase low-side transistor) and the driving of the IGBT  22  of the current detection bridge circuit  20   u  (a second U-phase low-side transistor) are controlled by the same driver circuit  32  (a U-phase low-side driver circuit). 
         [0097]    Meanwhile, the driving of the IGBT  13  within the main bridge circuit  10   v  (a first V-phase high-side transistor) and the driving of the IGBT  23  of the current detection bridge circuit  20   v  (a second V-phase high-side transistor) are controlled by the same driver circuit  33  (a V-phase high-side driver circuit). 
         [0098]    Additionally, the driving of the IGBT  14  within the main bridge circuit  10   v  (a first V-phase low-side transistor) and the driving of the IGBT  24  of the current detection bridge circuit  20   v  (a second V-phase low-side transistor) are controlled by the same driver circuit  34  (a V-phase low-side driver circuit). 
         [0099]    Furthermore, the driving of the IGBT  15  within the main bridge circuit  10   w  (a first W-phase high-side transistor) and the driving of the IGBT  25  of the current detection bridge circuit  20   w  (a second W-phase high-side transistor) are controlled by the same driver circuit  35  (a W-phase high-side driver circuit). 
         [0100]    Additionally, the driving of the IGBT  16  within the main bridge circuit  10   w  (a first W-phase low-side transistor) and the driving of the IGBT  26  of the current detection bridge circuit  20   w  (a second W-phase low-side transistor) are controlled by the same driver circuit  36  (a W-phase low-side driver circuit). 
         [0101]    As described above, the IPM  1 - 1  has a configuration in which in each phase, a current detection bridge circuit constituted of current detection IGBTs and diodes (FWDs) and a main bridge circuit constituted of main IGBTs and diode (FWDs) are connected in parallel. 
         [0102]    In other words, in the U phase, the current detection bridge circuit  20   u  including the IGBTs  21  and  22  and the diodes D 21  and D 22 , and the main bridge circuit  10   u  including the main IGBTs  11  and  12  and the diodes D 11  and D 12 , are connected in parallel. 
         [0103]    In the V phase, the current detection bridge circuit  20   v  including the IGBTs  23  and  24  and the diodes D 23  and D 24 , and the main bridge circuit  10   v  including the main IGBTs  13  and  14  and the diodes D 13  and D 14 , are connected in parallel. 
         [0104]    In the W phase, the current detection bridge circuit  20   w  including the IGBTs  25  and  26  and the diodes D 25  and D 26 , and the main bridge circuit  10   w  including the main IGBTs  15  and  16  and the diodes D 15  and D 16 , are connected in parallel. 
         [0105]    Additionally, the current transformer CT 1  is inserted into the output line Ls 1  of the current detection bridge circuit  20   u , and the current transformer CT 1  detects the sense current Is_U flowing in the current detection bridge circuit  20   u.    
         [0106]    Likewise, the current transformer CT 2  is inserted into the output line Ls 2  of the current detection bridge circuit  20   v , and the current transformer CT 2  detects the sense current Is_V flowing in the current detection bridge circuit  20   v.    
         [0107]    Furthermore, the current transformer CT 3  is inserted into the output line Ls 3  of the current detection bridge circuit  20   w , and the current transformer CT 3  detects the sense current Is_W flowing in the current detection bridge circuit  20   w.    
         [0108]    On the other hand, the output lines of the current detection bridge circuits in each phase are connected to the output lines of the main bridge circuits into which the current transformers have been inserted. In other words, the output line Ls 1  of the U-phase current detection bridge circuit  20   u  is connected to the output line Lm 1  of the main bridge circuit  10   u  at the node n 1  located beyond where the current transformer CT 1  is inserted. 
         [0109]    Additionally, the output line Ls 2  of the V-phase current detection bridge circuit  20   v  is connected to the output line Lm 2  of the main bridge circuit  10   v  at the node n 2  located beyond where the current transformer CT 2  is inserted. 
         [0110]    Furthermore, the output line Ls 3  of the W-phase current detection bridge circuit  20   w  is connected to the output line Lm 3  of the main bridge circuit  10   w  at the node n 3  located beyond where the current transformer CT 3  is inserted. 
         [0111]    As such, in the U phase, the sense current Is_U flowing in the current detection bridge circuit  20   u  is added to the main current Im_U flowing in the main bridge circuit  10   u , and thus a load current I_U outputted from the output terminal OUT 1  is I_U=Im_U+Is_U. 
         [0112]    Likewise, in the V phase, the sense current Is_V flowing in the current detection bridge circuit  20   v  is added to the main current Im_V flowing in the main bridge circuit  10   v , and thus a load current I_V outputted from the output terminal OUT 2  is I_V=Im_V+Is_V. 
         [0113]    Furthermore, in the W phase, the sense current Is_W flowing in the current detection bridge circuit  20   w  is added to the main current Im_W flowing in the main bridge circuit  10   w , and thus a load current I_W outputted from the output terminal OUT 3  is I_W=Im_W+Is_W. 
         [0114]    Next, a ratio between the main current Im and the sense current Is will be described. As described above, the IPM  1 - 1  is configured such that the load current outputted from a single output terminal is divided into a main current and a sense current flowing in two current paths, namely the output line of the main bridge circuit and the output line of the current detection bridge circuit, and the sense current is detected by the current transformer. 
         [0115]    In this case, a current ratio between the sense current flowing in the output line of the current detection bridge circuit and the main current flowing in the output line of the main bridge circuit is the same as a surface area ratio between a chip surface area of the semiconductor devices in the current detection bridge circuit and a chip surface area of the semiconductor devices in the main bridge circuit. Note that the surface area referred to here is, for example, an active surface area of the semiconductor devices (a surface area of active layers). 
         [0116]      FIGS. 5 to 7  are diagrams illustrating correspondence relationships between the surface area ratio and the current ratio. In the U phase illustrated in  FIG. 5 , a surface area ratio between a surface area of the IGBTs  21  and  22  and the diodes D 21  and D 22  of the current detection bridge circuit  20   u  (a second U-phase active surface area) and a surface area of the IGBTs  11  and  12  and the diodes D 11  and D 12  of the main bridge circuit  10   u  (a first U-phase active surface area) is 1:4, for example. 
         [0117]    Because the surface area ratio and the current ratio are equal, the current ratio between the sense current Is_U outputted from the current detection bridge circuit  20   u  and flowing in the output line Ls 1 , and the main current Im_U outputted from the main bridge circuit  10   u  and flowing in the output line Lm 1 , is also 1:4. 
         [0118]    Accordingly, the sense current Is_U in the U phase is ⅕ the total load current I_U in the U phase. In other words, Is_U=I_U/(1+4). Therefore, because the surface area ratio is determined at the design stage and is known, the U-phase load current I_U can be found by multiplying the current value detected by the current transformer CT 1  inserted into the output line Ls 1  of the current detection bridge circuit  20   u  by 5. 
         [0119]    Likewise, in the V phase illustrated in  FIG. 6 , a surface area ratio between a surface area of the IGBTs  23  and  24  and the diodes D 23  and D 24  of the current detection bridge circuit  20   v  (a second V-phase active surface area) and a surface area of the IGBTs  13  and  14  and the diodes D 13  and D 14  of the main bridge circuit  10   v  (a first V-phase active surface area) is 1:4, for example. 
         [0120]    Because the surface area ratio and the current ratio are equal, the current ratio between the sense current Is_V outputted from the current detection bridge circuit  20   v  and flowing in the output line Ls 2 , and the main current Im_V outputted from the main bridge circuit  10   v  and flowing in the output line Lm 2 , is also 1:4. 
         [0121]    Accordingly, the sense current Is_V in the V phase is ⅕ the total load current I_V in the V phase. In other words, Is_V=I_V/(1+4). Therefore, because the surface area ratio is determined at the design stage and is known, the V-phase load current I_V can be found by multiplying the current value detected by the current transformer CT 2  inserted into the output line Ls 2  of the current detection bridge circuit  20   v  by 5. 
         [0122]    Likewise, in the W phase illustrated in  FIG. 7 , a surface area ratio between a surface area of the IGBTs  25  and  26  and the diodes D 25  and D 26  of the current detection bridge circuit  20   w  (a second W-phase active surface area) and a surface area of the IGBTs  15  and  16  and the diodes D 15  and D 16  of the main bridge circuit  10   w  (a first W-phase active surface area) is 1:4, for example. 
         [0123]    Because the surface area ratio and the current ratio are equal, the current ratio between the sense current Is_W outputted from the current detection bridge circuit  20   w  and flowing in the output line Ls 3 , and the main current Im_W outputted from the main bridge circuit  10   w  and flowing in the output line Lm 3 , is also 1:4. 
         [0124]    Accordingly, the sense current Is_W in the W phase is ⅕ the total load current I_W in the W phase. In other words, Is_W=I_W/(1+4). Therefore, because the surface area ratio is determined at the design stage and is known, the W-phase load current I_W can be found by multiplying the current value detected by the current transformer CT 3  inserted into the output line Ls 3  of the current detection bridge circuit  20   w  by 5. 
         [0125]    To generalize the details described above, the surface area ratio between the surface area of the semiconductor devices in the current detection bridge circuit and the surface area of the semiconductor devices in the main bridge circuit is s:m. In this case, the current ratio between the sense current outputted from the current detection bridge circuit and the main current outputted from the main bridge circuit is s:m as well. Accordingly, a relational expression between the sense current Is and a total load current I is Is=I·s/(s+m). 
         [0126]    In this manner, the sense current flowing in the current detection bridge circuit and the main current flowing in the main bridge circuit are determined by the chip surface area ratio between the IGBTs and FWDs within the current detection bridge circuit and the IGBTs and FWDs within the main bridge circuit. Thus the total load current can be found by detecting the sense current using the current transformers and factoring in the surface area ratio of the semiconductor devices. 
         [0127]    Additionally, in this case, the chip surface area of the IGBTs and FWDs within the current detection bridge circuit is smaller than the chip surface area of the IGBTs and FWDs within the main bridge circuit. As a result, the sense current flowing in the current detection bridge circuit becomes lower than the main current flowing in the main bridge circuit (sense current Is&lt;main current Im). This makes it possible to employ small current transformers, which in turn makes it possible to reduce the scale of the device. 
         [0128]    For example, in the case where the IPM has a current rating of 300 A, an IPM in which a current transformer is inserted into the main line as illustrated in  FIG. 2  will require no less than 300 A as an input current range of the current transformer used therein, resulting in an increase in size. 
         [0129]    As opposed to this, with the IPM  1 - 1  illustrated in  FIG. 4 , the sense current flowing in the current detection bridge circuit connected in parallel to the main bridge circuit is detected. As such, in this example, a current transformer having an input current range of no less than ⅕ the current rating, namely 60 A, can be used. This makes it possible to use a small-size current transformer. 
         [0130]    Conventionally, the current information obtained by detecting the load current flowing in the main line is received by the controller, whereupon the controller generates the driving control signals to carry out switching control. As opposed to this, according to the present invention, the current information of the current flowing in the current detection bridge circuit is received by the controller, but as described above, the total load current can easily be calculated from the received current information. Thus no impediments to the switching control will arise. 
         [0131]    Additionally, according to the IPM  1 - 1  illustrated in  FIG. 4 , current detection is carried out for all three phases, namely U, V, and W, using the three current transformers CT 1  to CT 3 . The information of the detected currents is obtained for each of the phases using the information of the detected currents so that, for example, the controller can carry out protection control for overvoltage and the like in each phase. 
         [0132]    Thus in the case where the state of each phase is obtained from the current information, the current is detected for all of the three phases, namely U, V, and W (if the function is only for finding the load current, the configuration may be such that the current is detected for only two of the three phases). 
         [0133]    Variations on the current detection bridge circuit will be described next.  FIG. 8  is a diagram illustrating the configuration of a variation on the current detection bridge circuit. A current detection bridge circuit  20   u - 1  according to this variation has resistors Rgs 1  and Rgm 1  and resistors Rgs 2  and Rgm 2  as new elements. 
         [0134]    One end of the resistor Rgs 1  is connected to a gate of the IGBT  21 , and another end of the resistor Rgs 1  is connected to an output end of the driver circuit  31  and one end of the resistor Rgm 1 . Another end of the resistor Rgm 1  is connected to a gate of the IGBT  11 . 
         [0135]    One end of the resistor Rgs 2  is connected to a gate of the IGBT  22 , and another end of the resistor Rgs 2  is connected to an output end of the driver circuit  32  and one end of the resistor Rgm 2 . Another end of the resistor Rgm 2  is connected to a gate of the IGBT  12 . 
         [0136]    The stated resistors Rgs 1  and Rgm 1  and resistors Rgs 2  and Rgm 2  are gate resistors for timing adjustment. Providing such resistors makes it possible to eliminate gate timing differences. In other words, providing the resistors Rgs 1  and Rgm 1  reduces a gate driving timing difference for the IGBT  11  and the IGBT  21 . Likewise, providing the resistors Rgs 2  and Rgm 2  reduces a gate driving timing difference for the IGBT  12  and the IGBT  22 . 
         [0137]    Furthermore, providing the resistors Rgs 1  and Rgm 1  and the resistors Rgs 2  and Rgm 2  makes it possible to avoid a situation where current concentrates in the diodes. Although  FIG. 8  only illustrates the configuration of the variation on the U-phase current detection bridge circuit, the configuration is the same for the V- and W-phase current detection bridge circuits as well. 
         [0138]    Effects of the present invention will be described next, including points of difference from the conventional technique. Rather than detection a main current flowing in a main line using a current transformer as with the conventional IPM  110  illustrated in  FIG. 2 , the IPM  1 - 1  according to the technique of the present invention illustrated in  FIG. 4  is configured such that the bridge circuits are divided into main bridge circuits and current detection bridge circuits, and currents flowing in the current detection bridge circuits are detected by current transformers. 
         [0139]    The sense current flowing in the current detection bridge circuit is determined by a surface area ratio between the active surface area of the semiconductor devices constituting the current detection bridge circuit and the active surface area of the semiconductor devices constituting the main bridge circuit. 
         [0140]    Accordingly, if the design is such that the active surface area ratio is a ratio of approximately 1:several thousand, for example, the sense current can be brought to a small current on the order of 1/several thousand, compared to the main current. Accordingly, the sense current detected by the current transformer is much smaller than the main current, which makes it possible to use small current transformers. This in turn makes it possible to reduce the scale and costs of the device. 
         [0141]    Additionally, reducing the size of the current transformers makes integration into the IPM possible. In this case, no current transformer is inserted into the main line located between the output terminal of the IPM and the load, and thus a compact product form can be achieved. Furthermore, as an advantage for IPM developers, the current detection circuit can be integrated into a module, which makes designing a current detection circuit unnecessary. This can contribute to a reduction in the product design lead time. 
         [0142]    Furthermore, integrating the current transformers into the IPM makes it possible to make the main line, the bus bar, and so on short and thick, which in turn makes it easy to reduce parasitic elements. 
         [0143]    On the other hand, according to the above-described Patent Document 1, the semiconductor device is divided into a main region and a sense region (a current detection region), and current is detected by transforming current flowing in the sense region into a voltage signal using a sense resistor. 
         [0144]    As opposed to this, according to the present invention, bridge circuits in which the main bridge circuits and the current detection bridge circuits are connected in parallel are provided, and the configuration is such that currents flowing in the current detection bridge circuits are detected using current transformers rather than sense resistors. 
         [0145]    Additionally, the current transformer is a hollow coil in which an electric line is wrapped around a core material made from a ferromagnetic body, as illustrated in  FIG. 3 , and is a device in which the current transformer itself is insulated. 
         [0146]    Although Patent Document 1 requires a new component for insulation, the present invention uses current transformers and thus does not require insulating devices for signal transmission. Accordingly, increases in the number of components and costs can be suppressed. 
         [0147]    Furthermore, according to Patent Document 1, an emitter terminal is split between use for a main region and a sense region to obtain current, and thus a current detection circuit is provided for each semiconductor device. As opposed to this, the configuration of the present invention is such that the bridge circuit itself is divided into a main bridge circuit and a current detection bridge circuit, and a current transformer is inserted into the output line of that current detection bridge circuit. 
         [0148]    Thus comparing the three-phase full bridge circuit, while Patent Document 1 requires a maximum of six current detection circuits, the present invention only requires three current detection units (three current transformers), which makes it possible to achieve further miniaturization. 
         [0149]    While embodiments have been described thus far as examples, the configurations of the elements described in the embodiments can be replaced with other elements having equivalent functions. Other desired configurations, processes, and so on may be added as well. 
         [0150]    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.

Technology Classification (CPC): 7