Patent Abstract:
In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

Full Description:
This is a divisional of application Ser. No. 09/779,150, filed Feb. 8, 2001. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     This invention relates in general to integrated circuits, and more particularly to a microprocessor having hardware controlled power management. 
     BACKGROUND OF THE INVENTION 
     Increasingly, electronic circuit manufacturers need to reduce the power consumption of their boards. The conservation of power is particularly important in portable electronic devices, such as laptop or notebook computers, where the product is specifically designed for use in situations where power outlets are not available. Since laptop and notebook computers must operate using internal batteries or rechargeable battery packs for extended periods of time, the conservation of battery power becomes a primary concern. 
     In a laptop or notebook computer, the largest consumer of power is the display. The proportion of power consumed by the display will vary depending on the technology used. Thus, laptop and notebook computer manufacturers have disabled the power to the display during periods of inactivity. Decoupling the display from the power supply can be accomplished with fairly simple circuitry. 
     The next largest consumer of power on a laptop or notebook computer is the CPU motherboard microprocessor. Heretofore, computer manufacturers have used one or two techniques for reducing power consumption of the microprocessor during periods of inactivity. One technique reduces the speed of the system clock to a fraction of the normal operating frequency during periods of inactivity. Since the power consumption of the microprocessor is proportional to the frequency, reducing the frequency of the system clock also reduces the power consumption of the microprocessor. In an Intel 80386DX microprocessor (manufactured by Intel Corporation of Santa Clara, Calif.), reducing the operating frequency from 33 MHz to 4 MHz reduces the typical operating current of the microprocessor from 400 to approximately 100 milliamps. Nevertheless, an operating current of 100 milliamps still poses a large power drain on the battery. 
     A second technique for reducing power turns off the system clock during periods of inactivity. Turning off the system clock affects all circuitry on the motherboard. Consequently, the circuitry which disables the system clock must also save all pertinent information in the microprocessor and associated board logic and restore the data upon resumption of activity such that the state of the computer after resumption of the system clock will be identical to the state of the computer prior to disabling the system clock. As a result, this technique for consuming power is both costly because of the complicated circuitry and slow because of the need to store and restore the state of the computer. 
     Therefore, a need has arisen in the industry to provide a method and apparatus for conserving power in an electronic device which significantly reduces the power drain of the microprocessor without the need for complicated external circuitry. 
     SUMMARY OF THE INVENTION 
     In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal. 
     In accordance with one embodiment of the presently claimed invention, a method for externally controlling a processor used to execute instructions for data processing, including: 
     providing directly to the processor a low-power-mode control signal by 
     asserting the low-power-mode control signal in response to a detection of one or more conditions associated with having the processor enter a low power operational mode, and 
     de-asserting the low-power-mode control signal in response to a detection of another one or more conditions associated with having the processor exit the low power operational mode; and 
     receiving an acknowledgement signal from the processor subsequent to the assertion of the low-power-mode control signal. 
     In accordance with another embodiment of the presently claimed invention, a method for externally controlling a processor used to execute instructions for data processing, including: 
     providing directly to the processor a power consumption control signal by 
     asserting the power consumption control signal in response to a detection of one or more conditions associated with initiation of a power consumption reduction procedure, and 
     de-asserting the power consumption control signal in response to a detection of another one or more conditions associated with termination of the power consumption reduction procedure; and 
     receiving an acknowledgement signal from the processor subsequent to the assertion of the power consumption control signal. 
     In accordance with another embodiment of the presently claimed invention, a method for externally controlling a processor used to execute instructions for data processing, including: 
     providing directly to the processor a low-power-mode control signal which includes first and second values by 
     maintaining the first value in response to a detection of one or more conditions associated with having the processor enter a low power operational mode, and 
     maintaining the second value in response to a detection of another one or more conditions associated with having the processor exit the low power operational mode; and 
     receiving an acknowledgement signal from the processor subsequent to an attainment of the first low-power-mode control signal value. 
     In accordance with another embodiment of the presently claimed invention, a method for externally controlling a processor used to execute instructions for data processing, including: 
     providing directly to the processor a power consumption control signal which includes first and second values by 
     maintaining the first value in response to a detection of one or more conditions associated with initiation of a power consumption reduction procedure, and 
     maintaining the second value in response to a detection of another one or more conditions associated with termination of the power consumption reduction procedure; and 
     receiving an acknowledgement signal from the processor subsequent to an attainment of the first power consumption control signal value. 
     In accordance with another embodiment of the presently claimed invention, a method for externally controlling a processor used to execute instructions for data processing, including: 
     providing directly to the processor a low-power-mode control signal by 
     asserting the low-power-mode control signal in response to a detection of one or more conditions associated with having the processor enter a low power operational mode, and 
     de-asserting the low-power-mode control signal in response to a detection of another one or more conditions associated with having the processor exit the low power operational mode; 
     receiving an acknowledgement signal from the processor subsequent to the assertion of the low-power-mode control signal; and 
     providing to the processor a clock signal which is independent of the low-power-mode control signal. 
     In accordance with another embodiment of the presently claimed invention, a method for externally controlling a processor used to execute instructions for data processing, including: 
     providing directly to the processor a power consumption control signal by 
     asserting the power consumption control signal in response to a detection of one or more conditions associated with initiation of a power consumption reduction procedure, and 
     de-asserting the power consumption control signal in response to a detection of another one or more conditions associated with termination of the power consumption reduction procedure; 
     receiving an acknowledgement signal from the processor subsequent to the assertion of the power consumption control signal; and 
     providing to the processor a clock signal which is independent of the power consumption control signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 illustrates a block diagram of a computer system; 
     FIG. 2 illustrates a block diagram of the preferred embodiment of a microprocessor used in the computer system of FIG. 1; 
     FIG. 3 illustrates a detailed block diagram of portions of the microprocessor of FIG. 2 related to the power management circuitry; 
     FIG. 4 illustrates a flow chart describing a preferred embodiment of operation for reducing microprocessor power consumption; e 
     FIGS. 5 a-b  illustrate circuitry for enabling and disabling pins providing power management control signals; and 
     FIG. 6 illustrates a flow chart of the operation of software controlled embodiment for conserving microprocessor power consumption. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The preferred embodiment of the present invention and its advantages are best understood by referring to FIGS. 1-6 of the drawings, like numerals being used for like and corresponding parts of the various drawings. 
     FIG. 1 illustrates a block diagram of a computer system. The computer system  10  comprises a microprocessor  12  coupled to a memory subsystem  14 , BIOS ROM  16  and logic  18  (commonly referred to as the “chipset”). Microprocessor  12  is coupled to bus  20 . Bus  20  is used to communicate with a number of devices, shown in FIG. 1 as keyboard controller  22  video controller  24 , I/O circuitry  26  and disk controller  28 . Keyboard controller  22  is coupled to keyboard  29 . Disk controller  28  is coupled to hard disk  30  and floppy disk  32 . Video controller  24  is coupled to display  34 . An optional coprocessor  35  is coupled to microprocessor  12  and BIOS  16 . 
     The computer system  10  shown in FIG. 1 is a general-purpose architecture common to personal computers such as the IBM Personal Computer and compatibles. The BIOS  16  (basic input/output system) is typically a read-only memory which contains a set of programs for performing the basic control and supervision operations for the computer system  10 . The BIOS  16  acts as an interface between the computer circuitry and the application software being executed by the CPU  12 . Importantly, for power consumption purposes, the BIOS  16  and logic  18  monitor the circuitry to determine whether power consumption reduction procedures may be invoked. For example, the BIOS  16  and/or logic  18  may monitor the display  34  to determine whether its output has changed over a predetermined time period. If not, the BIOS  16  may invoke procedures to disable power to the display  34  (assuming computer system  10  is a portable computer) to conserve energy. Further, BIOS  16  monitors microprocessor  12  to determine whether the microprocessor can be idled without affecting operation of the computer system  10 . For example, the microprocessor  12  may be executing a routine to wait for a character from the keyboard. In this case, the operation of the microprocessor can be suspended until a key is pressed. 
     FIG. 2 illustrates a detailed block diagram of the various subcircuits of a preferred embodiment of the microprocessor  12 . For purposes of illustration, the microprocessor  12  will be described in connection with a microprocessor which is pin-compatible and instruction-compatible with the 80×86 family of processors by Intel Corporation, specifically the 80386 microprocessor although the invention could be used in other processors as well. The microprocessor  12  comprises three main functional groups: the core circuitry  36 , the memory circuitry  38  and the bus controller  40 . The core circuitry  36  includes an instruction queue  42  coupled to an internal data bus  44 . The output of the instruction queue  42  is coupled to a decoder  46  of the decode/sequence circuitry  47 . The decode/sequence circuitry  47  also includes a sequencer  50  and an exception processor  86 . The decoder  46  is coupled to a microcode ROM  48 , exception processor  86  and sequencer  50 . The sequencer  50  is also coupled to the microcode ROM  48  and to an execution unit  52 . The execution unit includes a limit unit  54 , a multiplier unit  56 , an adder unit  58 , a shift unit  60 , and a register file  62 . The execution unit  52  is coupled to the microcode ROM  48  and to multiplexer and I/O register circuitry  64 . The memory circuitry  38  comprises a memory management unit  66  coupled to a linear address bus  68  which is also connected to the execution unit  52  and an instruction/data cache memory  70 . Memory management unit  66  is further coupled to the internal data bus  44 . A prefetch unit  72  is coupled between the memory management unit  66  and the cache  70 . Bus controller  40  includes data buffers  74 , address buffers  76  and control circuitry  78 . The data buffers  74  are coupled to the data I/O pins D31-D0, the address buffers  76  are coupled to the address pins A31-A2 and BE3#-BE0#. A data address bus  80  couples the memory management unit  66 , the cache  70  and the address buffer  76 . An instruction address bus  82  couples the prefetch unit  72 , cache  70  and address buffer  76 . The data buffers  74  are coupled to the internal data bus  44 . 
     Clock module  84  receives an external clock signal (CLK 2 ) and generates CLKA (connected to the bus controller  40 ) and CLKB (coupled to the memory circuitry  38  and the core circuitry  36 ). CLKA and CLKB are both clock signals of one-half the frequency of CLK 2 . Clock module  84  receives control signals from bus controller  40 . 
     In operation, instructions are received by the microprocessor  12  from external memory under control of the memory management unit  66 . For enhanced performance, an instruction/data cache  70  caches instruction and data received through the bus controller  40 . Instructions are stored in the instruction queue and are subsequently translated by the decode circuitry  46  into microcode. The sequencer points to the next address in the microcode ROM  48  under control of the decoder  46  and the execution unit  52 . The execution unit  52  processes information under control of the microcode ROM  48 . 
     In the preferred embodiment, the microprocessor  12  has a static design, i.e., retention of data in the internal memories and registers of the microprocessor  12  is not dependent upon the clock signal. As described in greater detail hereinbelow, the clock module  84 , under control of the bus controller  40 , can disable clocks to the subcircuits of the core circuitry  36  and the memory circuitry  38  while continuing to generate clock signals to the bus controller  40 . Thus, during periods of inactivity, a large portion of the circuitry of the microprocessor may be suspended, thereby greatly reducing the power consumed by the microprocessor  12 . 
     FIGS. 3 and 4 describe the power reduction circuitry in greater detail. FIG. 3 is a block diagram showing control signals between various portions of the microprocessor. The bus controller  40  controls signals from external pins of the microprocessor  12 . A suspend e (SUSP) signal is input to the bus controller  40  and a suspend acknowledge (SUSPACK) is output from the bus controller  40 . A busy (BUSY) is received by the bus controller  40  from the coprocessor  35 . The bus e controller  40  also receives a maskable interrupt (INTR) and a non-maskable interrupt (NMI). The bus controller  40  outputs an interrupt (or “exception”) F_SUSP to the exception processor  86  and receives a control signal D_SUSPACK. The exception processor  86  also monitors the microcode ROM  48 , bus controller  40  and execution unit  52  to determine whether instructions are being executed. The exception processor  86  outputs a signal D_EXCEPTION to the sequencer  50  and receives a control signal U_AHALT from the microcode ROM  48 . The bus controller  40  outputs a control signal F_IDLE to the clock module  84 . 
     In operation, an external circuit (typically the BIOS  16  in conjunction with the logic  18 ) detects conditions where microprocessor operations could be suspended. Upon detection of such a situation, the external circuit asserts the SUSP pin (for example, by driving the SUSP pin with a logical low voltage). In response to the assertion of the SUSP signal, the bus controller  40 , in conjunction with the exception processor  86 , asserts the F_IDLE control signal to the clock module  84 . In response to the assertion of the F_IDLE signal, the clock module  84  disables the CLKB clock signals (by holding the disabled clock signal at a logical high or logical low voltage), while continuing to generating the CLKA clock signals. Since the design of the microprocessor is static, the memories do not require refreshing, and therefore suspending the clock will not result in a loss of data within the microprocessor  12 . The SUSPACK signal is asserted to notify external circuitry that the microprocessor  12  is in the suspended state. To resume operation of the microprocessor  12 , the SUSP signal is de-asserted (i.e., by applying a logical low voltage to the SUSP pin). 
     By suspending the clocks to the core circuitry  36  and memory circuitry  38 , a significant reduction in the power consumed by the microprocessor  12  is realized. The bus controller  40  remains active to observe and control I/O signals between the microprocessor  12  and the external circuitry. 
     FIG. 4 illustrates a flow chart showing a more detailed operation of the suspend mode. In decision block  88 , a loop is formed waiting for the SUSP signal to be asserted. In block  90 , after the SUSP signal is asserted, the bus controller  40  asserts the F_SUSP signal, which is coupled to the exception processor  86 . In block  92 , in response to the assertion of the F_SUSP signal, the instruction queue  42  is prevented from advancing new instructions. In block  94 , the decoder  46  ceases to advance new instructions to the microcode ROM  48  and any instructions currently being processed by the microcode ROM  48  or execution unit  52  (collectively, the “pipeline”) are completed, including any activity by the bus controller  40  related to the instructions in the pipeline. After all instructions in the pipeline have been executed, the control signal D_EXCEPTION is asserted by the exception processor  86  in block  96 . D_EXCEPTION is received by the sequencer  50  which initiates a power-down microcode routine (block  98 ) responsive to D_EXCEPTION. The power-down microcode routine prepares the microprocessor for suspend mode. In block  100 , the microcode ROM  48  asserts the control signal U_AHALT to the exception processor  86 . In response to receiving U_AHALT, the exception processor  86  asserts D_SUSPACK to the bus controller  40  in block  102 . In decision  104 , the bus controller  40 , after receiving D_SUSPACK from the exception processor, checks the busy signal received from the coprocessor. So long as the busy signal from the coprocessor is asserted, the SUSPACK signal to the external circuitry will not be asserted and CLKB will not be disabled. Once, the busy signal is de-asserted by the coprocessor, the SUSPACK signal is asserted by the bus controller  40  to alert the external circuitry that the microprocessor  12  is in a suspended state and that the coprocessor is not currently performing any calculations, and may also be suspended. In block  108 , F_IDLE is asserted by the bus controller  40  to the clock module  84 . In response to the assertion of the F_IDLE signal, the clock module  84  disables the CLKB in block  109 , thereby suspending operation of the core circuitry  36  and memory circuitry  38 . The bus controller  40  then waits until the SUSP signal is de-asserted in decision block  110 . Upon de-assertion of the SUSP signal, CLKB is resumed. 
     Most microprocessors, including the 80386, do not use all available pins on the chip package. Thus, the SUSP and SUSPACK signals may be communicated to and from the microprocessor  12  using unused pins, thereby maintaining compatibility with a pre-existing technology. Nonetheless, in the preferred embodiment, the pins for the SUSP and SUSPACK signals may be selectively enabled or disabled. In the preferred embodiment, the SUSP and SUSPACK pins are initially disabled, and the BIOS  16  must be configured to enable the pins in its start-up routine. To effect enabling or disabling of the SUSP and SUSPACK a pins, a control bit is provided which may be written to or read from via preselected I/O ports. The preferred embodiment of this aspect is shown in greater detail in connection with FIGS. 5 a-b.    
     In FIG. 5 a , a plurality of control registers are accessible using INDEX and DATA signals input to the control registers  120 . The majority of the registers (and bits thereof) are used for configuring the cache memory subsystem. For example, the control registers may be used to define non-cacheable regions of the main memory  14 , to select the cache method (direct-mapped or set associative), and to enable flushing of the cache memory  70  via an external pin. Each control register is accessible by writing the address (referred to herein as the INDEX) of the register to an I/O port, shown in FIG. 5 a  as I/O port  22   h . Another I/O port, shown herein as I/O port  23   h , is used to read or write data from the specified control register. In the preferred embodiment, each I/O port  23   h  operation is preceded by an I/O port  22   h  operation, otherwise the second and later I/O port  23   h  operation would be directed off-chip. In the illustrated embodiment of FIG. 5 a , the control registers each have an index between COh and CFh. 
     In FIG. 5 b , the register having an index of COh uses its least significant bit to control tri-state devices  124  and  126 . A bit equal to a logical high (i.e., a logical “1”) enables both tri-state devices  124  and  126  to provide transmission of the SUSP and SUSPACK signals. A logical “0” disables the SUSP and SUSPACK pins from the circuitry of the microprocessor  12 . 
     This aspect of the preferred embodiment ensures pin-compatibility with an existing pin structure. 
     FIG. 6 illustrates another aspect of the present invention wherein the operation of the microprocessor  12  may be suspended responsive to a software command. 80×86 devices support a “HALT” operation (Opcode F 4 ) which stops execution of all instructions and places the 80×86 in a HALT state. Execution is resumed responsive to a non-maskable interrupt (on the NMI pin) coupled to the bus controller  40 , an unmasked interrupt (on the INTR pin coupled to the bus controller  40 ) or a RESET. Normally, this instruction is used as the last instruction in a sequence which shuts down the system. 
     In the present invention, however, the HALT instruction has essentially the same consequence as asserting the SUSP pin. Thus, the BIOS  16  can issue a HALT instruction to the microprocessor  12 , thereby disabling CLKB. Again, disabling CLKB will result in a significant reduction of power consumed by the microprocessor  12 . 
     FIG. 6 illustrates a flow chart showing the operation of the HALT instruction in the preferred embodiment. Once a HALT instruction to the microprocessor  12  is received in decision block  130 , U_AHALT is asserted by the microcode ROM  48  in block  132 . In response to the U_AHALT signal from the microcode ROM, the exception processor  86  asserts D_SUSPACK. After checking the busy signal from the coprocessor in decision block  136 , the SUSPACK signal is asserted in block  140  by the bus controller  40  and the internal CLKB clock is disabled in block  142 . In decision block  144 , the microprocessor  12  remains in the suspended state until an interrupt is asserted in decision block  144 . Once the interrupt is asserted, the CLKB clock is enabled and processing continues. 
     The HALT instruction allows the BIOS  16  to place the microprocessor  12  in a suspended state without any additional hardware connections to the microprocessor. 
     The present invention provides significant advantages over the prior art. By suspending the clocks to the core circuitry and memory circuitry, a current consumption of less than  10  milliamps has been demonstrated. Since most BIOS programs support power conservation measures, the additional coding for supporting the SUSP and SUSPACK signals is relatively simple. Alternatively, the chipset logic  18  can be modified to support the SUSP and SUSPACK signals. Further, since the SUSPACK, in the preferred embodiment, is not asserted until after coprocessor operations are completed, the BIOS does not have to provide additional circuitry or codes for monitoring the coprocessor. Further, the power saving circuitry may be provided on the microprocessor chip without sacrificing pin-compatibility. Additionally, by using the enhanced HALT command, the microprocessor may be operated in a suspended state without any hardware interaction, other than asserting an interrupt to bring the microprocessor  12  out of a suspended state. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Classification (CPC): 8