Patent Abstract:
A single-phase DC-AC converter generates an AC voltage with five levels at the output converter side by using four controlled power switches. The converter has a relationship between the number of levels per number of switches (nL/nS) of five to four. The converter reduces the number of semiconductor devices required to generate a high number of levels at the output converter side, requires only one DC source to generate an AC output, and operates with high efficiency.

Full Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority to U.S. Provisional Application No. 61/868,393, which is entitled “Five-Level Four-Switch DC-AC Converter,” and was filed on Aug. 21, 2013, the entire contents of which are hereby incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    The present description generally relates to electrical power conversion systems including systems that convert direct current (DC) voltages to alternating current (AC) voltages. 
       BACKGROUND 
       [0003]    Inverter circuits are known to the art for the conversion of a DC voltage to an output AC voltage. Inverters that convert a DC source to an AC voltage with multiple output levels are of interest to a wide range of applications, including low-power applications. Existing inverter circuits that are configured to generate multiple output levels often require a large number of switching transistors and other components including, but not limited to, capacitors and transformers to generate an AC voltage from a DC input source.  FIG. 5  depicts examples of prior art converters that generate a five-level voltage for a single-phase output. The number of levels per number of switches (nL/nS) for the prior art configurations are given by 5/8 and 5/6. An improved inverter circuit that generates multi-level AC output voltages in an efficient manner would be beneficial to improve quality of the output voltage and efficiency of the inverter circuit. 
       SUMMARY 
       [0004]    A single-phase DC-AC converter is configured to generate an AC output voltage with five levels at the output converter side. An illustrative embodiment of the converter that is depicted in  FIG. 1  includes an optimized relationship between the number of levels per number of switches: nL/nS=5/4. Besides the nL/nS, the converter also includes a reduced number of semiconductor devices while maintaining a high number of levels at the output converter side, only requires one DC source without any need to balance the capacitor voltages, and operates with high efficiency. 
         [0005]    In one embodiment a power converter generates an AC output voltage from a DC voltage. The power converter includes a first switching device with a first terminal electrically connected to a first terminal of a split-wound coupled inductor and with a second terminal configured to be connected to a direct current (DC) voltage source, a second switching device with a first terminal electrically connected to a second terminal of the split-wound coupled inductor and with a second terminal configured to be connected to the direct current (DC) voltage source, a third switching device with a first terminal electrically connected to the second terminal of the first switching device and with a second terminal configured to be connected to a load, a fourth switching device with a first terminal electrically connected to the second terminal of the second switching device and with a second terminal configured to be connected to the load, and a controller operatively connected to the first switching device, second switching device, third switching device, and fourth switching device. The controller is configured to operate the first switching device, second switching device, third switching device, and fourth switching device to generate an alternating current (AC) output voltage that is supplied to the load through the second terminals of the third switching device and the fourth switching device and through a third terminal of the split-wound coupled inductor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a schematic diagram of a converter circuit that generates an AC output voltage with five levels using four switching elements. 
           [0007]      FIG. 2  is a set of schematic diagrams that depict a portion of the circuit of  FIG. 1  in different operating modes. 
           [0008]      FIG. 3  is a schematic diagram depicting pulse with modulation (PWM) controls for operating switching elements in the circuit of  FIG. 1  and  FIG. 2 . 
           [0009]      FIG. 4  is a set of graphs depicting simulated and measured results for DC to AC inversion using the circuit of  FIG. 1  and  FIG. 2 . 
           [0010]      FIG. 5  is a set of schematic diagrams for prior art inverter circuits. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    For a general understanding of the environment for the system and method disclosed herein as well as the details for the system and method, reference is made to the drawings. In the drawings, like reference numerals have been used throughout to designate like elements. 
         [0012]    Referring to  FIG. 1 , a converter circuit 100 includes four switching power devices (S 1a , S 2a , S 1b , and S 2b ), two diodes (D 1  and D 2 ) and one split-wound coupled inductor (L 1 ). The switching device S 1a  has a first terminal that is connected to a first terminal a 1  in the split-wound coupled inductor L 1  and a second terminal connected to a DC voltage source V dc . The switching device S 2a  has a first terminal that is connected to a second terminal a 2  in the split-wound coupled inductor L 1  and a second terminal connected to the DC voltage source V dc . The third switching device S 1b  has a first terminal that is connected to the second terminal of the first switching device S 1a  and a second terminal that is connected to a load V l . The fourth switching device S 2b  has a first terminal that is connected to the second terminal of the second switching device S 2a  and a second terminal that is connected to the load υ l . The split-wound coupled inductor L i  has a third terminal a that is between the windings connected to the terminals a1 and a2. The third terminal a is connected to the load υ l . The diode D 1  includes a cathode that is connected to the first terminal of the first switching device S 1a  and an anode that is connected to the DC voltage source V dc . The diode D 2  includes an anode that is connected to the first terminal of the second switching device S 2a  and a cathode that is connected to the DC voltage source V dc . 
         [0013]    In one embodiment the switching power devices S 1a , are controlled power transistors, such as metal oxide field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) and bipolar junction transistors (BJTs). In the description below, the state of the switches is represented by a binary variable, where S j =0 means an open switch and S j =1 means a closed switch (with j=1a, 2a, 1b and 2b). As described in more detail below, the switching devices S 1a , S 2a , S 1b , and S 2b  are closed and opened using pulse width modulation (PWM) control signals to enable the circuit  100  to generate an AC output voltage from the DC voltage that is supplied by the DC source V dc .  FIG. 1  depicts a PWM controller  150  that is operatively connected to the switching devices S 1a , S 2a , S 1b , and S 2b . In an embodiment where the switching devices S 1a , S 2a , S 1b , and S 2b  are transistors, the PWM controller  150  generates signals that control the base or gate of the transistors to switch the transistors on and off. 
         [0014]      FIG. 2  depicts different configurations of the switching devices S 1a  and S 2a  from the circuit  100  of  FIG. 1 . The circuit configuration  204  depicts a continuous conduction mode through the coupled-windings L 1 . The circuit configuration  208  depicts a configuration where the switching devices S 1a  and S 2a  are both open (0-0). The circuit configuration  212  depicts a configuration where the switching device S 1a  is open and the switching device and S 2a  is closed (0-1). The circuit configuration  216  depicts a configuration where the switching device S 1a  is closed and the switching device and S 2a  is open (1-0). The circuit configuration  220  depicts a configuration where the switching devices S 1a  and S 2a  are both closed (1-1). 
         [0015]    In the circuit configurations of  FIG. 1  and  FIG. 2 , the voltages υ a10  and υ a20  (voltages from the nodes a1 and a2 to zero) can be expressed as a function of the state of the switching devices with the following equations: 
         [0000]      υ a10 =S 1a V dc  
 
         [0000]      υ a20 =(1 −S   2a ) V   dc  
 
         [0000]    Similarly, the voltage υ b0  is the voltage from node b to zero and is expressed with the following equation: υ b0 =S 1b V dc , where S 1b =1−S 2b , where the switches S 1b  and S 2b  are operate in a complementary configuration to avoid a short circuit of the DC source. 
         [0016]    In the circuit  100 , the voltage υ a0  is provided by the following equation: 
         [0000]    
       
         
           
             
               v 
               
                 a 
                  
                 
                     
                 
                  
                 0 
               
             
             = 
             
               
                 1 
                 2 
               
                
               
                 ( 
                 
                   
                     v 
                     
                       a 
                        
                       
                           
                       
                        
                       10 
                     
                   
                   + 
                   
                     v 
                     
                       a 
                        
                       
                           
                       
                        
                       20 
                     
                   
                 
                 ) 
               
             
           
         
       
     
         [0017]    The load voltage υ l , which is the AC output voltage that is delivered to a load, is determined using υ a0  and υ b0  using the following equation: 
         [0000]      υ l =υ a0 −υ b0 .
 
         [0018]    Table 1 lists different voltages of the converter circuit when the switching devices are in different states. The AC voltage that is generated at the converter output has five different levels (V dc , V dc /2, 0, −V dc /2, −V dc ). 
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Load Voltage as a Function of Switching State 
               
             
          
           
               
                 S 1a   
                 S 2a   
                 S 1b   
                 S 2b   
                 v a10   
                 v a20   
                 v a0   
                 v b0   
                 v ind   
                 v l   
               
               
                   
               
               
                 0 
                 0 
                 0 
                 1 
                 0 
                 V dc   
                 V dc /2 
                 0 
                 −V dc   
                 V dc /2 
               
               
                 0 
                 0 
                 1 
                 0 
                 0 
                 V dc   
                 V dc /2 
                 V dc   
                 −V dc   
                 −V dc /2 
               
               
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 V dc   
                 0 
                 −V dc   
               
               
                 1 
                 0 
                 0 
                 1 
                 V dc   
                 V dc   
                 V dc   
                 0 
                 0 
                 V dc   
               
               
                 1 
                 0 
                 1 
                 0 
                 V dc   
                 V dc   
                 V dc   
                 V dc   
                 0 
                 0 
               
               
                 1 
                 1 
                 0 
                 1 
                 V dc   
                 0 
                 V dc /2 
                 0 
                 V dc   
                 V dc /2 
               
               
                 1 
                 1 
                 1 
                 0 
                 V dc   
                 0 
                 V dc /2 
                 V dc   
                 V dc   
                 −V dc /2 
               
               
                   
               
             
          
         
       
     
         [0019]    In the circuit  100 , the split-wound coupled inductor L 1  is operated in a continuous conduction mode. The voltage level υ ind  in the split-wound coupled inductor L 1  is provided by the following equation: 
         [0000]      υ ind =υ a10   −V   a20 .
 
         [0020]    As depicted in Table 1, the modulation parameters for operating the switching device S 1b  are defined with the following rules: (i) S 1b =1 if υ l *&lt;0 and S 1b =0 if υ l *≧0. The leg b in the circuit  100  operates at the frequency of the output AC load (e.g. 50 Hz or 60 Hz for many electrical grids), and the comparatively low frequency of the switching leg b reduces the switching losses in the circuit  100 . 
         [0021]    During operation of the circuit  100 , the signals that control the operation of the switching devices S 1a , S 2a , S 1b , and S 2b  produce an average load voltage υ l * and average inductor voltage υ ind * are characterized by the following instantaneous time equations: 
         [0000]    
       
         
           
             
               v 
               l 
               * 
             
             = 
             
               
                 
                   S 
                   
                     1 
                      
                     
                         
                     
                      
                     a 
                   
                 
                  
                 
                   
                     V 
                     dc 
                   
                   2 
                 
               
               + 
               
                 
                   ( 
                   
                     1 
                     - 
                     
                       S 
                       
                         2 
                          
                         a 
                       
                     
                   
                   ) 
                 
                  
                 
                   
                     V 
                     dc 
                   
                   2 
                 
               
               - 
               
                 
                   S 
                   
                     1 
                      
                     b 
                   
                 
                  
                 
                   V 
                   dc 
                 
               
             
           
         
       
       
         
           
             
               v 
               ind 
               * 
             
             = 
             
               
                 
                   S 
                   
                     1 
                      
                     a 
                   
                 
                  
                 
                   V 
                   dc 
                 
               
               - 
               
                 
                   ( 
                   
                     1 
                     - 
                     
                       S 
                       
                         2 
                          
                         a 
                       
                     
                   
                   ) 
                 
                  
                 
                   V 
                   dc 
                 
               
             
           
         
       
     
         [0022]    The previous equations are instantaneous time equations that describe the states of the switching devices S 1a  and S 2a  at single point in time. To control the circuit over time, a controller operates the switching devices using a pulse width modulation (PWM) control scheme in which each of the switching devices S 1a , S 1b , S 2a , S 2b  are switched between closed and opened states with duty cycles of d 1a , d 2a , d 1b , and d 2b , respectively. As described above, the PWM cycles for the transistors S 1b  and S 2b  are complementary where S 1b  is closed whenever S 2b  is opened, and vice-versa. The duty cycles for each of the switching devices are described in the following equations: 
         [0000]    
       
         
           
             
               d 
               
                 1 
                  
                 a 
               
             
             = 
             
               
                 1 
                 
                   T 
                   s 
                 
               
                
               
                 
                   ∫ 
                   t 
                   
                     t 
                     + 
                     
                       T 
                       s 
                     
                   
                 
                  
                 
                   
                     
                       S 
                       
                         1 
                          
                         a 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                    
                   
                      
                     t 
                   
                 
               
             
           
         
       
       
         
           
             
               d 
               
                 2 
                  
                 a 
               
             
             = 
             
               
                 1 
                 
                   T 
                   s 
                 
               
                
               
                 
                   ∫ 
                   t 
                   
                     t 
                     + 
                     
                       T 
                       s 
                     
                   
                 
                  
                 
                   
                     
                       S 
                       
                         2 
                          
                         a 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                    
                   
                      
                     t 
                   
                 
               
             
           
         
       
       
         
           
             
               d 
               
                 1 
                  
                 b 
               
             
             = 
             
               
                 1 
                 
                   T 
                   s 
                 
               
                
               
                 
                   ∫ 
                   t 
                   
                     t 
                     + 
                     
                       T 
                       s 
                     
                   
                 
                  
                 
                   
                     
                       S 
                       
                         1 
                          
                         b 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                    
                   
                      
                     t 
                   
                 
               
             
           
         
       
       
         
           
             
               d 
               
                 2 
                  
                 b 
               
             
             = 
             
               
                 
                   1 
                   
                     T 
                     s 
                   
                 
                  
                 
                   
                     ∫ 
                     t 
                     
                       t 
                       + 
                       
                         T 
                         s 
                       
                     
                   
                    
                   
                     
                       
                         S 
                         
                           2 
                            
                           b 
                         
                       
                        
                       
                         ( 
                         t 
                         ) 
                       
                     
                      
                     
                        
                       t 
                     
                   
                 
               
               = 
               
                 1 
                 - 
                 
                   d 
                   
                     1 
                      
                     b 
                   
                 
               
             
           
         
       
     
         [0000]    The following equations describe the average load voltage υ l * and average inductance voltage υ ind * in conjunction with the duty cycles: 
         [0000]    
       
         
           
             
               
                 2 
                  
                 
                   v 
                   l 
                   * 
                 
               
               
                 V 
                 dc 
               
             
             = 
             
               
                 d 
                 
                   1 
                    
                   a 
                 
               
               + 
               1 
               - 
               
                 d 
                 
                   2 
                    
                   a 
                 
               
               - 
               
                 2 
                  
                 
                   d 
                   
                     1 
                      
                     b 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 ind 
                 * 
               
               
                 V 
                 dc 
               
             
             = 
             
               
                 d 
                 
                   1 
                    
                   a 
                 
               
               + 
               
                 d 
                 
                   2 
                    
                   a 
                 
               
               - 
               1 
             
           
         
       
     
         [0000]    The terms d 1a  and d 2a  from the preceding equations are expressed in the following equations: 
         [0000]    
       
         
           
             
               d 
               
                 1 
                  
                 a 
               
             
             = 
             
               
                 
                   
                     v 
                     ind 
                     * 
                   
                   + 
                   
                     2 
                      
                     
                       v 
                       l 
                       * 
                     
                   
                 
                 
                   2 
                    
                   
                     V 
                     dc 
                   
                 
               
               + 
               
                 S 
                 
                   1 
                    
                   b 
                 
               
             
           
         
       
       
         
           
             
               d 
               
                 2 
                  
                 a 
               
             
             = 
             
               
                 
                   
                     v 
                     ind 
                     * 
                   
                   + 
                   
                     2 
                      
                     
                       v 
                       l 
                       * 
                     
                   
                 
                 
                   2 
                    
                   
                     V 
                     dc 
                   
                 
               
               + 
               
                 ( 
                 
                   1 
                   - 
                   
                     S 
                     
                       1 
                        
                       b 
                     
                   
                 
                 ) 
               
             
           
         
       
     
         [0023]    In the circuit  100 , the controller  150  is operatively connected to the power switching devices S 1a , S 2a , S 1b , and S 2b  to switch the devices on (closed switch) and off (opened switch) into the states that are depicted in Table 1. In one embodiment, the controller  150  generates the PWM signals that control the base or gate of the power transistors S 1a , S 2a , S 1b , and S 2b  to switch the transistors on and off  FIG. 3  depicts schematic diagrams  304  and  308  of circuits that are implemented in the controller  150  to generate the PWM control signals. The control circuits  304  and  308  generate PWM control signals with duty cycles that correspond to the equations listed above for d 1a , d 2a , d 1b , and d 2b . The controller  150  implements the functionality that is depicted in the schematic circuits  304  and  308  using, for example, discrete analog and digital circuit components, or as stored program instructions that are executed by a microcontroller or other appropriate digital processor. 
         [0024]      FIG. 4  depicts a graph  402  of simulated results including a simulated AC output voltage waveform  404  and output current waveform  408 . The graph  420  depicts measured output waveforms from an embodiment of the circuit  100  including a measured AC output voltage waveform  424  and measured AC output waveform  428 . The measured AC output waveform  428  is formed in a sinusoidal AC output waveform at the predetermined AC output voltage frequency with the five discrete output voltage levels that are described above in Table 1. In the illustrative example of  FIG. 4 , the DC voltage level is 400V, and the measured AC output voltage swings between +400V and −400V with the sinusoidal output waveform at the predetermined AC waveform frequency. As depicted in  FIG. 4 , the output voltage of the AC voltage has five voltage levels from the positive peak voltage amplitude to the negative peak voltage amplitude. 
         [0025]    While the embodiments have been illustrated and described in detail in the drawings and foregoing description, the same should be considered as illustrative and not restrictive in character. The reader should understand that only the preferred embodiments have been presented and that all changes, modifications and further applications that come within the spirit of the scope of the claims presented below are desired to be protected.

Technology Classification (CPC): 7