Patent Abstract:
To avoid burning out a capacitor in a synchronous rectification type DC-to-DC converter due to overvoltages, the synchronous rectification type DC-to-DC converter includes a storage unit storing therein power derived from a power supply, switching elements connecting and disconnecting respective signal paths from power and ground, and a control unit controlling the connecting/disconnecting operations of the switching elements to maintain a voltage output from the storage unit at a predetermined value. The DC/DC converter also includes an overvoltage detecting unit monitoring a voltage derived from the power supply to thereby output an alarm signal when the voltage derived from the power supply exceeds a preselected voltage value, a shortcircuiting unit influencing the connecting conditions of the switching elements when the alarm signal from the overvoltage detecting unit is input therein, whereby the voltage derived from the power supply is shortcircuited, and an interrupting unit interrupting one of the signal paths by the power shortcircuited by the shortcircuiting unit.

Full Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 08/694,581 filed Aug. 9, 1996, now U.S. Pat. No. 6,046,896, the contents of which are hereby incorporated by reference. This application is related to co-pending U.S. application Ser. No. 09/235,729 filed Jan. 22, 1999, the contents of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1). Field of the Invention 
     The present invention generally relates to a DC-to-DC converter. More specifically, the present invention is directed to a voltage drop type DC-to-DC converter capable of preventing overvoltages appearing in an input voltage and an output voltage. 
     2). Description of the Prior Art 
     Portable type electronic appliances such as notebook type personal computers install cells as power supplies thereof. To operate these portable type electronic appliances under stable conditions, these cells are preferably capable of supplying constant voltages. 
     To the contrary, general-purpose cells inherently owns such a characteristic that output voltages are gradually lowered during discharge operation. Therefore, portable type electronic appliances are equipped with DC-to-DC converters capable of maintaining the output voltages of these cells at constant values. 
     The operation time during which an electronic appliance can be effectively operated by a cell is one of the major important factors to evaluate the performance of this portable type electronic appliance. To maintain such an effective operation time as long as possible, power consumption by this portable type electronic appliance should be, of course, reduced, and furthermore, the converting efficiency of the DC/DC converter should be increased. This is because the converting efficiency of this DC/DC converter is directly reflected onto the power consuming ratio of the cell. 
     As one method for increasing the converting efficiency of the DC/DC converter, the synchronous rectification type DC/DC converter may be utilized. When this synchronous rectification type DC/DC converter is utilized, the resultant converting efficiency may be increased by approximately 10%, as compared with the conventional type DC/DC converter. 
     Also, the converting efficiency of the DC/DC converter may be influenced by the performance of a capacitor employed in this DC/DC converter. For instance, in the current DC/DC converters, signals are oscillated in high frequencies in order to increase the converting efficiency and also-to make the entire appliance compact. In such a high-frequency type DC/DC converter, a smoothing capacitor is required in an output unit thereof so as to reduce phase errors. 
     A smoothing capacitor includes an equivalent series resistor (ESR). When the resistance value of this equivalent series resistor (ESR) is large, the converting efficiency of the DC/DC converter would be deteriorated. 
     Therefore, such a capacitor is required, in which an equivalent series resistor (ESR) having a small resistance value is included, in order to increase the converting efficiency Qf the DC/DC converter. 
     As the capacitor in which the equivalent series resistor having the small resistance value is included, there is an organic capacitor. 
     When an organic capacitor is employed as a smoothing capacitor, since the converting efficiency of the DC/DC converter is increased, heat dissipation is reduced even when a large current flows. As a result, the DC/DC converter with employment of the organic capacitor may be utilized as such a DC/DC converter capable of allowing large currents, for instance, 3 to 5 amp. 
     In the case that the DC/DC converter with using the organic capacitor as the smoothing capacitor is employed in the apparatus capable of allowing large currents, it is preferable to use an organic capacitor capable of allowing high ripple components as the capacitor employed in the input unit of the DC/DC converter. 
     On the other hand, as explained above, although organic capacitors own great merits such as high frequency characteristics and temperature characteristics, these organic capacitors have such demerits that-the organic capacitors are easily destroyed by receiving overvoltages, resulting in fire and smoke explosion. 
     Accordingly, when an organic capacitor is employed in a DC/DC converter, an overvoltage protection mechanism is necessarily required for this organic capacitor. 
     As the factors why overvoltages are produced in DC/DC converters, various cases may be conceived. That is, the output voltage is increased due to circuit failure of this DC/DC converter. Also, since the cells and the recharging devices malfunction, or improper cells/recharging devices are employed, the voltage inputted into the DC/DC converter is increased to produce the overvoltage. 
     First, when the output voltage of the DC/DC converter becomes the overvoltage, the smoothing capacitor employed in the output unit of this DC/DC converter must be protected. 
     As the method for protecting the smoothing capacitor, a zener diode is employed in the output unit of the DC/DC converter. In this method, when the voltage outputted from the DC/DC converter exceeds the normal voltage of this zener diode, the zener diode would be burned out, so that a shortcircuit is established between this DC/DC converter and the load. 
     In this shortcircuit case, since the current flow is stopped due to this shortcircuit established between the DC/DC converter and the load, it is possible to prevent the overvoltage from being applied to the organic capacitor. 
     On the other hand, when the zener diode is used to protect the capacitor, if the zener diode fails in the shortcircuit mode, then this shortcircuited zener diode can having the protection function. To the contrary, when this zener diode fails in the opencircuit mode, the organic capacitor provided in the output unit of the DC/DC converter would be burned out, resulting in fire and smoke explosion. 
     Furthermore, it is practically impossible to define whether the zener diode fails in the opencircuit mode, or the shortcircuit mode. As a consequence, it is improper to utilize such a zener diode as the protection circuit of the DC/DC converter. 
     On the other hand, in order to prevent the organic capacitor from being burned out by receiving the overvoltage, it is conceivable to employ such a method for using a high withstanding voltage type organic capacitor. However, since such a high withstanding voltage type organic capacitor owns a small capacitance, a plurality of organic capacitors are necessarily employed so as to obtain a desired capacitance. Accordingly, the overall circuit would be made bulky. In addition, there is another problem that since the high withstanding voltage organic capacitor owns the high equivalent series resistor (ESR), the converting efficiency of the DC/DC converter would be lowered. 
     Also, to prevent the organic capacitor from being burned out by receiving the overvoltage, there is another method for providing a burning preventing fuse with each of all organic capacitors used in the DC/DC converter. However, this method has other demerits that a total number of constructive elements of this DC/DC converter is increased, and at the same time, the manufacturing cost of this DC/DC converter is increased. Moreover, when the fuses are provided with these organic capacitors respectively, there is another problem that the converting efficiency of the DC/DC converter is lowered due to the fuse resistance values. 
     In addition, since other organic capacitors are also employed in the input unit of the DC/DC converter, this organic capacitor must be protected from the overvoltages. 
     SUMMARY OF THE INVENTION 
     The present invention has-an object to provide a compact synchronous rectification mode voltage drop type DC/DC converter with a high converting efficiency. Concretely speaking, this DC/DC converter can be constructed of a simple circuit arrangement, and can be protected from an overvoltage appearing in an input voltage thereto. Also, this DC/DC converter can be protected from fire and smoke explosion of a capacitor caused by receiving overvoltages. 
     A DC/DC converter, according to the present invention, is such a synchronous rectification type DC-to-DC converter including: storage means for storing therein power derived from a power supply; a first switch element provided on a first signal path used to connect said power supply with said storage means, for connecting/disconnecting said first signal path; a second switch element provided on a second signal path used to connect said first switch element with said storage means, for connecting/disconnecting said second signal path to/from the ground; and control means for controlling the connecting/disconnecting operations of said first switch element and said second switch so as to maintain a voltage outputted from said storage means at a predetermined value. 
     A first DC/DC converter of the present invention is an apparatus capable of protecting a circuit (for instance, an organic capacitor) of the DC/DC converter when an input voltage becomes an overvoltage. 
     This first DC/DC converter is comprised of an overvoltage detecting means, a shortcircuiting means, and an interrupting means. 
     The overvoltage detecting means monitors a voltage derived from said power supply to thereby output an alarm signal when said voltage derived from said power supply exceeds a preselected voltage value. This alarm signal is inputted to the shortcircuiting means. 
     The shortcircuiting means brings said first switch element and said second switch element to connecting conditions when the alarm signal from the overvoltage detecting means is inputted thereinto, whereby the voltage derived from said power supply is shortcircuited. 
     At this time, since a large current flows through the DC/DC converter due to this shortcircuit, the interrupting means interrupts the first signal path when this large current is received. 
     As a result, the power supplied to the DC/DC converter is interrupted, so that it is possible to prevent the overvoltage from being applied to the circuit (for example, an organic capacitor) provided in the input unit of the DC/DC converter. 
     The above-described overvoltage means may include a reference voltage producing means for producing a reference voltage; and a-comparing unit for comparing said reference voltage produced from said reference voltage producing unit with the voltage derived from said power supply to thereby output the alarm signal when said voltage derived from said power supply is higher than said reference voltage. 
     A second DC/DC converter according to the present invention is such an apparatus capable of protecting a circuit provided in the output unit of this DC/DC converter, and a load of this DC/DC converter when the output voltage of the DC/DC converter becomes the overvoltage. 
     The second DC/DC converter is comprised of an overvoltage detecting means, and a clamping means. 
     The overvoltage detecting means monitors the voltage outputted from the DC/DC converter to thereby output an alarm signal when said output voltage exceeds a predetermined voltage value, and the alarm signal is inputted to the clamping means. 
     The clamping means brings said first switch element to a disconnecting state and, at the same time, brings said second switch element to a connecting state, whereby the output voltage from said storage means is clamped to the ground level. 
     As a result, it is possible to prevent the overvoltage from being applied to the circuit provided in the output unit of the DC/DC converter, and also the load for this DC/DC converter. 
     The overvoltage means may include a reference voltage producing means for producing a reference voltage; and a voltage comparator for comparing said reference voltage produced from said reference voltage producing unit with the voltage derived from said storage means to thereby output the alarm signal when said voltage derived from said storage means is higher than said reference voltage. 
     It should be noted that when the first switch element of the DC/DC converter malfunctions in the shortcircuit mode, the output voltage of the DC/DC converter is brought into the overvoltage condition. In such a case, it is also required to protect the load of the DC/DC converter, and also the circuit within this DC/DC converter. 
     Therefore, a third DC/DC converter of the present invention employs such an arrangement for protecting the circuit within this DC/DC converter and the load for this DC/DC converter when the first switch element fails in the shortcircuit mode. 
     That is, the third DC/DC converter is comprised of shortcircuiting means for bringing said second switch element to a connecting state when said first switch element fails under a shortcircuited state, whereby the voltage derived from said power supply is shortcircuited; and interrupting means for interrupting said first signal path by power shortcircuited by said shortcircuiting means. 
     This interrupting means is a fuse to be melted down by the large current produced by the shortcircuit. 
     As described above, according to the DC/DC converter of the present invention, when the input/output voltages of this DC/DC converter are under overvoltage conditions, the first and second switch elements are used as the overvoltage protection circuit. As a consequence, it is possible to prevent the overvoltages from being applied to the constructive elements of this DC/DC converter and the load for this DC/DC converter without making the circuit arrangement complex. 
     As a result, it is possible to prevent the organic capacitors use in the DC/DC converter from the fire and small exposition problems. Moreover, the DC/DC converter can be made compact with the improved converting efficiency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 schematically indicates an arrangement of a DC/DC converter according to an embodiment mode 1 of the present invention; 
     FIG. 2 represents an internal arrangement of a control circuit CTL of the embodiment mode 1; 
     FIG. 3 schematically shows an arrangement of a DC/DC converter according to another embodiment mode of the present invention; 
     FIG. 4 represents an internal arrangement of a control circuit CTR corresponding to the DC/DC converter of FIG. 3; 
     FIG. 5 schematically indicates an arrangement of a DC/DC converter according to an embodiment mode 2 of the present invention; 
     FIG. 6 represents an internal arrangement of a control circuit CTL of the embodiment mode 2; 
     FIG. 7 schematically shows an arrangement of a DC/DC converter according to another embodiment mode of the present invention; 
     FIG. 8 represents an internal arrangement of a control circuit CTR corresponding to the DC/DC converter of FIG. 7; 
     FIG. 9 schematically indicates an arrangement of a DC/DC converter according to an embodiment mode 3 of the present invention; 
     FIG. 10 schematically indicates an arrangement of a DC/DC converter according to a embodiment mode 4 of the present invention; 
     FIG. 11 represents an internal arrangement of a control circuit CTL of the embodiment mode 4; and 
     FIG. 12 schematically shows the arrangement of the conventional DC/DC converter. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to drawings, various DC/DC converters according to the present invention will be described. 
     First, for a better understanding of the present invention, a conventional DC-to-DC converter (DC/DC converter) will now be explained with reference to FIG.  12 . 
     It is assumed that this conventional DC/DC converter is provided between a cell (not shown in FIG. 12) and a load (not shown either). 
     The DC/DC converter is comprised of a main switching transistor Tr 1 , a transistor Tr 2  for synchronous rectification, a diode D 1 , a resistor R 1 , a capacitor C 1 , a choke coil L 1 , and a control circuit CTL. Furthermore, a zener diode D 2  is provided at an output portion of this DC/DC converter. 
     The main switching transistor Tr 1  is a field-effect transistor (FET) which is turned ON/OFF in response to a signal DH from the control circuit CTL. 
     The choke coil L 1  corresponds to a coil for converting a voltage. 
     The diode D 1  is such a flywheel diode for discharging energy to the output side, which has been stored in the choke coil L 1  while the main switching transistor Tr 1  is brought into-the OFF state. 
     The transistor Tr 2  for synchronous rectification is a flywheel switch circuit for discharging energy to the output side, which has been stored in the choke coil L 1  while the main switching transistor Tr 1  is turned OFF. This synchronous rectification transistor Tr 2  is a field-effect transistor (FET) which is turned ON/OFF in response to a signal DL from the control circuit CTL. 
     For example, the synchronous rectification transistor Tr 2  is brought into the ON state when the voltage is applied to the diode D 1  in the forward direction, and brought into the OFF state when this voltage is applied to the diode D 2  in the reverse direction. 
     The resistor R 1  is such a sense resistor R 1  used to measure a value of a current flowing from the DC/DC converter to the load. 
     The capacitor C 1  is a smoothing capacitor for eliminating an AC component of the signal outputted from the sense resistor R 1 . 
     The zener diode D 2  corresponds to a protection circuit for monitoring as to whether or not a voltage from which the AC component has been removed by the capacitor C 1  is lower than, or equal to the normal voltage, namely, whether or not a voltage from which the AC component has been removed by the capacitor C 1  is an overvoltage. 
     When the voltage from which the AC component is removed by the capacitor C 1  exceeds the standard voltage, this zener diode D 2  becomes the ON state to thereby clamp the output voltage from the DC/DC converter to the standard voltage. When the overvoltage (excess voltage) is further increased, the zener diode D 2  is burned out to be shortcircuited between the DC/DC converter and the load. 
     A voltage from the cell, a voltage CS inputted to the sense resistor R 1 , and a voltage FB outputted from the sense resistor R 1  are entered into the control circuit CTL. Furthermore, either an ON instruction value or an OFF instruction value, which are externally supplied, and a target voltage V ref  are entered into this control circuit CTL. 
     This control circuit CTL monitors the voltage CS inputted into the sense resistor R 1 , and the voltage FB outputted from the sense resistor R 1  so as to measure a voltage drop appearing in the sense resistor R 1 . 
     Also, the control circuit CTL compares the output voltage FB from the resistor R 1  with the externally supplied target voltage V ref  to thereby turn ON/OFF the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  in such a manner that the output voltage value of the DC/DC converter becomes a preselected voltage value. 
     In the case that the above-described DC/DC converter is operated under normal condition, since the output voltage of this DC/DC converter is sufficiently lower than the normal (voltage of the zener diode D 2 , the zener diode D 2  is brought into the OFF state. In this case, the voltage from which the AC component is removed by the capacitor C 1  is directly applied to the load. 
     On the other hand, when the output voltage from the DC/DC converter becomes the overvoltage, the output voltage value of the DC/DC converter becomes higher than the normal voltage value of the zener diode D 2 . When the output voltage becomes higher than the normal voltage, the zener diode D 2  is brought into the ON state. In this case, the output voltage of the DC/DC converter is clamped to the normal voltage of the zener diode D 2 . Accordingly, it is possible to prevent the overvoltage from being applied to the load. 
     Since the above-described conventional DC/DC converter owns no such a mechanism capable of limiting the current flow in the zener diode D 2 , if the overvoltage is further continued, then the zener diode D 2  would be burned out. In this case, a shortcircuit condition is made between this DC/DC converter and the load. As a result, no current may flow through the smoothing capacitor C 1 , so that burning out of this smoothing capacitor C 1  can be prevented. 
     However, when the zener diode is employed so as to protect the smoothing capacitor, if the zener diode fails in the shortcircuit mode, then this zener diode may function as the protection circuit, whereas if the zener diode fails in the opencircuit mode, then this zener diode could not have the protection function. In such a case that the zener diode malfunctions in the opencircuit mode, the organic capacitor provided in the output unit of this conventional DC/DC converter would be burned out. Thus, there is such a problem that this burned organic capacitor may emit smoke, or will make a fire. 
     Furthermore, since it is practically impossible to specify whether the zener diode will fail in the opencircuit mode, or in the shortcircuit mode, the use of such a zener diode as the protection circuit of the DC/DC converter would become improper. 
     Also, since another organic capacitor is employed in the input unit of this conventional DC/DC converter, these organic capacitors should be protected. 
     A description will now be made of a DC-to-DC converter according to an embodiment of the present invention, capable of solving the above-described problems. 
     EMBODIMENT MODE 1 
     FIG. 1 is a schematic diagram for showing a DC-to-DC converter according to a first embodiment mode 1 of the present invention. It should be noted that the same reference numerals used in the prior art DC/DC converter will be employed as those for denoting the same or similar constructive elements in the following embodiment modes. 
     A DC/DC converter is provided between a cell functioning as a power supply and a load (not shown in FIG.  1 ), and is such an apparatus for converting a voltage applied from the cell into a constant voltage so as to supply this constant voltage to the load. 
     ARRANGEMENT OF FIRST DC/DC CONVERTER 
     The DC/DC converter according to this embodiment mode 1 is constructed of a fuse F 1 , a control circuit CTL, a main switching transistor Tr 1 , a synchronous rectification transistor Tr 2 , a diode D 1 , a choke coil L 1 , a capacitor C 1 , a voltage comparator IC 1 , a power supply e 1  for producing a reference voltage e 1 , a capacitor C 2 , and a capacitor C 3 . 
     (CIRCUIT CONNECTIONS FOR FIRST DC/DC CONVERTER) 
     Now, connection modes of the above-described constructive elements will be described. 
     The fuse F 1  is employed in a half way of a signal line  14  used to connect the cell with the main switching transistor Tr 1 . 
     The main switching transistor Tr 1  connected via this signal line  14  to the cell is connected via another signal line  1  to the choke coil L 1 , and via another signal line  24  to the control circuit CTL. 
     The above-described main switching transistor Tr 1  is, for instance, an MOS-FET (Metal Oxide Semiconductor Field-Effect Transistor) having a source terminal, a drain terminal, and a gate terminal, namely three terminals. In this case, the signal line  14  is connected to the drain terminal of the main switching transistor Tr 1 . Also, the signal line  1  is connected to the source terminal of the main switching transistor Tr 1 . Furthermore, the signal line  24  is connected to the gate terminal of the main switching transistor Tr 1 . 
     The choke coil L 1  connected via the signal line  1  with the main switching transistor Tr 1  is further connected via the signal line  15  is to the load (not shown in FIG.  1 ). 
     Four signal lines  31 ,  17 ,  18 ,  19  are connected to a half way of the signal line  14  for connecting the fuse F 1  with the main switching transistor Tr 1 . 
     The signal line  31  located near the fuse F 1  among the above-described four signal lines  31 ,  17 ,  18 ,  19  is connected via the capacitor C 3  to the ground. 
     The signal line  17  among the above-described four signal lines  31 ,  17 ,  18 ,  19  is connected to the voltage comparator IC 1 . This voltage comparator IC 1  owns, for example, a non-inverting input terminal, an inverting input terminal, and an output terminal. In this case, the signal line  17  is connected to the non-inverting input terminal of the voltage comparator IC 1 . The inverting input terminal of the voltage comparator IC 1  is connected via another signal line  22  to the power supply e 1 . Furthermore, the output terminal of the voltage comparator IC 1  is connected via a signal line  23  to the control circuit CTL. 
     The signal line  18  among the above-explained four signal lines  31 ,  17 ,  18 ,  19  is-connected to the control circuit CTL. A signal line  18   a  is connected to a half way of this signal line  18 . This signal line  18   a  is connected via the capacitor C 2  to the ground. 
     The signal line  19  located near the main switching transistor Tr 1  among the four signal lines  31 ,  17 ,  18 ,  19  is connected to the control circuit CTL. 
     Two signal lines  2  and  3  are connected to a half way of the signal line  1  used to connect the main switching transistor Tr 1  with the choke coil L 1 . 
     The signal line  2  located near the main switching transistor Tnl among the two signal lines  2  and  3  is connected to the synchronous rectification transistor Tr 2 . This synchronous rectification transistor Tr 2  is connected via the signal line  25  to the control circuit CTL, and via a signal line  26  to the ground. 
     The synchronous rectification transistor Tr 2  is, for instance, an MOS-FET (Metal Oxide Semiconductor Field-Effect Transistor) having three terminals, namely a drain terminal, a source terminal, and a gate terminal. The signal line  2  is connected to the drain terminal of the synchronous rectification transistor Tr 2 . Also, the line  25  is-connected to the gate terminal of the synchronous rectification transistor Tr 2 . Further, the signal line  26  is connected to the source terminal of the synchronous rectification transistor Tr 2 . 
     The signal line  3  located-near the choke coil L 1  among the two signal lines  2  and  3  is connected to the cathode terminal of the diode D 1 . The anode terminal of this diode D 1  is connected via a signal line  27  to the ground. 
     Further, the signal lines  4  and  5  are connected to a half way of the signal line  15  for connecting the choke coil C 1  to the load. 
     The signal line  4  positioned near the choke coil L 1  among the two signal lines  4  and  5  is connected to the control circuit CTL. This signal line  4  is such a signal line for feeding back the output voltage FB of the DC/DC converter to the control circuit CTL. 
     The signal line  5  positioned near the load among the two signal lines  4  and  5  is connected via the capacitor C 1  to the ground. 
     (CIRCUIT FUNCTIONS OF FIRST DC/DC CONVERTER) 
     Then, functions of the above-described respective constructive elements will now be explained. 
     (POWER SUPPLY e 1 ) 
     The power supply e 1  produces a reference voltage “e 1 ” to be inputted to the DC/DC converter. 
     (VOLTAGE COMPARATOR IC 1 ) 
     The voltage comparator IC 1  compares the voltage Vi derived from the cell with the reference voltage e 1  produced from the power supply e 1  to thereby output a 0V indicative of the comparison result. The 0V outputted from the voltage comparator IC 1  is inputted via the signal line  23  to the control circuit CTL. 
     For instance, the voltage comparator IC 1  subtracts the reference voltage e 1  from the voltage Vi, and outputs a signal having a low level when the subtraction result is smaller than, or equal to “0”, otherwise outputs a signal having a high level when the subtraction result is a positive value. 
     (CAPACITOR C 2 ) 
     The capacitor C 2  stores therein power used to drive the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2 . 
     (CAPACITOR C 3 ) 
     The capacitor C 3  is organic capacitor which may be a smoothing capacitor for removing a pulsatory ripple component contained in the voltage inputted in the DC/DC convertor. 
     (MAIN SWITCHING TRANSISTOR Tr 1 ) 
     The main switching transistor Tr 1  inputs thereinto the control signal DH from the control circuit CTL and connects/disconnects a signal path between the signal line  14  and the signal line  1  in response to the input control signal DH. 
     For example, when the voltage from the control circuit CTL is applied to the gate terminal, the main switching transistor Tr 1  is turned ON to thereby connect between the drain terminal and the source terminal and also between the signal line  14  and the signal line  1 . 
     When the voltage from the control circuit CTL is not applied to the gate terminal, the main switching transistor Tr 1  is turned OFF to thereby disconnect between the drain terminal and the source terminal and also between the signal line  14  and the signal line  1 . 
     (CHOKE COIL L 1 ) 
     The choke coil L 1  is a voltage converting coil. 
     (DIODE D 1 ) 
     The diode D 1  is such a flywheel diode for discharging the energy stored in the choke coil L 1  when the main switching transistor Tr 1  is turned OFF toward the output circuit side. 
     (SYNCHRONOUS RECTIFICATION TRANSISTOR Tr 2 ) 
     The synchronous rectification transistor Tr 2  is a switch circuit which inputs thereinto the signal DL from the control circuit CTL, and connects/disconnects between the signal line  2  and the signal line  26  in response to the input signal DL. 
     For example, when the voltage from the control circuit CTL is applied to the gate terminal, the synchronous rectification transistor Tr 2  is turned ON to thereby connect between the drain terminal and the source terminal and also between the signal line  2  and the signal line  26 . 
     When the voltage from the control circuit CTL is not applied to the gate terminal, the synchronous rectification transistor Tr 2  is turned OFF to thereby disconnect between the drain terminal and the source terminal and also connect between the signal line  2  and the signal line  26 . 
     In this embodiment, the synchronous rectification transistor Tr 2  is a flywheel switch circuit for causing the energy stored in the choke coil L 1  while the main switching transistor Tr 1  is turned OFF to be outputted. 
     For instance, the synchronous rectification transistor Tr 2  is turned ON (namely, under condition to connect between signal line  2  and signal line  26 ) when the voltage is applied to the diode D 1  in the forward direction, and is turned OFF (namely, under condition to disconnect between signal line  2  and signal line  26 ) when voltage is applied to the diode D 1  in the reverse direction. At this time, the voltage drop of the diode D 1  is reduced. 
     (CAPACITOR C 1 ) 
     The capacitor C 1  is a smoothing capacitor for removing a pulsatory ripple component contained in the voltage outputted from the choke coil L 1 . 
     (CONTROL CIRCUIT CTL) 
     The ON instruction value, or the OFF instruction value, and the target voltage Vcom are externally entered into the control circuit CTL in addition to the above-described signal lines  4 ,  19 ,  23 ,  18 ,  24 ,  25 . The externally applied target voltage V ref  is a reference voltage to be outputted from the DC/DC converter. 
     Then, the control circuit CTL controls turning ON/OFF of the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  in response to the OV derived from the voltage comparator IC 1 , the output voltage FB inputted via the signal line  4 , and the externally supplied target voltage V ref . 
     Referring now to FIG. 2, an internal circuit a arrangement of the control circuit CTL will be explained. 
     (ARRANGEMENT OF CONTROL CIRCUIT CTL) 
     As indicated in FIG. 2, the control circuit CTL corresponds to a circuit with employment of the pulse width modulation system (PWM system). This control circuit CTL is constructed of a power supply  7 , a triangle wave oscillator  8 , a PMW comparator  9 , a charge pump circuit  12 , a synchronous rectification control circuit  13 , a flip-flop FF, a drive- 1  ( 10 ), and another drive- 2  ( 11 ). The control circuit CTL further includes a dividing resistor R 2 /R 3 , an error amplifier ERAI, an OR gate circuit OR 1 , and another OR gate circuit OR 2 . 
     (POWER SUPPLY  7 ) 
     Upon receipt of the externally supplied ON instruction value, the power supply  7  supplies operation power to the circuit for constituting this control circuit CTL. Upon receipt of the externally supplied OFF instruction value, the power supply  7  interrupts the supply of this operation power-to the circuit for constituting the control circuit CTL. 
     (TRIANGLE WAVE OSCILLATOR  8 ) 
     The triangle wave oscillator  8  oscillates a converting triangle wave at a constant frequency, which is used to convert the voltage into the pulse width. The triangle wave oscillated from this triangle wave oscillator  8  is inputted to the PWM comparator  9 . 
     (DIVIDING RESISTOR R 2 / 3 ) 
     The dividing resistor R 2 /R 3  is connected to the signal line  4  so as to accept the output voltage FB from the DC/DC converter. This dividing resistor R 2 /R 3  is a sense resistor for sensing the voltage value of the output voltage FB. 
     The voltage value sensed by the dividing resistor R 2 /R 3  is entered to the error amplifier ERA 1 . 
     (ERROR AMPLIFIER ERA 1 ) 
     The error amplifier ERA 1  is an error amplifying circuit for inputting thereinto the voltage value FB sensed by the dividing resistor R 2 /R 3 , and the externally supplied target voltage V ref , and for amplifying an error between the voltage FB and the target voltage V ref . The error amplified by this error amplifier ERA 1  is inputted to the non-inverting input terminal of the PWM comparator  9 . 
     (PWM COMPARATOR  9 ) 
     The PWM comparator  9  is a voltage comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal of the PWM comparator  9  inputs thereinto the converting triangle wave outputted from the triangle wave oscillator  8 . The non-inverting terminal of the PWM comparator  9  inputs thereinto the signal outputted from the error amplifier ERA 1 . 
     Then, the PWM comparator  9  compares the signal inputted to the non-inverting input terminal with the signal inputted to the inverting input terminal. 
     For example, the PWM comparator  9  subtracts the signal inputted to the inverting input terminal from the signal inputted into the non-inverting input terminal. Then, the PWM comparator  9  outputs a signal with a high level while the subtracted value indicates a negative value (namely, while the signal outputted from the triangle wave oscillator  8  is larger than the signal outputted from the error amplifier ERA 1 ). 
     Also, the PWM comparator  9  outputs a signal with a low level while the subtracted value indicates a positive value (namely,. while the signal outputted from the triangle wave oscillator  8  is smaller than the signal outputted from the error amplifier ERAl). 
     The signal outputted from the PWM comparator  9  (either a low-level signal or a high-level signal) is entered to the OR gate circuit OR 2  and the synchronous rectification control circuit  13 . 
     (CHARGE PUMP CIRCUIT  12 ) 
     The charge pump circuit  12  applies a voltage for driving the main switching transistor Tr 1  to the drive- 1  ( 10 ), and also another voltage for driving the synchronous rectification transistor Tr 2  to the drive- 2  ( 11 ). 
     (SYNCHRONOUS RECTIFICATION CONTROL CIRCUIT  13 ) 
     The synchronous rectification control circuit  13  inputs thereinto the signal outputted from the PWM comparator  9 . Then, the synchronous rectification control circuit  13  turns ON/OFF the synchronous rectification transistor Tr 2  to perform the synchronous rectification in response to the signal derived from the PWM comparator  9 . 
     For example, when a signal having a low level derived from the PWM comparator  8  is inputted, the synchronous rectification control circuit  13  outputs a signal having a high level. When a signal having a high level derived from the PWM comparator  8  is inputted, the synchronous rectification control circuit  13  outputs a signal having a low level. 
     The signals outputted from the synchronous rectification control circuit  13  is inputted to the OR gate circuit OR 1 . 
     (FLIP-FLOP FF) 
     The flip-flop FF owns a set terminal S, a reset terminal R, two input terminals, and an output terminal Q. The set terminal S of the flip-flop FF inputs thereinto the OV outputted from the voltage comparator ICI. At this time, the flip-flop FF stores therein the signal entered into the set terminal S. 
     Further, the reset terminal R of the flip-flop FF inputs thereinto either the externally ON instruction value or OFF instruction value. When the ON instruction or OFF instruction is inputted into the reset terminal R, the signal stored in the flip-flop FF is reset to a low-level signal. 
     Furthermore, the output terminal Q of the flip-flop FF is connected to the OR gate circuit OR 1  and the OR gate circuit OR 2 . This output terminal Q outputs the signal stored in the flip-flop FF. 
     For example, when the input voltage Vi of the DC/DC converter is lower than, or equal to the reference voltage e 1 , the set terminal S of the flip-flop FF inputs a low-level signal as the 0V derived from the voltage comparator IC 2 . In this case, the flip-flop FF stores therein the low-level signal inputted to the set terminal S, and the output terminal Q thereof outputs the low-level signal stored in this flip-flop FF. 
     For example, when the input voltage Vi of the DC/DC converter exceeds the reference voltage e 1  (namely overvoltage), the set terminal S of the flip-flop FF inputs a high-level signal as the 0V derived from the voltage comparator IC 2 . In this case, the flip-flop FF stores therein the high-level signal inputted to the set terminal S, and the output terminal Q thereof outputs the high-level signal stored in this flip-flop FF. 
     (OR GATE CIRCUIT OR 2 ) 
     The OR gate circuit OR 2  OR-gates the signal from the PWM comparator  9  and the signal from the flip-flop FF and supplies a signal indicative of this calculation result to the drive- 1  ( 10 ). 
     For instance, when the input voltage Vi of the DC/DC converter is lower than, or equal to the reference voltage e 1 , the OR gate circuit OR 2  inputs thereinto the low-level signal from the output terminal Q of the flip-flop FF. In this case, the OR gate circuit OR 2  directly outputs the signal derived from the PWM comparator  9 . As a result, in the case that the input voltage Vi to the DC/DC converter is-lower than, or equal to the reference voltage e 1 , the drive- 1  ( 10 ) is operated in response to the signal derived from the PWM modulator  9 . 
     Also, when the input voltage Vi of the DC/DC converter is larger than, the reference voltage e 1  (namely, overvoltage), the OR gate circuit OR 2  inputs thereinto the high-level signal from the output terminal Q of the flip-flop FF. In this case, the OR gate circuit OR 2  outputs the high-level signal irrelevant to the signal derived from the PWM comparator  9 . As a result, in the case that the input voltage Vi to the DC/DC converter is brought into the overvoltage condition the drive- 1  ( 10 ) is-operated in response to the signal from the flip-flop irrelevant to the signal derived from the PWM modulator  9 . 
     (OR GATE CIRCUIT OR 1 ) 
     The OR gate circuit OR 1  OR-gates the signal outputted from the synchronous rectification control circuit  13  and the signal outputted from the flip-flop FF, and outputs a signal indicative of this calculation result. The signal outputted from this OR gate circuit OR 1  is inputted to the drive- 2  ( 11 ). 
     For instance, when the input voltage Vi of the DC/DC converter is lower than, or equal to the reference voltage e 1 , the OR gate circuit OR 1  inputs thereinto the low-level signal from the flip-flop FF. In this case, the OR gate circuit OR 1  directly outputs the signal derived from the synchronous rectification control circuit  13 . As a result, in the case that the output voltage FB is lower than, or equal to the reference voltage e 1 , the drive- 1  ( 10 ) is operated in response to the signal derived from the synchronous rectification control circuit  13 . 
     Also, when the input voltage Vi of the DC/DC converter is larger than the reference voltage e 1  (namely, overvoltage), the OR gate circuit OR 1  inputs thereinto the high-level signal from the flip-flop FF. In this case, the OR gate circuit OR 1  directly outputs the high-level signal, irrelevant to the signal derived from the synchronous rectification control circuit  13 . As a result, in the case that the input voltage Vi to the DC/DC converter becomes the overvoltage, the drive- 2  ( 11 ) is operated in response to the high-level signal derived from the flip-flop FF, irrelevant to the signal derived from the synchronous rectification control circuit  13 . 
     (DRIVE- 1  ( 10 )) 
     In response to the signal from the OR gate circuit OR 2 , the drive- 1  ( 10 ) turns ON/OFF the main switching transistor Tr 1 . 
     For example, when the high-level signal from the OR gate circuit OR 2  is inputted, the drive- 1  ( 10 ) supplies the power supplied from the charge pump circuit  12  to the main switching transistor Tr 1 , so that the main switching transistor Tr 1  is brought into the ON state. 
     Also, when the low-level signal from the OR gate circuit OR 2  is inputted, the drive- 1  ( 10 ) interrupts the supply of power to the main switching transistor Tr 1 , so that this main switching transistor Tr 1  is brought into the OFF state. 
     (DRIVE- 2  ( 11 )) 
     In response to the signal from the OR gate circuit OR 1 , the drive- 2  ( 11 ) turns ON/OFF the synchronous rectification transistor Tr 2 . 
     For example, when the high-level signal from the OR gate circuit OR 1  is inputted, the drive- 2  ( 11 ) supplies the power supplied from the charge pump circuit  12  to the synchronous rectification transistor Tr 2 , so that the synchronous rectification transistor Tr 2  is brought into the ON state. 
     Also, when the low-level signal from the OR gate OR 1  is inputted, the drive- 2  ( 11 ) interrupts the supply of power to the synchronous rectification transistor Tr 2 , so that this synchronous rectification transistor Tr 2  is brought into the OFF state. 
     OPERATION/EFFECTS OF EMBODIMENT MODE 1 
     A description will now be made of operation/effects of the first DC/DC converter according to the first embodiment of the present in vention. 
     (1) In a Case that First DC/DC Converter is Operable Under Normal Condition 
     In a case that the first DC/DC converter is normally operated, namely when the input voltage Vi to the DC/DC converter indicates the normal voltage value, since the input voltage Vi becomes sufficiently lower than the reference voltage e 1 , the 0V from the voltage comparator IC 1  becomes a signal indicative of a low level. 
     In this case, the low-level signal outputted from the voltage comparator IC 1  is inputted to the set terminal S of the flip-flop FF of the control circuit CTL. Then, the flip-flop FF stores the inputted low-level signal. 
     When the flip-flop FF stores the low-level signal, the output terminal Q of the flip-flop FF outputs a low-level signal. 
     The low-level signal outputted from the output terminal Q of the flip-flop FF is entered into the OR gate circuit OR 2  and the OR gate OR 1  of the control circuit CTL. 
     The dividing resistor R 2 /R 3  of the control circuit CTL inputs thereinto the output voltage FB from the DC/DC converter via the signal line  4 . Then, the dividing resistor R 2 /R 3  senses the entered output voltage FB, and enters the sensed voltage value to the error amplifier ERA 1 . 
     The error amplifier ERA 1  into which the voltage value from the dividing resistor R 2 /R 3  is inputted amplifies an error between the voltage value derived from the dividing resistor R 2 /R 3  and the externally supplied target voltage V ref  to output the amplified error signal. The error signal outputted from the error amplifier ERA 1  is inputted to the PWM comparator  9 . 
     The PWM comparator  9  inputs thereinto the error signal from the error amplifier ERA 1 , and also inputs thereinto the converting triangle wave from the triangle wave oscillator  8 . when the error signal from the error amplifier ERA 1  is smaller than the converting triangle wave from the triangle wave oscillator  8 , the PWM comparator  9  outputs a high-level signal. 
     When the error signal from the error amplifier ERA 1  is larger than the converting triangle wave from the triangle wave oscillator  8 , the PWM comparator  9  outputs a low-level signal. 
     The signal outputted from the PWM comparator  9  is inputted to the OR gate circuit OR 2  and the synchronous rectification control circuit  13 . 
     When the signal derived from the PWM comparator  9  is a high-level signal, the synchronous rectification control circuit  13  for inputting thereinto the signal from the PWM comparator  9  outputs a low-level signal. On the other hand, when the signal derived from the PWM comparator  9  is a low-level signal, the synchronous rectification control circuit  13  outputs a high-level signal. The signal outputted from this synchronous rectification control circuit  13  is inputted to the OR gate circuit OR 1 . 
     As described above, the OR gate circuit OR 2  inputs thereinto the low-level signal from the flip-flop FF and the signal from the PWM comparator  9  (either high-level signal or low-level signal), whereas the OR gate circuit OR 1  inputs thereinto the low-level signal from the flip-flop FF and the signal from the synchronous rectification control circuit  13  (either high-level signal or low-level signal). 
     Since the OR gate circuit OR 2  inputs thereinto the low-level signal from the flip-flop FF, this OR gate circuit OR 2  directly outputs the signal derived from the PWM comparator  9 . For instance, when the high-level signal from the PWM comparator  9  is inputted, the OR gate circuit OR 2  outputs a high-level signal. Also, when the low-level signal from the PWM comparator  9  is entered, the OR gate circuit OR 2  outputs a low-level signal. 
     The signal outputted from the OR gate circuit OR 2  is entered into the drive- 1  ( 10 ). 
     If the signal from the OR gate circuit OR 2  is the low-level signal, then the drive- 1  ( 10 ) into which the signal from the OR gate circuit OR 2  is inputted interrupts the supply of power to the main switching transistor Tr 1 . At this time, the main switching transistor Tr 1  is brought into the OFF state to thereby disconnect between the signal line  14  and the signal line  1 . 
     When the signal from the OR gate circuit OR 2  is the high-level signal, the drive- 1  ( 10 ) supplies the power from the charge pump circuit  12  to the main switching transistor Tr 1 . At this time, the main switching transistor Tr 1  is brought into the ON state to thereby connect between the signal line  14  and the signal line  1 . 
     The OR gate circuit OR 1  into which the low-level signal from the flip-flop FF and the signal from the synchronous rectification control circuit  13  are inputted directly outputs the signal (either high-level signal or low-level signal) derived from the synchronous rectification control circuit  13 . 
     The signal outputted from the OR gate circuit OR 1  is entered into the drive- 2  ( 11 ). 
     If the signal from the OR gate circuit OR 1  is the low-level signal, then the drive- 2  ( 11 ) into which the signal from the OR gate circuit OR 1  is inputted interrupts the supply of power to the synchronous rectification transistor Tr 2 . At this time, the synchronous rectification transistor Tr 2  is brought to the OFF state to thereby disconnect between the signal line  2  and the signal line  26 . 
     When the signal from the OR gate circuit OR 1  is the high-level signal, the drive- 2  ( 11 ) supplies the power from the charge pump circuit  12  to the synchronous rectification transistor Tr 2 . At this time, the synchronous rectification transistor Tr 2  is brought into the ON state to thereby connect between the signal line  2  and the signal line  26 . 
     (2) In a Case that Input Voltage to First DC/DC Converter is Under Overvoltage Condition 
     In such a case that a voltage Vi inputted to the first DC/DC converter becomes an overvoltage, since the input voltage Vi is higher than the reference voltage el, the signal 0V derived from the voltage comparator IC 1  is a signal indicative of a high level. 
     The high-level signal outputted from the voltage comparator IC 1  is inputted to the set terminal S of the flip-flop FF of the control circuit CTL. At this time, the flip-flop FF stores the high-level signal inputted to the set terminal S. Then the flip-flop FF outputs the stored high-level signal from the output terminal Q of the flip-flop FF. 
     The high-level signal outputted from the output terminal Q of the flip-flop FF is entered into the OR gate circuit OR 2  and the OR gate OR 1  of the control circuit CTL. 
     The dividing resistor R 2 /R 3  of the control circuit CTL inputs thereinto the output voltage FB from the DC/DC converter via the signal line  4 . Then, the dividing resistor R 2 /R 3  senses the entered output voltage FB, and enters the sensed voltage value to the error amplifier ERA 1 . 
     The error amplifier ERA 1  into which the voltage value from the dividing resistor R 2 /R 3  is inputted amplifies an error between the voltage value derived from the dividing resistor R 2 /R 3  and the externally supplied target voltage V ref  to output the amplified error signal. The error signal outputted from the error amplifier ERA 1  is inputted to the PWM comparator  9 . 
     The PWM comparator  9  inputs thereinto the error signal from the error amplifier ERA 1 , and also inputs the converting triangle wave from the triangle wave oscillator  8 . when the error signal from the error amplifier ERA 1  is smaller than the converting triangle wave from the triangle wave oscillator  8 , the PWM comparator  9  outputs a high-level signal. 
     When the error signal from the error amplifier ERA 1  is larger than the converting triangle wave from the triangle wave oscillator  8 , the PWM comparator  9  outputs a low-level signal. 
     The signal outputted from the PWM comparator  9  is inputted to the OR gate circuit OR 2  and the synchronous rectification control circuit  13 . 
     When the signal derived from the PWM comparator  9  is a high-level signal, the synchronous rectification control circuit  13  for inputting thereinto the signal from the PWM comparator  9  outputs a low-level signal. On the other hand, when the signal derived from the PWM comparator  9  is a low-level signal, the synchronous rectification control circuit  13  outputs a high-level signal. The signal outputted from this synchronous rectification control circuit  13  is inputted to the OR gate circuit OR 1 . 
     As described above, the OR gate circuit OR 2  inputs thereinto the high-level signal from the flip-flop FF and the signal from the PWM comparator  9  (either high-level signal or low-level signal), whereas the OR gate circuit OR 1  inputs thereinto the high-level signal from the flip-flop FF and the signal from the synchronous rectification control circuit  13  (either high-level signal or low-level signal). 
     In this case, since the OR gate circuit OR 2  inputs thereinto the high-level signal derived from the flip-flop FF, this OR gate circuit OR 2  outputs a high-level signal irrelevant to the signal supplied from the PWM comparator  9 . 
     The high-level signal outputted from the OR gate OR 2  is inputted into the drive- 1  ( 10 ). 
     The drive- 1  ( 10 ) into which the high-level signal from the OR gate circuit OR 2  is inputted supplies the power from the charge pump circuit  12  to the main switching transistor Tr 1 . At this time, the main switching transistor Tr 1  is brought into the ON state to thereby connect between the signal line  14  and the signal line  1 . 
     Further, since the high-level signal from the flip-flop FF is inputted into the OR gate circuit OR 1 , this OR gate circuit OR 1  outputs a high level signal irrelevant to the signal (either high-level signal or low-level signal) from the synchronous rectification control circuit  13 . 
     The high-level signal outputted from the OR gate circuit OR 1  is entered into the drive- 2  ( 11 ). 
     The drive- 2  ( 11 ) into which the high-level signal from the OR gate circuit OR 1  is inputted supplies the power from the charge pump circuit  12  to the synchronous rectification transistor Tr 2 . At this time, the synchronous rectification transistor Tr 2  is brought into the ON state to thereby connect between the signal line  2  and the signal line  26 . 
     When both the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  are brought into the ON state, the current from the cell may flow through the fuse F 1 , the signal line  14 , the main switching transistor Tr 1 , the signal line  1 , the signal line  2 , the synchronous rectification transistor Tr 2 , and the signal line  26  to the ground. At this time, an overcurrent will flow through the fuse F 1 , so that this fuse F 1  is melted down. 
     As a result, since the fuse F 1  is melted down, it is possible to prevent the constructive elements of the first DC/DC converter, especially the capacitor C 3  provided in the input unit of this DC/DC converter from being applied the excessive high voltages. Therefore, it is possible to avoid that the capacitor C 3  would be burned out. 
     Further, in accordance with this first DC/DC converter, when the power supply of the control circuit CTL could not produce the drive power for the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2 , these main switching transistor Tr 1  and synchronous rectification transistor Tr 2  are driven by the power stored in the capacitor C 2 . As a consequence, the DC/DC converter can assure the operations of the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  until the fuse F 1  is melt down. 
     It should be noted that the power supply used to drive the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  are not limited to the capacitor C 3 . 
     According to the DC/DC converter of this first embodiment, no longer the high withstanding voltage type organic capacitor is required as the capacitor C 3 . Moreover, the burn-out preventing fuse is not required, but also a total number of constructive elements could be reduced. 
     In addition, since the burn-out preventing fuse for the capacitor C 3  is not required, the resistance value of the first DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     (ANOTHER EMBODIMENT MODE OF FIRST DC/DC CONVERTER) 
     In the DC/DC converter according to the embodiment mode 1, the voltage comparator IC 1  and the power supply el are provided independent from the control circuit CTL. Alternatively, as represented in FIG.  3  and FIG. 4, the voltage comparator IC 1  and the power supply e 1  may be employed within the control circuit CTL. 
     In this case, the signal line  17  is directly connected to the control circuit CTL. Then, a voltage “Vi” entered via the signal line  17  into the control circuit CTL is applied to a dividing resistor R 4 /R 5 . 
     The dividing resistor R 4 /R 5  is a resistor for sensing the voltage Vi inputted via the signal line  17 . The voltage Vi sensed by this dividing resistor R 4 /R 5  is inputted to the non-inverting input terminal of the voltage comparator IC 1 . 
     The inverting input terminal of the voltage comparator IC 1  is connected via a signal line  22  to the power supply e 1 . 
     Further, the output terminal of the voltage comparator IC 1  is connected via a signal line  23  to the set terminal S of the flip-flop FF. 
     When the control circuit CTL is arranged in the above-described manner, if the voltage Vi supplied from the cell becomes the overvoltage, then the voltage Vi under overvoltage state is inputted to the dividing resistor R 4 /R 5  of the control circuit CTL. 
     The dividing resistor R 4 /R 5  senses the voltage value of this voltage Vi under overvoltage state. The voltage value sensed by this dividing resistor R 4 /R 5  is inputted to the non-inverting input terminal of the voltage comparator IC 1 . 
     The voltage comparator IC 1  subtracts the reference voltage derived from the power supply e 1  from the voltage value derived from the dividing resistor R 4 /R 5 . At this time, since the voltage value from the dividing resistor R 4 /R 5  becomes higher than the reference voltage, the voltage comparator IC 1  outputs a high-level signal. 
     As a result, the high-level signal outputted from the voltage comparator IC 1  is inputted to the set terminal S of the flip-flop FF. 
     As described, even when both the voltage comparator IC 1  and the power supply e 1  are build in the control circuit CTL, it is possible to achieve an effect similar to that of the above-explained embodiment mode 1. 
     In the example shown in FIG.  3  and FIG. 4, the control circuit CTL contains another power e 2  for producing the target voltage V ref . 
     As described above, when the circuit arrangement as shown in FIG.  3  and FIG. 4 is employed, a similar effect to that of the embodiment mode 1 can be achieved, and also the circuit arrangement of the DC/DC converter can be made simple. 
     EMBODIMENT MODE 2 
     FIG. 2 is a schematic diagram for showing a DC-to-DC converter according to a second embodiment mode 2 of the present invention. It should be noted that the same reference numerals used in the first DC/DC converter will be employed as those for denoting the same or similar constructive elements in the following embodiment modes. 
     A DC/DC converter is provided between a cell functioning as a power supply and a load. 
     (ARRANGEMENT OF SECOND DC/DC CONVERTER) 
     The DC/DC converter according to this embodiment mode 2 is constructed of, a control circuit CTL, a main switching transistor Tr 1 , a synchronous rectification transistor Tr 2 , a diode D 1 , a choke coil L 1 , a capacitor C 1 , a voltage comparator IC 2 , and a power supply e 3  for producing a reference voltage e 3 . 
     (CIRCUIT CONNECTIONS FOR SECOND DC/DC CONVERTER) 
     Now, connection modes of the above-described constructive elements will be described. 
     The main switching transistor Tr 1  is connected via a signal line  14  to a cell. This main switching transistor Tr 1  is connected via another signal line  1  to the choke coil L 1 , and via another signal line  24  to the control circuit CTL. 
     The choke coil L 1  connected via the signal line  1  with the main switching transistor Tr 1  is further connected via the signal line  15  is to a resistor R 1 . 
     The resistor R 1  is connected via the signal line  16  to the load. 
     A signal line  19  is connected to a half way of the above-described signal line  14 . This signal line  19  is connected to the control circuit CTL. 
     Two signal lines  2  and  3  are connected to a half way of the signal line  1  used to connect the main switching transistor Tr 1  with the choke coil L 1 . 
     The signal line  2  located near the main switching transistor Tr 1  among the two signal lines  2  and  3  is connected to the synchronous rectification transistor Tr 2 . This synchronous rectification transistor Tr 2  is connected via the signal line  25  to the control circuit CTL, and via a signal line  26  to the ground. 
     The signal line  3  located near the choke coil L 1  among the two signal lines  2  and  3  is connected to the cathode terminal of the diode D 1 . The anode terminal of this diode D 1  is connected via a signal line  27  to the ground. 
     Further, a signal line  20  is connected to a half way of the signal line  15  for connecting the choke coil C 1  to the resistor R 1 . 
     The above-described signal line  20  is connected to the control circuit CTL, and may function as a signal line for supplying a voltage CS which is inputted to the resister R 1  to the control circuit CTL. 
     Three signal lines  4 ,  5 ,  21  are connected to a half way of the signal line  16  for connecting the resistor R 1  with the load. 
     The signal line  4  located near the resistor R 1  among the three signal lines  4 ,  5 ,  21  is connected to the control circuit CTL. This signal line  4  is a signal line used to feed back the voltage value FB outputted from the second DC/DC converter to the control circuit CTL. 
     The center signal line  5  among the three signal lines  4 ,  5 ,  21  is connected via the smoothing capacitor C 1  to the ground. 
     The signal line  21  located near the load among the above-described three signal lines  4 ,  5 ,  21  is connected to the voltage comparator IC 2 . This voltage comparator IC 2  owns, for example, a non-inverting input terminal, an inverting input terminal, and an output terminal. In this case, the signal line  21  is connected to the non-inverting input terminal of the voltage comparator IC 2 . The inverting input terminal of the voltage comparator IC 2  is connected via another signal line  28  to the power supply e 3 . Furthermore, the output terminal of the voltage comparator IC 2  is connected via a signal line  29  to the control circuit CTL. 
     (CIRCUIT FUNCTIONS OF SECOND DC/DC CONVERTER) 
     Then, functions of the above-described respective constructive elements will now be explained. It should be understood that explanations about the same constructive elements-as those of the embodiment mode 1 are omitted. 
     (RESISTOR R 1 ) 
     The resistor R 1  is a sense resistor for sensing an output current value of the second DC/DC converter. 
     (POWER SUPPLY e 3 ) 
     The power supply e 3  produces a reference voltage e 3  of the voltage outputted from the second DC/DC converter. 
     (VOLTAGE COMPARATOR IC 2 ) 
     The voltage comparator IC 2  inputs thereinto the output voltage of the second DC/DC converter via the signal line  21 , and at the same time, inputs thereinto the reference voltage e 3  derived from the power supply e 3 . Then, the voltage comparator IC 2  compares the output voltage of the second DC/DC converter with the reference voltage e 3  from the power supply e 3 , and then outputs a 0V indicative of the comparison result. 
     For instance, the voltage comparator IC 2  subtracts the reference voltage e 3  from the output voltage of the second DC/DC converter, and then outputs a low-level signal when the subtraction result is lower than, or equal to “0”, or outputs a high level signal when the subtraction result is a positive value. 
     (CONTROL CIRCUIT CTL) 
     The ON instruction value, or the OFF instruction value, and the target voltage V ref  are externally entered into the control circuit CTL in addition to the above-described signal lines  19 ,  23 ,  25 ,  4 ,  20 ,  29 . The externally applied target voltage V ref  is a reference voltage to be outputted from the DC/DC converter. 
     Then, the control circuit CTL controls turning ON/OFF of the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  in response to the 0V derived from the voltage comparator IC 2 , the output voltage FB inputted via the signal line  4 , and the target voltage V ref  of the voltage to be outputted from the DC/DC converter. 
     An internal circuit arrangement of the control circuit CTL will be explained. 
     (ARRANGEMENT OF CONTROL CIRCUIT CTL) 
     As indicated in FIG. 6, the control circuit CTL corresponds to a circuit with employment of the pulse width modulation system (PWM system). This control circuit CTL is constructed of a power supply  7 , a triangle wave oscillator  8 , a PMW comparator  9 , a charge pump circuit  12 , a synchronous rectification control circuit  13 , a flip-flop FF, a drive- 1  ( 10 ), and another drive- 2  ( 11 ). The control circuit CTL further includes a dividing resistor R 2 /R 3 , error amplifiers ERA 1  and ERA 2 , an AND gate circuit AND 1 , and an OR gate circuit OR 1 . 
     (PWM COMPARATOR  9 ) 
     The PWM comparator  9  is a voltage comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal of the PWM comparator  9  inputs thereinto the converting triangle wave outputted from the triangle wave oscillator  8 . The non-inverting terminal of the PWM comparator  9  inputs thereinto the signal outputted from the error amplifier ERA. 
     Then, the PWM comparator  9  compares the signal inputted to the non-inverting input terminal with the signal inputted to the inverting input terminal. 
     For example, the PWM comparator  9  subtracts the signal inputted to the inverting input terminal from the signal inputted into the non-inverting input terminal. Then, the PWM comparator  9  outputs a signal with a high level while the subtracted value indicates a negative value (namely, while the signal outputted from the triangle wave oscillator  8  is larger than the signal outputted from the error amplifier ERA 1 ). 
     Also, the PWM comparator  9  outputs a signal with a low level while the subtracted value indicates a positive value (namely, while the signal outputted from the triangle wave oscillator  8  is smaller than the signal outputted from the error amplifier ERA 1 ). 
     The signal outputted from the PWM comparator  9  is entered to the AND gate circuit AND 1  and the synchronous rectification control circuit  13 . 
     (ERROR AMPLIFIER ERA 2 ) 
     The error amplifier ERA 2  inputs thereinto the voltage FB which is outputted from the resister R 1  via the signal line  4 , and at the same time, inputs thereinto the voltage CS which is inputted to the resister R 1  via the signal line  20 . 
     This error amplifier ERA 2  is an error amplifier circuit for a voltage drop of the resistor R 1  based upon the voltage CS which is inputted to the resister R 1  and the output voltage FB of the DC/DC converter. 
     The voltage value outputted from the error amplifier ER 2  is inputted to the synchronous rectification control circuit  13 . 
     (SYNCHRONOUS RECTIFICATION CONTROL CIRCUIT  13 ) 
     The synchronous rectification control circuit  13  inputs thereinto the signal outputted from the PWM comparator  9  and the signal outputted from the error amplifier ERA 2 . Then, the synchronous rectification control circuit  13  turns ON/OFF the synchronous rectification transistor Tr 2  to perform the synchronous rectification in response to the signal derived from the PWM comparator  9 , and the signal from the error amplifier ERA 2 . 
     For example, when a signal having a low level derived from the PWM comparator  8  is inputted and only when the signal from the error amplifier ERA 2  is below a constant value, the synchronous rectification control circuit  13  outputs a signal having a high level. 
     The signals outputted from the synchronous rectification control circuit  13  is inputted to the OR gate circuit OR 1 . 
     (FLIP-FLOP FF) 
     The flip-flop FF owns two input terminals as a set terminal S and a reset terminal R, and two output terminals as a non-inverting output terminal Q and an inverting output terminal *Q. The set terminal S of the flip-flop FF inputs thereinto the 0V outputted from the voltage comparator IC 2 . At this time, the flip-flop FF stores therein the signal entered into the set terminal S. 
     The reset terminal R of the flip-flop FF inputs thereinto either the externally ON instruction value or OFF instruction value. When the ON instruction or OFF instruction is inputted into the reset terminal R, the signal stored in the flip-flop FF is reset to a low-level signal. 
     Furthermore, the non-inverting output terminal Q of the flip-flop FF is connected to the OR gate circuit OR 1 . This output terminal Q directly outputs the signal stored in the flip-flop FF. 
     For example, when the output voltage FB of the DC/DC converter is lower than, or equal to the reference voltage e 3 , the set terminal S of the flip-flop FF inputs a low-level signal as the 0V derived from the voltage comparator IC 2 . In this case, the flip-flop FF stores therein the low-level signal inputted to the set terminal S, and the non-inverting output terminal Q thereof outputs the low-level signal stored in this flip-flop FF. 
     For example, when the output voltage FB of the DC/DC converter exceeds the reference voltage e 3  (namely overvoltage), the set terminal S of the flip-flop FF inputs a high-level signal as the 0V derived from the voltage comparator IC 2 . In this case, the flip-flop FF stores therein the high-level signal inputted to the set terminal S, and the non-inverting output terminal Q thereof outputs the high-level signal stored in this flip-flop FF. 
     The inverting output terminal *Q of the flip-flop FF is connected to the AND gate circuit AND 1 . This inverting output terminal *Q outputs such a value produced by inverting the signal value stored in the flip-flop FF, namely signals whose high level and low level are inverted are outputted. 
     For instance, the inverting output terminal *Q outputs a high-level signal when the 0V stored in the flip-flop FF is the low-level signal (output voltage FB of DC/DC converter is lower than, or equal to reference voltage e 3 ). Also, the inverting output terminal *Q outputs a high-level signal when the 0V stored in the flip-flop FF is a high-level signal (if the output voltage FB of the DC/DC converter exceeds the reference voltage e 3 ). 
     (AND GATE CIRCUIT AND 1 ) 
     The AND gate circuit AND 1  inputs thereinto the signal outputted from the PWM comparator  9  and the signal outputted from the inverting output terminal *Q of the flip-flop FF. This AND gate circuit AND 1  AND-gates the signal derived from the PWM comparator  9  and the signal from the flip-flop FF to thereby output a signal indicative of this calculation result. The signal outputted from the AND gate circuit AND 1  is entered to the drive- 1  ( 10 ). 
     For instance, when the output voltage FB from the DC/DC converter is lower than, or equal to the reference voltage e 3 , the AND gate circuit AND 1  inputs a high-level signal from the inverting output terminal *Q of the flip-flop FF. In this case, the AND gate circuit AND 1  directly outputs the signal from the PWM comparator  9 . As a result, when the output voltage FB is lower than, or equal to the reference voltage e 3 , the drive- 1  ( 10 ) is operated in response to the signal from the PWM comparator  9 . 
     Also, when the output voltage FB from the DC/DC converter is higher than the reference voltage e 3 , the AND gate circuit AND 1  inputs a low-level signal from the inverting output terminal *Q of the flip-flop FF. In this case, the AND gate circuit AND 1  outputs a low-level signal, irrelevant to the signal from the PWM comparator  9 . As a result, when the output voltage FB becomes the overvoltage, the drive- 1  ( 10 ) is operated in response to the low-level signal from the flip-flop FF irrelevant to the signal from the PWM comparator  9 . 
     (OR GATE CIRCUIT OR 1 ) 
     The OR gate circuit OR 1  inputs thereinto the signal outputted from the synchronous rectification control circuit  13  and the signal outputted from the non-inverting output terminal Q of the flip-flop FF. The OR gate circuit OR 1  OR-gates the signal outputted from the synchronous rectification control circuit  13  and the signal outputted from the flip-flop FF, and outputs a signal indicative of this calculation result. The signal outputted from this OR gate circuit OR 1  is inputted to the drive- 2  ( 11 ). 
     For instance, when the output voltage FB of the DC/DC converter is lower than, or equal to the reference voltage e 3 , the OR gate circuit OR 1  inputs thereinto the low-level signal from the non-inverting output terminal Q of the flip-flop FF. In this case, the OR gate circuit OR 1  directly outputs the signal derived from the synchronous rectification control circuit  13 . As a result, in the case that the output voltage FB is lower than, or equal to the reference voltage e 3 , the drive- 2  ( 11 ) is operated in response to the signal derived from the synchronous rectification control circuit  13 . 
     Also, when the output voltage FB of the DC/DC converter is larger than the reference voltage e 3  (namely, overvoltage), the OR gate circuit OR 1  inputs thereinto the high-level signal from the non-inverting output terminal Q of the flip-flop FF. In this case, the OR gate circuit OR 1  directly outputs the high-level signal, irrelevant to the signal derived from the synchronous rectification control circuit  13 . As a result, in the case that the output voltage FB becomes the overvoltage, the drive- 2  ( 11 ) is operated in response to the high-level signal derived from the flip-flop FF, irrelevant to the signal derived from the synchronous rectification control circuit  13 . 
     (DRIVE- 1  ( 10 )) 
     In response to the signal from the AND gate circuit AND 1 , the drive- 1  ( 10 ) turns ON/OFF the main switching transistor Tr 1 . 
     For example, when the high-level signal from the AND gate circuit AND 1  is inputted, the drive- 1  ( 10 ) supplies the power supplied from the charge pump circuit  12  to the main switching transistor Tn, so that the main switching transistor Tn is brought into the ON state. 
     Also, when the low-level signal from the AND gate circuit AND 1  is inputted, the drive- 1  ( 10 ) interrupts the supply of power to the main switching transistor Tr 1 , so that this main switching transistor Tn is brought into the OFF state. 
     OPERATION/EFFECTS OF EMBODIMENT MODE 2 
     A description will now be made of operation/effects of the second DC/DC converter according to the second embodiment of the present invention. 
     (1) In a Case that Second DC/DC Converter is Operable Under Normal Condition 
     In a case that the second DC/DC converter is normally operated, namely when-the output voltage FB from the DC/DC converter indicates the normal voltage value, since the output voltage FB becomes sufficiently lower than the reference voltage e 3 , the voltage comparator IC 2  outputs a signal indicative of a low level. 
     In this case, the low-level signal outputted from the voltage comparator IC 2  is inputted to the set terminal S of the flip-flop FF of the control circuit CTL. Then, the flip-flop FF stores the inputted low-level signal. At this time, the non-inverting output terminal Q of the flip-flop FF outputs the low-level signal stored in the flip-flop FF. The inverting output terminal *Q of the flip-flop FF outputs a high-level signal. 
     The low-level signal outputted from the non-inverting output terminal Q of the flip-flop FF is inputted to the OR gate circuit OR 1 . In this case, the OR gate circuit OR 1  directly outputs the signal (low-level signal or high-level signal) derived from the synchronous rectification control circuit  13 . The signal outputted from the OR gate circuit OR 1  is inputted to the drive- 2  ( 11 ). 
     The drive- 2  ( 11 ) turns ON/OFF the synchronous rectification transistor Tr 2  in response to the signal from the OR gate circuit OR 1 , namely the signal from the synchronous rectification control circuit  13 . As a result, the drive- 2  ( 11 ) can turn ON the synchronous rectification transistor Tr 2  during a time period while the main switching transistor Tr 1  is under OFF state, and the diode D 1  discharges the energy stored in the choke coil L 1  to the output side. 
     The high-level signal outputted from the inverting output terminal *Q of the flip-flop FF is inputted into the AND gate circuit AND 1 . In this case, the AND gate circuit AND 1  directly outputs the signal (low-level signal, or high-level signal) derived from the PWM comparator  9 . The signal outputted from this AND gate circuit AND 1  is entered into the drive- 1  ( 10 ). 
     The drive- 1  ( 10 ) turns ON/OFF the main switching transistor Tr 1  in response to the signal derived from the AND gate circuit AND  1 , namely the signal from the PWM comparator  9 . As a result, the drive- 1  ( 10 ) turns ON the main switching transistor Tr 1  when the triangle wave from the triangle wave oscillator  8  is higher than the voltage value derived from the error amplifier ER 1 , whereas the drive- 1  ( 10 ) turned OFF the main switching transistor Tr 1  when the triangle wave from the triangle oscillator  8  is lower than the voltage value derived from the error amplifier ERA  1 . 
     (2) In a Case that Signal Line  4  is Disconnected 
     In such a case that the signal line  4  is disconnected, the control circuit CTL cannot enter therein the output voltage FB from the second DC/DC converter. At this time, no voltage is applied to the dividing resistor R 2 /R 3  of the control circuit CTL. As a result, a value of a signal outputted from the dividing resistor R 2 /R 3  becomes smaller than the target voltage V ref . 
     When the value of the signal outputted from the dividing resistor R 2 /R 3  becomes smaller than the target voltage V ref , the error amplifier ERA 1  outputs a signal with a value indicative of a negative value. At this time, the value outputted from the error amplifier ERA 1  becomes smaller than the triangle wave oscillated from the triangle wave oscillator  8 . 
     When the signal value derived from the error amplifier ERA 1  becomes smaller than the triangle wave derived from the triangle wave oscillator  8 , the PWM comparator  9  outputs a high-level signal. The high-level signal outputted from the PWM comparator  9  is inputted to the AND gate circuit AND 1 . 
     On the other hand, since the output voltage from the DC/DC converter is sufficiently lower than the reference voltage e 3  of the power supply e 3 , the voltage comparator IC 2  outputs a low-level signal. 
     The low-level signal outputted from the voltage comparator IC 2  is inputted to the set terminal S of the flip-flop FF of the control circuit CTL. At this time, the inverting output terminal *Q of the voltage comparator IC 2  outputs a high-level signal. The high-level signal outputted from the inverting output terminal *Q of the flip-flop FF is inputted into the AND gate circuit AND 1 . 
     As described above, the AND gate circuit AND 1  inputs thereinto the high-level signal from the PWM comparator  9  and the high-level signal from the flip-flop FF. At this time, the AND gate circuit AND 1  outputs a high-level signal. This high-level signal outputted from the AND gate circuit AND 1  is entered into the drive- 1  ( 10 ). 
     The drive- 1  ( 10 ) for entering therein the high-level signal supplies the drive power from the charge pump circuit  12  to the main switching transistor Tr 1  so as to turn ON this main switching transistor Tr 1 . 
     On the other hand, since the signal line  4  is brought into the disconnect condition, the control circuit CTL continues the control for increasing the output voltage FB in the above-described manner, while could not recognize the output voltage FB of the DC/DC converter. As a result, the output voltage of the DC/DC converter is actually increased. Therefore, there is a risk that the overvoltage state happens to occur. 
     When the output voltage from the DC/DC converter is under overvoltage state, since the output voltage becomes higher than the reference voltage e 3 , the voltage comparator IC 2  outputs a high-level signal. The high-level signal outputted from the voltage comparator IC 2  is inputted to the set terminals of the flip-flop FF of the control circuit CTL. 
     The flip-flop FF stores therein the high-level signal inputted into the set terminal S thereof. At this time, the non-inverting output terminal Q of the flip-flop FF outputs a high-level signal, and the inverting output terminal *Q thereof outputs a low-level signal. 
     The high-level signal outputted from the non-inverting output terminal Q of the flip-flop FF is inputted to the OR gate circuit OR 1 . At this time, the OR gate circuit OR 1  outputs a high-level signal, irrelevant to the signal derived from the synchronous control circuit  13 . The high-level signal outputted from the OR gate circuit OR 1  is inputted to the drive- 2  ( 11 ). 
     The drive- 2  ( 11 ) for inputting thereinto the high-level signal supplies the drive power from the charge pump circuit  13  to the synchronous rectification transistor Tr 2 , so that the synchronous rectification transistor Tr 2  is brought into the ON state. 
     The low-level signal outputted from the inverting output terminal *Q of the flip-flop FF is inputted to the AND gate circuit AND 1 . At this time, the AND gate circuit AND 1  outputs a low-level signal, irrelevant to the signal derived from the PWM circuit  9 . The low-level signal outputted from the AND gate circuit AND 1  is inputted to the drive- 1  ( 10 ). 
     The drive- 1  ( 10 ) for inputting thereinto the low-level signal interrupts the supply of power to the main switching transistor Tr 1 , so that the switching transistor Tr 1  is brought into the OFF state. 
     As previously explained, when the output voltage of the DC/DC converter is brought into the overvoltage state, the main switching transistor Tr 1  is forcibly turned OFF, and at the same time, the synchronous rectification transistor Tr 2  is forcibly turned ON. 
     As a consequence, the signal line  26 , the synchronous rectification transistor Tr 2 , the signal line  2 , the signal line  1 , the choke coil L 1 , the signal line  15 , the resistor R 1 , and the signal line  16  are connected to each other, so that the output voltage of the second DC/DC converter is clamped to the ground potential (0V) connected to the signal line  26 . 
     Accordingly, it is possible to prevent the overvoltage from being applied to the load of the second DC/DC converter. 
     According to the DC/DC converter of this second embodiment, no longer the high withstanding voltage type smoothing organic capacitor is required as the capacitor C 1 . Moreover, the burn-out preventing fuse is not required, resulting in the reduction of a total number of constructive elements. 
     In addition, since the burn-out preventing fuse for the capacitor C 1  is not required, the resistance value of the second DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     (3) In a Case that Main Switching Transistou Tr 1  is Shortcircuited 
     When the main switching transistor Tr 1  is shortcircuited, since the signal line  14  is connected to the signal line  1 , there is a risk that the output voltage of the second DC/DC converter is brought into the overvoltage state. 
     When the output voltage becomes the overvoltage condition due to the shortcircuit failure of the main switching transistor Tr 1 , since the output voltage is increased higher than the reference voltage e 3 , the output comparator IC 2  outputs a high-level signal. 
     As previously explained in the item (2), at this time, the control circuit CTL forcibly turns ON the synchronous rectification transistor Tr 2 , so that the output voltage of the DC/DC converter is clamped to the ground level. As a consequence, it is possible to present the overvoltage from being applied to the load of the DC/DC converter. 
     Furthermore, as indicated in the above-explained embodiment mode 1, if a fuse is provided at a half way of the signal line  14 , then the voltage applied to the DC/DC converter is shortcircuited via this fuse, the signal line  14 , the main switching transistor Tr 1 , the signal line  1 , the signal line  2 , and the synchronous rectification transistor Tr 2 . At this time, the fuse is melt down by this shortcircuit current. 
     As a result, the voltage applied to the DC/DC converter is interrupted within a very short time period, so that it is possible to prevent the overvoltage from being applied to this DC/DC converter at an earlier stage. 
     Accordingly, in accordance with the DC/DC converter of this embodiment mode, when the overvoltage condition happens to occur, the circuit of the second DC/DC converter and the load thereof can be firmly protected. 
     According to the DC/DC converter of this second embodiment, no longer the high withstanding voltage type organic capacitor is required as the smoothing capacitor C 1 . Moreover, the burn-out preventing fuse is not required, resulting in the reduction of a total number of constructive elements could. 
     In addition, since the burn-out preventing fuse for the smoothing capacitor C 1  is not required, the resistance value of the second DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     ANOTHER EMBODIMENT MODE OF SECOND DC/DC CONVERTER 
     In the DC/DC converter according to the embodiment mode 2, the voltage comparator IC 2  and the power supply e 3  are provided independent from the control circuit CTL. Alternatively, as represented in FIG.  7  and FIG. 8, the voltage comparator IC 2  and the power supply e 3  may be employed within the control circuit CTL. 
     In this case, as shown in FIG. 7, the signal line  21  is directly connected to the control circuit CTL. Further, as indicated in FIG. 8, the control circuit CTL is constructed of a dividing resistor R 6 /R 7  connected to the signal line  21 , the voltage comparator IC 2  connected to this dividing resistor R 6 /R 7 , and the power supply e 3  connected to this voltage comparator IC 2 . 
     The dividing resistor R 6 /R 7  is a resistor for sensing the voltage inputted via the signal line  21 . The voltage sensed by this dividing resistor R 6 /R 7  is inputted to the non-inverting input terminal of the voltage comparator IC 2 . 
     The inverting input terminal of the voltage comparator IC 2  is connected via a signal line  28  to the power supply e 3 . 
     Further, the output terminal of the voltage comparator IC 2  is connected via a signal line  29  to the set terminal S of the flip-flop FF. 
     When the control circuit CTL is arranged in the above-described manner, if the voltage outputted from the cell DC/DC converter becomes the overvoltage, then the output voltage under overvoltage state is inputted to the dividing resistor R 6 /R 7  of the control circuit CTL. 
     The dividing resistor R 6 /R 7  senses the voltage value of this output voltage under overvoltage state. 
     The voltage value sensed by this dividing resistor R 6 /R 7  is inputted to the non-inverting input terminal of the voltage comparator IC 2 . 
     The voltage comparator IC 2  subtracts the reference voltage e 3  derived from the power supply e 3  from the voltage value derived from the dividing resistor R 6 /R 7 . At this time, since the voltage value from the dividing resistor R 6 /R 7  becomes higher than the reference voltage e 3 , the voltage comparator IC 2  outputs a high-level signal. 
     As a result, the high-level signal outputted from the voltage comparator IC 2  is inputted to the set terminal S of the flip-flop FF. 
     Accordingly, the control circuit CTL can perform a similar control operation to that of the above-described embodiment. 
     As described, even when both the voltage comparator IC 2  and the power supply e 3  are build in the control circuit CTL, it is possible to achieve an advantage similar to that of the above-explained embodiment mode 1. 
     EMBODIMENT MODE 3 
     FIG. 9 is a schematic diagram for showing a DC-to-DC converter according to a third embodiment mode 3 of the present invention. It should be noted that the same reference numerals used in the above-described embodiment modes 1 and 2 will be employed as those for denoting the same or similar constructive elements in the following embodiment mode. 
     ARRANGEMENT OF THIRD DC/DC CONVERTER 
     The DC/DC converter is constructed of a fuse F 1 , a voltage comparator IC 1 , power supply e 1 , capacitor C 3 , capacitor C 2 , an OR gate circuit OR 3 , a control circuit CTL, a main switching transistor Tr 1 , a synchronous rectification transistor Tr 2 , a diode D 1 , a choke coil L 1 , a resistor R 1   a , capacitor C 1 , a voltage comparator IC 2 , and a power supply e 3 . 
     CIRCUIT CONNECTIONS FOR THIRD DC/DC CONVERTER 
     Now, connection modes of the above-described constructive elements will be described. 
     The fuse F 1  is employed in a half way of a signal line  14  used to connect the cell with the main switching transistor Tr 1 . 
     The main switching transistor Tr 1  connected via this signal line  14  to the cell is connected via another signal line  1  to the choke coil L 1 , and via another signal line  24  to the control circuit CTL. 
     The choke coil L 1  connected via the signal line  1  with the main switching transistor Tr 1  is further connected via the signal line  15  is to the resistor Ri. 
     The resistor R 1  connected via the signal line  15  to the choke coil L 1  is connected via a signal line  16  to the load. 
     Four signal lines  31 ,  17 ,  18 ,  19  are connected to a half way of the signal line  14  for connecting the fuse F 1  with the main switching transistor Tr 1 . 
     The signal line  31  located near the fuse F 1  among the above-described four signal lines  31 ,  17 ,  18 ,  19  is connected via the capacitor C 3  to the ground. 
     The signal line  17  among the above-described four signal lines  31 ,  17 ,  18 ,  19  is connected to the voltage comparator IC 1 . This voltage comparator IC 1  owns, for example, a non-inverting input terminal, an inverting input terminal, and an output terminal. In this case, the signal line  17  is connected to the non-inverting input terminal of the voltage comparator IC 1 . The inverting input terminal of the voltage comparator IC 1  is connected via another signal line  22  to the power supply e 1 . Furthermore, the output terminal of the voltage comparator IC 1  is connected via a signal line  23  to the OR gate circuit OR 3 . 
     The signal line  18  among the above-explained four signal lines  31 ,  17 ,  18 ,  19  is connected to the control circuit CTL. A signal line  18   a  is connected to a half way of this signal line  18 . This signal line  18   a  is connected via the capacitor C 2  to the ground. 
     The signal line  19  located near the main switching transistor Tr 1  among the four signal lines  31 ,  17 ,  18 ,  19  is connected to the control-circuit CTL. 
     Two signal lines  2  and  3  are connected to a half way of the signal line  1  used to connect the main switching transistor Tr 1  with the choke coil L 1 . 
     The signal line  2  located near the main switching transistor Tr 1  among the two signal lines  2  and  3  is connected to the synchronous rectification transistor Tr 2 . This synchronous rectification transistor Tr 2  is connected via the signal line  25  to the control circuit CTL, and via a signal line  26  to the ground. 
     The signal line  3  located near the choke coil L 1  among the two signal lines  2  and  3  is connected to the cathode terminal of the diode D 1 . The anode terminal of this diode D 1  is connected via a signal line  27  to the ground. 
     Further, a single signal line  20  is connected to a half way of the signal line  15  for connecting the choke coil C 1  to the resistor R 1 . 
     The signal line  20  is connected to the control circuit CTL, and is such a signal line for entering the voltage CS which is inputted to the resister R 1  to the control circuit CTL. 
     Three signal lines  4 ,  5 ,  21  are connected to a half way of the signal line  16  for connecting the resistor R 1  and the load. 
     The signal line  4  located near the resistor R 1  among the three signal lines  4 ,  5 ,  21  is connected to the control circuit CTL. This signal line  4  is a signal line for feeding back the voltage value FB outputted from the DC/DC converter to the control circuit CTL. 
     A central signal line  5  among the three signal lines  4 ,  5 ,  21  is connected via the smoothing capacitor C 1  to the ground. 
     The signal line  21  located near the load among the three signal lines  4 ,  5 ,  21  is connected to the voltage comparator IC 2 . This voltage comparator IC 2  is, for instance, a voltage comparator having a non-inverting input terminal, an inverting input terminal, and an output terminal. In this case, the signal line  21  is connected to the non-inverting input terminal of the voltage comparator IC 2 . The inverting input terminal of the voltage comparator IC 2  is connected via the signal line  28  to the power supply e 3 . Furthermore, the output terminal of the voltage comparator IC 2  is connected via the signal line  29  to the OR gate circuit OR 3 . 
     In addition, as described above, the OR gate circuit OR 3  is connected via the voltage comparator IC 1  and the signal line  23 , and at the same time, via the voltage comparator IC 2  and the signal line  29 . This OR gate circuit OR 3  is such a circuit having two input terminals and one output terminal. In this case, the signal line  23  and the signal line  29  are connected to the above two input terminals. The output terminal of the OR gate circuit OR 3  is connected via the signal line  30  to the control circuit CTL. 
     Also, as explained before, the signal lines  30 ,  18 ,  19 ,  24 ,  25 ,  20 ,  4  are connected to the control circuit CTL, and at the same time, either an ON instruction value or an OFF instruction value, and a target voltage V ref  are externally inputted thereto. 
     CIRCUIT FUNCTIONS OF THIRD DC/DC CONVERTER 
     Then, functions of the above-described respective constructive elements will now be explained. It should be understood that explanations about the same constructive elements as those of the embodiment modes 1 and 2 are omitted. 
     (OR GATE CIRCUIT OR 3 ) 
     The OR gate circuit OR 3  inputs thereinto the signal outputted from the voltage comparator IC 1  and the voltage outputted from the voltage comparator IC 2 . Then, the OR gate circuit OR 3  outputs a high-level signal for indicating that the overvoltage condition happens to occur when the high-level signal derived from at least one of the voltage comparator IC 1  and the voltage comparator IC 2  is inputted thereinto, namely, when the input voltage of the DC/DC converter is higher than the reference voltage e 1 , or the output voltage of the DC/DC converter is higher than the reference voltage e 3 . 
     Also, the OR gate circuit OR 3  outputs a low-level signal when the low-level signals derived from both the voltage comparator IC 1  and the voltage comparator IC 2  are inputted thereinto, namely, when the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , and also the output voltage of the DC/DC converter is lower than, or equal to the reference voltage e 3 . 
     OPERATION/EFFECTS OF EMBODIMENT MODE 3 
     A description will now be made of operation/effects of the third DC/DC converter according to the third embodiment of the present invention. 
     (1) In a Case that Third DC/DC Converter is Operable Under Normal Condition 
     In a case that the third DC/DC converter is normally operated, namely when the input voltage to the DC/DC converter is lower than, or equal to the reference voltage e 1 , and further, the output voltage from the DC/DC converter is lower than, or equal to the reference voltage e 3 , the voltage comparator IC 1  and the voltage comparator IC 2  output low-level signals. 
     The low-level signals outputted from the voltage comparator IC 1  and the voltage comparator IC 2  are inputted to the OR gate circuit OR 3 . In this case, the OR gate circuit OR 3  outputs a low-level signal. 
     The low-level signal outputted from the OR gate circuit OR 3  is inputted to the set terminal S of the flip-flop FF of the control circuit CTL. Then, the flip-flop FF stores the inputted low-level signal. At this time, the output terminal of the flip-flop FF outputs the low-level signal stored in the flip-flop FF. 
     The low-level signal outputted from the output terminal Q of the flip-flop FF is inputted to the OR gate circuit OR 1  and the OR gate circuit OR 2 . 
     The OR gate circuit OR 1  directly outputs the signal (low-level signal or high-level signal) derived from the synchronous rectification control circuit  13 . The signal outputted from the OR gate circuit OR 1  is inputted to the drive- 2  ( 11 ). 
     The drive- 2  ( 11 ) turns ON/OFF the synchronous rectification transistor Tr 2  in response to the signal from the OR gate circuit OR 1 , namely the signal from the synchronous rectification control circuit  13 . As a result, the drive- 2  ( 11 ) can turn ON the synchronous rectification transistor Tr 2  during a time period while the main switching transistor Tr 1  is under OFF state, and the diode D 1  discharges the energy stored in the choke coil L 1  to the output side. 
     The OR gate circuit OR 2  into which the low-level signal from the flip-flop FF is inputted directly outputs the signal (low-level signal, or high-level signal) derived from the PWM comparator  9 . The signal outputted from this OR gate circuit OR 2  is entered into the drive- 1  ( 10 ). 
     The drive- 1  ( 10 ) turns ON/OFF the main switching transistor Tr 1  in response to the signal derived from the OR gate circuit OR 2 , namely the signal from the PWM comparator  9 . As a result, the drive- 1  ( 10 ) turns ON the main switching transistor Tr 1  when the triangle wave from the triangle wave oscillator  8  is higher than the voltage value derived from the error amplifier ERA 1 , whereas the drive- 1  ( 10 ) turned OFF the main switching transistor Tr 1  when the triangle wave from the triangle oscillator  8  is lower than the voltage value derived from the error amplifier ERA  1 . 
     (2) In a Case that Input Voltage to Third DC/DC Converter is Under Overvoltage Condition 
     In such a case that a voltage inputted to the third DC/DC converter becomes an overvoltage, since the input voltage is higher than the reference voltage e 1 , the signal derived from the voltage comparator IC 1  is a signal indicative of a high level. The high-level signal outputted from the voltage comparator IC 1  is inputted to the OR gate circuit OR 3 . 
     On the other hand, since the output voltage of the DC/DC converter is lower than the reference voltage e 3 , a signal outputted from the voltage comparator IC 2  becomes a low-level signal. This low-level signal outputted from the voltage comparator IC 2  is inputted into the OR gate circuit OR 3 . 
     As described above, the OR gate circuit OR 3  inputs thereinto the high-level signal from the voltage comparator IC 1  and the low-level signal from the voltage comparator IC 2 . At this time, a 0V outputted from the OR gate circuit OR 3  becomes a high-level signal. The high-level signal outputted from the OR gate OR 3  is inputted into the flip-flop FF of the control circuit CTL. 
     The flip-flop FF into which the high-level signal derived from the OR gate circuit OR 3  is entered stores the inputted high-level signal. Then, the output terminal Q of the flip-flop FF outputs the high-level signal stored in the flip-flop FF. 
     The high-level signal outputted from the output terminal Q of the flip-flop FF is entered into the OR gate circuit OR 1  and the OR gate circuit OR 2 . 
     The OR gate circuit OR 1  into which the high-level signal outputted from the output terminal Q of the flip-flop FF is inputted outputs a high-level signal, irrelevant to the signal from the synchronous rectification control circuit  13 . The drive- 2  ( 11 ) for inputting thereinto the high-level signal derived from the OR gate circuit OR 1  supplies the power from the charge pump circuit  12  to the synchronous rectification transistor Tr 2 . At this time, the synchronous rectification transistor Tr 2  is turned ON to thereby connect between the signal line  2  and the signal line  26 . 
     Also, the OR gate circuit OR 2  into which the high-level signal derived from the flip-flop FF is entered outputs a high-level signal, irrelevant to the signal from the PWM comparator  9 . 
     The high-level signal outputted from the OR gate OR 2  is inputted into the drive- 1  ( 10 ). 
     The drive- 1  ( 10 ) into which the high-level signal from the OR gate circuit OR 2  is inputted supplies the power from the charge pump circuit  12  to the main switching transistor Tr 1 . At this time, the main switching transistor Tr 1  is brought into the ON state to thereby connect between the signal line  14  and the signal line  1 . 
     As a result, the voltage inputted to the DC/DC converter is applied via the fuse F 1 , the signal line  14 , the main switching transistor Tr 1 , the signal line  1 , the signal line  2 , the synchronous rectification transistor Tr 2 , and the signal line  26  to the ground. At this time, an overcurrent will flow through the fuse F 1 , so that this fuse F 1  is melted down. 
     As a result, since the fuse F 1  is melted down, it is possible to prevent the constructive elements of the third DC/DC converter, especially the capacitor C 3  provided in the input unit of this DC/DC converter from being applied by the excessive high voltages. Therefore, it is possible to avoid that the capacitor C 3  would be burned out. 
     According to the DC/DC converter of this third embodiment, no longer the high-withstanding voltage type organic capacitor is required as the capacitor C 3 . Moreover, the burn-out preventing fuse is not required, resulting in the reduction of a total number of constructive elements. 
     In addition, since the burn-out preventing fuse for the capacitor C 3  is not required, the resistance value of the third DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     (3) In a Case that Output Voltage from Third DC/DC Converter is Under Overvoltage Condition 
     In such a case that a voltage outputted from the third DC/DC converter becomes an overvoltage, since the output voltage is higher than the reference voltage e 3 , the signal derived from the voltage comparator IC 2  is a signal indicative of a high level. The high-level signal outputted from the voltage comparator IC 2  is inputted via a signal line  29  to the OR gate circuit OR 3 . 
     On the other hand, since the input voltage of the DC/DC converter is lower than the reference voltage e 1 , a signal outputted from the voltage comparator IC 1  becomes a low-level signal. This low-level signal outputted from the voltage comparator IC 1  is inputted via a signal line  23  into the OR gate circuit OR 3 . 
     The OR gate circuit OR 3  for inputting thereinto the low-level signal from the voltage comparator IC 1  and the high-level signal from the voltage comparator IC 3  will output a high-level signal. The high-level signal outputted from this OR gate circuit OR 3  is inputted into the control circuit CTL. 
     As previously described in item (1), the control circuit CTL forcibly turns ON the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2 . Thus, the input voltage to the third DC/DC converter is conducted through the fuse F 1 , the signal line  14 , the main switching transistor Tr 1 , the signal line  1 , the signal line  2 , the synchronous rectification transistor Tr 2 , and the signal line  26  to the ground. At this time, an overcurrent will flow through the fuse F 1 , so that this fuse F 1  is melted down. 
     As a result, the voltage inputted to the third DC/DC converter is interrupted, it is possible to prevent the overvoltage from being applied to the load of this DC/DC converter. 
     Therefore, according to the third DC/DC converter, when the output voltage of this DC/DC converter is brought into the overvoltage state, the circuit of this DC/DC converter and the load can be surely protected. 
     According to the DC/DC converter of this third embodiment, no longer the high withstanding voltage type organic capacitor is required as the smoothing capacitor C 1 . Moreover, the burn-out preventing fuse is not required, resulting in the reduction of a total number of constructive elements. 
     In addition, since the burn-out preventing fuse for the smoothing capacitor C 1  is not required, the resistance value of the third DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     EMBODIMENT MODE 4 
     FIG. 10 is a schematic diagram for showing a DC-to-DC converter according to a fourth embodiment mode 4 of the present invention. It should be noted that the same reference numerals used in the embodiment modes 1 to 3 will be employed as those for denoting the same or similar constructive elements in the following embodiment mode. 
     ARRANGEMENT OF FOURTH DC/DC CONVERTER 
     The DC/DC converter according to this embodiment mode 4 is constructed of a fuse F 1 , a voltage comparator IC 1 , a power supply e 1 , a capacitor C 3 , a capacitor C 2 , a control circuit CTL, a main switching transistor Tr 1 , a synchronous rectification transistor Tr 2 , a diode D 1 , a choke coil L 1 , a resistor R 1 , a capacitor C 1 , a voltage comparator IC 2 , and a power supply e 3 . 
     (CIRCUIT CONNECTIONS FOR FOURTH DC/DC CONVERTER) 
     Now, connection modes of the above-described constructive elements will be described. It should be understood that only different connection mode from the above-explained connection mode 3 will now be explained. 
     An output terminal of the voltage comparator IC 1  is directly connected via a signal line  23  to the control circuit CTL. In this case, a 0V1 outputted from the voltage comparator IC 1  is inputted via the signal line  23  to the control circuit CTL. 
     An output terminal of the voltage comparator IC 2  is directly connected via a signal line  29  to the control circuit CTL. In this case, a 0V2 outputted from the voltage comparator IC 2  is inputted via the signal line  29  to the control circuit CTL. Other connection modes are identical with that of the above described embodiment mode 3. 
     (CIRCUIT FUNCTIONS OF FOURTH DC/DC CONVERTER) 
     Then, functions of the above-described respective constructive elements will now be explained. It should be understood that explanations about the same constructive elements as those of the embodiment mode 3 are omitted. 
     (CONTROL CIRCUIT CTL) 
     The control circuit CTL is connected via the signal line  23  to the output terminal of the voltage comparator IC 1 , and then inputs thereinto the 0V1 outputted from the voltage comparator IC 1 . 
     The control circuit CTL is connected via the signal line  29  to the output terminal of the voltage comparator IC 2 , and then inputs thereinto the 0V2 outputted from the voltage comparator IC 2 . 
     In this case, when such a signal (high-level signal) for indicating that the input voltage to the fourth DC/DC converter is under overvoltage state is inputted as the 0V1 derived from the voltage comparator IC 1 , the control circuit CTL forcibly turns ON the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2 , so that the fuse F 1  is melted down. 
     Also, when such a signal (high-level signal) for indicating that the output voltage from the fourth DC/DC converter is under overvoltage state is inputted as the 0V2 derived from the voltage comparator IC 2 , the control circuit CTL forcibly turns OFF the main switching transistor Tr 1  and, at the same time, forcibly turns ON the synchronous rectification transistor Tr 2 , so that the output voltage from this DC/DC converter is clamped to the ground level. 
     An internal circuit arrangement of the control circuit CTL for realizing the above-described functions will be explained. 
     (ARRANGEMENT OF CONTROL CIRCUIT CTL) 
     As indicated in FIG. 11, the control circuit CTL is constructed of a power supply  7 , a triangle wave oscillator  8 , a PMW comparator  9 , a charge pump circuit  12 , a synchronous rectification control circuit  13 , a flip-flop FF 1  a flip-flop FF 2 , a drive- 1  ( 10 ), and another drive- 2  ( 11 ). The control circuit CTL further includes a dividing resistor R 2 /R 3 , error amplifiers ERA 1  and ERA 2 , an AND gate circuit AND 1 , an OR gate circuit OR 1 , another OR gate circuit OR 4 , and another OR gate circuit OR 5 . 
     (FLIP-FLOP FF 1 ) 
     The flip-flop FF 1  owns two input terminals as a set terminal S and a reset terminal R, and an output terminals Q. The set terminal S of the flip-flop FF 1  inputs thereinto the 0V1 outputted from the voltage comparator IC 1 . When the 0V1 is inputted to this set terminal S, the flip-flop FF 1  stores therein the signal 0V 1  entered into the set terminal S. 
     The reset terminal R of the flip-flop FF 1  inputs thereinto either the externally ON instruction value or OFF instruction value. The content stored in the flip-flop FF 1  is reset, and a low-level signal is stored when either the ON instruction value or the OFF instruction value is inputted to this reset terminal R. 
     Furthermore, the output terminal Q of the flip-flop FF 1  is connected to the OR gate circuit OR 1  and the OR gate circuit OR 4 . This output terminal Q outputs the signal stored in the flip-flop FF 1 . 
     For example, when the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , the set terminal S of the flip-flop FF 1  inputs thereinto a low-level signal as the 0V1 derived from the voltage comparator IC 1 . In this case, the flip-flop FF 1  stores therein the low-level signal inputted to the set terminal S. Then the output terminal Q thereof outputs the low-level signal stored in this flip-flop FF 1 . 
     Also, when the input voltage of the DC/DC converter exceeds the reference voltage e 1  (when input voltage becomes overvoltage), the set terminal S of the flip-flop FF 1  inputs a high-level signal as the 0V1 derived from the voltage comparator IC 1 . In this case, the flip-flop FF 1  stores therein the high-level signal inputted to the set terminal S, and the output terminal Q thereof outputs the high-level signal stored in this flip-flop FF 1 . 
     (FLIP-FLOP FF 2 ) 
     The flip-flop FF 2  owns two input terminals as a set terminal and a reset terminal, and two output terminals as a non-inverting output terminal Q and an inverting output terminal *Q. The set terminal S of the flip-flop FF 2  inputs thereinto the 0V2 outputted from the voltage comparator IC 2 . 
     The reset terminal R of the flip-flop FF 2  inputs thereinto either the externally ON instruction value or OFF instruction value. The signal stored in the flip-flop FF is reset to a low-level signal when either the ON instruction value or the OFF instruction value is inputted to the reset terminal. 
     Furthermore, the non-inverting output terminal Q of the flip-flop FF 2  is connected to the OR gate circuit OR 5 . This output terminal Q directly outputs the signal stored in the flip-flop FF 2 . 
     For example, when the output voltage of the DC/DC converter is lower than, or equal to the reference voltage e 3 , the set terminal S of the flip-flop FF 2  inputs thereinto a low-level signal as the 0V2 derived from the voltage comparator IC 2 . In this case, the flip-flop FF 2  stores therein the low-level signal inputted to the set terminal S, and the non-inverting output terminal Q thereof outputs the low-level signal stored in this flip-flop FF 2 . 
     Also, when the output voltage of the DC/DC converter exceeds the reference voltage e 3  (when output voltage becomes overvoltage), the set terminal S of the flip-flop FF 2  inputs a high-level signal as the 0V2 derived from the voltage comparator IC 2 . In this case, the flip-flop FF 2  stores therein the high-level signal inputted to the set terminal S, and the non-inverting output terminal Q thereof outputs the high-level signal stored in this flip-flop FF 2 . 
     The inverting output terminal *Q of the flip-flop FF 2  is connected to the AND gate circuit AND 1 . This inverting output terminal *Q outputs a value produced by inverting the signal value stored in the flip-flop FF 2 , namely signals whose high level and low level are inverted are outputted. 
     For instance, the-inverting output terminal *Q outputs a high-level signal when the 0V2 stored in the flip-flop FF 2  is the low-level signal (output voltage of DC/DC converter is lower than, or equal to reference voltage e 3 ). Also, the inverting output terminal *Q outputs a low-level signal when the 0V2 stored in the flip-flop FF 2  is a high-level signal (if the output voltage of the DC/DC converter exceeds the reference voltage e 3 ). 
     (AND GATE CIRCUIT AND 1 ) 
     The AND gate circuit AND 1  inputs thereinto the signal outputted from the PWM comparator  9  and the signal outputted from the inverting output terminal *Q of the flip-flop FF 2 . This AND gate circuit AND 1  AND-gates the signal derived from the PWM comparator  9  and the signal from the flip-flop FF 2  to thereby output a signal indicative of this calculation result. The signal outputted from the AND gate circuit AND 1  is entered to the OR gate-circuit OR 4 . 
     For instance, when the output voltage from the DC/DC converter is lower than, or equal to the reference voltage e 3 , the AND gate circuit AND 1  inputs the signal from the PWM comparator  9 , and a high-level signal from the inverting output terminal *Q of the flip-flop FF 2 . In this case, the AND gate circuit AND 1  directly outputs the signal from the PWM comparator  9 . 
     Also, when the output voltage from the DC/DC converter is higher than the reference voltage e 3 , the AND gate circuit AND 1  inputs the signal from the PWM. comparator  9 , and a low-level signal from the inverting output terminal *Q of the flip-flop FF 2 . In this case, the AND gate circuit AND 1  outputs a low-level signal, irrelevant to the signal from the PWM comparator  9 . 
     (OR GATE CIRCUIT OR 4 ) 
     The OR gate circuit OR 4  inputs thereinto the signal outputted from the AND gate circuit AND 1  and the signal outputted from the output terminal Q of the flip-flop FF 1 . The OR gate circuit OR 4  OR-gates the signal outputted from the AND gate circuit AND 1  and the signal outputted from the output terminal Q of the flip-flop FF 1 , and outputs a signal indicative of this calculation result. The signal outputted from this OR gate circuit OR 4  is inputted to the drive- 1  ( 10 ). 
     For instance, when the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , and also the output voltage thereof is lower than, or equal to the reference voltage e 3 , the OR gate circuit OR 4  inputs thereinto the signal (same as that of PWM comparator  9 ) from the AND gate circuit AND 1 , and the low-level signal from the output terminal Q of the flip-flop FF 1 . In this case, the OR gate circuit OR 4  directly outputs the signal derived from the AND gate circuit AND 1 , namely from the PWM comparator  9 . 
     Also, when the input voltage of the DC/DC converter is higher than the reference voltage e 1 , and the output voltage thereof is lower than, or equal to the reference voltage e 3 , the OR gate circuit OR 4  inputs thereinto the signal (equal to the signal derived from the PWM comparator  9 ) from the-AND gate circuit AND 1 , and the high-level signal from the output terminal Q of the flip-flop FF 1 . In this case, the OR gate circuit OR 4  outputs a high-level signal, irrelevant to the signal derived from the AND gate circuit AND 1 . 
     When the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , and also the output voltage thereof is higher than the reference voltage e 3 , the OR gate circuit OR 4  inputs thereinto the low-level signal from the AND gate circuit AND 1  and the low-level signal from the flip-flop FF 1 . In this case, the OR gate circuit OR 4  outputs the low-level signal. 
     (OR GATE CIRCUIT OR 1 ) 
     The OR gate circuit OR 1  inputs thereinto the signal outputted from the synchronous rectification control circuit  13  and the signal outputted from the output terminal Q of the flip-flop FF 1 . The OR gate circuit OR 1  OR-gates the signal outputted from the synchronous rectification control circuit  13  and the signal outputted from the flip-flop FF 1 , and outputs a signal indicative of this calculation-result. The signal outputted from this OR gate circuit OR 1  is inputted to the OR gate circuit OR 5 . 
     For instance, when the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , the OR gate circuit OR 1  inputs thereinto the signal from the synchronous rectification control circuit  13 , and the low-level signal from the output terminal of the flip-flop FF 1 . In this case, the OR gate circuit OR 1  directly outputs the signal derived from the synchronous rectification control circuit  13 . 
     Also, when the input voltage of the DC/DC converter is higher than the reference voltage e 1 , the OR gate circuit OR 1  inputs thereinto the signal from the synchronous rectification control circuit  13 , and the high-level signal from the output terminal Q of the flip-flop FF 1 . In this case, the OR gate circuit OR 1  outputs a high-level signal, irrelevant to the signal from the synchronous rectification control circuit  13 . 
     (OR GATE CIRCUIT OR 5 ) 
     The OR gate circuit OR 5  inputs thereinto the signal outputted from the OR gate circuit OR 1  and the signal outputted from the output terminal Q of the flip-flop FF 2 . The OR gate circuit OR 5  OR-gates the signal outputted from the circuit OR 1  and the signal outputted from the flip-flop FF 2 , and outputs a signal indicative of this calculation result. The signal outputted from this OR gate circuit OR 5  is inputted to the drive- 2  ( 11 ). 
     For instance, when the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , and also the output voltage is lower than, or equal to the reference voltage e 3 , the OR gate circuit OR 5  inputs thereinto the high-level signal from the OR gate circuit OR 1 , and the low-level signal from the output terminal Q of the flip-flop FF 2 . In this case, the OR gate circuit OR 5  outputs a high-level signal. 
     Also, when the input voltage of the DC/DC converter is higher than the reference voltage e 1 , and also the output voltage is lower than, or equal to the reference voltage e 3 , the OR gate circuit OR 5  inputs thereinto the high-level signal from the OR gate circuit OR 1  and the low-level signal from the output terminal Q of the flip-flop FF 2 . In this case, the OR gate circuit OR 5  outputs a high-level signal. 
     When the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , and the output voltage is higher than the reference voltage e 3 , the OR gate circuit OR 5  inputs thereinto the signal (equal to the signal outputted from the synchronous rectification circuit  13 ) from the OR gate circuit OR 1 , and the high-level signal from the flip-flop FF 2 . In this case, the OR gate circuit OR 5  outputs a high-level signal, irrelevant to the signal from the OR gate circuit OR 1 . 
     (DRIVE- 1  ( 10 )) 
     In response to the signal from the OR gate circuit OR 4 , the drive- 1  ( 10 ) turns ON/OFF the main switching transistor Tr 1 . 
     For example, when the high-level signal from the OR gate circuit OR 4  is inputted, the drive- 1  ( 10 ) supplies the power supplied from the charge pump circuit  12  to the main switching transistor Tr 1 , so that the main switching transistor Tr 1  is brought into the ON state. 
     Also, when the low-level signal from the AND gate circuit AND 1  is inputted, the drive- 1  ( 10 ) interrupts the supply of power to the main switching transistor Tnl, so that this main switching transistor Tnl is brought into the OFF state. 
     OPERATION/EFFECTS OF EMBODIMENT MODE 4 
     A description will now be made of operation/effects of the fourth DC/DC converter according to the fourth embodiment of the present invention. 
     (1) In s Case that Fourth DC/DC Converter is Operable Under Normal Condition 
     In a case that the fourth DC/DC converter is normally operated, namely when the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , and further the output voltage from the DC/DC converter is lower than, or equal to the reference voltage e 3 , the voltage comparator IC 1  and the voltage comparator IC 2  output low-level signals. 
     The low-level signal outputted from the voltage comparator IC 1  is inputted to the set terminal S of the flip-flop FF 1  of the control circuit CTL. Also, the low-level signal outputted from the voltage comparator IC 2  is inputted to the set terminal S of the flip-flop FF 2  of the control circuit CTL. 
     The flip-flop FF 1  into which the low-level signal from the voltage comparator IC 1  is inputted stores therein the inputted low-level signal. Then, the output terminal Q of the flip-flop FF 1  outputs a low-level signal. The low-level signal outputted from the output terminal Q of the flip-flop FF 1  is inputted to the OR gate circuit OR 4  and the OR gate circuit OR 1 . 
     Also, the flip-flop FF 2  into which the low-level signal from the voltage comparator IC 2  is inputted stores therein the inputted low-level signal. Then, the output terminal Q of the flip-flop FF 2  outputs a low-level signal, and the output terminal *Q thereof outputs a high-level signal. The low-level signal outputted from the output terminal Q of the flip-flop FF 2  is inputted to the OR gate circuit OR 5 , and the high-level signal outputted from the output terminal *Q is inputted to the AND gate circuit AND 1 . 
     The AND gate circuit AND 1  inputs thereinto the high-level signal from the output terminal *Q of the flip-flop FF 2 , and also inputs-thereinto the signal from the PWM comparator  9 . At this time, the AND gate circuit AND 1  directly outputs the signal derived from the PWM comparator  9 . The signal outputted from the AND gate circuit AND 1  is inputted to the OR gate circuit OR 4   
     As previously explained, the OR gate circuit OR 4  inputs thereinto the low-level signal from the output terminal Q of the flip-flop FF 1 , and the signal (equal to the signal from the PWM comparator  9 ) from the AND gate circuit AND 1 . In this case, the OR gate circuit OR 4  directly outputs the signal derived from the AND gate circuit AND 1 , namely the signal from the PWM comparator  9 . 
     The signal (equal to the signal from the PWM comparator  9 ) outputted from the OR gate circuit OR 4  is inputted into the drive- 1  ( 10 ). As a result, the drive- 1  ( 10 ) can turn ON/OFF the main switching transistor Tr 1  in response to the signal from the PWM comparator  9 . 
     The OR gate circuit OR 1  into which the low-level signal from the output terminal Q of the flip-flop FF 1  is entered also inputs thereinto the signal derived from the synchronous rectification control circuit  13 . In this case, the OR gate circuit OR 1  directly outputs the signal derived from the synchronous rectification control circuit  13 . The signal (equal to the signal from the synchronous rectification control circuit  13 ) outputted from the OR gate circuit OR 1  is inputted to the OR gate circuit OR 5 . 
     As previously described, the OR gate circuit OR 5  inputs thereinto the signal from the OR gate circuit OR 1  (equal to the signal outputted from the synchronous rectification control circuit  13 ) and the low-level signal from the output terminal Q of the flip-flop FF 2 . At this time, the OR gate circuit OR 5  outputs the signal from the OR gate circuit OR 1 , namely the signal identical to the signal outputted from the synchronous rectification control circuit  13 . The signal outputted from the OR gate circuit OR 5  (equal to the signal outputted from the synchronous rectification control circuit  13 ) is inputted into the drive  2 -( 11 ). As a result, the drive  2 -( 11 ) can turn ON/OFF the synchronous rectification transistor Tr 2  in response to the signal from the synchronous rectification control circuit  13 . 
     (2) In a Case that Input Voltage to Fourth DC/DC Converter is Under Overvoltage State 
     When the voltage inputted into the DC/DC converter is brought into the overvoltage state, the voltage comparator IC 1  outputs a high-level signal. Since the output voltage of the DC/DC converter is lower than, or equal to the reference voltage e 3 , the voltage comparator IC 2  outputs a low-level signal. 
     The high-level signal outputted from the voltage comparator IC 1  is inputted to the set terminal S of the flip-flop FF 1  of the control circuit CTL. Also, the low-level signal outputted from the voltage comparator IC 2  is inputted to the set terminal S of the flip-flop FF 2  of the control circuit CTL. 
     The flip-flop FF 1  into which the high level signal from the voltage comparator IC 1  is inputted stores therein the inputted high-level signal. Then, the output terminal Q of the flip-flop FF 1  outputs a high level signal. The high-level signal outputted from the output terminal Q of the flip-flop FF 1  is inputted to the OR gate circuit OR 4  and the OR gate circuit OR 1 . 
     Also, the flip-flop FF 2  into which the low-level signal from the voltage comparator IC 2  is inputted stores therein the inputted low-level signal. Then, the output terminal Q of the flip-flop FF 2  outputs a low-level signal, and the output terminal *Q thereof outputs a high-level signal. The low-level signal outputted from the output terminal Q of the flip-flop FF 2  is inputted to the OR gate circuit OR 5 , and the high-level signal outputted from the output terminal *Q is inputted to the AND gate circuit AND 1 . 
     The AND gate circuit AND 1  inputs thereinto the high-level signal from the output terminal *Q of the flip-flop FF 2 , and also inputs thereinto the signal from the PWM comparator  9 . At this time, the AND gate circuit AND 1  directly outputs the signal derived from the PWM comparator  9 . The signal outputted from the AND gate circuit AND 1  (equal to the signal from the PWM comparator  9 ) is inputted to the OR gate circuit OR 4 . 
     As previously explained, the OR gate circuit OR 4  inputs thereinto the signal (equal to the signal from the PWM comparator  9 ) from the AND gate circuit AND 1 , and the high-level signal from the output terminal Q of the flip-flop FF 1 . In this case, the OR gate circuit OR 4  directly outputs a high-level signal, irrelevant to the signal derived from the AND gate circuit AND 1  (equal to the signal outputted from the PWM comparator  9 ). As a result, the drive- 1  ( 10 ) turns ON the main switching transistor Tr 1 , irrelevant to the signal outputted from the PWM comparator  9 . 
     Also, the OR gate circuit OR 1  inputs thereinto the high-level signal from the output terminal Q of the flip-flop FF 1 , and also inputs the signal from the synchronous rectification control circuit  13 . In this case, the OR gate circuit OR 1  outputs a high-level signal, irrelevant to the signal from the synchronous rectification control circuit  13 . This high-level signal outputted from the OR gate circuit OR 1  is inputted to the OR gate circuit OR 5 . 
     As explained above, the OR gate circuit OR 5  inputs thereinto the low-level signal from the output terminal Q of the flip-flop FF 2  and the high-level signal from the OR gate circuit OR 1 . At this time, the OR gate circuit OR 5  outputs a high-level signal. As a result, the drive  2 -( 11 ) turns ON the-synchronous rectification transistor Tr 2 , irrelevant to the signal derived from the synchronous rectification control circuit  13 . 
     Thus, when the input voltage to the fourth DC/DC converter is under overvoltage state, the main switching transistor Tr 1  and the synchronous rectification transistor Tr 2  are forcibly turned ON. 
     As a result, the voltage inputted to the DC/DC converter is applied via the fuse F 1 , the signal line  14 , the main switching transistor Tr 1 , the signal line  1 , the signal line  2 , the synchronous rectification transistor Tr 2 , and the signal line  26  to the ground. At this time, an overcurrent will flow through the fuse F 1 , so that this fuse F 1  is melted down. 
     As a result, since the fuse F 1  is melted down, it is possible to prevent the constructive elements of the fourth DC/DC converter, especially the capacitor C 3  provided in the input unit of this DC/DC converter from being applied by the excessive high voltages. Therefore, it is possible to avoid that the capacitor C 3  would be burned out. 
     According to the DC/DC converter of this fourth embodiment, the burn-out preventing fuse for the capacitor C 3  is not required, resulting in the reduction of a total number of constructive elements. 
     In addition, since the burn-out preventing fuse for the capacitor C 3  is not required, the resistance value of the fourth DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     (3) In a Case that Signal Line  4  is Disconnected 
     As previously described in the embodiment mode 2, when the signal line  4  is disconnected, there is a risk that the output voltage of the DC/DC converter is brought into the overvoltage state 
     If the output voltage of the DC/DC converter is brought into the overvoltage state, since the output voltage becomes higher than the reference voltage e 3 , the voltage comparator IC 2  outputs a high-level signal. 
     On the other hand, since the input voltage to the DC/DC converter is lower than, or equal to e 1 , the voltage comparator IC 1  output a low-level signal. 
     The low-level signal outputted from the voltage comparator IC 1  is inputted to the set terminal S of the flip-flop FF 1  of the control circuit CTL. Also, the high-level signal outputted from the voltage comparator IC 2  is inputted to the set terminal S of the flip-flop FF 2  of the control circuit CTL. 
     The flip-flop FF 1  into which the low-level signal from the voltage comparator IC 1  is inputted stores therein the inputted low-level signal. Then, the output terminal Q of the flip-flop FF 1  outputs a low-level signal. The low-level signal outputted from the output terminal Q of the flip-.flop FF 1  is inputted to the OR gate circuit OR 4  and the OR gate circuit OR 1 . 
     Also, the flip-flop FF 2  into which the high-level signal from the voltage comparator IC 2  is inputted stores therein the inputted high-level signal. Then, the output terminal Q of the flip-flop FF 2  outputs a high-level signal, and the output terminal *Q thereof outputs a low-level signal. The high-level signal outputted from the output terminal Q of the flip-flop FF 2  is inputted to the OR gate circuit OR 5 , and the low-level signal outputted from the output terminal *Q is inputted to the AND gate circuit AND 1 . 
     The AND gate circuit AND 1  inputs thereinto the low-level signal from the output terminal *Q of the flip-flop FF 2 , and also inputs thereinto the signal from the PWM comparator  9 . At this time, the AND gate circuit AND 1  directly outputs a low-level signal, irrelevant to the signal derived from the PWM comparator  9 . The low-level signal outputted from the AND gate circuit AND 1  is inputted to the OR gate circuit OR 4 . 
     As described above, the OR gate circuit OR 4  inputs thereinto the low-level signal outputted from the AND gate circuit AND 1  and the the low-level signal from output terminal Q of the flip-flop FF 2 . In this case, the OR gate circuit OR 4  outputs a low-level signal. As a consequence, the drive  1  ( 10 ) turns OFF the main switching transistor Tr 1 , irrelevant to the output signal from the PWM comparator  9 . 
     Also, the OR gate circuit-OR 1  inputs thereinto the low-level signal from the output terminal Q of the flip-flop FF 1 , and also inputs the signal from the synchronous rectification control circuit  13 . In this case, the OR gate circuit OR 1  directly outputs the signal derived from the synchronous rectification control circuit  13 . The signal outputted from this OR gate circuit OR 1  (equal to the signal from the synchronous rectification control circuit  13 ) is entered into the OR gate circuit OR 5 . 
     As explained before, the OR gate circuit OR 5  inputs thereinto the high-level signal from the output terminal Q of the flip-flop FF 2 , and also the signal derived from the OR gate circuit OR 1  (equal to the signal outputted from the synchronous rectification control circuit  13 ). At this time, the OR gate circuit OR 5  outputs a high-level signal, irrelevant to the signal outputted from the OR gate OR 1  (equal to the signal outputted from the synchronous rectification control circuit  13 ). As a result, the drive- 2  ( 11 ) turns ON the synchronous rectification transistor Tr 2 , irrelevant to the signal from the synchronous control circuit  13 . 
     As previously explained, when the output voltage of the DC/DC converter is brought into the overvoltage state, the main switching transistor Tr 1  is forcibly turned OFF, and at the same time, the synchronous rectification transistor Tr 2  is forcibly turned ON. 
     As a consequence, the signal line  26 , the synchronous rectification transistor Tr 2 , the signal line  2 , the signal line  1 , the choke coil L, the signal line  15 , the resistor R 1 , and the signal line  16  are connected to each other, so that the output voltage of the second DC/DC converter is clamped to the ground potential (0V) connected to the signal line  26 . 
     Accordingly, it is possible to prevent the overvoltage from being applied to the load of the second DC/DC converter. At the same time, it is possible to prevent the overvoltage from being applied to the constructive element of the DC/DC converter, especially, to the smoothing capacitor C 1 . 
     Accordingly to the DC/DC converter of this second embodiment, no longer the high withstanding voltage type organic capacitor is required as the smoothing capacitor C 1 . Moreover, the burn-out preventing fuse is not required, resulting in the reduction of a total number of constructive elements. 
     In addition, since the burn-out preventing fuse for the capacitor C 1  is not required, the resistance value of the second DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased. 
     (4) In a Case that Main Switching Transistor Tr 1  is Shortcircuited 
     When the main switching transistor Tr 1  is shortcircuited, since the signal line  14  is connected to the signal line  1 , there is a risk that the output voltage of the fourth DC/DC converter is brought into the overvoltage state. 
     When the output voltage becomes the overvoltage condition due to the shortcircuit failure of the main switching transistor Tr 1 , since the output voltage is increased higher than the reference voltage e 3 , the output comparator IC 2  outputs a high-level signal. 
     On the other hand, since the input voltage of the DC/DC converter is lower than, or equal to the reference voltage e 1 , the 0V1 outputted from the voltage comparator IC 1  becomes a low-level signal. 
     As previously explained in the item (2), at this time, the control circuit CTL forcibly turns OFF the main switching transistor Tr 1 , and at the same time, forcibly turns ON the synchronous rectification transistor Tr 2 . It should be understood that since the main switching transistor Tr 1  fails due to the shortcircuit, the voltage applied to the DC/DC converter is shortcircuited via this fuse F 1 , the signal line  14 , the main switching transistor Tr 1 , the signal line  1 , the signal line  2 , and the synchronous rectification transistor Tr 2 . At this time, the fuse F 1  is melt down by this shortcircuit current. 
     As a result, the voltage applied to the DC/DC converter is interrupted within a very short time period, so that it is possible-to prevent the overvoltage from being applied to the load of this DC/DC converter at an earlier stage. At the same time, it is possible to prevent the overvoltage from being applied to the constructive element of the DC/DC converter. 
     According to the DC/DC converter of this fourth embodiment, no longer the high withstanding voltage type organic capacitor as the smoothing capacitor C 1  is required as the capacitor C 2 . Moreover, the burn-out preventing fuse is not required, resulting in the reduction of a total number of constructive elements. 
     In addition, since the burn-out preventing fuse for the smoothing capacitor C 1  is not required, the resistance value of the second DC/DC converter would be lowered, so that the converting efficiency of the DC/DC converter could be increased.

Technology Classification (CPC): 8