Patent Abstract:
The present invention relating to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a TFT on the substrate, forming an inter-layer insulator layer, forming a plurality of via holes, forming a metal layer which electrically contacts a source and a drain, forming a transparent electrode, a pixel define layer and a LED. Because the present invention omits a passivation layer, the cost decreases and the process is simpler.

Full Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     A method of manufacturing a TFT panel, and more particularly, to a method of manufacturing a LTPS TFT OLED panel.  
         [0003]     2. Description of the Prior Art  
         [0004]     In general, low temperature poly crystalline silicon thin film transistor (LTPS TFT) array manufacturing needs about six to nine photo-masks to process a photolithograph etching process, which is more complex than five photo-masks required to manufacture the hydrogenated amorphous silicon thin film transistor (α-Si:H TFT). In addition, the active matrix organic light-emitting diode (AMOLED) needs seven to ten photo-masks, because of the need to manufacture an LTPS TFT array and a pixel define layer (PDL).  
         [0005]     Please refer to  FIG. 1 .  FIG. 1  is schematic diagram of a traditional OLED TFT structure. In the prior art, a glass substructure  102  is provided, with an insulator layer  104  and amorphous silicon film (not shown) deposited on the glass substructure  102 . The amorphous silicon film then re-crystallizes to polycrystalline silicon after an excimer laser annealing (ELA) process. Then, an active layer  106  pattern is etched on the polycrystalline silicon, and a gate insulator layer  108  is deposited on the active layer  106  and the insulator layer  104 .  
         [0006]     Moreover, a gate metal  110  is etched by a metal etching process, a second mask, and a second PEP. The gate metal  100  is a self-alignment mask and the boron ion doping process proceeds on the active layer  106 , forming a source  103  and a drain  105  on the corresponding sides of the gate metal  110 . In the prior art, a capacitance (Cst)  113  is formed on a poly silicon lower panel  107 , the gate insulator layer  108  and a metal upper panel  111  by the above-mentioned first PEP and the second PEP individually. Then, an inter-layer dielectric (ILD)  112  is deposited on the glass substructure  102  to cover the gate metal  110 , the metal upper panel  111 , and the gate insulator layer  108 . The particle ILD and the gate insulator layer  108  of the source  103  and the drain  105  are then removed by a third photo-mask and a third PEP to define a corresponding via hole  115 . Furthermore, a metal forming process is performed utilizing a fourth photo-mask, and the fourth mask etches a data line and a drain metal on the via hole  115  of metal layer  114  for electrically contacting the source  103  and the drain  105 . A flat passivation layer  116  is forming on the metal layer  114  and the ILD  112  using a fifth photo-mask and a fifth PEP, and the passivation layer  116  on the metal layer  114  which electrically contacts the drain  105  is removed. An ITO transparent electrode film (not shown) is formed on the passivation layer  116 , and a sixth photo-mask and a sixth PEP are used to define a suitable shape for the transparent electrode  118 . Then, a pixel define layer (PDL)  120  is doped and is etched by a seven photo-mask and a seven PEP. Finally, a LED (not shown) is formed on the transparent electrode  118  to complete the traditional OLED panel  100 .  
         [0007]     In the prior art, seven photo-masks are needed to complete the above-mentioned OLED. The process is complex and the use of too many masks increases the cost and increases the misalignment, thereby decreasing the yield. That is why decreasing the number of the photo-masks is an important issue in the monitor manufacturing industry.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention relates to a method of manufacturing an AMOLED to solve the above-mentioned problems.  
         [0009]     The present invention provides an embodiment relating to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a TFT on the substrate, forming an inter-layer insulator layer, forming a plurality of via holes, forming a metal layer which electrically contacts a source and a drain, and forming a transparent electrode, a pixel define layer and a LED.  
         [0010]     The present invention omits the passivation layer, dopes the transparent electrode on the metal layer and the ILD, and needs only six photo-masks. If the metal layer and the transparent electrode are made by the same PEP, the present invention only needs five photo-masks. Therefore, the present invention could decrease costs and simplify the manufacturing process.  
         [0011]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is schematic diagram of a traditional OLED TFT structure.  
         [0013]     FIGS.  2  to  6  are schematic diagrams of manufacturing an AMOLED according to the present invention.  
         [0014]      FIG. 7  is schematic diagram of forming the transparent electrode and metal layer using the same photo-mask according to the second embodiment. 
     
    
     DETAILED DESCRIPTION  
       [0015]     Please refer to FIGS.  2  to  6 . FIGS.  2  to  6  are schematic diagrams of manufacturing an AMOLED according to the present invention. Firstly,  FIG. 2  illustrates providing a glass substructure  202  as a lower base, forming a buffer insulator layer  204  and an amorphous silicon film (not shown) on the glass substructure  202 , shooting lasers and annealing, such that the amorphous silicon film (not shown) becomes a polycrystalline silicon film. A desired pattern is then etched on an active layer  206  utilizing a first photo-mask and a first PEP, wherein each pixel area forms a poly silicon lower panel  207  as a result of the first PEP.  
         [0016]     Please refer to  FIG. 3 , a gate insulator layer  208  deposited on the active layer  206  and the buffer insulator layer  204 . Then, a first metal film (not shown) is deposited on the gate insulator layer  208  using a second photo-mask and a second PEP forms patterns of a scan line (not shown), a gate metal  210 , and a metal upper panel  211 . A capacitance (Cst)  213  forms from the poly silicon lower panel  207 , the gate insulator layer  208  and the metal upper panel  211 . After that, the gate metal  210  is used as a self-alignment mask for performing a boron ion doping process, and the result forms a source  203  and drain  205  on the corresponding sides of the gate metal  210 . Moreover, a silica or sensitization material is smeared on the gate metal  210 , the metal upper panel  211 , and the gate insulator layer  208  through a spin on glass (SOG) process, which forms a flat inter-layer dielectric (ILD)  212 . Because of the SOG process, a drive array of the lower base has a better flat effect and the organic material ladder cover is better, too.  
         [0017]     Please refer to  FIG. 4 , which illustrates removing partial of the ILD  212  and the gate insulator layer  208  on the source  203  and drain  205  using a third photo-mask and a third PEP. Please refer  FIG. 5 , which illustrates performing a second metal film etching process using a fourth photo-mask and a fourth PEP to etch a data line and a metal layer  214  on a via hole  215  surface, where the data line and the metal layer  214  electrically contact the source  203  and the drain  205  individually. Then, ITO or IZO is formed as a transparent electrode layer (not shown) on the metal layer  214  and the ILD  212 , using a fifth photo-mask and a fifth PEP for defining a suitably shaped transparent electrode  218 .  
         [0018]     Please refer to  FIG. 6 , which illustrates spinning on glass (SOG) by silica smearing a pixel define layer (PDL)  220  on the metal layer  214 , the transparent electrode  218  and the ILD  212 , using a sixth photo-mask and a sixth PEP to form a suitably shaped pixel define layer  220 . Finally, an organic light emitting diode (OLED) is formed on the transparent electrode  218  to complete the OLED panel  600 . Of note, if the transparent electrode  218  cover of this embodiment is wider than the metal layer  214  which electrically contacts the drain  205 , the light of the OLED  222  emits up and down to be a bottom emission LED panel or a top and bottom emission OLED.  
         [0019]     Otherwise, please refer to  FIG. 7 .  FIG. 7  is a schematic diagram of forming the transparent electrode and metal layer using the same photo-mask according to the second embodiment. The difference between the second embodiment and the above-mentioned embodiment is the use of the same fourth photo-mask and fourth PEP after forming a metal layer  714  and a transparent electrode  718  to etch the data line and the same pattern of the metal layer  714  and the transparent electrode  718 . In addition, the metal layer  714  and the transparent electrode  718  electrically contact the source  203  and the drain  205 . Because of the transparent electrode  718  and the metal layer  714  having the same shape and the metal layer having a reflective effect, the metal layer  714  reflects the LED light to form a top emission LED panel. Finally, the pixel define layer and LED are formed in the same way as mentioned above. Thus, the second embodiment only needs five masks.  
         [0020]     Compared to the prior art, the present invention omits the passivation layer, dopes the transparent electrode on the metal layer and the ILD, and needs only six photo-masks. If the metal layer and the transparent electrode are made by the same PEP, the present invention only needs five photo-masks. Since the number of the photo-mask is less than the prior art, the present invention is able to decrease manufacturing costs and simplify the manufacturing process. In addition, the present invention can be applied in a low temperature polycrystalline silicon TFT (LTPS TFT) array LCD panel manufacturing process. This not only simplifies the photo-mask, but also forms the reflecting, penetrating or half-reflecting-half-penetrating LCD using different corresponding positions of the metal layer and the transparent electrode.  
         [0021]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 7