Patent Abstract:
A digital-to-analog converter is disclosed, which includes a decoder stage having a decoder output capable of receiving input data, a level shifter stage coupled to the decoder output capable of shifting the level of the decoder output, an output stage communicatively coupled to the level shifter stage capable of responding based upon an output value of the level shifter stage, and a current mirror communicatively coupled to the level shifter and capable to shift the level of the decoder output, and further includes an output stage having switches, which are selectively turned on by an output signal from the decoder stage thus outputting a reference voltage.

Full Description:
PRIORITY 
     Priority is claimed to the following U.S. provisional patent application: 
     Provisional U.S. Patent Application No. 60/280,677, entitled “Improved Switching Circuit for Column Display Driver,” filed on Mar. 30, 2001. 
     RELATED APPLICATIONS 
     The following identified U.S. patent applications are relied upon and are incorporated by reference in this application. 
     U.S. patent application Ser. No. 10/109,633, entitled “Slew Rate Enhancement and Method,” and filed on the same date herewith, which also claims priority to provisional U.S. Patent Application No. 60/280,677. 
     U.S. patent application Ser. No. 10/109,632, entitled “Improved Switching Circuit for Column Display Driver,” and filed on the same date herewith, which also claims priority to provisional U.S. Patent Application No. 60/280,677. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to transistor circuits and, more particularly, to digital-to-analog converters used for decoding and signal level shifting applications. 
     BACKGROUND 
     The liquid crystal display has become well known, driven in part by popular applications such as notebook computers, car navigational displays, and flat panel displays for personal computers. In each of these applications, a column driver circuit enables the operation of each liquid crystal display unit. Liquid crystal displays comprise a plurality of individual picture elements, called pixels, which are uniquely addressable in a row and column arrangement. The column driver circuitry provides the driving voltage to the columns of the liquid crystal display. 
     Column driver circuitry components act as intermediaries between the digital format of the electronics that process information and the analog format of the display that presents the results to the user. Accordingly, the column driver circuitry includes a digital-to-analog converter (“DAC”) that converts digital signals from the processing unit, bus, and memory into analog signals. However, DACs may be used in many applications other than in column driver circuitry. 
     One type of conventional DAC includes an inverter and a p-channel field effect transistor (“FET”) that is used as a feedback element for coupling a decoder circuit, which forms the input of the DAC, to an output stage such as, e.g., a multiplex switch, which forms the output of the DAC. One problem that occurs is that the FETs in a FET stack of the decoder circuit may have difficulty in driving the voltage level at the input of the inverter. As a result, the p-channel FET that forms the feedback element is formed with a large channel length, since the total resistance of the FETs in the FET stack has to be less than the resistance of the feedback FET. This large channel length requires substantial die space. 
     SUMMARY 
     In one embodiment of the invention, a digital to analog converter comprises a current source, a level shifter coupled to the current source, a stack of transistors coupled to the level shifter, wherein the stack of transistors is responsive to a reset signal, and an output stage coupled to the level shifter, wherein the output stage includes a transistor forming a path between a reference voltage level and an output voltage. 
     In another embodiment of the invention, a digital to analog converter comprises a decoder means, and an output means coupled to the decoder means. 
     In yet another embodiment of the invention, a digital to analog converter comprises a decoder stage, including a level shifter stage coupled to a decoder stage output, and a current source coupled to the level shifter, and an output stage coupled to the decoder stage. 
     In still another embodiment of the invention, a digital to analog converter comprises a decoder stage including a current source, a level shifter, and a stack of transistors, wherein the level shifter comprises an inverter with a feedback channel, and an output stage coupled to the decoder stage, the output stage including a transistor forming a path between a reference voltage level and an output voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate possible embodiments of the invention and together with the description, serve to explain the principles of the invention. In the drawings: 
     FIG. 1 is a schematic circuit diagram consistent with an embodiment of the present invention; and 
     FIG. 2 is a schematic circuit diagram consistent with another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring in detail now to the drawings, FIG. 1 shows a schematic block diagram of a digital-to-analog converter (“DAC”)  100  consistent with an embodiment of the invention. DAC  100  includes an output stage  105  for generating an analog output voltage V OUT , and one or more decoder stages  130 ( i ) (where, i=1, 2, . . . , n). As another example, in a typical 6-bit application, one implementation of DAC  100  would include sixty-four (64) decoder stages  130 ( i ) (where, i=1, 2, . . . , 64) for controlling output stage  105 . However, the number of decoder stages  130 ( i ) may also vary (e.g., i=1, 2, . . . , 32) in a 6-bit application. As described below, decoder stage  130 ( i ) further comprises a level shifter. 
     Output stage  105  includes an n-channel transistor  135 ( i ) (where, i=1, 2, . . . , n) that functions as a switch. Generally, transistor  135 ( i ) has a drain connected to a voltage source with a value of V ri (where, i=1, 2, . . . , n), a gate connected to the output of decoder stage  130 ( i ), and source connected to an output node  140 . That is, transistor  135 ( l ) has a drain connected to a voltage source with a value of V rl , a gate connected to the output of decoder stage  130 ( l ) and a source connected to output node  140 . Transistor  135 ( n-l ) has a drain connected to a voltage source with a value of V r(n-1) , a gate connected to the output of decoder stage  130 ( n-l ), and source connected to output node  140 . Transistor  135 ( n ) has a drain connected to a voltage source with a value of V rn , a gate connected to the output of decoder stage  130 ( n ), and a source connected to output node  140 . Voltages V r1 , V r2 , . . . V r(n-1) , and V rn  provide a series of reference voltage levels as an output. An output voltage (“V OUT ”) detected at node  140  is output from output stage  105 . The output voltage V OUT  can range from approximately zero (0) volt to approximately the positive voltage source value V DDA . As an example, V DDA  may have a value of about 12.0 volts. 
     Decoder stage  130 ( i ) includes a current source  120 , a feedback p-channel transistor  115 , an analog inverter  110 , a pre-charge p-channel transistor  125 , and a stacked n-channel transistor  160 ( j ) (where, j=0, 1, 2, . . . , m), which form a path  177  between a node  170  and V SS . Current source  120  may be a current mirror. Current source  120  may include a p-channel transistor  150  with a source connected to a voltage source V DDA  and a drain connected to V SS . Transistor  150  is diode-connected with its gate tied to its drain. Current source  120  also includes a p-channel transistor  155  with a source connected to the V DDA  voltage source, a gate connected to the gate of transistor  150  at node  156  and is biased by bias voltage V BIAS , and a drain connected to the source of transistor  115  at node  157 . 
     The drain of transistor  115  is coupled to the input of inverter  110 , the output of which is coupled to the gate of transistor  115 . Inverter  110  also may receive V DDA  as an input when transistor  125  is turned on. Inverter  110  is biased between a first voltage supply V DDA  and a second voltage supply V SS  where V SS  may be a negative, positive, or ground voltage and where V DDA  has a higher potential than V SS . The drain of transistor  115  is further coupled to the drain of transistor  125 , which has its source coupled to V DDA  and its gate configured to receive a reset signal (“RESET”). Thus, during a reset operation of decoder stage  130 ( i ), a negative RESET pulse will turn on transistor  125  to pull up node  170  to V DDA . The drain of transistor  125  is further coupled to the source of transistor  160 ( j ). Transistor  160 ( j ) has its drain coupled to V SS . The gate of transistor  160 ( j ) (where, j=0, 2, . . . , (m- 1 )) is coupled to a data input signal Dj (where, j=0, 2, . . . , (m- 1 )). The number of transistors  160 ( j ) (i.e., the value of m) in decoder stage  130 ( i ) maybe varied in order to configure decoder stage  130 ( i ) to receive various numbers of input signals. The gate of transistor  160 ( m ) is coupled to the output of an AND gate  165 , which has inputs of RESET and Dj (where, j=m). 
     Each decoder stage  130 ( i ) functions as a logic decoder with a level shifter. In the embodiment shown in FIG. 1, the output signal at node  170 , which is coupled to transistors  125  and  160 ( j ) of decoder stage  130 ( i ) (e.g., signal SELB) can be a low signal (pulled to ground) or can be a high impedance (Z) output. 
     Each of the input data received at terminals Dj (where, j=0, 1, 2, . . . , m) will have a logic high or logic low level. A logic high level signal will turn on an n-channel transistor in the transistor stack in decoder stage  130 ( i ), while a logic low level signal will turn off an n-channel transistor in the transistor stack. As an example, if DAC  100  is being used in a column driver application, the input data provided at terminals D 0  through D 5  are obtained from a data storage register (not shown). In a column driver application, the data stored in the data storage register at a given time would represent the intensity desired for one pixel in a given line. 
     In order to trip, or set, on decoder stage  130 ( i ), all of n-channel transistors  160 ( l ) through  160 ( m ) must turn on, and the SELB signal at node  170  will be pulled to ground. The values of the input data provided at terminals D 0  through Dm determine whether or not decoder stage  130 ( i ) will trip. When decoder stage  130 ( i ) trips, SELB will go low and will be inverted by inverter  110  to output a high SEL signal. The high SEL signal will input to output stage  105  and turn on corresponding transistor  135 ( i ) to set the V OUT  output voltage value to V ri . For a given input data that is received by one of decoder stage  130 ( i ), only one of transistors  135 ( i ) in the output stage  105  will turn on to determine the V OUT  output signal value. 
     The series layout of transistor  115  and transistor  155  will be smaller in size than if, instead, feedback transistor  115  were made weak. If transistor  115  is made weak, the width W will be very small and the length L will be long in the W/L ratio for MOSFETs. The long length L takes up a significant amount of die area, particularly if there are many decoder stages  130 ( i ) in particular implementations. In contrast, according to an embodiment of the invention, the W/L ratio is made small for feedback transistor  115  (i.e., minimum L and minimum W for transistor  115 ). However, this configuration would make transistor  115  too strong if L is not long enough, and a strong transistor  115  will not permit stacked transistors  160 ( j ) to pull down node  170  during a set operation. In an embodiment of the invention, L was minimized for transistor  155  and this minimization reduced the required die space for transistor  115 . To weaken the path at node  157 , current source  120  is coupled in series with feedback transistor  115 . The voltage V BIAS  at node  156  could be adjusted to set a current  158  value, which flows from current source  120 . 
     Reset Operation 
     A reset operation occurs when a low logic pulse in the RESET is received by transistor  125  and by AND gate  165 . The low logic RESET will turn on transistor  125  and will cause AND gate  165  to output a low logic signal to turn off transistor  160 ( m ), or in this case transistor  160 ( 5 ). As a result, path  177  becomes disconnected since transistor  160 ( m ) is turned off by the low logic signal from AND gate  165 . Node  170  is therefore pulled by transistor  125  to V DDA  since transistor  125  will turn on and path  177  is disconnected by transistor  160 ( m ). 
     Each of decoder stages  130 ( i ) (where, i=1, 2, . . . , n) receives the low logic RESET during a reset operation and functions as described above during the reset operation. 
     Since node  170  is pulled high during reset, the SELB signal is pulled high. Inverter  110  will invert the high SELB signal into a low SEL signal that turns off transistor  135 ( i ) in output stage  105 . Typically, the trip point voltage V TRIP  of inverter  110  (i.e., when inverter  110  output switches from one logic level to the opposite logic level) is when the input signal of inverter  110  reaches a value that is less than one-half (½) of the supply voltage V DDA  that powers inverter  110 . The low SEL signals from each of decoder stages  130 ( i ) (where, i=1, 2, . . . , n) will also turn off the corresponding output stage transistors  135 ( i ) (where, i=1, 2, . . . , n). 
     The low SEL signal will turn on transistor  115  and will cause transistor  115  to pull node  170  to V DDA . This action by transistor  115  thus reinforces the reset action by permitting current source  120  to hold node  170  to a high level and avoids the problems of the dynamic-type reset. 
     It is also noted that when SELB is high and thus SEL is low, transistor  115  is on. Since the drain of transistor  115  (connected to node  170 ) and the source of transistor  115  (connected to node  157 ) are at the same voltage level of VDDA, current source  120  shuts off and will not supply current. 
     Select Operation 
     Prior to the select operation, the SELB signal may be pre-charged high such that the SEL signal is at a low level. The low level SEL maintains transistor  115  in an on state. Thus, nodes  157  and  170  are both at the V DDA  voltage level, and this condition keeps current source  120  in an off state. When the input signals at the gates of transistors  160 ( j ) are high, each of transistors  160 ( j ) will turn on. As a result, stacked transistors  160 ( 0 ) through  160 ( m ) will pull node  170  to a low level of V SS , resulting in the SELB signal to change from a high level to a low level. When the SELB signal decreases from the V DDA  level to the V TRIP  trip point voltage of inverter  110 , the voltage at node  157  will also decrease from V DDA  to the V TRIP  trip point voltage. When the SELB signal decreases to the V TRIP  trip point voltage, inverter  110  will switch the SEL output signal from a low level to a high level. The high level SEL signal will turn off transistor  115 . Since transistor  115  is turned off, stacked transistors  160 ( 0 ) through  160 ( m ) can easily continue to pull down the SELB signal to the ground level. The low SELB signal is inverted into a high SEL signal that turns on the output stage transistor  135 ( i ). Since transistor  135 ( i ) is on, the output voltage V OUT  will be approximately equal to V ri . Since transistor  115  is off, the current  158  from current source  120  will pull node  157  to the V DDA  level. After node  157  is pulled to the V DDA  level, current source  120  will shut off. 
     Decoder stage  130 ( i ) can have other configurations. For example, FIG. 2 is a schematic circuit diagram of another embodiment of the decoder that can be implemented with the invention. Decoder stage  230 ( i ) (where, i=1, 2, . . . , n) includes a reset n-channel transistor  205  with a gate for receiving the RESET signal and a drain coupled to node  170 . Decoder stage  230 ( i ) also includes an n-channel transistor  210  with a gate for receiving data, a drain connected to the source of transistor  205 , and a source connected to ground, or V SS . In a reset operation, transistor  205  receives the low pulse from the RESET signal to turn off transistor  205  and disconnect a path  277 , which comprises transistors  205  and  210 , from node  170  to ground. The low RESET pulse will also turn on transistor  125  so that node  170  is pulled to V DDA . During a select operation, the input data will turn on transistor  210  and node  170  will be pulled to ground. The SELB signal will go low and the SEL signal will go high to turn on output stage transistor  135 ( i ). As similarly with reference to FIG. 1 described above, the high SEL signal will turn off feedback transistor  115  and node  157  will be pulled to the V DDA  level. 
     Other variations and modifications of the above-described embodiments and methods are possible in light of the foregoing teaching. For example, components of this invention may be implemented using field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), discrete elements, or a network of interconnected components and circuits. Connections may be wired, wireless, modem, and the like. 
     Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Technology Classification (CPC): 6