Patent Abstract:
A semiconductor device comprises a semiconductor chip in which a circuit part provided in a center of the semiconductor chip is connected with power-supply lines and power-supply electrodes to supply power from an external power source to the circuit part. A substrate is provided for carrying the semiconductor chip thereon and provided so that first terminals in a region encircling the semiconductor chip are electrically connected to the power-supply electrodes. A first opening is formed on the power-supply line in a center of the circuit part. A second opening is formed on the power-supply line at a peripheral part of the circuit part. A conductor layer is electrically connected to second terminals in the region encircling the semiconductor chip on the substrate, and provided so that the power-supply line in the first opening and the power-supply line in the second opening are connected together.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2004-164857, filed on Jun. 2, 2004, the entire contents of which are herein incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention generally relates to a semiconductor device, and more particularly relates to a semiconductor device which has the power supply wiring to supply power to a circuit part of a semiconductor chip via a power-supply line of the semiconductor chip.  
         [0004]     2. Description of the Related Art  
         [0005]     Conventionally, in the semiconductor device in which the semiconductor chip is mounted using the wire bonding method, the electrode at the peripheral part of the semiconductor chip carried on the substrate and the bonding lead on the substrate are electrically connected together by a wire etc.  
         [0006]     At the time of operation, the power supply current is supplied from the electrode of the peripheral part of the semiconductor chip to the circuit part in the center of the semiconductor chip through the power-supply line.  
         [0007]      FIG. 1  shows the composition of the conventional semiconductor device  10 . The semiconductor chip  1 , such as LSI, is carried on the interposer used as the substrate indicated by the dotted line in  FIG. 1 . The semiconductor chip  1  comprises the core part  5  which forms the circuit part, the plurality of electrode pads  2  disposed at the peripheral part of the core part  5 , and the power-supply line  4 .  
         [0008]     The electrode pad  2  disposed for the power supply, among the plurality of electrode pads  2 , is connected by the circuit part and the power-supply line  4  of the semiconductor chip  1 . The electrode pad  2  disposed for the grounding, among the plurality of electrode pads  2 , is connected by the circuit part and the power-supply line  4  of the semiconductor chip  1 .  
         [0009]     The power supply current from the power supply (not illustrated) is supplied at the time of operation to the circuit of the core part  5  in the center of the semiconductor chip  1  through the power-supply line  4  from the periphery of the semiconductor chip  1 .  
         [0010]     On the substrate of the semiconductor device  1 , the plurality of bonding leads  7  are disposed in the region encircling the semiconductor chip  1 . Among the plurality of bonding leads  7 , the bonding lead  7  for the power supply is connected to the power supply (not illustrated), and the bonding lead  7  for the grounding among the plurality of bonding leads  7  is grounded. All the bonding leads  7  provided on the substrate are electrically bonded to the electrode pads  2  at the periphery of the semiconductor chip  1  by the wires  8 .  
         [0011]     As the known method concerning the power supply wiring of the semiconductor device, Japanese Laid-Open Patent Application No. 03-008360 discloses the power supply wiring provided in the semiconductor device having the plurality of wiring layers. This semiconductor device has the wiring structure in which the plurality of semiconductor chips and the power supply wiring are connected via the through holes.  
         [0012]     Moreover, Japanese Laid-Open Patent Application No. 64-089447 discloses the semiconductor integrated circuit device having the multilayer interconnection structure. In order to avoid the influence from the electric field and the magnetic field on the exterior of the integrated circuit, the semiconductor circuit device is configured to have the wiring structure in which at least one conductor layer among the plurality of conductor layers is connected to the power supply or the ground so as to cover entirely the periphery of the element (transistor) on the substrate.  
         [0013]     In the conventional semiconductor device  10  of  FIG. 1 , the power supply current is supplied to the core part  5  of the semiconductor chip  1  via the power-supply line  4  at the time of operation. However, there is a tendency that the supply voltage in the center of the core part  5  falls to be lower than the supply voltage at the peripheral part of the core part  5 .  
         [0014]     Especially, at the time of high-speed operation, the power supply current is consumed with the passive component parts, such as resistors and inductors, and the supply voltage in the center of the core part  5  will be lower than the supply voltage in the peripheral part of the core part  5 . There may arise the problem in which the predetermined operation cannot be performed by the circuit part of the semiconductor chip  1  due to the supply voltage drop. Therefore, in the case of the conventional semiconductor device  10 , the supply voltage drop becomes the cause of the operational fault of the semiconductor chip  1 .  
       SUMMARY OF THE INVENTION  
       [0015]     An object of the present invention is to provide an improved semiconductor device in which the above-mentioned problems are eliminated.  
         [0016]     Another object of the present invention is to provide a simple and low-cost semiconductor device in which the structure of the power-supply line is improved and the operation of the semiconductor chip can be stabilized effectively.  
         [0017]     In order to achieve the above-mentioned objects, the present invention provides a semiconductor device in which the openings are respectively formed on the power-supply line in the center of the circuit part of the semiconductor chip and the power-supply line at the peripheral part of the circuit part of the semiconductor chip. And the power-supply line on the opening of the center of the circuit part and the power-supply line on the opening of the peripheral part of the circuit part are mutually connected by the conductor layer formed from the silver paste etc. It is possible to make the power supply current supplied in the center of the circuit part during the operation increase. Therefore, it is possible for the present invention to prevent that the supply voltage in the center of the circuit part falls during the operation, and the operation of the semiconductor chip can be stabilized effectively. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     Other objects, features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.  
         [0019]      FIG. 1  is a diagram showing the composition of the conventional semiconductor device.  
         [0020]      FIG. 2A  is a diagram for explaining the conductor layer formed on the power-supply line of the circuit part of the semiconductor chip in the preferred embodiment of the present invention.  
         [0021]      FIG. 2B  is a diagram for explaining the conductor layer formed on the power-supply line of the circuit part of the semiconductor chip in the preferred embodiment of the present invention.  
         [0022]      FIG. 3  is a cross-sectional view showing the connection between the power-supply line and the conductor layer in the semiconductor chip of  FIG. 2B .  
         [0023]      FIG. 4  is a diagram showing the composition of the semiconductor device in one embodiment of the present invention.  
         [0024]      FIG. 5  is a diagram showing the composition of the semiconductor device in another embodiment of the present invention.  
         [0025]      FIG. 6  is a cross-sectional view showing the connection between the substrate, the semiconductor chip and the conductor layer in the semiconductor device of  FIG. 5 .  
         [0026]      FIG. 7  is a diagram showing the composition of the semiconductor device in another embodiment of the present invention.  
         [0027]      FIG. 8  is a cross-sectional view showing the connection between the TAB tape, the semiconductor chip and the conductor layer in the semiconductor device of  FIG. 7 .  
         [0028]      FIG. 9  is a cross-sectional view showing the cross-sectional structure of the semiconductor chip of  FIG. 2B .  
         [0029]      FIG. 10  is a side view showing the connection between the wiring board, the semiconductor chip and the conductor layer in the semiconductor device of  FIG. 4 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0030]     A description will now be given of the preferred embodiments of the present invention with reference to the accompanying drawings.  
         [0031]      FIG. 4  shows the composition of the semiconductor device in one preferred embodiment of the present invention.  FIG. 10  shows the connection between the wiring board, the semiconductor chip and the conductor layer in the semiconductor device of  FIG. 4 .  
         [0032]     The semiconductor device  20  of  FIG. 4  comprises the semiconductor chip  11  carried on the wiring board  21 , such as LSI. The wiring board  21  is used as the interposer, for example. The semiconductor chip  11  contains the circuit part (core part) formed in the center, the plurality of electrode pads  12  disposed at the peripheral part of the circuit part, and the power-supply line  14 .  
         [0033]     As shown in  FIG. 10 , the semiconductor chip  11  is mounted on the wiring board  21  via the die material  21   a  with its circuit part formed on the front surface being placed up side and its back surface being placed down side. The electrode pad  12  disposed for the power supply among the plurality of electrode pads  12  is connected with the circuit part and the power-supply line  14  of the semiconductor chip  11 .  
         [0034]     The electrode pad  12  disposed for the grounding among the plurality of electrode pads  12  is connected with the circuit part and the power-supply line  14  of the semiconductor chip  11 . The power supply current from the power supply (not illustrated) is supplied at the time of operation from the peripheral part of the semiconductor chip  11  to the circuit part in the center of the semiconductor chip through the power-supply line  14 .  
         [0035]     On the wiring board  21  of the semiconductor device  20 , the plurality of bonding leads  17  are disposed in the region encircling the semiconductor chip  11 . Among the plurality of bonding leads  17 , the bonding lead  17  for the power supply is connected with the power supply (not illustrated), and the bonding lead  17  for the grounding among the plurality of bonding leads  17  is grounded.  
         [0036]     Each electrode pad  12  at the periphery of the semiconductor chip  11  is electrically connected to one of the plurality of bonding leads  17  by a wire  18 , respectively.  
         [0037]     In order to solve the problem in which the supply voltage supplied in the center of the circuit part of the semiconductor chip falls at the time of operation of the conventional semiconductor device mentioned above, the semiconductor device  20  of  FIG. 4  is configured as in the following. The opening  13  is formed on each of the power-supply lines  14  in the center and at the peripheral part of the circuit part of the semiconductor chip  11 , respectively. The conductor layer  16  is formed on these openings  13  to cover the whole surface of the circuit part of the semiconductor chip  11 , and the power-supply line  14  on the opening  13  of the center of the circuit part and the power-supply line  14  on the opening  13  of the peripheral part of the circuit part are mutually connected by the conductor layer  16 .  
         [0038]     This conductor layer  16  can be formed by applying the conductive material, such as a silver paste, to the semiconductor chip  11 . The bonding leads  17  for the conductor layer, among the plurality of bonding leads  17  on the wiring board  21  of the semiconductor device  20 , are electrically connected to the conductor layer  16  by the wires  18 . These bonding leads  17  for the conductor layer (in the example of  FIG. 4 , eight pieces) include the bonding lead connected to the power supply (not illustrated), and the bonding lead connected to the ground.  
         [0039]     Therefore, at the time of operation, the power supply current from the power supply (not illustrated) is directly supplied to the conductor layer  16  through the bonding leads  17  for the conductor layer and the wires  18 . By forming this conductor layer  16  in the semiconductor device of the present invention, it is possible to increase the amount of the power supply current supplied to the circuit part in the center of the semiconductor chip  11  at the time of operation.  
         [0040]     Therefore, in the time of operation, it is possible to prevent the falling of the supply voltage in the center of the circuit part of the semiconductor chip  11 , and the operation of the semiconductor ship  11  can be stabilized effectively.  
         [0041]      FIG. 2A  and  FIG. 2B  are diagrams for explaining the conductor layer  16  formed on the power-supply line  14  of the circuit part of the semiconductor chip  11  of  FIG. 4 .  
         [0042]     Before forming the conductor layer  16 , the plurality of openings  13  are formed on the power-supply line  14  of the semiconductor chip  11  as shown in  FIG. 2A . The positions where the plurality of openings  13  are formed are distributed equally for the positions on the power-supply line  14  near the peripheral part of the circuit part of the semiconductor chip  11 , and the positions on the power-supply line  14  near the center of the circuit part of the semiconductor chip  11  in which the voltage drop tends to arise.  
         [0043]     In each of the plurality of openings  13 , the opening is formed such that other wiring layers, insulating layers, etc. may not close a part of the power-supply line  14  of the semiconductor chip  11 . These openings  13  can be formed additionally within the manufacturing processes of the semiconductor chip  11 . Alternatively, these openings  13  may be formed after the manufacture of the semiconductor chip  11 .  
         [0044]     As shown in  FIG. 2B , after the plurality of openings  13  are formed, the conductor layer  16  is formed thereon. By applying or printing the conductive substance, such as a silver paste, the conductor layer  16  is formed to cover all the plurality of openings  13  on the semiconductor chip  11 , and the conductor layer  16  and the power-supply line  14  are connected together at each opening  13 .  
         [0045]      FIG. 9  shows the cross-sectional structure of the semiconductor chip  11  of  FIG. 2B .  
         [0046]     As shown in  FIG. 9 , the semiconductor chip  11  comprises the substrate  19 , such as silicon, the wiring layer  15  formed on the substrate  19 , the conductor layer  16  formed on the wiring layer  15 , and the electrode pads  12 . The wiring layer  15  includes the insulating layer  15   a , the power-supply line  14 , and other wiring layers.  
         [0047]     The opening  13  is formed by removing the insulating layer  15   a  of the wiring layer  15 , so that the power-supply line  14  is exposed. The conductor layer  16  is formed by applying or printing the silver paste or the like, so that all the openings  13  on the semiconductor chip  11  are covered by the conductor layer  16 .  
         [0048]     In this embodiment, the silver (Ag) content of the silver paste used is 60% or more, the silver paste is heated and hardened, and the silver content of the hardened material is 99% or more. It is a matter of course that the metal, such as gold (Au) or copper (Cu), and other conductive substances, other than silver (Ag), may be used as the material for forming the conductor layer  16 .  
         [0049]      FIG. 3  shows the connection between the power-supply line  14  and the conductor layer  16  in the opening  13  of the semiconductor chip  11  of  FIG. 2B .  
         [0050]     The wiring of the semiconductor chip  11  of  FIG. 2B  is formed with aluminum (Al) or copper (Cu) and the wiring width of the power-supply line  14  is comparatively small (about ten micrometers). For this reason, before the silver paste is applied, the non-electrolytic plating is performed so that the plating of nickel (Ni) and gold (Au) is formed on the power-supply line  14  at the position of the opening  13 , in order to avoid the disconnection of the wiring by the thermal stress at the time of hardening of the silver paste.  
         [0051]     As shown in  FIG. 3 , in the opening  13  disposed in the circuit part of the semiconductor chip  11 , the nickel plating layer  17   a  and the Au plating layer  17   b  are formed on the power-supply line  14 , and the conductor layer  16  is further formed on the plating layers  17   a  and  17   b  by applying and hardening of the silver paste, so that the conductive layer  16  covers almost the whole surface of the circuit part of the semiconductor chip  11  including the center and the peripheral part thereof.  
         [0052]     In the semiconductor device  20  having the above-described structure, the opening  13  disposed in the center of the circuit part of the semiconductor chip  11  and the openings  13  disposed at the peripheral part of the circuit part of the semiconductor chip  11  are connected with each other by the conductor layer  16 , and the conductor layer  16  is electrically connected with the power-supply line  14  at each of these openings  13 .  
         [0053]     As explained above, in the semiconductor device  20  of  FIG. 4 , by forming the openings  13  and the conductor layer  16  in the circuit part of the semiconductor chip  11 , it is possible to increase the power supply current supplied to the circuit part in the center of the semiconductor chip  11  at the time of operation. Therefore, it is possible to prevent the falling of the supply voltage in the center of the circuit part of the semiconductor chip  11  at the time of operation, and the operation of the semiconductor chip  11  can be stabilized effectively.  
         [0054]     In addition, the openings  13  and the conductor layer  16  in this embodiment can be easily formed on the semiconductor chip  11  by using the known wiring method, and it is possible for the present invention to provide a simple and low-cost semiconductor device.  
         [0055]     Next, the semiconductor device in another embodiment of the present invention will be explained using  FIG. 5  and  FIG. 6 .  
         [0056]     As for the chip mounting technology which mounts the IC or LSI chip, the wire bonding method, the flip-chip bonding method, the TAB (Tape Automated Bonding) method, etc. are known. And these methods are properly used depending on the device or product field concerned.  
         [0057]     The above-described semiconductor device  20  of  FIG. 4  is one embodiment of the invention in which the mounting of the semiconductor chip is performed by using the wire bonding method.  
         [0058]     In contrast, the semiconductor device  30  shown in  FIG. 5  and  FIG. 6  is one embodiment of the invention in which the mounting of the semiconductor chip is performed by using the flip-chip bonding method.  
         [0059]      FIG. 5  shows the composition of the circuit formation surface (back surface) of the semiconductor chip  11   a  in this embodiment.  FIG. 6  shows the connection between the substrate  22 , the semiconductor chip  11   a , and the conductor layer  16  in the semiconductor device  30  of this embodiment.  
         [0060]     The semiconductor device  30  of this embodiment comprises the semiconductor chip  11   a  carried on the substrate  22 , such as LSI. Unlike the semiconductor chip  11  of  FIG. 2B  in which the plurality of electrode pads  12  are disposed, the plurality of bumps  12   a  are disposed at the peripheral part of the semiconductor chip  11   a  in this embodiment, instead of the plurality of electrode pads  12 , as shown in  FIG. 5 .  
         [0061]     As shown in  FIG. 5 , the semiconductor chip  11   a  comprises the circuit part (core part) formed in the center, the plurality of bumps  12   a  disposed at the peripheral part of the circuit part, the power-supply line  14 , the plurality of openings  13 , and the conductor layer  16 . The bump  12   a  disposed for the power supply, among the plurality of bumps  12   a , is connected with the circuit part and the power-supply line  14  of the semiconductor chip  11   a . The bump  12   a  disposed for the grounding, among the plurality of bumps  12   a , is connected with the circuit part and the power-supply line  14  of the semiconductor chip  11   a.    
         [0062]     The power supply current from the power supply (not illustrated) is supplied at the time of operation from the peripheral part of the semiconductor chip  11   a  to the circuit part in the center of the semiconductor chip  11   a  through the power-supply line  14 .  
         [0063]     The openings  13  are formed respectively on the power-supply line  14  disposed in the center of the circuit part of the semiconductor chip  11   a  and on the power-supply line  14  at the peripheral part of the circuit part of the semiconductor chip  11   a . The conductor layer  16  is formed on these openings  13  to cover the whole surface of the circuit part of the semiconductor chip  11   a , and the power-supply line  14  on the opening  13  of the center of the circuit part and the power-supply line  14  on the opening  13  of the peripheral part of the circuit part are connected with each other by the conductor layer  16 .  
         [0064]     Similar to the formation method mentioned above using  FIG. 2B , the conductor layer  16  can be formed by applying and hardening the conductive material, such as a silver paste, to the semiconductor chip  11   a . In the following, the overlapping explanation will be omitted.  
         [0065]     As shown in  FIG. 6 , the terminal  24  is disposed on the substrate  22  of the semiconductor device  30  in the region confronting the circuit part of the semiconductor chip  11   a , and the plurality of terminals  23  are disposed on the substrate  22  in the region confronting the plurality of bumps  12   a  of the semiconductor chip  11   a.    
         [0066]     Among the plurality of terminals  23 , the terminal  23  for the power supply is connected with the power supply (not illustrated), and the terminal  23  for the grounding among the plurality of terminals  23  is grounded.  
         [0067]     In the semiconductor device  30  of  FIG. 6 , each of the plurality of bumps  12   a  at the periphery of the semiconductor chip  11   a  is electrically connected to one of the plurality of terminals  23  disposed on the substrate  22 , respectively. The conductor layer  16  in the center of the semiconductor chip  11   a  is also electrically connected to the terminal  24  disposed on the substrate  22 .  
         [0068]     Similar to the previous embodiment of  FIG. 4 , in the semiconductor device  30  of this embodiment, by forming the openings  13  and the conductor layer  16  in the circuit part of the semiconductor chip  11   a , it is possible to increase the power supply current supplied to the circuit part in the center of the semiconductor chip  11   a  at the time of operation. Therefore, it is possible to prevent the falling of the supply voltage in the center of the circuit part of the semiconductor chip  11   a  at the time of operation, and the operation of the semiconductor chip  11   a  can be stabilized effectively.  
         [0069]     Since the openings  13  and the conductor layer  16  in this embodiment can also be easily formed on the semiconductor chip  11   a  by using the known wiring method, it is possible for the present invention to provide a simple and low-cost semiconductor device.  
         [0070]     Next, the semiconductor device in another embodiment of the present invention will be explained using  FIG. 7  and  FIG. 8 .  
         [0071]     As mentioned above, the semiconductor device  20  of  FIG. 4  is one embodiment of the invention in which the mounting of the semiconductor chip is performed by using the wire bonding method. In contrast, the semiconductor device  40  shown in  FIG. 7  and  FIG. 8  is one embodiment of the invention in which the mounting of the semiconductor chip is performed by using the TAB method.  
         [0072]      FIG. 7  shows the composition of the circuit formation surface (front surface) of the semiconductor chip  11   b  of this embodiment and the TAB tape  28 .  FIG. 8  shows the connection between the TAB tape  28 , the semiconductor chip  11   b  and the conductor layer  16  in the semiconductor device  40  of this embodiment.  
         [0073]     The semiconductor device  40  of this embodiment comprises the semiconductor chip  11   b  carried on the TAB tape  28 . Unlike the example of  FIG. 2B , the plurality of bumps  12   b  are disposed at the peripheral part of the semiconductor chip  11   b  as shown in  FIG. 7 , instead of the plurality of electrode pads  12 .  
         [0074]     As shown in  FIG. 7 , the semiconductor chip  11   b  comprises the circuit part (core part) formed in the center, the plurality of bumps  12   b  disposed at the peripheral part of the circuit part, the power-supply line  14 , the plurality of openings  13 , and the conductor layer  16 .  
         [0075]     The bump  12   b  disposed for the power supply, among the plurality of bumps  12   b , is connected with the circuit part and the power-supply line  14  of the semiconductor chip  11   b . The bump  12   b  disposed for the grounding, among the plurality of bumps  12   b , is connected with the circuit part and the power-supply line  14  of the semiconductor chip  11   b.    
         [0076]     The power supply current from the power supply (not illustrated) is supplied, at the time of operation, from the peripheral part of the semiconductor chip  11   b  to the central circuit part through the power-supply line  14 .  
         [0077]     The openings  13  are formed respectively on the power-supply line  14  disposed in the center of the circuit part of the semiconductor chip  11   a  and on the power-supply line disposed at the peripheral part of the circuit part of the semiconductor chip  11   b . The conductor layer  16  is formed on these openings  13  to cover the whole surface of the circuit part of the semiconductor chip  11   b , and the power-supply line  14  on the opening  13  of the center of the circuit part and the power-supply line  14  on the opening  13  of the peripheral part of the circuit part are connected with each other by the conductor layer  16 .  
         [0078]     Similar to the formation method mentioned above using  FIG. 2B , the conductor layer  16  can be formed by applying and hardening the conductive material, such as a silver paste, to the semiconductor chip  11   b . In the following, the overlapping explanation will be omitted.  
         [0079]     In the TAB tape  28 , the plurality of leads  27  are disposed at the positions confronting the plurality of bumps  12   b  of the semiconductor chip  11   b  respectively. The lead  27  for the power supply, among the plurality of leads  27 , is connected with the power supply (not illustrated), and the lead  27  for the grounding among the plurality of leads  27  is grounded. Furthermore, a pair of leads  29  for the power supply which are arranged in the X-shaped formation are disposed in the opening of the TAB tape  28  at the position confronting the circuit part of the semiconductor chip  11   b.    
         [0080]     As shown in  FIG. 8 , in semiconductor device  40  of this embodiment, each of the plurality of bumps  12   b  at the periphery of the semiconductor chip  11   b  is electrically connected to one of the plurality of leads  27  disposed on the TAB tape  28 , respectively. And the conductor layer  16  in the center of the semiconductor chip  11   b  is also electrically connected to the lead  29  for the power supply formed on the TAB tape  28 .  
         [0081]     Similar to the previous embodiment of  FIG. 4 , in the semiconductor device  40  of this embodiment, by forming the openings  13  and the conductor layer  16  in the circuit part of the semiconductor chip  11   b , it is possible to increase the power supply current supplied to the center of the circuit part of the semiconductor chip  11   b  at the time of operation. Therefore, it is possible to prevent the falling of the supply voltage in the center of the circuit part of the semiconductor chip  11   b  during the operation, and the operation of the semiconductor chip  11   b  can be stabilized effectively. Since the openings  13  and the conductor layer  16  in this embodiment can also be easily formed on the semiconductor chip  11   b  by using the known wiring method, it is possible for the present invention to provide a simple and low-cost semiconductor device.  
         [0082]     The present invention is not limited to the above-described embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Technology Classification (CPC): 7