Patent Abstract:
A processor includes a cache hierarchy including a level-1 cache and a higher-level cache. The processor maps a portion of physical memory space to a portion of the higher-level cache, executes instructions, at least some of which comprise microcode, allows microcode to access the portion of the higher-level cache, and prevents instructions that do not comprise microcode from accessing the portion of the higher-level cache. The first portion of the physical memory space can be permanently allocated for use by microcode. The processor can move one or more cache lines of the first portion of the higher-level cache from the higher-level cache to a first portion of the level-1 cache, allow microcode to access the first portion of the first level-1 cache, and prevent instructions that do not comprise microcode from accessing the first portion of the first level-1 cache.

Full Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates to microprocessors and, more particularly, to emulation of complex instructions by microcode, and still more particularly, to caching of memory used during such emulation. 
         [0003]    2. Description of the Related Art 
         [0004]    While it is desirable for microprocessors to maintain compatibility with a complex instruction set computer (CISC) architecture, other architectures offer improved execution speed and performance. Microprocessor designers have attempted to achieve both CISC compatibility and high performance by emulating CISC instructions. For example, superscalar, reduced instruction set computer (RISC) architectures may include microcode that performs CISC instruction emulation. During the emulation process, microcode makes use of a scratchpad memory for saving intermediate values. To maintain high performance, it is desirable for a microprocessor&#39;s microcode to be able to access the emulation memory as quickly as possible. 
         [0005]    In addition, microprocessors commonly include multiple memory caches, arranged hierarchically and shared by multiple cores or execution units. A variety of caching architectures are used and include various combinations of on-chip cache and off-chip cache. Memory operations that read data from cache or memory may be referred to more succinctly herein as “loads”. Memory operations that write data to cache or memory may be referred to more succinctly herein as “stores”. A load or a store may target a particular cache line (or portion of a cache line) and include an address identifying the targeted line as well as including data to be loaded from or stored within the cache line. Since cache accesses are faster than memory accesses, various caching techniques are used to increase the likelihood that data is located in a cache when a core or execution unit needs to access it, thereby improving execution speed. Consequently caching the microcode emulation memory offers the performance advantage of the relatively faster access time of cache memory compared to system memory. The shortest access times are generally those associated with the lowest level of the cache hierarchy, commonly referred to as L1-cache, or simply L1. Therefore, it is desirable to cache the microcode emulation memory in L1. Such performance advantages have often been reinforced by the permanent allocation of a portion of L1 for microcode emulation memory. 
         [0006]    Of course, the performance advantages of using the L1-cache would benefit other processes as well. Consequently, it is desirable to make the L1-cache as large as possible to increase the availability of L1-cache space for any process. However, increasing the size of L1 increases the cost and complexity of the microprocessor. Also, if the microcode emulation memory is permanently allocated in L1, this portion of L1 is not available to other processes. In order to address the above concerns, what is needed is a way to improve availability of space in a given size L1-cache to all processes while maintaining the advantages of caching the microcode emulation memory. 
       SUMMARY OF THE INVENTION 
       [0007]    Various embodiments of a processor, a computer system, and methods are disclosed. The processor includes a cache hierarchy including at least a first level-1 cache and a higher-level cache. The processor is configured to map a first portion of a physical memory space to a first portion of the higher-level cache, execute instructions, at least some of which comprise microcode, allow microcode to access the first portion of the higher-level cache, and prevent instructions that do not comprise microcode from accessing the first portion of the higher-level cache. In one embodiment, the higher-level cache is a level-2 cache. In another embodiment, the first portion of the physical memory space is permanently allocated for use by microcode. 
         [0008]    In a further embodiment, the processor is configured to move one or more cache lines of the first portion of the higher-level cache from the higher-level cache to a first portion of the first level-1 cache. The processor is further configured to allow microcode to access the first portion of the first level-1 cache and prevent instructions that do not comprise microcode from accessing the first portion of the first level-1 cache. 
         [0009]    In a still further embodiment, the processor is configured to detect a microcode access signal. The processor is further configured to prevent instructions from accessing the first portion of the physical memory space if the microcode access signal is not asserted and allow instructions to access the first portion of the physical memory space if the microcode access signal is asserted. 
         [0010]    In a still further embodiment, the processor includes a translation lookaside buffer (TLB), wherein to prevent instructions that do not comprise microcode from accessing the first portion of the physical memory space the processor is further configured to disallow TLB refills to the first portion of the physical memory space. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a generalized block diagram of one embodiment of a computer system. 
           [0012]      FIG. 2  illustrates one embodiment of a virtual memory and cache architecture. 
           [0013]      FIG. 3  illustrates one embodiment of a process for accessing a memory hierarchy including microcode emulation memory. 
           [0014]      FIG. 4  illustrates one embodiment of a process for accessing microcode emulation memory in a level-1 cache. 
           [0015]      FIG. 5  is a block diagram of one embodiment of a computer system including a L2 data cache and microcode emulation memory coupled to a variety of system components. 
       
    
    
       [0016]    While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed descriptions thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0017]      FIG. 1  is a generalized block diagram of one embodiment of a computer system  100 . In the illustrated embodiment, processor  110  is shown coupled to a memory  150 . Memory  150  may include SDRAM, SRAM, ROM, DRAM and/or other conventional memory devices. Processor  110  includes a core  120 , an L2 data cache  130 , and an L2 translation lookaside buffer (TLB)  140 . Core  120  includes an execution unit  122 , a load/store unit  124 , an L1 data cache  126 , and an L1 TLB  128 . L2 data cache  130  includes a microcode emulation memory  135 . In alternative embodiments, processor  110  may include more than one core, each core including a level-1 data cache and each core sharing a single level-2 data cache. In one alternative embodiment, L1 data cache  126  may be separate from core  120 . In other alternative embodiments, additional cache levels may be included in computer system  100 , such as a level-3 cache, either included in processor  110  or separate from processor  110 . In these and other alternative embodiments, microcode emulation memory  135  may be included in any cache level above level-1. A variety of other embodiments are also contemplated. However, for ease of understanding, the examples that follow will assume that space is permanently allocated in a level-2 data cache for microcode emulation memory  135 . 
         [0018]    During operation, execution unit  122  may receive the data portion of loads to be executed from load/store unit  124  via link  161  and convey the data portion of stores to load/store unit  124  via link  162 . Load/store unit  124  may receive the data portion of loads to be executed from L1 data cache  126  via link  163  and convey the data portion of stores to L1 data cache  126  via link  164 . L1 data cache  126  may receive the data portion of loads from L2 data cache  130  via link  165  and convey the data portion of stores to L2 data cache  130  via link  166 . L2 data cache  130  may receive the data portion of loads from and convey the data portion of stores to memory  150  via link  167 . L1 TLB  128  is shown coupled to L1 data cache  126  via link  171 , to L2 data cache  130  via link  172 , and to L2 TLB  140  via link  173 . L2 TLB  140  is also shown coupled to L2 data cache  130  via link  174 . 
         [0019]    L1 data cache  126 , L1 TLB  128 , L2 data cache  130 , and L2 TLB  140  may perform conventional address translation and caching functions. For example, L1 TLB  128  may cache mappings of virtual addresses to physical addresses. When a memory access request occurs, L1 TLB  128  may be checked to see if a mapping of the desired virtual address to a physical address is cached. Mappings cached in L1 TLB  128  may be used to determine if a desired cache line is present in L1 data cache  126 . If a desired cache line is not present in L1 data cache  126 , i.e., there is an L1 cache miss, L2 TLB  140  may be checked to see if a mapping of the desired virtual address to a physical address is cached. Mappings cached in L2 TLB  140  may be used to determine if a desired cache line is present in L2 data cache  130 . When a cache miss occurs in L1 data cache  126 , in order to make room for a new entry, a cache line may be evicted from L1 data cache  126  to L2 data cache  130 . A corresponding entry in L1 TLB  128  may be moved to L2 TLB  140 . In order to make room for a new entry in L2 data cache  130 , it may be necessary to evict a cache line from L2 data cache  130  to memory  150 . A new address translation may be performed for the desired cache line and the result cached in L1 TLB  128 , a process that may be referred to as a TLB refill. Further details of the operation of data caches  126  and  130  and TLBs  128  and  140  that account for and avoid corruption of microcode emulation memory  135  are presented below. 
         [0020]      FIG. 2  illustrates one embodiment of a virtual memory and cache architecture that may be used with processor  110 . In the illustration, a virtual memory space  210  is shown, portions of which are mapped to a physical memory address space  220 . Portions of physical memory address space  220  are shown mapped to L2 cache space  230 , portions of which are in turn mapped to L1 cache space  240 . Each application that executes on processor  110  may employ a separate virtual memory address space. Virtual memory address space  210 , as shown in  FIG. 2 , includes blocks  211 - 215  that represent the portions of virtual memory that are mapped to physical memory address space  220  and are available to be accessed by an application at a given point in time. Similarly, physical memory address space  220  includes blocks  221 - 224  that represent the portions of physical memory that are cached in L2 cache space  230 . Likewise, L2 cache space  230  includes blocks  231 - 233  that represent the portions of L2 cache that are cached in L1 cache space  240 . More particularly, blocks  231 ,  232 , and  233  of L2 cache space  230  are mapped to blocks  242 ,  243 , and  241  of L1 cache space  240 , respectively. In various embodiments, each block described above may represent one of a set of cache lines, blocks of a uniform size, a group of cache lines or blocks, or blocks of varying sizes. In alternative embodiments, any of virtual memory address space  210 , physical memory address space  220 , L2 cache space  230 , and L1 cache space  240  may include more or fewer blocks than the number shown in  FIG. 2 . 
         [0021]    In one embodiment, block  221  may be reserved in physical memory space  220  as microcode emulation memory. Further, block  231  of L2 cache space  230  may be permanently reserved for caching the contents of microcode emulation memory. During operation, when processor  110  desires to access microcode emulation memory, block  231  may be cached in level 1 cache, such as in block  242 , as shown in  FIG. 2 . However, block  242  may not be permanently reserved for the use of microcode emulation memory, as is block  231 . The blocks that are cached in L1 may change from time to time, depending on program execution. Accordingly, microcode emulation memory may be evicted from L1 to L2, where block  231  is reserved for its use. In one embodiment, access to microcode emulation memory by applications or processes other than microcode may be prevented by disallowing L1 TLB refills involving block  221  of physical memory space. 
         [0022]      FIG. 3  illustrates one embodiment of a process  300  for accessing a memory hierarchy including microcode emulation memory. A memory access may begin with a check for the presence of a microcode access signal (not shown) associated with each instruction decoded by an execution unit (decision block  310 ). For example, in one embodiment, a bit of each decoded instruction may be used as a microcode access signal. In an alternative embodiment, microcode instructions may have a special opcode that serves as a microcode access signal and by which they may be identified as microcode. Any of a variety of alternative microcode access signals may be conveyed from an execution unit to a cache controller to indicate whether or not an instruction is a microcode instruction. If a microcode access signal is detected, then access to the microcode emulation memory may be allowed (block  320 ) and the access is completed. 
         [0023]    If the microcode access signal is not detected, process  300  may proceed as follows. One or more TLBs may be searched to find an entry matching the cache line targeted by the access (block  330 ). If a matching entry is found in an L1 TLB (decision block  340 ), then the targeted cache line may be accessed (block  390 ) and the access is completed. If a matching entry is not found in an L1 TLB but is found in an L2 TLB (decision block  350 ), then the targeted cache line may be moved from the L2 cache to the L1 cache (block  360 ), the targeted cache line may be accessed (block  390 ), and the access is completed. If a matching entry is not found in either L1 or L2 cache, then an address translation may be performed (block  370 ). If the result of the address translation produces a target address that is located in the microcode emulation memory (decision block  380 ), then the access may be prevented (block  384 ) ending the access attempt. If the result of the address translation produces a target address that is not located in the microcode emulation memory (decision block  380 ), then a TLB refill may be performed (block  382 ), the targeted cache line may be accessed (block  390 ), and the access is completed. 
         [0024]      FIG. 4  illustrates one embodiment of a process  400  for accessing microcode emulation memory in a level-1 cache. An access request targeted to microcode emulation memory may begin with a check to see if the targeted cache line is cached in an L1 cache (decision block  410 ). If so, access to the targeted cache line may be allowed (block  420 ) and the access is completed. If the targeted cache line is not cached in an L1 cache, then the reserved location of the targeted cache line in L2 cache may be obtained (block  430 ) The targeted cache line may then be moved from L2 cache to L1 cache (block  440 ). Once the target cache line is moved to L1 cache, access may be allowed (block  420 ) and the access is completed. 
         [0025]    Turning now to  FIG. 5  a block diagram of one embodiment of a computer system  500  including L2 data cache  560  and microcode emulation memory  135  coupled to a variety of system components is shown. In the depicted system, processor  510  is shown coupled to peripherals  520  and to a memory  530 . Peripherals  520  may include any of a variety of devices such as network interfaces, timing circuits, storage media, input/output devices, etc. that may be found in a conventional computer system. Memory  530  may include SDRAM, SRAM, ROM, DRAM and/or other conventional memory devices. Processor  510  includes cores  540 A and  540 B, write coalescing cache  550 , level-2 data cache  560 , and I/O interface  570 . I/O interface  570  may couple each of cores  540  to peripherals  520 . Elements referred to herein by a reference numeral followed by a letter may be collectively referred to by the reference numeral alone. For example, cores  540 A and  540 B may be referred to as cores  540  and an unspecified one of cores  540  may be referred to as a core  540 . 
         [0026]    Each of cores  540  includes a level-1 data cache  542 , a store logic unit  544 , and a load/store pipeline  546 . Store logic unit  544  (alternately referred to as “store unit”) may represent a portion of a load/store unit, a separate logic unit, or a combination thereof. Store logic  544  is coupled to both level-1 data cache  542  and write coalescing cache  550  to enable core  540  to write to either cache level. More specifically, store logic  544  may convey stores  584  to level-1 data cache  542  and stores  582  to write coalescing cache  550 . Write coalescing cache  550  may be further coupled to level-2 data cache  560  via fills  564  and evicts  566 . Write coalescing cache  550  may coalesce stores  582  with fills  564  to produce a reduced number of evicts  566 . Level-2 data cache  560  may be further coupled to each level-1 data cache  542 . More specifically, level-2 data cache  560  may convey fills  562  to level-1 data cache  542 . Level-2 data cache  560  may also be bi-directionally coupled to memory  530 . 
         [0027]    During operation, core  540  may execute a stream of instructions that, when decoded, cause loads  586  from L1 data cache  542  to load/store pipeline  546  and/or stores  580  from load/store pipeline  546  to store logic  544 . The instructions executed by core  540  may include execution of microcode. When microcode execution requires access to a cache line in microcode emulation memory  135 , the targeted cache line may be accessed and, if necessary, moved from L2 data cache  560  to L1 data cache  542  using the process described in  FIG. 4  above. Once the targeted cache line is moved to L1 data cache  542 , it may be accessed via loads  586  and/or stores  580  and  584 . 
         [0028]    Although system  500 , as shown, include two cores, in alternative embodiments more than two cores may be included and/or each core may represent a cluster of execution units. Additional level-2 caches may also be included in further alternative embodiments in which more than two cores are included. Further, although level-2 data cache  560  is shown coupled directly to memory  530  and memory  530  is shown as off-processor memory, processor  510  may include a memory controller and/or on-processor memory. Alternatively, an off-processor memory controller may couple level-2 data cache  560  to memory  530 . A variety of processor core and memory configurations will be apparent to one of ordinary skill in the art. 
         [0029]    It is noted that the above-described embodiments may comprise software. In such an embodiment, the program instructions that implement the methods and/or mechanisms may be conveyed or stored on a computer accessible medium. Numerous types of media which are configured to store program instructions are available and include hard disks, floppy disks, CD-ROM, DVD, flash memory, Programmable ROMs (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Still other forms of media configured to convey program instructions for access by a computing device include terrestrial and non-terrestrial communication links such as network, wireless, and satellite links on which electrical, electromagnetic, optical, or digital signals may be conveyed. Thus, various embodiments may further include receiving, sending or storing instructions and/or data implemented in accordance with the foregoing description upon a computer accessible medium. 
         [0030]    Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Technology Classification (CPC): 6