Patent Abstract:
A single-stage switched-mode power supply comprises: a dual-source ac rectifying unit (501), for converting an alternating current input by an alternating current power source into at least two direct current sources, namely, a first direct current source (606) and a second direct current source (607); a combination switch unit, at least comprising a first switch circuit (603) and a second switch circuit (605), used for respectively performing power conversion on the first direct current source (606) and the second direct current source (607), to output a direct current, wherein the first direct current source (606) is connected to the first switch circuit (603) through an energy-storage capacitor (604), the first switch circuit (603) is any circuit capable of functioning as a switch circuit, and the second switch circuit (605) is a circuit capable of functioning as a flyback switch circuit. The single-stage switch power supply has complete power factor correction and output hold-up time, and further improves power source conversion efficiency.

Full Description:
TECHNOLOGY AREA 
       [0001]    The present disclosure provides a single-stage switched-mode power supply (SMPS). 
       BACKGROUND 
       [0002]    Electricity is among the most convenient and widely used energy form. With the ever increasing rate of energy use, there is increasing attention on energy efficiency, especially on increasing the power conversion efficiency of the SMPS. As it is often the input power supply of many appliances, the SMPS contributes a large part to the appliance&#39;s overall efficiency, which can only be lower than that of the SMPS. 
         [0003]      FIG. 1 through 4  are schematic depictions of four prior art single-transistor, single-stage high-frequency SMPS topologies. Their implementations are limited to low-power ac-dc power conversion. The simplest topology of  FIG. 1  contains an active clamp network  101 . It has significant drawbacks when used in low-voltage high-current output applications, due to the need of large output capacitance for energy storage, the complexity of clamp network control and associated minimal amount of loss. The drawbacks in topology of  FIG. 2  are present in added size and cost of the two rectifier diodes and their contribution to the clamp network&#39;s losses. The drawbacks in topology of  FIG. 3  are present as results of the additional half conversion stage, the control complexity of achieving unity power factor and the large current stress and related loss in the power switch during turn-on resulting from stored energies in the inductor and transformer. The topology in  FIG. 4  suffers from issues such as low efficiency, the addition of two rectifiers which increases converter loss, size and cost, and similar problems associated with the power switch as described for the  FIG. 3  topology. 
         [0004]    To meet the many high-end power management requirements, a modern SMPS needs to be highly efficient and contains advanced technologies such as interleaving, soft-switching, synchronous rectification, output management and reduced power conversion stages. In contrast, the performance of single-stage SMPS with prior art technologies has not seen a dramatic increase, making their commercialization difficult. 
       SUMMARY 
       [0005]    The present disclosure provides a single-stage SMPS. The SMPS comprises of, a dual-source ac rectifying unit, used to convert an input ac source and generate at least two new (first and second) dc sources; a combined switching cell, comprised of first and second switching circuits used for power conversion from the first and second dc sources, with the two circuits&#39; outputs paralleled and producing dc; connection of the first dc source and switching circuit via a bulk capacitor; the first switching circuit being any switched-mode topology; the second switching circuit being the flyback-derived topology. 
         [0006]    By using a topology with dual-source single-stage, active clamping, multi-phase interleaved switching and integrated control properties, the present disclosure can realize improved power conversion efficiency while retaining complete control of ac power factor correction and power supply output hold-up time. 
         [0007]    To allow for easy understanding of the present disclosure&#39;s features and merits, the remaining text provides detailed description along with drawings and embodiments. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    To better clarify embodiments of and technologies used in prior art and present disclosure, the following descriptions of their drawings are provided. The embodiments contained herein should not be limited to disclose embodiments but rather should be limited only by the spirit and scope of the appended claims. It will become apparent to one of ordinary skill in the art that other embodiments incorporating the same concepts may also be used. 
           [0009]      FIG. 1  is a schematic depiction of a prior art SMPS topology; 
           [0010]      FIG. 2  is a schematic depiction of a prior art SMPS topology; 
           [0011]      FIG. 3  is a schematic depiction of a prior art SMPS topology; 
           [0012]      FIG. 4  is a schematic depiction of a prior art SMPS topology; 
           [0013]      FIG. 5  is a system block diagram of the single-stage SMPS in the disclosure; 
           [0014]      FIG. 6  is a schematic depiction of topology used in the single-stage SMPS in the disclosure; 
           [0015]      FIG. 7  is a waveform diagram of currents and voltages in the single-stage SMPS in the disclosure; 
           [0016]      FIG. 8  is a schematic depiction of topology used in the single-stage SMPS in the disclosure; 
           [0017]      FIG. 9  is a schematic depiction of topology used in the single-stage SMPS in the disclosure; 
           [0018]      FIG. 10  is a schematic depiction of topology used in the single-stage SMPS in the disclosure; 
           [0019]      FIG. 11  is a schematic representation of a single-stage SMPS in accordance with exemplary embodiments of the disclosure; 
           [0020]      FIG. 12  is an integrated circuit diagram of controller used in a single-phase single-stage SMPS in accordance with exemplary embodiments of the disclosure; 
           [0021]      FIG. 13  is another schematic representation of a single-stage SMPS in accordance with exemplary embodiments of the disclosure; 
           [0022]      FIG. 14  is another integrated circuit diagram of controller used in a dual-phase single-stage SMPS in accordance with exemplary embodiments of the disclosure; 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    The embodiments of the present disclosure are now described in full detail using their drawings previously given. The embodiments contained herein should not be limited to the disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. Other embodiments incorporating the same concepts may be developed by one of ordinary skill in the art and shall be protected by the present disclosure. 
         [0024]    This disclosure provides a single-stage SMPS.  FIG. 5  shows the system block diagram of the single-stage SMPS in the disclosure. It includes a dual-source ac rectifying unit  501 , used to convert an input ac source and generate at least two new sources (first and second) with dc or quasi-dc characteristics, a combined switching cell  502 , comprised of first  5021  and second  5022  switching circuits, is used for power conversion from the first and second dc sources, with the two circuits&#39; outputs paralleled and producing dc. The first dc source and switching circuit are connected via a bulk capacitor. The second switching circuit is of the flyback-derived topology. The dual-source ac rectifying unit includes two rectifier bridges, where the bridges&#39; input ac terminals are paralleled, and the bridges&#39; negative dc output terminals are tied together. Together, they convert input ac to two dc sources. 
         [0025]    The single-stage SMPS of the disclosure also provides a current merging unit  503  and a dual-source controller unit  504 . The current merging unit is used to deliver the charging current from the combined switching cell back to the ac source, and forms a closed loop. The dual-source controller unit is used to control the first and second switching circuits in the combined switching cell  502 . 
         [0026]      FIG. 6  shows a schematic depiction of topology used in the single-stage SMPS in the disclosure. A dual-source ac rectifying network is formed using rectifier bridges  601  and  602 , with their ac input terminals paralleled and negative dc output terminals tied. This network contains two ac input and three dc output terminals and converts single-phase ac into two dc sources. Dc source  606  contains a large capacitor  604 , used as an energy-storage source. Dc source  607  contains no capacitor and is a time-varying voltage source. 
         [0027]    This combination of two dc sources forms a dual-source dc supply. The dc output of the SMPS is generated from converter cells  603  and  605 . Converter  605  is connected to dc source  607  and is of the flyback-derived topology. Converter  603  is connected to dc source  606  and energy-storage capacitor  604 . In addition, converter  603  can be realized with any switched-mode circuit topology, including but not limited to forward, flyback, push-pull and half or full-bridge. The two converters&#39; dc outputs are parallel-connected and store energy in output capacitor  609 . 
         [0028]    The single-stage SMPS of the disclosure also contains a line-frequency current merging network, which consists of two series-connected current-sensing resistors. The first end terminal of the resistor network is connected to the ac rectifying unit&#39;s negative output. The second end terminal is used to sink the line-frequency time-varying current I PFC , which is current flowing through converter  605  and is used by the SMPS to control the ac current. The middle terminal is used to sink the line-frequency charging current I CHG , which is the current flowing through converter  603  and describes the charging current in capacitor  604  due to ac. The total current flowing through the SMPS is I AC , and the relationship between the three currents is as follows: I AC =I CHG +I PFC . 
         [0029]    Waveforms in  FIG. 7  show graphically this relationship. The voltage on the energy storage is V CHG  and is essentially constant dc with small ripple. The voltage from the time-varying source is V AC  and has a full-wave rectified waveform following that of input ac. The magnitude and waveform of charging current I chg  is only dependent on the SMPS output load. The total SMPS input current I AC  is dependent on both load and ac power factor. The time-varying current I PFC  is uniquely determined by the above two currents and expressed as follows: I PFC =I AC −I CHG . 
         [0030]    The time-varying current I PFC  becomes one of the controlled variables of the dual-source controller. This quantity is used to achieve ac power factor correction. 
         [0031]    The dual-source ac rectifying unit can be realized with at least four different circuit topologies, as shown in  FIGS. 6 ,  8 ,  9  and  10 .  FIG. 6  shows a dual-source ac rectifying unit realized with eight diode rectifiers.  FIG. 8  shows a dual-source ac rectifying unit realized with five diode rectifiers.  FIG. 9  shows a dual-source ac rectifying unit realized with two diode rectifiers.  FIG. 10  shows a dual-source ac rectifying unit realized with six diode rectifiers. 
         [0032]    During the operation of the flyback converter cell used in this disclosure, the transient energy change developed by the transformer primary winding needs to be suppressed by a clamping circuit. The clamping circuits used in embodiments of this disclosure are classified as primary-side and secondary-side lossless voltage-clamp networks. They are used to suppress voltage transients that occur during the switch turn-off period in the second switching circuit. The secondary-side lossless voltage-clamp network includes a series-connected inductor and capacitor network, in which the first inductor terminal is connected to the transformer&#39;s secondary-side output in the second switching circuit, and the second inductor terminal is tied with the first capacitor terminal, and the second capacitor terminal is connected to the transformer&#39;s secondary-side ground. The primary-side lossless voltage-clamp network includes a series-connected inductor and capacitor network, in which the inductor is made up of a section of the transformer primary winding in the second switching circuit, and the first inductor terminal is connected to the switching device&#39;s drain or collector terminal, and the second inductor terminal is tied with the first capacitor terminal, and the second capacitor terminal is connected to the transformer primary winding&#39;s input ground. Further detailed description of the embodiments of this disclosure is now provided using two application examples. 
       APPLICATION EXAMPLE #1 
       [0033]      FIG. 11  shows a schematic of a dual-source single-phase single-stage ac-dc SMPS. It consists of ac rectifying bridges  1101  and  1102 , large energy-storage capacitor  1103 , transformers  1104   a  and  1104   b,  primary-side lossless voltage-clamp network  1106 , power switch  1108 , diode rectifier  1109  and single-phase single-stage SMPS dual-source controller integrated circuit (IC). Through rectifying bridges  1101  and  1102 , the ac input is decomposed into two dc sources, which are referred to as energy-storage source  1111  and time-varying source  1112 . These two sources together form a dual-dc source. They differ in that the energy-storage source contains a large energy-storage capacitor  1103 , which is not present in the time-varying source. The energy-storage and time-varying sources are connected to primary windings of transformers  1104   a  and  1104   b  respectively, the other ends of which are connected power switches  1108  and  1109  respectively. The above components and their connections form two single-switch converter circuits. The time-varying source is connected to a flyback converter or its variants, such as an interleaved flyback, any other flyback-derived converters or a parallel-connected combination of the above. The flyback converter is used to achieve ac power factor correction and to process on average half the total SMPS power. The energy-storage source is connected to an isolated dc-dc converter of any topology, including but not limited to forward, flyback, push-pull, half/full-bridge or a parallel-connected combination of the above. This application chooses the flyback converter to improve the SMPS output characteristics, especially under low voltage and high current conditions. It is also used to maintain hold-up time and to process on average half the total SMPS power. To suppress the voltage transient appearing across the power switch, this application uses the secondary-side lossless voltage-clamp network  1107 . 
         [0034]    The dc output voltage  1113  is fed back to the primary-side composite signal network  1151  through opto-coupler and the output sensing network  1114 . This voltage feedback signal is combined with the zero-current detection signal  1115  to form a synchronizing composite signal SYN, which is connected to controller  1120 . The controller&#39;s decoupling circuit then recovers both the zero-current detection signal  1115  and feedback signal from the output voltage  1113 . This single-phase single-stage SMPS dual-source controller IC saves one input signal by using the composite signal to control both converters. 
         [0035]    The charging current I CHG  in first switching circuit and energy-storage source  1111  flows through the current-sensing resistor  1116 . The power factor correction current I PFC  in second switching circuit and time-varying source  1112  flows through the current-sensing resistor  1117 . These two currents flows into ac after merging. The ac current signal is indirectly sampled by sampling the time-varying voltage signal VAC. The power factor correction current signal CS is the sum of voltages on resistors  1116  and  1117  in the current merging network  1150 . This implementation realizes the current relationship I PFC =I AC −I CHG  and achieves power factor correction. 
         [0036]    The detailed description of the primary-side lossless voltage-clamp network  1106  in this disclosure is now given. The primary-side lossless voltage-clamp network  1106  includes a series-connected inductor and capacitor network, in which the inductor is made up of a section of the transformer  1104   b  primary winding in the second switching circuit, and the first inductor terminal is connected to the drain or collector terminal of the switching device  1108 , and the second inductor terminal is tied with the first capacitor terminal, and the second capacitor terminal is connected to the transformer  1104   b  primary winding&#39;s input ground. When switching device  1108  turns on, its current consists of both the transformer  1104   b  primary winding current and the discharge current of the capacitor in clamp network  1106 . The energy stored in the clamping capacitor is released and stored in the primary winding inductance. When switching device  1108  turning off, the energy in transformer  1104   b  primary winding due to instantaneous change in electric potential is stored in the clamping capacitor through the clamping inductor. This energy transfer process suppresses losslessly the energy due to instantaneous change in electric potential. As the clamping inductor is realized with a winding sharing the same magnetic core with the primary winding but with different polarity, the induced voltage in the inductor winding further suppresses energy in this transient. 
         [0037]    The detailed description of the secondary-side lossless voltage-clamp network  1107  in this disclosure is now given. When power switch  1109  is turned on, the transformer  1104   a  primary winding is storing energy, and no current flows in the secondary winding. At same time, the energy stored in the capacitor in clamp network  1107  is released to the inductor. The capacitive energy is losslessly transformed into current in the inductor. The capacitor and inductor energies are together transferred to the output load. When power switch  1109  is turned off, the energy in transformer  1104   a  primary winding due to instantaneous change in electric potential is transferred to the capacitor in clamp network  1107  through the secondary winding. This energy is quickly absorbed and stored in the capacitor. This energy transfer process losslessly suppresses the energy due to instantaneous change in electric potential on power switch  1109 . 
         [0038]    In this application, the voltage transient on power switch  1108  during turn-off is suppressed by primary-side lossless voltage-clamp network  1106 . The network  1106  is consisted of a capacitor and inductor. The inductor winding shares same magnetic core with transformer  1104   b.  The capacitor is used to clamp the rapidly rising voltage. The inductor is used to recycle energy stored in the capacitor and stores it in the transformer during its energy-storing period. The clamping performance can be adjusted via capacitance selection. 
         [0039]    In this application, the voltage transient on power switch  1109  during turn-off is suppressed by secondary-side lossless voltage-clamp network  1107 . The network&#39;s capacitor is used to clamp the rapidly rising voltage coupled from primary of transformer  1104   a  to secondary. The network&#39;s inductor is used to transfer energy stored in the capacitor to output capacitor  1110  during the non-output period of the transformer. The clamping performance can be adjusted via capacitance selection. In both clamp networks, no dissipative elements participate in the energy storage and recovery processes. Therefore, both are lossless clamp networks. 
         [0040]      FIG. 12  shows integrated circuit  1120  of the single-phase single-stage dual-source controller unit. It contains at least one flyback SMPS controller  1122 , such as the commonly-used L6562 or similar controller. It also contains a flyback SMPS controller  1123 , such as the commonly-used UC3842 or similar controller. It finally contains a feedback signal de-coupler  1124 . Controller  1122  is used to control power switch  1108 . Controller  1123  is used to control power switch  1109 . Feedback signal de-coupler  1124  is used to restore the feedback composite signal SYN into zero-current detection signal ZCD and output voltage feedback signal FB. 
       APPLICATION EXAMPLE #2 
       [0041]    Shown in  FIG. 13  schematic, an interleaved single-stage ac-dc SMPS consists of at least dual-source ac rectifying bridges  1301  and  1302 , large energy-storage capacitor  1303 , an interleaved flyback switched-mode circuit  1304 , a circuit  1305  of any switched-mode circuit topology, an optional circuit  1306  also of any switched-mode circuit topology used as standby supply and an interleaved single-stage SMPS dual-source controller IC.  FIG. 14  shows schematic drawing of the interleaved single-stage SMPS dual-source controller IC. Through rectifying bridges  1301  and  1302 , the ac input is decomposed into an energy-storage source and a time-varying source. These two sources together form a dual-dc source. They differ in that the energy-storage source contains a large energy-storage capacitor  1303 , which is not present in the time-varying source. The time-varying source is connected to a switched-mode circuit based on the flyback topology, thereby enabling power factor correction of the SMPS and processing roughly half the total SMPS power. The switched-mode circuit connected to the energy-storage source can be of any topology, including but not limited to forward, flyback, push-pull and half/full-bridge. A LLC bridge-type circuit is used in this application to improve the SMPS output characteristics, especially under low voltage and high current conditions. It is also used to maintain hold-up time and to process on average half the total SMPS power. 
         [0042]    The dc output voltage VDC is fed back to the primary-side composite signal network  1351  through an opto-coupler and the output sensing network  1314 . This voltage feedback signal is combined with the zero-current detection signal  1351  to form a synchronizing composite signal SYN 1 , which is connected to controller  1320  as shown in  FIG. 14 . The controller&#39;s decoupling circuit  1324   a  then recovers both the zero-current detection signal and feedback signal from the dc output voltage, thereby saving one input signal. 
         [0043]    Standby dc output voltage VSB is fed back to the primary-side composite signal network  1352  through an opto-coupler and the output sensing network  1344 . This voltage feedback signal is combined with the zero-current detection signal to form a synchronizing composite signal SYN 2 , which is connected to controller. The controller&#39;s decoupling circuit  1324   c  then recovers both the zero-current detection signal and feedback signal from the standby dc output voltage, thereby saving an additional input signal. 
         [0044]    The standby supply in this application uses the flyback topology. It contains a synchronizing composite signal network  1353  that consists of two resistors. The network&#39;s switch current sensing signal CS and zero-current detection signal ZCsb are combined to form a composite signal Csb. The controller&#39;s decoupling circuit  1324   b  recovers the original signals CS and ZCsb from Csb, thereby saving another input signal. 
         [0045]    The charging current I CHG  in switched-mode circuit associated with energy-storage source  1311  flows through current sensing resistor  1316 . The power factor correction current I PFC  in switched-mode circuit associated with the time-varying source is the sum of currents I PFC     —     A  and I PFC     —     B , flowing through current sensing resistors  1317   a  and  1317   b  respectively. These three currents are merged, and the combined current is delivered to the ac source. The ac current is indirectly sensed through sensing signal VAC of the time-varying voltage. The power factor correction currents CSIa and CSIb are sensed through summing the voltages of resistors  1316 ,  1317   a  and  1317   b  in the current merging network. This results in the following expressions for the interleaved power factor correction current: 
         [0000]        I   PFC   =I   PFC     —     A   +I   PFC     —     B ; 
         [0000]        I   PFC   =I   AC   −I   CHG . 
         [0046]    This achieves desirable correction of the power factor. 
         [0047]    The single-phase single-stage SMPS dual-source controller IC  1320  is consisted of at least one interleaved flyback SMPS controller  1322  (e.g. commonly-used FAN9612 or similar controller), one LLC resonant SMPS controller  1323  (e.g. commonly-used UCC25600 or similar controller) and three signal de-couplers  1324   a,    1324   b  and  1324   c.  Controllers  1322  and  1323  are used to control switched-mode circuits  1304  and  1305 , respectively. Feedback signal de-coupler  1324   a  is used to recover the feedback composite signal SYN 1  into zero-current detection signal ZCD 1  and output voltage feedback signal FB. Feedback signal de-coupler  1324   c  is used to recover the feedback composite signal SYN 2  into zero-current detection signal ZCD 2  and standby voltage feedback signal FBsb. Synchronizing signal de-coupler  1324   b  is used to recover the synchronizing composite signal Csb into zero-current detection signal ZCsb and standby current sensing signal CS. 
         [0048]    The dual-source switched-mode circuit in the present disclosure is equivalent to the combination of two conventional switched-mode circuits. Some of the control signals in the two circuits are related. Therefore, complexity reduction and practicality improvements are expected in the dual-source switched-mode circuit by integrating controllers  1122  and  1123  of conventional circuits into single-phase dual-source controller  1120 . The same can be achieved by integrating controllers  1322  and  1323  of conventional circuits into dual-phase interleaved dual-source controller  1320 . 
         [0049]    The application examples have applied operating principles and explained implementations of the present disclosure. The examples&#39; descriptions only serve to help one understand methods and fundamental ideas of the present disclosure. It will become apparent to one of ordinary skill in the art that other embodiments incorporating the same concepts may also be used. Therefore, the embodiments contained herein should not be limited to be disclosed embodiments.

Technology Classification (CPC): 8