Patent Abstract:
This invention provide a new and improved output circuit of a semiconductor integrated circuit device that enables output of a slew-rate waveform with a desired gradient without generating unwanted delay and also enables reduction in switching noise. According to this invention, an output circuit of a semiconductor integrated circuit device for controlling the gradient of an output waveform of a CMOS output transistor using first and second variable resistance units (transfer gates) controlled by a signal of an input part has another CMOS output circuit for delaying rise of a gate by dividing an output part and connecting first and second resistance units (NMOS transistor and PMOS transistor) to the gates.

Full Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to an output buffer circuit of a semiconductor integrated circuit device, and particularly to an output circuit that makes the gradient of a rise/fall waveform of an output gentler.  
           [0003]    2. Description of the Related Art  
           [0004]    In a semiconductor integrated circuit device, if a rise/fall output waveform at the time of switching is steep, noise easily occurs in the power-supply potential and GND. Therefore, as a method for reducing the switching noise, it is conventionally effective to increase the rise/fall time (to make the gradient gentler).  
           [0005]    As a conventional circuit for making the rise/fall gradient of an output waveform gentler, a slew-rate output circuit of a CMOS transistor as shown in FIG. 1 is used. The main features of its circuit structure will now be described. An input A is connected to the gates of a PMOS transistor P 22 , an NMOS transistor N 22 , a PMOS transistor P 23  and an NMOS transistor N 23  constituting initial-stage inverters C 22  and C 23 . Transfer gates T 22  and T 23  are connected to the initial-stage inverters C 22  and C 23 , respectively. The drain of the PMOS transistor P 22  is connected to the gate of a PMOS transistor P 24  constituting a next-stage inverter C 24 . The drain of the NMOS transistor N 23  is connected to the gate of an NMOS transistor N 24  of the next-stage inverter.  
           [0006]    An output of the next-stage inverter NC 24  is connected to the gates of the transfer gates T 22  and T 23 . The drains of the transfer gates T 22  and T 23  are connected to the gates of a PMOS transistor P 21  and an NMOS transistor N 21  constituting an output transistor, respectively. An output Y is taken out from the drain of a CMOS output transistor C 21  connected to a first power-supply potential Vc and a second power-supply potential Vs (GND).  
           [0007]    In the operation of this circuit, first, when the input A is switched from 0 (L) to a power-supply voltage (H), the NMOS transistor N 22  is turned into ON-state. Influenced by ON-state resistance of the transfer gate T 22 , the gate potentials of the PMOS transistors P 21  and P 24  are gradually switched to L, and after a while, the PMOS transistors P 21  and P 24  are turned into ON-state. When also the NMOS transistor of the transfer gate T 22  is turned into ON-state, the fall in gate potential of the PMOS transistors P 21  and P 24  becomes much gentler. As a result, the output Y has a gentle rise waveform.  
           [0008]    When the input A is switched from the power-supply voltage (H) to 0 (L), the PMOS transistor P 23  is turned into ON-state. Influenced by ON-state resistance of the transfer gate T 23 , the gate potentials of the NMOS transistors N 21  and N 24  are gradually switched to H, and after a while, the NMOS transistors N 21  and N 24  are turned into ON-state. Since also the PMOS transistor of the transfer gate T 23  is turned into ON-state, the rise in gate potential of the NMOS transistors N 21  and N 24  becomes much gentler. As a result, the output Y has a gentle fall waveform.  
           [0009]    Other than the above-described technique, JP-A-5-218847, JP-A-9-148909, JP-A-10-290154, and Japanese Patent No. 3,014,164 disclose output circuits for controlling the slew rate in order to prevent the switching noise.  
           [0010]    However, in the above-described circuit for controlling the rise/fall time of an output waveform (to make the waveform gradient gentler) using the transfer gates, in order to increase ON-state resistance and make the rise/fall in gate potential of the output transistor gentler, a large number of constituent transistors must be used in the transfer gates for controlling the output transistor. Moreover, even a dimensional change of the transistors is not enough for making the waveform gradient gentler, and a problem arises that only the delay of an output signal increases while the waveform does not become gentler.  
         SUMMARY OF THE INVENTION  
         [0011]    Thus, it is an object of the present invention to provide a new and improved output circuit of a semiconductor integrated circuit device that enables output of a slew-rate waveform with a desired gradient without generating unwanted delay and also enables reduction in switching noise. According to the present invention, an output circuit of a semiconductor integrated circuit device for controlling the gradient of an output waveform of a CMOS output transistor using first and second variable resistance units (transfer gates) controlled by a signal of an input part has another CMOS output circuit for delaying rise of a gate by dividing an output part and connecting first and second resistance units (NMOS transistor and PMOS transistor) to the gates. In the output circuit thus constituted, an output of an output transistor in a circuit according to the conventional technique for controlling the rise/fall time of an output waveform (to make the waveform gradient gentler) using a transfer gate is divided, and an output transistor having a much gentler rise/fall waveform gradient is connected using the first and second resistance units (ON-state resistance of the transistor) connected to the gate, thereby enabling provision of an output waveform with a gentle gradient without significantly delaying an output signal. Thus, it is possible to restrain switching noise. By changing the rate of division, it is possible to provide a waveform with a desired output gradient. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    [0012]FIG. 1 is a diagram showing a conventional output circuit.  
         [0013]    [0013]FIG. 2 is a diagram showing an output circuit according to a first preferred embodiment.  
         [0014]    [0014]FIG. 3 is a diagram showing an output circuit according to a second preferred embodiment.  
         [0015]    [0015]FIG. 4 is a diagram showing an output circuit according to a third preferred embodiment.  
         [0016]    [0016]FIG. 5 is a diagram showing an output circuit according to a fourth preferred embodiment.  
         [0017]    [0017]FIGS. 6A and 6B are views showing the relation between output voltage and time in the output circuits of the first to fourth embodiments and the conventional output circuit. FIG. 6A shows rise waveforms. FIG. 6B shows fall waveforms. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]    Preferred embodiments of the output circuit of the semiconductor integrated circuit device according to the present invention will now be described in detail with reference to the attached drawings. In this specification and drawings, constituent elements having substantially the same functional structures are denoted by the same symbols and numerals and will not be described repeatedly.  
         [0019]    First Preferred Embodiment  
         [0020]    A first preferred embodiment will be described with reference to FIG. 2. On the input side, an input A is connected to the gates of a PMOS transistor P 2  and an NMOS transistor N 2  forming a CMOS inverter C 2 , which is a first CMOS inverter circuit, and the gates of a PMOS transistor P 3  and an NMOS transistor N 3  forming a CMOS inverter C 3 , which is a second CMOS inverter circuit, the CMOS inverters C 2  and C 3  being connected in series between a first power-supply potential (for example, power Vc) and a second power-supply potential (for example, ground GND).  
         [0021]    Between the drains of the CMOS inverters C 2  and C 3 , transfer gates T 2  and T 3  are connected, which are first and second variable resistance units each being constituted by an NMOS transistor and a PMOS transistor. The drain (node n 2 ) of the CMOS inverter C 2  and the drain (node n 3 ) of the CMOS inverter C 3  are connected to the gates of a PMOS transistor P 4  and an NMOS transistor N 4  forming a first CMOS circuit C 4  and the gates of a PMOS transistor P 5  and an NMOS transistor N 5  forming a second CMOS circuit C 5 , the PMOS transistor P 4  and the NMOS transistor N 4 , and the PMOS transistor P 5  and the NMOS transistor N 5  being connected in series between the first power-supply potential and the second power-supply potential.  
         [0022]    Moreover, an output part (node n 1 ) of the CMOS circuit C 4  with its gates connected with the node n 2  and the node n 3  is connected to the gates of the transfer gates T 2  and T 3 . An output of the CMOS circuit C 5  and an output Y are divided via a node n 4 , and to these outputs, a PMOS transistor P 1  and an NMOS transistor N 1  forming a third CMOS circuit C 1  and connected in series between the first power-supply potential and the second power-supply potential are connected.  
         [0023]    To the gates of the CMOS circuit C 1 , an NMOS transistor N 6  and a PMOS transistor P 6  of normally-on state are connected, which are connected as first and second resistance units and have their gates connected to the first power-supply potential and the second power-supply potential, respectively. Between the sources and drains of the NMOS transistor N 6  and the PMOS transistor P 6 , a PMOS transistor P 7  and an NMOS transistor N 7  are connected by their gates and drains, respectively. The source of the PMOS transistor P 7  is connected to the first power-supply potential. The source of the NMOS transistor N 7  is connected to the second power-supply potential.  
         [0024]    The operation of these circuits will be described now. When the input A is switched from 0 (L) to a power-supply voltage (H), the NMOS transistor N 2  is turned into ON-state. Influenced by ON-state resistance of the transfer gate T 2 , the gate potentials of the PMOS transistors P 5  and P 4  are gradually switched to L, and after a while, the PMOS transistors P 5  and P 4  are turned into ON-state. As a result, the output of the PMOS transistor P 5  is gently switched from L to H. As the NMOS transistor of the transfer gate T 2  is thus turned into ON-state, the fall in gate potential of the PMOS transistors P 5  and P 1  becomes gentler. Also the gate potential of the PMOS transistor P 1  gradually falls, influenced by ON-state resistance of the NMOS transistor N 6 . As a result the output waveform of the output Y is gently switched from L to H.  
         [0025]    When the input A is switched from the power-supply voltage (H) to 0 (L), the PMOS transistor P 3  is turned into ON-state. Influenced by ON-state resistance of the transfer gate T 3 , the gate potentials of the NMOS transistors N 5  and N 4  are gradually switched to H. As a result, the output of the NMOS transistor N 5  is gently switched from H to L. As the PMOS transistor of the transfer gate T 3  is turned into ON-state, the rise in gate potential of the NMOS transistors N 5  and N 1  becomes gentler. Also the gate potential of the NMOS transistor N 1  gradually rises, influenced by ON-state resistance of the PMOS transistor P 6 . As a result, the output waveform of the output Y is gently switched from H to L.  
         [0026]    To increase the ON-state resistance of the transfer gates and the ON-state resistance of the NMOS transistor and PMOS transistor, plural NMOS transistors and PMOS transistors may be connected in parallel to the gates, and a gentler output waveform can be thus realized.  
         [0027]    In this preferred embodiment, the effect of dividing the output transistor is that only the waveform gradient of the transistor can be made gentler in order to cause desired rise/fall in output at one output transistor and restrain acute rise/fall in output at the other output transistor having delayed rise/fall, thus preventing occurrence of unwanted delay. The waveform can also be controlled to a desired waveform in accordance with the rate of division, that is, different combinations of output transistors.  
         [0028]    [0028]FIGS. 6A and 6B show rise/fall output waveforms according to this preferred embodiment. It can be seen that a gentler gradient than in the conventional technique can be realized without generating delay.  
         [0029]    As described above, as the drains of the transistor having large ON-state resistance are connected to the gates of the divided output transistors, the output waveform can be made gentler. Moreover, a desired output waveform can be realized in accordance with the rate of division of the output transistors (output ratio of the output transistors).  
         [0030]    Second Preferred Embodiment  
         [0031]    A second preferred embodiment will be described with reference to FIG. 3. The structures up to first and second CMOS inverter circuits are the same as those of the first preferred embodiment shown in FIG. 2. The structure of an output part includes a CMOS circuit C 1  including a PMOS transistor P 1  and an NMOS transistor N 1 , a CMOS inverter C 8 , which is a third CMOS inverter circuit, and a CMOS inverter C 9 , which is a fourth CMOS inverter circuit. An output (node n 4 ) of the CMOS circuit C 1  is connected to the gates of the CMOS inverter C 8 . An output (node n 5 ) of the CMOS inverter C 8  is connected to the gates of the CMOS inverter C 9 . An output (node n 6 ) of the CMOS inverter C 9  is connected to the gates of the transfer gates T 2  and T 3 . The CMOS inverters and the CMOS output transistors are connected in series between the first power-supply potential and the second power-supply potential.  
         [0032]    Similarly to the first preferred embodiment, when the input A is switched from 0 (L) to a power-supply voltage (H), the output of the transfer gate T 2  is gradually switched from H to L. As a result, the gate potential of the PMOS transistor P 1  is gradually switched from L to H and the output Y rises gently. The output Y is fed back by two-stage inverters constituted by the CMOS inverter C 8  and the CMOS inverter C 9  and the gate potential of the transfer gate T 2  is gradually switched from L to H. With the synergistic effect of these, the gate potential of the PMOS transistor P 1  is switched from H to L more gently and the output Y rises more gently.  
         [0033]    When the input A is switched from the power-supply voltage (H) to 0 (L), the output of the transfer gate T 3  is switched from L to H more gently. As a result, the gate potential of the NMOS transistor N 1  is gradually switched from H to L and the output Y falls gently. The output Y is fed back by the two-stage inverters constituted by the CMOS inverter C 8  and the CMOS inverter C 9  and the gate potential of the transfer gate T 3  is gradually switched from H to L. With the synergistic effect of these, the gate potential of the NMOS transistor N 1  is switched from L to H more gently and the output Y falls more gently.  
         [0034]    [0034]FIGS. 6A and 6B show rise/fall output wave forms according to this preferred embodiment. It can be seen that a gentler gradient than in the conventional technique and the first preferred embodiment can be realized. The reason for the steep gradient from near 20 nS in the rise waveform is that the transfer gate is initially in OFF-state for a while because of the influence of delay at the two-stage inverters and has a relatively steep gradient from 20 nS after it is turned into ON-state. A similar action is taken in the fall waveform, too. However, since the output NMOS transistor has high performance, the change in gradient does not appear.  
         [0035]    As described above, according to the second preferred embodiment, since the feedback output of the CMOS output transistor can be delayed by the two-stage inverters, the switching of the transfer gate can be delayed. Therefore, the input signal of the gate of the output transistor gently rises and falls, and the output waveform can be thus made gentler.  
         [0036]    Third Preferred Embodiment  
         [0037]    A third preferred embodiment will be described with reference to FIG. 4. As this preferred embodiment has a structure constituted by adding the structure of the second preferred embodiment to the structure of the first preferred embodiment, it will not be described further in detail.  
         [0038]    The output Y is divided into a CMOS circuit C 5  including a PMOS transistor P 5  and an NMOS transistor N 5 , which is a first CMOS circuit, and a CMOS circuit C 1  including a PMOS transistor P 1  and an NMOS transistor N 1 , which is a second CMOS circuit. Similarly to the first preferred embodiment, PMOS transistors P 6  and P 7  and NMOS transistors N 6  and N 7  are connected the gates of the PMOS and NMOS transistors P 1  and N 1  of the CMOS circuit C 1 . Similarly to the second preferred embodiment, CMOS inverters C 8  and C 9  are connected to a node n 4  of the CMOS circuit C 5 .  
         [0039]    Similarly to the first preferred embodiment, when the input A is switched from 0 (L) to a power-supply voltage (H), the output of the transfer gate T 2  is gradually switched from H to L. Influenced by ON-state resistance of the NMOS transistor N 6 , the gate potential of the PMOS transistor P 1  is gradually switched from H to L and the output Y is gently switched from L to H. The output Y is fed back by two-stage inverters constituted by the CMOS inverters C 8  and C 9  and the gate potential of the transfer gate T 2  is gradually switched from L to H. With the synergistic effect of these, the gate potential of the PMOS transistor P 1  is switched from H to L more gently and the output Y rises more gently.  
         [0040]    When the input A is switched from the power-supply voltage (H) to 0 (L), the output of the transfer gate T 3  is switched from L to H gently. Influenced by ON-state resistance of the PMOS transistor P 6 , the gate potential of the NMOS transistor N 1  is gradually switched from L to H and the output Y is gently switched from H to L. The output Y is fed back by the two-stage inverters constituted by the CMOS inverters C 8  and C 9  and the gate potential of the transfer gate T 3  is gradually switched from H to L. With the synergistic effect of these, the gate potential of the NMOS transistor N 1  is switched from H to L more gently and the output Y falls more gently.  
         [0041]    As described above, according to the third preferred embodiment, in addition to the effect of the second preferred embodiment, the gate input signal of the CMOS output transistor can gently rise and fall because of the ON-state resistance of the transistors. Therefore, the output waveform of the output transistor can be made gentler, as shown in FIGS. 6A and 6B.  
         [0042]    Fourth Preferred Embodiment  
         [0043]    A fourth preferred embodiment will be described with reference to FIG. 5. This embodiment employs a structure that realizes gentler rise/fall in gate potential of a CMOS output circuit. The drain (node n 2 ) of a CMOS inverter C 2 , which is a first CMOS inverter circuit, and the drain (node n 3 ) of a CMOS inverter C 3 , which is a second CMOS inverter circuit, are connected to the gates of a PMOS transistor P 4  and an NMOS transistor N 4  constituting a CMOS circuit C 4  and the gates of a PMOS transistor P 15  and an NMOS transistor N 15  constituting a CMOS circuit C 15 . An output (node n 7 ) of the CMOS circuit C 15  is connected to the gate of an NMOS transistor N 16  with its source connected to the node n 2  and is also connected to the gate of a PMOS transistor P 16  with its source connected to the node n 3 .  
         [0044]    Between the source and drain of the NMOS transistor N 16 , a PMOS transistor P 7  is connected by its gate and drain. Between the source and drain of the PMOS transistor P 16 , an NMOS transistor N 7  is connected by its gate and drain. The sources of the PMOS transistor P 7  and the NMOS transistor N 7  are connected to the first power-supply potential and the second power-supply potential, respectively. The drains of the NMOS transistor N 16  and the PMOS transistor P 16  are connected to the gates of a CMOS circuit C 1  including a PMOS transistor P 1  and an NMOS transistor N 1 . An output of the CMOS circuit C 1  is taken out from the output part Y. The CMOS inverters and the CMOS output transistors are connected in series between the first power-supply potential and the second power-supply potential.  
         [0045]    When the input A is switched from 0 (L) to a power-supply potential (H), the output of the transfer gate T 2  is gradually switched from H to L. As the output of the transfer gate T 2  is inputted to the gate of the CMOS circuit C 15 , the output of the inverter is gently switched from L to H. Since the output of the CMOS circuit  15  is connected to the gate of the NMOS transistor N 16 , the NMOS transistor N 16  is turned on with a delay. Because of the ON-state resistance and the switching delay of the NMOS transistor N 16 , the input signal of the gate of the PMOS transistor P 1  is delayed and gently switched from H to L. Therefore, the output of the CMOS circuit C 1  is gently switched from L to H.  
         [0046]    When the input A is switched from the power-supply potential (H) to 0 (L), the output of the transfer gate T 3  is gradually switched from L to H. As the output of the transfer gate T 3  is inputted to the gate of the CMOS circuit C 15 , the output is gently switched from H to L. Since the output of the CMOS circuit  15  is connected to the gate of the PMOS transistor P 16 , the PMOS transistor P 16  is turned on with a delay. Because of the ON-state resistance and the switching delay of the PMOS transistor P 16 , the input signal of the gate of the NMOS transistor N 1  is delayed and gently switched from L to H. Therefore, the output of the CMOS circuit C 1  is gently switched from H to L.  
         [0047]    Also in this preferred embodiment, to increase the ON-state resistance of the transfer gates and the ON-state resistance of the NMOS transistor and PMOS transistor, plural NMOS transistors and PMOS transistors may be connected in parallel to the gates, and a gentler output waveform can be thus realized.  
         [0048]    As described above, according to the fourth preferred embodiment, since the gate input signal of the output transistor gently rises and falls because of the ON-state resistance of the inverters, a very gentle output waveform can be realized, as shown in FIGS. 6A and 6B.  
         [0049]    While the preferred embodiments of the output circuit of the semiconductor integrated circuit device according to the present invention are described above with reference to the attached drawings, the present invention is not limited to these embodiments. It is clear to those skilled in the art that various changes and modifications can be implemented without departing from the technical scope of the invention as defined by the appended claims, and that such changes and modifications are included in the technical scope of the invention.

Technology Classification (CPC): 7