Patent Abstract:
A method and system are provided for deriving a resultant software program from an originating software program having overlapping branches, wherein the resultant software project has either no overlapping branches or fewer overlapping branches than the originating software program. A preferred embodiment of the invented method generates a resultant software program that has no overlapping branches. The resultant software is more easily converted into programming reconfigurable logic than the originating software program. Separate and individually applicable aspects of the invented method are used to eliminate all four possible states of two overlapping branches, i.e., forward branch overlapping forward branch, back branch overlapping back branch, and each of the two possible and distinguishable states of forward branch and back branch overlap. One or more elements of each aspect of the invention may be performed by one or more computers or processors, or by means of a computer or a communications network.

Full Description:
CO-PENDING PATENT APPLICATIONS 
     This Nonprovisional Patent Application is a Continuation Application to Nonprovisional patent application Ser. No. 13/360,805, filed on Jan. 30, 2012 by inventor Robert Mykland and titled “SYSTEM AND METHOD FOR COMPILING MACHINE-EXECUTABLE CODE GENERATED FROM A SEQUENTIALLY ORDERED PLURALITY OF PROCESSOR INSTRUCTIONS”. 
     Nonprovisional patent application Ser. No. 13/360,805 is hereby incorporated by reference in its entirety and for all purposes, to include claiming benefit of the priority date of filing of Nonprovisional patent application Ser. No. 13/360,805. 
     This Nonprovisional Patent Application is also a Continuation-in-Part Application to Nonprovisional patent application Ser. No. 13/301,763, filed on Nov. 21, 2011 by inventor Robert Mykland and titled “CONFIGURABLE CIRCUIT ARRAY”. 
     Nonprovisional patent application Ser. No. 13/301,763 is hereby incorporated by reference in its entirety and for all purposes, to include claiming benefit of the priority date of filing of Nonprovisional patent application Ser. No. 13/301,763. 
     In addition, this Nonprovisional Patent Application is a Continuation-in-Part Application to Provisional Patent Application Ser. No. 61/500,619, filed on Jun. 24, 2011 by inventor Robert Mykland. Provisional Patent Application Ser. No. 61/500,619 is hereby incorporated by reference in its entirety and for all purposes, to include claiming benefit of the priority date of filing of Provisional Patent Application Ser. No. 61/500,619. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to information technology. More particularly, the present invention relates to methods of and systems for modifying software code for application with programmable logic. 
     BACKGROUND OF THE INVENTION 
     The prior art provides software programs that consist of sequences of machine-executable commands wherein overlapping logic branches are sometimes included. The application of prior art software programs exhibiting overlapping branches in programming reconfigurable logic can inhibit or degrade the performance of the reconfigurable logic. Certain reconfigurable logic simply cannot reliably execute software programs that present one or more overlapping branches. 
     There is therefore a long-felt need to provide methods and systems that enable a conversion of an originating software program having one or more overlapping branches into a resultant software program that includes either no overlapping branches or fewer overlapping branches than the originating software program. 
     SUMMARY AND OBJECTS OF INVENTION 
     It is an object of the invented method to provide a method and a system that enable the conversion of an originating software program having one or more overlapping logic branches into a resultant software program that includes either no overlapping branches, or fewer overlapping branches than the originating software program. 
     It is another optional object of the present invention to provide a system and method for modifying a plurality of sequential software instructions to generate a resultant software program that may be executed by a computer, an applications specific circuit and/or a custom device logic circuit having programmable logic circuitry, reconfigurable logic circuitry, and/or an array of reconfigurable logic circuits. 
     It is yet another optional object of the invented method to provide a system and method wherein the resultant software program may be provided to and executed by a computer and/or a data processing system that comprises a reconfigurable logic processor. 
     Towards these objects and other objects that will be made obvious in light of this disclosure, a first version of the invented method provides a method and a system that modifies a plurality of software encoded instructions to generate a resultant software program that may be executed by and/or in concert with reconfigurable logic circuitry. 
     According to the method of the present invention (hereinafter “the invented method”), a source software program is provided that comprises a sequentially ordered series of machine-executable instructions. The source software program, or “source program” is then modified by finding one, more than one, or each instance of overlapping conditional logic branch pairs and generating a resultant code that provides equivalent logical flow of the source program but eliminates or reduces the instances of overlapping conditional branching of the source program. 
     According to a first optional aspect of the invented method, the source program is modified by (a.) locating an instance of instructions (hereinafter “back overlap pattern”) of the source program that instantiate a pair of overlapping conditional back branches when these instructions of an instant back overlap pattern are executed in a descending order from a first-executed instruction to a last-executed instruction of the source program; (b.) deriving a set of instructions (hereinafter “back set”) that when executed are logically equivalent to the back overlap pattern, wherein the back set do not encode overlapping conditional back branches; and (c.) replacing the back overlap pattern with the back set. 
     The first optional aspect of the invented method may be applied to either the entire source program or a selected instruction sequence of the source program (hereinafter “selected sequence”) to generate a first resultant code that when executed does not instantiate overlapping conditional back branches. The first resultant code may be derived from the selected sequence by modification of the selected sequence in an ascending order proceeding from a last-executed conditional back branch instruction of the selected sequence to a first-executed back branch target label of the selected sequence, wherein the first-executed back branch target label is located earlier in the selected sequence than the last-executed conditional back branch instruction. 
     In a second optional aspect of the invented method, a second resultant code may generated by modification of the first resultant code, wherein the first resultant code is modified by sequentially finding each pair of mixed overlapping conditional branches of the first resultant code, wherein each pair of mixed overlapping conditional branches includes a conditional back The second resultant code provides a process flow that is logically equivalent to both the selected sequence and the first resultant code, and wherein the second resultant code does not instantiate either mixed overlapping conditional branches or overlapping conditional back branches. The preferred order of deriving the second resultant code from the first resultant code is in an ascending order proceeding from a last-executed instruction of the first resultant code or selected sequence and toward a first-executed instruction of the first resultant code or selected sequence. 
     According to the second optional aspect of the invented method, an instruction pattern of the selected sequence or the first resultant code is identified as an “owner overlap pattern” when the owner overlap pattern of instructions includes a forward conditional branch instruction that is located within the first resultant code or selected sequence in between (a.) a back conditional branch instruction and (b.) a back target label of the instant back conditional branch instruction. Each toe overlap pattern thereby includes instructions that define a forward conditional branch that overlaps a back conditional branch, and each instance of owner overlap pattern is preferably replaced with an “owner set” of instructions, wherein each owner set provides the same logical process flow of a selected set of owner overlap pattern but eliminates or reduces overlapping conditional branching. 
     According further to the second optional aspect of the invented method, an instruction pattern of the selected sequence or the first resultant code is identified as a “toe overlap pattern” when the toe overlap pattern of instruction includes a forward conditional branch instruction (a.) is located earlier in the selected sequence or the first resultant code, i.e., more proximate to the first-executed instruction of the selected sequence or first resultant code, than a back target label of a back conditional branch instruction and (b.) the instant forward conditional branch instruction points to a forward target label that is positioned between the instant back target label and the back conditional branch instruction that points to the instant back target label. Additionally according to the second optional aspect of the invented method, each toe overlap pattern includes instructions that define a forward conditional branch that overlaps a back conditional branch, and each toe overlap pattern of instructions is preferably replaced with a “toe set” of instructions, wherein each toe set provides the same logical process flow of the originating toe overlap pattern of instructions but eliminates or reduces overlapping conditional branching. 
     According to a third optional aspect of the invented method, the second resultant code is modified to generate a third resultant code by (a.) locating a yet alternate instance of instructions (hereinafter “forward overlap pattern”) of the second resultant code that instantiate a pair of overlapping conditional front branches when these forward overlap instructions are executed; (b.) deriving a set of instructions (hereinafter “forward set”) that when executed are logically equivalent to the forward overlap pattern, wherein the forward set do not encode overlapping conditional forward branches; and (c.) replacing the forward overlap pattern with the forward set in a third resultant code. 
     The preferred order of deriving the third resultant code from the second resultant code is in a descending order proceeding from a first-executed instruction of the second resultant code and toward a last-executed instruction of the second resultant code. 
     In a fourth optional aspect of the invented method, one or more elements of one or more aspects of the invented method are applied in singularity or combination to modify the source program or an instruction sequence thereof of overlapping conditional branches by generating a logically equivalent resultant code. For example, a fourth resultant code might be generated by applying the third aspect of the invented code to the source program and to thereby replace all forward overlap instructions of the source program with forward sets and remove some or all forward overlapping conditional branches from the fourth resultant code. In another example, a fifth resultant code might be generated by applying the second aspect of the invented code to the source program and to thereby replace all mixed overlap instructions of the source program with owner sets and/or toe sets and thereby remove some or all mixed overlapping conditional branches from the fifth resultant code. 
     In a yet another optional aspect of the invented method, one, more than one, or all of the first through the third aspects of the invented method may be in singularity, in combination and/or sequentially applied to the selected sequence or the source program to derive a fifth resultant software program, wherein the resultant software may be executed by a computational system having programmable logic, reconfigurable logic and/or an information technology network that comprises reconfigurable or programmable logic. 
     In still another optional aspect of the method the present invention, an order of modifying a source program to remove overlapping branches is implemented in the following order: (1.) firstly, all overlapping back branch pairs are sequentially removed in an ascending order within the source program, wherein new code sequences are generated within a resultant software program that provide logic equivalent to the logic of the removed overlapping back branches; (2.) secondly, all pairs of overlapping back and forward branches are sequentially removed in an ascending order within the source program, wherein new code sequences are generated that provide logic equivalent to the logic of the removed overlapping pairs of back and forward branches; and (3.) thirdly, all overlapping forward branch pairs are sequentially removed in a descending order within the source program, wherein new code sequences are generated that provide logic equivalent to the logic of the removed overlapping forward branches. 
     In an additional optional aspect of the invented method, a computational system having reconfigurable logic, and/or an information technology network that comprises reconfigurable logic, is provided that accepts and executes the resultant software code derived in accordance with one or more of the recited aspects of the invented method. 
     In certain still alternate preferred embodiments of the invented method, some or all of an array of reconfigurable logic circuits are communicatively or bi-directionally communicatively coupled to a memory, a back buffer, and one or more memory controllers. 
     Additionally or alternately, the invented method provides a reprogrammable logic unit as disclosed in U.S. Pat. No. 7,840,777 issued on Nov. 23, 2010 to inventor Robert Mykland and titled “Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime” and a method of programming thereof. 
     Still additionally or alternately, the invented method provides a reprogrammable logic unit as disclosed in U.S. Nonprovisional patent application Ser. No. 13/301,763 filed on Nov. 21, 2011 to inventor Robert Mykland and titled “CONFIGURABLE CIRCUIT ARRAY” and a method of programming thereof. 
     INCORPORATION BY REFERENCE 
     All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited. All publications, patents, and patent applications mentioned in this specification are herein incorporated by reference in their entirety and for all purposes to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference. 
     Such incorporations include U.S. Pat. No. 8,078,849 (inventors: Libby, et al.; issued on Dec. 13, 2011) titled “Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table”; U.S. Pat. No. 7,840,950 (titled Stoodley, et al.; issued on Nov. 23, 2010) titled “Programmatic compiler optimization of glacial constants”; U.S. Pat. No. 7,840,777 (inventor: Mykland; issued on Nov. 23, 2010) titled “Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime”; U.S. Pat. No. 6,438,737 (inventors: Morelli, et al.; issued on Aug. 20, 2002) titled “Reconfigurable logic for a computer”; U.S. Pat. No. 7,171,659 (inventors: Becker, et al.; issued on Jan. 30, 2007) titled “System and method for configurable software provisioning”; U.S. Pat. No. 7,167,976 (inventor: Poznanovic, D.; issued on Jan. 23, 2007) titled “Interface for integrating reconfigurable processors into a general purpose computing system”; U.S. Pat. No. 7,155,602 (inventor: Poznanovic, D.; issued on Dec. 26, 2006) titled “Interface for integrating reconfigurable processors into a general purpose computing system”; U.S. Pat. No. 7,076,575 (inventor: Baitinger, et al.; issued on Jul. 11, 2006) titled “Method and system for efficient access to remote I/O functions in embedded control environments”; U.S. Pat. No. 6,868,017 (inventor: Ikeda, K.; issued on Mar. 15, 2005) titled “Integrated circuit device”; and U.S. Pat. No. 6,717,436 (inventors: Kress, et al.; issued on Apr. 6, 2004) titled “Reconfigurable gate array”. 
     Such incorporations further include in U.S. Nonprovisional patent application Ser. No. 13/301,763 filed on Nov. 21, 2011 to inventor Robert Mykland and titled “CONFIGURABLE CIRCUIT ARRAY”; US Patent Appn. Publication Ser. No. 20060004997 (inventor: Mykland, Robert; published on Jan. 5, 2006) titled “Method and apparatus for computing”; US Patent Appn. Publication Ser. No. 20040068329 (inventor: Mykland, Robert; published on Apr. 8, 2004) titled “Method and apparatus for general purpose computing”; US Patent Appn. Publication Ser. No. 20040019765 (inventor: Klein, Robert C. JR.; published on Jan. 29, 2004) titled “Pipelined reconfigurable dynamic instruction set processor”; and US Patent Appn. Publication Ser. No. 20040107331 (inventor: Baxter, Michael A.; published on Jun. 3, 2004) titled “Meta-address architecture for parallel, dynamically reconfigurable computing”. 
     In addition, each and all publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent in their entirety and for all purposes as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference. The publications discussed or mentioned herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Furthermore, the dates of publication provided herein may differ from the actual publication dates which may need to be independently confirmed. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       These, and further features of the invention, may be better understood with reference to the accompanying specification and drawings depicting the preferred embodiment, in which: 
         FIG. 1  is a functional block diagram of a prior art computational device having a processor module communicatively coupled with a memory module, a network interface, one or more input modules and one or more output modules; 
         FIG. 2  is a functional block diagram of a reconfigurable computational device having a reconfigurable logic circuit array communicatively coupled with a memory controller, a system memory, a back buffer, one or more input modules, one or more output modules, and an optional processor; 
         FIG. 3  is an information technology network that comprises at least one prior art computational device of  FIG. 1  and optionally one or more reconfigurable computational devices of  FIG. 2 ; 
         FIG. 4  is a representation of a sequential listing of software-encoded, machine-executable instructions that comprise or are provided within a selected sequence of a source software program or a resultant program as disclosed within; 
         FIG. 5  presents a detail view of the sequential listing of  FIG. 4  that includes an exemplary back overlap pattern that defines two overlapping conditional back branches; 
         FIG. 6A  is a flow chart of an application of the first aspect of the invented method wherein overlapping back branches are sequentially removed in an ascending order within the selected sequence of instructions of  FIG. 4  and  FIG. 5 , and each back overlap pattern of is replaced with a back set generated therefrom; 
         FIG. 6B  is a flow chart of a derivation of an exemplary back set from the exemplary back overlap pattern of  FIG. 6A  and an imposition of the exemplary back set into the selected sequence of  FIG. 4  in the application of the method of  FIG. 6A ; 
         FIG. 6C  is a representation of a detail of a first resultant software code that includes a back set of instructions derived from the exemplary back overlap pattern of  FIG. 5  and in accordance with the first aspect of the invented method of  FIGS. 6A and 6B ; 
         FIG. 7  presents a detail view of a second portion of the selected sequence of instructions of  FIG. 4  that an owner pattern of overlapping conditional branches and a toe pattern of overlapping conditional branches; 
         FIG. 8  is a flow chart of an application of the second aspect of the invented method wherein overlapping owner patterns and toe patterns an are sequentially removed in an ascending order within the first resultant code of  FIGS. 1 and 2 , and each overlapping owner pattern and toe pattern is respectively is respectively replaced with an equivalent owner set or toe set; 
         FIG. 9A  is a detail view of an exemplary owner pattern of the first resultant code and/or the source program of  FIGS. 1 and 2 ; 
         FIG. 9B  is a flow chart of a derivation and imposition of an owner set into the software code of  FIG. 9A ; 
         FIG. 9C  is a representation of the owner set generated by the method of  FIG. 9B  as written into the second resultant software of  FIGS. 1 and 2 ; 
         FIG. 10A  is a detail view of an exemplary toe pattern of the first resultant code and/or the source program of  FIGS. 1 and 2 ; 
         FIG. 10B  is a flow chart of a derivation and imposition of a toe set into the software code of  FIG. 10A ; 
         FIG. 10C  is a representation of the toe set generated by the method of  FIG. 9B  as written into the second resultant software of  FIGS. 1 and 2 ; 
         FIG. 11  presents a detail view of the sequential listing of  FIG. 4 , the first resultant code of  FIGS. 1 and 2  and/or the second resultant code of  FIGS. 1 and 2  that includes an exemplary forward overlap pattern that defines two overlapping conditional forward branches; 
         FIG. 12A  is a flow chart of an application of the third aspect of the invented method wherein overlapping forward branches are sequentially removed in a descending order within the source program, the first resultant code and/or the second resultant code of  FIGS. 1 and 2 , and whereby each forward overlap pattern is replaced with a forward set derived therefrom; 
         FIG. 12B  is a flow chart of a derivation and imposition of an exemplary forward set into the software code of  FIG. 11  in the application of the method of  FIG. 12A ; 
         FIG. 12C  is a representation of a detail of a third resultant software code that includes a back set of instructions derived from the exemplary back overlap pattern of  FIG. 12A  and in accordance with the second aspect of the invented method of  FIGS. 12A and 12B ; 
         FIG. 13  is a flow chart of a successive application of the first four aspects of the invented method of  FIGS. 5 through 1C  to a sequential listing of software encoded instructions of  FIG. 4 ; and 
         FIG. 14  is a process chart of a derivation of resultant software code of  FIG. 13  and application of the resultant software code by a computational system having reconfigurable logic of  FIG. 2  and/or an informational technology network of  FIG. 3  comprising reconfigurable logic. In step  14 . 2  the source program is input into either the computer  2 , the reconfigurable computer  4 , and/or distributed within the system  2 ,  3 C &amp;  4  of the network  3 . 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that this invention is not limited to particular aspects of the present invention described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims. 
     Methods recited herein may be carried out in any order of the recited events which is logically possible, as well as the recited order of events. 
     Where a range of values is provided herein, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range, is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges and are also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits ranges excluding either or both of those included limits are also included in the invention. 
     Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present invention, the methods and materials are now described. 
     It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. It is further noted that the claims may be drafted to exclude any optional element. As such, this statement is intended to serve as antecedent basis for use of such exclusive terminology as “solely,” “only” and the like in connection with the recitation of claim elements, or use of a “negative” limitation. 
       FIG. 1  is a functional block diagram of a prior art computational device  2  (hereinafter “computer”  2 ) having a processor module  2 A communicatively coupled with a memory module  2 B, a network interface  2 C, one or more input modules  2 D. 1 - 2 D.N and one or more output modules  2 E. 1 - 2 E.N. The processor module  2 A may comprise one or more digital electronic microprocessors, such as, but not limited to, a COR I7 Extreme Processor™ processor or a NEHALEM™ processor as marketed by Intel Corporation of Santa, or other suitable electronic logic processors known in the art. 
     The computer  2  may be (a.) a network-communications enabled SUN SPARCSERVER™ computer workstation marketed by Sun Microsystems of Santa Clara, Calif. running LINUX™ or UNIX™ operating system; (b.) a network-communications enabled personal computer configured for running WINDOWS XP™, VISTA™ or WINDOWS 7™ operating system marketed by Microsoft Corporation of Redmond, Wash.; (c.) a VAIO FS8900™ notebook computer marketed by Sony Corporation of America, of New York City, New York; (d.) a PowerBook G4™ personal computer as marketed by Apple, Inc. of Cupertino, Calif.; (e.) an IPAD™ tablet computer as marketed by Apple, Inc. of Cupertino, Calif.; (f.) an IPHONE™ cellular telephone as marketed by Apple, Inc. of Cupertino, Calif.; or (g.) an other suitable computational device known in the art. 
     A bi-directional internal communications bus  2 F communicatively couples and provides electrical power to the processor module  2 A with the memory module  2 B, the network interface  2 C, the input modules  2 D. 1 - 2 D.N and the output modules  2 E. 1 - 2 E.N. 
     One or more input modules  2 D. 1 - 2 D.N may be or comprise a computer keyboard, a computer mouse, a point and click selection device, a track ball, a mouse pad, an external disk drive module, a memory stick and/or other suitable user input or data input devices known in the art. One or more output modules  2 E. 1 - 2 E.N may be or comprise a display device having a display screen, a touch screen, a portable memory module and and/or other suitable data output devices known in the art. 
     The network interface  2 C is adapted to bi-directionally communicatively couple the computer  2  with an electronic communications network  3 , such as the Internet, a computer network and/or a telephony network. It is understood that the network interface  2 C may be adapted to provide wireless bi-directional communication between the computer  2  and the electronic communications network  3 . 
     The system memory  2 B stores an operating system SW. 1 , a first system software SW. 2 , an originating software program SW. 3 , and a plurality of resultant software programs R. 1 -R.N. The operating system SW. 1  directs the operations of computer  2 , controlling and scheduling the execution of other programs, and managing storage, input/output actions, and communication resources, and may be or comprise a LINUX™ or UNIX™ or derivative operating system, such as the DEBIAN™ operating system software as provided by Software in the Public Interest, Inc. of Indianapolis, Ind.; a WINDOWS XP™, VISTA™ or WINDOWS 7™ operating system as marketed by Microsoft Corporation of Redmond, Wash.; a MAC OS X operating system or iPhone G4 OS™ operating system as marketed by Apple, Inc. of Cupertino, Calif.; or an other suitable operating system known in the art. 
     The first system software SW. 2  provides machine executable instructions to cause and enable the computer  2  to instantiate the aspects of the invented method as disclosed herein. The originating source software program SW. 3  (hereinafter “source program” SW. 3 ) is a sequential series of instructions  4000 - 4999  SEQ upon which one or more aspects of the invented method may be applied by the computer  2  to generate each of the plurality of resultant software programs R. 1 -R.N (hereinafter “resultant code” R. 1 -R.N. It is understood that the term “source program” as used within the present disclosure indicates machine-executable software code and does not refer to higher-level source code programs or source programming languages. It is further understood that each resultant code R. 1 -R.N may be generated by the computer  2  applying on or more aspects of the invented method to the source program SW. 3  alternately in singularity and in various combinations and sequences to generate different resultant code R. 1 -R.N. 
       FIG. 2  is a functional block diagram of a reconfigurable computational device  4  (hereinafter “reconfigurable computer”  4 ) having a reconfigurable logic circuit array (hereinafter “RLC”  4 A) communicatively coupled with a memory controller  4 B (hereinafter “MC”  4 B), a system memory  4 C, a back buffer  4 D, one or more input modules  2 D. 1 - 2 D.N, the network interface  2 C, one or more output modules  2 E. 1 - 2 E.N, and an optional processor module  2 A. The bi-directional internal power and communications bus  2 F couples and provides electrical power to the RLC  4 A, the MC  4 B, the system memory  4 C, the back buffer  4 D, the optional processor module  2 A, the network interface  2 C, the input modules  2 D. 1 - 2 D.N and the output modules  2 E. 1 - 2 E.N. 
     The RLC  4 A is further directly bi-directionally communicatively coupled with the system memory  4 C. The back buffer  4 D is bi-directionally communicatively coupled with the system memory  4 C and the MC  4 B. The back buffer  4 D is further adapted to program the RLC  4 A. The MC  4 B is bi-directionally communicatively coupled with the system memory  4 C and the back buffer  4 D. The MC  4 B is further adapted to program the RLC  4 A. 
     The network interface  2 C is adapted to bi-directionally communicatively couple the reconfigurable computer  4  with an electronic communications network  3 , such as the Internet, a computer network and/or a telephony network. It is understood that the network interface  2 C may be adapted to provide wireless bi-directional communication between the reconfigurable computer  4  and the electronic communications network  3 . 
     A second operating system SW. 4  directs the operations of reconfigurable computer  4 , controlling and scheduling the execution of other programs, and managing storage, input/output actions, and communication resources, and may be or comprise the system software SW. 1  and/or some or all aspects of the software encoded instructions for directing the RLC  4 A to execute a plurality of successive computational array instructions at runtime as disclosed in Nonprovisional patent application Ser. No. 13/301,763, filed on Nov. 21, 2011 by inventor Robert Mykland and titled “CONFIGURABLE CIRCUIT ARRAY”. 
     The second system software SW. 5  provides machine executable instructions to cause and enable the reconfigurable computer  4  to instantiate the aspects of the invented method as disclosed herein. It is further understood that each resultant code R. 1 -R.N may be generated by applying on or more aspects of the invented method by the reconfigurable computer  4  to the source program SW. 3  in various combinations and sequences to generate different resultant code R. 1 -R.N. 
       FIG. 3  is a schematic diagram of the electronics communications network  3  (hereinafter “network”  3 ) that comprises at least one computer  2  and/or at least one reconfigurable computer  4 . The network  3  is an information technology network that may additionally comprise a telephony network  3 A and/or the Internet  3 B. The network  3  may further comprise a database server  3 C, wherein the database server  3 C may include one or more elements  2 A- 4 D or aspects of the computer  2  and/or the reconfigurable computer  4 . 
     It is understood that one or more of the aspects of the invented method may be executed in singularity, in concert, or in combination by one or more computer  2 , reconfigurable computer  4  and/or database server  3 C. 
     It is further understood that more computer  2 , reconfigurable computer  4  and/or database server  3 C may be applied to derive one or more resultant code R. 1 -R.N by the application of various aspects of the invented method from the source program SW. 3  or another resultant code R. 1 -R.N. 
       FIG. 4  is a representation of a representative sequential listing of software-encoded, machine-executable instructions  4000 - 4999  SEQ that comprise, or are provided within, the source program SW. 3  and/or a resultant code R. 1 -R.N. The executable instructions  4000 - 4999  SEQ are ordered for an intended order of sequential execution of the source program SW. 3  or resultant code R. 1 -R.N starting at a first instruction  4000  and proceeding through the execution of intervening instructions  4001  through  4998  until the execution of a last instruction  4999 , wherein branch operations can cause the processor module  2 A or the RLC  4 A to not execute certain instructions  4000 - 4999  SEQ and/or to repeatedly execute certain instructions  4000 - 4999  SEQ. 
     It is understood that the term “descending order” is defined herein to denote executing, instantiating, analyzing, processing or examining the instructions  4000 - 4999  SEQ in sequential order starting at the first instruction  4000  and proceeding to the last instruction  4999 . 
     It is also understood that the term “ascending order” is defined herein to denote executing, instantiating, analyzing, processing or examining the instructions  4000 - 4999  SEQ in sequential order opposite form the intended order of execution starting at the last instruction  4999  and proceeding to the first instruction  4000 . 
     It is further understood that exemplary first forward branch XFB. 1  and exemplary first back branch XBB. 1  can be applied by the computer  2  to direct the processor module  2 A to alternately (a.) skip over and not execute certain instructions; or (b.) to repeat an execution of certain instructions. For example, a first exemplary forward branch conditional logical query XFBI 1  of the instruction  4100  directs the processor module  2 A to proceed from executing step  4100  to step  4199  when a logical condition or value of X 1  is determined to exist at the instant execution of step  4100 . Logical instructions  4101  to  4199  are thus not executed by the computer  2  when the processor module  2 A finds in an execution of instruction  4100  that a logical condition X 1  exists, but rather the computer  2  proceeds to execute instruction  4199 , i.e., forward target label  4199 , as a next executed instruction after the instant execution of step  4100 . 
     The term “forward branch instruction” is defined herein to denote a software encoded conditional logical query or test wherein a determination by the executing computer  2  or  4  of a condition or value directs the computer  2  or the reconfigurable computer  4  to proceed from the instant instruction to a forward target label, e.g., instruction  4199 , without executing all instructions of comprising the source program SW. 3  or resultant code R. 1 -R.N intervening between the instant exemplary forward branch instruction XFBI 1  and an associated exemplary forward target label XFT 1 . 
     It is further understood that a back branch conditional logical query or test of the first exemplary back branch instruction XBBI 1  located within instruction  4399  directs the processor module  2 A to proceed from executing back branch instruction  4399  to executing an instruction  4300  associated with an exemplary back target label XBT 1  when the processor module  2 A finds in an execution of instruction  4399  that a pre-specified logical condition exists. According to the exemplary first back branch instruction XBBI 1 , the processor module  2 A proceeds from instruction  4399  to execute instruction  4300  when a logical condition Y 1  is met in the execution of instruction  4399  that is associated with the first back branch instruction XBBI 1 . 
     The term “back branch instruction” is defined herein to denote a software encoded conditional logical query or test wherein a determination of a condition or value directs the computer  2  or the reconfigurable computer  4  to proceed from processing the instant back branch instruction, e.g., instruction  4399 , to next executing a back target label XBT 1 , e.g., the back target label XBT 1  associated with instruction  4300 . 
     It is still further understood that one or more conditional logical queries or tests X 1 -XN or Y 1 -YN may be a negative query or test, wherein a determination of a nonexistence of a specified logical condition or value at the time of execution of the instant branch instruction FB. 1 -FB.N or BB. 1 -BB.N will lead to a positive finding of the query or test and thereby result in an activation of an associated back branch BB. 1 -BB.N or a forward branch FB. 1 -FB.N. 
     The term “back branch instruction” is defined herein to denote a conditional logical query or test wherein a positive finding directs the computer  2  or the reconfigurable computer  4  to proceed from an instant back branch instruction, e.g., instruction  4399 , to a back target label, e.g., instruction  4300 , wherein the back target label is located previous to the instant back branch instruction in the instruction sequence of instructions  4000 - 4999  SEQ. 
     It is understood that the terms “target” and “target label” as used herein indicate software code  4199  &amp;  4300  within the instruction sequence  4000 - 4999  SEQ to which a computer  2  or  4  next references or executes after the execution of a branch instruction  4100  &amp;  4399  as determined by the host computer  2  or  4 . 
       FIG. 5  presents a detail view of a first portion of the sequential listing of instructions  4000 - 4999  SEQ that includes a back overlapping pattern that defines two overlapping back branches BB. 1  &amp; BB. 2 . A sequence A of instructions of the source program SW. 3  is disposed between a second back target label BT 2  and a first back target label BT 1 . 
     A sequence B of instructions of the source program SW. 3  is disposed between the first back target label BT 1  and a second back branch instruction BBI 2 . A sequence C of instructions of the source program SW. 3  is disposed between the second branch instruction BBI 2  and a first back branch instruction BBI 1 . The three sequence of instructions A, B &amp; C of  FIG. 5  are placed in a descending order from Sequence A to Sequence C within the source program instructions  4000 - 4999  SEQ. 
     According to the logic of the first back branch BB. 1 , a program execution of the source program SW. 3  by the processor module  2 A proceeds from the first back branch instruction BBI 1  to the first back target label BT 1  when a logic condition of X 1  is met In the execution of the first back branch instruction BBI 1 . 
     In addition, according to the logic of the second back branch BB. 2  a program execution of the source program SW. 3  by the processor module  2 A proceeds from the second back branch instruction BBI 2  to the second back target label BT 2  when a logic condition of Y 1  is met in the execution of the second back branch instruction BBI 2 . 
       FIG. 6A  is a flow chart of a portion of the instruction sequence  4000 - 4999  SEQ that in the generation of a first resultant code R. 1  replaces the back overlap pattern of  FIG. 5  with a back set of  FIG. 6C  and thereby remove the overlapping back branches from the sequence of instructions  4000 - 4999  SEQ from the first resultant code R. 1 . A current line value CRNT and a first line value FIRST are initialized in step  6 A. 02  wherein the current line value CRNT is equal to the value of the final line of code  4999  of the sequence of instructions  4000 - 4999  SEQ and the first line value FIRST is set equal to the first line of code  4000  of the sequence of instructions  4000 - 4999  SEQ. In step  6 A. 04  the computer  2  determines if the current line value CRNT has been decremented by cycling through the loop of steps  6 A. 10  through  6 A. 22  to be made equal to or less than the first line value FIRST of  4000 . When the computer  2  determines in step  6 A. 04  that the current line value CRNT has been decremented to be equal to or lesser than the first line value FIRST, the computer  2  proceeds on to store the software code modified by execution of steps  6 A. 04  through  6 A. 22  as a first resultant code R. 1 , and proceeds from step  6 A. 06  to step  6 A. 08  and to perform alternate computational operations. 
     When the computer  2  determines in step  6 A. 04  that the code line value CRNT of the sequence of instructions  4000 - 4999  SEQ is greater than the first line value FIRST, the computer  2  proceeds on to step  6 A. 10  to determine if software code at line value CRNT provides a back branch instruction. When the computer  2  determines in step  6 A. 10  that the software code at line value CRNT is not a back branch instruction, the computer  2  proceeds onto step  6 A. 12  and to decrement the current line value CRNT. The computer  2  proceeds from step  6 A. 12  to an additional execution of step  6 A. 04 . When the computer  2  determines in step  6 A. 10  that the software code at line value CRNT is a back branch instruction BBI 1 , the computer  2  proceeds onto step  6 A. 14  and to seek a first instance of an overlapping additional back branch instruction BBI 2 , or “OBB”, positioned between a first back branch instruction BBI 1  determined in the last instance of step  6 A. 10  and a first back target label BT 1  as specified by the first back branch instruction BB 1 . When an overlapping second back branch instruction BB 2  is not found by the computer  2  within the sequence of instructions SEQ between the first branch instruction BB 1  and the first back target label BT 1  in step  6 A. 16 , the computer  2  proceeds onto step  6 A. 18  and to load a value of the code line associated with the first back target label BT 1  and therefrom onto step  6 A. 04 . 
     When an overlapping second back branch instruction BB 2  is discovered by the computer  2  within the sequence of instructions SEQ between the first branch instruction BB 1  and the first back target label BT 1  in step  6 A. 16 , the computer  2  proceeds onto step  6 A. 20  and to apply a back branch algorithm of the first aspect of the method of the present invention as disclosed in  FIG. 6B  and accompanying text. The computer  2  proceeds from step  6 A. 20  to step  6 A. 22  in the process of generating the first resultant code R. 1  and to update all pointers and references within the source program SW. 3  that have been altered by the modifications of the instruction sequence  4000 - 4999  SEQ in the most recent instance of step  6 A. 20 . 
       FIG. 6B  is a flow chart of an exemplary instance of step  6 A. 20  of an instantiation of the back branch algorithm of the first aspect of the invented method, wherein a pair of overlapping back branches BB. 1  &amp;BB. 2  are replaced with a back set that comprises logically equivalent resultant code, wherein the equivalent first resultant code R. 1  includes a first resultant first forward branch R.FB. 1  and a first resultant back branch R.BB. 1  and the second back branch is removed from resultant code. In step  6 B. 02  a new first resultant forward target label R.FT 1  is inserted in the instruction sequence  4000 - 4999  SEQ immediately after the first back branch instruction BBI 1 . In step  6 B. 04  the second back branch instruction BBI 2  is overwritten with a new first resultant forward branch instruction R.FBI 1 , wherein the new first resultant forward branch instruction R.FBI 1  specifies that when a logical condition of Y 1  is met that execution of the resultant code R. 1  by the computer  2  or the reconfigurable computer  4  proceeds from first resultant forward branch instruction R.FBI 1  to the first resultant forward target label R.FT 1  of the first resultant code R. 1 . In step  6 B. 06  a new first resultant back branch instruction R.BBI 1  is inserted into the resultant code R. 1 , wherein the new first resultant back branch instruction R.BBI 1  specifies that when the logical condition of Y 1  is met that execution of the resultant code R. 1  by the computer  2  or the reconfigurable computer  4  proceeds from first resultant back branch instruction R.BBI 1  to the original second back target label BT 2 . The current value CRNT is incremented by a value of two in step  6 B. 08  in recognition that the length of the resultant code of  FIG. 6C  contains two more instructions than the original code of  FIG. 6A . 
       FIG. 6C  is an illustration of an element of a back set of a first resultant code R. 1  that is derived from the first code portion of  FIG. 5  in accordance with the first aspect of the invented method and in an implementation of the method of  FIG. 6B , wherein the system software SW. 2  or SW. 5  modifies the source program SW. 3  to generate the first resultant code R. 1  by reformulating the second back branch BB. 2  as a first resultant forward branch R.FB. 1  and a first resultant back branch R.BB. 1 . 
     According to the first resultant forward branch R.FB. 1 , a program execution of the resultant code R. 1  by the processor module  2 A or RLC  4 A proceeds from a resultant forward branch instruction R.FB 1  of the first resultant forward branch R.FB. 1  to the second branch target label BT 2  when a logic condition of Y 1  is met in the execution of the resultant forward branch instruction R.FBI 1 . 
     According to the first resultant back branch R.BB. 1  a program execution of the resultant code R. 1  by the processor module  2 A or RLC  4 A proceeds from a resultant third back branch instruction R.BBI 3  to a resultant back target label R.BT 3  when a logic condition of Y 1  is met in the execution of the resultant third back branch instruction R.BBI 3 . 
     The first resultant code R. 1  is organized as follows: (1.) sequence A of the source program SW. 3  is disposed between the resultant branch third target label R.BT 3  and the first branch target label BT 1 ; (2.) sequence B of the source program SW. 3  is disposed between the first branch target label BT 1  and the resultant first forward branch instruction R.FBI 1 ; (3.) sequence C of the source program SW. 3  is disposed between the resultant first forward branch instruction R.FBI 1  and the back branch instruction BBI 1 ; (4.) and the resultant first branch target label R.FT 1  is disposed between the back branch instruction BBI 1  and the third resultant back branch instruction R.BB 3 . 
       FIG. 7  presents a detail view of the instruction sequence  4000 - 4999  SEQ that includes the first back branch BB. 1  and two exemplary overlapping forward branches OFB. 1  &amp; OFB. 2 . The second optional aspect of the invented method is applied to provide a second resultant code R. 2  that removes forward branch overlapping of each back branch of the first resultant code R. 1  in that generation of a second resultant code R. 2 , wherein the second resultant code R. 2  includes an equivalent logical flow of the instruction sequence  4000 - 4999  SEQ of the instruction sequence  4000 - 4999 . 
     For the purpose of explanation of the second aspect of the invented method,  FIG. 7  presents an exemplary toe overlapping forward branch TFB. 1  and an exemplary owner overlapping forward branch OFB. 1 . 
     The exemplary first toe overlapping forward branch TOFB. 1  is generated by a toe forward branch instruction TFBI that both (a.) is positioned earlier in the instruction sequence  4000 - 4999  SEQ than the target label BT 1  of the first back branch instruction BBI 1 ; and (b.) points to a toe forward branch target TFT that is positioned between the first back branch instruction BBI 1  and the first back branch target BT 1 . 
     The exemplary owner overlapping forward branch OFB. 1  is generated by an owner forward branch instruction OFBI that (a.) is positioned in the instruction sequence  4000 - 4999  SEQ between the first target label BT 1  and the first back branch instruction BBI 1 ; and (b.) is directed to an owner forward target label OFT that is positioned within the instruction sequence  4000 - 4999  SEQ after the first back branch instruction BBI 1 . 
       FIG. 8  is a flow chart of a second portion of the first system software SW. 2  that implements the second optional aspect of the invented method and removes mutual overlapping of back branches and forward branches from the sequence of instructions  4000 - 4999  SEQ. 
     The current line value CRNT and the first line value FIRST are initialized in step  802  wherein the current line value CRNT is set to be equal to the value of the final line of code  4999  of the sequence of instructions  4000 - 4999  SEQ and the first line value FIRST is set to be equal to the first line of code  4000  of the sequence of instructions  4000 - 4999  SEQ. In step  804  the computer  2  determines if the current line value CRNT has been decremented by cycling through the loop of steps  810  through  816  to be made equal to or less than the first line value FIRST of  4000 . When the computer  2  determines in step  804  that the current line value CRNT has been decremented to be equal to or lesser than the first line value FIRST, the computer  2  proceeds on to store the software code modified by execution of steps  810  through  816  as the second resultant code R. 2 , and proceeds from step  806  to step  808  and to perform alternate computational operations. 
     When the computer  2  determines in step  804  that the code line value CRNT of the sequence of instructions  4000 - 4999  SEQ is greater than the first line value FIRST, the computer  2  proceeds on to  810  to determine if software code at line value CRNT provides a back branch instruction. When the computer  2  determines in step  810  that the software code at line value CRNT is not a back branch instruction, the computer  2  proceeds onto step  812  and to decrement the current line value CRNT. The computer  2  proceeds from step  812  to an additional execution of step  804 . 
     When the computer  2  determines in step  810  that the software code at line value CRNT is an exemplary third back branch instruction BBI 3 , the computer  2  proceeds onto step  814  to (a.) detect each instance on an overlapping internal forward branch instruction OFB positioned between the exemplary instant third back branch instruction BBI 3  and a third back target label BT 3 ; and (b.) apply an owner algorithm to each detected instance of forward branches that overlap the instant third branch BB. 3  to generate the second resultant code R. 2 , wherein the overlapping instructions of the first resultant code R. 1  is replaced in the second resultant code R. 2  with one or more owner sets that thereby reduce or avoid the generation of internal forward branches overlapping the instant third back branch BB. 3 . 
     After the removal of internal forward branches that overlap the instant exemplary third back branch BB. 3 , the computer  2  proceeds on to step  816  to remove each instance of overlapping external forward branches of the first resultant code R. 1  in the generation of the second resultant code R. 2 . In step  816 , the computer  2  proceeds to (a.) detect each instance on an overlapping external forward branch instruction OFB positioned between the exemplary instant third back target label BT 3  and the first instruction  4000  of the instruction sequence  4000 - 4999  SEQ; and (b.) apply a toe algorithm to each instance of forward branches detected in step  816  that overlap the instant third branch BB. 3  to generate the second resultant code R. 2 , wherein the overlapping instructions of the first resultant code R. 1  are replaced in the second resultant code R. 2  with one or more toe sets that thereby reduce or avoid the generation of external forward branches overlapping the instant third back branch BB. 3 . 
     The computer  2  proceeds from step  816  to step  812  and to decrement the current value CRNT, and therefrom to another execution of step  804 . 
     Referring generally to Figures and particularly to  FIGS. 8, 9A, 9B, 9C, 10A, 10B and 100 , it is understood that the generation of owner sets as illustrated in  FIGS. 9A, 9B and 9C  may occur repeatedly in succeeding modifications of the first resultant code R. 1 , or alternatively of source code SW. 3 , in the execution of step  814 . It is understood that the generation of toe sets as illustrated in  FIGS. 10A, 10B and 100  may occur repeatedly in succeeding modifications of the first resultant code R. 1 , or alternatively of source code SW. 3 , in the execution of step  816 . 
       FIGS. 9A through 9C  illustrate the partial generation of the second resultant code R. 2  by replacement of owner instruction patterns of the first resultant code R. 1  with owner sets of the second resultant code R. 2 . 
       FIG. 9A  presents a detail view of a first instruction sequence R 1 .SEQ 1  of the resultant code R. 1 , or optionally the source program SW. 3 , that includes an owner instruction pattern and three sequences of instructions D, E &amp; F. 
     The owner instruction pattern provides a third forward branch FB. 3  that overlaps a third back branch BB. 3 , wherein the third back branch BB. 3  is formed by a third back branch instruction BBI 3  that points to a third back target label BT 3 , and the third forward branch FB. 3  is formed by a third forward branch instruction FBI 3  that points to a third forward target label FT 3 . The third forward target label FT 3  is positioned at the end of the first instruction sequence R 1 .SEQ 1 . 
     According to the logic of the third forward branch FB. 3 , a program execution of the first instruction sequence R 1 .SEQ 1  by the processor module  2 A proceeds from the third forward branch instruction FBI 3  to the third forward target label FT 3  when a logic condition of Y 3  is met In the execution of the third forward branch instruction FBI 3 . Furthermore, according to the logic of the third back branch BB. 3 , a program execution of the first instruction sequence R 1 .SEQ 1  by the processor module  2 A proceeds from the third back branch instruction BBI 3  to the third back target label BT 3  when a logic condition of X 3  is met In the execution of the third back branch instruction BBI 3 . 
     An instruction sequence D of instructions of the first resultant code R. 1  is disposed between third back target label BT 3  and the third forward branch instruction FBI 3 . An instruction sequence E of instructions of the first resultant code R. 1  is disposed between the third forward branch instruction FBI 3  and the third back branch instruction BBI 3 . An instruction sequence F of instructions of the first resultant code R. 1  is disposed between the third back branch instruction BBI 3  and the third forward target label FT 3 . The three sequences of instructions D, E &amp; F of  FIG. 9A  are placed in a descending order from Sequence D to Sequence F within the instruction sequence  4000 - 4999  SEQ of the first resultant code R. 1 . 
       FIG. 9B  is an Illustration of an execution of the owner algorithm that is applied in step  814  as often as required in ascending order within the resultant code R. 1  to replace owner overlap patterns with owner sets. Toward this end, system software SW. 2  directs the computer  2  or  4  to seek all forward branch instructions that form an owner overlap pattern in combination with the instant back branch instruction, wherein each relevant forward branch (1.) is located in the first resultant code R. 1  between the instant back branch instruction selected in the most previous execution of step  810  and the back target label of the instant back branch instruction; and (2.) forms an overlap pattern by having an associated forward target label that is located later in the first resultant code R. 1  than the instant back branch instruction. 
     In step  9 B. 2  a new forward target label R.FT 3  is inserted at the end of sequence E. In step  9 B. 4 , the third forward branch instruction FBI 3  is modified to point to the newly inserted forward target label R.FT 3 . In step  9 B. 6  a new owner back branch instruction R.BBI 3  is inserted into the first instruction sequence R 1 .SEQ 1  immediately after the new forward target label R.FT 3 . The owner back branch instruction R.BBI 3  includes logic that directs the computer to proceed to the third back target label BT 3  when the following logical statement is true:
         [X 3  and NOT(Y 3 )].       

     In step  9 B. 8  a new resultant forward branch instruction R.FBI 3  is inserted into the first instruction sequence R 1 .SEQ 1  immediately after the owner back branch instruction R.BBI 3 , wherein the new resultant forward branch instruction R.FBI 3  directs execution of the second resultant code R. 2  to proceed from the forward branch instruction R.FBI 3  to the original third forward target label FT 3  of the forward branch instruction FBI 3  of the owner overlap pattern of  FIG. 9A . Any and all pointers and references of the first resultant code R. 1  are updated as necessary in step  9 B. 10  in view of the addition of instructions to the first resultant code R. 1  imposed by the execution of steps  9 B. 2 - 9 B. 8 . 
     It is understood the that owner set of  FIG. 9C  creates three branches owner branches OBB. 1 , OFB. 1  &amp; OFB. 2  in the generation of the second resultant code R. 2 , namely a first owner forward branch OFB. 1  that extends from the third forward branch instruction FBI 3  to the resultant forward target label R.FT 3  and is activated when the logical state of Y 3  is true at the moment of execution of the third forward branch instruction FBI 3 ; a first owner back branch OBB. 1  that extends from the owner back branch instruction R.BBI 3  to the third back target label BT 3  and is activated when the logical equation of [X 3  and NOT(Y 3 )] is true at the moment of execution of the owner back branch instruction R.BBI 3 ; and a second owner forward branch OFB. 2  that extends from the resultant forward branch instruction R.FBI 3  to the third forward target label FT 3  located at the end of the Instruction sequence I, wherein the second owner forward branch OFB. 2  is activated when the logical condition Y 3  is true at the moment of execution of the resultant forward branch instruction R.FBI 3 . 
     Referring now to  FIGS. 10A through 10C ,  FIGS. 10A through 10C  illustrate the partial generation of the second resultant code R. 2  by replacement of toe instruction patterns of the first resultant code R. 1  with toe sets of the second resultant code R. 2 .  FIG. 10A  illustrates an exemplary first toe instruction pattern positioned within a second resultant instruction sequence R 1 .SEQ 2  of the first resultant sequence R. 1 . The exemplary toe instruction pattern includes a fourth forward branch instruction FBI 4  placed immediately before an instruction sequence J; a fourth back target label BT 4  located immediately after the instruction sequence J and immediately before an instruction sequence K; and a fourth forward target label FT 4  located immediately after the instruction sequence K and immediately before an instruction sequence L. 
     The fourth forward branch instruction FBI 4  activates a fourth forward branch FB. 4 , wherein an execution of the first resultant code R. 1  proceeds from the fourth forward branch instruction FBI 4  to the fourth forward target FT 4  when a logic condition Y 4  is determined to be true at the moment of execution of the fourth forward branch instruction FBI 4 . The fourth back branch instruction FBI 4  activates a fourth back branch BB. 4 , wherein an execution of the first resultant code R. 1  proceeds from the fourth back branch instruction BBI 4  to the fourth back target BT 4  when a logic condition X 4  is determined to be true at the moment of execution of the fourth back branch instruction BBI 4 . 
     The owner instruction pattern provides a fourth forward branch FB. 4  that overlaps a fourth back branch BB. 4 , wherein the fourth back branch BB. 4  is formed by a fourth back branch instruction BBI 4  that points to a fourth back target label BT 4 , and the fourth forward branch FB. 4  is formed by a fourth forward branch instruction FBI 4  that points to a fourth forward target label FT 4 . The fourth forward branch instruction FBI 4  is positioned at the beginning of the first instruction sequence R 1 .SEQ 2  and the fourth forward target label FT 4  is positioned in between the third back branch target FT 4  and the fourth back branch target FT 4 . 
     According to the logic of the fourth forward branch FB. 4 , a program execution of the second instruction sequence R 1 .SEQ 2  by the processor module  2 A proceeds from the fourth forward branch instruction FBI 4  to the fourth forward target label FT 4  when a logic condition of Y 4  is true at the moment of execution of the fourth forward branch instruction FBI 4 . Furthermore, according to the logic of the fourth back branch BB. 4 , a program execution of the second instruction sequence R 1 .SEQ 2  by the processor module  2 A proceeds from the fourth back branch instruction BBI 4  to the fourth back target label BT 4  when a logic condition of X 4  is true at the moment of execution of the fourth back branch instruction BBI 4 . 
       FIG. 10A  further illustrates that an instruction sequence G is disposed between the fourth branch instruction FBI 4  and the fourth back target label BT 4 ; that an instruction sequence H is disposed between the fourth forward back label BT 4  and the fourth forward target label FT 4 ; and an instruction sequence I is disposed between the fourth forward target label FT 4  and the fourth back target instruction BBI 4 . 
       FIG. 10B  is an Illustration of an execution of the toe algorithm that is applied in step  816  as often as required in ascending order within the resultant code R. 1  to replace toe overlap patterns with toe sets in the second resultant code R. 2 . Toward this end, system software SW. 2  or SW. 5  directs the computer  2  or  4  to seek all forward branch instructions that form a toe overlap pattern in combination with the instant back branch instruction, wherein each relevant toe pattern forward branch instruction (1.) is located in the first resultant code R. 1  after the back target label of the instant back branch instruction; and (2.) forms a toe overlap pattern in combination with the instant back branch instruction by having an associated forward target label that is located between the instant back target label and the instant back branch instruction. 
     According to the software-encoded toe algorithm of  FIG. 10B , when a toe instruction pattern is determined in step  8 . 16 , a new resultant forward target label R.FT 4  is inserted in step  10 B. 2  immediately after the end of instruction sequence G. The fourth forward branch instruction FBI 4  is modified to point to the new resultant forward target label R.FT 4  in step  10 B. 4  and thereby to form the first toe forward branch TFB. 1 . A new first toe set instruction TI. 1  is inserted between the new resultant forward target label R.FT 4  and the fourth back target label BT 4 , wherein the first toe set instruction TI. 1  sets the condition X 4  to be true. 
     A new resultant toe fourth branch instruction R.FBI 4  is inserted in step  10 B. 8 , wherein the resultant toe fourth branch instruction R.FBI 4  includes logic that directs the computer to proceed to the fourth forward target label FT 4  when the following logical statement is true:
         [NOT(X 4 ) or Y 4 ].       

     Any and all pointers and references of the first resultant code R. 1  are updated as necessary in step  10 B. 10  in view of the addition of instructions to the first resultant code R. 1  imposed by the execution of steps  10 B. 2 - 10 B. 8 . 
       FIG. 10C  is an illustration of an exemplary application of the toe algorithm of the invented method by the software-encoded method of  FIG. 10B  upon the toe instruction pattern of  FIG. 10A  to generate the exemplary toe set of  FIG. 10C  of the second resultant code R. 2 . As presented in  FIG. 10C , the first toe forward branch TFB. 1  of the toe set is formed by the fourth forward branch instruction FBI 4  and the fourth resultant forward target R.FT 4 . The second toe forward branch TFB. 2  of the exemplary toe set is formed by the resultant toe fourth branch instruction R.FBI 4  and the fourth forward target label FT 4 . 
       FIG. 11  is an illustration of a first sequence of software code S 2 .SEQ 1  of the second resultant code R. 2  that provides an overlapping pair of forward branches FB. 1  &amp; FB. 2 . The first sequence of software code S 2 .SEQ 1  includes a forward overlap pattern composed of a first forward branch instruction FBI 1  and a second forward branch instruction FBI 2 , wherein the first forward branch instruction FBI 1  points to a first forward target label FT 1  that is located between the second forward branch instruction FBI 2  and a second forward target label FT 2  to which the second forward branch instruction FBI 2  points. The first forward branch instruction FBI 1  is located immediately before an instruction sequence J and the second forward branch instruction FBI 2  is located immediately after the instruction sequence J. A sequence K of code is disposed immediately after the second forward branch instruction FBI 2  and immediately before the first target label FT 1 . An instruction sequence L is disposed immediately between the first target label FT 1  and the second target label FT 2 . 
       FIG. 12A  is a flow chart of a portion of the first system software SW. 2  and the second system software SW. 5  that in the generation of a third resultant code R. 3  replaces the forward overlap patterns of  FIG. 11  with a forward set of  FIG. 12C  and thereby remove the overlapping forward branches from the sequence of instructions  4000 - 4999  SEQ from the second resultant code R. 2 . A current line value CRNT and a last line value END are initialized in step  12 A. 02  wherein the current line value CRNT is equal to the value of the first line of code  4000  of the sequence of instructions  4000 - 4999  SEQ and the last line value END is set equal to the last line of code  4999  of the sequence of instructions  4000 - 4999  SEQ. In step  12 A. 04  the computer  2  determines if the current line value CRNT has been incremented by cycling through the loop of steps  12 A. 10  through  12 A. 22  to be made equal to or greater than the last line value END of  4999 . When the computer  2  determines in step  12 A. 04  that the current line value CRNT has been incremented to be equal to or greater than the last line value END, the computer  2  proceeds on to store the software code modified by execution of steps  12 A. 04  through  12 A. 22  as a third resultant code R. 3 , and proceeds from step  12 A. 06  to step  12 A. 08  and to perform alternate computational operations. 
     When the computer  2  determines in step  12 A. 04  that the code line value CRNT of the sequence of instructions  4000 - 4999  SEQ is less than the last line value END, the computer  2  proceeds on to step  12 A. 10  to determine if software code at line value CRNT provides a forward branch instruction. When the computer  2  determines in step  12 A. 10  that the software code at line value CRNT is not a forward branch instruction, the computer  2  proceeds onto step  12 A. 12  and to increment the current line value CRNT. The computer  2  proceeds from step  12 A. 12  to an additional execution of step  12 A. 04 . 
     Alternately, when the computer  2  determines in step  12 A. 10  that the software code at line value CRNT is a forward branch instruction, the computer  2  proceeds onto step  12 A. 14  and to seek a first instance of an overlapping additional forward branch instruction FBI 2 , or “OBB”, positioned between a forward branch instruction FBI 1  determined in the last instance of step  12 A. 10  and a first forward target label FT 1  as specified by the first forward branch instruction FBI 1 . When an overlapping second forward branch instruction FBI 22  is not found by the computer  2  within the sequence of instructions found between the first forward branch instruction FBI 1  and the first forward target label FT 1  in step  12 A. 16 , the computer  2  proceeds onto step  12 A. 12  and therefrom onto step  12 A. 04 . 
     When an overlapping forward branch instruction FBI 2  is found in step  12 A. 16 , the forward algorithm is applied in step  12 A. 18  as illustrated in  FIG. 12B . The computer  2  or  4  proceeds from step  12 A. 18  to step  12 A. 20  in the process of generating the third resultant code R. 3  and to update all pointers and references within the source program SW. 3  that have been altered by the modifications of the instruction sequence  4000 - 4999  SEQ in the most recent instance of step  12 A. 18 . 
       FIG. 12B  is a flow chart of a software-encoded application of the third optional aspect of the invented method that removes a forward instruction pattern from a second resultant R. 2  software and replaces the forward instruction pattern with a logically equivalent forward set in the third resultant code R. 3 . In step  12 B. 02  the second forward branch instruction FBI 2  is modified to point to the first forward target label FT 1  to which the first forward branch instruction FBI 1  also points. 
     In step  12 B. 04  the a new third resultant forward branch instruction R.FBI 3  is inserted between the first forward target label FT 1  and the sequence L, wherein the third resultant forward branch instruction R.FBI 3  directs the computer  2  or  4  to proceed directly on to the first forward target label FT 1  when the logic condition of Y 2  is TRUE. 
       FIG. 12C  is an illustration of the forward set as generated by the method of  FIG. 2B  as an element of the third resultant code R. 3 , wherein the first forward branch FB. 1  of the forward instruction pattern, a second resultant branch R.FB. 2  and a third resultant forward branch R.FB. 3  provide logic equivalent to the originating forward instruction pattern of  FIG. 11 . 
       FIG. 13  is a flow chart of a successive application of the first four aspects of the invented method to the sequential instructions  4000 - 4999  SEQ that are used to generate a final resultant code R. 3 . The source program SW. 3  is acquired by the computer  2  or the reconfigurable computer  4  in step  13 . 2  The first aspect of the invented method of  FIG. 6  is applied in step  13 . 4  to the entire instruction sequence  4000 - 4999  SEQ of the source program SW. 3  in an ascending order from instruction  4999  to instruction  4000  to generate a first resultant code R. 1 , whereby the first resultant code R. 1  is generated and all overlapping back branches of the source program SW. 3  are transformed within the first resultant code R. 1  into either nested branches or unrelated branches. 
     The third aspect of the invented method of  FIG. 10  and the fourth aspect of the invented method of  FIG. 12  are applied in step  13 . 6  to the entire instruction sequence  4000 - 4999  SEQ of the first resultant code R. 1  in an ascending order from instruction  4999  to instruction  4000  to generate a second resultant code R. 2 , whereby overlapping forward and back branches are transformed within the second resultant code R. 2  into either nested branches or unrelated branches. 
     The second aspect of the invented method of  FIG. 8  is applied in step  13 . 8  to the entire instruction sequence  4000 - 4999  SEQ of the second resultant code R. 2  in an descending order from instruction  4000  to instruction  4999  to generate a final resultant code R. 3 , whereby overlapping forward branches are transformed within the final resultant code R. 3  into either nested branches or unrelated branches. 
       FIG. 14  is a process chart of a derivation of final resultant code R. 3  and application of the final resultant code R. 3  by the computer  2 , the reconfigurable computer  4  and/or the network  3 . In step  14 . 2  is input into the computer  2 , the reconfigurable computer  4  and/or the network  3 . It is understood when the process of  FIG. 14  is applied by the network  3 , that the source program SW. 3  is isolated into portions and the portions are distributed among systems  2 ,  3 C &amp;  4  of the network  3 . When the process of  FIG. 14  is applied by the reconfigurable computer  4 , optional step  14 . 4  is applied wherein the RLC  4 A of the reconfigurable computer  4  may be configured or programmed to process the source program SW. 3 . The final resultant code R. 3  generated by the method of  FIG. 13  in step  14 . 6 . The final resultant code R. 3  is then input (if not already present within) the reconfigurable computer  4  in step  14 . 8 , and the final resultant code R. 3  is executed by the reconfigurable computer  4  with participation by the RLC  4 A in step  14 . 10 . 
     The foregoing disclosures and statements are illustrative only of the Present Invention, and are not intended to limit or define the scope of the Present Invention. The above description is intended to be illustrative, and not restrictive. Although the examples given include many specificities, they are intended as illustrative of only certain possible configurations or aspects of the Present Invention. The examples given should only be interpreted as illustrations of some of the preferred configurations or aspects of the Present Invention, and the full scope of the Present Invention should be determined by the appended claims and their legal equivalents. Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiments can be configured without departing from the scope and spirit of the Present Invention. Therefore, it is to be understood that the Present Invention may be practiced other than as specifically described herein. The scope of the present invention as disclosed and claimed should, therefore, be determined with reference to the knowledge of one skilled in the art and in light of the disclosures presented above.

Technology Classification (CPC): 6