Patent Abstract:
A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Full Description:
[0001]    This application claims the benefit of Korean patent application No. 96-62231, filed Dec. 6, 1996, which is hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a thin film transistor of an active matrix liquid crystal display device and a method of manufacturing the same, and, more particularly, to a thin film transistor having a double gate layer and a method of manufacturing the same.  
           [0004]    2. Discussion of the Related Art  
           [0005]    In general, a thin film transistor (TFT) using amorphous silicon has an advantage in that a thin film semiconductor layer is formed on a glass substrate by a low-temperature process, and no leakage current is generated in the OFF state due to a wide energy band gap and a high resistance of the thin film itself However, because the charge carrier mobility in the amorphous silicon of the thin film transistor is low, its current characteristic in the ON state is poor compared to a single-crystal or polycrystalline transistor. Moreover, the amorphous silicon thin film transistor does not employ a driving circuit on the same substrate.  
           [0006]    A thin film transistor using polysilicon has higher charge carrier mobility and lower resistance than a thin film transistor using amorphous silicon, thus driving a large current in the ON state and forming a driving circuit with pixels on the same substrate. However, because the polysilicon thin film transistor has a narrow energy band gap and numerous Si dangling bonds, a large leakage current is generated around the drain region.  
           [0007]    Therefore, a thin film transistor was developed having a LDD (lightly doped drain) region, or an offset region, to decrease the leakage current.  
           [0008]    [0008]FIG. 1 is a sectional view of a conventional TFT. A buffer oxide layer  13  is formed on a transparent insulating substrate  11 , and a semiconductor layer  15  is formed on a predetermined portion on the buffer oxide layer  13 . A gate oxide layer  17  is formed on a predetermined portion on the semiconductor layer  15 . A gate  19   a  is formed on a predetermined portion of the gate oxide layer  17 .  
           [0009]    The semiconductor layer  15  includes an active region  15   a  with no impurity doping, and an impurity region  15   b  where N type or P type impurities are highly doped to be used for the source and drain regions. The active region  15   a  consists of a channel region C 1  where a channel is formed under the gate  19   a , and an offset region O 1  between the channel region C 1  and an impurity region  15   b.    
           [0010]    An aluminum gate  19   a  is formed overlapping the channel region C 1  of the active region  15   a . Anode oxide layers  21  and  27  are formed on the surface of the gate  19   a.    
           [0011]    In the TFT described above, when a voltage is applied to the gate  19   a , a channel is formed in the offset region O 1  as well as in the channel region C 1  due to an electric field, thereby turning the TFT on. When no voltage is applied to the gate  19   a , no electric field is applied to the offset region O 1 , thereby preventing any leakage current.  
           [0012]    FIGS.  2 A- 2 D show the manufacturing process of the TFT. Referring to FIG. 2A, the buffer oxide layer  13  is formed on the transparent insulating substrate  11 . The semiconductor layer  15  is formed on the buffer oxide layer  13  by depositing polysilicon. The semiconductor layer  15  is patterned by a typical photolithography process to expose a predetermined region of the buffer oxide layer  13 .  
           [0013]    Referring to FIG. 2B, the gate oxide layer  17  is formed covering the buffer oxide layer  13  and the semiconductor layer  15 . A gate metal layer  19  is formed by depositing an anode-oxidative metal such as aluminum, and the surface of the gate metal layer  19  is anodized to form a first anode oxide layer  21 .  
           [0014]    Referring to FIG. 2C, a photoresist pattern  23  is formed on a portion of the first anode-oxide layer  21 . The first oxide layer  21  and the gate metal layer  19  are anisotropically etched using the photoresist pattern  23  as a mask. A part of the gate metal layer  19  that is not etched and removed becomes the gate  19   a . The second anode oxide layer  25  is formed by anodizing the lateral sides of the gate  19   a . The second anode-oxide layer  25  is anodized in a horizontal direction to define the offset region O 1 . In the anodizing process, large current flows to the gate  19   a  to speed up the anodizing of the gate  19   a . As a result, the second anode oxide layer  25  is porous.  
           [0015]    Referring to FIG. 2D, the gate oxide layer  17  is anisotropically etched using the photoresist layer  23  as a mask to expose a predetermined portion of the semiconductor layer  15  and the buffer oxide layer  13 . The photoresist pattern  23  is then eliminated. Next, a third anode-oxide layer  27  is formed between the lateral side of the gate  19   a  and the second anode-oxide layer  25 . Here, an electrolyte liquid makes contact with the lateral side of the gate  19   a  through the second porous anode-oxide layer  25  and therefore the third anode-oxide layer  27  is formed by anodizing the gate  19   a . The second anode-oxide layer  25  is etched away, while the first and third anode oxide layers  21  and  27 , which are denser than the second anode oxide layer  25 , remain during the etching process. The second anode oxide layer  25  is removed entirely. Thus, the third anode-oxide layer  27  remains on the lateral side of the gate  19   a . Thereafter, N type or P type impurities are highly doped into exposed portions of the semiconductor layer  15 , using the first anode oxide layer  21  and the gate oxide layer  17  as a mask, thus forming source and drain regions  15   b . Here, the remaining portion of the semiconductor layer  15  is the active region  15   a . In this active region  15   a , the portion overlapping the gate  19   a  becomes the channel region C 1 , while the portion between the impurity region  15   b  and the channel region C 1  is the offset region O 1 .  
           [0016]    As described above, in the conventional TFT the gate metal layer is patterned using the photoresist pattern  23  as a mask to form the gate  19   a , the lateral sides of the gate  19   a  are anodized at a high rate without eliminating the photoresist pattern in order to form a second porous anode-oxide layer  25  in a horizontal direction, the photoresist pattern  23  is eliminated, and the portion between the lateral side of the gate and the second anode-oxide layer  23  is anodized to form the third anode-oxide layer. The third anode oxide layer  27  defines the offset region O 1 .  
           [0017]    The conventional process for forming a TFT has certain drawbacks because it requires a complicated process to eliminate the lateral side of the gate  19   a  after the anodizing in the horizontal direction in order to define the offset region O 1 . Also, a hillock is generated due to the gate  19   a  consisting of A 1 .  
         SUMMARY OF THE INVENTION  
         [0018]    Accordingly, the present invention is directed to a thin film transistor and method of manufacturing the same that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.  
           [0019]    An object of the present invention is to provide a thin film transistor that does not have a hillock due to a gate.  
           [0020]    Another object of the present invention is to provide a method for manufacturing a thin film transistor which can reduce the number of the processes by facilitating the definition of the offset region.  
           [0021]    Additional features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0022]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in a first aspect of the present invention there is provided a thin film transistor including an insulating substrate, a semiconductor layer formed on the insulating substrate and having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a portion of the active region of the semiconductor layer defining a channel region, and a second gate metal layer formed on the first gate metal layer.  
           [0023]    In a second aspect of the present invention there is provided a method for manufacturing a thin film transistor, including the steps of forming a semiconductor layer on an insulating substrate, wherein the semiconductor layer has no impurity doping, depositing a gate insulating layer, a first gate metal layer and a second gate metal layer on the semiconductor layer, forming a photoresist pattern on a portion on the second gate metal layer, the photoresist pattern overlapping the portion of the semiconductor layer, and etching the first and second gate metal layers using the photoresist pattern as a mask to expose both sides of the first gate metal layer to form exposed portions of the first gate metal layer, wherein the second gate metal layer etches faster than the first gate metal layer.  
           [0024]    In a third aspect of the present invention there is provided a method of manufacturing a thin film transistor, including the steps of forming a semiconductor layer on an insulating substrate, depositing a gate insulating layer, a first gate metal layer and a second gate metal layer on the semiconductor layer, forming a photoresist pattern on a portion of the second gate metal layer, the photoresist pattern overlapping a predetermined portion of the semiconductor layer, etching the first and second gate metal layers using the photoresist pattern as a mask to expose both sides of the first gate metal layer to form an exposed portion of the first gate metal layer, wherein the second gate metal layer etches faster than the first gate metal layer, anodizing the exposed portion of the first gate metal layer to form spacers, removing the photoresist pattern, forming impurity regions by doping impurities into exposed portions of the semiconductor layer, forming an insulating interlayer, removing a portion of the insulating interlayer to form contact holes exposing the impurity regions, forming source and drain electrodes making contact with the impurity regions through the contact holes, forming a first protective layer on the insulating interlayer and the source and drain electrodes, forming a light shielding layer covering a portion excluding a pixel region on the first protective layer, forming a second protective layer on the first insulating layer and light shielding layer, removing a portion of the first and second protective layers to form a contact hole exposing the drain electrode, and forming a pixel electrode on the second protective layer of the pixel region in contact with the drain electrode through the contact hole.  
           [0025]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.  
         [0027]    In the drawings:  
         [0028]    [0028]FIG. 1 is a sectional view of a conventional thin film transistor;  
         [0029]    FIGS.  2 A- 2 D illustrate a conventional process for manufacturing the thin film transistor of FIG. 1;  
         [0030]    [0030]FIG. 3 is a sectional view of a thin film transistor of the present invention;  
         [0031]    FIGS.  4 A- 4 D illustrate the process steps for the fabrication of the thin film transistor of FIG. 3; and  
         [0032]    FIGS.  5 A- 5 C illustrate the subsequent process steps performed after the process steps of FIGS.  4 A- 4 D. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0034]    [0034]FIG. 3 shows a sectional view of a TFT according to the present invention. A buffer oxide layer  33  of SiO 2  is formed on a transparent insulating layer  31 , and a semiconductor layer  35  is formed on a predetermined portion of the buffer oxide layer  33 .  
         [0035]    The semiconductor layer  35  is formed by depositing polysilicon or amorphous silicon to a thickness between 500 and 500 Å, and patterning it into a predetermined shape. The semiconductor layer  35  includes of an active region  35   a  having a channel region C 2  and an offset region O 2  where impurities are not doped, and an impurity region  35   b  used for source and drain regions where N type or P type impurities are highly doped. The channel region C 2  is positioned at the center of the active region  35   a . The offset region O 2  is formed between the channel region C 2  and the impurity region  35   b.    
         [0036]    A gate oxide layer  37  is formed on the active region  35   a  on the semiconductor layer  35  by depositing SiO 2  to a thickness of between 500 and 1500 Å.  
         [0037]    A double metal-layered gate  42  comprising first and second gate metal layers  39  and  41  is formed on the gate oxide layer  37  over the channel region C 2 . A spacer  45  is formed on both sides of the first gate metal layer  39  of the gate over the channel region C 2 . Here, the first gate metal layer  39  is formed over the channel region C 2  by depositing aluminum to a thickness of between 500 and 4000 Å. The spacer  45 , formed on both sides of the first gate metal layer  39  through an anodizing process, has a width of between 0.1 and 1 μm. The second gate metal layer  41  is formed on the first gate metal layer  39  by depositing molybdenum to a thickness of between 500 and 2000 Å, and is used as a barrier to the generation of a hillock due to the diffusion of the aluminum of the first gate metal layer  37  to another insulating layer formed on the first gate metal layer  39 .  
         [0038]    In the TFT above, since the first gate metal layer  39  made of aluminum is surrounded by the second gate metal layer  41  and the spacer  45 , the hillock cannot be generated. Also, the offset region O 1  is easily defined by the spacer  45 .  
         [0039]    FIGS.  4 A- 4 D illustrate the manufacturing process of the thin film transistor of FIG. 3.  
         [0040]    As illustrated in FIG. 4A, the buffer oxide layer  33  and the semiconductor layer  35  are sequentially formed on a transparent insulating substrate  31 . Here, the buffer oxide layer  33  is formed by depositing SiO 2  by chemical vapor deposition (CVD). The semiconductor layer  35  is formed by depositing polysilicon or amorphous silicon to a thickness of between 500 and 1500 Å and does not contain impurities therein. When forming the semiconductor layer  35  of polysilicon, the polysilicon is deposited by CVD, or formed by depositing amorphous silicon and then annealing by a laser to crystallize the amorphous silicon into polysilicon. The semiconductor layer  35  is patterned by a typical photolithographic process to expose a portion of the buffer oxide layer  33 .  
         [0041]    As illustrated in FIG. 4B, the gate oxide layer  37  is formed by depositing SiO 2  through CVD to cover the buffer oxide layer  33  and the semiconductor layer  35 . The a first and second gate metal layers  39  and  41  are formed on the gate oxide layer  37  by sequentially depositing aluminum and molybdenum. Here, the first and second gate metal layers  39  and  41  are between 500 and 4000 Å thick and between 500 and 2000 Å thick, respectively.  
         [0042]    As illustrated in FIG. 4C, a photoresist pattern  43  is formed on the second gate metal layer  41 . The second and first gate metal layers  41  and  39  are sequentially etched to expose the gate oxide layer  37 , using the photoresist pattern  43  as a mask. The first and second gate metal layers  39  and  41  are etched for between 1 and 3 minutes with an etchant containing the mixture solution of H 3 PO 4 , CH 3 COOH and HNO 3 . Here, the etchant can etch the molybdenum in the second gate metal layer  41  one to ten times faster than the aluminum in the first gate metal layer  39 . Therefore, the second gate metal layer  41  is over-etched to expose both sides of the first gate metal layer  39  by 0.1 to 2 μm. The lateral side of the second gate metal layer  41  is etched perpendicularly or at a slope. The gate oxide layer  37  is dry-etched to expose the active layer  35  and the buffer oxide layer  33  using the photoresist pattern  43  as a mask.  
         [0043]    As illustrated in FIG. 4D, the exposed portion of the first gate metal layer  39  is anodized, forming the spacer  45 . Here, the remaining first and second gate metal layers  39  and  41  are the double metal-layered gate  42 . Thereafter, the photoresist pattern  43  is eliminated. Even though the spacer  45  is formed using the photoresist pattern  43  in the above description, the spacer  45  can also be formed without the photoresist pattern  43 .  
         [0044]    N type impurities such as phosphorus, or P type impurities such as boron are injected by ion doping to form the high impurity regions  35   b  used for source and drain regions. The remaining portion of the semiconductor layer  35  is the active region  35   a . In the active region  35   a , the portion overlapped by the first gate metal layer  39  is the channel region C 2  and the portion under the spacer  45  is an offset region O 2 . Consequently, the offset region O 2  is positioned between the impurity region  35   b  and the channel region C 2 .  
         [0045]    FIGS.  5 A- 5 C illustrate process steps following the steps of FIGS.  4 A- 4 D. As illustrated in FIG. 5A, an insulating interlayer  47  is formed on the resultant structure as shown in FIG. 4D by depositing silicon oxide SiO 2  using CVD. A predetermined portion of the insulating interlayer  47  is eliminated by a photolithographic process to form a first contact hole that exposes the impurity region  35   b . Conductive metal such as Al, Ti or Cr is deposited and fills up the first contact hole to provide a contact with the impurity region  35   b . A deposited conductive metal layer is patterned to form the source and drain electrodes  51  and  53 . The impurity regions  35   b  making contact with the source and drain electrodes  51  and  53  are the source and drain, respectively.  
         [0046]    As illustrated in FIG. 5B, a first protective layer  55  is formed on the insulating interlayer  47  and the source and drain electrodes  51  and  53  by depositing an inorganic insulating substance such as SiO 2  or Si 3 N 4 , or by coating them with an organic insulating layer including a material having a low dielectric constant, such as BCB (Benzo Cyclo Butene), Polyimide with added Fluorine, PCB (Perfluoro Cyclo Butane), or FPAE (Fluoro Poly Allyl Ether). A light shielding layer  57  is formed on the first protective layer  55  by coating it with an opaque insulating resin, and then exposing and developing the opaque layer. The light shielding layer  57  covers the region excluding the pixel region (not shown).  
         [0047]    As illustrated in FIG. 5C, a second protective layer  59  having the same insulating material as the first protective layer  59  is formed on the first insulating layer  55  and the light shielding layer  57 . Predetermined portions of the first and second protective layers  55  and  59  are eliminated in a photolithographic process to form a second contact hole that exposes the drain electrode  53 . A transparent conductive material such as ITO or SnO 2  is deposited on the second protective layer  59  by sputtering to form a contact with the drain electrode  53  through the second contact hole. The deposited transparent conductive material is patterned to form a pixel electrode  61  in contact with the drain electrode  53 .  
         [0048]    As described above, the thin film transistor of the present invention is fabricated as follows. The first gate metal layer  39  of aluminum and the second gate metal layer  41  of molybdenum are sequentially deposited onto the gate oxide layer  37 . The first and second gate metal layers  39  and  41  are sequentially etched with an etching solution that etches the second gate metal layer faster than the first gate metal layer  39 , using the photoresist pattern  43  as a mask, so that a portion of the first gate metal layer  39  is exposed to a predetermined width. Thereafter, the exposed portion of the first gate metal layer  39  is anode-oxidized to form a spacer  45 .  
         [0049]    Therefore, the present invention can prevent the generation of the hillock in the first gate metal layer  39  because of the second gate metal layer  41 , and the offset region O 1  is easily defined by the spacer  45  formed on both sides of the first gate metal layer  39 , so that the number of process steps is reduced.  
         [0050]    While the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Technology Classification (CPC): 7