Patent Abstract:
A method and apparatus for fast signal processing is presented. Increase of traffic over data communication networks requires increase of data processing speed. The proposed method is faster than the conventional technique, because it uses less operations of multiplications and additions. The method implements a flexible algorithm architecture based on an elementary cell which is used for both direct and inverse transforms. The method can be implemented for fast analysis and synthesis of different signal types; for fast multiplexing and demultiplexing; and for channel estimation and modeling. The flexible architecture allows: 1) conducting signal analysis according to a certain criterion, and operating on the whole signal or it&#39;s part; 2) modifying multiplexed datastream number “on the fly”, splitting and merging groups of datastreams from different sources; 3) splitting a communication channel into a set of sub-channels of different bandwidth, organizing data communication in particular subchannels that satisfy certain requirement.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     Related U.S. Application Data 
       [0001]    This is a division of application Ser. No. 13/090,608, filed on Apr. 21, 2011 
       Foreign Application Priority Data 
       [0002]    May 03, 2010 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0003]    Not Applicable 
       REFERENCE TO SEQUENCE LISTING, A TABLE, OR A COMPUTER PROGRAM LISTING COMPACT DISK APPENDIX 
       [0004]    Not Applicable 
       BACKGROUND OF THE INVENTION 
       [0005]    Traffic over data communication networks is increasing constantly. This fact requires data communication systems to increase data processing speed. Conventional signal processing techniques often fail to satisfy new requirements. The present invention is in the technical field of signal processing. More particularly, the present invention is in the technical field of signal analysis/synthesis, channel estimation/modeling, and data multiplexing/demultiplexing. The proposed signal processing method uses less operations of multiplications and additions, than the conventional signal processing technique does. Hence it is faster than the conventional technique such as a Fast Fourier Transform (FFT). The proposed method uses the same algorithm for direct and inverse transforms. Hence it requires less system resources compare to the conventional technique such as a pair of transforms: Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT). The proposed method uses a flexible algorithm architecture based on an elementary cell. This fact allows to adapt the algorithm structure to capabilities of platform it is deployed on. Also the flexible algorithm architecture allows to modify the algorithm structure “on the fly” without interrupting the processing. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    The present invention is a method and apparatus for fast signal analysis/synthesis, channel estimation/modeling, and data multiplexing/demultiplexing. The proposed method can be implemented for fast analysis and synthesis of a one-dimensional (1D) signal, such as an audio signal, a voice, a control sequence; a two-dimensional (2D) signal, such as a grayscale image; a three dimensional signal (3D), such as a static 3D mesh or a color image; a four dimensional signal, such as a dynamic 3D mesh or a color video signal; and a five dimensional signal such as a stereo color video signal. The flexible algorithm architecture allows to conduct a signal analysis according to a certain criterion. Also the flexible algorithm architecture allows to operate on the whole signal or it&#39;s part. The proposed method can be implemented for fast multiplexing and demultiplexing of multiple datastreams. The flexible algorithm architecture allows to modify datastream number “on the fly” without interrupting the processing. Also the flexible algorithm architecture allows split and merge groups of datastreams from different sources. For example, the proposed method can be used to implement a multiple user access to a single communication channel. The proposed method can be implemented for communication channel estimation and modeling. The flexible algorithm architecture allows to split a communication channel into a set of subchannels of different bandwidth. Also the flexible algorithm architecture allows organizing data communication in particular subchannels that satisfy the requirement on Quality of Service (QoS). The proposed method is used in a system implementing a method of Data Transmission Oriented on the Object, Communication Media, Agents, and State of Communication Systems described in [1]. In that system, the proposed method is implemented for data analysis/synthesis, channel estimation/modeling, and datastream multiplexing/demultiplexing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0007]      FIG. 5  are the elementary cells W 2  and V 2 ; 
           [0008]      FIG. 6  is the Fast Fourier Transform (FFT) butterfly; 
           [0009]      FIG. 7  is the scheme of the third level of the analysis-synthesis of the digital signal x[n]; 
           [0010]      FIG. 8  is the scheme of the W 4  cell as a combination of four elementary cells W 2 ; 
           [0011]      FIG. 9  is the W 4  cell structure; 
           [0012]      FIG. 10  is the W 8  cell structure; 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    Referring now to the invention in more detail. 
       The Elementary Cell W 2    
       [0014]    The core of the fast signal processing method is an elementary cell W 2    110  and an elementary cell V 2    130 . They are shown on  FIG. 5 . 
         [0015]    The elementary cell W 2    110  consists of an inverter  112 , an adder  114 , an adder  116 , a multiplier  118 , a multiplier  120 , and a block  122  generating a constant 
         [0000]    
       
         
           
             
               1 
               
                 2 
               
             
             . 
           
         
       
     
         [0016]    The elementary cell V 2    130  consists of the inverter  112 , the adder  114 , and the adder  116 . 
         [0017]    In other view, the elementary cell W 2    110  consists of the elementary cell V 2    130 , a multiplier  118 , a multiplier  118 , and a block  122  generating a constant 
         [0000]    
       
         
           
             
               1 
               
                 2 
               
             
             . 
           
         
       
     
         [0018]    The elementary cell W 2    110  possesses a particular property which allows it to be used both for analysis and synthesis. 
         [0019]    In case the elementary cell W 2    110  is used for analysis of a digital signal x[n], odd samples of the signal x[2n−1] inputs to a pin x 1  and even samples of the signal x[2n] inputs to a pin x 2 . 
         [0020]    In case the elementary cell W 2    110  is used for analysis of the digital signal x[n], the pin y 1  outputs the approximation signal 
         [0000]    
       
         
           
             
               
                 A 
                  
                 
                   [ 
                   k 
                   ] 
                 
               
               = 
               
                 
                   1 
                   
                     2 
                   
                 
                  
                 
                   ( 
                   
                     
                       x 
                        
                       
                         [ 
                         
                           
                             2 
                              
                             n 
                           
                           - 
                           1 
                         
                         ] 
                       
                     
                     + 
                     
                       x 
                        
                       
                         [ 
                         
                           2 
                            
                           n 
                         
                         ] 
                       
                     
                   
                   ) 
                 
               
             
             , 
           
         
       
     
         [0000]    and the pin y 2  outputs the detail signal 
         [0000]    
       
         
           
             
               D 
                
               
                 [ 
                 k 
                 ] 
               
             
             = 
             
               
                 1 
                 
                   2 
                 
               
                
               
                 
                   ( 
                   
                     
                       x 
                        
                       
                         [ 
                         
                           
                             2 
                              
                             n 
                           
                           - 
                           1 
                         
                         ] 
                       
                     
                     - 
                     
                       x 
                        
                       
                         [ 
                         
                           2 
                            
                           n 
                         
                         ] 
                       
                     
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
         [0021]    In case the elementary cell W 2    110  is used for synthesis of the digital signal x[n], the approximation signal A[k] inputs to the pin x 1  and the detail signal D[k] inputs to the pin x 2 . 
         [0022]    In case the elementary cell W 2    110  is used for synthesis of the digital signal x[n], the pin y 1  outputs the odd samples of the signal 
         [0000]    
       
         
           
             
               
                 x 
                  
                 
                   [ 
                   
                     
                       2 
                        
                       n 
                     
                     - 
                     1 
                   
                   ] 
                 
               
               = 
               
                 
                   1 
                   
                     2 
                   
                 
                  
                 
                   ( 
                   
                     
                       A 
                        
                       
                         [ 
                         k 
                         ] 
                       
                     
                     + 
                     
                       D 
                        
                       
                         [ 
                         k 
                         ] 
                       
                     
                   
                   ) 
                 
               
             
             , 
           
         
       
     
         [0000]    and the pin y 2  outputs the even samples of the signal 
         [0000]    
       
         
           
             
               x 
                
               
                 [ 
                 
                   2 
                    
                   n 
                 
                 ] 
               
             
             = 
             
               
                 1 
                 
                   2 
                 
               
                
               
                 
                   ( 
                   
                     
                       A 
                        
                       
                         [ 
                         k 
                         ] 
                       
                     
                     - 
                     
                       D 
                        
                       
                         [ 
                         k 
                         ] 
                       
                     
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
         [0023]    The assignments for Input/Output pins are presented in Table 1. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Input/Output pin assignment of the fast elementary cell 
               
             
          
           
               
                 Input 
                 Analysis 
                 Synthesis 
                 Output 
                 Analysis 
                 Synthesis 
               
               
                   
               
               
                 x 1   
                 x[2n − 1] 
                 A[k] 
                 y 1   
                 A[k] 
                 x[2n − 1] 
               
               
                 x 2   
                 x[2n] 
                 D[k] 
                 y 2   
                 D[k] 
                 x[2n] 
               
               
                   
               
             
          
         
       
     
         [0024]    Nowadays, the most common algorithm in Digital Signal Processing (DSP) is the Fast Fourier Transform (FFT).  FIG. 6  shows is the two-point Fast Fourier Transform (FFT), or 2-FFT decimation-in-time butterfly. 
         [0025]    The first advantage of the elementary cell W 2    110  over 2-FFT is that the elementary cell W 2    110  can be used for both data analysis and data synthesis. 
         [0026]    The second advantage of the elementary cell W 2    110  is that it&#39;s complexity is less than the one of the 2-FFT. The results are presented in Table 2. The complexity of an algorithm is measured by quantity of real adders (⊕), real multipliers (         ) and real inverters (⊖). Use of the elementary cell W 2    110  and the elementary cell V 2    130  does not change the nature of input numbers, i.e. the real input numbers stay real. However, output of 2-FFT butterfly is always represented by complex numbers. Since, the 2-FFT butterly is applied more than ones, the input of the next stage 2-FFT operation will be complex, and there is no reason to consider the real input numbers for 2-FFT. Therefore the slot, corresponding to the number of operations on real input numbers, is empty in Table 2. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Complexity of W 2 , V 2  cells and 2-FFT 
               
               
                 butterfly in terms of real operations 
               
             
          
           
               
                 Input numbers 
                 W 2   
                 V 2   
                 2-FFT 
               
               
                   
               
               
                 Real 
                 2 ⊕ + 2            + 1⊖ 
                 2 ⊕ + 1⊖ 
                 n/a 
               
               
                 Complex 
                 4 ⊕ + 4            + 2⊖ 
                 4 ⊕ + 2⊖ 
                 6 ⊕ + 4            + 3⊖ 
               
               
                   
               
             
          
         
       
     
         [0027]    The elementary cell W 2    110  outputs the approximation and detail features of the input signal. One might decide to continue the procedure by analysing the features of features etc. The decision of whether to proceed with further analysis is based on certain criteria. Signal analysis is stopped upon a certain parameter of feature segment is reached.  FIG. 7  shows the schemes of the third level analysis-synthesis of the one-dimensional data object x[n]. 
       The W 4  and W 8  Cells 
       [0028]    The elementary cell W 2  is used to build processing cells of higher orders, such as W 4  and W 8  cells. The scheme on  FIG. 7   a ) is purely based on the elementary cells W 2    110 . The third level analysis scheme consists of seven elementary cells W 2  ( 144 ,  150 ,  152 ,  162 ,  164 ,  166 ,  168 ), and seven shift registers ( 142 ,  146 ,  148 ,  154 ,  156 ,  158 ,  160 ). The shift register  140 , used in the analysis scheme, outputs two datastreams. The first datastream consists of the odd samples z 2n−1  of the input datastream z. The second datastream consists of the even samples z 2n  of the input datastream z. The third level synthesis scheme consists of seven elementary cells W 2  ( 172 ,  174 ,  176 ,  178 ,  200 ,  202 ,  214 ), and seven shift registers ( 184 ,  186 ,  188 ,  190 ,  206 ,  208 ,  212 ). The shift register  210 , used in the synthesis scheme, inputs two datastreams. The first datastream consists of the odd samples z 2n−1  of the output datastream z. The second datastream consists of the even samples z 2n  of the output datastream z. 
         [0029]    In case a computational platform possesses enough resources, the computational speed of the analysis-synthesis can be increased by applying parallel computing techniques instead of serial ones. The scheme on  FIG. 7   b ) is based on the combination of the elementary cells W 2    110  and W 4  cells. The third level analysis scheme consists of one cell  224 , four elementary cells W 2  ( 162 ,  164 ,  166 ,  168 ), a four stage shift register  222 , and four shift registers of type  140  ( 154 ,  156 ,  158 ,  160 ). The four stage shift register  220 , used in the analysis scheme, outputs four datastreams. The four stage shift register  220  serves as a serial-to-parallel converter. The third level synthesis scheme consists of one W 4  cell  226 , four elementary cells W 2  ( 172 ,  174 ,  176 ,  178 ), four shift registers of type  210  ( 184 ,  186 ,  188 ,  190 ), and a four stage shift register  230 . The four stage shift register  230 , used in the synthesis scheme, inputs four datastreams. The four stage shift register  230  serves as a parallel-to-serial converter. 
         [0030]    In case a computational platform possesses even more resources, the computational speed of the analysis-synthesis can be increased even more. The scheme on  FIG. 7   c ) is based on W 8  cells. The third level analysis scheme consists of one W 8  cell  244 , and an eight stage shift register  242 . The eight stage shift register  240 , used in the analysis scheme, outputs eight datastreams. The four stage shift register  240  serves as a serial-to-parallel converter. The third level synthesis scheme consists of one W 8  cell  246 , and an eight stage shift register  248 . The eight stage shift register  250 , used in the synthesis scheme, inputs eight datastreams. The eight stage shift register  250  serves as a parallel-to-serial converter. 
         [0031]      FIG. 8  shows the scheme of the W 4  cell as a combination of four elementary cells W 2 . 
         [0032]    The W 4  cell can be employed for analysis-synthesis of two-dimensional data object, or image. During analysis the W 4  cell transforms four image pixels (X[2n−1,2m−1], X[2n−1, 2m], X[ 2 n, 2m−1], X[2n, 2m]) into an approximation (A[n,m]) coefficient, and three detail coefficients: horizontal (H[n,m]), vertical (V[n,m]) and diagonal (D[n,m]). During synthesis the W 4  cell transforms the approximation (A[n,m]) coefficient, and three detail coefficients: horizontal (H[n,m]), vertical (V[n,m]) and diagonal (D[n,m]) into four image pixels (X[2n−1, 2m−1], X[2n−1, 2m],X[2n, 2m−1], X[2n, 2m]). Where n=1 . . . N, m=1 . . . M, N×M is the image size. The assignments for Input/Output pins are presented in Table 3 for both cases of use the two-dimensional elementary cell in image analysis and synthesis. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 Input/Output pin assignment of the 2D fast elementary cell 
               
             
          
           
               
                 Input 
                 Analysis 
                 Synthesis 
                 Output 
                 Analysis 
                 Synthesis 
               
               
                   
               
               
                 x 1   
                 X[2n − 1, 2m − 1] 
                 A[n, m] 
                 y 1   
                 A[n, m] 
                 X[2n − 1, 2m − 1] 
               
               
                 x 2   
                 X[2n − 1, 2m] 
                 H[n, m] 
                 y 2   
                 H[n, m] 
                 X[2n − 1, 2m] 
               
               
                 x 3   
                 X[2n, 2m −1] 
                 V[n, m] 
                 y 3   
                 V[n, m] 
                 X[2n, 2m − 1] 
               
               
                 x 4   
                 X[2n, 2m] 
                 D[n, m] 
                 y 4   
                 D[n, m] 
                 X[2n, 2m] 
               
               
                   
               
             
          
         
       
     
         [0033]      FIG. 9  shows the structure of the W 4  and V 4  cells as a combination inverters, adders, multipliers, and blocks generating a constant ½. Complexities W 4  and V 4  cells are presented in 4 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 Complexity of W 4 , V 4  cells in terms of real operations 
               
             
          
           
               
                   
                 Input numbers 
                 W 4   
                 V 4   
               
               
                   
                   
               
               
                   
                 Real 
                 10 ⊕ + 4            + 3⊖ 
                 10 ⊕ + 3⊖ 
               
               
                   
                 Complex 
                 20 ⊕ + 8            + 10⊖ 
                 20 ⊕ + 6⊖ 
               
               
                   
                   
               
             
          
         
       
     
         [0034]    An operation of multiplication by ½ can be replaced by the shift operation. In that case no multiplication operations required in W 4 . 
         [0035]      FIG. 10  shows the structure of the W 8  cell as a combination of the W 2  cells. 
         [0000]    The W N  cell (N=2 n , n ∈ Z) 
         [0036]    Generally, the W N  cell (N=2 n , n ∈ Z) can be build. It will be able to operate on data points simultaneously. An implementation of the W N  cell is limited by computational platform resources. 
         [0037]    The complexity of W N  cell (N=2 n , n ∈ Z) n comparison with the complexity of the N-point (FFT) is presented in Table 5. 
         [0038]    The elementary cell W 2    110  can be envisioned as the elementary cell V 2    114  whose output is multiplied by 
         [0000]    
       
         
           
             
               1 
               
                 2 
               
             
             . 
           
         
       
     
         [0000]    By analogy, the W N  can be envisioned as the V N  whose output is multiplied by 
         [0000]    
       
         
           
             
               
                 
                   ( 
                   
                     1 
                     
                       2 
                     
                   
                   ) 
                 
                 d 
               
               = 
               
                 2 
                 
                   - 
                   
                     d 
                     2 
                   
                 
               
             
             , 
           
         
       
     
         [0000]    where d=log 2 N. In case d=2k is even, the multiplier 
         [0000]    
       
         
           
             
               2 
               
                 - 
                 
                   d 
                   2 
                 
               
             
             = 
             
               2 
               
                 - 
                 k 
               
             
           
         
       
     
         [0000]    can be replaced by the shift register. In case d=2k+1 is odd, the multiplier can be envisioned as the two multipliers 
         [0000]    
       
         
           
             
               2 
               
                 - 
                 
                   
                     
                       2 
                        
                       k 
                     
                     + 
                     1 
                   
                   2 
                 
               
             
             = 
             
               
                 2 
                 
                   - 
                   k 
                 
               
               · 
               
                 
                   1 
                   
                     2 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    Multiplication by 2 −k  can be replaced by the shift register, however multiplication by 
         [0000]    
       
         
           
             1 
             
               2 
             
           
         
       
     
         [0000]    should be implemented. Totally N multipliers by 
         [0000]    
       
         
           
             1 
             
               2 
             
           
         
       
     
         [0000]    are required for W N  in case d=Log 2 N is odd. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                 Complexity of the N-point FWPT vs. the N-point FFT in terms 
               
               
                 of real operations 
               
             
          
           
               
                 Input 
                   
                   
               
               
                 numbers 
                 W N   
                 FFT 
               
               
                   
               
               
                 Real 
                 
                   
                     
                       
                         
                           
                             N 
                             2 
                           
                            
                           
                             log 
                             2 
                           
                            
                           
                             N 
                             ( 
                             
                               2 
                               ⊕ 
                               
                                 
                                   + 
                                   1 
                                 
                                 ⊖ 
                               
                             
                             ) 
                           
                         
                         + 
                         
                           βN 
                           ⊗ 
                         
                       
                     
                   
                 
                 n/a 
               
               
                   
               
               
                 Complex 
                 
                   
                     
                       
                         
                           
                             N 
                             2 
                           
                            
                           
                             log 
                             2 
                           
                            
                           
                             N 
                             ( 
                             
                               4 
                               ⊕ 
                               
                                 
                                   + 
                                   2 
                                 
                                 ⊖ 
                               
                             
                             ) 
                           
                         
                         + 
                         
                           2 
                            
                           
                             βN 
                             ⊗ 
                           
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         
                           N 
                           2 
                         
                          
                         
                           log 
                           2 
                         
                          
                         
                           N 
                            
                           
                             ( 
                             
                               6 
                               ⊕ 
                               
                                 
                                   
                                     + 
                                     4 
                                   
                                   ⊗ 
                                   
                                     + 
                                     3 
                                   
                                 
                                 ⊖ 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                   
               
               
                   
                 
                   
                     
                       where 
                     
                   
                   
                     
                       
                         β 
                         = 
                         
                           { 
                           
                             
                               
                                 0 
                               
                               
                                 
                                   
                                     if 
                                      
                                     
                                         
                                     
                                      
                                     d 
                                   
                                   = 
                                   
                                     
                                       log 
                                       2 
                                     
                                      
                                     N 
                                      
                                     
                                         
                                     
                                      
                                     is 
                                      
                                     
                                         
                                     
                                      
                                     even 
                                   
                                 
                               
                             
                             
                               
                                 1 
                               
                               
                                 
                                   
                                     if 
                                      
                                     
                                         
                                     
                                      
                                     d 
                                   
                                   = 
                                   
                                     
                                       log 
                                       2 
                                     
                                      
                                     N 
                                      
                                     
                                         
                                     
                                      
                                     is 
                                      
                                     
                                         
                                     
                                      
                                     odd 
                                   
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Spectral 
                        
                       
                           
                       
                        
                       Efficiency 
                     
                     = 
                     
                       
                         Total 
                          
                         
                             
                         
                          
                         Object 
                          
                         
                             
                         
                          
                         Bits 
                       
                       
                         Transmitted 
                          
                         
                             
                         
                          
                         Symbols 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     Complexity 
                     = 
                     
                       
                         Total 
                          
                         
                             
                         
                          
                         Processing 
                          
                         
                             
                         
                          
                         Operations 
                       
                       
                         Total 
                          
                         
                             
                         
                          
                         Object 
                          
                         
                             
                         
                          
                         Bits 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     Total 
                      
                     
                         
                     
                      
                     Object 
                      
                     
                         
                     
                      
                     Bits 
                   
                   = 
                   
                     
                       N 
                       · 
                       M 
                       · 
                       bit 
                     
                      
                     
                       - 
                     
                      
                     per 
                      
                     
                       - 
                     
                      
                     
                       pixel 
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0039]    (1) 
         [0040]    (2). 
         [0041]    Same W N  cell can be implemented for both multiplexing and demultiplexing of N=2 n  (n ∈ Z) datastreams. For multiplexing of N datastreams they should be applied to the inputs of the W N  cell. Outputs of the W N  cell are connected to the shift register of order N. Shift register  250  represents an example of the shift register of the order 8. The shift register of order N outputs a serial datastream. For demultiplexing, the serial datastream is applied to the input of the shift register of order N. Shift register  240  represents an example of the shift register of the order 8. The parallel outputs of the shift register of order N are connected to the inputs of W N  cell. The N outputs of the W N  cell represent N demultiplexed datastreams. 
         [0042]    The W N  cell based multiplexing-demultiplexing can be implemented for communication channel estimation and modeling. N pilot signals multiplexed and sent over a communication channel allow to estimate a channel profile. According to that profile, the channel can be divided into subchannels of different bandwidth. Efficient data communication can be organized in particular subchannels that satisfy the requirement on Quality of Service (QoS). 
         [0043]    The invention can be implemented in a form of software, firmware running on computing devices or a hardware. 
         [0044]    While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. 
       References 
       [0000]    
       
         [1] M. Sabelkin, “Method and apparatus for data transmission oriented on the object, communication media, agents, and state of communication systems,” patent application Ser. No. 13/090,608, filed on Apr. 21, 2011.

Technology Classification (CPC): 7