Patent Abstract:
A comparator detects rising transitions of an input waveform and another comparator detects falling transitions. Each comparator detects their respective transition with a different threshold voltage. The outputs of these comparators are multiplexed into the clock input of a flip-flop. The flip-flop&#39;s inverted output is connected through a time delay to the input of the flip-flop to form a toggling configuration. The output of the time delay is also connected to the select input of a multiplexer that controls the multiplexer to multiplex the outputs of the two comparators into the clock input of the flip-flop. The threshold voltages chosen for the two comparators are chosen to be in the center of the incident edges of the distorted signal of a source-terminated transmission line. The time delay is chosen to be longer than the difference between the arrival of the incident wave and the arrival of the first reflected wave.

Full Description:
FIELD OF THE INVENTION 
     This invention relates generally to logic analyzer probes and more particularly to a circuit and method for detecting incident edges on a source terminated transmission line. 
     BACKGROUND OF THE INVENTION 
     Several techniques exist for interfacing integrated circuits and other digital electronic devices with one another in high-performance, transmission line environments. Some of these use load termination to eliminate unwanted signal reflections that occur because of impedance mismatches along the transmission line. Standard interfaces such as GTL (Gunning Transceiver Logic) and PECL commonly use this kind of transmission. Another technique that offers some advantages over this accepted method of termination is the source-terminated driver method. A source-terminated line does not use load termination. Instead, a source-terminated line relies upon reflections off an unterminated end-of-line to reach a valid voltage level and then terminates the reflected waves back at the source. 
     Source-terminated lines and busses may be difficult to probe because the electrical signals can appear distorted if viewed or probed at a location other than the receiving end of the bus. This distortion is caused by the separation between the incident and reflected waves of logic transition traveling on the line. This distortion can also cause glitches and timing uncertainty in the detected version of the probed signal&#39;s logic transitions. 
     Accordingly, there is a need in the art for a probe circuit that can reliably detect the incident wave of a logic transition on a source-terminated bus. By detecting the incident wave and ignoring any reflections, the timing of the logic transition can be measured with greater certainty than detecting both the incident wave and possibly some reflected waves. Furthermore, detecting just the incident wave prevents reflected waves from possibly being detected as glitches on the line. 
     SUMMARY OF THE INVENTION 
     A preferred embodiment of the invention provides a means of detecting the state of a source terminated line when not probing the line at the receiving end. The invention may be tuned to different logic levels, propagation delays, and is capable of separating minor reflections from true line glitches. 
     The present invention includes two comparators. One comparator detects rising transitions of the input waveform and one comparator detects falling transitions. Each comparator detects their respective transition with a different threshold voltage. The outputs of these comparators are multiplexed into the clock input of a flip-flop. The flip-flop&#39;s inverted output is connected through a time delay to the input of the flip-flop to form a toggling configuration. The output of the time delay is also connected to the select input of a multiplexer to control the multiplexer to multiplex the outputs of the two comparators into the clock input of the flip-flop. In a preferred embodiment the threshold voltages chosen for the two comparators are chosen to be in the center of the incident edges of the distorted signal. The time delay is chosen to be longer than the difference between the arrival of the incident wave and the arrival of the first reflected wave. 
     Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of an exemplary source-terminated line being probed. 
     FIG. 2 is an exemplary plot of voltage versus time on a source-terminated line as seen at a probe point. 
     FIG. 3 is schematic diagram of the incident-edge detection circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a schematic diagram of an exemplary source-terminated line being probed. Driver  1002  drives transmission line  1006  with a source impedance  1004 . Source impedance  1004  may be inherent in driver  1002  or it may be a separate component. Receiver  1008  receives the signal transmission line  1006  that is driven by driver  1002 . The input of probe circuit  1010  is connected to transmission line  1010  at a propagation delay of ΔT from the receiving end of transmission line  1010 . 
     FIG. 2 is an exemplary plot of voltage versus time on a source-terminated line as seen at a probe point. As can be seen, the voltage at the probe point starts at or around V OL . Then, some time after driver  1002  begins driving a low-to-high transition, the rising incident edge arrives at the probe point. Note that after the incident edge has passed the probe point, the voltage on the line as seen by the probe may not be a valid logic level. The voltage as seen by the probe can be too high to be a valid logic low, and too low to be a valid logic high. Later, after the incident wave has propagated to, and reflected off, the end of the transmission line  1006  and the reflected wave has propagated back to the probe point (a delay of 2ΔT total), the voltage at the probe point rises above V OH . Also, further reflections can occur both off of the driving end and receiving end of transmission line  1006 . Some of these reflections can cause the voltage as seen at the probe point to fall below V OH . 
     For a falling edge, the voltage at the probe point starts at or around V OH . Then, some time after driver  1002  begins driving a high-to-low transition, the falling incident edge arrives at the probe point. Note that after the incident edge has passed the probe point, the voltage on the line as seen by the probe may not be a valid logic level. The voltage as seen by the probe can be too low to be a valid logic high, and too high to be a valid logic low. Later, after the incident wave has propagated to, and reflected off, the end of the transmission line  1006  and the reflected wave has propagated back to the probe point (a delay of 2ΔT total), the voltage at the probe point falls below V OL . Also, further reflections can occur both off of the driving end and receiving end of transmission line  1006 . Some of these reflections can cause the voltage as seen at the probe point to rise above V OL . 
     Because the voltage at the probe point is at an intermediate value for at least 2ΔT during each transition, and because reflections can cause the voltage at the probe point to rise above V OL  or fall below V OH , a probe circuit that relies solely on valid logic levels will produce results that can have timing uncertainty and may produce glitches. The present invention solves this problem. 
     FIG. 3 is a schematic diagram of an incident-edge detection circuit. In FIG. 3, the input (IN) of the incident-edge detection circuit is connected to the inverting input of comparator  3002  and the non-inverting input of comparator  3004 . The non-inverting input of comparator  3002  is connected to the high-to-low threshold voltage, V TH . The inverting input of comparator  3004  is connected to the low-to-high threshold voltage, V TL . The output of comparator  3002  is connected to one data input of a two-to-one multiplexer  3006 . The output of comparator  3004  is connected to the other data input of multiplexer  3006 . The output of multiplexer  3006  is connected to the clock input of flip-flop  3008 . The output of flip-flop  3008  is the output of the incident-edge detector, OUT. An inverted output of flip-flop  3008  (or the output of  3008  inverted) is connected to the input of a time delay element  3010 . The output of time delay element  3010  follows its input except that it is delayed by predetermined period of time, ΔT 1 . The output of time delay element  3010  is connected to the data input of flip-flop  3008 . Since the output of time delay element  3010  is an inverted and time delayed version of the output of flip-flop  3008 , this arrangement will toggle when clocked. Other arrangements that toggle when clocked, such as a “T” type flip-flop or an appropriately wired “JK” type flip-flop could also be used. The output of time delay element  3010  is also connected to the control input of multiplexer  3006 . When high, the control input causes multiplexer  3006  to relay the output of comparator  3002  to the clock input of flip-flop  3008 . When low, the control input causes multiplexer  3006  to relay the output of comparator  3004  to the clock input of flip-flop  3008 . 
     When the incident-edge detector is initialized, its output, OUT, can be chosen to have the same logic state as the logic state on transmission line  1006 . Similarly, if an inverted output is desired, the incident-edge detector can be initialized such that its output is the opposite as the logic state on transmission line  1006 . For the purposes of this discussion, it will be assumed that the edge detector was initialized so that its output will invert the logic state on transmission line  1006 . Accordingly, when transmission line  1006  is at or near V OL , as is shown at the start of FIG. 2, OUT is at a logical high, and the control input to multiplexer  3006  is at a logical low so that the output of comparator  3004  is being relayed to the clock input of flip-flop  3008 . 
     In FIG. 2, the voltage at the probe point starts at or around V OL . Then, some time after driver  1002  begins driving a low-to-high transition, the rising incident-edge arrives at the probe point. After the incident-edge has passed the probe point, the voltage on the line as seen by the probe is at some intermediate level that may not be a valid logic level. However, the threshold voltage V TL  is chosen to be lower than this intermediate level. Therefore, the output of comparator  3004  switches from a low to a high level. This transition is relayed to the clock input of flip-flop  3008  causing OUT to toggle from a logical high to a logical low. At roughly the same time, the inverting output of flip-flop  3008  makes a low-to-high transition. This transition is then delayed by ΔT 1 , by delay element  3010 . In a preferred embodiment the delay ΔT 1 , is chosen to be greater than 2ΔT. In this case, by the time the output of delay element  3010  makes its low-to-high transition, the incident-edge has propagated to the end of transmission line  1006 , been reflected, and the reflected wave has propagated past the probe point so that the voltage at the probe point is greater than V TH . Accordingly, the output of comparator  3002  will be low when the control input to multiplexer  3006  goes high. When the control input to multiplexer  3006  goes high, multiplexer  3006  begins relaying the output of comparator  3002  to the clock input of flip-flop  3008 . Any further reflections are now ignored by the incident-edge detector as long as they don&#39;t go below V TH . 
     On a falling incident edge, the voltage at the probe point starts at or around V OH . Then, some time after driver  1002  begins driving a high-to-low transition, the falling incident-edge arrives at the probe point. After the incident-edge has passed the probe point, the voltage on the line as seen by the probe is at some intermediate level that may not be a valid logic level. However, the threshold voltage V TH  is chosen to be higher than this intermediate level. Therefore, the output of comparator  3002  switches from a low to a high level. This transition is relayed to the clock input of flip-flop  3008  causing OUT to toggle from a logical low to a logical high. At roughly the same time, the inverting output of flip-flop  3008  makes a high-to-low transition. This transition is then delayed by ΔT 1  by delay element  3010 . In a preferred embodiment the delay ΔT 1  is chosen to be greater than 2ΔT. In this case, by the time the output of delay element  3010  makes its high-to-low transition, the incident-edge has propagated to the end of transmission line  1006 , been reflected, and the reflected wave has propagated past the probe point so that the voltage at the probe point is less than V TL . Accordingly, the output of comparator  3004  will be low when the control input to multiplexer  3006  goes low. When the control input to multiplexer  3006  goes low, multiplexer  3006  begins relaying the output of comparator  3004  to the clock input of flip-flop  3008 . Any further reflections are now ignored by the incident-edge detector as long as they don&#39;t go above V TL . 
     From the foregoing it will be appreciated that the probe circuit of the invention provides a novel and advantageous way of detecting the logic state being driven on a source-terminated transmission line. In cases where the driver&#39;s source impedance is smaller than the transmission line&#39;s characteristic impedance or for signals with excessive ring-back, detecting incident edges has better noise margins that the reflected edges. Also, many systems are intolerant to glitches on edge-sensitive signals. These glitches can be filtered out by this circuit. Finally, the threshold levels (V TH  and V TL ) of two independent compartors can typically be controlled more accurately than those achieved using a single comparator having hysteresis. 
     Although several specific embodiments of the inventions have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The invention is limited only by the claims.

Technology Classification (CPC): 7