Patent Abstract:
A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

Full Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of provisional patent application No. 61/493,407 filed on Jun. 3, 2011 by the present inventors. 
     
    
     FEDERALLY SPONSORED RESEARCH 
       [0002]    Not Applicable 
       SEQUENCE LISTING OR PROGRAM 
       [0003]    Not Applicable 
       RELEVANT PRIOR ART 
       [0004]    U.S. Pat. No. 8,135,768, Mar. 13, 2012—Stewart 
         [0005]    U.S. Patent Application Publication No. US 2012/0105105, May 3, 2012—Shukh 
         [0006]    Matsunaga S. et al., Fabrication of Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions, Applied Physics Express, vol. 1, 091301, 2008. 
         [0007]    Kang S.-M. et al., CMOS Digital Integrated Circuits: Analysis and Design, 3 rd  edition, McGraw-Hill Companies, Inc., 2003. 
       BACKGROUND 
       [0008]    A full adder is a fundamental logic circuit of numerous logic devices such as microcontrollers, processors, field programmable gate arrays (FPGAs) and many others. In general, a full adder represents an electronic circuit that has several inputs and two outputs, S (or SUM) and C OUT  (or CARRY-OUT). The one-bit full adder  10  ( FIG. 1 ) includes a logic block  12  electrically coupled to a high V DD  and low V SS  voltage sources, three input terminals A, B and C (or carry in bit C IN ) and two output terminals S and C OUT . A functionality of the one-bit full adder can be described by the following logic functions: 
         [0000]        S=A⊕B⊕C=ABC+AB*C*+A*B*C+A*BC*,   (1)
 
         [0000]        C   OUT   =AB+AC+BC,   (2)
 
         [0000]    where A, B and C are input numbers with C (or C IN ) being derived from the previous logic block, A*, B* and C* (or C IN *) are negations (or complements) of A, B and C, respectively. A truth table for the one-bit full adder is given in Table 1. 
         [0009]    There are a number of circuit designs of electronic blocks for performing SUM (S) and CARRY-OUT (C OUT ) functions. They are distinguished by the number and type of transistors, speed, voltage, power consumption, etc. These circuits are mostly built using a complimentary metal-oxide-semiconductor (CMOS) technology employing p-type and n-type of metal-oxide-semiconductor field effect transistors (MOSFETs) to perform logic functions. The CMOS-based adder circuits are volatile. They can lose their logic states when the power is off. 
         [0000]    
       
         
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Truth table for one-bit full adder 
               
             
          
           
               
                 A 
                 B 
                 C (or C IN ) 
                 S 
                 C OUT   
               
               
                   
               
               
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                 0 
                 1 
                 0 
                 1 
                 0 
               
               
                 0 
                 1 
                 1 
                 0 
                 1 
               
               
                 1 
                 0 
                 0 
                 1 
                 0 
               
               
                 1 
                 0 
                 1 
                 0 
                 1 
               
               
                 1 
                 1 
                 0 
                 0 
                 1 
               
               
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                   
               
             
          
         
       
     
         [0010]    A CMOS inverter is one of key elements of the full adder circuits.  FIG. 2  shows a nonvolatile CMOS inverter  20  according to a prior art. The inverter  20  includes an p-type MOS (pMOS) transistor  2 P 1 , an n-type MOS (nMOS) transistor  2 N 1 , and a nonvolatile magnetoresitive (MR) memory element (or magnetic tunnel junction (MTJ))  2 J 1 . Gates of the pMOS transistor  2 P 1  and the nMOS transistor  2 N 1  are connected in common to serve as an input terminal IN. Drains of the transistors  2 P 1  and  2 N 1  also connected in common serve as an output terminal OUT. Sources of the pMOS transistor  2 P 1  and the nMOS transistor  2 N 1  are connected to voltage sources V DD  and V SS , respectively. The nonvolatile memory element  2 J 1  is connected to the output terminal OUT of the inverter  20  at its first end and to a memory (intermediate) voltage source V M  at its second end, where V DD &gt;V M &gt;V SS . The source terminal of the nMOS transistor  2 N 1  can be connected to a grounding source GRD (V DD &gt;V M &gt;GRD). Moreover, the MTJ element  2 J 1  can also be connected to the grounding source GRD. In this case the following relation between electric potentials of the voltage sources can be observed: V DD &gt;GRD&gt;V SS . 
         [0011]    The MR element  2 J 1  can comprise at least a free (or storage) layer  22  with a reversible magnetization direction (shown by a dashed arrow), a pinned (or reference) layer  24  with a fixed magnetization direction (shown by a solid arrow), and a nonmagnetic insulating tunnel barrier layer  26  sandwiched in-between. Resistance of the memory element  2 J 1  depends on a mutual orientation of the magnetization directions in the free  22  and pinned  24  layers. The resistance has a highest value when the magnetization directions are antiparallel to each other, and the lowest value when they are parallel. Hence the magnetization direction of the free layer  22  can have two stable logic states. It can be controlled by a direction of a spin-polarized current I S  running through the element  2 J 1  in a direction perpendicular to layers surface (or plane). The direction of the current I S  and hence the magnetization direction of the free layer  22  depends of the polarity of the input signal at the gates of the transistors  2 P 1  and  2 N 1 . 
         [0012]    When an input signal IN=1 (logic “1”) is applied to the common gate terminal of the transistors  2 P 1  and  2 N 1 , the pMOS transistor  2 P 1  is “Off” and the nMOS transistor  2 N 1  is “On”. The spin-polarized current I S  is running in the direction from the memory source V M  to the source V SS . The current I S  of this direction can force the magnetization direction of the free layer  22  in parallel to the magnetization direction of the pinned layer  24 , which corresponds to a logic “0”. When the input signal is changed to IN=0 (a logic “0”), the pMOS transistor  2 P 1  turns “On” but the nMOS transistor  2 N 1  is “Off”. The spin-polarizing current A is running in the opposite direction from the logic source V DD  to the memory source V M . As a result, the magnetization direction of the free layer  22  can be forced in antiparallel to the magnetization direction of the pinned layer  24 . This mutual orientation of the magnetizations corresponds to a high resistance state or to logic “1”. Hence, the logic value of the memory element  2 J 1  corresponds to a logic value at the output terminal of the conventional volatile CMOS inverter. The memory element  2 J 1  can provide a nonvolatile storage of the logic state of the inverter  20 . The data may not be lost when the power is off. 
         [0013]    CMOS-based adders are volatile. They can lose their data when the power is off. The present disclosure addresses to this problem. 
       SUMMARY 
       [0014]    Disclosed herein is a nonvolatile full adder circuit comprising: a full adder electrical circuitry comprising first input terminal for receiving first binary input signals, a second input terminal for receiving second binary input signals, a third input terminal for receiving binary carry-in signals, a first output terminal for providing a sum output signal, and a second output terminal for providing a carry-out signal; a high voltage source electrically coupled to a first source terminal of the full adder electrical circuitry; a low voltage source electrically coupled to a second source terminal of the full adder electrical circuitry; a first nonvolatile memory element comprising two stable logic states and electrically coupled to the first output terminal at its first end and to an intermediate voltage source at its second end, and a second nonvolatile memory element comprising two stable logic states and electrically coupled to the second output terminal at its first end and to the intermediate voltage source at its second end, wherein a logic state each of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends, and wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source. 
         [0015]    Also disclosed is a nonvolatile full adder circuit comprising: a full adder electrical circuitry comprising a first input terminal for receiving first binary input signals, a second input terminal for receiving second binary input signals, a third input terminal for receiving binary carry-in signals, a first output terminal for providing a sum output signal, and a second output terminal for providing a carry-out signal; a first nonvolatile memory element comprising two stable logic states and electrically coupled to the first output terminal at its first end and to an intermediate voltage source at its second end, and a second nonvolatile memory element comprising two stable logic states and electrically coupled to the second output terminal at its first end and to the intermediate voltage source at its second end, wherein the first memory element provides a nonvolatile storage of the sum output signal and the second memory element provides the nonvolatile storage of the carry-out signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a block-level circuit diagram of a conventional one-bit full adder according to a prior art. 
           [0017]      FIG. 2  is a transistor-level circuit diagram of a nonvolatile CMOS inverter according to a prior art. 
           [0018]      FIGS. 3A and 3B  are transistor-level and gate-level circuit diagrams, respectively of a nonvolatile conventional CMOS-based full adder according to a first embodiment of the present disclosure. 
           [0019]      FIGS. 4A and 4B  are transistor-level circuit diagrams of sum and carry modules, respectively of a nonvolatile complementary pass-transistor logic full adder according to a second embodiment of the present disclosure. 
           [0020]      FIGS. 5A and 5B  are a transistor-level and gate-level circuit diagrams of a nonvolatile CMOS transmission gates full adder according to a third embodiment of the present disclosure. 
           [0021]      FIG. 6  is a block-level circuit diagram of a nonvolatile full adder of an embodiment according to the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Embodiments of the present disclosure will be explained below with reference to the accompanying drawings. Note that in the following explanation the same reference numerals denote constituent elements having almost the same functions and arrangements, and a repetitive explanation will be made only when necessary. 
         [0023]    Note also that each embodiment to be presented below merely discloses an device for embodying the technical idea of the present disclosure. An order of the embodiments can be any. Therefore, the technical idea of the present disclosure does not limit the materials, shapes, structures, arrangements, and the like of constituent parts to those described below. The technical idea of the present disclosure can be variously changed within the scope of the appended claims. 
         [0024]    Refining now to the drawings,  FIG. 2  illustrates a prior art. Specifically, the figure shows a magnetoresistive (MR) element (or magnetic tunnel junction (MTJ)) having a multilayer structure with ferromagnetic free and pinned layers having a perpendicular anisotropy. The MR element  2 J 1  shown in  FIG. 2  for illustrative purpose comprises only the free  22  and pinned  24  magnetic layers separated by a tunnel barrier layer  26 . Note that additional layers can also be included in the structure of the MR element  2 J 1 . The ferromagnetic layers  22  and  24  may also have an in-plane direction of the magnetization without departing from a scope of the present disclosure. The direction of the magnetization in the magnetic layers  22  and  24  are shown by dashed or solid arrows. The MR element  2 J 1  can store binary data by using steady logic states determined by a mutual orientation of the magnetizations in the free  22  and pinned  24  ferromagnetic layers separated by a tunnel barrier layer  26 . The logic state “0” or “1” of the MR element  2 J 1  can be changed by a spin-polarized current I S  running through the element in the direction perpendicular to layers surface (or substrate). 
         [0025]    The MR element herein mentioned in this specification and in the scope of claims is a general term of a tunneling magnetoresistance element using a nonmagnetic insulator or semiconductor as the tunnel barrier layer. 
         [0026]      FIGS. 3A and 3B  show a transistor-level and gate-level circuit diagrams, respectively of a nonvolatile one-bit full adder  30  according to a first embodiment of the present disclosure.  FIG. 3A  shows the transistor-level circuit diagram of a nonvolatile conventional CMOS-based full adder  30  according to a first embodiment of the disclosure. The nonvolatile full adder  30  comprises four logic blocks  31 - 34 . 
         [0027]    The logic block  33  implements an inverted CARRY function. It includes five pMOS transistors  3 P 1 - 3 P 5  that perform a pull-up function and five nMOS transistors  3 N 1 - 3 N 5  performing pull-down function, and a MR memory element  3 J 3 . Source terminals of the pMOS transistors  3 P 1 ,  3 P 3  and  3 P 5  are connected to a high voltage source V DD . Source terminals of the nMOS transistors  3 N 2 ,  3 N 3 , and  3 N 5  are connected to the grounding source GRD. Drain terminals of the pMOS transistor  3 P 4  and the nMOS transistor  3 N 4  connected in common serve as an output terminal of the logic block  33 . The CARRY block  33  receives thee three inputs A, B, and C, and implements an inverted CARRY function C OUT *. A logic value C OUT * can be stored in the nonvolatile memory element  3 J 3 . The MTJ element  3 J 3  employs a spin induced writing mechanism that was described above for the nonvolatile inverter  20  shown in  FIG. 2 . The memory element  3 J 3  can be connected to the output terminal of the block  33  at its first end and to a memory voltage source V M  at its second end, where V DD &gt;V M &gt;GRD. 
         [0028]    The logic block  34  inverts the inverted output signal C OUT * of the carry block  33  to provide a carry output C OUT . The inverter block  34  can include an pMOS transistor  3 P 14 , an nMOS transistor  3 N 14 , and a nonvolatile memory element  3 J 4  connected to the output terminal of the CMOS inverter formed by the transistors  3 P 14  and  3 N 14  at its first end and to the memory voltage source V M  at its second end. The source terminals of the pMOS transistor  3 P 14  and the nMOS transistor  3 N 14  can be connected to the voltage sources V DD  and GRD, respectively. The MR element  3 J 4  can provide a nonvolatile storage of the value C OUT . 
         [0029]    A logic block  31  comprises seven pMOS transistors  3 P 6 - 3 P 12  and seven nMOS transistor  3 N 6 - 3 N 12  forming a pull-up and pull-down circuits, respectively, and an MR element  3 J 1 . The nonvolatile memory element  3 J 1  can be connected to the output terminal of the logic block  31  at its first end and to the memory voltage source V M  at its second end. The logic block  31  can perform an inverted sum function S*. It can receive the inverted carry output C OUT * outputted from the inverted carry block  33 , and three input signals A, B, and C. Logic value of the inverted output S* can be stored in the nonvolatile memory element  3 J 1 . The output S* of the inverted sum block  31  can be applied to the input of the nonvolatile inverter block  32  composed by the transistors  3 P 13  and  3 N 13 , and a nonvolatile MR element  3 J 2 . The memory element  3 J 2  is connected to the output terminal of the CMOS inverter composed by the transistors  3 P 13  and  3 N 13  at its first end and to the memory voltage source V M  at its second end. The memory element  3 J 2  can provide a nonvolatile storage of the value S. The nonvolatile full adder  30  can provide a full-swing output and good driving capabilities. 
         [0030]    Note that other combinations of voltage sources can be used, for example the memory elements  3 J 1 - 3 J 4  can be connected to the grounding voltage source GRD at their second ends while the source terminal of the nMOS transistors  3 N 2 ,  3 N 3 ,  3 N 5 ,  3 N 6 ,  3 N 8 ,  3 N 9 ,  3 N 12 , and  3 N 14  being connected to the low voltage source V SS . For these connections the following correlation between electrical potentials of the voltage sources is true: V DD &gt;GRD&gt;V SS . 
         [0031]      FIG. 3B  shows the logic gate-level circuit diagram of the nonvolatile one-bit full adder  30  disclosed above ( FIG. 3A ). The nonvolatile full adder  30  comprises four logic blocks  31 - 34 . The logic blocks  31  and  32  implement a SUM function. The logic blocks  33  and  34  implement a CARRY function. The logic block  33  represents an inverted carry block that comprises an OR logic gate  301 , two AND gates  302  and  305 , an NOR gate  307 , and an MR element  3 J 3  connected to the output terminal of the NOR gate  307  at its first end and to the memory voltage source V M  at its second end. The logic block  34  implements a NOT function. It comprises an inverter  309  and an MR element  3 J 4  connected to the output terminal of the inverter  309  at its first end and to the memory voltage source V M  at its second end. The memory elements  3 J 3  and  3 J 4  provides a nonvolatile storage of C OUT * and C OUT  values, respectively. Note that one of the memory elements  3 J 3  or  3 J 4  may be omitted without violating the non-volatility of the circuit. 
         [0032]    The SUM function is implemented by the logic blocks  31  and  32 . The logic block  31  receives the inverted carry-out signal C OUT * outputted from the first logic block  33 , and three inputs A, B, and C to implement an inverted sum S*. The block  31  comprises an OR logic gate  303 , two AND gates  304  and  306 , an NOR gate  308 , and an MR element  3 J 1 . The nonvolatile memory element  3 J 1  can be connected to the output terminal of the NOR gate  308  at its first end and to the memory voltage source V M  at its second end. The MR element  3 J 1  can store an S* logic value. The output terminal of the logic block  31  is connected to the input terminal of the logic block  32  that is composed of an NOT gate  310  and an MR element  3 J 2 . The memory element  3 J 2  can be connected to the output terminal of the NOT gate  310  at its first end and to the memory voltage source V M  at its second end. The memory elements  3 J 1  and  3 J 2  can provide a nonvolatile storage of S* and S logic values, respectively. 
         [0033]    The nonvolatile full adder  30  shown in  FIGS. 3A and 3B  can include four MR elements  3 J 1 - 3 J 4  to provide the nonvolatile storage of the logic values S, S*, C OUT , and C OUT *. Note that the number of the MR elements of the nonvolatile adder  30  can be different from the indicated above, for example the MR elements  3 J 1  and  3 J 3  can be omitted. 
         [0034]      FIGS. 4A and 4B  show transistor-level circuit diagrams of nonvolatile logic modules  40 - 1  and  40 - 2  implementing SUM ( FIG. 4A ) and CARRY ( FIG. 4B ) functions, respectively according to a second embodiment of the disclosure. The modules  40 - 1  and  40 - 2  represent a nonvolatile complementary pass-transition logic (CPL) full adder. The sum logic module  40 - 1  ( FIG. 4A ) can comprise four logic blocks  41 - 44 . The logic block  41  is a matrix block comprising eight nMOS transistors  4 N 1 - 4 N 8  with twelve inputs for A, A*, B, B*, C, and C* signals. The nonvolatile logic block  42  represents a pull-up block comprising two pMOS transistors  4 P 1  and  4 P 2 , and two MR elements  4 J 1  and  4 J 2 . The memory element  4 J 1  can be connected to drain terminals (or to a common drain terminal) of the transistors  4 P 1 ,  4 N 5 , and  4 N 6  at its first end and to the memory voltage source V M  at its second end. Respectively, the MR element  4 J 2  can be connected to the drain terminals (or to a common drain terminal) of the transistor  4 P 2 ,  4 N 7 , and  4 N 8  at its first end and to the memory voltage source V M  at its second end. Source terminals of the pMOS transistors  4 P 1  and  4 P 2  can be connected to the logic voltage source V DD . 
         [0035]    The nonvolatile inverter  43  can include a pMOS transistor  4 P 3  and an nMOS transistor  4 N 9 , and an MR element  4 J 3 . The nonvolatile memory element  4 J 3  can be connected to the drain terminals (or to a common drain terminal) of the transistors at its first end and to the memory voltage source V M  at its second end. The MR element  4 J 3  can provide a nonvolatile storage of the logic value S*. The source terminal of the pMOS transistor  4 P 3  can be connected to the high voltage source V DD , and the source terminal of the nMOS transistor  4 N 9  can be connected to the ground source GRD, where V DD &gt;V M &gt;GRD. The nonvolatile inverter  44  can comprise an pMOS transistor  4 P 4 , an nMOS transistor  4 N 10 , and an MR element  4 J 4 . The MR element  4 J 4  can provide a nonvolatile storage of the logic value S. 
         [0036]    The nonvolatile carry module  40 - 2  is shown in  FIG. 4B . The logic module  40 - 2  can comprise four logic blocks  45 - 48 . The logic block  45  is a matrix block comprising twelve nMOS transistors  4 N 11 - 4 N 22  and sixteen inputs for signals A, A*, B, B*, C, and C*. Source terminals of the transistors  4 N 12  and  4 N 13  can be connected to the ground voltage source GRD. Drain terminals of the transistors  4 N 15  and  4 N 18  can be connected to the high voltage source V DD . The nonvolatile logic block  46  represents a pull-up block. It can comprise two pMOS transistors  4 P 5  and  4 P 6 , and two MR elements  4 J 5  and  4 J 6 . The MR element  4 J 5  can be connected to the drain terminals (or to a common drain terminal) of the transistors  4 N 19 ,  4 N 20  and  4 P 5  at its first end and to the memory voltage source V M  at its second end. The source terminals of the transistors  4 P 5  and  4 P 6  can be connected to the high voltage source V DD . Respectively, the MR element  4 J 6  can be connected to the drain terminals of the transistors  4 N 21 ,  4 N 22  and  4 P 6  at its first end and to the memory voltage source V M  at its second end, where V DD &gt;V M &gt;GRD. The MR elements can provide a nonvolatile storage of the output signals of the logic block  46 . 
         [0037]    The nonvolatile inverter  47  can include an pMOS transistor  4 P 7 , an nMOS transistor  4 N 13 , and an MR element  4 J 7  electrically connected to the drain terminals of the transistors  4 P 7  and  4 N 13  at its first end and to the memory voltage source V M  at its second end. The source terminals of the transistors  4 P 7  and  4 N 23  can be connected to the high voltage source V DD  and to the grounding source GRD, respectively, where V DD &gt;V M &gt;GRD. The nonvolatile inverter  48  can comprise an pMOS transistor  4 P 8 , an nMOS transistor  4 N 24  and an MR element  4 J 8 , respectively. The MR elements  4 J 7  and  4 J 8  can provide a nonvolatile storage of C OUT * and C OUT  logic values of the carry module  40 - 2 , respectively. 
         [0038]    The nonvolatile full adder  40  shown in  FIGS. 4A and 4B  can comprise eight MR elements  4 J 1 - 4 J 8  to provide the nonvolatile storage of the logic values. Note that the number of the MR elements of the nonvolatile adder  40  can be different from the indicated above, for example the MR elements  4 J 1 ,  4 J 2 ,  4 J 5 , and  4 J 6  can be omitted. 
         [0039]      FIGS. 5A and 5B  show a transistor-level and gate-level circuit diagrams of a nonvolatile one-bit full adder  50  constructed according to a third embodiment of the present disclosure. The diagrams represent the nonvolatile transmission-gates full adder  50 . 
         [0040]    The transistor-level nonvolatile full adder  50  is shown in  FIG. 5A . It can include four inverters  501 - 504 , six transmission gates  51 - 56 , two pMOS transistors  5 P 1 ,  5 P 2  and two nMOS transistors  5 N 1 ,  5 N 2  connected in series, and two nonvolatile MR elements  5 J 1  and  5 J 2 . The transmission gate  51  can comprise an pMOS transistor  5 P 3  and an nMOS transistor  5 N 3  connected in parallel to each other. The transmission gates  52 - 56  can have similar design. The MR element  5 J 1  can be electrically coupled to the output terminal of the inverter  503  at its first end and to the memory voltage source V M  at its second end to provide a nonvolatile storage of the logic value S. Respectively, the MR element  5 J 2  can be electrically coupled to the output terminal of the inverter  504  at its first end and to the memory voltage source V M  at its second end to provide a nonvolatile storage of the logic value C OUT . 
         [0041]    The logic gate-level circuit diagram of the nonvolatile full adder  50  is given in  FIG. 5B . The nonvolatile full adder  50  can comprise two inverters  501  and  502 , two XOR logic gates  505  and  506 , two multiplexers  507  and  508 , and two MR memory elements  5 J 1  and  5 J 2 . The memory element  5 J 1  can be electrically coupled to the output terminal of the multiplexer  507  at its first end and to the memory voltage source V M  at its second end. The MR element  5 J 1  can provide the nonvolatile storage of the logic value S. Respectively, the MR element  5 J 2  can be connected to the output terminal of the multiplexer  508  at its first end and to the memory voltage source V M  at its second end to provide the nonvolatile storage of the logic value C OUT . 
         [0042]      FIG. 6  shows a block-level circuit diagram of the nonvolatile one-bit full adder  60  according to an embodiment of the present disclosure. The nonvolatile adder  60  can comprise a logic block  62  for performing SUM and CARRY logic functions, three input terminals for logic values A, B, and C, two output terminals for logic values S and C OUT , and two nonvolatile memory elements  6 J 1  and  6 J 2 . One memory element  6 J 1  can be electrically coupled to the S output terminal of the logic block  62  at its first end and to the memory voltage source V M  at its second end. Another nonvolatile memory element  6 J 2  can be connected to the C OUT  output terminal at its first end and to the memory voltage source V M  at its second end. The MR elements  6 J 1  and  6 J 2  can provide the nonvolatile storage of the logic values S and C OUT , respectively. The logic block  62  can be electrically connected to the high voltage source V DD  at its first source terminal and to the low voltage source V SS  at its second source terminal, where V DD &gt;V M &gt;V SS . Note that one of the voltage sources can be replaced by a grounding source GRD, for example the MR elements  6 J 1  and  6 J 2  can be electrically coupled to GRD source at their second ends. In this case the following correlation between electrical potentials of the voltage sources can be observed: V DD &gt;GRD&gt;V SS . 
         [0043]    The full adder circuits shown in  FIGS. 3-6  employ the MR elements (or MTJs) as nonvolatile memory elements. Note that the MR elements can be replaced by another nonvolatile memory elements such as a phase change memory element, resistive memory element and others without departing from the scope of the present disclosure. 
         [0044]    The disclosed nonvolatile full adder circuits comprise the nonvolatile memory elements disposed above a CMOS logic circuitry formed on a wafer. The embedded nonvolatile memory elements can have a marginal impact on a design and manufacturing process of the conventional volatile CMOS-based adder circuits. 
         [0045]    While the specification of this disclosure contains many specifics, these should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination. 
         [0046]    It is understood that the above embodiments are intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the embodiments should be, therefore, determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. 
         [0047]    While the disclosure has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the disclosure can be practiced with modification within the spirit and scope of the appended claims. Specifically, one of ordinary skill in the art will understand that the drawings herein are meant to be illustrative, and the spirit and scope of the disclosure are not limited to the embodiments and aspects disclosed herein but may be modified.

Technology Classification (CPC): 7