Patent Abstract:
Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.

Full Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     The present application is a continuation application of U.S. Ser. No. 11/215,778, filed on Aug. 30, 2005, now issued as U.S. Pat. No. 7,768,049, which is a divisional of U.S. Ser. No. 10/421,157, filed on Apr. 23, 2003, now issued as U.S. Pat. No. 7,049,153, which applications are herein incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     Integrated memory circuits serve as data-storage components in thousands of products, from televisions, to automobiles, to computers. Often, these memory circuits are implemented as arrays of memory cells, with each memory cell storing an electrical charge representative of a one or a zero. 
     In recent years, these memory cells have been modified to include a layer of ceramic-based ferroelectric material that exhibits electric polarizations, analogous to north-south magnetic polarizations, in response to appropriate electrical signals. One electrical signal polarizes the material to represent a zero, and another signal oppositely polarizes the material to represent a one. The polarizations can be detected with special circuitry that allows recovery of stored data. Memory circuits using these ferroelectric memory transistors generally enjoy advantages, such as faster write cycles and lower power requirements, over conventional charge-storage memories. 
     More recently, polymer-based ferroelectrics have emerged as a potential substitute for ceramic-based ferroelectrics because they generally overcome or ameliorate problems, such as fatigue and imprint, that ceramic-based ferroelectrics may suffer. Moreover, polymer-based ferroelectrics are generally more amenable to use in multi-layer (stacked) memory circuits, which provide increased storage capacity. However, polymer-based ferroelectrics are not without their own problems. 
     For example, conventional fabrication methods that deposit the ferroelectric polymer over metal structures separated by empty gaps may create hills and valleys in the deposited ferroelectric material. The changing thickness of the ferroelectric material is undesirable, because it not only causes cell-to-cell performance variations, but also produces too many defective cells and thus reduces manufacturing yield. Poor yield ultimately raises the cost of manufacturing these type memories. Moreover, as the number of layers in a multi-layer memory increases, the hills and valleys tend to become higher and deeper, exaggerating the thickness variations in the deposited ferroelectric material and further detracting from desired performance and yield. 
     Accordingly, the present inventors have recognized a need for developing other methods of making polymer-based ferroelectric memories. 
     SUMMARY 
     To address these and other needs, unique methods, structures, circuits, and systems for polymer-based ferroelectric memories have been devised. One method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. 
     In some embodiments, forming the gap-filling structure entails depositing a spin-on-glass material within the gap between the two first conductors and/or depositing a polymer-based material. For example, one embodiment deposits a polymer-based materials having a different solvent concentration than that used for the polymer-based ferroelectric. Still other methods extend the use of gap-filling structures to subsequent layers in a multi-layer memory circuit. 
     Other aspects of various embodiments include arrays of memory cells and memory circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of an integrated-circuit assembly including a substrate  12 , lower electrode structures  14 ,  16 , and  18 , and gaps  15  and  17 . 
         FIG. 2  is a cross-sectional view of the  FIG. 1  assembly after forming gap-filling layer  20 , which includes gap-filling structures  22  and  24 . 
         FIG. 3  is a cross-sectional view of the  FIG. 2  assembly after forming polymer-based ferroelectric layer  30 . 
         FIG. 4  is a cross-sectional view of the  FIG. 3  assembly after forming conductive layers  32 A,  32 B, and  32 C atop polymer-based ferroelectric layer  30 . 
         FIG. 5  is a cross-sectional view of the  FIG. 4  assembly, taken along line  5 - 5 , after forming upper electrode structures  34 ,  36 , and  38 . 
         FIG. 6  is a cross-sectional view of the  FIG. 5  assembly after forming gap-filling layer  40 , to complete a first cross-point polymer-based memory array  60 . 
         FIG. 7  is a cross-sectional view of the  FIG. 6  assembly after forming a second cross-point polymer-based memory array structure  60 ′ atop memory array  60 . 
         FIG. 8  is a cross-sectional view of a cross-point polymer-based memory array structure, which is similar to array  60  in  FIG. 6 , but includes floating gate polymer-based memory transistors, such as transistor  80 . 
         FIG. 9  is a cross-sectional view of an integrated-circuit assembly including a substrate  12  which has a number of trenches, such as trenches  92 ,  94 , and  96 . 
         FIG. 10  is a cross-sectional view of the  FIG. 9  assembly after formation of lower electrode structures  102 ,  104 , and  106  in the trenches. 
         FIG. 11  is a cross-sectional view of the  FIG. 10  assembly after formation of a polymer-based ferroelectric layer  110  over lower electrode structures  102 ,  104 ,  106 . 
         FIG. 12  is a cross-sectional view of the  FIG. 11  assembly taken along line  12 - 12  of  FIG. 11 , after formation of upper electrode structures  122 ,  124 , and  126  on polymer-based ferroelectric layer  110 . 
         FIG. 13  is a block diagram of a system including a polymer-based ferroelectric-memory circuit that incorporates ferroelectric memory arrays and/or other structures according to the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description, which references and incorporates  FIGS. 1-13 , describes and illustrates specific embodiments of the invention. These embodiments, offered as examples, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of ordinary skill in the art. 
       FIGS. 1-7  show a number of integrated-circuit assemblies, which collectively illustrate at least one method of fabricating polymer-based ferroelectric memory arrays according to the present invention. (Other embodiments may be formed by changing the order of formation or by combining or eliminating formation or processing of certain features.)  FIG. 8  shows alternative polymer-based memory array using floating-gate transistors.  FIGS. 9-12  collectively illustrate another method of fabricating polymer-based ferroelectric memory arrays according to the present invention.  FIG. 13  shows a random-access-memory circuit incorporating ferroelectric memory transistors or memory cells of the present invention. 
     Fabrication Methods and Structures for Ferroelectric Memories 
     The first method, as shown in  FIG. 1 , begins with formation of a number of lower electrode structures, such as electrode structures  14 ,  16 , and  18 , on a surface of a substrate  12 . The term “substrate,” as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, semi-insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures. 
     In this embodiment, substrate  12  comprises an insulative layer, which itself lies on a layer of semiconductive material (not shown). Useful insulative materials include silicon dioxide, silicon nitrides, silicon oxynitrides, or carbides. Useful semiconductive materials include silicon, silicon carbide, and silicon germanium. However, other embodiments may use different materials. This method forms the insulative layer through oxidation of the semiconductive surface. Other embodiments, however, may grow or deposit another insulative material. In some embodiments, substrate  12  comprises a layer of polymer, for example, a ferroelectric polymer, which is processed as a continuous roll. 
     More specifically, lower electrode structures  14 ,  16 , and  18  include respective 5-100-nanometer-thick titanium layers  14 A,  16 A, and  18 A; respective 20-1000-nanometer-thick aluminum layers  14 B,  16 B, and  18 B; and respective 5-100-nanometer-thick titanium-nitride layers  14 C,  16 C, and  18 C. (Other embodiments form layers  14 C,  16 C, and  18 C using tantalum nitride, tungsten, and tungsten nitride.) Lower electrode structures  14  and  16  are separated by a gap  15 , and lower electrode structures  16  and  18  are separated by a gap  17 . 
     In this embodiment, forming the lower electrode structures entails sequential deposition of titanium, aluminum, and titanium nitride to form respective titanium, aluminum, and titanium-nitride layers. The titanium layer is then masked to define parallel conductive traces (which appear as islands in this cross-sectional view) and all three layers are etched down to (or into) substrate  12 . 
     Some embodiments form the conductive layers of the electrode structures from different materials. For example, some embodiments replace the titanium-nitride layer with a platinum-based layer or a tantalum-nitride layer. And, some embodiments replace the aluminum layer with a copper-, sliver-, or gold-based metallic layer. Some embodiments may use non-metal conductive materials. Note that some embodiments form an adhesion layer on the substrate as preparation for the titanium or other metal. 
       FIG. 2  shows that after forming the lower electrode structures  14 ,  16 , and  18 , the method forms a gap-filling layer  20 , which substantially fills gaps  15  and  17  (in  FIG. 1 ) with respective gap-filling structures  22  and  24 . In some embodiments, gap-filling layer  20 , which has a thickness that is 20-200 nanometers or 10-100 percent thicker than the height of the lower electrode structures, comprises an insulative material, such as a spin-on-glass material, a Flow-Fill™ oxide, a high-density-plasma (HDP) oxide, or an insulative polymer. (Flow-fill may be a trademark of Electrotech Limited of Bristol, United Kingdom. For further information regarding a flow-fill technique, see, for example, U.S. Pat. No. 6,372,669, which is assigned to the assignee of the embodiments described in this document, and incorporated herein by reference in its entirety.) In some other embodiments, gap-filling layer has thickness which makes it substantially flush with the lower electrode structures. After deposition of the gap-filling layer, one or more portions of the layer overlying the lower electrode structures are removed using a wet or dry etch or a chemical-mechanical planarization technique. 
     In some embodiments that use an insulative polymer filler, the polymer includes a polymer-based ferroelectric material. (As used herein, the term “ferroelectric,” indicates that a subject material, material composition, or material structure, exhibits a detectable spontaneous electrical polarization in response to appropriate electrical stimulus. Thus, the term without other express contextual modification or qualification generally encompasses elemental ferroelectric materials as well as combination and composite ferroelectric materials.) Useful ferroelectric polymers include polyvinylidene fluoride (PVDF), trifluoroethylene, (TrFe), and co-polymers of PVDF and TrFe. Useful co-polymers include the PVDF and TrFe in concentrations ranging from 10-90 percent. However, other embodiments may use other concentrations. 
     Some embodiments optimize the spin-characteristics of the ferroelectric polymer by controlling solvent concentrations. Useful solvent concentrations range between 20-80 percent. Such optimization can be achieved by changing the molecular weight distribution, copolymer composition, and/or polymer thickness. 
       FIG. 3  shows that after forming gap-filling structures  22  and  24 , the method entails formation of a polymer-based ferroelectric layer  30 . More specifically, this polymer-based ferroelectric layer is formed to a thickness of 10-1000 nanometers. In this embodiment, polymer-based ferroelectric layer  30  has different characteristics than the gap-filling layer, more precisely polymer-based gap-filling structures  22  and  24 . Specifically, unlike the polymer-based gap-filling structures  22  and  24 , which is optimized for spin casting, polymer-based ferroelectric layer  30  is optimized for other properties, such as its ferroelectricity. 
     Notably, polymer-based ferroelectric layer  30  contacts only the gap-filling material ( 20 ,  22 ,  24 ) and the uppermost layers of lower electrode structures  14 ,  16 , and  18 . In some conventional polymer-based memory structures, the lower electrode structures are formed by lining a trench or other opening in an insulative surface with a diffusion barrier metal and then filling the lined trench with a second metal. In these conventional cases (which also lack the gap-filling layer and associated gap-filling structures), the polymer-based ferroelectric material therefore contacts both the trench-lining metal and the fill metal. This dual-metal interface is undesirable because it produces fringing fields. 
       FIG. 4  shows that the next step in the method entails sequentially forming conductive layers  32 A,  32 B, and  32 C atop polymer-based ferroelectric layer  30 . These conductive layers generally correspond in dimension and composition to those of lower electrode structures  14 ,  16 , and  18 . More specifically, conductive layer  32 A is 5-100-nanometer-thick titanium layers  14 A; conductive layer  32 B is a 20-1000-nanometer-thick aluminum layer; and conductive layer  32 C is a 5-100-nanometer-thick titanium-nitride layer. However, some embodiments use other materials and dimensions, as described for the lower electrode structures. 
       FIG. 5 , a cross-sectional view taken along line  5 - 5  of  FIG. 4 , shows that after forming conductive layers  32 A,  32 B, and  32 C, the method forms these layers into upper electrode structures  34 ,  36 , and  38 . Formed orthogonal to the lower electrode structures  14 ,  16 , and  18 , and separated by gaps  35  and  37 , upper electrode structures  34 ,  36 , and  38  include respective 5-100-nanometer-thick titanium layers  34 A,  36 A, and  38 A; respective 20-1000-nanometer-thick aluminum layers  34 B,  36 B, and  38 B; and respective 5-100-nanometer-thick titanium-nitride layers  34 C,  36 C, and  38 C. Notably, the thicknesses of the respective portions  30 A,  30 B, and  30 C of polymer-based ferroelectric layer  30  separating each upper electrode structure from its counterpart lower electrode structure are substantially equal, even at the edges of the substrate. 
     In this embodiment, forming the upper electrode structures entails masking titanium-nitride layer  34  to define bars and etching it and layers  36  and  38  down into polymer-based ferroelectric layer  30 . The depth of the etch, for example 2-30 percent of the layer thickness, is generally sufficient to ensure separation of the upper electrode structures. 
       FIG. 6  shows that the method next forms a gap-filling layer  40 , which substantially fills gaps  35  and  37  (in  FIG. 4 ) with gap-filling structures  42  and  44 , and thus completes a first polymer-based memory array  60 . In this embodiment, gap-filling layer  40 , which has a thickness at least as great as the height of the upper electrode structures plus the depth of the etch into ferroelectric layer  30 , comprises an insulative material, such as a spin-on-glass material, an HDP oxide, an insulative polymer, or a polymer-based ferroelectric material, as in the formation of gap-filling layer  20 . (Using a polymer-based ferroelectric material to fill the gaps may ameliorate fringe-field issues.) Forming the layer to this height entails spin casting the material and then planarizing using chemical-mechanical planarization for example, to expose upper electrode structures  34 ,  36 , and  38 . Some embodiments may expose the upper electrode structures using a dry or wet etch. 
       FIG. 7  shows that the next step in the method may entail building at least one additional polymer-based memory array  60 ′ atop memory array  60  to realize a multilevel memory array  70 . The fabrication of memory array  60 ′ may follow the same procedure used for memory array  60 . However, other embodiments may make material and/or dimensional changes, or use entirely different methods and materials to realize other memory arrays, analogous or non-analogous to array  60 . Although not shown, other embodiments continue by forming support circuitry and associated interconnections to realize a complete memory circuit. 
       FIG. 8  shows an alternative version of the integrated-circuit assembly in  FIG. 3 . The alternative version includes a semiconductive substrate  12  and a number of polymer-based ferroelectric floating gate transistors, of which transistor  80  is representative. 
     Transistor  80  includes self-aligned source/drain regions  82  and  84 , a semiconductive channel region  83 , and a gate insulator  86 . Source and drain regions  82  and  84 , formed using a conventional ion-implantation and diffusion techniques, define the length of channel region  83 . Although this embodiment shows simple drain and source profiles, any desirable profile, for example, a lightly doped drain (LDD) profile, an abrupt junction or a “fully overlapped, lightly doped drain” (FOLD) profile, may be used. (Some profiles entail formation of insulative sidewall spacers on the lower electrode structure, before executing the ion-implantation procedure that forms the drain and source regions.) Gate insulator  86 , which consists of a silicon oxide or other suitable dielectric material, lies between channel region  83  and lower electrode structure  14 . Drain and source contacts (not shown) are formed and interconnected as desired to complete an integrated memory circuit 
     In operation, the polarization state of a portion of the polymer-based ferroelectric in memory arrays described herein can be controlled by applying appropriate voltages to the electrode structures and/or to the gate, source and drains. Conventional circuitry and related techniques can also be used for sensing the polarization state of each memory cell in the arrays. 
       FIGS. 9-12  show another series of integrated-circuit assemblies which sequentially and collectively illustrate another method of making a polymer-based ferroelectric memory array. (Other embodiments may be formed by changing the order of formation or by combining or eliminating formation or processing of certain features.) This method, as shown in  FIG. 9 , begins with forming in substrate  12  a number of trenches, such as trenches  92 ,  94 , and  96 . The trenches may be formed using any available technique appropriate for the composition of substrate  12 . For example, if substrate  12  is an insulative material, such as silicon dioxide, one may form the trenches using conventional photolithographic techniques. 
     Next,  FIG. 10  shows that this method forms lower electrode structures  102 ,  104 , and  106  in the trenches. More specifically, this entails blanket depositing a conductive material, such as aluminum or titanium, over the trenches and surrounding substrate regions, with the layer having a thickness greater than the depth of the trenches. After the blanket deposition, the method removes conductive material outside the trenches using a planarization process, such as chemical-mechanical planarization. In this embodiment, planarization removes substantially all conductive material outside the trenches and leaves the conductive material within the trenches substantially flush with the top surface of the substrate, ultimately defining the lower electrode structures. Some other embodiments may form the lower electrode structures as multilayer structures, analogous to previously described lower electrode structures  14 ,  16 , and  18 . 
       FIG. 11  shows the results of forming a polymer-based ferroelectric layer  110  over lower electrode structures  102 ,  104 ,  106 . It is expected that the aluminum or titanium composition of the lower electrode will provide sufficient adhesion and diffusion-barrier properties to interface effectively with the polymer-based ferroelectric layer. Notably, this form of material interface, like the previous embodiment, avoids undesirable fringing fields that result from multiple metallic layers contacting the polymer-based ferroelectric layer. 
       FIG. 12 , a cross-sectional view taken along line  12 - 12  of  FIG. 11 , shows that the method may next faun upper electrode structures  122 ,  124 , and  126  on polymer-based ferroelectric layer  110 . These upper electrodes generally correspond in dimension and composition to those of lower electrode structures  102 ,  104 , and  106 . 
     More precisely, this embodiment forms the upper electrodes by forming trenches in polymer-based ferroelectric layer  110  that are transverse or orthogonal to the lower electrodes, blanket depositing aluminum or titanium over the trenches and surrounding regions, and then removing substantially all the metal outside the trenches using a planarization process, such as chemical-mechanical planarization. The planarization ultimately forms upper electrode structures that are substantially flush with a top surface of the polymer-based ferroelectric layer, thus completing a polymer-based memory array  130 . Some other embodiments may form the upper electrode structures as multilayer structures, analogous to previously described structures  34 ,  36 , and  38 . 
     Further processing can be used to define one or more additional polymer-based memory arrays atop memory array  130  to produce a multi-level memory analogous to multilevel memory array  70  in  FIG. 7 . Additionally, further processing may also define a number of polymer-based ferroelectric floating gate transistors. 
     Systems and Circuits 
       FIG. 13  shows a computer system  1300  including a memory circuit  1310 , a processing unit  1320 , input-output devices  1330 , data-storage  1340 , and a bus  1350 . Memory circuit  1310 , which operates according to well-known and understood principles and is coupled to one or more other components of the system via bus  1350 , includes one or more memory arrays  1312 , a row address decoder  1314 , a column address decoder  1316 , a level address decoder  1318 , and sense circuitry  1319 . 
     In this embodiment, memory arrays  1312  incorporate one or more of the memory arrays or intermediate integrated-circuit assemblies based on teachings of the present invention. Also, in this embodiment, memory arrays, the address decoders, and the sense circuitry exist in a single integrated circuit. However, in other embodiments, one or more may exist on separate integrated circuits. 
     Processing unit  1320 , input-output devices  1330 , and data-storage devices  1340  are intercoupled conventionally via bus  1350 . Processing unit  1320  includes one or more processors or virtual processors. Input-output devices  1330  includes one or more keyboards, pointing devices, monitors, etc. And data-storage devices  1340  include one or more optical, electronic, or magnetic storage devices. 
     CONCLUSION 
     In furtherance of the art, the inventors have presented unique methods and structures for polymer-based ferroelectric memories. One method entails forming two or more first conductive structures on a substrate, with at least two of the first electrode structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first electrode structures. Two or more second electrode structures are then formed over the polymer-based ferroelectric layer, orthogonal to the first electrode structures. Notably, the gap-filling structures may facilitate formation of a substantially planar and uniformly thick polymer-based ferroelectric layer, thereby promoting memory performance and yield. 
     The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.

Technology Classification (CPC): 7