Patent Abstract:
A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level.

Full Description:
FIELD OF THE INVENTION 
   The present invention relates to non-volatile memory cells generally and to methods of reading them in particular. 
   BACKGROUND OF THE INVENTION 
   Dual bit memory cells are known in the art. One such memory cell is the NROM (nitride read only memory) cell  10 , shown in  FIG. 1  to which reference is now made, which stores two bits  12  and  14  in a nitride based layer  16  sandwiched between a conductive layer  18  and a channel  20 . NROM cells are described in many patents, for example in U.S. Pat. No. 6,649,972, assigned to the common assignees of the present invention, whose disclosure is incorporated herein. 
   Bits  12  and  14  are individually accessible, and thus, may be programmed (conventionally noted as a ‘0’), erased (conventionally noted as a ‘1’) or read separately. Reading a bit ( 12  or  14 ) involves determining if a threshold voltage Vt, as seen when reading the particular bit, is above (programmed) or below (erased) a read reference voltage level RD. 
     FIG. 2 , to which reference is now made, illustrates the distribution of programmed and erased states of a memory chip (which typically has a large multiplicity of NROM cells formed into a memory array) as a function of threshold voltage Vt. An erased bit is one whose threshold voltage has been reduced below an erase threshold voltage EV. Thus, an erase distribution  30  has typically its rightmost point in the vicinity of (and preferably at or below) the erase threshold voltage EV. Similarly, a programmed bit is one whose threshold voltage has been increased above a program threshold voltage PV. Thus, a programmed distribution  32  has typically its leftmost point in the vicinity of (and preferably at or above) the program threshold voltage PV. 
   The difference between the two threshold voltages PV and EV is a window W 0  of operation. Read reference voltage level RD is typically placed within window W 0  and can be generated, as an example, from a read reference cell. The read reference cell is usually, but not necessarily, in a non-native state, as described in U.S. Pat. No. 6,490,204, assigned to the common assignee of the present invention, whose disclosure is incorporated herein by reference. In such case, the threshold voltage of read reference cell may be at the RD level in  FIG. 2 . 
   The signal from the bit being read is then compared with a comparison circuit (e.g. a differential sense amplifier) to the signal generated by the read reference level, and the result should determine if the array cell is in a programmed or erased state. Alternatively, instead of using a reference cell, the read reference signal can be an independently generated voltage or a current signal. Other methods to generate a read reference signal are known in the art. 
   Since the sensing scheme circuitry may not be perfect, and its characteristics may vary at different operating and environmental conditions, margins M 0  and M 1  are typically required to correctly read a ‘0’ and a ‘1’, respectively. As long as the programmed and erased distributions are beyond these margins, reliable reads may be achieved. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which: 
       FIG. 1  is a schematic illustration of a prior art NROM cell; 
       FIG. 2  is a schematic illustration of the distribution of programmed and erased states of a memory chip of NROM cells as a function of threshold voltage Vt; 
       FIG. 3  is a schematic illustration of erase and programmed distributions at some point after the start of operation of an exemplary memory array, 
       FIG. 4  is a schematic illustration of erase and programmed distributions once the distributions have shifted from those of  FIG. 3 ; 
       FIGS. 5A ,  5 B and  5 C are schematic illustrations of a method of reading memory cells, constructed and operative in accordance with the present invention, using a moving read reference level which may move as a function of changes in the window of operation; and 
       FIGS. 6A ,  6 B and  6 C are schematic illustrations of alternative locations of history cells and memory cells, useful in implementing the method of  FIGS. 5A ,  5 B and  5 C. 
   

   It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. 
   DETAILED DESCRIPTION OF THE INVENTION 
   In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention. 
   Applicants have realized that the window of operation may change over time as the cells go through multiple erase and programming cycles. The window of operation may shrink and/or may drift, both of which may affect the accuracy of the read operation. 
   Reference is now made to  FIG. 3 , which illustrates erase and programmed distributions  40  and  42 , respectively, at some point after the start of operation of an exemplary memory array. 
   Although each bit may be erased to a threshold voltage below erase voltage EV, erase distribution  40  may appear to be shifted slightly above erase voltage EV. Applicants have realized that this may be due to the fact that the two bits of a cell have some effect on each other. If both bits are erased, then the threshold voltage of each bit may be below erase voltage EV (as indicated by the smaller distribution  44  within erase distribution  40 ). However, if one of the bits is programmed while the other bit is erased, the threshold voltage of the erased bit may appear higher, due to the programmed state of the other bit. This is indicated by the second small distribution  46  within erase distribution  40 , some of whose bits may have threshold voltages that appear to be above erase voltage EV. This is typically referred as a “second bit effect”. 
   Applicants have additionally realized that, after repeated program and erase cycles, programmed distribution  42  may shift below programming voltage PV. This may be due to charge redistribution within the trapping layer, aging characteristics, or retention properties of the cells after many erase/program cycles. This downward shift of the programmed distribution  42  is time and temperature dependent, and the shift rate also depends on the number of program/erase cycles that the cell has experienced in its past. 
   The result of these shifting distributions may be to shrink the window of operation to a different window Wm of operation. Applicants have realized that the different window Wm may or may not be aligned with the original window W 0 .  FIG. 3  shows an exemplary window Wm with its center shifted from the center of the original window W 0 . Applicants have realized that one or both of these changes may have an effect on the quality of the read operation. This is illustrated in  FIG. 4 , to which reference is now made. 
   As mentioned in the Background, a margin M 1  may be required to compensate circuit deficiencies and to ensure a correct read of an erased bit. The original placement of the erased bits below the EV level (typically after an erase operation), provided a larger than M 1  margin, and thus a reliable read of ‘1’ bits. Unfortunately, as shown in  FIG. 4 , since erase distribution  40  may have drifted above erase threshold voltage EV, margin M 1  may no longer be maintained. There may be some bits within erase distribution  46 , indicated by solid markings, which may be wrongly read (i.e. read as programmed) since their threshold voltages are not below margin M 1 . 
   Reference is now made to  FIGS. 5A ,  5 B and  5 C, which together illustrate a method of reading memory cells, constructed and operative in accordance with the present invention, using a moving read reference level MRL, which may move as a function of changes in the window of operation. 
   In accordance with a preferred embodiment of the present invention, shortly after an erase and a program operation ( FIG. 5A ), moving read level MRL may be placed at a read level RD 1  between an erase distribution  50 A and a programmed distribution  52 A, where erase distribution  50 A is now slightly above erase threshold voltage EV (due to the second bit effect) and programmed distribution  52 A is now entirely or almost entirely above programming threshold voltage PV. Suitable margins M 1  and M 0  may be defined from read level RD 1  to overcome circuit and sensing scheme deficiencies and to ensure correct detection of the bit states. In  FIG. 5A , the erase and program distributions are beyond margins M 1  and M 0 , respectively. Therefore, at this point, read level RD 1  may successfully and reliably read both 1&#39;s and 0&#39;s. 
   If the cells have already passed multiple programming and erase cycles, then, after a period of time, the distributions may shift. In  FIG. 5B , the program distribution, now labeled  52 B, has moved lower and thus, a significant part of it is below program threshold voltage PV. However, the erase distribution, here labeled  50 B, has typically also moved lower. Even if the window of operation W B  is close to or the same width as that in  FIG. 5A  (labeled W A ), its center has changed. As a result, read reference level RD 1  with margin M 0  may no longer correctly read all the bits in the program distribution  52 B as ‘0’. 
   In accordance with a preferred embodiment of the present invention, for the situation of  FIG. 5B , moving read level MRL may move to a second read level RD 2 . In this situation, when reading bits with reference to read level RD 2 , margins M 0  and M 1  are maintained, but relative to the shifted RD 2  read level, and therefore all the bits in both distributions ( 50 B and  52 B) may be correctly read as erased (‘1’) or programmed (‘0’). 
     FIG. 5C  shows a third case where the distributions may have shifted further, resulting in a window of operation W C  that is further shrunk and/or shifted. In accordance with a preferred embodiment of the present invention, moving read level MRL may move to a third read level RD 3  (along with margins M 0  and M 1 ) to accommodate the changed window of operation, and to ensure a reliable read of all the bits in the distributions  50 C and  52 C. 
   It will be appreciated that read levels RD 1  and RD 2  would not successfully read the distribution of  FIG. 5C . Both read levels RD 1  and RD 2  would erroneously read at least some of the 0&#39;s (since the distance of the left side of the program distribution  52 C to the read level is smaller than the required margin M 0 ). Similarly, third read level RD 3  would erroneously read some of the 1&#39;s had it been used for the distributions of  FIGS. 5A and 5B  since the right sides of distributions  50 A and  50 B do not maintain a required margin M 1  from the read level RD 3 . 
   Selecting which read level to utilize at any given time may be done in any suitable manner and all such methods are included in the present invention. An example is shown in  FIG. 6A , to which reference is now made. In this example, the memory array, labeled  60 , may comprise memory cells  62  to be read, and history cells  64 . At least one history cell  64  may be associated with a subset of memory cells  62  and may pass through substantially the same events and preferably substantially at the same time and with the same conditions as its corresponding subset of memory cells  62 . 
   A specific example is shown in  FIG. 6B , to which reference is now made. In this example, a history cell  64 A may be associated with a row A of memory cells  62  and may be programmed and erased at the same time as cells  62  in row A, always being brought back to a its known predetermined state. This predetermined state may be, for example, such that both bits (i.e. both storage areas) of the cell are in a programmed state, or, in a different case, only one of the bits is in a programmed state while the other bit remains erased. 
   Another example is shown in  FIG. 6C , to which reference is now made. In this example, a set of history cells  64 G may be associated with a section G in array  60 . History cells  64 G may be anywhere in the memory array as long as they pass through substantially the same events at substantially the same conditions as the subset of memory cells with whom they are associated. The history cells  64 G are always brought back to a predetermined state. Some of the history cells may have both bits (i.e. both storage areas) in a programmed state while other history cells may have only one of their bits in a programmed state. 
   The history cells  64  may be utilized to determine the most appropriate reference read level to use for reading the subset of memory cells  62  to which they are associated. The reference read level, or more preferably, the highest reference read level, that may produce a correct readout of history cells  64  (a ‘0’ readout, since the history cells  64  typically are in a programmed state) may be utilized to read its associated subset of memory cells  62 . 
   The reference read level used to correctly read history cell  64  may be known as a “history read reference level”. The associated subset of memory cells  62  may be read with a “memory read reference level” which may be the same as the history read reference level or it may have a margin added to it. 
   In one example, there may be three available reference read levels RD 1 &gt;RD 2 &gt;RD 3 . If a programmed history cell  64  is incorrectly read using RD(j) (i.e. it is read as erased), but correctly read using RD(j+1), then the associated subset of memory cells  62  may preferably be read using the RD(j+1) reference read level, with or without a margin added to it. 
   Alternatively, if a programmed history cell  64  cannot be read with enough margin (Mh) using RD(j) (i.e. it is read as erased using RD(j)+Mh), but can be read with enough margin using RD(j+1) (i.e. it is read as programmed using RD(j+1)+Mh), then the associated subset of memory cells  62  may preferably be read using the RD(j+1) reference read level. The margin Mh may be defined as the amount of desired margin between the reliable readout of the history cell and the reliable readout of the memory cells  62  associated therewith. 
   The most appropriate reference read level to be used for reading each of the subsets of memory cells  62  may be determined in any one of a number of ways, of which four are described hereinbelow.
         A) reading all or part of the history cells  64  vs. all or part of existing read reference cells having read reference levels RD(j).   B) reading all or part of the history cells  64  vs. specific reference cells placed at the read reference levels RD(j) plus some margin Mh. There can be separate margins Mh(j) for each read level RD(j).   C) reading all or part of the history cells  64  vs. all or part of the existing read reference cells having read reference levels RD(j) but activating the word lines of the history cells  64  at a different level than the word line of the read reference cells, in order to introduce some margin.   D) reading all or part of the history cells  64  vs. all or part of the existing read reference cells having read reference levels RD(j) but introducing some margin Mh(j) at each of these read operations, for example by adding or subtracting a current or voltage signal to the signals of at least one of the history or the read reference cells.       

   These operations may be performed “on the fly” (before reading the associated subset of memory cells  62 ) in applications that allow sufficient time to read the history cells  64  vs. the different read reference levels and to determine the optimal memory read reference level for reading the associated subset of memory cells  62 . Alternatively, the history cells  64  may be read at predetermined times and, after analyzing the readouts and choosing the appropriate read reference level for each set of history cells, the results may be stored for later use when a read of memory cells  62  may be required. Such predetermined times may be at power-up of the device, prior to or after long operations (e.g. program or erase) or at idle times. The history cells  64  may be read serially, in parallel, and in a mixed serial/parallel form. 
   The history cells  64  may be of the same type of multi bit NROM cells as the array memory cells  62 . They may be operated in a one bit per cell mode, in a dual bit per cell mode, or in a multilevel mode. The programmed state of history cells  64  may be achieved by programming only one or both bits in their cells. The history cells  64  may be erased close to, together with, or while erasing their associated memory cells  62 . The programming of the history cells may be performed shortly after erasing them and their associated memory cells  62 , or close to programming a subset of bits in their associated memory cells  62 . 
   While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Technology Classification (CPC): 6