Patent Abstract:
A phase selector is disclosed. The phase selector is utilized for outputting an output clock to a flip-flop according to an input data signal latched by the flip-flop. The phase selector includes: a clock phase adjustor, for adjusting the delay of an input clock to generate a first clock and a second clock, wherein the clock phases of the first clock and the second clock are different; a phase detector, for detecting phase relation between the input data signal and the first clock to generate a detecting signal; a decision circuit, coupled to the phase detector, for generating a selecting signal according to the detecting signal; and a selection circuit, coupled to the decision circuit, for selecting the input clock or the second clock to generate the output clock to the flip-flop according to the selecting signal.

Full Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a phase selector, and more particularly, to a phase selector with the functionality of deciding a phase of an output clock to trigger a flip-flop by comparing phases of an input data signal and an input clock. 
     2. Description of the Prior Art 
     In digital circuits, clock signals are essential reference signals for accessing digital data. Typically, latch time for accessing digital data in digital circuits is determined using either rising edge or falling edge triggers. In some cases, even though two different sub-circuits in a circuit system utilize exactly the same clock source, clocks and digital data transmitted to the sub-circuits may be asynchronous due to transmission delay or noise interference. 
     Take a transmitting device comprising two flip-flops as an example herein. Please refer to  FIG. 1  and  FIG. 2 .  FIG. 1  is a schematic diagram illustrating digital data transmitted between two flip-flops  110  and  120 .  FIG. 2  is a timing diagram illustrating clocks and digital data in  FIG. 1 . An input data signal D 1  and a clock C 1  are used herein as inputs to the flip-flop  110 , having waveforms and timing relation shown in  FIG. 2 . Assume that both flip-flops  110  and  120  are rising edge triggered, thus the input data signal D 1  will be latched at t 1 , the flip-flop  110  will output latch data D L  to the flip-flop  120 , and the latch data D L  will have a transition from “0” to “1” from t 1 , as shown in  FIG. 2 . Clocks C 1  and C 2  respectively for the two flip-flops  110  and  120  are asynchronous. Therefore, if a rising edge trigger of the clock C 2  happens at t 2  during the period when the latch data D L  is changing from “0” to “1” as shown in  FIG. 2 , latch errors will be induced in the flip-flop  120 , resulting in errors in digital data transmission. 
     SUMMARY OF THE INVENTION 
     It is therefore one of the objectives of the present invention to provide a phase selector and a related clock selection method for generating an appropriate reference clock in data transmitting device, thus improving the accuracy of reading/writing data. 
     According to one embodiment of the present invention, the present invention discloses a phase selector, for outputting an output clock to a flip-flop according to an input data signal latched by the flip-flop, the phase selector comprising: a clock phase adjustor, for adjusting the delay of an input clock to generate a first clock and a second clock, wherein the clock phases of the first clock and the second clock are different; a phase detector, for detecting phase relation between the input data signal and the first clock to generate a detecting signal; a decision circuit, coupled to the phase detector, for generating a selecting signal according to the detecting signal; and a selection circuit, coupled to the decision circuit, for selecting the input clock or the second clock to generate the output clock to the flip-flop according to the selecting signal. 
     According to another embodiment of the present invention, the present invention discloses a data transmitting device, comprising: a first flip-flop, for latching an input data signal to output a data signal according to a first clock; a second flip-flop, coupled to the first flip-flop, for latching the data signal to output an output data signal according to an output clock; and a phase selector, coupled to the first flip-flop and the second flip-flop, for generating the output clock to the second flip-flop according to phase relation between the data signal and a second clock; wherein the frequency of the output clock is substantially equal to the frequency of the second clock. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram illustrating digital data transmitted between two flip-flops according to the prior art. 
         FIG. 2  is a timing diagram illustrating clocks and digital data in  FIG. 1 . 
         FIG. 3  is a schematic diagram illustrating a data transmitting device with a phase selector. 
         FIG. 4  is a timing diagram illustrating clocks and digital data in  FIG. 3 . 
         FIG. 5  is a schematic diagram illustrating an embodiment of a phase selector of the present invention. 
         FIG. 6  is a schematic diagram illustrating the phase selector in  FIG. 5  in detail. 
         FIG. 7  is a truth table of related signals in  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 3  and  FIG. 4 .  FIG. 3  is a schematic diagram illustrating a data transmitting device with a phase selector  330  of the present invention.  FIG. 4  is a timing diagram illustrating clocks and digital data in  FIG. 3 . As shown in  FIG. 3 , the phase selector  330  determines whether a phase of a clock C 2  needs to be delayed to generate a delay clock C 3  according to a latch data D L . Therefore, the delay clock C 3  with a relatively delayed phase can be used to latch bit values of the latch data D L  accurately. For example, in  FIG. 4 , the phase selector  330  delays the clock C 2  for a half-period, i.e. 180 degrees of phase. A rising edge trigger of the delay clock C 3  occurs at t 3  for a flip-flop  320  to latch the latch data D L . Distinct from the clock C 2  with no delay ( FIG. 2 ), the delay clock C 3  with a relatively delayed phase ( FIG. 4 ) can latch bit values of the latch data D L  accurately. In practical embodiments, the delay amount applied to the clock C 2  can be programmable by circuit designers. In other words, the clock C 2  can be delayed for a delay amount other than a half-period if appropriate. Accordingly, in one embodiment of the present invention, the flip-flop  310  is positioned in an analog signal domain, and the flip-flop  320  is positioned in a digital signal domain. In such a case, a signal D 1  is outputted from an analog circuit, and a signal D 0  is outputted to a digital circuit. In other embodiments, the flip-flop  310  can be positioned in a digital signal domain, and the flip-flop  320  can be positioned in an analog signal domain. In such a case, the signal D 1  is outputted from a digital circuit, and the signal D 0  is outputted to an analog circuit. Please note that the two above examples are not meant to be a limitation of the present invention. 
       FIG. 5  is a schematic diagram illustrating an embodiment of a phase selector  500  of the present invention. The phase selector  500  comprises a clock phase adjustor  515 , a phase detector  510 , a decision circuit  590 , and a selection circuit, such as a multiplexer  570 . The clock phase adjustor  515  comprises a first delay unit  550  and a second delay unit  560 . The decision circuit  590  comprises a first counter  520 , a second counter  530 , and a control circuit  505 . The control circuit  505  comprises a selection circuit  540  and a latch circuit  580 . 
     The first delay unit  550  delays an input clock C 2  for some degree of phase delay to generate a first delay clock C D1 . Because the phase detector  510  detects that a phase of an input data signal D L  lags behind that of the first delay clock C D1 , a detecting signal S 1  remains at a logic level “0”, and another detecting signal S 2  is a continuous square wave. If the phase of the input data signal D L  leads that of the first delay clock C D1 , the detecting signal S 1  is a continuous square wave, and the detecting signal S 2  remains at the logic level “0”. The selection circuit  540  decides whether a selecting signal S W  is output to switch the multiplexer  570  according to the detecting signals S 1  and S 2 . In one preferred embodiment that can prevent an erroneous switching operation of the multiplexer  570 , the decision circuit  590  receives the detecting signals S 1  and S 2  via the first and second counters  520  and  530  respectively and thus outputs the selecting signal S W ; and the second delay unit  560  delays the input clock C 2  for some degree of phase delay to generate a second delay clock C D2 . The multiplexer  570  then selects the input clock C 2  or the second delay clock C D2  to be an output clock C 3  according to the selecting signal S W . In other words, the selecting signal S W  for controlling the multiplexer  570  is decided according to phase relation between the input data signal D L  and the first delay clock C D1 . When the phase of the input data signal D L  leads that of the first delay clock C D1 , the multiplexer  570  selects the input clock C 2  as the output clock C 3 . When the phase of the input data signal D L  lags behind that of the first delay clock C D1 , however, the multiplexer  570  selects the second delay clock C D2  as the output clock C 3 . 
     Moreover, after the selection circuit  540  sends the selecting signal S W  to switch the multiplexer  570 , the latch circuit  580  will send a disable signal S DIS  to the selection circuit  540 . The disable signal S DIS  thus stops the selection circuit  540  from switching the multiplexer  570 , thereby avoiding system instability due to frequent switching operations. After the selection circuit  540  is stopped for an appropriate period of time, the latch circuit  580  will send an enable signal S EN  to restart the selection circuit  540 . 
       FIG. 6  is a schematic diagram illustrating the phase selector in  FIG. 5  in detail. As shown in  FIG. 6 , the phase selector  600  comprises a Bang-Bang phase detector  610 , a first counter  620 , a second counter  630 , an AND gate  640 , a delay circuit  650 , a NOR gate  660 , a multiplexer  670 , a NOT gate  680 , and an OR gate  690 . The AND gate  640 , the NOR gate  660 , and the OR gate  690  form a control circuit  605 . The delay circuit  650  delays an input clock C 2  for a quarter-period, i.e. 90 degrees of phase, to generate a first delay clock C D1 . The NOT gate  680  inverts the input clock C 2  to generate a second delay clock C D2 . In other words, the NOT gate  680  delays the input clock C 2  for 180 degrees of phase. The second delay clock C D2  is thus sent to the multiplexer  670 . If a phase of an input data signal D L  leads that of the first delay clock C D1 , a detecting signal S 1  is a continuous square wave, and another detecting signal S 2  remains at a level “0”. Moreover, when a square wave number (i.e. a pulse number) of the detecting signal S 1  counted by the first counter  620  reaches a threshold value, the phase of the input data signal D L  will lead that of the first delay clock C D1 . Therefore, the first counter  620  outputs a first selecting signal S W1  at a logical level “1”. Because the detecting signal S 2  remains at the level “0”, a square wave number of the detecting signal S 2  counted by the second counter  630  is zero. Thus, the second counter  630  outputs a second selecting signal S W2  at a logical level “0”. In such a case, the multiplexer  670  selects the input clock C 2  as an output clock C 3 . Otherwise, the multiplexer  670  selects the second delay clock C D2  as the output clock C 3 . The first and second selecting signals S W1  and S W2  are input into the NOR gate  660  to generate a disable signal S DIS . The disable signal S DIS  and an enable signal S EN  are input into the OR gate  690  to generate a reset signal S R . Further, the reset signal S R  and the first delay clock C D1  are input into the AND gate  640  to generate a control signal S C  for controlling the first and second counters  620  and  630 . After Boolean calculation, the relation between the control signal S C  and other signals can be represented as follows:
 
 S   C   =C   D1   [S   EN +( S   W1   +S   W2 )′].
 
       FIG. 7  is a truth table  700  of the first selecting signal S W1 , the second selecting signal S W2 , the disable signal S DIS , the enable signal S EN , the reset signal S R , the first delay clock C D1 , and the control signal S C . As shown in  FIG. 7 , when square wave numbers counted by the first and second counters  620  and  630  are below the threshold value, the first and second selecting signals S W1  and S W2  are both logically “0”. Meanwhile, the disable signal S DIS  is “1”, thus the reset signal S R  is certain to be “1”. Because the first delay clock C D1  is a clock signal, the control signal S C  is also a clock signal serving as a reference clock for the first and second counters  620  and  630 . In other words, the first and second counters  620  and  630  continue to count the square wave numbers. When either square wave number reaches the threshold value, the corresponding selecting signal (i.e. the first selecting signal S W1  or the second selecting signal S W2 ) changes to be logically “1”. The disable signal S DIS  thus becomes logically “0”. Meanwhile, if the enable signal S EN  is not available, i.e. logically “0”, the reset signal S R  becomes logically “0”, and the control signal S C  also becomes logically “0”. Therefore, the reference clock for the first and second counters  620  and  630  is “0”, so the first and second counters  620  and  630  stop counting the square wave numbers. Additionally, the counters act as memories to store the results of the selecting signals S W1  and S W2 . When the enable signal S EN  is available, i.e. logically “1”, the reset signal S R  becomes logically “1”, and the control signal S C  is a clock signal again. The counters are reset to “0” at rising edges of the enable signal S EN . In the above described way, the control circuit  605  formed by the NOR gate  660 , the OR gate  690 , and the AND gate  640  is utilized to avoid system instability due to frequent switching operations of the output clock C 3 . 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Classification (CPC): 7