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train · 70 rows

Module stringlengths 6 28	Name stringlengths 1 9	Type stringclasses 5 values	Width float64 1 320 ⌀	Description stringlengths 9 26
euclid_dividion	dividend	input	32	32-bit dividend
cnlfsr_tb	clk	reg	1	Clock signal
ascon_permutation	rst	input	1	Reset signal
Chinese_remainder_theorem	b	input	32	32-bit input B
Chinese_remainder_theorem_tb	result	wire	32	32-bit result
Helix_adder	b	input	8	8-bit input B
BoothMultiplier_tb	clk	reg	1	Clock signal
Chinese_remainder_theorem	a	input	32	32-bit input A
BoothMultiplier_tb	b	reg	16	16-bit multiplier
Helix_adder_tb	sum	wire	8	8-bit sum
CarrySaveAdder_tb	sum	wire	8	8-bit sum output
dadda_multiplier	clk	input	1	Clock signal
BoothMultiplier	a	input	16	16-bit multiplicand
CarrySaveAdder_tb	b	reg	8	8-bit input B
euclid_dividion_tb	dividend	reg	32	32-bit dividend
Chinese_remainder_theorem_tb	a	reg	32	32-bit input A
WallaceMultiplier_tb	b	reg	16	16-bit multiplier
CarrySaveAdder_tb	c	reg	8	8-bit input C
Helix_adder_tb	rst	reg	1	Reset signal
cnlfsr	clk	input	1	Clock signal
Chinese_remainder_theorem	rst	input	1	Reset signal
cnlfsr	rst	input	1	Reset signal
euclid_dividion_tb	divisor	reg	32	32-bit divisor
Chinese_remainder_theorem	clk	input	1	Clock signal
cnlfsr_tb	seed	reg	16	16-bit seed value
Chinese_remainder_theorem_tb	dut	instance	null	Device Under Test instance
BoothMultiplier_tb	dut	instance	null	Device Under Test instance
dadda_multiplier_tb	b	reg	16	16-bit multiplier
Chinese_remainder_theorem_tb	rst	reg	1	Reset signal
Chinese_remainder_theorem_tb	clk	reg	1	Clock signal
euclid_dividion_tb	clk	reg	1	Clock signal
euclid_dividion_tb	dut	instance	null	Device Under Test instance
Helix_adder	sum	output	8	8-bit sum
CarrySaveAdder	sum	output	8	8-bit sum output
dadda_multiplier	a	input	16	16-bit multiplicand
Chinese_remainder_theorem_tb	mod	reg	32	32-bit modulus
ascon_permutation_tb	data_out	wire	128	128-bit output data
euclid_dividion	quotient	output	32	32-bit quotient
euclid_dividion	rst	input	1	Reset signal
ascon_permutation_tb	rst	reg	1	Reset signal
ascon_permutation	state	reg	320	320-bit internal state
euclid_dividion_tb	remainder	wire	32	32-bit remainder
ascon_permutation_tb	data_in	reg	128	128-bit input data
dadda_multiplier_tb	clk	reg	1	Clock signal
WallaceMultiplier	clk	input	1	Clock signal
WallaceMultiplier_tb	a	reg	16	16-bit multiplicand
euclid_dividion_tb	quotient	wire	32	32-bit quotient
CarrySaveAdder_tb	a	reg	8	8-bit input A
cnlfsr_tb	rst	reg	1	Reset signal
CarrySaveAdder_tb	dut	instance	null	Device Under Test instance
dadda_multiplier_tb	dut	instance	null	Device Under Test instance
dadda_multiplier_tb	rst	reg	1	Reset signal
CarrySaveAdder	carry	output	8	8-bit carry output
euclid_dividion	remainder	output	32	32-bit remainder
Chinese_remainder_theorem	mod	input	32	32-bit modulus
dadda_multiplier	product	output	32	32-bit product
WallaceMultiplier_tb	rst	reg	1	Reset signal
Chinese_remainder_theorem	result	output	32	32-bit result
Helix_adder_tb	a	reg	8	8-bit input A
CarrySaveAdder	c	input	8	8-bit input C
WallaceMultiplier	product	output	32	32-bit product
euclid_dividion	divisor	input	32	32-bit divisor
Helix_adder_tb	dut	instance	null	Device Under Test instance
WallaceMultiplier_tb	dut	instance	null	Device Under Test instance
dadda_multiplier_tb	product	wire	32	32-bit product
Helix_adder	a	input	8	8-bit input A
WallaceMultiplier	rst	input	1	Reset signal
cnlfsr_tb	out	wire	16	16-bit LFSR output
WallaceMultiplier	a	input	16	16-bit multiplicand
dadda_multiplier	rst	input	1	Reset signal

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